YiFive SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Table of contents

Overview

YiFive is a 32 bit RISC V based SOC design targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

YiFive Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * industry-grade and silicon-proven Open-Source RISC-V core from syntacore 
    * industry-graded and silicon-proven 8-bit SDRAM controller
    * Quad SPI Master
    * UART with 16Byte FIFO
    * I2C Master
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Sub IP features

RISC V Core

YiFive SOC Integrated Syntacore SCR1 Open-source RISV-V compatible MCU-class core. It is industry-grade and silicon-proven IP. Git link: https://github.com/syntacore/scr1

Block Diagram

RISC V Core Key feature

   * RV32I or RV32E ISA base + optional RVM and RVC standard extensions
   * Machine privilege mode only
   * 2 to 4 stage pipeline
   * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
   * Optional RISC-V Debug subsystem with JTAG interface
   * Optional on-chip Tightly-Coupled Memory

RISC V core customization YiFive SOC

  • Update: Modified some of the system verilog syntax to basic verilog syntax to compile/synthesis in open source tool like simulator (iverilog) and synthesis (yosys).
  • Modification: Modified the AXI/AHB interface to wishbone interface towards instruction & data memory interface

8bit SDRAM Controller

Due to number of pin limitation in carvel shuttle, YiFive SOC integrate 8bit SDRAM controller. This is a silicon proven IP. IP Link: https://opencores.org/projects/sdr_ctrl

Block Diagram

SDRAM Controller key Feature

    * 8/16/32 Configurable SDRAM data width
    * Wish Bone compatible
    * Application clock and SDRAM clock can be async
    * Programmable column address
    * Support for industry-standard SDRAM devices and modules
    * Supports all standard SDRAM functions.
    * Fully Synchronous; All signals registered on positive edge of system clock.
    * One chip-select signals
    * Support SDRAM with four banks
    * Programmable CAS latency
    * Data mask signals for partial write operations
    * Bank management architecture, which minimizes latency.
    * Automatic controlled refresh

SOC Memory Map

SOC Size

BlockTotal CellSeqCombo
RISC26642315823484
GLOBAL REG27535752178
SDRAM719812075991
SPI760712796328
UART_I2C35616052956
WB_HOST30735152558
WB_INTC12911101181
TOTAL52125744944676

SOC Register Map

Register Map: Wishbone HOST
OffsetNameDescription
0x00GLBL_CTRL[RW] Global Wishbone Access Control Register
0x04BANK_CTRL[RW] Bank Selection, MSB 8 bit Address
0x08CLK_SKEW_CTRL1[RW] Clock Skew Control2
0x0cCLK_SKEW_CTRL2[RW] Clock Skew Control2
Register: GLBL_CTRL
BitsNameDescription
31:24ReseveredUnsused
23:20RTC_CLK_CTRLRTC Clock Div Selection
19:16CPU_CLK_CTRLCPU Clock Div Selection
15:12SDARM_CLK_CTRLSDRAM Clock Div Selection
10:8WB_CLK_CTRLCore Wishbone Clock Div Selection
7UART_I2C_SEL0 - UART , 1 - I2C Master IO Selection
5I2C_RSTI2C Reset Control
4UART_RSTUART Reset Control
3SDRAM_RSTSDRAM Reset Control
2SPI_RSTSPI Reset Control
1CPU_RSTCPU Reset Control
0WB_RSTWishbone Core Reset Control
Register: BANK_CTRL
BitsNameDescription
31:24ReseveredUnsused
7:0BANK_SELHolds the upper 8 bit address core Wishbone Address
Register: CLK_SKEW_CTRL1
BitsNameDescription
31:28ReseveredUnsused
27:24CLK_SKEW_WBWishBone Core Clk Skew Control
23:20CLK_SKEW_GLBLGlbal Register Clk Skew Control
19:16CLK_SKEW_SDRAMSDRAM Clk Skew Control
15:12CLK_SKEW_SPISPI Clk Skew Control
11:8CLK_SKEW_UARTUART/I2C Clk Skew Control
7:4CLK_SKEW_RISCRISC Clk Skew Control
3:0CLK_SKEW_WIWishbone Clk Skew Control
Register Map: SPI MASTER
OffsetNameDescription
0x00GLBL_CTRL[RW] Global SPI Access Control Register
0x04DMEM_CTRL1[RW] Direct SPI Memory Access Control Register1
0x08DMEM_CTRL2[RW] Direct SPI Memory Access Control Register2
0x0cIMEM_CTRL1[RW] Indirect SPI Memory Access Control Register1
0x10IMEM_CTRL2[RW] Indirect SPI Memory Access Control Register2
0x14IMEM_ADDR[RW] Indirect SPI Memory Address
0x18IMEM_WDATA[W] Indirect SPI Memory Write Data
0x1cIMEM_RDATA[R] Indirect SPI Memory Read Data
0x20SPI_STATUS[R] SPI Debug Status
Register: GLBL_CTRL
BitsNameDescription
31:16ReseveredUnsused
15:8SPI_CLK_DIVSPI Clock Div Rato Selection
7:4ReservedUnused
3:2CS_LATECS DE_ASSERTION CONTROL
1:0CS_EARLYCS ASSERTION CONTROL
Register: DMEM_CTRL1
BitsNameDescription
31:9ReseveredUnsused
8FSM_RSTDirect Mem State Machine Reset
7:6SPI_SWITCHPhase at which SPI Mode need to switch
5:4SPI_MODESPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0CS_SELECTCHIP SELECT
Register: DMEM_CTRL2
BitsNameDescription
31:24DATA_CNTTotal Data Byte Count
23:22DUMMY_CNTTotal Dummy Byte Count
21:20ADDR_CNTTotal Address Byte Count
19:16SPI_SEQSPI Access Sequence
15:8MODE_REGMode Register Value
7:0CMD_REGCommand Register Value
Register: IMEM_CTRL1
BitsNameDescription
31:9ReseveredUnsused
8FSM_RSTInDirect Mem State Machine Reset
7:6SPI_SWITCHPhase at which SPI Mode need to switch
5:4SPI_MODESPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0CS_SELECTCHIP SELECT
Register: IMEM_CTRL2
BitsNameDescription
31:24DATA_CNTTotal Data Byte Count
23:22DUMMY_CNTTotal Dummy Byte Count
21:20ADDR_CNTTotal Address Byte Count
19:16SPI_SEQSPI Access Sequence
15:8MODE_REGMode Register Value
7:0CMD_REGCommand Register Value
Register: IMEM_ADDR
BitsNameDescription
31:0ADDRIndirect Memory Address
Register: IMEM_WDATA
BitsNameDescription
31:0WDATAIndirect Memory Write Data
Register: IMEM_RDATA
BitsNameDescription
31:0RDATAIndirect Memory Read Data
Register: SPI_STATUS
BitsNameDescription
31:0DEBUGSPI Debug Status
Register Map: Global Register
OffsetNameDescription
0x00SOFT_REG0[RW] Software Register0
0x04RISC_FUSE[RW] Risc Fuse Value
0x08SOFT_REG2[RW] Software Register2
0x0cINTR_CTRL[RW] Interrupt Control
0x10SDRAM_CTRL1[RW] Indirect SPI Memory Access Control Register2
0x14SDRAM_CTRL2[RW] Indirect SPI Memory Address
0x18SOFT_REG6[RW] Software Register6
0x1CSOFT_REG7[RW] Software Register7
0x20SOFT_REG8[RW] Software Register8
0x24SOFT_REG9[RW] Software Register9
0x28SOFT_REG10[RW] Software Register10
0x2CSOFT_REG11[RW] Software Register11
0x30SOFT_REG12[RW] Software Register12
0x34SOFT_REG13[RW] Software Register13
0x38SOFT_REG14[RW] Software Register14
0x3CSOFT_REG15[RW] Software Register15
Register: RISC_FUSE
BitsNameDescription
31:0RISC_FUSERISC Core Fuse Value
Register: INTR_CTRL
BitsNameDescription
31:20ReservedUnused
19:17USER_IRQUser Interrupt generation toward riscv
16SOFT_IRQSoftware Interrupt generation toward riscv
15:0EXT_IRQExternal Interrupt generation toward riscv
Register: SDRAM_CTRL1
BitsNameDescription
31ReservedUnused
30SDRAM_INIT_DONESDRAM init done indication
29SDR_ENSDRAM controller enable
28:26SDR_CASSDRAM CAS latency
25:24SDR_REQ_DPSDRAM Maximum Request accepted by SDRAM controller
23:20SDR_TWRSDRAM Write Recovery delay
19:16SDR_TRCARSDRAM Auto Refresh Period
15:12SDR_TRCDSDRAM Active ti R/W delay
11:8SDR_TRPSDRAM Prechard to active delay
7:4SDR_TRASSDRAM Active to precharge
3:2SDR_COLSDRAM Colum Address
1:0SDR_WDSDRAM Interface Width, 0 - 32bit, 1 - 16 bit, 2 - 8 bit
Register: SDRAM_CTRL2
BitsNameDescription
31:28ReservedUnused
27:16SDRAM_REFRESHSDRAM Refresh Rate per row
15:3SDR_MODE_REGSDRAM Mode Register
2:0SDR_MODE_REGNumber of rows to rfsh at a time

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. YiFive SOC GPIO Pin Mapping as follows

Repository contents

|verilog
|   ├─  rtl
|   |     |-  syntacore
|   |     |     |─  scr1
|   |     |     |    ├─ **docs**                           | **SCR1 documentation**
|   |     |     |    |      ├─ scr1_eas.pdf                | SCR1 External Architecture Specification
|   |     |     |    |      └─ scr1_um.pdf                 | SCR1 User Manual
|   |     |     |    |─  **src**                           | **SCR1 RTL source and testbench files**
|   |     |     |    |   ├─ includes                       | Header files
|   |     |     |    |   ├─ core                           | Core top source files
|   |     |     |    |   ├─ top                            | Cluster source files
|   |     |     |    |─  **synth**                         | **SCR1 RTL Synthesis files **
|   |     |- sdram_ctrl
|   |     |     |- **src**
|   |     |     |   |- **docs**                            | **SDRAM Controller Documentation**
|   |     |     |   |     |- sdram_controller_specs.pdf    | SDRAM Controller Design Specification
|   |     |     |   |             
|   |     |     |   |- core                                | SDRAM Core integration source files                          
|   |     |     |   |- defs                                | SDRAM Core defines
|   |     |     |   |- top                                 | SDRAM Top integration source files
|   |     |     |   |- wb2sdrc                             | SDRAM Wishbone source files
|   |     |- spi_master
|   |     |     |- src                                     | Qard SPI Master Source files
|   |     |-wb_interconnect
|   |     |     |- src                                     | 3x4 Wishbone Interconnect
|   |     |- digital_core
|   |     |     |- src                                     | Digital core Source files
|   |     |- lib                                           | common library source files
|   |- dv
|   |   |- la_test1                                        | carevel LA test
|   |   |- risc_boot                                       | user core risc boot test
|   |   |- wb_port                                         | user wishbone test
|   |   |- user_risc_boot                                  | user standalone test without carevel soc
|   |- gl                                                  | ** GLS Source files **
|
|- openlane
    |- sdram                                               | sdram openlane scripts   
    |- spi_master                                          | spi_master openlane scripts   
    |- syntacore                                           | Risc Core openlane scripts   
    |- yifive                                              | yifive digital core openlane scripts
    |- user_project_wrapper                                | carvel user project wrapper

Prerequisites

  • Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Environment setting

    export CARAVEL_ROOT=<Carvel Installed Path>
    export OPENLANE_ROOT=<OpenLane Installed Path>
    export PDK_ROOT=<PDK Installed Path>
    export IMAGE_NAME=dineshannayya/openlane:rc7

Tests preparation

The simulation package includes the following tests:

  • risc_boot - Simple User Risc core boot
  • wb_port - User Wishbone validation
  • user_risc_boot - Standalone User Risc core boot

Running Simulation

Examples:

    make verify-wb_port  
    make verify-risc_boot
    make verify-user_uart
    make verify-user_spi
    make verify-user_i2cm
    make verify-user_risc_boot

Tool Sets

YiFive Soc flow uses Openlane tool sets.

  1. Synthesis
    1. yosys - Performs RTL synthesis
    2. abc - Performs technology mapping
    3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
  2. Floorplan and PDN
    1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
    2. ioplacer - Places the macro input and output ports
    3. pdn - Generates the power distribution network
    4. tapcell - Inserts welltap and decap cells in the floorplan
  3. Placement
    1. RePLace - Performs global placement
    2. Resizer - Performs optional optimizations on the design
    3. OpenPhySyn - Performs timing optimizations on the design
    4. OpenDP - Perfroms detailed placement to legalize the globally placed components
  4. CTS
    1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
  5. Routing
    1. FastRoute - Performs global routing to generate a guide file for the detailed router
    2. CU-GR - Another option for performing global routing.
    3. TritonRoute - Performs detailed routing
    4. SPEF-Extractor - Performs SPEF extraction
  6. GDSII Generation
    1. Magic - Streams out the final GDSII layout file from the routed def
    2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
  7. Checks
    1. Magic - Performs DRC Checks & Antenna Checks
    2. Klayout - Performs DRC Checks
    3. Netgen - Performs LVS Checks
    4. CVC - Performs Circuit Validity Checks

important Note

Following tools in openlane docker is older version, we need to update these tool set.

  • Icarus Verilog version 12.0 (devel) (s20150603-1107-ga446c34d)
  • Yosys 0.9+4081 (git sha1 b6721aa9, clang 10.0.0-4ubuntu1 -fPIC -Os)

We have modified these openlane changes in our git repo, you can use from these path git clone https://github.com/dineshannayya/openlane.git docker pull dineshannayya/openlane:rc7

Contacts

Report an issue: https://github.com/dineshannayya/yifive_r0/issues

Documentation