)]}'
{
  "commit": "be01ead0d353835c9db513a041d2b2393b6e062d",
  "tree": "031ba8da365ca02548c9415567edf1c9112d9905",
  "parents": [
    "0081f48c68a7be711c439d0fabc80a350e46347d"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Aug 27 13:42:48 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Aug 27 13:42:48 2021 +0530"
  },
  "message": "sdram ctrl bug fix tRAS violation, changed the define to ASIC\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d566f6f96afd9ce315f9130e4ad6fc36eb60a953",
      "old_mode": 33261,
      "old_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v",
      "new_id": "2ce60d3b4e1fc47b3ff785d14236e68111e2008f",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v"
    },
    {
      "type": "modify",
      "old_id": "24308312c497937f645e8c1ec07d6797076edb6b",
      "old_mode": 33261,
      "old_path": "verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v",
      "new_id": "018c6836767d6952977d6142f155fcca039a8cdc",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v"
    },
    {
      "type": "modify",
      "old_id": "c845d023a142a83d281d2ac4e0df011fa2360f53",
      "old_mode": 33261,
      "old_path": "verilog/rtl/sdram_ctrl/src/top/sdrc_top.v",
      "new_id": "cff5e76bc4b209df99322e0ee52f517973f99dff",
      "new_mode": 33261,
      "new_path": "verilog/rtl/sdram_ctrl/src/top/sdrc_top.v"
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}