| /root/riscduino-r1/run_regress |
| /root/riscduino-r1/Makefile |
| /root/riscduino-r1/sta/base.sdc |
| /root/riscduino-r1/sta/Makefile |
| /root/riscduino-r1/sta/run_sta |
| /root/riscduino-r1/sta/scripts/or_write_verilog.tcl |
| /root/riscduino-r1/sta/scripts/sta.tcl |
| /root/riscduino-r1/sta/scripts/caravel_timing.tcl |
| /root/riscduino-r1/sta/sdc/caravel.sdc |
| /root/riscduino-r1/verilog/dv/Makefile |
| /root/riscduino-r1/verilog/dv/risc_boot/risc_boot.c |
| /root/riscduino-r1/verilog/dv/risc_boot/risc_boot_tb.v |
| /root/riscduino-r1/verilog/dv/risc_boot/Makefile |
| /root/riscduino-r1/verilog/dv/risc_boot/user_uart.c |
| /root/riscduino-r1/verilog/dv/risc_boot/run_iverilog |
| /root/riscduino-r1/verilog/dv/vpi/system/system.c |
| /root/riscduino-r1/verilog/dv/user_spi/Makefile |
| /root/riscduino-r1/verilog/dv/user_spi/user_spi_tb.v |
| /root/riscduino-r1/verilog/dv/user_spi/user_risc_boot.c |
| /root/riscduino-r1/verilog/dv/user_spi/run_iverilog |
| /root/riscduino-r1/verilog/dv/riscv_regress/user_risc_regress_tb.v |
| /root/riscduino-r1/verilog/dv/riscv_regress/riscv_runtests.sv |
| /root/riscduino-r1/verilog/dv/riscv_regress/Makefile |
| /root/riscduino-r1/verilog/dv/riscv_regress/uprj_netlists.v |
| /root/riscduino-r1/verilog/dv/agents/uart_master_tasks.sv |
| /root/riscduino-r1/verilog/dv/agents/uart_agent.v |
| /root/riscduino-r1/verilog/dv/uart_master/Makefile |
| /root/riscduino-r1/verilog/dv/uart_master/run_verilog |
| /root/riscduino-r1/verilog/dv/uart_master/uart_master_tb.v |
| /root/riscduino-r1/verilog/dv/uart_master/uart_master.c |
| /root/riscduino-r1/verilog/dv/user_i2cm/Makefile |
| /root/riscduino-r1/verilog/dv/user_i2cm/user_i2cm_tb.v |
| /root/riscduino-r1/verilog/dv/user_i2cm/user_uart.c |
| /root/riscduino-r1/verilog/dv/user_i2cm/run_iverilog |
| /root/riscduino-r1/verilog/dv/model/s25fl256s.sv |
| /root/riscduino-r1/verilog/dv/model/i2c_slave_model.v |
| /root/riscduino-r1/verilog/dv/user_uart_master/Makefile |
| /root/riscduino-r1/verilog/dv/user_uart_master/user_uart_master_tb.v |
| /root/riscduino-r1/verilog/dv/user_uart_master/user_uart.c |
| /root/riscduino-r1/verilog/dv/user_uart_master/run_iverilog |
| /root/riscduino-r1/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v |
| /root/riscduino-r1/verilog/dv/user_mbist_test1/Makefile |
| /root/riscduino-r1/verilog/dv/user_mbist_test1/run_iverilog |
| /root/riscduino-r1/verilog/dv/user_risc_boot/user_risc_boot_tb.v |
| /root/riscduino-r1/verilog/dv/user_risc_boot/Makefile |
| /root/riscduino-r1/verilog/dv/user_risc_boot/user_uart.c |
| /root/riscduino-r1/verilog/dv/user_risc_boot/user_risc_boot.c |
| /root/riscduino-r1/verilog/dv/user_risc_boot/run_iverilog |
| /root/riscduino-r1/verilog/dv/user_basic/user_basic_tb.v |
| /root/riscduino-r1/verilog/dv/user_basic/Makefile |
| /root/riscduino-r1/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v |
| /root/riscduino-r1/verilog/dv/user_risc_soft_boot/Makefile |
| /root/riscduino-r1/verilog/dv/user_risc_soft_boot/user_risc_boot.c |
| /root/riscduino-r1/verilog/dv/user_risc_soft_boot/run_iverilog |
| /root/riscduino-r1/verilog/dv/wb_port/wb_port_tb.v |
| /root/riscduino-r1/verilog/dv/wb_port/Makefile |
| /root/riscduino-r1/verilog/dv/wb_port/run_verilog |
| /root/riscduino-r1/verilog/dv/wb_port/wb_port.c |
| /root/riscduino-r1/verilog/dv/user_uart/Makefile |
| /root/riscduino-r1/verilog/dv/user_uart/user_uart_tb.v |
| /root/riscduino-r1/verilog/dv/user_uart/user_uart.c |
| /root/riscduino-r1/verilog/dv/user_uart/run_iverilog |
| /root/riscduino-r1/verilog/rtl/uprj_netlists.v |
| /root/riscduino-r1/verilog/rtl/user_proj_example.v |
| /root/riscduino-r1/verilog/rtl/user_project_wrapper.v |
| /root/riscduino-r1/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv |
| /root/riscduino-r1/verilog/rtl/wb_interconnect/src/wb_interconnect.sv |
| /root/riscduino-r1/verilog/rtl/wb_interconnect/src/wb_arb.sv |
| /root/riscduino-r1/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-r1/verilog/rtl/wb_host/src/wb_host.sv |
| /root/riscduino-r1/verilog/rtl/uart2wb/src/run_verilog |
| /root/riscduino-r1/verilog/rtl/uart2wb/src/uart2_core.sv |
| /root/riscduino-r1/verilog/rtl/uart2wb/src/uart_msg_handler.v |
| /root/riscduino-r1/verilog/rtl/uart2wb/src/uart2wb.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/filelist.f |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/top/usb1_host.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/phy/usb_transceiver.v |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/includes/usbh_host_defs.v |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/core/usbh_sie.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/core/usbh_crc5.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/core/usbh_core.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/core/usbh_crc16.sv |
| /root/riscduino-r1/verilog/rtl/usb1_host/src/core/usbh_fifo.sv |
| /root/riscduino-r1/verilog/rtl/mbist/run_verilator |
| /root/riscduino-r1/verilog/rtl/mbist/run_iverilog |
| /root/riscduino-r1/verilog/rtl/mbist/include/mbist_def.svh |
| /root/riscduino-r1/verilog/rtl/mbist/src/top/mbist_top2.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/top/mbist_top1.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/top/mbist_top.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_sti_sel.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_fsm.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_pat_sel.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_addr_gen.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_repair_addr.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_data_cmp.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_mux.sv |
| /root/riscduino-r1/verilog/rtl/mbist/src/core/mbist_op_sel.sv |
| /root/riscduino-r1/verilog/rtl/uart_i2c/src/uart_i2c_top.sv |
| /root/riscduino-r1/verilog/rtl/sar_adc/DAC_8BIT.v |
| /root/riscduino-r1/verilog/rtl/sar_adc/adc_reg.sv |
| /root/riscduino-r1/verilog/rtl/sar_adc/ACMP.sv |
| /root/riscduino-r1/verilog/rtl/sar_adc/SAR.sv |
| /root/riscduino-r1/verilog/rtl/sar_adc/sar_adc.sv |
| /root/riscduino-r1/verilog/rtl/sar_adc/ACMP_HVL.v |
| /root/riscduino-r1/verilog/rtl/sspim/src/filelist_spi.f |
| /root/riscduino-r1/verilog/rtl/sspim/src/sspim_if.sv |
| /root/riscduino-r1/verilog/rtl/sspim/src/sspim_ctl.sv |
| /root/riscduino-r1/verilog/rtl/sspim/src/sspim_top.sv |
| /root/riscduino-r1/verilog/rtl/sspim/src/sspim_cfg.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_fifo.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_top.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_tx.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_rx.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_clkgen.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/filelist.f |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_ctrl.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_regs.sv |
| /root/riscduino-r1/verilog/rtl/qspim/src/qspim_if.sv |
| /root/riscduino-r1/verilog/rtl/uart/src/uart_cfg.sv |
| /root/riscduino-r1/verilog/rtl/uart/src/uart_core.sv |
| /root/riscduino-r1/verilog/rtl/uart/src/uart_txfsm.sv |
| /root/riscduino-r1/verilog/rtl/uart/src/uart_rxfsm.sv |
| /root/riscduino-r1/verilog/rtl/i2cm/src/includes/i2cm_defines.v |
| /root/riscduino-r1/verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v |
| /root/riscduino-r1/verilog/rtl/i2cm/src/core/i2cm_top.v |
| /root/riscduino-r1/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v |
| /root/riscduino-r1/verilog/rtl/digital_core/run_modelsim |
| /root/riscduino-r1/verilog/rtl/digital_core/filelist_rtl.f |
| /root/riscduino-r1/verilog/rtl/digital_core/src/digital_core.sv |
| /root/riscduino-r1/verilog/rtl/digital_core/src/glbl_cfg.sv |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/run_modelsim |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/filelist_rtl.f |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v |
| /root/riscduino-r1/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/synth/synth.tcl |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/synth/base.sdc |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/synth/run_synth |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/synth/sta.tcl |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/synth/Makefile |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/run_modemsim |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/wb_top.files |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core.files |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv |
| /root/riscduino-r1/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv |
| /root/riscduino-r1/verilog/rtl/pinmux/src/pinmux.sv |
| /root/riscduino-r1/verilog/rtl/pinmux/src/gpio_control.sv |
| /root/riscduino-r1/verilog/rtl/pinmux/src/pwm.sv |
| /root/riscduino-r1/verilog/rtl/pinmux/src/pinmux_reg.sv |
| /root/riscduino-r1/verilog/rtl/pinmux/src/gpio_intr.sv |
| /root/riscduino-r1/verilog/rtl/clk_skew_adjust/synth/synth.tcl |
| /root/riscduino-r1/verilog/rtl/clk_skew_adjust/synth/Makefile |
| /root/riscduino-r1/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v |
| /root/riscduino-r1/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv |
| /root/riscduino-r1/verilog/rtl/lib/pulse_gen_type1.sv |
| /root/riscduino-r1/verilog/rtl/lib/async_fifo.sv |
| /root/riscduino-r1/verilog/rtl/lib/ctech_cells.sv |
| /root/riscduino-r1/verilog/rtl/lib/wb_interface.v |
| /root/riscduino-r1/verilog/rtl/lib/reset_sync.sv |
| /root/riscduino-r1/verilog/rtl/lib/ser_inf_32b.sv |
| /root/riscduino-r1/verilog/rtl/lib/async_reg_bus.sv |
| /root/riscduino-r1/verilog/rtl/lib/clk_buf.v |
| /root/riscduino-r1/verilog/rtl/lib/pulse_gen_type2.sv |
| /root/riscduino-r1/verilog/rtl/lib/ser_shift.sv |
| /root/riscduino-r1/verilog/rtl/lib/registers.v |
| /root/riscduino-r1/verilog/rtl/lib/sync_fifo.sv |
| /root/riscduino-r1/verilog/rtl/lib/async_fifo_th.sv |
| /root/riscduino-r1/verilog/rtl/lib/wb_stagging.sv |
| /root/riscduino-r1/verilog/rtl/lib/double_sync_low.v |
| /root/riscduino-r1/verilog/rtl/lib/async_wb.sv |
| /root/riscduino-r1/verilog/rtl/lib/double_sync_high.v |
| /root/riscduino-r1/verilog/rtl/lib/clk_ctl.v |
| /root/riscduino-r1/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv |
| /root/riscduino-r1/gds/.magicrc |
| /root/riscduino-r1/openlane/Makefile |
| /root/riscduino-r1/openlane/wb_interconnect/pdn.tcl |
| /root/riscduino-r1/openlane/wb_interconnect/base.sdc |
| /root/riscduino-r1/openlane/wb_interconnect/sta.tcl |
| /root/riscduino-r1/openlane/wb_interconnect/config.tcl |
| /root/riscduino-r1/openlane/wb_interconnect/interactive.tcl |
| /root/riscduino-r1/openlane/mbist1/base.sdc |
| /root/riscduino-r1/openlane/mbist1/sta.tcl |
| /root/riscduino-r1/openlane/mbist1/config.tcl |
| /root/riscduino-r1/openlane/mbist1/interactive.tcl |
| /root/riscduino-r1/openlane/wb_host/base.sdc |
| /root/riscduino-r1/openlane/wb_host/config.tcl |
| /root/riscduino-r1/openlane/wb_host/interactive.tcl |
| /root/riscduino-r1/openlane/mbist/base.sdc |
| /root/riscduino-r1/openlane/mbist/sta.tcl |
| /root/riscduino-r1/openlane/mbist/config.tcl |
| /root/riscduino-r1/openlane/mbist/interactive.tcl |
| /root/riscduino-r1/openlane/sar_adc/pdn.tcl |
| /root/riscduino-r1/openlane/sar_adc/config.tcl |
| /root/riscduino-r1/openlane/sar_adc/interactive.tcl |
| /root/riscduino-r1/openlane/qspim/pdn.tcl |
| /root/riscduino-r1/openlane/qspim/base.sdc |
| /root/riscduino-r1/openlane/qspim/sta.tcl |
| /root/riscduino-r1/openlane/qspim/config.tcl |
| /root/riscduino-r1/openlane/qspim/interactive.tcl |
| /root/riscduino-r1/openlane/uart_i2cm_usb_spi/pdn.tcl |
| /root/riscduino-r1/openlane/uart_i2cm_usb_spi/base.sdc |
| /root/riscduino-r1/openlane/uart_i2cm_usb_spi/sta.tcl |
| /root/riscduino-r1/openlane/uart_i2cm_usb_spi/config.tcl |
| /root/riscduino-r1/openlane/uart_i2cm_usb_spi/interactive.tcl |
| /root/riscduino-r1/openlane/syntacore/pdn.tcl |
| /root/riscduino-r1/openlane/syntacore/base.sdc |
| /root/riscduino-r1/openlane/syntacore/sta.tcl |
| /root/riscduino-r1/openlane/syntacore/config.tcl |
| /root/riscduino-r1/openlane/syntacore/interactive.tcl |
| /root/riscduino-r1/openlane/pinmux/base.sdc |
| /root/riscduino-r1/openlane/pinmux/config.tcl |
| /root/riscduino-r1/openlane/pinmux/interactive.tcl |
| /root/riscduino-r1/openlane/clk_skew_adjust/config.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/pdn.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/base.sdc |
| /root/riscduino-r1/openlane/user_project_wrapper/sta.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/config.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/gen_pdn.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/mod.tcl |
| /root/riscduino-r1/openlane/user_project_wrapper/interactive.tcl |
| /root/riscduino-r1/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/riscduino-r1/spef/qspim_top.spef |
| /root/riscduino-r1/spef/user_project_wrapper.spef |
| /root/riscduino-r1/spef/scr1_top_wb.spef |
| /root/riscduino-r1/spef/wb_host.spef |
| /root/riscduino-r1/spef/pinmux.spef |
| /root/riscduino-r1/spef/uart_i2c_usb_spi_top.spef |
| /root/riscduino-r1/spef/wb_interconnect.spef |
| /root/riscduino-r1/spef/mbist_top.spef |
