)]}'
{
  "commit": "26743b220f2d184cba74d212eccbaec4fc76ecc8",
  "tree": "685bf7b4ff5c7bb53ad1ce160d78aa5a390b62fc",
  "parents": [
    "337d9f86bef06f4583bf3a8327cb8efc597878ad"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 16 19:18:49 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 16 19:18:49 2021 +0530"
  },
  "message": "modelsim compile cleanup\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "eabaf4953a57c93c36dc45504ae86ce7ececc87c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv",
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}