)]}'
{
  "commit": "0081f48c68a7be711c439d0fabc80a350e46347d",
  "tree": "0885d4e61fd1df6f13036a849829fdf13bdb16f7",
  "parents": [
    "66179f714c7c48607c73df1eedf6747a4e95c3c2"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 23 15:38:36 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 23 15:38:36 2021 +0530"
  },
  "message": "timer_irq connectivity bug fix\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f6e545fe4381d77c59a8e12097e9218af1f6726e",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/Makefile",
      "new_id": "8aac4cced3b879672764b7176f5948f37a1425f7",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/Makefile"
    },
    {
      "type": "modify",
      "old_id": "68553707f9ecd65d07f8db5ad1ee6e9ac9adf003",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S",
      "new_id": "288b8fb3c6d8a835f64a7e251f538f279330a850",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S"
    },
    {
      "type": "modify",
      "old_id": "71b99281d3a0185d963c1c0aad1453a4fae9c5cd",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh",
      "new_id": "c00ffe3546f812fe71c9e8ebc8710ce0f17af76a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh"
    },
    {
      "type": "modify",
      "old_id": "bb51ee9d24d5b91b8ef844c73877f688319866ff",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv",
      "new_id": "b0efee3ac8b72501a546326772e37704b67b2e33",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv"
    },
    {
      "type": "modify",
      "old_id": "302adda49b78ece4ebfbca5a9a808da863f97512",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv",
      "new_id": "adc8f86a4125a026200a64e8c046033e1d555db3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv"
    }
  ]
}
