commit cb34d0977c95c1b359fdd51ec4cc9463ecc3133d
author dineshannayya <dinesh.annayya@gmail.com> Sun Nov 14 23:03:09 2021 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Sun Nov 14 23:03:09 2021 +0530
tree adc09ca546dccd7302cbf5396c442fe1de35654e
parent ff3bedde9d56ddae52490c00828eb93ade7e9be0

test bench update due to ctech cell addition in wb_host and mbist

verilog/dv/user_mbist_test1/user_mbist_test1_tb.v

diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
index 703de4b..2f8e946 100644
--- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -367,6 +367,35 @@
 	force u_top.u_wb_host.u_clkbuf_mem.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_mem.VNB = VSS;
 
+	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
+
+	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
+	
+	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VNB = VSS;
+
+	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VNB = VSS;
+
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
+	
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
     end
 `endif    
 

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 6ab16ab..3eedb96 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -49,6 +49,7 @@
     `include "lib/clk_ctl.v"
     `include "lib/reset_sync.sv"
     `include "lib/ser_inf_32b.sv"
+    `include "lib/ctech_cells.sv"
 
     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"