diff --git a/.gitmodules b/.gitmodules
index 4798126..e69de29 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "caravel"]
-	path = caravel
-	url = https://github.com/efabless/caravel-lite.git
diff --git a/README.md b/README.md
index ab6c9d4..4ecc1f7 100644
--- a/README.md
+++ b/README.md
@@ -45,7 +45,8 @@
     * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
     * Mbist controller with memory repair supported
     * Currently only Row Redudency is supported
-    * 2KB SRAM for data memory
+    * 4 Address location memory repair reported
+    * 2KB SRAM
     * Wishbone compatible design
     * Written in System Verilog
     * Open-source tool set
@@ -101,11 +102,21 @@
 
 The simulation package includes the following tests:
 
-
+* **wb_port**        - User Wishbone validation
+* **user_mbist_test1** - Standalone Mbist Controller Specific Test for Non Error/Single/Two/Three/Four/Five Location Error
 
 
 # Running Simulation
 
+Examples:
+``` sh
+    make verify-wb_port  
+    make verify-user_mbist_test1
+    make verify-wb_port SIM=RTL DUMP=OFF
+    make verify-wb_port SIM=RTL DUMP=ON
+    make verify-user_mbist_test1 SIM=RTL DUMP=OFF
+    make verify-user_mbist_test1 SIM=RTL DUMP=ON
+```
 
 # Tool Sets
 
diff --git a/caravel b/caravel
deleted file mode 160000
index 0f16ba8..0000000
--- a/caravel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 44d3f22..895c6ea 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -23,7 +23,7 @@
     # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
     # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
     # set_def $pdndef
-    puts "\[INFO\]:Dinesh-A: Running Placement Step"
+    puts "\[INFO\]: Running Placement Step"
     if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
         set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -35,7 +35,7 @@
 
 proc run_cts_step {args} {
     # set_def $::env(opendp_result_file_tag).def
-    puts "\[INFO\]:Dinesh-A: Running CTS"
+    puts "\[INFO\]: Running CTS"
     if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
         set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -50,7 +50,7 @@
     # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
     # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
     # set_def $resizerdef
-    puts "\[INFO\]:Dinesh-A: Running Routing"
+    puts "\[INFO\]: Running Routing"
     if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
         set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -60,7 +60,7 @@
 }
 
 proc run_diode_insertion_2_5_step {args} {
-    puts "\[INFO\]:Dinesh-A: Running Diode Insertion"
+    puts "\[INFO\]: Running Diode Insertion"
     # set_def $::env(tritonRoute_result_file_tag).def
     if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
         set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
@@ -75,7 +75,7 @@
 }
 
 proc run_power_pins_insertion_step {args} {
-    puts "\[INFO\]:Dinesh-A: Running Power Pin Insertion"
+    puts "\[INFO\]:Running Power Pin Insertion"
     # set_def $::env(tritonRoute_result_file_tag).def
     if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
         set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
@@ -91,7 +91,7 @@
 
 proc run_lvs_step {{ lvs_enabled 1 }} {
     # set_def $::env(tritonRoute_result_file_tag).def
-    puts "\[INFO\]:Dinesh-A: Running LVS Step"
+    puts "\[INFO\]:Running LVS Step"
     if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
         set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -105,7 +105,7 @@
 }
 
 proc run_drc_step {{ drc_enabled 1 }} {
-    puts "\[INFO\]:Dinesh-A: Running DRC"
+    puts "\[INFO\]:Running DRC"
     if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
         set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -118,7 +118,7 @@
 }
 
 proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    puts "\[INFO\]:Dinesh-A: Running Antenna checl"
+    puts "\[INFO\]: Running Antenna checl"
     if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
         set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
     } else {
@@ -220,7 +220,7 @@
 	foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 		set ::env(VDD_NET) $vdd
 		set ::env(GND_NET) $gnd
-                puts "\[INFO\]:Dinesh-A: Processing Power Nets: $vdd and $gnd."
+                puts "\[INFO\]: Processing Power Nets: $vdd and $gnd."
 
 		# internal macros power connections
 		set ::env(FP_PDN_MACROS) ""
@@ -239,7 +239,7 @@
 					}
 				}
 			} 
-                   puts "\[INFO\]:Dinesh-A: FP_PDN_MACROS: $::env(FP_PDN_MACROS) ."
+                   puts "\[INFO\]: FP_PDN_MACROS: $::env(FP_PDN_MACROS) ."
 		} else {
 			puts_warn "All internal macros will not be connected to power."
 		}
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
index 53183ae..703de4b 100644
--- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -92,7 +92,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(4, user_mbist_test1_tb);
+	   	$dumpvars(5, user_mbist_test1_tb);
 		$dumpoff;
 	   end
        `endif
@@ -129,7 +129,7 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Single Address Failure");
 	    	$display("###################################################");
-
+                $dumpon;
 		   // Check Is there is any BIST Error
 		   // [0]   - Bist Done      - 1
 		   // [1]   - Bist Error     - 0
@@ -149,7 +149,6 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Two Address Failure");
 	    	$display("###################################################");
-
 		// Check Is there is any BIST Error
 		// [0]   - Bist Done      - 1
 		// [1]   - Bist Error     - 0
@@ -185,6 +184,7 @@
 	        end else begin
 	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed");
 		 end
+                $dumpoff;
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Fours Address Failure");
 	    	$display("###################################################");
@@ -438,6 +438,19 @@
    end
    join_any
    disable fork; //disable pending fork activity
+
+   if(num_fault == 1)
+       wb_user_core_read_check('h3080_0014,read_data,{16'h0,7'h0,faultaddr[0]},32'h0000_FFFF);
+   if(num_fault == 2)
+       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+   if(num_fault == 3) begin
+       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3080_0014,read_data,{16'h0,7'h0,faultaddr[2]},32'h0000_FFFF);
+   end
+   if(num_fault >= 4) begin
+       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[3],7'h0,faultaddr[2]},32'hFFFF_FFFF);
+   end
 end
 endtask
 
@@ -482,6 +495,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  #1;
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -512,6 +526,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  #1;
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
diff --git a/verilog/rtl/lib/ser_inf_32b.sv b/verilog/rtl/lib/ser_inf_32b.sv
new file mode 100644
index 0000000..8228852
--- /dev/null
+++ b/verilog/rtl/lib/ser_inf_32b.sv
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  ser_inf_32                                                  ////
+////                                                              ////
+////  This file is part of the mbist_ctrl cores project           ////
+////  https://github.com/dineshannayya/mbist_ctrl.git             ////
+////                                                              ////
+////  Description                                                 ////
+////   This block manages the serial to Parallel conversion       ////
+////   This block usefull for Bist SDI/SDO access                 ////
+////   Function:                                                  ////
+////      1. When reg_wr=1, this block set shift=1 and shift      ////
+////         reg_wdata serial through sdi for 32 cycles and       ////
+////         asserts Reg Ack                                      ////
+////      2. When reg_rd=1, this block set shoft=1 and serial     ////
+////         capture the sdo to reg_rdata for 32 cycles and       ////
+////         asserts Reg Ack                                      ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.0 - 20th Oct 2021, Dinesh A                             ////
+////          Initial integration                                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module ser_inf_32b
+       (
+
+    // Master Port
+       input   logic               rst_n       ,  // Regular Reset signal
+       input   logic               clk         ,  // System clock
+       input   logic               reg_wr      ,  // Write Request
+       input   logic               reg_rd      ,  // Read Request
+       input   logic [31:0]        reg_wdata   ,  // data output
+       output  logic [31:0]        reg_rdata   ,  // data input
+       output  logic               reg_ack     ,  // acknowlegement
+
+    // Slave Port
+       output  logic               sdi         ,  // Serial SDI
+       output  logic               shift       ,  // Shift Signal
+       input   logic               sdo            // Serial SDO
+
+    );
+
+
+    parameter IDLE = 1'b0;
+    parameter SHIFT_DATA = 1'b1;
+
+    logic        state;
+    logic [5:0]  bit_cnt;
+    logic [31:0] shift_data;
+
+
+always@(negedge rst_n or posedge clk)
+begin
+   if(rst_n == 0) begin
+      state   <= IDLE;
+      reg_rdata <= 'h0;
+      reg_ack <= 1'b0;
+      sdi     <= 1'b0;
+      bit_cnt <= 6'h0;
+      shift   <= 'b0;
+      shift_data <= 32'h0;
+   end else begin
+       case(state)
+       IDLE: begin
+                reg_ack <= 1'b0;
+                bit_cnt    <= 6'h0;
+		if(reg_wr) begin
+                   shift      <= 'b1;
+	           shift_data <= reg_wdata;
+		   state      <= SHIFT_DATA;
+                end else if(reg_rd) begin
+                   shift      <= 'b1;
+	           shift_data <= 'h0;
+	           state      <= SHIFT_DATA;
+	        end
+	     end
+        SHIFT_DATA: begin 
+		shift_data <= {1'b0,shift_data[31:1]};
+		reg_rdata  <= {sdo,reg_rdata[31:1]};
+	        sdi        <= shift_data[0];
+              	if(bit_cnt < 31) begin
+		    bit_cnt    <= bit_cnt +1;
+	        end else begin
+                    reg_ack <= 1'b1;
+                    shift   <= 'b0;
+                    state   <= IDLE;
+	        end
+	     end
+       endcase
+   end
+end
+
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/mbist_mux.sv b/verilog/rtl/mbist/src/mbist_mux.sv
index cd2ebe2..23edd6c 100755
--- a/verilog/rtl/mbist/src/mbist_mux.sv
+++ b/verilog/rtl/mbist/src/mbist_mux.sv
@@ -58,6 +58,9 @@
       input   logic                      bist_error,
       input   logic  [BIST_ADDR_WD-1:0]  bist_error_addr,
       output  logic                      bist_correct,
+      input   logic                      bist_sdi,
+      input   logic                      bist_shift,
+      output  logic                      bist_sdo,
 
       // FUNCTIONAL CTRL SIGNAL
       input   logic                      func_clk_a,
@@ -117,23 +120,29 @@
 mbist_repair_addr u_repair_A(
     .AddressOut    (mem_addr_a       ),
     .Correct       (bist_correct     ),
+    .sdo           (bist_sdo         ),
 
     .AddressIn     (addr_a           ),
     .clk           (mem_clk_a        ),
     .rst_n         (rst_n            ),
     .Error         (bist_error       ),
-    .ErrorAddr     (bist_error_addr  )
+    .ErrorAddr     (bist_error_addr  ),
+    .scan_shift    (bist_shift       ),
+    .sdi           (bist_sdi         )
 );
 
 mbist_repair_addr u_repair_B(
     .AddressOut    (mem_addr_b      ),
     .Correct       (                ), // Both Bist Correct are same
+    .sdo           (                ),
 
     .AddressIn     (addr_b          ),
     .clk           (mem_clk_b       ),
     .rst_n         (rst_n           ),
     .Error         (bist_error      ),
-    .ErrorAddr     (bist_error_addr )
+    .ErrorAddr     (bist_error_addr ),
+    .scan_shift    (1'b0            ), // Both Repair hold same address
+    .sdi           (1'b0            )
 );
 
 
diff --git a/verilog/rtl/mbist/src/mbist_repair_addr.sv b/verilog/rtl/mbist/src/mbist_repair_addr.sv
index f6508ac..8aea358 100644
--- a/verilog/rtl/mbist/src/mbist_repair_addr.sv
+++ b/verilog/rtl/mbist/src/mbist_repair_addr.sv
@@ -53,17 +53,25 @@
 	
     output logic [BIST_RAD_WD_O-1:0] AddressOut,
     output logic                     Correct,
+    output  logic                    sdo,         //  scan data output
 
     input logic [BIST_RAD_WD_I-1:0]  AddressIn,
     input logic                      clk,
     input logic                      rst_n,
     input logic                      Error,
-    input logic [BIST_RAD_WD_I-1:0]  ErrorAddr
+    input logic [BIST_RAD_WD_I-1:0]  ErrorAddr,
+    input logic                      scan_shift,  //  shift scan input
+    input logic                      sdi          //  scan data input 
 
 
 );
 
 logic [3:0]   ErrorCnt; // Assumed Maximum Error correction is less than 16
+logic [15:0]  shift_reg;
+logic [15:0]  shift_load;
+logic [7:0]   shift_cnt;
+logic         scan_shift_d;
+logic         shift_pos_edge;
 
 logic [BIST_RAD_WD_I-1:0] RepairMem [0:BIST_ERR_LIMIT-1];
 
@@ -95,8 +103,42 @@
    end
 end
 
+/********************************************
+* Serial shifting the Repair address
+* *******************************************/
 
+always@(posedge clk or negedge rst_n)
+begin
+   if(!rst_n) begin
+     shift_reg   <= '0;
+     shift_cnt   <= '0;
+     scan_shift_d <= 1'b0;
+   end begin
+      if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin
+         shift_cnt <= shift_cnt+1;
+      end
+      scan_shift_d <= scan_shift;
+      shift_reg <= shift_load;
+   end
+end
 
+// Detect scan_shift pos edge
+assign shift_pos_edge = (scan_shift_d ==0) && (scan_shift);
+
+always_comb 
+begin
+  shift_load = shift_reg;
+  // Block the data reloading every pos edge of shift
+  if(scan_shift && ((shift_cnt[7:4]+1) < BIST_ERR_LIMIT) && (shift_cnt[3:0] == 4'b1111))
+     shift_load = {RepairMem[shift_cnt[7:4]+1]};
+  else if(scan_shift)
+     shift_load = {sdi,shift_reg[15:1]};
+  else
+     shift_load = {RepairMem[shift_cnt[7:4]]};
+  
+end
+
+assign sdo   = shift_reg[0];
 endmodule
 
 
diff --git a/verilog/rtl/mbist/src/mbist_top.sv b/verilog/rtl/mbist/src/mbist_top.sv
index 71470cc..fbb46bd 100644
--- a/verilog/rtl/mbist/src/mbist_top.sv
+++ b/verilog/rtl/mbist/src/mbist_top.sv
@@ -34,7 +34,10 @@
 ////                                                              ////
 ////  Revision :                                                  ////
 ////    0.0 - 11th Oct 2021, Dinesh A                             ////
-////          Initial integration 
+////          Initial integration                                 ////
+////    0.1 - 26th Oct 2021, Dinesh A                             ////
+////          Fixed Error Address are serial shifted through      ////
+////          sdi/sdo                                             ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 
@@ -120,7 +123,7 @@
 
 //---------------------------------
 // SDI => SDO diasy chain
-// bist_sdi => bist_addr_sdo =>  bist_sti_sdo =>  bist_op_sdo => bist_sdo
+// bist_sdi => bist_addr_sdo =>  bist_sti_sdo =>  bist_op_sdo => bist_pat_sdo => bist_sdo
 // ---------------------------------
 logic                    bist_addr_sdo   ;                 
 logic                    bist_sti_sdo    ;                 
@@ -285,11 +288,11 @@
       u_pat_sel (
                     .pat_last           (last_pat           ),
                     .pat_data           (pat_data           ),
-                    .sdo                (bist_sdo           ),
+                    .sdo                (bist_pat_sdo       ),
                     .clk                (bist_clk           ),
                     .rst_n              (srst_n             ),
                     .run                (run_pat            ),
-                    .scan_shift         (scan_shift         ),
+                    .scan_shift         (bist_shift         ),
                     .sdi                (bist_op_sdo        )
 
    );
@@ -348,6 +351,9 @@
                     .bist_error           (bist_error_correct),
                     .bist_error_addr      (bist_error_addr),
                     .bist_correct         (bist_correct  ),
+		    .bist_sdi             (bist_pat_sdo),
+		    .bist_shift           (bist_shift),
+		    .bist_sdo             (bist_sdo),
 
                     // FUNCTIONAL CTRL SIGNAL
                     .func_clk_a          (func_clk_a     ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 6c317e9..6ab16ab 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -16,6 +16,7 @@
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
 `define USE_POWER_PINS
+`define UNIT_DELAY #0.1
 
 `ifdef GL
     // Assume default net type to be wire because GL netlists don't have the wire definitions
@@ -47,6 +48,7 @@
     `include "lib/registers.v"
     `include "lib/clk_ctl.v"
     `include "lib/reset_sync.sv"
+    `include "lib/ser_inf_32b.sv"
 
     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index a8f081a..94dd3fa 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -136,7 +136,7 @@
 logic               wbm_err_int; // error
 
 logic               reg_sel    ;
-logic [1:0]         sw_addr    ;
+logic [2:0]         sw_addr    ;
 logic               sw_rd_en   ;
 logic               sw_wr_en   ;
 logic [31:0]        reg_rdata  ;
@@ -146,6 +146,8 @@
 logic               sw_wr_en_1;
 logic               sw_wr_en_2;
 logic               sw_wr_en_3;
+logic               sw_wr_en_4;
+logic               sw_rd_en_5;
 logic [7:0]         cfg_bank_sel;
 logic [31:0]        wbm_adr_int;
 logic               wbm_stb_int;
@@ -170,6 +172,10 @@
 
 logic [31:0]        cfg_bist_ctrl    ;
 logic [31:0]        cfg_bist_status  ;
+logic               ser_acc          ; // Serial Access
+logic               non_ser_acc      ; // Non Serial Access
+logic [31:0]        serail_dout      ;
+logic               serial_ack       ;
 
 assign io_out = 'h0;
 assign io_oeb  = 'h0;
@@ -186,14 +192,21 @@
 // To reduce the load/Timing Wishbone I/F, Strobe is register to create
 // multi-cycle
 logic wb_req;
+logic wb_req_d;
+logic wb_req_pedge;
 always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
     if ( wbm_rst_n == 1'b0 ) begin
-        wb_req   <= '0;
+        wb_req     <= '0;
+        wb_req_d   <= '0;
    end else begin
        wb_req   <= wbm_stb_i && (wbm_ack_o == 0) ;
+       wb_req_d <= wb_req;
    end
 end
 
+// Detect pos edge of request
+assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
+
 assign  wbm_dat_o   = (reg_sel) ? reg_rdata : wbm_dat_int;  // data input
 assign  wbm_ack_o   = (reg_sel) ? reg_ack   : wbm_ack_int; // acknowlegement
 assign  wbm_err_o   = (reg_sel) ? 1'b0      : wbm_err_int;  // error
@@ -211,31 +224,33 @@
 // ---------------------------------------------------------------------
 assign reg_sel       = wb_req & (wbm_adr_i[23] == 1'b1);
 
-assign sw_addr       = wbm_adr_i [3:2];
+assign sw_addr       = wbm_adr_i [4:2];
 assign sw_rd_en      = reg_sel & !wbm_we_i;
 assign sw_wr_en      = reg_sel & wbm_we_i;
 
-assign  sw_wr_en_0 = sw_wr_en && (sw_addr==0);
-assign  sw_wr_en_1 = sw_wr_en && (sw_addr==1);
-assign  sw_wr_en_2 = sw_wr_en && (sw_addr==2);
-assign  sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+assign  sw_wr_en_0 = sw_wr_en && (sw_addr=='h0);
+assign  sw_wr_en_1 = sw_wr_en && (sw_addr=='h1);
+assign  sw_wr_en_2 = sw_wr_en && (sw_addr=='h2);
+assign  sw_wr_en_3 = sw_wr_en && (sw_addr=='h3);
+assign  sw_wr_en_4 = sw_wr_en && (sw_addr=='h4);
+assign  sw_rd_en_5 = sw_rd_en && (sw_addr=='h5);
+
+
+assign ser_acc = sw_wr_en_4 | sw_rd_en_5;
+assign non_ser_acc = reg_sel ? !ser_acc : 1'b0;
 
 always @ (posedge wbm_clk_i or negedge wbm_rst_n)
 begin : preg_out_Seq
-   if (wbm_rst_n == 1'b0)
-   begin
+   if (wbm_rst_n == 1'b0) begin
       reg_rdata  <= 'h0;
       reg_ack    <= 1'b0;
-   end
-   else if (sw_rd_en && !reg_ack) 
-   begin
+   end else if (ser_acc && serial_ack)  begin
+      reg_rdata <= serail_dout ;
+      reg_ack   <= 1'b1;
+   end else if (non_ser_acc && !reg_ack) begin
       reg_rdata <= reg_out ;
       reg_ack   <= 1'b1;
-   end
-   else if (sw_wr_en && !reg_ack) 
-      reg_ack          <= 1'b1;
-   else
-   begin
+   end else begin
       reg_ack        <= 1'b0;
    end
 end
@@ -253,23 +268,24 @@
 // BIST Control
 assign bist_en           = cfg_bist_ctrl[0];
 assign bist_run          = cfg_bist_ctrl[1];
-assign bist_shift        = cfg_bist_ctrl[2];
-assign bist_load         = cfg_bist_ctrl[3];
-assign bist_sdi          = cfg_bist_ctrl[4];
+assign bist_load         = cfg_bist_ctrl[2];
 
 // BIST Status
-assign cfg_bist_status   = {24'h0,bist_sdo,bist_error_cnt,bist_correct,bist_error,bist_done};
+assign cfg_bist_status   = {25'h0,bist_error_cnt,bist_correct,bist_error,bist_done};
 
 
 always @( *)
 begin 
   reg_out [31:0] = 8'd0;
 
-  case (sw_addr [1:0])
-    2'b00 :   reg_out [31:0] = reg_0;
-    2'b01 :   reg_out [31:0] = reg_1;
-    2'b10 :   reg_out [31:0] = cfg_bist_ctrl [31:0];    
-    2'b11 :   reg_out [31:0] = cfg_bist_status [31:0];     
+  case (sw_addr [2:0])
+    3'b000 :   reg_out [31:0] = reg_0;
+    3'b001 :   reg_out [31:0] = reg_1;
+    3'b010 :   reg_out [31:0] = cfg_bist_ctrl [31:0];    
+    3'b011 :   reg_out [31:0] = cfg_bist_status [31:0];     
+    3'b100 :   reg_out [31:0] = 'h0; // Serial Write Data
+    3'b101 :   reg_out [31:0] = serail_dout; // This is with  Shift
+    3'b110 :   reg_out [31:0] = serail_dout; // This is previous Shift 
     default : reg_out [31:0] = 'h0;
   endcase
 end
@@ -309,6 +325,31 @@
 
 
 
+
+ser_inf_32b u_ser_intf
+       (
+
+    // Master Port
+       .rst_n       (wbm_rst_n),  // Regular Reset signal
+       .clk         (wbm_clk_i),  // System clock
+       .reg_wr      (sw_wr_en_4 & wb_req_pedge),  // Write Request
+       .reg_rd      (sw_rd_en_5 & wb_req_pedge),  // Read Request
+       .reg_wdata   (wbm_dat_i) ,  // data output
+       .reg_rdata   (serail_dout),  // data input
+       .reg_ack     (serial_ack),  // acknowlegement
+
+    // Slave Port
+       .sdi         (bist_sdi),    // Serial SDI
+       .shift       (bist_shift),  // Shift Signal
+       .sdo         (bist_sdo)     // Serial SDO
+
+    );
+
+
+//--------------------------------------------------
+// Wishbone Master to Wishbone Slave 
+// -------------------------------------------------
+
 assign wbm_stb_int = wb_req & !reg_sel;
 
 // Since design need more than 16MB address space, we have implemented