)]}' { "commit": "fe4778a90a6bf9680b95e6621ee9480ba7d89406", "tree": "6f1d7ed6845c9f4a87b5662feccf830f697dc164", "parents": [ "2a3c94373ffc0e53a287be94a569a2139b1cb496" ], "author": { "name": "nguyendao-uom", "email": "nguyen.dao@manchester.ac.uk", "time": "Tue Dec 28 11:07:32 2021 +0000" }, "committer": { "name": "nguyendao-uom", "email": "nguyen.dao@manchester.ac.uk", "time": "Tue Dec 28 11:07:32 2021 +0000" }, "message": "update icesoc\n", "tree_diff": [ { "type": "modify", "old_id": "793bf634c2c1b1af90be95fcd85688e869bfb667", "old_mode": 57344, "old_path": "caravel", "new_id": "860878e32b033d76fda7cf6ea7212fa697ef6eee", "new_mode": 57344, "new_path": "caravel" }, { "type": "modify", "old_id": "0527663dcd9dd0918690a8c96dcd8fe3dbf942e5", "old_mode": 33188, "old_path": "def/user_project_wrapper.def", "new_id": "c1f295b16b60b033488f0b16c43ed9562dbf0554", "new_mode": 33188, "new_path": "def/user_project_wrapper.def" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "7c973d95faee0ec45ac916a74d3f447f568155fe", "new_mode": 33188, "new_path": "gds/user_project_wrapper.gds.gz" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "712c038f17df0d731da965478ff3fd0bbb33e2c9", "new_mode": 33188, "new_path": "info.yaml" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "2a633615f31fde1a49369b4cb0e84354ad59718f", "new_mode": 33188, "new_path": "lef/eFPGA_CPU_top.lef" }, { "type": "modify", "old_id": "f5854c30df6f1bedb1496b6d4f71a9567c860f04", "old_mode": 33188, "old_path": "lef/user_project_wrapper.lef", "new_id": "bca152c0aa5ec03de311d8478ee4ef7bb4ac4bd9", "new_mode": 33188, "new_path": "lef/user_project_wrapper.lef" }, { "type": "modify", "old_id": "5006ced434254d9ebae1d4519ca1b583ddb362b7", "old_mode": 33261, "old_path": "openlane/user_project_wrapper/config.tcl", "new_id": "3a7dbfba8b638b88d344310afaf10f74808395b9", "new_mode": 33261, "new_path": "openlane/user_project_wrapper/config.tcl" }, { "type": "modify", "old_id": "a7365ab26ff25197ed46ceb62342f48e1473ea19", "old_mode": 33188, "old_path": "openlane/user_project_wrapper/macro.cfg", "new_id": "884c6b8fc2f8c0c15e06cb8daf74a12fa499f9a9", "new_mode": 33188, "new_path": "openlane/user_project_wrapper/macro.cfg" }, { "type": "delete", "old_id": "8797dcdee01982869d8ce5675cdc7171aa9a1275", "old_mode": 40960, "old_path": "openlane/user_project_wrapper/pin_order.cfg", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "90cde69dafd452ecc23a064a28755acbb930dc37", "new_mode": 33188, "new_path": "openlane/user_project_wrapper/pin_order.cfg" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0291c3a1abb5266d0e1ee15c6336c3f75f96e359", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/Makefile" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ade76f21ab3873eb66beff7e69d0fcdb93f5e850", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/Makefile" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9cc353c1d19f0f020ef14ab8cf115f51f5265f78", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/aes_common.h" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "5cdfafa7eedcf835e595ed21df8a53743c14d68c", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/crt.s" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9bc356fa90b6b04600fe8f63a696c69a6a087d49", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/gen_program.py" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "a30bbd48c14fdaee18551bcfa6467b48397947c4", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/link.ld" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "5040a3e8359d897bf2fcd928df0e6d6892140f0f", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/rv32zk.S" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "bf13a54f2b72eb568df1143c104da77a2e4f2038", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/test.c" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e3c0d0993165618230567c03b5a34ade5db4c53e", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/ibex_prog/zkn.h" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "77ccdf76ebc9d93e8e4633f1cd9c8aa813d2d5e0", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/wb_test_icesoc.c" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b26d03a79f8ac3da7079348a6aa5c949c057ab74", "new_mode": 33188, "new_path": "verilog/dv/wb_test_icesoc/wb_test_icesoc_tb.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "829ad5078138b1ab81ba9e90638e5595e506d6b0", "new_mode": 33188, "new_path": "verilog/dv/wb_to_sram/Makefile" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "fd864c869642b5881ffc9c5d5b3988daf5fa48a1", "new_mode": 33188, "new_path": "verilog/dv/wb_to_sram/wb_to_sram.c" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "38a5cff0901b1135222a3651ef90ee26767cc69f", "new_mode": 33261, "new_path": "verilog/dv/wb_to_sram/wb_to_sram.hex" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "d4d1ee183e5728547ae5d5e6f44890debdf8c361", "new_mode": 33188, "new_path": "verilog/dv/wb_to_sram/wb_to_sram_tb.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8da90bf644bb0a4dc9451153a8af7929c173c91b", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_CPU_top.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "37cf652da6a92e3579d577e413d1b72611404ac0", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/Config.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "fa143aca3c63d63c7a8233289132b147d4b186ca", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/ConfigFSM.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "014f33ae89b066f2a82e3fa2e1cef0db70010f5c", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/Config_access.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "f8b197198d26f7b56d80f26958bc4a064d047ccd", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/Frame_Data_Reg_Pack.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "7423643811050e62df00d5de069034ccf0a2e094", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/Frame_Select_Pack.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "17e691d573a2a228c2aceecacd59a1bc16b846c3", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/bitbang.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "1cf9cd20fdc55757e5ed7cd97add298fa6ec2cdf", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/config_UART.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "25385f98b2d5d37e5746e4f75353f68bf6dfc9c3", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/eFPGAconf_netlists.vh" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "217478b44b037c83f23e7d9b194c767b2ab5f612", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_conf/fabric_DSP_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "71d4e0dc21b7be7692d6b899ad00f003d254fb97", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_bot_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "26f4e78d1f57b35f3533b14ccc984f4400d1fd4e", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_bot_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "d14f814ac36e93f0193a39c34027585aed963fdb", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_bot_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "abd773ca7908a1316296112dbbc96edc0ede4d8b", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b933548ebab9a8d192a645121f164c80488ca205", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_top_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b2402dea7bc0978d4580d22c498185cde8a0dae6", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_top_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "cd3f3105abf1fb06bc6e014e4307bf80a1fd1739", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/DSP_top_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "56b07d65633602a2a0ff3e154581c523f30ffe5a", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "727f86776fe9235f87280761e5e14af63c9413dd", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_bot_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "05ccd1020d21cfe016b886af2ff1171794148ac4", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_bot_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9e3731f76412743a48838e1511c6fcb836b5e218", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_bot_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "dd9a9080368aa45b4e58134387e24702ab378742", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "da84af68e6f70208ac673cac386df8b2542bae8b", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/E_CPU_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "1c48e5580488ab1eb59e3c63176f7a108c0e2dae", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/IO_1_bidirectional_frame_config_pass.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c008ce3b4cd5616cb4ce164f17868620895455c3", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/InPass4_frame_config_mux.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "76d0dd6a39e7220f316e27d8fbb49b856d47750a", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/LUT4AB_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c229ab11efe2a84574ee3b9a6cca6514723c007d", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/LUT4AB_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "591d44d01b9df023320e482b212bdcc90462ebe2", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/LUT4AB_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "85c0bda87c6c4c9d72ff7250da77c646d1ca78e7", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/LUT4c_frame_config_dffesr.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "d04ac1717bd78129ca708a2706fe72116c42f261", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/MULADD.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "05310ede4da5b09443a9345f236fe33f7ef508fd", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/MUX8LUT_frame_config_mux.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "191c608c79b6d261604efebaa4340d49e8058236", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_DSP_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "99063cb76099164780afb65ed1145eca4741c2fd", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_DSP_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e32ce137bb4bb7ec67909dd53342eaaf065969c8", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_RAM_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "37ce9ae692b6e7a88edeb1dbb9eb870fcfe59427", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_RAM_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "25270dbb7d54bd93680347a6e136545234a8f341", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_single2_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0cc1a736abaf31613555b45333707ae62f53eed9", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_single2_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c5ef424d7b2e0a3768e42013d24376ee3aa89b79", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_single_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e5e54092d4de938e7ad3edeaada1d979e97b2f14", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/N_term_single_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "4668174a50ee5c06fe1c7ea71d5ee48010e57715", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/OutPass4_frame_config_mux.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "f4449984d910361832d451315c0e4f33029c097b", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RAM_IO_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "114335c7d07c5f3038159406264bcf1dfbbe3007", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RAM_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "5cbbe320b6923e420f8d8ee2614c98525aa76f53", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RAM_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "01032e10105aebafa5174f2114c479f2fee4734d", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RegFile_32x4.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b6fa03bf1b07d4880a18377d96cb490d1e9dfaa7", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RegFile_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "81345d1becfb072e2beacda1f2d162838b2260d4", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RegFile_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c1faec310cef3db25029e5755278947c50ea204a", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/RegFile_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "312527ea2631f8b253895112ce5c075804d9ac7f", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_DSP_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "19324e27c4993a552c907689dec8c380904be75f", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_DSP_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8af861b578c7ed6a94f09948d69be0bb7b08916c", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_RAM_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3660cce1283b722d79b775edf1c46ac3fa693a64", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_RAM_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "47eded7a2e8041d13f535bcce0da372c34aa0176", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_single2_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ae84adeda1f7cc69c4b8c5c5a41b3f0977cc791d", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_single2_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "baf7be32d953374c385599ee0750cd8f2ec0951c", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_single_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ef1a1f4e7bfc0d50d20931cea55cf633bb89956d", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/S_term_single_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9f44f1d10e4cd3ac95df3d3df86744f5715e6d1b", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b35531d2feea1fc9109ea09b12d45902a51b9097", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_bot_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "7e9dc2946893bb1c36e28d017b4abb2ea9ced5dc", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_bot_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9469d67ba719f8b58c27f0531d05a4c03faea5b0", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_bot_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "851f85c959e7f09e6eb9395c54545f964d7b6420", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "83555464e3bb28c267adb8be37e6cd441d48b8e8", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_CPU_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e49fadc329e5acc7b432021a2451f184e9e5f202", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_IO_ConfigMem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "fac4c0ae392d0ec9e8be7994ad65ef768e36aa68", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_IO_switch_matrix.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ab4f260ad8f960f4e45f23fc952d3d9c32aaf9c2", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/W_IO_tile.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8d0affd641f4cb954922f7da0bcb97b17a645507", "new_mode": 33188, "new_path": "verilog/rtl/eFPGA_core/eFPGAcore_netlists.vh" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "1a126d1761a29f0fed529de125f91e01d4308655", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_alu.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "95ee5fae78726d959daf438cc1b2a61d84b9c075", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_compressed_decoder.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ade64aa3be52ba263e89af30b61cee329bed4d4c", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_controller.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8fa21250518569561d91eb165ca22c8b025f00eb", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_core.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0230adc1ea59ba934b22e98f60f51401810c9483", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_cs_registers.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "d763cfff673a7edd29040de6a38769c001d3aa9d", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_decoder.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8b137891791fe96927ad78e64b0aad7bded08bdc", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_defines.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "78389c5cf0576a095877817a2507b2bfb00989bf", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_eFPGA.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "f4d2e47b1cab8b4590b696cc563a6e6f37f0de8a", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_ex_block.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9117da75931fd75bfba346eb9ed20302c382bef3", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_fetch_fifo.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "dfc16cb2c1e5b4c6ef4293729e654dcea4b383db", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_id_stage.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "329709c0ae9026da0c90ed66e3d92fa17ed98db9", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_if_stage.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "6ed4e7fd2da2b67a42ee2a3a015e3096882c7cbd", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_int_controller.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8d35751b4f525ab6b84dc67b1014d7de3ab22985", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_load_store_unit.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0c2e0ddcb9c9852d21f8fa081af2d8d43e8eda24", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_multdiv_fast.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8919dec10eaf3b442e149faa33caf6272dfbe275", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_prefetch_buffer.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c7ebfacf2001aa8773e42e7a02fde75baaa2a0cc", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_ibex_register_file.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0d11945398f770d882c2eac297c3e72358ab73c1", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/flexbex_prim_clock_gating.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "abe658d6e6a7ff97c9dc64980c29cabea4576431", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_aes_sbox.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b5ec3ef2d1de7f5b3683ae41f27e72a1728134ed", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_alu.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0fe812664f2533de55373ef68404963429ba01c9", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_branch_predict.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "131abd10a96798b2cc6702cf87eaf8204f6ddf35", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_compressed_decoder.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "fec6b6bf0f476070d41b5a6bfc38f8e8480ff67d", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_controller.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "209a9ceafed4510bfb12927d2c33592679fa2cb1", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_core.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "159d73531558d8dfd9f7faa2a083b6644d8a365e", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_counter.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3135d7ac7efc0b31982ce84380ad32c2ae07ae38", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_cs_registers.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "edae878e0cd6929e1bfe570797283d0ba9cab545", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_csr.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ae09c5d2bd9ebbc4c793cb166f1c61c9b619fd95", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_decoder.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c2018084741b376af461041debe84998295a1a7c", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_eFPGA.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ed5140934a0cd66fd6887f5cd58ee9d8b729e692", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_ex_block.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9ecc882a4996169be3e9baee07567cb50354009f", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_fetch_fifo.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "fc2ad5c0c25f8f46164ffe1fd87385015cdb6449", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_icache.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3eec58df725a610f2fda11aabc252b9c8ec1f0d0", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_id_stage.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "eda4468cf67aa1458540dab88c735af6049f7ca3", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_if_stage.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c9abb0b262740efc5c0ed3dc273cab1fd1ea211f", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_load_store_unit.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "8922093eb46c7d9cb88fbb55bcee3fa1cbcdbc39", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_multdiv_fast.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "43ca1bf1c71063bd8c79a0718bf0c9959ff9c2be", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_multdiv_slow.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e7e7ea0f40cd5f5e64a8685ce16fcabe4e4ae8a8", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_poly16_mul.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e7345163c3dda1d0075fa7b63379ba5ef7dd37b2", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_prefetch_buffer.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b11bc487ded6b0e0a2797e2d9958f9acb7725017", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_register_file_ff.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "a249fcfb4e114fda6a2aceb2c3a2bd1cef8b06a2", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_register_file_fpga.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "4bbdacdd9de65c9e018316131d66155dac00df6f", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_register_file_latch.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9abf01d958c3b91e3bc5580cf96f92a8c266bc42", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_sm4_sbox.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "4aeb609688f6716164b6804009e90857dbf6bc3a", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_top.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3460e52d0a4296bf439ebfbb78d68c56409c9df8", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_wb_stage.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "1e80e35eae64e09d16bbacde3df09c5aeb8bc73e", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibex_zk.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "50091772763d95e7d15d0c2fec11b33af4998bc9", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/ibexcore_netlists.vh" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "4c79019650bca4c01767b4fa9d6988dae224cd7f", "new_mode": 33188, "new_path": "verilog/rtl/ibex_core/prim_clock_gating.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "a87640683a9b32c6a0083f9dafc173ab049528a1", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/axi_uart.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "c0e7c13b3e1d2bdc6e3edec170f3d794d26533cb", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/icesoc_netlists.vh" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "5b0a066d41502adb64f2db7f749d4627743827ec", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/icesoc_top.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3aa2b091436a3e9f3df74cdfe781927ee675e7c6", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/inter.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "3fedbf8acacfa1d4014811d41a59b0fe025a4219", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/inter_read.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ee1a51dfab1c9dcf1f37f512bbea65acde5e2cfc", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/peripheral.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0be018f0c5f069f95cd3947a4181aa199005c5cb", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/sky130_sram_1kbyte_1rw1r_32x256_8.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "f1095c264c12fe5353466fb20ab04149fc2609f6", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/uart.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "9c7985daa41c48154ab216fe839a6bba756b463f", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/uart_rx.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "dace924552fa7646f02087e0477f0413afbe42d5", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/uart_to_mem.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "518b6d3f2f4f119d16da71422d196b1449306cfb", "new_mode": 33188, "new_path": "verilog/rtl/icesoc/uart_tx.v" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b30bd69b265c5a64ae5f30abbccd21936ec1570e", "new_mode": 33188, "new_path": "verilog/rtl/models_pack.v" }, { "type": "modify", "old_id": "5ee1ceecfb5f08335c33a73de2e09ef869af17a9", "old_mode": 33188, "old_path": "verilog/rtl/user_project_wrapper.v", "new_id": "a1590a6bba9aa081eeb36e6e1214318a27ffb6c6", "new_mode": 33188, "new_path": "verilog/rtl/user_project_wrapper.v" } ] }