diff --git a/caravel b/caravel
index 793bf63..860878e 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 793bf634c2c1b1af90be95fcd85688e869bfb667
+Subproject commit 860878e32b033d76fda7cf6ea7212fa697ef6eee
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index 0527663..c1f295b 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -1303,13 +1303,15 @@
 TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ;
 TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ;
 GCELLGRID X 0 DO 423 STEP 6900 ;
-GCELLGRID Y 0 DO 511 STEP 6900 ;
-VIAS 2 ;
+GCELLGRID Y 0 DO 510 STEP 6900 ;
+VIAS 4 ;
     - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 350 350 350 350  + ROWCOL 2 2  ;
-    - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 350 400 350  + ROWCOL 2 1  ;
+    - via4_3000x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 1100 350 1100 350  + ROWCOL 2 1  ;
+    - via4_1200x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 200 350 310 350  + ROWCOL 2 1  ;
+    - via4_1740x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 470 350 470 350  + ROWCOL 2 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+    - inst_eFPGA_CPU_top eFPGA_CPU_top + FIXED ( 20000 150000 ) N ;
 END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
@@ -3424,237 +3426,294 @@
       + PORT
         + LAYER met2 ( -280 -3600 ) ( 280 3600 )
         + PLACED ( 2899150 -1200 ) N ;
-    - user_irq[0] + NET user_irq[0] + DIRECTION OUTPUT + USE SIGNAL
+    - user_irq[0] + NET zero_ + DIRECTION OUTPUT + USE SIGNAL
       + PORT
         + LAYER met2 ( -280 -3600 ) ( 280 3600 )
         + PLACED ( 2905130 -1200 ) N ;
-    - user_irq[1] + NET user_irq[1] + DIRECTION OUTPUT + USE SIGNAL
+    - user_irq[1] + NET zero_ + DIRECTION OUTPUT + USE SIGNAL
       + PORT
         + LAYER met2 ( -280 -3600 ) ( 280 3600 )
         + PLACED ( 2911110 -1200 ) N ;
-    - user_irq[2] + NET user_irq[2] + DIRECTION OUTPUT + USE SIGNAL
+    - user_irq[2] + NET zero_ + DIRECTION OUTPUT + USE SIGNAL
       + PORT
         + LAYER met2 ( -280 -3600 ) ( 280 3600 )
         + PLACED ( 2917090 -1200 ) N ;
     - vccd1 + NET vccd1 + SPECIAL + DIRECTION INPUT + USE POWER
       + PORT
-        + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
-        + LAYER met4 ( -181550 -1769310 ) ( -178450 1769310 )
-        + LAYER met4 ( -361550 -1769310 ) ( -358450 1769310 )
-        + LAYER met4 ( -541550 -1769310 ) ( -538450 1769310 )
-        + LAYER met4 ( -721550 -1769310 ) ( -718450 1769310 )
-        + LAYER met4 ( -901550 530160 ) ( -898450 1769310 )
-        + LAYER met4 ( -1081550 530160 ) ( -1078450 1769310 )
-        + LAYER met4 ( -1261550 530160 ) ( -1258450 1769310 )
-        + LAYER met4 ( -1441550 530160 ) ( -1438450 1769310 )
-        + LAYER met4 ( -1621550 530160 ) ( -1618450 1769310 )
-        + LAYER met4 ( -1801550 -1769310 ) ( -1798450 1769310 )
-        + LAYER met4 ( -1981550 -1769310 ) ( -1978450 1769310 )
-        + LAYER met4 ( -2161550 -1769310 ) ( -2158450 1769310 )
-        + LAYER met4 ( -2341550 -1769310 ) ( -2338450 1769310 )
-        + LAYER met4 ( -2521550 -1769310 ) ( -2518450 1769310 )
-        + LAYER met4 ( -2701550 -1769310 ) ( -2698450 1769310 )
-        + LAYER met4 ( -2881550 -1769310 ) ( -2878450 1769310 )
-        + LAYER met4 ( 36030 -1764510 ) ( 39130 1764510 )
-        + LAYER met4 ( -2900550 -1764510 ) ( -2897450 1764510 )
-        + LAYER met4 ( -901550 -1769310 ) ( -898450 -69840 )
-        + LAYER met4 ( -1081550 -1769310 ) ( -1078450 -69840 )
-        + LAYER met4 ( -1261550 -1769310 ) ( -1258450 -69840 )
-        + LAYER met4 ( -1441550 -1769310 ) ( -1438450 -69840 )
-        + LAYER met4 ( -1621550 -1769310 ) ( -1618450 -69840 )
-        + LAYER met5 ( -2900550 1761410 ) ( 39130 1764510 )
-        + LAYER met5 ( -2905350 1674490 ) ( 43930 1677590 )
-        + LAYER met5 ( -2905350 1494490 ) ( 43930 1497590 )
-        + LAYER met5 ( -2905350 1314490 ) ( 43930 1317590 )
-        + LAYER met5 ( -2905350 1134490 ) ( 43930 1137590 )
-        + LAYER met5 ( -2905350 954490 ) ( 43930 957590 )
-        + LAYER met5 ( -2905350 774490 ) ( 43930 777590 )
-        + LAYER met5 ( -2905350 594490 ) ( 43930 597590 )
-        + LAYER met5 ( -2905350 414490 ) ( 43930 417590 )
-        + LAYER met5 ( -2905350 234490 ) ( 43930 237590 )
-        + LAYER met5 ( -2905350 54490 ) ( 43930 57590 )
-        + LAYER met5 ( -2905350 -125510 ) ( 43930 -122410 )
-        + LAYER met5 ( -2905350 -305510 ) ( 43930 -302410 )
-        + LAYER met5 ( -2905350 -485510 ) ( 43930 -482410 )
-        + LAYER met5 ( -2905350 -665510 ) ( 43930 -662410 )
-        + LAYER met5 ( -2905350 -845510 ) ( 43930 -842410 )
-        + LAYER met5 ( -2905350 -1025510 ) ( 43930 -1022410 )
-        + LAYER met5 ( -2905350 -1205510 ) ( 43930 -1202410 )
-        + LAYER met5 ( -2905350 -1385510 ) ( 43930 -1382410 )
-        + LAYER met5 ( -2905350 -1565510 ) ( 43930 -1562410 )
-        + LAYER met5 ( -2905350 -1745510 ) ( 43930 -1742410 )
-        + LAYER met5 ( -2900550 -1764510 ) ( 39130 -1761410 )
-        + FIXED ( 2890520 1759840 ) N ;
+        + LAYER met4 ( -1550 -62605 ) ( 1550 62605 )
+        + LAYER met4 ( -181550 -62605 ) ( -178450 62605 )
+        + LAYER met4 ( -361550 -62605 ) ( -358450 62605 )
+        + LAYER met4 ( -541550 -62605 ) ( -538450 62605 )
+        + LAYER met4 ( -721550 -62605 ) ( -718450 62605 )
+        + LAYER met4 ( -901550 -62605 ) ( -898450 62605 )
+        + LAYER met4 ( -1081550 -62605 ) ( -1078450 62605 )
+        + LAYER met4 ( -1261550 -62605 ) ( -1258450 62605 )
+        + LAYER met4 ( -1441550 -62605 ) ( -1438450 62605 )
+        + LAYER met4 ( -1621550 -62605 ) ( -1618450 62605 )
+        + LAYER met4 ( -1801550 -62605 ) ( -1798450 62605 )
+        + LAYER met4 ( -1981550 -62605 ) ( -1978450 62605 )
+        + LAYER met4 ( -2161550 -62605 ) ( -2158450 62605 )
+        + LAYER met4 ( -2341550 -62605 ) ( -2338450 62605 )
+        + LAYER met4 ( -2521550 -62605 ) ( -2518450 62605 )
+        + LAYER met4 ( -2701550 -62605 ) ( -2698450 62605 )
+        + LAYER met4 ( -2881550 -62605 ) ( -2878450 62605 )
+        + LAYER met4 ( 36030 -3471215 ) ( 39130 57805 )
+        + LAYER met4 ( -2900550 -3471215 ) ( -2897450 57805 )
+        + LAYER met4 ( -1550 -3476015 ) ( 1550 -3326545 )
+        + LAYER met4 ( -181550 -3476015 ) ( -178450 -3326545 )
+        + LAYER met4 ( -361550 -3476015 ) ( -358450 -3326545 )
+        + LAYER met4 ( -541550 -3476015 ) ( -538450 -3326545 )
+        + LAYER met4 ( -721550 -3476015 ) ( -718450 -3326545 )
+        + LAYER met4 ( -901550 -3476015 ) ( -898450 -3326545 )
+        + LAYER met4 ( -1081550 -3476015 ) ( -1078450 -3326545 )
+        + LAYER met4 ( -1261550 -3476015 ) ( -1258450 -3326545 )
+        + LAYER met4 ( -1441550 -3476015 ) ( -1438450 -3326545 )
+        + LAYER met4 ( -1621550 -3476015 ) ( -1618450 -3326545 )
+        + LAYER met4 ( -1801550 -3476015 ) ( -1798450 -3326545 )
+        + LAYER met4 ( -1981550 -3476015 ) ( -1978450 -3326545 )
+        + LAYER met4 ( -2161550 -3476015 ) ( -2158450 -3326545 )
+        + LAYER met4 ( -2341550 -3476015 ) ( -2338450 -3326545 )
+        + LAYER met4 ( -2521550 -3476015 ) ( -2518450 -3326545 )
+        + LAYER met4 ( -2701550 -3476015 ) ( -2698450 -3326545 )
+        + LAYER met4 ( -2881550 -3476015 ) ( -2878450 -3326545 )
+        + LAYER met5 ( -2900550 54705 ) ( 39130 57805 )
+        + LAYER met5 ( -2905350 -32215 ) ( 43930 -29115 )
+        + LAYER met5 ( -2905350 -212215 ) ( 43930 -209115 )
+        + LAYER met5 ( -2905350 -392215 ) ( 43930 -389115 )
+        + LAYER met5 ( -2905350 -572215 ) ( 43930 -569115 )
+        + LAYER met5 ( -2905350 -752215 ) ( 43930 -749115 )
+        + LAYER met5 ( -2905350 -932215 ) ( 43930 -929115 )
+        + LAYER met5 ( -2905350 -1112215 ) ( 43930 -1109115 )
+        + LAYER met5 ( -2905350 -1292215 ) ( 43930 -1289115 )
+        + LAYER met5 ( -2905350 -1472215 ) ( 43930 -1469115 )
+        + LAYER met5 ( -2905350 -1652215 ) ( 43930 -1649115 )
+        + LAYER met5 ( -2905350 -1832215 ) ( 43930 -1829115 )
+        + LAYER met5 ( -2905350 -2012215 ) ( 43930 -2009115 )
+        + LAYER met5 ( -2905350 -2192215 ) ( 43930 -2189115 )
+        + LAYER met5 ( -2905350 -2372215 ) ( 43930 -2369115 )
+        + LAYER met5 ( -2905350 -2552215 ) ( 43930 -2549115 )
+        + LAYER met5 ( -2905350 -2732215 ) ( 43930 -2729115 )
+        + LAYER met5 ( -2905350 -2912215 ) ( 43930 -2909115 )
+        + LAYER met5 ( -2905350 -3092215 ) ( 43930 -3089115 )
+        + LAYER met5 ( -2905350 -3272215 ) ( 43930 -3269115 )
+        + LAYER met5 ( -2905350 -3452215 ) ( 43930 -3449115 )
+        + LAYER met5 ( -2900550 -3471215 ) ( 39130 -3468115 )
+        + FIXED ( 2890520 3466545 ) N ;
     - vccd2 + NET vccd2 + SPECIAL + DIRECTION INPUT + USE POWER
       + PORT
-        + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
-        + LAYER met4 ( -181550 -1778910 ) ( -178450 1778910 )
-        + LAYER met4 ( -361550 -1778910 ) ( -358450 1778910 )
-        + LAYER met4 ( -541550 -1778910 ) ( -538450 1778910 )
-        + LAYER met4 ( -721550 -1778910 ) ( -718450 1778910 )
-        + LAYER met4 ( -901550 540160 ) ( -898450 1778910 )
-        + LAYER met4 ( -1081550 540160 ) ( -1078450 1778910 )
-        + LAYER met4 ( -1261550 540160 ) ( -1258450 1778910 )
-        + LAYER met4 ( -1441550 540160 ) ( -1438450 1778910 )
-        + LAYER met4 ( -1621550 540160 ) ( -1618450 1778910 )
-        + LAYER met4 ( -1801550 -1778910 ) ( -1798450 1778910 )
-        + LAYER met4 ( -1981550 -1778910 ) ( -1978450 1778910 )
-        + LAYER met4 ( -2161550 -1778910 ) ( -2158450 1778910 )
-        + LAYER met4 ( -2341550 -1778910 ) ( -2338450 1778910 )
-        + LAYER met4 ( -2521550 -1778910 ) ( -2518450 1778910 )
-        + LAYER met4 ( -2701550 -1778910 ) ( -2698450 1778910 )
-        + LAYER met4 ( -2881550 -1778910 ) ( -2878450 1778910 )
-        + LAYER met4 ( 27030 -1774110 ) ( 30130 1774110 )
-        + LAYER met4 ( -2928750 -1774110 ) ( -2925650 1774110 )
-        + LAYER met4 ( -901550 -1778910 ) ( -898450 -79840 )
-        + LAYER met4 ( -1081550 -1778910 ) ( -1078450 -79840 )
-        + LAYER met4 ( -1261550 -1778910 ) ( -1258450 -79840 )
-        + LAYER met4 ( -1441550 -1778910 ) ( -1438450 -79840 )
-        + LAYER met4 ( -1621550 -1778910 ) ( -1618450 -79840 )
-        + LAYER met5 ( -2928750 1771010 ) ( 30130 1774110 )
-        + LAYER met5 ( -2933550 1693090 ) ( 34930 1696190 )
-        + LAYER met5 ( -2933550 1513090 ) ( 34930 1516190 )
-        + LAYER met5 ( -2933550 1333090 ) ( 34930 1336190 )
-        + LAYER met5 ( -2933550 1153090 ) ( 34930 1156190 )
-        + LAYER met5 ( -2933550 973090 ) ( 34930 976190 )
-        + LAYER met5 ( -2933550 793090 ) ( 34930 796190 )
-        + LAYER met5 ( -2933550 613090 ) ( 34930 616190 )
-        + LAYER met5 ( -2933550 433090 ) ( 34930 436190 )
-        + LAYER met5 ( -2933550 253090 ) ( 34930 256190 )
-        + LAYER met5 ( -2933550 73090 ) ( 34930 76190 )
-        + LAYER met5 ( -2933550 -106910 ) ( 34930 -103810 )
-        + LAYER met5 ( -2933550 -286910 ) ( 34930 -283810 )
-        + LAYER met5 ( -2933550 -466910 ) ( 34930 -463810 )
-        + LAYER met5 ( -2933550 -646910 ) ( 34930 -643810 )
-        + LAYER met5 ( -2933550 -826910 ) ( 34930 -823810 )
-        + LAYER met5 ( -2933550 -1006910 ) ( 34930 -1003810 )
-        + LAYER met5 ( -2933550 -1186910 ) ( 34930 -1183810 )
-        + LAYER met5 ( -2933550 -1366910 ) ( 34930 -1363810 )
-        + LAYER met5 ( -2933550 -1546910 ) ( 34930 -1543810 )
-        + LAYER met5 ( -2933550 -1726910 ) ( 34930 -1723810 )
-        + LAYER met5 ( -2928750 -1774110 ) ( 30130 -1771010 )
-        + FIXED ( 2909120 1759840 ) N ;
+        + LAYER met4 ( -1550 -67405 ) ( 1550 67405 )
+        + LAYER met4 ( -181550 -67405 ) ( -178450 67405 )
+        + LAYER met4 ( -361550 -67405 ) ( -358450 67405 )
+        + LAYER met4 ( -541550 -67405 ) ( -538450 67405 )
+        + LAYER met4 ( -721550 -67405 ) ( -718450 67405 )
+        + LAYER met4 ( -901550 -67405 ) ( -898450 67405 )
+        + LAYER met4 ( -1081550 -67405 ) ( -1078450 67405 )
+        + LAYER met4 ( -1261550 -67405 ) ( -1258450 67405 )
+        + LAYER met4 ( -1441550 -67405 ) ( -1438450 67405 )
+        + LAYER met4 ( -1621550 -67405 ) ( -1618450 67405 )
+        + LAYER met4 ( -1801550 -67405 ) ( -1798450 67405 )
+        + LAYER met4 ( -1981550 -67405 ) ( -1978450 67405 )
+        + LAYER met4 ( -2161550 -67405 ) ( -2158450 67405 )
+        + LAYER met4 ( -2341550 -67405 ) ( -2338450 67405 )
+        + LAYER met4 ( -2521550 -67405 ) ( -2518450 67405 )
+        + LAYER met4 ( -2701550 -67405 ) ( -2698450 67405 )
+        + LAYER met4 ( -2881550 -67405 ) ( -2878450 67405 )
+        + LAYER met4 ( 27030 -3485615 ) ( 30130 62605 )
+        + LAYER met4 ( -2928750 -3485615 ) ( -2925650 62605 )
+        + LAYER met4 ( -1550 -3490415 ) ( 1550 -3331345 )
+        + LAYER met4 ( -181550 -3490415 ) ( -178450 -3331345 )
+        + LAYER met4 ( -361550 -3490415 ) ( -358450 -3331345 )
+        + LAYER met4 ( -541550 -3490415 ) ( -538450 -3331345 )
+        + LAYER met4 ( -721550 -3490415 ) ( -718450 -3331345 )
+        + LAYER met4 ( -901550 -3490415 ) ( -898450 -3331345 )
+        + LAYER met4 ( -1081550 -3490415 ) ( -1078450 -3331345 )
+        + LAYER met4 ( -1261550 -3490415 ) ( -1258450 -3331345 )
+        + LAYER met4 ( -1441550 -3490415 ) ( -1438450 -3331345 )
+        + LAYER met4 ( -1621550 -3490415 ) ( -1618450 -3331345 )
+        + LAYER met4 ( -1801550 -3490415 ) ( -1798450 -3331345 )
+        + LAYER met4 ( -1981550 -3490415 ) ( -1978450 -3331345 )
+        + LAYER met4 ( -2161550 -3490415 ) ( -2158450 -3331345 )
+        + LAYER met4 ( -2341550 -3490415 ) ( -2338450 -3331345 )
+        + LAYER met4 ( -2521550 -3490415 ) ( -2518450 -3331345 )
+        + LAYER met4 ( -2701550 -3490415 ) ( -2698450 -3331345 )
+        + LAYER met4 ( -2881550 -3490415 ) ( -2878450 -3331345 )
+        + LAYER met5 ( -2928750 59505 ) ( 30130 62605 )
+        + LAYER met5 ( -2933550 -18415 ) ( 34930 -15315 )
+        + LAYER met5 ( -2933550 -198415 ) ( 34930 -195315 )
+        + LAYER met5 ( -2933550 -378415 ) ( 34930 -375315 )
+        + LAYER met5 ( -2933550 -558415 ) ( 34930 -555315 )
+        + LAYER met5 ( -2933550 -738415 ) ( 34930 -735315 )
+        + LAYER met5 ( -2933550 -918415 ) ( 34930 -915315 )
+        + LAYER met5 ( -2933550 -1098415 ) ( 34930 -1095315 )
+        + LAYER met5 ( -2933550 -1278415 ) ( 34930 -1275315 )
+        + LAYER met5 ( -2933550 -1458415 ) ( 34930 -1455315 )
+        + LAYER met5 ( -2933550 -1638415 ) ( 34930 -1635315 )
+        + LAYER met5 ( -2933550 -1818415 ) ( 34930 -1815315 )
+        + LAYER met5 ( -2933550 -1998415 ) ( 34930 -1995315 )
+        + LAYER met5 ( -2933550 -2178415 ) ( 34930 -2175315 )
+        + LAYER met5 ( -2933550 -2358415 ) ( 34930 -2355315 )
+        + LAYER met5 ( -2933550 -2538415 ) ( 34930 -2535315 )
+        + LAYER met5 ( -2933550 -2718415 ) ( 34930 -2715315 )
+        + LAYER met5 ( -2933550 -2898415 ) ( 34930 -2895315 )
+        + LAYER met5 ( -2933550 -3078415 ) ( 34930 -3075315 )
+        + LAYER met5 ( -2933550 -3258415 ) ( 34930 -3255315 )
+        + LAYER met5 ( -2933550 -3438415 ) ( 34930 -3435315 )
+        + LAYER met5 ( -2928750 -3485615 ) ( 30130 -3482515 )
+        + FIXED ( 2909120 3471345 ) N ;
     - vdda1 + NET vdda1 + SPECIAL + DIRECTION INPUT + USE POWER
       + PORT
-        + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
-        + LAYER met4 ( -181550 -1788510 ) ( -178450 1788510 )
-        + LAYER met4 ( -361550 -1788510 ) ( -358450 1788510 )
-        + LAYER met4 ( -541550 -1788510 ) ( -538450 1788510 )
-        + LAYER met4 ( -721550 540160 ) ( -718450 1788510 )
-        + LAYER met4 ( -901550 540160 ) ( -898450 1788510 )
-        + LAYER met4 ( -1081550 540160 ) ( -1078450 1788510 )
-        + LAYER met4 ( -1261550 540160 ) ( -1258450 1788510 )
-        + LAYER met4 ( -1441550 540160 ) ( -1438450 1788510 )
-        + LAYER met4 ( -1621550 -1788510 ) ( -1618450 1788510 )
-        + LAYER met4 ( -1801550 -1788510 ) ( -1798450 1788510 )
-        + LAYER met4 ( -1981550 -1788510 ) ( -1978450 1788510 )
-        + LAYER met4 ( -2161550 -1788510 ) ( -2158450 1788510 )
-        + LAYER met4 ( -2341550 -1788510 ) ( -2338450 1788510 )
-        + LAYER met4 ( -2521550 -1788510 ) ( -2518450 1788510 )
-        + LAYER met4 ( -2701550 -1788510 ) ( -2698450 1788510 )
-        + LAYER met4 ( 198030 -1783710 ) ( 201130 1783710 )
-        + LAYER met4 ( -2776950 -1783710 ) ( -2773850 1783710 )
-        + LAYER met4 ( -721550 -1788510 ) ( -718450 -79840 )
-        + LAYER met4 ( -901550 -1788510 ) ( -898450 -79840 )
-        + LAYER met4 ( -1081550 -1788510 ) ( -1078450 -79840 )
-        + LAYER met4 ( -1261550 -1788510 ) ( -1258450 -79840 )
-        + LAYER met4 ( -1441550 -1788510 ) ( -1438450 -79840 )
-        + LAYER met5 ( -2776950 1780610 ) ( 201130 1783710 )
-        + LAYER met5 ( -2781750 1711690 ) ( 205930 1714790 )
-        + LAYER met5 ( -2781750 1531690 ) ( 205930 1534790 )
-        + LAYER met5 ( -2781750 1351690 ) ( 205930 1354790 )
-        + LAYER met5 ( -2781750 1171690 ) ( 205930 1174790 )
-        + LAYER met5 ( -2781750 991690 ) ( 205930 994790 )
-        + LAYER met5 ( -2781750 811690 ) ( 205930 814790 )
-        + LAYER met5 ( -2781750 631690 ) ( 205930 634790 )
-        + LAYER met5 ( -2781750 451690 ) ( 205930 454790 )
-        + LAYER met5 ( -2781750 271690 ) ( 205930 274790 )
-        + LAYER met5 ( -2781750 91690 ) ( 205930 94790 )
-        + LAYER met5 ( -2781750 -88310 ) ( 205930 -85210 )
-        + LAYER met5 ( -2781750 -268310 ) ( 205930 -265210 )
-        + LAYER met5 ( -2781750 -448310 ) ( 205930 -445210 )
-        + LAYER met5 ( -2781750 -628310 ) ( 205930 -625210 )
-        + LAYER met5 ( -2781750 -808310 ) ( 205930 -805210 )
-        + LAYER met5 ( -2781750 -988310 ) ( 205930 -985210 )
-        + LAYER met5 ( -2781750 -1168310 ) ( 205930 -1165210 )
-        + LAYER met5 ( -2781750 -1348310 ) ( 205930 -1345210 )
-        + LAYER met5 ( -2781750 -1528310 ) ( 205930 -1525210 )
-        + LAYER met5 ( -2781750 -1708310 ) ( 205930 -1705210 )
-        + LAYER met5 ( -2776950 -1783710 ) ( 201130 -1780610 )
-        + FIXED ( 2747720 1759840 ) N ;
+        + LAYER met4 ( -1550 -72205 ) ( 1550 72205 )
+        + LAYER met4 ( -181550 -72205 ) ( -178450 72205 )
+        + LAYER met4 ( -361550 -72205 ) ( -358450 72205 )
+        + LAYER met4 ( -541550 -72205 ) ( -538450 72205 )
+        + LAYER met4 ( -721550 -72205 ) ( -718450 72205 )
+        + LAYER met4 ( -901550 -72205 ) ( -898450 72205 )
+        + LAYER met4 ( -1081550 -72205 ) ( -1078450 72205 )
+        + LAYER met4 ( -1261550 -72205 ) ( -1258450 72205 )
+        + LAYER met4 ( -1441550 -72205 ) ( -1438450 72205 )
+        + LAYER met4 ( -1621550 -72205 ) ( -1618450 72205 )
+        + LAYER met4 ( -1801550 -72205 ) ( -1798450 72205 )
+        + LAYER met4 ( -1981550 -72205 ) ( -1978450 72205 )
+        + LAYER met4 ( -2161550 -72205 ) ( -2158450 72205 )
+        + LAYER met4 ( -2341550 -72205 ) ( -2338450 72205 )
+        + LAYER met4 ( -2521550 -72205 ) ( -2518450 72205 )
+        + LAYER met4 ( -2701550 -72205 ) ( -2698450 72205 )
+        + LAYER met4 ( 198030 -3500015 ) ( 201130 67405 )
+        + LAYER met4 ( -2776950 -3500015 ) ( -2773850 67405 )
+        + LAYER met4 ( -1550 -3504815 ) ( 1550 -3336145 )
+        + LAYER met4 ( -181550 -3504815 ) ( -178450 -3336145 )
+        + LAYER met4 ( -361550 -3504815 ) ( -358450 -3336145 )
+        + LAYER met4 ( -541550 -3504815 ) ( -538450 -3336145 )
+        + LAYER met4 ( -721550 -3504815 ) ( -718450 -3336145 )
+        + LAYER met4 ( -901550 -3504815 ) ( -898450 -3336145 )
+        + LAYER met4 ( -1081550 -3504815 ) ( -1078450 -3336145 )
+        + LAYER met4 ( -1261550 -3504815 ) ( -1258450 -3336145 )
+        + LAYER met4 ( -1441550 -3504815 ) ( -1438450 -3336145 )
+        + LAYER met4 ( -1621550 -3504815 ) ( -1618450 -3336145 )
+        + LAYER met4 ( -1801550 -3504815 ) ( -1798450 -3336145 )
+        + LAYER met4 ( -1981550 -3504815 ) ( -1978450 -3336145 )
+        + LAYER met4 ( -2161550 -3504815 ) ( -2158450 -3336145 )
+        + LAYER met4 ( -2341550 -3504815 ) ( -2338450 -3336145 )
+        + LAYER met4 ( -2521550 -3504815 ) ( -2518450 -3336145 )
+        + LAYER met4 ( -2701550 -3504815 ) ( -2698450 -3336145 )
+        + LAYER met5 ( -2776950 64305 ) ( 201130 67405 )
+        + LAYER met5 ( -2781750 -4615 ) ( 205930 -1515 )
+        + LAYER met5 ( -2781750 -184615 ) ( 205930 -181515 )
+        + LAYER met5 ( -2781750 -364615 ) ( 205930 -361515 )
+        + LAYER met5 ( -2781750 -544615 ) ( 205930 -541515 )
+        + LAYER met5 ( -2781750 -724615 ) ( 205930 -721515 )
+        + LAYER met5 ( -2781750 -904615 ) ( 205930 -901515 )
+        + LAYER met5 ( -2781750 -1084615 ) ( 205930 -1081515 )
+        + LAYER met5 ( -2781750 -1264615 ) ( 205930 -1261515 )
+        + LAYER met5 ( -2781750 -1444615 ) ( 205930 -1441515 )
+        + LAYER met5 ( -2781750 -1624615 ) ( 205930 -1621515 )
+        + LAYER met5 ( -2781750 -1804615 ) ( 205930 -1801515 )
+        + LAYER met5 ( -2781750 -1984615 ) ( 205930 -1981515 )
+        + LAYER met5 ( -2781750 -2164615 ) ( 205930 -2161515 )
+        + LAYER met5 ( -2781750 -2344615 ) ( 205930 -2341515 )
+        + LAYER met5 ( -2781750 -2524615 ) ( 205930 -2521515 )
+        + LAYER met5 ( -2781750 -2704615 ) ( 205930 -2701515 )
+        + LAYER met5 ( -2781750 -2884615 ) ( 205930 -2881515 )
+        + LAYER met5 ( -2781750 -3064615 ) ( 205930 -3061515 )
+        + LAYER met5 ( -2781750 -3244615 ) ( 205930 -3241515 )
+        + LAYER met5 ( -2781750 -3424615 ) ( 205930 -3421515 )
+        + LAYER met5 ( -2776950 -3500015 ) ( 201130 -3496915 )
+        + FIXED ( 2747720 3476145 ) N ;
     - vdda2 + NET vdda2 + SPECIAL + DIRECTION INPUT + USE POWER
       + PORT
-        + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
-        + LAYER met4 ( -181550 -1798110 ) ( -178450 1798110 )
-        + LAYER met4 ( -361550 -1798110 ) ( -358450 1798110 )
-        + LAYER met4 ( -541550 -1798110 ) ( -538450 1798110 )
-        + LAYER met4 ( -721550 540160 ) ( -718450 1798110 )
-        + LAYER met4 ( -901550 540160 ) ( -898450 1798110 )
-        + LAYER met4 ( -1081550 540160 ) ( -1078450 1798110 )
-        + LAYER met4 ( -1261550 540160 ) ( -1258450 1798110 )
-        + LAYER met4 ( -1441550 540160 ) ( -1438450 1798110 )
-        + LAYER met4 ( -1621550 -1798110 ) ( -1618450 1798110 )
-        + LAYER met4 ( -1801550 -1798110 ) ( -1798450 1798110 )
-        + LAYER met4 ( -1981550 -1798110 ) ( -1978450 1798110 )
-        + LAYER met4 ( -2161550 -1798110 ) ( -2158450 1798110 )
-        + LAYER met4 ( -2341550 -1798110 ) ( -2338450 1798110 )
-        + LAYER met4 ( -2521550 -1798110 ) ( -2518450 1798110 )
-        + LAYER met4 ( -2701550 -1798110 ) ( -2698450 1798110 )
-        + LAYER met4 ( 189030 -1793310 ) ( 192130 1793310 )
-        + LAYER met4 ( -2805150 -1793310 ) ( -2802050 1793310 )
-        + LAYER met4 ( -721550 -1798110 ) ( -718450 -79840 )
-        + LAYER met4 ( -901550 -1798110 ) ( -898450 -79840 )
-        + LAYER met4 ( -1081550 -1798110 ) ( -1078450 -79840 )
-        + LAYER met4 ( -1261550 -1798110 ) ( -1258450 -79840 )
-        + LAYER met4 ( -1441550 -1798110 ) ( -1438450 -79840 )
-        + LAYER met5 ( -2805150 1790210 ) ( 192130 1793310 )
-        + LAYER met5 ( -2809950 1730290 ) ( 196930 1733390 )
-        + LAYER met5 ( -2809950 1550290 ) ( 196930 1553390 )
-        + LAYER met5 ( -2809950 1370290 ) ( 196930 1373390 )
-        + LAYER met5 ( -2809950 1190290 ) ( 196930 1193390 )
-        + LAYER met5 ( -2809950 1010290 ) ( 196930 1013390 )
-        + LAYER met5 ( -2809950 830290 ) ( 196930 833390 )
-        + LAYER met5 ( -2809950 650290 ) ( 196930 653390 )
-        + LAYER met5 ( -2809950 470290 ) ( 196930 473390 )
-        + LAYER met5 ( -2809950 290290 ) ( 196930 293390 )
-        + LAYER met5 ( -2809950 110290 ) ( 196930 113390 )
-        + LAYER met5 ( -2809950 -69710 ) ( 196930 -66610 )
-        + LAYER met5 ( -2809950 -249710 ) ( 196930 -246610 )
-        + LAYER met5 ( -2809950 -429710 ) ( 196930 -426610 )
-        + LAYER met5 ( -2809950 -609710 ) ( 196930 -606610 )
-        + LAYER met5 ( -2809950 -789710 ) ( 196930 -786610 )
-        + LAYER met5 ( -2809950 -969710 ) ( 196930 -966610 )
-        + LAYER met5 ( -2809950 -1149710 ) ( 196930 -1146610 )
-        + LAYER met5 ( -2809950 -1329710 ) ( 196930 -1326610 )
-        + LAYER met5 ( -2809950 -1509710 ) ( 196930 -1506610 )
-        + LAYER met5 ( -2809950 -1689710 ) ( 196930 -1686610 )
-        + LAYER met5 ( -2805150 -1793310 ) ( 192130 -1790210 )
-        + FIXED ( 2766320 1759840 ) N ;
+        + LAYER met4 ( -1550 -77005 ) ( 1550 77005 )
+        + LAYER met4 ( -181550 -77005 ) ( -178450 77005 )
+        + LAYER met4 ( -361550 -77005 ) ( -358450 77005 )
+        + LAYER met4 ( -541550 -77005 ) ( -538450 77005 )
+        + LAYER met4 ( -721550 -77005 ) ( -718450 77005 )
+        + LAYER met4 ( -901550 -77005 ) ( -898450 77005 )
+        + LAYER met4 ( -1081550 -77005 ) ( -1078450 77005 )
+        + LAYER met4 ( -1261550 -77005 ) ( -1258450 77005 )
+        + LAYER met4 ( -1441550 -77005 ) ( -1438450 77005 )
+        + LAYER met4 ( -1621550 -77005 ) ( -1618450 77005 )
+        + LAYER met4 ( -1801550 -77005 ) ( -1798450 77005 )
+        + LAYER met4 ( -1981550 -77005 ) ( -1978450 77005 )
+        + LAYER met4 ( -2161550 -77005 ) ( -2158450 77005 )
+        + LAYER met4 ( -2341550 -77005 ) ( -2338450 77005 )
+        + LAYER met4 ( -2521550 -77005 ) ( -2518450 77005 )
+        + LAYER met4 ( -2701550 -77005 ) ( -2698450 77005 )
+        + LAYER met4 ( 189030 -3514415 ) ( 192130 72205 )
+        + LAYER met4 ( -2805150 -3514415 ) ( -2802050 72205 )
+        + LAYER met4 ( -1550 -3519215 ) ( 1550 -3340945 )
+        + LAYER met4 ( -181550 -3519215 ) ( -178450 -3340945 )
+        + LAYER met4 ( -361550 -3519215 ) ( -358450 -3340945 )
+        + LAYER met4 ( -541550 -3519215 ) ( -538450 -3340945 )
+        + LAYER met4 ( -721550 -3519215 ) ( -718450 -3340945 )
+        + LAYER met4 ( -901550 -3519215 ) ( -898450 -3340945 )
+        + LAYER met4 ( -1081550 -3519215 ) ( -1078450 -3340945 )
+        + LAYER met4 ( -1261550 -3519215 ) ( -1258450 -3340945 )
+        + LAYER met4 ( -1441550 -3519215 ) ( -1438450 -3340945 )
+        + LAYER met4 ( -1621550 -3519215 ) ( -1618450 -3340945 )
+        + LAYER met4 ( -1801550 -3519215 ) ( -1798450 -3340945 )
+        + LAYER met4 ( -1981550 -3519215 ) ( -1978450 -3340945 )
+        + LAYER met4 ( -2161550 -3519215 ) ( -2158450 -3340945 )
+        + LAYER met4 ( -2341550 -3519215 ) ( -2338450 -3340945 )
+        + LAYER met4 ( -2521550 -3519215 ) ( -2518450 -3340945 )
+        + LAYER met4 ( -2701550 -3519215 ) ( -2698450 -3340945 )
+        + LAYER met5 ( -2805150 69105 ) ( 192130 72205 )
+        + LAYER met5 ( -2809950 9185 ) ( 196930 12285 )
+        + LAYER met5 ( -2809950 -170815 ) ( 196930 -167715 )
+        + LAYER met5 ( -2809950 -350815 ) ( 196930 -347715 )
+        + LAYER met5 ( -2809950 -530815 ) ( 196930 -527715 )
+        + LAYER met5 ( -2809950 -710815 ) ( 196930 -707715 )
+        + LAYER met5 ( -2809950 -890815 ) ( 196930 -887715 )
+        + LAYER met5 ( -2809950 -1070815 ) ( 196930 -1067715 )
+        + LAYER met5 ( -2809950 -1250815 ) ( 196930 -1247715 )
+        + LAYER met5 ( -2809950 -1430815 ) ( 196930 -1427715 )
+        + LAYER met5 ( -2809950 -1610815 ) ( 196930 -1607715 )
+        + LAYER met5 ( -2809950 -1790815 ) ( 196930 -1787715 )
+        + LAYER met5 ( -2809950 -1970815 ) ( 196930 -1967715 )
+        + LAYER met5 ( -2809950 -2150815 ) ( 196930 -2147715 )
+        + LAYER met5 ( -2809950 -2330815 ) ( 196930 -2327715 )
+        + LAYER met5 ( -2809950 -2510815 ) ( 196930 -2507715 )
+        + LAYER met5 ( -2809950 -2690815 ) ( 196930 -2687715 )
+        + LAYER met5 ( -2809950 -2870815 ) ( 196930 -2867715 )
+        + LAYER met5 ( -2809950 -3050815 ) ( 196930 -3047715 )
+        + LAYER met5 ( -2809950 -3230815 ) ( 196930 -3227715 )
+        + LAYER met5 ( -2809950 -3410815 ) ( 196930 -3407715 )
+        + LAYER met5 ( -2805150 -3514415 ) ( 192130 -3511315 )
+        + FIXED ( 2766320 3480945 ) N ;
     - vssa1 + NET vssa1 + SPECIAL + DIRECTION INPUT + USE GROUND
       + PORT
         + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
-        + LAYER met4 ( -115930 -1788510 ) ( -112830 1788510 )
-        + LAYER met4 ( -295930 -1788510 ) ( -292830 1788510 )
-        + LAYER met4 ( -475930 -1788510 ) ( -472830 1788510 )
-        + LAYER met4 ( -655930 -1788510 ) ( -652830 1788510 )
-        + LAYER met4 ( -835930 -1788510 ) ( -832830 1788510 )
-        + LAYER met4 ( -1015930 540160 ) ( -1012830 1788510 )
-        + LAYER met4 ( -1195930 540160 ) ( -1192830 1788510 )
-        + LAYER met4 ( -1375930 540160 ) ( -1372830 1788510 )
-        + LAYER met4 ( -1555930 540160 ) ( -1552830 1788510 )
-        + LAYER met4 ( -1735930 540160 ) ( -1732830 1788510 )
-        + LAYER met4 ( -1915930 -1788510 ) ( -1912830 1788510 )
-        + LAYER met4 ( -2095930 -1788510 ) ( -2092830 1788510 )
-        + LAYER met4 ( -2275930 -1788510 ) ( -2272830 1788510 )
-        + LAYER met4 ( -2455930 -1788510 ) ( -2452830 1788510 )
-        + LAYER met4 ( -2635930 -1788510 ) ( -2632830 1788510 )
-        + LAYER met4 ( -2815930 -1788510 ) ( -2812830 1788510 )
+        + LAYER met4 ( -115930 1644100 ) ( -112830 1788510 )
+        + LAYER met4 ( -295930 1644100 ) ( -292830 1788510 )
+        + LAYER met4 ( -475930 1644100 ) ( -472830 1788510 )
+        + LAYER met4 ( -655930 1644100 ) ( -652830 1788510 )
+        + LAYER met4 ( -835930 1644100 ) ( -832830 1788510 )
+        + LAYER met4 ( -1015930 1644100 ) ( -1012830 1788510 )
+        + LAYER met4 ( -1195930 1644100 ) ( -1192830 1788510 )
+        + LAYER met4 ( -1375930 1644100 ) ( -1372830 1788510 )
+        + LAYER met4 ( -1555930 1644100 ) ( -1552830 1788510 )
+        + LAYER met4 ( -1735930 1644100 ) ( -1732830 1788510 )
+        + LAYER met4 ( -1915930 1644100 ) ( -1912830 1788510 )
+        + LAYER met4 ( -2095930 1644100 ) ( -2092830 1788510 )
+        + LAYER met4 ( -2275930 1644100 ) ( -2272830 1788510 )
+        + LAYER met4 ( -2455930 1644100 ) ( -2452830 1788510 )
+        + LAYER met4 ( -2635930 1644100 ) ( -2632830 1788510 )
+        + LAYER met4 ( -2815930 1644100 ) ( -2812830 1788510 )
         + LAYER met4 ( -2986130 -1788510 ) ( -2983030 1788510 )
-        + LAYER met4 ( -1015930 -1788510 ) ( -1012830 -79840 )
-        + LAYER met4 ( -1195930 -1788510 ) ( -1192830 -79840 )
-        + LAYER met4 ( -1375930 -1788510 ) ( -1372830 -79840 )
-        + LAYER met4 ( -1555930 -1788510 ) ( -1552830 -79840 )
-        + LAYER met4 ( -1735930 -1788510 ) ( -1732830 -79840 )
+        + LAYER met4 ( -115930 -1788510 ) ( -112830 -1619840 )
+        + LAYER met4 ( -295930 -1788510 ) ( -292830 -1619840 )
+        + LAYER met4 ( -475930 -1788510 ) ( -472830 -1619840 )
+        + LAYER met4 ( -655930 -1788510 ) ( -652830 -1619840 )
+        + LAYER met4 ( -835930 -1788510 ) ( -832830 -1619840 )
+        + LAYER met4 ( -1015930 -1788510 ) ( -1012830 -1619840 )
+        + LAYER met4 ( -1195930 -1788510 ) ( -1192830 -1619840 )
+        + LAYER met4 ( -1375930 -1788510 ) ( -1372830 -1619840 )
+        + LAYER met4 ( -1555930 -1788510 ) ( -1552830 -1619840 )
+        + LAYER met4 ( -1735930 -1788510 ) ( -1732830 -1619840 )
+        + LAYER met4 ( -1915930 -1788510 ) ( -1912830 -1619840 )
+        + LAYER met4 ( -2095930 -1788510 ) ( -2092830 -1619840 )
+        + LAYER met4 ( -2275930 -1788510 ) ( -2272830 -1619840 )
+        + LAYER met4 ( -2455930 -1788510 ) ( -2452830 -1619840 )
+        + LAYER met4 ( -2635930 -1788510 ) ( -2632830 -1619840 )
+        + LAYER met4 ( -2815930 -1788510 ) ( -2812830 -1619840 )
         + LAYER met5 ( -2986130 1785410 ) ( 1550 1788510 )
         + LAYER met5 ( -2986130 1621690 ) ( 1550 1624790 )
         + LAYER met5 ( -2986130 1441690 ) ( 1550 1444790 )
@@ -3680,28 +3739,39 @@
     - vssa2 + NET vssa2 + SPECIAL + DIRECTION INPUT + USE GROUND
       + PORT
         + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
-        + LAYER met4 ( -106930 -1798110 ) ( -103830 1798110 )
-        + LAYER met4 ( -286930 -1798110 ) ( -283830 1798110 )
-        + LAYER met4 ( -466930 -1798110 ) ( -463830 1798110 )
-        + LAYER met4 ( -646930 -1798110 ) ( -643830 1798110 )
-        + LAYER met4 ( -826930 -1798110 ) ( -823830 1798110 )
-        + LAYER met4 ( -1006930 540160 ) ( -1003830 1798110 )
-        + LAYER met4 ( -1186930 540160 ) ( -1183830 1798110 )
-        + LAYER met4 ( -1366930 540160 ) ( -1363830 1798110 )
-        + LAYER met4 ( -1546930 540160 ) ( -1543830 1798110 )
-        + LAYER met4 ( -1726930 540160 ) ( -1723830 1798110 )
-        + LAYER met4 ( -1906930 -1798110 ) ( -1903830 1798110 )
-        + LAYER met4 ( -2086930 -1798110 ) ( -2083830 1798110 )
-        + LAYER met4 ( -2266930 -1798110 ) ( -2263830 1798110 )
-        + LAYER met4 ( -2446930 -1798110 ) ( -2443830 1798110 )
-        + LAYER met4 ( -2626930 -1798110 ) ( -2623830 1798110 )
-        + LAYER met4 ( -2806930 -1798110 ) ( -2803830 1798110 )
+        + LAYER met4 ( -106930 1644100 ) ( -103830 1798110 )
+        + LAYER met4 ( -286930 1644100 ) ( -283830 1798110 )
+        + LAYER met4 ( -466930 1644100 ) ( -463830 1798110 )
+        + LAYER met4 ( -646930 1644100 ) ( -643830 1798110 )
+        + LAYER met4 ( -826930 1644100 ) ( -823830 1798110 )
+        + LAYER met4 ( -1006930 1644100 ) ( -1003830 1798110 )
+        + LAYER met4 ( -1186930 1644100 ) ( -1183830 1798110 )
+        + LAYER met4 ( -1366930 1644100 ) ( -1363830 1798110 )
+        + LAYER met4 ( -1546930 1644100 ) ( -1543830 1798110 )
+        + LAYER met4 ( -1726930 1644100 ) ( -1723830 1798110 )
+        + LAYER met4 ( -1906930 1644100 ) ( -1903830 1798110 )
+        + LAYER met4 ( -2086930 1644100 ) ( -2083830 1798110 )
+        + LAYER met4 ( -2266930 1644100 ) ( -2263830 1798110 )
+        + LAYER met4 ( -2446930 1644100 ) ( -2443830 1798110 )
+        + LAYER met4 ( -2626930 1644100 ) ( -2623830 1798110 )
+        + LAYER met4 ( -2806930 1644100 ) ( -2803830 1798110 )
         + LAYER met4 ( -3005330 -1798110 ) ( -3002230 1798110 )
-        + LAYER met4 ( -1006930 -1798110 ) ( -1003830 -79840 )
-        + LAYER met4 ( -1186930 -1798110 ) ( -1183830 -79840 )
-        + LAYER met4 ( -1366930 -1798110 ) ( -1363830 -79840 )
-        + LAYER met4 ( -1546930 -1798110 ) ( -1543830 -79840 )
-        + LAYER met4 ( -1726930 -1798110 ) ( -1723830 -79840 )
+        + LAYER met4 ( -106930 -1798110 ) ( -103830 -1619840 )
+        + LAYER met4 ( -286930 -1798110 ) ( -283830 -1619840 )
+        + LAYER met4 ( -466930 -1798110 ) ( -463830 -1619840 )
+        + LAYER met4 ( -646930 -1798110 ) ( -643830 -1619840 )
+        + LAYER met4 ( -826930 -1798110 ) ( -823830 -1619840 )
+        + LAYER met4 ( -1006930 -1798110 ) ( -1003830 -1619840 )
+        + LAYER met4 ( -1186930 -1798110 ) ( -1183830 -1619840 )
+        + LAYER met4 ( -1366930 -1798110 ) ( -1363830 -1619840 )
+        + LAYER met4 ( -1546930 -1798110 ) ( -1543830 -1619840 )
+        + LAYER met4 ( -1726930 -1798110 ) ( -1723830 -1619840 )
+        + LAYER met4 ( -1906930 -1798110 ) ( -1903830 -1619840 )
+        + LAYER met4 ( -2086930 -1798110 ) ( -2083830 -1619840 )
+        + LAYER met4 ( -2266930 -1798110 ) ( -2263830 -1619840 )
+        + LAYER met4 ( -2446930 -1798110 ) ( -2443830 -1619840 )
+        + LAYER met4 ( -2626930 -1798110 ) ( -2623830 -1619840 )
+        + LAYER met4 ( -2806930 -1798110 ) ( -2803830 -1619840 )
         + LAYER met5 ( -3005330 1795010 ) ( 1550 1798110 )
         + LAYER met5 ( -3005330 1640290 ) ( 1550 1643390 )
         + LAYER met5 ( -3005330 1460290 ) ( 1550 1463390 )
@@ -3727,28 +3797,39 @@
     - vssd1 + NET vssd1 + SPECIAL + DIRECTION INPUT + USE GROUND
       + PORT
         + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
-        + LAYER met4 ( -133930 -1769310 ) ( -130830 1769310 )
-        + LAYER met4 ( -313930 -1769310 ) ( -310830 1769310 )
-        + LAYER met4 ( -493930 -1769310 ) ( -490830 1769310 )
-        + LAYER met4 ( -673930 -1769310 ) ( -670830 1769310 )
-        + LAYER met4 ( -853930 -1769310 ) ( -850830 1769310 )
-        + LAYER met4 ( -1033930 530160 ) ( -1030830 1769310 )
-        + LAYER met4 ( -1213930 530160 ) ( -1210830 1769310 )
-        + LAYER met4 ( -1393930 530160 ) ( -1390830 1769310 )
-        + LAYER met4 ( -1573930 530160 ) ( -1570830 1769310 )
-        + LAYER met4 ( -1753930 530160 ) ( -1750830 1769310 )
-        + LAYER met4 ( -1933930 -1769310 ) ( -1930830 1769310 )
-        + LAYER met4 ( -2113930 -1769310 ) ( -2110830 1769310 )
-        + LAYER met4 ( -2293930 -1769310 ) ( -2290830 1769310 )
-        + LAYER met4 ( -2473930 -1769310 ) ( -2470830 1769310 )
-        + LAYER met4 ( -2653930 -1769310 ) ( -2650830 1769310 )
-        + LAYER met4 ( -2833930 -1769310 ) ( -2830830 1769310 )
+        + LAYER met4 ( -133930 1644100 ) ( -130830 1769310 )
+        + LAYER met4 ( -313930 1644100 ) ( -310830 1769310 )
+        + LAYER met4 ( -493930 1644100 ) ( -490830 1769310 )
+        + LAYER met4 ( -673930 1644100 ) ( -670830 1769310 )
+        + LAYER met4 ( -853930 1644100 ) ( -850830 1769310 )
+        + LAYER met4 ( -1033930 1644100 ) ( -1030830 1769310 )
+        + LAYER met4 ( -1213930 1644100 ) ( -1210830 1769310 )
+        + LAYER met4 ( -1393930 1644100 ) ( -1390830 1769310 )
+        + LAYER met4 ( -1573930 1644100 ) ( -1570830 1769310 )
+        + LAYER met4 ( -1753930 1644100 ) ( -1750830 1769310 )
+        + LAYER met4 ( -1933930 1644100 ) ( -1930830 1769310 )
+        + LAYER met4 ( -2113930 1644100 ) ( -2110830 1769310 )
+        + LAYER met4 ( -2293930 1644100 ) ( -2290830 1769310 )
+        + LAYER met4 ( -2473930 1644100 ) ( -2470830 1769310 )
+        + LAYER met4 ( -2653930 1644100 ) ( -2650830 1769310 )
+        + LAYER met4 ( -2833930 1644100 ) ( -2830830 1769310 )
         + LAYER met4 ( -2947730 -1769310 ) ( -2944630 1769310 )
-        + LAYER met4 ( -1033930 -1769310 ) ( -1030830 -69840 )
-        + LAYER met4 ( -1213930 -1769310 ) ( -1210830 -69840 )
-        + LAYER met4 ( -1393930 -1769310 ) ( -1390830 -69840 )
-        + LAYER met4 ( -1573930 -1769310 ) ( -1570830 -69840 )
-        + LAYER met4 ( -1753930 -1769310 ) ( -1750830 -69840 )
+        + LAYER met4 ( -133930 -1769310 ) ( -130830 -1619840 )
+        + LAYER met4 ( -313930 -1769310 ) ( -310830 -1619840 )
+        + LAYER met4 ( -493930 -1769310 ) ( -490830 -1619840 )
+        + LAYER met4 ( -673930 -1769310 ) ( -670830 -1619840 )
+        + LAYER met4 ( -853930 -1769310 ) ( -850830 -1619840 )
+        + LAYER met4 ( -1033930 -1769310 ) ( -1030830 -1619840 )
+        + LAYER met4 ( -1213930 -1769310 ) ( -1210830 -1619840 )
+        + LAYER met4 ( -1393930 -1769310 ) ( -1390830 -1619840 )
+        + LAYER met4 ( -1573930 -1769310 ) ( -1570830 -1619840 )
+        + LAYER met4 ( -1753930 -1769310 ) ( -1750830 -1619840 )
+        + LAYER met4 ( -1933930 -1769310 ) ( -1930830 -1619840 )
+        + LAYER met4 ( -2113930 -1769310 ) ( -2110830 -1619840 )
+        + LAYER met4 ( -2293930 -1769310 ) ( -2290830 -1619840 )
+        + LAYER met4 ( -2473930 -1769310 ) ( -2470830 -1619840 )
+        + LAYER met4 ( -2653930 -1769310 ) ( -2650830 -1619840 )
+        + LAYER met4 ( -2833930 -1769310 ) ( -2830830 -1619840 )
         + LAYER met5 ( -2947730 1766210 ) ( 1550 1769310 )
         + LAYER met5 ( -2947730 1584490 ) ( 1550 1587590 )
         + LAYER met5 ( -2947730 1404490 ) ( 1550 1407590 )
@@ -3774,28 +3855,39 @@
     - vssd2 + NET vssd2 + SPECIAL + DIRECTION INPUT + USE GROUND
       + PORT
         + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
-        + LAYER met4 ( -124930 -1778910 ) ( -121830 1778910 )
-        + LAYER met4 ( -304930 -1778910 ) ( -301830 1778910 )
-        + LAYER met4 ( -484930 -1778910 ) ( -481830 1778910 )
-        + LAYER met4 ( -664930 -1778910 ) ( -661830 1778910 )
-        + LAYER met4 ( -844930 -1778910 ) ( -841830 1778910 )
-        + LAYER met4 ( -1024930 540160 ) ( -1021830 1778910 )
-        + LAYER met4 ( -1204930 540160 ) ( -1201830 1778910 )
-        + LAYER met4 ( -1384930 540160 ) ( -1381830 1778910 )
-        + LAYER met4 ( -1564930 540160 ) ( -1561830 1778910 )
-        + LAYER met4 ( -1744930 540160 ) ( -1741830 1778910 )
-        + LAYER met4 ( -1924930 -1778910 ) ( -1921830 1778910 )
-        + LAYER met4 ( -2104930 -1778910 ) ( -2101830 1778910 )
-        + LAYER met4 ( -2284930 -1778910 ) ( -2281830 1778910 )
-        + LAYER met4 ( -2464930 -1778910 ) ( -2461830 1778910 )
-        + LAYER met4 ( -2644930 -1778910 ) ( -2641830 1778910 )
-        + LAYER met4 ( -2824930 -1778910 ) ( -2821830 1778910 )
+        + LAYER met4 ( -124930 1644100 ) ( -121830 1778910 )
+        + LAYER met4 ( -304930 1644100 ) ( -301830 1778910 )
+        + LAYER met4 ( -484930 1644100 ) ( -481830 1778910 )
+        + LAYER met4 ( -664930 1644100 ) ( -661830 1778910 )
+        + LAYER met4 ( -844930 1644100 ) ( -841830 1778910 )
+        + LAYER met4 ( -1024930 1644100 ) ( -1021830 1778910 )
+        + LAYER met4 ( -1204930 1644100 ) ( -1201830 1778910 )
+        + LAYER met4 ( -1384930 1644100 ) ( -1381830 1778910 )
+        + LAYER met4 ( -1564930 1644100 ) ( -1561830 1778910 )
+        + LAYER met4 ( -1744930 1644100 ) ( -1741830 1778910 )
+        + LAYER met4 ( -1924930 1644100 ) ( -1921830 1778910 )
+        + LAYER met4 ( -2104930 1644100 ) ( -2101830 1778910 )
+        + LAYER met4 ( -2284930 1644100 ) ( -2281830 1778910 )
+        + LAYER met4 ( -2464930 1644100 ) ( -2461830 1778910 )
+        + LAYER met4 ( -2644930 1644100 ) ( -2641830 1778910 )
+        + LAYER met4 ( -2824930 1644100 ) ( -2821830 1778910 )
         + LAYER met4 ( -2966930 -1778910 ) ( -2963830 1778910 )
-        + LAYER met4 ( -1024930 -1778910 ) ( -1021830 -79840 )
-        + LAYER met4 ( -1204930 -1778910 ) ( -1201830 -79840 )
-        + LAYER met4 ( -1384930 -1778910 ) ( -1381830 -79840 )
-        + LAYER met4 ( -1564930 -1778910 ) ( -1561830 -79840 )
-        + LAYER met4 ( -1744930 -1778910 ) ( -1741830 -79840 )
+        + LAYER met4 ( -124930 -1778910 ) ( -121830 -1619840 )
+        + LAYER met4 ( -304930 -1778910 ) ( -301830 -1619840 )
+        + LAYER met4 ( -484930 -1778910 ) ( -481830 -1619840 )
+        + LAYER met4 ( -664930 -1778910 ) ( -661830 -1619840 )
+        + LAYER met4 ( -844930 -1778910 ) ( -841830 -1619840 )
+        + LAYER met4 ( -1024930 -1778910 ) ( -1021830 -1619840 )
+        + LAYER met4 ( -1204930 -1778910 ) ( -1201830 -1619840 )
+        + LAYER met4 ( -1384930 -1778910 ) ( -1381830 -1619840 )
+        + LAYER met4 ( -1564930 -1778910 ) ( -1561830 -1619840 )
+        + LAYER met4 ( -1744930 -1778910 ) ( -1741830 -1619840 )
+        + LAYER met4 ( -1924930 -1778910 ) ( -1921830 -1619840 )
+        + LAYER met4 ( -2104930 -1778910 ) ( -2101830 -1619840 )
+        + LAYER met4 ( -2284930 -1778910 ) ( -2281830 -1619840 )
+        + LAYER met4 ( -2464930 -1778910 ) ( -2461830 -1619840 )
+        + LAYER met4 ( -2644930 -1778910 ) ( -2641830 -1619840 )
+        + LAYER met4 ( -2824930 -1778910 ) ( -2821830 -1619840 )
         + LAYER met5 ( -2966930 1775810 ) ( 1550 1778910 )
         + LAYER met5 ( -2966930 1603090 ) ( 1550 1606190 )
         + LAYER met5 ( -2966930 1423090 ) ( 1550 1426190 )
@@ -4248,9 +4340,1314 @@
 END BLOCKAGES
 SPECIALNETS 8 ;
     - vccd1 ( PIN vccd1 ) + USE POWER
-      + ROUTED met4 0 + SHAPE STRIPE ( 1196840 2175880 ) via4_1600x3100
-      NEW met4 0 + SHAPE STRIPE ( 1196840 1995880 ) via4_1600x3100
-      NEW met4 0 + SHAPE STRIPE ( 1196840 1815880 ) via4_1600x3100
+      + ROUTED met4 0 + SHAPE STRIPE ( 2893940 3255880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1553410 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 947590 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 3255880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 3255880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 3075880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2855770 3075880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2387250 3075880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 3075880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 534270 3075880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 65750 3075880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 3075880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 2895880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2855770 2895880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2387250 2895880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 949430 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 2895880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 534270 2895880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 65750 2895880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 2895880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 2715880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 2715880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 2715880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 2535880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 2535880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 2535880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 2355880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2855240 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2848680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2803680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2713680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2668680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2623680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2578680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2533680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2488680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2443680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2398680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2353680 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2317400 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 604120 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 567840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 522840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 477840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 432840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 387840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 342840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 297840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 252840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 207840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 162840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 117840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 72840 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 66280 2355880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 2355880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 2175880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2855240 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2848680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2803680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2713680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2668680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2623680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2578680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2533680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2488680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2443680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2398680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2353680 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2317400 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 604120 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 567840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 522840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 477840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 432840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 387840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 342840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 297840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 252840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 207840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 162840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 117840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 72840 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 66280 2175880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 2175880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1995880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2855240 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2848680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2803680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2713680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2668680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2623680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2578680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2533680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2488680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2443680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2398680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2353680 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2317400 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 949430 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 604120 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 567840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 522840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 477840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 432840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 387840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 342840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 297840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 252840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 207840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 162840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 117840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 72840 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 66280 1995880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1995880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1815880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 1815880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1815880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1635880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2283640 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2197750 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 949430 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 708100 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 703870 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 637880 1635880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1635880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1455880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 946670 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 744500 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 1455880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1455880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1275880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 946670 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 744500 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 1275880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1275880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 1095880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 946670 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 744500 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 1095880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 1095880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 915880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 915880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 915880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 735880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 735880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 735880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 555880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 555880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 555880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 375880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2867970 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2814120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2769120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2764890 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2758030 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2749020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2704020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2659020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2614020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2569020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2564790 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2557930 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2548920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2503920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2458920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2413920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2368920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2364690 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2357830 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2348820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2303820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2258820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2213820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2168820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2164590 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2157730 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2148720 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2103720 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2058720 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2013720 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1968720 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1964490 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1957630 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1948620 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1903620 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1858620 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1813620 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1768620 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1764390 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1752530 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1743520 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1698520 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1653520 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1608520 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1563520 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1559290 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1547430 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1538420 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1493420 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1448420 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1403420 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1358420 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1354190 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1347330 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1338320 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1293320 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1248320 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1203320 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1158320 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1154090 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1147230 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1138220 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1093220 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1048220 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1003220 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 958220 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 953990 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 942130 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 933120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 888120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 843120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 798120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 753120 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 748890 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 737030 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 728020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 683020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 638020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 593020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 548020 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 543790 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 536930 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 527920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 482920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 437920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 392920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 347920 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 343690 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 336830 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 327820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 282820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 237820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 192820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 147820 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 143590 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 136730 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 112780 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 67780 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 63550 375880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 375880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2893940 195880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 27500 195880 ) via4_3000x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
@@ -4290,331 +5687,40 @@
       NEW met4 0 + SHAPE STRIPE ( 10520 3435880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 3435880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 3255880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 3255880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 3255880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 3075880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 3075880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 3075880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 2895880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 2895880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 2895880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 2715880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 2715880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 2715880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 2535880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 2535880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 2355880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 2355880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 2175880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 2175880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 2175880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1995880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1995880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1995880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1815880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1815880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1815880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1635880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1635880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1635880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1455880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1455880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1455880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1275880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1275880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1275880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 1095880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 1095880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 1095880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 915880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 915880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 915880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 735880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 735880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 735880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 555880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 555880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 555880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 375880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 375880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 375880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2890520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2710520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2530520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2350520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2170520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1990520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1810520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1630520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1450520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1090520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 910520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 730520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 550520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 370520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 190520 195880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 10520 195880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -8480 195880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2928100 15880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2890520 15880 ) via4_3100x3100
@@ -4676,30 +5782,42 @@
       NEW met5 3100 + SHAPE STRIPE ( -14830 195880 ) ( 2934450 195880 )
       NEW met5 3100 + SHAPE STRIPE ( -14830 15880 ) ( 2934450 15880 )
       NEW met5 3100 + SHAPE STRIPE ( -10030 -3120 ) ( 2929650 -3120 )
-      NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1990520 2290000 ) ( 1990520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1810520 2290000 ) ( 1810520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1630520 2290000 ) ( 1630520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1450520 2290000 ) ( 1450520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1270520 2290000 ) ( 1270520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2890520 3403940 ) ( 2890520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2710520 3403940 ) ( 2710520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2530520 3403940 ) ( 2530520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2350520 3403940 ) ( 2350520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2170520 3403940 ) ( 2170520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1990520 3403940 ) ( 1990520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1810520 3403940 ) ( 1810520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1630520 3403940 ) ( 1630520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1450520 3403940 ) ( 1450520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1270520 3403940 ) ( 1270520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1090520 3403940 ) ( 1090520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 910520 3403940 ) ( 910520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 730520 3403940 ) ( 730520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 550520 3403940 ) ( 550520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 370520 3403940 ) ( 370520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 190520 3403940 ) ( 190520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 10520 3403940 ) ( 10520 3529150 )
       NEW met4 3100 + SHAPE STRIPE ( 2928100 -4670 ) ( 2928100 3524350 )
       NEW met4 3100 + SHAPE STRIPE ( -8480 -4670 ) ( -8480 3524350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 1690000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 140000 ) ;
     - vccd2 ( PIN vccd2 ) + USE POWER
       + ROUTED met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2909120 3532400 ) via4_3100x3100
@@ -4740,331 +5858,40 @@
       NEW met4 0 + SHAPE STRIPE ( 29120 3454480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 3454480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 3274480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 3274480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 3274480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 3094480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 3094480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 3094480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2914480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2914480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2914480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2734480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2734480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2734480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2554480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2554480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2554480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2374480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2374480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2374480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2194480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2194480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2194480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 2014480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 2014480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 2014480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 1834480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 1834480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 1834480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 1654480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 1654480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 1654480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 1474480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 1474480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 1474480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 1294480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 1294480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 1294480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 1114480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 1114480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 1114480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 934480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 934480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 934480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 754480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 754480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 754480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 574480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 574480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 574480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 394480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 394480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 394480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2909120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2729120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2549120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2369120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2189120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2009120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1829120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1649120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1469120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1289120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1109120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 929120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 749120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 569120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 389120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 209120 214480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 29120 214480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -18080 214480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2937700 34480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2909120 34480 ) via4_3100x3100
@@ -5126,30 +5953,42 @@
       NEW met5 3100 + SHAPE STRIPE ( -24430 214480 ) ( 2944050 214480 )
       NEW met5 3100 + SHAPE STRIPE ( -24430 34480 ) ( 2944050 34480 )
       NEW met5 3100 + SHAPE STRIPE ( -19630 -12720 ) ( 2939250 -12720 )
-      NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2009120 2300000 ) ( 2009120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1829120 2300000 ) ( 1829120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1649120 2300000 ) ( 1649120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1469120 2300000 ) ( 1469120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1289120 2300000 ) ( 1289120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2909120 3403940 ) ( 2909120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2729120 3403940 ) ( 2729120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2549120 3403940 ) ( 2549120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2369120 3403940 ) ( 2369120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2189120 3403940 ) ( 2189120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2009120 3403940 ) ( 2009120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1829120 3403940 ) ( 1829120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1649120 3403940 ) ( 1649120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1469120 3403940 ) ( 1469120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1289120 3403940 ) ( 1289120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1109120 3403940 ) ( 1109120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 929120 3403940 ) ( 929120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 749120 3403940 ) ( 749120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 569120 3403940 ) ( 569120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 389120 3403940 ) ( 389120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 209120 3403940 ) ( 209120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 29120 3403940 ) ( 29120 3538750 )
       NEW met4 3100 + SHAPE STRIPE ( 2937700 -14270 ) ( 2937700 3533950 )
       NEW met4 3100 + SHAPE STRIPE ( -18080 -14270 ) ( -18080 3533950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 140000 ) ;
     - vdda1 ( PIN vdda1 ) + USE POWER
       + ROUTED met4 0 + SHAPE STRIPE ( 2947300 3542000 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2747720 3542000 ) via4_3100x3100
@@ -5188,313 +6027,40 @@
       NEW met4 0 + SHAPE STRIPE ( 47720 3473080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 3473080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 3293080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 3293080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 3293080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 3113080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 3113080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 3113080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2933080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2933080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2933080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2753080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2753080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2753080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2573080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2573080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2573080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2393080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2393080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2393080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2213080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2213080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2213080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 2033080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 2033080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 2033080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 1853080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 1853080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 1853080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 1673080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 1673080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 1673080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 1493080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 1493080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 1493080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 1313080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 1313080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 1313080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 1133080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 1133080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 1133080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 953080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 953080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 953080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 773080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 773080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 773080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 593080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 593080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 593080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 413080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 413080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 413080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2747720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2567720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2387720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2207720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2027720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1847720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1667720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1487720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1307720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1127720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 947720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 767720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 587720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 407720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 227720 233080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 47720 233080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -27680 233080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2947300 53080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2747720 53080 ) via4_3100x3100
@@ -5554,29 +6120,40 @@
       NEW met5 3100 + SHAPE STRIPE ( -34030 233080 ) ( 2953650 233080 )
       NEW met5 3100 + SHAPE STRIPE ( -34030 53080 ) ( 2953650 53080 )
       NEW met5 3100 + SHAPE STRIPE ( -29230 -22320 ) ( 2948850 -22320 )
-      NEW met4 3100 + SHAPE STRIPE ( 2747720 -28670 ) ( 2747720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2567720 -28670 ) ( 2567720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2387720 -28670 ) ( 2387720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2207720 -28670 ) ( 2207720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2027720 2300000 ) ( 2027720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1847720 2300000 ) ( 1847720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1667720 2300000 ) ( 1667720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1487720 2300000 ) ( 1487720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1307720 2300000 ) ( 1307720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1127720 -28670 ) ( 1127720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 947720 -28670 ) ( 947720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 767720 -28670 ) ( 767720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 587720 -28670 ) ( 587720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 407720 -28670 ) ( 407720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 227720 -28670 ) ( 227720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 47720 -28670 ) ( 47720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2747720 3403940 ) ( 2747720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2567720 3403940 ) ( 2567720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2387720 3403940 ) ( 2387720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2207720 3403940 ) ( 2207720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2027720 3403940 ) ( 2027720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1847720 3403940 ) ( 1847720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1667720 3403940 ) ( 1667720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1487720 3403940 ) ( 1487720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1307720 3403940 ) ( 1307720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1127720 3403940 ) ( 1127720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 947720 3403940 ) ( 947720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 767720 3403940 ) ( 767720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 587720 3403940 ) ( 587720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 407720 3403940 ) ( 407720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 227720 3403940 ) ( 227720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 47720 3403940 ) ( 47720 3548350 )
       NEW met4 3100 + SHAPE STRIPE ( 2947300 -23870 ) ( 2947300 3543550 )
       NEW met4 3100 + SHAPE STRIPE ( -27680 -23870 ) ( -27680 3543550 )
-      NEW met4 3100 + SHAPE STRIPE ( 2027720 -28670 ) ( 2027720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1847720 -28670 ) ( 1847720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1667720 -28670 ) ( 1667720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2747720 -28670 ) ( 2747720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2567720 -28670 ) ( 2567720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2387720 -28670 ) ( 2387720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2207720 -28670 ) ( 2207720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2027720 -28670 ) ( 2027720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1847720 -28670 ) ( 1847720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1667720 -28670 ) ( 1667720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1127720 -28670 ) ( 1127720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 947720 -28670 ) ( 947720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 767720 -28670 ) ( 767720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 587720 -28670 ) ( 587720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 407720 -28670 ) ( 407720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 227720 -28670 ) ( 227720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 47720 -28670 ) ( 47720 140000 ) ;
     - vdda2 ( PIN vdda2 ) + USE POWER
       + ROUTED met4 0 + SHAPE STRIPE ( 2956900 3551600 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2766320 3551600 ) via4_3100x3100
@@ -5615,308 +6192,40 @@
       NEW met4 0 + SHAPE STRIPE ( 66320 3491680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 3491680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 3311680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 3311680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 3311680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 3131680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 3131680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 3131680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2951680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2951680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2951680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2771680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2771680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2771680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2591680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2591680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2591680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2411680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2411680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2411680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2231680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2231680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2231680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 2051680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 2051680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 2051680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 1871680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 1871680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 1871680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 1691680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 1691680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 1691680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 1511680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 1511680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 1511680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 1331680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 1331680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 1331680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 1151680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 1151680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 1151680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 971680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 971680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 971680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 791680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 791680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 791680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 611680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 611680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 611680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 431680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 431680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 431680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2766320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2586320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2406320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2226320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2046320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1866320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1686320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1506320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1326320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1146320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 966320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 786320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 606320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 426320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 246320 251680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 66320 251680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -37280 251680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2956900 71680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2766320 71680 ) via4_3100x3100
@@ -5976,29 +6285,40 @@
       NEW met5 3100 + SHAPE STRIPE ( -43630 251680 ) ( 2963250 251680 )
       NEW met5 3100 + SHAPE STRIPE ( -43630 71680 ) ( 2963250 71680 )
       NEW met5 3100 + SHAPE STRIPE ( -38830 -31920 ) ( 2958450 -31920 )
-      NEW met4 3100 + SHAPE STRIPE ( 2766320 -38270 ) ( 2766320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2046320 2300000 ) ( 2046320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1866320 2300000 ) ( 1866320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1686320 2300000 ) ( 1686320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1506320 2300000 ) ( 1506320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1326320 2300000 ) ( 1326320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1146320 -38270 ) ( 1146320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 966320 -38270 ) ( 966320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 426320 -38270 ) ( 426320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 246320 -38270 ) ( 246320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2766320 3403940 ) ( 2766320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2586320 3403940 ) ( 2586320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2406320 3403940 ) ( 2406320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2226320 3403940 ) ( 2226320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2046320 3403940 ) ( 2046320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1866320 3403940 ) ( 1866320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1686320 3403940 ) ( 1686320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1506320 3403940 ) ( 1506320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1326320 3403940 ) ( 1326320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1146320 3403940 ) ( 1146320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 966320 3403940 ) ( 966320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 786320 3403940 ) ( 786320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 606320 3403940 ) ( 606320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 426320 3403940 ) ( 426320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 246320 3403940 ) ( 246320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 66320 3403940 ) ( 66320 3557950 )
       NEW met4 3100 + SHAPE STRIPE ( 2956900 -33470 ) ( 2956900 3553150 )
       NEW met4 3100 + SHAPE STRIPE ( -37280 -33470 ) ( -37280 3553150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2046320 -38270 ) ( 2046320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1866320 -38270 ) ( 1866320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2766320 -38270 ) ( 2766320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2046320 -38270 ) ( 2046320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1866320 -38270 ) ( 1866320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1146320 -38270 ) ( 1146320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 966320 -38270 ) ( 966320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 426320 -38270 ) ( 426320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 246320 -38270 ) ( 246320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 140000 ) ;
     - vssa1 ( PIN vssa1 ) + USE GROUND
       + ROUTED met4 0 + SHAPE STRIPE ( 2952100 3546800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2837720 3546800 ) via4_3100x3100
@@ -6019,331 +6339,42 @@
       NEW met4 0 + SHAPE STRIPE ( 137720 3546800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 3546800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 3383080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 3383080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 3383080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 3203080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 3203080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 3203080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 3023080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 3023080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 3023080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 2843080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 2843080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 2843080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 2663080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 2663080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 2663080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 2483080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 2483080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 2483080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 2303080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 2303080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 2303080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 2123080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 2123080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 2123080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1943080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1943080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1943080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1763080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1763080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1763080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1583080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1583080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1583080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1403080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1403080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1403080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1223080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1223080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1223080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 1043080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 1043080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 1043080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 863080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 863080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 863080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 683080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 683080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 683080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 503080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 503080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 503080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 323080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 323080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 323080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2837720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2657720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2477720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2297720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2117720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1937720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1757720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1577720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1397720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1217720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1037720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 857720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 677720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 497720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 317720 143080 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 137720 143080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -32480 143080 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2952100 -27120 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2837720 -27120 ) via4_3100x3100
@@ -6385,28 +6416,39 @@
       NEW met5 3100 + SHAPE STRIPE ( -34030 143080 ) ( 2953650 143080 )
       NEW met5 3100 + SHAPE STRIPE ( -34030 -27120 ) ( 2953650 -27120 )
       NEW met4 3100 + SHAPE STRIPE ( 2952100 -28670 ) ( 2952100 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2297720 -28670 ) ( 2297720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 2117720 -28670 ) ( 2117720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1937720 2300000 ) ( 1937720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1757720 2300000 ) ( 1757720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1577720 2300000 ) ( 1577720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1397720 2300000 ) ( 1397720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1217720 2300000 ) ( 1217720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1037720 -28670 ) ( 1037720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2837720 3403940 ) ( 2837720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2657720 3403940 ) ( 2657720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2477720 3403940 ) ( 2477720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2297720 3403940 ) ( 2297720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 2117720 3403940 ) ( 2117720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1937720 3403940 ) ( 1937720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1757720 3403940 ) ( 1757720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1577720 3403940 ) ( 1577720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1397720 3403940 ) ( 1397720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1217720 3403940 ) ( 1217720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 1037720 3403940 ) ( 1037720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 857720 3403940 ) ( 857720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 677720 3403940 ) ( 677720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 497720 3403940 ) ( 497720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 317720 3403940 ) ( 317720 3548350 )
+      NEW met4 3100 + SHAPE STRIPE ( 137720 3403940 ) ( 137720 3548350 )
       NEW met4 3100 + SHAPE STRIPE ( -32480 -28670 ) ( -32480 3548350 )
-      NEW met4 3100 + SHAPE STRIPE ( 1937720 -28670 ) ( 1937720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1757720 -28670 ) ( 1757720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2297720 -28670 ) ( 2297720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2117720 -28670 ) ( 2117720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1937720 -28670 ) ( 1937720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1757720 -28670 ) ( 1757720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1037720 -28670 ) ( 1037720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 140000 ) ;
     - vssa2 ( PIN vssa2 ) + USE GROUND
       + ROUTED met4 0 + SHAPE STRIPE ( 2961700 3556400 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2856320 3556400 ) via4_3100x3100
@@ -6427,331 +6469,42 @@
       NEW met4 0 + SHAPE STRIPE ( 156320 3556400 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 3556400 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 3401680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 3401680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 3401680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 3221680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 3221680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 3221680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 3041680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 3041680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 3041680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 2861680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 2861680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 2861680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 2681680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 2681680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 2681680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 2501680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 2501680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 2501680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 2321680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 2321680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 2321680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 2141680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 2141680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 2141680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1961680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1961680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1961680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1781680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1781680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1781680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1601680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1601680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1601680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1421680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1421680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1421680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1241680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1241680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1241680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 1061680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 1061680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 1061680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 881680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 881680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 881680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 701680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 701680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 701680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 521680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 521680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 521680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 341680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 341680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 341680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2856320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2676320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2496320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2316320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2136320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1956320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1776320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1596320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1416320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1236320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1056320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 876320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 696320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 516320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 336320 161680 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 156320 161680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -42080 161680 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2961700 -36720 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2856320 -36720 ) via4_3100x3100
@@ -6793,33 +6546,1430 @@
       NEW met5 3100 + SHAPE STRIPE ( -43630 161680 ) ( 2963250 161680 )
       NEW met5 3100 + SHAPE STRIPE ( -43630 -36720 ) ( 2963250 -36720 )
       NEW met4 3100 + SHAPE STRIPE ( 2961700 -38270 ) ( 2961700 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 2136320 -38270 ) ( 2136320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1956320 2300000 ) ( 1956320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1776320 2300000 ) ( 1776320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1596320 2300000 ) ( 1596320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1416320 2300000 ) ( 1416320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1236320 2300000 ) ( 1236320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1056320 -38270 ) ( 1056320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2856320 3403940 ) ( 2856320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2676320 3403940 ) ( 2676320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2496320 3403940 ) ( 2496320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2316320 3403940 ) ( 2316320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 2136320 3403940 ) ( 2136320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1956320 3403940 ) ( 1956320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1776320 3403940 ) ( 1776320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1596320 3403940 ) ( 1596320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1416320 3403940 ) ( 1416320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1236320 3403940 ) ( 1236320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 1056320 3403940 ) ( 1056320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 876320 3403940 ) ( 876320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 696320 3403940 ) ( 696320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 516320 3403940 ) ( 516320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 336320 3403940 ) ( 336320 3557950 )
+      NEW met4 3100 + SHAPE STRIPE ( 156320 3403940 ) ( 156320 3557950 )
       NEW met4 3100 + SHAPE STRIPE ( -42080 -38270 ) ( -42080 3557950 )
-      NEW met4 3100 + SHAPE STRIPE ( 1956320 -38270 ) ( 1956320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1776320 -38270 ) ( 1776320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2136320 -38270 ) ( 2136320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1956320 -38270 ) ( 1956320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1776320 -38270 ) ( 1776320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1056320 -38270 ) ( 1056320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 140000 ) ;
     - vssd1 ( PIN vssd1 ) + USE GROUND
-      + ROUTED met4 0 + SHAPE STRIPE ( 1273640 2265880 ) via4_1600x3100
-      NEW met4 0 + SHAPE STRIPE ( 1273640 2085880 ) via4_1600x3100
-      NEW met4 0 + SHAPE STRIPE ( 1273640 1905880 ) via4_1600x3100
-      NEW met4 0 + SHAPE STRIPE ( 1273640 1725880 ) via4_1600x3100
+      + ROUTED met4 0 + SHAPE STRIPE ( 2897940 3345880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 3345880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 3345880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 3165880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859170 3165880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2383850 3165880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 3165880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 537670 3165880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 62350 3165880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 3165880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2985880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859170 2985880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2383850 2985880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2985880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 537670 2985880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 62350 2985880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2985880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2805880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2859170 2805880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2383850 2805880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2805880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 537670 2805880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 62350 2805880 ) via4_1740x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2805880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2625880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2625880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2625880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2445880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857440 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2850680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2805680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2760680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2715680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2670680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2625680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2580680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2535680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2490680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2445680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2400680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2355680 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2315200 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 949430 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 606320 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 565840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 520840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 475840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 430840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 385840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 340840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 295840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 250840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 205840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 160840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 115840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 70840 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 2445880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2445880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2265880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857440 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2850680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2805680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2760680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2715680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2670680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2625680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2580680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2535680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2490680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2445680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2400680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2355680 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2315200 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 606320 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 565840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 520840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 475840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 430840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 385840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 340840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 295840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 250840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 205840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 160840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 115840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 70840 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 2265880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2265880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 2085880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857440 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2850680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2805680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2760680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2715680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2670680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2625680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2580680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2535680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2490680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2445680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2400680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2355680 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2315200 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 606320 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 565840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 520840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 475840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 430840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 385840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 340840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 295840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 250840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 205840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 160840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 115840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 70840 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 2085880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 2085880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1905880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 606320 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 565840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 520840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 475840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 430840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 385840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 340840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 295840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 250840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 205840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 160840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 115840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 70840 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 1905880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1905880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1725880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 1725880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1725880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1545880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2285640 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2199550 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 706100 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 702070 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 635880 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 64080 1545880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1545880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1365880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1757190 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1554790 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 1365880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1365880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1185880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1757190 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1554790 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 138530 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 110780 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 65780 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 61750 1185880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1185880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 1005880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 138530 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 110780 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 65780 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 61750 1005880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 1005880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 825880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 138530 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 110780 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 65780 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 61750 825880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 825880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 645880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 138530 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 110780 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 65780 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 61750 645880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 645880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 465880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 138530 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 110780 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 65780 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 61750 465880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 465880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2897940 285880 ) via4_3000x3100
+      NEW met4 0 + SHAPE STRIPE ( 2869770 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2857120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2812120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2767120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2763090 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2759830 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2747020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2702020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2657020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2612020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2567020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2562990 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2559730 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2546920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2501920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2456920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2411920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2366920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2362890 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2359630 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2346820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2301820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2256820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2211820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2166820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2162790 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2159530 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2146720 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2101720 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2056720 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 2011720 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1966720 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1962690 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1959430 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1946620 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1901620 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1856620 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1811620 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1766620 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1762590 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1754330 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1741520 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1696520 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1651520 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1606520 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1561520 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1557490 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1549230 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1536420 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1491420 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1446420 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1401420 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1356420 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1352390 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1349130 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1336320 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1291320 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1246320 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1201320 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1156320 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1152290 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1149030 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1136220 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1091220 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1046220 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 1001220 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 956220 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 952190 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 943930 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 931120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 886120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 841120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 796120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 751120 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 747090 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 738830 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 726020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 681020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 636020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 591020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 546020 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 541990 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 538730 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 525920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 480920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 435920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 390920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 345920 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 341890 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 338630 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 325820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 280820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 235820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 190820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 145820 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 141790 285880 ) via4_1200x3100
+      NEW met4 0 + SHAPE STRIPE ( 23500 285880 ) via4_3000x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 3527600 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2800520 3527600 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2620520 3527600 ) via4_3100x3100
@@ -6839,308 +7989,40 @@
       NEW met4 0 + SHAPE STRIPE ( 100520 3527600 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 3527600 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 3345880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 3345880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 3345880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 3165880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 3165880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 3165880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2985880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2985880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2985880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2805880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2805880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2805880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2625880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2625880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2625880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2445880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2445880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2445880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2265880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2265880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2265880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 2085880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 2085880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 2085880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1905880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1905880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1905880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1725880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1725880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1725880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1545880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1545880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1545880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1365880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1365880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1365880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1185880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1185880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1185880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 1005880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 1005880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 1005880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 825880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 825880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 825880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 645880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 645880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 645880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 465880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 465880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 465880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2800520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2620520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2440520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2260520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2080520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1900520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1720520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1540520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1360520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1180520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1000520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 820520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 640520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 460520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 280520 285880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 100520 285880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -13280 285880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2932900 105880 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2800520 105880 ) via4_3100x3100
@@ -7200,28 +8082,39 @@
       NEW met5 3100 + SHAPE STRIPE ( -14830 105880 ) ( 2934450 105880 )
       NEW met5 3100 + SHAPE STRIPE ( -14830 -7920 ) ( 2934450 -7920 )
       NEW met4 3100 + SHAPE STRIPE ( 2932900 -9470 ) ( 2932900 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1900520 2290000 ) ( 1900520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1720520 2290000 ) ( 1720520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1540520 2290000 ) ( 1540520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1360520 2290000 ) ( 1360520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1180520 2290000 ) ( 1180520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2800520 3403940 ) ( 2800520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2620520 3403940 ) ( 2620520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2440520 3403940 ) ( 2440520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2260520 3403940 ) ( 2260520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 2080520 3403940 ) ( 2080520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1900520 3403940 ) ( 1900520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1720520 3403940 ) ( 1720520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1540520 3403940 ) ( 1540520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1360520 3403940 ) ( 1360520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1180520 3403940 ) ( 1180520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 1000520 3403940 ) ( 1000520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 820520 3403940 ) ( 820520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 640520 3403940 ) ( 640520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 460520 3403940 ) ( 460520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 280520 3403940 ) ( 280520 3529150 )
+      NEW met4 3100 + SHAPE STRIPE ( 100520 3403940 ) ( 100520 3529150 )
       NEW met4 3100 + SHAPE STRIPE ( -13280 -9470 ) ( -13280 3529150 )
-      NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 1690000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 1690000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 140000 ) ;
     - vssd2 ( PIN vssd2 ) + USE GROUND
       + ROUTED met4 0 + SHAPE STRIPE ( 2942500 3537200 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2819120 3537200 ) via4_3100x3100
@@ -7242,308 +8135,40 @@
       NEW met4 0 + SHAPE STRIPE ( 119120 3537200 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 3537200 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 3364480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 3364480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 3364480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 3184480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 3184480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 3184480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 3004480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 3004480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 3004480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 2824480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 2824480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 2824480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 2644480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 2644480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 2644480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 2464480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 2464480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 2464480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 2284480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 2284480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 2284480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 2104480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 2104480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 2104480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1924480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1924480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1924480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1744480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1744480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1744480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1564480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1564480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1564480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1384480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1384480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1384480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1204480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1204480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1204480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 1024480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 1024480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 1024480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 844480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 844480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 844480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 664480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 664480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 664480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 484480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 484480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 484480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2819120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2639120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2459120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2279120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2099120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1919120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1739120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1559120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1379120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1199120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1019120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 839120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 659120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 479120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 299120 304480 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 119120 304480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( -22880 304480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2942500 124480 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2819120 124480 ) via4_3100x3100
@@ -7603,30 +8228,41 @@
       NEW met5 3100 + SHAPE STRIPE ( -24430 124480 ) ( 2944050 124480 )
       NEW met5 3100 + SHAPE STRIPE ( -24430 -17520 ) ( 2944050 -17520 )
       NEW met4 3100 + SHAPE STRIPE ( 2942500 -19070 ) ( 2942500 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1919120 2300000 ) ( 1919120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1739120 2300000 ) ( 1739120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1559120 2300000 ) ( 1559120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1379120 2300000 ) ( 1379120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1199120 2300000 ) ( 1199120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2819120 3403940 ) ( 2819120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2639120 3403940 ) ( 2639120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2459120 3403940 ) ( 2459120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2279120 3403940 ) ( 2279120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 2099120 3403940 ) ( 2099120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1919120 3403940 ) ( 1919120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1739120 3403940 ) ( 1739120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1559120 3403940 ) ( 1559120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1379120 3403940 ) ( 1379120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1199120 3403940 ) ( 1199120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 1019120 3403940 ) ( 1019120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 839120 3403940 ) ( 839120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 659120 3403940 ) ( 659120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 479120 3403940 ) ( 479120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 299120 3403940 ) ( 299120 3538750 )
+      NEW met4 3100 + SHAPE STRIPE ( 119120 3403940 ) ( 119120 3538750 )
       NEW met4 3100 + SHAPE STRIPE ( -22880 -19070 ) ( -22880 3538750 )
-      NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
-      NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
+      NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 140000 )
+      NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 140000 ) ;
 END SPECIALNETS
-NETS 637 ;
+NETS 635 ;
     - analog_io[0] ( PIN analog_io[0] ) + USE SIGNAL ;
     - analog_io[10] ( PIN analog_io[10] ) + USE SIGNAL ;
     - analog_io[11] ( PIN analog_io[11] ) + USE SIGNAL ;
@@ -7656,6643 +8292,2671 @@
     - analog_io[7] ( PIN analog_io[7] ) + USE SIGNAL ;
     - analog_io[8] ( PIN analog_io[8] ) + USE SIGNAL ;
     - analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ;
-    - io_in[0] ( PIN io_in[0] ) ( mprj io_in[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 32980 ) ( * 34170 )
-      NEW met3 ( 2900990 32980 ) ( 2917780 * 0 )
-      NEW met2 ( 1173230 2286500 ) ( 1178980 * 0 )
-      NEW met2 ( 1173230 34170 ) ( * 2286500 )
-      NEW met1 ( 1173230 34170 ) ( 2900990 * )
-      NEW met1 ( 1173230 34170 ) M1M2_PR
-      NEW met1 ( 2900990 34170 ) M1M2_PR
-      NEW met2 ( 2900990 32980 ) M2M3_PR_M ;
-    - io_in[10] ( PIN io_in[10] ) ( mprj io_in[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2899150 2284290 ) ( * 2290580 )
-      NEW met3 ( 2899150 2290580 ) ( 2917780 * 0 )
-      NEW li1 ( 1417490 2284290 ) ( * 2288030 )
-      NEW met2 ( 1417490 2287860 ) ( * 2288030 )
-      NEW met2 ( 1415880 2287860 0 ) ( 1417490 * )
-      NEW met1 ( 1417490 2284290 ) ( 2899150 * )
-      NEW met1 ( 2899150 2284290 ) M1M2_PR
-      NEW met2 ( 2899150 2290580 ) M2M3_PR_M
-      NEW li1 ( 1417490 2284290 ) L1M1_PR_MR
-      NEW li1 ( 1417490 2288030 ) L1M1_PR_MR
-      NEW met1 ( 1417490 2288030 ) M1M2_PR
-      NEW met1 ( 1417490 2288030 ) RECT ( -355 -70 0 70 )  ;
-    - io_in[11] ( PIN io_in[11] ) ( mprj io_in[11] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2553230 ) ( * 2556460 )
-      NEW met3 ( 2900990 2556460 ) ( 2917780 * 0 )
-      NEW met1 ( 1441870 2553230 ) ( 2900990 * )
-      NEW met2 ( 1441870 2332200 ) ( * 2553230 )
-      NEW met2 ( 1439340 2289900 0 ) ( 1441410 * )
-      NEW met2 ( 1441410 2289900 ) ( * 2332200 )
-      NEW met2 ( 1441410 2332200 ) ( 1441870 * )
-      NEW met1 ( 1441870 2553230 ) M1M2_PR
-      NEW met1 ( 2900990 2553230 ) M1M2_PR
-      NEW met2 ( 2900990 2556460 ) M2M3_PR_M ;
-    - io_in[12] ( PIN io_in[12] ) ( mprj io_in[12] ) + USE SIGNAL
-      + ROUTED met2 ( 2899150 2815370 ) ( * 2821660 )
-      NEW met3 ( 2899150 2821660 ) ( 2917780 * 0 )
-      NEW met2 ( 1463260 2289900 0 ) ( 1464870 * )
-      NEW met2 ( 1464870 2289900 ) ( * 2297890 )
-      NEW met1 ( 1464870 2297890 ) ( 1469470 * )
-      NEW met2 ( 1469470 2297890 ) ( * 2815370 )
-      NEW met1 ( 1469470 2815370 ) ( 2899150 * )
-      NEW met1 ( 1469470 2815370 ) M1M2_PR
-      NEW met1 ( 2899150 2815370 ) M1M2_PR
-      NEW met2 ( 2899150 2821660 ) M2M3_PR_M
-      NEW met1 ( 1464870 2297890 ) M1M2_PR
-      NEW met1 ( 1469470 2297890 ) M1M2_PR ;
-    - io_in[13] ( PIN io_in[13] ) ( mprj io_in[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3084310 ) ( * 3087540 )
-      NEW met3 ( 2900990 3087540 ) ( 2917780 * 0 )
-      NEW met1 ( 1490170 3084310 ) ( 2900990 * )
-      NEW met2 ( 1486720 2289900 0 ) ( 1488790 * )
-      NEW met2 ( 1488790 2289900 ) ( * 2304600 )
-      NEW met2 ( 1488790 2304600 ) ( 1490170 * )
-      NEW met2 ( 1490170 2304600 ) ( * 3084310 )
-      NEW met1 ( 2900990 3084310 ) M1M2_PR
-      NEW met2 ( 2900990 3087540 ) M2M3_PR_M
-      NEW met1 ( 1490170 3084310 ) M1M2_PR ;
-    - io_in[14] ( PIN io_in[14] ) ( mprj io_in[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3353420 ) ( * 3353930 )
-      NEW met3 ( 2900990 3353420 ) ( 2917780 * 0 )
-      NEW met2 ( 1510640 2289900 0 ) ( * 2291260 )
-      NEW met2 ( 1510640 2291260 ) ( 1510870 * )
-      NEW met2 ( 1510870 2291260 ) ( * 3353930 )
-      NEW met1 ( 1510870 3353930 ) ( 2900990 * )
-      NEW met1 ( 2900990 3353930 ) M1M2_PR
-      NEW met2 ( 2900990 3353420 ) M2M3_PR_M
-      NEW met1 ( 1510870 3353930 ) M1M2_PR ;
-    - io_in[15] ( PIN io_in[15] ) ( mprj io_in[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1534100 2289900 0 ) ( 1535710 * )
-      NEW met2 ( 1535710 2289900 ) ( * 2300950 )
-      NEW met2 ( 2794730 2300950 ) ( * 3512100 )
+    - io_in[0] ( PIN io_in[0] ) ( inst_eFPGA_CPU_top io_in[0] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 32980 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 160820 ) ( 2912030 * )
+      NEW met3 ( 2903980 160640 ) ( * 160820 )
+      NEW met3 ( 2901220 160640 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 32980 ) ( * 160820 )
+      NEW met2 ( 2912030 32980 ) M2M3_PR_M
+      NEW met2 ( 2912030 160820 ) M2M3_PR_M ;
+    - io_in[10] ( PIN io_in[10] ) ( inst_eFPGA_CPU_top io_in[10] ) + USE SIGNAL
+      + ROUTED met3 ( 2903290 2290580 ) ( 2917780 * 0 )
+      NEW met3 ( 2901220 2358470 0 ) ( 2903290 * )
+      NEW met2 ( 2903290 2290580 ) ( * 2358470 )
+      NEW met2 ( 2903290 2290580 ) M2M3_PR_M
+      NEW met2 ( 2903290 2358470 ) M2M3_PR_M ;
+    - io_in[11] ( PIN io_in[11] ) ( inst_eFPGA_CPU_top io_in[11] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 2578070 0 ) ( 2903980 * )
+      NEW met3 ( 2903980 2578070 ) ( * 2578220 )
+      NEW met3 ( 2903980 2578220 ) ( 2912030 * )
+      NEW met2 ( 2912030 2556460 ) ( * 2578220 )
+      NEW met3 ( 2912030 2556460 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 2578220 ) M2M3_PR_M
+      NEW met2 ( 2912030 2556460 ) M2M3_PR_M ;
+    - io_in[12] ( PIN io_in[12] ) ( inst_eFPGA_CPU_top io_in[12] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 2798280 0 ) ( 2903980 * )
+      NEW met3 ( 2903980 2798280 ) ( * 2798540 )
+      NEW met3 ( 2903980 2798540 ) ( 2912030 * )
+      NEW met2 ( 2912030 2798540 ) ( * 2821660 )
+      NEW met3 ( 2912030 2821660 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 2798540 ) M2M3_PR_M
+      NEW met2 ( 2912030 2821660 ) M2M3_PR_M ;
+    - io_in[13] ( PIN io_in[13] ) ( inst_eFPGA_CPU_top io_in[13] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 3017880 0 ) ( 2902830 * )
+      NEW met3 ( 2902830 3087540 ) ( 2917780 * 0 )
+      NEW met2 ( 2902830 3017880 ) ( * 3087540 )
+      NEW met2 ( 2902830 3017880 ) M2M3_PR_M
+      NEW met2 ( 2902830 3087540 ) M2M3_PR_M ;
+    - io_in[14] ( PIN io_in[14] ) ( inst_eFPGA_CPU_top io_in[14] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 3237820 ) ( 2908350 * )
+      NEW met3 ( 2903980 3237480 ) ( * 3237820 )
+      NEW met3 ( 2901220 3237480 0 ) ( 2903980 * )
+      NEW met3 ( 2908350 3353420 ) ( 2917780 * 0 )
+      NEW met2 ( 2908350 3237820 ) ( * 3353420 )
+      NEW met2 ( 2908350 3237820 ) M2M3_PR_M
+      NEW met2 ( 2908350 3353420 ) M2M3_PR_M ;
+    - io_in[15] ( PIN io_in[15] ) ( inst_eFPGA_CPU_top io_in[15] ) + USE SIGNAL
+      + ROUTED met2 ( 2890630 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2890410 3394220 ) ( 2890630 * )
+      NEW met2 ( 2890410 3394220 ) ( * 3404930 )
+      NEW met2 ( 2794730 3404930 ) ( * 3512100 )
       NEW met2 ( 2794730 3512100 ) ( 2798410 * )
       NEW met2 ( 2798410 3512100 ) ( * 3517980 0 )
-      NEW met1 ( 1535710 2300950 ) ( 2794730 * )
-      NEW met1 ( 1535710 2300950 ) M1M2_PR
-      NEW met1 ( 2794730 2300950 ) M1M2_PR ;
-    - io_in[16] ( PIN io_in[16] ) ( mprj io_in[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1558020 2289900 0 ) ( 1559170 * )
-      NEW met2 ( 1559170 2289900 ) ( * 2301630 )
-      NEW met1 ( 1559170 2301630 ) ( 2470430 * )
+      NEW met1 ( 2794730 3404930 ) ( 2890410 * )
+      NEW met1 ( 2794730 3404930 ) M1M2_PR
+      NEW met1 ( 2890410 3404930 ) M1M2_PR ;
+    - io_in[16] ( PIN io_in[16] ) ( inst_eFPGA_CPU_top io_in[16] ) + USE SIGNAL
+      + ROUTED met2 ( 2560810 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2560590 3394220 ) ( 2560810 * )
+      NEW met2 ( 2560590 3394220 ) ( * 3404930 )
+      NEW met1 ( 2470430 3404930 ) ( 2560590 * )
       NEW met2 ( 2470430 3517980 ) ( 2473190 * )
       NEW met2 ( 2473190 3517300 ) ( * 3517980 )
       NEW met2 ( 2473190 3517300 ) ( 2474110 * )
       NEW met2 ( 2474110 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 2470430 2301630 ) ( * 3517980 )
-      NEW met1 ( 1559170 2301630 ) M1M2_PR
-      NEW met1 ( 2470430 2301630 ) M1M2_PR ;
-    - io_in[17] ( PIN io_in[17] ) ( mprj io_in[17] ) + USE SIGNAL
-      + ROUTED met2 ( 2146130 3517980 ) ( 2148430 * )
+      NEW met2 ( 2470430 3404930 ) ( * 3517980 )
+      NEW met1 ( 2470430 3404930 ) M1M2_PR
+      NEW met1 ( 2560590 3404930 ) M1M2_PR ;
+    - io_in[17] ( PIN io_in[17] ) ( inst_eFPGA_CPU_top io_in[17] ) + USE SIGNAL
+      + ROUTED met2 ( 2230530 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2230310 3394220 ) ( 2230530 * )
+      NEW met2 ( 2230310 3394220 ) ( * 3404930 )
+      NEW met2 ( 2146130 3517980 ) ( 2148430 * )
       NEW met2 ( 2148430 3517300 ) ( * 3517980 )
       NEW met2 ( 2148430 3517300 ) ( 2149350 * )
       NEW met2 ( 2149350 3517300 ) ( * 3517980 0 )
-      NEW met2 ( 2146130 2302990 ) ( * 3517980 )
-      NEW met2 ( 1581480 2289900 0 ) ( 1583090 * )
-      NEW met2 ( 1583090 2289900 ) ( * 2302990 )
-      NEW met1 ( 1583090 2302990 ) ( 2146130 * )
-      NEW met1 ( 2146130 2302990 ) M1M2_PR
-      NEW met1 ( 1583090 2302990 ) M1M2_PR ;
-    - io_in[18] ( PIN io_in[18] ) ( mprj io_in[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1821830 2303670 ) ( * 3512100 )
+      NEW met2 ( 2146130 3404930 ) ( * 3517980 )
+      NEW met1 ( 2146130 3404930 ) ( 2230310 * )
+      NEW met1 ( 2146130 3404930 ) M1M2_PR
+      NEW met1 ( 2230310 3404930 ) M1M2_PR ;
+    - io_in[18] ( PIN io_in[18] ) ( inst_eFPGA_CPU_top io_in[18] ) + USE SIGNAL
+      + ROUTED met2 ( 1821830 3404930 ) ( * 3512100 )
       NEW met2 ( 1821830 3512100 ) ( 1825050 * )
       NEW met2 ( 1825050 3512100 ) ( * 3517980 0 )
-      NEW met2 ( 1605400 2289900 0 ) ( 1607010 * )
-      NEW met2 ( 1607010 2289900 ) ( * 2303670 )
-      NEW met1 ( 1607010 2303670 ) ( 1821830 * )
-      NEW met1 ( 1821830 2303670 ) M1M2_PR
-      NEW met1 ( 1607010 2303670 ) M1M2_PR ;
-    - io_in[19] ( PIN io_in[19] ) ( mprj io_in[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1628630 2289900 ) ( 1628860 * 0 )
-      NEW met2 ( 1628630 2289900 ) ( * 2304010 )
-      NEW met1 ( 1500750 3498430 ) ( 1503970 * )
-      NEW met2 ( 1503970 2304010 ) ( * 3498430 )
-      NEW met2 ( 1500750 3498430 ) ( * 3517980 0 )
-      NEW met1 ( 1503970 2304010 ) ( 1628630 * )
-      NEW met1 ( 1628630 2304010 ) M1M2_PR
-      NEW met1 ( 1500750 3498430 ) M1M2_PR
-      NEW met1 ( 1503970 3498430 ) M1M2_PR
-      NEW met1 ( 1503970 2304010 ) M1M2_PR ;
-    - io_in[1] ( PIN io_in[1] ) ( mprj io_in[1] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 228140 ) ( * 230860 )
-      NEW met3 ( 2916860 230860 ) ( 2917780 * )
-      NEW met3 ( 2916860 230860 ) ( * 231540 )
-      NEW met3 ( 2916860 231540 ) ( 2917780 * 0 )
-      NEW met3 ( 1204050 2286500 ) ( 1206580 * )
-      NEW met2 ( 1202440 2286500 0 ) ( 1204050 * )
-      NEW met4 ( 1206580 228140 ) ( * 2286500 )
-      NEW met3 ( 1206580 228140 ) ( 2917780 * )
-      NEW met3 ( 1206580 228140 ) M3M4_PR_M
-      NEW met3 ( 1206580 2286500 ) M3M4_PR_M
-      NEW met2 ( 1204050 2286500 ) M2M3_PR_M ;
-    - io_in[20] ( PIN io_in[20] ) ( mprj io_in[20] ) + USE SIGNAL
-      + ROUTED met1 ( 1175990 3498430 ) ( 1179670 * )
-      NEW met2 ( 1179670 2303330 ) ( * 3498430 )
-      NEW met2 ( 1175990 3498430 ) ( * 3517980 0 )
-      NEW met2 ( 1651170 2289900 ) ( 1652780 * 0 )
-      NEW met2 ( 1651170 2289900 ) ( * 2303330 )
-      NEW met1 ( 1179670 2303330 ) ( 1651170 * )
-      NEW met1 ( 1175990 3498430 ) M1M2_PR
-      NEW met1 ( 1179670 3498430 ) M1M2_PR
-      NEW met1 ( 1179670 2303330 ) M1M2_PR
-      NEW met1 ( 1651170 2303330 ) M1M2_PR ;
-    - io_in[21] ( PIN io_in[21] ) ( mprj io_in[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1674630 2289900 ) ( 1676240 * 0 )
-      NEW met2 ( 1674630 2289900 ) ( * 2301970 )
-      NEW met1 ( 851690 3498430 ) ( 855370 * )
-      NEW met2 ( 855370 2301970 ) ( * 3498430 )
-      NEW met2 ( 851690 3498430 ) ( * 3517980 0 )
-      NEW li1 ( 1438190 2301970 ) ( 1439110 * )
-      NEW met1 ( 855370 2301970 ) ( 1438190 * )
-      NEW met1 ( 1439110 2301970 ) ( 1674630 * )
-      NEW met1 ( 1674630 2301970 ) M1M2_PR
-      NEW met1 ( 851690 3498430 ) M1M2_PR
-      NEW met1 ( 855370 3498430 ) M1M2_PR
-      NEW met1 ( 855370 2301970 ) M1M2_PR
-      NEW li1 ( 1438190 2301970 ) L1M1_PR_MR
-      NEW li1 ( 1439110 2301970 ) L1M1_PR_MR ;
-    - io_in[22] ( PIN io_in[22] ) ( mprj io_in[22] ) + USE SIGNAL
-      + ROUTED met1 ( 527390 3498430 ) ( 531070 * )
-      NEW met2 ( 531070 2301290 ) ( * 3498430 )
-      NEW met2 ( 527390 3498430 ) ( * 3517980 0 )
-      NEW met2 ( 1698550 2289900 ) ( 1700160 * 0 )
-      NEW met2 ( 1698550 2289900 ) ( * 2301290 )
-      NEW met1 ( 531070 2301290 ) ( 1698550 * )
-      NEW met1 ( 527390 3498430 ) M1M2_PR
-      NEW met1 ( 531070 3498430 ) M1M2_PR
-      NEW met1 ( 531070 2301290 ) M1M2_PR
-      NEW met1 ( 1698550 2301290 ) M1M2_PR ;
-    - io_in[23] ( PIN io_in[23] ) ( mprj io_in[23] ) + USE SIGNAL
-      + ROUTED met2 ( 202630 3502170 ) ( * 3517980 0 )
-      NEW met1 ( 202630 3502170 ) ( 1718330 * )
-      NEW met2 ( 1721550 2289900 ) ( 1723620 * 0 )
-      NEW met2 ( 1718330 2401200 ) ( 1721550 * )
-      NEW met2 ( 1721550 2289900 ) ( * 2401200 )
-      NEW met2 ( 1718330 2401200 ) ( * 3502170 )
-      NEW met1 ( 202630 3502170 ) M1M2_PR
-      NEW met1 ( 1718330 3502170 ) M1M2_PR ;
-    - io_in[24] ( PIN io_in[24] ) ( mprj io_in[24] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3421420 0 ) ( 17250 * )
-      NEW met2 ( 17250 3415810 ) ( * 3421420 )
-      NEW met2 ( 1745930 2289900 ) ( 1747540 * 0 )
-      NEW met2 ( 1745930 2289900 ) ( * 3415810 )
-      NEW met1 ( 17250 3415810 ) ( 1745930 * )
-      NEW met2 ( 17250 3421420 ) M2M3_PR_M
-      NEW met1 ( 17250 3415810 ) M1M2_PR
-      NEW met1 ( 1745930 3415810 ) M1M2_PR ;
-    - io_in[25] ( PIN io_in[25] ) ( mprj io_in[25] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3160300 0 ) ( 17250 * )
-      NEW met2 ( 17250 3160300 ) ( * 3160470 )
-      NEW met2 ( 1768930 2289900 ) ( 1771000 * 0 )
-      NEW met2 ( 1766630 2401200 ) ( 1768930 * )
-      NEW met2 ( 1768930 2289900 ) ( * 2401200 )
-      NEW met2 ( 1766630 2401200 ) ( * 3160470 )
-      NEW met1 ( 17250 3160470 ) ( 1766630 * )
-      NEW met2 ( 17250 3160300 ) M2M3_PR_M
-      NEW met1 ( 17250 3160470 ) M1M2_PR
-      NEW met1 ( 1766630 3160470 ) M1M2_PR ;
-    - io_in[26] ( PIN io_in[26] ) ( mprj io_in[26] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2899860 0 ) ( 16790 * )
-      NEW met2 ( 16790 2898330 ) ( * 2899860 )
-      NEW met1 ( 16790 2898330 ) ( 1794230 * )
-      NEW met2 ( 1794230 2289900 ) ( 1794920 * 0 )
-      NEW met2 ( 1794230 2289900 ) ( * 2898330 )
-      NEW met2 ( 16790 2899860 ) M2M3_PR_M
-      NEW met1 ( 16790 2898330 ) M1M2_PR
-      NEW met1 ( 1794230 2898330 ) M1M2_PR ;
-    - io_in[27] ( PIN io_in[27] ) ( mprj io_in[27] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2639420 0 ) ( 17250 * )
-      NEW met2 ( 17250 2635850 ) ( * 2639420 )
-      NEW met1 ( 17250 2635850 ) ( 1814930 * )
-      NEW met2 ( 1816310 2289900 ) ( 1818380 * 0 )
-      NEW met2 ( 1814930 2401200 ) ( 1816310 * )
-      NEW met2 ( 1816310 2289900 ) ( * 2401200 )
-      NEW met2 ( 1814930 2401200 ) ( * 2635850 )
-      NEW met2 ( 17250 2639420 ) M2M3_PR_M
-      NEW met1 ( 17250 2635850 ) M1M2_PR
-      NEW met1 ( 1814930 2635850 ) M1M2_PR ;
-    - io_in[28] ( PIN io_in[28] ) ( mprj io_in[28] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2378300 0 ) ( 17250 * )
-      NEW met2 ( 17250 2373710 ) ( * 2378300 )
-      NEW met2 ( 1840230 2289900 ) ( 1842300 * 0 )
-      NEW met2 ( 1840230 2289900 ) ( * 2373710 )
-      NEW met1 ( 17250 2373710 ) ( 1840230 * )
-      NEW met2 ( 17250 2378300 ) M2M3_PR_M
-      NEW met1 ( 17250 2373710 ) M1M2_PR
-      NEW met1 ( 1840230 2373710 ) M1M2_PR ;
-    - io_in[29] ( PIN io_in[29] ) ( mprj io_in[29] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2117860 0 ) ( 17250 * )
-      NEW met2 ( 17250 2117860 ) ( * 2291090 )
-      NEW met2 ( 1865760 2289900 0 ) ( * 2291090 )
-      NEW met1 ( 17250 2291090 ) ( 1865760 * )
-      NEW met2 ( 17250 2117860 ) M2M3_PR_M
-      NEW met1 ( 17250 2291090 ) M1M2_PR
-      NEW met1 ( 1865760 2291090 ) M1M2_PR ;
-    - io_in[2] ( PIN io_in[2] ) ( mprj io_in[2] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 428060 ) ( * 430100 )
-      NEW met3 ( 2916860 430100 ) ( 2917780 * )
-      NEW met3 ( 2916860 430100 ) ( * 430780 )
-      NEW met3 ( 2916860 430780 ) ( 2917780 * 0 )
-      NEW met3 ( 1227510 2286500 ) ( 1227740 * )
-      NEW met2 ( 1226360 2286500 0 ) ( 1227510 * )
-      NEW met4 ( 1227740 428060 ) ( * 2286500 )
-      NEW met3 ( 1227740 428060 ) ( 2917780 * )
-      NEW met3 ( 1227740 428060 ) M3M4_PR_M
-      NEW met3 ( 1227740 2286500 ) M3M4_PR_M
-      NEW met2 ( 1227510 2286500 ) M2M3_PR_M
-      NEW met3 ( 1227740 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_in[30] ( PIN io_in[30] ) ( mprj io_in[30] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1856740 0 ) ( 14030 * )
-      NEW met2 ( 14030 1856740 ) ( * 1857250 )
-      NEW met1 ( 14030 1857250 ) ( 24150 * )
-      NEW met2 ( 24150 1857250 ) ( * 2283950 )
-      NEW li1 ( 1888070 2283950 ) ( * 2287350 )
-      NEW met2 ( 1888070 2287180 ) ( * 2287350 )
-      NEW met2 ( 1888070 2287180 ) ( 1889680 * 0 )
-      NEW met1 ( 24150 2283950 ) ( 1888070 * )
+      NEW met2 ( 1900710 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1900490 3394220 ) ( 1900710 * )
+      NEW met2 ( 1900490 3394220 ) ( * 3404930 )
+      NEW met1 ( 1821830 3404930 ) ( 1900490 * )
+      NEW met1 ( 1821830 3404930 ) M1M2_PR
+      NEW met1 ( 1900490 3404930 ) M1M2_PR ;
+    - io_in[19] ( PIN io_in[19] ) ( inst_eFPGA_CPU_top io_in[19] ) + USE SIGNAL
+      + ROUTED met2 ( 1570430 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1570210 3394220 ) ( 1570430 * )
+      NEW met2 ( 1570210 3394220 ) ( * 3404930 )
+      NEW met1 ( 1497530 3404930 ) ( 1570210 * )
+      NEW met2 ( 1497530 3517980 ) ( 1499830 * )
+      NEW met2 ( 1499830 3517300 ) ( * 3517980 )
+      NEW met2 ( 1499830 3517300 ) ( 1500750 * )
+      NEW met2 ( 1500750 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 1497530 3404930 ) ( * 3517980 )
+      NEW met1 ( 1570210 3404930 ) M1M2_PR
+      NEW met1 ( 1497530 3404930 ) M1M2_PR ;
+    - io_in[1] ( PIN io_in[1] ) ( inst_eFPGA_CPU_top io_in[1] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 380460 ) ( 2908810 * )
+      NEW met3 ( 2903980 380240 ) ( * 380460 )
+      NEW met3 ( 2901220 380240 0 ) ( 2903980 * )
+      NEW met3 ( 2908810 231540 ) ( 2917780 * 0 )
+      NEW met2 ( 2908810 231540 ) ( * 380460 )
+      NEW met2 ( 2908810 380460 ) M2M3_PR_M
+      NEW met2 ( 2908810 231540 ) M2M3_PR_M ;
+    - io_in[20] ( PIN io_in[20] ) ( inst_eFPGA_CPU_top io_in[20] ) + USE SIGNAL
+      + ROUTED met2 ( 1173230 3517980 ) ( 1175070 * )
+      NEW met2 ( 1175070 3517300 ) ( * 3517980 )
+      NEW met2 ( 1175070 3517300 ) ( 1175990 * )
+      NEW met2 ( 1175990 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 1173230 3404930 ) ( * 3517980 )
+      NEW met2 ( 1240610 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1240390 3394220 ) ( 1240610 * )
+      NEW met2 ( 1240390 3394220 ) ( * 3404930 )
+      NEW met1 ( 1173230 3404930 ) ( 1240390 * )
+      NEW met1 ( 1173230 3404930 ) M1M2_PR
+      NEW met1 ( 1240390 3404930 ) M1M2_PR ;
+    - io_in[21] ( PIN io_in[21] ) ( inst_eFPGA_CPU_top io_in[21] ) + USE SIGNAL
+      + ROUTED met2 ( 910330 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 910110 3394220 ) ( 910330 * )
+      NEW met2 ( 910110 3394220 ) ( * 3404930 )
+      NEW met1 ( 848930 3404930 ) ( 910110 * )
+      NEW met2 ( 848930 3404930 ) ( * 3512100 )
+      NEW met2 ( 848930 3512100 ) ( 851690 * )
+      NEW met2 ( 851690 3512100 ) ( * 3517980 0 )
+      NEW met1 ( 848930 3404930 ) M1M2_PR
+      NEW met1 ( 910110 3404930 ) M1M2_PR ;
+    - io_in[22] ( PIN io_in[22] ) ( inst_eFPGA_CPU_top io_in[22] ) + USE SIGNAL
+      + ROUTED met2 ( 580050 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 579830 3394220 ) ( 580050 * )
+      NEW met2 ( 579830 3394220 ) ( * 3404930 )
+      NEW met1 ( 524630 3404930 ) ( 579830 * )
+      NEW met2 ( 524630 3517980 ) ( 526470 * )
+      NEW met2 ( 526470 3517300 ) ( * 3517980 )
+      NEW met2 ( 526470 3517300 ) ( 527390 * )
+      NEW met2 ( 527390 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 524630 3404930 ) ( * 3517980 )
+      NEW met1 ( 579830 3404930 ) M1M2_PR
+      NEW met1 ( 524630 3404930 ) M1M2_PR ;
+    - io_in[23] ( PIN io_in[23] ) ( inst_eFPGA_CPU_top io_in[23] ) + USE SIGNAL
+      + ROUTED met2 ( 200330 3517980 ) ( 201710 * )
+      NEW met2 ( 201710 3517300 ) ( * 3517980 )
+      NEW met2 ( 201710 3517300 ) ( 202630 * )
+      NEW met2 ( 202630 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 200330 3404930 ) ( * 3517980 )
+      NEW met2 ( 250230 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 250010 3394220 ) ( 250230 * )
+      NEW met2 ( 250010 3394220 ) ( * 3404930 )
+      NEW met1 ( 200330 3404930 ) ( 250010 * )
+      NEW met1 ( 200330 3404930 ) M1M2_PR
+      NEW met1 ( 250010 3404930 ) M1M2_PR ;
+    - io_in[24] ( PIN io_in[24] ) ( inst_eFPGA_CPU_top io_in[24] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 3227110 ) ( 20240 * 0 )
+      NEW met3 ( 17020 3226940 ) ( * 3227110 )
+      NEW met3 ( 230 3226940 ) ( 17020 * )
+      NEW met3 ( 230 3418700 ) ( 460 * )
+      NEW met3 ( 460 3418700 ) ( * 3420740 )
+      NEW met3 ( 460 3420740 ) ( 3220 * )
+      NEW met3 ( 3220 3420740 ) ( * 3421420 )
+      NEW met3 ( 1380 3421420 0 ) ( 3220 * )
+      NEW met2 ( 230 3226940 ) ( * 3418700 )
+      NEW met2 ( 230 3226940 ) M2M3_PR_M
+      NEW met2 ( 230 3418700 ) M2M3_PR_M ;
+    - io_in[25] ( PIN io_in[25] ) ( inst_eFPGA_CPU_top io_in[25] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 2991040 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2990980 ) ( * 2991040 )
+      NEW met3 ( 230 2990980 ) ( 17020 * )
+      NEW met1 ( 230 3160470 ) ( 2990 * )
+      NEW met2 ( 2990 3160300 ) ( * 3160470 )
+      NEW met3 ( 1380 3160300 0 ) ( 2990 * )
+      NEW met2 ( 230 2990980 ) ( * 3160470 )
+      NEW met2 ( 230 2990980 ) M2M3_PR_M
+      NEW met1 ( 230 3160470 ) M1M2_PR
+      NEW met1 ( 2990 3160470 ) M1M2_PR
+      NEW met2 ( 2990 3160300 ) M2M3_PR_M ;
+    - io_in[26] ( PIN io_in[26] ) ( inst_eFPGA_CPU_top io_in[26] ) + USE SIGNAL
+      + ROUTED met3 ( 690 2898500 ) ( 1380 * )
+      NEW met3 ( 1380 2898500 ) ( * 2899180 )
+      NEW met3 ( 1380 2899180 ) ( 3220 * )
+      NEW met3 ( 3220 2899180 ) ( * 2899860 )
+      NEW met3 ( 1380 2899860 0 ) ( 3220 * )
+      NEW met3 ( 17020 2754970 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2754970 ) ( * 2755020 )
+      NEW met3 ( 690 2755020 ) ( 17020 * )
+      NEW met2 ( 690 2755020 ) ( * 2898500 )
+      NEW met2 ( 690 2898500 ) M2M3_PR_M
+      NEW met2 ( 690 2755020 ) M2M3_PR_M ;
+    - io_in[27] ( PIN io_in[27] ) ( inst_eFPGA_CPU_top io_in[27] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 2519510 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2519510 ) ( * 2519740 )
+      NEW met3 ( 690 2519740 ) ( 17020 * )
+      NEW met3 ( 690 2636700 ) ( 1380 * )
+      NEW met3 ( 1380 2636700 ) ( * 2638740 )
+      NEW met3 ( 1380 2638740 ) ( 3220 * )
+      NEW met3 ( 3220 2638740 ) ( * 2639420 )
+      NEW met3 ( 1380 2639420 0 ) ( 3220 * )
+      NEW met2 ( 690 2519740 ) ( * 2636700 )
+      NEW met2 ( 690 2519740 ) M2M3_PR_M
+      NEW met2 ( 690 2636700 ) M2M3_PR_M ;
+    - io_in[28] ( PIN io_in[28] ) ( inst_eFPGA_CPU_top io_in[28] ) + USE SIGNAL
+      + ROUTED met3 ( 18860 2283440 ) ( 20240 * 0 )
+      NEW met3 ( 18860 2283440 ) ( * 2283780 )
+      NEW met3 ( 690 2283780 ) ( 18860 * )
+      NEW met3 ( 690 2375580 ) ( 1380 * )
+      NEW met3 ( 1380 2375580 ) ( * 2377620 )
+      NEW met3 ( 1380 2377620 ) ( 3220 * )
+      NEW met3 ( 3220 2377620 ) ( * 2378300 )
+      NEW met3 ( 1380 2378300 0 ) ( 3220 * )
+      NEW met2 ( 690 2283780 ) ( * 2375580 )
+      NEW met2 ( 690 2283780 ) M2M3_PR_M
+      NEW met2 ( 690 2375580 ) M2M3_PR_M ;
+    - io_in[29] ( PIN io_in[29] ) ( inst_eFPGA_CPU_top io_in[29] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 2047370 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2047140 ) ( * 2047370 )
+      NEW met3 ( 14030 2047140 ) ( 17020 * )
+      NEW met3 ( 1380 2117860 0 ) ( 14030 * )
+      NEW met2 ( 14030 2047140 ) ( * 2117860 )
+      NEW met2 ( 14030 2047140 ) M2M3_PR_M
+      NEW met2 ( 14030 2117860 ) M2M3_PR_M ;
+    - io_in[2] ( PIN io_in[2] ) ( inst_eFPGA_CPU_top io_in[2] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 599420 ) ( 2908810 * )
+      NEW met3 ( 2903980 599420 ) ( * 599840 )
+      NEW met3 ( 2901220 599840 0 ) ( 2903980 * )
+      NEW met3 ( 2908810 430780 ) ( 2917780 * 0 )
+      NEW met2 ( 2908810 430780 ) ( * 599420 )
+      NEW met2 ( 2908810 599420 ) M2M3_PR_M
+      NEW met2 ( 2908810 430780 ) M2M3_PR_M ;
+    - io_in[30] ( PIN io_in[30] ) ( inst_eFPGA_CPU_top io_in[30] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 1856740 0 ) ( 14030 * )
+      NEW met3 ( 17020 1811300 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1811180 ) ( * 1811300 )
+      NEW met3 ( 14030 1811180 ) ( 17020 * )
+      NEW met2 ( 14030 1811180 ) ( * 1856740 )
       NEW met2 ( 14030 1856740 ) M2M3_PR_M
-      NEW met1 ( 14030 1857250 ) M1M2_PR
-      NEW met1 ( 24150 1857250 ) M1M2_PR
-      NEW met1 ( 24150 2283950 ) M1M2_PR
-      NEW li1 ( 1888070 2283950 ) L1M1_PR_MR
-      NEW li1 ( 1888070 2287350 ) L1M1_PR_MR
-      NEW met1 ( 1888070 2287350 ) M1M2_PR
-      NEW met1 ( 1888070 2287350 ) RECT ( -355 -70 0 70 )  ;
-    - io_in[31] ( PIN io_in[31] ) ( mprj io_in[31] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1596300 0 ) ( 15870 * )
-      NEW met2 ( 15870 1596300 ) ( * 1600550 )
-      NEW met2 ( 1156210 1600550 ) ( * 2294490 )
-      NEW met1 ( 15870 1600550 ) ( 1156210 * )
-      NEW met2 ( 1911530 2289900 ) ( 1913140 * 0 )
-      NEW met2 ( 1911530 2289900 ) ( * 2294490 )
-      NEW met1 ( 1156210 2294490 ) ( 1911530 * )
-      NEW met2 ( 15870 1596300 ) M2M3_PR_M
-      NEW met1 ( 15870 1600550 ) M1M2_PR
-      NEW met1 ( 1156210 1600550 ) M1M2_PR
-      NEW met1 ( 1156210 2294490 ) M1M2_PR
-      NEW met1 ( 1911530 2294490 ) M1M2_PR ;
-    - io_in[32] ( PIN io_in[32] ) ( mprj io_in[32] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1335860 0 ) ( 17710 * )
-      NEW met2 ( 17710 1335860 ) ( * 1338410 )
-      NEW met2 ( 1163110 1338410 ) ( * 2286670 )
-      NEW met2 ( 1935450 2286500 ) ( * 2286670 )
-      NEW met2 ( 1935450 2286500 ) ( 1937060 * 0 )
-      NEW met1 ( 17710 1338410 ) ( 1163110 * )
-      NEW met1 ( 1163110 2286670 ) ( 1935450 * )
-      NEW met2 ( 17710 1335860 ) M2M3_PR_M
-      NEW met1 ( 17710 1338410 ) M1M2_PR
-      NEW met1 ( 1163110 1338410 ) M1M2_PR
-      NEW met1 ( 1163110 2286670 ) M1M2_PR
-      NEW met1 ( 1935450 2286670 ) M1M2_PR ;
-    - io_in[33] ( PIN io_in[33] ) ( mprj io_in[33] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1074740 0 ) ( 16790 * )
-      NEW met2 ( 16790 1074740 ) ( * 1076270 )
-      NEW met2 ( 1170010 1076270 ) ( * 2293470 )
-      NEW met2 ( 1959830 2289900 ) ( 1960520 * 0 )
-      NEW met2 ( 1959830 2289900 ) ( * 2293470 )
-      NEW met1 ( 16790 1076270 ) ( 1170010 * )
-      NEW met1 ( 1170010 2293470 ) ( 1959830 * )
-      NEW met2 ( 16790 1074740 ) M2M3_PR_M
-      NEW met1 ( 16790 1076270 ) M1M2_PR
-      NEW met1 ( 1170010 1076270 ) M1M2_PR
-      NEW met1 ( 1170010 2293470 ) M1M2_PR
-      NEW met1 ( 1959830 2293470 ) M1M2_PR ;
-    - io_in[34] ( PIN io_in[34] ) ( mprj io_in[34] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 814300 0 ) ( 16330 * )
-      NEW met2 ( 16330 814300 ) ( * 820930 )
-      NEW met1 ( 16330 820930 ) ( 1135050 * )
-      NEW met2 ( 1135050 820930 ) ( * 2285990 )
-      NEW met1 ( 1966500 2285990 ) ( * 2286670 )
-      NEW met1 ( 1966500 2286670 ) ( 1982830 * )
-      NEW met2 ( 1982830 2286500 ) ( * 2286670 )
-      NEW met2 ( 1982830 2286500 ) ( 1984440 * 0 )
-      NEW met1 ( 1135050 2285990 ) ( 1966500 * )
-      NEW met2 ( 16330 814300 ) M2M3_PR_M
-      NEW met1 ( 16330 820930 ) M1M2_PR
-      NEW met1 ( 1135050 820930 ) M1M2_PR
-      NEW met1 ( 1135050 2285990 ) M1M2_PR
-      NEW met1 ( 1982830 2286670 ) M1M2_PR ;
-    - io_in[35] ( PIN io_in[35] ) ( mprj io_in[35] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 553180 0 ) ( 17250 * )
-      NEW met2 ( 17250 553180 ) ( * 558790 )
-      NEW met1 ( 17250 558790 ) ( 1141950 * )
-      NEW met2 ( 1141950 558790 ) ( * 2292450 )
-      NEW met2 ( 2006290 2289900 ) ( 2007900 * 0 )
-      NEW met2 ( 2006290 2289900 ) ( * 2292450 )
-      NEW met1 ( 1141950 2292450 ) ( 2006290 * )
-      NEW met2 ( 17250 553180 ) M2M3_PR_M
-      NEW met1 ( 17250 558790 ) M1M2_PR
-      NEW met1 ( 1141950 558790 ) M1M2_PR
-      NEW met1 ( 1141950 2292450 ) M1M2_PR
-      NEW met1 ( 2006290 2292450 ) M1M2_PR ;
-    - io_in[36] ( PIN io_in[36] ) ( mprj io_in[36] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 358020 0 ) ( 17250 * )
-      NEW met2 ( 17250 358020 ) ( * 358530 )
-      NEW li1 ( 2015030 2285310 ) ( * 2287350 )
-      NEW met1 ( 2015030 2287350 ) ( 2030210 * )
-      NEW met2 ( 2030210 2287180 ) ( * 2287350 )
-      NEW met2 ( 2030210 2287180 ) ( 2031820 * 0 )
-      NEW met1 ( 17250 358530 ) ( 1100550 * )
-      NEW met2 ( 1100550 358530 ) ( * 2285310 )
-      NEW met1 ( 1100550 2285310 ) ( 2015030 * )
-      NEW met2 ( 17250 358020 ) M2M3_PR_M
-      NEW met1 ( 17250 358530 ) M1M2_PR
-      NEW li1 ( 2015030 2285310 ) L1M1_PR_MR
-      NEW li1 ( 2015030 2287350 ) L1M1_PR_MR
-      NEW met1 ( 2030210 2287350 ) M1M2_PR
-      NEW met1 ( 1100550 358530 ) M1M2_PR
-      NEW met1 ( 1100550 2285310 ) M1M2_PR ;
-    - io_in[37] ( PIN io_in[37] ) ( mprj io_in[37] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 162180 0 ) ( 16790 * )
-      NEW met2 ( 16790 162180 ) ( * 165580 )
-      NEW met3 ( 2049300 2286500 ) ( 2053670 * )
-      NEW met2 ( 2053670 2286500 ) ( 2055280 * 0 )
-      NEW met4 ( 2049300 165580 ) ( * 2286500 )
-      NEW met3 ( 16790 165580 ) ( 2049300 * )
-      NEW met2 ( 16790 162180 ) M2M3_PR_M
-      NEW met2 ( 16790 165580 ) M2M3_PR_M
-      NEW met3 ( 2049300 165580 ) M3M4_PR_M
-      NEW met3 ( 2049300 2286500 ) M3M4_PR_M
-      NEW met2 ( 2053670 2286500 ) M2M3_PR_M ;
-    - io_in[3] ( PIN io_in[3] ) ( mprj io_in[3] ) + USE SIGNAL
-      + ROUTED met3 ( 1251430 2286500 ) ( 1255340 * )
-      NEW met2 ( 1249820 2286500 0 ) ( 1251430 * )
-      NEW met4 ( 1255340 627980 ) ( * 2286500 )
-      NEW met3 ( 2917780 627980 ) ( * 629340 )
-      NEW met3 ( 2916860 629340 ) ( 2917780 * )
-      NEW met3 ( 2916860 629340 ) ( * 630020 )
-      NEW met3 ( 2916860 630020 ) ( 2917780 * 0 )
-      NEW met3 ( 1255340 627980 ) ( 2917780 * )
-      NEW met3 ( 1255340 627980 ) M3M4_PR_M
-      NEW met3 ( 1255340 2286500 ) M3M4_PR_M
-      NEW met2 ( 1251430 2286500 ) M2M3_PR_M ;
-    - io_in[4] ( PIN io_in[4] ) ( mprj io_in[4] ) + USE SIGNAL
-      + ROUTED met2 ( 1273740 2289900 0 ) ( 1275350 * )
-      NEW met2 ( 1275350 2289900 ) ( * 2297890 )
-      NEW met3 ( 2901450 829260 ) ( 2917780 * 0 )
-      NEW met2 ( 2901450 829260 ) ( * 2294150 )
-      NEW met2 ( 1301110 2294150 ) ( * 2297890 )
-      NEW met1 ( 1275350 2297890 ) ( 1301110 * )
-      NEW met1 ( 1301110 2294150 ) ( 2901450 * )
-      NEW met1 ( 1275350 2297890 ) M1M2_PR
-      NEW met2 ( 2901450 829260 ) M2M3_PR_M
-      NEW met1 ( 2901450 2294150 ) M1M2_PR
-      NEW met1 ( 1301110 2297890 ) M1M2_PR
-      NEW met1 ( 1301110 2294150 ) M1M2_PR ;
-    - io_in[5] ( PIN io_in[5] ) ( mprj io_in[5] ) + USE SIGNAL
-      + ROUTED met3 ( 1296510 2286500 ) ( 1296740 * )
-      NEW met2 ( 1296510 2286500 ) ( 1297200 * 0 )
-      NEW met4 ( 1296740 1028500 ) ( * 2286500 )
-      NEW met3 ( 1296740 1028500 ) ( 2917780 * 0 )
-      NEW met3 ( 1296740 1028500 ) M3M4_PR_M
-      NEW met3 ( 1296740 2286500 ) M3M4_PR_M
-      NEW met2 ( 1296510 2286500 ) M2M3_PR_M
-      NEW met3 ( 1296740 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_in[6] ( PIN io_in[6] ) ( mprj io_in[6] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 1221620 ) ( * 1227060 )
-      NEW met3 ( 2916860 1227060 ) ( 2917780 * )
-      NEW met3 ( 2916860 1227060 ) ( * 1227740 )
-      NEW met3 ( 2916860 1227740 ) ( 2917780 * 0 )
-      NEW met3 ( 1322730 2286500 ) ( 1323420 * )
-      NEW met2 ( 1321120 2286500 0 ) ( 1322730 * )
-      NEW met4 ( 1323420 1221620 ) ( * 2286500 )
-      NEW met3 ( 1323420 1221620 ) ( 2917780 * )
-      NEW met3 ( 1323420 1221620 ) M3M4_PR_M
-      NEW met3 ( 1323420 2286500 ) M3M4_PR_M
-      NEW met2 ( 1322730 2286500 ) M2M3_PR_M ;
-    - io_in[7] ( PIN io_in[7] ) ( mprj io_in[7] ) + USE SIGNAL
-      + ROUTED met3 ( 1344580 2286500 ) ( 1345270 * )
-      NEW met2 ( 1344580 2286500 0 ) ( 1345270 * )
-      NEW met4 ( 1344580 1490900 ) ( * 2286500 )
-      NEW met3 ( 2917780 1490900 ) ( * 1492940 )
-      NEW met3 ( 2916860 1492940 ) ( 2917780 * )
-      NEW met3 ( 2916860 1492940 ) ( * 1493620 )
-      NEW met3 ( 2916860 1493620 ) ( 2917780 * 0 )
-      NEW met3 ( 1344580 1490900 ) ( 2917780 * )
-      NEW met3 ( 1344580 1490900 ) M3M4_PR_M
-      NEW met3 ( 1344580 2286500 ) M3M4_PR_M
-      NEW met2 ( 1345270 2286500 ) M2M3_PR_M ;
-    - io_in[8] ( PIN io_in[8] ) ( mprj io_in[8] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 1759500 ) ( * 1766130 )
-      NEW met3 ( 2900990 1759500 ) ( 2917780 * 0 )
-      NEW met2 ( 1368500 2289900 0 ) ( 1370110 * )
-      NEW met2 ( 1370110 2289900 ) ( * 2294830 )
-      NEW met1 ( 2094150 1766130 ) ( 2900990 * )
-      NEW met2 ( 2094150 1766130 ) ( * 2294830 )
-      NEW met1 ( 1370110 2294830 ) ( 2094150 * )
-      NEW met1 ( 2900990 1766130 ) M1M2_PR
-      NEW met2 ( 2900990 1759500 ) M2M3_PR_M
-      NEW met1 ( 1370110 2294830 ) M1M2_PR
-      NEW met1 ( 2094150 1766130 ) M1M2_PR
-      NEW met1 ( 2094150 2294830 ) M1M2_PR ;
-    - io_in[9] ( PIN io_in[9] ) ( mprj io_in[9] ) + USE SIGNAL
-      + ROUTED met2 ( 2898230 2024700 ) ( * 2028270 )
-      NEW met3 ( 2898230 2024700 ) ( 2917780 * 0 )
-      NEW met1 ( 2107950 2028270 ) ( 2898230 * )
-      NEW met2 ( 1393570 2287860 ) ( * 2288030 )
-      NEW met2 ( 1391960 2287860 0 ) ( 1393570 * )
-      NEW met2 ( 2107950 2028270 ) ( * 2287690 )
-      NEW met1 ( 1393570 2288030 ) ( 1414500 * )
-      NEW met1 ( 1414500 2287690 ) ( * 2288030 )
-      NEW met1 ( 1414500 2287690 ) ( 2107950 * )
-      NEW met1 ( 2898230 2028270 ) M1M2_PR
-      NEW met2 ( 2898230 2024700 ) M2M3_PR_M
-      NEW met1 ( 2107950 2028270 ) M1M2_PR
-      NEW met1 ( 1393570 2288030 ) M1M2_PR
-      NEW met1 ( 2107950 2287690 ) M1M2_PR ;
-    - io_oeb[0] ( PIN io_oeb[0] ) ( mprj io_oeb[0] ) + USE SIGNAL
-      + ROUTED met3 ( 1186110 2286500 ) ( 1186340 * )
-      NEW met2 ( 1186110 2286500 ) ( 1186800 * 0 )
-      NEW met4 ( 1186340 158780 ) ( * 2286500 )
-      NEW met3 ( 2917780 158780 ) ( * 164900 )
-      NEW met3 ( 2916860 164900 ) ( 2917780 * )
-      NEW met3 ( 2916860 164900 ) ( * 165580 )
-      NEW met3 ( 2916860 165580 ) ( 2917780 * 0 )
-      NEW met3 ( 1186340 158780 ) ( 2917780 * )
-      NEW met3 ( 1186340 158780 ) M3M4_PR_M
-      NEW met3 ( 1186340 2286500 ) M3M4_PR_M
-      NEW met2 ( 1186110 2286500 ) M2M3_PR_M
-      NEW met3 ( 1186340 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_oeb[10] ( PIN io_oeb[10] ) ( mprj io_oeb[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2421990 ) ( * 2423180 )
-      NEW met3 ( 2900990 2423180 ) ( 2917780 * 0 )
-      NEW met1 ( 1428070 2421990 ) ( 2900990 * )
-      NEW met2 ( 1423700 2289900 0 ) ( 1425310 * )
-      NEW met2 ( 1425310 2289900 ) ( * 2304010 )
-      NEW met1 ( 1425310 2304010 ) ( 1428070 * )
-      NEW met2 ( 1428070 2304010 ) ( * 2421990 )
-      NEW met1 ( 2900990 2421990 ) M1M2_PR
-      NEW met2 ( 2900990 2423180 ) M2M3_PR_M
-      NEW met1 ( 1428070 2421990 ) M1M2_PR
-      NEW met1 ( 1425310 2304010 ) M1M2_PR
-      NEW met1 ( 1428070 2304010 ) M1M2_PR ;
-    - io_oeb[11] ( PIN io_oeb[11] ) ( mprj io_oeb[11] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2684130 ) ( * 2689060 )
-      NEW met3 ( 2900990 2689060 ) ( 2917780 * 0 )
-      NEW met1 ( 1448770 2684130 ) ( 2900990 * )
-      NEW met2 ( 1447160 2289900 0 ) ( 1448770 * )
-      NEW met2 ( 1448770 2289900 ) ( * 2684130 )
-      NEW met1 ( 1448770 2684130 ) M1M2_PR
-      NEW met1 ( 2900990 2684130 ) M1M2_PR
-      NEW met2 ( 2900990 2689060 ) M2M3_PR_M ;
-    - io_oeb[12] ( PIN io_oeb[12] ) ( mprj io_oeb[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1471080 2289900 0 ) ( 1472690 * )
-      NEW met2 ( 1472690 2289900 ) ( * 2297890 )
-      NEW met1 ( 1472690 2297890 ) ( 1476370 * )
-      NEW met2 ( 1476370 2297890 ) ( * 2953410 )
-      NEW met2 ( 2899150 2953410 ) ( * 2954940 )
-      NEW met3 ( 2899150 2954940 ) ( 2917780 * 0 )
-      NEW met1 ( 1476370 2953410 ) ( 2899150 * )
-      NEW met1 ( 1472690 2297890 ) M1M2_PR
-      NEW met1 ( 1476370 2297890 ) M1M2_PR
-      NEW met1 ( 1476370 2953410 ) M1M2_PR
-      NEW met1 ( 2899150 2953410 ) M1M2_PR
-      NEW met2 ( 2899150 2954940 ) M2M3_PR_M ;
-    - io_oeb[13] ( PIN io_oeb[13] ) ( mprj io_oeb[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3215550 ) ( * 3220140 )
-      NEW met3 ( 2900990 3220140 ) ( 2917780 * 0 )
-      NEW met1 ( 1497070 3215550 ) ( 2900990 * )
-      NEW met2 ( 1494540 2289900 0 ) ( 1496610 * )
-      NEW met2 ( 1496610 2289900 ) ( * 2304600 )
-      NEW met2 ( 1496610 2304600 ) ( 1497070 * )
-      NEW met2 ( 1497070 2304600 ) ( * 3215550 )
-      NEW met1 ( 2900990 3215550 ) M1M2_PR
-      NEW met2 ( 2900990 3220140 ) M2M3_PR_M
-      NEW met1 ( 1497070 3215550 ) M1M2_PR ;
-    - io_oeb[14] ( PIN io_oeb[14] ) ( mprj io_oeb[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3484830 ) ( * 3486020 )
-      NEW met3 ( 2900990 3486020 ) ( 2917780 * 0 )
-      NEW met1 ( 1524670 3484830 ) ( 2900990 * )
-      NEW met2 ( 1518460 2289900 0 ) ( 1520070 * )
-      NEW met2 ( 1520070 2289900 ) ( * 2297890 )
-      NEW met1 ( 1520070 2297890 ) ( 1524670 * )
-      NEW met2 ( 1524670 2297890 ) ( * 3484830 )
-      NEW met1 ( 2900990 3484830 ) M1M2_PR
-      NEW met2 ( 2900990 3486020 ) M2M3_PR_M
-      NEW met1 ( 1524670 3484830 ) M1M2_PR
-      NEW met1 ( 1520070 2297890 ) M1M2_PR
-      NEW met1 ( 1524670 2297890 ) M1M2_PR ;
-    - io_oeb[15] ( PIN io_oeb[15] ) ( mprj io_oeb[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1541920 2289900 0 ) ( 1543990 * )
-      NEW met2 ( 1543990 2289900 ) ( * 2304600 )
-      NEW met2 ( 1543990 2304600 ) ( 1545370 * )
-      NEW met2 ( 1545370 2304600 ) ( * 3503530 )
-      NEW met2 ( 2636030 3503530 ) ( * 3517980 0 )
-      NEW met1 ( 1545370 3503530 ) ( 2636030 * )
-      NEW met1 ( 1545370 3503530 ) M1M2_PR
-      NEW met1 ( 2636030 3503530 ) M1M2_PR ;
-    - io_oeb[16] ( PIN io_oeb[16] ) ( mprj io_oeb[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1565840 2289900 0 ) ( * 2291260 )
-      NEW met2 ( 1565840 2291260 ) ( 1566070 * )
-      NEW met2 ( 1566070 2291260 ) ( * 3504890 )
-      NEW met2 ( 2311730 3504890 ) ( * 3517980 0 )
-      NEW met1 ( 1566070 3504890 ) ( 2311730 * )
-      NEW met1 ( 1566070 3504890 ) M1M2_PR
-      NEW met1 ( 2311730 3504890 ) M1M2_PR ;
-    - io_oeb[17] ( PIN io_oeb[17] ) ( mprj io_oeb[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1593670 3500130 ) ( 1987430 * )
-      NEW met2 ( 1589300 2289900 0 ) ( 1589990 * )
-      NEW met2 ( 1589990 2289900 ) ( * 2297890 )
-      NEW met1 ( 1589990 2297890 ) ( 1593670 * )
-      NEW met2 ( 1593670 2297890 ) ( * 3500130 )
-      NEW met2 ( 1987430 3500130 ) ( * 3517980 0 )
-      NEW met1 ( 1593670 3500130 ) M1M2_PR
-      NEW met1 ( 1987430 3500130 ) M1M2_PR
-      NEW met1 ( 1589990 2297890 ) M1M2_PR
-      NEW met1 ( 1593670 2297890 ) M1M2_PR ;
-    - io_oeb[18] ( PIN io_oeb[18] ) ( mprj io_oeb[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1662670 3498770 ) ( * 3517980 0 )
-      NEW met1 ( 1614370 3498770 ) ( 1662670 * )
-      NEW met2 ( 1613220 2289900 0 ) ( 1614370 * )
-      NEW met2 ( 1614370 2289900 ) ( * 3498770 )
-      NEW met1 ( 1662670 3498770 ) M1M2_PR
-      NEW met1 ( 1614370 3498770 ) M1M2_PR ;
-    - io_oeb[19] ( PIN io_oeb[19] ) ( mprj io_oeb[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1635530 2289900 ) ( 1636680 * 0 )
-      NEW met2 ( 1635530 2289900 ) ( * 3499790 )
-      NEW met1 ( 1338370 3499790 ) ( 1635530 * )
-      NEW met2 ( 1338370 3499790 ) ( * 3517980 0 )
-      NEW met1 ( 1635530 3499790 ) M1M2_PR
-      NEW met1 ( 1338370 3499790 ) M1M2_PR ;
-    - io_oeb[1] ( PIN io_oeb[1] ) ( mprj io_oeb[1] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 359380 ) ( * 364140 )
-      NEW met3 ( 2916860 364140 ) ( 2917780 * )
-      NEW met3 ( 2916860 364140 ) ( * 364820 )
-      NEW met3 ( 2916860 364820 ) ( 2917780 * 0 )
-      NEW met3 ( 1211870 2286500 ) ( 1213940 * )
-      NEW met2 ( 1210260 2286500 0 ) ( 1211870 * )
-      NEW met4 ( 1213940 359380 ) ( * 2286500 )
-      NEW met3 ( 1213940 359380 ) ( 2917780 * )
-      NEW met3 ( 1213940 359380 ) M3M4_PR_M
-      NEW met3 ( 1213940 2286500 ) M3M4_PR_M
-      NEW met2 ( 1211870 2286500 ) M2M3_PR_M ;
-    - io_oeb[20] ( PIN io_oeb[20] ) ( mprj io_oeb[20] ) + USE SIGNAL
-      + ROUTED met2 ( 1658530 2289900 ) ( 1660600 * 0 )
-      NEW met2 ( 1656690 2401200 ) ( 1658530 * )
-      NEW met2 ( 1658530 2289900 ) ( * 2401200 )
-      NEW met2 ( 1656690 2401200 ) ( * 3501150 )
-      NEW met1 ( 1014070 3501150 ) ( 1656690 * )
-      NEW met2 ( 1014070 3501150 ) ( * 3517980 0 )
-      NEW met1 ( 1656690 3501150 ) M1M2_PR
-      NEW met1 ( 1014070 3501150 ) M1M2_PR ;
-    - io_oeb[21] ( PIN io_oeb[21] ) ( mprj io_oeb[21] ) + USE SIGNAL
-      + ROUTED met2 ( 689310 3503870 ) ( * 3517980 0 )
-      NEW met1 ( 689310 3503870 ) ( 1683830 * )
-      NEW met2 ( 1683830 2289900 ) ( 1684060 * 0 )
-      NEW met2 ( 1683830 2289900 ) ( * 3503870 )
-      NEW met1 ( 689310 3503870 ) M1M2_PR
-      NEW met1 ( 1683830 3503870 ) M1M2_PR ;
-    - io_oeb[22] ( PIN io_oeb[22] ) ( mprj io_oeb[22] ) + USE SIGNAL
-      + ROUTED met1 ( 365010 3502510 ) ( 1704530 * )
-      NEW met2 ( 365010 3502510 ) ( * 3517980 0 )
-      NEW met2 ( 1705910 2289900 ) ( 1707980 * 0 )
-      NEW met2 ( 1704530 2401200 ) ( 1705910 * )
-      NEW met2 ( 1705910 2289900 ) ( * 2401200 )
-      NEW met2 ( 1704530 2401200 ) ( * 3502510 )
-      NEW met1 ( 365010 3502510 ) M1M2_PR
-      NEW met1 ( 1704530 3502510 ) M1M2_PR ;
-    - io_oeb[23] ( PIN io_oeb[23] ) ( mprj io_oeb[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1729370 2289900 ) ( 1731440 * 0 )
-      NEW met2 ( 1725230 2401200 ) ( 1729370 * )
-      NEW met2 ( 1729370 2289900 ) ( * 2401200 )
-      NEW met2 ( 1725230 2401200 ) ( * 3501490 )
-      NEW met1 ( 40710 3501490 ) ( 1725230 * )
-      NEW met2 ( 40710 3501490 ) ( * 3517980 0 )
-      NEW met1 ( 1725230 3501490 ) M1M2_PR
-      NEW met1 ( 40710 3501490 ) M1M2_PR ;
-    - io_oeb[24] ( PIN io_oeb[24] ) ( mprj io_oeb[24] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3290860 0 ) ( 17250 * )
-      NEW met2 ( 17250 3284570 ) ( * 3290860 )
-      NEW met2 ( 1753290 2289900 ) ( 1755360 * 0 )
-      NEW met2 ( 1752830 2401200 ) ( 1753290 * )
-      NEW met2 ( 1753290 2289900 ) ( * 2401200 )
-      NEW met2 ( 1752830 2401200 ) ( * 3284570 )
-      NEW met1 ( 17250 3284570 ) ( 1752830 * )
-      NEW met2 ( 17250 3290860 ) M2M3_PR_M
-      NEW met1 ( 17250 3284570 ) M1M2_PR
-      NEW met1 ( 1752830 3284570 ) M1M2_PR ;
-    - io_oeb[25] ( PIN io_oeb[25] ) ( mprj io_oeb[25] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3030420 0 ) ( 16330 * )
-      NEW met2 ( 16330 3029230 ) ( * 3030420 )
-      NEW met2 ( 1776750 2289900 ) ( 1778820 * 0 )
-      NEW met2 ( 1773530 2401200 ) ( 1776750 * )
-      NEW met2 ( 1776750 2289900 ) ( * 2401200 )
-      NEW met1 ( 16330 3029230 ) ( 1773530 * )
-      NEW met2 ( 1773530 2401200 ) ( * 3029230 )
-      NEW met2 ( 16330 3030420 ) M2M3_PR_M
-      NEW met1 ( 16330 3029230 ) M1M2_PR
-      NEW met1 ( 1773530 3029230 ) M1M2_PR ;
-    - io_oeb[26] ( PIN io_oeb[26] ) ( mprj io_oeb[26] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2769300 0 ) ( 17250 * )
-      NEW met2 ( 17250 2767090 ) ( * 2769300 )
-      NEW met2 ( 1801130 2289900 ) ( 1802740 * 0 )
-      NEW met1 ( 17250 2767090 ) ( 1801130 * )
-      NEW met2 ( 1801130 2289900 ) ( * 2767090 )
-      NEW met2 ( 17250 2769300 ) M2M3_PR_M
-      NEW met1 ( 17250 2767090 ) M1M2_PR
-      NEW met1 ( 1801130 2767090 ) M1M2_PR ;
-    - io_oeb[27] ( PIN io_oeb[27] ) ( mprj io_oeb[27] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2508860 0 ) ( 15410 * )
-      NEW met2 ( 15410 2504950 ) ( * 2508860 )
-      NEW met2 ( 1824130 2289900 ) ( 1826200 * 0 )
-      NEW met2 ( 1822290 2401200 ) ( 1824130 * )
-      NEW met2 ( 1824130 2289900 ) ( * 2401200 )
-      NEW met2 ( 1822290 2401200 ) ( * 2504950 )
-      NEW met1 ( 15410 2504950 ) ( 1822290 * )
-      NEW met2 ( 15410 2508860 ) M2M3_PR_M
-      NEW met1 ( 15410 2504950 ) M1M2_PR
-      NEW met1 ( 1822290 2504950 ) M1M2_PR ;
-    - io_oeb[28] ( PIN io_oeb[28] ) ( mprj io_oeb[28] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2247740 0 ) ( 16790 * )
-      NEW met2 ( 16790 2247740 ) ( * 2249270 )
-      NEW met2 ( 1849430 2287180 ) ( * 2287350 )
-      NEW met2 ( 1849430 2287180 ) ( 1850120 * 0 )
-      NEW met1 ( 16790 2249270 ) ( 1121250 * )
-      NEW met2 ( 1121250 2249270 ) ( * 2287350 )
-      NEW met1 ( 1121250 2287350 ) ( 1849430 * )
-      NEW met2 ( 16790 2247740 ) M2M3_PR_M
-      NEW met1 ( 16790 2249270 ) M1M2_PR
-      NEW met1 ( 1849430 2287350 ) M1M2_PR
-      NEW met1 ( 1121250 2249270 ) M1M2_PR
-      NEW met1 ( 1121250 2287350 ) M1M2_PR ;
-    - io_oeb[29] ( PIN io_oeb[29] ) ( mprj io_oeb[29] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1987300 0 ) ( 16330 * )
-      NEW met2 ( 16330 1987300 ) ( * 1993930 )
-      NEW met1 ( 16330 1993930 ) ( 1114350 * )
-      NEW met2 ( 1114350 1993930 ) ( * 2293810 )
-      NEW met2 ( 1871970 2289900 ) ( 1873580 * 0 )
-      NEW met2 ( 1871970 2289900 ) ( * 2293810 )
-      NEW met1 ( 1114350 2293810 ) ( 1871970 * )
-      NEW met2 ( 16330 1987300 ) M2M3_PR_M
-      NEW met1 ( 16330 1993930 ) M1M2_PR
-      NEW met1 ( 1114350 1993930 ) M1M2_PR
-      NEW met1 ( 1114350 2293810 ) M1M2_PR
-      NEW met1 ( 1871970 2293810 ) M1M2_PR ;
-    - io_oeb[2] ( PIN io_oeb[2] ) ( mprj io_oeb[2] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 559300 ) ( * 563380 )
-      NEW met3 ( 2916860 563380 ) ( 2917780 * )
-      NEW met3 ( 2916860 563380 ) ( * 564060 )
-      NEW met3 ( 2916860 564060 ) ( 2917780 * 0 )
-      NEW met3 ( 1234180 2286500 ) ( 1234870 * )
-      NEW met2 ( 1234180 2286500 0 ) ( 1234870 * )
-      NEW met4 ( 1234180 559300 ) ( * 2286500 )
-      NEW met3 ( 1234180 559300 ) ( 2917780 * )
-      NEW met3 ( 1234180 559300 ) M3M4_PR_M
-      NEW met3 ( 1234180 2286500 ) M3M4_PR_M
-      NEW met2 ( 1234870 2286500 ) M2M3_PR_M ;
-    - io_oeb[30] ( PIN io_oeb[30] ) ( mprj io_oeb[30] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1726860 0 ) ( 15870 * )
-      NEW met2 ( 15870 1726860 ) ( * 1731790 )
-      NEW met2 ( 1079850 1731790 ) ( * 2286330 )
-      NEW met1 ( 15870 1731790 ) ( 1079850 * )
-      NEW li1 ( 1895890 2286330 ) ( * 2287350 )
-      NEW met2 ( 1895890 2287180 ) ( * 2287350 )
-      NEW met2 ( 1895890 2287180 ) ( 1897500 * 0 )
-      NEW met1 ( 1079850 2286330 ) ( 1895890 * )
-      NEW met2 ( 15870 1726860 ) M2M3_PR_M
-      NEW met1 ( 15870 1731790 ) M1M2_PR
-      NEW met1 ( 1079850 1731790 ) M1M2_PR
-      NEW met1 ( 1079850 2286330 ) M1M2_PR
-      NEW li1 ( 1895890 2286330 ) L1M1_PR_MR
-      NEW li1 ( 1895890 2287350 ) L1M1_PR_MR
-      NEW met1 ( 1895890 2287350 ) M1M2_PR
-      NEW met1 ( 1895890 2287350 ) RECT ( -355 -70 0 70 )  ;
-    - io_oeb[31] ( PIN io_oeb[31] ) ( mprj io_oeb[31] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1465740 0 ) ( 15410 * )
-      NEW met2 ( 15410 1465740 ) ( * 1469650 )
-      NEW met2 ( 1066510 1469650 ) ( * 2292790 )
-      NEW met2 ( 1919810 2289900 ) ( 1920960 * 0 )
-      NEW met2 ( 1919810 2289900 ) ( * 2292790 )
-      NEW met1 ( 15410 1469650 ) ( 1066510 * )
-      NEW met1 ( 1066510 2292790 ) ( 1919810 * )
-      NEW met2 ( 15410 1465740 ) M2M3_PR_M
-      NEW met1 ( 15410 1469650 ) M1M2_PR
-      NEW met1 ( 1066510 1469650 ) M1M2_PR
-      NEW met1 ( 1066510 2292790 ) M1M2_PR
-      NEW met1 ( 1919810 2292790 ) M1M2_PR ;
-    - io_oeb[32] ( PIN io_oeb[32] ) ( mprj io_oeb[32] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1205300 0 ) ( 17250 * )
-      NEW met2 ( 17250 1205300 ) ( * 1207170 )
-      NEW met2 ( 1073410 1207170 ) ( * 2285650 )
-      NEW li1 ( 1943270 2285650 ) ( * 2286670 )
-      NEW met2 ( 1943270 2286500 ) ( * 2286670 )
-      NEW met2 ( 1943270 2286500 ) ( 1944880 * 0 )
-      NEW met1 ( 17250 1207170 ) ( 1073410 * )
-      NEW met1 ( 1073410 2285650 ) ( 1943270 * )
-      NEW met2 ( 17250 1205300 ) M2M3_PR_M
-      NEW met1 ( 17250 1207170 ) M1M2_PR
-      NEW met1 ( 1073410 1207170 ) M1M2_PR
-      NEW met1 ( 1073410 2285650 ) M1M2_PR
-      NEW li1 ( 1943270 2285650 ) L1M1_PR_MR
-      NEW li1 ( 1943270 2286670 ) L1M1_PR_MR
-      NEW met1 ( 1943270 2286670 ) M1M2_PR
-      NEW met1 ( 1943270 2286670 ) RECT ( -355 -70 0 70 )  ;
-    - io_oeb[33] ( PIN io_oeb[33] ) ( mprj io_oeb[33] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 944180 0 ) ( 17250 * )
-      NEW met2 ( 17250 944180 ) ( * 945030 )
-      NEW met1 ( 17250 945030 ) ( 1024650 * )
-      NEW met2 ( 1024650 945030 ) ( * 2291770 )
-      NEW met2 ( 1967650 2289900 ) ( 1968340 * 0 )
-      NEW met2 ( 1967650 2289900 ) ( * 2291770 )
-      NEW met1 ( 1024650 2291770 ) ( 1967650 * )
-      NEW met2 ( 17250 944180 ) M2M3_PR_M
-      NEW met1 ( 17250 945030 ) M1M2_PR
-      NEW met1 ( 1024650 945030 ) M1M2_PR
-      NEW met1 ( 1024650 2291770 ) M1M2_PR
-      NEW met1 ( 1967650 2291770 ) M1M2_PR ;
-    - io_oeb[34] ( PIN io_oeb[34] ) ( mprj io_oeb[34] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 683740 0 ) ( 16330 * )
-      NEW met2 ( 16330 683740 ) ( * 689690 )
-      NEW met1 ( 16330 689690 ) ( 1045350 * )
-      NEW met2 ( 1045350 689690 ) ( * 2292110 )
-      NEW met2 ( 1990650 2289900 ) ( 1992260 * 0 )
-      NEW met2 ( 1990650 2289900 ) ( * 2292110 )
-      NEW met1 ( 1045350 2292110 ) ( 1990650 * )
-      NEW met2 ( 16330 683740 ) M2M3_PR_M
-      NEW met1 ( 16330 689690 ) M1M2_PR
-      NEW met1 ( 1045350 689690 ) M1M2_PR
-      NEW met1 ( 1045350 2292110 ) M1M2_PR
-      NEW met1 ( 1990650 2292110 ) M1M2_PR ;
-    - io_oeb[35] ( PIN io_oeb[35] ) ( mprj io_oeb[35] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 423300 0 ) ( 15870 * )
-      NEW met2 ( 15870 423300 ) ( * 427550 )
-      NEW li1 ( 2015490 2284630 ) ( * 2286670 )
-      NEW met1 ( 2015030 2286670 ) ( 2015490 * )
-      NEW met2 ( 2015030 2286500 ) ( * 2286670 )
-      NEW met2 ( 2015030 2286500 ) ( 2015720 * 0 )
-      NEW met1 ( 15870 427550 ) ( 1010850 * )
-      NEW met2 ( 1010850 427550 ) ( * 2284630 )
-      NEW met1 ( 1010850 2284630 ) ( 2015490 * )
-      NEW met2 ( 15870 423300 ) M2M3_PR_M
-      NEW met1 ( 15870 427550 ) M1M2_PR
-      NEW li1 ( 2015490 2284630 ) L1M1_PR_MR
-      NEW li1 ( 2015490 2286670 ) L1M1_PR_MR
-      NEW met1 ( 2015030 2286670 ) M1M2_PR
-      NEW met1 ( 1010850 427550 ) M1M2_PR
-      NEW met1 ( 1010850 2284630 ) M1M2_PR ;
-    - io_oeb[36] ( PIN io_oeb[36] ) ( mprj io_oeb[36] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 227460 0 ) ( 17250 * )
-      NEW met2 ( 17250 227460 ) ( * 227630 )
-      NEW met1 ( 2015950 2284970 ) ( * 2285310 )
-      NEW met1 ( 2015950 2285310 ) ( 2038030 * )
-      NEW met1 ( 2038030 2285310 ) ( * 2286670 )
-      NEW met2 ( 2038030 2286500 ) ( * 2286670 )
-      NEW met2 ( 2038030 2286500 ) ( 2039640 * 0 )
-      NEW met1 ( 17250 227630 ) ( 1031550 * )
-      NEW met2 ( 1031550 227630 ) ( * 2284970 )
-      NEW met1 ( 1031550 2284970 ) ( 2015950 * )
-      NEW met2 ( 17250 227460 ) M2M3_PR_M
-      NEW met1 ( 17250 227630 ) M1M2_PR
-      NEW met1 ( 2038030 2286670 ) M1M2_PR
-      NEW met1 ( 1031550 227630 ) M1M2_PR
-      NEW met1 ( 1031550 2284970 ) M1M2_PR ;
-    - io_oeb[37] ( PIN io_oeb[37] ) ( mprj io_oeb[37] ) + USE SIGNAL
-      + ROUTED met3 ( 2056660 2286500 ) ( 2061490 * )
-      NEW met4 ( 2056660 34340 ) ( * 2286500 )
-      NEW met3 ( 2300 32300 0 ) ( 34500 * )
-      NEW met3 ( 34500 32300 ) ( * 34340 )
-      NEW met3 ( 34500 34340 ) ( 2056660 * )
-      NEW met2 ( 2061490 2286500 ) ( 2063100 * 0 )
-      NEW met3 ( 2056660 34340 ) M3M4_PR_M
-      NEW met3 ( 2056660 2286500 ) M3M4_PR_M
-      NEW met2 ( 2061490 2286500 ) M2M3_PR_M ;
-    - io_oeb[3] ( PIN io_oeb[3] ) ( mprj io_oeb[3] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 759220 ) ( * 762620 )
-      NEW met3 ( 2916860 762620 ) ( 2917780 * )
-      NEW met3 ( 2916860 762620 ) ( * 763300 )
-      NEW met3 ( 2916860 763300 ) ( 2917780 * 0 )
-      NEW met3 ( 1259250 2286500 ) ( 1261780 * )
-      NEW met2 ( 1257640 2286500 0 ) ( 1259250 * )
-      NEW met4 ( 1261780 759220 ) ( * 2286500 )
-      NEW met3 ( 1261780 759220 ) ( 2917780 * )
-      NEW met3 ( 1261780 759220 ) M3M4_PR_M
-      NEW met3 ( 1261780 2286500 ) M3M4_PR_M
-      NEW met2 ( 1259250 2286500 ) M2M3_PR_M ;
-    - io_oeb[4] ( PIN io_oeb[4] ) ( mprj io_oeb[4] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 959140 ) ( * 961860 )
-      NEW met3 ( 2916860 961860 ) ( 2917780 * )
-      NEW met3 ( 2916860 961860 ) ( * 962540 )
-      NEW met3 ( 2916860 962540 ) ( 2917780 * 0 )
-      NEW met3 ( 1282710 2286500 ) ( 1282940 * )
-      NEW met2 ( 1281560 2286500 0 ) ( 1282710 * )
-      NEW met4 ( 1282940 959140 ) ( * 2286500 )
-      NEW met3 ( 1282940 959140 ) ( 2917780 * )
-      NEW met3 ( 1282940 959140 ) M3M4_PR_M
-      NEW met3 ( 1282940 2286500 ) M3M4_PR_M
-      NEW met2 ( 1282710 2286500 ) M2M3_PR_M
-      NEW met3 ( 1282940 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_oeb[5] ( PIN io_oeb[5] ) ( mprj io_oeb[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 1159740 ) ( * 1161100 )
-      NEW met3 ( 2916860 1161100 ) ( 2917780 * )
-      NEW met3 ( 2916860 1161100 ) ( * 1161780 )
-      NEW met3 ( 2916860 1161780 ) ( 2917780 * 0 )
-      NEW met3 ( 1310540 1159740 ) ( 2917780 * )
-      NEW met3 ( 1306630 2286500 ) ( 1310540 * )
-      NEW met2 ( 1305020 2286500 0 ) ( 1306630 * )
-      NEW met4 ( 1310540 1159740 ) ( * 2286500 )
-      NEW met3 ( 1310540 1159740 ) M3M4_PR_M
-      NEW met3 ( 1310540 2286500 ) M3M4_PR_M
-      NEW met2 ( 1306630 2286500 ) M2M3_PR_M ;
-    - io_oeb[6] ( PIN io_oeb[6] ) ( mprj io_oeb[6] ) + USE SIGNAL
-      + ROUTED met3 ( 1330780 1359660 ) ( 2835900 * )
-      NEW met3 ( 2835900 1359660 ) ( * 1361020 )
-      NEW met3 ( 2835900 1361020 ) ( 2917780 * 0 )
-      NEW met3 ( 1330550 2286500 ) ( 1330780 * )
-      NEW met2 ( 1328940 2286500 0 ) ( 1330550 * )
-      NEW met4 ( 1330780 1359660 ) ( * 2286500 )
-      NEW met3 ( 1330780 1359660 ) M3M4_PR_M
-      NEW met3 ( 1330780 2286500 ) M3M4_PR_M
-      NEW met2 ( 1330550 2286500 ) M2M3_PR_M
-      NEW met3 ( 1330780 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_oeb[7] ( PIN io_oeb[7] ) ( mprj io_oeb[7] ) + USE SIGNAL
-      + ROUTED met2 ( 1352170 2289900 ) ( 1352400 * 0 )
-      NEW met2 ( 1352170 2289900 ) ( * 2293130 )
-      NEW met2 ( 2142450 1628090 ) ( * 2293130 )
-      NEW met2 ( 2899610 1626220 ) ( * 1628090 )
-      NEW met3 ( 2899610 1626220 ) ( 2917780 * 0 )
-      NEW met1 ( 2142450 1628090 ) ( 2899610 * )
-      NEW met1 ( 1352170 2293130 ) ( 2142450 * )
-      NEW met1 ( 1352170 2293130 ) M1M2_PR
-      NEW met1 ( 2142450 1628090 ) M1M2_PR
-      NEW met1 ( 2142450 2293130 ) M1M2_PR
-      NEW met1 ( 2899610 1628090 ) M1M2_PR
-      NEW met2 ( 2899610 1626220 ) M2M3_PR_M ;
-    - io_oeb[8] ( PIN io_oeb[8] ) ( mprj io_oeb[8] ) + USE SIGNAL
-      + ROUTED met2 ( 1377930 2287010 ) ( * 2287180 )
-      NEW met2 ( 1376320 2287180 0 ) ( 1377930 * )
-      NEW met2 ( 2128650 1897370 ) ( * 2287010 )
-      NEW met2 ( 2900990 1892100 ) ( * 1897370 )
-      NEW met3 ( 2900990 1892100 ) ( 2917780 * 0 )
-      NEW met1 ( 2128650 1897370 ) ( 2900990 * )
-      NEW met1 ( 1377930 2287010 ) ( 2128650 * )
-      NEW met1 ( 1377930 2287010 ) M1M2_PR
-      NEW met1 ( 2128650 1897370 ) M1M2_PR
-      NEW met1 ( 2128650 2287010 ) M1M2_PR
-      NEW met1 ( 2900990 1897370 ) M1M2_PR
-      NEW met2 ( 2900990 1892100 ) M2M3_PR_M ;
-    - io_oeb[9] ( PIN io_oeb[9] ) ( mprj io_oeb[9] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2157980 ) ( * 2159510 )
-      NEW met3 ( 2900990 2157980 ) ( 2917780 * 0 )
-      NEW met1 ( 2087250 2159510 ) ( 2900990 * )
-      NEW met2 ( 1399780 2289900 0 ) ( 1400470 * )
-      NEW met2 ( 1400470 2289900 ) ( * 2302650 )
-      NEW met2 ( 2087250 2159510 ) ( * 2302650 )
-      NEW met1 ( 1400470 2302650 ) ( 2087250 * )
-      NEW met1 ( 2900990 2159510 ) M1M2_PR
-      NEW met2 ( 2900990 2157980 ) M2M3_PR_M
-      NEW met1 ( 2087250 2159510 ) M1M2_PR
-      NEW met1 ( 1400470 2302650 ) M1M2_PR
-      NEW met1 ( 2087250 2302650 ) M1M2_PR ;
-    - io_out[0] ( PIN io_out[0] ) ( mprj io_out[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2912030 98940 ) ( * 99110 )
-      NEW met3 ( 2912030 98940 ) ( 2917780 * 0 )
-      NEW li1 ( 2912030 99110 ) ( * 2291430 )
-      NEW met2 ( 1194620 2289900 0 ) ( 1196230 * )
-      NEW met2 ( 1196230 2289900 ) ( * 2291430 )
-      NEW met1 ( 1196230 2291430 ) ( 2912030 * )
-      NEW li1 ( 2912030 99110 ) L1M1_PR_MR
-      NEW met1 ( 2912030 99110 ) M1M2_PR
-      NEW met2 ( 2912030 98940 ) M2M3_PR_M
-      NEW li1 ( 2912030 2291430 ) L1M1_PR_MR
-      NEW met1 ( 1196230 2291430 ) M1M2_PR
-      NEW met1 ( 2912030 99110 ) RECT ( -355 -70 0 70 )  ;
-    - io_out[10] ( PIN io_out[10] ) ( mprj io_out[10] ) + USE SIGNAL
-      + ROUTED met2 ( 2900070 2352970 ) ( * 2357220 )
-      NEW met3 ( 2900070 2357220 ) ( 2917780 * 0 )
-      NEW met1 ( 1434970 2352970 ) ( 2900070 * )
-      NEW met2 ( 1434970 2332200 ) ( * 2352970 )
-      NEW met2 ( 1431520 2289900 0 ) ( 1433590 * )
-      NEW met2 ( 1433590 2289900 ) ( * 2332200 )
-      NEW met2 ( 1433590 2332200 ) ( 1434970 * )
-      NEW met1 ( 2900070 2352970 ) M1M2_PR
-      NEW met2 ( 2900070 2357220 ) M2M3_PR_M
-      NEW met1 ( 1434970 2352970 ) M1M2_PR ;
-    - io_out[11] ( PIN io_out[11] ) ( mprj io_out[11] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2622250 ) ( * 2622420 )
-      NEW met3 ( 2900990 2622420 ) ( 2917780 * 0 )
-      NEW met1 ( 1455670 2622250 ) ( 2900990 * )
-      NEW met2 ( 1454980 2289900 0 ) ( 1455670 * )
-      NEW met2 ( 1455670 2289900 ) ( * 2622250 )
-      NEW met1 ( 1455670 2622250 ) M1M2_PR
-      NEW met1 ( 2900990 2622250 ) M1M2_PR
-      NEW met2 ( 2900990 2622420 ) M2M3_PR_M ;
-    - io_out[12] ( PIN io_out[12] ) ( mprj io_out[12] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2884390 ) ( * 2888300 )
-      NEW met3 ( 2900990 2888300 ) ( 2917780 * 0 )
-      NEW met2 ( 1478900 2289900 0 ) ( 1480510 * )
-      NEW met2 ( 1480510 2289900 ) ( * 2297890 )
-      NEW met1 ( 1480510 2297890 ) ( 1483270 * )
-      NEW met2 ( 1483270 2297890 ) ( * 2884390 )
-      NEW met1 ( 1483270 2884390 ) ( 2900990 * )
-      NEW met1 ( 1483270 2884390 ) M1M2_PR
-      NEW met1 ( 2900990 2884390 ) M1M2_PR
-      NEW met2 ( 2900990 2888300 ) M2M3_PR_M
-      NEW met1 ( 1480510 2297890 ) M1M2_PR
-      NEW met1 ( 1483270 2297890 ) M1M2_PR ;
-    - io_out[13] ( PIN io_out[13] ) ( mprj io_out[13] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3153330 ) ( * 3154180 )
-      NEW met3 ( 2900990 3154180 ) ( 2917780 * 0 )
-      NEW met2 ( 1502360 2289900 0 ) ( 1503510 * )
-      NEW met2 ( 1503510 2289900 ) ( * 3153330 )
-      NEW met1 ( 1503510 3153330 ) ( 2900990 * )
-      NEW met1 ( 2900990 3153330 ) M1M2_PR
-      NEW met2 ( 2900990 3154180 ) M2M3_PR_M
-      NEW met1 ( 1503510 3153330 ) M1M2_PR ;
-    - io_out[14] ( PIN io_out[14] ) ( mprj io_out[14] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 3416150 ) ( * 3419380 )
-      NEW met3 ( 2900990 3419380 ) ( 2917780 * 0 )
-      NEW met2 ( 1526280 2289900 0 ) ( 1527890 * )
-      NEW met2 ( 1527890 2289900 ) ( * 2297890 )
-      NEW met1 ( 1527890 2297890 ) ( 1531570 * )
-      NEW met2 ( 1531570 2297890 ) ( * 3416150 )
-      NEW met1 ( 1531570 3416150 ) ( 2900990 * )
-      NEW met1 ( 2900990 3416150 ) M1M2_PR
-      NEW met2 ( 2900990 3419380 ) M2M3_PR_M
-      NEW met1 ( 1527890 2297890 ) M1M2_PR
-      NEW met1 ( 1531570 2297890 ) M1M2_PR
-      NEW met1 ( 1531570 3416150 ) M1M2_PR ;
-    - io_out[15] ( PIN io_out[15] ) ( mprj io_out[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1549740 2289900 0 ) ( 1551810 * )
-      NEW met2 ( 1551810 2289900 ) ( * 2304600 )
-      NEW met2 ( 1551810 2304600 ) ( 1552270 * )
-      NEW met2 ( 1552270 2304600 ) ( * 3503190 )
-      NEW met2 ( 2717450 3503190 ) ( * 3517980 0 )
-      NEW met1 ( 1552270 3503190 ) ( 2717450 * )
-      NEW met1 ( 1552270 3503190 ) M1M2_PR
-      NEW met1 ( 2717450 3503190 ) M1M2_PR ;
-    - io_out[16] ( PIN io_out[16] ) ( mprj io_out[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1573660 2289900 0 ) ( 1575270 * )
-      NEW met2 ( 1575270 2289900 ) ( * 2297890 )
-      NEW met1 ( 1575270 2297890 ) ( 1579870 * )
-      NEW met2 ( 1579870 2297890 ) ( * 3504550 )
-      NEW met1 ( 1579870 3504550 ) ( 2392690 * )
-      NEW met2 ( 2392690 3504550 ) ( * 3517980 0 )
-      NEW met1 ( 1579870 3504550 ) M1M2_PR
-      NEW met1 ( 1575270 2297890 ) M1M2_PR
-      NEW met1 ( 1579870 2297890 ) M1M2_PR
-      NEW met1 ( 2392690 3504550 ) M1M2_PR ;
-    - io_out[17] ( PIN io_out[17] ) ( mprj io_out[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1600570 3500470 ) ( 2068390 * )
-      NEW met2 ( 1597120 2289900 0 ) ( 1599190 * )
-      NEW met2 ( 1599190 2289900 ) ( * 2304600 )
-      NEW met2 ( 1599190 2304600 ) ( 1600570 * )
-      NEW met2 ( 1600570 2304600 ) ( * 3500470 )
-      NEW met2 ( 2068390 3500470 ) ( * 3517980 0 )
-      NEW met1 ( 1600570 3500470 ) M1M2_PR
-      NEW met1 ( 2068390 3500470 ) M1M2_PR ;
-    - io_out[18] ( PIN io_out[18] ) ( mprj io_out[18] ) + USE SIGNAL
-      + ROUTED met2 ( 1744090 3499110 ) ( * 3517980 0 )
-      NEW met1 ( 1621270 3499110 ) ( 1744090 * )
-      NEW met2 ( 1621040 2289900 0 ) ( * 2291260 )
-      NEW met2 ( 1621040 2291260 ) ( 1621270 * )
-      NEW met2 ( 1621270 2291260 ) ( * 3499110 )
-      NEW met1 ( 1744090 3499110 ) M1M2_PR
-      NEW met1 ( 1621270 3499110 ) M1M2_PR ;
-    - io_out[19] ( PIN io_out[19] ) ( mprj io_out[19] ) + USE SIGNAL
-      + ROUTED met2 ( 1642430 2289900 ) ( 1644500 * 0 )
-      NEW met2 ( 1642430 2289900 ) ( * 3499450 )
-      NEW met1 ( 1419330 3499450 ) ( 1642430 * )
-      NEW met2 ( 1419330 3499450 ) ( * 3517980 0 )
-      NEW met1 ( 1642430 3499450 ) M1M2_PR
-      NEW met1 ( 1419330 3499450 ) M1M2_PR ;
-    - io_out[1] ( PIN io_out[1] ) ( mprj io_out[1] ) + USE SIGNAL
-      + ROUTED met3 ( 1220380 296820 ) ( 2835900 * )
-      NEW met3 ( 2835900 296820 ) ( * 298180 )
-      NEW met3 ( 2835900 298180 ) ( 2917780 * 0 )
-      NEW met3 ( 1219690 2286500 ) ( 1220380 * )
-      NEW met2 ( 1218080 2286500 0 ) ( 1219690 * )
-      NEW met4 ( 1220380 296820 ) ( * 2286500 )
-      NEW met3 ( 1220380 296820 ) M3M4_PR_M
-      NEW met3 ( 1220380 2286500 ) M3M4_PR_M
-      NEW met2 ( 1219690 2286500 ) M2M3_PR_M ;
-    - io_out[20] ( PIN io_out[20] ) ( mprj io_out[20] ) + USE SIGNAL
-      + ROUTED met2 ( 1095030 3500810 ) ( * 3517980 0 )
-      NEW met2 ( 1666350 2289900 ) ( 1668420 * 0 )
-      NEW met2 ( 1663130 2401200 ) ( 1666350 * )
-      NEW met2 ( 1666350 2289900 ) ( * 2401200 )
-      NEW met2 ( 1663130 2401200 ) ( * 3500810 )
-      NEW met1 ( 1095030 3500810 ) ( 1663130 * )
-      NEW met1 ( 1095030 3500810 ) M1M2_PR
-      NEW met1 ( 1663130 3500810 ) M1M2_PR ;
-    - io_out[21] ( PIN io_out[21] ) ( mprj io_out[21] ) + USE SIGNAL
-      + ROUTED met2 ( 770730 3504210 ) ( * 3517980 0 )
-      NEW met1 ( 770730 3504210 ) ( 1690730 * )
-      NEW met2 ( 1690730 2289900 ) ( 1691880 * 0 )
-      NEW met2 ( 1690730 2289900 ) ( * 3504210 )
-      NEW met1 ( 770730 3504210 ) M1M2_PR
-      NEW met1 ( 1690730 3504210 ) M1M2_PR ;
-    - io_out[22] ( PIN io_out[22] ) ( mprj io_out[22] ) + USE SIGNAL
-      + ROUTED met1 ( 445970 3502850 ) ( 1711430 * )
-      NEW met2 ( 445970 3502850 ) ( * 3517980 0 )
-      NEW met2 ( 1713730 2289900 ) ( 1715800 * 0 )
-      NEW met2 ( 1711430 2401200 ) ( 1713730 * )
-      NEW met2 ( 1713730 2289900 ) ( * 2401200 )
-      NEW met2 ( 1711430 2401200 ) ( * 3502850 )
-      NEW met1 ( 445970 3502850 ) M1M2_PR
-      NEW met1 ( 1711430 3502850 ) M1M2_PR ;
-    - io_out[23] ( PIN io_out[23] ) ( mprj io_out[23] ) + USE SIGNAL
-      + ROUTED met2 ( 121670 3501830 ) ( * 3517980 0 )
-      NEW met2 ( 1739260 2289900 0 ) ( * 2291260 )
-      NEW met2 ( 1739260 2291260 ) ( 1739490 * )
-      NEW met2 ( 1739490 2291260 ) ( * 3501830 )
-      NEW met1 ( 121670 3501830 ) ( 1739490 * )
-      NEW met1 ( 121670 3501830 ) M1M2_PR
-      NEW met1 ( 1739490 3501830 ) M1M2_PR ;
-    - io_out[24] ( PIN io_out[24] ) ( mprj io_out[24] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3356140 0 ) ( 17710 * )
-      NEW met2 ( 17710 3353590 ) ( * 3356140 )
-      NEW met2 ( 1761110 2289900 ) ( 1763180 * 0 )
-      NEW met2 ( 1759730 2401200 ) ( 1761110 * )
-      NEW met2 ( 1761110 2289900 ) ( * 2401200 )
-      NEW met2 ( 1759730 2401200 ) ( * 3353590 )
-      NEW met1 ( 17710 3353590 ) ( 1759730 * )
-      NEW met2 ( 17710 3356140 ) M2M3_PR_M
-      NEW met1 ( 17710 3353590 ) M1M2_PR
-      NEW met1 ( 1759730 3353590 ) M1M2_PR ;
-    - io_out[25] ( PIN io_out[25] ) ( mprj io_out[25] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 3095700 0 ) ( 15870 * )
-      NEW met2 ( 15870 3091450 ) ( * 3095700 )
-      NEW met1 ( 15870 3091450 ) ( 1780430 * )
-      NEW met2 ( 1784570 2289900 ) ( 1786640 * 0 )
-      NEW met2 ( 1780430 2401200 ) ( 1784570 * )
-      NEW met2 ( 1784570 2289900 ) ( * 2401200 )
-      NEW met2 ( 1780430 2401200 ) ( * 3091450 )
-      NEW met2 ( 15870 3095700 ) M2M3_PR_M
-      NEW met1 ( 15870 3091450 ) M1M2_PR
-      NEW met1 ( 1780430 3091450 ) M1M2_PR ;
-    - io_out[26] ( PIN io_out[26] ) ( mprj io_out[26] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2834580 0 ) ( 17250 * )
-      NEW met2 ( 17250 2829310 ) ( * 2834580 )
-      NEW met1 ( 17250 2829310 ) ( 1808030 * )
-      NEW met2 ( 1808490 2289900 ) ( 1810560 * 0 )
-      NEW met2 ( 1808030 2401200 ) ( 1808490 * )
-      NEW met2 ( 1808490 2289900 ) ( * 2401200 )
-      NEW met2 ( 1808030 2401200 ) ( * 2829310 )
-      NEW met2 ( 17250 2834580 ) M2M3_PR_M
-      NEW met1 ( 17250 2829310 ) M1M2_PR
-      NEW met1 ( 1808030 2829310 ) M1M2_PR ;
-    - io_out[27] ( PIN io_out[27] ) ( mprj io_out[27] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2574140 0 ) ( 17250 * )
-      NEW met2 ( 17250 2573970 ) ( * 2574140 )
-      NEW met2 ( 1831950 2289900 ) ( 1834020 * 0 )
-      NEW met2 ( 1828730 2401200 ) ( 1831950 * )
-      NEW met2 ( 1831950 2289900 ) ( * 2401200 )
-      NEW met2 ( 1828730 2401200 ) ( * 2573970 )
-      NEW met1 ( 17250 2573970 ) ( 1828730 * )
-      NEW met2 ( 17250 2574140 ) M2M3_PR_M
-      NEW met1 ( 17250 2573970 ) M1M2_PR
-      NEW met1 ( 1828730 2573970 ) M1M2_PR ;
-    - io_out[28] ( PIN io_out[28] ) ( mprj io_out[28] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2313020 0 ) ( 16330 * )
-      NEW met2 ( 16330 2311830 ) ( * 2313020 )
-      NEW met2 ( 1856330 2289900 ) ( 1857940 * 0 )
-      NEW met2 ( 1856330 2289900 ) ( * 2311830 )
-      NEW met1 ( 16330 2311830 ) ( 1856330 * )
-      NEW met2 ( 16330 2313020 ) M2M3_PR_M
-      NEW met1 ( 16330 2311830 ) M1M2_PR
-      NEW met1 ( 1856330 2311830 ) M1M2_PR ;
-    - io_out[29] ( PIN io_out[29] ) ( mprj io_out[29] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 2052580 0 ) ( 17250 * )
-      NEW met2 ( 17250 2052580 ) ( * 2056150 )
-      NEW met2 ( 293250 2056150 ) ( * 2299930 )
-      NEW met1 ( 17250 2056150 ) ( 293250 * )
-      NEW met2 ( 1879790 2289900 ) ( 1881400 * 0 )
-      NEW met2 ( 1879790 2289900 ) ( * 2299930 )
-      NEW met1 ( 293250 2299930 ) ( 1879790 * )
-      NEW met2 ( 17250 2052580 ) M2M3_PR_M
-      NEW met1 ( 17250 2056150 ) M1M2_PR
-      NEW met1 ( 293250 2056150 ) M1M2_PR
-      NEW met1 ( 293250 2299930 ) M1M2_PR
-      NEW met1 ( 1879790 2299930 ) M1M2_PR ;
-    - io_out[2] ( PIN io_out[2] ) ( mprj io_out[2] ) + USE SIGNAL
-      + ROUTED met3 ( 1241540 497420 ) ( 2917780 * 0 )
-      NEW met3 ( 1241310 2286500 ) ( 1241540 * )
-      NEW met2 ( 1241310 2286500 ) ( 1242000 * 0 )
-      NEW met4 ( 1241540 497420 ) ( * 2286500 )
-      NEW met3 ( 1241540 497420 ) M3M4_PR_M
-      NEW met3 ( 1241540 2286500 ) M3M4_PR_M
-      NEW met2 ( 1241310 2286500 ) M2M3_PR_M
-      NEW met3 ( 1241540 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_out[30] ( PIN io_out[30] ) ( mprj io_out[30] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1792140 0 ) ( 16790 * )
-      NEW met2 ( 16790 1792140 ) ( * 1793670 )
-      NEW met2 ( 307050 1793670 ) ( * 2298910 )
-      NEW met1 ( 16790 1793670 ) ( 307050 * )
-      NEW met2 ( 1904630 2289900 ) ( 1905320 * 0 )
-      NEW met2 ( 1904630 2289900 ) ( * 2298910 )
-      NEW met1 ( 307050 2298910 ) ( 1904630 * )
-      NEW met2 ( 16790 1792140 ) M2M3_PR_M
-      NEW met1 ( 16790 1793670 ) M1M2_PR
-      NEW met1 ( 307050 1793670 ) M1M2_PR
-      NEW met1 ( 307050 2298910 ) M1M2_PR
-      NEW met1 ( 1904630 2298910 ) M1M2_PR ;
-    - io_out[31] ( PIN io_out[31] ) ( mprj io_out[31] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1531020 0 ) ( 17250 * )
-      NEW met2 ( 17250 1531020 ) ( * 1531530 )
-      NEW met2 ( 1927170 2289900 ) ( 1928780 * 0 )
-      NEW met2 ( 1927170 2289900 ) ( * 2298570 )
-      NEW met1 ( 17250 1531530 ) ( 327750 * )
-      NEW met2 ( 327750 1531530 ) ( * 2298570 )
-      NEW met1 ( 327750 2298570 ) ( 1927170 * )
-      NEW met2 ( 17250 1531020 ) M2M3_PR_M
-      NEW met1 ( 17250 1531530 ) M1M2_PR
-      NEW met1 ( 1927170 2298570 ) M1M2_PR
-      NEW met1 ( 327750 1531530 ) M1M2_PR
-      NEW met1 ( 327750 2298570 ) M1M2_PR ;
-    - io_out[32] ( PIN io_out[32] ) ( mprj io_out[32] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1270580 0 ) ( 17250 * )
-      NEW met2 ( 17250 1270580 ) ( * 1276190 )
-      NEW met2 ( 1951090 2289900 ) ( 1952700 * 0 )
-      NEW met2 ( 1951090 2289900 ) ( * 2299590 )
-      NEW met1 ( 17250 1276190 ) ( 355350 * )
-      NEW met2 ( 355350 1276190 ) ( * 2299590 )
-      NEW met1 ( 355350 2299590 ) ( 1951090 * )
-      NEW met2 ( 17250 1270580 ) M2M3_PR_M
-      NEW met1 ( 17250 1276190 ) M1M2_PR
-      NEW met1 ( 1951090 2299590 ) M1M2_PR
-      NEW met1 ( 355350 1276190 ) M1M2_PR
-      NEW met1 ( 355350 2299590 ) M1M2_PR ;
-    - io_out[33] ( PIN io_out[33] ) ( mprj io_out[33] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 1009460 0 ) ( 17250 * )
-      NEW met2 ( 17250 1009460 ) ( * 1014050 )
-      NEW met1 ( 17250 1014050 ) ( 362250 * )
-      NEW met2 ( 362250 1014050 ) ( * 2304350 )
-      NEW met2 ( 1974550 2289900 ) ( 1976160 * 0 )
-      NEW met2 ( 1974550 2289900 ) ( * 2304350 )
-      NEW met1 ( 362250 2304350 ) ( 1974550 * )
-      NEW met2 ( 17250 1009460 ) M2M3_PR_M
-      NEW met1 ( 17250 1014050 ) M1M2_PR
-      NEW met1 ( 362250 1014050 ) M1M2_PR
-      NEW met1 ( 362250 2304350 ) M1M2_PR
-      NEW met1 ( 1974550 2304350 ) M1M2_PR ;
-    - io_out[34] ( PIN io_out[34] ) ( mprj io_out[34] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 749020 0 ) ( 17250 * )
-      NEW met2 ( 17250 749020 ) ( * 751910 )
-      NEW met2 ( 396750 751910 ) ( * 2299250 )
-      NEW met1 ( 17250 751910 ) ( 396750 * )
-      NEW met2 ( 1998470 2289900 ) ( 2000080 * 0 )
-      NEW met2 ( 1998470 2289900 ) ( * 2299250 )
-      NEW met1 ( 396750 2299250 ) ( 1998470 * )
-      NEW met2 ( 17250 749020 ) M2M3_PR_M
-      NEW met1 ( 17250 751910 ) M1M2_PR
-      NEW met1 ( 396750 751910 ) M1M2_PR
-      NEW met1 ( 396750 2299250 ) M1M2_PR
-      NEW met1 ( 1998470 2299250 ) M1M2_PR ;
-    - io_out[35] ( PIN io_out[35] ) ( mprj io_out[35] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 487900 0 ) ( 17250 * )
-      NEW met2 ( 17250 487900 ) ( * 489770 )
-      NEW met2 ( 417450 489770 ) ( * 2298230 )
-      NEW met2 ( 2021930 2289900 ) ( 2023540 * 0 )
-      NEW met2 ( 2021930 2289900 ) ( * 2298230 )
-      NEW met1 ( 17250 489770 ) ( 417450 * )
-      NEW met1 ( 417450 2298230 ) ( 2021930 * )
-      NEW met2 ( 17250 487900 ) M2M3_PR_M
-      NEW met1 ( 17250 489770 ) M1M2_PR
-      NEW met1 ( 417450 489770 ) M1M2_PR
-      NEW met1 ( 417450 2298230 ) M1M2_PR
-      NEW met1 ( 2021930 2298230 ) M1M2_PR ;
-    - io_out[36] ( PIN io_out[36] ) ( mprj io_out[36] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 292740 0 ) ( 16790 * )
-      NEW met2 ( 16790 292740 ) ( * 296140 )
-      NEW met3 ( 2043780 2286500 ) ( 2045850 * )
-      NEW met2 ( 2045850 2286500 ) ( 2047460 * 0 )
-      NEW met4 ( 2043780 296140 ) ( * 2286500 )
-      NEW met3 ( 16790 296140 ) ( 2043780 * )
-      NEW met2 ( 16790 292740 ) M2M3_PR_M
-      NEW met2 ( 16790 296140 ) M2M3_PR_M
-      NEW met3 ( 2043780 296140 ) M3M4_PR_M
-      NEW met3 ( 2043780 2286500 ) M3M4_PR_M
-      NEW met2 ( 2045850 2286500 ) M2M3_PR_M ;
-    - io_out[37] ( PIN io_out[37] ) ( mprj io_out[37] ) + USE SIGNAL
-      + ROUTED met3 ( 2300 96900 0 ) ( 17250 * )
-      NEW met2 ( 17250 96900 ) ( * 103190 )
-      NEW met1 ( 17250 103190 ) ( 2074830 * )
-      NEW met2 ( 2070920 2286500 0 ) ( 2074830 * )
-      NEW met2 ( 2074830 103190 ) ( * 2286500 )
-      NEW met2 ( 17250 96900 ) M2M3_PR_M
-      NEW met1 ( 17250 103190 ) M1M2_PR
-      NEW met1 ( 2074830 103190 ) M1M2_PR ;
-    - io_out[3] ( PIN io_out[3] ) ( mprj io_out[3] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 690540 ) ( * 695980 )
-      NEW met3 ( 2916860 695980 ) ( 2917780 * )
-      NEW met3 ( 2916860 695980 ) ( * 696660 )
-      NEW met3 ( 2916860 696660 ) ( 2917780 * 0 )
-      NEW met3 ( 1267070 2286500 ) ( 1268220 * )
-      NEW met2 ( 1265460 2286500 0 ) ( 1267070 * )
-      NEW met4 ( 1268220 690540 ) ( * 2286500 )
-      NEW met3 ( 1268220 690540 ) ( 2917780 * )
-      NEW met3 ( 1268220 690540 ) M3M4_PR_M
-      NEW met3 ( 1268220 2286500 ) M3M4_PR_M
-      NEW met2 ( 1267070 2286500 ) M2M3_PR_M ;
-    - io_out[4] ( PIN io_out[4] ) ( mprj io_out[4] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 890460 ) ( * 895220 )
-      NEW met3 ( 2916860 895220 ) ( 2917780 * )
-      NEW met3 ( 2916860 895220 ) ( * 895900 )
-      NEW met3 ( 2916860 895900 ) ( 2917780 * 0 )
-      NEW met3 ( 1286620 2286500 ) ( 1287770 * )
-      NEW met2 ( 1287770 2286500 ) ( 1289380 * 0 )
-      NEW met4 ( 1286620 890460 ) ( * 2286500 )
-      NEW met3 ( 1286620 890460 ) ( 2917780 * )
-      NEW met3 ( 1286620 890460 ) M3M4_PR_M
-      NEW met3 ( 1286620 2286500 ) M3M4_PR_M
-      NEW met2 ( 1287770 2286500 ) M2M3_PR_M ;
-    - io_out[5] ( PIN io_out[5] ) ( mprj io_out[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2917780 1090380 ) ( * 1094460 )
-      NEW met3 ( 2916860 1094460 ) ( 2917780 * )
-      NEW met3 ( 2916860 1094460 ) ( * 1095140 )
-      NEW met3 ( 2916860 1095140 ) ( 2917780 * 0 )
-      NEW met3 ( 1316980 1090380 ) ( 2917780 * )
-      NEW met3 ( 1314450 2286500 ) ( 1316980 * )
-      NEW met2 ( 1312840 2286500 0 ) ( 1314450 * )
-      NEW met4 ( 1316980 1090380 ) ( * 2286500 )
-      NEW met3 ( 1316980 1090380 ) M3M4_PR_M
-      NEW met3 ( 1316980 2286500 ) M3M4_PR_M
-      NEW met2 ( 1314450 2286500 ) M2M3_PR_M ;
-    - io_out[6] ( PIN io_out[6] ) ( mprj io_out[6] ) + USE SIGNAL
-      + ROUTED met3 ( 1339060 1289620 ) ( * 1290300 )
-      NEW met3 ( 2916860 1293700 ) ( 2917780 * )
-      NEW met3 ( 2916860 1293700 ) ( * 1294380 )
-      NEW met3 ( 2916860 1294380 ) ( 2917780 * 0 )
-      NEW met3 ( 2917780 1289620 ) ( * 1293700 )
-      NEW met3 ( 1339060 1289620 ) ( 2917780 * )
-      NEW met3 ( 1338140 1290300 ) ( 1339060 * )
-      NEW met3 ( 1337910 2286500 ) ( 1338140 * )
-      NEW met2 ( 1336760 2286500 0 ) ( 1337910 * )
-      NEW met4 ( 1338140 1290300 ) ( * 2286500 )
-      NEW met3 ( 1338140 1290300 ) M3M4_PR_M
-      NEW met3 ( 1338140 2286500 ) M3M4_PR_M
-      NEW met2 ( 1337910 2286500 ) M2M3_PR_M
-      NEW met3 ( 1338140 2286500 ) RECT ( 0 -150 390 150 )  ;
-    - io_out[7] ( PIN io_out[7] ) ( mprj io_out[7] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 1560260 ) ( * 1566210 )
-      NEW met3 ( 2900990 1560260 ) ( 2917780 * 0 )
-      NEW met2 ( 1360220 2289900 0 ) ( 1361830 * )
-      NEW met2 ( 1361830 2289900 ) ( * 2300270 )
-      NEW met2 ( 2156250 1566210 ) ( * 2300270 )
-      NEW met1 ( 2156250 1566210 ) ( 2900990 * )
-      NEW met1 ( 1361830 2300270 ) ( 2156250 * )
-      NEW met1 ( 2156250 1566210 ) M1M2_PR
-      NEW met1 ( 2900990 1566210 ) M1M2_PR
-      NEW met2 ( 2900990 1560260 ) M2M3_PR_M
-      NEW met1 ( 1361830 2300270 ) M1M2_PR
-      NEW met1 ( 2156250 2300270 ) M1M2_PR ;
-    - io_out[8] ( PIN io_out[8] ) ( mprj io_out[8] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 1825460 ) ( * 1828350 )
-      NEW met3 ( 2900990 1825460 ) ( 2917780 * 0 )
-      NEW met2 ( 1384140 2289900 0 ) ( 1385290 * )
-      NEW met2 ( 1385290 2289900 ) ( * 2300610 )
-      NEW met1 ( 2163150 1828350 ) ( 2900990 * )
-      NEW met2 ( 2163150 1828350 ) ( * 2300610 )
-      NEW met1 ( 1385290 2300610 ) ( 2163150 * )
-      NEW met1 ( 2900990 1828350 ) M1M2_PR
-      NEW met2 ( 2900990 1825460 ) M2M3_PR_M
-      NEW met1 ( 1385290 2300610 ) M1M2_PR
-      NEW met1 ( 2163150 1828350 ) M1M2_PR
-      NEW met1 ( 2163150 2300610 ) M1M2_PR ;
-    - io_out[9] ( PIN io_out[9] ) ( mprj io_out[9] ) + USE SIGNAL
-      + ROUTED met2 ( 2900990 2091340 ) ( * 2097290 )
-      NEW met3 ( 2900990 2091340 ) ( 2917780 * 0 )
-      NEW met2 ( 2176950 2097290 ) ( * 2302310 )
-      NEW met1 ( 2176950 2097290 ) ( 2900990 * )
-      NEW met2 ( 1407600 2289900 0 ) ( 1409210 * )
-      NEW met2 ( 1409210 2289900 ) ( * 2302310 )
-      NEW met1 ( 1409210 2302310 ) ( 2176950 * )
-      NEW met1 ( 2900990 2097290 ) M1M2_PR
-      NEW met2 ( 2900990 2091340 ) M2M3_PR_M
-      NEW met1 ( 2176950 2097290 ) M1M2_PR
-      NEW met1 ( 2176950 2302310 ) M1M2_PR
-      NEW met1 ( 1409210 2302310 ) M1M2_PR ;
-    - la_data_in[0] ( PIN la_data_in[0] ) ( mprj la_data_in[0] ) + USE SIGNAL
-      + ROUTED met1 ( 1172770 1676370 ) ( * 1676710 )
-      NEW met2 ( 1367810 1676710 ) ( * 1690140 )
-      NEW met2 ( 1367810 1690140 ) ( 1368960 * 0 )
-      NEW met1 ( 634570 1676370 ) ( 1172770 * )
-      NEW met2 ( 629510 2380 0 ) ( * 34500 )
-      NEW met2 ( 629510 34500 ) ( 634570 * )
-      NEW met2 ( 634570 34500 ) ( * 1676370 )
-      NEW met1 ( 1172770 1676710 ) ( 1367810 * )
-      NEW met1 ( 1367810 1676710 ) M1M2_PR
-      NEW met1 ( 634570 1676370 ) M1M2_PR ;
-    - la_data_in[100] ( PIN la_data_in[100] ) ( mprj la_data_in[100] ) + USE SIGNAL
-      + ROUTED met2 ( 2402810 2380 0 ) ( * 27710 )
-      NEW met1 ( 2377050 27710 ) ( 2402810 * )
-      NEW met2 ( 1917510 1681470 ) ( * 1690140 )
-      NEW met2 ( 1916820 1690140 0 ) ( 1917510 * )
-      NEW met1 ( 1917510 1681470 ) ( 2377050 * )
-      NEW met2 ( 2377050 27710 ) ( * 1681470 )
-      NEW met1 ( 2402810 27710 ) M1M2_PR
-      NEW met1 ( 2377050 27710 ) M1M2_PR
-      NEW met1 ( 1917510 1681470 ) M1M2_PR
-      NEW met1 ( 2377050 1681470 ) M1M2_PR ;
-    - la_data_in[101] ( PIN la_data_in[101] ) ( mprj la_data_in[101] ) + USE SIGNAL
-      + ROUTED met1 ( 1923490 1680110 ) ( 1945110 * )
-      NEW met2 ( 1923490 1680110 ) ( * 1690140 )
-      NEW met2 ( 1922340 1690140 0 ) ( 1923490 * )
-      NEW met2 ( 1945110 1675690 ) ( * 1680110 )
-      NEW met2 ( 2415230 82800 ) ( 2420290 * )
-      NEW met2 ( 2420290 2380 0 ) ( * 82800 )
-      NEW met2 ( 2415230 82800 ) ( * 1675690 )
-      NEW met1 ( 1945110 1675690 ) ( 2415230 * )
-      NEW met1 ( 1945110 1675690 ) M1M2_PR
-      NEW met1 ( 2415230 1675690 ) M1M2_PR
-      NEW met1 ( 1945110 1680110 ) M1M2_PR
-      NEW met1 ( 1923490 1680110 ) M1M2_PR ;
-    - la_data_in[102] ( PIN la_data_in[102] ) ( mprj la_data_in[102] ) + USE SIGNAL
-      + ROUTED met2 ( 2438230 2380 0 ) ( * 27710 )
-      NEW met1 ( 2432250 27710 ) ( 2438230 * )
-      NEW li1 ( 1956150 1676710 ) ( * 1680790 )
-      NEW met1 ( 1936370 1676710 ) ( 1956150 * )
-      NEW li1 ( 1936370 1676710 ) ( * 1682150 )
-      NEW li1 ( 1935910 1682150 ) ( 1936370 * )
-      NEW met1 ( 1929010 1682150 ) ( 1935910 * )
-      NEW met2 ( 1929010 1682150 ) ( * 1690140 )
-      NEW met2 ( 1927860 1690140 0 ) ( 1929010 * )
-      NEW met2 ( 2432250 27710 ) ( * 1680790 )
-      NEW met1 ( 1956150 1680790 ) ( 2432250 * )
-      NEW met1 ( 2438230 27710 ) M1M2_PR
-      NEW met1 ( 2432250 27710 ) M1M2_PR
-      NEW li1 ( 1956150 1680790 ) L1M1_PR_MR
-      NEW li1 ( 1956150 1676710 ) L1M1_PR_MR
-      NEW li1 ( 1936370 1676710 ) L1M1_PR_MR
-      NEW li1 ( 1935910 1682150 ) L1M1_PR_MR
-      NEW met1 ( 1929010 1682150 ) M1M2_PR
-      NEW met1 ( 2432250 1680790 ) M1M2_PR ;
-    - la_data_in[103] ( PIN la_data_in[103] ) ( mprj la_data_in[103] ) + USE SIGNAL
-      + ROUTED met1 ( 1934530 1680790 ) ( 1940050 * )
-      NEW met2 ( 1934530 1680790 ) ( * 1690140 )
-      NEW met2 ( 1933380 1690140 0 ) ( 1934530 * )
-      NEW met2 ( 1940050 1675010 ) ( * 1680790 )
-      NEW met2 ( 2455710 2380 0 ) ( * 3060 )
-      NEW met2 ( 2454790 3060 ) ( 2455710 * )
-      NEW met2 ( 2454790 2380 ) ( * 3060 )
-      NEW met2 ( 2453410 2380 ) ( 2454790 * )
-      NEW met1 ( 1940050 1675010 ) ( 2450190 * )
-      NEW met2 ( 2450190 82800 ) ( 2453410 * )
-      NEW met2 ( 2453410 2380 ) ( * 82800 )
-      NEW met2 ( 2450190 82800 ) ( * 1675010 )
-      NEW met1 ( 1940050 1675010 ) M1M2_PR
-      NEW met1 ( 1940050 1680790 ) M1M2_PR
-      NEW met1 ( 1934530 1680790 ) M1M2_PR
-      NEW met1 ( 2450190 1675010 ) M1M2_PR ;
-    - la_data_in[104] ( PIN la_data_in[104] ) ( mprj la_data_in[104] ) + USE SIGNAL
-      + ROUTED met2 ( 1939130 1680620 ) ( * 1682660 )
-      NEW met2 ( 1938670 1682660 ) ( 1939130 * )
-      NEW met2 ( 1938670 1682660 ) ( * 1690140 )
-      NEW met2 ( 1938670 1690140 ) ( 1938900 * 0 )
-      NEW met3 ( 1939130 1680620 ) ( 2087710 * )
-      NEW met2 ( 2087710 45050 ) ( * 1680620 )
-      NEW met1 ( 2087710 45050 ) ( 2473650 * )
-      NEW met2 ( 2473650 2380 0 ) ( * 45050 )
-      NEW met2 ( 1939130 1680620 ) M2M3_PR_M
-      NEW met1 ( 2087710 45050 ) M1M2_PR
-      NEW met2 ( 2087710 1680620 ) M2M3_PR_M
-      NEW met1 ( 2473650 45050 ) M1M2_PR ;
-    - la_data_in[105] ( PIN la_data_in[105] ) ( mprj la_data_in[105] ) + USE SIGNAL
-      + ROUTED met1 ( 1955460 1680450 ) ( * 1680790 )
-      NEW met1 ( 1945110 1680790 ) ( 1955460 * )
-      NEW met2 ( 1945110 1680790 ) ( * 1690140 )
-      NEW met2 ( 1944420 1690140 0 ) ( 1945110 * )
-      NEW met2 ( 2491130 2380 0 ) ( * 27710 )
-      NEW met1 ( 2487450 27710 ) ( 2491130 * )
-      NEW met1 ( 1955460 1680450 ) ( 2487450 * )
-      NEW met2 ( 2487450 27710 ) ( * 1680450 )
-      NEW met1 ( 1945110 1680790 ) M1M2_PR
-      NEW met1 ( 2491130 27710 ) M1M2_PR
-      NEW met1 ( 2487450 27710 ) M1M2_PR
-      NEW met1 ( 2487450 1680450 ) M1M2_PR ;
-    - la_data_in[106] ( PIN la_data_in[106] ) ( mprj la_data_in[106] ) + USE SIGNAL
-      + ROUTED met2 ( 2509070 2380 0 ) ( * 3060 )
-      NEW met2 ( 2508150 3060 ) ( 2509070 * )
-      NEW met2 ( 2508150 2380 ) ( * 3060 )
-      NEW met2 ( 2506770 2380 ) ( 2508150 * )
-      NEW met2 ( 1949940 1690140 0 ) ( 1950630 * )
-      NEW met2 ( 1950630 1674670 ) ( * 1690140 )
-      NEW met2 ( 2504930 82800 ) ( 2506770 * )
-      NEW met2 ( 2506770 2380 ) ( * 82800 )
-      NEW met2 ( 2504930 82800 ) ( * 1674670 )
-      NEW met1 ( 1950630 1674670 ) ( 2504930 * )
-      NEW met1 ( 1950630 1674670 ) M1M2_PR
-      NEW met1 ( 2504930 1674670 ) M1M2_PR ;
-    - la_data_in[107] ( PIN la_data_in[107] ) ( mprj la_data_in[107] ) + USE SIGNAL
-      + ROUTED met2 ( 2527010 2380 0 ) ( * 27710 )
-      NEW met1 ( 2521950 27710 ) ( 2527010 * )
-      NEW met2 ( 1956150 1680110 ) ( * 1690140 )
-      NEW met2 ( 1955460 1690140 0 ) ( 1956150 * )
-      NEW met2 ( 2521950 27710 ) ( * 1680110 )
-      NEW met1 ( 1956150 1680110 ) ( 2521950 * )
-      NEW met1 ( 2527010 27710 ) M1M2_PR
-      NEW met1 ( 2521950 27710 ) M1M2_PR
-      NEW met1 ( 1956150 1680110 ) M1M2_PR
-      NEW met1 ( 2521950 1680110 ) M1M2_PR ;
-    - la_data_in[108] ( PIN la_data_in[108] ) ( mprj la_data_in[108] ) + USE SIGNAL
-      + ROUTED met2 ( 1960520 1690140 0 ) ( 1961670 * )
-      NEW met2 ( 1961670 1673990 ) ( * 1690140 )
-      NEW met2 ( 2539430 82800 ) ( 2544490 * )
-      NEW met2 ( 2544490 2380 0 ) ( * 82800 )
-      NEW met2 ( 2539430 82800 ) ( * 1673990 )
-      NEW met1 ( 1961670 1673990 ) ( 2539430 * )
-      NEW met1 ( 1961670 1673990 ) M1M2_PR
-      NEW met1 ( 2539430 1673990 ) M1M2_PR ;
-    - la_data_in[109] ( PIN la_data_in[109] ) ( mprj la_data_in[109] ) + USE SIGNAL
-      + ROUTED met2 ( 1965350 1690140 ) ( 1966040 * 0 )
-      NEW met2 ( 1965350 21250 ) ( * 1690140 )
-      NEW met2 ( 2562430 2380 0 ) ( * 21250 )
-      NEW met1 ( 1965350 21250 ) ( 2562430 * )
-      NEW met1 ( 1965350 21250 ) M1M2_PR
-      NEW met1 ( 2562430 21250 ) M1M2_PR ;
-    - la_data_in[10] ( PIN la_data_in[10] ) ( mprj la_data_in[10] ) + USE SIGNAL
-      + ROUTED met2 ( 806610 2380 0 ) ( * 34500 )
-      NEW met2 ( 806610 34500 ) ( 807070 * )
-      NEW met2 ( 807070 34500 ) ( * 1671270 )
-      NEW met2 ( 1187030 1671270 ) ( * 1677390 )
-      NEW met1 ( 807070 1671270 ) ( 1187030 * )
-      NEW met2 ( 1422550 1677390 ) ( * 1690140 )
-      NEW met2 ( 1422550 1690140 ) ( 1423700 * 0 )
-      NEW met1 ( 1187030 1677390 ) ( 1422550 * )
-      NEW met1 ( 807070 1671270 ) M1M2_PR
-      NEW met1 ( 1187030 1671270 ) M1M2_PR
-      NEW met1 ( 1187030 1677390 ) M1M2_PR
-      NEW met1 ( 1422550 1677390 ) M1M2_PR ;
-    - la_data_in[110] ( PIN la_data_in[110] ) ( mprj la_data_in[110] ) + USE SIGNAL
-      + ROUTED met2 ( 2579910 2380 0 ) ( * 21590 )
-      NEW met1 ( 1972250 21590 ) ( 2579910 * )
-      NEW met2 ( 1971560 1690140 0 ) ( 1972250 * )
-      NEW met2 ( 1972250 21590 ) ( * 1690140 )
-      NEW met1 ( 1972250 21590 ) M1M2_PR
-      NEW met1 ( 2579910 21590 ) M1M2_PR ;
-    - la_data_in[111] ( PIN la_data_in[111] ) ( mprj la_data_in[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2597850 2380 0 ) ( * 21930 )
-      NEW met1 ( 1979150 21930 ) ( 2597850 * )
-      NEW met2 ( 1979150 21930 ) ( * 1676700 )
-      NEW met2 ( 1978230 1676700 ) ( 1979150 * )
-      NEW met2 ( 1978230 1676700 ) ( * 1690140 )
-      NEW met2 ( 1977080 1690140 0 ) ( 1978230 * )
-      NEW met1 ( 2597850 21930 ) M1M2_PR
-      NEW met1 ( 1979150 21930 ) M1M2_PR ;
-    - la_data_in[112] ( PIN la_data_in[112] ) ( mprj la_data_in[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2615330 2380 0 ) ( * 22270 )
-      NEW met1 ( 1985590 22270 ) ( 2615330 * )
-      NEW met2 ( 1983750 1628400 ) ( 1985590 * )
-      NEW met2 ( 1985590 22270 ) ( * 1628400 )
-      NEW met2 ( 1982600 1690140 0 ) ( 1983750 * )
-      NEW met2 ( 1983750 1628400 ) ( * 1690140 )
-      NEW met1 ( 2615330 22270 ) M1M2_PR
-      NEW met1 ( 1985590 22270 ) M1M2_PR ;
-    - la_data_in[113] ( PIN la_data_in[113] ) ( mprj la_data_in[113] ) + USE SIGNAL
-      + ROUTED met2 ( 2633270 2380 0 ) ( * 22610 )
-      NEW met1 ( 1992950 22610 ) ( 2633270 * )
-      NEW met1 ( 1989270 1676710 ) ( 1992950 * )
-      NEW met2 ( 1989270 1676710 ) ( * 1690140 )
-      NEW met2 ( 1988120 1690140 0 ) ( 1989270 * )
-      NEW met2 ( 1992950 22610 ) ( * 1676710 )
-      NEW met1 ( 2633270 22610 ) M1M2_PR
-      NEW met1 ( 1992950 22610 ) M1M2_PR
-      NEW met1 ( 1992950 1676710 ) M1M2_PR
-      NEW met1 ( 1989270 1676710 ) M1M2_PR ;
-    - la_data_in[114] ( PIN la_data_in[114] ) ( mprj la_data_in[114] ) + USE SIGNAL
-      + ROUTED met2 ( 2650750 2380 0 ) ( * 22950 )
-      NEW met1 ( 1993410 22950 ) ( 2650750 * )
-      NEW met2 ( 1993410 1690140 ) ( 1993640 * 0 )
-      NEW met2 ( 1993410 22950 ) ( * 1690140 )
-      NEW met1 ( 1993410 22950 ) M1M2_PR
-      NEW met1 ( 2650750 22950 ) M1M2_PR ;
-    - la_data_in[115] ( PIN la_data_in[115] ) ( mprj la_data_in[115] ) + USE SIGNAL
-      + ROUTED met2 ( 2668690 2380 0 ) ( * 23290 )
-      NEW met1 ( 1999390 23290 ) ( 2668690 * )
-      NEW met2 ( 1999160 1688780 ) ( 1999390 * )
-      NEW met2 ( 1999160 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1999390 23290 ) ( * 1688780 )
-      NEW met1 ( 1999390 23290 ) M1M2_PR
-      NEW met1 ( 2668690 23290 ) M1M2_PR ;
-    - la_data_in[116] ( PIN la_data_in[116] ) ( mprj la_data_in[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2686170 2380 0 ) ( * 23630 )
-      NEW met1 ( 2006750 23630 ) ( 2686170 * )
-      NEW met2 ( 2006750 23630 ) ( * 1676700 )
-      NEW met2 ( 2005830 1676700 ) ( 2006750 * )
-      NEW met2 ( 2005830 1676700 ) ( * 1690140 )
-      NEW met2 ( 2004680 1690140 0 ) ( 2005830 * )
-      NEW met1 ( 2006750 23630 ) M1M2_PR
-      NEW met1 ( 2686170 23630 ) M1M2_PR ;
-    - la_data_in[117] ( PIN la_data_in[117] ) ( mprj la_data_in[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2704110 2380 0 ) ( * 27370 )
-      NEW met1 ( 2013650 27370 ) ( 2704110 * )
-      NEW met1 ( 2011350 1676710 ) ( 2013650 * )
-      NEW met2 ( 2011350 1676710 ) ( * 1690140 )
-      NEW met2 ( 2010200 1690140 0 ) ( 2011350 * )
-      NEW met2 ( 2013650 27370 ) ( * 1676710 )
-      NEW met1 ( 2704110 27370 ) M1M2_PR
-      NEW met1 ( 2013650 27370 ) M1M2_PR
-      NEW met1 ( 2013650 1676710 ) M1M2_PR
-      NEW met1 ( 2011350 1676710 ) M1M2_PR ;
-    - la_data_in[118] ( PIN la_data_in[118] ) ( mprj la_data_in[118] ) + USE SIGNAL
-      + ROUTED met2 ( 2722050 2380 0 ) ( * 27030 )
-      NEW met1 ( 2016410 1676710 ) ( 2020550 * )
-      NEW met2 ( 2016410 1676710 ) ( * 1690140 )
-      NEW met2 ( 2015720 1690140 0 ) ( 2016410 * )
-      NEW met2 ( 2020550 27030 ) ( * 1676710 )
-      NEW met1 ( 2020550 27030 ) ( 2722050 * )
-      NEW met1 ( 2020550 27030 ) M1M2_PR
-      NEW met1 ( 2722050 27030 ) M1M2_PR
-      NEW met1 ( 2020550 1676710 ) M1M2_PR
-      NEW met1 ( 2016410 1676710 ) M1M2_PR ;
-    - la_data_in[119] ( PIN la_data_in[119] ) ( mprj la_data_in[119] ) + USE SIGNAL
-      + ROUTED met2 ( 2020780 1688780 ) ( 2021010 * )
-      NEW met2 ( 2020780 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2021010 26690 ) ( * 1688780 )
-      NEW met2 ( 2739530 2380 0 ) ( * 26690 )
-      NEW met1 ( 2021010 26690 ) ( 2739530 * )
-      NEW met1 ( 2021010 26690 ) M1M2_PR
-      NEW met1 ( 2739530 26690 ) M1M2_PR ;
-    - la_data_in[11] ( PIN la_data_in[11] ) ( mprj la_data_in[11] ) + USE SIGNAL
-      + ROUTED met2 ( 1079850 27370 ) ( * 1679090 )
-      NEW met2 ( 824550 2380 0 ) ( * 27370 )
-      NEW met1 ( 824550 27370 ) ( 1079850 * )
-      NEW met2 ( 1428530 1679090 ) ( * 1690140 )
-      NEW met2 ( 1428530 1690140 ) ( 1429220 * 0 )
-      NEW met1 ( 1079850 1679090 ) ( 1428530 * )
-      NEW met1 ( 1079850 27370 ) M1M2_PR
-      NEW met1 ( 1079850 1679090 ) M1M2_PR
-      NEW met1 ( 824550 27370 ) M1M2_PR
-      NEW met1 ( 1428530 1679090 ) M1M2_PR ;
-    - la_data_in[120] ( PIN la_data_in[120] ) ( mprj la_data_in[120] ) + USE SIGNAL
-      + ROUTED met1 ( 2026990 1676710 ) ( 2027910 * )
-      NEW met2 ( 2026990 1676710 ) ( * 1690140 )
-      NEW met2 ( 2026300 1690140 0 ) ( 2026990 * )
-      NEW met2 ( 2027910 26350 ) ( * 1676710 )
-      NEW met2 ( 2757470 2380 0 ) ( * 26350 )
-      NEW met1 ( 2027910 26350 ) ( 2757470 * )
-      NEW met1 ( 2027910 26350 ) M1M2_PR
-      NEW met1 ( 2027910 1676710 ) M1M2_PR
-      NEW met1 ( 2026990 1676710 ) M1M2_PR
-      NEW met1 ( 2757470 26350 ) M1M2_PR ;
-    - la_data_in[121] ( PIN la_data_in[121] ) ( mprj la_data_in[121] ) + USE SIGNAL
-      + ROUTED met1 ( 2032970 1676710 ) ( 2034350 * )
-      NEW met2 ( 2032970 1676710 ) ( * 1690140 )
-      NEW met2 ( 2031820 1690140 0 ) ( 2032970 * )
-      NEW met2 ( 2034350 26010 ) ( * 1676710 )
-      NEW met2 ( 2774950 2380 0 ) ( * 26010 )
-      NEW met1 ( 2034350 26010 ) ( 2774950 * )
-      NEW met1 ( 2034350 26010 ) M1M2_PR
-      NEW met1 ( 2034350 1676710 ) M1M2_PR
-      NEW met1 ( 2032970 1676710 ) M1M2_PR
-      NEW met1 ( 2774950 26010 ) M1M2_PR ;
-    - la_data_in[122] ( PIN la_data_in[122] ) ( mprj la_data_in[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2792890 2380 0 ) ( * 25670 )
-      NEW met1 ( 2038490 1676710 ) ( 2041710 * )
-      NEW met2 ( 2038490 1676710 ) ( * 1690140 )
-      NEW met2 ( 2037340 1690140 0 ) ( 2038490 * )
-      NEW met2 ( 2041710 25670 ) ( * 1676710 )
-      NEW met1 ( 2041710 25670 ) ( 2792890 * )
-      NEW met1 ( 2041710 25670 ) M1M2_PR
-      NEW met1 ( 2792890 25670 ) M1M2_PR
-      NEW met1 ( 2041710 1676710 ) M1M2_PR
-      NEW met1 ( 2038490 1676710 ) M1M2_PR ;
-    - la_data_in[123] ( PIN la_data_in[123] ) ( mprj la_data_in[123] ) + USE SIGNAL
-      + ROUTED met1 ( 2044010 1652230 ) ( 2048610 * )
-      NEW met2 ( 2810370 2380 0 ) ( * 25330 )
-      NEW met2 ( 2048610 25330 ) ( * 1652230 )
-      NEW met2 ( 2042860 1690140 0 ) ( 2044010 * )
-      NEW met2 ( 2044010 1652230 ) ( * 1690140 )
-      NEW met1 ( 2048610 25330 ) ( 2810370 * )
-      NEW met1 ( 2048610 25330 ) M1M2_PR
-      NEW met1 ( 2044010 1652230 ) M1M2_PR
-      NEW met1 ( 2048610 1652230 ) M1M2_PR
-      NEW met1 ( 2810370 25330 ) M1M2_PR ;
-    - la_data_in[124] ( PIN la_data_in[124] ) ( mprj la_data_in[124] ) + USE SIGNAL
-      + ROUTED met2 ( 2828310 2380 0 ) ( * 24990 )
-      NEW met2 ( 2048150 1690140 ) ( 2048380 * 0 )
-      NEW met2 ( 2048150 24990 ) ( * 1690140 )
-      NEW met1 ( 2048150 24990 ) ( 2828310 * )
-      NEW met1 ( 2048150 24990 ) M1M2_PR
-      NEW met1 ( 2828310 24990 ) M1M2_PR ;
-    - la_data_in[125] ( PIN la_data_in[125] ) ( mprj la_data_in[125] ) + USE SIGNAL
-      + ROUTED met1 ( 2053670 1676710 ) ( 2055510 * )
-      NEW met2 ( 2053670 1676710 ) ( * 1690140 )
-      NEW met2 ( 2053670 1690140 ) ( 2053900 * 0 )
-      NEW met2 ( 2055510 24650 ) ( * 1676710 )
-      NEW met2 ( 2845790 2380 0 ) ( * 24650 )
-      NEW met1 ( 2055510 24650 ) ( 2845790 * )
-      NEW met1 ( 2055510 24650 ) M1M2_PR
-      NEW met1 ( 2055510 1676710 ) M1M2_PR
-      NEW met1 ( 2053670 1676710 ) M1M2_PR
-      NEW met1 ( 2845790 24650 ) M1M2_PR ;
-    - la_data_in[126] ( PIN la_data_in[126] ) ( mprj la_data_in[126] ) + USE SIGNAL
-      + ROUTED met1 ( 2060570 1676710 ) ( 2061950 * )
-      NEW met2 ( 2060570 1676710 ) ( * 1690140 )
-      NEW met2 ( 2059420 1690140 0 ) ( 2060570 * )
-      NEW met2 ( 2061950 24310 ) ( * 1676710 )
-      NEW met2 ( 2863730 2380 0 ) ( * 24310 )
-      NEW met1 ( 2061950 24310 ) ( 2863730 * )
-      NEW met1 ( 2061950 24310 ) M1M2_PR
-      NEW met1 ( 2061950 1676710 ) M1M2_PR
-      NEW met1 ( 2060570 1676710 ) M1M2_PR
-      NEW met1 ( 2863730 24310 ) M1M2_PR ;
-    - la_data_in[127] ( PIN la_data_in[127] ) ( mprj la_data_in[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2881670 2380 0 ) ( * 23970 )
-      NEW met1 ( 2069310 23970 ) ( 2881670 * )
-      NEW met1 ( 2066090 1678070 ) ( 2069310 * )
-      NEW met2 ( 2066090 1678070 ) ( * 1690140 )
-      NEW met2 ( 2064940 1690140 0 ) ( 2066090 * )
-      NEW met2 ( 2069310 23970 ) ( * 1678070 )
-      NEW met1 ( 2069310 23970 ) M1M2_PR
-      NEW met1 ( 2881670 23970 ) M1M2_PR
-      NEW met1 ( 2069310 1678070 ) M1M2_PR
-      NEW met1 ( 2066090 1678070 ) M1M2_PR ;
-    - la_data_in[12] ( PIN la_data_in[12] ) ( mprj la_data_in[12] ) + USE SIGNAL
-      + ROUTED met2 ( 842030 2380 0 ) ( * 20910 )
-      NEW met1 ( 842030 20910 ) ( 848470 * )
-      NEW met1 ( 848470 1675690 ) ( 1433590 * )
-      NEW met2 ( 848470 20910 ) ( * 1675690 )
-      NEW met2 ( 1433590 1690140 ) ( 1434740 * 0 )
-      NEW met2 ( 1433590 1675690 ) ( * 1690140 )
-      NEW met1 ( 842030 20910 ) M1M2_PR
-      NEW met1 ( 848470 20910 ) M1M2_PR
-      NEW met1 ( 848470 1675690 ) M1M2_PR
-      NEW met1 ( 1433590 1675690 ) M1M2_PR ;
-    - la_data_in[13] ( PIN la_data_in[13] ) ( mprj la_data_in[13] ) + USE SIGNAL
-      + ROUTED met2 ( 859970 2380 0 ) ( * 23290 )
-      NEW met2 ( 1439110 1678410 ) ( * 1690140 )
-      NEW met2 ( 1439110 1690140 ) ( 1440260 * 0 )
-      NEW met1 ( 859970 23290 ) ( 1114350 * )
-      NEW met2 ( 1114350 23290 ) ( * 1678410 )
-      NEW met1 ( 1114350 1678410 ) ( 1439110 * )
-      NEW met1 ( 859970 23290 ) M1M2_PR
-      NEW met1 ( 1439110 1678410 ) M1M2_PR
-      NEW met1 ( 1114350 23290 ) M1M2_PR
-      NEW met1 ( 1114350 1678410 ) M1M2_PR ;
-    - la_data_in[14] ( PIN la_data_in[14] ) ( mprj la_data_in[14] ) + USE SIGNAL
-      + ROUTED met2 ( 877450 2380 0 ) ( * 3060 )
-      NEW met2 ( 877450 3060 ) ( 878370 * )
-      NEW met2 ( 878370 2380 ) ( * 3060 )
-      NEW met2 ( 878370 2380 ) ( 879750 * )
-      NEW met2 ( 879750 2380 ) ( * 60010 )
-      NEW met2 ( 1444630 1678750 ) ( * 1690140 )
-      NEW met2 ( 1444630 1690140 ) ( 1445780 * 0 )
-      NEW met1 ( 879750 60010 ) ( 1121250 * )
-      NEW met2 ( 1121250 60010 ) ( * 1678750 )
-      NEW met1 ( 1121250 1678750 ) ( 1444630 * )
-      NEW met1 ( 879750 60010 ) M1M2_PR
-      NEW met1 ( 1444630 1678750 ) M1M2_PR
-      NEW met1 ( 1121250 60010 ) M1M2_PR
-      NEW met1 ( 1121250 1678750 ) M1M2_PR ;
-    - la_data_in[15] ( PIN la_data_in[15] ) ( mprj la_data_in[15] ) + USE SIGNAL
-      + ROUTED met2 ( 895390 2380 0 ) ( * 34500 )
-      NEW met2 ( 895390 34500 ) ( 896770 * )
-      NEW met2 ( 896770 34500 ) ( * 1676030 )
-      NEW met1 ( 1449000 1676710 ) ( 1450150 * )
-      NEW met2 ( 1450150 1676710 ) ( * 1690140 )
-      NEW met2 ( 1450150 1690140 ) ( 1451300 * 0 )
-      NEW met1 ( 1449000 1676030 ) ( * 1676710 )
-      NEW met1 ( 896770 1676030 ) ( 1449000 * )
-      NEW met1 ( 896770 1676030 ) M1M2_PR
-      NEW met1 ( 1450150 1676710 ) M1M2_PR ;
-    - la_data_in[16] ( PIN la_data_in[16] ) ( mprj la_data_in[16] ) + USE SIGNAL
-      + ROUTED met2 ( 990150 26350 ) ( * 1683510 )
-      NEW li1 ( 1441870 1682830 ) ( * 1683510 )
-      NEW met1 ( 1441870 1682830 ) ( 1456130 * )
-      NEW met2 ( 1456130 1682830 ) ( * 1690140 )
-      NEW met2 ( 1456130 1690140 ) ( 1456820 * 0 )
-      NEW met2 ( 912870 2380 0 ) ( * 26350 )
-      NEW met1 ( 912870 26350 ) ( 990150 * )
-      NEW met1 ( 990150 1683510 ) ( 1441870 * )
-      NEW met1 ( 990150 26350 ) M1M2_PR
-      NEW met1 ( 990150 1683510 ) M1M2_PR
-      NEW li1 ( 1441870 1683510 ) L1M1_PR_MR
-      NEW li1 ( 1441870 1682830 ) L1M1_PR_MR
-      NEW met1 ( 1456130 1682830 ) M1M2_PR
-      NEW met1 ( 912870 26350 ) M1M2_PR ;
-    - la_data_in[17] ( PIN la_data_in[17] ) ( mprj la_data_in[17] ) + USE SIGNAL
-      + ROUTED met2 ( 983250 26690 ) ( * 1682830 )
-      NEW met1 ( 1441410 1682490 ) ( * 1682830 )
-      NEW met1 ( 1441410 1682490 ) ( 1461190 * )
-      NEW met2 ( 1461190 1682490 ) ( * 1690140 )
-      NEW met2 ( 1461190 1690140 ) ( 1462340 * 0 )
-      NEW met2 ( 930810 2380 0 ) ( * 26690 )
-      NEW met1 ( 930810 26690 ) ( 983250 * )
-      NEW met1 ( 983250 1682830 ) ( 1441410 * )
-      NEW met1 ( 983250 26690 ) M1M2_PR
-      NEW met1 ( 983250 1682830 ) M1M2_PR
-      NEW met1 ( 1461190 1682490 ) M1M2_PR
-      NEW met1 ( 930810 26690 ) M1M2_PR ;
-    - la_data_in[18] ( PIN la_data_in[18] ) ( mprj la_data_in[18] ) + USE SIGNAL
-      + ROUTED met2 ( 955650 23630 ) ( * 1682490 )
-      NEW met2 ( 1466710 1682150 ) ( * 1690140 )
-      NEW met2 ( 1466710 1690140 ) ( 1467860 * 0 )
-      NEW met2 ( 948750 2380 0 ) ( * 23630 )
-      NEW met1 ( 948750 23630 ) ( 955650 * )
-      NEW met1 ( 1435200 1682150 ) ( 1466710 * )
-      NEW met1 ( 1435200 1682150 ) ( * 1682490 )
-      NEW met1 ( 955650 1682490 ) ( 1435200 * )
-      NEW met1 ( 955650 23630 ) M1M2_PR
-      NEW met1 ( 955650 1682490 ) M1M2_PR
-      NEW met1 ( 1466710 1682150 ) M1M2_PR
-      NEW met1 ( 948750 23630 ) M1M2_PR ;
-    - la_data_in[19] ( PIN la_data_in[19] ) ( mprj la_data_in[19] ) + USE SIGNAL
-      + ROUTED met2 ( 966230 2380 0 ) ( * 20910 )
-      NEW met1 ( 966230 20910 ) ( 972670 * )
-      NEW met2 ( 972670 20910 ) ( * 60350 )
-      NEW met2 ( 1155750 60350 ) ( * 1678070 )
-      NEW met1 ( 1441410 1677730 ) ( * 1678070 )
-      NEW met1 ( 1441410 1677730 ) ( 1472230 * )
-      NEW met2 ( 1472230 1677730 ) ( * 1690140 )
-      NEW met2 ( 1472230 1690140 ) ( 1473380 * 0 )
-      NEW met1 ( 972670 60350 ) ( 1155750 * )
-      NEW met1 ( 1155750 1678070 ) ( 1441410 * )
-      NEW met1 ( 966230 20910 ) M1M2_PR
-      NEW met1 ( 972670 20910 ) M1M2_PR
-      NEW met1 ( 972670 60350 ) M1M2_PR
-      NEW met1 ( 1155750 60350 ) M1M2_PR
-      NEW met1 ( 1155750 1678070 ) M1M2_PR
-      NEW met1 ( 1472230 1677730 ) M1M2_PR ;
-    - la_data_in[1] ( PIN la_data_in[1] ) ( mprj la_data_in[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1373330 1690140 ) ( 1374480 * 0 )
-      NEW met2 ( 646990 2380 0 ) ( * 25330 )
-      NEW met1 ( 646990 25330 ) ( 1373330 * )
-      NEW met2 ( 1373330 25330 ) ( * 1690140 )
-      NEW met1 ( 1373330 25330 ) M1M2_PR
-      NEW met1 ( 646990 25330 ) M1M2_PR ;
-    - la_data_in[20] ( PIN la_data_in[20] ) ( mprj la_data_in[20] ) + USE SIGNAL
-      + ROUTED met2 ( 984170 2380 0 ) ( * 3060 )
-      NEW met2 ( 984170 3060 ) ( 985090 * )
-      NEW met2 ( 985090 2380 ) ( * 3060 )
-      NEW met2 ( 985090 2380 ) ( 986470 * )
-      NEW met2 ( 986470 2380 ) ( * 60690 )
-      NEW met2 ( 1162650 60690 ) ( * 1677730 )
-      NEW met2 ( 1477290 1677390 ) ( * 1690140 )
-      NEW met2 ( 1477290 1690140 ) ( 1478440 * 0 )
-      NEW met1 ( 986470 60690 ) ( 1162650 * )
-      NEW met1 ( 1435200 1677390 ) ( 1477290 * )
-      NEW met1 ( 1435200 1677390 ) ( * 1677730 )
-      NEW met1 ( 1162650 1677730 ) ( 1435200 * )
-      NEW met1 ( 986470 60690 ) M1M2_PR
-      NEW met1 ( 1162650 60690 ) M1M2_PR
-      NEW met1 ( 1162650 1677730 ) M1M2_PR
-      NEW met1 ( 1477290 1677390 ) M1M2_PR ;
-    - la_data_in[21] ( PIN la_data_in[21] ) ( mprj la_data_in[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1066050 61030 ) ( * 1679430 )
-      NEW met2 ( 1001650 2380 0 ) ( * 3060 )
-      NEW met2 ( 1001650 3060 ) ( 1002570 * )
-      NEW met2 ( 1002570 2380 ) ( * 3060 )
-      NEW met2 ( 1002570 2380 ) ( 1003950 * )
-      NEW met2 ( 1003950 2380 ) ( * 61030 )
-      NEW met1 ( 1003950 61030 ) ( 1066050 * )
-      NEW met2 ( 1483730 1679430 ) ( * 1690140 )
-      NEW met2 ( 1483730 1690140 ) ( 1483960 * 0 )
-      NEW met1 ( 1066050 1679430 ) ( 1483730 * )
-      NEW met1 ( 1066050 61030 ) M1M2_PR
-      NEW met1 ( 1066050 1679430 ) M1M2_PR
-      NEW met1 ( 1003950 61030 ) M1M2_PR
-      NEW met1 ( 1483730 1679430 ) M1M2_PR ;
-    - la_data_in[22] ( PIN la_data_in[22] ) ( mprj la_data_in[22] ) + USE SIGNAL
-      + ROUTED met2 ( 1019590 2380 0 ) ( * 26010 )
-      NEW met1 ( 1019590 26010 ) ( 1484650 * )
-      NEW met2 ( 1484650 26010 ) ( * 1580100 )
-      NEW met2 ( 1484650 1580100 ) ( 1488330 * )
-      NEW met2 ( 1488330 1690140 ) ( 1489480 * 0 )
-      NEW met2 ( 1488330 1580100 ) ( * 1690140 )
-      NEW met1 ( 1019590 26010 ) M1M2_PR
-      NEW met1 ( 1484650 26010 ) M1M2_PR ;
-    - la_data_in[23] ( PIN la_data_in[23] ) ( mprj la_data_in[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1037070 2380 0 ) ( * 26350 )
-      NEW met1 ( 1037070 26350 ) ( 1491550 * )
-      NEW met2 ( 1491550 26350 ) ( * 1580100 )
-      NEW met2 ( 1491550 1580100 ) ( 1493850 * )
-      NEW met2 ( 1493850 1690140 ) ( 1495000 * 0 )
-      NEW met2 ( 1493850 1580100 ) ( * 1690140 )
-      NEW met1 ( 1037070 26350 ) M1M2_PR
-      NEW met1 ( 1491550 26350 ) M1M2_PR ;
-    - la_data_in[24] ( PIN la_data_in[24] ) ( mprj la_data_in[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1055010 2380 0 ) ( * 26690 )
-      NEW met1 ( 1055010 26690 ) ( 1498910 * )
-      NEW met2 ( 1498910 26690 ) ( * 1580100 )
-      NEW met2 ( 1498910 1580100 ) ( 1499370 * )
-      NEW met2 ( 1499370 1690140 ) ( 1500520 * 0 )
-      NEW met2 ( 1499370 1580100 ) ( * 1690140 )
-      NEW met1 ( 1055010 26690 ) M1M2_PR
-      NEW met1 ( 1498910 26690 ) M1M2_PR ;
-    - la_data_in[25] ( PIN la_data_in[25] ) ( mprj la_data_in[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1072490 2380 0 ) ( * 27030 )
-      NEW met1 ( 1072490 27030 ) ( 1505350 * )
-      NEW met2 ( 1505350 1690140 ) ( 1506040 * 0 )
-      NEW met2 ( 1505350 27030 ) ( * 1690140 )
-      NEW met1 ( 1072490 27030 ) M1M2_PR
-      NEW met1 ( 1505350 27030 ) M1M2_PR ;
-    - la_data_in[26] ( PIN la_data_in[26] ) ( mprj la_data_in[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1090430 2380 0 ) ( * 27370 )
-      NEW met1 ( 1090430 27370 ) ( 1511790 * )
-      NEW met2 ( 1511560 1688780 ) ( 1511790 * )
-      NEW met2 ( 1511560 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1511790 27370 ) ( * 1688780 )
-      NEW met1 ( 1090430 27370 ) M1M2_PR
-      NEW met1 ( 1511790 27370 ) M1M2_PR ;
-    - la_data_in[27] ( PIN la_data_in[27] ) ( mprj la_data_in[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1107910 2380 0 ) ( * 23630 )
-      NEW met1 ( 1107910 23630 ) ( 1512710 * )
-      NEW met2 ( 1512710 23630 ) ( * 1580100 )
-      NEW met2 ( 1512710 1580100 ) ( 1515930 * )
-      NEW met2 ( 1515930 1690140 ) ( 1517080 * 0 )
-      NEW met2 ( 1515930 1580100 ) ( * 1690140 )
-      NEW met1 ( 1107910 23630 ) M1M2_PR
-      NEW met1 ( 1512710 23630 ) M1M2_PR ;
-    - la_data_in[28] ( PIN la_data_in[28] ) ( mprj la_data_in[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1125850 2380 0 ) ( * 23290 )
-      NEW met1 ( 1125850 23290 ) ( 1519150 * )
-      NEW met2 ( 1519150 23290 ) ( * 1580100 )
-      NEW met2 ( 1519150 1580100 ) ( 1521450 * )
-      NEW met2 ( 1521450 1690140 ) ( 1522600 * 0 )
-      NEW met2 ( 1521450 1580100 ) ( * 1690140 )
-      NEW met1 ( 1125850 23290 ) M1M2_PR
-      NEW met1 ( 1519150 23290 ) M1M2_PR ;
-    - la_data_in[29] ( PIN la_data_in[29] ) ( mprj la_data_in[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1143790 2380 0 ) ( * 22950 )
-      NEW met1 ( 1143790 22950 ) ( 1525130 * )
-      NEW met1 ( 1525130 1652570 ) ( 1526970 * )
-      NEW met2 ( 1525130 22950 ) ( * 1652570 )
-      NEW met2 ( 1526970 1690140 ) ( 1528120 * 0 )
-      NEW met2 ( 1526970 1652570 ) ( * 1690140 )
-      NEW met1 ( 1143790 22950 ) M1M2_PR
-      NEW met1 ( 1525130 22950 ) M1M2_PR
-      NEW met1 ( 1525130 1652570 ) M1M2_PR
-      NEW met1 ( 1526970 1652570 ) M1M2_PR ;
-    - la_data_in[2] ( PIN la_data_in[2] ) ( mprj la_data_in[2] ) + USE SIGNAL
-      + ROUTED met2 ( 664930 2380 0 ) ( * 25670 )
-      NEW met2 ( 1378850 1690140 ) ( 1380000 * 0 )
-      NEW met1 ( 664930 25670 ) ( 1373790 * )
-      NEW met1 ( 1373790 1631830 ) ( 1378850 * )
-      NEW met2 ( 1373790 25670 ) ( * 1631830 )
-      NEW met2 ( 1378850 1631830 ) ( * 1690140 )
-      NEW met1 ( 664930 25670 ) M1M2_PR
-      NEW met1 ( 1373790 25670 ) M1M2_PR
-      NEW met1 ( 1373790 1631830 ) M1M2_PR
-      NEW met1 ( 1378850 1631830 ) M1M2_PR ;
-    - la_data_in[30] ( PIN la_data_in[30] ) ( mprj la_data_in[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1161270 2380 0 ) ( * 22610 )
-      NEW met2 ( 1532030 22610 ) ( * 1676700 )
-      NEW met2 ( 1532030 1676700 ) ( 1532490 * )
-      NEW met2 ( 1532490 1676700 ) ( * 1690140 )
-      NEW met2 ( 1532490 1690140 ) ( 1533640 * 0 )
-      NEW met1 ( 1161270 22610 ) ( 1532030 * )
-      NEW met1 ( 1161270 22610 ) M1M2_PR
-      NEW met1 ( 1532030 22610 ) M1M2_PR ;
-    - la_data_in[31] ( PIN la_data_in[31] ) ( mprj la_data_in[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1179210 2380 0 ) ( * 23970 )
-      NEW met1 ( 1532490 1652570 ) ( 1537550 * )
-      NEW met2 ( 1532490 23970 ) ( * 1652570 )
-      NEW met2 ( 1537550 1690140 ) ( 1538700 * 0 )
-      NEW met2 ( 1537550 1652570 ) ( * 1690140 )
-      NEW met1 ( 1179210 23970 ) ( 1532490 * )
-      NEW met1 ( 1179210 23970 ) M1M2_PR
-      NEW met1 ( 1532490 23970 ) M1M2_PR
-      NEW met1 ( 1532490 1652570 ) M1M2_PR
-      NEW met1 ( 1537550 1652570 ) M1M2_PR ;
-    - la_data_in[32] ( PIN la_data_in[32] ) ( mprj la_data_in[32] ) + USE SIGNAL
-      + ROUTED met1 ( 1538930 1652570 ) ( 1543070 * )
-      NEW met2 ( 1538930 24310 ) ( * 1652570 )
-      NEW met2 ( 1543070 1690140 ) ( 1544220 * 0 )
-      NEW met2 ( 1543070 1652570 ) ( * 1690140 )
-      NEW met2 ( 1196690 2380 0 ) ( * 24310 )
-      NEW met1 ( 1196690 24310 ) ( 1538930 * )
-      NEW met1 ( 1538930 24310 ) M1M2_PR
-      NEW met1 ( 1538930 1652570 ) M1M2_PR
-      NEW met1 ( 1543070 1652570 ) M1M2_PR
-      NEW met1 ( 1196690 24310 ) M1M2_PR ;
-    - la_data_in[33] ( PIN la_data_in[33] ) ( mprj la_data_in[33] ) + USE SIGNAL
-      + ROUTED met1 ( 1545830 1652230 ) ( 1548590 * )
-      NEW met2 ( 1545830 24650 ) ( * 1652230 )
-      NEW met2 ( 1548590 1690140 ) ( 1549740 * 0 )
-      NEW met2 ( 1548590 1652230 ) ( * 1690140 )
-      NEW met2 ( 1214630 2380 0 ) ( * 24650 )
-      NEW met1 ( 1214630 24650 ) ( 1545830 * )
-      NEW met1 ( 1545830 24650 ) M1M2_PR
-      NEW met1 ( 1545830 1652230 ) M1M2_PR
-      NEW met1 ( 1548590 1652230 ) M1M2_PR
-      NEW met1 ( 1214630 24650 ) M1M2_PR ;
-    - la_data_in[34] ( PIN la_data_in[34] ) ( mprj la_data_in[34] ) + USE SIGNAL
-      + ROUTED met1 ( 1552730 1683170 ) ( 1554110 * )
-      NEW met2 ( 1554110 1683170 ) ( * 1690140 )
-      NEW met2 ( 1554110 1690140 ) ( 1555260 * 0 )
-      NEW met2 ( 1552730 24990 ) ( * 1683170 )
-      NEW met2 ( 1232110 2380 0 ) ( * 24990 )
-      NEW met1 ( 1232110 24990 ) ( 1552730 * )
-      NEW met1 ( 1552730 24990 ) M1M2_PR
-      NEW met1 ( 1552730 1683170 ) M1M2_PR
-      NEW met1 ( 1554110 1683170 ) M1M2_PR
-      NEW met1 ( 1232110 24990 ) M1M2_PR ;
-    - la_data_in[35] ( PIN la_data_in[35] ) ( mprj la_data_in[35] ) + USE SIGNAL
-      + ROUTED met2 ( 1250050 2380 0 ) ( * 17510 )
-      NEW met1 ( 1250050 17510 ) ( 1255570 * )
-      NEW met2 ( 1255570 17510 ) ( * 60010 )
-      NEW met2 ( 1459350 60010 ) ( * 1580100 )
-      NEW met2 ( 1459350 1580100 ) ( 1459810 * )
-      NEW met2 ( 1459810 1580100 ) ( * 1678410 )
-      NEW met2 ( 1559630 1678410 ) ( * 1690140 )
-      NEW met2 ( 1559630 1690140 ) ( 1560780 * 0 )
-      NEW met1 ( 1255570 60010 ) ( 1459350 * )
-      NEW met1 ( 1459810 1678410 ) ( 1559630 * )
-      NEW met1 ( 1250050 17510 ) M1M2_PR
-      NEW met1 ( 1255570 17510 ) M1M2_PR
-      NEW met1 ( 1255570 60010 ) M1M2_PR
-      NEW met1 ( 1459350 60010 ) M1M2_PR
-      NEW met1 ( 1459810 1678410 ) M1M2_PR
-      NEW met1 ( 1559630 1678410 ) M1M2_PR ;
-    - la_data_in[36] ( PIN la_data_in[36] ) ( mprj la_data_in[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1267530 2380 0 ) ( * 3060 )
-      NEW met2 ( 1267530 3060 ) ( 1268450 * )
-      NEW met2 ( 1268450 2380 ) ( * 3060 )
-      NEW met2 ( 1268450 2380 ) ( 1269370 * )
-      NEW met2 ( 1269370 2380 ) ( * 52870 )
-      NEW met2 ( 1445550 52870 ) ( * 1679090 )
-      NEW met2 ( 1565150 1679090 ) ( * 1690140 )
-      NEW met2 ( 1565150 1690140 ) ( 1566300 * 0 )
-      NEW met1 ( 1269370 52870 ) ( 1445550 * )
-      NEW met1 ( 1445550 1679090 ) ( 1565150 * )
-      NEW met1 ( 1269370 52870 ) M1M2_PR
-      NEW met1 ( 1445550 52870 ) M1M2_PR
-      NEW met1 ( 1445550 1679090 ) M1M2_PR
-      NEW met1 ( 1565150 1679090 ) M1M2_PR ;
-    - la_data_in[37] ( PIN la_data_in[37] ) ( mprj la_data_in[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1285470 2380 0 ) ( * 30770 )
-      NEW met1 ( 1566530 1652570 ) ( 1570670 * )
-      NEW met2 ( 1566530 30770 ) ( * 1652570 )
-      NEW met2 ( 1570670 1690140 ) ( 1571820 * 0 )
-      NEW met2 ( 1570670 1652570 ) ( * 1690140 )
-      NEW met1 ( 1285470 30770 ) ( 1566530 * )
-      NEW met1 ( 1285470 30770 ) M1M2_PR
-      NEW met1 ( 1566530 30770 ) M1M2_PR
-      NEW met1 ( 1566530 1652570 ) M1M2_PR
-      NEW met1 ( 1570670 1652570 ) M1M2_PR ;
-    - la_data_in[38] ( PIN la_data_in[38] ) ( mprj la_data_in[38] ) + USE SIGNAL
-      + ROUTED li1 ( 1552270 1683170 ) ( 1554570 * )
-      NEW met1 ( 1554570 1683170 ) ( 1576190 * )
-      NEW met2 ( 1576190 1683170 ) ( * 1690140 )
-      NEW met2 ( 1576190 1690140 ) ( 1577340 * 0 )
-      NEW met2 ( 1303410 2380 0 ) ( * 53210 )
-      NEW met1 ( 1303410 53210 ) ( 1431750 * )
-      NEW met2 ( 1431750 53210 ) ( * 1580100 )
-      NEW met2 ( 1431750 1580100 ) ( 1432210 * )
-      NEW met2 ( 1432210 1580100 ) ( * 1683170 )
-      NEW met1 ( 1432210 1683170 ) ( 1552270 * )
-      NEW li1 ( 1552270 1683170 ) L1M1_PR_MR
-      NEW li1 ( 1554570 1683170 ) L1M1_PR_MR
-      NEW met1 ( 1576190 1683170 ) M1M2_PR
-      NEW met1 ( 1303410 53210 ) M1M2_PR
-      NEW met1 ( 1431750 53210 ) M1M2_PR
-      NEW met1 ( 1432210 1683170 ) M1M2_PR ;
-    - la_data_in[39] ( PIN la_data_in[39] ) ( mprj la_data_in[39] ) + USE SIGNAL
-      + ROUTED met2 ( 1320890 2380 0 ) ( * 17510 )
-      NEW met1 ( 1320890 17510 ) ( 1324570 * )
-      NEW met2 ( 1324570 17510 ) ( * 51850 )
-      NEW met1 ( 1324570 51850 ) ( 1580790 * )
-      NEW met2 ( 1580790 1683340 ) ( 1581710 * )
-      NEW met2 ( 1581710 1683340 ) ( * 1690140 )
-      NEW met2 ( 1581710 1690140 ) ( 1582860 * 0 )
-      NEW met2 ( 1580790 51850 ) ( * 1683340 )
-      NEW met1 ( 1320890 17510 ) M1M2_PR
-      NEW met1 ( 1324570 17510 ) M1M2_PR
-      NEW met1 ( 1324570 51850 ) M1M2_PR
-      NEW met1 ( 1580790 51850 ) M1M2_PR ;
-    - la_data_in[3] ( PIN la_data_in[3] ) ( mprj la_data_in[3] ) + USE SIGNAL
-      + ROUTED met2 ( 682410 2380 0 ) ( * 26010 )
-      NEW met2 ( 1384370 1683170 ) ( * 1690140 )
-      NEW met2 ( 1384370 1690140 ) ( 1385520 * 0 )
-      NEW met1 ( 682410 26010 ) ( 941850 * )
-      NEW met2 ( 941850 26010 ) ( * 1683170 )
-      NEW met1 ( 941850 1683170 ) ( 1384370 * )
-      NEW met1 ( 682410 26010 ) M1M2_PR
-      NEW met1 ( 1384370 1683170 ) M1M2_PR
-      NEW met1 ( 941850 26010 ) M1M2_PR
-      NEW met1 ( 941850 1683170 ) M1M2_PR ;
-    - la_data_in[40] ( PIN la_data_in[40] ) ( mprj la_data_in[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1338830 2380 0 ) ( * 17510 )
-      NEW met1 ( 1338830 17510 ) ( 1345270 * )
-      NEW met2 ( 1345270 17510 ) ( * 52190 )
-      NEW met1 ( 1345270 52190 ) ( 1588150 * )
-      NEW met2 ( 1588150 1690140 ) ( 1588380 * 0 )
-      NEW met2 ( 1588150 52190 ) ( * 1690140 )
-      NEW met1 ( 1338830 17510 ) M1M2_PR
-      NEW met1 ( 1345270 17510 ) M1M2_PR
-      NEW met1 ( 1345270 52190 ) M1M2_PR
-      NEW met1 ( 1588150 52190 ) M1M2_PR ;
-    - la_data_in[41] ( PIN la_data_in[41] ) ( mprj la_data_in[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1356310 2380 0 ) ( * 17510 )
-      NEW met1 ( 1356310 17510 ) ( 1359070 * )
-      NEW met2 ( 1359070 17510 ) ( * 52530 )
-      NEW met1 ( 1587690 1652570 ) ( 1592750 * )
-      NEW met1 ( 1359070 52530 ) ( 1587690 * )
-      NEW met2 ( 1587690 52530 ) ( * 1652570 )
-      NEW met2 ( 1592750 1690140 ) ( 1593900 * 0 )
-      NEW met2 ( 1592750 1652570 ) ( * 1690140 )
-      NEW met1 ( 1356310 17510 ) M1M2_PR
-      NEW met1 ( 1359070 17510 ) M1M2_PR
-      NEW met1 ( 1359070 52530 ) M1M2_PR
-      NEW met1 ( 1587690 1652570 ) M1M2_PR
-      NEW met1 ( 1592750 1652570 ) M1M2_PR
-      NEW met1 ( 1587690 52530 ) M1M2_PR ;
-    - la_data_in[42] ( PIN la_data_in[42] ) ( mprj la_data_in[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1374250 2380 0 ) ( * 25330 )
-      NEW met1 ( 1374250 25330 ) ( 1594590 * )
-      NEW met1 ( 1594590 1652570 ) ( 1597810 * )
-      NEW met2 ( 1594590 25330 ) ( * 1652570 )
-      NEW met2 ( 1597810 1690140 ) ( 1598960 * 0 )
-      NEW met2 ( 1597810 1652570 ) ( * 1690140 )
-      NEW met1 ( 1374250 25330 ) M1M2_PR
-      NEW met1 ( 1594590 25330 ) M1M2_PR
-      NEW met1 ( 1594590 1652570 ) M1M2_PR
-      NEW met1 ( 1597810 1652570 ) M1M2_PR ;
-    - la_data_in[43] ( PIN la_data_in[43] ) ( mprj la_data_in[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1391730 2380 0 ) ( * 25670 )
-      NEW met1 ( 1391730 25670 ) ( 1601950 * )
-      NEW met2 ( 1601950 25670 ) ( * 1580100 )
-      NEW met2 ( 1601950 1580100 ) ( 1603330 * )
-      NEW met2 ( 1603330 1690140 ) ( 1604480 * 0 )
-      NEW met2 ( 1603330 1580100 ) ( * 1690140 )
-      NEW met1 ( 1391730 25670 ) M1M2_PR
-      NEW met1 ( 1601950 25670 ) M1M2_PR ;
-    - la_data_in[44] ( PIN la_data_in[44] ) ( mprj la_data_in[44] ) + USE SIGNAL
-      + ROUTED met2 ( 1409670 2380 0 ) ( * 22270 )
-      NEW met1 ( 1409670 22270 ) ( 1608850 * )
-      NEW met2 ( 1608850 1690140 ) ( 1610000 * 0 )
-      NEW met2 ( 1608850 22270 ) ( * 1690140 )
-      NEW met1 ( 1409670 22270 ) M1M2_PR
-      NEW met1 ( 1608850 22270 ) M1M2_PR ;
-    - la_data_in[45] ( PIN la_data_in[45] ) ( mprj la_data_in[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1427150 2380 0 ) ( * 21930 )
-      NEW met1 ( 1427150 21930 ) ( 1615290 * )
-      NEW met2 ( 1615290 1690140 ) ( 1615520 * 0 )
-      NEW met2 ( 1615290 21930 ) ( * 1690140 )
-      NEW met1 ( 1427150 21930 ) M1M2_PR
-      NEW met1 ( 1615290 21930 ) M1M2_PR ;
-    - la_data_in[46] ( PIN la_data_in[46] ) ( mprj la_data_in[46] ) + USE SIGNAL
-      + ROUTED met2 ( 1445090 2380 0 ) ( * 21590 )
-      NEW met1 ( 1445090 21590 ) ( 1615750 * )
-      NEW met1 ( 1615750 1652570 ) ( 1619890 * )
-      NEW met2 ( 1615750 21590 ) ( * 1652570 )
-      NEW met2 ( 1619890 1690140 ) ( 1621040 * 0 )
-      NEW met2 ( 1619890 1652570 ) ( * 1690140 )
-      NEW met1 ( 1445090 21590 ) M1M2_PR
-      NEW met1 ( 1615750 21590 ) M1M2_PR
-      NEW met1 ( 1615750 1652570 ) M1M2_PR
-      NEW met1 ( 1619890 1652570 ) M1M2_PR ;
-    - la_data_in[47] ( PIN la_data_in[47] ) ( mprj la_data_in[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1463030 2380 0 ) ( * 21250 )
-      NEW met1 ( 1463030 21250 ) ( 1623110 * )
-      NEW met2 ( 1623110 21250 ) ( * 1580100 )
-      NEW met2 ( 1623110 1580100 ) ( 1625410 * )
-      NEW met2 ( 1625410 1690140 ) ( 1626560 * 0 )
-      NEW met2 ( 1625410 1580100 ) ( * 1690140 )
-      NEW met1 ( 1463030 21250 ) M1M2_PR
-      NEW met1 ( 1623110 21250 ) M1M2_PR ;
-    - la_data_in[48] ( PIN la_data_in[48] ) ( mprj la_data_in[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1480510 2380 0 ) ( * 15130 )
-      NEW met1 ( 1480510 15130 ) ( 1483270 * )
-      NEW met2 ( 1483270 15130 ) ( * 1682490 )
-      NEW met2 ( 1630930 1682490 ) ( * 1690140 )
-      NEW met2 ( 1630930 1690140 ) ( 1632080 * 0 )
-      NEW met1 ( 1483270 1682490 ) ( 1630930 * )
-      NEW met1 ( 1480510 15130 ) M1M2_PR
-      NEW met1 ( 1483270 15130 ) M1M2_PR
-      NEW met1 ( 1483270 1682490 ) M1M2_PR
-      NEW met1 ( 1630930 1682490 ) M1M2_PR ;
-    - la_data_in[49] ( PIN la_data_in[49] ) ( mprj la_data_in[49] ) + USE SIGNAL
-      + ROUTED met2 ( 1636450 1680110 ) ( * 1690140 )
-      NEW met2 ( 1636450 1690140 ) ( 1637600 * 0 )
-      NEW met2 ( 1498450 2380 0 ) ( * 31790 )
-      NEW met1 ( 1498450 31790 ) ( 1583550 * )
-      NEW met2 ( 1583550 31790 ) ( * 1580100 )
-      NEW met2 ( 1583550 1580100 ) ( 1584010 * )
-      NEW met2 ( 1584010 1580100 ) ( * 1680110 )
-      NEW met1 ( 1584010 1680110 ) ( 1636450 * )
-      NEW met1 ( 1636450 1680110 ) M1M2_PR
-      NEW met1 ( 1498450 31790 ) M1M2_PR
-      NEW met1 ( 1583550 31790 ) M1M2_PR
-      NEW met1 ( 1584010 1680110 ) M1M2_PR ;
-    - la_data_in[4] ( PIN la_data_in[4] ) ( mprj la_data_in[4] ) + USE SIGNAL
-      + ROUTED met2 ( 700350 2380 0 ) ( * 34500 )
-      NEW met2 ( 700350 34500 ) ( 703570 * )
-      NEW met2 ( 703570 34500 ) ( * 1674670 )
-      NEW met1 ( 703570 1674670 ) ( 1389890 * )
-      NEW met2 ( 1389890 1690140 ) ( 1391040 * 0 )
-      NEW met2 ( 1389890 1674670 ) ( * 1690140 )
-      NEW met1 ( 703570 1674670 ) M1M2_PR
-      NEW met1 ( 1389890 1674670 ) M1M2_PR ;
-    - la_data_in[50] ( PIN la_data_in[50] ) ( mprj la_data_in[50] ) + USE SIGNAL
-      + ROUTED met1 ( 1638750 1678070 ) ( 1642430 * )
-      NEW met2 ( 1642430 1678070 ) ( * 1690140 )
-      NEW met2 ( 1642430 1690140 ) ( 1643120 * 0 )
-      NEW met2 ( 1638750 31450 ) ( * 1678070 )
-      NEW met2 ( 1515930 2380 0 ) ( * 31450 )
-      NEW met1 ( 1515930 31450 ) ( 1638750 * )
-      NEW met1 ( 1638750 31450 ) M1M2_PR
-      NEW met1 ( 1638750 1678070 ) M1M2_PR
-      NEW met1 ( 1642430 1678070 ) M1M2_PR
-      NEW met1 ( 1515930 31450 ) M1M2_PR ;
-    - la_data_in[51] ( PIN la_data_in[51] ) ( mprj la_data_in[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1533870 2380 0 ) ( * 16830 )
-      NEW met2 ( 1643810 16830 ) ( * 1580100 )
-      NEW met2 ( 1643810 1580100 ) ( 1645190 * )
-      NEW met2 ( 1645190 1683340 ) ( 1647490 * )
-      NEW met2 ( 1647490 1683340 ) ( * 1690140 )
-      NEW met2 ( 1647490 1690140 ) ( 1648640 * 0 )
-      NEW met2 ( 1645190 1580100 ) ( * 1683340 )
-      NEW met1 ( 1533870 16830 ) ( 1643810 * )
-      NEW met1 ( 1533870 16830 ) M1M2_PR
-      NEW met1 ( 1643810 16830 ) M1M2_PR ;
-    - la_data_in[52] ( PIN la_data_in[52] ) ( mprj la_data_in[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1551350 2380 0 ) ( * 16490 )
-      NEW met1 ( 1649330 1652570 ) ( 1653010 * )
-      NEW met2 ( 1649330 16490 ) ( * 1652570 )
-      NEW met2 ( 1653010 1690140 ) ( 1654160 * 0 )
-      NEW met2 ( 1653010 1652570 ) ( * 1690140 )
-      NEW met1 ( 1551350 16490 ) ( 1649330 * )
-      NEW met1 ( 1551350 16490 ) M1M2_PR
-      NEW met1 ( 1649330 16490 ) M1M2_PR
-      NEW met1 ( 1649330 1652570 ) M1M2_PR
-      NEW met1 ( 1653010 1652570 ) M1M2_PR ;
-    - la_data_in[53] ( PIN la_data_in[53] ) ( mprj la_data_in[53] ) + USE SIGNAL
-      + ROUTED met2 ( 1569290 2380 0 ) ( * 15470 )
-      NEW met2 ( 1658530 1690140 ) ( 1659220 * 0 )
-      NEW met1 ( 1569290 15470 ) ( 1657150 * )
-      NEW met2 ( 1657150 1631660 ) ( 1658530 * )
-      NEW met2 ( 1657150 15470 ) ( * 1631660 )
-      NEW met2 ( 1658530 1631660 ) ( * 1690140 )
-      NEW met1 ( 1569290 15470 ) M1M2_PR
-      NEW met1 ( 1657150 15470 ) M1M2_PR ;
-    - la_data_in[54] ( PIN la_data_in[54] ) ( mprj la_data_in[54] ) + USE SIGNAL
-      + ROUTED met2 ( 1663130 1683340 ) ( 1663590 * )
-      NEW met2 ( 1663590 1683340 ) ( * 1690140 )
-      NEW met2 ( 1663590 1690140 ) ( 1664740 * 0 )
-      NEW met2 ( 1586770 2380 0 ) ( * 14790 )
-      NEW met1 ( 1586770 14790 ) ( 1663130 * )
-      NEW met2 ( 1663130 14790 ) ( * 1683340 )
-      NEW met1 ( 1663130 14790 ) M1M2_PR
-      NEW met1 ( 1586770 14790 ) M1M2_PR ;
-    - la_data_in[55] ( PIN la_data_in[55] ) ( mprj la_data_in[55] ) + USE SIGNAL
-      + ROUTED li1 ( 1631390 19210 ) ( 1632310 * )
-      NEW met1 ( 1632310 19210 ) ( 1645650 * )
-      NEW met1 ( 1645650 1682490 ) ( 1670030 * )
-      NEW met2 ( 1670030 1682490 ) ( * 1690140 )
-      NEW met2 ( 1670030 1690140 ) ( 1670260 * 0 )
-      NEW met2 ( 1645650 19210 ) ( * 1682490 )
-      NEW met2 ( 1604710 2380 0 ) ( * 19210 )
-      NEW met1 ( 1604710 19210 ) ( 1631390 * )
-      NEW li1 ( 1631390 19210 ) L1M1_PR_MR
-      NEW li1 ( 1632310 19210 ) L1M1_PR_MR
-      NEW met1 ( 1645650 19210 ) M1M2_PR
-      NEW met1 ( 1645650 1682490 ) M1M2_PR
-      NEW met1 ( 1670030 1682490 ) M1M2_PR
-      NEW met1 ( 1604710 19210 ) M1M2_PR ;
-    - la_data_in[56] ( PIN la_data_in[56] ) ( mprj la_data_in[56] ) + USE SIGNAL
-      + ROUTED met1 ( 1631850 18870 ) ( * 19550 )
-      NEW met1 ( 1631850 19550 ) ( 1671410 * )
-      NEW met2 ( 1671410 19550 ) ( * 1580100 )
-      NEW met2 ( 1671410 1580100 ) ( 1674630 * )
-      NEW met2 ( 1674630 1690140 ) ( 1675780 * 0 )
-      NEW met2 ( 1622190 2380 0 ) ( * 18870 )
-      NEW met1 ( 1622190 18870 ) ( 1631850 * )
-      NEW met2 ( 1674630 1580100 ) ( * 1690140 )
-      NEW met1 ( 1671410 19550 ) M1M2_PR
-      NEW met1 ( 1622190 18870 ) M1M2_PR ;
-    - la_data_in[57] ( PIN la_data_in[57] ) ( mprj la_data_in[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1640130 2380 0 ) ( * 3060 )
-      NEW met2 ( 1640130 3060 ) ( 1641050 * )
-      NEW met2 ( 1641050 2380 ) ( * 3060 )
-      NEW met2 ( 1641050 2380 ) ( 1641970 * )
-      NEW met2 ( 1641970 2380 ) ( * 1680110 )
-      NEW met2 ( 1680150 1680110 ) ( * 1690140 )
-      NEW met2 ( 1680150 1690140 ) ( 1681300 * 0 )
-      NEW met1 ( 1641970 1680110 ) ( 1680150 * )
-      NEW met1 ( 1641970 1680110 ) M1M2_PR
-      NEW met1 ( 1680150 1680110 ) M1M2_PR ;
-    - la_data_in[58] ( PIN la_data_in[58] ) ( mprj la_data_in[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1658070 2380 0 ) ( * 17510 )
-      NEW met1 ( 1658070 17510 ) ( 1662670 * )
-      NEW met2 ( 1685670 1676710 ) ( * 1690140 )
-      NEW met2 ( 1685670 1690140 ) ( 1686820 * 0 )
-      NEW met1 ( 1662670 1676710 ) ( 1685670 * )
-      NEW met2 ( 1662670 17510 ) ( * 1676710 )
-      NEW met1 ( 1658070 17510 ) M1M2_PR
-      NEW met1 ( 1662670 17510 ) M1M2_PR
-      NEW met1 ( 1662670 1676710 ) M1M2_PR
-      NEW met1 ( 1685670 1676710 ) M1M2_PR ;
-    - la_data_in[59] ( PIN la_data_in[59] ) ( mprj la_data_in[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1675550 2380 0 ) ( * 17170 )
-      NEW met1 ( 1675550 17170 ) ( 1676700 * )
-      NEW met1 ( 1676700 17170 ) ( * 17850 )
-      NEW met1 ( 1676700 17850 ) ( 1691650 * )
-      NEW met2 ( 1691650 1690140 ) ( 1692340 * 0 )
-      NEW met2 ( 1691650 17850 ) ( * 1690140 )
-      NEW met1 ( 1675550 17170 ) M1M2_PR
-      NEW met1 ( 1691650 17850 ) M1M2_PR ;
-    - la_data_in[5] ( PIN la_data_in[5] ) ( mprj la_data_in[5] ) + USE SIGNAL
-      + ROUTED met2 ( 1385290 1675350 ) ( * 1683170 )
-      NEW met2 ( 717830 2380 0 ) ( * 20910 )
-      NEW met1 ( 717830 20910 ) ( 724270 * )
-      NEW met1 ( 724270 1675350 ) ( 1385290 * )
-      NEW met2 ( 724270 20910 ) ( * 1675350 )
-      NEW met2 ( 1395410 1683170 ) ( * 1690140 )
-      NEW met2 ( 1395410 1690140 ) ( 1396560 * 0 )
-      NEW met1 ( 1385290 1683170 ) ( 1395410 * )
-      NEW met1 ( 1385290 1675350 ) M1M2_PR
-      NEW met1 ( 1385290 1683170 ) M1M2_PR
+      NEW met2 ( 14030 1811180 ) M2M3_PR_M ;
+    - io_in[31] ( PIN io_in[31] ) ( inst_eFPGA_CPU_top io_in[31] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 1575840 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1575840 ) ( * 1575900 )
+      NEW met3 ( 14030 1575900 ) ( 17020 * )
+      NEW met3 ( 1380 1596300 0 ) ( 14030 * )
+      NEW met2 ( 14030 1575900 ) ( * 1596300 )
+      NEW met2 ( 14030 1575900 ) M2M3_PR_M
+      NEW met2 ( 14030 1596300 ) M2M3_PR_M ;
+    - io_in[32] ( PIN io_in[32] ) ( inst_eFPGA_CPU_top io_in[32] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 1339770 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1339770 ) ( * 1339940 )
+      NEW met3 ( 6670 1339940 ) ( 17020 * )
+      NEW met3 ( 1380 1335860 0 ) ( 6670 * )
+      NEW met2 ( 6670 1335860 ) ( * 1339940 )
+      NEW met2 ( 6670 1339940 ) M2M3_PR_M
+      NEW met2 ( 6670 1335860 ) M2M3_PR_M ;
+    - io_in[33] ( PIN io_in[33] ) ( inst_eFPGA_CPU_top io_in[33] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 1074740 0 ) ( 10350 * )
+      NEW met3 ( 17020 1103700 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1103700 ) ( * 1103980 )
+      NEW met3 ( 10350 1103980 ) ( 17020 * )
+      NEW met2 ( 10350 1074740 ) ( * 1103980 )
+      NEW met2 ( 10350 1074740 ) M2M3_PR_M
+      NEW met2 ( 10350 1103980 ) M2M3_PR_M ;
+    - io_in[34] ( PIN io_in[34] ) ( inst_eFPGA_CPU_top io_in[34] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 868240 ) ( 20240 * 0 )
+      NEW met3 ( 17020 868020 ) ( * 868240 )
+      NEW met3 ( 14030 868020 ) ( 17020 * )
+      NEW met3 ( 1380 814300 0 ) ( 14030 * )
+      NEW met2 ( 14030 814300 ) ( * 868020 )
+      NEW met2 ( 14030 868020 ) M2M3_PR_M
+      NEW met2 ( 14030 814300 ) M2M3_PR_M ;
+    - io_in[35] ( PIN io_in[35] ) ( inst_eFPGA_CPU_top io_in[35] ) + USE SIGNAL
+      + ROUTED met3 ( 690 555900 ) ( 1380 * )
+      NEW met3 ( 1380 553860 ) ( * 555900 )
+      NEW met3 ( 1380 553860 ) ( 3220 * )
+      NEW met3 ( 3220 553180 ) ( * 553860 )
+      NEW met3 ( 1380 553180 0 ) ( 3220 * )
+      NEW met3 ( 17020 632170 ) ( 20240 * 0 )
+      NEW met3 ( 17020 632060 ) ( * 632170 )
+      NEW met3 ( 690 632060 ) ( 17020 * )
+      NEW met2 ( 690 555900 ) ( * 632060 )
+      NEW met2 ( 690 555900 ) M2M3_PR_M
+      NEW met2 ( 690 632060 ) M2M3_PR_M ;
+    - io_in[36] ( PIN io_in[36] ) ( inst_eFPGA_CPU_top io_in[36] ) + USE SIGNAL
+      + ROUTED met3 ( 14030 396100 ) ( 20240 * 0 )
+      NEW met3 ( 1380 358020 0 ) ( 14030 * )
+      NEW met2 ( 14030 358020 ) ( * 396100 )
+      NEW met2 ( 14030 396100 ) M2M3_PR_M
+      NEW met2 ( 14030 358020 ) M2M3_PR_M ;
+    - io_in[37] ( PIN io_in[37] ) ( inst_eFPGA_CPU_top io_in[37] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 160030 ) ( 20240 * 0 )
+      NEW met3 ( 17020 160030 ) ( * 162180 )
+      NEW met3 ( 1380 162180 0 ) ( 17020 * ) ;
+    - io_in[3] ( PIN io_in[3] ) ( inst_eFPGA_CPU_top io_in[3] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 630020 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 819740 ) ( 2908810 * )
+      NEW met3 ( 2903980 819740 ) ( * 820050 )
+      NEW met3 ( 2901220 820050 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 630020 ) ( * 819740 )
+      NEW met2 ( 2908810 630020 ) M2M3_PR_M
+      NEW met2 ( 2908810 819740 ) M2M3_PR_M ;
+    - io_in[4] ( PIN io_in[4] ) ( inst_eFPGA_CPU_top io_in[4] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 829260 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1039380 ) ( 2908810 * )
+      NEW met3 ( 2903980 1039380 ) ( * 1039650 )
+      NEW met3 ( 2901220 1039650 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 829260 ) ( * 1039380 )
+      NEW met2 ( 2908810 829260 ) M2M3_PR_M
+      NEW met2 ( 2908810 1039380 ) M2M3_PR_M ;
+    - io_in[5] ( PIN io_in[5] ) ( inst_eFPGA_CPU_top io_in[5] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 1259020 ) ( 2909270 * )
+      NEW met3 ( 2903980 1259020 ) ( * 1259250 )
+      NEW met3 ( 2901220 1259250 0 ) ( 2903980 * )
+      NEW met3 ( 2909270 1028500 ) ( 2917780 * 0 )
+      NEW met2 ( 2909270 1028500 ) ( * 1259020 )
+      NEW met2 ( 2909270 1259020 ) M2M3_PR_M
+      NEW met2 ( 2909270 1028500 ) M2M3_PR_M ;
+    - io_in[6] ( PIN io_in[6] ) ( inst_eFPGA_CPU_top io_in[6] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 1479340 ) ( 2908350 * )
+      NEW met3 ( 2903980 1479340 ) ( * 1479460 )
+      NEW met3 ( 2901220 1479460 0 ) ( 2903980 * )
+      NEW met3 ( 2908350 1227740 ) ( 2917780 * 0 )
+      NEW met2 ( 2908350 1227740 ) ( * 1479340 )
+      NEW met2 ( 2908350 1479340 ) M2M3_PR_M
+      NEW met2 ( 2908350 1227740 ) M2M3_PR_M ;
+    - io_in[7] ( PIN io_in[7] ) ( inst_eFPGA_CPU_top io_in[7] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 1493620 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1698980 ) ( 2908810 * )
+      NEW met3 ( 2903980 1698980 ) ( * 1699060 )
+      NEW met3 ( 2901220 1699060 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 1493620 ) ( * 1698980 )
+      NEW met2 ( 2908810 1493620 ) M2M3_PR_M
+      NEW met2 ( 2908810 1698980 ) M2M3_PR_M ;
+    - io_in[8] ( PIN io_in[8] ) ( inst_eFPGA_CPU_top io_in[8] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 1759500 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1918620 ) ( 2908810 * )
+      NEW met3 ( 2903980 1918620 ) ( * 1918660 )
+      NEW met3 ( 2901220 1918660 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 1759500 ) ( * 1918620 )
+      NEW met2 ( 2908810 1759500 ) M2M3_PR_M
+      NEW met2 ( 2908810 1918620 ) M2M3_PR_M ;
+    - io_in[9] ( PIN io_in[9] ) ( inst_eFPGA_CPU_top io_in[9] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 2024700 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 2138940 ) ( 2908810 * )
+      NEW met3 ( 2903980 2138870 ) ( * 2138940 )
+      NEW met3 ( 2901220 2138870 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 2024700 ) ( * 2138940 )
+      NEW met2 ( 2908810 2024700 ) M2M3_PR_M
+      NEW met2 ( 2908810 2138940 ) M2M3_PR_M ;
+    - io_oeb[0] ( PIN io_oeb[0] ) ( inst_eFPGA_CPU_top io_oeb[0] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 307020 ) ( 2908350 * )
+      NEW met3 ( 2903980 307020 ) ( * 307040 )
+      NEW met3 ( 2901220 307040 0 ) ( 2903980 * )
+      NEW met3 ( 2908350 165580 ) ( 2917780 * 0 )
+      NEW met2 ( 2908350 165580 ) ( * 307020 )
+      NEW met2 ( 2908350 307020 ) M2M3_PR_M
+      NEW met2 ( 2908350 165580 ) M2M3_PR_M ;
+    - io_oeb[10] ( PIN io_oeb[10] ) ( inst_eFPGA_CPU_top io_oeb[10] ) + USE SIGNAL
+      + ROUTED met3 ( 2901910 2423180 ) ( 2917780 * 0 )
+      NEW met3 ( 2901220 2504870 0 ) ( 2901910 * )
+      NEW met2 ( 2901910 2423180 ) ( * 2504870 )
+      NEW met2 ( 2901910 2423180 ) M2M3_PR_M
+      NEW met2 ( 2901910 2504870 ) M2M3_PR_M ;
+    - io_oeb[11] ( PIN io_oeb[11] ) ( inst_eFPGA_CPU_top io_oeb[11] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 2724470 0 ) ( 2901910 * )
+      NEW met3 ( 2901910 2689060 ) ( 2917780 * 0 )
+      NEW met2 ( 2901910 2689060 ) ( * 2724470 )
+      NEW met2 ( 2901910 2724470 ) M2M3_PR_M
+      NEW met2 ( 2901910 2689060 ) M2M3_PR_M ;
+    - io_oeb[12] ( PIN io_oeb[12] ) ( inst_eFPGA_CPU_top io_oeb[12] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 2944680 0 ) ( 2903980 * )
+      NEW met3 ( 2903980 2944680 ) ( * 2944740 )
+      NEW met3 ( 2903980 2944740 ) ( 2912030 * )
+      NEW met2 ( 2912030 2944740 ) ( * 2954940 )
+      NEW met3 ( 2912030 2954940 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 2944740 ) M2M3_PR_M
+      NEW met2 ( 2912030 2954940 ) M2M3_PR_M ;
+    - io_oeb[13] ( PIN io_oeb[13] ) ( inst_eFPGA_CPU_top io_oeb[13] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 3220140 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 3164380 ) ( 2912030 * )
+      NEW met3 ( 2903980 3164280 ) ( * 3164380 )
+      NEW met3 ( 2901220 3164280 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 3164380 ) ( * 3220140 )
+      NEW met2 ( 2912030 3220140 ) M2M3_PR_M
+      NEW met2 ( 2912030 3164380 ) M2M3_PR_M ;
+    - io_oeb[14] ( PIN io_oeb[14] ) ( inst_eFPGA_CPU_top io_oeb[14] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 3383880 0 ) ( 2901910 * )
+      NEW met3 ( 2901910 3486020 ) ( 2917780 * 0 )
+      NEW met2 ( 2901910 3383880 ) ( * 3486020 )
+      NEW met2 ( 2901910 3383880 ) M2M3_PR_M
+      NEW met2 ( 2901910 3486020 ) M2M3_PR_M ;
+    - io_oeb[15] ( PIN io_oeb[15] ) ( inst_eFPGA_CPU_top io_oeb[15] ) + USE SIGNAL
+      + ROUTED met2 ( 2636030 3404930 ) ( * 3517980 0 )
+      NEW met2 ( 2670750 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2670530 3394220 ) ( 2670750 * )
+      NEW met2 ( 2670530 3394220 ) ( * 3404930 )
+      NEW met1 ( 2636030 3404930 ) ( 2670530 * )
+      NEW met1 ( 2636030 3404930 ) M1M2_PR
+      NEW met1 ( 2670530 3404930 ) M1M2_PR ;
+    - io_oeb[16] ( PIN io_oeb[16] ) ( inst_eFPGA_CPU_top io_oeb[16] ) + USE SIGNAL
+      + ROUTED met2 ( 2340930 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2340710 3394220 ) ( 2340930 * )
+      NEW met2 ( 2340710 3394220 ) ( * 3404590 )
+      NEW met1 ( 2311730 3404590 ) ( 2340710 * )
+      NEW met2 ( 2311730 3404590 ) ( * 3517980 0 )
+      NEW met1 ( 2340710 3404590 ) M1M2_PR
+      NEW met1 ( 2311730 3404590 ) M1M2_PR ;
+    - io_oeb[17] ( PIN io_oeb[17] ) ( inst_eFPGA_CPU_top io_oeb[17] ) + USE SIGNAL
+      + ROUTED met2 ( 2010650 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2010430 3394220 ) ( 2010650 * )
+      NEW met2 ( 2010430 3394220 ) ( * 3404590 )
+      NEW met1 ( 1987430 3404590 ) ( 2010430 * )
+      NEW met2 ( 1987430 3404590 ) ( * 3517980 0 )
+      NEW met1 ( 2010430 3404590 ) M1M2_PR
+      NEW met1 ( 1987430 3404590 ) M1M2_PR ;
+    - io_oeb[18] ( PIN io_oeb[18] ) ( inst_eFPGA_CPU_top io_oeb[18] ) + USE SIGNAL
+      + ROUTED met1 ( 1656230 3515090 ) ( 1662670 * )
+      NEW met2 ( 1662670 3515090 ) ( * 3517980 0 )
+      NEW met2 ( 1656230 3405270 ) ( * 3515090 )
+      NEW met2 ( 1680370 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1680150 3394220 ) ( 1680370 * )
+      NEW met2 ( 1680150 3394220 ) ( * 3405270 )
+      NEW met1 ( 1656230 3405270 ) ( 1680150 * )
+      NEW met1 ( 1656230 3405270 ) M1M2_PR
+      NEW met1 ( 1656230 3515090 ) M1M2_PR
+      NEW met1 ( 1662670 3515090 ) M1M2_PR
+      NEW met1 ( 1680150 3405270 ) M1M2_PR ;
+    - io_oeb[19] ( PIN io_oeb[19] ) ( inst_eFPGA_CPU_top io_oeb[19] ) + USE SIGNAL
+      + ROUTED met2 ( 1350550 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1350330 3394220 ) ( 1350550 * )
+      NEW met2 ( 1350330 3394220 ) ( * 3405270 )
+      NEW met1 ( 1331930 3405270 ) ( 1350330 * )
+      NEW met1 ( 1331930 3487890 ) ( 1338370 * )
+      NEW met2 ( 1331930 3405270 ) ( * 3487890 )
+      NEW met2 ( 1338370 3487890 ) ( * 3517980 0 )
+      NEW met1 ( 1350330 3405270 ) M1M2_PR
+      NEW met1 ( 1331930 3405270 ) M1M2_PR
+      NEW met1 ( 1331930 3487890 ) M1M2_PR
+      NEW met1 ( 1338370 3487890 ) M1M2_PR ;
+    - io_oeb[1] ( PIN io_oeb[1] ) ( inst_eFPGA_CPU_top io_oeb[1] ) + USE SIGNAL
+      + ROUTED met3 ( 2908350 364820 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 526660 ) ( 2908350 * )
+      NEW met3 ( 2903980 526640 ) ( * 526660 )
+      NEW met3 ( 2901220 526640 0 ) ( 2903980 * )
+      NEW met2 ( 2908350 364820 ) ( * 526660 )
+      NEW met2 ( 2908350 364820 ) M2M3_PR_M
+      NEW met2 ( 2908350 526660 ) M2M3_PR_M ;
+    - io_oeb[20] ( PIN io_oeb[20] ) ( inst_eFPGA_CPU_top io_oeb[20] ) + USE SIGNAL
+      + ROUTED met2 ( 1020270 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1020050 3394220 ) ( 1020270 * )
+      NEW met2 ( 1020050 3394220 ) ( * 3404590 )
+      NEW met1 ( 1007630 3404590 ) ( 1020050 * )
+      NEW met1 ( 1007630 3515090 ) ( 1014070 * )
+      NEW met2 ( 1014070 3515090 ) ( * 3517980 0 )
+      NEW met2 ( 1007630 3404590 ) ( * 3515090 )
+      NEW met1 ( 1020050 3404590 ) M1M2_PR
+      NEW met1 ( 1007630 3404590 ) M1M2_PR
+      NEW met1 ( 1007630 3515090 ) M1M2_PR
+      NEW met1 ( 1014070 3515090 ) M1M2_PR ;
+    - io_oeb[21] ( PIN io_oeb[21] ) ( inst_eFPGA_CPU_top io_oeb[21] ) + USE SIGNAL
+      + ROUTED met2 ( 690450 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 690230 3394220 ) ( 690450 * )
+      NEW met2 ( 690230 3394220 ) ( * 3404590 )
+      NEW met1 ( 683330 3404590 ) ( 690230 * )
+      NEW met2 ( 683330 3517980 ) ( 688390 * )
+      NEW met2 ( 688390 3517300 ) ( * 3517980 )
+      NEW met2 ( 688390 3517300 ) ( 689310 * )
+      NEW met2 ( 689310 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 683330 3404590 ) ( * 3517980 )
+      NEW met1 ( 690230 3404590 ) M1M2_PR
+      NEW met1 ( 683330 3404590 ) M1M2_PR ;
+    - io_oeb[22] ( PIN io_oeb[22] ) ( inst_eFPGA_CPU_top io_oeb[22] ) + USE SIGNAL
+      + ROUTED met2 ( 360170 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 359030 3394220 ) ( 360170 * )
+      NEW met1 ( 359030 3515090 ) ( 365010 * )
+      NEW met2 ( 365010 3515090 ) ( * 3517980 0 )
+      NEW met2 ( 359030 3394220 ) ( * 3515090 )
+      NEW met1 ( 359030 3515090 ) M1M2_PR
+      NEW met1 ( 365010 3515090 ) M1M2_PR ;
+    - io_oeb[23] ( PIN io_oeb[23] ) ( inst_eFPGA_CPU_top io_oeb[23] ) + USE SIGNAL
+      + ROUTED met2 ( 30350 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 30350 3394220 ) ( 30590 * )
+      NEW met2 ( 30590 3394220 ) ( * 3408330 )
+      NEW met1 ( 30590 3408330 ) ( 34730 * )
+      NEW met2 ( 34730 3517980 ) ( 39790 * )
+      NEW met2 ( 39790 3517300 ) ( * 3517980 )
+      NEW met2 ( 39790 3517300 ) ( 40710 * )
+      NEW met2 ( 40710 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 34730 3408330 ) ( * 3517980 )
+      NEW met1 ( 30590 3408330 ) M1M2_PR
+      NEW met1 ( 34730 3408330 ) M1M2_PR ;
+    - io_oeb[24] ( PIN io_oeb[24] ) ( inst_eFPGA_CPU_top io_oeb[24] ) + USE SIGNAL
+      + ROUTED met1 ( 690 3291030 ) ( 2990 * )
+      NEW met2 ( 2990 3290860 ) ( * 3291030 )
+      NEW met3 ( 1380 3290860 0 ) ( 2990 * )
+      NEW met3 ( 17020 3383880 ) ( 20240 * 0 )
+      NEW met3 ( 17020 3383880 ) ( * 3384020 )
+      NEW met3 ( 690 3384020 ) ( 17020 * )
+      NEW met2 ( 690 3291030 ) ( * 3384020 )
+      NEW met1 ( 690 3291030 ) M1M2_PR
+      NEW met1 ( 2990 3291030 ) M1M2_PR
+      NEW met2 ( 2990 3290860 ) M2M3_PR_M
+      NEW met2 ( 690 3384020 ) M2M3_PR_M ;
+    - io_oeb[25] ( PIN io_oeb[25] ) ( inst_eFPGA_CPU_top io_oeb[25] ) + USE SIGNAL
+      + ROUTED met3 ( 690 3033140 ) ( 1380 * )
+      NEW met3 ( 1380 3031100 ) ( * 3033140 )
+      NEW met3 ( 1380 3031100 ) ( 3220 * )
+      NEW met3 ( 3220 3030420 ) ( * 3031100 )
+      NEW met3 ( 1380 3030420 0 ) ( 3220 * )
+      NEW met3 ( 18860 3148420 ) ( 20240 * 0 )
+      NEW met3 ( 18860 3148060 ) ( * 3148420 )
+      NEW met3 ( 690 3148060 ) ( 18860 * )
+      NEW met2 ( 690 3033140 ) ( * 3148060 )
+      NEW met2 ( 690 3033140 ) M2M3_PR_M
+      NEW met2 ( 690 3148060 ) M2M3_PR_M ;
+    - io_oeb[26] ( PIN io_oeb[26] ) ( inst_eFPGA_CPU_top io_oeb[26] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 2912350 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2912100 ) ( * 2912350 )
+      NEW met3 ( 230 2912100 ) ( 17020 * )
+      NEW met3 ( 230 2772020 ) ( 460 * )
+      NEW met3 ( 460 2769980 ) ( * 2772020 )
+      NEW met3 ( 460 2769980 ) ( 3220 * )
+      NEW met3 ( 3220 2769300 ) ( * 2769980 )
+      NEW met3 ( 1380 2769300 0 ) ( 3220 * )
+      NEW met2 ( 230 2772020 ) ( * 2912100 )
+      NEW met2 ( 230 2912100 ) M2M3_PR_M
+      NEW met2 ( 230 2772020 ) M2M3_PR_M ;
+    - io_oeb[27] ( PIN io_oeb[27] ) ( inst_eFPGA_CPU_top io_oeb[27] ) + USE SIGNAL
+      + ROUTED met3 ( 230 2511580 ) ( 460 * )
+      NEW met3 ( 460 2509540 ) ( * 2511580 )
+      NEW met3 ( 460 2509540 ) ( 3220 * )
+      NEW met3 ( 3220 2508860 ) ( * 2509540 )
+      NEW met3 ( 1380 2508860 0 ) ( 3220 * )
+      NEW met3 ( 17020 2676280 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2676140 ) ( * 2676280 )
+      NEW met3 ( 230 2676140 ) ( 17020 * )
+      NEW met2 ( 230 2511580 ) ( * 2676140 )
+      NEW met2 ( 230 2511580 ) M2M3_PR_M
+      NEW met2 ( 230 2676140 ) M2M3_PR_M ;
+    - io_oeb[28] ( PIN io_oeb[28] ) ( inst_eFPGA_CPU_top io_oeb[28] ) + USE SIGNAL
+      + ROUTED met3 ( 230 2249100 ) ( 460 * )
+      NEW met3 ( 460 2248420 ) ( * 2249100 )
+      NEW met3 ( 460 2248420 ) ( 3220 * )
+      NEW met3 ( 3220 2247740 ) ( * 2248420 )
+      NEW met3 ( 1380 2247740 0 ) ( 3220 * )
+      NEW met3 ( 17020 2440820 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2440820 ) ( * 2440860 )
+      NEW met3 ( 230 2440860 ) ( 17020 * )
+      NEW met2 ( 230 2249100 ) ( * 2440860 )
+      NEW met2 ( 230 2249100 ) M2M3_PR_M
+      NEW met2 ( 230 2440860 ) M2M3_PR_M ;
+    - io_oeb[29] ( PIN io_oeb[29] ) ( inst_eFPGA_CPU_top io_oeb[29] ) + USE SIGNAL
+      + ROUTED met3 ( 230 1990020 ) ( 460 * )
+      NEW met3 ( 460 1987980 ) ( * 1990020 )
+      NEW met3 ( 460 1987980 ) ( 3220 * )
+      NEW met3 ( 3220 1987300 ) ( * 1987980 )
+      NEW met3 ( 1380 1987300 0 ) ( 3220 * )
+      NEW met3 ( 17020 2204750 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2204750 ) ( * 2204900 )
+      NEW met3 ( 230 2204900 ) ( 17020 * )
+      NEW met2 ( 230 1990020 ) ( * 2204900 )
+      NEW met2 ( 230 1990020 ) M2M3_PR_M
+      NEW met2 ( 230 2204900 ) M2M3_PR_M ;
+    - io_oeb[2] ( PIN io_oeb[2] ) ( inst_eFPGA_CPU_top io_oeb[2] ) + USE SIGNAL
+      + ROUTED met3 ( 2908350 564060 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 746300 ) ( 2908350 * )
+      NEW met3 ( 2903980 746240 ) ( * 746300 )
+      NEW met3 ( 2901220 746240 0 ) ( 2903980 * )
+      NEW met2 ( 2908350 564060 ) ( * 746300 )
+      NEW met2 ( 2908350 564060 ) M2M3_PR_M
+      NEW met2 ( 2908350 746300 ) M2M3_PR_M ;
+    - io_oeb[30] ( PIN io_oeb[30] ) ( inst_eFPGA_CPU_top io_oeb[30] ) + USE SIGNAL
+      + ROUTED met3 ( 690 1729580 ) ( 1380 * )
+      NEW met3 ( 1380 1727540 ) ( * 1729580 )
+      NEW met3 ( 1380 1727540 ) ( 3220 * )
+      NEW met3 ( 3220 1726860 ) ( * 1727540 )
+      NEW met3 ( 1380 1726860 0 ) ( 3220 * )
+      NEW met3 ( 17020 1968680 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1968680 ) ( * 1968940 )
+      NEW met3 ( 690 1968940 ) ( 17020 * )
+      NEW met2 ( 690 1729580 ) ( * 1968940 )
+      NEW met2 ( 690 1729580 ) M2M3_PR_M
+      NEW met2 ( 690 1968940 ) M2M3_PR_M ;
+    - io_oeb[31] ( PIN io_oeb[31] ) ( inst_eFPGA_CPU_top io_oeb[31] ) + USE SIGNAL
+      + ROUTED met3 ( 230 1468460 ) ( 460 * )
+      NEW met3 ( 460 1466420 ) ( * 1468460 )
+      NEW met3 ( 460 1466420 ) ( 3220 * )
+      NEW met3 ( 3220 1465740 ) ( * 1466420 )
+      NEW met3 ( 1380 1465740 0 ) ( 3220 * )
+      NEW met3 ( 17020 1733220 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1732980 ) ( * 1733220 )
+      NEW met3 ( 230 1732980 ) ( 17020 * )
+      NEW met2 ( 230 1468460 ) ( * 1732980 )
+      NEW met2 ( 230 1468460 ) M2M3_PR_M
+      NEW met2 ( 230 1732980 ) M2M3_PR_M ;
+    - io_oeb[32] ( PIN io_oeb[32] ) ( inst_eFPGA_CPU_top io_oeb[32] ) + USE SIGNAL
+      + ROUTED met3 ( 690 1207340 ) ( 1380 * )
+      NEW met3 ( 1380 1205980 ) ( * 1207340 )
+      NEW met3 ( 1380 1205980 ) ( 3220 * )
+      NEW met3 ( 3220 1205300 ) ( * 1205980 )
+      NEW met3 ( 1380 1205300 0 ) ( 3220 * )
+      NEW met3 ( 17020 1497150 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1497020 ) ( * 1497150 )
+      NEW met3 ( 690 1497020 ) ( 17020 * )
+      NEW met2 ( 690 1207340 ) ( * 1497020 )
+      NEW met2 ( 690 1207340 ) M2M3_PR_M
+      NEW met2 ( 690 1497020 ) M2M3_PR_M ;
+    - io_oeb[33] ( PIN io_oeb[33] ) ( inst_eFPGA_CPU_top io_oeb[33] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 1261080 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1261060 ) ( * 1261080 )
+      NEW met3 ( 230 1261060 ) ( 17020 * )
+      NEW met3 ( 230 945540 ) ( 460 * )
+      NEW met3 ( 460 944860 ) ( * 945540 )
+      NEW met3 ( 460 944860 ) ( 3220 * )
+      NEW met3 ( 3220 944180 ) ( * 944860 )
+      NEW met3 ( 1380 944180 0 ) ( 3220 * )
+      NEW met2 ( 230 945540 ) ( * 1261060 )
+      NEW met2 ( 230 1261060 ) M2M3_PR_M
+      NEW met2 ( 230 945540 ) M2M3_PR_M ;
+    - io_oeb[34] ( PIN io_oeb[34] ) ( inst_eFPGA_CPU_top io_oeb[34] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 683740 0 ) ( 10350 * )
+      NEW met3 ( 17020 1025010 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1025010 ) ( * 1025100 )
+      NEW met3 ( 10350 1025100 ) ( 17020 * )
+      NEW met2 ( 10350 683740 ) ( * 1025100 )
+      NEW met2 ( 10350 683740 ) M2M3_PR_M
+      NEW met2 ( 10350 1025100 ) M2M3_PR_M ;
+    - io_oeb[35] ( PIN io_oeb[35] ) ( inst_eFPGA_CPU_top io_oeb[35] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 789550 ) ( 20240 * 0 )
+      NEW met3 ( 17020 789550 ) ( * 789820 )
+      NEW met3 ( 230 789820 ) ( 17020 * )
+      NEW met3 ( 230 426020 ) ( 460 * )
+      NEW met3 ( 460 423980 ) ( * 426020 )
+      NEW met3 ( 460 423980 ) ( 3220 * )
+      NEW met3 ( 3220 423300 ) ( * 423980 )
+      NEW met3 ( 1380 423300 0 ) ( 3220 * )
+      NEW met2 ( 230 426020 ) ( * 789820 )
+      NEW met2 ( 230 789820 ) M2M3_PR_M
+      NEW met2 ( 230 426020 ) M2M3_PR_M ;
+    - io_oeb[36] ( PIN io_oeb[36] ) ( inst_eFPGA_CPU_top io_oeb[36] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 227460 0 ) ( 10350 * )
+      NEW met3 ( 17020 553480 ) ( 20240 * 0 )
+      NEW met3 ( 17020 553180 ) ( * 553480 )
+      NEW met3 ( 10350 553180 ) ( 17020 * )
+      NEW met2 ( 10350 227460 ) ( * 553180 )
+      NEW met2 ( 10350 227460 ) M2M3_PR_M
+      NEW met2 ( 10350 553180 ) M2M3_PR_M ;
+    - io_oeb[37] ( PIN io_oeb[37] ) ( inst_eFPGA_CPU_top io_oeb[37] ) + USE SIGNAL
+      + ROUTED met3 ( 230 33660 ) ( 460 * )
+      NEW met3 ( 460 32980 ) ( * 33660 )
+      NEW met3 ( 460 32980 ) ( 3220 * )
+      NEW met3 ( 3220 32300 ) ( * 32980 )
+      NEW met3 ( 1380 32300 0 ) ( 3220 * )
+      NEW met3 ( 18860 317410 ) ( 20240 * 0 )
+      NEW met3 ( 18860 317410 ) ( * 317900 )
+      NEW met3 ( 230 317900 ) ( 18860 * )
+      NEW met2 ( 230 33660 ) ( * 317900 )
+      NEW met2 ( 230 33660 ) M2M3_PR_M
+      NEW met2 ( 230 317900 ) M2M3_PR_M ;
+    - io_oeb[3] ( PIN io_oeb[3] ) ( inst_eFPGA_CPU_top io_oeb[3] ) + USE SIGNAL
+      + ROUTED met3 ( 2909270 763300 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 966620 ) ( 2909270 * )
+      NEW met3 ( 2903980 966450 ) ( * 966620 )
+      NEW met3 ( 2901220 966450 0 ) ( 2903980 * )
+      NEW met2 ( 2909270 763300 ) ( * 966620 )
+      NEW met2 ( 2909270 763300 ) M2M3_PR_M
+      NEW met2 ( 2909270 966620 ) M2M3_PR_M ;
+    - io_oeb[4] ( PIN io_oeb[4] ) ( inst_eFPGA_CPU_top io_oeb[4] ) + USE SIGNAL
+      + ROUTED met3 ( 2908350 962540 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1186260 ) ( 2908350 * )
+      NEW met3 ( 2903980 1186050 ) ( * 1186260 )
+      NEW met3 ( 2901220 1186050 0 ) ( 2903980 * )
+      NEW met2 ( 2908350 962540 ) ( * 1186260 )
+      NEW met2 ( 2908350 962540 ) M2M3_PR_M
+      NEW met2 ( 2908350 1186260 ) M2M3_PR_M ;
+    - io_oeb[5] ( PIN io_oeb[5] ) ( inst_eFPGA_CPU_top io_oeb[5] ) + USE SIGNAL
+      + ROUTED met3 ( 2908810 1161780 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1405220 ) ( 2908810 * )
+      NEW met3 ( 2903980 1405220 ) ( * 1405650 )
+      NEW met3 ( 2901220 1405650 0 ) ( 2903980 * )
+      NEW met2 ( 2908810 1161780 ) ( * 1405220 )
+      NEW met2 ( 2908810 1161780 ) M2M3_PR_M
+      NEW met2 ( 2908810 1405220 ) M2M3_PR_M ;
+    - io_oeb[6] ( PIN io_oeb[6] ) ( inst_eFPGA_CPU_top io_oeb[6] ) + USE SIGNAL
+      + ROUTED met3 ( 2912490 1361020 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1625540 ) ( 2912490 * )
+      NEW met3 ( 2903980 1625540 ) ( * 1625860 )
+      NEW met3 ( 2901220 1625860 0 ) ( 2903980 * )
+      NEW met2 ( 2912490 1361020 ) ( * 1625540 )
+      NEW met2 ( 2912490 1361020 ) M2M3_PR_M
+      NEW met2 ( 2912490 1625540 ) M2M3_PR_M ;
+    - io_oeb[7] ( PIN io_oeb[7] ) ( inst_eFPGA_CPU_top io_oeb[7] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 1845180 ) ( 2908350 * )
+      NEW met3 ( 2903980 1845180 ) ( * 1845460 )
+      NEW met3 ( 2901220 1845460 0 ) ( 2903980 * )
+      NEW met3 ( 2908350 1626220 ) ( 2917780 * 0 )
+      NEW met2 ( 2908350 1626220 ) ( * 1845180 )
+      NEW met2 ( 2908350 1845180 ) M2M3_PR_M
+      NEW met2 ( 2908350 1626220 ) M2M3_PR_M ;
+    - io_oeb[8] ( PIN io_oeb[8] ) ( inst_eFPGA_CPU_top io_oeb[8] ) + USE SIGNAL
+      + ROUTED met3 ( 2908350 1892100 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 2064820 ) ( 2908350 * )
+      NEW met3 ( 2903980 2064820 ) ( * 2065060 )
+      NEW met3 ( 2901220 2065060 0 ) ( 2903980 * )
+      NEW met2 ( 2908350 1892100 ) ( * 2064820 )
+      NEW met2 ( 2908350 1892100 ) M2M3_PR_M
+      NEW met2 ( 2908350 2064820 ) M2M3_PR_M ;
+    - io_oeb[9] ( PIN io_oeb[9] ) ( inst_eFPGA_CPU_top io_oeb[9] ) + USE SIGNAL
+      + ROUTED met3 ( 2908350 2157980 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 2285140 ) ( 2908350 * )
+      NEW met3 ( 2903980 2285140 ) ( * 2285270 )
+      NEW met3 ( 2901220 2285270 0 ) ( 2903980 * )
+      NEW met2 ( 2908350 2157980 ) ( * 2285140 )
+      NEW met2 ( 2908350 2157980 ) M2M3_PR_M
+      NEW met2 ( 2908350 2285140 ) M2M3_PR_M ;
+    - io_out[0] ( PIN io_out[0] ) ( inst_eFPGA_CPU_top io_out[0] ) + USE SIGNAL
+      + ROUTED met3 ( 2912490 98940 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 233580 ) ( 2912490 * )
+      NEW met3 ( 2903980 233580 ) ( * 233840 )
+      NEW met3 ( 2901220 233840 0 ) ( 2903980 * )
+      NEW met2 ( 2912490 98940 ) ( * 233580 )
+      NEW met2 ( 2912490 98940 ) M2M3_PR_M
+      NEW met2 ( 2912490 233580 ) M2M3_PR_M ;
+    - io_out[10] ( PIN io_out[10] ) ( inst_eFPGA_CPU_top io_out[10] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 2431670 0 ) ( 2902370 * )
+      NEW met3 ( 2902370 2357220 ) ( 2917780 * 0 )
+      NEW met2 ( 2902370 2357220 ) ( * 2431670 )
+      NEW met2 ( 2902370 2431670 ) M2M3_PR_M
+      NEW met2 ( 2902370 2357220 ) M2M3_PR_M ;
+    - io_out[11] ( PIN io_out[11] ) ( inst_eFPGA_CPU_top io_out[11] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 2622420 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 2650980 ) ( 2912030 * )
+      NEW met3 ( 2903980 2650980 ) ( * 2651270 )
+      NEW met3 ( 2901220 2651270 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 2622420 ) ( * 2650980 )
+      NEW met2 ( 2912030 2622420 ) M2M3_PR_M
+      NEW met2 ( 2912030 2650980 ) M2M3_PR_M ;
+    - io_out[12] ( PIN io_out[12] ) ( inst_eFPGA_CPU_top io_out[12] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 2888300 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 2871300 ) ( 2912030 * )
+      NEW met3 ( 2903980 2871300 ) ( * 2871480 )
+      NEW met3 ( 2901220 2871480 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 2871300 ) ( * 2888300 )
+      NEW met2 ( 2912030 2888300 ) M2M3_PR_M
+      NEW met2 ( 2912030 2871300 ) M2M3_PR_M ;
+    - io_out[13] ( PIN io_out[13] ) ( inst_eFPGA_CPU_top io_out[13] ) + USE SIGNAL
+      + ROUTED met3 ( 2901220 3091080 0 ) ( 2901910 * )
+      NEW met3 ( 2901910 3154180 ) ( 2917780 * 0 )
+      NEW met2 ( 2901910 3091080 ) ( * 3154180 )
+      NEW met2 ( 2901910 3091080 ) M2M3_PR_M
+      NEW met2 ( 2901910 3154180 ) M2M3_PR_M ;
+    - io_out[14] ( PIN io_out[14] ) ( inst_eFPGA_CPU_top io_out[14] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 3310580 ) ( 2912030 * )
+      NEW met3 ( 2903980 3310580 ) ( * 3310680 )
+      NEW met3 ( 2901220 3310680 0 ) ( 2903980 * )
+      NEW met3 ( 2912030 3419380 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 3310580 ) ( * 3419380 )
+      NEW met2 ( 2912030 3310580 ) M2M3_PR_M
+      NEW met2 ( 2912030 3419380 ) M2M3_PR_M ;
+    - io_out[15] ( PIN io_out[15] ) ( inst_eFPGA_CPU_top io_out[15] ) + USE SIGNAL
+      + ROUTED met2 ( 2711930 3404930 ) ( * 3512100 )
+      NEW met2 ( 2711930 3512100 ) ( 2717450 * )
+      NEW met2 ( 2717450 3512100 ) ( * 3517980 0 )
+      NEW met2 ( 2780690 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2780470 3394220 ) ( 2780690 * )
+      NEW met2 ( 2780470 3394220 ) ( * 3404930 )
+      NEW met1 ( 2711930 3404930 ) ( 2780470 * )
+      NEW met1 ( 2711930 3404930 ) M1M2_PR
+      NEW met1 ( 2780470 3404930 ) M1M2_PR ;
+    - io_out[16] ( PIN io_out[16] ) ( inst_eFPGA_CPU_top io_out[16] ) + USE SIGNAL
+      + ROUTED met2 ( 2450870 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2450650 3394220 ) ( 2450870 * )
+      NEW met2 ( 2450650 3394220 ) ( * 3404930 )
+      NEW met1 ( 2387630 3404930 ) ( 2450650 * )
+      NEW met2 ( 2387630 3404930 ) ( * 3512100 )
+      NEW met2 ( 2387630 3512100 ) ( 2392690 * )
+      NEW met2 ( 2392690 3512100 ) ( * 3517980 0 )
+      NEW met1 ( 2387630 3404930 ) M1M2_PR
+      NEW met1 ( 2450650 3404930 ) M1M2_PR ;
+    - io_out[17] ( PIN io_out[17] ) ( inst_eFPGA_CPU_top io_out[17] ) + USE SIGNAL
+      + ROUTED met2 ( 2120590 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 2120370 3394220 ) ( 2120590 * )
+      NEW met2 ( 2120370 3394220 ) ( * 3404930 )
+      NEW met1 ( 2063330 3404930 ) ( 2120370 * )
+      NEW met2 ( 2063330 3517980 ) ( 2067470 * )
+      NEW met2 ( 2067470 3517300 ) ( * 3517980 )
+      NEW met2 ( 2067470 3517300 ) ( 2068390 * )
+      NEW met2 ( 2068390 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 2063330 3404930 ) ( * 3517980 )
+      NEW met1 ( 2120370 3404930 ) M1M2_PR
+      NEW met1 ( 2063330 3404930 ) M1M2_PR ;
+    - io_out[18] ( PIN io_out[18] ) ( inst_eFPGA_CPU_top io_out[18] ) + USE SIGNAL
+      + ROUTED met2 ( 1739030 3404930 ) ( * 3512100 )
+      NEW met2 ( 1739030 3512100 ) ( 1744090 * )
+      NEW met2 ( 1744090 3512100 ) ( * 3517980 0 )
+      NEW met2 ( 1790770 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1790550 3394220 ) ( 1790770 * )
+      NEW met2 ( 1790550 3394220 ) ( * 3404930 )
+      NEW met1 ( 1739030 3404930 ) ( 1790550 * )
+      NEW met1 ( 1739030 3404930 ) M1M2_PR
+      NEW met1 ( 1790550 3404930 ) M1M2_PR ;
+    - io_out[19] ( PIN io_out[19] ) ( inst_eFPGA_CPU_top io_out[19] ) + USE SIGNAL
+      + ROUTED met2 ( 1460490 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1460270 3394220 ) ( 1460490 * )
+      NEW met2 ( 1460270 3394220 ) ( * 3404930 )
+      NEW met1 ( 1414730 3404930 ) ( 1460270 * )
+      NEW met2 ( 1414730 3404930 ) ( * 3512100 )
+      NEW met2 ( 1414730 3512100 ) ( 1419330 * )
+      NEW met2 ( 1419330 3512100 ) ( * 3517980 0 )
+      NEW met1 ( 1460270 3404930 ) M1M2_PR
+      NEW met1 ( 1414730 3404930 ) M1M2_PR ;
+    - io_out[1] ( PIN io_out[1] ) ( inst_eFPGA_CPU_top io_out[1] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 298180 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 453220 ) ( 2912030 * )
+      NEW met3 ( 2903980 453220 ) ( * 453440 )
+      NEW met3 ( 2901220 453440 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 298180 ) ( * 453220 )
+      NEW met2 ( 2912030 298180 ) M2M3_PR_M
+      NEW met2 ( 2912030 453220 ) M2M3_PR_M ;
+    - io_out[20] ( PIN io_out[20] ) ( inst_eFPGA_CPU_top io_out[20] ) + USE SIGNAL
+      + ROUTED met2 ( 1090430 3517980 ) ( 1094110 * )
+      NEW met2 ( 1094110 3517300 ) ( * 3517980 )
+      NEW met2 ( 1094110 3517300 ) ( 1095030 * )
+      NEW met2 ( 1095030 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 1090430 3404930 ) ( * 3517980 )
+      NEW met2 ( 1130210 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 1129990 3394220 ) ( 1130210 * )
+      NEW met2 ( 1129990 3394220 ) ( * 3404930 )
+      NEW met1 ( 1090430 3404930 ) ( 1129990 * )
+      NEW met1 ( 1090430 3404930 ) M1M2_PR
+      NEW met1 ( 1129990 3404930 ) M1M2_PR ;
+    - io_out[21] ( PIN io_out[21] ) ( inst_eFPGA_CPU_top io_out[21] ) + USE SIGNAL
+      + ROUTED met2 ( 800390 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 800170 3394220 ) ( 800390 * )
+      NEW met2 ( 800170 3394220 ) ( * 3403230 )
+      NEW met1 ( 766130 3403230 ) ( 800170 * )
+      NEW met2 ( 766130 3403230 ) ( * 3512100 )
+      NEW met2 ( 766130 3512100 ) ( 770730 * )
+      NEW met2 ( 770730 3512100 ) ( * 3517980 0 )
+      NEW met1 ( 800170 3403230 ) M1M2_PR
+      NEW met1 ( 766130 3403230 ) M1M2_PR ;
+    - io_out[22] ( PIN io_out[22] ) ( inst_eFPGA_CPU_top io_out[22] ) + USE SIGNAL
+      + ROUTED met2 ( 470110 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 469890 3394220 ) ( 470110 * )
+      NEW met2 ( 469890 3394220 ) ( * 3407650 )
+      NEW met1 ( 441830 3407650 ) ( 469890 * )
+      NEW met2 ( 441830 3407650 ) ( * 3512100 )
+      NEW met2 ( 441830 3512100 ) ( 445970 * )
+      NEW met2 ( 445970 3512100 ) ( * 3517980 0 )
+      NEW met1 ( 469890 3407650 ) M1M2_PR
+      NEW met1 ( 441830 3407650 ) M1M2_PR ;
+    - io_out[23] ( PIN io_out[23] ) ( inst_eFPGA_CPU_top io_out[23] ) + USE SIGNAL
+      + ROUTED met2 ( 117530 3517980 ) ( 120750 * )
+      NEW met2 ( 120750 3517300 ) ( * 3517980 )
+      NEW met2 ( 120750 3517300 ) ( 121670 * )
+      NEW met2 ( 121670 3517300 ) ( * 3517980 0 )
+      NEW met2 ( 117530 3406970 ) ( * 3517980 )
+      NEW met2 ( 140290 3393880 0 ) ( * 3394220 )
+      NEW met2 ( 140070 3394220 ) ( 140290 * )
+      NEW met2 ( 140070 3394220 ) ( * 3406970 )
+      NEW met1 ( 117530 3406970 ) ( 140070 * )
+      NEW met1 ( 117530 3406970 ) M1M2_PR
+      NEW met1 ( 140070 3406970 ) M1M2_PR ;
+    - io_out[24] ( PIN io_out[24] ) ( inst_eFPGA_CPU_top io_out[24] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 3305800 ) ( 20240 * 0 )
+      NEW met3 ( 17020 3305800 ) ( * 3305820 )
+      NEW met3 ( 14030 3305820 ) ( 17020 * )
+      NEW met3 ( 1380 3356140 0 ) ( 14030 * )
+      NEW met2 ( 14030 3305820 ) ( * 3356140 )
+      NEW met2 ( 14030 3305820 ) M2M3_PR_M
+      NEW met2 ( 14030 3356140 ) M2M3_PR_M ;
+    - io_out[25] ( PIN io_out[25] ) ( inst_eFPGA_CPU_top io_out[25] ) + USE SIGNAL
+      + ROUTED met3 ( 1150 3092980 ) ( 1380 * )
+      NEW met3 ( 1380 3092980 ) ( * 3095020 )
+      NEW met3 ( 1380 3095020 ) ( 3220 * )
+      NEW met3 ( 3220 3095020 ) ( * 3095700 )
+      NEW met3 ( 1380 3095700 0 ) ( 3220 * )
+      NEW met3 ( 17020 3069730 ) ( 20240 * 0 )
+      NEW met3 ( 17020 3069730 ) ( * 3069860 )
+      NEW met3 ( 1150 3069860 ) ( 17020 * )
+      NEW met2 ( 1150 3069860 ) ( * 3092980 )
+      NEW met2 ( 1150 3092980 ) M2M3_PR_M
+      NEW met2 ( 1150 3069860 ) M2M3_PR_M ;
+    - io_out[26] ( PIN io_out[26] ) ( inst_eFPGA_CPU_top io_out[26] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 2833660 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2833660 ) ( * 2834580 )
+      NEW met3 ( 1380 2834580 0 ) ( 17020 * ) ;
+    - io_out[27] ( PIN io_out[27] ) ( inst_eFPGA_CPU_top io_out[27] ) + USE SIGNAL
+      + ROUTED met3 ( 18860 2597590 ) ( 20240 * 0 )
+      NEW met3 ( 18860 2597260 ) ( * 2597590 )
+      NEW met3 ( 12650 2597260 ) ( 18860 * )
+      NEW met3 ( 1380 2574140 0 ) ( 12650 * )
+      NEW met2 ( 12650 2574140 ) ( * 2597260 )
+      NEW met2 ( 12650 2597260 ) M2M3_PR_M
+      NEW met2 ( 12650 2574140 ) M2M3_PR_M ;
+    - io_out[28] ( PIN io_out[28] ) ( inst_eFPGA_CPU_top io_out[28] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 2313020 0 ) ( 14030 * )
+      NEW met3 ( 17020 2362130 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2361980 ) ( * 2362130 )
+      NEW met3 ( 14030 2361980 ) ( 17020 * )
+      NEW met2 ( 14030 2313020 ) ( * 2361980 )
+      NEW met2 ( 14030 2313020 ) M2M3_PR_M
+      NEW met2 ( 14030 2361980 ) M2M3_PR_M ;
+    - io_out[29] ( PIN io_out[29] ) ( inst_eFPGA_CPU_top io_out[29] ) + USE SIGNAL
+      + ROUTED met3 ( 690 2055300 ) ( 1380 * )
+      NEW met3 ( 1380 2053260 ) ( * 2055300 )
+      NEW met3 ( 1380 2053260 ) ( 3220 * )
+      NEW met3 ( 3220 2052580 ) ( * 2053260 )
+      NEW met3 ( 1380 2052580 0 ) ( 3220 * )
+      NEW met3 ( 17020 2126060 ) ( 20240 * 0 )
+      NEW met3 ( 17020 2126020 ) ( * 2126060 )
+      NEW met3 ( 690 2126020 ) ( 17020 * )
+      NEW met2 ( 690 2055300 ) ( * 2126020 )
+      NEW met2 ( 690 2055300 ) M2M3_PR_M
+      NEW met2 ( 690 2126020 ) M2M3_PR_M ;
+    - io_out[2] ( PIN io_out[2] ) ( inst_eFPGA_CPU_top io_out[2] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 497420 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 672860 ) ( 2912030 * )
+      NEW met3 ( 2903980 672860 ) ( * 673040 )
+      NEW met3 ( 2901220 673040 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 497420 ) ( * 672860 )
+      NEW met2 ( 2912030 497420 ) M2M3_PR_M
+      NEW met2 ( 2912030 672860 ) M2M3_PR_M ;
+    - io_out[30] ( PIN io_out[30] ) ( inst_eFPGA_CPU_top io_out[30] ) + USE SIGNAL
+      + ROUTED met3 ( 230 1793500 ) ( 460 * )
+      NEW met3 ( 460 1792820 ) ( * 1793500 )
+      NEW met3 ( 460 1792820 ) ( 3220 * )
+      NEW met3 ( 3220 1792140 ) ( * 1792820 )
+      NEW met3 ( 1380 1792140 0 ) ( 3220 * )
+      NEW met3 ( 17020 1889990 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1889990 ) ( * 1890060 )
+      NEW met3 ( 230 1890060 ) ( 17020 * )
+      NEW met2 ( 230 1793500 ) ( * 1890060 )
+      NEW met2 ( 230 1793500 ) M2M3_PR_M
+      NEW met2 ( 230 1890060 ) M2M3_PR_M ;
+    - io_out[31] ( PIN io_out[31] ) ( inst_eFPGA_CPU_top io_out[31] ) + USE SIGNAL
+      + ROUTED met3 ( 460 1532380 ) ( 690 * )
+      NEW met3 ( 17020 1654530 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1654530 ) ( * 1654780 )
+      NEW met3 ( 690 1654780 ) ( 17020 * )
+      NEW met3 ( 460 1531700 ) ( 3220 * )
+      NEW met3 ( 3220 1531020 ) ( * 1531700 )
+      NEW met3 ( 1380 1531020 0 ) ( 3220 * )
+      NEW met3 ( 460 1531700 ) ( * 1532380 )
+      NEW met2 ( 690 1532380 ) ( * 1654780 )
+      NEW met2 ( 690 1532380 ) M2M3_PR_M
+      NEW met2 ( 690 1654780 ) M2M3_PR_M ;
+    - io_out[32] ( PIN io_out[32] ) ( inst_eFPGA_CPU_top io_out[32] ) + USE SIGNAL
+      + ROUTED met3 ( 230 1273300 ) ( 460 * )
+      NEW met3 ( 460 1271260 ) ( * 1273300 )
+      NEW met3 ( 460 1271260 ) ( 3220 * )
+      NEW met3 ( 3220 1270580 ) ( * 1271260 )
+      NEW met3 ( 1380 1270580 0 ) ( 3220 * )
+      NEW met3 ( 18860 1418460 ) ( 20240 * 0 )
+      NEW met3 ( 18860 1418140 ) ( * 1418460 )
+      NEW met3 ( 230 1418140 ) ( 18860 * )
+      NEW met2 ( 230 1273300 ) ( * 1418140 )
+      NEW met2 ( 230 1273300 ) M2M3_PR_M
+      NEW met2 ( 230 1418140 ) M2M3_PR_M ;
+    - io_out[33] ( PIN io_out[33] ) ( inst_eFPGA_CPU_top io_out[33] ) + USE SIGNAL
+      + ROUTED met3 ( 17020 1182390 ) ( 20240 * 0 )
+      NEW met3 ( 17020 1182180 ) ( * 1182390 )
+      NEW met3 ( 690 1182180 ) ( 17020 * )
+      NEW met3 ( 690 1012180 ) ( 1380 * )
+      NEW met3 ( 1380 1010140 ) ( * 1012180 )
+      NEW met3 ( 1380 1010140 ) ( 3220 * )
+      NEW met3 ( 3220 1009460 ) ( * 1010140 )
+      NEW met3 ( 1380 1009460 0 ) ( 3220 * )
+      NEW met2 ( 690 1012180 ) ( * 1182180 )
+      NEW met2 ( 690 1182180 ) M2M3_PR_M
+      NEW met2 ( 690 1012180 ) M2M3_PR_M ;
+    - io_out[34] ( PIN io_out[34] ) ( inst_eFPGA_CPU_top io_out[34] ) + USE SIGNAL
+      + ROUTED met3 ( 690 751740 ) ( 1380 * )
+      NEW met3 ( 1380 749700 ) ( * 751740 )
+      NEW met3 ( 1380 749700 ) ( 3220 * )
+      NEW met3 ( 3220 749020 ) ( * 749700 )
+      NEW met3 ( 1380 749020 0 ) ( 3220 * )
+      NEW met3 ( 17020 946930 ) ( 20240 * 0 )
+      NEW met3 ( 17020 946900 ) ( * 946930 )
+      NEW met3 ( 690 946900 ) ( 17020 * )
+      NEW met2 ( 690 751740 ) ( * 946900 )
+      NEW met2 ( 690 751740 ) M2M3_PR_M
+      NEW met2 ( 690 946900 ) M2M3_PR_M ;
+    - io_out[35] ( PIN io_out[35] ) ( inst_eFPGA_CPU_top io_out[35] ) + USE SIGNAL
+      + ROUTED met3 ( 1380 487900 0 ) ( 10810 * )
+      NEW met3 ( 17020 710860 ) ( 20240 * 0 )
+      NEW met3 ( 17020 710860 ) ( * 710940 )
+      NEW met3 ( 10810 710940 ) ( 17020 * )
+      NEW met2 ( 10810 487900 ) ( * 710940 )
+      NEW met2 ( 10810 487900 ) M2M3_PR_M
+      NEW met2 ( 10810 710940 ) M2M3_PR_M ;
+    - io_out[36] ( PIN io_out[36] ) ( inst_eFPGA_CPU_top io_out[36] ) + USE SIGNAL
+      + ROUTED met3 ( 690 295460 ) ( 1380 * )
+      NEW met3 ( 1380 293420 ) ( * 295460 )
+      NEW met3 ( 1380 293420 ) ( 3220 * )
+      NEW met3 ( 3220 292740 ) ( * 293420 )
+      NEW met3 ( 1380 292740 0 ) ( 3220 * )
+      NEW met3 ( 17020 474790 ) ( 20240 * 0 )
+      NEW met3 ( 17020 474790 ) ( * 474980 )
+      NEW met3 ( 690 474980 ) ( 17020 * )
+      NEW met2 ( 690 295460 ) ( * 474980 )
+      NEW met2 ( 690 295460 ) M2M3_PR_M
+      NEW met2 ( 690 474980 ) M2M3_PR_M ;
+    - io_out[37] ( PIN io_out[37] ) ( inst_eFPGA_CPU_top io_out[37] ) + USE SIGNAL
+      + ROUTED met3 ( 690 99620 ) ( 1380 * )
+      NEW met3 ( 1380 97580 ) ( * 99620 )
+      NEW met3 ( 1380 97580 ) ( 3220 * )
+      NEW met3 ( 3220 96900 ) ( * 97580 )
+      NEW met3 ( 1380 96900 0 ) ( 3220 * )
+      NEW met3 ( 17020 238720 ) ( 20240 * 0 )
+      NEW met3 ( 17020 238720 ) ( * 239020 )
+      NEW met3 ( 690 239020 ) ( 17020 * )
+      NEW met2 ( 690 99620 ) ( * 239020 )
+      NEW met2 ( 690 99620 ) M2M3_PR_M
+      NEW met2 ( 690 239020 ) M2M3_PR_M ;
+    - io_out[3] ( PIN io_out[3] ) ( inst_eFPGA_CPU_top io_out[3] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 696660 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 893180 ) ( 2912030 * )
+      NEW met3 ( 2903980 893180 ) ( * 893250 )
+      NEW met3 ( 2901220 893250 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 696660 ) ( * 893180 )
+      NEW met2 ( 2912030 696660 ) M2M3_PR_M
+      NEW met2 ( 2912030 893180 ) M2M3_PR_M ;
+    - io_out[4] ( PIN io_out[4] ) ( inst_eFPGA_CPU_top io_out[4] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 895900 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1112820 ) ( 2912030 * )
+      NEW met3 ( 2903980 1112820 ) ( * 1112850 )
+      NEW met3 ( 2901220 1112850 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 895900 ) ( * 1112820 )
+      NEW met2 ( 2912030 895900 ) M2M3_PR_M
+      NEW met2 ( 2912030 1112820 ) M2M3_PR_M ;
+    - io_out[5] ( PIN io_out[5] ) ( inst_eFPGA_CPU_top io_out[5] ) + USE SIGNAL
+      + ROUTED met3 ( 2912490 1095140 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1332460 ) ( 2912490 * )
+      NEW met3 ( 2903980 1332450 ) ( * 1332460 )
+      NEW met3 ( 2901220 1332450 0 ) ( 2903980 * )
+      NEW met2 ( 2912490 1095140 ) ( * 1332460 )
+      NEW met2 ( 2912490 1095140 ) M2M3_PR_M
+      NEW met2 ( 2912490 1332460 ) M2M3_PR_M ;
+    - io_out[6] ( PIN io_out[6] ) ( inst_eFPGA_CPU_top io_out[6] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 1552780 ) ( 2912030 * )
+      NEW met3 ( 2903980 1552660 ) ( * 1552780 )
+      NEW met3 ( 2901220 1552660 0 ) ( 2903980 * )
+      NEW met3 ( 2912030 1294380 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 1294380 ) ( * 1552780 )
+      NEW met2 ( 2912030 1552780 ) M2M3_PR_M
+      NEW met2 ( 2912030 1294380 ) M2M3_PR_M ;
+    - io_out[7] ( PIN io_out[7] ) ( inst_eFPGA_CPU_top io_out[7] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 1560260 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1772420 ) ( 2912030 * )
+      NEW met3 ( 2903980 1772260 ) ( * 1772420 )
+      NEW met3 ( 2901220 1772260 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 1560260 ) ( * 1772420 )
+      NEW met2 ( 2912030 1560260 ) M2M3_PR_M
+      NEW met2 ( 2912030 1772420 ) M2M3_PR_M ;
+    - io_out[8] ( PIN io_out[8] ) ( inst_eFPGA_CPU_top io_out[8] ) + USE SIGNAL
+      + ROUTED met3 ( 2912030 1825460 ) ( 2917780 * 0 )
+      NEW met3 ( 2903980 1992060 ) ( 2912030 * )
+      NEW met3 ( 2903980 1991860 ) ( * 1992060 )
+      NEW met3 ( 2901220 1991860 0 ) ( 2903980 * )
+      NEW met2 ( 2912030 1825460 ) ( * 1992060 )
+      NEW met2 ( 2912030 1825460 ) M2M3_PR_M
+      NEW met2 ( 2912030 1992060 ) M2M3_PR_M ;
+    - io_out[9] ( PIN io_out[9] ) ( inst_eFPGA_CPU_top io_out[9] ) + USE SIGNAL
+      + ROUTED met3 ( 2903980 2211700 ) ( 2912030 * )
+      NEW met3 ( 2903980 2211700 ) ( * 2212070 )
+      NEW met3 ( 2901220 2212070 0 ) ( 2903980 * )
+      NEW met3 ( 2912030 2091340 ) ( 2917780 * 0 )
+      NEW met2 ( 2912030 2091340 ) ( * 2211700 )
+      NEW met2 ( 2912030 2211700 ) M2M3_PR_M
+      NEW met2 ( 2912030 2091340 ) M2M3_PR_M ;
+    - la_data_in[0] ( PIN la_data_in[0] ) ( inst_eFPGA_CPU_top la_data_in[0] ) + USE SIGNAL
+      + ROUTED met2 ( 2432250 37910 ) ( * 135490 )
+      NEW met2 ( 2637630 149260 ) ( * 150240 0 )
+      NEW met2 ( 2637410 149260 ) ( 2637630 * )
+      NEW met2 ( 2637410 135150 ) ( * 149260 )
+      NEW met2 ( 629510 1700 0 ) ( * 37910 )
+      NEW met1 ( 629510 37910 ) ( 2432250 * )
+      NEW met1 ( 2432250 135490 ) ( 2449500 * )
+      NEW met1 ( 2449500 135150 ) ( * 135490 )
+      NEW met1 ( 2449500 135150 ) ( 2637410 * )
+      NEW met1 ( 2432250 37910 ) M1M2_PR
+      NEW met1 ( 2432250 135490 ) M1M2_PR
+      NEW met1 ( 2637410 135150 ) M1M2_PR
+      NEW met1 ( 629510 37910 ) M1M2_PR ;
+    - la_data_in[100] ( PIN la_data_in[100] ) + USE SIGNAL ;
+    - la_data_in[101] ( PIN la_data_in[101] ) + USE SIGNAL ;
+    - la_data_in[102] ( PIN la_data_in[102] ) + USE SIGNAL ;
+    - la_data_in[103] ( PIN la_data_in[103] ) + USE SIGNAL ;
+    - la_data_in[104] ( PIN la_data_in[104] ) + USE SIGNAL ;
+    - la_data_in[105] ( PIN la_data_in[105] ) + USE SIGNAL ;
+    - la_data_in[106] ( PIN la_data_in[106] ) + USE SIGNAL ;
+    - la_data_in[107] ( PIN la_data_in[107] ) + USE SIGNAL ;
+    - la_data_in[108] ( PIN la_data_in[108] ) + USE SIGNAL ;
+    - la_data_in[109] ( PIN la_data_in[109] ) + USE SIGNAL ;
+    - la_data_in[10] ( PIN la_data_in[10] ) + USE SIGNAL ;
+    - la_data_in[110] ( PIN la_data_in[110] ) + USE SIGNAL ;
+    - la_data_in[111] ( PIN la_data_in[111] ) + USE SIGNAL ;
+    - la_data_in[112] ( PIN la_data_in[112] ) + USE SIGNAL ;
+    - la_data_in[113] ( PIN la_data_in[113] ) + USE SIGNAL ;
+    - la_data_in[114] ( PIN la_data_in[114] ) + USE SIGNAL ;
+    - la_data_in[115] ( PIN la_data_in[115] ) + USE SIGNAL ;
+    - la_data_in[116] ( PIN la_data_in[116] ) + USE SIGNAL ;
+    - la_data_in[117] ( PIN la_data_in[117] ) + USE SIGNAL ;
+    - la_data_in[118] ( PIN la_data_in[118] ) + USE SIGNAL ;
+    - la_data_in[119] ( PIN la_data_in[119] ) + USE SIGNAL ;
+    - la_data_in[11] ( PIN la_data_in[11] ) + USE SIGNAL ;
+    - la_data_in[120] ( PIN la_data_in[120] ) + USE SIGNAL ;
+    - la_data_in[121] ( PIN la_data_in[121] ) + USE SIGNAL ;
+    - la_data_in[122] ( PIN la_data_in[122] ) + USE SIGNAL ;
+    - la_data_in[123] ( PIN la_data_in[123] ) + USE SIGNAL ;
+    - la_data_in[124] ( PIN la_data_in[124] ) + USE SIGNAL ;
+    - la_data_in[125] ( PIN la_data_in[125] ) + USE SIGNAL ;
+    - la_data_in[126] ( PIN la_data_in[126] ) + USE SIGNAL ;
+    - la_data_in[127] ( PIN la_data_in[127] ) + USE SIGNAL ;
+    - la_data_in[12] ( PIN la_data_in[12] ) + USE SIGNAL ;
+    - la_data_in[13] ( PIN la_data_in[13] ) + USE SIGNAL ;
+    - la_data_in[14] ( PIN la_data_in[14] ) + USE SIGNAL ;
+    - la_data_in[15] ( PIN la_data_in[15] ) + USE SIGNAL ;
+    - la_data_in[16] ( PIN la_data_in[16] ) + USE SIGNAL ;
+    - la_data_in[17] ( PIN la_data_in[17] ) + USE SIGNAL ;
+    - la_data_in[18] ( PIN la_data_in[18] ) + USE SIGNAL ;
+    - la_data_in[19] ( PIN la_data_in[19] ) + USE SIGNAL ;
+    - la_data_in[1] ( PIN la_data_in[1] ) ( inst_eFPGA_CPU_top la_data_in[1] ) + USE SIGNAL
+      + ROUTED met2 ( 2608430 51850 ) ( * 131100 )
+      NEW met2 ( 2612330 149260 ) ( * 150240 0 )
+      NEW met2 ( 2612110 149260 ) ( 2612330 * )
+      NEW met2 ( 2612110 131100 ) ( * 149260 )
+      NEW met2 ( 2608430 131100 ) ( 2612110 * )
+      NEW met2 ( 646990 1700 0 ) ( * 51850 )
+      NEW met1 ( 646990 51850 ) ( 2608430 * )
+      NEW met1 ( 2608430 51850 ) M1M2_PR
+      NEW met1 ( 646990 51850 ) M1M2_PR ;
+    - la_data_in[20] ( PIN la_data_in[20] ) + USE SIGNAL ;
+    - la_data_in[21] ( PIN la_data_in[21] ) + USE SIGNAL ;
+    - la_data_in[22] ( PIN la_data_in[22] ) + USE SIGNAL ;
+    - la_data_in[23] ( PIN la_data_in[23] ) + USE SIGNAL ;
+    - la_data_in[24] ( PIN la_data_in[24] ) + USE SIGNAL ;
+    - la_data_in[25] ( PIN la_data_in[25] ) + USE SIGNAL ;
+    - la_data_in[26] ( PIN la_data_in[26] ) + USE SIGNAL ;
+    - la_data_in[27] ( PIN la_data_in[27] ) + USE SIGNAL ;
+    - la_data_in[28] ( PIN la_data_in[28] ) + USE SIGNAL ;
+    - la_data_in[29] ( PIN la_data_in[29] ) + USE SIGNAL ;
+    - la_data_in[2] ( PIN la_data_in[2] ) ( inst_eFPGA_CPU_top la_data_in[2] ) + USE SIGNAL
+      + ROUTED met2 ( 664930 1700 0 ) ( * 58650 )
+      NEW met1 ( 664930 58650 ) ( 2577150 * )
+      NEW met2 ( 2587030 149260 ) ( * 150240 0 )
+      NEW met2 ( 2586810 149260 ) ( 2587030 * )
+      NEW met2 ( 2586810 137870 ) ( * 149260 )
+      NEW met1 ( 2577150 137870 ) ( 2586810 * )
+      NEW met2 ( 2577150 58650 ) ( * 137870 )
+      NEW met1 ( 664930 58650 ) M1M2_PR
+      NEW met1 ( 2577150 58650 ) M1M2_PR
+      NEW met1 ( 2586810 137870 ) M1M2_PR
+      NEW met1 ( 2577150 137870 ) M1M2_PR ;
+    - la_data_in[30] ( PIN la_data_in[30] ) + USE SIGNAL ;
+    - la_data_in[31] ( PIN la_data_in[31] ) + USE SIGNAL ;
+    - la_data_in[32] ( PIN la_data_in[32] ) + USE SIGNAL ;
+    - la_data_in[33] ( PIN la_data_in[33] ) + USE SIGNAL ;
+    - la_data_in[34] ( PIN la_data_in[34] ) + USE SIGNAL ;
+    - la_data_in[35] ( PIN la_data_in[35] ) + USE SIGNAL ;
+    - la_data_in[36] ( PIN la_data_in[36] ) + USE SIGNAL ;
+    - la_data_in[37] ( PIN la_data_in[37] ) + USE SIGNAL ;
+    - la_data_in[38] ( PIN la_data_in[38] ) + USE SIGNAL ;
+    - la_data_in[39] ( PIN la_data_in[39] ) + USE SIGNAL ;
+    - la_data_in[3] ( PIN la_data_in[3] ) ( inst_eFPGA_CPU_top la_data_in[3] ) + USE SIGNAL
+      + ROUTED met2 ( 682410 1700 0 ) ( * 44710 )
+      NEW met1 ( 682410 44710 ) ( 2560130 * )
+      NEW met2 ( 2560130 44710 ) ( * 131100 )
+      NEW met2 ( 2561730 149260 ) ( * 150240 0 )
+      NEW met2 ( 2561510 149260 ) ( 2561730 * )
+      NEW met2 ( 2561510 131100 ) ( * 149260 )
+      NEW met2 ( 2560130 131100 ) ( 2561510 * )
+      NEW met1 ( 682410 44710 ) M1M2_PR
+      NEW met1 ( 2560130 44710 ) M1M2_PR ;
+    - la_data_in[40] ( PIN la_data_in[40] ) + USE SIGNAL ;
+    - la_data_in[41] ( PIN la_data_in[41] ) + USE SIGNAL ;
+    - la_data_in[42] ( PIN la_data_in[42] ) + USE SIGNAL ;
+    - la_data_in[43] ( PIN la_data_in[43] ) + USE SIGNAL ;
+    - la_data_in[44] ( PIN la_data_in[44] ) + USE SIGNAL ;
+    - la_data_in[45] ( PIN la_data_in[45] ) + USE SIGNAL ;
+    - la_data_in[46] ( PIN la_data_in[46] ) + USE SIGNAL ;
+    - la_data_in[47] ( PIN la_data_in[47] ) + USE SIGNAL ;
+    - la_data_in[48] ( PIN la_data_in[48] ) + USE SIGNAL ;
+    - la_data_in[49] ( PIN la_data_in[49] ) + USE SIGNAL ;
+    - la_data_in[4] ( PIN la_data_in[4] ) + USE SIGNAL ;
+    - la_data_in[50] ( PIN la_data_in[50] ) + USE SIGNAL ;
+    - la_data_in[51] ( PIN la_data_in[51] ) + USE SIGNAL ;
+    - la_data_in[52] ( PIN la_data_in[52] ) + USE SIGNAL ;
+    - la_data_in[53] ( PIN la_data_in[53] ) + USE SIGNAL ;
+    - la_data_in[54] ( PIN la_data_in[54] ) + USE SIGNAL ;
+    - la_data_in[55] ( PIN la_data_in[55] ) + USE SIGNAL ;
+    - la_data_in[56] ( PIN la_data_in[56] ) + USE SIGNAL ;
+    - la_data_in[57] ( PIN la_data_in[57] ) + USE SIGNAL ;
+    - la_data_in[58] ( PIN la_data_in[58] ) + USE SIGNAL ;
+    - la_data_in[59] ( PIN la_data_in[59] ) + USE SIGNAL ;
+    - la_data_in[5] ( PIN la_data_in[5] ) + USE SIGNAL ;
+    - la_data_in[60] ( PIN la_data_in[60] ) + USE SIGNAL ;
+    - la_data_in[61] ( PIN la_data_in[61] ) + USE SIGNAL ;
+    - la_data_in[62] ( PIN la_data_in[62] ) + USE SIGNAL ;
+    - la_data_in[63] ( PIN la_data_in[63] ) + USE SIGNAL ;
+    - la_data_in[64] ( PIN la_data_in[64] ) + USE SIGNAL ;
+    - la_data_in[65] ( PIN la_data_in[65] ) + USE SIGNAL ;
+    - la_data_in[66] ( PIN la_data_in[66] ) + USE SIGNAL ;
+    - la_data_in[67] ( PIN la_data_in[67] ) + USE SIGNAL ;
+    - la_data_in[68] ( PIN la_data_in[68] ) + USE SIGNAL ;
+    - la_data_in[69] ( PIN la_data_in[69] ) + USE SIGNAL ;
+    - la_data_in[6] ( PIN la_data_in[6] ) + USE SIGNAL ;
+    - la_data_in[70] ( PIN la_data_in[70] ) + USE SIGNAL ;
+    - la_data_in[71] ( PIN la_data_in[71] ) + USE SIGNAL ;
+    - la_data_in[72] ( PIN la_data_in[72] ) + USE SIGNAL ;
+    - la_data_in[73] ( PIN la_data_in[73] ) + USE SIGNAL ;
+    - la_data_in[74] ( PIN la_data_in[74] ) + USE SIGNAL ;
+    - la_data_in[75] ( PIN la_data_in[75] ) + USE SIGNAL ;
+    - la_data_in[76] ( PIN la_data_in[76] ) + USE SIGNAL ;
+    - la_data_in[77] ( PIN la_data_in[77] ) + USE SIGNAL ;
+    - la_data_in[78] ( PIN la_data_in[78] ) + USE SIGNAL ;
+    - la_data_in[79] ( PIN la_data_in[79] ) + USE SIGNAL ;
+    - la_data_in[7] ( PIN la_data_in[7] ) + USE SIGNAL ;
+    - la_data_in[80] ( PIN la_data_in[80] ) + USE SIGNAL ;
+    - la_data_in[81] ( PIN la_data_in[81] ) + USE SIGNAL ;
+    - la_data_in[82] ( PIN la_data_in[82] ) + USE SIGNAL ;
+    - la_data_in[83] ( PIN la_data_in[83] ) + USE SIGNAL ;
+    - la_data_in[84] ( PIN la_data_in[84] ) + USE SIGNAL ;
+    - la_data_in[85] ( PIN la_data_in[85] ) + USE SIGNAL ;
+    - la_data_in[86] ( PIN la_data_in[86] ) + USE SIGNAL ;
+    - la_data_in[87] ( PIN la_data_in[87] ) + USE SIGNAL ;
+    - la_data_in[88] ( PIN la_data_in[88] ) + USE SIGNAL ;
+    - la_data_in[89] ( PIN la_data_in[89] ) + USE SIGNAL ;
+    - la_data_in[8] ( PIN la_data_in[8] ) + USE SIGNAL ;
+    - la_data_in[90] ( PIN la_data_in[90] ) + USE SIGNAL ;
+    - la_data_in[91] ( PIN la_data_in[91] ) + USE SIGNAL ;
+    - la_data_in[92] ( PIN la_data_in[92] ) + USE SIGNAL ;
+    - la_data_in[93] ( PIN la_data_in[93] ) + USE SIGNAL ;
+    - la_data_in[94] ( PIN la_data_in[94] ) + USE SIGNAL ;
+    - la_data_in[95] ( PIN la_data_in[95] ) + USE SIGNAL ;
+    - la_data_in[96] ( PIN la_data_in[96] ) + USE SIGNAL ;
+    - la_data_in[97] ( PIN la_data_in[97] ) + USE SIGNAL ;
+    - la_data_in[98] ( PIN la_data_in[98] ) + USE SIGNAL ;
+    - la_data_in[99] ( PIN la_data_in[99] ) + USE SIGNAL ;
+    - la_data_in[9] ( PIN la_data_in[9] ) + USE SIGNAL ;
+    - la_data_out[0] ( PIN la_data_out[0] ) + USE SIGNAL ;
+    - la_data_out[100] ( PIN la_data_out[100] ) + USE SIGNAL ;
+    - la_data_out[101] ( PIN la_data_out[101] ) + USE SIGNAL ;
+    - la_data_out[102] ( PIN la_data_out[102] ) + USE SIGNAL ;
+    - la_data_out[103] ( PIN la_data_out[103] ) + USE SIGNAL ;
+    - la_data_out[104] ( PIN la_data_out[104] ) + USE SIGNAL ;
+    - la_data_out[105] ( PIN la_data_out[105] ) + USE SIGNAL ;
+    - la_data_out[106] ( PIN la_data_out[106] ) + USE SIGNAL ;
+    - la_data_out[107] ( PIN la_data_out[107] ) + USE SIGNAL ;
+    - la_data_out[108] ( PIN la_data_out[108] ) + USE SIGNAL ;
+    - la_data_out[109] ( PIN la_data_out[109] ) + USE SIGNAL ;
+    - la_data_out[10] ( PIN la_data_out[10] ) + USE SIGNAL ;
+    - la_data_out[110] ( PIN la_data_out[110] ) + USE SIGNAL ;
+    - la_data_out[111] ( PIN la_data_out[111] ) + USE SIGNAL ;
+    - la_data_out[112] ( PIN la_data_out[112] ) + USE SIGNAL ;
+    - la_data_out[113] ( PIN la_data_out[113] ) + USE SIGNAL ;
+    - la_data_out[114] ( PIN la_data_out[114] ) + USE SIGNAL ;
+    - la_data_out[115] ( PIN la_data_out[115] ) + USE SIGNAL ;
+    - la_data_out[116] ( PIN la_data_out[116] ) + USE SIGNAL ;
+    - la_data_out[117] ( PIN la_data_out[117] ) + USE SIGNAL ;
+    - la_data_out[118] ( PIN la_data_out[118] ) + USE SIGNAL ;
+    - la_data_out[119] ( PIN la_data_out[119] ) + USE SIGNAL ;
+    - la_data_out[11] ( PIN la_data_out[11] ) + USE SIGNAL ;
+    - la_data_out[120] ( PIN la_data_out[120] ) + USE SIGNAL ;
+    - la_data_out[121] ( PIN la_data_out[121] ) + USE SIGNAL ;
+    - la_data_out[122] ( PIN la_data_out[122] ) + USE SIGNAL ;
+    - la_data_out[123] ( PIN la_data_out[123] ) + USE SIGNAL ;
+    - la_data_out[124] ( PIN la_data_out[124] ) + USE SIGNAL ;
+    - la_data_out[125] ( PIN la_data_out[125] ) + USE SIGNAL ;
+    - la_data_out[126] ( PIN la_data_out[126] ) + USE SIGNAL ;
+    - la_data_out[127] ( PIN la_data_out[127] ) + USE SIGNAL ;
+    - la_data_out[12] ( PIN la_data_out[12] ) + USE SIGNAL ;
+    - la_data_out[13] ( PIN la_data_out[13] ) + USE SIGNAL ;
+    - la_data_out[14] ( PIN la_data_out[14] ) + USE SIGNAL ;
+    - la_data_out[15] ( PIN la_data_out[15] ) + USE SIGNAL ;
+    - la_data_out[16] ( PIN la_data_out[16] ) + USE SIGNAL ;
+    - la_data_out[17] ( PIN la_data_out[17] ) + USE SIGNAL ;
+    - la_data_out[18] ( PIN la_data_out[18] ) + USE SIGNAL ;
+    - la_data_out[19] ( PIN la_data_out[19] ) + USE SIGNAL ;
+    - la_data_out[1] ( PIN la_data_out[1] ) + USE SIGNAL ;
+    - la_data_out[20] ( PIN la_data_out[20] ) + USE SIGNAL ;
+    - la_data_out[21] ( PIN la_data_out[21] ) + USE SIGNAL ;
+    - la_data_out[22] ( PIN la_data_out[22] ) + USE SIGNAL ;
+    - la_data_out[23] ( PIN la_data_out[23] ) + USE SIGNAL ;
+    - la_data_out[24] ( PIN la_data_out[24] ) + USE SIGNAL ;
+    - la_data_out[25] ( PIN la_data_out[25] ) + USE SIGNAL ;
+    - la_data_out[26] ( PIN la_data_out[26] ) + USE SIGNAL ;
+    - la_data_out[27] ( PIN la_data_out[27] ) + USE SIGNAL ;
+    - la_data_out[28] ( PIN la_data_out[28] ) + USE SIGNAL ;
+    - la_data_out[29] ( PIN la_data_out[29] ) + USE SIGNAL ;
+    - la_data_out[2] ( PIN la_data_out[2] ) + USE SIGNAL ;
+    - la_data_out[30] ( PIN la_data_out[30] ) + USE SIGNAL ;
+    - la_data_out[31] ( PIN la_data_out[31] ) + USE SIGNAL ;
+    - la_data_out[32] ( PIN la_data_out[32] ) + USE SIGNAL ;
+    - la_data_out[33] ( PIN la_data_out[33] ) + USE SIGNAL ;
+    - la_data_out[34] ( PIN la_data_out[34] ) + USE SIGNAL ;
+    - la_data_out[35] ( PIN la_data_out[35] ) + USE SIGNAL ;
+    - la_data_out[36] ( PIN la_data_out[36] ) + USE SIGNAL ;
+    - la_data_out[37] ( PIN la_data_out[37] ) + USE SIGNAL ;
+    - la_data_out[38] ( PIN la_data_out[38] ) + USE SIGNAL ;
+    - la_data_out[39] ( PIN la_data_out[39] ) + USE SIGNAL ;
+    - la_data_out[3] ( PIN la_data_out[3] ) + USE SIGNAL ;
+    - la_data_out[40] ( PIN la_data_out[40] ) + USE SIGNAL ;
+    - la_data_out[41] ( PIN la_data_out[41] ) + USE SIGNAL ;
+    - la_data_out[42] ( PIN la_data_out[42] ) + USE SIGNAL ;
+    - la_data_out[43] ( PIN la_data_out[43] ) + USE SIGNAL ;
+    - la_data_out[44] ( PIN la_data_out[44] ) + USE SIGNAL ;
+    - la_data_out[45] ( PIN la_data_out[45] ) + USE SIGNAL ;
+    - la_data_out[46] ( PIN la_data_out[46] ) + USE SIGNAL ;
+    - la_data_out[47] ( PIN la_data_out[47] ) + USE SIGNAL ;
+    - la_data_out[48] ( PIN la_data_out[48] ) + USE SIGNAL ;
+    - la_data_out[49] ( PIN la_data_out[49] ) + USE SIGNAL ;
+    - la_data_out[4] ( PIN la_data_out[4] ) ( inst_eFPGA_CPU_top la_data_out[0] ) + USE SIGNAL
+      + ROUTED met2 ( 704030 82800 ) ( * 106930 )
+      NEW met2 ( 704030 82800 ) ( 706330 * )
+      NEW met2 ( 706330 1700 0 ) ( * 82800 )
+      NEW met2 ( 2711930 106930 ) ( * 131100 )
+      NEW met2 ( 2713530 149260 ) ( * 150240 0 )
+      NEW met2 ( 2713310 149260 ) ( 2713530 * )
+      NEW met2 ( 2713310 131100 ) ( * 149260 )
+      NEW met2 ( 2711930 131100 ) ( 2713310 * )
+      NEW met1 ( 704030 106930 ) ( 2711930 * )
+      NEW met1 ( 704030 106930 ) M1M2_PR
+      NEW met1 ( 2711930 106930 ) M1M2_PR ;
+    - la_data_out[50] ( PIN la_data_out[50] ) + USE SIGNAL ;
+    - la_data_out[51] ( PIN la_data_out[51] ) + USE SIGNAL ;
+    - la_data_out[52] ( PIN la_data_out[52] ) + USE SIGNAL ;
+    - la_data_out[53] ( PIN la_data_out[53] ) + USE SIGNAL ;
+    - la_data_out[54] ( PIN la_data_out[54] ) + USE SIGNAL ;
+    - la_data_out[55] ( PIN la_data_out[55] ) + USE SIGNAL ;
+    - la_data_out[56] ( PIN la_data_out[56] ) + USE SIGNAL ;
+    - la_data_out[57] ( PIN la_data_out[57] ) + USE SIGNAL ;
+    - la_data_out[58] ( PIN la_data_out[58] ) + USE SIGNAL ;
+    - la_data_out[59] ( PIN la_data_out[59] ) + USE SIGNAL ;
+    - la_data_out[5] ( PIN la_data_out[5] ) ( inst_eFPGA_CPU_top la_data_out[1] ) + USE SIGNAL
+      + ROUTED met2 ( 723810 1700 0 ) ( * 20910 )
+      NEW met1 ( 717830 20910 ) ( 723810 * )
+      NEW met1 ( 717830 113730 ) ( 2684330 * )
+      NEW met2 ( 717830 20910 ) ( * 113730 )
+      NEW met2 ( 2684330 113730 ) ( * 131100 )
+      NEW met2 ( 2688230 149260 ) ( * 150240 0 )
+      NEW met2 ( 2688010 149260 ) ( 2688230 * )
+      NEW met2 ( 2688010 131100 ) ( * 149260 )
+      NEW met2 ( 2684330 131100 ) ( 2688010 * )
+      NEW met1 ( 723810 20910 ) M1M2_PR
       NEW met1 ( 717830 20910 ) M1M2_PR
-      NEW met1 ( 724270 20910 ) M1M2_PR
-      NEW met1 ( 724270 1675350 ) M1M2_PR
-      NEW met1 ( 1395410 1683170 ) M1M2_PR ;
-    - la_data_in[60] ( PIN la_data_in[60] ) ( mprj la_data_in[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1693490 2380 0 ) ( * 15470 )
-      NEW met1 ( 1693490 15470 ) ( 1698090 * )
-      NEW met2 ( 1697860 1688780 ) ( 1698090 * )
-      NEW met2 ( 1697860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1698090 15470 ) ( * 1688780 )
-      NEW met1 ( 1693490 15470 ) M1M2_PR
-      NEW met1 ( 1698090 15470 ) M1M2_PR ;
-    - la_data_in[61] ( PIN la_data_in[61] ) ( mprj la_data_in[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1710970 2380 0 ) ( * 15300 )
-      NEW met2 ( 1710050 15300 ) ( 1710970 * )
-      NEW met2 ( 1705910 82800 ) ( 1710050 * )
-      NEW met2 ( 1710050 15300 ) ( * 82800 )
-      NEW met2 ( 1704070 1683340 ) ( 1705910 * )
-      NEW met2 ( 1704070 1683340 ) ( * 1690140 )
-      NEW met2 ( 1703380 1690140 0 ) ( 1704070 * )
-      NEW met2 ( 1705910 82800 ) ( * 1683340 ) ;
-    - la_data_in[62] ( PIN la_data_in[62] ) ( mprj la_data_in[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1728910 2380 0 ) ( * 3060 )
-      NEW met2 ( 1727990 3060 ) ( 1728910 * )
-      NEW met2 ( 1727990 2380 ) ( * 3060 )
-      NEW met2 ( 1726610 2380 ) ( 1727990 * )
-      NEW met2 ( 1725690 82800 ) ( 1726610 * )
-      NEW met2 ( 1726610 2380 ) ( * 82800 )
-      NEW met2 ( 1725690 82800 ) ( * 1677390 )
-      NEW met2 ( 1710050 1677390 ) ( * 1690140 )
-      NEW met2 ( 1708900 1690140 0 ) ( 1710050 * )
-      NEW met1 ( 1710050 1677390 ) ( 1725690 * )
-      NEW met1 ( 1725690 1677390 ) M1M2_PR
-      NEW met1 ( 1710050 1677390 ) M1M2_PR ;
-    - la_data_in[63] ( PIN la_data_in[63] ) ( mprj la_data_in[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1746390 2380 0 ) ( * 19890 )
-      NEW met1 ( 1716950 19890 ) ( 1746390 * )
-      NEW met2 ( 1715110 1628400 ) ( 1716950 * )
-      NEW met2 ( 1716950 19890 ) ( * 1628400 )
-      NEW met2 ( 1714420 1690140 0 ) ( 1715110 * )
-      NEW met2 ( 1715110 1628400 ) ( * 1690140 )
-      NEW met1 ( 1746390 19890 ) M1M2_PR
-      NEW met1 ( 1716950 19890 ) M1M2_PR ;
-    - la_data_in[64] ( PIN la_data_in[64] ) ( mprj la_data_in[64] ) + USE SIGNAL
-      + ROUTED met2 ( 1764330 2380 0 ) ( * 17510 )
-      NEW met1 ( 1728450 17510 ) ( 1764330 * )
-      NEW met2 ( 1728450 17510 ) ( * 1681470 )
-      NEW met2 ( 1720630 1681470 ) ( * 1690140 )
-      NEW met2 ( 1719480 1690140 0 ) ( 1720630 * )
-      NEW met1 ( 1720630 1681470 ) ( 1728450 * )
-      NEW met1 ( 1764330 17510 ) M1M2_PR
-      NEW met1 ( 1728450 17510 ) M1M2_PR
-      NEW met1 ( 1728450 1681470 ) M1M2_PR
-      NEW met1 ( 1720630 1681470 ) M1M2_PR ;
-    - la_data_in[65] ( PIN la_data_in[65] ) ( mprj la_data_in[65] ) + USE SIGNAL
-      + ROUTED met1 ( 1728910 19210 ) ( 1765710 * )
-      NEW li1 ( 1765710 18190 ) ( * 19210 )
-      NEW met2 ( 1728910 19210 ) ( * 1676710 )
-      NEW met2 ( 1781810 2380 0 ) ( * 18190 )
-      NEW met1 ( 1765710 18190 ) ( 1781810 * )
-      NEW met2 ( 1724770 1676710 ) ( * 1690140 )
-      NEW met2 ( 1724770 1690140 ) ( 1725000 * 0 )
-      NEW met1 ( 1724770 1676710 ) ( 1728910 * )
-      NEW met1 ( 1728910 19210 ) M1M2_PR
-      NEW li1 ( 1765710 19210 ) L1M1_PR_MR
-      NEW li1 ( 1765710 18190 ) L1M1_PR_MR
-      NEW met1 ( 1728910 1676710 ) M1M2_PR
-      NEW met1 ( 1781810 18190 ) M1M2_PR
-      NEW met1 ( 1724770 1676710 ) M1M2_PR ;
-    - la_data_in[66] ( PIN la_data_in[66] ) ( mprj la_data_in[66] ) + USE SIGNAL
-      + ROUTED met1 ( 1735810 17850 ) ( 1764790 * )
-      NEW met1 ( 1764790 17510 ) ( * 17850 )
-      NEW met1 ( 1731670 1683510 ) ( 1735810 * )
-      NEW met2 ( 1731670 1683510 ) ( * 1690140 )
-      NEW met2 ( 1730520 1690140 0 ) ( 1731670 * )
-      NEW met2 ( 1735810 17850 ) ( * 1683510 )
-      NEW met2 ( 1799750 2380 0 ) ( * 17510 )
-      NEW met1 ( 1764790 17510 ) ( 1799750 * )
-      NEW met1 ( 1735810 17850 ) M1M2_PR
-      NEW met1 ( 1735810 1683510 ) M1M2_PR
-      NEW met1 ( 1731670 1683510 ) M1M2_PR
-      NEW met1 ( 1799750 17510 ) M1M2_PR ;
-    - la_data_in[67] ( PIN la_data_in[67] ) ( mprj la_data_in[67] ) + USE SIGNAL
-      + ROUTED met1 ( 1737190 1681810 ) ( 1769850 * )
-      NEW met2 ( 1737190 1681810 ) ( * 1690140 )
-      NEW met2 ( 1736040 1690140 0 ) ( 1737190 * )
-      NEW met2 ( 1769850 15470 ) ( * 1681810 )
-      NEW met2 ( 1817690 2380 0 ) ( * 15470 )
-      NEW met1 ( 1769850 15470 ) ( 1817690 * )
-      NEW met1 ( 1769850 15470 ) M1M2_PR
-      NEW met1 ( 1769850 1681810 ) M1M2_PR
-      NEW met1 ( 1737190 1681810 ) M1M2_PR
-      NEW met1 ( 1817690 15470 ) M1M2_PR ;
-    - la_data_in[68] ( PIN la_data_in[68] ) ( mprj la_data_in[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1835170 2380 0 ) ( * 27710 )
-      NEW met2 ( 1742710 1682830 ) ( * 1690140 )
-      NEW met2 ( 1741560 1690140 0 ) ( 1742710 * )
-      NEW met1 ( 1818150 27710 ) ( 1835170 * )
-      NEW met1 ( 1742710 1682830 ) ( 1818150 * )
-      NEW met2 ( 1818150 27710 ) ( * 1682830 )
-      NEW met1 ( 1835170 27710 ) M1M2_PR
-      NEW met1 ( 1742710 1682830 ) M1M2_PR
-      NEW met1 ( 1818150 27710 ) M1M2_PR
-      NEW met1 ( 1818150 1682830 ) M1M2_PR ;
-    - la_data_in[69] ( PIN la_data_in[69] ) ( mprj la_data_in[69] ) + USE SIGNAL
-      + ROUTED met1 ( 1748230 1681130 ) ( 1751450 * )
-      NEW met2 ( 1748230 1681130 ) ( * 1690140 )
-      NEW met2 ( 1747080 1690140 0 ) ( 1748230 * )
-      NEW met2 ( 1751450 44710 ) ( * 1681130 )
-      NEW met2 ( 1853110 2380 0 ) ( * 44710 )
-      NEW met1 ( 1751450 44710 ) ( 1853110 * )
-      NEW met1 ( 1751450 44710 ) M1M2_PR
-      NEW met1 ( 1751450 1681130 ) M1M2_PR
-      NEW met1 ( 1748230 1681130 ) M1M2_PR
-      NEW met1 ( 1853110 44710 ) M1M2_PR ;
-    - la_data_in[6] ( PIN la_data_in[6] ) ( mprj la_data_in[6] ) + USE SIGNAL
-      + ROUTED met2 ( 735770 2380 0 ) ( * 3060 )
-      NEW met2 ( 735770 3060 ) ( 736690 * )
-      NEW met2 ( 736690 2380 ) ( * 3060 )
-      NEW met2 ( 736690 2380 ) ( 738070 * )
-      NEW met1 ( 738070 1675010 ) ( 1401390 * )
-      NEW met2 ( 738070 2380 ) ( * 1675010 )
-      NEW met2 ( 1401390 1690140 ) ( 1402080 * 0 )
-      NEW met2 ( 1401390 1675010 ) ( * 1690140 )
-      NEW met1 ( 738070 1675010 ) M1M2_PR
-      NEW met1 ( 1401390 1675010 ) M1M2_PR ;
-    - la_data_in[70] ( PIN la_data_in[70] ) ( mprj la_data_in[70] ) + USE SIGNAL
-      + ROUTED met2 ( 1751910 1690140 ) ( 1752600 * 0 )
-      NEW met2 ( 1751910 22270 ) ( * 1690140 )
-      NEW met2 ( 1870590 2380 0 ) ( * 22270 )
-      NEW met1 ( 1751910 22270 ) ( 1870590 * )
-      NEW met1 ( 1751910 22270 ) M1M2_PR
-      NEW met1 ( 1870590 22270 ) M1M2_PR ;
-    - la_data_in[71] ( PIN la_data_in[71] ) ( mprj la_data_in[71] ) + USE SIGNAL
-      + ROUTED met2 ( 1758120 1688780 ) ( 1758350 * )
-      NEW met2 ( 1758120 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1758350 22610 ) ( * 1688780 )
-      NEW met2 ( 1888530 2380 0 ) ( * 22610 )
-      NEW met1 ( 1758350 22610 ) ( 1888530 * )
-      NEW met1 ( 1758350 22610 ) M1M2_PR
-      NEW met1 ( 1888530 22610 ) M1M2_PR ;
-    - la_data_in[72] ( PIN la_data_in[72] ) ( mprj la_data_in[72] ) + USE SIGNAL
-      + ROUTED met1 ( 1764330 1683510 ) ( 1765710 * )
-      NEW met2 ( 1764330 1683510 ) ( * 1690140 )
-      NEW met2 ( 1763640 1690140 0 ) ( 1764330 * )
-      NEW met2 ( 1765710 22950 ) ( * 1683510 )
-      NEW met2 ( 1906010 2380 0 ) ( * 22950 )
-      NEW met1 ( 1765710 22950 ) ( 1906010 * )
-      NEW met1 ( 1765710 22950 ) M1M2_PR
-      NEW met1 ( 1765710 1683510 ) M1M2_PR
-      NEW met1 ( 1764330 1683510 ) M1M2_PR
-      NEW met1 ( 1906010 22950 ) M1M2_PR ;
-    - la_data_in[73] ( PIN la_data_in[73] ) ( mprj la_data_in[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1923950 2380 0 ) ( * 23290 )
-      NEW met1 ( 1770310 1681810 ) ( 1772610 * )
-      NEW met2 ( 1770310 1681810 ) ( * 1690140 )
-      NEW met2 ( 1769160 1690140 0 ) ( 1770310 * )
-      NEW met2 ( 1772610 23290 ) ( * 1681810 )
-      NEW met1 ( 1772610 23290 ) ( 1923950 * )
-      NEW met1 ( 1772610 23290 ) M1M2_PR
-      NEW met1 ( 1923950 23290 ) M1M2_PR
-      NEW met1 ( 1772610 1681810 ) M1M2_PR
-      NEW met1 ( 1770310 1681810 ) M1M2_PR ;
-    - la_data_in[74] ( PIN la_data_in[74] ) ( mprj la_data_in[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1941430 2380 0 ) ( * 23630 )
-      NEW met1 ( 1779510 23630 ) ( 1941430 * )
-      NEW met1 ( 1775370 1683170 ) ( 1779510 * )
-      NEW met2 ( 1775370 1683170 ) ( * 1690140 )
-      NEW met2 ( 1774680 1690140 0 ) ( 1775370 * )
-      NEW met2 ( 1779510 23630 ) ( * 1683170 )
-      NEW met1 ( 1941430 23630 ) M1M2_PR
-      NEW met1 ( 1779510 23630 ) M1M2_PR
-      NEW met1 ( 1779510 1683170 ) M1M2_PR
-      NEW met1 ( 1775370 1683170 ) M1M2_PR ;
-    - la_data_in[75] ( PIN la_data_in[75] ) ( mprj la_data_in[75] ) + USE SIGNAL
-      + ROUTED met2 ( 1959370 2380 0 ) ( * 27370 )
-      NEW met1 ( 1779050 27370 ) ( 1959370 * )
-      NEW met2 ( 1779050 1690140 ) ( 1779740 * 0 )
-      NEW met2 ( 1779050 27370 ) ( * 1690140 )
-      NEW met1 ( 1959370 27370 ) M1M2_PR
-      NEW met1 ( 1779050 27370 ) M1M2_PR ;
-    - la_data_in[76] ( PIN la_data_in[76] ) ( mprj la_data_in[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1976850 2380 0 ) ( * 27030 )
-      NEW met1 ( 1786410 27030 ) ( 1976850 * )
-      NEW met1 ( 1785030 1683510 ) ( 1786410 * )
-      NEW met2 ( 1785030 1683510 ) ( * 1690140 )
-      NEW met2 ( 1785030 1690140 ) ( 1785260 * 0 )
-      NEW met2 ( 1786410 27030 ) ( * 1683510 )
-      NEW met1 ( 1786410 27030 ) M1M2_PR
-      NEW met1 ( 1976850 27030 ) M1M2_PR
-      NEW met1 ( 1786410 1683510 ) M1M2_PR
-      NEW met1 ( 1785030 1683510 ) M1M2_PR ;
-    - la_data_in[77] ( PIN la_data_in[77] ) ( mprj la_data_in[77] ) + USE SIGNAL
-      + ROUTED met2 ( 1994790 2380 0 ) ( * 26690 )
-      NEW met1 ( 1793310 26690 ) ( 1994790 * )
-      NEW met1 ( 1791930 1683510 ) ( 1793310 * )
-      NEW met2 ( 1791930 1683510 ) ( * 1690140 )
-      NEW met2 ( 1790780 1690140 0 ) ( 1791930 * )
-      NEW met2 ( 1793310 26690 ) ( * 1683510 )
-      NEW met1 ( 1793310 26690 ) M1M2_PR
-      NEW met1 ( 1994790 26690 ) M1M2_PR
-      NEW met1 ( 1793310 1683510 ) M1M2_PR
-      NEW met1 ( 1791930 1683510 ) M1M2_PR ;
-    - la_data_in[78] ( PIN la_data_in[78] ) ( mprj la_data_in[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2012730 2380 0 ) ( * 26010 )
-      NEW met1 ( 1799750 26010 ) ( 2012730 * )
-      NEW met1 ( 1797450 1683510 ) ( 1799750 * )
-      NEW met2 ( 1797450 1683510 ) ( * 1690140 )
-      NEW met2 ( 1796300 1690140 0 ) ( 1797450 * )
-      NEW met2 ( 1799750 26010 ) ( * 1683510 )
-      NEW met1 ( 1799750 26010 ) M1M2_PR
-      NEW met1 ( 2012730 26010 ) M1M2_PR
-      NEW met1 ( 1799750 1683510 ) M1M2_PR
-      NEW met1 ( 1797450 1683510 ) M1M2_PR ;
-    - la_data_in[79] ( PIN la_data_in[79] ) ( mprj la_data_in[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2030210 2380 0 ) ( * 25330 )
-      NEW met1 ( 1806190 25330 ) ( 2030210 * )
-      NEW met1 ( 1802970 1679770 ) ( 1805730 * )
-      NEW met2 ( 1802970 1679770 ) ( * 1690140 )
-      NEW met2 ( 1801820 1690140 0 ) ( 1802970 * )
-      NEW met2 ( 1806190 25330 ) ( * 1607700 )
-      NEW met2 ( 1805730 1607700 ) ( 1806190 * )
-      NEW met2 ( 1805730 1607700 ) ( * 1679770 )
-      NEW met1 ( 2030210 25330 ) M1M2_PR
-      NEW met1 ( 1806190 25330 ) M1M2_PR
-      NEW met1 ( 1805730 1679770 ) M1M2_PR
-      NEW met1 ( 1802970 1679770 ) M1M2_PR ;
-    - la_data_in[7] ( PIN la_data_in[7] ) ( mprj la_data_in[7] ) + USE SIGNAL
-      + ROUTED met2 ( 753250 2380 0 ) ( * 3060 )
-      NEW met2 ( 753250 3060 ) ( 754170 * )
-      NEW met2 ( 754170 2380 ) ( * 3060 )
-      NEW met2 ( 754170 2380 ) ( 755550 * )
-      NEW met1 ( 758770 1667870 ) ( 1407370 * )
-      NEW met2 ( 755550 2380 ) ( * 34500 )
-      NEW met2 ( 755550 34500 ) ( 758770 * )
-      NEW met2 ( 758770 34500 ) ( * 1667870 )
-      NEW met2 ( 1407370 1690140 ) ( 1407600 * 0 )
-      NEW met2 ( 1407370 1667870 ) ( * 1690140 )
-      NEW met1 ( 758770 1667870 ) M1M2_PR
-      NEW met1 ( 1407370 1667870 ) M1M2_PR ;
-    - la_data_in[80] ( PIN la_data_in[80] ) ( mprj la_data_in[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2048150 2380 0 ) ( * 24310 )
-      NEW met1 ( 1807110 24310 ) ( 2048150 * )
-      NEW met2 ( 1807110 1690140 ) ( 1807340 * 0 )
-      NEW met2 ( 1807110 24310 ) ( * 1690140 )
-      NEW met1 ( 2048150 24310 ) M1M2_PR
-      NEW met1 ( 1807110 24310 ) M1M2_PR ;
-    - la_data_in[81] ( PIN la_data_in[81] ) ( mprj la_data_in[81] ) + USE SIGNAL
-      + ROUTED met2 ( 2065630 2380 0 ) ( * 23970 )
-      NEW met1 ( 1813550 23970 ) ( 2065630 * )
-      NEW met2 ( 1812860 1690140 0 ) ( 1813550 * )
-      NEW met2 ( 1813550 23970 ) ( * 1690140 )
-      NEW met1 ( 1813550 23970 ) M1M2_PR
-      NEW met1 ( 2065630 23970 ) M1M2_PR ;
-    - la_data_in[82] ( PIN la_data_in[82] ) ( mprj la_data_in[82] ) + USE SIGNAL
-      + ROUTED met2 ( 1819530 1678750 ) ( * 1690140 )
-      NEW met2 ( 1818380 1690140 0 ) ( 1819530 * )
-      NEW met1 ( 1819530 1678750 ) ( 1880250 * )
-      NEW met2 ( 1880250 45050 ) ( * 1678750 )
-      NEW met1 ( 1880250 45050 ) ( 2083570 * )
-      NEW met2 ( 2083570 2380 0 ) ( * 45050 )
-      NEW met1 ( 1819530 1678750 ) M1M2_PR
-      NEW met1 ( 1880250 45050 ) M1M2_PR
-      NEW met1 ( 1880250 1678750 ) M1M2_PR
-      NEW met1 ( 2083570 45050 ) M1M2_PR ;
-    - la_data_in[83] ( PIN la_data_in[83] ) ( mprj la_data_in[83] ) + USE SIGNAL
-      + ROUTED met2 ( 1825050 1677390 ) ( * 1690140 )
-      NEW met2 ( 1823900 1690140 0 ) ( 1825050 * )
-      NEW met1 ( 2087250 48110 ) ( 2101050 * )
-      NEW met2 ( 2101050 2380 0 ) ( * 48110 )
-      NEW met1 ( 1825050 1677390 ) ( 2087250 * )
-      NEW met2 ( 2087250 48110 ) ( * 1677390 )
-      NEW met1 ( 1825050 1677390 ) M1M2_PR
-      NEW met1 ( 2087250 48110 ) M1M2_PR
-      NEW met1 ( 2101050 48110 ) M1M2_PR
-      NEW met1 ( 2087250 1677390 ) M1M2_PR ;
-    - la_data_in[84] ( PIN la_data_in[84] ) ( mprj la_data_in[84] ) + USE SIGNAL
-      + ROUTED met2 ( 1830570 1678070 ) ( * 1690140 )
-      NEW met2 ( 1829420 1690140 0 ) ( 1830570 * )
-      NEW met2 ( 2118990 2380 0 ) ( * 41650 )
-      NEW met1 ( 2107950 41650 ) ( 2118990 * )
-      NEW li1 ( 2065630 1676710 ) ( * 1678070 )
-      NEW met1 ( 2065630 1676710 ) ( 2107950 * )
-      NEW met1 ( 1830570 1678070 ) ( 2065630 * )
-      NEW met2 ( 2107950 41650 ) ( * 1676710 )
-      NEW met1 ( 1830570 1678070 ) M1M2_PR
-      NEW met1 ( 2118990 41650 ) M1M2_PR
-      NEW met1 ( 2107950 41650 ) M1M2_PR
-      NEW li1 ( 2065630 1678070 ) L1M1_PR_MR
-      NEW li1 ( 2065630 1676710 ) L1M1_PR_MR
-      NEW met1 ( 2107950 1676710 ) M1M2_PR ;
-    - la_data_in[85] ( PIN la_data_in[85] ) ( mprj la_data_in[85] ) + USE SIGNAL
-      + ROUTED met2 ( 1834710 1677050 ) ( * 1690140 )
-      NEW met2 ( 1834710 1690140 ) ( 1834940 * 0 )
-      NEW met2 ( 2136470 2380 0 ) ( * 45390 )
-      NEW met1 ( 2094150 45390 ) ( 2136470 * )
-      NEW met1 ( 1834710 1677050 ) ( 2094150 * )
-      NEW met2 ( 2094150 45390 ) ( * 1677050 )
-      NEW met1 ( 1834710 1677050 ) M1M2_PR
-      NEW met1 ( 2136470 45390 ) M1M2_PR
-      NEW met1 ( 2094150 45390 ) M1M2_PR
-      NEW met1 ( 2094150 1677050 ) M1M2_PR ;
-    - la_data_in[86] ( PIN la_data_in[86] ) ( mprj la_data_in[86] ) + USE SIGNAL
-      + ROUTED met2 ( 1840000 1690140 0 ) ( 1840690 * )
-      NEW met2 ( 1840690 1672630 ) ( * 1690140 )
-      NEW met2 ( 2153030 82800 ) ( 2154410 * )
-      NEW met2 ( 2154410 2380 0 ) ( * 82800 )
-      NEW met2 ( 2153030 82800 ) ( * 1672630 )
-      NEW met1 ( 1840690 1672630 ) ( 2153030 * )
-      NEW met1 ( 1840690 1672630 ) M1M2_PR
-      NEW met1 ( 2153030 1672630 ) M1M2_PR ;
-    - la_data_in[87] ( PIN la_data_in[87] ) ( mprj la_data_in[87] ) + USE SIGNAL
-      + ROUTED met2 ( 1846670 1681470 ) ( * 1690140 )
-      NEW met2 ( 1845520 1690140 0 ) ( 1846670 * )
-      NEW li1 ( 1880710 1679090 ) ( * 1681470 )
-      NEW met1 ( 1846670 1681470 ) ( 1880710 * )
-      NEW met1 ( 2163150 37570 ) ( 2172350 * )
-      NEW met2 ( 2172350 2380 0 ) ( * 37570 )
-      NEW met1 ( 1880710 1679090 ) ( 2163150 * )
-      NEW met2 ( 2163150 37570 ) ( * 1679090 )
-      NEW met1 ( 1846670 1681470 ) M1M2_PR
-      NEW li1 ( 1880710 1681470 ) L1M1_PR_MR
-      NEW li1 ( 1880710 1679090 ) L1M1_PR_MR
-      NEW met1 ( 2163150 37570 ) M1M2_PR
-      NEW met1 ( 2172350 37570 ) M1M2_PR
-      NEW met1 ( 2163150 1679090 ) M1M2_PR ;
-    - la_data_in[88] ( PIN la_data_in[88] ) ( mprj la_data_in[88] ) + USE SIGNAL
-      + ROUTED met2 ( 1852190 1679430 ) ( * 1690140 )
-      NEW met2 ( 1851040 1690140 0 ) ( 1852190 * )
-      NEW met1 ( 2176950 37570 ) ( 2189830 * )
-      NEW met2 ( 2189830 2380 0 ) ( * 37570 )
-      NEW met1 ( 1852190 1679430 ) ( 2176950 * )
-      NEW met2 ( 2176950 37570 ) ( * 1679430 )
-      NEW met1 ( 1852190 1679430 ) M1M2_PR
-      NEW met1 ( 2176950 37570 ) M1M2_PR
-      NEW met1 ( 2189830 37570 ) M1M2_PR
-      NEW met1 ( 2176950 1679430 ) M1M2_PR ;
-    - la_data_in[89] ( PIN la_data_in[89] ) ( mprj la_data_in[89] ) + USE SIGNAL
-      + ROUTED met2 ( 1856560 1690140 0 ) ( 1857710 * )
-      NEW met2 ( 1857710 1676370 ) ( * 1690140 )
-      NEW met1 ( 1857710 1676370 ) ( 2201790 * )
-      NEW met1 ( 2201790 58650 ) ( 2207770 * )
-      NEW met2 ( 2207770 2380 0 ) ( * 58650 )
-      NEW met2 ( 2201790 58650 ) ( * 1676370 )
-      NEW met1 ( 1857710 1676370 ) M1M2_PR
-      NEW met1 ( 2201790 1676370 ) M1M2_PR
-      NEW met1 ( 2201790 58650 ) M1M2_PR
-      NEW met1 ( 2207770 58650 ) M1M2_PR ;
-    - la_data_in[8] ( PIN la_data_in[8] ) ( mprj la_data_in[8] ) + USE SIGNAL
-      + ROUTED met2 ( 771190 2380 0 ) ( * 26350 )
-      NEW met1 ( 771190 26350 ) ( 852150 * )
-      NEW met2 ( 852150 26350 ) ( * 1682150 )
-      NEW met2 ( 1410590 1682150 ) ( * 1682660 )
-      NEW met2 ( 1410590 1682660 ) ( 1411970 * )
-      NEW met2 ( 1411970 1682660 ) ( * 1690140 )
-      NEW met2 ( 1411970 1690140 ) ( 1413120 * 0 )
-      NEW met1 ( 852150 1682150 ) ( 1410590 * )
-      NEW met1 ( 771190 26350 ) M1M2_PR
-      NEW met1 ( 852150 26350 ) M1M2_PR
-      NEW met1 ( 852150 1682150 ) M1M2_PR
-      NEW met1 ( 1410590 1682150 ) M1M2_PR ;
-    - la_data_in[90] ( PIN la_data_in[90] ) ( mprj la_data_in[90] ) + USE SIGNAL
-      + ROUTED met2 ( 1862770 1683510 ) ( * 1690140 )
-      NEW met2 ( 1862080 1690140 0 ) ( 1862770 * )
-      NEW met2 ( 2225250 2380 0 ) ( * 37570 )
-      NEW met1 ( 2197650 37570 ) ( 2225250 * )
-      NEW met1 ( 1862770 1683510 ) ( 2197650 * )
-      NEW met2 ( 2197650 37570 ) ( * 1683510 )
-      NEW met1 ( 1862770 1683510 ) M1M2_PR
-      NEW met1 ( 2225250 37570 ) M1M2_PR
-      NEW met1 ( 2197650 37570 ) M1M2_PR
-      NEW met1 ( 2197650 1683510 ) M1M2_PR ;
-    - la_data_in[91] ( PIN la_data_in[91] ) ( mprj la_data_in[91] ) + USE SIGNAL
-      + ROUTED met2 ( 2243190 2380 0 ) ( * 28050 )
-      NEW met2 ( 1869210 28050 ) ( * 1676700 )
-      NEW met2 ( 1868750 1676700 ) ( 1869210 * )
-      NEW met2 ( 1868750 1676700 ) ( * 1690140 )
-      NEW met2 ( 1867600 1690140 0 ) ( 1868750 * )
-      NEW met1 ( 1869210 28050 ) ( 2243190 * )
-      NEW met1 ( 1869210 28050 ) M1M2_PR
-      NEW met1 ( 2243190 28050 ) M1M2_PR ;
-    - la_data_in[92] ( PIN la_data_in[92] ) ( mprj la_data_in[92] ) + USE SIGNAL
-      + ROUTED met2 ( 2260670 2380 0 ) ( * 28390 )
-      NEW met1 ( 1876110 28390 ) ( 2260670 * )
-      NEW met2 ( 1874270 1628400 ) ( 1876110 * )
-      NEW met2 ( 1876110 28390 ) ( * 1628400 )
-      NEW met2 ( 1873120 1690140 0 ) ( 1874270 * )
-      NEW met2 ( 1874270 1628400 ) ( * 1690140 )
-      NEW met1 ( 1876110 28390 ) M1M2_PR
-      NEW met1 ( 2260670 28390 ) M1M2_PR ;
-    - la_data_in[93] ( PIN la_data_in[93] ) ( mprj la_data_in[93] ) + USE SIGNAL
-      + ROUTED met2 ( 2278610 2380 0 ) ( * 28730 )
-      NEW met1 ( 1883470 28730 ) ( 2278610 * )
-      NEW met1 ( 1879790 1682830 ) ( 1883470 * )
-      NEW met2 ( 1879790 1682830 ) ( * 1690140 )
-      NEW met2 ( 1878640 1690140 0 ) ( 1879790 * )
-      NEW met2 ( 1883470 28730 ) ( * 1682830 )
-      NEW met1 ( 1883470 28730 ) M1M2_PR
-      NEW met1 ( 2278610 28730 ) M1M2_PR
-      NEW met1 ( 1883470 1682830 ) M1M2_PR
-      NEW met1 ( 1879790 1682830 ) M1M2_PR ;
-    - la_data_in[94] ( PIN la_data_in[94] ) ( mprj la_data_in[94] ) + USE SIGNAL
-      + ROUTED met2 ( 2296090 2380 0 ) ( * 29070 )
-      NEW met1 ( 1889450 29070 ) ( 2296090 * )
-      NEW met1 ( 1885310 1681130 ) ( 1889450 * )
-      NEW met2 ( 1885310 1681130 ) ( * 1690140 )
-      NEW met2 ( 1884160 1690140 0 ) ( 1885310 * )
-      NEW met2 ( 1889450 29070 ) ( * 1681130 )
-      NEW met1 ( 1889450 29070 ) M1M2_PR
-      NEW met1 ( 2296090 29070 ) M1M2_PR
-      NEW met1 ( 1889450 1681130 ) M1M2_PR
-      NEW met1 ( 1885310 1681130 ) M1M2_PR ;
-    - la_data_in[95] ( PIN la_data_in[95] ) ( mprj la_data_in[95] ) + USE SIGNAL
-      + ROUTED met2 ( 2314030 2380 0 ) ( * 29410 )
-      NEW met1 ( 1889910 29410 ) ( 2314030 * )
-      NEW met2 ( 1889680 1688780 ) ( 1889910 * )
-      NEW met2 ( 1889680 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1889910 29410 ) ( * 1688780 )
-      NEW met1 ( 2314030 29410 ) M1M2_PR
-      NEW met1 ( 1889910 29410 ) M1M2_PR ;
-    - la_data_in[96] ( PIN la_data_in[96] ) ( mprj la_data_in[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2331510 2380 0 ) ( * 29750 )
-      NEW met1 ( 1897270 29750 ) ( 2331510 * )
-      NEW met2 ( 1895890 1628400 ) ( 1897270 * )
-      NEW met2 ( 1897270 29750 ) ( * 1628400 )
-      NEW met2 ( 1895200 1690140 0 ) ( 1895890 * )
-      NEW met2 ( 1895890 1628400 ) ( * 1690140 )
-      NEW met1 ( 2331510 29750 ) M1M2_PR
-      NEW met1 ( 1897270 29750 ) M1M2_PR ;
-    - la_data_in[97] ( PIN la_data_in[97] ) ( mprj la_data_in[97] ) + USE SIGNAL
-      + ROUTED met2 ( 2349450 2380 0 ) ( * 30090 )
-      NEW met1 ( 1903710 30090 ) ( 2349450 * )
-      NEW met1 ( 1901410 1682830 ) ( 1903710 * )
-      NEW met2 ( 1901410 1682830 ) ( * 1690140 )
-      NEW met2 ( 1900260 1690140 0 ) ( 1901410 * )
-      NEW met2 ( 1903710 30090 ) ( * 1682830 )
-      NEW met1 ( 2349450 30090 ) M1M2_PR
-      NEW met1 ( 1903710 30090 ) M1M2_PR
-      NEW met1 ( 1903710 1682830 ) M1M2_PR
-      NEW met1 ( 1901410 1682830 ) M1M2_PR ;
-    - la_data_in[98] ( PIN la_data_in[98] ) ( mprj la_data_in[98] ) + USE SIGNAL
-      + ROUTED met2 ( 2367390 2380 0 ) ( * 30430 )
-      NEW met1 ( 1910610 30430 ) ( 2367390 * )
-      NEW met1 ( 1906930 1682490 ) ( 1910610 * )
-      NEW met2 ( 1906930 1682490 ) ( * 1690140 )
-      NEW met2 ( 1905780 1690140 0 ) ( 1906930 * )
-      NEW met2 ( 1910610 30430 ) ( * 1682490 )
-      NEW met1 ( 1910610 30430 ) M1M2_PR
-      NEW met1 ( 2367390 30430 ) M1M2_PR
-      NEW met1 ( 1910610 1682490 ) M1M2_PR
-      NEW met1 ( 1906930 1682490 ) M1M2_PR ;
-    - la_data_in[99] ( PIN la_data_in[99] ) ( mprj la_data_in[99] ) + USE SIGNAL
-      + ROUTED met2 ( 2384870 2380 0 ) ( * 33830 )
-      NEW met1 ( 1910150 33830 ) ( 2384870 * )
-      NEW met2 ( 1910150 1690140 ) ( 1911300 * 0 )
-      NEW met2 ( 1910150 33830 ) ( * 1690140 )
-      NEW met1 ( 1910150 33830 ) M1M2_PR
-      NEW met1 ( 2384870 33830 ) M1M2_PR ;
-    - la_data_in[9] ( PIN la_data_in[9] ) ( mprj la_data_in[9] ) + USE SIGNAL
-      + ROUTED met2 ( 789130 2380 0 ) ( * 3060 )
-      NEW met2 ( 789130 3060 ) ( 790050 * )
-      NEW met2 ( 790050 2380 ) ( * 3060 )
-      NEW met2 ( 790050 2380 ) ( 791430 * )
-      NEW met2 ( 791430 2380 ) ( * 34500 )
-      NEW met2 ( 791430 34500 ) ( 793270 * )
-      NEW met2 ( 793270 34500 ) ( * 1668210 )
-      NEW met1 ( 793270 1668210 ) ( 1413810 * )
-      NEW met1 ( 1413810 1683170 ) ( 1417030 * )
-      NEW met2 ( 1417030 1683170 ) ( * 1690140 )
-      NEW met2 ( 1417030 1690140 ) ( 1418180 * 0 )
-      NEW met2 ( 1413810 1668210 ) ( * 1683170 )
-      NEW met1 ( 793270 1668210 ) M1M2_PR
-      NEW met1 ( 1413810 1668210 ) M1M2_PR
-      NEW met1 ( 1413810 1683170 ) M1M2_PR
-      NEW met1 ( 1417030 1683170 ) M1M2_PR ;
-    - la_data_out[0] ( PIN la_data_out[0] ) ( mprj la_data_out[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1169550 59670 ) ( * 1677050 )
-      NEW met2 ( 1369650 1677050 ) ( * 1690140 )
-      NEW met2 ( 1369650 1690140 ) ( 1370800 * 0 )
-      NEW met2 ( 635030 2380 0 ) ( * 59670 )
-      NEW met1 ( 635030 59670 ) ( 1169550 * )
-      NEW met1 ( 1169550 1677050 ) ( 1369650 * )
-      NEW met1 ( 1169550 59670 ) M1M2_PR
-      NEW met1 ( 1169550 1677050 ) M1M2_PR
-      NEW met1 ( 1369650 1677050 ) M1M2_PR
-      NEW met1 ( 635030 59670 ) M1M2_PR ;
-    - la_data_out[100] ( PIN la_data_out[100] ) ( mprj la_data_out[100] ) + USE SIGNAL
-      + ROUTED met2 ( 2408790 2380 0 ) ( * 33490 )
-      NEW met1 ( 1919810 1682150 ) ( 1924410 * )
-      NEW met2 ( 1919810 1682150 ) ( * 1690140 )
-      NEW met2 ( 1918660 1690140 0 ) ( 1919810 * )
-      NEW met2 ( 1924410 33490 ) ( * 1682150 )
-      NEW met1 ( 1924410 33490 ) ( 2408790 * )
-      NEW met1 ( 1924410 33490 ) M1M2_PR
-      NEW met1 ( 2408790 33490 ) M1M2_PR
-      NEW met1 ( 1924410 1682150 ) M1M2_PR
-      NEW met1 ( 1919810 1682150 ) M1M2_PR ;
-    - la_data_out[101] ( PIN la_data_out[101] ) ( mprj la_data_out[101] ) + USE SIGNAL
-      + ROUTED met2 ( 2426270 2380 0 ) ( * 33150 )
-      NEW met2 ( 1923950 1690140 ) ( 1924180 * 0 )
-      NEW met2 ( 1923950 33150 ) ( * 1690140 )
-      NEW met1 ( 1923950 33150 ) ( 2426270 * )
-      NEW met1 ( 1923950 33150 ) M1M2_PR
-      NEW met1 ( 2426270 33150 ) M1M2_PR ;
-    - la_data_out[102] ( PIN la_data_out[102] ) ( mprj la_data_out[102] ) + USE SIGNAL
-      + ROUTED met2 ( 2444210 2380 0 ) ( * 32810 )
-      NEW met2 ( 1930850 1628400 ) ( 1931770 * )
-      NEW met2 ( 1931770 32810 ) ( * 1628400 )
-      NEW met2 ( 1929700 1690140 0 ) ( 1930850 * )
-      NEW met2 ( 1930850 1628400 ) ( * 1690140 )
-      NEW met1 ( 1931770 32810 ) ( 2444210 * )
-      NEW met1 ( 1931770 32810 ) M1M2_PR
-      NEW met1 ( 2444210 32810 ) M1M2_PR ;
-    - la_data_out[103] ( PIN la_data_out[103] ) ( mprj la_data_out[103] ) + USE SIGNAL
-      + ROUTED met1 ( 1936370 1682150 ) ( 1938670 * )
-      NEW met2 ( 1936370 1682150 ) ( * 1690140 )
-      NEW met2 ( 1935220 1690140 0 ) ( 1936370 * )
-      NEW met2 ( 1938670 32470 ) ( * 1682150 )
-      NEW met2 ( 2461690 2380 0 ) ( * 32470 )
-      NEW met1 ( 1938670 32470 ) ( 2461690 * )
-      NEW met1 ( 1938670 32470 ) M1M2_PR
-      NEW met1 ( 1938670 1682150 ) M1M2_PR
-      NEW met1 ( 1936370 1682150 ) M1M2_PR
-      NEW met1 ( 2461690 32470 ) M1M2_PR ;
-    - la_data_out[104] ( PIN la_data_out[104] ) ( mprj la_data_out[104] ) + USE SIGNAL
-      + ROUTED met1 ( 1941890 1682150 ) ( 1945570 * )
-      NEW met2 ( 1941890 1682150 ) ( * 1690140 )
-      NEW met2 ( 1940740 1690140 0 ) ( 1941890 * )
-      NEW met2 ( 1945570 32130 ) ( * 1682150 )
-      NEW met2 ( 2479630 2380 0 ) ( * 32130 )
-      NEW met1 ( 1945570 32130 ) ( 2479630 * )
-      NEW met1 ( 1945570 32130 ) M1M2_PR
-      NEW met1 ( 1945570 1682150 ) M1M2_PR
-      NEW met1 ( 1941890 1682150 ) M1M2_PR
-      NEW met1 ( 2479630 32130 ) M1M2_PR ;
-    - la_data_out[105] ( PIN la_data_out[105] ) ( mprj la_data_out[105] ) + USE SIGNAL
-      + ROUTED met1 ( 1947410 1682150 ) ( 1952010 * )
-      NEW met2 ( 1947410 1682150 ) ( * 1690140 )
-      NEW met2 ( 1946260 1690140 0 ) ( 1947410 * )
-      NEW met2 ( 1952010 31790 ) ( * 1682150 )
-      NEW met2 ( 2497110 2380 0 ) ( * 31790 )
-      NEW met1 ( 1952010 31790 ) ( 2497110 * )
-      NEW met1 ( 1952010 31790 ) M1M2_PR
-      NEW met1 ( 1952010 1682150 ) M1M2_PR
-      NEW met1 ( 1947410 1682150 ) M1M2_PR
-      NEW met1 ( 2497110 31790 ) M1M2_PR ;
-    - la_data_out[106] ( PIN la_data_out[106] ) ( mprj la_data_out[106] ) + USE SIGNAL
-      + ROUTED met2 ( 2515050 2380 0 ) ( * 15980 )
-      NEW met2 ( 2514590 15980 ) ( 2515050 * )
-      NEW met2 ( 2514590 15980 ) ( * 31450 )
-      NEW met2 ( 1951090 1690140 ) ( 1951780 * 0 )
-      NEW met2 ( 1951090 31450 ) ( * 1690140 )
-      NEW met1 ( 1951090 31450 ) ( 2514590 * )
-      NEW met1 ( 1951090 31450 ) M1M2_PR
-      NEW met1 ( 2514590 31450 ) M1M2_PR ;
-    - la_data_out[107] ( PIN la_data_out[107] ) ( mprj la_data_out[107] ) + USE SIGNAL
-      + ROUTED met2 ( 2532530 2380 0 ) ( * 31110 )
-      NEW met2 ( 1958450 31110 ) ( * 1676700 )
-      NEW met2 ( 1957990 1676700 ) ( 1958450 * )
-      NEW met2 ( 1957990 1676700 ) ( * 1690140 )
-      NEW met2 ( 1956840 1690140 0 ) ( 1957990 * )
-      NEW met1 ( 1958450 31110 ) ( 2532530 * )
-      NEW met1 ( 1958450 31110 ) M1M2_PR
-      NEW met1 ( 2532530 31110 ) M1M2_PR ;
-    - la_data_out[108] ( PIN la_data_out[108] ) ( mprj la_data_out[108] ) + USE SIGNAL
-      + ROUTED met2 ( 1963510 1679940 ) ( * 1690140 )
-      NEW met2 ( 1962360 1690140 0 ) ( 1963510 * )
-      NEW met2 ( 2535750 27710 ) ( * 1679940 )
-      NEW met2 ( 2550470 2380 0 ) ( * 27710 )
-      NEW met1 ( 2535750 27710 ) ( 2550470 * )
-      NEW met3 ( 1963510 1679940 ) ( 2535750 * )
-      NEW met1 ( 2535750 27710 ) M1M2_PR
-      NEW met2 ( 1963510 1679940 ) M2M3_PR_M
-      NEW met2 ( 2535750 1679940 ) M2M3_PR_M
-      NEW met1 ( 2550470 27710 ) M1M2_PR ;
-    - la_data_out[109] ( PIN la_data_out[109] ) ( mprj la_data_out[109] ) + USE SIGNAL
-      + ROUTED met2 ( 2567950 2380 0 ) ( * 15810 )
-      NEW met1 ( 2563350 15810 ) ( 2567950 * )
-      NEW met1 ( 1969030 1673650 ) ( 2563350 * )
-      NEW met2 ( 1967880 1690140 0 ) ( 1969030 * )
-      NEW met2 ( 1969030 1673650 ) ( * 1690140 )
-      NEW met2 ( 2563350 15810 ) ( * 1673650 )
-      NEW met1 ( 1969030 1673650 ) M1M2_PR
-      NEW met1 ( 2567950 15810 ) M1M2_PR
-      NEW met1 ( 2563350 15810 ) M1M2_PR
-      NEW met1 ( 2563350 1673650 ) M1M2_PR ;
-    - la_data_out[10] ( PIN la_data_out[10] ) ( mprj la_data_out[10] ) + USE SIGNAL
-      + ROUTED met1 ( 813970 1668550 ) ( 1424390 * )
-      NEW met2 ( 812590 2380 0 ) ( * 34500 )
-      NEW met2 ( 812590 34500 ) ( 813970 * )
-      NEW met2 ( 813970 34500 ) ( * 1668550 )
-      NEW met2 ( 1424390 1690140 ) ( 1425540 * 0 )
-      NEW met2 ( 1424390 1668550 ) ( * 1690140 )
-      NEW met1 ( 813970 1668550 ) M1M2_PR
-      NEW met1 ( 1424390 1668550 ) M1M2_PR ;
-    - la_data_out[110] ( PIN la_data_out[110] ) ( mprj la_data_out[110] ) + USE SIGNAL
-      + ROUTED met2 ( 2585890 2380 0 ) ( * 16490 )
-      NEW met1 ( 2577150 16490 ) ( 2585890 * )
-      NEW met1 ( 1973170 1667870 ) ( 2577150 * )
-      NEW met2 ( 1973170 1690140 ) ( 1973400 * 0 )
-      NEW met2 ( 1973170 1667870 ) ( * 1690140 )
-      NEW met2 ( 2577150 16490 ) ( * 1667870 )
-      NEW met1 ( 1973170 1667870 ) M1M2_PR
-      NEW met1 ( 2585890 16490 ) M1M2_PR
-      NEW met1 ( 2577150 16490 ) M1M2_PR
-      NEW met1 ( 2577150 1667870 ) M1M2_PR ;
-    - la_data_out[111] ( PIN la_data_out[111] ) ( mprj la_data_out[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2603830 2380 0 ) ( * 3060 )
-      NEW met2 ( 2602910 3060 ) ( 2603830 * )
-      NEW met2 ( 2602910 2380 ) ( * 3060 )
-      NEW met2 ( 2601530 2380 ) ( 2602910 * )
-      NEW met2 ( 2601530 2380 ) ( * 1667530 )
-      NEW met1 ( 1979610 1667530 ) ( 2601530 * )
-      NEW met2 ( 1978920 1690140 0 ) ( 1979610 * )
-      NEW met2 ( 1979610 1667530 ) ( * 1690140 )
-      NEW met1 ( 2601530 1667530 ) M1M2_PR
-      NEW met1 ( 1979610 1667530 ) M1M2_PR ;
-    - la_data_out[112] ( PIN la_data_out[112] ) ( mprj la_data_out[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2621310 2380 0 ) ( * 16490 )
-      NEW met1 ( 2611650 16490 ) ( 2621310 * )
-      NEW met2 ( 2611650 16490 ) ( * 1673310 )
-      NEW met1 ( 1985590 1673310 ) ( 2611650 * )
-      NEW met2 ( 1984440 1690140 0 ) ( 1985590 * )
-      NEW met2 ( 1985590 1673310 ) ( * 1690140 )
-      NEW met1 ( 2621310 16490 ) M1M2_PR
-      NEW met1 ( 2611650 16490 ) M1M2_PR
-      NEW met1 ( 2611650 1673310 ) M1M2_PR
-      NEW met1 ( 1985590 1673310 ) M1M2_PR ;
-    - la_data_out[113] ( PIN la_data_out[113] ) ( mprj la_data_out[113] ) + USE SIGNAL
-      + ROUTED met2 ( 2639250 2380 0 ) ( * 16150 )
-      NEW met1 ( 2632350 16150 ) ( 2639250 * )
-      NEW met2 ( 2632350 16150 ) ( * 1672970 )
-      NEW met1 ( 1991110 1672970 ) ( 2632350 * )
-      NEW met2 ( 1989960 1690140 0 ) ( 1991110 * )
-      NEW met2 ( 1991110 1672970 ) ( * 1690140 )
-      NEW met1 ( 2639250 16150 ) M1M2_PR
-      NEW met1 ( 2632350 16150 ) M1M2_PR
-      NEW met1 ( 2632350 1672970 ) M1M2_PR
-      NEW met1 ( 1991110 1672970 ) M1M2_PR ;
-    - la_data_out[114] ( PIN la_data_out[114] ) ( mprj la_data_out[114] ) + USE SIGNAL
-      + ROUTED met1 ( 2038950 1666850 ) ( * 1667190 )
-      NEW met1 ( 1996630 1667190 ) ( 2038950 * )
-      NEW met2 ( 2656730 2380 0 ) ( * 16830 )
-      NEW met1 ( 2653050 16830 ) ( 2656730 * )
-      NEW met1 ( 2038950 1666850 ) ( 2653050 * )
-      NEW met2 ( 1995480 1690140 0 ) ( 1996630 * )
-      NEW met2 ( 1996630 1667190 ) ( * 1690140 )
-      NEW met2 ( 2653050 16830 ) ( * 1666850 )
-      NEW met1 ( 1996630 1667190 ) M1M2_PR
-      NEW met1 ( 2656730 16830 ) M1M2_PR
-      NEW met1 ( 2653050 16830 ) M1M2_PR
-      NEW met1 ( 2653050 1666850 ) M1M2_PR ;
-    - la_data_out[115] ( PIN la_data_out[115] ) ( mprj la_data_out[115] ) + USE SIGNAL
-      + ROUTED met1 ( 2038490 1666510 ) ( * 1666850 )
-      NEW met1 ( 2000770 1666850 ) ( 2038490 * )
-      NEW met2 ( 2674670 2380 0 ) ( * 16830 )
-      NEW met1 ( 2666850 16830 ) ( 2674670 * )
-      NEW met1 ( 2038490 1666510 ) ( 2666850 * )
-      NEW met2 ( 2000770 1690140 ) ( 2001000 * 0 )
-      NEW met2 ( 2000770 1666850 ) ( * 1690140 )
-      NEW met2 ( 2666850 16830 ) ( * 1666510 )
-      NEW met1 ( 2000770 1666850 ) M1M2_PR
-      NEW met1 ( 2674670 16830 ) M1M2_PR
-      NEW met1 ( 2666850 16830 ) M1M2_PR
-      NEW met1 ( 2666850 1666510 ) M1M2_PR ;
-    - la_data_out[116] ( PIN la_data_out[116] ) ( mprj la_data_out[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2691230 82800 ) ( 2692150 * )
-      NEW met2 ( 2692150 2380 0 ) ( * 82800 )
-      NEW met2 ( 2691230 82800 ) ( * 1666170 )
-      NEW met1 ( 2007670 1666170 ) ( 2691230 * )
-      NEW met2 ( 2006520 1690140 0 ) ( 2007670 * )
-      NEW met2 ( 2007670 1666170 ) ( * 1690140 )
-      NEW met1 ( 2691230 1666170 ) M1M2_PR
-      NEW met1 ( 2007670 1666170 ) M1M2_PR ;
-    - la_data_out[117] ( PIN la_data_out[117] ) ( mprj la_data_out[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2710090 2380 0 ) ( * 40970 )
-      NEW met2 ( 2012040 1690140 0 ) ( 2013190 * )
-      NEW met2 ( 2013190 40970 ) ( * 1690140 )
-      NEW met1 ( 2013190 40970 ) ( 2710090 * )
-      NEW met1 ( 2710090 40970 ) M1M2_PR
-      NEW met1 ( 2013190 40970 ) M1M2_PR ;
-    - la_data_out[118] ( PIN la_data_out[118] ) ( mprj la_data_out[118] ) + USE SIGNAL
-      + ROUTED met2 ( 2018250 1628400 ) ( 2020090 * )
-      NEW met2 ( 2020090 40630 ) ( * 1628400 )
-      NEW met2 ( 2017100 1690140 0 ) ( 2018250 * )
-      NEW met2 ( 2018250 1628400 ) ( * 1690140 )
-      NEW met2 ( 2727570 2380 0 ) ( * 40630 )
-      NEW met1 ( 2020090 40630 ) ( 2727570 * )
-      NEW met1 ( 2020090 40630 ) M1M2_PR
-      NEW met1 ( 2727570 40630 ) M1M2_PR ;
-    - la_data_out[119] ( PIN la_data_out[119] ) ( mprj la_data_out[119] ) + USE SIGNAL
-      + ROUTED met2 ( 2026530 1628400 ) ( 2026990 * )
-      NEW met2 ( 2026990 40290 ) ( * 1628400 )
-      NEW met1 ( 2023770 1676710 ) ( 2026530 * )
-      NEW met2 ( 2023770 1676710 ) ( * 1690140 )
-      NEW met2 ( 2022620 1690140 0 ) ( 2023770 * )
-      NEW met2 ( 2026530 1628400 ) ( * 1676710 )
-      NEW met1 ( 2026990 40290 ) ( 2745510 * )
-      NEW met2 ( 2745510 2380 0 ) ( * 40290 )
-      NEW met1 ( 2026990 40290 ) M1M2_PR
-      NEW met1 ( 2026530 1676710 ) M1M2_PR
-      NEW met1 ( 2023770 1676710 ) M1M2_PR
-      NEW met1 ( 2745510 40290 ) M1M2_PR ;
-    - la_data_out[11] ( PIN la_data_out[11] ) ( mprj la_data_out[11] ) + USE SIGNAL
-      + ROUTED met2 ( 830530 2380 0 ) ( * 33490 )
-      NEW met1 ( 830530 33490 ) ( 1429450 * )
-      NEW met2 ( 1429450 33490 ) ( * 1580100 )
-      NEW met2 ( 1429450 1580100 ) ( 1429910 * )
-      NEW met2 ( 1429910 1690140 ) ( 1431060 * 0 )
-      NEW met2 ( 1429910 1580100 ) ( * 1690140 )
-      NEW met1 ( 830530 33490 ) M1M2_PR
-      NEW met1 ( 1429450 33490 ) M1M2_PR ;
-    - la_data_out[120] ( PIN la_data_out[120] ) ( mprj la_data_out[120] ) + USE SIGNAL
-      + ROUTED met2 ( 2027450 1690140 ) ( 2028140 * 0 )
-      NEW met2 ( 2027450 39950 ) ( * 1690140 )
-      NEW met1 ( 2027450 39950 ) ( 2763450 * )
-      NEW met2 ( 2763450 2380 0 ) ( * 39950 )
-      NEW met1 ( 2027450 39950 ) M1M2_PR
-      NEW met1 ( 2763450 39950 ) M1M2_PR ;
-    - la_data_out[121] ( PIN la_data_out[121] ) ( mprj la_data_out[121] ) + USE SIGNAL
-      + ROUTED met2 ( 2033660 1688780 ) ( 2033890 * )
-      NEW met2 ( 2033660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2033890 39610 ) ( * 1688780 )
-      NEW met1 ( 2033890 39610 ) ( 2780930 * )
-      NEW met2 ( 2780930 2380 0 ) ( * 39610 )
-      NEW met1 ( 2033890 39610 ) M1M2_PR
-      NEW met1 ( 2780930 39610 ) M1M2_PR ;
-    - la_data_out[122] ( PIN la_data_out[122] ) ( mprj la_data_out[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2041250 39270 ) ( * 1676700 )
-      NEW met2 ( 2040330 1676700 ) ( 2041250 * )
-      NEW met2 ( 2040330 1676700 ) ( * 1690140 )
-      NEW met2 ( 2039180 1690140 0 ) ( 2040330 * )
-      NEW met2 ( 2798870 2380 0 ) ( * 39270 )
-      NEW met1 ( 2041250 39270 ) ( 2798870 * )
-      NEW met1 ( 2041250 39270 ) M1M2_PR
-      NEW met1 ( 2798870 39270 ) M1M2_PR ;
-    - la_data_out[123] ( PIN la_data_out[123] ) ( mprj la_data_out[123] ) + USE SIGNAL
-      + ROUTED met2 ( 2045850 1628400 ) ( 2047690 * )
-      NEW met2 ( 2047690 38930 ) ( * 1628400 )
-      NEW met2 ( 2044700 1690140 0 ) ( 2045850 * )
-      NEW met2 ( 2045850 1628400 ) ( * 1690140 )
-      NEW met2 ( 2816350 2380 0 ) ( * 38930 )
-      NEW met1 ( 2047690 38930 ) ( 2816350 * )
-      NEW met1 ( 2047690 38930 ) M1M2_PR
-      NEW met1 ( 2816350 38930 ) M1M2_PR ;
-    - la_data_out[124] ( PIN la_data_out[124] ) ( mprj la_data_out[124] ) + USE SIGNAL
-      + ROUTED met1 ( 2051370 1652230 ) ( 2055050 * )
-      NEW met2 ( 2055050 38590 ) ( * 1652230 )
-      NEW met2 ( 2050220 1690140 0 ) ( 2051370 * )
-      NEW met2 ( 2051370 1652230 ) ( * 1690140 )
-      NEW met2 ( 2834290 2380 0 ) ( * 38590 )
-      NEW met1 ( 2055050 38590 ) ( 2834290 * )
-      NEW met1 ( 2051370 1652230 ) M1M2_PR
-      NEW met1 ( 2055050 1652230 ) M1M2_PR
-      NEW met1 ( 2055050 38590 ) M1M2_PR
-      NEW met1 ( 2834290 38590 ) M1M2_PR ;
-    - la_data_out[125] ( PIN la_data_out[125] ) ( mprj la_data_out[125] ) + USE SIGNAL
-      + ROUTED met2 ( 2054590 1690140 ) ( 2055740 * 0 )
-      NEW met2 ( 2054590 38250 ) ( * 1690140 )
-      NEW met1 ( 2054590 38250 ) ( 2851770 * )
-      NEW met2 ( 2851770 2380 0 ) ( * 38250 )
-      NEW met1 ( 2054590 38250 ) M1M2_PR
-      NEW met1 ( 2851770 38250 ) M1M2_PR ;
-    - la_data_out[126] ( PIN la_data_out[126] ) ( mprj la_data_out[126] ) + USE SIGNAL
-      + ROUTED met2 ( 2061260 1688780 ) ( 2061490 * )
-      NEW met2 ( 2061260 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2061490 30770 ) ( * 1688780 )
-      NEW met2 ( 2869710 2380 0 ) ( * 30770 )
-      NEW met1 ( 2061490 30770 ) ( 2869710 * )
-      NEW met1 ( 2061490 30770 ) M1M2_PR
-      NEW met1 ( 2869710 30770 ) M1M2_PR ;
-    - la_data_out[127] ( PIN la_data_out[127] ) ( mprj la_data_out[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2887190 2380 0 ) ( * 37910 )
-      NEW met2 ( 2068850 37910 ) ( * 1676700 )
-      NEW met2 ( 2067930 1676700 ) ( 2068850 * )
-      NEW met2 ( 2067930 1676700 ) ( * 1690140 )
-      NEW met2 ( 2066780 1690140 0 ) ( 2067930 * )
-      NEW met1 ( 2068850 37910 ) ( 2887190 * )
-      NEW met1 ( 2887190 37910 ) M1M2_PR
-      NEW met1 ( 2068850 37910 ) M1M2_PR ;
-    - la_data_out[12] ( PIN la_data_out[12] ) ( mprj la_data_out[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1435890 1690140 ) ( 1436580 * 0 )
-      NEW met2 ( 1435890 33830 ) ( * 1690140 )
-      NEW met2 ( 848010 2380 0 ) ( * 33830 )
-      NEW met1 ( 848010 33830 ) ( 1435890 * )
-      NEW met1 ( 1435890 33830 ) M1M2_PR
-      NEW met1 ( 848010 33830 ) M1M2_PR ;
-    - la_data_out[13] ( PIN la_data_out[13] ) ( mprj la_data_out[13] ) + USE SIGNAL
-      + ROUTED met2 ( 865950 2380 0 ) ( * 30430 )
-      NEW met2 ( 1436350 30430 ) ( * 1580100 )
-      NEW met2 ( 1436350 1580100 ) ( 1440950 * )
-      NEW met2 ( 1440950 1690140 ) ( 1442100 * 0 )
-      NEW met2 ( 1440950 1580100 ) ( * 1690140 )
-      NEW met1 ( 865950 30430 ) ( 1436350 * )
-      NEW met1 ( 865950 30430 ) M1M2_PR
-      NEW met1 ( 1436350 30430 ) M1M2_PR ;
-    - la_data_out[14] ( PIN la_data_out[14] ) ( mprj la_data_out[14] ) + USE SIGNAL
-      + ROUTED met2 ( 883430 2380 0 ) ( * 30090 )
-      NEW met2 ( 1443250 30090 ) ( * 1580100 )
-      NEW met2 ( 1443250 1580100 ) ( 1445090 * )
-      NEW met2 ( 1445090 1683340 ) ( 1446470 * )
-      NEW met2 ( 1446470 1683340 ) ( * 1690140 )
-      NEW met2 ( 1446470 1690140 ) ( 1447620 * 0 )
-      NEW met2 ( 1445090 1580100 ) ( * 1683340 )
-      NEW met1 ( 883430 30090 ) ( 1443250 * )
-      NEW met1 ( 883430 30090 ) M1M2_PR
-      NEW met1 ( 1443250 30090 ) M1M2_PR ;
-    - la_data_out[15] ( PIN la_data_out[15] ) ( mprj la_data_out[15] ) + USE SIGNAL
-      + ROUTED met2 ( 901370 2380 0 ) ( * 29750 )
-      NEW met2 ( 1450150 29750 ) ( * 1580100 )
-      NEW met2 ( 1450150 1580100 ) ( 1451990 * )
-      NEW met2 ( 1451990 1690140 ) ( 1453140 * 0 )
-      NEW met2 ( 1451990 1580100 ) ( * 1690140 )
-      NEW met1 ( 901370 29750 ) ( 1450150 * )
-      NEW met1 ( 901370 29750 ) M1M2_PR
-      NEW met1 ( 1450150 29750 ) M1M2_PR ;
-    - la_data_out[16] ( PIN la_data_out[16] ) ( mprj la_data_out[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1457050 29410 ) ( * 1580100 )
-      NEW met2 ( 1457050 1580100 ) ( 1457510 * )
-      NEW met2 ( 1457510 1690140 ) ( 1458660 * 0 )
-      NEW met2 ( 1457510 1580100 ) ( * 1690140 )
-      NEW met2 ( 918850 2380 0 ) ( * 29410 )
-      NEW met1 ( 918850 29410 ) ( 1457050 * )
-      NEW met1 ( 1457050 29410 ) M1M2_PR
-      NEW met1 ( 918850 29410 ) M1M2_PR ;
-    - la_data_out[17] ( PIN la_data_out[17] ) ( mprj la_data_out[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1463490 1690140 ) ( 1464180 * 0 )
-      NEW met2 ( 1463490 29070 ) ( * 1690140 )
-      NEW met2 ( 936790 2380 0 ) ( * 29070 )
-      NEW met1 ( 936790 29070 ) ( 1463490 * )
-      NEW met1 ( 1463490 29070 ) M1M2_PR
-      NEW met1 ( 936790 29070 ) M1M2_PR ;
-    - la_data_out[18] ( PIN la_data_out[18] ) ( mprj la_data_out[18] ) + USE SIGNAL
-      + ROUTED met2 ( 954270 2380 0 ) ( * 28730 )
-      NEW met2 ( 1463950 28730 ) ( * 1580100 )
-      NEW met2 ( 1463950 1580100 ) ( 1468550 * )
-      NEW met2 ( 1468550 1690140 ) ( 1469700 * 0 )
-      NEW met2 ( 1468550 1580100 ) ( * 1690140 )
-      NEW met1 ( 954270 28730 ) ( 1463950 * )
-      NEW met1 ( 954270 28730 ) M1M2_PR
-      NEW met1 ( 1463950 28730 ) M1M2_PR ;
-    - la_data_out[19] ( PIN la_data_out[19] ) ( mprj la_data_out[19] ) + USE SIGNAL
-      + ROUTED met2 ( 972210 2380 0 ) ( * 28390 )
-      NEW met2 ( 1471310 28390 ) ( * 1580100 )
-      NEW met2 ( 1471310 1580100 ) ( 1474070 * )
-      NEW met2 ( 1474070 1690140 ) ( 1475220 * 0 )
-      NEW met2 ( 1474070 1580100 ) ( * 1690140 )
-      NEW met1 ( 972210 28390 ) ( 1471310 * )
-      NEW met1 ( 972210 28390 ) M1M2_PR
-      NEW met1 ( 1471310 28390 ) M1M2_PR ;
-    - la_data_out[1] ( PIN la_data_out[1] ) ( mprj la_data_out[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1374250 1676700 ) ( 1375170 * )
-      NEW met2 ( 1375170 1676700 ) ( * 1690140 )
-      NEW met2 ( 1375170 1690140 ) ( 1376320 * 0 )
-      NEW met2 ( 652970 2380 0 ) ( * 33150 )
-      NEW met1 ( 652970 33150 ) ( 1374250 * )
-      NEW met2 ( 1374250 33150 ) ( * 1676700 )
-      NEW met1 ( 1374250 33150 ) M1M2_PR
-      NEW met1 ( 652970 33150 ) M1M2_PR ;
-    - la_data_out[20] ( PIN la_data_out[20] ) ( mprj la_data_out[20] ) + USE SIGNAL
-      + ROUTED met2 ( 989690 2380 0 ) ( * 3060 )
-      NEW met2 ( 989690 3060 ) ( 990610 * )
-      NEW met2 ( 990610 2380 ) ( * 3060 )
-      NEW met2 ( 990610 2380 ) ( 991990 * )
-      NEW met2 ( 991990 2380 ) ( * 34500 )
-      NEW met2 ( 991990 34500 ) ( 993370 * )
-      NEW met2 ( 993370 34500 ) ( * 1669230 )
-      NEW met2 ( 1479130 1690140 ) ( 1480280 * 0 )
-      NEW met2 ( 1479130 1669230 ) ( * 1690140 )
-      NEW met1 ( 993370 1669230 ) ( 1479130 * )
-      NEW met1 ( 993370 1669230 ) M1M2_PR
-      NEW met1 ( 1479130 1669230 ) M1M2_PR ;
-    - la_data_out[21] ( PIN la_data_out[21] ) ( mprj la_data_out[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1482810 1672630 ) ( * 1682830 )
-      NEW met2 ( 1007630 2380 0 ) ( * 20910 )
-      NEW met1 ( 1007630 20910 ) ( 1014070 * )
-      NEW met1 ( 1014070 1672630 ) ( 1482810 * )
-      NEW met2 ( 1014070 20910 ) ( * 1672630 )
-      NEW met2 ( 1484650 1682830 ) ( * 1690140 )
-      NEW met2 ( 1484650 1690140 ) ( 1485800 * 0 )
-      NEW met1 ( 1482810 1682830 ) ( 1484650 * )
-      NEW met1 ( 1482810 1672630 ) M1M2_PR
-      NEW met1 ( 1482810 1682830 ) M1M2_PR
-      NEW met1 ( 1007630 20910 ) M1M2_PR
-      NEW met1 ( 1014070 20910 ) M1M2_PR
-      NEW met1 ( 1014070 1672630 ) M1M2_PR
-      NEW met1 ( 1484650 1682830 ) M1M2_PR ;
-    - la_data_out[22] ( PIN la_data_out[22] ) ( mprj la_data_out[22] ) + USE SIGNAL
-      + ROUTED met2 ( 1025570 2380 0 ) ( * 3060 )
-      NEW met2 ( 1025570 3060 ) ( 1026490 * )
-      NEW met2 ( 1026490 2380 ) ( * 3060 )
-      NEW met2 ( 1026490 2380 ) ( 1027870 * )
-      NEW met1 ( 1027870 1672290 ) ( 1490630 * )
-      NEW met2 ( 1027870 2380 ) ( * 1672290 )
-      NEW met2 ( 1490630 1690140 ) ( 1491320 * 0 )
-      NEW met2 ( 1490630 1672290 ) ( * 1690140 )
-      NEW met1 ( 1027870 1672290 ) M1M2_PR
-      NEW met1 ( 1490630 1672290 ) M1M2_PR ;
-    - la_data_out[23] ( PIN la_data_out[23] ) ( mprj la_data_out[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1043050 2380 0 ) ( * 3060 )
-      NEW met2 ( 1043050 3060 ) ( 1043970 * )
-      NEW met2 ( 1043970 2380 ) ( * 3060 )
-      NEW met2 ( 1043970 2380 ) ( 1045350 * )
-      NEW met1 ( 1048570 1669570 ) ( 1495690 * )
-      NEW met2 ( 1045350 2380 ) ( * 34500 )
-      NEW met2 ( 1045350 34500 ) ( 1048570 * )
-      NEW met2 ( 1048570 34500 ) ( * 1669570 )
-      NEW met2 ( 1495690 1690140 ) ( 1496840 * 0 )
-      NEW met2 ( 1495690 1669570 ) ( * 1690140 )
-      NEW met1 ( 1048570 1669570 ) M1M2_PR
-      NEW met1 ( 1495690 1669570 ) M1M2_PR ;
-    - la_data_out[24] ( PIN la_data_out[24] ) ( mprj la_data_out[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1060990 2380 0 ) ( * 20910 )
-      NEW met1 ( 1060990 20910 ) ( 1071570 * )
-      NEW met2 ( 1071570 20910 ) ( * 34500 )
-      NEW met2 ( 1071570 34500 ) ( 1072950 * )
-      NEW met2 ( 1072950 34500 ) ( * 1679770 )
-      NEW met2 ( 1501210 1679770 ) ( * 1690140 )
-      NEW met2 ( 1501210 1690140 ) ( 1502360 * 0 )
-      NEW met1 ( 1072950 1679770 ) ( 1501210 * )
-      NEW met1 ( 1060990 20910 ) M1M2_PR
-      NEW met1 ( 1071570 20910 ) M1M2_PR
-      NEW met1 ( 1072950 1679770 ) M1M2_PR
-      NEW met1 ( 1501210 1679770 ) M1M2_PR ;
-    - la_data_out[25] ( PIN la_data_out[25] ) ( mprj la_data_out[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1078470 2380 0 ) ( * 17340 )
-      NEW met2 ( 1078470 17340 ) ( 1080310 * )
-      NEW met2 ( 1080310 17340 ) ( * 34500 )
-      NEW met2 ( 1080310 34500 ) ( 1083070 * )
-      NEW met2 ( 1083070 34500 ) ( * 1671950 )
-      NEW met1 ( 1083070 1671950 ) ( 1503510 * )
-      NEW met1 ( 1503510 1683510 ) ( 1506730 * )
-      NEW met2 ( 1506730 1683510 ) ( * 1690140 )
-      NEW met2 ( 1506730 1690140 ) ( 1507880 * 0 )
-      NEW met2 ( 1503510 1671950 ) ( * 1683510 )
-      NEW met1 ( 1083070 1671950 ) M1M2_PR
-      NEW met1 ( 1503510 1671950 ) M1M2_PR
-      NEW met1 ( 1503510 1683510 ) M1M2_PR
-      NEW met1 ( 1506730 1683510 ) M1M2_PR ;
-    - la_data_out[26] ( PIN la_data_out[26] ) ( mprj la_data_out[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1096410 2380 0 ) ( * 1665830 )
-      NEW met1 ( 1096410 1665830 ) ( 1512250 * )
-      NEW met2 ( 1512250 1690140 ) ( 1513400 * 0 )
-      NEW met2 ( 1512250 1665830 ) ( * 1690140 )
-      NEW met1 ( 1096410 1665830 ) M1M2_PR
-      NEW met1 ( 1512250 1665830 ) M1M2_PR ;
-    - la_data_out[27] ( PIN la_data_out[27] ) ( mprj la_data_out[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1113890 2380 0 ) ( * 3060 )
-      NEW met2 ( 1113890 3060 ) ( 1114810 * )
-      NEW met2 ( 1114810 2380 ) ( * 3060 )
-      NEW met2 ( 1114810 2380 ) ( 1116190 * )
-      NEW met1 ( 1117570 1671610 ) ( 1518230 * )
-      NEW met2 ( 1116190 2380 ) ( * 34500 )
-      NEW met2 ( 1116190 34500 ) ( 1117570 * )
-      NEW met2 ( 1117570 34500 ) ( * 1671610 )
-      NEW met2 ( 1518230 1690140 ) ( 1518920 * 0 )
-      NEW met2 ( 1518230 1671610 ) ( * 1690140 )
-      NEW met1 ( 1117570 1671610 ) M1M2_PR
-      NEW met1 ( 1518230 1671610 ) M1M2_PR ;
-    - la_data_out[28] ( PIN la_data_out[28] ) ( mprj la_data_out[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1131830 2380 0 ) ( * 20910 )
-      NEW met1 ( 1131830 20910 ) ( 1138270 * )
-      NEW met1 ( 1138270 1665490 ) ( 1523290 * )
-      NEW met2 ( 1138270 20910 ) ( * 1665490 )
-      NEW met2 ( 1523290 1690140 ) ( 1524440 * 0 )
-      NEW met2 ( 1523290 1665490 ) ( * 1690140 )
-      NEW met1 ( 1131830 20910 ) M1M2_PR
-      NEW met1 ( 1138270 20910 ) M1M2_PR
-      NEW met1 ( 1138270 1665490 ) M1M2_PR
-      NEW met1 ( 1523290 1665490 ) M1M2_PR ;
-    - la_data_out[29] ( PIN la_data_out[29] ) ( mprj la_data_out[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1149310 2380 0 ) ( * 35530 )
-      NEW met1 ( 1525590 1652230 ) ( 1528810 * )
-      NEW met1 ( 1149310 35530 ) ( 1525590 * )
-      NEW met2 ( 1525590 35530 ) ( * 1652230 )
-      NEW met2 ( 1528810 1690140 ) ( 1529960 * 0 )
-      NEW met2 ( 1528810 1652230 ) ( * 1690140 )
-      NEW met1 ( 1149310 35530 ) M1M2_PR
-      NEW met1 ( 1525590 1652230 ) M1M2_PR
-      NEW met1 ( 1528810 1652230 ) M1M2_PR
-      NEW met1 ( 1525590 35530 ) M1M2_PR ;
-    - la_data_out[2] ( PIN la_data_out[2] ) ( mprj la_data_out[2] ) + USE SIGNAL
-      + ROUTED met2 ( 670910 2380 0 ) ( * 40970 )
-      NEW met2 ( 1381150 1690140 ) ( 1381840 * 0 )
-      NEW met1 ( 670910 40970 ) ( 1381150 * )
-      NEW met1 ( 1381150 1631150 ) ( * 1632170 )
-      NEW met2 ( 1381150 40970 ) ( * 1631150 )
-      NEW met2 ( 1381150 1632170 ) ( * 1690140 )
-      NEW met1 ( 670910 40970 ) M1M2_PR
-      NEW met1 ( 1381150 40970 ) M1M2_PR
-      NEW met1 ( 1381150 1631150 ) M1M2_PR
-      NEW met1 ( 1381150 1632170 ) M1M2_PR ;
-    - la_data_out[30] ( PIN la_data_out[30] ) ( mprj la_data_out[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1167250 2380 0 ) ( * 35190 )
-      NEW met2 ( 1532950 35190 ) ( * 1676700 )
-      NEW met2 ( 1532950 1676700 ) ( 1534330 * )
-      NEW met2 ( 1534330 1676700 ) ( * 1690140 )
-      NEW met2 ( 1534330 1690140 ) ( 1535480 * 0 )
-      NEW met1 ( 1167250 35190 ) ( 1532950 * )
-      NEW met1 ( 1167250 35190 ) M1M2_PR
-      NEW met1 ( 1532950 35190 ) M1M2_PR ;
-    - la_data_out[31] ( PIN la_data_out[31] ) ( mprj la_data_out[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1185190 2380 0 ) ( * 37910 )
-      NEW met2 ( 1539390 1690140 ) ( 1540540 * 0 )
-      NEW met2 ( 1539390 37910 ) ( * 1690140 )
-      NEW met1 ( 1185190 37910 ) ( 1539390 * )
-      NEW met1 ( 1185190 37910 ) M1M2_PR
-      NEW met1 ( 1539390 37910 ) M1M2_PR ;
-    - la_data_out[32] ( PIN la_data_out[32] ) ( mprj la_data_out[32] ) + USE SIGNAL
-      + ROUTED met2 ( 1546060 1688780 ) ( 1546290 * )
-      NEW met2 ( 1546060 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1546290 38250 ) ( * 1688780 )
-      NEW met2 ( 1202670 2380 0 ) ( * 38250 )
-      NEW met1 ( 1202670 38250 ) ( 1546290 * )
-      NEW met1 ( 1546290 38250 ) M1M2_PR
-      NEW met1 ( 1202670 38250 ) M1M2_PR ;
-    - la_data_out[33] ( PIN la_data_out[33] ) ( mprj la_data_out[33] ) + USE SIGNAL
-      + ROUTED met1 ( 1546750 1652570 ) ( 1550430 * )
-      NEW met2 ( 1546750 38590 ) ( * 1652570 )
-      NEW met2 ( 1550430 1690140 ) ( 1551580 * 0 )
-      NEW met2 ( 1550430 1652570 ) ( * 1690140 )
-      NEW met2 ( 1220610 2380 0 ) ( * 38590 )
-      NEW met1 ( 1220610 38590 ) ( 1546750 * )
-      NEW met1 ( 1546750 1652570 ) M1M2_PR
-      NEW met1 ( 1550430 1652570 ) M1M2_PR
-      NEW met1 ( 1546750 38590 ) M1M2_PR
-      NEW met1 ( 1220610 38590 ) M1M2_PR ;
-    - la_data_out[34] ( PIN la_data_out[34] ) ( mprj la_data_out[34] ) + USE SIGNAL
-      + ROUTED met1 ( 1553190 1652570 ) ( 1555950 * )
-      NEW met2 ( 1553190 38930 ) ( * 1652570 )
-      NEW met2 ( 1555950 1690140 ) ( 1557100 * 0 )
-      NEW met2 ( 1555950 1652570 ) ( * 1690140 )
-      NEW met2 ( 1238090 2380 0 ) ( * 38930 )
-      NEW met1 ( 1238090 38930 ) ( 1553190 * )
-      NEW met1 ( 1553190 1652570 ) M1M2_PR
-      NEW met1 ( 1555950 1652570 ) M1M2_PR
-      NEW met1 ( 1553190 38930 ) M1M2_PR
-      NEW met1 ( 1238090 38930 ) M1M2_PR ;
-    - la_data_out[35] ( PIN la_data_out[35] ) ( mprj la_data_out[35] ) + USE SIGNAL
-      + ROUTED met2 ( 1256030 2380 0 ) ( * 39610 )
-      NEW met2 ( 1560550 39270 ) ( * 1580100 )
-      NEW met2 ( 1560550 1580100 ) ( 1561470 * )
-      NEW met2 ( 1561470 1690140 ) ( 1562620 * 0 )
-      NEW met2 ( 1561470 1580100 ) ( * 1690140 )
-      NEW met1 ( 1290990 39270 ) ( * 39610 )
-      NEW met1 ( 1256030 39610 ) ( 1290990 * )
-      NEW met1 ( 1290990 39270 ) ( 1560550 * )
-      NEW met1 ( 1256030 39610 ) M1M2_PR
-      NEW met1 ( 1560550 39270 ) M1M2_PR ;
-    - la_data_out[36] ( PIN la_data_out[36] ) ( mprj la_data_out[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1273510 2380 0 ) ( * 39270 )
-      NEW met2 ( 1566990 1690140 ) ( 1568140 * 0 )
-      NEW met2 ( 1566990 39610 ) ( * 1690140 )
-      NEW li1 ( 1290530 39270 ) ( * 39950 )
-      NEW met1 ( 1290530 39950 ) ( 1291450 * )
-      NEW met1 ( 1291450 39610 ) ( * 39950 )
-      NEW met1 ( 1273510 39270 ) ( 1290530 * )
-      NEW met1 ( 1291450 39610 ) ( 1566990 * )
-      NEW met1 ( 1273510 39270 ) M1M2_PR
-      NEW met1 ( 1566990 39610 ) M1M2_PR
-      NEW li1 ( 1290530 39270 ) L1M1_PR_MR
-      NEW li1 ( 1290530 39950 ) L1M1_PR_MR ;
-    - la_data_out[37] ( PIN la_data_out[37] ) ( mprj la_data_out[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1573660 1688780 ) ( 1573890 * )
-      NEW met2 ( 1573660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1573890 39950 ) ( * 1688780 )
-      NEW met1 ( 1291450 40290 ) ( 1305250 * )
-      NEW met1 ( 1305250 39950 ) ( * 40290 )
-      NEW met2 ( 1291450 2380 0 ) ( * 40290 )
-      NEW met1 ( 1305250 39950 ) ( 1573890 * )
-      NEW met1 ( 1573890 39950 ) M1M2_PR
-      NEW met1 ( 1291450 40290 ) M1M2_PR ;
-    - la_data_out[38] ( PIN la_data_out[38] ) ( mprj la_data_out[38] ) + USE SIGNAL
-      + ROUTED met2 ( 1574350 40290 ) ( * 1580100 )
-      NEW met2 ( 1574350 1580100 ) ( 1578030 * )
-      NEW met2 ( 1578030 1690140 ) ( 1579180 * 0 )
-      NEW met2 ( 1578030 1580100 ) ( * 1690140 )
-      NEW met2 ( 1308930 2380 0 ) ( * 40290 )
-      NEW met1 ( 1308930 40290 ) ( 1574350 * )
-      NEW met1 ( 1574350 40290 ) M1M2_PR
-      NEW met1 ( 1308930 40290 ) M1M2_PR ;
-    - la_data_out[39] ( PIN la_data_out[39] ) ( mprj la_data_out[39] ) + USE SIGNAL
-      + ROUTED met2 ( 1326870 2380 0 ) ( * 40630 )
-      NEW met1 ( 1326870 40630 ) ( 1581250 * )
-      NEW met2 ( 1581250 40630 ) ( * 1676700 )
-      NEW met2 ( 1581250 1676700 ) ( 1583550 * )
-      NEW met2 ( 1583550 1676700 ) ( * 1690140 )
-      NEW met2 ( 1583550 1690140 ) ( 1584700 * 0 )
-      NEW met1 ( 1326870 40630 ) M1M2_PR
-      NEW met1 ( 1581250 40630 ) M1M2_PR ;
-    - la_data_out[3] ( PIN la_data_out[3] ) ( mprj la_data_out[3] ) + USE SIGNAL
-      + ROUTED met2 ( 688390 2380 0 ) ( * 41310 )
-      NEW met1 ( 688390 41310 ) ( 1388510 * )
-      NEW met2 ( 1387360 1688780 ) ( 1387590 * )
-      NEW met2 ( 1387360 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1387590 1631830 ) ( 1388510 * )
-      NEW met2 ( 1387590 1631830 ) ( * 1688780 )
-      NEW met2 ( 1388510 41310 ) ( * 1631830 )
-      NEW met1 ( 688390 41310 ) M1M2_PR
-      NEW met1 ( 1388510 41310 ) M1M2_PR
-      NEW met1 ( 1387590 1631830 ) M1M2_PR
-      NEW met1 ( 1388510 1631830 ) M1M2_PR ;
-    - la_data_out[40] ( PIN la_data_out[40] ) ( mprj la_data_out[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1344350 2380 0 ) ( * 31110 )
-      NEW met1 ( 1344350 31110 ) ( 1588610 * )
-      NEW met2 ( 1588610 31110 ) ( * 1580100 )
-      NEW met2 ( 1588610 1580100 ) ( 1589070 * )
-      NEW met2 ( 1589070 1690140 ) ( 1590220 * 0 )
-      NEW met2 ( 1589070 1580100 ) ( * 1690140 )
-      NEW met1 ( 1344350 31110 ) M1M2_PR
-      NEW met1 ( 1588610 31110 ) M1M2_PR ;
-    - la_data_out[41] ( PIN la_data_out[41] ) ( mprj la_data_out[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1362290 2380 0 ) ( * 17170 )
-      NEW met1 ( 1362290 17170 ) ( 1595050 * )
-      NEW met2 ( 1595050 1690140 ) ( 1595740 * 0 )
-      NEW met2 ( 1595050 17170 ) ( * 1690140 )
-      NEW met1 ( 1362290 17170 ) M1M2_PR
-      NEW met1 ( 1595050 17170 ) M1M2_PR ;
-    - la_data_out[42] ( PIN la_data_out[42] ) ( mprj la_data_out[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1380230 2380 0 ) ( * 14450 )
-      NEW met1 ( 1380230 14450 ) ( 1386670 * )
-      NEW met2 ( 1599650 1681810 ) ( * 1690140 )
-      NEW met2 ( 1599650 1690140 ) ( 1600800 * 0 )
-      NEW met1 ( 1386670 1681810 ) ( 1599650 * )
-      NEW met2 ( 1386670 14450 ) ( * 1681810 )
-      NEW met1 ( 1380230 14450 ) M1M2_PR
-      NEW met1 ( 1386670 14450 ) M1M2_PR
-      NEW met1 ( 1386670 1681810 ) M1M2_PR
-      NEW met1 ( 1599650 1681810 ) M1M2_PR ;
-    - la_data_out[43] ( PIN la_data_out[43] ) ( mprj la_data_out[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1397710 2380 0 ) ( * 17850 )
-      NEW met1 ( 1397710 17850 ) ( 1407830 * )
-      NEW met1 ( 1407830 17510 ) ( * 17850 )
-      NEW met1 ( 1407830 17510 ) ( 1601030 * )
-      NEW met1 ( 1601030 1652570 ) ( 1605170 * )
-      NEW met2 ( 1601030 17510 ) ( * 1652570 )
-      NEW met2 ( 1605170 1690140 ) ( 1606320 * 0 )
-      NEW met2 ( 1605170 1652570 ) ( * 1690140 )
-      NEW met1 ( 1397710 17850 ) M1M2_PR
-      NEW met1 ( 1601030 17510 ) M1M2_PR
-      NEW met1 ( 1601030 1652570 ) M1M2_PR
-      NEW met1 ( 1605170 1652570 ) M1M2_PR ;
-    - la_data_out[44] ( PIN la_data_out[44] ) ( mprj la_data_out[44] ) + USE SIGNAL
-      + ROUTED met2 ( 1415650 2380 0 ) ( * 17340 )
-      NEW met3 ( 1415650 17340 ) ( 1609310 * )
-      NEW met2 ( 1609310 17340 ) ( * 1580100 )
-      NEW met2 ( 1609310 1580100 ) ( 1610690 * )
-      NEW met2 ( 1610690 1690140 ) ( 1611840 * 0 )
-      NEW met2 ( 1610690 1580100 ) ( * 1690140 )
-      NEW met2 ( 1415650 17340 ) M2M3_PR_M
-      NEW met2 ( 1609310 17340 ) M2M3_PR_M ;
-    - la_data_out[45] ( PIN la_data_out[45] ) ( mprj la_data_out[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1433130 2380 0 ) ( * 18190 )
-      NEW met1 ( 1433130 18190 ) ( 1616210 * )
-      NEW met2 ( 1616210 1690140 ) ( 1617360 * 0 )
-      NEW met2 ( 1616210 18190 ) ( * 1690140 )
-      NEW met1 ( 1433130 18190 ) M1M2_PR
-      NEW met1 ( 1616210 18190 ) M1M2_PR ;
-    - la_data_out[46] ( PIN la_data_out[46] ) ( mprj la_data_out[46] ) + USE SIGNAL
-      + ROUTED met2 ( 1451070 2380 0 ) ( * 18020 )
-      NEW met3 ( 1451070 18020 ) ( 1622650 * )
-      NEW met2 ( 1622650 1690140 ) ( 1622880 * 0 )
-      NEW met2 ( 1622650 18020 ) ( * 1690140 )
-      NEW met2 ( 1451070 18020 ) M2M3_PR_M
-      NEW met2 ( 1622650 18020 ) M2M3_PR_M ;
-    - la_data_out[47] ( PIN la_data_out[47] ) ( mprj la_data_out[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1468550 2380 0 ) ( * 18870 )
-      NEW met2 ( 1621730 18870 ) ( * 19550 )
-      NEW met2 ( 1621730 19550 ) ( 1622190 * )
-      NEW met1 ( 1468550 18870 ) ( 1621730 * )
-      NEW met1 ( 1622190 1652230 ) ( 1627250 * )
-      NEW met2 ( 1622190 19550 ) ( * 1652230 )
-      NEW met2 ( 1627250 1690140 ) ( 1628400 * 0 )
-      NEW met2 ( 1627250 1652230 ) ( * 1690140 )
-      NEW met1 ( 1468550 18870 ) M1M2_PR
-      NEW met1 ( 1621730 18870 ) M1M2_PR
-      NEW met1 ( 1622190 1652230 ) M1M2_PR
-      NEW met1 ( 1627250 1652230 ) M1M2_PR ;
-    - la_data_out[48] ( PIN la_data_out[48] ) ( mprj la_data_out[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1629550 19550 ) ( * 1580100 )
-      NEW met2 ( 1629550 1580100 ) ( 1632770 * )
-      NEW met2 ( 1632770 1690140 ) ( 1633920 * 0 )
-      NEW met2 ( 1632770 1580100 ) ( * 1690140 )
-      NEW met2 ( 1486490 2380 0 ) ( * 19210 )
-      NEW met1 ( 1604250 19210 ) ( * 19550 )
-      NEW met1 ( 1486490 19210 ) ( 1604250 * )
-      NEW met1 ( 1604250 19550 ) ( 1629550 * )
-      NEW met1 ( 1629550 19550 ) M1M2_PR
-      NEW met1 ( 1486490 19210 ) M1M2_PR ;
-    - la_data_out[49] ( PIN la_data_out[49] ) ( mprj la_data_out[49] ) + USE SIGNAL
-      + ROUTED met2 ( 1637830 1683510 ) ( * 1684020 )
-      NEW met2 ( 1637830 1684020 ) ( 1638290 * )
-      NEW met2 ( 1638290 1684020 ) ( * 1690140 )
-      NEW met2 ( 1638290 1690140 ) ( 1639440 * 0 )
-      NEW met1 ( 1503970 1682830 ) ( 1508110 * )
-      NEW li1 ( 1508110 1682830 ) ( * 1683170 )
-      NEW li1 ( 1508110 1683170 ) ( 1509030 * )
-      NEW li1 ( 1509030 1683170 ) ( * 1683510 )
-      NEW met2 ( 1503970 2380 0 ) ( * 1682830 )
-      NEW met1 ( 1509030 1683510 ) ( 1637830 * )
-      NEW met1 ( 1637830 1683510 ) M1M2_PR
-      NEW met1 ( 1503970 1682830 ) M1M2_PR
-      NEW li1 ( 1508110 1682830 ) L1M1_PR_MR
-      NEW li1 ( 1509030 1683510 ) L1M1_PR_MR ;
-    - la_data_out[4] ( PIN la_data_out[4] ) ( mprj la_data_out[4] ) + USE SIGNAL
-      + ROUTED met2 ( 706330 2380 0 ) ( * 37570 )
-      NEW met1 ( 706330 37570 ) ( 1387590 * )
-      NEW met2 ( 1391730 1690140 ) ( 1392880 * 0 )
-      NEW met1 ( 1387590 1631150 ) ( 1391730 * )
-      NEW met2 ( 1387590 37570 ) ( * 1631150 )
-      NEW met2 ( 1391730 1631150 ) ( * 1690140 )
-      NEW met1 ( 706330 37570 ) M1M2_PR
-      NEW met1 ( 1387590 37570 ) M1M2_PR
-      NEW met1 ( 1387590 1631150 ) M1M2_PR
-      NEW met1 ( 1391730 1631150 ) M1M2_PR ;
-    - la_data_out[50] ( PIN la_data_out[50] ) ( mprj la_data_out[50] ) + USE SIGNAL
-      + ROUTED met2 ( 1642890 1679770 ) ( * 1684700 )
-      NEW met2 ( 1642890 1684700 ) ( 1643810 * )
-      NEW met2 ( 1643810 1684700 ) ( * 1690140 )
-      NEW met2 ( 1643810 1690140 ) ( 1644960 * 0 )
-      NEW met2 ( 1521910 2380 0 ) ( * 16830 )
-      NEW met1 ( 1521910 16830 ) ( 1524670 * )
-      NEW met2 ( 1524670 16830 ) ( * 1679770 )
-      NEW met1 ( 1524670 1679770 ) ( 1642890 * )
-      NEW met1 ( 1642890 1679770 ) M1M2_PR
-      NEW met1 ( 1521910 16830 ) M1M2_PR
-      NEW met1 ( 1524670 16830 ) M1M2_PR
-      NEW met1 ( 1524670 1679770 ) M1M2_PR ;
-    - la_data_out[51] ( PIN la_data_out[51] ) ( mprj la_data_out[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1539850 2380 0 ) ( * 20230 )
-      NEW met2 ( 1650250 1690140 ) ( 1650480 * 0 )
-      NEW met2 ( 1650250 20230 ) ( * 1690140 )
-      NEW met1 ( 1539850 20230 ) ( 1650250 * )
-      NEW met1 ( 1539850 20230 ) M1M2_PR
-      NEW met1 ( 1650250 20230 ) M1M2_PR ;
-    - la_data_out[52] ( PIN la_data_out[52] ) ( mprj la_data_out[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1557330 2380 0 ) ( * 16150 )
-      NEW met2 ( 1650710 16150 ) ( * 1580100 )
-      NEW met2 ( 1650710 1580100 ) ( 1654850 * )
-      NEW met2 ( 1654850 1690140 ) ( 1655540 * 0 )
-      NEW met2 ( 1654850 1580100 ) ( * 1690140 )
-      NEW met1 ( 1557330 16150 ) ( 1650710 * )
-      NEW met1 ( 1557330 16150 ) M1M2_PR
-      NEW met1 ( 1650710 16150 ) M1M2_PR ;
-    - la_data_out[53] ( PIN la_data_out[53] ) ( mprj la_data_out[53] ) + USE SIGNAL
-      + ROUTED met2 ( 1575270 2380 0 ) ( * 15130 )
-      NEW met2 ( 1659910 1690140 ) ( 1661060 * 0 )
-      NEW met1 ( 1575270 15130 ) ( 1656690 * )
-      NEW met1 ( 1656690 1631830 ) ( 1659910 * )
-      NEW met2 ( 1656690 15130 ) ( * 1631830 )
-      NEW met2 ( 1659910 1631830 ) ( * 1690140 )
-      NEW met1 ( 1575270 15130 ) M1M2_PR
-      NEW met1 ( 1656690 15130 ) M1M2_PR
-      NEW met1 ( 1656690 1631830 ) M1M2_PR
-      NEW met1 ( 1659910 1631830 ) M1M2_PR ;
-    - la_data_out[54] ( PIN la_data_out[54] ) ( mprj la_data_out[54] ) + USE SIGNAL
-      + ROUTED met1 ( 1663590 58650 ) ( 1664510 * )
-      NEW met2 ( 1664510 14110 ) ( * 58650 )
-      NEW met2 ( 1663590 1676700 ) ( 1665430 * )
-      NEW met2 ( 1665430 1676700 ) ( * 1690140 )
-      NEW met2 ( 1665430 1690140 ) ( 1666580 * 0 )
-      NEW met2 ( 1592750 2380 0 ) ( * 14110 )
-      NEW met1 ( 1592750 14110 ) ( 1664510 * )
-      NEW met2 ( 1663590 58650 ) ( * 1676700 )
-      NEW met1 ( 1664510 14110 ) M1M2_PR
-      NEW met1 ( 1663590 58650 ) M1M2_PR
-      NEW met1 ( 1664510 58650 ) M1M2_PR
-      NEW met1 ( 1592750 14110 ) M1M2_PR ;
-    - la_data_out[55] ( PIN la_data_out[55] ) ( mprj la_data_out[55] ) + USE SIGNAL
-      + ROUTED li1 ( 1649790 17510 ) ( * 18870 )
-      NEW met1 ( 1649790 18870 ) ( 1670950 * )
-      NEW met2 ( 1670950 1690140 ) ( 1672100 * 0 )
-      NEW met2 ( 1610690 2380 0 ) ( * 17510 )
-      NEW met1 ( 1610690 17510 ) ( 1649790 * )
-      NEW met2 ( 1670950 18870 ) ( * 1690140 )
-      NEW li1 ( 1649790 17510 ) L1M1_PR_MR
-      NEW li1 ( 1649790 18870 ) L1M1_PR_MR
-      NEW met1 ( 1670950 18870 ) M1M2_PR
-      NEW met1 ( 1610690 17510 ) M1M2_PR ;
-    - la_data_out[56] ( PIN la_data_out[56] ) ( mprj la_data_out[56] ) + USE SIGNAL
-      + ROUTED met2 ( 1628170 2380 0 ) ( * 18190 )
-      NEW met1 ( 1628170 18190 ) ( 1677850 * )
-      NEW met2 ( 1677620 1688780 ) ( 1677850 * )
-      NEW met2 ( 1677620 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1677850 18190 ) ( * 1688780 )
-      NEW met1 ( 1628170 18190 ) M1M2_PR
-      NEW met1 ( 1677850 18190 ) M1M2_PR ;
-    - la_data_out[57] ( PIN la_data_out[57] ) ( mprj la_data_out[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1646110 2380 0 ) ( * 19890 )
-      NEW met1 ( 1646110 19890 ) ( 1678310 * )
-      NEW met2 ( 1681990 1690140 ) ( 1683140 * 0 )
-      NEW met1 ( 1678310 1631830 ) ( 1681990 * )
-      NEW met2 ( 1678310 19890 ) ( * 1631830 )
-      NEW met2 ( 1681990 1631830 ) ( * 1690140 )
-      NEW met1 ( 1646110 19890 ) M1M2_PR
-      NEW met1 ( 1678310 19890 ) M1M2_PR
-      NEW met1 ( 1678310 1631830 ) M1M2_PR
-      NEW met1 ( 1681990 1631830 ) M1M2_PR ;
-    - la_data_out[58] ( PIN la_data_out[58] ) ( mprj la_data_out[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1663590 2380 0 ) ( * 20570 )
-      NEW met1 ( 1663590 20570 ) ( 1680150 * )
-      NEW met1 ( 1680150 1679090 ) ( 1687510 * )
-      NEW met2 ( 1687510 1679090 ) ( * 1690140 )
-      NEW met2 ( 1687510 1690140 ) ( 1688660 * 0 )
-      NEW met2 ( 1680150 20570 ) ( * 1679090 )
-      NEW met1 ( 1663590 20570 ) M1M2_PR
-      NEW met1 ( 1680150 20570 ) M1M2_PR
-      NEW met1 ( 1680150 1679090 ) M1M2_PR
-      NEW met1 ( 1687510 1679090 ) M1M2_PR ;
-    - la_data_out[59] ( PIN la_data_out[59] ) ( mprj la_data_out[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1681530 2380 0 ) ( * 17170 )
-      NEW met1 ( 1681530 17170 ) ( 1691190 * )
-      NEW met2 ( 1693030 1690140 ) ( 1694180 * 0 )
-      NEW met1 ( 1691190 1631830 ) ( 1693030 * )
-      NEW met2 ( 1691190 17170 ) ( * 1631830 )
-      NEW met2 ( 1693030 1631830 ) ( * 1690140 )
-      NEW met1 ( 1681530 17170 ) M1M2_PR
-      NEW met1 ( 1691190 17170 ) M1M2_PR
-      NEW met1 ( 1691190 1631830 ) M1M2_PR
-      NEW met1 ( 1693030 1631830 ) M1M2_PR ;
-    - la_data_out[5] ( PIN la_data_out[5] ) ( mprj la_data_out[5] ) + USE SIGNAL
-      + ROUTED met2 ( 723810 2380 0 ) ( * 37230 )
-      NEW met1 ( 723810 37230 ) ( 1394950 * )
-      NEW met2 ( 1394950 37230 ) ( * 1580100 )
-      NEW met2 ( 1394950 1580100 ) ( 1397250 * )
-      NEW met2 ( 1397250 1690140 ) ( 1398400 * 0 )
-      NEW met2 ( 1397250 1580100 ) ( * 1690140 )
-      NEW met1 ( 723810 37230 ) M1M2_PR
-      NEW met1 ( 1394950 37230 ) M1M2_PR ;
-    - la_data_out[60] ( PIN la_data_out[60] ) ( mprj la_data_out[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1699470 2380 0 ) ( * 3060 )
-      NEW met2 ( 1698550 3060 ) ( 1699470 * )
-      NEW met2 ( 1698550 2380 ) ( * 3060 )
-      NEW met2 ( 1697630 2380 ) ( 1698550 * )
-      NEW met1 ( 1697630 1683510 ) ( 1699010 * )
-      NEW met2 ( 1699010 1683510 ) ( * 1690140 )
-      NEW met2 ( 1699010 1690140 ) ( 1699700 * 0 )
-      NEW met2 ( 1697630 2380 ) ( * 1683510 )
-      NEW met1 ( 1697630 1683510 ) M1M2_PR
-      NEW met1 ( 1699010 1683510 ) M1M2_PR ;
-    - la_data_out[61] ( PIN la_data_out[61] ) ( mprj la_data_out[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1716950 2380 0 ) ( * 3060 )
-      NEW met2 ( 1716030 3060 ) ( 1716950 * )
-      NEW met2 ( 1716030 2380 ) ( * 3060 )
-      NEW met2 ( 1714650 2380 ) ( 1716030 * )
-      NEW met2 ( 1713270 82800 ) ( 1714650 * )
-      NEW met2 ( 1714650 2380 ) ( * 82800 )
-      NEW met1 ( 1706370 1683170 ) ( 1713270 * )
-      NEW met2 ( 1706370 1683170 ) ( * 1690140 )
-      NEW met2 ( 1705220 1690140 0 ) ( 1706370 * )
-      NEW met2 ( 1713270 82800 ) ( * 1683170 )
-      NEW met1 ( 1713270 1683170 ) M1M2_PR
-      NEW met1 ( 1706370 1683170 ) M1M2_PR ;
-    - la_data_out[62] ( PIN la_data_out[62] ) ( mprj la_data_out[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1734890 2380 0 ) ( * 18530 )
-      NEW met1 ( 1710970 18530 ) ( 1734890 * )
-      NEW met2 ( 1710740 1688780 ) ( 1710970 * )
-      NEW met2 ( 1710740 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1710970 18530 ) ( * 1688780 )
-      NEW met1 ( 1734890 18530 ) M1M2_PR
-      NEW met1 ( 1710970 18530 ) M1M2_PR ;
-    - la_data_out[63] ( PIN la_data_out[63] ) ( mprj la_data_out[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1752370 2380 0 ) ( * 20570 )
-      NEW met1 ( 1717870 20570 ) ( 1752370 * )
-      NEW met1 ( 1716490 1678410 ) ( 1717870 * )
-      NEW met2 ( 1716490 1678410 ) ( * 1690140 )
-      NEW met2 ( 1715800 1690140 0 ) ( 1716490 * )
-      NEW met2 ( 1717870 20570 ) ( * 1678410 )
-      NEW met1 ( 1752370 20570 ) M1M2_PR
-      NEW met1 ( 1717870 20570 ) M1M2_PR
-      NEW met1 ( 1717870 1678410 ) M1M2_PR
-      NEW met1 ( 1716490 1678410 ) M1M2_PR ;
-    - la_data_out[64] ( PIN la_data_out[64] ) ( mprj la_data_out[64] ) + USE SIGNAL
-      + ROUTED met2 ( 1770310 2380 0 ) ( * 15810 )
-      NEW met1 ( 1735350 15810 ) ( 1770310 * )
-      NEW met2 ( 1735350 15810 ) ( * 1677050 )
-      NEW met2 ( 1722470 1677050 ) ( * 1690140 )
-      NEW met2 ( 1721320 1690140 0 ) ( 1722470 * )
-      NEW met1 ( 1722470 1677050 ) ( 1735350 * )
-      NEW met1 ( 1770310 15810 ) M1M2_PR
-      NEW met1 ( 1735350 15810 ) M1M2_PR
-      NEW met1 ( 1735350 1677050 ) M1M2_PR
-      NEW met1 ( 1722470 1677050 ) M1M2_PR ;
-    - la_data_out[65] ( PIN la_data_out[65] ) ( mprj la_data_out[65] ) + USE SIGNAL
-      + ROUTED met1 ( 1727990 1682490 ) ( 1749150 * )
-      NEW met2 ( 1727990 1682490 ) ( * 1690140 )
-      NEW met2 ( 1726840 1690140 0 ) ( 1727990 * )
-      NEW met2 ( 1749150 15130 ) ( * 1682490 )
-      NEW met2 ( 1787790 2380 0 ) ( * 15130 )
-      NEW met1 ( 1749150 15130 ) ( 1787790 * )
-      NEW met1 ( 1749150 15130 ) M1M2_PR
-      NEW met1 ( 1749150 1682490 ) M1M2_PR
-      NEW met1 ( 1727990 1682490 ) M1M2_PR
-      NEW met1 ( 1787790 15130 ) M1M2_PR ;
-    - la_data_out[66] ( PIN la_data_out[66] ) ( mprj la_data_out[66] ) + USE SIGNAL
-      + ROUTED met1 ( 1752830 1682150 ) ( * 1682490 )
-      NEW met1 ( 1733510 1682150 ) ( 1752830 * )
-      NEW met2 ( 1733510 1682150 ) ( * 1690140 )
-      NEW met2 ( 1732360 1690140 0 ) ( 1733510 * )
-      NEW met2 ( 1805730 2380 0 ) ( * 14790 )
-      NEW met1 ( 1790550 14790 ) ( 1805730 * )
-      NEW met1 ( 1752830 1682490 ) ( 1790550 * )
-      NEW met2 ( 1790550 14790 ) ( * 1682490 )
-      NEW met1 ( 1733510 1682150 ) M1M2_PR
-      NEW met1 ( 1805730 14790 ) M1M2_PR
-      NEW met1 ( 1790550 14790 ) M1M2_PR
-      NEW met1 ( 1790550 1682490 ) M1M2_PR ;
-    - la_data_out[67] ( PIN la_data_out[67] ) ( mprj la_data_out[67] ) + USE SIGNAL
-      + ROUTED met1 ( 1738110 14790 ) ( 1770770 * )
-      NEW li1 ( 1770770 14790 ) ( * 15810 )
-      NEW met2 ( 1823210 2380 0 ) ( * 15810 )
-      NEW met2 ( 1737880 1688780 ) ( 1738110 * )
-      NEW met2 ( 1737880 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1738110 14790 ) ( * 1688780 )
-      NEW met1 ( 1770770 15810 ) ( 1823210 * )
-      NEW met1 ( 1738110 14790 ) M1M2_PR
-      NEW li1 ( 1770770 14790 ) L1M1_PR_MR
-      NEW li1 ( 1770770 15810 ) L1M1_PR_MR
-      NEW met1 ( 1823210 15810 ) M1M2_PR ;
-    - la_data_out[68] ( PIN la_data_out[68] ) ( mprj la_data_out[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1841150 2380 0 ) ( * 3060 )
-      NEW met2 ( 1840230 3060 ) ( 1841150 * )
-      NEW met2 ( 1840230 2380 ) ( * 3060 )
-      NEW met2 ( 1838850 2380 ) ( 1840230 * )
-      NEW met2 ( 1744550 1681470 ) ( * 1690140 )
-      NEW met2 ( 1743400 1690140 0 ) ( 1744550 * )
-      NEW met2 ( 1837470 82800 ) ( 1838850 * )
-      NEW met2 ( 1838850 2380 ) ( * 82800 )
-      NEW met1 ( 1744550 1681470 ) ( 1837010 * )
-      NEW met2 ( 1837010 1656000 ) ( * 1681470 )
-      NEW met2 ( 1837010 1656000 ) ( 1837470 * )
-      NEW met2 ( 1837470 82800 ) ( * 1656000 )
-      NEW met1 ( 1744550 1681470 ) M1M2_PR
-      NEW met1 ( 1837010 1681470 ) M1M2_PR ;
-    - la_data_out[69] ( PIN la_data_out[69] ) ( mprj la_data_out[69] ) + USE SIGNAL
-      + ROUTED met2 ( 1858630 2380 0 ) ( * 3060 )
-      NEW met2 ( 1857710 3060 ) ( 1858630 * )
-      NEW met2 ( 1857710 2380 ) ( * 3060 )
-      NEW met2 ( 1856790 2380 ) ( 1857710 * )
-      NEW met2 ( 1750070 1680790 ) ( * 1690140 )
-      NEW met2 ( 1748920 1690140 0 ) ( 1750070 * )
-      NEW met2 ( 1856790 2380 ) ( * 1680790 )
-      NEW met1 ( 1750070 1680790 ) ( 1856790 * )
-      NEW met1 ( 1750070 1680790 ) M1M2_PR
-      NEW met1 ( 1856790 1680790 ) M1M2_PR ;
-    - la_data_out[6] ( PIN la_data_out[6] ) ( mprj la_data_out[6] ) + USE SIGNAL
-      + ROUTED met2 ( 741750 2380 0 ) ( * 36890 )
-      NEW met1 ( 741750 36890 ) ( 1401850 * )
-      NEW met2 ( 1401850 36890 ) ( * 1580100 )
-      NEW met2 ( 1401850 1580100 ) ( 1402770 * )
-      NEW met2 ( 1402770 1690140 ) ( 1403920 * 0 )
-      NEW met2 ( 1402770 1580100 ) ( * 1690140 )
-      NEW met1 ( 741750 36890 ) M1M2_PR
-      NEW met1 ( 1401850 36890 ) M1M2_PR ;
-    - la_data_out[70] ( PIN la_data_out[70] ) ( mprj la_data_out[70] ) + USE SIGNAL
-      + ROUTED met1 ( 1755590 1683170 ) ( 1758810 * )
-      NEW met2 ( 1755590 1683170 ) ( * 1690140 )
-      NEW met2 ( 1754440 1690140 0 ) ( 1755590 * )
-      NEW met2 ( 1758810 20570 ) ( * 1683170 )
-      NEW met2 ( 1876570 2380 0 ) ( * 20570 )
-      NEW met1 ( 1758810 20570 ) ( 1876570 * )
-      NEW met1 ( 1758810 20570 ) M1M2_PR
-      NEW met1 ( 1758810 1683170 ) M1M2_PR
-      NEW met1 ( 1755590 1683170 ) M1M2_PR
-      NEW met1 ( 1876570 20570 ) M1M2_PR ;
-    - la_data_out[71] ( PIN la_data_out[71] ) ( mprj la_data_out[71] ) + USE SIGNAL
-      + ROUTED met2 ( 1761110 1681130 ) ( * 1690140 )
-      NEW met2 ( 1759960 1690140 0 ) ( 1761110 * )
-      NEW met2 ( 1859090 1628400 ) ( 1859550 * )
-      NEW met2 ( 1859550 30770 ) ( * 1628400 )
-      NEW met2 ( 1859090 1628400 ) ( * 1681130 )
-      NEW met2 ( 1894510 2380 0 ) ( * 30770 )
-      NEW met1 ( 1859550 30770 ) ( 1894510 * )
-      NEW met1 ( 1761110 1681130 ) ( 1859090 * )
-      NEW met1 ( 1859550 30770 ) M1M2_PR
-      NEW met1 ( 1761110 1681130 ) M1M2_PR
-      NEW met1 ( 1859090 1681130 ) M1M2_PR
-      NEW met1 ( 1894510 30770 ) M1M2_PR ;
-    - la_data_out[72] ( PIN la_data_out[72] ) ( mprj la_data_out[72] ) + USE SIGNAL
-      + ROUTED met2 ( 1765250 1690140 ) ( 1765480 * 0 )
-      NEW met2 ( 1765250 51510 ) ( * 1690140 )
-      NEW met1 ( 1765250 51510 ) ( 1911990 * )
-      NEW met2 ( 1911990 2380 0 ) ( * 51510 )
-      NEW met1 ( 1765250 51510 ) M1M2_PR
-      NEW met1 ( 1911990 51510 ) M1M2_PR ;
-    - la_data_out[73] ( PIN la_data_out[73] ) ( mprj la_data_out[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1772150 1682150 ) ( * 1690140 )
-      NEW met2 ( 1771000 1690140 0 ) ( 1772150 * )
-      NEW met2 ( 1852650 45050 ) ( * 1681810 )
-      NEW met2 ( 1929930 2380 0 ) ( * 44710 )
-      NEW met1 ( 1772150 1682150 ) ( 1773300 * )
-      NEW met1 ( 1773300 1681810 ) ( * 1682150 )
-      NEW met1 ( 1773300 1681810 ) ( 1852650 * )
-      NEW met1 ( 1852650 45050 ) ( 1869900 * )
-      NEW met1 ( 1869900 44710 ) ( * 45050 )
-      NEW met1 ( 1869900 44710 ) ( 1929930 * )
-      NEW met1 ( 1772150 1682150 ) M1M2_PR
-      NEW met1 ( 1852650 45050 ) M1M2_PR
-      NEW met1 ( 1852650 1681810 ) M1M2_PR
-      NEW met1 ( 1929930 44710 ) M1M2_PR ;
-    - la_data_out[74] ( PIN la_data_out[74] ) ( mprj la_data_out[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1947410 2380 0 ) ( * 51510 )
-      NEW met2 ( 1777210 1680450 ) ( * 1690140 )
-      NEW met2 ( 1776060 1690140 0 ) ( 1777210 * )
-      NEW met1 ( 1914750 51510 ) ( 1947410 * )
-      NEW li1 ( 1892210 1680450 ) ( * 1681130 )
-      NEW met1 ( 1892210 1681130 ) ( 1914750 * )
-      NEW met1 ( 1777210 1680450 ) ( 1892210 * )
-      NEW met2 ( 1914750 51510 ) ( * 1681130 )
-      NEW met1 ( 1947410 51510 ) M1M2_PR
-      NEW met1 ( 1777210 1680450 ) M1M2_PR
-      NEW met1 ( 1914750 51510 ) M1M2_PR
-      NEW li1 ( 1892210 1680450 ) L1M1_PR_MR
-      NEW li1 ( 1892210 1681130 ) L1M1_PR_MR
-      NEW met1 ( 1914750 1681130 ) M1M2_PR ;
-    - la_data_out[75] ( PIN la_data_out[75] ) ( mprj la_data_out[75] ) + USE SIGNAL
-      + ROUTED met2 ( 1965350 2380 0 ) ( * 3060 )
-      NEW met2 ( 1964430 3060 ) ( 1965350 * )
-      NEW met2 ( 1964430 2380 ) ( * 3060 )
-      NEW met2 ( 1963050 2380 ) ( 1964430 * )
-      NEW met2 ( 1959830 82800 ) ( 1963050 * )
-      NEW met2 ( 1963050 2380 ) ( * 82800 )
-      NEW met2 ( 1959830 82800 ) ( * 1672970 )
-      NEW met1 ( 1782730 1672970 ) ( 1959830 * )
-      NEW met2 ( 1781580 1690140 0 ) ( 1782730 * )
-      NEW met2 ( 1782730 1672970 ) ( * 1690140 )
-      NEW met1 ( 1959830 1672970 ) M1M2_PR
-      NEW met1 ( 1782730 1672970 ) M1M2_PR ;
-    - la_data_out[76] ( PIN la_data_out[76] ) ( mprj la_data_out[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1785950 1690140 ) ( 1787100 * 0 )
-      NEW met2 ( 1785950 45390 ) ( * 1690140 )
-      NEW met1 ( 1785950 45390 ) ( 1982830 * )
-      NEW met2 ( 1982830 2380 0 ) ( * 45390 )
-      NEW met1 ( 1785950 45390 ) M1M2_PR
-      NEW met1 ( 1982830 45390 ) M1M2_PR ;
-    - la_data_out[77] ( PIN la_data_out[77] ) ( mprj la_data_out[77] ) + USE SIGNAL
-      + ROUTED met2 ( 2000770 2380 0 ) ( * 26350 )
-      NEW met1 ( 1792850 26350 ) ( 2000770 * )
-      NEW met2 ( 1792620 1688780 ) ( 1792850 * )
-      NEW met2 ( 1792620 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1792850 26350 ) ( * 1688780 )
-      NEW met1 ( 1792850 26350 ) M1M2_PR
-      NEW met1 ( 2000770 26350 ) M1M2_PR ;
-    - la_data_out[78] ( PIN la_data_out[78] ) ( mprj la_data_out[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2018250 2380 0 ) ( * 25670 )
-      NEW met1 ( 1799290 25670 ) ( 2018250 * )
-      NEW met2 ( 1798140 1690140 0 ) ( 1799290 * )
-      NEW met2 ( 1799290 25670 ) ( * 1690140 )
-      NEW met1 ( 2018250 25670 ) M1M2_PR
-      NEW met1 ( 1799290 25670 ) M1M2_PR ;
-    - la_data_out[79] ( PIN la_data_out[79] ) ( mprj la_data_out[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2036190 2380 0 ) ( * 24990 )
-      NEW met1 ( 1806650 24990 ) ( 2036190 * )
-      NEW met2 ( 1803660 1690140 0 ) ( 1804810 * )
-      NEW met1 ( 1804810 1631830 ) ( 1806650 * )
-      NEW met2 ( 1804810 1631830 ) ( * 1690140 )
-      NEW met2 ( 1806650 24990 ) ( * 1631830 )
-      NEW met1 ( 2036190 24990 ) M1M2_PR
-      NEW met1 ( 1806650 24990 ) M1M2_PR
-      NEW met1 ( 1804810 1631830 ) M1M2_PR
-      NEW met1 ( 1806650 1631830 ) M1M2_PR ;
-    - la_data_out[7] ( PIN la_data_out[7] ) ( mprj la_data_out[7] ) + USE SIGNAL
-      + ROUTED met2 ( 759230 2380 0 ) ( * 36550 )
-      NEW met1 ( 759230 36550 ) ( 1408750 * )
-      NEW met2 ( 1408750 1690140 ) ( 1409440 * 0 )
-      NEW met2 ( 1408750 36550 ) ( * 1690140 )
-      NEW met1 ( 759230 36550 ) M1M2_PR
-      NEW met1 ( 1408750 36550 ) M1M2_PR ;
-    - la_data_out[80] ( PIN la_data_out[80] ) ( mprj la_data_out[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2054130 2380 0 ) ( * 24650 )
-      NEW met1 ( 1812630 1676030 ) ( 1814010 * )
-      NEW met1 ( 1814010 24650 ) ( 2054130 * )
-      NEW met1 ( 1810330 1676710 ) ( 1812630 * )
-      NEW met2 ( 1810330 1676710 ) ( * 1690140 )
-      NEW met2 ( 1809180 1690140 0 ) ( 1810330 * )
-      NEW met1 ( 1812630 1676030 ) ( * 1676710 )
-      NEW met2 ( 1814010 24650 ) ( * 1676030 )
-      NEW met1 ( 2054130 24650 ) M1M2_PR
-      NEW met1 ( 1814010 24650 ) M1M2_PR
-      NEW met1 ( 1814010 1676030 ) M1M2_PR
-      NEW met1 ( 1810330 1676710 ) M1M2_PR ;
-    - la_data_out[81] ( PIN la_data_out[81] ) ( mprj la_data_out[81] ) + USE SIGNAL
-      + ROUTED met1 ( 1813090 1683510 ) ( 1814010 * )
-      NEW met2 ( 1814010 1683510 ) ( * 1690140 )
-      NEW met2 ( 1814010 1690140 ) ( 1814700 * 0 )
-      NEW met1 ( 1813090 35190 ) ( 2071610 * )
-      NEW met2 ( 2071610 2380 0 ) ( * 35190 )
-      NEW met2 ( 1813090 35190 ) ( * 1683510 )
-      NEW met1 ( 1813090 35190 ) M1M2_PR
-      NEW met1 ( 1813090 1683510 ) M1M2_PR
-      NEW met1 ( 1814010 1683510 ) M1M2_PR
-      NEW met1 ( 2071610 35190 ) M1M2_PR ;
-    - la_data_out[82] ( PIN la_data_out[82] ) ( mprj la_data_out[82] ) + USE SIGNAL
-      + ROUTED met2 ( 1820220 1690140 0 ) ( 1820910 * )
-      NEW met1 ( 1820910 35530 ) ( 2089550 * )
-      NEW met2 ( 2089550 2380 0 ) ( * 35530 )
-      NEW met2 ( 1820910 35530 ) ( * 1690140 )
-      NEW met1 ( 1820910 35530 ) M1M2_PR
-      NEW met1 ( 2089550 35530 ) M1M2_PR ;
-    - la_data_out[83] ( PIN la_data_out[83] ) ( mprj la_data_out[83] ) + USE SIGNAL
-      + ROUTED met2 ( 1826890 1676700 ) ( 1827810 * )
-      NEW met2 ( 1826890 1676700 ) ( * 1690140 )
-      NEW met2 ( 1825740 1690140 0 ) ( 1826890 * )
-      NEW met1 ( 1827810 35870 ) ( 2107030 * )
-      NEW met2 ( 2107030 2380 0 ) ( * 35870 )
-      NEW met2 ( 1827810 35870 ) ( * 1676700 )
-      NEW met1 ( 1827810 35870 ) M1M2_PR
-      NEW met1 ( 2107030 35870 ) M1M2_PR ;
-    - la_data_out[84] ( PIN la_data_out[84] ) ( mprj la_data_out[84] ) + USE SIGNAL
-      + ROUTED met1 ( 1832410 1683510 ) ( 1835170 * )
-      NEW met2 ( 1832410 1683510 ) ( * 1690140 )
-      NEW met2 ( 1831260 1690140 0 ) ( 1832410 * )
-      NEW met2 ( 2124970 2380 0 ) ( * 36210 )
-      NEW met1 ( 1835170 36210 ) ( 2124970 * )
-      NEW met2 ( 1835170 36210 ) ( * 1683510 )
-      NEW met1 ( 1835170 36210 ) M1M2_PR
-      NEW met1 ( 1835170 1683510 ) M1M2_PR
-      NEW met1 ( 1832410 1683510 ) M1M2_PR
-      NEW met1 ( 2124970 36210 ) M1M2_PR ;
-    - la_data_out[85] ( PIN la_data_out[85] ) ( mprj la_data_out[85] ) + USE SIGNAL
-      + ROUTED met1 ( 1837470 1683510 ) ( 1841150 * )
-      NEW met2 ( 1837470 1683510 ) ( * 1690140 )
-      NEW met2 ( 1836320 1690140 0 ) ( 1837470 * )
-      NEW met2 ( 2142450 2380 0 ) ( * 36550 )
-      NEW met1 ( 1841150 36550 ) ( 2142450 * )
-      NEW met2 ( 1841150 36550 ) ( * 1683510 )
-      NEW met1 ( 1841150 36550 ) M1M2_PR
-      NEW met1 ( 1841150 1683510 ) M1M2_PR
-      NEW met1 ( 1837470 1683510 ) M1M2_PR
-      NEW met1 ( 2142450 36550 ) M1M2_PR ;
-    - la_data_out[86] ( PIN la_data_out[86] ) ( mprj la_data_out[86] ) + USE SIGNAL
-      + ROUTED met2 ( 1841610 1690140 ) ( 1841840 * 0 )
-      NEW met1 ( 1841610 36890 ) ( 2160390 * )
-      NEW met2 ( 2160390 2380 0 ) ( * 36890 )
-      NEW met2 ( 1841610 36890 ) ( * 1690140 )
-      NEW met1 ( 1841610 36890 ) M1M2_PR
-      NEW met1 ( 2160390 36890 ) M1M2_PR ;
-    - la_data_out[87] ( PIN la_data_out[87] ) ( mprj la_data_out[87] ) + USE SIGNAL
-      + ROUTED met2 ( 1847360 1690140 0 ) ( 1848510 * )
-      NEW met1 ( 2162230 36550 ) ( * 37230 )
-      NEW met1 ( 2162230 36550 ) ( 2177870 * )
-      NEW met1 ( 1848510 37230 ) ( 2162230 * )
-      NEW met2 ( 2177870 2380 0 ) ( * 36550 )
-      NEW met2 ( 1848510 37230 ) ( * 1690140 )
-      NEW met1 ( 1848510 37230 ) M1M2_PR
-      NEW met1 ( 2177870 36550 ) M1M2_PR ;
-    - la_data_out[88] ( PIN la_data_out[88] ) ( mprj la_data_out[88] ) + USE SIGNAL
-      + ROUTED met2 ( 1855410 37570 ) ( * 1676700 )
-      NEW met2 ( 1854030 1676700 ) ( 1855410 * )
-      NEW met2 ( 1854030 1676700 ) ( * 1690140 )
-      NEW met2 ( 1852880 1690140 0 ) ( 1854030 * )
-      NEW met1 ( 2162690 36890 ) ( * 37570 )
-      NEW met1 ( 2162690 36890 ) ( 2195810 * )
-      NEW met1 ( 1855410 37570 ) ( 2162690 * )
-      NEW met2 ( 2195810 2380 0 ) ( * 36890 )
-      NEW met1 ( 1855410 37570 ) M1M2_PR
-      NEW met1 ( 2195810 36890 ) M1M2_PR ;
-    - la_data_out[89] ( PIN la_data_out[89] ) ( mprj la_data_out[89] ) + USE SIGNAL
-      + ROUTED met1 ( 1859550 1677730 ) ( 1862310 * )
-      NEW met2 ( 1859550 1677730 ) ( * 1690140 )
-      NEW met2 ( 1858400 1690140 0 ) ( 1859550 * )
-      NEW met2 ( 1862310 41310 ) ( * 1677730 )
-      NEW met2 ( 2213290 2380 0 ) ( * 41310 )
-      NEW met1 ( 1862310 41310 ) ( 2213290 * )
-      NEW met1 ( 1862310 41310 ) M1M2_PR
-      NEW met1 ( 1862310 1677730 ) M1M2_PR
-      NEW met1 ( 1859550 1677730 ) M1M2_PR
-      NEW met1 ( 2213290 41310 ) M1M2_PR ;
-    - la_data_out[8] ( PIN la_data_out[8] ) ( mprj la_data_out[8] ) + USE SIGNAL
-      + ROUTED met2 ( 777170 2380 0 ) ( * 36210 )
-      NEW met1 ( 777170 36210 ) ( 1415650 * )
-      NEW met2 ( 1414960 1690140 0 ) ( 1415650 * )
-      NEW met2 ( 1415650 36210 ) ( * 1690140 )
-      NEW met1 ( 777170 36210 ) M1M2_PR
-      NEW met1 ( 1415650 36210 ) M1M2_PR ;
-    - la_data_out[90] ( PIN la_data_out[90] ) ( mprj la_data_out[90] ) + USE SIGNAL
-      + ROUTED met2 ( 2231230 2380 0 ) ( * 3060 )
-      NEW met2 ( 2230310 3060 ) ( 2231230 * )
-      NEW met2 ( 2230310 2380 ) ( * 3060 )
-      NEW met2 ( 2228930 2380 ) ( 2230310 * )
-      NEW met2 ( 1865070 1680790 ) ( * 1690140 )
-      NEW met2 ( 1863920 1690140 0 ) ( 1865070 * )
-      NEW met2 ( 2228930 2380 ) ( * 1669230 )
-      NEW met1 ( 1873350 1669230 ) ( 2228930 * )
-      NEW met1 ( 1865070 1680790 ) ( 1873350 * )
-      NEW met2 ( 1873350 1669230 ) ( * 1680790 )
-      NEW met1 ( 2228930 1669230 ) M1M2_PR
-      NEW met1 ( 1865070 1680790 ) M1M2_PR
-      NEW met1 ( 1873350 1669230 ) M1M2_PR
-      NEW met1 ( 1873350 1680790 ) M1M2_PR ;
-    - la_data_out[91] ( PIN la_data_out[91] ) ( mprj la_data_out[91] ) + USE SIGNAL
-      + ROUTED met2 ( 2249170 2380 0 ) ( * 15470 )
-      NEW met1 ( 2242730 15470 ) ( 2249170 * )
-      NEW met2 ( 1869210 1679090 ) ( * 1690140 )
-      NEW met2 ( 1869210 1690140 ) ( 1869440 * 0 )
-      NEW met2 ( 2242730 15470 ) ( * 1668890 )
-      NEW met1 ( 1877030 1668890 ) ( 2242730 * )
-      NEW met1 ( 1869210 1679090 ) ( 1877030 * )
-      NEW met2 ( 1877030 1668890 ) ( * 1679090 )
-      NEW met1 ( 2249170 15470 ) M1M2_PR
-      NEW met1 ( 2242730 15470 ) M1M2_PR
-      NEW met1 ( 2242730 1668890 ) M1M2_PR
-      NEW met1 ( 1869210 1679090 ) M1M2_PR
-      NEW met1 ( 1877030 1668890 ) M1M2_PR
-      NEW met1 ( 1877030 1679090 ) M1M2_PR ;
-    - la_data_out[92] ( PIN la_data_out[92] ) ( mprj la_data_out[92] ) + USE SIGNAL
-      + ROUTED met1 ( 1876110 1661410 ) ( 2263430 * )
-      NEW met2 ( 1874960 1690140 0 ) ( 1876110 * )
-      NEW met2 ( 1876110 1661410 ) ( * 1690140 )
-      NEW met2 ( 2263430 82800 ) ( 2266650 * )
-      NEW met2 ( 2266650 2380 0 ) ( * 82800 )
-      NEW met2 ( 2263430 82800 ) ( * 1661410 )
-      NEW met1 ( 1876110 1661410 ) M1M2_PR
-      NEW met1 ( 2263430 1661410 ) M1M2_PR ;
-    - la_data_out[93] ( PIN la_data_out[93] ) ( mprj la_data_out[93] ) + USE SIGNAL
-      + ROUTED met1 ( 1881170 1661070 ) ( 2284590 * )
-      NEW met2 ( 1880480 1690140 0 ) ( 1881170 * )
-      NEW met2 ( 1881170 1661070 ) ( * 1690140 )
-      NEW met2 ( 2284590 2380 0 ) ( * 1661070 )
-      NEW met1 ( 1881170 1661070 ) M1M2_PR
-      NEW met1 ( 2284590 1661070 ) M1M2_PR ;
-    - la_data_out[94] ( PIN la_data_out[94] ) ( mprj la_data_out[94] ) + USE SIGNAL
-      + ROUTED met2 ( 2302070 2380 0 ) ( * 3060 )
-      NEW met2 ( 2301150 3060 ) ( 2302070 * )
-      NEW met2 ( 2301150 2380 ) ( * 3060 )
-      NEW met2 ( 2299770 2380 ) ( 2301150 * )
-      NEW met1 ( 1887150 1668550 ) ( 2297930 * )
-      NEW met2 ( 1886000 1690140 0 ) ( 1887150 * )
-      NEW met2 ( 1887150 1668550 ) ( * 1690140 )
-      NEW met2 ( 2297930 82800 ) ( 2299770 * )
-      NEW met2 ( 2299770 2380 ) ( * 82800 )
-      NEW met2 ( 2297930 82800 ) ( * 1668550 )
-      NEW met1 ( 1887150 1668550 ) M1M2_PR
-      NEW met1 ( 2297930 1668550 ) M1M2_PR ;
-    - la_data_out[95] ( PIN la_data_out[95] ) ( mprj la_data_out[95] ) + USE SIGNAL
-      + ROUTED met2 ( 2318630 82800 ) ( 2320010 * )
-      NEW met2 ( 2320010 2380 0 ) ( * 82800 )
-      NEW met2 ( 2318630 82800 ) ( * 1660730 )
-      NEW met1 ( 1892670 1660730 ) ( 2318630 * )
-      NEW met2 ( 1891520 1690140 0 ) ( 1892670 * )
-      NEW met2 ( 1892670 1660730 ) ( * 1690140 )
-      NEW met1 ( 2318630 1660730 ) M1M2_PR
-      NEW met1 ( 1892670 1660730 ) M1M2_PR ;
-    - la_data_out[96] ( PIN la_data_out[96] ) ( mprj la_data_out[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2332430 82800 ) ( 2337490 * )
-      NEW met2 ( 2337490 2380 0 ) ( * 82800 )
-      NEW met2 ( 2332430 82800 ) ( * 1660390 )
-      NEW met1 ( 1897270 1660390 ) ( 2332430 * )
-      NEW met2 ( 1896580 1690140 0 ) ( 1897270 * )
-      NEW met2 ( 1897270 1660390 ) ( * 1690140 )
-      NEW met1 ( 2332430 1660390 ) M1M2_PR
-      NEW met1 ( 1897270 1660390 ) M1M2_PR ;
-    - la_data_out[97] ( PIN la_data_out[97] ) ( mprj la_data_out[97] ) + USE SIGNAL
-      + ROUTED met2 ( 2355430 2380 0 ) ( * 3060 )
-      NEW met2 ( 2354510 3060 ) ( 2355430 * )
-      NEW met2 ( 2354510 2380 ) ( * 3060 )
-      NEW met2 ( 2353130 2380 ) ( 2354510 * )
-      NEW met1 ( 1902790 1676030 ) ( 2353130 * )
-      NEW met2 ( 1902100 1690140 0 ) ( 1902790 * )
-      NEW met2 ( 1902790 1676030 ) ( * 1690140 )
-      NEW met2 ( 2353130 2380 ) ( * 1676030 )
-      NEW met1 ( 1902790 1676030 ) M1M2_PR
-      NEW met1 ( 2353130 1676030 ) M1M2_PR ;
-    - la_data_out[98] ( PIN la_data_out[98] ) ( mprj la_data_out[98] ) + USE SIGNAL
-      + ROUTED met1 ( 1935910 1675690 ) ( 1942350 * )
-      NEW met2 ( 1942350 44710 ) ( * 1675690 )
-      NEW li1 ( 1919350 1676710 ) ( * 1682150 )
-      NEW met1 ( 1919350 1676710 ) ( 1935910 * )
-      NEW li1 ( 1935910 1675690 ) ( * 1676710 )
-      NEW met2 ( 1908770 1682150 ) ( * 1690140 )
-      NEW met2 ( 1907620 1690140 0 ) ( 1908770 * )
-      NEW met1 ( 1908770 1682150 ) ( 1919350 * )
-      NEW met1 ( 1942350 44710 ) ( 2372910 * )
-      NEW met2 ( 2372910 2380 0 ) ( * 44710 )
-      NEW li1 ( 1935910 1675690 ) L1M1_PR_MR
-      NEW met1 ( 1942350 1675690 ) M1M2_PR
-      NEW met1 ( 1942350 44710 ) M1M2_PR
-      NEW li1 ( 1919350 1682150 ) L1M1_PR_MR
-      NEW li1 ( 1919350 1676710 ) L1M1_PR_MR
-      NEW li1 ( 1935910 1676710 ) L1M1_PR_MR
-      NEW met1 ( 1908770 1682150 ) M1M2_PR
-      NEW met1 ( 2372910 44710 ) M1M2_PR ;
-    - la_data_out[99] ( PIN la_data_out[99] ) ( mprj la_data_out[99] ) + USE SIGNAL
-      + ROUTED met1 ( 1914290 1680790 ) ( 1917970 * )
-      NEW met2 ( 1914290 1680790 ) ( * 1690140 )
-      NEW met2 ( 1913140 1690140 0 ) ( 1914290 * )
-      NEW met2 ( 1917970 72250 ) ( * 1680790 )
-      NEW met1 ( 1917970 72250 ) ( 2390850 * )
-      NEW met2 ( 2390850 2380 0 ) ( * 72250 )
-      NEW met1 ( 1917970 72250 ) M1M2_PR
-      NEW met1 ( 1917970 1680790 ) M1M2_PR
-      NEW met1 ( 1914290 1680790 ) M1M2_PR
-      NEW met1 ( 2390850 72250 ) M1M2_PR ;
-    - la_data_out[9] ( PIN la_data_out[9] ) ( mprj la_data_out[9] ) + USE SIGNAL
-      + ROUTED met2 ( 794650 2380 0 ) ( * 35870 )
-      NEW met1 ( 1415190 1630130 ) ( 1418870 * )
-      NEW met1 ( 794650 35870 ) ( 1415190 * )
-      NEW met2 ( 1415190 35870 ) ( * 1630130 )
-      NEW met2 ( 1418870 1690140 ) ( 1420020 * 0 )
-      NEW met2 ( 1418870 1630130 ) ( * 1690140 )
-      NEW met1 ( 794650 35870 ) M1M2_PR
-      NEW met1 ( 1415190 1630130 ) M1M2_PR
-      NEW met1 ( 1418870 1630130 ) M1M2_PR
-      NEW met1 ( 1415190 35870 ) M1M2_PR ;
-    - la_oenb[0] ( PIN la_oenb[0] ) ( mprj la_oenb[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1367350 65450 ) ( * 1580100 )
-      NEW met2 ( 1367350 1580100 ) ( 1371490 * )
-      NEW met2 ( 1371490 1690140 ) ( 1372640 * 0 )
-      NEW met2 ( 641010 2380 0 ) ( * 65450 )
-      NEW met1 ( 641010 65450 ) ( 1367350 * )
-      NEW met2 ( 1371490 1580100 ) ( * 1690140 )
-      NEW met1 ( 1367350 65450 ) M1M2_PR
-      NEW met1 ( 641010 65450 ) M1M2_PR ;
-    - la_oenb[100] ( PIN la_oenb[100] ) ( mprj la_oenb[100] ) + USE SIGNAL
-      + ROUTED met2 ( 2414310 2380 0 ) ( * 3060 )
-      NEW met2 ( 2413390 3060 ) ( 2414310 * )
-      NEW met2 ( 2413390 2380 ) ( * 3060 )
-      NEW met2 ( 2412010 2380 ) ( 2413390 * )
-      NEW met2 ( 1920500 1690140 0 ) ( 1921650 * )
-      NEW met2 ( 1921650 1675350 ) ( * 1690140 )
-      NEW met2 ( 2408330 82800 ) ( 2412010 * )
-      NEW met2 ( 2412010 2380 ) ( * 82800 )
-      NEW met2 ( 2408330 82800 ) ( * 1675350 )
-      NEW met1 ( 1921650 1675350 ) ( 2408330 * )
-      NEW met1 ( 1921650 1675350 ) M1M2_PR
-      NEW met1 ( 2408330 1675350 ) M1M2_PR ;
-    - la_oenb[101] ( PIN la_oenb[101] ) ( mprj la_oenb[101] ) + USE SIGNAL
-      + ROUTED met2 ( 2432250 2380 0 ) ( * 17340 )
-      NEW met2 ( 2431790 17340 ) ( 2432250 * )
-      NEW met2 ( 1926020 1690140 0 ) ( 1926710 * )
-      NEW met2 ( 1926710 1660050 ) ( * 1690140 )
-      NEW met2 ( 2429030 82800 ) ( 2431790 * )
-      NEW met2 ( 2431790 17340 ) ( * 82800 )
-      NEW met2 ( 2429030 82800 ) ( * 1660050 )
-      NEW met1 ( 1926710 1660050 ) ( 2429030 * )
-      NEW met1 ( 1926710 1660050 ) M1M2_PR
-      NEW met1 ( 2429030 1660050 ) M1M2_PR ;
-    - la_oenb[102] ( PIN la_oenb[102] ) ( mprj la_oenb[102] ) + USE SIGNAL
-      + ROUTED met2 ( 1931540 1688780 ) ( 1931770 * )
-      NEW met2 ( 1931540 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1931770 1653930 ) ( * 1688780 )
-      NEW met2 ( 2446050 16830 ) ( * 1653930 )
-      NEW met1 ( 1931770 1653930 ) ( 2446050 * )
-      NEW met2 ( 2449730 2380 0 ) ( * 16830 )
-      NEW met1 ( 2446050 16830 ) ( 2449730 * )
-      NEW met1 ( 1931770 1653930 ) M1M2_PR
-      NEW met1 ( 2446050 16830 ) M1M2_PR
-      NEW met1 ( 2446050 1653930 ) M1M2_PR
-      NEW met1 ( 2449730 16830 ) M1M2_PR ;
-    - la_oenb[103] ( PIN la_oenb[103] ) ( mprj la_oenb[103] ) + USE SIGNAL
-      + ROUTED met2 ( 1937060 1690140 0 ) ( 1938210 * )
-      NEW met2 ( 1938210 1668210 ) ( * 1690140 )
-      NEW met2 ( 2467670 2380 0 ) ( * 3060 )
-      NEW met2 ( 2466750 3060 ) ( 2467670 * )
-      NEW met2 ( 2466750 2380 ) ( * 3060 )
-      NEW met2 ( 2465370 2380 ) ( 2466750 * )
-      NEW met1 ( 1938210 1668210 ) ( 2463530 * )
-      NEW met2 ( 2463530 82800 ) ( 2465370 * )
-      NEW met2 ( 2465370 2380 ) ( * 82800 )
-      NEW met2 ( 2463530 82800 ) ( * 1668210 )
-      NEW met1 ( 1938210 1668210 ) M1M2_PR
-      NEW met1 ( 2463530 1668210 ) M1M2_PR ;
-    - la_oenb[104] ( PIN la_oenb[104] ) ( mprj la_oenb[104] ) + USE SIGNAL
-      + ROUTED met2 ( 1942580 1690140 0 ) ( 1943730 * )
-      NEW met2 ( 1943730 1653590 ) ( * 1690140 )
-      NEW met1 ( 1943730 1653590 ) ( 2484230 * )
-      NEW met2 ( 2484230 82800 ) ( 2485610 * )
-      NEW met2 ( 2485610 2380 0 ) ( * 82800 )
-      NEW met2 ( 2484230 82800 ) ( * 1653590 )
-      NEW met1 ( 1943730 1653590 ) M1M2_PR
-      NEW met1 ( 2484230 1653590 ) M1M2_PR ;
-    - la_oenb[105] ( PIN la_oenb[105] ) ( mprj la_oenb[105] ) + USE SIGNAL
-      + ROUTED met2 ( 1948100 1690140 0 ) ( 1949250 * )
-      NEW met2 ( 1949250 1659710 ) ( * 1690140 )
-      NEW met2 ( 2498030 82800 ) ( 2503090 * )
-      NEW met2 ( 2503090 2380 0 ) ( * 82800 )
-      NEW met2 ( 2498030 82800 ) ( * 1659710 )
-      NEW met1 ( 1949250 1659710 ) ( 2498030 * )
-      NEW met1 ( 1949250 1659710 ) M1M2_PR
-      NEW met1 ( 2498030 1659710 ) M1M2_PR ;
-    - la_oenb[106] ( PIN la_oenb[106] ) ( mprj la_oenb[106] ) + USE SIGNAL
-      + ROUTED met2 ( 2521030 2380 0 ) ( * 16490 )
-      NEW met1 ( 2515050 16490 ) ( 2521030 * )
-      NEW met2 ( 1953620 1690140 0 ) ( 1954770 * )
-      NEW met2 ( 1954770 1674330 ) ( * 1690140 )
-      NEW met2 ( 2515050 16490 ) ( * 1674330 )
-      NEW met1 ( 1954770 1674330 ) ( 2515050 * )
-      NEW met1 ( 1954770 1674330 ) M1M2_PR
-      NEW met1 ( 2521030 16490 ) M1M2_PR
-      NEW met1 ( 2515050 16490 ) M1M2_PR
-      NEW met1 ( 2515050 1674330 ) M1M2_PR ;
-    - la_oenb[107] ( PIN la_oenb[107] ) ( mprj la_oenb[107] ) + USE SIGNAL
-      + ROUTED met2 ( 2538510 2380 0 ) ( * 3060 )
-      NEW met2 ( 2537590 3060 ) ( 2538510 * )
-      NEW met2 ( 2537590 2380 ) ( * 3060 )
-      NEW met2 ( 2536210 2380 ) ( 2537590 * )
-      NEW met2 ( 2536210 2380 ) ( * 3060 )
-      NEW met2 ( 2535290 3060 ) ( 2536210 * )
-      NEW met2 ( 1958680 1690140 0 ) ( 1959370 * )
-      NEW met2 ( 1959370 1659370 ) ( * 1690140 )
-      NEW met2 ( 2532530 82800 ) ( 2535290 * )
-      NEW met2 ( 2535290 3060 ) ( * 82800 )
-      NEW met2 ( 2532530 82800 ) ( * 1659370 )
-      NEW met1 ( 1959370 1659370 ) ( 2532530 * )
-      NEW met1 ( 1959370 1659370 ) M1M2_PR
-      NEW met1 ( 2532530 1659370 ) M1M2_PR ;
-    - la_oenb[108] ( PIN la_oenb[108] ) ( mprj la_oenb[108] ) + USE SIGNAL
-      + ROUTED met2 ( 1964200 1690140 0 ) ( 1964890 * )
-      NEW met2 ( 1964890 1653250 ) ( * 1690140 )
-      NEW met1 ( 1964890 1653250 ) ( 2553230 * )
-      NEW met2 ( 2553230 82800 ) ( 2556450 * )
-      NEW met2 ( 2556450 2380 0 ) ( * 82800 )
-      NEW met2 ( 2553230 82800 ) ( * 1653250 )
-      NEW met1 ( 1964890 1653250 ) M1M2_PR
-      NEW met1 ( 2553230 1653250 ) M1M2_PR ;
-    - la_oenb[109] ( PIN la_oenb[109] ) ( mprj la_oenb[109] ) + USE SIGNAL
-      + ROUTED met1 ( 1970870 1676710 ) ( 1972710 * )
-      NEW met2 ( 1970870 1676710 ) ( * 1690140 )
-      NEW met2 ( 1969720 1690140 0 ) ( 1970870 * )
-      NEW met2 ( 1972710 51510 ) ( * 1676710 )
-      NEW met1 ( 1972710 51510 ) ( 2573930 * )
-      NEW met2 ( 2573930 2380 0 ) ( * 51510 )
-      NEW met1 ( 1972710 51510 ) M1M2_PR
-      NEW met1 ( 1972710 1676710 ) M1M2_PR
-      NEW met1 ( 1970870 1676710 ) M1M2_PR
-      NEW met1 ( 2573930 51510 ) M1M2_PR ;
-    - la_oenb[10] ( PIN la_oenb[10] ) ( mprj la_oenb[10] ) + USE SIGNAL
-      + ROUTED met2 ( 818570 2380 0 ) ( * 3060 )
-      NEW met2 ( 818570 3060 ) ( 819490 * )
-      NEW met2 ( 819490 2380 ) ( * 3060 )
-      NEW met2 ( 819490 2380 ) ( 820870 * )
-      NEW met2 ( 820870 2380 ) ( * 66130 )
-      NEW met1 ( 820870 66130 ) ( 1422550 * )
-      NEW met2 ( 1422550 66130 ) ( * 1580100 )
-      NEW met2 ( 1422550 1580100 ) ( 1426230 * )
-      NEW met2 ( 1426230 1690140 ) ( 1427380 * 0 )
-      NEW met2 ( 1426230 1580100 ) ( * 1690140 )
-      NEW met1 ( 820870 66130 ) M1M2_PR
-      NEW met1 ( 1422550 66130 ) M1M2_PR ;
-    - la_oenb[110] ( PIN la_oenb[110] ) ( mprj la_oenb[110] ) + USE SIGNAL
-      + ROUTED met2 ( 2591870 2380 0 ) ( * 3060 )
-      NEW met2 ( 2590950 3060 ) ( 2591870 * )
-      NEW met2 ( 2590950 2380 ) ( * 3060 )
-      NEW met2 ( 2589570 2380 ) ( 2590950 * )
-      NEW met1 ( 1976390 1645770 ) ( 2587730 * )
-      NEW met2 ( 1975240 1690140 0 ) ( 1976390 * )
-      NEW met2 ( 1976390 1645770 ) ( * 1690140 )
-      NEW met2 ( 2587730 82800 ) ( 2589570 * )
-      NEW met2 ( 2589570 2380 ) ( * 82800 )
-      NEW met2 ( 2587730 82800 ) ( * 1645770 )
-      NEW met1 ( 1976390 1645770 ) M1M2_PR
-      NEW met1 ( 2587730 1645770 ) M1M2_PR ;
-    - la_oenb[111] ( PIN la_oenb[111] ) ( mprj la_oenb[111] ) + USE SIGNAL
-      + ROUTED met2 ( 2609350 2380 0 ) ( * 16490 )
-      NEW met1 ( 2598310 16490 ) ( 2609350 * )
-      NEW met2 ( 2597850 82800 ) ( 2598310 * )
-      NEW met2 ( 2598310 16490 ) ( * 82800 )
-      NEW met2 ( 2597850 82800 ) ( * 1652910 )
-      NEW met1 ( 1981910 1652910 ) ( 2597850 * )
-      NEW met2 ( 1980760 1690140 0 ) ( 1981910 * )
-      NEW met2 ( 1981910 1652910 ) ( * 1690140 )
-      NEW met1 ( 2609350 16490 ) M1M2_PR
-      NEW met1 ( 2598310 16490 ) M1M2_PR
-      NEW met1 ( 2597850 1652910 ) M1M2_PR
-      NEW met1 ( 1981910 1652910 ) M1M2_PR ;
-    - la_oenb[112] ( PIN la_oenb[112] ) ( mprj la_oenb[112] ) + USE SIGNAL
-      + ROUTED met2 ( 2622230 82800 ) ( 2627290 * )
-      NEW met2 ( 2627290 2380 0 ) ( * 82800 )
-      NEW met2 ( 2622230 82800 ) ( * 1645430 )
-      NEW met1 ( 1986970 1645430 ) ( 2622230 * )
-      NEW met2 ( 1986280 1690140 0 ) ( 1986970 * )
-      NEW met2 ( 1986970 1645430 ) ( * 1690140 )
-      NEW met1 ( 2622230 1645430 ) M1M2_PR
-      NEW met1 ( 1986970 1645430 ) M1M2_PR ;
-    - la_oenb[113] ( PIN la_oenb[113] ) ( mprj la_oenb[113] ) + USE SIGNAL
-      + ROUTED li1 ( 2039410 1667190 ) ( * 1669570 )
-      NEW met1 ( 1992490 1669570 ) ( 2039410 * )
-      NEW met2 ( 2645230 2380 0 ) ( * 3060 )
-      NEW met2 ( 2644310 3060 ) ( 2645230 * )
-      NEW met2 ( 2644310 2380 ) ( * 3060 )
-      NEW met2 ( 2642930 2380 ) ( 2644310 * )
-      NEW met1 ( 2039410 1667190 ) ( 2642930 * )
-      NEW met2 ( 1991800 1690140 0 ) ( 1992490 * )
-      NEW met2 ( 1992490 1669570 ) ( * 1690140 )
-      NEW met2 ( 2642930 2380 ) ( * 1667190 )
-      NEW li1 ( 2039410 1669570 ) L1M1_PR_MR
-      NEW li1 ( 2039410 1667190 ) L1M1_PR_MR
-      NEW met1 ( 1992490 1669570 ) M1M2_PR
-      NEW met1 ( 2642930 1667190 ) M1M2_PR ;
-    - la_oenb[114] ( PIN la_oenb[114] ) ( mprj la_oenb[114] ) + USE SIGNAL
-      + ROUTED met2 ( 2425350 16490 ) ( * 1646110 )
-      NEW met1 ( 1998470 1646110 ) ( 2425350 * )
-      NEW met1 ( 2497800 16490 ) ( * 16830 )
-      NEW met1 ( 2425350 16490 ) ( 2497800 * )
-      NEW met1 ( 2497800 16830 ) ( 2642700 * )
-      NEW met2 ( 2662710 2380 0 ) ( * 16490 )
-      NEW met1 ( 2642700 16490 ) ( 2662710 * )
-      NEW met1 ( 2642700 16490 ) ( * 16830 )
-      NEW met2 ( 1997320 1690140 0 ) ( 1998470 * )
-      NEW met2 ( 1998470 1646110 ) ( * 1690140 )
-      NEW met1 ( 2425350 16490 ) M1M2_PR
-      NEW met1 ( 2425350 1646110 ) M1M2_PR
-      NEW met1 ( 1998470 1646110 ) M1M2_PR
-      NEW met1 ( 2662710 16490 ) M1M2_PR ;
-    - la_oenb[115] ( PIN la_oenb[115] ) ( mprj la_oenb[115] ) + USE SIGNAL
-      + ROUTED met1 ( 2003990 1652230 ) ( 2014800 * )
-      NEW met1 ( 2014800 1652230 ) ( * 1652570 )
-      NEW met1 ( 2014800 1652570 ) ( 2677430 * )
-      NEW met2 ( 2002840 1690140 0 ) ( 2003990 * )
-      NEW met2 ( 2003990 1652230 ) ( * 1690140 )
-      NEW met2 ( 2677430 82800 ) ( 2680650 * )
-      NEW met2 ( 2680650 2380 0 ) ( * 82800 )
-      NEW met2 ( 2677430 82800 ) ( * 1652570 )
-      NEW met1 ( 2003990 1652230 ) M1M2_PR
-      NEW met1 ( 2677430 1652570 ) M1M2_PR ;
-    - la_oenb[116] ( PIN la_oenb[116] ) ( mprj la_oenb[116] ) + USE SIGNAL
-      + ROUTED met2 ( 2698130 2380 0 ) ( * 16830 )
-      NEW met1 ( 2009510 1652570 ) ( 2014110 * )
-      NEW li1 ( 2675130 16830 ) ( * 20570 )
-      NEW met1 ( 2014110 20570 ) ( 2675130 * )
-      NEW met1 ( 2675130 16830 ) ( 2698130 * )
-      NEW met2 ( 2014110 20570 ) ( * 1652570 )
-      NEW met2 ( 2008360 1690140 0 ) ( 2009510 * )
-      NEW met2 ( 2009510 1652570 ) ( * 1690140 )
-      NEW met1 ( 2698130 16830 ) M1M2_PR
-      NEW met1 ( 2014110 20570 ) M1M2_PR
-      NEW met1 ( 2009510 1652570 ) M1M2_PR
-      NEW met1 ( 2014110 1652570 ) M1M2_PR
-      NEW li1 ( 2675130 20570 ) L1M1_PR_MR
-      NEW li1 ( 2675130 16830 ) L1M1_PR_MR ;
-    - la_oenb[117] ( PIN la_oenb[117] ) ( mprj la_oenb[117] ) + USE SIGNAL
-      + ROUTED met2 ( 2716070 2380 0 ) ( * 20230 )
-      NEW met1 ( 2014570 20230 ) ( 2716070 * )
-      NEW met2 ( 2013880 1690140 0 ) ( 2014570 * )
-      NEW met2 ( 2014570 20230 ) ( * 1690140 )
-      NEW met1 ( 2716070 20230 ) M1M2_PR
-      NEW met1 ( 2014570 20230 ) M1M2_PR ;
-    - la_oenb[118] ( PIN la_oenb[118] ) ( mprj la_oenb[118] ) + USE SIGNAL
-      + ROUTED met1 ( 2020090 1652230 ) ( 2021470 * )
-      NEW met2 ( 2733550 2380 0 ) ( * 19890 )
-      NEW met2 ( 2021470 19890 ) ( * 1652230 )
-      NEW met2 ( 2018940 1690140 0 ) ( 2020090 * )
-      NEW met2 ( 2020090 1652230 ) ( * 1690140 )
-      NEW met1 ( 2021470 19890 ) ( 2733550 * )
-      NEW met1 ( 2021470 19890 ) M1M2_PR
-      NEW met1 ( 2020090 1652230 ) M1M2_PR
-      NEW met1 ( 2021470 1652230 ) M1M2_PR
-      NEW met1 ( 2733550 19890 ) M1M2_PR ;
-    - la_oenb[119] ( PIN la_oenb[119] ) ( mprj la_oenb[119] ) + USE SIGNAL
-      + ROUTED met1 ( 2025610 1652230 ) ( 2028370 * )
-      NEW met2 ( 2028370 19550 ) ( * 1652230 )
-      NEW met2 ( 2024460 1690140 0 ) ( 2025610 * )
-      NEW met2 ( 2025610 1652230 ) ( * 1690140 )
-      NEW met2 ( 2751490 2380 0 ) ( * 19550 )
-      NEW met1 ( 2028370 19550 ) ( 2751490 * )
-      NEW met1 ( 2028370 19550 ) M1M2_PR
-      NEW met1 ( 2025610 1652230 ) M1M2_PR
-      NEW met1 ( 2028370 1652230 ) M1M2_PR
-      NEW met1 ( 2751490 19550 ) M1M2_PR ;
-    - la_oenb[11] ( PIN la_oenb[11] ) ( mprj la_oenb[11] ) + USE SIGNAL
-      + ROUTED met2 ( 836050 2380 0 ) ( * 3060 )
-      NEW met2 ( 836050 3060 ) ( 836970 * )
-      NEW met2 ( 836970 2380 ) ( * 3060 )
-      NEW met2 ( 836970 2380 ) ( 838350 * )
-      NEW met1 ( 1428990 1652570 ) ( 1431750 * )
-      NEW met2 ( 838350 2380 ) ( * 59330 )
-      NEW met1 ( 838350 59330 ) ( 1428990 * )
-      NEW met2 ( 1428990 59330 ) ( * 1652570 )
-      NEW met2 ( 1431750 1690140 ) ( 1432900 * 0 )
-      NEW met2 ( 1431750 1652570 ) ( * 1690140 )
-      NEW met1 ( 1428990 1652570 ) M1M2_PR
-      NEW met1 ( 1431750 1652570 ) M1M2_PR
-      NEW met1 ( 838350 59330 ) M1M2_PR
-      NEW met1 ( 1428990 59330 ) M1M2_PR ;
-    - la_oenb[120] ( PIN la_oenb[120] ) ( mprj la_oenb[120] ) + USE SIGNAL
-      + ROUTED met1 ( 2031130 1652230 ) ( 2035270 * )
-      NEW met2 ( 2035270 19210 ) ( * 1652230 )
-      NEW met2 ( 2029980 1690140 0 ) ( 2031130 * )
-      NEW met2 ( 2031130 1652230 ) ( * 1690140 )
-      NEW met2 ( 2768970 2380 0 ) ( * 19210 )
-      NEW met1 ( 2035270 19210 ) ( 2768970 * )
-      NEW met1 ( 2035270 19210 ) M1M2_PR
-      NEW met1 ( 2031130 1652230 ) M1M2_PR
-      NEW met1 ( 2035270 1652230 ) M1M2_PR
-      NEW met1 ( 2768970 19210 ) M1M2_PR ;
-    - la_oenb[121] ( PIN la_oenb[121] ) ( mprj la_oenb[121] ) + USE SIGNAL
-      + ROUTED met2 ( 2034810 1690140 ) ( 2035500 * 0 )
-      NEW met2 ( 2034810 18870 ) ( * 1690140 )
-      NEW met2 ( 2786910 2380 0 ) ( * 18870 )
-      NEW met1 ( 2034810 18870 ) ( 2786910 * )
-      NEW met1 ( 2034810 18870 ) M1M2_PR
-      NEW met1 ( 2786910 18870 ) M1M2_PR ;
-    - la_oenb[122] ( PIN la_oenb[122] ) ( mprj la_oenb[122] ) + USE SIGNAL
-      + ROUTED met2 ( 2804390 2380 0 ) ( * 18530 )
-      NEW met2 ( 2041020 1690140 0 ) ( 2042170 * )
-      NEW met2 ( 2042170 18530 ) ( * 1690140 )
-      NEW met1 ( 2042170 18530 ) ( 2804390 * )
-      NEW met1 ( 2042170 18530 ) M1M2_PR
-      NEW met1 ( 2804390 18530 ) M1M2_PR ;
-    - la_oenb[123] ( PIN la_oenb[123] ) ( mprj la_oenb[123] ) + USE SIGNAL
-      + ROUTED met2 ( 2822330 2380 0 ) ( * 18190 )
-      NEW met1 ( 2047690 1676710 ) ( 2049070 * )
-      NEW met2 ( 2047690 1676710 ) ( * 1690140 )
-      NEW met2 ( 2046540 1690140 0 ) ( 2047690 * )
-      NEW met2 ( 2049070 18190 ) ( * 1676710 )
-      NEW met1 ( 2049070 18190 ) ( 2822330 * )
-      NEW met1 ( 2049070 18190 ) M1M2_PR
-      NEW met1 ( 2822330 18190 ) M1M2_PR
-      NEW met1 ( 2049070 1676710 ) M1M2_PR
-      NEW met1 ( 2047690 1676710 ) M1M2_PR ;
-    - la_oenb[124] ( PIN la_oenb[124] ) ( mprj la_oenb[124] ) + USE SIGNAL
-      + ROUTED met1 ( 2053210 1651890 ) ( 2055970 * )
-      NEW met2 ( 2055970 17850 ) ( * 1651890 )
-      NEW met2 ( 2052060 1690140 0 ) ( 2053210 * )
-      NEW met2 ( 2053210 1651890 ) ( * 1690140 )
-      NEW met2 ( 2840270 2380 0 ) ( * 17850 )
-      NEW met1 ( 2055970 17850 ) ( 2840270 * )
-      NEW met1 ( 2055970 17850 ) M1M2_PR
-      NEW met1 ( 2053210 1651890 ) M1M2_PR
-      NEW met1 ( 2055970 1651890 ) M1M2_PR
-      NEW met1 ( 2840270 17850 ) M1M2_PR ;
-    - la_oenb[125] ( PIN la_oenb[125] ) ( mprj la_oenb[125] ) + USE SIGNAL
-      + ROUTED met1 ( 2058730 1652230 ) ( 2062410 * )
-      NEW met2 ( 2062410 17510 ) ( * 1652230 )
-      NEW met2 ( 2057580 1690140 0 ) ( 2058730 * )
-      NEW met2 ( 2058730 1652230 ) ( * 1690140 )
-      NEW met2 ( 2857750 2380 0 ) ( * 17510 )
-      NEW met1 ( 2062410 17510 ) ( 2857750 * )
-      NEW met1 ( 2062410 17510 ) M1M2_PR
-      NEW met1 ( 2058730 1652230 ) M1M2_PR
-      NEW met1 ( 2062410 1652230 ) M1M2_PR
-      NEW met1 ( 2857750 17510 ) M1M2_PR ;
-    - la_oenb[126] ( PIN la_oenb[126] ) ( mprj la_oenb[126] ) + USE SIGNAL
-      + ROUTED met2 ( 2062870 17170 ) ( * 1690140 )
-      NEW met2 ( 2875690 2380 0 ) ( * 17170 )
-      NEW met1 ( 2062870 17170 ) ( 2875690 * )
-      NEW met2 ( 2062870 1690140 ) ( 2063100 * 0 )
-      NEW met1 ( 2062870 17170 ) M1M2_PR
-      NEW met1 ( 2875690 17170 ) M1M2_PR ;
-    - la_oenb[127] ( PIN la_oenb[127] ) ( mprj la_oenb[127] ) + USE SIGNAL
-      + ROUTED met2 ( 2893170 2380 0 ) ( * 18700 )
-      NEW met3 ( 2069770 18700 ) ( 2893170 * )
-      NEW met2 ( 2068620 1690140 0 ) ( 2069770 * )
-      NEW met2 ( 2069770 18700 ) ( * 1690140 )
-      NEW met2 ( 2893170 18700 ) M2M3_PR_M
-      NEW met2 ( 2069770 18700 ) M2M3_PR_M ;
-    - la_oenb[12] ( PIN la_oenb[12] ) ( mprj la_oenb[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1437270 1690140 ) ( 1438420 * 0 )
-      NEW met2 ( 1437270 1661750 ) ( * 1690140 )
-      NEW met1 ( 855370 1661750 ) ( 1437270 * )
-      NEW met2 ( 853990 2380 0 ) ( * 34500 )
-      NEW met2 ( 853990 34500 ) ( 855370 * )
-      NEW met2 ( 855370 34500 ) ( * 1661750 )
-      NEW met1 ( 1437270 1661750 ) M1M2_PR
-      NEW met1 ( 855370 1661750 ) M1M2_PR ;
-    - la_oenb[13] ( PIN la_oenb[13] ) ( mprj la_oenb[13] ) + USE SIGNAL
-      + ROUTED met2 ( 871470 2380 0 ) ( * 34500 )
-      NEW met2 ( 871470 34500 ) ( 876070 * )
-      NEW met2 ( 876070 34500 ) ( * 1662090 )
-      NEW met2 ( 1442790 1690140 ) ( 1443940 * 0 )
-      NEW met2 ( 1442790 1662090 ) ( * 1690140 )
-      NEW met1 ( 876070 1662090 ) ( 1442790 * )
-      NEW met1 ( 876070 1662090 ) M1M2_PR
-      NEW met1 ( 1442790 1662090 ) M1M2_PR ;
-    - la_oenb[14] ( PIN la_oenb[14] ) ( mprj la_oenb[14] ) + USE SIGNAL
-      + ROUTED met2 ( 889410 2380 0 ) ( * 34500 )
-      NEW met2 ( 889410 34500 ) ( 889870 * )
-      NEW met2 ( 889870 34500 ) ( * 1668890 )
-      NEW met1 ( 1442330 1683510 ) ( 1449230 * )
-      NEW met2 ( 1449230 1683510 ) ( * 1690140 )
-      NEW met2 ( 1449230 1690140 ) ( 1449460 * 0 )
-      NEW met2 ( 1442330 1668890 ) ( * 1683510 )
-      NEW met1 ( 889870 1668890 ) ( 1442330 * )
-      NEW met1 ( 889870 1668890 ) M1M2_PR
-      NEW met1 ( 1442330 1668890 ) M1M2_PR
-      NEW met1 ( 1442330 1683510 ) M1M2_PR
-      NEW met1 ( 1449230 1683510 ) M1M2_PR ;
-    - la_oenb[15] ( PIN la_oenb[15] ) ( mprj la_oenb[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1454750 1690140 ) ( 1454980 * 0 )
-      NEW met2 ( 1454750 1662430 ) ( * 1690140 )
-      NEW met1 ( 910570 1662430 ) ( 1454750 * )
-      NEW met2 ( 907350 2380 0 ) ( * 34500 )
-      NEW met2 ( 907350 34500 ) ( 910570 * )
-      NEW met2 ( 910570 34500 ) ( * 1662430 )
-      NEW met1 ( 1454750 1662430 ) M1M2_PR
-      NEW met1 ( 910570 1662430 ) M1M2_PR ;
-    - la_oenb[16] ( PIN la_oenb[16] ) ( mprj la_oenb[16] ) + USE SIGNAL
-      + ROUTED met1 ( 1456590 1652570 ) ( 1459350 * )
-      NEW met2 ( 1456590 66470 ) ( * 1652570 )
-      NEW met2 ( 1459350 1690140 ) ( 1460500 * 0 )
-      NEW met2 ( 1459350 1652570 ) ( * 1690140 )
-      NEW met2 ( 924830 2380 0 ) ( * 66470 )
-      NEW met1 ( 924830 66470 ) ( 1456590 * )
-      NEW met1 ( 1456590 1652570 ) M1M2_PR
-      NEW met1 ( 1459350 1652570 ) M1M2_PR
-      NEW met1 ( 1456590 66470 ) M1M2_PR
-      NEW met1 ( 924830 66470 ) M1M2_PR ;
-    - la_oenb[17] ( PIN la_oenb[17] ) ( mprj la_oenb[17] ) + USE SIGNAL
-      + ROUTED met1 ( 1457050 1683510 ) ( 1464870 * )
-      NEW met2 ( 1464870 1683510 ) ( * 1690140 )
-      NEW met2 ( 1464870 1690140 ) ( 1466020 * 0 )
-      NEW met2 ( 1457050 1662770 ) ( * 1683510 )
-      NEW met2 ( 942770 2380 0 ) ( * 3060 )
-      NEW met2 ( 942770 3060 ) ( 943690 * )
-      NEW met2 ( 943690 2380 ) ( * 3060 )
-      NEW met2 ( 943690 2380 ) ( 945070 * )
-      NEW met1 ( 945070 1662770 ) ( 1457050 * )
-      NEW met2 ( 945070 2380 ) ( * 1662770 )
-      NEW met1 ( 1457050 1662770 ) M1M2_PR
-      NEW met1 ( 1457050 1683510 ) M1M2_PR
-      NEW met1 ( 1464870 1683510 ) M1M2_PR
-      NEW met1 ( 945070 1662770 ) M1M2_PR ;
-    - la_oenb[18] ( PIN la_oenb[18] ) ( mprj la_oenb[18] ) + USE SIGNAL
-      + ROUTED met2 ( 960250 2380 0 ) ( * 46410 )
-      NEW met2 ( 1470390 1690140 ) ( 1471540 * 0 )
-      NEW met2 ( 1470390 46410 ) ( * 1690140 )
-      NEW met1 ( 960250 46410 ) ( 1470390 * )
-      NEW met1 ( 960250 46410 ) M1M2_PR
-      NEW met1 ( 1470390 46410 ) M1M2_PR ;
-    - la_oenb[19] ( PIN la_oenb[19] ) ( mprj la_oenb[19] ) + USE SIGNAL
-      + ROUTED met1 ( 1470850 1652570 ) ( 1475910 * )
-      NEW met2 ( 978190 2380 0 ) ( * 46750 )
-      NEW met2 ( 1470850 46750 ) ( * 1652570 )
-      NEW met2 ( 1475910 1690140 ) ( 1476600 * 0 )
-      NEW met2 ( 1475910 1652570 ) ( * 1690140 )
-      NEW met1 ( 978190 46750 ) ( 1470850 * )
-      NEW met1 ( 1470850 1652570 ) M1M2_PR
-      NEW met1 ( 1475910 1652570 ) M1M2_PR
-      NEW met1 ( 978190 46750 ) M1M2_PR
-      NEW met1 ( 1470850 46750 ) M1M2_PR ;
-    - la_oenb[1] ( PIN la_oenb[1] ) ( mprj la_oenb[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1374710 45730 ) ( * 1580100 )
-      NEW met2 ( 1374710 1580100 ) ( 1377010 * )
-      NEW met2 ( 1377010 1690140 ) ( 1378160 * 0 )
-      NEW met2 ( 658950 2380 0 ) ( * 45730 )
-      NEW met1 ( 658950 45730 ) ( 1374710 * )
-      NEW met2 ( 1377010 1580100 ) ( * 1690140 )
-      NEW met1 ( 1374710 45730 ) M1M2_PR
-      NEW met1 ( 658950 45730 ) M1M2_PR ;
-    - la_oenb[20] ( PIN la_oenb[20] ) ( mprj la_oenb[20] ) + USE SIGNAL
-      + ROUTED met2 ( 995670 2380 0 ) ( * 47090 )
-      NEW met2 ( 1477750 47090 ) ( * 1580100 )
-      NEW met2 ( 1477750 1580100 ) ( 1479590 * )
-      NEW met2 ( 1479590 1683340 ) ( 1480970 * )
-      NEW met2 ( 1480970 1683340 ) ( * 1690140 )
-      NEW met2 ( 1480970 1690140 ) ( 1482120 * 0 )
-      NEW met2 ( 1479590 1580100 ) ( * 1683340 )
-      NEW met1 ( 995670 47090 ) ( 1477750 * )
-      NEW met1 ( 995670 47090 ) M1M2_PR
-      NEW met1 ( 1477750 47090 ) M1M2_PR ;
-    - la_oenb[21] ( PIN la_oenb[21] ) ( mprj la_oenb[21] ) + USE SIGNAL
-      + ROUTED met2 ( 1013610 2380 0 ) ( * 47430 )
-      NEW met1 ( 1013610 47430 ) ( 1484190 * )
-      NEW met2 ( 1484190 47430 ) ( * 1676700 )
-      NEW met2 ( 1484190 1676700 ) ( 1486490 * )
-      NEW met2 ( 1486490 1676700 ) ( * 1690140 )
-      NEW met2 ( 1486490 1690140 ) ( 1487640 * 0 )
-      NEW met1 ( 1013610 47430 ) M1M2_PR
-      NEW met1 ( 1484190 47430 ) M1M2_PR ;
-    - la_oenb[22] ( PIN la_oenb[22] ) ( mprj la_oenb[22] ) + USE SIGNAL
-      + ROUTED met2 ( 1031090 2380 0 ) ( * 47770 )
-      NEW met1 ( 1031090 47770 ) ( 1491090 * )
-      NEW met2 ( 1491090 47770 ) ( * 1676700 )
-      NEW met2 ( 1491090 1676700 ) ( 1492010 * )
-      NEW met2 ( 1492010 1676700 ) ( * 1690140 )
-      NEW met2 ( 1492010 1690140 ) ( 1493160 * 0 )
-      NEW met1 ( 1031090 47770 ) M1M2_PR
-      NEW met1 ( 1491090 47770 ) M1M2_PR ;
-    - la_oenb[23] ( PIN la_oenb[23] ) ( mprj la_oenb[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1049030 2380 0 ) ( * 48110 )
-      NEW met1 ( 1049030 48110 ) ( 1498450 * )
-      NEW met2 ( 1498450 1690140 ) ( 1498680 * 0 )
-      NEW met2 ( 1498450 48110 ) ( * 1690140 )
-      NEW met1 ( 1049030 48110 ) M1M2_PR
-      NEW met1 ( 1498450 48110 ) M1M2_PR ;
-    - la_oenb[24] ( PIN la_oenb[24] ) ( mprj la_oenb[24] ) + USE SIGNAL
-      + ROUTED met2 ( 1066970 2380 0 ) ( * 44370 )
-      NEW met1 ( 1497990 1652570 ) ( 1503050 * )
-      NEW met1 ( 1066970 44370 ) ( 1497990 * )
-      NEW met2 ( 1497990 44370 ) ( * 1652570 )
-      NEW met2 ( 1503050 1690140 ) ( 1504200 * 0 )
-      NEW met2 ( 1503050 1652570 ) ( * 1690140 )
-      NEW met1 ( 1066970 44370 ) M1M2_PR
-      NEW met1 ( 1497990 1652570 ) M1M2_PR
-      NEW met1 ( 1503050 1652570 ) M1M2_PR
-      NEW met1 ( 1497990 44370 ) M1M2_PR ;
-    - la_oenb[25] ( PIN la_oenb[25] ) ( mprj la_oenb[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1084450 2380 0 ) ( * 44030 )
-      NEW met1 ( 1504890 1652570 ) ( 1508570 * )
-      NEW met1 ( 1084450 44030 ) ( 1504890 * )
-      NEW met2 ( 1504890 44030 ) ( * 1652570 )
-      NEW met2 ( 1508570 1690140 ) ( 1509720 * 0 )
-      NEW met2 ( 1508570 1652570 ) ( * 1690140 )
-      NEW met1 ( 1084450 44030 ) M1M2_PR
-      NEW met1 ( 1504890 1652570 ) M1M2_PR
-      NEW met1 ( 1508570 1652570 ) M1M2_PR
-      NEW met1 ( 1504890 44030 ) M1M2_PR ;
-    - la_oenb[26] ( PIN la_oenb[26] ) ( mprj la_oenb[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1512250 1652570 ) ( 1512710 * )
-      NEW met2 ( 1102390 2380 0 ) ( * 43690 )
-      NEW met1 ( 1102390 43690 ) ( 1512250 * )
-      NEW met2 ( 1512250 43690 ) ( * 1652570 )
-      NEW met2 ( 1512710 1652570 ) ( * 1676700 )
-      NEW met2 ( 1512710 1676700 ) ( 1514090 * )
-      NEW met2 ( 1514090 1676700 ) ( * 1690140 )
-      NEW met2 ( 1514090 1690140 ) ( 1515240 * 0 )
-      NEW met1 ( 1102390 43690 ) M1M2_PR
-      NEW met1 ( 1512250 43690 ) M1M2_PR ;
-    - la_oenb[27] ( PIN la_oenb[27] ) ( mprj la_oenb[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1119870 2380 0 ) ( * 43350 )
-      NEW met1 ( 1119870 43350 ) ( 1518690 * )
-      NEW met2 ( 1518690 43350 ) ( * 1676700 )
-      NEW met2 ( 1518690 1676700 ) ( 1519610 * )
-      NEW met2 ( 1519610 1676700 ) ( * 1690140 )
-      NEW met2 ( 1519610 1690140 ) ( 1520760 * 0 )
-      NEW met1 ( 1119870 43350 ) M1M2_PR
-      NEW met1 ( 1518690 43350 ) M1M2_PR ;
-    - la_oenb[28] ( PIN la_oenb[28] ) ( mprj la_oenb[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1137810 2380 0 ) ( * 43010 )
-      NEW met1 ( 1137810 43010 ) ( 1526050 * )
-      NEW met2 ( 1526050 1690140 ) ( 1526280 * 0 )
-      NEW met2 ( 1526050 43010 ) ( * 1690140 )
-      NEW met1 ( 1137810 43010 ) M1M2_PR
-      NEW met1 ( 1526050 43010 ) M1M2_PR ;
-    - la_oenb[29] ( PIN la_oenb[29] ) ( mprj la_oenb[29] ) + USE SIGNAL
-      + ROUTED met2 ( 1155290 2380 0 ) ( * 42670 )
-      NEW met1 ( 1155290 42670 ) ( 1526510 * )
-      NEW met2 ( 1526510 42670 ) ( * 1580100 )
-      NEW met2 ( 1526510 1580100 ) ( 1530650 * )
-      NEW met2 ( 1530650 1690140 ) ( 1531800 * 0 )
-      NEW met2 ( 1530650 1580100 ) ( * 1690140 )
-      NEW met1 ( 1155290 42670 ) M1M2_PR
-      NEW met1 ( 1526510 42670 ) M1M2_PR ;
-    - la_oenb[2] ( PIN la_oenb[2] ) ( mprj la_oenb[2] ) + USE SIGNAL
-      + ROUTED met2 ( 676430 2380 0 ) ( * 46070 )
-      NEW met2 ( 1381610 1676700 ) ( 1382530 * )
-      NEW met2 ( 1382530 1676700 ) ( * 1690140 )
-      NEW met2 ( 1382530 1690140 ) ( 1383680 * 0 )
-      NEW met1 ( 676430 46070 ) ( 1380690 * )
-      NEW met1 ( 1380690 1607690 ) ( 1381610 * )
-      NEW met2 ( 1380690 46070 ) ( * 1607690 )
-      NEW met2 ( 1381610 1607690 ) ( * 1676700 )
-      NEW met1 ( 676430 46070 ) M1M2_PR
-      NEW met1 ( 1380690 46070 ) M1M2_PR
-      NEW met1 ( 1380690 1607690 ) M1M2_PR
-      NEW met1 ( 1381610 1607690 ) M1M2_PR ;
-    - la_oenb[30] ( PIN la_oenb[30] ) ( mprj la_oenb[30] ) + USE SIGNAL
-      + ROUTED met2 ( 1173230 2380 0 ) ( * 17340 )
-      NEW met2 ( 1173230 17340 ) ( 1175070 * )
-      NEW met2 ( 1175070 17340 ) ( * 42330 )
-      NEW met2 ( 1533410 42330 ) ( * 1580100 )
-      NEW met2 ( 1533410 1580100 ) ( 1536170 * )
-      NEW met2 ( 1536170 1690140 ) ( 1536860 * 0 )
-      NEW met2 ( 1536170 1580100 ) ( * 1690140 )
-      NEW met1 ( 1175070 42330 ) ( 1533410 * )
-      NEW met1 ( 1175070 42330 ) M1M2_PR
-      NEW met1 ( 1533410 42330 ) M1M2_PR ;
-    - la_oenb[31] ( PIN la_oenb[31] ) ( mprj la_oenb[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1190710 2380 0 ) ( * 44710 )
-      NEW met2 ( 1539850 44710 ) ( * 1580100 )
-      NEW met2 ( 1539850 1580100 ) ( 1541230 * )
-      NEW met2 ( 1541230 1690140 ) ( 1542380 * 0 )
-      NEW met2 ( 1541230 1580100 ) ( * 1690140 )
-      NEW met1 ( 1190710 44710 ) ( 1539850 * )
-      NEW met1 ( 1190710 44710 ) M1M2_PR
-      NEW met1 ( 1539850 44710 ) M1M2_PR ;
-    - la_oenb[32] ( PIN la_oenb[32] ) ( mprj la_oenb[32] ) + USE SIGNAL
-      + ROUTED met2 ( 1547210 1690140 ) ( 1547900 * 0 )
-      NEW met2 ( 1547210 41990 ) ( * 1690140 )
-      NEW met2 ( 1208650 2380 0 ) ( * 41990 )
-      NEW met1 ( 1208650 41990 ) ( 1547210 * )
-      NEW met1 ( 1547210 41990 ) M1M2_PR
-      NEW met1 ( 1208650 41990 ) M1M2_PR ;
-    - la_oenb[33] ( PIN la_oenb[33] ) ( mprj la_oenb[33] ) + USE SIGNAL
-      + ROUTED met2 ( 1553420 1688780 ) ( 1553650 * )
-      NEW met2 ( 1553420 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1553650 45050 ) ( * 1688780 )
-      NEW met2 ( 1226130 2380 0 ) ( * 45050 )
-      NEW met1 ( 1226130 45050 ) ( 1553650 * )
-      NEW met1 ( 1553650 45050 ) M1M2_PR
-      NEW met1 ( 1226130 45050 ) M1M2_PR ;
-    - la_oenb[34] ( PIN la_oenb[34] ) ( mprj la_oenb[34] ) + USE SIGNAL
-      + ROUTED met2 ( 1244070 2380 0 ) ( * 45390 )
-      NEW met2 ( 1554110 45390 ) ( * 1580100 )
-      NEW met2 ( 1554110 1580100 ) ( 1557790 * )
-      NEW met2 ( 1557790 1690140 ) ( 1558940 * 0 )
-      NEW met2 ( 1557790 1580100 ) ( * 1690140 )
-      NEW met1 ( 1244070 45390 ) ( 1554110 * )
-      NEW met1 ( 1244070 45390 ) M1M2_PR
-      NEW met1 ( 1554110 45390 ) M1M2_PR ;
-    - la_oenb[35] ( PIN la_oenb[35] ) ( mprj la_oenb[35] ) + USE SIGNAL
-      + ROUTED met1 ( 1560090 1652570 ) ( 1563310 * )
-      NEW met2 ( 1262010 2380 0 ) ( * 59670 )
-      NEW met2 ( 1560090 59670 ) ( * 1652570 )
-      NEW met2 ( 1563310 1690140 ) ( 1564460 * 0 )
-      NEW met2 ( 1563310 1652570 ) ( * 1690140 )
-      NEW met1 ( 1262010 59670 ) ( 1560090 * )
-      NEW met1 ( 1560090 1652570 ) M1M2_PR
-      NEW met1 ( 1563310 1652570 ) M1M2_PR
-      NEW met1 ( 1262010 59670 ) M1M2_PR
-      NEW met1 ( 1560090 59670 ) M1M2_PR ;
-    - la_oenb[36] ( PIN la_oenb[36] ) ( mprj la_oenb[36] ) + USE SIGNAL
-      + ROUTED met2 ( 1279490 2380 0 ) ( * 17510 )
-      NEW met1 ( 1279490 17510 ) ( 1283170 * )
-      NEW met2 ( 1283170 17510 ) ( * 51510 )
-      NEW met2 ( 1567450 51510 ) ( * 1580100 )
-      NEW met2 ( 1567450 1580100 ) ( 1568830 * )
-      NEW met2 ( 1568830 1690140 ) ( 1569980 * 0 )
-      NEW met2 ( 1568830 1580100 ) ( * 1690140 )
-      NEW met1 ( 1283170 51510 ) ( 1567450 * )
-      NEW met1 ( 1279490 17510 ) M1M2_PR
-      NEW met1 ( 1283170 17510 ) M1M2_PR
-      NEW met1 ( 1283170 51510 ) M1M2_PR
-      NEW met1 ( 1567450 51510 ) M1M2_PR ;
-    - la_oenb[37] ( PIN la_oenb[37] ) ( mprj la_oenb[37] ) + USE SIGNAL
-      + ROUTED met2 ( 1480050 31450 ) ( * 1678750 )
-      NEW met2 ( 1574350 1678750 ) ( * 1690140 )
-      NEW met2 ( 1574350 1690140 ) ( 1575500 * 0 )
-      NEW met2 ( 1297430 2380 0 ) ( * 31450 )
-      NEW met1 ( 1297430 31450 ) ( 1480050 * )
-      NEW met1 ( 1480050 1678750 ) ( 1574350 * )
-      NEW met1 ( 1480050 31450 ) M1M2_PR
-      NEW met1 ( 1480050 1678750 ) M1M2_PR
-      NEW met1 ( 1574350 1678750 ) M1M2_PR
-      NEW met1 ( 1297430 31450 ) M1M2_PR ;
-    - la_oenb[38] ( PIN la_oenb[38] ) ( mprj la_oenb[38] ) + USE SIGNAL
-      + ROUTED met2 ( 1314910 2380 0 ) ( * 17510 )
-      NEW met1 ( 1314910 17510 ) ( 1317670 * )
-      NEW met2 ( 1317670 17510 ) ( * 1680110 )
-      NEW met2 ( 1580330 1680110 ) ( * 1690140 )
-      NEW met2 ( 1580330 1690140 ) ( 1581020 * 0 )
-      NEW met1 ( 1317670 1680110 ) ( 1580330 * )
-      NEW met1 ( 1314910 17510 ) M1M2_PR
-      NEW met1 ( 1317670 17510 ) M1M2_PR
-      NEW met1 ( 1317670 1680110 ) M1M2_PR
-      NEW met1 ( 1580330 1680110 ) M1M2_PR ;
-    - la_oenb[39] ( PIN la_oenb[39] ) ( mprj la_oenb[39] ) + USE SIGNAL
-      + ROUTED li1 ( 1343890 1680790 ) ( 1344810 * )
-      NEW met2 ( 1332850 2380 0 ) ( * 17510 )
-      NEW met1 ( 1332850 17510 ) ( 1338370 * )
-      NEW met2 ( 1338370 17510 ) ( * 1680790 )
-      NEW met1 ( 1338370 1680790 ) ( 1343890 * )
-      NEW met2 ( 1585390 1680790 ) ( * 1690140 )
-      NEW met2 ( 1585390 1690140 ) ( 1586540 * 0 )
-      NEW met1 ( 1344810 1680790 ) ( 1585390 * )
-      NEW li1 ( 1343890 1680790 ) L1M1_PR_MR
-      NEW li1 ( 1344810 1680790 ) L1M1_PR_MR
-      NEW met1 ( 1332850 17510 ) M1M2_PR
-      NEW met1 ( 1338370 17510 ) M1M2_PR
-      NEW met1 ( 1338370 1680790 ) M1M2_PR
-      NEW met1 ( 1585390 1680790 ) M1M2_PR ;
-    - la_oenb[3] ( PIN la_oenb[3] ) ( mprj la_oenb[3] ) + USE SIGNAL
-      + ROUTED met2 ( 694370 2380 0 ) ( * 3060 )
-      NEW met2 ( 694370 3060 ) ( 695290 * )
-      NEW met2 ( 695290 2380 ) ( * 3060 )
-      NEW met2 ( 695290 2380 ) ( 696670 * )
-      NEW met2 ( 696670 2380 ) ( * 72250 )
-      NEW met1 ( 696670 72250 ) ( 1388050 * )
-      NEW met2 ( 1388050 1690140 ) ( 1389200 * 0 )
-      NEW met2 ( 1388050 72250 ) ( * 1690140 )
-      NEW met1 ( 696670 72250 ) M1M2_PR
-      NEW met1 ( 1388050 72250 ) M1M2_PR ;
-    - la_oenb[40] ( PIN la_oenb[40] ) ( mprj la_oenb[40] ) + USE SIGNAL
-      + ROUTED met2 ( 1350330 2380 0 ) ( * 3060 )
-      NEW met2 ( 1350330 3060 ) ( 1351250 * )
-      NEW met2 ( 1351250 2380 ) ( * 3060 )
-      NEW met2 ( 1351250 2380 ) ( 1352170 * )
-      NEW met2 ( 1352170 2380 ) ( * 1680450 )
-      NEW met2 ( 1590910 1680450 ) ( * 1690140 )
-      NEW met2 ( 1590910 1690140 ) ( 1592060 * 0 )
-      NEW met1 ( 1352170 1680450 ) ( 1590910 * )
-      NEW met1 ( 1352170 1680450 ) M1M2_PR
-      NEW met1 ( 1590910 1680450 ) M1M2_PR ;
-    - la_oenb[41] ( PIN la_oenb[41] ) ( mprj la_oenb[41] ) + USE SIGNAL
-      + ROUTED met2 ( 1368270 2380 0 ) ( * 17510 )
-      NEW met1 ( 1368270 17510 ) ( 1372870 * )
-      NEW met2 ( 1596430 1681130 ) ( * 1690140 )
-      NEW met2 ( 1596430 1690140 ) ( 1597120 * 0 )
-      NEW met1 ( 1372870 1681130 ) ( 1596430 * )
-      NEW met2 ( 1372870 17510 ) ( * 1681130 )
-      NEW met1 ( 1368270 17510 ) M1M2_PR
-      NEW met1 ( 1372870 17510 ) M1M2_PR
-      NEW met1 ( 1372870 1681130 ) M1M2_PR
-      NEW met1 ( 1596430 1681130 ) M1M2_PR ;
-    - la_oenb[42] ( PIN la_oenb[42] ) ( mprj la_oenb[42] ) + USE SIGNAL
-      + ROUTED met2 ( 1385750 2380 0 ) ( * 16660 )
-      NEW met3 ( 1385750 16660 ) ( 1601490 * )
-      NEW met2 ( 1601490 1690140 ) ( 1602640 * 0 )
-      NEW met2 ( 1601490 16660 ) ( * 1690140 )
-      NEW met2 ( 1385750 16660 ) M2M3_PR_M
-      NEW met2 ( 1601490 16660 ) M2M3_PR_M ;
-    - la_oenb[43] ( PIN la_oenb[43] ) ( mprj la_oenb[43] ) + USE SIGNAL
-      + ROUTED met2 ( 1403690 2380 0 ) ( * 17510 )
-      NEW met1 ( 1403690 17510 ) ( 1407370 * )
-      NEW met2 ( 1607930 1681470 ) ( * 1690140 )
-      NEW met2 ( 1607930 1690140 ) ( 1608160 * 0 )
-      NEW met1 ( 1406910 1681470 ) ( 1607930 * )
-      NEW met2 ( 1406910 1656000 ) ( * 1681470 )
-      NEW met2 ( 1406910 1656000 ) ( 1407370 * )
-      NEW met2 ( 1407370 17510 ) ( * 1656000 )
-      NEW met1 ( 1403690 17510 ) M1M2_PR
-      NEW met1 ( 1407370 17510 ) M1M2_PR
-      NEW met1 ( 1406910 1681470 ) M1M2_PR
-      NEW met1 ( 1607930 1681470 ) M1M2_PR ;
-    - la_oenb[44] ( PIN la_oenb[44] ) ( mprj la_oenb[44] ) + USE SIGNAL
-      + ROUTED met2 ( 1421630 2380 0 ) ( * 17850 )
-      NEW met1 ( 1421630 17850 ) ( 1608390 * )
-      NEW met1 ( 1608390 1652570 ) ( 1612530 * )
-      NEW met2 ( 1608390 17850 ) ( * 1652570 )
-      NEW met2 ( 1612530 1690140 ) ( 1613680 * 0 )
-      NEW met2 ( 1612530 1652570 ) ( * 1690140 )
-      NEW met1 ( 1421630 17850 ) M1M2_PR
-      NEW met1 ( 1608390 17850 ) M1M2_PR
-      NEW met1 ( 1608390 1652570 ) M1M2_PR
-      NEW met1 ( 1612530 1652570 ) M1M2_PR ;
-    - la_oenb[45] ( PIN la_oenb[45] ) ( mprj la_oenb[45] ) + USE SIGNAL
-      + ROUTED met2 ( 1439110 2380 0 ) ( * 16830 )
-      NEW met1 ( 1439110 16830 ) ( 1441870 * )
-      NEW met1 ( 1441870 1678070 ) ( 1467170 * )
-      NEW li1 ( 1467170 1678070 ) ( * 1682150 )
-      NEW met2 ( 1441870 16830 ) ( * 1678070 )
-      NEW met2 ( 1618050 1682150 ) ( * 1690140 )
-      NEW met2 ( 1618050 1690140 ) ( 1619200 * 0 )
-      NEW met1 ( 1467170 1682150 ) ( 1618050 * )
-      NEW met1 ( 1439110 16830 ) M1M2_PR
-      NEW met1 ( 1441870 16830 ) M1M2_PR
-      NEW met1 ( 1441870 1678070 ) M1M2_PR
-      NEW li1 ( 1467170 1678070 ) L1M1_PR_MR
-      NEW li1 ( 1467170 1682150 ) L1M1_PR_MR
-      NEW met1 ( 1618050 1682150 ) M1M2_PR ;
-    - la_oenb[46] ( PIN la_oenb[46] ) ( mprj la_oenb[46] ) + USE SIGNAL
-      + ROUTED met2 ( 1457050 2380 0 ) ( * 18530 )
-      NEW li1 ( 1601490 17510 ) ( * 18530 )
-      NEW met1 ( 1601490 17510 ) ( 1608850 * )
-      NEW met1 ( 1608850 17510 ) ( * 17850 )
-      NEW met1 ( 1608850 17850 ) ( 1616670 * )
-      NEW met1 ( 1616670 17850 ) ( * 18190 )
-      NEW met1 ( 1616670 18190 ) ( 1621270 * )
-      NEW met2 ( 1621270 18190 ) ( * 20060 )
-      NEW met2 ( 1621270 20060 ) ( 1621730 * )
-      NEW met1 ( 1457050 18530 ) ( 1601490 * )
-      NEW met1 ( 1621730 1652570 ) ( 1623570 * )
-      NEW met2 ( 1621730 20060 ) ( * 1652570 )
-      NEW met2 ( 1623570 1690140 ) ( 1624720 * 0 )
-      NEW met2 ( 1623570 1652570 ) ( * 1690140 )
-      NEW met1 ( 1457050 18530 ) M1M2_PR
-      NEW li1 ( 1601490 18530 ) L1M1_PR_MR
-      NEW li1 ( 1601490 17510 ) L1M1_PR_MR
-      NEW met1 ( 1621270 18190 ) M1M2_PR
-      NEW met1 ( 1621730 1652570 ) M1M2_PR
-      NEW met1 ( 1623570 1652570 ) M1M2_PR ;
-    - la_oenb[47] ( PIN la_oenb[47] ) ( mprj la_oenb[47] ) + USE SIGNAL
-      + ROUTED met2 ( 1474530 2380 0 ) ( * 18700 )
-      NEW met2 ( 1629090 1690140 ) ( 1630240 * 0 )
-      NEW met2 ( 1629090 18700 ) ( * 1690140 )
-      NEW met3 ( 1474530 18700 ) ( 1629090 * )
-      NEW met2 ( 1474530 18700 ) M2M3_PR_M
-      NEW met2 ( 1629090 18700 ) M2M3_PR_M ;
-    - la_oenb[48] ( PIN la_oenb[48] ) ( mprj la_oenb[48] ) + USE SIGNAL
-      + ROUTED met2 ( 1635530 1682830 ) ( * 1690140 )
-      NEW met2 ( 1635530 1690140 ) ( 1635760 * 0 )
-      NEW met2 ( 1492470 2380 0 ) ( * 16830 )
-      NEW met1 ( 1492470 16830 ) ( 1497070 * )
-      NEW met1 ( 1497070 1679430 ) ( 1508570 * )
-      NEW li1 ( 1508570 1679430 ) ( * 1682830 )
-      NEW met2 ( 1497070 16830 ) ( * 1679430 )
-      NEW met1 ( 1508570 1682830 ) ( 1635530 * )
-      NEW met1 ( 1635530 1682830 ) M1M2_PR
-      NEW met1 ( 1492470 16830 ) M1M2_PR
-      NEW met1 ( 1497070 16830 ) M1M2_PR
-      NEW met1 ( 1497070 1679430 ) M1M2_PR
-      NEW li1 ( 1508570 1679430 ) L1M1_PR_MR
-      NEW li1 ( 1508570 1682830 ) L1M1_PR_MR ;
-    - la_oenb[49] ( PIN la_oenb[49] ) ( mprj la_oenb[49] ) + USE SIGNAL
-      + ROUTED met1 ( 1632310 18530 ) ( * 18870 )
-      NEW met1 ( 1632310 18870 ) ( 1636450 * )
-      NEW met2 ( 1636450 18870 ) ( * 1580100 )
-      NEW met2 ( 1636450 1580100 ) ( 1638290 * )
-      NEW met2 ( 1638290 1683340 ) ( 1640130 * )
-      NEW met2 ( 1640130 1683340 ) ( * 1690140 )
-      NEW met2 ( 1640130 1690140 ) ( 1641280 * 0 )
-      NEW met2 ( 1638290 1580100 ) ( * 1683340 )
-      NEW met2 ( 1509950 2380 0 ) ( * 19550 )
-      NEW li1 ( 1603790 18530 ) ( * 19550 )
-      NEW met1 ( 1509950 19550 ) ( 1603790 * )
-      NEW met1 ( 1603790 18530 ) ( 1632310 * )
-      NEW met1 ( 1636450 18870 ) M1M2_PR
-      NEW met1 ( 1509950 19550 ) M1M2_PR
-      NEW li1 ( 1603790 19550 ) L1M1_PR_MR
-      NEW li1 ( 1603790 18530 ) L1M1_PR_MR ;
-    - la_oenb[4] ( PIN la_oenb[4] ) ( mprj la_oenb[4] ) + USE SIGNAL
-      + ROUTED met1 ( 717370 1661410 ) ( 1393570 * )
-      NEW met2 ( 712310 2380 0 ) ( * 34500 )
-      NEW met2 ( 712310 34500 ) ( 717370 * )
-      NEW met2 ( 717370 34500 ) ( * 1661410 )
-      NEW met2 ( 1393570 1661410 ) ( * 1676700 )
-      NEW met2 ( 1393570 1676700 ) ( 1394030 * )
-      NEW met2 ( 1394030 1676700 ) ( * 1690140 )
-      NEW met2 ( 1394030 1690140 ) ( 1394720 * 0 )
-      NEW met1 ( 717370 1661410 ) M1M2_PR
-      NEW met1 ( 1393570 1661410 ) M1M2_PR ;
-    - la_oenb[50] ( PIN la_oenb[50] ) ( mprj la_oenb[50] ) + USE SIGNAL
-      + ROUTED met2 ( 1642890 19890 ) ( * 1580100 )
-      NEW met2 ( 1642890 1580100 ) ( 1643350 * )
-      NEW met2 ( 1643350 1684020 ) ( 1645650 * )
-      NEW met2 ( 1645650 1684020 ) ( * 1690140 )
-      NEW met2 ( 1645650 1690140 ) ( 1646800 * 0 )
-      NEW met2 ( 1643350 1580100 ) ( * 1684020 )
-      NEW met2 ( 1527890 2380 0 ) ( * 19890 )
-      NEW met1 ( 1527890 19890 ) ( 1642890 * )
-      NEW met1 ( 1642890 19890 ) M1M2_PR
-      NEW met1 ( 1527890 19890 ) M1M2_PR ;
-    - la_oenb[51] ( PIN la_oenb[51] ) ( mprj la_oenb[51] ) + USE SIGNAL
-      + ROUTED met2 ( 1545370 2380 0 ) ( * 20570 )
-      NEW met1 ( 1649790 1633190 ) ( 1651170 * )
-      NEW met2 ( 1649790 20570 ) ( * 1633190 )
-      NEW met2 ( 1651170 1690140 ) ( 1652320 * 0 )
-      NEW met2 ( 1651170 1633190 ) ( * 1690140 )
-      NEW met1 ( 1545370 20570 ) ( 1649790 * )
-      NEW met1 ( 1545370 20570 ) M1M2_PR
-      NEW met1 ( 1649790 20570 ) M1M2_PR
-      NEW met1 ( 1649790 1633190 ) M1M2_PR
-      NEW met1 ( 1651170 1633190 ) M1M2_PR ;
-    - la_oenb[52] ( PIN la_oenb[52] ) ( mprj la_oenb[52] ) + USE SIGNAL
-      + ROUTED met2 ( 1563310 2380 0 ) ( * 15810 )
-      NEW met1 ( 1651170 15810 ) ( * 16150 )
-      NEW met1 ( 1651170 16150 ) ( 1658990 * )
-      NEW met2 ( 1658070 82800 ) ( 1658990 * )
-      NEW met2 ( 1658990 16150 ) ( * 82800 )
-      NEW met2 ( 1657380 1688780 ) ( 1657610 * )
-      NEW met2 ( 1657380 1688780 ) ( * 1690140 0 )
-      NEW met1 ( 1563310 15810 ) ( 1651170 * )
-      NEW met2 ( 1658070 82800 ) ( * 1607700 )
-      NEW met1 ( 1657610 1632170 ) ( 1658990 * )
-      NEW met2 ( 1658990 1607700 ) ( * 1632170 )
-      NEW met2 ( 1658070 1607700 ) ( 1658990 * )
-      NEW met2 ( 1657610 1632170 ) ( * 1688780 )
-      NEW met1 ( 1563310 15810 ) M1M2_PR
-      NEW met1 ( 1658990 16150 ) M1M2_PR
-      NEW met1 ( 1657610 1632170 ) M1M2_PR
-      NEW met1 ( 1658990 1632170 ) M1M2_PR ;
-    - la_oenb[53] ( PIN la_oenb[53] ) ( mprj la_oenb[53] ) + USE SIGNAL
-      + ROUTED met2 ( 1658530 14450 ) ( * 34500 )
-      NEW met2 ( 1657610 34500 ) ( 1658530 * )
-      NEW met2 ( 1661750 1690140 ) ( 1662900 * 0 )
-      NEW met2 ( 1581250 2380 0 ) ( * 14450 )
-      NEW met1 ( 1581250 14450 ) ( 1658530 * )
-      NEW met1 ( 1657610 1631150 ) ( 1661750 * )
-      NEW met2 ( 1657610 34500 ) ( * 1631150 )
-      NEW met2 ( 1661750 1631150 ) ( * 1690140 )
-      NEW met1 ( 1658530 14450 ) M1M2_PR
-      NEW met1 ( 1581250 14450 ) M1M2_PR
-      NEW met1 ( 1657610 1631150 ) M1M2_PR
-      NEW met1 ( 1661750 1631150 ) M1M2_PR ;
-    - la_oenb[54] ( PIN la_oenb[54] ) ( mprj la_oenb[54] ) + USE SIGNAL
-      + ROUTED met2 ( 1664050 17170 ) ( * 1580100 )
-      NEW met2 ( 1664050 1580100 ) ( 1665890 * )
-      NEW met2 ( 1665890 1683340 ) ( 1667270 * )
-      NEW met2 ( 1667270 1683340 ) ( * 1690140 )
-      NEW met2 ( 1667270 1690140 ) ( 1668420 * 0 )
-      NEW met2 ( 1598730 2380 0 ) ( * 17170 )
-      NEW met1 ( 1598730 17170 ) ( 1664050 * )
-      NEW met2 ( 1665890 1580100 ) ( * 1683340 )
-      NEW met1 ( 1664050 17170 ) M1M2_PR
-      NEW met1 ( 1598730 17170 ) M1M2_PR ;
-    - la_oenb[55] ( PIN la_oenb[55] ) ( mprj la_oenb[55] ) + USE SIGNAL
-      + ROUTED met2 ( 1672790 1690140 ) ( 1673940 * 0 )
-      NEW met2 ( 1616670 2380 0 ) ( * 9180 )
-      NEW met2 ( 1616670 9180 ) ( 1617130 * )
-      NEW met2 ( 1617130 9180 ) ( * 17850 )
-      NEW met1 ( 1617130 17850 ) ( 1670490 * )
-      NEW met1 ( 1670490 1631830 ) ( 1672790 * )
-      NEW met2 ( 1670490 17850 ) ( * 1631830 )
-      NEW met2 ( 1672790 1631830 ) ( * 1690140 )
-      NEW met1 ( 1670490 17850 ) M1M2_PR
-      NEW met1 ( 1617130 17850 ) M1M2_PR
-      NEW met1 ( 1670490 1631830 ) M1M2_PR
-      NEW met1 ( 1672790 1631830 ) M1M2_PR ;
-    - la_oenb[56] ( PIN la_oenb[56] ) ( mprj la_oenb[56] ) + USE SIGNAL
-      + ROUTED met2 ( 1634150 2380 0 ) ( * 18530 )
-      NEW met1 ( 1634150 18530 ) ( 1677390 * )
-      NEW met1 ( 1677390 1683510 ) ( 1678310 * )
-      NEW met2 ( 1678310 1683510 ) ( * 1690140 )
-      NEW met2 ( 1678310 1690140 ) ( 1679460 * 0 )
-      NEW met2 ( 1677390 18530 ) ( * 1683510 )
-      NEW met1 ( 1634150 18530 ) M1M2_PR
-      NEW met1 ( 1677390 18530 ) M1M2_PR
-      NEW met1 ( 1677390 1683510 ) M1M2_PR
-      NEW met1 ( 1678310 1683510 ) M1M2_PR ;
-    - la_oenb[57] ( PIN la_oenb[57] ) ( mprj la_oenb[57] ) + USE SIGNAL
-      + ROUTED met2 ( 1652090 2380 0 ) ( * 15810 )
-      NEW met1 ( 1652090 15810 ) ( 1666350 * )
-      NEW met2 ( 1683830 1679430 ) ( * 1690140 )
-      NEW met2 ( 1683830 1690140 ) ( 1684980 * 0 )
-      NEW met1 ( 1666350 1679430 ) ( 1683830 * )
-      NEW met2 ( 1666350 15810 ) ( * 1679430 )
-      NEW met1 ( 1652090 15810 ) M1M2_PR
-      NEW met1 ( 1666350 15810 ) M1M2_PR
-      NEW met1 ( 1666350 1679430 ) M1M2_PR
-      NEW met1 ( 1683830 1679430 ) M1M2_PR ;
-    - la_oenb[58] ( PIN la_oenb[58] ) ( mprj la_oenb[58] ) + USE SIGNAL
-      + ROUTED met2 ( 1669570 2380 0 ) ( * 19210 )
-      NEW met1 ( 1669570 19210 ) ( 1684750 * )
-      NEW met2 ( 1684750 19210 ) ( * 1580100 )
-      NEW met2 ( 1684750 1580100 ) ( 1689350 * )
-      NEW met2 ( 1689350 1690140 ) ( 1690500 * 0 )
-      NEW met2 ( 1689350 1580100 ) ( * 1690140 )
-      NEW met1 ( 1669570 19210 ) M1M2_PR
-      NEW met1 ( 1684750 19210 ) M1M2_PR ;
-    - la_oenb[59] ( PIN la_oenb[59] ) ( mprj la_oenb[59] ) + USE SIGNAL
-      + ROUTED met2 ( 1687510 2380 0 ) ( * 17510 )
-      NEW met1 ( 1687510 17510 ) ( 1690730 * )
-      NEW met2 ( 1694870 1690140 ) ( 1696020 * 0 )
-      NEW met1 ( 1690730 1632170 ) ( 1694870 * )
-      NEW met2 ( 1690730 17510 ) ( * 1632170 )
-      NEW met2 ( 1694870 1632170 ) ( * 1690140 )
-      NEW met1 ( 1687510 17510 ) M1M2_PR
-      NEW met1 ( 1690730 17510 ) M1M2_PR
-      NEW met1 ( 1690730 1632170 ) M1M2_PR
-      NEW met1 ( 1694870 1632170 ) M1M2_PR ;
-    - la_oenb[5] ( PIN la_oenb[5] ) ( mprj la_oenb[5] ) + USE SIGNAL
-      + ROUTED met1 ( 731170 1667530 ) ( 1399090 * )
-      NEW met2 ( 729790 2380 0 ) ( * 34500 )
-      NEW met2 ( 729790 34500 ) ( 731170 * )
-      NEW met2 ( 731170 34500 ) ( * 1667530 )
-      NEW met2 ( 1399090 1690140 ) ( 1400240 * 0 )
-      NEW met2 ( 1399090 1667530 ) ( * 1690140 )
-      NEW met1 ( 731170 1667530 ) M1M2_PR
-      NEW met1 ( 1399090 1667530 ) M1M2_PR ;
-    - la_oenb[60] ( PIN la_oenb[60] ) ( mprj la_oenb[60] ) + USE SIGNAL
-      + ROUTED met2 ( 1704990 2380 0 ) ( * 17340 )
-      NEW met2 ( 1704070 17340 ) ( 1704990 * )
-      NEW met2 ( 1702690 1676700 ) ( 1704070 * )
-      NEW met2 ( 1702690 1676700 ) ( * 1690140 )
-      NEW met2 ( 1701540 1690140 0 ) ( 1702690 * )
-      NEW met2 ( 1704070 17340 ) ( * 1676700 ) ;
-    - la_oenb[61] ( PIN la_oenb[61] ) ( mprj la_oenb[61] ) + USE SIGNAL
-      + ROUTED met2 ( 1722930 2380 0 ) ( * 15810 )
-      NEW met1 ( 1710510 15810 ) ( 1722930 * )
-      NEW met1 ( 1708210 1683510 ) ( 1710510 * )
-      NEW met2 ( 1708210 1683510 ) ( * 1690140 )
-      NEW met2 ( 1707060 1690140 0 ) ( 1708210 * )
-      NEW met2 ( 1710510 15810 ) ( * 1683510 )
-      NEW met1 ( 1722930 15810 ) M1M2_PR
-      NEW met1 ( 1710510 15810 ) M1M2_PR
-      NEW met1 ( 1710510 1683510 ) M1M2_PR
-      NEW met1 ( 1708210 1683510 ) M1M2_PR ;
-    - la_oenb[62] ( PIN la_oenb[62] ) ( mprj la_oenb[62] ) + USE SIGNAL
-      + ROUTED met2 ( 1739490 82800 ) ( 1740410 * )
-      NEW met2 ( 1740410 2380 0 ) ( * 82800 )
-      NEW met2 ( 1739490 82800 ) ( * 1680110 )
-      NEW met2 ( 1713730 1680110 ) ( * 1690140 )
-      NEW met2 ( 1712580 1690140 0 ) ( 1713730 * )
-      NEW met1 ( 1713730 1680110 ) ( 1739490 * )
-      NEW met1 ( 1739490 1680110 ) M1M2_PR
-      NEW met1 ( 1713730 1680110 ) M1M2_PR ;
-    - la_oenb[63] ( PIN la_oenb[63] ) ( mprj la_oenb[63] ) + USE SIGNAL
-      + ROUTED met2 ( 1758350 2380 0 ) ( * 20230 )
-      NEW met1 ( 1717410 20230 ) ( 1758350 * )
-      NEW met2 ( 1717410 1690140 ) ( 1717640 * 0 )
-      NEW met2 ( 1717410 20230 ) ( * 1690140 )
-      NEW met1 ( 1758350 20230 ) M1M2_PR
-      NEW met1 ( 1717410 20230 ) M1M2_PR ;
-    - la_oenb[64] ( PIN la_oenb[64] ) ( mprj la_oenb[64] ) + USE SIGNAL
-      + ROUTED met1 ( 1748230 18530 ) ( * 18870 )
-      NEW met1 ( 1724770 18870 ) ( 1748230 * )
-      NEW met2 ( 1776290 2380 0 ) ( * 18530 )
-      NEW met1 ( 1748230 18530 ) ( 1776290 * )
-      NEW met2 ( 1724310 1628400 ) ( 1724770 * )
-      NEW met2 ( 1724770 18870 ) ( * 1628400 )
-      NEW met2 ( 1723160 1690140 0 ) ( 1724310 * )
-      NEW met2 ( 1724310 1628400 ) ( * 1690140 )
-      NEW met1 ( 1724770 18870 ) M1M2_PR
-      NEW met1 ( 1776290 18530 ) M1M2_PR ;
-    - la_oenb[65] ( PIN la_oenb[65] ) ( mprj la_oenb[65] ) + USE SIGNAL
-      + ROUTED met1 ( 1731670 18190 ) ( 1765250 * )
-      NEW met1 ( 1765250 17850 ) ( * 18190 )
-      NEW met2 ( 1731670 18190 ) ( * 1676700 )
-      NEW met2 ( 1729830 1676700 ) ( 1731670 * )
-      NEW met2 ( 1729830 1676700 ) ( * 1690140 )
-      NEW met2 ( 1728680 1690140 0 ) ( 1729830 * )
-      NEW met2 ( 1793770 2380 0 ) ( * 17850 )
-      NEW met1 ( 1765250 17850 ) ( 1793770 * )
-      NEW met1 ( 1731670 18190 ) M1M2_PR
-      NEW met1 ( 1793770 17850 ) M1M2_PR ;
-    - la_oenb[66] ( PIN la_oenb[66] ) ( mprj la_oenb[66] ) + USE SIGNAL
-      + ROUTED met1 ( 1735350 1683170 ) ( 1738570 * )
-      NEW met2 ( 1735350 1683170 ) ( * 1690140 )
-      NEW met2 ( 1734200 1690140 0 ) ( 1735350 * )
-      NEW met2 ( 1738570 17170 ) ( * 1683170 )
-      NEW met2 ( 1811710 2380 0 ) ( * 17170 )
-      NEW met1 ( 1738570 17170 ) ( 1811710 * )
-      NEW met1 ( 1738570 17170 ) M1M2_PR
-      NEW met1 ( 1738570 1683170 ) M1M2_PR
-      NEW met1 ( 1735350 1683170 ) M1M2_PR
-      NEW met1 ( 1811710 17170 ) M1M2_PR ;
-    - la_oenb[67] ( PIN la_oenb[67] ) ( mprj la_oenb[67] ) + USE SIGNAL
-      + ROUTED met2 ( 1829190 2380 0 ) ( * 16150 )
-      NEW met1 ( 1740870 1683510 ) ( 1745010 * )
-      NEW met2 ( 1740870 1683510 ) ( * 1690140 )
-      NEW met2 ( 1739720 1690140 0 ) ( 1740870 * )
-      NEW met2 ( 1745010 16150 ) ( * 1683510 )
-      NEW met1 ( 1745010 16150 ) ( 1829190 * )
-      NEW met1 ( 1745010 16150 ) M1M2_PR
-      NEW met1 ( 1829190 16150 ) M1M2_PR
-      NEW met1 ( 1745010 1683510 ) M1M2_PR
-      NEW met1 ( 1740870 1683510 ) M1M2_PR ;
-    - la_oenb[68] ( PIN la_oenb[68] ) ( mprj la_oenb[68] ) + USE SIGNAL
-      + ROUTED met2 ( 1847130 2380 0 ) ( * 16490 )
-      NEW met2 ( 1745240 1688780 ) ( 1745470 * )
-      NEW met2 ( 1745240 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1745470 16490 ) ( * 1688780 )
-      NEW met1 ( 1745470 16490 ) ( 1847130 * )
-      NEW met1 ( 1745470 16490 ) M1M2_PR
-      NEW met1 ( 1847130 16490 ) M1M2_PR ;
-    - la_oenb[69] ( PIN la_oenb[69] ) ( mprj la_oenb[69] ) + USE SIGNAL
-      + ROUTED met2 ( 1751910 21420 ) ( 1752370 * )
-      NEW met2 ( 1751910 16830 ) ( * 21420 )
-      NEW met2 ( 1864610 2380 0 ) ( * 16830 )
-      NEW met1 ( 1751450 1683510 ) ( 1752370 * )
-      NEW met2 ( 1751450 1683510 ) ( * 1690140 )
-      NEW met2 ( 1750760 1690140 0 ) ( 1751450 * )
-      NEW met2 ( 1752370 21420 ) ( * 1683510 )
-      NEW met1 ( 1751910 16830 ) ( 1864610 * )
-      NEW met1 ( 1751910 16830 ) M1M2_PR
-      NEW met1 ( 1864610 16830 ) M1M2_PR
-      NEW met1 ( 1752370 1683510 ) M1M2_PR
-      NEW met1 ( 1751450 1683510 ) M1M2_PR ;
-    - la_oenb[6] ( PIN la_oenb[6] ) ( mprj la_oenb[6] ) + USE SIGNAL
-      + ROUTED met2 ( 747730 2380 0 ) ( * 3060 )
-      NEW met2 ( 747730 3060 ) ( 748650 * )
-      NEW met2 ( 748650 2380 ) ( * 3060 )
-      NEW met2 ( 748650 2380 ) ( 750030 * )
-      NEW met2 ( 750030 2380 ) ( * 65790 )
-      NEW met1 ( 750030 65790 ) ( 1401390 * )
-      NEW met2 ( 1404610 1690140 ) ( 1405760 * 0 )
-      NEW met1 ( 1401390 1631830 ) ( 1404610 * )
-      NEW met2 ( 1401390 65790 ) ( * 1631830 )
-      NEW met2 ( 1404610 1631830 ) ( * 1690140 )
-      NEW met1 ( 750030 65790 ) M1M2_PR
-      NEW met1 ( 1401390 65790 ) M1M2_PR
-      NEW met1 ( 1401390 1631830 ) M1M2_PR
-      NEW met1 ( 1404610 1631830 ) M1M2_PR ;
-    - la_oenb[70] ( PIN la_oenb[70] ) ( mprj la_oenb[70] ) + USE SIGNAL
-      + ROUTED met1 ( 1757430 1683510 ) ( 1759270 * )
-      NEW met2 ( 1757430 1683510 ) ( * 1690140 )
-      NEW met2 ( 1756280 1690140 0 ) ( 1757430 * )
-      NEW met2 ( 1759270 20230 ) ( * 1683510 )
-      NEW met2 ( 1882550 2380 0 ) ( * 20230 )
-      NEW met1 ( 1759270 20230 ) ( 1882550 * )
-      NEW met1 ( 1759270 20230 ) M1M2_PR
-      NEW met1 ( 1759270 1683510 ) M1M2_PR
-      NEW met1 ( 1757430 1683510 ) M1M2_PR
-      NEW met1 ( 1882550 20230 ) M1M2_PR ;
-    - la_oenb[71] ( PIN la_oenb[71] ) ( mprj la_oenb[71] ) + USE SIGNAL
-      + ROUTED met1 ( 1762950 1678410 ) ( 1766170 * )
-      NEW met2 ( 1762950 1678410 ) ( * 1690140 )
-      NEW met2 ( 1761800 1690140 0 ) ( 1762950 * )
-      NEW met2 ( 1766170 19890 ) ( * 1678410 )
-      NEW met2 ( 1900030 2380 0 ) ( * 19890 )
-      NEW met1 ( 1766170 19890 ) ( 1900030 * )
-      NEW met1 ( 1766170 19890 ) M1M2_PR
-      NEW met1 ( 1766170 1678410 ) M1M2_PR
-      NEW met1 ( 1762950 1678410 ) M1M2_PR
-      NEW met1 ( 1900030 19890 ) M1M2_PR ;
-    - la_oenb[72] ( PIN la_oenb[72] ) ( mprj la_oenb[72] ) + USE SIGNAL
-      + ROUTED met2 ( 1768470 1680110 ) ( * 1690140 )
-      NEW met2 ( 1767320 1690140 0 ) ( 1768470 * )
-      NEW met2 ( 1917970 2380 0 ) ( * 34500 )
-      NEW met2 ( 1912450 34500 ) ( 1917970 * )
-      NEW met1 ( 1768470 1680110 ) ( 1912450 * )
-      NEW met2 ( 1912450 34500 ) ( * 1680110 )
-      NEW met1 ( 1768470 1680110 ) M1M2_PR
-      NEW met1 ( 1912450 1680110 ) M1M2_PR ;
-    - la_oenb[73] ( PIN la_oenb[73] ) ( mprj la_oenb[73] ) + USE SIGNAL
-      + ROUTED met2 ( 1935910 2380 0 ) ( * 19550 )
-      NEW met2 ( 1772840 1688780 ) ( 1773070 * )
-      NEW met2 ( 1772840 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1773070 19550 ) ( * 1688780 )
-      NEW met1 ( 1773070 19550 ) ( 1935910 * )
-      NEW met1 ( 1773070 19550 ) M1M2_PR
-      NEW met1 ( 1935910 19550 ) M1M2_PR ;
-    - la_oenb[74] ( PIN la_oenb[74] ) ( mprj la_oenb[74] ) + USE SIGNAL
-      + ROUTED met2 ( 1953390 2380 0 ) ( * 19210 )
-      NEW met1 ( 1779970 19210 ) ( 1953390 * )
-      NEW met1 ( 1778590 1683510 ) ( 1779970 * )
-      NEW met2 ( 1778590 1683510 ) ( * 1690140 )
-      NEW met2 ( 1777900 1690140 0 ) ( 1778590 * )
-      NEW met2 ( 1779970 19210 ) ( * 1683510 )
-      NEW met1 ( 1953390 19210 ) M1M2_PR
-      NEW met1 ( 1779970 19210 ) M1M2_PR
-      NEW met1 ( 1779970 1683510 ) M1M2_PR
-      NEW met1 ( 1778590 1683510 ) M1M2_PR ;
-    - la_oenb[75] ( PIN la_oenb[75] ) ( mprj la_oenb[75] ) + USE SIGNAL
-      + ROUTED met2 ( 1971330 2380 0 ) ( * 18870 )
-      NEW met1 ( 1785490 18870 ) ( 1971330 * )
-      NEW met2 ( 1785490 18870 ) ( * 1676700 )
-      NEW met2 ( 1784570 1676700 ) ( 1785490 * )
-      NEW met2 ( 1784570 1676700 ) ( * 1690140 )
-      NEW met2 ( 1783420 1690140 0 ) ( 1784570 * )
-      NEW met1 ( 1785490 18870 ) M1M2_PR
-      NEW met1 ( 1971330 18870 ) M1M2_PR ;
-    - la_oenb[76] ( PIN la_oenb[76] ) ( mprj la_oenb[76] ) + USE SIGNAL
-      + ROUTED met2 ( 1988810 2380 0 ) ( * 18530 )
-      NEW met1 ( 1793770 18530 ) ( 1988810 * )
-      NEW met1 ( 1790090 1683170 ) ( 1793770 * )
-      NEW met2 ( 1790090 1683170 ) ( * 1690140 )
-      NEW met2 ( 1788940 1690140 0 ) ( 1790090 * )
-      NEW met2 ( 1793770 18530 ) ( * 1683170 )
-      NEW met1 ( 1793770 18530 ) M1M2_PR
-      NEW met1 ( 1988810 18530 ) M1M2_PR
-      NEW met1 ( 1793770 1683170 ) M1M2_PR
-      NEW met1 ( 1790090 1683170 ) M1M2_PR ;
-    - la_oenb[77] ( PIN la_oenb[77] ) ( mprj la_oenb[77] ) + USE SIGNAL
-      + ROUTED met2 ( 2006750 2380 0 ) ( * 18190 )
-      NEW met1 ( 1800210 18190 ) ( 2006750 * )
-      NEW met1 ( 1795610 1679770 ) ( 1800210 * )
-      NEW met2 ( 1795610 1679770 ) ( * 1690140 )
-      NEW met2 ( 1794460 1690140 0 ) ( 1795610 * )
-      NEW met2 ( 1800210 18190 ) ( * 1679770 )
-      NEW met1 ( 1800210 18190 ) M1M2_PR
-      NEW met1 ( 2006750 18190 ) M1M2_PR
-      NEW met1 ( 1800210 1679770 ) M1M2_PR
-      NEW met1 ( 1795610 1679770 ) M1M2_PR ;
-    - la_oenb[78] ( PIN la_oenb[78] ) ( mprj la_oenb[78] ) + USE SIGNAL
-      + ROUTED met2 ( 2024230 2380 0 ) ( * 17850 )
-      NEW met1 ( 1800670 17850 ) ( 2024230 * )
-      NEW met2 ( 1799980 1690140 0 ) ( 1800670 * )
-      NEW met2 ( 1800670 17850 ) ( * 1690140 )
-      NEW met1 ( 2024230 17850 ) M1M2_PR
-      NEW met1 ( 1800670 17850 ) M1M2_PR ;
-    - la_oenb[79] ( PIN la_oenb[79] ) ( mprj la_oenb[79] ) + USE SIGNAL
-      + ROUTED met2 ( 2042170 2380 0 ) ( * 17510 )
-      NEW met1 ( 1807570 17510 ) ( 2042170 * )
-      NEW met1 ( 1806190 1683170 ) ( 1807570 * )
-      NEW met2 ( 1806190 1683170 ) ( * 1690140 )
-      NEW met2 ( 1805500 1690140 0 ) ( 1806190 * )
-      NEW met2 ( 1807570 17510 ) ( * 1683170 )
-      NEW met1 ( 2042170 17510 ) M1M2_PR
-      NEW met1 ( 1807570 17510 ) M1M2_PR
-      NEW met1 ( 1807570 1683170 ) M1M2_PR
-      NEW met1 ( 1806190 1683170 ) M1M2_PR ;
-    - la_oenb[7] ( PIN la_oenb[7] ) ( mprj la_oenb[7] ) + USE SIGNAL
-      + ROUTED met2 ( 765210 2380 0 ) ( * 34500 )
-      NEW met2 ( 765210 34500 ) ( 765670 * )
-      NEW met2 ( 765670 34500 ) ( * 1654950 )
-      NEW met2 ( 1410130 1690140 ) ( 1411280 * 0 )
-      NEW met1 ( 765670 1654950 ) ( 1410130 * )
-      NEW met2 ( 1410130 1654950 ) ( * 1690140 )
-      NEW met1 ( 765670 1654950 ) M1M2_PR
-      NEW met1 ( 1410130 1654950 ) M1M2_PR ;
-    - la_oenb[80] ( PIN la_oenb[80] ) ( mprj la_oenb[80] ) + USE SIGNAL
-      + ROUTED met2 ( 2059650 2380 0 ) ( * 17170 )
-      NEW met1 ( 1814470 17170 ) ( 2059650 * )
-      NEW met1 ( 1812170 1679770 ) ( 1814470 * )
-      NEW met2 ( 1812170 1679770 ) ( * 1690140 )
-      NEW met2 ( 1811020 1690140 0 ) ( 1812170 * )
-      NEW met2 ( 1814470 17170 ) ( * 1679770 )
-      NEW met1 ( 2059650 17170 ) M1M2_PR
-      NEW met1 ( 1814470 17170 ) M1M2_PR
-      NEW met1 ( 1814470 1679770 ) M1M2_PR
-      NEW met1 ( 1812170 1679770 ) M1M2_PR ;
-    - la_oenb[81] ( PIN la_oenb[81] ) ( mprj la_oenb[81] ) + USE SIGNAL
-      + ROUTED met2 ( 2077590 2380 0 ) ( * 14110 )
-      NEW met1 ( 1821370 14110 ) ( 2077590 * )
-      NEW met1 ( 1817690 1683510 ) ( 1821370 * )
-      NEW met2 ( 1817690 1683510 ) ( * 1690140 )
-      NEW met2 ( 1816540 1690140 0 ) ( 1817690 * )
-      NEW met2 ( 1821370 14110 ) ( * 1683510 )
-      NEW met1 ( 1821370 14110 ) M1M2_PR
-      NEW met1 ( 2077590 14110 ) M1M2_PR
-      NEW met1 ( 1821370 1683510 ) M1M2_PR
-      NEW met1 ( 1817690 1683510 ) M1M2_PR ;
-    - la_oenb[82] ( PIN la_oenb[82] ) ( mprj la_oenb[82] ) + USE SIGNAL
-      + ROUTED li1 ( 1862770 1677730 ) ( * 1679090 )
-      NEW met1 ( 1823210 1679090 ) ( 1862770 * )
-      NEW met2 ( 1823210 1679090 ) ( * 1690140 )
-      NEW met2 ( 1822060 1690140 0 ) ( 1823210 * )
-      NEW met2 ( 2095070 2380 0 ) ( * 3060 )
-      NEW met2 ( 2094150 3060 ) ( 2095070 * )
-      NEW met2 ( 2094150 2380 ) ( * 3060 )
-      NEW met2 ( 2092770 2380 ) ( 2094150 * )
-      NEW met2 ( 2090930 82800 ) ( 2092770 * )
-      NEW met2 ( 2092770 2380 ) ( * 82800 )
-      NEW met1 ( 1862770 1677730 ) ( 2090930 * )
-      NEW met2 ( 2090930 82800 ) ( * 1677730 )
-      NEW li1 ( 1862770 1677730 ) L1M1_PR_MR
-      NEW li1 ( 1862770 1679090 ) L1M1_PR_MR
-      NEW met1 ( 1823210 1679090 ) M1M2_PR
-      NEW met1 ( 2090930 1677730 ) M1M2_PR ;
-    - la_oenb[83] ( PIN la_oenb[83] ) ( mprj la_oenb[83] ) + USE SIGNAL
-      + ROUTED met2 ( 2113010 2380 0 ) ( * 14450 )
-      NEW met2 ( 1827580 1690140 0 ) ( 1828270 * )
-      NEW met1 ( 1828270 14450 ) ( 2113010 * )
-      NEW met2 ( 1828270 14450 ) ( * 1690140 )
-      NEW met1 ( 1828270 14450 ) M1M2_PR
-      NEW met1 ( 2113010 14450 ) M1M2_PR ;
-    - la_oenb[84] ( PIN la_oenb[84] ) ( mprj la_oenb[84] ) + USE SIGNAL
-      + ROUTED met2 ( 2130950 2380 0 ) ( * 3060 )
-      NEW met2 ( 2130030 3060 ) ( 2130950 * )
-      NEW met2 ( 2130030 2380 ) ( * 3060 )
-      NEW met2 ( 2128650 2380 ) ( 2130030 * )
-      NEW met2 ( 1834250 1678410 ) ( * 1690140 )
-      NEW met2 ( 1833100 1690140 0 ) ( 1834250 * )
-      NEW met2 ( 2125430 82800 ) ( 2128650 * )
-      NEW met2 ( 2128650 2380 ) ( * 82800 )
-      NEW met2 ( 2125430 82800 ) ( * 1678410 )
-      NEW met1 ( 1834250 1678410 ) ( 2125430 * )
-      NEW met1 ( 1834250 1678410 ) M1M2_PR
-      NEW met1 ( 2125430 1678410 ) M1M2_PR ;
-    - la_oenb[85] ( PIN la_oenb[85] ) ( mprj la_oenb[85] ) + USE SIGNAL
-      + ROUTED met2 ( 2148430 2380 0 ) ( * 3060 )
-      NEW met2 ( 2147510 3060 ) ( 2148430 * )
-      NEW met2 ( 2147510 2380 ) ( * 3060 )
-      NEW met2 ( 2146130 2380 ) ( 2147510 * )
-      NEW met2 ( 1839310 1682490 ) ( * 1690140 )
-      NEW met2 ( 1838160 1690140 0 ) ( 1839310 * )
-      NEW met2 ( 2146130 2380 ) ( * 1678750 )
-      NEW li1 ( 1894050 1678750 ) ( * 1682490 )
-      NEW met1 ( 1839310 1682490 ) ( 1894050 * )
-      NEW met1 ( 1894050 1678750 ) ( 2146130 * )
-      NEW met1 ( 1839310 1682490 ) M1M2_PR
-      NEW met1 ( 2146130 1678750 ) M1M2_PR
-      NEW li1 ( 1894050 1682490 ) L1M1_PR_MR
-      NEW li1 ( 1894050 1678750 ) L1M1_PR_MR ;
-    - la_oenb[86] ( PIN la_oenb[86] ) ( mprj la_oenb[86] ) + USE SIGNAL
-      + ROUTED met1 ( 1844830 1683170 ) ( 1848970 * )
-      NEW met2 ( 1844830 1683170 ) ( * 1690140 )
-      NEW met2 ( 1843680 1690140 0 ) ( 1844830 * )
-      NEW met2 ( 2166370 2380 0 ) ( * 14790 )
-      NEW met1 ( 1848970 14790 ) ( 2166370 * )
-      NEW met2 ( 1848970 14790 ) ( * 1683170 )
-      NEW met1 ( 1848970 14790 ) M1M2_PR
-      NEW met1 ( 1848970 1683170 ) M1M2_PR
-      NEW met1 ( 1844830 1683170 ) M1M2_PR
-      NEW met1 ( 2166370 14790 ) M1M2_PR ;
-    - la_oenb[87] ( PIN la_oenb[87] ) ( mprj la_oenb[87] ) + USE SIGNAL
-      + ROUTED met2 ( 1849430 1679770 ) ( * 1684020 )
-      NEW met2 ( 1848970 1684020 ) ( 1849430 * )
-      NEW met2 ( 1848970 1684020 ) ( * 1690140 )
-      NEW met2 ( 1848970 1690140 ) ( 1849200 * 0 )
-      NEW met2 ( 2180630 82800 ) ( 2183850 * )
-      NEW met2 ( 2183850 2380 0 ) ( * 82800 )
-      NEW met1 ( 1849430 1679770 ) ( 2180630 * )
-      NEW met2 ( 2180630 82800 ) ( * 1679770 )
-      NEW met1 ( 1849430 1679770 ) M1M2_PR
-      NEW met1 ( 2180630 1679770 ) M1M2_PR ;
-    - la_oenb[88] ( PIN la_oenb[88] ) ( mprj la_oenb[88] ) + USE SIGNAL
-      + ROUTED met2 ( 1854720 1690140 0 ) ( 1855870 * )
-      NEW met2 ( 1855870 15130 ) ( * 1690140 )
-      NEW met2 ( 2201790 2380 0 ) ( * 15130 )
-      NEW met1 ( 1855870 15130 ) ( 2201790 * )
-      NEW met1 ( 1855870 15130 ) M1M2_PR
-      NEW met1 ( 2201790 15130 ) M1M2_PR ;
-    - la_oenb[89] ( PIN la_oenb[89] ) ( mprj la_oenb[89] ) + USE SIGNAL
-      + ROUTED met2 ( 2219270 2380 0 ) ( * 3060 )
-      NEW met2 ( 2218350 3060 ) ( 2219270 * )
-      NEW met2 ( 2218350 2380 ) ( * 3060 )
-      NEW met2 ( 2216970 2380 ) ( 2218350 * )
-      NEW met2 ( 1861390 1683170 ) ( * 1690140 )
-      NEW met2 ( 1860240 1690140 0 ) ( 1861390 * )
-      NEW met2 ( 2215130 82800 ) ( 2216970 * )
-      NEW met2 ( 2216970 2380 ) ( * 82800 )
-      NEW met2 ( 2215130 82800 ) ( * 1683170 )
-      NEW met1 ( 1861390 1683170 ) ( 2215130 * )
-      NEW met1 ( 1861390 1683170 ) M1M2_PR
-      NEW met1 ( 2215130 1683170 ) M1M2_PR ;
-    - la_oenb[8] ( PIN la_oenb[8] ) ( mprj la_oenb[8] ) + USE SIGNAL
-      + ROUTED met2 ( 783150 2380 0 ) ( * 79390 )
-      NEW met1 ( 783150 79390 ) ( 1411050 * )
-      NEW met1 ( 1411050 1682150 ) ( 1416110 * )
-      NEW met2 ( 1416110 1682150 ) ( * 1690140 )
-      NEW met2 ( 1416110 1690140 ) ( 1416340 * 0 )
-      NEW met2 ( 1411050 79390 ) ( * 1682150 )
-      NEW met1 ( 783150 79390 ) M1M2_PR
-      NEW met1 ( 1411050 79390 ) M1M2_PR
-      NEW met1 ( 1411050 1682150 ) M1M2_PR
-      NEW met1 ( 1416110 1682150 ) M1M2_PR ;
-    - la_oenb[90] ( PIN la_oenb[90] ) ( mprj la_oenb[90] ) + USE SIGNAL
-      + ROUTED met2 ( 2237210 2380 0 ) ( * 15470 )
-      NEW met1 ( 1866910 1682830 ) ( 1869670 * )
-      NEW met2 ( 1866910 1682830 ) ( * 1690140 )
-      NEW met2 ( 1865760 1690140 0 ) ( 1866910 * )
-      NEW met2 ( 1869670 15470 ) ( * 1682830 )
-      NEW met1 ( 1869670 15470 ) ( 2237210 * )
-      NEW met1 ( 1869670 15470 ) M1M2_PR
-      NEW met1 ( 2237210 15470 ) M1M2_PR
-      NEW met1 ( 1869670 1682830 ) M1M2_PR
-      NEW met1 ( 1866910 1682830 ) M1M2_PR ;
-    - la_oenb[91] ( PIN la_oenb[91] ) ( mprj la_oenb[91] ) + USE SIGNAL
-      + ROUTED met2 ( 2249630 82800 ) ( 2254690 * )
-      NEW met2 ( 2254690 2380 0 ) ( * 82800 )
-      NEW met2 ( 2249630 82800 ) ( * 1682830 )
-      NEW li1 ( 1911530 1680790 ) ( * 1682830 )
-      NEW met1 ( 1884850 1680790 ) ( 1911530 * )
-      NEW met1 ( 1884850 1680790 ) ( * 1681130 )
-      NEW met1 ( 1872430 1681130 ) ( 1884850 * )
-      NEW met2 ( 1872430 1681130 ) ( * 1690140 )
-      NEW met2 ( 1871280 1690140 0 ) ( 1872430 * )
-      NEW met1 ( 1911530 1682830 ) ( 2249630 * )
-      NEW met1 ( 2249630 1682830 ) M1M2_PR
-      NEW li1 ( 1911530 1682830 ) L1M1_PR_MR
-      NEW li1 ( 1911530 1680790 ) L1M1_PR_MR
-      NEW met1 ( 1872430 1681130 ) M1M2_PR ;
-    - la_oenb[92] ( PIN la_oenb[92] ) ( mprj la_oenb[92] ) + USE SIGNAL
-      + ROUTED met2 ( 1876110 24820 ) ( 1876570 * )
-      NEW met2 ( 1876110 15810 ) ( * 24820 )
-      NEW met2 ( 2272630 2380 0 ) ( * 15810 )
-      NEW met1 ( 1876110 15810 ) ( 2272630 * )
-      NEW met2 ( 1876570 1690140 ) ( 1876800 * 0 )
-      NEW met2 ( 1876570 24820 ) ( * 1690140 )
-      NEW met1 ( 1876110 15810 ) M1M2_PR
-      NEW met1 ( 2272630 15810 ) M1M2_PR ;
-    - la_oenb[93] ( PIN la_oenb[93] ) ( mprj la_oenb[93] ) + USE SIGNAL
-      + ROUTED met2 ( 2290570 2380 0 ) ( * 15810 )
-      NEW met1 ( 2284130 15810 ) ( 2290570 * )
-      NEW li1 ( 1914290 1681470 ) ( * 1682490 )
-      NEW met1 ( 1883010 1681470 ) ( 1914290 * )
-      NEW met2 ( 1883010 1681470 ) ( * 1690140 )
-      NEW met2 ( 1882320 1690140 0 ) ( 1883010 * )
-      NEW met1 ( 1914290 1682490 ) ( 2284130 * )
-      NEW met2 ( 2284130 15810 ) ( * 1682490 )
-      NEW met1 ( 2290570 15810 ) M1M2_PR
-      NEW met1 ( 2284130 15810 ) M1M2_PR
-      NEW li1 ( 1914290 1682490 ) L1M1_PR_MR
-      NEW li1 ( 1914290 1681470 ) L1M1_PR_MR
-      NEW met1 ( 1883010 1681470 ) M1M2_PR
-      NEW met1 ( 2284130 1682490 ) M1M2_PR ;
-    - la_oenb[94] ( PIN la_oenb[94] ) ( mprj la_oenb[94] ) + USE SIGNAL
-      + ROUTED met2 ( 2308050 2380 0 ) ( * 16150 )
-      NEW met1 ( 1888990 16150 ) ( 2308050 * )
-      NEW met2 ( 1887840 1690140 0 ) ( 1888990 * )
-      NEW met2 ( 1888990 16150 ) ( * 1690140 )
-      NEW met1 ( 2308050 16150 ) M1M2_PR
-      NEW met1 ( 1888990 16150 ) M1M2_PR ;
-    - la_oenb[95] ( PIN la_oenb[95] ) ( mprj la_oenb[95] ) + USE SIGNAL
-      + ROUTED li1 ( 1952470 1680450 ) ( * 1682150 )
-      NEW met2 ( 2325530 82800 ) ( 2325990 * )
-      NEW met2 ( 2325990 2380 0 ) ( * 82800 )
-      NEW met2 ( 2325530 82800 ) ( * 1682150 )
-      NEW met2 ( 1894510 1680450 ) ( * 1690140 )
-      NEW met2 ( 1893360 1690140 0 ) ( 1894510 * )
-      NEW met1 ( 1894510 1680450 ) ( 1952470 * )
-      NEW met1 ( 1952470 1682150 ) ( 2325530 * )
-      NEW li1 ( 1952470 1680450 ) L1M1_PR_MR
-      NEW li1 ( 1952470 1682150 ) L1M1_PR_MR
-      NEW met1 ( 2325530 1682150 ) M1M2_PR
-      NEW met1 ( 1894510 1680450 ) M1M2_PR ;
-    - la_oenb[96] ( PIN la_oenb[96] ) ( mprj la_oenb[96] ) + USE SIGNAL
-      + ROUTED met2 ( 2343470 2380 0 ) ( * 16490 )
-      NEW met1 ( 1903250 16490 ) ( 2343470 * )
-      NEW met1 ( 1899570 1682490 ) ( 1903250 * )
-      NEW met2 ( 1899570 1682490 ) ( * 1690140 )
-      NEW met2 ( 1898420 1690140 0 ) ( 1899570 * )
-      NEW met2 ( 1903250 16490 ) ( * 1682490 )
-      NEW met1 ( 2343470 16490 ) M1M2_PR
-      NEW met1 ( 1903250 16490 ) M1M2_PR
-      NEW met1 ( 1903250 1682490 ) M1M2_PR
-      NEW met1 ( 1899570 1682490 ) M1M2_PR ;
-    - la_oenb[97] ( PIN la_oenb[97] ) ( mprj la_oenb[97] ) + USE SIGNAL
-      + ROUTED met2 ( 1904170 1681810 ) ( * 1688780 )
-      NEW met2 ( 1903940 1688780 ) ( 1904170 * )
-      NEW met2 ( 1903940 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 2360030 82800 ) ( 2361410 * )
-      NEW met2 ( 2361410 2380 0 ) ( * 82800 )
-      NEW met1 ( 1904170 1681810 ) ( 2360030 * )
-      NEW met2 ( 2360030 82800 ) ( * 1681810 )
-      NEW met1 ( 1904170 1681810 ) M1M2_PR
-      NEW met1 ( 2360030 1681810 ) M1M2_PR ;
-    - la_oenb[98] ( PIN la_oenb[98] ) ( mprj la_oenb[98] ) + USE SIGNAL
-      + ROUTED met2 ( 2378890 2380 0 ) ( * 16830 )
-      NEW met1 ( 1911070 16830 ) ( 2378890 * )
-      NEW met1 ( 1909230 1682830 ) ( 1911070 * )
-      NEW met2 ( 1909230 1682830 ) ( * 1690140 )
-      NEW met2 ( 1909230 1690140 ) ( 1909460 * 0 )
-      NEW met2 ( 1911070 16830 ) ( * 1682830 )
-      NEW met1 ( 1911070 16830 ) M1M2_PR
-      NEW met1 ( 2378890 16830 ) M1M2_PR
-      NEW met1 ( 1911070 1682830 ) M1M2_PR
-      NEW met1 ( 1909230 1682830 ) M1M2_PR ;
-    - la_oenb[99] ( PIN la_oenb[99] ) ( mprj la_oenb[99] ) + USE SIGNAL
-      + ROUTED met2 ( 2396830 2380 0 ) ( * 3060 )
-      NEW met2 ( 2395910 3060 ) ( 2396830 * )
-      NEW met2 ( 2395910 2380 ) ( * 3060 )
-      NEW met2 ( 2394530 2380 ) ( 2395910 * )
-      NEW met2 ( 1916130 1681130 ) ( * 1690140 )
-      NEW met2 ( 1914980 1690140 0 ) ( 1916130 * )
-      NEW met1 ( 1916130 1681130 ) ( 2394530 * )
-      NEW met2 ( 2394530 2380 ) ( * 1681130 )
-      NEW met1 ( 1916130 1681130 ) M1M2_PR
-      NEW met1 ( 2394530 1681130 ) M1M2_PR ;
-    - la_oenb[9] ( PIN la_oenb[9] ) ( mprj la_oenb[9] ) + USE SIGNAL
-      + ROUTED met1 ( 800630 58310 ) ( 806610 * )
-      NEW met2 ( 800630 2380 0 ) ( * 58310 )
-      NEW met2 ( 806610 58310 ) ( * 86190 )
-      NEW met1 ( 806610 86190 ) ( 1422090 * )
-      NEW met2 ( 1421860 1688780 ) ( 1422090 * )
-      NEW met2 ( 1421860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1422090 86190 ) ( * 1688780 )
-      NEW met1 ( 806610 86190 ) M1M2_PR
-      NEW met1 ( 800630 58310 ) M1M2_PR
-      NEW met1 ( 806610 58310 ) M1M2_PR
-      NEW met1 ( 1422090 86190 ) M1M2_PR ;
-    - user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
-    - user_irq[0] ( PIN user_irq[0] ) ( mprj irq[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2905130 2380 0 ) ( * 18020 )
-      NEW met1 ( 2071610 1651890 ) ( 2076670 * )
-      NEW met3 ( 2076670 18020 ) ( 2905130 * )
-      NEW met2 ( 2076670 18020 ) ( * 1651890 )
-      NEW met2 ( 2070460 1690140 0 ) ( 2071610 * )
-      NEW met2 ( 2071610 1651890 ) ( * 1690140 )
-      NEW met2 ( 2905130 18020 ) M2M3_PR_M
-      NEW met2 ( 2076670 18020 ) M2M3_PR_M
-      NEW met1 ( 2071610 1651890 ) M1M2_PR
-      NEW met1 ( 2076670 1651890 ) M1M2_PR ;
-    - user_irq[1] ( PIN user_irq[1] ) ( mprj irq[1] ) + USE SIGNAL
-      + ROUTED met2 ( 2911110 2380 0 ) ( * 17340 )
-      NEW met1 ( 2073450 1652230 ) ( 2075750 * )
-      NEW met3 ( 2075750 17340 ) ( 2911110 * )
-      NEW met2 ( 2075750 17340 ) ( * 1652230 )
-      NEW met2 ( 2072300 1690140 0 ) ( 2073450 * )
-      NEW met2 ( 2073450 1652230 ) ( * 1690140 )
-      NEW met2 ( 2911110 17340 ) M2M3_PR_M
-      NEW met2 ( 2075750 17340 ) M2M3_PR_M
-      NEW met1 ( 2073450 1652230 ) M1M2_PR
-      NEW met1 ( 2075750 1652230 ) M1M2_PR ;
-    - user_irq[2] ( PIN user_irq[2] ) ( mprj irq[2] ) + USE SIGNAL
-      + ROUTED met2 ( 2917090 2380 0 ) ( * 16660 )
-      NEW met3 ( 2076210 16660 ) ( 2917090 * )
-      NEW met1 ( 2073910 1678070 ) ( 2076210 * )
-      NEW met2 ( 2073910 1678070 ) ( * 1690140 )
-      NEW met2 ( 2073910 1690140 ) ( 2074140 * 0 )
-      NEW met2 ( 2076210 16660 ) ( * 1678070 )
-      NEW met2 ( 2917090 16660 ) M2M3_PR_M
-      NEW met2 ( 2076210 16660 ) M2M3_PR_M
-      NEW met1 ( 2076210 1678070 ) M1M2_PR
-      NEW met1 ( 2073910 1678070 ) M1M2_PR ;
-    - wb_clk_i ( PIN wb_clk_i ) ( mprj wb_clk_i ) + USE SIGNAL
-      + ROUTED met2 ( 2990 2380 0 ) ( * 23970 )
-      NEW met2 ( 1174610 1690140 ) ( 1175760 * 0 )
-      NEW met2 ( 1174610 23970 ) ( * 1690140 )
-      NEW met1 ( 2990 23970 ) ( 1174610 * )
-      NEW met1 ( 2990 23970 ) M1M2_PR
-      NEW met1 ( 1174610 23970 ) M1M2_PR ;
-    - wb_rst_i ( PIN wb_rst_i ) ( mprj wb_rst_i ) + USE SIGNAL
-      + ROUTED met2 ( 8510 2380 0 ) ( * 24310 )
-      NEW met1 ( 1174150 1652230 ) ( 1176450 * )
-      NEW met2 ( 1174150 24310 ) ( * 1652230 )
-      NEW met2 ( 1176450 1690140 ) ( 1177140 * 0 )
-      NEW met2 ( 1176450 1652230 ) ( * 1690140 )
-      NEW met1 ( 8510 24310 ) ( 1174150 * )
-      NEW met1 ( 8510 24310 ) M1M2_PR
-      NEW met1 ( 1174150 24310 ) M1M2_PR
-      NEW met1 ( 1174150 1652230 ) M1M2_PR
-      NEW met1 ( 1176450 1652230 ) M1M2_PR ;
-    - wbs_ack_o ( PIN wbs_ack_o ) ( mprj wbs_ack_o ) + USE SIGNAL
-      + ROUTED met2 ( 14490 2380 0 ) ( * 24650 )
-      NEW met1 ( 1173690 1651890 ) ( 1177830 * )
-      NEW met2 ( 1173690 24650 ) ( * 1651890 )
-      NEW met2 ( 1177830 1690140 ) ( 1178980 * 0 )
-      NEW met2 ( 1177830 1651890 ) ( * 1690140 )
-      NEW met1 ( 14490 24650 ) ( 1173690 * )
-      NEW met1 ( 14490 24650 ) M1M2_PR
-      NEW met1 ( 1173690 24650 ) M1M2_PR
-      NEW met1 ( 1173690 1651890 ) M1M2_PR
-      NEW met1 ( 1177830 1651890 ) M1M2_PR ;
-    - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj wbs_adr_i[0] ) + USE SIGNAL
-      + ROUTED met1 ( 1180590 1652230 ) ( 1185190 * )
-      NEW met2 ( 1180590 24990 ) ( * 1652230 )
-      NEW met2 ( 1185190 1690140 ) ( 1186340 * 0 )
-      NEW met2 ( 1185190 1652230 ) ( * 1690140 )
-      NEW met2 ( 38410 2380 0 ) ( * 24990 )
-      NEW met1 ( 38410 24990 ) ( 1180590 * )
-      NEW met1 ( 1180590 24990 ) M1M2_PR
-      NEW met1 ( 1180590 1652230 ) M1M2_PR
-      NEW met1 ( 1185190 1652230 ) M1M2_PR
-      NEW met1 ( 38410 24990 ) M1M2_PR ;
-    - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ( mprj wbs_adr_i[10] ) + USE SIGNAL
-      + ROUTED met1 ( 1242690 1652570 ) ( 1247290 * )
-      NEW met2 ( 1242690 30770 ) ( * 1652570 )
-      NEW met2 ( 1247290 1690140 ) ( 1248440 * 0 )
-      NEW met2 ( 1247290 1652570 ) ( * 1690140 )
-      NEW met2 ( 239430 2380 0 ) ( * 30770 )
-      NEW met1 ( 239430 30770 ) ( 1242690 * )
-      NEW met1 ( 1242690 30770 ) M1M2_PR
-      NEW met1 ( 1242690 1652570 ) M1M2_PR
-      NEW met1 ( 1247290 1652570 ) M1M2_PR
-      NEW met1 ( 239430 30770 ) M1M2_PR ;
-    - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ( mprj wbs_adr_i[11] ) + USE SIGNAL
-      + ROUTED met2 ( 1250510 31110 ) ( * 1580100 )
-      NEW met2 ( 1250510 1580100 ) ( 1252810 * )
-      NEW met2 ( 1252810 1690140 ) ( 1253960 * 0 )
-      NEW met2 ( 1252810 1580100 ) ( * 1690140 )
-      NEW met2 ( 256910 2380 0 ) ( * 31110 )
-      NEW met1 ( 256910 31110 ) ( 1250510 * )
-      NEW met1 ( 1250510 31110 ) M1M2_PR
-      NEW met1 ( 256910 31110 ) M1M2_PR ;
-    - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ( mprj wbs_adr_i[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1256950 31450 ) ( * 1580100 )
-      NEW met2 ( 1256950 1580100 ) ( 1258330 * )
-      NEW met2 ( 1258330 1690140 ) ( 1259480 * 0 )
-      NEW met2 ( 1258330 1580100 ) ( * 1690140 )
-      NEW met2 ( 274850 2380 0 ) ( * 31450 )
-      NEW met1 ( 274850 31450 ) ( 1256950 * )
-      NEW met1 ( 1256950 31450 ) M1M2_PR
-      NEW met1 ( 274850 31450 ) M1M2_PR ;
-    - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ( mprj wbs_adr_i[13] ) + USE SIGNAL
-      + ROUTED met2 ( 292330 2380 0 ) ( * 31790 )
-      NEW met2 ( 1264310 1690140 ) ( 1265000 * 0 )
-      NEW met2 ( 1264310 31790 ) ( * 1690140 )
-      NEW met1 ( 292330 31790 ) ( 1264310 * )
-      NEW met1 ( 292330 31790 ) M1M2_PR
-      NEW met1 ( 1264310 31790 ) M1M2_PR ;
-    - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ( mprj wbs_adr_i[14] ) + USE SIGNAL
-      + ROUTED met2 ( 310270 2380 0 ) ( * 32130 )
-      NEW met2 ( 1270290 1690140 ) ( 1270520 * 0 )
-      NEW met2 ( 1270290 32130 ) ( * 1690140 )
-      NEW met1 ( 310270 32130 ) ( 1270290 * )
-      NEW met1 ( 310270 32130 ) M1M2_PR
-      NEW met1 ( 1270290 32130 ) M1M2_PR ;
-    - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ( mprj wbs_adr_i[15] ) + USE SIGNAL
-      + ROUTED met1 ( 1270750 1652570 ) ( 1274890 * )
-      NEW met2 ( 1270750 32470 ) ( * 1652570 )
-      NEW met2 ( 1274890 1690140 ) ( 1276040 * 0 )
-      NEW met2 ( 1274890 1652570 ) ( * 1690140 )
-      NEW met2 ( 327750 2380 0 ) ( * 32470 )
-      NEW met1 ( 327750 32470 ) ( 1270750 * )
-      NEW met1 ( 1270750 32470 ) M1M2_PR
-      NEW met1 ( 1270750 1652570 ) M1M2_PR
-      NEW met1 ( 1274890 1652570 ) M1M2_PR
-      NEW met1 ( 327750 32470 ) M1M2_PR ;
-    - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ( mprj wbs_adr_i[16] ) + USE SIGNAL
-      + ROUTED met1 ( 1277190 1652230 ) ( 1280410 * )
-      NEW met2 ( 1277190 32810 ) ( * 1652230 )
-      NEW met2 ( 1280410 1690140 ) ( 1281560 * 0 )
-      NEW met2 ( 1280410 1652230 ) ( * 1690140 )
-      NEW met2 ( 345690 2380 0 ) ( * 32810 )
-      NEW met1 ( 345690 32810 ) ( 1277190 * )
-      NEW met1 ( 1277190 32810 ) M1M2_PR
-      NEW met1 ( 1277190 1652230 ) M1M2_PR
-      NEW met1 ( 1280410 1652230 ) M1M2_PR
-      NEW met1 ( 345690 32810 ) M1M2_PR ;
-    - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ( mprj wbs_adr_i[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1284090 39950 ) ( * 1676700 )
-      NEW met2 ( 1284090 1676700 ) ( 1285930 * )
-      NEW met2 ( 1285930 1676700 ) ( * 1690140 )
-      NEW met2 ( 1285930 1690140 ) ( 1287080 * 0 )
-      NEW met2 ( 363170 2380 0 ) ( * 39950 )
-      NEW met1 ( 363170 39950 ) ( 1284090 * )
-      NEW met1 ( 1284090 39950 ) M1M2_PR
-      NEW met1 ( 363170 39950 ) M1M2_PR ;
-    - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ( mprj wbs_adr_i[18] ) + USE SIGNAL
-      + ROUTED met2 ( 381110 2380 0 ) ( * 40290 )
-      NEW met1 ( 1290990 40290 ) ( * 40630 )
-      NEW met1 ( 1290990 40630 ) ( 1291910 * )
-      NEW met2 ( 1291910 40630 ) ( * 41140 )
-      NEW met2 ( 1291450 41140 ) ( 1291910 * )
-      NEW met1 ( 381110 40290 ) ( 1290990 * )
-      NEW met2 ( 1291450 1690140 ) ( 1292600 * 0 )
-      NEW met2 ( 1291450 41140 ) ( * 1690140 )
-      NEW met1 ( 381110 40290 ) M1M2_PR
-      NEW met1 ( 1291910 40630 ) M1M2_PR ;
-    - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ( mprj wbs_adr_i[19] ) + USE SIGNAL
-      + ROUTED met2 ( 398590 2380 0 ) ( * 40630 )
-      NEW li1 ( 1290530 40630 ) ( 1292370 * )
-      NEW met1 ( 1292370 40630 ) ( 1297890 * )
-      NEW met1 ( 398590 40630 ) ( 1290530 * )
-      NEW met2 ( 1297660 1688780 ) ( 1297890 * )
-      NEW met2 ( 1297660 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1297890 40630 ) ( * 1688780 )
-      NEW met1 ( 398590 40630 ) M1M2_PR
-      NEW li1 ( 1290530 40630 ) L1M1_PR_MR
-      NEW li1 ( 1292370 40630 ) L1M1_PR_MR
-      NEW met1 ( 1297890 40630 ) M1M2_PR ;
-    - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj wbs_adr_i[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1187950 38250 ) ( * 1580100 )
-      NEW met2 ( 1187950 1580100 ) ( 1192550 * )
-      NEW met2 ( 1192550 1580100 ) ( * 1690140 )
-      NEW met2 ( 61870 2380 0 ) ( * 38250 )
-      NEW met1 ( 61870 38250 ) ( 1187950 * )
-      NEW met2 ( 1192550 1690140 ) ( 1193700 * 0 )
-      NEW met1 ( 1187950 38250 ) M1M2_PR
-      NEW met1 ( 61870 38250 ) M1M2_PR ;
-    - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ( mprj wbs_adr_i[20] ) + USE SIGNAL
-      + ROUTED met2 ( 416530 2380 0 ) ( * 16830 )
-      NEW met1 ( 416530 16830 ) ( 420670 * )
-      NEW met2 ( 420670 16830 ) ( * 1660050 )
-      NEW met1 ( 420670 1660050 ) ( 1302030 * )
-      NEW met2 ( 1302030 1690140 ) ( 1303180 * 0 )
-      NEW met2 ( 1302030 1660050 ) ( * 1690140 )
-      NEW met1 ( 416530 16830 ) M1M2_PR
-      NEW met1 ( 420670 16830 ) M1M2_PR
-      NEW met1 ( 420670 1660050 ) M1M2_PR
-      NEW met1 ( 1302030 1660050 ) M1M2_PR ;
-    - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ( mprj wbs_adr_i[21] ) + USE SIGNAL
-      + ROUTED met1 ( 434470 1673990 ) ( 1297430 * )
-      NEW met2 ( 434470 2380 0 ) ( * 1673990 )
-      NEW met1 ( 1297430 1680790 ) ( 1307550 * )
-      NEW met2 ( 1307550 1680790 ) ( * 1690140 )
-      NEW met2 ( 1307550 1690140 ) ( 1308700 * 0 )
-      NEW met2 ( 1297430 1673990 ) ( * 1680790 )
-      NEW met1 ( 434470 1673990 ) M1M2_PR
-      NEW met1 ( 1297430 1673990 ) M1M2_PR
-      NEW met1 ( 1297430 1680790 ) M1M2_PR
-      NEW met1 ( 1307550 1680790 ) M1M2_PR ;
-    - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ( mprj wbs_adr_i[22] ) + USE SIGNAL
-      + ROUTED met2 ( 451950 2380 0 ) ( * 16830 )
-      NEW met1 ( 451950 16830 ) ( 455170 * )
-      NEW met2 ( 455170 16830 ) ( * 54570 )
-      NEW met1 ( 455170 54570 ) ( 1312150 * )
-      NEW met2 ( 1312150 54570 ) ( * 1676700 )
-      NEW met2 ( 1312150 1676700 ) ( 1313070 * )
-      NEW met2 ( 1313070 1676700 ) ( * 1690140 )
-      NEW met2 ( 1313070 1690140 ) ( 1314220 * 0 )
-      NEW met1 ( 451950 16830 ) M1M2_PR
-      NEW met1 ( 455170 16830 ) M1M2_PR
-      NEW met1 ( 455170 54570 ) M1M2_PR
-      NEW met1 ( 1312150 54570 ) M1M2_PR ;
-    - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ( mprj wbs_adr_i[23] ) + USE SIGNAL
-      + ROUTED met2 ( 469890 2380 0 ) ( * 15810 )
-      NEW met1 ( 469890 15810 ) ( 475410 * )
-      NEW met2 ( 475410 15810 ) ( * 54910 )
-      NEW met1 ( 475410 54910 ) ( 1318590 * )
-      NEW met2 ( 1318590 1690140 ) ( 1319740 * 0 )
-      NEW met2 ( 1318590 54910 ) ( * 1690140 )
-      NEW met1 ( 469890 15810 ) M1M2_PR
-      NEW met1 ( 475410 15810 ) M1M2_PR
-      NEW met1 ( 475410 54910 ) M1M2_PR
-      NEW met1 ( 1318590 54910 ) M1M2_PR ;
-    - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ( mprj wbs_adr_i[24] ) + USE SIGNAL
-      + ROUTED met2 ( 487370 2380 0 ) ( * 16490 )
-      NEW met1 ( 487370 16490 ) ( 489670 * )
-      NEW met2 ( 489670 16490 ) ( * 51170 )
-      NEW met1 ( 489670 51170 ) ( 1325950 * )
-      NEW met2 ( 1325260 1690140 0 ) ( 1325950 * )
-      NEW met2 ( 1325950 51170 ) ( * 1690140 )
-      NEW met1 ( 487370 16490 ) M1M2_PR
-      NEW met1 ( 489670 16490 ) M1M2_PR
-      NEW met1 ( 489670 51170 ) M1M2_PR
-      NEW met1 ( 1325950 51170 ) M1M2_PR ;
-    - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ( mprj wbs_adr_i[25] ) + USE SIGNAL
-      + ROUTED met2 ( 505310 2380 0 ) ( * 16490 )
-      NEW met1 ( 505310 16490 ) ( 510370 * )
-      NEW met2 ( 510370 16490 ) ( * 50830 )
-      NEW met1 ( 1325490 1646450 ) ( 1329630 * )
-      NEW met1 ( 510370 50830 ) ( 1325490 * )
-      NEW met2 ( 1325490 50830 ) ( * 1646450 )
-      NEW met2 ( 1329630 1690140 ) ( 1330780 * 0 )
-      NEW met2 ( 1329630 1646450 ) ( * 1690140 )
-      NEW met1 ( 505310 16490 ) M1M2_PR
-      NEW met1 ( 510370 16490 ) M1M2_PR
-      NEW met1 ( 510370 50830 ) M1M2_PR
-      NEW met1 ( 1325490 1646450 ) M1M2_PR
-      NEW met1 ( 1329630 1646450 ) M1M2_PR
-      NEW met1 ( 1325490 50830 ) M1M2_PR ;
-    - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ( mprj wbs_adr_i[26] ) + USE SIGNAL
-      + ROUTED met1 ( 1332390 1652570 ) ( 1335150 * )
-      NEW met2 ( 522790 2380 0 ) ( * 50490 )
-      NEW met1 ( 522790 50490 ) ( 1332390 * )
-      NEW met2 ( 1332390 50490 ) ( * 1652570 )
-      NEW met2 ( 1335150 1690140 ) ( 1336300 * 0 )
-      NEW met2 ( 1335150 1652570 ) ( * 1690140 )
-      NEW met1 ( 1332390 1652570 ) M1M2_PR
-      NEW met1 ( 1335150 1652570 ) M1M2_PR
-      NEW met1 ( 522790 50490 ) M1M2_PR
-      NEW met1 ( 1332390 50490 ) M1M2_PR ;
-    - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ( mprj wbs_adr_i[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1339290 50150 ) ( * 1676700 )
-      NEW met2 ( 1339290 1676700 ) ( 1340670 * )
-      NEW met2 ( 1340670 1676700 ) ( * 1690140 )
-      NEW met2 ( 1340670 1690140 ) ( 1341820 * 0 )
-      NEW met2 ( 540730 2380 0 ) ( * 15470 )
-      NEW met1 ( 540730 15470 ) ( 544870 * )
-      NEW met2 ( 544870 15470 ) ( * 50150 )
-      NEW met1 ( 544870 50150 ) ( 1339290 * )
-      NEW met1 ( 1339290 50150 ) M1M2_PR
-      NEW met1 ( 540730 15470 ) M1M2_PR
-      NEW met1 ( 544870 15470 ) M1M2_PR
-      NEW met1 ( 544870 50150 ) M1M2_PR ;
-    - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ( mprj wbs_adr_i[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1346650 1690140 ) ( 1347340 * 0 )
-      NEW met2 ( 1346650 49810 ) ( * 1690140 )
-      NEW met2 ( 558210 2380 0 ) ( * 49810 )
-      NEW met1 ( 558210 49810 ) ( 1346650 * )
-      NEW met1 ( 1346650 49810 ) M1M2_PR
-      NEW met1 ( 558210 49810 ) M1M2_PR ;
-    - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ( mprj wbs_adr_i[29] ) + USE SIGNAL
-      + ROUTED met2 ( 576150 2380 0 ) ( * 14450 )
-      NEW met1 ( 576150 14450 ) ( 579370 * )
-      NEW met2 ( 579370 14450 ) ( * 49470 )
-      NEW met2 ( 1352860 1688780 ) ( 1353090 * )
-      NEW met2 ( 1352860 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1353090 49470 ) ( * 1688780 )
-      NEW met1 ( 579370 49470 ) ( 1353090 * )
-      NEW met1 ( 576150 14450 ) M1M2_PR
-      NEW met1 ( 579370 14450 ) M1M2_PR
-      NEW met1 ( 579370 49470 ) M1M2_PR
-      NEW met1 ( 1353090 49470 ) M1M2_PR ;
-    - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj wbs_adr_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 85330 2380 0 ) ( * 38590 )
-      NEW met1 ( 85330 38590 ) ( 1200830 * )
-      NEW met2 ( 1200830 1690140 ) ( 1201060 * 0 )
-      NEW met2 ( 1200830 38590 ) ( * 1690140 )
-      NEW met1 ( 85330 38590 ) M1M2_PR
-      NEW met1 ( 1200830 38590 ) M1M2_PR ;
-    - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ( mprj wbs_adr_i[30] ) + USE SIGNAL
-      + ROUTED met2 ( 594090 2380 0 ) ( * 14450 )
-      NEW met1 ( 594090 14450 ) ( 599150 * )
-      NEW met1 ( 1353550 1652570 ) ( 1356770 * )
-      NEW met2 ( 599150 14450 ) ( * 49130 )
-      NEW met2 ( 1353550 49130 ) ( * 1652570 )
-      NEW met2 ( 1356770 1690140 ) ( 1357920 * 0 )
-      NEW met2 ( 1356770 1652570 ) ( * 1690140 )
-      NEW met1 ( 599150 49130 ) ( 1353550 * )
-      NEW met1 ( 594090 14450 ) M1M2_PR
-      NEW met1 ( 599150 14450 ) M1M2_PR
-      NEW met1 ( 1353550 1652570 ) M1M2_PR
-      NEW met1 ( 1356770 1652570 ) M1M2_PR
-      NEW met1 ( 599150 49130 ) M1M2_PR
-      NEW met1 ( 1353550 49130 ) M1M2_PR ;
-    - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ( mprj wbs_adr_i[31] ) + USE SIGNAL
-      + ROUTED met2 ( 611570 2380 0 ) ( * 3060 )
-      NEW met2 ( 611570 3060 ) ( 612490 * )
-      NEW met2 ( 612490 2380 ) ( * 3060 )
-      NEW met2 ( 612490 2380 ) ( 613870 * )
-      NEW met1 ( 1359990 1652570 ) ( 1362290 * )
-      NEW met2 ( 613870 2380 ) ( * 48790 )
-      NEW met2 ( 1359990 48790 ) ( * 1652570 )
-      NEW met2 ( 1362290 1690140 ) ( 1363440 * 0 )
-      NEW met2 ( 1362290 1652570 ) ( * 1690140 )
-      NEW met1 ( 613870 48790 ) ( 1359990 * )
-      NEW met1 ( 1359990 1652570 ) M1M2_PR
-      NEW met1 ( 1362290 1652570 ) M1M2_PR
-      NEW met1 ( 613870 48790 ) M1M2_PR
-      NEW met1 ( 1359990 48790 ) M1M2_PR ;
-    - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj wbs_adr_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 109250 2380 0 ) ( * 38930 )
-      NEW met2 ( 1209110 38930 ) ( * 42500 )
-      NEW met2 ( 1208650 42500 ) ( 1209110 * )
-      NEW met1 ( 109250 38930 ) ( 1209110 * )
-      NEW met2 ( 1208420 1688780 ) ( 1208650 * )
-      NEW met2 ( 1208420 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1208650 42500 ) ( * 1688780 )
-      NEW met1 ( 109250 38930 ) M1M2_PR
-      NEW met1 ( 1209110 38930 ) M1M2_PR ;
-    - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj wbs_adr_i[4] ) + USE SIGNAL
-      + ROUTED met2 ( 132710 2380 0 ) ( * 39270 )
-      NEW met1 ( 132710 39270 ) ( 1215550 * )
-      NEW met2 ( 1215550 1690140 ) ( 1215780 * 0 )
-      NEW met2 ( 1215550 39270 ) ( * 1690140 )
-      NEW met1 ( 132710 39270 ) M1M2_PR
-      NEW met1 ( 1215550 39270 ) M1M2_PR ;
-    - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj wbs_adr_i[5] ) + USE SIGNAL
-      + ROUTED met1 ( 1215090 1652570 ) ( 1220150 * )
-      NEW met2 ( 150650 2380 0 ) ( * 39610 )
-      NEW met1 ( 150650 39610 ) ( 1215090 * )
-      NEW met2 ( 1215090 39610 ) ( * 1652570 )
-      NEW met2 ( 1220150 1690140 ) ( 1221300 * 0 )
-      NEW met2 ( 1220150 1652570 ) ( * 1690140 )
-      NEW met1 ( 1215090 1652570 ) M1M2_PR
-      NEW met1 ( 1220150 1652570 ) M1M2_PR
-      NEW met1 ( 150650 39610 ) M1M2_PR
-      NEW met1 ( 1215090 39610 ) M1M2_PR ;
-    - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj wbs_adr_i[6] ) + USE SIGNAL
-      + ROUTED met1 ( 1221990 1652570 ) ( 1225670 * )
-      NEW met2 ( 168130 2380 0 ) ( * 45050 )
-      NEW met1 ( 168130 45050 ) ( 1221990 * )
-      NEW met2 ( 1221990 45050 ) ( * 1652570 )
-      NEW met2 ( 1225670 1690140 ) ( 1226820 * 0 )
-      NEW met2 ( 1225670 1652570 ) ( * 1690140 )
-      NEW met1 ( 1221990 1652570 ) M1M2_PR
-      NEW met1 ( 1225670 1652570 ) M1M2_PR
-      NEW met1 ( 168130 45050 ) M1M2_PR
-      NEW met1 ( 1221990 45050 ) M1M2_PR ;
-    - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj wbs_adr_i[7] ) + USE SIGNAL
-      + ROUTED met2 ( 186070 2380 0 ) ( * 45390 )
-      NEW met1 ( 186070 45390 ) ( 1229810 * )
-      NEW met2 ( 1229810 45390 ) ( * 1580100 )
-      NEW met2 ( 1229810 1580100 ) ( 1231190 * )
-      NEW met2 ( 1231190 1690140 ) ( 1232340 * 0 )
-      NEW met2 ( 1231190 1580100 ) ( * 1690140 )
-      NEW met1 ( 186070 45390 ) M1M2_PR
-      NEW met1 ( 1229810 45390 ) M1M2_PR ;
-    - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ( mprj wbs_adr_i[8] ) + USE SIGNAL
-      + ROUTED met2 ( 203550 2380 0 ) ( * 17850 )
-      NEW met1 ( 203550 17850 ) ( 206770 * )
-      NEW met2 ( 206770 17850 ) ( * 51510 )
-      NEW met1 ( 206770 51510 ) ( 1236250 * )
-      NEW met2 ( 1236250 1690140 ) ( 1237400 * 0 )
-      NEW met2 ( 1236250 51510 ) ( * 1690140 )
-      NEW met1 ( 203550 17850 ) M1M2_PR
-      NEW met1 ( 206770 17850 ) M1M2_PR
-      NEW met1 ( 206770 51510 ) M1M2_PR
-      NEW met1 ( 1236250 51510 ) M1M2_PR ;
-    - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ( mprj wbs_adr_i[9] ) + USE SIGNAL
-      + ROUTED met2 ( 221490 2380 0 ) ( * 16830 )
-      NEW met1 ( 221490 16830 ) ( 227470 * )
-      NEW met2 ( 227470 16830 ) ( * 51850 )
-      NEW met2 ( 1242920 1688780 ) ( 1243150 * )
-      NEW met2 ( 1242920 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1243150 51850 ) ( * 1688780 )
-      NEW met1 ( 227470 51850 ) ( 1243150 * )
-      NEW met1 ( 221490 16830 ) M1M2_PR
-      NEW met1 ( 227470 16830 ) M1M2_PR
-      NEW met1 ( 227470 51850 ) M1M2_PR
-      NEW met1 ( 1243150 51850 ) M1M2_PR ;
-    - wbs_cyc_i ( PIN wbs_cyc_i ) ( mprj wbs_cyc_i ) + USE SIGNAL
-      + ROUTED met2 ( 20470 2380 0 ) ( * 37910 )
-      NEW met2 ( 1180820 1688780 ) ( 1181050 * )
-      NEW met2 ( 1180820 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1181050 37910 ) ( * 1688780 )
-      NEW met1 ( 20470 37910 ) ( 1181050 * )
-      NEW met1 ( 20470 37910 ) M1M2_PR
-      NEW met1 ( 1181050 37910 ) M1M2_PR ;
-    - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mprj wbs_dat_i[0] ) + USE SIGNAL
-      + ROUTED met2 ( 1187490 1690140 ) ( 1188180 * 0 )
-      NEW met2 ( 1187490 44710 ) ( * 1690140 )
-      NEW met2 ( 43930 2380 0 ) ( * 44710 )
-      NEW met1 ( 43930 44710 ) ( 1187490 * )
-      NEW met1 ( 1187490 44710 ) M1M2_PR
-      NEW met1 ( 43930 44710 ) M1M2_PR ;
-    - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mprj wbs_dat_i[10] ) + USE SIGNAL
-      + ROUTED met2 ( 1250050 1690140 ) ( 1250280 * 0 )
-      NEW met2 ( 1250050 52190 ) ( * 1690140 )
-      NEW met2 ( 244950 2380 0 ) ( * 14450 )
-      NEW met1 ( 244950 14450 ) ( 248170 * )
-      NEW met2 ( 248170 14450 ) ( * 52190 )
-      NEW met1 ( 248170 52190 ) ( 1250050 * )
-      NEW met1 ( 1250050 52190 ) M1M2_PR
-      NEW met1 ( 244950 14450 ) M1M2_PR
-      NEW met1 ( 248170 14450 ) M1M2_PR
-      NEW met1 ( 248170 52190 ) M1M2_PR ;
-    - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mprj wbs_dat_i[11] ) + USE SIGNAL
-      + ROUTED met1 ( 1249590 1652570 ) ( 1254650 * )
-      NEW met2 ( 1249590 52530 ) ( * 1652570 )
-      NEW met2 ( 1254650 1690140 ) ( 1255800 * 0 )
-      NEW met2 ( 1254650 1652570 ) ( * 1690140 )
-      NEW met2 ( 262890 2380 0 ) ( * 16830 )
-      NEW met1 ( 262890 16830 ) ( 268870 * )
-      NEW met2 ( 268870 16830 ) ( * 52530 )
-      NEW met1 ( 268870 52530 ) ( 1249590 * )
-      NEW met1 ( 1249590 1652570 ) M1M2_PR
-      NEW met1 ( 1254650 1652570 ) M1M2_PR
-      NEW met1 ( 1249590 52530 ) M1M2_PR
-      NEW met1 ( 262890 16830 ) M1M2_PR
-      NEW met1 ( 268870 16830 ) M1M2_PR
-      NEW met1 ( 268870 52530 ) M1M2_PR ;
-    - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mprj wbs_dat_i[12] ) + USE SIGNAL
-      + ROUTED met2 ( 280370 2380 0 ) ( * 16830 )
-      NEW met1 ( 280370 16830 ) ( 282670 * )
-      NEW met1 ( 1256490 1652570 ) ( 1260170 * )
-      NEW met2 ( 282670 16830 ) ( * 52870 )
-      NEW met2 ( 1256490 52870 ) ( * 1652570 )
-      NEW met2 ( 1260170 1690140 ) ( 1261320 * 0 )
-      NEW met2 ( 1260170 1652570 ) ( * 1690140 )
-      NEW met1 ( 282670 52870 ) ( 1256490 * )
-      NEW met1 ( 280370 16830 ) M1M2_PR
-      NEW met1 ( 282670 16830 ) M1M2_PR
-      NEW met1 ( 1256490 1652570 ) M1M2_PR
-      NEW met1 ( 1260170 1652570 ) M1M2_PR
-      NEW met1 ( 282670 52870 ) M1M2_PR
-      NEW met1 ( 1256490 52870 ) M1M2_PR ;
-    - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mprj wbs_dat_i[13] ) + USE SIGNAL
-      + ROUTED met2 ( 298310 2380 0 ) ( * 16830 )
-      NEW met1 ( 298310 16830 ) ( 303370 * )
-      NEW met1 ( 1263390 1652570 ) ( 1265690 * )
-      NEW met2 ( 303370 16830 ) ( * 53210 )
-      NEW met2 ( 1263390 53210 ) ( * 1652570 )
-      NEW met2 ( 1265690 1690140 ) ( 1266840 * 0 )
-      NEW met2 ( 1265690 1652570 ) ( * 1690140 )
-      NEW met1 ( 303370 53210 ) ( 1263390 * )
-      NEW met1 ( 298310 16830 ) M1M2_PR
-      NEW met1 ( 303370 16830 ) M1M2_PR
-      NEW met1 ( 1263390 1652570 ) M1M2_PR
-      NEW met1 ( 1265690 1652570 ) M1M2_PR
-      NEW met1 ( 303370 53210 ) M1M2_PR
-      NEW met1 ( 1263390 53210 ) M1M2_PR ;
-    - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mprj wbs_dat_i[14] ) + USE SIGNAL
-      + ROUTED met2 ( 316250 2380 0 ) ( * 53550 )
-      NEW met2 ( 1271210 1690140 ) ( 1272360 * 0 )
-      NEW met2 ( 1271210 53550 ) ( * 1690140 )
-      NEW met1 ( 316250 53550 ) ( 1271210 * )
-      NEW met1 ( 316250 53550 ) M1M2_PR
-      NEW met1 ( 1271210 53550 ) M1M2_PR ;
-    - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mprj wbs_dat_i[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1277650 1690140 ) ( 1277880 * 0 )
-      NEW met2 ( 1277650 53890 ) ( * 1690140 )
-      NEW met2 ( 333730 2380 0 ) ( * 16830 )
-      NEW met1 ( 333730 16830 ) ( 337870 * )
-      NEW met2 ( 337870 16830 ) ( * 53890 )
-      NEW met1 ( 337870 53890 ) ( 1277650 * )
-      NEW met1 ( 1277650 53890 ) M1M2_PR
-      NEW met1 ( 333730 16830 ) M1M2_PR
-      NEW met1 ( 337870 16830 ) M1M2_PR
-      NEW met1 ( 337870 53890 ) M1M2_PR ;
-    - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mprj wbs_dat_i[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1278110 54230 ) ( * 1580100 )
-      NEW met2 ( 1278110 1580100 ) ( 1282250 * )
-      NEW met2 ( 1282250 1690140 ) ( 1283400 * 0 )
-      NEW met2 ( 1282250 1580100 ) ( * 1690140 )
-      NEW met2 ( 351670 2380 0 ) ( * 54230 )
-      NEW met1 ( 351670 54230 ) ( 1278110 * )
-      NEW met1 ( 1278110 54230 ) M1M2_PR
-      NEW met1 ( 351670 54230 ) M1M2_PR ;
-    - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mprj wbs_dat_i[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1284550 58650 ) ( * 1580100 )
-      NEW met2 ( 1284550 1580100 ) ( 1287770 * )
-      NEW met2 ( 1287770 1690140 ) ( 1288920 * 0 )
-      NEW met2 ( 1287770 1580100 ) ( * 1690140 )
-      NEW met2 ( 369150 2380 0 ) ( * 15130 )
-      NEW met1 ( 369150 15130 ) ( 372370 * )
-      NEW met2 ( 372370 15130 ) ( * 58650 )
-      NEW met1 ( 372370 58650 ) ( 1284550 * )
-      NEW met1 ( 1284550 58650 ) M1M2_PR
-      NEW met1 ( 369150 15130 ) M1M2_PR
-      NEW met1 ( 372370 15130 ) M1M2_PR
-      NEW met1 ( 372370 58650 ) M1M2_PR ;
-    - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mprj wbs_dat_i[18] ) + USE SIGNAL
-      + ROUTED met2 ( 387090 2380 0 ) ( * 16830 )
-      NEW met1 ( 387090 16830 ) ( 393070 * )
-      NEW met2 ( 393070 16830 ) ( * 58990 )
-      NEW met1 ( 393070 58990 ) ( 1291910 * )
-      NEW met2 ( 1291910 58990 ) ( * 1580100 )
-      NEW met2 ( 1291910 1580100 ) ( 1293290 * )
-      NEW met2 ( 1293290 1690140 ) ( 1294440 * 0 )
-      NEW met2 ( 1293290 1580100 ) ( * 1690140 )
-      NEW met1 ( 387090 16830 ) M1M2_PR
-      NEW met1 ( 393070 16830 ) M1M2_PR
-      NEW met1 ( 393070 58990 ) M1M2_PR
-      NEW met1 ( 1291910 58990 ) M1M2_PR ;
-    - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mprj wbs_dat_i[19] ) + USE SIGNAL
-      + ROUTED met2 ( 404570 2380 0 ) ( * 16830 )
-      NEW met1 ( 404570 16830 ) ( 406870 * )
-      NEW met2 ( 406870 16830 ) ( * 1653250 )
-      NEW met1 ( 406870 1653250 ) ( 1298350 * )
-      NEW met2 ( 1298350 1690140 ) ( 1299500 * 0 )
-      NEW met2 ( 1298350 1653250 ) ( * 1690140 )
-      NEW met1 ( 404570 16830 ) M1M2_PR
-      NEW met1 ( 406870 16830 ) M1M2_PR
-      NEW met1 ( 406870 1653250 ) M1M2_PR
-      NEW met1 ( 1298350 1653250 ) M1M2_PR ;
-    - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mprj wbs_dat_i[1] ) + USE SIGNAL
-      + ROUTED met2 ( 67850 2380 0 ) ( * 17510 )
+      NEW met1 ( 717830 113730 ) M1M2_PR
+      NEW met1 ( 2684330 113730 ) M1M2_PR ;
+    - la_data_out[60] ( PIN la_data_out[60] ) + USE SIGNAL ;
+    - la_data_out[61] ( PIN la_data_out[61] ) + USE SIGNAL ;
+    - la_data_out[62] ( PIN la_data_out[62] ) + USE SIGNAL ;
+    - la_data_out[63] ( PIN la_data_out[63] ) + USE SIGNAL ;
+    - la_data_out[64] ( PIN la_data_out[64] ) + USE SIGNAL ;
+    - la_data_out[65] ( PIN la_data_out[65] ) + USE SIGNAL ;
+    - la_data_out[66] ( PIN la_data_out[66] ) + USE SIGNAL ;
+    - la_data_out[67] ( PIN la_data_out[67] ) + USE SIGNAL ;
+    - la_data_out[68] ( PIN la_data_out[68] ) + USE SIGNAL ;
+    - la_data_out[69] ( PIN la_data_out[69] ) + USE SIGNAL ;
+    - la_data_out[6] ( PIN la_data_out[6] ) ( inst_eFPGA_CPU_top la_data_out[2] ) + USE SIGNAL
+      + ROUTED met2 ( 741750 1700 0 ) ( * 65450 )
+      NEW met1 ( 741750 65450 ) ( 2646150 * )
+      NEW met2 ( 2662930 149260 ) ( * 150240 0 )
+      NEW met2 ( 2662710 149260 ) ( 2662930 * )
+      NEW met2 ( 2662710 137870 ) ( * 149260 )
+      NEW met1 ( 2646150 137870 ) ( 2662710 * )
+      NEW met2 ( 2646150 65450 ) ( * 137870 )
+      NEW met1 ( 741750 65450 ) M1M2_PR
+      NEW met1 ( 2646150 65450 ) M1M2_PR
+      NEW met1 ( 2662710 137870 ) M1M2_PR
+      NEW met1 ( 2646150 137870 ) M1M2_PR ;
+    - la_data_out[70] ( PIN la_data_out[70] ) + USE SIGNAL ;
+    - la_data_out[71] ( PIN la_data_out[71] ) + USE SIGNAL ;
+    - la_data_out[72] ( PIN la_data_out[72] ) + USE SIGNAL ;
+    - la_data_out[73] ( PIN la_data_out[73] ) + USE SIGNAL ;
+    - la_data_out[74] ( PIN la_data_out[74] ) + USE SIGNAL ;
+    - la_data_out[75] ( PIN la_data_out[75] ) + USE SIGNAL ;
+    - la_data_out[76] ( PIN la_data_out[76] ) + USE SIGNAL ;
+    - la_data_out[77] ( PIN la_data_out[77] ) + USE SIGNAL ;
+    - la_data_out[78] ( PIN la_data_out[78] ) + USE SIGNAL ;
+    - la_data_out[79] ( PIN la_data_out[79] ) + USE SIGNAL ;
+    - la_data_out[7] ( PIN la_data_out[7] ) + USE SIGNAL ;
+    - la_data_out[80] ( PIN la_data_out[80] ) + USE SIGNAL ;
+    - la_data_out[81] ( PIN la_data_out[81] ) + USE SIGNAL ;
+    - la_data_out[82] ( PIN la_data_out[82] ) + USE SIGNAL ;
+    - la_data_out[83] ( PIN la_data_out[83] ) + USE SIGNAL ;
+    - la_data_out[84] ( PIN la_data_out[84] ) + USE SIGNAL ;
+    - la_data_out[85] ( PIN la_data_out[85] ) + USE SIGNAL ;
+    - la_data_out[86] ( PIN la_data_out[86] ) + USE SIGNAL ;
+    - la_data_out[87] ( PIN la_data_out[87] ) + USE SIGNAL ;
+    - la_data_out[88] ( PIN la_data_out[88] ) + USE SIGNAL ;
+    - la_data_out[89] ( PIN la_data_out[89] ) + USE SIGNAL ;
+    - la_data_out[8] ( PIN la_data_out[8] ) + USE SIGNAL ;
+    - la_data_out[90] ( PIN la_data_out[90] ) + USE SIGNAL ;
+    - la_data_out[91] ( PIN la_data_out[91] ) + USE SIGNAL ;
+    - la_data_out[92] ( PIN la_data_out[92] ) + USE SIGNAL ;
+    - la_data_out[93] ( PIN la_data_out[93] ) + USE SIGNAL ;
+    - la_data_out[94] ( PIN la_data_out[94] ) + USE SIGNAL ;
+    - la_data_out[95] ( PIN la_data_out[95] ) + USE SIGNAL ;
+    - la_data_out[96] ( PIN la_data_out[96] ) + USE SIGNAL ;
+    - la_data_out[97] ( PIN la_data_out[97] ) + USE SIGNAL ;
+    - la_data_out[98] ( PIN la_data_out[98] ) + USE SIGNAL ;
+    - la_data_out[99] ( PIN la_data_out[99] ) + USE SIGNAL ;
+    - la_data_out[9] ( PIN la_data_out[9] ) + USE SIGNAL ;
+    - la_oenb[0] ( PIN la_oenb[0] ) + USE SIGNAL ;
+    - la_oenb[100] ( PIN la_oenb[100] ) + USE SIGNAL ;
+    - la_oenb[101] ( PIN la_oenb[101] ) + USE SIGNAL ;
+    - la_oenb[102] ( PIN la_oenb[102] ) + USE SIGNAL ;
+    - la_oenb[103] ( PIN la_oenb[103] ) + USE SIGNAL ;
+    - la_oenb[104] ( PIN la_oenb[104] ) + USE SIGNAL ;
+    - la_oenb[105] ( PIN la_oenb[105] ) + USE SIGNAL ;
+    - la_oenb[106] ( PIN la_oenb[106] ) + USE SIGNAL ;
+    - la_oenb[107] ( PIN la_oenb[107] ) + USE SIGNAL ;
+    - la_oenb[108] ( PIN la_oenb[108] ) + USE SIGNAL ;
+    - la_oenb[109] ( PIN la_oenb[109] ) + USE SIGNAL ;
+    - la_oenb[10] ( PIN la_oenb[10] ) + USE SIGNAL ;
+    - la_oenb[110] ( PIN la_oenb[110] ) + USE SIGNAL ;
+    - la_oenb[111] ( PIN la_oenb[111] ) + USE SIGNAL ;
+    - la_oenb[112] ( PIN la_oenb[112] ) + USE SIGNAL ;
+    - la_oenb[113] ( PIN la_oenb[113] ) + USE SIGNAL ;
+    - la_oenb[114] ( PIN la_oenb[114] ) + USE SIGNAL ;
+    - la_oenb[115] ( PIN la_oenb[115] ) + USE SIGNAL ;
+    - la_oenb[116] ( PIN la_oenb[116] ) + USE SIGNAL ;
+    - la_oenb[117] ( PIN la_oenb[117] ) + USE SIGNAL ;
+    - la_oenb[118] ( PIN la_oenb[118] ) + USE SIGNAL ;
+    - la_oenb[119] ( PIN la_oenb[119] ) + USE SIGNAL ;
+    - la_oenb[11] ( PIN la_oenb[11] ) + USE SIGNAL ;
+    - la_oenb[120] ( PIN la_oenb[120] ) + USE SIGNAL ;
+    - la_oenb[121] ( PIN la_oenb[121] ) + USE SIGNAL ;
+    - la_oenb[122] ( PIN la_oenb[122] ) + USE SIGNAL ;
+    - la_oenb[123] ( PIN la_oenb[123] ) + USE SIGNAL ;
+    - la_oenb[124] ( PIN la_oenb[124] ) + USE SIGNAL ;
+    - la_oenb[125] ( PIN la_oenb[125] ) + USE SIGNAL ;
+    - la_oenb[126] ( PIN la_oenb[126] ) + USE SIGNAL ;
+    - la_oenb[127] ( PIN la_oenb[127] ) + USE SIGNAL ;
+    - la_oenb[12] ( PIN la_oenb[12] ) + USE SIGNAL ;
+    - la_oenb[13] ( PIN la_oenb[13] ) + USE SIGNAL ;
+    - la_oenb[14] ( PIN la_oenb[14] ) + USE SIGNAL ;
+    - la_oenb[15] ( PIN la_oenb[15] ) + USE SIGNAL ;
+    - la_oenb[16] ( PIN la_oenb[16] ) + USE SIGNAL ;
+    - la_oenb[17] ( PIN la_oenb[17] ) + USE SIGNAL ;
+    - la_oenb[18] ( PIN la_oenb[18] ) + USE SIGNAL ;
+    - la_oenb[19] ( PIN la_oenb[19] ) + USE SIGNAL ;
+    - la_oenb[1] ( PIN la_oenb[1] ) + USE SIGNAL ;
+    - la_oenb[20] ( PIN la_oenb[20] ) + USE SIGNAL ;
+    - la_oenb[21] ( PIN la_oenb[21] ) + USE SIGNAL ;
+    - la_oenb[22] ( PIN la_oenb[22] ) + USE SIGNAL ;
+    - la_oenb[23] ( PIN la_oenb[23] ) + USE SIGNAL ;
+    - la_oenb[24] ( PIN la_oenb[24] ) + USE SIGNAL ;
+    - la_oenb[25] ( PIN la_oenb[25] ) + USE SIGNAL ;
+    - la_oenb[26] ( PIN la_oenb[26] ) + USE SIGNAL ;
+    - la_oenb[27] ( PIN la_oenb[27] ) + USE SIGNAL ;
+    - la_oenb[28] ( PIN la_oenb[28] ) + USE SIGNAL ;
+    - la_oenb[29] ( PIN la_oenb[29] ) + USE SIGNAL ;
+    - la_oenb[2] ( PIN la_oenb[2] ) + USE SIGNAL ;
+    - la_oenb[30] ( PIN la_oenb[30] ) + USE SIGNAL ;
+    - la_oenb[31] ( PIN la_oenb[31] ) + USE SIGNAL ;
+    - la_oenb[32] ( PIN la_oenb[32] ) + USE SIGNAL ;
+    - la_oenb[33] ( PIN la_oenb[33] ) + USE SIGNAL ;
+    - la_oenb[34] ( PIN la_oenb[34] ) + USE SIGNAL ;
+    - la_oenb[35] ( PIN la_oenb[35] ) + USE SIGNAL ;
+    - la_oenb[36] ( PIN la_oenb[36] ) + USE SIGNAL ;
+    - la_oenb[37] ( PIN la_oenb[37] ) + USE SIGNAL ;
+    - la_oenb[38] ( PIN la_oenb[38] ) + USE SIGNAL ;
+    - la_oenb[39] ( PIN la_oenb[39] ) + USE SIGNAL ;
+    - la_oenb[3] ( PIN la_oenb[3] ) + USE SIGNAL ;
+    - la_oenb[40] ( PIN la_oenb[40] ) + USE SIGNAL ;
+    - la_oenb[41] ( PIN la_oenb[41] ) + USE SIGNAL ;
+    - la_oenb[42] ( PIN la_oenb[42] ) + USE SIGNAL ;
+    - la_oenb[43] ( PIN la_oenb[43] ) + USE SIGNAL ;
+    - la_oenb[44] ( PIN la_oenb[44] ) + USE SIGNAL ;
+    - la_oenb[45] ( PIN la_oenb[45] ) + USE SIGNAL ;
+    - la_oenb[46] ( PIN la_oenb[46] ) + USE SIGNAL ;
+    - la_oenb[47] ( PIN la_oenb[47] ) + USE SIGNAL ;
+    - la_oenb[48] ( PIN la_oenb[48] ) + USE SIGNAL ;
+    - la_oenb[49] ( PIN la_oenb[49] ) + USE SIGNAL ;
+    - la_oenb[4] ( PIN la_oenb[4] ) + USE SIGNAL ;
+    - la_oenb[50] ( PIN la_oenb[50] ) + USE SIGNAL ;
+    - la_oenb[51] ( PIN la_oenb[51] ) + USE SIGNAL ;
+    - la_oenb[52] ( PIN la_oenb[52] ) + USE SIGNAL ;
+    - la_oenb[53] ( PIN la_oenb[53] ) + USE SIGNAL ;
+    - la_oenb[54] ( PIN la_oenb[54] ) + USE SIGNAL ;
+    - la_oenb[55] ( PIN la_oenb[55] ) + USE SIGNAL ;
+    - la_oenb[56] ( PIN la_oenb[56] ) + USE SIGNAL ;
+    - la_oenb[57] ( PIN la_oenb[57] ) + USE SIGNAL ;
+    - la_oenb[58] ( PIN la_oenb[58] ) + USE SIGNAL ;
+    - la_oenb[59] ( PIN la_oenb[59] ) + USE SIGNAL ;
+    - la_oenb[5] ( PIN la_oenb[5] ) + USE SIGNAL ;
+    - la_oenb[60] ( PIN la_oenb[60] ) + USE SIGNAL ;
+    - la_oenb[61] ( PIN la_oenb[61] ) + USE SIGNAL ;
+    - la_oenb[62] ( PIN la_oenb[62] ) + USE SIGNAL ;
+    - la_oenb[63] ( PIN la_oenb[63] ) + USE SIGNAL ;
+    - la_oenb[64] ( PIN la_oenb[64] ) + USE SIGNAL ;
+    - la_oenb[65] ( PIN la_oenb[65] ) + USE SIGNAL ;
+    - la_oenb[66] ( PIN la_oenb[66] ) + USE SIGNAL ;
+    - la_oenb[67] ( PIN la_oenb[67] ) + USE SIGNAL ;
+    - la_oenb[68] ( PIN la_oenb[68] ) + USE SIGNAL ;
+    - la_oenb[69] ( PIN la_oenb[69] ) + USE SIGNAL ;
+    - la_oenb[6] ( PIN la_oenb[6] ) + USE SIGNAL ;
+    - la_oenb[70] ( PIN la_oenb[70] ) + USE SIGNAL ;
+    - la_oenb[71] ( PIN la_oenb[71] ) + USE SIGNAL ;
+    - la_oenb[72] ( PIN la_oenb[72] ) + USE SIGNAL ;
+    - la_oenb[73] ( PIN la_oenb[73] ) + USE SIGNAL ;
+    - la_oenb[74] ( PIN la_oenb[74] ) + USE SIGNAL ;
+    - la_oenb[75] ( PIN la_oenb[75] ) + USE SIGNAL ;
+    - la_oenb[76] ( PIN la_oenb[76] ) + USE SIGNAL ;
+    - la_oenb[77] ( PIN la_oenb[77] ) + USE SIGNAL ;
+    - la_oenb[78] ( PIN la_oenb[78] ) + USE SIGNAL ;
+    - la_oenb[79] ( PIN la_oenb[79] ) + USE SIGNAL ;
+    - la_oenb[7] ( PIN la_oenb[7] ) + USE SIGNAL ;
+    - la_oenb[80] ( PIN la_oenb[80] ) + USE SIGNAL ;
+    - la_oenb[81] ( PIN la_oenb[81] ) + USE SIGNAL ;
+    - la_oenb[82] ( PIN la_oenb[82] ) + USE SIGNAL ;
+    - la_oenb[83] ( PIN la_oenb[83] ) + USE SIGNAL ;
+    - la_oenb[84] ( PIN la_oenb[84] ) + USE SIGNAL ;
+    - la_oenb[85] ( PIN la_oenb[85] ) + USE SIGNAL ;
+    - la_oenb[86] ( PIN la_oenb[86] ) + USE SIGNAL ;
+    - la_oenb[87] ( PIN la_oenb[87] ) + USE SIGNAL ;
+    - la_oenb[88] ( PIN la_oenb[88] ) + USE SIGNAL ;
+    - la_oenb[89] ( PIN la_oenb[89] ) + USE SIGNAL ;
+    - la_oenb[8] ( PIN la_oenb[8] ) + USE SIGNAL ;
+    - la_oenb[90] ( PIN la_oenb[90] ) + USE SIGNAL ;
+    - la_oenb[91] ( PIN la_oenb[91] ) + USE SIGNAL ;
+    - la_oenb[92] ( PIN la_oenb[92] ) + USE SIGNAL ;
+    - la_oenb[93] ( PIN la_oenb[93] ) + USE SIGNAL ;
+    - la_oenb[94] ( PIN la_oenb[94] ) + USE SIGNAL ;
+    - la_oenb[95] ( PIN la_oenb[95] ) + USE SIGNAL ;
+    - la_oenb[96] ( PIN la_oenb[96] ) + USE SIGNAL ;
+    - la_oenb[97] ( PIN la_oenb[97] ) + USE SIGNAL ;
+    - la_oenb[98] ( PIN la_oenb[98] ) + USE SIGNAL ;
+    - la_oenb[99] ( PIN la_oenb[99] ) + USE SIGNAL ;
+    - la_oenb[9] ( PIN la_oenb[9] ) + USE SIGNAL ;
+    - user_clock2 ( PIN user_clock2 ) ( inst_eFPGA_CPU_top user_clock2 ) + USE CLOCK
+      + ROUTED met2 ( 2899150 1700 0 ) ( * 17170 )
+      NEW met2 ( 2738830 149090 ) ( * 150240 0 )
+      NEW met1 ( 2732630 149090 ) ( 2738830 * )
+      NEW met2 ( 2732630 17170 ) ( * 149090 )
+      NEW met1 ( 2732630 17170 ) ( 2899150 * )
+      NEW met1 ( 2732630 17170 ) M1M2_PR
+      NEW met1 ( 2899150 17170 ) M1M2_PR
+      NEW met1 ( 2738830 149090 ) M1M2_PR
+      NEW met1 ( 2732630 149090 ) M1M2_PR ;
+    - wb_clk_i ( PIN wb_clk_i ) ( inst_eFPGA_CPU_top wb_clk_i ) + USE SIGNAL
+      + ROUTED met2 ( 1150 82800 ) ( 2990 * )
+      NEW met2 ( 2990 1700 0 ) ( * 82800 )
+      NEW met2 ( 30350 149260 ) ( * 150240 0 )
+      NEW met2 ( 30130 149260 ) ( 30350 * )
+      NEW met2 ( 30130 137870 ) ( * 149260 )
+      NEW met1 ( 1150 137870 ) ( 30130 * )
+      NEW met2 ( 1150 82800 ) ( * 137870 )
+      NEW met1 ( 30130 137870 ) M1M2_PR
+      NEW met1 ( 1150 137870 ) M1M2_PR ;
+    - wb_rst_i ( PIN wb_rst_i ) ( inst_eFPGA_CPU_top wb_rst_i ) + USE SIGNAL
+      + ROUTED met2 ( 8510 1700 0 ) ( * 17170 )
+      NEW met1 ( 8510 17170 ) ( 37950 * )
+      NEW met1 ( 37950 127670 ) ( 2760230 * )
+      NEW met2 ( 37950 17170 ) ( * 127670 )
+      NEW met2 ( 2760230 127670 ) ( * 131100 )
+      NEW met2 ( 2764130 149090 ) ( * 150240 0 )
+      NEW met2 ( 2763910 149090 ) ( 2764130 * )
+      NEW met2 ( 2763910 131100 ) ( * 149090 )
+      NEW met2 ( 2760230 131100 ) ( 2763910 * )
+      NEW met1 ( 8510 17170 ) M1M2_PR
+      NEW met1 ( 37950 17170 ) M1M2_PR
+      NEW met1 ( 37950 127670 ) M1M2_PR
+      NEW met1 ( 2760230 127670 ) M1M2_PR ;
+    - wbs_ack_o ( PIN wbs_ack_o ) ( inst_eFPGA_CPU_top wbs_ack_o ) + USE SIGNAL
+      + ROUTED met2 ( 14490 1700 0 ) ( * 72250 )
+      NEW met2 ( 2787830 72250 ) ( * 131100 )
+      NEW met2 ( 2789430 149260 ) ( * 150240 0 )
+      NEW met2 ( 2789210 149260 ) ( 2789430 * )
+      NEW met2 ( 2789210 131100 ) ( * 149260 )
+      NEW met2 ( 2787830 131100 ) ( 2789210 * )
+      NEW met1 ( 14490 72250 ) ( 2787830 * )
+      NEW met1 ( 14490 72250 ) M1M2_PR
+      NEW met1 ( 2787830 72250 ) M1M2_PR ;
+    - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( inst_eFPGA_CPU_top wbs_adr_i[0] ) + USE SIGNAL
+      + ROUTED met2 ( 1725230 23970 ) ( * 131100 )
+      NEW met2 ( 1726370 149260 ) ( * 150240 0 )
+      NEW met2 ( 1726150 149260 ) ( 1726370 * )
+      NEW met2 ( 1726150 131100 ) ( * 149260 )
+      NEW met2 ( 1725230 131100 ) ( 1726150 * )
+      NEW met2 ( 38410 1700 0 ) ( * 23970 )
+      NEW met1 ( 38410 23970 ) ( 1725230 * )
+      NEW met1 ( 1725230 23970 ) M1M2_PR
+      NEW met1 ( 38410 23970 ) M1M2_PR ;
+    - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ( inst_eFPGA_CPU_top wbs_adr_i[10] ) + USE SIGNAL
+      + ROUTED met2 ( 1469930 24650 ) ( * 131100 )
+      NEW met2 ( 1473370 149260 ) ( * 150240 0 )
+      NEW met2 ( 1473150 149260 ) ( 1473370 * )
+      NEW met2 ( 1473150 131100 ) ( * 149260 )
+      NEW met2 ( 1469930 131100 ) ( 1473150 * )
+      NEW met2 ( 239430 1700 0 ) ( * 24650 )
+      NEW met1 ( 239430 24650 ) ( 1469930 * )
+      NEW met1 ( 1469930 24650 ) M1M2_PR
+      NEW met1 ( 239430 24650 ) M1M2_PR ;
+    - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ( inst_eFPGA_CPU_top wbs_adr_i[11] ) + USE SIGNAL
+      + ROUTED met2 ( 1442330 24990 ) ( * 131100 )
+      NEW met2 ( 1447610 149260 ) ( * 150240 0 )
+      NEW met2 ( 1447390 149260 ) ( 1447610 * )
+      NEW met2 ( 1447390 131100 ) ( * 149260 )
+      NEW met2 ( 1442330 131100 ) ( 1447390 * )
+      NEW met2 ( 256910 1700 0 ) ( * 24990 )
+      NEW met1 ( 256910 24990 ) ( 1442330 * )
+      NEW met1 ( 1442330 24990 ) M1M2_PR
+      NEW met1 ( 256910 24990 ) M1M2_PR ;
+    - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ( inst_eFPGA_CPU_top wbs_adr_i[12] ) + USE SIGNAL
+      + ROUTED met2 ( 274850 1700 0 ) ( * 25330 )
+      NEW met1 ( 274850 25330 ) ( 1421630 * )
+      NEW met2 ( 1421630 25330 ) ( * 131100 )
+      NEW met2 ( 1422310 149260 ) ( * 150240 0 )
+      NEW met2 ( 1422090 149260 ) ( 1422310 * )
+      NEW met2 ( 1422090 131100 ) ( * 149260 )
+      NEW met2 ( 1421630 131100 ) ( 1422090 * )
+      NEW met1 ( 274850 25330 ) M1M2_PR
+      NEW met1 ( 1421630 25330 ) M1M2_PR ;
+    - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ( inst_eFPGA_CPU_top wbs_adr_i[13] ) + USE SIGNAL
+      + ROUTED met2 ( 292330 1700 0 ) ( * 25670 )
+      NEW met1 ( 292330 25670 ) ( 1394030 * )
+      NEW met2 ( 1394030 25670 ) ( * 131100 )
+      NEW met2 ( 1397010 149260 ) ( * 150240 0 )
+      NEW met2 ( 1396790 149260 ) ( 1397010 * )
+      NEW met2 ( 1396790 131100 ) ( * 149260 )
+      NEW met2 ( 1394030 131100 ) ( 1396790 * )
+      NEW met1 ( 292330 25670 ) M1M2_PR
+      NEW met1 ( 1394030 25670 ) M1M2_PR ;
+    - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ( inst_eFPGA_CPU_top wbs_adr_i[14] ) + USE SIGNAL
+      + ROUTED met2 ( 310270 1700 0 ) ( * 26010 )
+      NEW met2 ( 1366430 26010 ) ( * 131100 )
+      NEW met2 ( 1371710 149260 ) ( * 150240 0 )
+      NEW met2 ( 1371490 149260 ) ( 1371710 * )
+      NEW met2 ( 1371490 131100 ) ( * 149260 )
+      NEW met2 ( 1366430 131100 ) ( 1371490 * )
+      NEW met1 ( 310270 26010 ) ( 1366430 * )
+      NEW met1 ( 310270 26010 ) M1M2_PR
+      NEW met1 ( 1366430 26010 ) M1M2_PR ;
+    - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ( inst_eFPGA_CPU_top wbs_adr_i[15] ) + USE SIGNAL
+      + ROUTED met2 ( 1345730 26350 ) ( * 131100 )
+      NEW met2 ( 1346410 149260 ) ( * 150240 0 )
+      NEW met2 ( 1346190 149260 ) ( 1346410 * )
+      NEW met2 ( 1346190 131100 ) ( * 149260 )
+      NEW met2 ( 1345730 131100 ) ( 1346190 * )
+      NEW met2 ( 327750 1700 0 ) ( * 26350 )
+      NEW met1 ( 327750 26350 ) ( 1345730 * )
+      NEW met1 ( 1345730 26350 ) M1M2_PR
+      NEW met1 ( 327750 26350 ) M1M2_PR ;
+    - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ( inst_eFPGA_CPU_top wbs_adr_i[16] ) + USE SIGNAL
+      + ROUTED met2 ( 345690 1700 0 ) ( * 26690 )
+      NEW met1 ( 345690 26690 ) ( 1318130 * )
+      NEW met2 ( 1318130 26690 ) ( * 131100 )
+      NEW met2 ( 1321110 149260 ) ( * 150240 0 )
+      NEW met2 ( 1320890 149260 ) ( 1321110 * )
+      NEW met2 ( 1320890 131100 ) ( * 149260 )
+      NEW met2 ( 1318130 131100 ) ( 1320890 * )
+      NEW met1 ( 345690 26690 ) M1M2_PR
+      NEW met1 ( 1318130 26690 ) M1M2_PR ;
+    - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ( inst_eFPGA_CPU_top wbs_adr_i[17] ) + USE SIGNAL
+      + ROUTED met2 ( 363170 1700 0 ) ( * 27030 )
+      NEW met1 ( 363170 27030 ) ( 1290530 * )
+      NEW met2 ( 1290530 27030 ) ( * 131100 )
+      NEW met2 ( 1295810 149260 ) ( * 150240 0 )
+      NEW met2 ( 1295590 149260 ) ( 1295810 * )
+      NEW met2 ( 1295590 131100 ) ( * 149260 )
+      NEW met2 ( 1290530 131100 ) ( 1295590 * )
+      NEW met1 ( 363170 27030 ) M1M2_PR
+      NEW met1 ( 1290530 27030 ) M1M2_PR ;
+    - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ( inst_eFPGA_CPU_top wbs_adr_i[18] ) + USE SIGNAL
+      + ROUTED met2 ( 381110 1700 0 ) ( * 27370 )
+      NEW met2 ( 1269830 27370 ) ( * 131100 )
+      NEW met2 ( 1270510 149260 ) ( * 150240 0 )
+      NEW met2 ( 1270290 149260 ) ( 1270510 * )
+      NEW met2 ( 1270290 131100 ) ( * 149260 )
+      NEW met2 ( 1269830 131100 ) ( 1270290 * )
+      NEW met1 ( 381110 27370 ) ( 1269830 * )
+      NEW met1 ( 381110 27370 ) M1M2_PR
+      NEW met1 ( 1269830 27370 ) M1M2_PR ;
+    - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ( inst_eFPGA_CPU_top wbs_adr_i[19] ) + USE SIGNAL
+      + ROUTED met2 ( 398590 1700 0 ) ( * 23630 )
+      NEW met2 ( 1242230 23630 ) ( * 131100 )
+      NEW met2 ( 1245210 149260 ) ( * 150240 0 )
+      NEW met2 ( 1244990 149260 ) ( 1245210 * )
+      NEW met2 ( 1244990 131100 ) ( * 149260 )
+      NEW met2 ( 1242230 131100 ) ( 1244990 * )
+      NEW met1 ( 398590 23630 ) ( 1242230 * )
+      NEW met1 ( 398590 23630 ) M1M2_PR
+      NEW met1 ( 1242230 23630 ) M1M2_PR ;
+    - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( inst_eFPGA_CPU_top wbs_adr_i[1] ) + USE SIGNAL
+      + ROUTED met2 ( 61870 1700 0 ) ( * 24310 )
+      NEW met1 ( 61870 24310 ) ( 1697630 * )
+      NEW met2 ( 1697630 24310 ) ( * 131100 )
+      NEW met2 ( 1701070 149090 ) ( * 150240 0 )
+      NEW met2 ( 1700850 149090 ) ( 1701070 * )
+      NEW met2 ( 1700850 131100 ) ( * 149090 )
+      NEW met2 ( 1697630 131100 ) ( 1700850 * )
+      NEW met1 ( 61870 24310 ) M1M2_PR
+      NEW met1 ( 1697630 24310 ) M1M2_PR ;
+    - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ( inst_eFPGA_CPU_top wbs_adr_i[20] ) + USE SIGNAL
+      + ROUTED met2 ( 416530 1700 0 ) ( * 23290 )
+      NEW met1 ( 416530 23290 ) ( 1214630 * )
+      NEW met2 ( 1214630 23290 ) ( * 131100 )
+      NEW met2 ( 1219910 149260 ) ( * 150240 0 )
+      NEW met2 ( 1219690 149260 ) ( 1219910 * )
+      NEW met2 ( 1219690 131100 ) ( * 149260 )
+      NEW met2 ( 1214630 131100 ) ( 1219690 * )
+      NEW met1 ( 416530 23290 ) M1M2_PR
+      NEW met1 ( 1214630 23290 ) M1M2_PR ;
+    - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ( inst_eFPGA_CPU_top wbs_adr_i[21] ) + USE SIGNAL
+      + ROUTED met2 ( 434470 1700 0 ) ( * 22950 )
+      NEW met1 ( 434470 22950 ) ( 1193930 * )
+      NEW met2 ( 1193930 22950 ) ( * 131100 )
+      NEW met2 ( 1194610 149260 ) ( * 150240 0 )
+      NEW met2 ( 1194390 149260 ) ( 1194610 * )
+      NEW met2 ( 1194390 131100 ) ( * 149260 )
+      NEW met2 ( 1193930 131100 ) ( 1194390 * )
+      NEW met1 ( 434470 22950 ) M1M2_PR
+      NEW met1 ( 1193930 22950 ) M1M2_PR ;
+    - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ( inst_eFPGA_CPU_top wbs_adr_i[22] ) + USE SIGNAL
+      + ROUTED met2 ( 1166330 22610 ) ( * 131100 )
+      NEW met2 ( 1169310 149260 ) ( * 150240 0 )
+      NEW met2 ( 1169090 149260 ) ( 1169310 * )
+      NEW met2 ( 1169090 131100 ) ( * 149260 )
+      NEW met2 ( 1166330 131100 ) ( 1169090 * )
+      NEW met2 ( 451950 1700 0 ) ( * 22610 )
+      NEW met1 ( 451950 22610 ) ( 1166330 * )
+      NEW met1 ( 1166330 22610 ) M1M2_PR
+      NEW met1 ( 451950 22610 ) M1M2_PR ;
+    - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ( inst_eFPGA_CPU_top wbs_adr_i[23] ) + USE SIGNAL
+      + ROUTED met2 ( 469890 1700 0 ) ( * 22270 )
+      NEW met1 ( 469890 22270 ) ( 1138730 * )
+      NEW met2 ( 1138730 22270 ) ( * 131100 )
+      NEW met2 ( 1144010 149260 ) ( * 150240 0 )
+      NEW met2 ( 1143790 149260 ) ( 1144010 * )
+      NEW met2 ( 1143790 131100 ) ( * 149260 )
+      NEW met2 ( 1138730 131100 ) ( 1143790 * )
+      NEW met1 ( 469890 22270 ) M1M2_PR
+      NEW met1 ( 1138730 22270 ) M1M2_PR ;
+    - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ( inst_eFPGA_CPU_top wbs_adr_i[24] ) + USE SIGNAL
+      + ROUTED met2 ( 487370 1700 0 ) ( * 21930 )
+      NEW met1 ( 487370 21930 ) ( 1118030 * )
+      NEW met2 ( 1118030 21930 ) ( * 131100 )
+      NEW met2 ( 1118710 149260 ) ( * 150240 0 )
+      NEW met2 ( 1118490 149260 ) ( 1118710 * )
+      NEW met2 ( 1118490 131100 ) ( * 149260 )
+      NEW met2 ( 1118030 131100 ) ( 1118490 * )
+      NEW met1 ( 487370 21930 ) M1M2_PR
+      NEW met1 ( 1118030 21930 ) M1M2_PR ;
+    - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ( inst_eFPGA_CPU_top wbs_adr_i[25] ) + USE SIGNAL
+      + ROUTED met2 ( 505310 1700 0 ) ( * 21590 )
+      NEW met2 ( 1090430 21590 ) ( * 131100 )
+      NEW met2 ( 1093410 149260 ) ( * 150240 0 )
+      NEW met2 ( 1093190 149260 ) ( 1093410 * )
+      NEW met2 ( 1093190 131100 ) ( * 149260 )
+      NEW met2 ( 1090430 131100 ) ( 1093190 * )
+      NEW met1 ( 505310 21590 ) ( 1090430 * )
+      NEW met1 ( 505310 21590 ) M1M2_PR
+      NEW met1 ( 1090430 21590 ) M1M2_PR ;
+    - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ( inst_eFPGA_CPU_top wbs_adr_i[26] ) + USE SIGNAL
+      + ROUTED met2 ( 1062830 21250 ) ( * 131100 )
+      NEW met2 ( 1068110 149260 ) ( * 150240 0 )
+      NEW met2 ( 1067890 149260 ) ( 1068110 * )
+      NEW met2 ( 1067890 131100 ) ( * 149260 )
+      NEW met2 ( 1062830 131100 ) ( 1067890 * )
+      NEW met2 ( 522790 1700 0 ) ( * 21250 )
+      NEW met1 ( 522790 21250 ) ( 1062830 * )
+      NEW met1 ( 1062830 21250 ) M1M2_PR
+      NEW met1 ( 522790 21250 ) M1M2_PR ;
+    - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ( inst_eFPGA_CPU_top wbs_adr_i[27] ) + USE SIGNAL
+      + ROUTED met2 ( 540730 1700 0 ) ( * 32130 )
+      NEW met1 ( 540730 32130 ) ( 1042130 * )
+      NEW met2 ( 1042130 32130 ) ( * 131100 )
+      NEW met2 ( 1042810 149260 ) ( * 150240 0 )
+      NEW met2 ( 1042590 149260 ) ( 1042810 * )
+      NEW met2 ( 1042590 131100 ) ( * 149260 )
+      NEW met2 ( 1042130 131100 ) ( 1042590 * )
+      NEW met1 ( 540730 32130 ) M1M2_PR
+      NEW met1 ( 1042130 32130 ) M1M2_PR ;
+    - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ( inst_eFPGA_CPU_top wbs_adr_i[28] ) + USE SIGNAL
+      + ROUTED met2 ( 558210 1700 0 ) ( * 32470 )
+      NEW met1 ( 558210 32470 ) ( 1014530 * )
+      NEW met2 ( 1014530 32470 ) ( * 131100 )
+      NEW met2 ( 1017510 149260 ) ( * 150240 0 )
+      NEW met2 ( 1017290 149260 ) ( 1017510 * )
+      NEW met2 ( 1017290 131100 ) ( * 149260 )
+      NEW met2 ( 1014530 131100 ) ( 1017290 * )
+      NEW met1 ( 558210 32470 ) M1M2_PR
+      NEW met1 ( 1014530 32470 ) M1M2_PR ;
+    - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ( inst_eFPGA_CPU_top wbs_adr_i[29] ) + USE SIGNAL
+      + ROUTED met2 ( 576150 1700 0 ) ( * 32810 )
+      NEW met2 ( 986930 32810 ) ( * 131100 )
+      NEW met2 ( 992210 149260 ) ( * 150240 0 )
+      NEW met2 ( 991990 149260 ) ( 992210 * )
+      NEW met2 ( 991990 131100 ) ( * 149260 )
+      NEW met2 ( 986930 131100 ) ( 991990 * )
+      NEW met1 ( 576150 32810 ) ( 986930 * )
+      NEW met1 ( 576150 32810 ) M1M2_PR
+      NEW met1 ( 986930 32810 ) M1M2_PR ;
+    - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( inst_eFPGA_CPU_top wbs_adr_i[2] ) + USE SIGNAL
+      + ROUTED met2 ( 85330 1700 0 ) ( * 30770 )
+      NEW met2 ( 1675770 149090 ) ( * 150240 0 )
+      NEW met1 ( 1670030 149090 ) ( 1675770 * )
+      NEW met2 ( 1670030 30770 ) ( * 149090 )
+      NEW met1 ( 85330 30770 ) ( 1670030 * )
+      NEW met1 ( 85330 30770 ) M1M2_PR
+      NEW met1 ( 1670030 30770 ) M1M2_PR
+      NEW met1 ( 1675770 149090 ) M1M2_PR
+      NEW met1 ( 1670030 149090 ) M1M2_PR ;
+    - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ( inst_eFPGA_CPU_top wbs_adr_i[30] ) + USE SIGNAL
+      + ROUTED met2 ( 594090 1700 0 ) ( * 34500 )
+      NEW met2 ( 593630 34500 ) ( 594090 * )
+      NEW met2 ( 593630 34500 ) ( * 120870 )
+      NEW met2 ( 966230 120870 ) ( * 131100 )
+      NEW met2 ( 966910 149260 ) ( * 150240 0 )
+      NEW met2 ( 966690 149260 ) ( 966910 * )
+      NEW met2 ( 966690 131100 ) ( * 149260 )
+      NEW met2 ( 966230 131100 ) ( 966690 * )
+      NEW met1 ( 593630 120870 ) ( 966230 * )
+      NEW met1 ( 593630 120870 ) M1M2_PR
+      NEW met1 ( 966230 120870 ) M1M2_PR ;
+    - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ( inst_eFPGA_CPU_top wbs_adr_i[31] ) + USE SIGNAL
+      + ROUTED met2 ( 611570 1700 0 ) ( * 80070 )
+      NEW met1 ( 611570 80070 ) ( 938630 * )
+      NEW met2 ( 938630 80070 ) ( * 131100 )
+      NEW met2 ( 941610 149260 ) ( * 150240 0 )
+      NEW met2 ( 941390 149260 ) ( 941610 * )
+      NEW met2 ( 941390 131100 ) ( * 149260 )
+      NEW met2 ( 938630 131100 ) ( 941390 * )
+      NEW met1 ( 611570 80070 ) M1M2_PR
+      NEW met1 ( 938630 80070 ) M1M2_PR ;
+    - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( inst_eFPGA_CPU_top wbs_adr_i[3] ) + USE SIGNAL
+      + ROUTED met2 ( 109250 1700 0 ) ( * 31110 )
+      NEW met2 ( 1649330 31110 ) ( * 131100 )
+      NEW met2 ( 1650470 149260 ) ( * 150240 0 )
+      NEW met2 ( 1650250 149260 ) ( 1650470 * )
+      NEW met2 ( 1650250 131100 ) ( * 149260 )
+      NEW met2 ( 1649330 131100 ) ( 1650250 * )
+      NEW met1 ( 109250 31110 ) ( 1649330 * )
+      NEW met1 ( 109250 31110 ) M1M2_PR
+      NEW met1 ( 1649330 31110 ) M1M2_PR ;
+    - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( inst_eFPGA_CPU_top wbs_adr_i[4] ) + USE SIGNAL
+      + ROUTED met2 ( 132710 1700 0 ) ( * 31450 )
+      NEW met1 ( 132710 31450 ) ( 1621730 * )
+      NEW met2 ( 1621730 31450 ) ( * 131100 )
+      NEW met2 ( 1625170 149260 ) ( * 150240 0 )
+      NEW met2 ( 1624950 149260 ) ( 1625170 * )
+      NEW met2 ( 1624950 131100 ) ( * 149260 )
+      NEW met2 ( 1621730 131100 ) ( 1624950 * )
+      NEW met1 ( 132710 31450 ) M1M2_PR
+      NEW met1 ( 1621730 31450 ) M1M2_PR ;
+    - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( inst_eFPGA_CPU_top wbs_adr_i[5] ) + USE SIGNAL
+      + ROUTED met2 ( 150650 1700 0 ) ( * 31790 )
+      NEW met1 ( 150650 31790 ) ( 1594130 * )
+      NEW met2 ( 1599870 149090 ) ( * 150240 0 )
+      NEW met1 ( 1594130 149090 ) ( 1599870 * )
+      NEW met2 ( 1594130 31790 ) ( * 149090 )
+      NEW met1 ( 150650 31790 ) M1M2_PR
+      NEW met1 ( 1594130 31790 ) M1M2_PR
+      NEW met1 ( 1599870 149090 ) M1M2_PR
+      NEW met1 ( 1594130 149090 ) M1M2_PR ;
+    - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( inst_eFPGA_CPU_top wbs_adr_i[6] ) + USE SIGNAL
+      + ROUTED met2 ( 1573430 92990 ) ( * 131100 )
+      NEW met2 ( 1574570 149260 ) ( * 150240 0 )
+      NEW met2 ( 1574350 149260 ) ( 1574570 * )
+      NEW met2 ( 1574350 131100 ) ( * 149260 )
+      NEW met2 ( 1573430 131100 ) ( 1574350 * )
+      NEW met1 ( 165830 92990 ) ( 1573430 * )
+      NEW met2 ( 165830 82800 ) ( * 92990 )
+      NEW met2 ( 165830 82800 ) ( 168130 * )
+      NEW met2 ( 168130 1700 0 ) ( * 82800 )
+      NEW met1 ( 1573430 92990 ) M1M2_PR
+      NEW met1 ( 165830 92990 ) M1M2_PR ;
+    - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( inst_eFPGA_CPU_top wbs_adr_i[7] ) + USE SIGNAL
+      + ROUTED met2 ( 186070 1700 0 ) ( * 13770 )
+      NEW met1 ( 179630 13770 ) ( 186070 * )
+      NEW met2 ( 179630 13770 ) ( * 86530 )
+      NEW met2 ( 1545830 86530 ) ( * 131100 )
+      NEW met2 ( 1549270 149260 ) ( * 150240 0 )
+      NEW met2 ( 1549050 149260 ) ( 1549270 * )
+      NEW met2 ( 1549050 131100 ) ( * 149260 )
+      NEW met2 ( 1545830 131100 ) ( 1549050 * )
+      NEW met1 ( 179630 86530 ) ( 1545830 * )
+      NEW met1 ( 186070 13770 ) M1M2_PR
+      NEW met1 ( 179630 13770 ) M1M2_PR
+      NEW met1 ( 179630 86530 ) M1M2_PR
+      NEW met1 ( 1545830 86530 ) M1M2_PR ;
+    - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ( inst_eFPGA_CPU_top wbs_adr_i[8] ) + USE SIGNAL
+      + ROUTED met2 ( 200330 82800 ) ( * 99790 )
+      NEW met2 ( 200330 82800 ) ( 203550 * )
+      NEW met2 ( 203550 1700 0 ) ( * 82800 )
+      NEW met1 ( 200330 99790 ) ( 1518230 * )
+      NEW met2 ( 1523970 149090 ) ( * 150240 0 )
+      NEW met1 ( 1518230 149090 ) ( 1523970 * )
+      NEW met2 ( 1518230 99790 ) ( * 149090 )
+      NEW met1 ( 200330 99790 ) M1M2_PR
+      NEW met1 ( 1518230 99790 ) M1M2_PR
+      NEW met1 ( 1523970 149090 ) M1M2_PR
+      NEW met1 ( 1518230 149090 ) M1M2_PR ;
+    - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ( inst_eFPGA_CPU_top wbs_adr_i[9] ) + USE SIGNAL
+      + ROUTED met2 ( 221490 1700 0 ) ( * 65790 )
+      NEW met1 ( 221490 65790 ) ( 1497530 * )
+      NEW met2 ( 1497530 65790 ) ( * 131100 )
+      NEW met2 ( 1498670 149260 ) ( * 150240 0 )
+      NEW met2 ( 1498450 149260 ) ( 1498670 * )
+      NEW met2 ( 1498450 131100 ) ( * 149260 )
+      NEW met2 ( 1497530 131100 ) ( 1498450 * )
+      NEW met1 ( 221490 65790 ) M1M2_PR
+      NEW met1 ( 1497530 65790 ) M1M2_PR ;
+    - wbs_cyc_i ( PIN wbs_cyc_i ) ( inst_eFPGA_CPU_top wbs_cyc_i ) + USE SIGNAL
+      + ROUTED met2 ( 20470 1700 0 ) ( * 17510 )
+      NEW met1 ( 14030 17510 ) ( 20470 * )
+      NEW met2 ( 14030 17510 ) ( * 134470 )
+      NEW met2 ( 80950 149260 ) ( * 150240 0 )
+      NEW met2 ( 80730 149260 ) ( 80950 * )
+      NEW met2 ( 80730 134470 ) ( * 149260 )
+      NEW met1 ( 14030 134470 ) ( 80730 * )
+      NEW met1 ( 20470 17510 ) M1M2_PR
+      NEW met1 ( 14030 17510 ) M1M2_PR
+      NEW met1 ( 14030 134470 ) M1M2_PR
+      NEW met1 ( 80730 134470 ) M1M2_PR ;
+    - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( inst_eFPGA_CPU_top wbs_dat_i[0] ) + USE SIGNAL
+      + ROUTED met2 ( 43930 1700 0 ) ( * 16150 )
+      NEW met1 ( 43930 16150 ) ( 58650 * )
+      NEW met1 ( 58650 114070 ) ( 911030 * )
+      NEW met2 ( 58650 16150 ) ( * 114070 )
+      NEW met2 ( 911030 114070 ) ( * 131100 )
+      NEW met2 ( 916310 149260 ) ( * 150240 0 )
+      NEW met2 ( 916090 149260 ) ( 916310 * )
+      NEW met2 ( 916090 131100 ) ( * 149260 )
+      NEW met2 ( 911030 131100 ) ( 916090 * )
+      NEW met1 ( 43930 16150 ) M1M2_PR
+      NEW met1 ( 58650 16150 ) M1M2_PR
+      NEW met1 ( 58650 114070 ) M1M2_PR
+      NEW met1 ( 911030 114070 ) M1M2_PR ;
+    - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( inst_eFPGA_CPU_top wbs_dat_i[10] ) + USE SIGNAL
+      + ROUTED met2 ( 662850 149260 ) ( * 150240 0 )
+      NEW met2 ( 662630 149260 ) ( 662850 * )
+      NEW met2 ( 662630 44710 ) ( * 149260 )
+      NEW met2 ( 244950 1700 0 ) ( * 44710 )
+      NEW met1 ( 244950 44710 ) ( 662630 * )
+      NEW met1 ( 662630 44710 ) M1M2_PR
+      NEW met1 ( 244950 44710 ) M1M2_PR ;
+    - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( inst_eFPGA_CPU_top wbs_dat_i[11] ) + USE SIGNAL
+      + ROUTED met1 ( 262890 106930 ) ( 635030 * )
+      NEW met2 ( 262890 1700 0 ) ( * 106930 )
+      NEW met2 ( 635030 106930 ) ( * 131100 )
+      NEW met2 ( 637550 149260 ) ( * 150240 0 )
+      NEW met2 ( 637330 149260 ) ( 637550 * )
+      NEW met2 ( 637330 131100 ) ( * 149260 )
+      NEW met2 ( 635030 131100 ) ( 637330 * )
+      NEW met1 ( 262890 106930 ) M1M2_PR
+      NEW met1 ( 635030 106930 ) M1M2_PR ;
+    - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( inst_eFPGA_CPU_top wbs_dat_i[12] ) + USE SIGNAL
+      + ROUTED met2 ( 280370 1700 0 ) ( * 37910 )
+      NEW met2 ( 607430 37910 ) ( * 131100 )
+      NEW met2 ( 612250 149260 ) ( * 150240 0 )
+      NEW met2 ( 612030 149260 ) ( 612250 * )
+      NEW met2 ( 612030 131100 ) ( * 149260 )
+      NEW met2 ( 607430 131100 ) ( 612030 * )
+      NEW met1 ( 280370 37910 ) ( 607430 * )
+      NEW met1 ( 280370 37910 ) M1M2_PR
+      NEW met1 ( 607430 37910 ) M1M2_PR ;
+    - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( inst_eFPGA_CPU_top wbs_dat_i[13] ) + USE SIGNAL
+      + ROUTED met2 ( 298310 1700 0 ) ( * 52190 )
+      NEW met2 ( 586950 149260 ) ( * 150240 0 )
+      NEW met2 ( 586730 149260 ) ( 586950 * )
+      NEW met2 ( 586730 52190 ) ( * 149260 )
+      NEW met1 ( 298310 52190 ) ( 586730 * )
+      NEW met1 ( 298310 52190 ) M1M2_PR
+      NEW met1 ( 586730 52190 ) M1M2_PR ;
+    - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( inst_eFPGA_CPU_top wbs_dat_i[14] ) + USE SIGNAL
+      + ROUTED met2 ( 316250 1700 0 ) ( * 58650 )
+      NEW met1 ( 316250 58650 ) ( 559590 * )
+      NEW met2 ( 559590 58650 ) ( * 131100 )
+      NEW met2 ( 561650 149260 ) ( * 150240 0 )
+      NEW met2 ( 561430 149260 ) ( 561650 * )
+      NEW met2 ( 561430 131100 ) ( * 149260 )
+      NEW met2 ( 559590 131100 ) ( 561430 * )
+      NEW met1 ( 316250 58650 ) M1M2_PR
+      NEW met1 ( 559590 58650 ) M1M2_PR ;
+    - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( inst_eFPGA_CPU_top wbs_dat_i[15] ) + USE SIGNAL
+      + ROUTED met2 ( 333730 1700 0 ) ( * 38590 )
+      NEW met1 ( 333730 38590 ) ( 531990 * )
+      NEW met2 ( 531990 38590 ) ( * 131100 )
+      NEW met2 ( 536350 149260 ) ( * 150240 0 )
+      NEW met2 ( 536130 149260 ) ( 536350 * )
+      NEW met2 ( 536130 131100 ) ( * 149260 )
+      NEW met2 ( 531990 131100 ) ( 536130 * )
+      NEW met1 ( 333730 38590 ) M1M2_PR
+      NEW met1 ( 531990 38590 ) M1M2_PR ;
+    - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( inst_eFPGA_CPU_top wbs_dat_i[16] ) + USE SIGNAL
+      + ROUTED met2 ( 511050 149260 ) ( * 150240 0 )
+      NEW met2 ( 510830 149260 ) ( 511050 * )
+      NEW met2 ( 510830 121550 ) ( * 149260 )
+      NEW met2 ( 351670 1700 0 ) ( * 16830 )
+      NEW met1 ( 345230 16830 ) ( 351670 * )
+      NEW met1 ( 345230 121550 ) ( 510830 * )
+      NEW met2 ( 345230 16830 ) ( * 121550 )
+      NEW met1 ( 510830 121550 ) M1M2_PR
+      NEW met1 ( 351670 16830 ) M1M2_PR
+      NEW met1 ( 345230 16830 ) M1M2_PR
+      NEW met1 ( 345230 121550 ) M1M2_PR ;
+    - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( inst_eFPGA_CPU_top wbs_dat_i[17] ) + USE SIGNAL
+      + ROUTED met2 ( 483230 45390 ) ( * 131100 )
+      NEW met2 ( 485750 149260 ) ( * 150240 0 )
+      NEW met2 ( 485530 149260 ) ( 485750 * )
+      NEW met2 ( 485530 131100 ) ( * 149260 )
+      NEW met2 ( 483230 131100 ) ( 485530 * )
+      NEW met2 ( 369150 1700 0 ) ( * 45390 )
+      NEW met1 ( 369150 45390 ) ( 483230 * )
+      NEW met1 ( 483230 45390 ) M1M2_PR
+      NEW met1 ( 369150 45390 ) M1M2_PR ;
+    - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( inst_eFPGA_CPU_top wbs_dat_i[18] ) + USE SIGNAL
+      + ROUTED met2 ( 387090 1700 0 ) ( * 52530 )
+      NEW met1 ( 387090 52530 ) ( 451950 * )
+      NEW met2 ( 460450 149260 ) ( * 150240 0 )
+      NEW met2 ( 460230 149260 ) ( 460450 * )
+      NEW met2 ( 460230 137870 ) ( * 149260 )
+      NEW met1 ( 451950 137870 ) ( 460230 * )
+      NEW met2 ( 451950 52530 ) ( * 137870 )
+      NEW met1 ( 387090 52530 ) M1M2_PR
+      NEW met1 ( 451950 52530 ) M1M2_PR
+      NEW met1 ( 460230 137870 ) M1M2_PR
+      NEW met1 ( 451950 137870 ) M1M2_PR ;
+    - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( inst_eFPGA_CPU_top wbs_dat_i[19] ) + USE SIGNAL
+      + ROUTED met2 ( 404570 1700 0 ) ( * 80070 )
+      NEW met1 ( 404570 80070 ) ( 434930 * )
+      NEW met2 ( 435150 149260 ) ( * 150240 0 )
+      NEW met2 ( 434930 149260 ) ( 435150 * )
+      NEW met2 ( 434930 80070 ) ( * 149260 )
+      NEW met1 ( 404570 80070 ) M1M2_PR
+      NEW met1 ( 434930 80070 ) M1M2_PR ;
+    - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( inst_eFPGA_CPU_top wbs_dat_i[1] ) + USE SIGNAL
+      + ROUTED met2 ( 890330 79390 ) ( * 131100 )
+      NEW met2 ( 891010 149260 ) ( * 150240 0 )
+      NEW met2 ( 890790 149260 ) ( 891010 * )
+      NEW met2 ( 890790 131100 ) ( * 149260 )
+      NEW met2 ( 890330 131100 ) ( 890790 * )
+      NEW met2 ( 67850 1700 0 ) ( * 17510 )
       NEW met1 ( 67850 17510 ) ( 72450 * )
-      NEW met1 ( 72450 1672970 ) ( 1194390 * )
-      NEW met2 ( 72450 17510 ) ( * 1672970 )
-      NEW met2 ( 1194390 1690140 ) ( 1195540 * 0 )
-      NEW met2 ( 1194390 1672970 ) ( * 1690140 )
+      NEW met2 ( 72450 17510 ) ( * 79390 )
+      NEW met1 ( 72450 79390 ) ( 890330 * )
+      NEW met1 ( 890330 79390 ) M1M2_PR
       NEW met1 ( 67850 17510 ) M1M2_PR
       NEW met1 ( 72450 17510 ) M1M2_PR
-      NEW met1 ( 72450 1672970 ) M1M2_PR
-      NEW met1 ( 1194390 1672970 ) M1M2_PR ;
-    - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mprj wbs_dat_i[20] ) + USE SIGNAL
-      + ROUTED met2 ( 422510 2380 0 ) ( * 16830 )
-      NEW met1 ( 422510 16830 ) ( 438150 * )
-      NEW met1 ( 438150 1666510 ) ( 1304790 * )
-      NEW met2 ( 438150 16830 ) ( * 1666510 )
-      NEW met2 ( 1304790 1690140 ) ( 1305020 * 0 )
-      NEW met2 ( 1304790 1666510 ) ( * 1690140 )
-      NEW met1 ( 422510 16830 ) M1M2_PR
-      NEW met1 ( 438150 16830 ) M1M2_PR
-      NEW met1 ( 438150 1666510 ) M1M2_PR
-      NEW met1 ( 1304790 1666510 ) M1M2_PR ;
-    - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mprj wbs_dat_i[21] ) + USE SIGNAL
-      + ROUTED met2 ( 439990 2380 0 ) ( * 16830 )
-      NEW met1 ( 439990 16830 ) ( 445050 * )
-      NEW met1 ( 445050 1674330 ) ( 1309390 * )
-      NEW met2 ( 445050 16830 ) ( * 1674330 )
-      NEW met2 ( 1309390 1690140 ) ( 1310540 * 0 )
-      NEW met2 ( 1309390 1674330 ) ( * 1690140 )
-      NEW met1 ( 439990 16830 ) M1M2_PR
-      NEW met1 ( 445050 16830 ) M1M2_PR
-      NEW met1 ( 445050 1674330 ) M1M2_PR
-      NEW met1 ( 1309390 1674330 ) M1M2_PR ;
-    - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mprj wbs_dat_i[22] ) + USE SIGNAL
-      + ROUTED met2 ( 457930 2380 0 ) ( * 16830 )
-      NEW met1 ( 457930 16830 ) ( 465750 * )
-      NEW met1 ( 465750 1666850 ) ( 1314910 * )
-      NEW met2 ( 465750 16830 ) ( * 1666850 )
-      NEW met2 ( 1314910 1690140 ) ( 1316060 * 0 )
-      NEW met2 ( 1314910 1666850 ) ( * 1690140 )
-      NEW met1 ( 457930 16830 ) M1M2_PR
-      NEW met1 ( 465750 16830 ) M1M2_PR
-      NEW met1 ( 465750 1666850 ) M1M2_PR
-      NEW met1 ( 1314910 1666850 ) M1M2_PR ;
-    - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mprj wbs_dat_i[23] ) + USE SIGNAL
-      + ROUTED met2 ( 475870 2380 0 ) ( * 1660390 )
-      NEW met1 ( 475870 1660390 ) ( 1320430 * )
-      NEW met2 ( 1320430 1690140 ) ( 1321580 * 0 )
-      NEW met2 ( 1320430 1660390 ) ( * 1690140 )
-      NEW met1 ( 475870 1660390 ) M1M2_PR
-      NEW met1 ( 1320430 1660390 ) M1M2_PR ;
-    - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mprj wbs_dat_i[24] ) + USE SIGNAL
-      + ROUTED met2 ( 493350 2380 0 ) ( * 16490 )
-      NEW met1 ( 493350 16490 ) ( 496570 * )
-      NEW met2 ( 496570 16490 ) ( * 1653590 )
-      NEW met1 ( 496570 1653590 ) ( 1324570 * )
-      NEW met1 ( 1324570 1680790 ) ( 1326410 * )
-      NEW met2 ( 1326410 1680790 ) ( * 1690140 )
-      NEW met2 ( 1326410 1690140 ) ( 1327100 * 0 )
-      NEW met2 ( 1324570 1653590 ) ( * 1680790 )
-      NEW met1 ( 493350 16490 ) M1M2_PR
-      NEW met1 ( 496570 16490 ) M1M2_PR
-      NEW met1 ( 496570 1653590 ) M1M2_PR
-      NEW met1 ( 1324570 1653590 ) M1M2_PR
-      NEW met1 ( 1324570 1680790 ) M1M2_PR
-      NEW met1 ( 1326410 1680790 ) M1M2_PR ;
-    - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mprj wbs_dat_i[25] ) + USE SIGNAL
-      + ROUTED met2 ( 511290 2380 0 ) ( * 15470 )
-      NEW met1 ( 511290 15470 ) ( 520950 * )
-      NEW met1 ( 520950 1660730 ) ( 1331930 * )
-      NEW met2 ( 520950 15470 ) ( * 1660730 )
-      NEW met2 ( 1331930 1690140 ) ( 1332620 * 0 )
-      NEW met2 ( 1331930 1660730 ) ( * 1690140 )
-      NEW met1 ( 511290 15470 ) M1M2_PR
-      NEW met1 ( 520950 15470 ) M1M2_PR
-      NEW met1 ( 520950 1660730 ) M1M2_PR
-      NEW met1 ( 1331930 1660730 ) M1M2_PR ;
-    - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mprj wbs_dat_i[26] ) + USE SIGNAL
-      + ROUTED met2 ( 528770 2380 0 ) ( * 15470 )
-      NEW met1 ( 528770 15470 ) ( 531070 * )
-      NEW met1 ( 531070 1667190 ) ( 1336990 * )
-      NEW met2 ( 531070 15470 ) ( * 1667190 )
-      NEW met2 ( 1336990 1690140 ) ( 1338140 * 0 )
-      NEW met2 ( 1336990 1667190 ) ( * 1690140 )
-      NEW met1 ( 528770 15470 ) M1M2_PR
-      NEW met1 ( 531070 15470 ) M1M2_PR
-      NEW met1 ( 531070 1667190 ) M1M2_PR
-      NEW met1 ( 1336990 1667190 ) M1M2_PR ;
-    - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mprj wbs_dat_i[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1342510 1690140 ) ( 1343660 * 0 )
-      NEW met2 ( 1342510 1653930 ) ( * 1690140 )
-      NEW met2 ( 546710 2380 0 ) ( * 15470 )
-      NEW met1 ( 546710 15470 ) ( 555450 * )
-      NEW met1 ( 555450 1653930 ) ( 1342510 * )
-      NEW met2 ( 555450 15470 ) ( * 1653930 )
-      NEW met1 ( 1342510 1653930 ) M1M2_PR
-      NEW met1 ( 546710 15470 ) M1M2_PR
-      NEW met1 ( 555450 15470 ) M1M2_PR
-      NEW met1 ( 555450 1653930 ) M1M2_PR ;
-    - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mprj wbs_dat_i[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1348030 1690140 ) ( 1349180 * 0 )
-      NEW met2 ( 1348030 1654270 ) ( * 1690140 )
-      NEW met1 ( 565570 1654270 ) ( 1348030 * )
-      NEW met2 ( 564190 2380 0 ) ( * 34500 )
-      NEW met2 ( 564190 34500 ) ( 565570 * )
-      NEW met2 ( 565570 34500 ) ( * 1654270 )
-      NEW met1 ( 1348030 1654270 ) M1M2_PR
-      NEW met1 ( 565570 1654270 ) M1M2_PR ;
-    - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mprj wbs_dat_i[29] ) + USE SIGNAL
-      + ROUTED met2 ( 582130 2380 0 ) ( * 14450 )
-      NEW met1 ( 582130 14450 ) ( 586270 * )
-      NEW met2 ( 586270 14450 ) ( * 1654610 )
-      NEW met2 ( 1354470 1690140 ) ( 1354700 * 0 )
-      NEW met2 ( 1354470 1654610 ) ( * 1690140 )
-      NEW met1 ( 586270 1654610 ) ( 1354470 * )
-      NEW met1 ( 582130 14450 ) M1M2_PR
-      NEW met1 ( 586270 14450 ) M1M2_PR
-      NEW met1 ( 586270 1654610 ) M1M2_PR
-      NEW met1 ( 1354470 1654610 ) M1M2_PR ;
-    - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mprj wbs_dat_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 91310 2380 0 ) ( * 16490 )
-      NEW met1 ( 91310 16490 ) ( 113850 * )
-      NEW met2 ( 113850 16490 ) ( * 1645430 )
-      NEW met1 ( 113850 1645430 ) ( 1201750 * )
-      NEW met2 ( 1201750 1690140 ) ( 1202900 * 0 )
-      NEW met2 ( 1201750 1645430 ) ( * 1690140 )
-      NEW met1 ( 91310 16490 ) M1M2_PR
-      NEW met1 ( 113850 16490 ) M1M2_PR
-      NEW met1 ( 113850 1645430 ) M1M2_PR
-      NEW met1 ( 1201750 1645430 ) M1M2_PR ;
-    - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mprj wbs_dat_i[30] ) + USE SIGNAL
-      + ROUTED met2 ( 599610 2380 0 ) ( * 34500 )
-      NEW met2 ( 599610 34500 ) ( 600070 * )
-      NEW met2 ( 600070 34500 ) ( * 1647130 )
-      NEW met1 ( 1345730 1681810 ) ( 1359530 * )
-      NEW met2 ( 1359530 1681810 ) ( * 1690140 )
-      NEW met2 ( 1359530 1690140 ) ( 1359760 * 0 )
-      NEW met2 ( 1345730 1647130 ) ( * 1681810 )
-      NEW met1 ( 600070 1647130 ) ( 1345730 * )
-      NEW met1 ( 600070 1647130 ) M1M2_PR
-      NEW met1 ( 1345730 1647130 ) M1M2_PR
-      NEW met1 ( 1345730 1681810 ) M1M2_PR
-      NEW met1 ( 1359530 1681810 ) M1M2_PR ;
-    - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mprj wbs_dat_i[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1364130 1690140 ) ( 1365280 * 0 )
-      NEW met2 ( 1364130 1661070 ) ( * 1690140 )
-      NEW met1 ( 620770 1661070 ) ( 1364130 * )
-      NEW met2 ( 617550 2380 0 ) ( * 34500 )
-      NEW met2 ( 617550 34500 ) ( 620770 * )
-      NEW met2 ( 620770 34500 ) ( * 1661070 )
-      NEW met1 ( 1364130 1661070 ) M1M2_PR
-      NEW met1 ( 620770 1661070 ) M1M2_PR ;
-    - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mprj wbs_dat_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 115230 2380 0 ) ( * 15470 )
-      NEW met1 ( 115230 15470 ) ( 127650 * )
-      NEW met2 ( 127650 15470 ) ( * 1666170 )
-      NEW met1 ( 127650 1666170 ) ( 1209110 * )
-      NEW met2 ( 1209110 1690140 ) ( 1210260 * 0 )
-      NEW met2 ( 1209110 1666170 ) ( * 1690140 )
-      NEW met1 ( 115230 15470 ) M1M2_PR
-      NEW met1 ( 127650 15470 ) M1M2_PR
-      NEW met1 ( 127650 1666170 ) M1M2_PR
-      NEW met1 ( 1209110 1666170 ) M1M2_PR ;
-    - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mprj wbs_dat_i[4] ) + USE SIGNAL
-      + ROUTED met2 ( 138690 2380 0 ) ( * 18190 )
-      NEW met1 ( 138690 18190 ) ( 162150 * )
-      NEW met1 ( 162150 1673310 ) ( 1216470 * )
-      NEW met2 ( 162150 18190 ) ( * 1673310 )
-      NEW met2 ( 1216470 1690140 ) ( 1217620 * 0 )
-      NEW met2 ( 1216470 1673310 ) ( * 1690140 )
-      NEW met1 ( 138690 18190 ) M1M2_PR
-      NEW met1 ( 162150 18190 ) M1M2_PR
-      NEW met1 ( 162150 1673310 ) M1M2_PR
-      NEW met1 ( 1216470 1673310 ) M1M2_PR ;
-    - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mprj wbs_dat_i[5] ) + USE SIGNAL
-      + ROUTED met2 ( 196650 18190 ) ( * 1652570 )
-      NEW met2 ( 156630 2380 0 ) ( * 16490 )
-      NEW met1 ( 156630 16490 ) ( 162610 * )
-      NEW li1 ( 162610 16490 ) ( * 18190 )
-      NEW met1 ( 162610 18190 ) ( 196650 * )
-      NEW met1 ( 196650 1652570 ) ( 1193700 * )
-      NEW met1 ( 1193700 1652230 ) ( * 1652570 )
-      NEW met1 ( 1193700 1652230 ) ( 1222450 * )
-      NEW met2 ( 1222450 1690140 ) ( 1223140 * 0 )
-      NEW met2 ( 1222450 1652230 ) ( * 1690140 )
-      NEW met1 ( 196650 18190 ) M1M2_PR
-      NEW met1 ( 196650 1652570 ) M1M2_PR
-      NEW met1 ( 156630 16490 ) M1M2_PR
-      NEW li1 ( 162610 16490 ) L1M1_PR_MR
-      NEW li1 ( 162610 18190 ) L1M1_PR_MR
-      NEW met1 ( 1222450 1652230 ) M1M2_PR ;
-    - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mprj wbs_dat_i[6] ) + USE SIGNAL
-      + ROUTED met2 ( 174110 2380 0 ) ( * 18870 )
-      NEW met1 ( 174110 18870 ) ( 251850 * )
-      NEW met1 ( 251850 1646110 ) ( 1228430 * )
-      NEW met2 ( 251850 18870 ) ( * 1646110 )
-      NEW met2 ( 1228430 1690140 ) ( 1228660 * 0 )
-      NEW met2 ( 1228430 1646110 ) ( * 1690140 )
-      NEW met1 ( 174110 18870 ) M1M2_PR
-      NEW met1 ( 251850 18870 ) M1M2_PR
-      NEW met1 ( 251850 1646110 ) M1M2_PR
-      NEW met1 ( 1228430 1646110 ) M1M2_PR ;
-    - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mprj wbs_dat_i[7] ) + USE SIGNAL
-      + ROUTED met2 ( 192050 2380 0 ) ( * 18530 )
-      NEW met1 ( 192050 18530 ) ( 203550 * )
-      NEW met2 ( 203550 18530 ) ( * 1645770 )
-      NEW met1 ( 203550 1645770 ) ( 1233030 * )
-      NEW met2 ( 1233030 1690140 ) ( 1234180 * 0 )
-      NEW met2 ( 1233030 1645770 ) ( * 1690140 )
-      NEW met1 ( 192050 18530 ) M1M2_PR
-      NEW met1 ( 203550 18530 ) M1M2_PR
-      NEW met1 ( 203550 1645770 ) M1M2_PR
-      NEW met1 ( 1233030 1645770 ) M1M2_PR ;
-    - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mprj wbs_dat_i[8] ) + USE SIGNAL
-      + ROUTED met2 ( 209530 2380 0 ) ( * 19890 )
-      NEW met1 ( 209530 19890 ) ( 258750 * )
-      NEW met1 ( 258750 1673650 ) ( 1238090 * )
-      NEW met2 ( 258750 19890 ) ( * 1673650 )
-      NEW met2 ( 1238090 1690140 ) ( 1239240 * 0 )
-      NEW met2 ( 1238090 1673650 ) ( * 1690140 )
-      NEW met1 ( 209530 19890 ) M1M2_PR
-      NEW met1 ( 258750 19890 ) M1M2_PR
-      NEW met1 ( 258750 1673650 ) M1M2_PR
-      NEW met1 ( 1238090 1673650 ) M1M2_PR ;
-    - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mprj wbs_dat_i[9] ) + USE SIGNAL
-      + ROUTED met2 ( 227470 2380 0 ) ( * 9860 )
-      NEW met2 ( 227010 9860 ) ( 227470 * )
-      NEW met2 ( 227010 9860 ) ( * 19210 )
-      NEW met2 ( 285890 19210 ) ( * 34500 )
-      NEW met2 ( 285890 34500 ) ( 286350 * )
-      NEW met2 ( 286350 34500 ) ( * 1646450 )
-      NEW met2 ( 1243610 1690140 ) ( 1244760 * 0 )
-      NEW met2 ( 1243610 1646450 ) ( * 1690140 )
-      NEW met1 ( 227010 19210 ) ( 285890 * )
-      NEW met1 ( 286350 1646450 ) ( 1243610 * )
-      NEW met1 ( 227010 19210 ) M1M2_PR
-      NEW met1 ( 285890 19210 ) M1M2_PR
-      NEW met1 ( 286350 1646450 ) M1M2_PR
-      NEW met1 ( 1243610 1646450 ) M1M2_PR ;
-    - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj wbs_dat_o[0] ) + USE SIGNAL
-      + ROUTED met2 ( 93150 20570 ) ( * 1681300 )
-      NEW met2 ( 1188870 1681300 ) ( * 1690140 )
-      NEW met2 ( 1188870 1690140 ) ( 1190020 * 0 )
-      NEW met2 ( 49910 2380 0 ) ( * 20570 )
-      NEW met1 ( 49910 20570 ) ( 93150 * )
-      NEW met3 ( 93150 1681300 ) ( 1188870 * )
-      NEW met1 ( 93150 20570 ) M1M2_PR
-      NEW met2 ( 93150 1681300 ) M2M3_PR_M
-      NEW met2 ( 1188870 1681300 ) M2M3_PR_M
-      NEW met1 ( 49910 20570 ) M1M2_PR ;
-    - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ( mprj wbs_dat_o[10] ) + USE SIGNAL
-      + ROUTED met2 ( 1250970 1690140 ) ( 1252120 * 0 )
-      NEW met2 ( 1250970 1659370 ) ( * 1690140 )
-      NEW met2 ( 250930 2380 0 ) ( * 15810 )
-      NEW met1 ( 250930 15810 ) ( 272550 * )
-      NEW met1 ( 272550 1659370 ) ( 1250970 * )
-      NEW met2 ( 272550 15810 ) ( * 1659370 )
-      NEW met1 ( 1250970 1659370 ) M1M2_PR
-      NEW met1 ( 250930 15810 ) M1M2_PR
-      NEW met1 ( 272550 15810 ) M1M2_PR
-      NEW met1 ( 272550 1659370 ) M1M2_PR ;
-    - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ( mprj wbs_dat_o[11] ) + USE SIGNAL
-      + ROUTED met2 ( 293250 18870 ) ( * 1652910 )
-      NEW met2 ( 1256950 1690140 ) ( 1257640 * 0 )
-      NEW met2 ( 1256950 1652910 ) ( * 1690140 )
-      NEW met2 ( 268870 2380 0 ) ( * 9860 )
-      NEW met2 ( 268410 9860 ) ( 268870 * )
-      NEW met2 ( 268410 9860 ) ( * 18870 )
-      NEW met1 ( 268410 18870 ) ( 293250 * )
-      NEW met1 ( 293250 1652910 ) ( 1256950 * )
-      NEW met1 ( 293250 18870 ) M1M2_PR
-      NEW met1 ( 293250 1652910 ) M1M2_PR
-      NEW met1 ( 1256950 1652910 ) M1M2_PR
-      NEW met1 ( 268410 18870 ) M1M2_PR ;
-    - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ( mprj wbs_dat_o[12] ) + USE SIGNAL
-      + ROUTED met2 ( 286350 2380 0 ) ( * 15810 )
-      NEW met1 ( 286350 15810 ) ( 307050 * )
-      NEW met2 ( 307050 15810 ) ( * 1659710 )
-      NEW met2 ( 1262930 1690140 ) ( 1263160 * 0 )
-      NEW met2 ( 1262930 1659710 ) ( * 1690140 )
-      NEW met1 ( 307050 1659710 ) ( 1262930 * )
-      NEW met1 ( 286350 15810 ) M1M2_PR
-      NEW met1 ( 307050 15810 ) M1M2_PR
-      NEW met1 ( 307050 1659710 ) M1M2_PR
-      NEW met1 ( 1262930 1659710 ) M1M2_PR ;
-    - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ( mprj wbs_dat_o[13] ) + USE SIGNAL
-      + ROUTED met2 ( 304290 2380 0 ) ( * 19550 )
-      NEW met2 ( 1267530 1690140 ) ( 1268680 * 0 )
-      NEW met2 ( 1267530 1646790 ) ( * 1690140 )
-      NEW met1 ( 304290 19550 ) ( 341550 * )
-      NEW met1 ( 341550 1646790 ) ( 1267530 * )
-      NEW met2 ( 341550 19550 ) ( * 1646790 )
-      NEW met1 ( 304290 19550 ) M1M2_PR
-      NEW met1 ( 1267530 1646790 ) M1M2_PR
-      NEW met1 ( 341550 19550 ) M1M2_PR
-      NEW met1 ( 341550 1646790 ) M1M2_PR ;
-    - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ( mprj wbs_dat_o[14] ) + USE SIGNAL
-      + ROUTED met2 ( 321770 2380 0 ) ( * 18870 )
-      NEW met1 ( 1269830 1652230 ) ( 1273050 * )
-      NEW met2 ( 1269830 18870 ) ( * 1652230 )
-      NEW met2 ( 1273050 1690140 ) ( 1274200 * 0 )
-      NEW met2 ( 1273050 1652230 ) ( * 1690140 )
-      NEW met1 ( 321770 18870 ) ( 1269830 * )
-      NEW met1 ( 321770 18870 ) M1M2_PR
-      NEW met1 ( 1269830 18870 ) M1M2_PR
-      NEW met1 ( 1269830 1652230 ) M1M2_PR
-      NEW met1 ( 1273050 1652230 ) M1M2_PR ;
-    - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ( mprj wbs_dat_o[15] ) + USE SIGNAL
-      + ROUTED met1 ( 1276730 1652570 ) ( 1278570 * )
-      NEW met2 ( 1276730 19210 ) ( * 1652570 )
-      NEW met2 ( 1278570 1690140 ) ( 1279720 * 0 )
-      NEW met2 ( 1278570 1652570 ) ( * 1690140 )
-      NEW met2 ( 339710 2380 0 ) ( * 19210 )
-      NEW met1 ( 339710 19210 ) ( 1276730 * )
-      NEW met1 ( 1276730 19210 ) M1M2_PR
-      NEW met1 ( 1276730 1652570 ) M1M2_PR
-      NEW met1 ( 1278570 1652570 ) M1M2_PR
-      NEW met1 ( 339710 19210 ) M1M2_PR ;
-    - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ( mprj wbs_dat_o[16] ) + USE SIGNAL
-      + ROUTED met2 ( 1283630 1683340 ) ( 1284090 * )
-      NEW met2 ( 1284090 1683340 ) ( * 1690140 )
-      NEW met2 ( 1284090 1690140 ) ( 1285240 * 0 )
-      NEW met2 ( 1283630 19550 ) ( * 1683340 )
-      NEW met2 ( 357650 2380 0 ) ( * 19550 )
-      NEW met1 ( 357650 19550 ) ( 1283630 * )
-      NEW met1 ( 1283630 19550 ) M1M2_PR
-      NEW met1 ( 357650 19550 ) M1M2_PR ;
-    - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ( mprj wbs_dat_o[17] ) + USE SIGNAL
-      + ROUTED met2 ( 375130 2380 0 ) ( * 19890 )
-      NEW met1 ( 375130 19890 ) ( 1290990 * )
-      NEW met2 ( 1290760 1688780 ) ( 1290990 * )
-      NEW met2 ( 1290760 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1290990 19890 ) ( * 1688780 )
-      NEW met1 ( 375130 19890 ) M1M2_PR
-      NEW met1 ( 1290990 19890 ) M1M2_PR ;
-    - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ( mprj wbs_dat_o[18] ) + USE SIGNAL
-      + ROUTED met2 ( 393070 2380 0 ) ( * 10540 )
-      NEW met2 ( 392610 10540 ) ( 393070 * )
-      NEW met2 ( 392610 10540 ) ( * 20570 )
-      NEW met1 ( 392610 20570 ) ( 420210 * )
-      NEW met1 ( 420210 20570 ) ( * 20910 )
-      NEW met1 ( 422510 20230 ) ( * 20910 )
-      NEW met1 ( 420210 20910 ) ( 422510 * )
-      NEW met1 ( 422510 20230 ) ( 1290530 * )
-      NEW met1 ( 1290530 1652570 ) ( 1295130 * )
-      NEW met2 ( 1290530 20230 ) ( * 1652570 )
-      NEW met2 ( 1295130 1690140 ) ( 1295820 * 0 )
-      NEW met2 ( 1295130 1652570 ) ( * 1690140 )
-      NEW met1 ( 392610 20570 ) M1M2_PR
-      NEW met1 ( 1290530 20230 ) M1M2_PR
-      NEW met1 ( 1290530 1652570 ) M1M2_PR
-      NEW met1 ( 1295130 1652570 ) M1M2_PR ;
-    - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ( mprj wbs_dat_o[19] ) + USE SIGNAL
-      + ROUTED met2 ( 410550 2380 0 ) ( * 20230 )
-      NEW li1 ( 421590 20230 ) ( * 20570 )
-      NEW li1 ( 421590 20570 ) ( 422970 * )
-      NEW met1 ( 410550 20230 ) ( 421590 * )
-      NEW met1 ( 422970 20570 ) ( 1298810 * )
-      NEW met2 ( 1298810 20570 ) ( * 1580100 )
-      NEW met2 ( 1298810 1580100 ) ( 1300190 * )
-      NEW met2 ( 1300190 1690140 ) ( 1301340 * 0 )
-      NEW met2 ( 1300190 1580100 ) ( * 1690140 )
-      NEW met1 ( 410550 20230 ) M1M2_PR
-      NEW li1 ( 421590 20230 ) L1M1_PR_MR
-      NEW li1 ( 422970 20570 ) L1M1_PR_MR
-      NEW met1 ( 1298810 20570 ) M1M2_PR ;
-    - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj wbs_dat_o[1] ) + USE SIGNAL
-      + ROUTED met2 ( 73830 2380 0 ) ( * 17340 )
-      NEW met3 ( 73830 17340 ) ( 1194390 * )
-      NEW met2 ( 1194390 1652570 ) ( 1194850 * )
-      NEW met2 ( 1194390 17340 ) ( * 1652570 )
-      NEW met2 ( 1194850 1652570 ) ( * 1676700 )
-      NEW met2 ( 1194850 1676700 ) ( 1196230 * )
-      NEW met2 ( 1196230 1676700 ) ( * 1690140 )
-      NEW met2 ( 1196230 1690140 ) ( 1197380 * 0 )
-      NEW met2 ( 73830 17340 ) M2M3_PR_M
-      NEW met2 ( 1194390 17340 ) M2M3_PR_M ;
-    - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ( mprj wbs_dat_o[20] ) + USE SIGNAL
-      + ROUTED met2 ( 428490 2380 0 ) ( * 16490 )
-      NEW met1 ( 428490 16490 ) ( 469200 * )
-      NEW met1 ( 469200 16490 ) ( * 16830 )
-      NEW met1 ( 469200 16830 ) ( 1305250 * )
-      NEW met2 ( 1305250 16830 ) ( * 1580100 )
-      NEW met2 ( 1305250 1580100 ) ( 1305710 * )
-      NEW met2 ( 1305710 1690140 ) ( 1306860 * 0 )
-      NEW met2 ( 1305710 1580100 ) ( * 1690140 )
-      NEW met1 ( 428490 16490 ) M1M2_PR
-      NEW met1 ( 1305250 16830 ) M1M2_PR ;
-    - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ( mprj wbs_dat_o[21] ) + USE SIGNAL
-      + ROUTED li1 ( 510830 15470 ) ( * 16490 )
-      NEW met2 ( 445970 2380 0 ) ( * 15470 )
-      NEW met1 ( 445970 15470 ) ( 510830 * )
-      NEW met1 ( 510830 16490 ) ( 1311690 * )
-      NEW met2 ( 1311690 1690140 ) ( 1312380 * 0 )
-      NEW met2 ( 1311690 16490 ) ( * 1690140 )
-      NEW li1 ( 510830 15470 ) L1M1_PR_MR
-      NEW li1 ( 510830 16490 ) L1M1_PR_MR
-      NEW met1 ( 445970 15470 ) M1M2_PR
-      NEW met1 ( 1311690 16490 ) M1M2_PR ;
-    - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ( mprj wbs_dat_o[22] ) + USE SIGNAL
-      + ROUTED met2 ( 463910 2380 0 ) ( * 16150 )
-      NEW met1 ( 463910 16150 ) ( 1312610 * )
-      NEW met2 ( 1312610 16150 ) ( * 1580100 )
-      NEW met2 ( 1312610 1580100 ) ( 1316750 * )
-      NEW met2 ( 1316750 1690140 ) ( 1317900 * 0 )
-      NEW met2 ( 1316750 1580100 ) ( * 1690140 )
-      NEW met1 ( 463910 16150 ) M1M2_PR
-      NEW met1 ( 1312610 16150 ) M1M2_PR ;
-    - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ( mprj wbs_dat_o[23] ) + USE SIGNAL
-      + ROUTED met2 ( 481390 2380 0 ) ( * 15810 )
-      NEW met1 ( 481390 15810 ) ( 1319050 * )
-      NEW met2 ( 1319050 15810 ) ( * 1580100 )
-      NEW met2 ( 1319050 1580100 ) ( 1322270 * )
-      NEW met2 ( 1322270 1690140 ) ( 1323420 * 0 )
-      NEW met2 ( 1322270 1580100 ) ( * 1690140 )
-      NEW met1 ( 481390 15810 ) M1M2_PR
-      NEW met1 ( 1319050 15810 ) M1M2_PR ;
-    - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ( mprj wbs_dat_o[24] ) + USE SIGNAL
-      + ROUTED met2 ( 499330 2380 0 ) ( * 14790 )
-      NEW met1 ( 499330 14790 ) ( 517500 * )
-      NEW met1 ( 517500 14450 ) ( * 14790 )
-      NEW met1 ( 517500 14450 ) ( 555910 * )
-      NEW li1 ( 555910 14450 ) ( * 15470 )
-      NEW met1 ( 555910 15470 ) ( 1326410 * )
-      NEW met2 ( 1326410 15470 ) ( * 1580100 )
-      NEW met2 ( 1326410 1580100 ) ( 1327790 * )
-      NEW met2 ( 1327790 1690140 ) ( 1328940 * 0 )
-      NEW met2 ( 1327790 1580100 ) ( * 1690140 )
-      NEW met1 ( 499330 14790 ) M1M2_PR
-      NEW li1 ( 555910 14450 ) L1M1_PR_MR
-      NEW li1 ( 555910 15470 ) L1M1_PR_MR
-      NEW met1 ( 1326410 15470 ) M1M2_PR ;
-    - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ( mprj wbs_dat_o[25] ) + USE SIGNAL
-      + ROUTED met2 ( 516810 2380 0 ) ( * 15130 )
-      NEW met1 ( 516810 15130 ) ( 1333310 * )
-      NEW met2 ( 1333310 1690140 ) ( 1334460 * 0 )
-      NEW met2 ( 1333310 15130 ) ( * 1690140 )
-      NEW met1 ( 516810 15130 ) M1M2_PR
-      NEW met1 ( 1333310 15130 ) M1M2_PR ;
-    - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ( mprj wbs_dat_o[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1339290 1681130 ) ( * 1690140 )
-      NEW met2 ( 1339290 1690140 ) ( 1339980 * 0 )
-      NEW met2 ( 534750 2380 0 ) ( * 15470 )
-      NEW met1 ( 534750 15470 ) ( 537970 * )
-      NEW met2 ( 537970 15470 ) ( * 1681130 )
-      NEW met1 ( 537970 1681130 ) ( 1339290 * )
-      NEW met1 ( 1339290 1681130 ) M1M2_PR
-      NEW met1 ( 534750 15470 ) M1M2_PR
-      NEW met1 ( 537970 15470 ) M1M2_PR
-      NEW met1 ( 537970 1681130 ) M1M2_PR ;
-    - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ( mprj wbs_dat_o[27] ) + USE SIGNAL
-      + ROUTED met2 ( 1339750 14790 ) ( * 1580100 )
-      NEW met2 ( 1339750 1580100 ) ( 1344350 * )
-      NEW met2 ( 1344350 1690140 ) ( 1345500 * 0 )
-      NEW met2 ( 1344350 1580100 ) ( * 1690140 )
-      NEW met2 ( 552690 2380 0 ) ( * 14790 )
-      NEW met1 ( 552690 14790 ) ( 1339750 * )
-      NEW met1 ( 1339750 14790 ) M1M2_PR
-      NEW met1 ( 552690 14790 ) M1M2_PR ;
-    - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ( mprj wbs_dat_o[28] ) + USE SIGNAL
-      + ROUTED met2 ( 570170 2380 0 ) ( * 14450 )
-      NEW met1 ( 570170 14450 ) ( 572470 * )
-      NEW met2 ( 572470 14450 ) ( * 1681470 )
-      NEW met1 ( 1344350 1680450 ) ( * 1681470 )
-      NEW met1 ( 1344350 1680450 ) ( 1349870 * )
-      NEW met2 ( 1349870 1680450 ) ( * 1690140 )
-      NEW met2 ( 1349870 1690140 ) ( 1351020 * 0 )
-      NEW met1 ( 572470 1681470 ) ( 1344350 * )
-      NEW met1 ( 570170 14450 ) M1M2_PR
-      NEW met1 ( 572470 14450 ) M1M2_PR
-      NEW met1 ( 572470 1681470 ) M1M2_PR
-      NEW met1 ( 1349870 1680450 ) M1M2_PR ;
-    - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ( mprj wbs_dat_o[29] ) + USE SIGNAL
-      + ROUTED met2 ( 588110 2380 0 ) ( * 14110 )
-      NEW met1 ( 588110 14110 ) ( 600530 * )
-      NEW met1 ( 600530 14110 ) ( * 14450 )
-      NEW met2 ( 1354010 14450 ) ( * 1580100 )
-      NEW met2 ( 1354010 1580100 ) ( 1355390 * )
-      NEW met2 ( 1355390 1690140 ) ( 1356080 * 0 )
-      NEW met2 ( 1355390 1580100 ) ( * 1690140 )
-      NEW met1 ( 600530 14450 ) ( 1354010 * )
-      NEW met1 ( 588110 14110 ) M1M2_PR
-      NEW met1 ( 1354010 14450 ) M1M2_PR ;
-    - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj wbs_dat_o[2] ) + USE SIGNAL
-      + ROUTED met2 ( 97290 2380 0 ) ( * 15130 )
-      NEW met1 ( 97290 15130 ) ( 106950 * )
-      NEW met2 ( 106950 15130 ) ( * 1680620 )
-      NEW met2 ( 1203590 1680620 ) ( * 1690140 )
-      NEW met2 ( 1203590 1690140 ) ( 1204740 * 0 )
-      NEW met3 ( 106950 1680620 ) ( 1203590 * )
-      NEW met1 ( 97290 15130 ) M1M2_PR
-      NEW met1 ( 106950 15130 ) M1M2_PR
-      NEW met2 ( 106950 1680620 ) M2M3_PR_M
-      NEW met2 ( 1203590 1680620 ) M2M3_PR_M ;
-    - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ( mprj wbs_dat_o[30] ) + USE SIGNAL
-      + ROUTED met2 ( 605590 2380 0 ) ( * 14110 )
-      NEW met2 ( 1360450 1690140 ) ( 1361600 * 0 )
-      NEW met2 ( 1360450 14110 ) ( * 1690140 )
-      NEW met1 ( 605590 14110 ) ( 1360450 * )
-      NEW met1 ( 605590 14110 ) M1M2_PR
-      NEW met1 ( 1360450 14110 ) M1M2_PR ;
-    - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ( mprj wbs_dat_o[31] ) + USE SIGNAL
-      + ROUTED met1 ( 1345270 1681470 ) ( * 1681810 )
-      NEW met1 ( 1345270 1681470 ) ( 1366430 * )
-      NEW met2 ( 1366430 1681470 ) ( * 1690140 )
-      NEW met2 ( 1366430 1690140 ) ( 1367120 * 0 )
-      NEW met2 ( 623530 2380 0 ) ( * 3060 )
-      NEW met2 ( 623530 3060 ) ( 624450 * )
-      NEW met2 ( 624450 2380 ) ( * 3060 )
-      NEW met2 ( 624450 2380 ) ( 625830 * )
-      NEW met2 ( 625830 2380 ) ( * 34500 )
-      NEW met2 ( 625830 34500 ) ( 627670 * )
-      NEW met2 ( 627670 34500 ) ( * 1681810 )
-      NEW met1 ( 627670 1681810 ) ( 1345270 * )
-      NEW met1 ( 1366430 1681470 ) M1M2_PR
-      NEW met1 ( 627670 1681810 ) M1M2_PR ;
-    - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj wbs_dat_o[3] ) + USE SIGNAL
-      + ROUTED met2 ( 121210 2380 0 ) ( * 18700 )
-      NEW met3 ( 121210 18700 ) ( 1209570 * )
-      NEW met2 ( 1209110 82800 ) ( 1209570 * )
-      NEW met2 ( 1209570 18700 ) ( * 82800 )
-      NEW met2 ( 1209110 82800 ) ( * 1580100 )
-      NEW met2 ( 1209110 1580100 ) ( 1210950 * )
-      NEW met2 ( 1210950 1690140 ) ( 1212100 * 0 )
-      NEW met2 ( 1210950 1580100 ) ( * 1690140 )
-      NEW met2 ( 121210 18700 ) M2M3_PR_M
-      NEW met2 ( 1209570 18700 ) M2M3_PR_M ;
-    - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj wbs_dat_o[4] ) + USE SIGNAL
-      + ROUTED met2 ( 144670 2380 0 ) ( * 16830 )
-      NEW met1 ( 144670 16830 ) ( 175950 * )
-      NEW met2 ( 175950 16830 ) ( * 1680110 )
-      NEW met2 ( 1218310 1680110 ) ( * 1690140 )
-      NEW met2 ( 1218310 1690140 ) ( 1219460 * 0 )
-      NEW met1 ( 175950 1680110 ) ( 1218310 * )
-      NEW met1 ( 144670 16830 ) M1M2_PR
-      NEW met1 ( 175950 16830 ) M1M2_PR
-      NEW met1 ( 175950 1680110 ) M1M2_PR
-      NEW met1 ( 1218310 1680110 ) M1M2_PR ;
-    - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj wbs_dat_o[5] ) + USE SIGNAL
-      + ROUTED met2 ( 162150 2380 0 ) ( * 17510 )
-      NEW met1 ( 162150 17510 ) ( 1222450 * )
-      NEW met2 ( 1222450 17510 ) ( * 1580100 )
-      NEW met2 ( 1222450 1580100 ) ( 1223830 * )
-      NEW met2 ( 1223830 1690140 ) ( 1224980 * 0 )
-      NEW met2 ( 1223830 1580100 ) ( * 1690140 )
+      NEW met1 ( 72450 79390 ) M1M2_PR ;
+    - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( inst_eFPGA_CPU_top wbs_dat_i[20] ) + USE SIGNAL
+      + ROUTED met2 ( 409850 149260 ) ( * 150240 0 )
+      NEW met2 ( 409850 149260 ) ( 410090 * )
+      NEW met2 ( 410090 137870 ) ( * 149260 )
+      NEW met1 ( 410090 137870 ) ( 417450 * )
+      NEW met2 ( 417450 34510 ) ( * 137870 )
+      NEW met1 ( 417450 34510 ) ( 422510 * )
+      NEW met2 ( 422510 1700 0 ) ( * 34510 )
+      NEW met1 ( 417450 34510 ) M1M2_PR
+      NEW met1 ( 410090 137870 ) M1M2_PR
+      NEW met1 ( 417450 137870 ) M1M2_PR
+      NEW met1 ( 422510 34510 ) M1M2_PR ;
+    - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( inst_eFPGA_CPU_top wbs_dat_i[21] ) + USE SIGNAL
+      + ROUTED met2 ( 379730 59330 ) ( * 131100 )
+      NEW met2 ( 384550 149260 ) ( * 150240 0 )
+      NEW met2 ( 384330 149260 ) ( 384550 * )
+      NEW met2 ( 384330 131100 ) ( * 149260 )
+      NEW met2 ( 379730 131100 ) ( 384330 * )
+      NEW met1 ( 379730 59330 ) ( 439990 * )
+      NEW met2 ( 439990 1700 0 ) ( * 59330 )
+      NEW met1 ( 379730 59330 ) M1M2_PR
+      NEW met1 ( 439990 59330 ) M1M2_PR ;
+    - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( inst_eFPGA_CPU_top wbs_dat_i[22] ) + USE SIGNAL
+      + ROUTED met2 ( 359250 149260 ) ( * 150240 0 )
+      NEW met2 ( 359030 149260 ) ( 359250 * )
+      NEW met2 ( 359030 66130 ) ( * 149260 )
+      NEW met1 ( 359030 66130 ) ( 457930 * )
+      NEW met2 ( 457930 1700 0 ) ( * 66130 )
+      NEW met1 ( 359030 66130 ) M1M2_PR
+      NEW met1 ( 457930 66130 ) M1M2_PR ;
+    - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( inst_eFPGA_CPU_top wbs_dat_i[23] ) + USE SIGNAL
+      + ROUTED met2 ( 475870 1700 0 ) ( * 16150 )
+      NEW met1 ( 469430 16150 ) ( 475870 * )
+      NEW met2 ( 469430 16150 ) ( * 114410 )
+      NEW met1 ( 344770 114410 ) ( 469430 * )
+      NEW met2 ( 333950 149260 ) ( * 150240 0 )
+      NEW met2 ( 333950 149260 ) ( 334190 * )
+      NEW met2 ( 334190 137870 ) ( * 149260 )
+      NEW met1 ( 334190 137870 ) ( 344770 * )
+      NEW met2 ( 344770 114410 ) ( * 137870 )
+      NEW met1 ( 475870 16150 ) M1M2_PR
+      NEW met1 ( 469430 16150 ) M1M2_PR
+      NEW met1 ( 469430 114410 ) M1M2_PR
+      NEW met1 ( 344770 114410 ) M1M2_PR
+      NEW met1 ( 334190 137870 ) M1M2_PR
+      NEW met1 ( 344770 137870 ) M1M2_PR ;
+    - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( inst_eFPGA_CPU_top wbs_dat_i[24] ) + USE SIGNAL
+      + ROUTED met2 ( 303830 121210 ) ( * 131100 )
+      NEW met2 ( 308650 149260 ) ( * 150240 0 )
+      NEW met2 ( 308430 149260 ) ( 308650 * )
+      NEW met2 ( 308430 131100 ) ( * 149260 )
+      NEW met2 ( 303830 131100 ) ( 308430 * )
+      NEW met2 ( 490130 82800 ) ( * 121210 )
+      NEW met2 ( 490130 82800 ) ( 493350 * )
+      NEW met2 ( 493350 1700 0 ) ( * 82800 )
+      NEW met1 ( 303830 121210 ) ( 490130 * )
+      NEW met1 ( 303830 121210 ) M1M2_PR
+      NEW met1 ( 490130 121210 ) M1M2_PR ;
+    - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( inst_eFPGA_CPU_top wbs_dat_i[25] ) + USE SIGNAL
+      + ROUTED met2 ( 283350 149260 ) ( * 150240 0 )
+      NEW met2 ( 283350 149260 ) ( 283590 * )
+      NEW met2 ( 283590 72930 ) ( * 149260 )
+      NEW met2 ( 511290 1700 0 ) ( * 72930 )
+      NEW met1 ( 283590 72930 ) ( 511290 * )
+      NEW met1 ( 283590 72930 ) M1M2_PR
+      NEW met1 ( 511290 72930 ) M1M2_PR ;
+    - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( inst_eFPGA_CPU_top wbs_dat_i[26] ) + USE SIGNAL
+      + ROUTED met1 ( 255530 86870 ) ( 524630 * )
+      NEW met2 ( 255530 86870 ) ( * 131100 )
+      NEW met2 ( 258050 149260 ) ( * 150240 0 )
+      NEW met2 ( 257830 149260 ) ( 258050 * )
+      NEW met2 ( 257830 131100 ) ( * 149260 )
+      NEW met2 ( 255530 131100 ) ( 257830 * )
+      NEW met2 ( 524630 82800 ) ( * 86870 )
+      NEW met2 ( 524630 82800 ) ( 528770 * )
+      NEW met2 ( 528770 1700 0 ) ( * 82800 )
+      NEW met1 ( 255530 86870 ) M1M2_PR
+      NEW met1 ( 524630 86870 ) M1M2_PR ;
+    - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( inst_eFPGA_CPU_top wbs_dat_i[27] ) + USE SIGNAL
+      + ROUTED met2 ( 232750 149260 ) ( * 150240 0 )
+      NEW met2 ( 232750 149260 ) ( 232990 * )
+      NEW met2 ( 232990 137870 ) ( * 149260 )
+      NEW met1 ( 232990 137870 ) ( 238050 * )
+      NEW met2 ( 238050 51850 ) ( * 137870 )
+      NEW met1 ( 238050 51850 ) ( 546710 * )
+      NEW met2 ( 546710 1700 0 ) ( * 51850 )
+      NEW met1 ( 238050 51850 ) M1M2_PR
+      NEW met1 ( 232990 137870 ) M1M2_PR
+      NEW met1 ( 238050 137870 ) M1M2_PR
+      NEW met1 ( 546710 51850 ) M1M2_PR ;
+    - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( inst_eFPGA_CPU_top wbs_dat_i[28] ) + USE SIGNAL
+      + ROUTED met2 ( 207450 149260 ) ( * 150240 0 )
+      NEW met2 ( 207450 149260 ) ( 207690 * )
+      NEW met2 ( 207690 137870 ) ( * 149260 )
+      NEW met1 ( 207690 137870 ) ( 217350 * )
+      NEW met2 ( 217350 107610 ) ( * 137870 )
+      NEW met1 ( 217350 107610 ) ( 559130 * )
+      NEW met2 ( 564190 1700 0 ) ( * 34500 )
+      NEW met2 ( 559130 34500 ) ( 564190 * )
+      NEW met2 ( 559130 34500 ) ( * 107610 )
+      NEW met1 ( 217350 107610 ) M1M2_PR
+      NEW met1 ( 207690 137870 ) M1M2_PR
+      NEW met1 ( 217350 137870 ) M1M2_PR
+      NEW met1 ( 559130 107610 ) M1M2_PR ;
+    - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( inst_eFPGA_CPU_top wbs_dat_i[29] ) + USE SIGNAL
+      + ROUTED met2 ( 179630 120870 ) ( * 131100 )
+      NEW met2 ( 182150 149260 ) ( * 150240 0 )
+      NEW met2 ( 181930 149260 ) ( 182150 * )
+      NEW met2 ( 181930 131100 ) ( * 149260 )
+      NEW met2 ( 179630 131100 ) ( 181930 * )
+      NEW met2 ( 579830 82800 ) ( * 120870 )
+      NEW met2 ( 579830 82800 ) ( 582130 * )
+      NEW met2 ( 582130 1700 0 ) ( * 82800 )
+      NEW met1 ( 179630 120870 ) ( 579830 * )
+      NEW met1 ( 179630 120870 ) M1M2_PR
+      NEW met1 ( 579830 120870 ) M1M2_PR ;
+    - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( inst_eFPGA_CPU_top wbs_dat_i[2] ) + USE SIGNAL
+      + ROUTED met2 ( 91310 1700 0 ) ( * 58990 )
+      NEW met2 ( 862730 58990 ) ( * 131100 )
+      NEW met2 ( 865710 149260 ) ( * 150240 0 )
+      NEW met2 ( 865490 149260 ) ( 865710 * )
+      NEW met2 ( 865490 131100 ) ( * 149260 )
+      NEW met2 ( 862730 131100 ) ( 865490 * )
+      NEW met1 ( 91310 58990 ) ( 862730 * )
+      NEW met1 ( 91310 58990 ) M1M2_PR
+      NEW met1 ( 862730 58990 ) M1M2_PR ;
+    - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( inst_eFPGA_CPU_top wbs_dat_i[30] ) + USE SIGNAL
+      + ROUTED met2 ( 594090 82800 ) ( * 100130 )
+      NEW met2 ( 594090 82800 ) ( 599610 * )
+      NEW met2 ( 599610 1700 0 ) ( * 82800 )
+      NEW met1 ( 165370 100130 ) ( 594090 * )
+      NEW met2 ( 156850 149260 ) ( * 150240 0 )
+      NEW met2 ( 156850 149260 ) ( 157090 * )
+      NEW met2 ( 157090 137870 ) ( * 149260 )
+      NEW met1 ( 157090 137870 ) ( 165370 * )
+      NEW met2 ( 165370 100130 ) ( * 137870 )
+      NEW met1 ( 594090 100130 ) M1M2_PR
+      NEW met1 ( 165370 100130 ) M1M2_PR
+      NEW met1 ( 157090 137870 ) M1M2_PR
+      NEW met1 ( 165370 137870 ) M1M2_PR ;
+    - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( inst_eFPGA_CPU_top wbs_dat_i[31] ) + USE SIGNAL
+      + ROUTED met1 ( 131330 93330 ) ( 614330 * )
+      NEW met2 ( 131550 149260 ) ( * 150240 0 )
+      NEW met2 ( 131330 149260 ) ( 131550 * )
+      NEW met2 ( 131330 93330 ) ( * 149260 )
+      NEW met2 ( 614330 82800 ) ( * 93330 )
+      NEW met2 ( 614330 82800 ) ( 617550 * )
+      NEW met2 ( 617550 1700 0 ) ( * 82800 )
+      NEW met1 ( 131330 93330 ) M1M2_PR
+      NEW met1 ( 614330 93330 ) M1M2_PR ;
+    - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( inst_eFPGA_CPU_top wbs_dat_i[3] ) + USE SIGNAL
+      + ROUTED met2 ( 110630 82800 ) ( * 128010 )
+      NEW met2 ( 110630 82800 ) ( 115230 * )
+      NEW met2 ( 115230 1700 0 ) ( * 82800 )
+      NEW met1 ( 110630 128010 ) ( 835130 * )
+      NEW met2 ( 835130 128010 ) ( * 131100 )
+      NEW met2 ( 840410 149260 ) ( * 150240 0 )
+      NEW met2 ( 840190 149260 ) ( 840410 * )
+      NEW met2 ( 840190 131100 ) ( * 149260 )
+      NEW met2 ( 835130 131100 ) ( 840190 * )
+      NEW met1 ( 110630 128010 ) M1M2_PR
+      NEW met1 ( 835130 128010 ) M1M2_PR ;
+    - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( inst_eFPGA_CPU_top wbs_dat_i[4] ) + USE SIGNAL
+      + ROUTED met1 ( 138230 107270 ) ( 814430 * )
+      NEW met2 ( 138230 82800 ) ( * 107270 )
+      NEW met2 ( 138230 82800 ) ( 138690 * )
+      NEW met2 ( 138690 1700 0 ) ( * 82800 )
+      NEW met2 ( 814430 107270 ) ( * 131100 )
+      NEW met2 ( 815110 149260 ) ( * 150240 0 )
+      NEW met2 ( 814890 149260 ) ( 815110 * )
+      NEW met2 ( 814890 131100 ) ( * 149260 )
+      NEW met2 ( 814430 131100 ) ( 814890 * )
+      NEW met1 ( 138230 107270 ) M1M2_PR
+      NEW met1 ( 814430 107270 ) M1M2_PR ;
+    - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( inst_eFPGA_CPU_top wbs_dat_i[5] ) + USE SIGNAL
+      + ROUTED met2 ( 786830 38250 ) ( * 131100 )
+      NEW met2 ( 789810 149260 ) ( * 150240 0 )
+      NEW met2 ( 789590 149260 ) ( 789810 * )
+      NEW met2 ( 789590 131100 ) ( * 149260 )
+      NEW met2 ( 786830 131100 ) ( 789590 * )
+      NEW met2 ( 156630 1700 0 ) ( * 38250 )
+      NEW met1 ( 156630 38250 ) ( 786830 * )
+      NEW met1 ( 786830 38250 ) M1M2_PR
+      NEW met1 ( 156630 38250 ) M1M2_PR ;
+    - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( inst_eFPGA_CPU_top wbs_dat_i[6] ) + USE SIGNAL
+      + ROUTED met2 ( 759230 79730 ) ( * 131100 )
+      NEW met2 ( 764510 149260 ) ( * 150240 0 )
+      NEW met2 ( 764290 149260 ) ( 764510 * )
+      NEW met2 ( 764290 131100 ) ( * 149260 )
+      NEW met2 ( 759230 131100 ) ( 764290 * )
+      NEW met2 ( 174110 1700 0 ) ( * 79730 )
+      NEW met1 ( 174110 79730 ) ( 759230 * )
+      NEW met1 ( 759230 79730 ) M1M2_PR
+      NEW met1 ( 174110 79730 ) M1M2_PR ;
+    - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( inst_eFPGA_CPU_top wbs_dat_i[7] ) + USE SIGNAL
+      + ROUTED met2 ( 192050 1700 0 ) ( * 45050 )
+      NEW met1 ( 192050 45050 ) ( 738530 * )
+      NEW met2 ( 738750 149260 ) ( * 150240 0 )
+      NEW met2 ( 738530 149260 ) ( 738750 * )
+      NEW met2 ( 738530 45050 ) ( * 149260 )
+      NEW met1 ( 192050 45050 ) M1M2_PR
+      NEW met1 ( 738530 45050 ) M1M2_PR ;
+    - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( inst_eFPGA_CPU_top wbs_dat_i[8] ) + USE SIGNAL
+      + ROUTED met2 ( 209530 1700 0 ) ( * 65450 )
+      NEW met1 ( 209530 65450 ) ( 710930 * )
+      NEW met2 ( 710930 65450 ) ( * 131100 )
+      NEW met2 ( 713450 149260 ) ( * 150240 0 )
+      NEW met2 ( 713230 149260 ) ( 713450 * )
+      NEW met2 ( 713230 131100 ) ( * 149260 )
+      NEW met2 ( 710930 131100 ) ( 713230 * )
+      NEW met1 ( 209530 65450 ) M1M2_PR
+      NEW met1 ( 710930 65450 ) M1M2_PR ;
+    - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( inst_eFPGA_CPU_top wbs_dat_i[9] ) + USE SIGNAL
+      + ROUTED met2 ( 227470 1700 0 ) ( * 16830 )
+      NEW met1 ( 221030 16830 ) ( 227470 * )
+      NEW met2 ( 221030 16830 ) ( * 113730 )
+      NEW met2 ( 683330 113730 ) ( * 131100 )
+      NEW met2 ( 688150 149260 ) ( * 150240 0 )
+      NEW met2 ( 687930 149260 ) ( 688150 * )
+      NEW met2 ( 687930 131100 ) ( * 149260 )
+      NEW met2 ( 683330 131100 ) ( 687930 * )
+      NEW met1 ( 221030 113730 ) ( 683330 * )
+      NEW met1 ( 227470 16830 ) M1M2_PR
+      NEW met1 ( 221030 16830 ) M1M2_PR
+      NEW met1 ( 221030 113730 ) M1M2_PR
+      NEW met1 ( 683330 113730 ) M1M2_PR ;
+    - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( inst_eFPGA_CPU_top wbs_dat_o[0] ) + USE SIGNAL
+      + ROUTED met2 ( 2532530 51510 ) ( * 131100 )
+      NEW met2 ( 2536430 149260 ) ( * 150240 0 )
+      NEW met2 ( 2536210 149260 ) ( 2536430 * )
+      NEW met2 ( 2536210 131100 ) ( * 149260 )
+      NEW met2 ( 2532530 131100 ) ( 2536210 * )
+      NEW met2 ( 49910 1700 0 ) ( * 51510 )
+      NEW met1 ( 49910 51510 ) ( 2532530 * )
+      NEW met1 ( 2532530 51510 ) M1M2_PR
+      NEW met1 ( 49910 51510 ) M1M2_PR ;
+    - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ( inst_eFPGA_CPU_top wbs_dat_o[10] ) + USE SIGNAL
+      + ROUTED met2 ( 250930 1700 0 ) ( * 72590 )
+      NEW met1 ( 250930 72590 ) ( 2273550 * )
+      NEW met2 ( 2283430 149260 ) ( * 150240 0 )
+      NEW met2 ( 2283210 149260 ) ( 2283430 * )
+      NEW met2 ( 2283210 137870 ) ( * 149260 )
+      NEW met1 ( 2273550 137870 ) ( 2283210 * )
+      NEW met2 ( 2273550 72590 ) ( * 137870 )
+      NEW met1 ( 250930 72590 ) M1M2_PR
+      NEW met1 ( 2273550 72590 ) M1M2_PR
+      NEW met1 ( 2283210 137870 ) M1M2_PR
+      NEW met1 ( 2273550 137870 ) M1M2_PR ;
+    - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ( inst_eFPGA_CPU_top wbs_dat_o[11] ) + USE SIGNAL
+      + ROUTED met2 ( 268870 1700 0 ) ( * 16830 )
+      NEW met1 ( 262430 16830 ) ( 268870 * )
+      NEW met1 ( 262430 120530 ) ( 2256530 * )
+      NEW met2 ( 262430 16830 ) ( * 120530 )
+      NEW met2 ( 2256530 120530 ) ( * 131100 )
+      NEW met2 ( 2258130 149260 ) ( * 150240 0 )
+      NEW met2 ( 2257910 149260 ) ( 2258130 * )
+      NEW met2 ( 2257910 131100 ) ( * 149260 )
+      NEW met2 ( 2256530 131100 ) ( 2257910 * )
+      NEW met1 ( 268870 16830 ) M1M2_PR
+      NEW met1 ( 262430 16830 ) M1M2_PR
+      NEW met1 ( 262430 120530 ) M1M2_PR
+      NEW met1 ( 2256530 120530 ) M1M2_PR ;
+    - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ( inst_eFPGA_CPU_top wbs_dat_o[12] ) + USE SIGNAL
+      + ROUTED met2 ( 286350 1700 0 ) ( * 34500 )
+      NEW met2 ( 283130 34500 ) ( 286350 * )
+      NEW met2 ( 283130 34500 ) ( * 86190 )
+      NEW met2 ( 2228930 86190 ) ( * 131100 )
+      NEW met2 ( 2232830 149090 ) ( * 150240 0 )
+      NEW met2 ( 2232610 149090 ) ( 2232830 * )
+      NEW met2 ( 2232610 131100 ) ( * 149090 )
+      NEW met2 ( 2228930 131100 ) ( 2232610 * )
+      NEW met1 ( 283130 86190 ) ( 2228930 * )
+      NEW met1 ( 283130 86190 ) M1M2_PR
+      NEW met1 ( 2228930 86190 ) M1M2_PR ;
+    - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ( inst_eFPGA_CPU_top wbs_dat_o[13] ) + USE SIGNAL
+      + ROUTED met2 ( 304290 1700 0 ) ( * 19210 )
+      NEW met1 ( 304290 19210 ) ( 2201330 * )
+      NEW met2 ( 2207530 149090 ) ( * 150240 0 )
+      NEW met1 ( 2201330 149090 ) ( 2207530 * )
+      NEW met2 ( 2201330 19210 ) ( * 149090 )
+      NEW met1 ( 304290 19210 ) M1M2_PR
+      NEW met1 ( 2201330 19210 ) M1M2_PR
+      NEW met1 ( 2207530 149090 ) M1M2_PR
+      NEW met1 ( 2201330 149090 ) M1M2_PR ;
+    - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ( inst_eFPGA_CPU_top wbs_dat_o[14] ) + USE SIGNAL
+      + ROUTED met2 ( 321770 1700 0 ) ( * 19550 )
+      NEW met1 ( 321770 19550 ) ( 2180630 * )
+      NEW met2 ( 2180630 19550 ) ( * 131100 )
+      NEW met2 ( 2182230 149260 ) ( * 150240 0 )
+      NEW met2 ( 2182010 149260 ) ( 2182230 * )
+      NEW met2 ( 2182010 131100 ) ( * 149260 )
+      NEW met2 ( 2180630 131100 ) ( 2182010 * )
+      NEW met1 ( 321770 19550 ) M1M2_PR
+      NEW met1 ( 2180630 19550 ) M1M2_PR ;
+    - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ( inst_eFPGA_CPU_top wbs_dat_o[15] ) + USE SIGNAL
+      + ROUTED met2 ( 2153030 19890 ) ( * 131100 )
+      NEW met2 ( 2156470 149260 ) ( * 150240 0 )
+      NEW met2 ( 2156250 149260 ) ( 2156470 * )
+      NEW met2 ( 2156250 131100 ) ( * 149260 )
+      NEW met2 ( 2153030 131100 ) ( 2156250 * )
+      NEW met2 ( 339710 1700 0 ) ( * 19890 )
+      NEW met1 ( 339710 19890 ) ( 2153030 * )
+      NEW met1 ( 2153030 19890 ) M1M2_PR
+      NEW met1 ( 339710 19890 ) M1M2_PR ;
+    - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ( inst_eFPGA_CPU_top wbs_dat_o[16] ) + USE SIGNAL
+      + ROUTED met2 ( 2131170 149090 ) ( * 150240 0 )
+      NEW met1 ( 2125430 149090 ) ( 2131170 * )
+      NEW met2 ( 2125430 20230 ) ( * 149090 )
+      NEW met2 ( 357650 1700 0 ) ( * 20230 )
+      NEW met1 ( 357650 20230 ) ( 2125430 * )
+      NEW met1 ( 2125430 20230 ) M1M2_PR
+      NEW met1 ( 2131170 149090 ) M1M2_PR
+      NEW met1 ( 2125430 149090 ) M1M2_PR
+      NEW met1 ( 357650 20230 ) M1M2_PR ;
+    - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ( inst_eFPGA_CPU_top wbs_dat_o[17] ) + USE SIGNAL
+      + ROUTED met2 ( 375130 1700 0 ) ( * 20570 )
+      NEW met1 ( 375130 20570 ) ( 2104730 * )
+      NEW met2 ( 2104730 20570 ) ( * 131100 )
+      NEW met2 ( 2105870 149260 ) ( * 150240 0 )
+      NEW met2 ( 2105650 149260 ) ( 2105870 * )
+      NEW met2 ( 2105650 131100 ) ( * 149260 )
+      NEW met2 ( 2104730 131100 ) ( 2105650 * )
+      NEW met1 ( 375130 20570 ) M1M2_PR
+      NEW met1 ( 2104730 20570 ) M1M2_PR ;
+    - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ( inst_eFPGA_CPU_top wbs_dat_o[18] ) + USE SIGNAL
+      + ROUTED met2 ( 393070 1700 0 ) ( * 16830 )
+      NEW met1 ( 393070 16830 ) ( 2077130 * )
+      NEW met2 ( 2077130 16830 ) ( * 131100 )
+      NEW met2 ( 2080570 149260 ) ( * 150240 0 )
+      NEW met2 ( 2080350 149260 ) ( 2080570 * )
+      NEW met2 ( 2080350 131100 ) ( * 149260 )
+      NEW met2 ( 2077130 131100 ) ( 2080350 * )
+      NEW met1 ( 393070 16830 ) M1M2_PR
+      NEW met1 ( 2077130 16830 ) M1M2_PR ;
+    - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ( inst_eFPGA_CPU_top wbs_dat_o[19] ) + USE SIGNAL
+      + ROUTED met2 ( 407330 82800 ) ( 410550 * )
+      NEW met2 ( 410550 1700 0 ) ( * 82800 )
+      NEW met2 ( 407330 82800 ) ( * 135490 )
+      NEW met2 ( 2055270 149260 ) ( * 150240 0 )
+      NEW met2 ( 2055050 149260 ) ( 2055270 * )
+      NEW met2 ( 2055050 135490 ) ( * 149260 )
+      NEW met1 ( 407330 135490 ) ( 2055050 * )
+      NEW met1 ( 407330 135490 ) M1M2_PR
+      NEW met1 ( 2055050 135490 ) M1M2_PR ;
+    - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( inst_eFPGA_CPU_top wbs_dat_o[1] ) + USE SIGNAL
+      + ROUTED met2 ( 2511130 149090 ) ( * 150240 0 )
+      NEW met1 ( 2504930 149090 ) ( 2511130 * )
+      NEW met2 ( 2504930 18020 ) ( * 149090 )
+      NEW met2 ( 73830 1700 0 ) ( * 18020 )
+      NEW met3 ( 73830 18020 ) ( 2504930 * )
+      NEW met2 ( 2504930 18020 ) M2M3_PR_M
+      NEW met1 ( 2511130 149090 ) M1M2_PR
+      NEW met1 ( 2504930 149090 ) M1M2_PR
+      NEW met2 ( 73830 18020 ) M2M3_PR_M ;
+    - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ( inst_eFPGA_CPU_top wbs_dat_o[20] ) + USE SIGNAL
+      + ROUTED met2 ( 2029970 149260 ) ( * 150240 0 )
+      NEW met2 ( 2029750 149260 ) ( 2029970 * )
+      NEW met2 ( 2029750 135830 ) ( * 149260 )
+      NEW met2 ( 428030 82800 ) ( 428490 * )
+      NEW met2 ( 428490 1700 0 ) ( * 82800 )
+      NEW met2 ( 428030 82800 ) ( * 135830 )
+      NEW met1 ( 428030 135830 ) ( 2029750 * )
+      NEW met1 ( 2029750 135830 ) M1M2_PR
+      NEW met1 ( 428030 135830 ) M1M2_PR ;
+    - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ( inst_eFPGA_CPU_top wbs_dat_o[21] ) + USE SIGNAL
+      + ROUTED met2 ( 445970 1700 0 ) ( * 16490 )
+      NEW met1 ( 445970 16490 ) ( 2001230 * )
+      NEW met2 ( 2001230 16490 ) ( * 131100 )
+      NEW met2 ( 2004670 149260 ) ( * 150240 0 )
+      NEW met2 ( 2004450 149260 ) ( 2004670 * )
+      NEW met2 ( 2004450 131100 ) ( * 149260 )
+      NEW met2 ( 2001230 131100 ) ( 2004450 * )
+      NEW met1 ( 445970 16490 ) M1M2_PR
+      NEW met1 ( 2001230 16490 ) M1M2_PR ;
+    - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ( inst_eFPGA_CPU_top wbs_dat_o[22] ) + USE SIGNAL
+      + ROUTED met2 ( 462530 82800 ) ( 463910 * )
+      NEW met2 ( 463910 1700 0 ) ( * 82800 )
+      NEW met2 ( 462530 82800 ) ( * 136170 )
+      NEW met2 ( 1979370 149260 ) ( * 150240 0 )
+      NEW met2 ( 1979150 149260 ) ( 1979370 * )
+      NEW met2 ( 1979150 136170 ) ( * 149260 )
+      NEW met1 ( 462530 136170 ) ( 1979150 * )
+      NEW met1 ( 462530 136170 ) M1M2_PR
+      NEW met1 ( 1979150 136170 ) M1M2_PR ;
+    - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ( inst_eFPGA_CPU_top wbs_dat_o[23] ) + USE SIGNAL
+      + ROUTED met2 ( 481390 1700 0 ) ( * 16150 )
+      NEW met2 ( 1952930 16150 ) ( * 131100 )
+      NEW met2 ( 1954070 149260 ) ( * 150240 0 )
+      NEW met2 ( 1953850 149260 ) ( 1954070 * )
+      NEW met2 ( 1953850 131100 ) ( * 149260 )
+      NEW met2 ( 1952930 131100 ) ( 1953850 * )
+      NEW met1 ( 481390 16150 ) ( 1952930 * )
+      NEW met1 ( 481390 16150 ) M1M2_PR
+      NEW met1 ( 1952930 16150 ) M1M2_PR ;
+    - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ( inst_eFPGA_CPU_top wbs_dat_o[24] ) + USE SIGNAL
+      + ROUTED met2 ( 499330 1700 0 ) ( * 15810 )
+      NEW met2 ( 1925330 15810 ) ( * 131100 )
+      NEW met2 ( 1928770 149260 ) ( * 150240 0 )
+      NEW met2 ( 1928550 149260 ) ( 1928770 * )
+      NEW met2 ( 1928550 131100 ) ( * 149260 )
+      NEW met2 ( 1925330 131100 ) ( 1928550 * )
+      NEW met1 ( 499330 15810 ) ( 1925330 * )
+      NEW met1 ( 499330 15810 ) M1M2_PR
+      NEW met1 ( 1925330 15810 ) M1M2_PR ;
+    - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ( inst_eFPGA_CPU_top wbs_dat_o[25] ) + USE SIGNAL
+      + ROUTED met2 ( 516810 1700 0 ) ( * 15470 )
+      NEW met1 ( 516810 15470 ) ( 1897730 * )
+      NEW met2 ( 1903470 149090 ) ( * 150240 0 )
+      NEW met1 ( 1897730 149090 ) ( 1903470 * )
+      NEW met2 ( 1897730 15470 ) ( * 149090 )
+      NEW met1 ( 516810 15470 ) M1M2_PR
+      NEW met1 ( 1897730 15470 ) M1M2_PR
+      NEW met1 ( 1903470 149090 ) M1M2_PR
+      NEW met1 ( 1897730 149090 ) M1M2_PR ;
+    - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ( inst_eFPGA_CPU_top wbs_dat_o[26] ) + USE SIGNAL
+      + ROUTED met2 ( 534750 1700 0 ) ( * 34500 )
+      NEW met2 ( 531530 34500 ) ( 534750 * )
+      NEW met2 ( 531530 34500 ) ( * 136510 )
+      NEW met2 ( 1878170 149260 ) ( * 150240 0 )
+      NEW met2 ( 1877950 149260 ) ( 1878170 * )
+      NEW met2 ( 1877950 136510 ) ( * 149260 )
+      NEW met1 ( 531530 136510 ) ( 1877950 * )
+      NEW met1 ( 531530 136510 ) M1M2_PR
+      NEW met1 ( 1877950 136510 ) M1M2_PR ;
+    - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ( inst_eFPGA_CPU_top wbs_dat_o[27] ) + USE SIGNAL
+      + ROUTED met2 ( 1849430 15130 ) ( * 131100 )
+      NEW met2 ( 1852870 149260 ) ( * 150240 0 )
+      NEW met2 ( 1852650 149260 ) ( 1852870 * )
+      NEW met2 ( 1852650 131100 ) ( * 149260 )
+      NEW met2 ( 1849430 131100 ) ( 1852650 * )
+      NEW met2 ( 552690 1700 0 ) ( * 15130 )
+      NEW met1 ( 552690 15130 ) ( 1849430 * )
+      NEW met1 ( 1849430 15130 ) M1M2_PR
+      NEW met1 ( 552690 15130 ) M1M2_PR ;
+    - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ( inst_eFPGA_CPU_top wbs_dat_o[28] ) + USE SIGNAL
+      + ROUTED met2 ( 566030 82800 ) ( 570170 * )
+      NEW met2 ( 570170 1700 0 ) ( * 82800 )
+      NEW met2 ( 566030 82800 ) ( * 136850 )
+      NEW met2 ( 1827570 149260 ) ( * 150240 0 )
+      NEW met2 ( 1827350 149260 ) ( 1827570 * )
+      NEW met2 ( 1827350 136850 ) ( * 149260 )
+      NEW met1 ( 566030 136850 ) ( 1827350 * )
+      NEW met1 ( 566030 136850 ) M1M2_PR
+      NEW met1 ( 1827350 136850 ) M1M2_PR ;
+    - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ( inst_eFPGA_CPU_top wbs_dat_o[29] ) + USE SIGNAL
+      + ROUTED met2 ( 588110 1700 0 ) ( * 14790 )
+      NEW met1 ( 588110 14790 ) ( 1801130 * )
+      NEW met2 ( 1801130 14790 ) ( * 131100 )
+      NEW met2 ( 1802270 149260 ) ( * 150240 0 )
+      NEW met2 ( 1802050 149260 ) ( 1802270 * )
+      NEW met2 ( 1802050 131100 ) ( * 149260 )
+      NEW met2 ( 1801130 131100 ) ( 1802050 * )
+      NEW met1 ( 588110 14790 ) M1M2_PR
+      NEW met1 ( 1801130 14790 ) M1M2_PR ;
+    - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( inst_eFPGA_CPU_top wbs_dat_o[2] ) + USE SIGNAL
+      + ROUTED met2 ( 97290 1700 0 ) ( * 18700 )
+      NEW met3 ( 97290 18700 ) ( 2484230 * )
+      NEW met2 ( 2484230 18700 ) ( * 131100 )
+      NEW met2 ( 2485830 149260 ) ( * 150240 0 )
+      NEW met2 ( 2485610 149260 ) ( 2485830 * )
+      NEW met2 ( 2485610 131100 ) ( * 149260 )
+      NEW met2 ( 2484230 131100 ) ( 2485610 * )
+      NEW met2 ( 97290 18700 ) M2M3_PR_M
+      NEW met2 ( 2484230 18700 ) M2M3_PR_M ;
+    - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ( inst_eFPGA_CPU_top wbs_dat_o[30] ) + USE SIGNAL
+      + ROUTED met2 ( 605590 1700 0 ) ( * 14450 )
+      NEW met1 ( 605590 14450 ) ( 1773530 * )
+      NEW met2 ( 1773530 14450 ) ( * 131100 )
+      NEW met2 ( 1776970 149260 ) ( * 150240 0 )
+      NEW met2 ( 1776750 149260 ) ( 1776970 * )
+      NEW met2 ( 1776750 131100 ) ( * 149260 )
+      NEW met2 ( 1773530 131100 ) ( 1776750 * )
+      NEW met1 ( 605590 14450 ) M1M2_PR
+      NEW met1 ( 1773530 14450 ) M1M2_PR ;
+    - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ( inst_eFPGA_CPU_top wbs_dat_o[31] ) + USE SIGNAL
+      + ROUTED met2 ( 1751670 149090 ) ( * 150240 0 )
+      NEW met1 ( 1745930 149090 ) ( 1751670 * )
+      NEW met2 ( 1745930 14110 ) ( * 149090 )
+      NEW met2 ( 623530 1700 0 ) ( * 14110 )
+      NEW met1 ( 623530 14110 ) ( 1745930 * )
+      NEW met1 ( 1745930 14110 ) M1M2_PR
+      NEW met1 ( 1751670 149090 ) M1M2_PR
+      NEW met1 ( 1745930 149090 ) M1M2_PR
+      NEW met1 ( 623530 14110 ) M1M2_PR ;
+    - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( inst_eFPGA_CPU_top wbs_dat_o[3] ) + USE SIGNAL
+      + ROUTED met2 ( 121210 1700 0 ) ( * 17170 )
+      NEW met1 ( 121210 17170 ) ( 2456630 * )
+      NEW met2 ( 2456630 17170 ) ( * 131100 )
+      NEW met2 ( 2460530 149260 ) ( * 150240 0 )
+      NEW met2 ( 2460310 149260 ) ( 2460530 * )
+      NEW met2 ( 2460310 131100 ) ( * 149260 )
+      NEW met2 ( 2456630 131100 ) ( 2460310 * )
+      NEW met1 ( 121210 17170 ) M1M2_PR
+      NEW met1 ( 2456630 17170 ) M1M2_PR ;
+    - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( inst_eFPGA_CPU_top wbs_dat_o[4] ) + USE SIGNAL
+      + ROUTED met2 ( 2435230 149260 ) ( * 150240 0 )
+      NEW met2 ( 2435010 149260 ) ( 2435230 * )
+      NEW met2 ( 2435010 135150 ) ( * 149260 )
+      NEW met2 ( 144670 1700 0 ) ( * 17510 )
+      NEW met1 ( 144670 17510 ) ( 162150 * )
+      NEW met2 ( 162150 17510 ) ( * 135150 )
+      NEW met1 ( 162150 135150 ) ( 2435010 * )
+      NEW met1 ( 2435010 135150 ) M1M2_PR
+      NEW met1 ( 144670 17510 ) M1M2_PR
       NEW met1 ( 162150 17510 ) M1M2_PR
-      NEW met1 ( 1222450 17510 ) M1M2_PR ;
-    - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj wbs_dat_o[6] ) + USE SIGNAL
-      + ROUTED met2 ( 180090 2380 0 ) ( * 19550 )
-      NEW met1 ( 180090 19550 ) ( 238050 * )
-      NEW met2 ( 238050 19550 ) ( * 1680790 )
-      NEW met2 ( 1229350 1680790 ) ( * 1690140 )
-      NEW met2 ( 1229350 1690140 ) ( 1230500 * 0 )
-      NEW met1 ( 238050 1680790 ) ( 1229350 * )
-      NEW met1 ( 180090 19550 ) M1M2_PR
-      NEW met1 ( 238050 19550 ) M1M2_PR
-      NEW met1 ( 238050 1680790 ) M1M2_PR
-      NEW met1 ( 1229350 1680790 ) M1M2_PR ;
-    - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj wbs_dat_o[7] ) + USE SIGNAL
-      + ROUTED met2 ( 198030 2380 0 ) ( * 18190 )
-      NEW met1 ( 198030 18190 ) ( 207230 * )
-      NEW met1 ( 207230 17850 ) ( * 18190 )
-      NEW met1 ( 207230 17850 ) ( 1236710 * )
-      NEW met1 ( 1235790 1652570 ) ( 1236710 * )
-      NEW met2 ( 1236710 17850 ) ( * 1652570 )
-      NEW met2 ( 1235560 1688780 ) ( 1235790 * )
-      NEW met2 ( 1235560 1688780 ) ( * 1690140 0 )
-      NEW met2 ( 1235790 1652570 ) ( * 1688780 )
+      NEW met1 ( 162150 135150 ) M1M2_PR ;
+    - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( inst_eFPGA_CPU_top wbs_dat_o[5] ) + USE SIGNAL
+      + ROUTED met2 ( 2408330 17510 ) ( * 131100 )
+      NEW met2 ( 2409930 149260 ) ( * 150240 0 )
+      NEW met2 ( 2409710 149260 ) ( 2409930 * )
+      NEW met2 ( 2409710 131100 ) ( * 149260 )
+      NEW met2 ( 2408330 131100 ) ( 2409710 * )
+      NEW met2 ( 162150 1700 0 ) ( * 9180 )
+      NEW met2 ( 162150 9180 ) ( 162610 * )
+      NEW met2 ( 162610 9180 ) ( * 17510 )
+      NEW met1 ( 162610 17510 ) ( 2408330 * )
+      NEW met1 ( 2408330 17510 ) M1M2_PR
+      NEW met1 ( 162610 17510 ) M1M2_PR ;
+    - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( inst_eFPGA_CPU_top wbs_dat_o[6] ) + USE SIGNAL
+      + ROUTED met2 ( 180090 1700 0 ) ( * 17850 )
+      NEW met1 ( 180090 17850 ) ( 2380730 * )
+      NEW met2 ( 2380730 17850 ) ( * 131100 )
+      NEW met2 ( 2384630 149260 ) ( * 150240 0 )
+      NEW met2 ( 2384410 149260 ) ( 2384630 * )
+      NEW met2 ( 2384410 131100 ) ( * 149260 )
+      NEW met2 ( 2380730 131100 ) ( 2384410 * )
+      NEW met1 ( 180090 17850 ) M1M2_PR
+      NEW met1 ( 2380730 17850 ) M1M2_PR ;
+    - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( inst_eFPGA_CPU_top wbs_dat_o[7] ) + USE SIGNAL
+      + ROUTED met2 ( 198030 1700 0 ) ( * 18190 )
+      NEW met1 ( 198030 18190 ) ( 2353130 * )
+      NEW met2 ( 2359330 149090 ) ( * 150240 0 )
+      NEW met1 ( 2353130 149090 ) ( 2359330 * )
+      NEW met2 ( 2353130 18190 ) ( * 149090 )
       NEW met1 ( 198030 18190 ) M1M2_PR
-      NEW met1 ( 1236710 17850 ) M1M2_PR
-      NEW met1 ( 1235790 1652570 ) M1M2_PR
-      NEW met1 ( 1236710 1652570 ) M1M2_PR ;
-    - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj wbs_dat_o[8] ) + USE SIGNAL
-      + ROUTED met2 ( 215510 2380 0 ) ( * 18190 )
-      NEW met1 ( 215510 18190 ) ( 1235790 * )
-      NEW met1 ( 1235790 1636930 ) ( 1239930 * )
-      NEW met2 ( 1235790 18190 ) ( * 1636930 )
-      NEW met2 ( 1239930 1690140 ) ( 1241080 * 0 )
-      NEW met2 ( 1239930 1636930 ) ( * 1690140 )
-      NEW met1 ( 215510 18190 ) M1M2_PR
-      NEW met1 ( 1235790 18190 ) M1M2_PR
-      NEW met1 ( 1235790 1636930 ) M1M2_PR
-      NEW met1 ( 1239930 1636930 ) M1M2_PR ;
-    - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj wbs_dat_o[9] ) + USE SIGNAL
-      + ROUTED met2 ( 1243610 18530 ) ( * 1580100 )
-      NEW met2 ( 1243610 1580100 ) ( 1245450 * )
-      NEW met2 ( 1245450 1690140 ) ( 1246600 * 0 )
-      NEW met2 ( 1245450 1580100 ) ( * 1690140 )
-      NEW met2 ( 233450 2380 0 ) ( * 18530 )
-      NEW met1 ( 233450 18530 ) ( 1243610 * )
-      NEW met1 ( 1243610 18530 ) M1M2_PR
-      NEW met1 ( 233450 18530 ) M1M2_PR ;
-    - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj wbs_sel_i[0] ) + USE SIGNAL
-      + ROUTED met2 ( 182850 17850 ) ( * 1680450 )
-      NEW met2 ( 1190710 1680450 ) ( * 1690140 )
-      NEW met2 ( 1190710 1690140 ) ( 1191860 * 0 )
-      NEW met2 ( 55890 2380 0 ) ( * 17850 )
-      NEW met1 ( 55890 17850 ) ( 182850 * )
-      NEW met1 ( 182850 1680450 ) ( 1190710 * )
-      NEW met1 ( 182850 17850 ) M1M2_PR
-      NEW met1 ( 182850 1680450 ) M1M2_PR
-      NEW met1 ( 1190710 1680450 ) M1M2_PR
+      NEW met1 ( 2353130 18190 ) M1M2_PR
+      NEW met1 ( 2359330 149090 ) M1M2_PR
+      NEW met1 ( 2353130 149090 ) M1M2_PR ;
+    - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( inst_eFPGA_CPU_top wbs_dat_o[8] ) + USE SIGNAL
+      + ROUTED met2 ( 215510 1700 0 ) ( * 18530 )
+      NEW met2 ( 2332430 18530 ) ( * 131100 )
+      NEW met2 ( 2334030 149090 ) ( * 150240 0 )
+      NEW met2 ( 2333810 149090 ) ( 2334030 * )
+      NEW met2 ( 2333810 131100 ) ( * 149090 )
+      NEW met2 ( 2332430 131100 ) ( 2333810 * )
+      NEW met1 ( 215510 18530 ) ( 2332430 * )
+      NEW met1 ( 215510 18530 ) M1M2_PR
+      NEW met1 ( 2332430 18530 ) M1M2_PR ;
+    - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( inst_eFPGA_CPU_top wbs_dat_o[9] ) + USE SIGNAL
+      + ROUTED met2 ( 2304830 18870 ) ( * 131100 )
+      NEW met2 ( 2308730 149090 ) ( * 150240 0 )
+      NEW met2 ( 2308510 149090 ) ( 2308730 * )
+      NEW met2 ( 2308510 131100 ) ( * 149090 )
+      NEW met2 ( 2304830 131100 ) ( 2308510 * )
+      NEW met2 ( 233450 1700 0 ) ( * 18870 )
+      NEW met1 ( 233450 18870 ) ( 2304830 * )
+      NEW met1 ( 2304830 18870 ) M1M2_PR
+      NEW met1 ( 233450 18870 ) M1M2_PR ;
+    - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( inst_eFPGA_CPU_top wbs_sel_i[0] ) + USE SIGNAL
+      + ROUTED met2 ( 93150 17850 ) ( * 134470 )
+      NEW met2 ( 2891090 149260 ) ( * 150240 0 )
+      NEW met2 ( 2890870 149260 ) ( 2891090 * )
+      NEW met2 ( 2890870 134470 ) ( * 149260 )
+      NEW met2 ( 55890 1700 0 ) ( * 17850 )
+      NEW met1 ( 55890 17850 ) ( 93150 * )
+      NEW met1 ( 93150 134470 ) ( 2890870 * )
+      NEW met1 ( 93150 17850 ) M1M2_PR
+      NEW met1 ( 93150 134470 ) M1M2_PR
+      NEW met1 ( 2890870 134470 ) M1M2_PR
       NEW met1 ( 55890 17850 ) M1M2_PR ;
-    - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ( mprj wbs_sel_i[1] ) + USE SIGNAL
-      + ROUTED met2 ( 79810 2380 0 ) ( * 18020 )
-      NEW met3 ( 79810 18020 ) ( 1194850 * )
-      NEW met2 ( 1194850 18020 ) ( * 1580100 )
-      NEW met2 ( 1194850 1580100 ) ( 1198070 * )
-      NEW met2 ( 1198070 1690140 ) ( 1199220 * 0 )
-      NEW met2 ( 1198070 1580100 ) ( * 1690140 )
-      NEW met2 ( 79810 18020 ) M2M3_PR_M
-      NEW met2 ( 1194850 18020 ) M2M3_PR_M ;
-    - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ( mprj wbs_sel_i[2] ) + USE SIGNAL
-      + ROUTED met2 ( 103270 2380 0 ) ( * 18530 )
-      NEW li1 ( 182390 18530 ) ( * 19210 )
-      NEW met1 ( 182390 19210 ) ( 217350 * )
-      NEW met2 ( 217350 19210 ) ( * 1681980 )
-      NEW met1 ( 103270 18530 ) ( 182390 * )
-      NEW met2 ( 1205430 1681980 ) ( * 1690140 )
-      NEW met2 ( 1205430 1690140 ) ( 1206580 * 0 )
-      NEW met3 ( 217350 1681980 ) ( 1205430 * )
-      NEW met1 ( 103270 18530 ) M1M2_PR
-      NEW li1 ( 182390 18530 ) L1M1_PR_MR
-      NEW li1 ( 182390 19210 ) L1M1_PR_MR
-      NEW met1 ( 217350 19210 ) M1M2_PR
-      NEW met2 ( 217350 1681980 ) M2M3_PR_M
-      NEW met2 ( 1205430 1681980 ) M2M3_PR_M ;
-    - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ( mprj wbs_sel_i[3] ) + USE SIGNAL
-      + ROUTED met2 ( 126730 2380 0 ) ( * 17170 )
-      NEW met1 ( 126730 17170 ) ( 1208190 * )
-      NEW met1 ( 1208190 1652570 ) ( 1212790 * )
-      NEW met2 ( 1208190 17170 ) ( * 1652570 )
-      NEW met2 ( 1212790 1690140 ) ( 1213940 * 0 )
-      NEW met2 ( 1212790 1652570 ) ( * 1690140 )
-      NEW met1 ( 126730 17170 ) M1M2_PR
-      NEW met1 ( 1208190 17170 ) M1M2_PR
-      NEW met1 ( 1208190 1652570 ) M1M2_PR
-      NEW met1 ( 1212790 1652570 ) M1M2_PR ;
-    - wbs_stb_i ( PIN wbs_stb_i ) ( mprj wbs_stb_i ) + USE SIGNAL
-      + ROUTED met2 ( 26450 2380 0 ) ( * 17510 )
-      NEW met2 ( 1181510 1679940 ) ( * 1690140 )
-      NEW met2 ( 1181510 1690140 ) ( 1182660 * 0 )
-      NEW met1 ( 26450 17510 ) ( 58650 * )
-      NEW met2 ( 58650 17510 ) ( * 1679940 )
-      NEW met3 ( 58650 1679940 ) ( 1181510 * )
-      NEW met1 ( 26450 17510 ) M1M2_PR
-      NEW met2 ( 1181510 1679940 ) M2M3_PR_M
-      NEW met1 ( 58650 17510 ) M1M2_PR
-      NEW met2 ( 58650 1679940 ) M2M3_PR_M ;
-    - wbs_we_i ( PIN wbs_we_i ) ( mprj wbs_we_i ) + USE SIGNAL
-      + ROUTED met2 ( 32430 2380 0 ) ( * 16660 )
-      NEW met2 ( 1181510 16660 ) ( * 1580100 )
-      NEW met2 ( 1181510 1580100 ) ( 1183350 * )
-      NEW met2 ( 1183350 1690140 ) ( 1184500 * 0 )
-      NEW met2 ( 1183350 1580100 ) ( * 1690140 )
-      NEW met3 ( 32430 16660 ) ( 1181510 * )
-      NEW met2 ( 32430 16660 ) M2M3_PR_M
-      NEW met2 ( 1181510 16660 ) M2M3_PR_M ;
+    - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ( inst_eFPGA_CPU_top wbs_sel_i[1] ) + USE SIGNAL
+      + ROUTED met2 ( 79810 1700 0 ) ( * 16660 )
+      NEW met3 ( 79810 16660 ) ( 2863730 * )
+      NEW met2 ( 2863730 16660 ) ( * 131100 )
+      NEW met2 ( 2865330 149260 ) ( * 150240 0 )
+      NEW met2 ( 2865110 149260 ) ( 2865330 * )
+      NEW met2 ( 2865110 131100 ) ( * 149260 )
+      NEW met2 ( 2863730 131100 ) ( 2865110 * )
+      NEW met2 ( 79810 16660 ) M2M3_PR_M
+      NEW met2 ( 2863730 16660 ) M2M3_PR_M ;
+    - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ( inst_eFPGA_CPU_top wbs_sel_i[2] ) + USE SIGNAL
+      + ROUTED met2 ( 103270 1700 0 ) ( * 14790 )
+      NEW met1 ( 103270 14790 ) ( 127650 * )
+      NEW met2 ( 127650 14790 ) ( * 134810 )
+      NEW met2 ( 2840030 149260 ) ( * 150240 0 )
+      NEW met2 ( 2839810 149260 ) ( 2840030 * )
+      NEW met2 ( 2839810 134810 ) ( * 149260 )
+      NEW met1 ( 127650 134810 ) ( 2839810 * )
+      NEW met1 ( 103270 14790 ) M1M2_PR
+      NEW met1 ( 127650 14790 ) M1M2_PR
+      NEW met1 ( 127650 134810 ) M1M2_PR
+      NEW met1 ( 2839810 134810 ) M1M2_PR ;
+    - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ( inst_eFPGA_CPU_top wbs_sel_i[3] ) + USE SIGNAL
+      + ROUTED met2 ( 126730 1700 0 ) ( * 17340 )
+      NEW met2 ( 2814730 149090 ) ( * 150240 0 )
+      NEW met1 ( 2808530 149090 ) ( 2814730 * )
+      NEW met2 ( 2808530 17340 ) ( * 149090 )
+      NEW met3 ( 126730 17340 ) ( 2808530 * )
+      NEW met2 ( 126730 17340 ) M2M3_PR_M
+      NEW met2 ( 2808530 17340 ) M2M3_PR_M
+      NEW met1 ( 2814730 149090 ) M1M2_PR
+      NEW met1 ( 2808530 149090 ) M1M2_PR ;
+    - wbs_stb_i ( PIN wbs_stb_i ) ( inst_eFPGA_CPU_top wbs_stb_i ) + USE SIGNAL
+      + ROUTED met2 ( 20930 82800 ) ( 26450 * )
+      NEW met2 ( 26450 1700 0 ) ( * 82800 )
+      NEW met2 ( 20930 82800 ) ( * 135150 )
+      NEW met2 ( 55650 149260 ) ( * 150240 0 )
+      NEW met2 ( 55430 149260 ) ( 55650 * )
+      NEW met2 ( 55430 135150 ) ( * 149260 )
+      NEW met1 ( 20930 135150 ) ( 55430 * )
+      NEW met1 ( 20930 135150 ) M1M2_PR
+      NEW met1 ( 55430 135150 ) M1M2_PR ;
+    - wbs_we_i ( PIN wbs_we_i ) ( inst_eFPGA_CPU_top wbs_we_i ) + USE SIGNAL
+      + ROUTED met2 ( 27830 82800 ) ( 32430 * )
+      NEW met2 ( 32430 1700 0 ) ( * 82800 )
+      NEW met2 ( 27830 82800 ) ( * 134810 )
+      NEW met2 ( 106250 149260 ) ( * 150240 0 )
+      NEW met2 ( 106030 149260 ) ( 106250 * )
+      NEW met2 ( 106030 134810 ) ( * 149260 )
+      NEW met1 ( 27830 134810 ) ( 106030 * )
+      NEW met1 ( 27830 134810 ) M1M2_PR
+      NEW met1 ( 106030 134810 ) M1M2_PR ;
+    - zero_ ( PIN user_irq[2] ) ( PIN user_irq[1] ) ( PIN user_irq[0] ) + USE GROUND ;
 END NETS
 END DESIGN
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..7c973d9
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..712c038
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,18 @@
+---
+project:
+  description: "ICESOC - Ibex Crypto eFPGA SoC"
+  foundry: "SkyWater"
+  git_url: "https://github.com/nguyendao-uom/ICESOC.git"
+  organization: ""
+  organization_url: ""
+  owner: "Nguyen Dao - Thinh Pham - Andrew Attworth"
+  process: "SKY130"
+  project_name: "ICESOC"
+  project_id: "00000000"
+  tags:
+    - "Open MPW"
+  category: "ICESOC Caravel User Project"
+  top_level_netlist: "caravel/verilog/gl/caravel.v"
+  user_level_netlist: "verilog/gl/user_project_wrapper.v"
+  version: "1.00"
+  cover_image: "pics/icesoc_top.png"
diff --git a/lef/eFPGA_CPU_top.lef b/lef/eFPGA_CPU_top.lef
new file mode 100644
index 0000000..2a63361
--- /dev/null
+++ b/lef/eFPGA_CPU_top.lef
@@ -0,0 +1,115716 @@
+##
+## LEF for PtnCells ;
+## created by Innovus v19.11-s128_1 on Thu Dec 23 15:34:09 2021
+##
+
+VERSION 5.7 ;
+
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO eFPGA_CPU_top
+  CLASS BLOCK ;
+  SIZE 2881.440000 BY 3243.940000 ;
+  FOREIGN eFPGA_CPU_top 0.000000 0.000000 ;
+  ORIGIN 0 0 ;
+  SYMMETRY X Y R90 ;
+  PIN wb_clk_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 7.0867 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 34.8635 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met2  ;
+    ANTENNAMAXAREACAR 23.6049 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 99.2301 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.407937 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 10.280000 0.000000 10.420000 0.485000 ;
+    END
+  END wb_clk_i
+  PIN wb_rst_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.3452 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 61.565 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 9.0637 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 49.28 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.3758 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 23.808 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 76.9079 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 389.984 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2744.060000 0.000000 2744.200000 0.485000 ;
+    END
+  END wb_rst_i
+  PIN wbs_stb_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 97.3268 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 485.765 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 20.877 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 113.696 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.465 LAYER met3  ;
+    ANTENNAMAXAREACAR 153.98 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 785.517 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.43297 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 35.580000 0.000000 35.720000 0.485000 ;
+    END
+  END wbs_stb_i
+  PIN wbs_cyc_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 25.3622 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 126.532 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 11.8882 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 68.104 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 2.9244 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 19.36 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.378 LAYER met4  ;
+    ANTENNAMAXAREACAR 136.275 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 705.328 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.85635 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 60.880000 0.000000 61.020000 0.485000 ;
+    END
+  END wbs_cyc_i
+  PIN wbs_we_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.0014 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.997 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met2  ;
+    ANTENNAMAXAREACAR 43.7262 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 205.123 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.407937 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 86.180000 0.000000 86.320000 0.485000 ;
+    END
+  END wbs_we_i
+  PIN wbs_sel_i[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 167.055 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 834.876 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.2509 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.7788 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 20.624 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 43.3397 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 217.627 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2794.660000 0.000000 2794.800000 0.485000 ;
+    END
+  END wbs_sel_i[3]
+  PIN wbs_sel_i[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 166.513 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 832.286 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 64.3817 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 324.095 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2819.960000 0.000000 2820.100000 0.485000 ;
+    END
+  END wbs_sel_i[2]
+  PIN wbs_sel_i[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 169.653 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 847.987 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.814 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.9696 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.112 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 74.9103 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 395.54 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2845.260000 0.000000 2845.400000 0.485000 ;
+    END
+  END wbs_sel_i[1]
+  PIN wbs_sel_i[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0026 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 10.003 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met2  ;
+    ANTENNAMAXAREACAR 30.5444 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 138.679 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.407937 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2871.020000 0.000000 2871.160000 0.485000 ;
+    END
+  END wbs_sel_i[0]
+  PIN wbs_dat_i[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 17.8846 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 89.026 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 1.4848 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.856 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 2.265 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 14.432 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met4  ;
+    ANTENNAMAXAREACAR 57.1721 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 303.376 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.616901 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 111.480000 0.000000 111.620000 0.485000 ;
+    END
+  END wbs_dat_i[31]
+  PIN wbs_dat_i[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 53.881 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 268.772 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 36.763 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 196.536 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 49.4254 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 247.032 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 136.780000 0.000000 136.920000 0.485000 ;
+    END
+  END wbs_dat_i[30]
+  PIN wbs_dat_i[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.723 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 63.336 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 151.64 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 811.096 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 69.0786 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 345.802 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 162.080000 0.000000 162.220000 0.485000 ;
+    END
+  END wbs_dat_i[29]
+  PIN wbs_dat_i[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.5462 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 71.862 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 52.1566 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 291.336 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 0.9696 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.112 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met4  ;
+    ANTENNAMAXAREACAR 106.066 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 530.966 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.729187 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 187.380000 0.000000 187.520000 0.485000 ;
+    END
+  END wbs_dat_i[28]
+  PIN wbs_dat_i[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.307 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.237 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.4 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.6 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 7.4388 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.144 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met4  ;
+    ANTENNAMAXAREACAR 69.6458 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 360.408 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.616901 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 212.680000 0.000000 212.820000 0.485000 ;
+    END
+  END wbs_dat_i[27]
+  PIN wbs_dat_i[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 38.806 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 193.515 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 26.0542 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 143.656 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 2.2344 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 13.328 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 105.526 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 533.881 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 237.980000 0.000000 238.120000 0.485000 ;
+    END
+  END wbs_dat_i[26]
+  PIN wbs_dat_i[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 110.142 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 550.312 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 349.311 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1863.93 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.8508 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 5.008 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 20.3817 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 96.8016 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 263.280000 0.000000 263.420000 0.485000 ;
+    END
+  END wbs_dat_i[25]
+  PIN wbs_dat_i[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 58.3048 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 290.773 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 472.731 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2525.46 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 60.8024 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 317.675 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 288.580000 0.000000 288.720000 0.485000 ;
+    END
+  END wbs_dat_i[24]
+  PIN wbs_dat_i[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 48.6774 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 242.872 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 36.943 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 197.496 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 58.6619 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 289.667 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 313.880000 0.000000 314.020000 0.485000 ;
+    END
+  END wbs_dat_i[23]
+  PIN wbs_dat_i[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.5128 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 27.167 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.883 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 5.176 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 32.1276 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 172.288 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met4  ;
+    ANTENNAMAXAREACAR 79.3096 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 399.363 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.23435 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 339.180000 0.000000 339.320000 0.485000 ;
+    END
+  END wbs_dat_i[22]
+  PIN wbs_dat_i[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 31.5984 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 157.241 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 4.2946 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.312 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.9696 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.112 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 72.0643 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 385.198 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 364.480000 0.000000 364.620000 0.485000 ;
+    END
+  END wbs_dat_i[21]
+  PIN wbs_dat_i[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 19.178 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 95.375 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 3.367 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 18.424 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.7388 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 74.4888 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 397.744 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 1.8648 LAYER met4  ;
+    ANTENNAMAXAREACAR 49.6305 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 243.866 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.161143 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 389.780000 0.000000 389.920000 0.485000 ;
+    END
+  END wbs_dat_i[20]
+  PIN wbs_dat_i[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.098 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 30.093 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 49.7404 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 267.16 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 28.5444 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 145.722 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 415.080000 0.000000 415.220000 0.485000 ;
+    END
+  END wbs_dat_i[19]
+  PIN wbs_dat_i[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 34.5372 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 172.053 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 32.638 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 179.24 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 9.0054 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 49.44 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met4  ;
+    ANTENNAMAXAREACAR 73.1231 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 358.814 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.23435 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 440.380000 0.000000 440.520000 0.485000 ;
+    END
+  END wbs_dat_i[18]
+  PIN wbs_dat_i[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.9158 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 34.3 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 283.037 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1511.88 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 19.2722 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 94.0556 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 465.680000 0.000000 465.820000 0.485000 ;
+    END
+  END wbs_dat_i[17]
+  PIN wbs_dat_i[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.9044 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 34.125 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 19.5973 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 108.752 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.2474 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.064 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 140.925 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 724.357 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 490.980000 0.000000 491.120000 0.485000 ;
+    END
+  END wbs_dat_i[16]
+  PIN wbs_dat_i[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.6978 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 48.328 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 6.1578 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 33.312 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 68.7421 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 350.77 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 516.280000 0.000000 516.420000 0.485000 ;
+    END
+  END wbs_dat_i[15]
+  PIN wbs_dat_i[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 114.695 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 571.781 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 201.245 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1077.06 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 37.15 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 184.722 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 541.580000 0.000000 541.720000 0.485000 ;
+    END
+  END wbs_dat_i[14]
+  PIN wbs_dat_i[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 55.5152 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 276.353 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 7.3944 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.848 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 110.836 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 569.619 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.725397 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 566.880000 0.000000 567.020000 0.485000 ;
+    END
+  END wbs_dat_i[13]
+  PIN wbs_dat_i[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.2936 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 36.071 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 14.8456 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 82.936 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 105.202 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 524.722 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 592.180000 0.000000 592.320000 0.485000 ;
+    END
+  END wbs_dat_i[12]
+  PIN wbs_dat_i[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.325 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 61.439 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 9.6024 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 52.624 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 1.4247 LAYER met3  ;
+    ANTENNAMAXAREACAR 134.379 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 654.531 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.354037 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 617.480000 0.000000 617.620000 0.485000 ;
+    END
+  END wbs_dat_i[11]
+  PIN wbs_dat_i[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.0752 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.215 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 69.5844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 372.528 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 1.9197 LAYER met3  ;
+    ANTENNAMAXAREACAR 67.4019 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 347.885 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.302277 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 642.780000 0.000000 642.920000 0.485000 ;
+    END
+  END wbs_dat_i[10]
+  PIN wbs_dat_i[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 27.0006 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 134.134 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 32.611 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 179.096 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 16.4442 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 89.584 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met4  ;
+    ANTENNAMAXAREACAR 57.9492 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 288.077 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.23435 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 668.080000 0.000000 668.220000 0.485000 ;
+    END
+  END wbs_dat_i[9]
+  PIN wbs_dat_i[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 42.9708 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 214.221 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 21.6634 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 117.416 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 85.7087 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 427.698 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 693.380000 0.000000 693.520000 0.485000 ;
+    END
+  END wbs_dat_i[8]
+  PIN wbs_dat_i[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 17.2226 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 85.834 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 38.8714 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 213.896 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 7.3584 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.656 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 192.772 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 1002.63 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 718.680000 0.000000 718.820000 0.485000 ;
+    END
+  END wbs_dat_i[7]
+  PIN wbs_dat_i[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 191.72 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 958.202 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 17.488 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 93.736 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 50.1968 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 262.19 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 744.440000 0.000000 744.580000 0.485000 ;
+    END
+  END wbs_dat_i[6]
+  PIN wbs_dat_i[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 20.3112 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 100.569 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 4.2462 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.528 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 97.8452 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 500.357 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.725397 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 769.740000 0.000000 769.880000 0.485000 ;
+    END
+  END wbs_dat_i[5]
+  PIN wbs_dat_i[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 21.3528 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 105.777 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 109.906 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 591.336 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 44.9667 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 228.373 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 795.040000 0.000000 795.180000 0.485000 ;
+    END
+  END wbs_dat_i[4]
+  PIN wbs_dat_i[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0026 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 10.003 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met2  ;
+    ANTENNAMAXAREACAR 23.9 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 105.456 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.407937 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 820.340000 0.000000 820.480000 0.485000 ;
+    END
+  END wbs_dat_i[3]
+  PIN wbs_dat_i[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.5522 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 62.482 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 11.7772 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 65.16 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 55.1976 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 279.183 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 845.640000 0.000000 845.780000 0.485000 ;
+    END
+  END wbs_dat_i[2]
+  PIN wbs_dat_i[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 17.4746 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 86.632 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.4347 LAYER met2  ;
+    ANTENNAMAXAREACAR 44.2922 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 202.03 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAMAXCUTCAR 0.21026 LAYER via2  ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 38.3658 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 205.536 LAYER met3  ;
+    ANTENNAGATEAREA 0.4347 LAYER met3  ;
+    ANTENNAMAXAREACAR 132.55 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 674.853 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAMAXCUTCAR 0.302277 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAGATEAREA 0.9297 LAYER met4  ;
+    ANTENNAMAXAREACAR 136.812 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 698.086 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.302277 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 870.940000 0.000000 871.080000 0.485000 ;
+    END
+  END wbs_dat_i[1]
+  PIN wbs_dat_i[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 14.257 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 70.77 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.4347 LAYER met2  ;
+    ANTENNAMAXAREACAR 36.8903 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 165.541 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAMAXCUTCAR 0.21026 LAYER via2  ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 92.053 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 491.416 LAYER met3  ;
+    ANTENNAGATEAREA 0.4347 LAYER met3  ;
+    ANTENNAMAXAREACAR 248.652 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 1296.01 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAMAXCUTCAR 0.302277 LAYER via3  ;
+    ANTENNADIFFAREA 0.4347 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 96.9096 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 517.792 LAYER met4  ;
+    ANTENNAGATEAREA 1.4247 LAYER met4  ;
+    ANTENNAMAXAREACAR 316.673 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 1659.45 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.302277 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 896.240000 0.000000 896.380000 0.485000 ;
+    END
+  END wbs_dat_i[0]
+  PIN wbs_adr_i[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 921.540000 0.000000 921.680000 0.485000 ;
+    END
+  END wbs_adr_i[31]
+  PIN wbs_adr_i[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 946.840000 0.000000 946.980000 0.485000 ;
+    END
+  END wbs_adr_i[30]
+  PIN wbs_adr_i[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 972.140000 0.000000 972.280000 0.485000 ;
+    END
+  END wbs_adr_i[29]
+  PIN wbs_adr_i[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 997.440000 0.000000 997.580000 0.485000 ;
+    END
+  END wbs_adr_i[28]
+  PIN wbs_adr_i[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1022.740000 0.000000 1022.880000 0.485000 ;
+    END
+  END wbs_adr_i[27]
+  PIN wbs_adr_i[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1048.040000 0.000000 1048.180000 0.485000 ;
+    END
+  END wbs_adr_i[26]
+  PIN wbs_adr_i[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1073.340000 0.000000 1073.480000 0.485000 ;
+    END
+  END wbs_adr_i[25]
+  PIN wbs_adr_i[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1098.640000 0.000000 1098.780000 0.485000 ;
+    END
+  END wbs_adr_i[24]
+  PIN wbs_adr_i[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1123.940000 0.000000 1124.080000 0.485000 ;
+    END
+  END wbs_adr_i[23]
+  PIN wbs_adr_i[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1149.240000 0.000000 1149.380000 0.485000 ;
+    END
+  END wbs_adr_i[22]
+  PIN wbs_adr_i[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1174.540000 0.000000 1174.680000 0.485000 ;
+    END
+  END wbs_adr_i[21]
+  PIN wbs_adr_i[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1199.840000 0.000000 1199.980000 0.485000 ;
+    END
+  END wbs_adr_i[20]
+  PIN wbs_adr_i[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1225.140000 0.000000 1225.280000 0.485000 ;
+    END
+  END wbs_adr_i[19]
+  PIN wbs_adr_i[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1250.440000 0.000000 1250.580000 0.485000 ;
+    END
+  END wbs_adr_i[18]
+  PIN wbs_adr_i[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1275.740000 0.000000 1275.880000 0.485000 ;
+    END
+  END wbs_adr_i[17]
+  PIN wbs_adr_i[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1301.040000 0.000000 1301.180000 0.485000 ;
+    END
+  END wbs_adr_i[16]
+  PIN wbs_adr_i[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1326.340000 0.000000 1326.480000 0.485000 ;
+    END
+  END wbs_adr_i[15]
+  PIN wbs_adr_i[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1351.640000 0.000000 1351.780000 0.485000 ;
+    END
+  END wbs_adr_i[14]
+  PIN wbs_adr_i[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1376.940000 0.000000 1377.080000 0.485000 ;
+    END
+  END wbs_adr_i[13]
+  PIN wbs_adr_i[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1402.240000 0.000000 1402.380000 0.485000 ;
+    END
+  END wbs_adr_i[12]
+  PIN wbs_adr_i[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 87.6844 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 436.373 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 1.8552 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 11.776 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 83.1103 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 415.389 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.725397 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1427.540000 0.000000 1427.680000 0.485000 ;
+    END
+  END wbs_adr_i[11]
+  PIN wbs_adr_i[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 29.0062 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 143.808 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.7896 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 5.152 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met3  ;
+    ANTENNAMAXAREACAR 55.2631 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 276.385 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.429108 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1453.300000 0.000000 1453.440000 0.485000 ;
+    END
+  END wbs_adr_i[10]
+  PIN wbs_adr_i[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1478.600000 0.000000 1478.740000 0.485000 ;
+    END
+  END wbs_adr_i[9]
+  PIN wbs_adr_i[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 1503.900000 0.000000 1504.040000 0.485000 ;
+    END
+  END wbs_adr_i[8]
+  PIN wbs_adr_i[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 15.7378 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 77.938 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 19.1926 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 106.12 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.9696 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.112 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 67.5294 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 360.492 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1529.200000 0.000000 1529.340000 0.485000 ;
+    END
+  END wbs_adr_i[7]
+  PIN wbs_adr_i[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 32.614 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 161.847 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 5.4628 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 30.072 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.9696 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.112 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 75.0357 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 384.214 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1554.500000 0.000000 1554.640000 0.485000 ;
+    END
+  END wbs_adr_i[6]
+  PIN wbs_adr_i[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 109.523 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 547.218 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.2509 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.5588 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.784 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 77.6476 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 407.841 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1579.800000 0.000000 1579.940000 0.485000 ;
+    END
+  END wbs_adr_i[5]
+  PIN wbs_adr_i[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.7786 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 73.024 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.1448 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 22.576 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 186.139 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 929.619 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1605.100000 0.000000 1605.240000 0.485000 ;
+    END
+  END wbs_adr_i[4]
+  PIN wbs_adr_i[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.488 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 7.161 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 6.2766 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 34.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 80.45 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 415.349 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1630.400000 0.000000 1630.540000 0.485000 ;
+    END
+  END wbs_adr_i[3]
+  PIN wbs_adr_i[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 62.4846 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 310.492 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 24.679 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 134.44 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.3258 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.208 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 107.931 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 542.762 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1655.700000 0.000000 1655.840000 0.485000 ;
+    END
+  END wbs_adr_i[2]
+  PIN wbs_adr_i[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.3462 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.216 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 39.7756 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 213.544 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.3258 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.208 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met4  ;
+    ANTENNAMAXAREACAR 92.0195 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 472.85 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.616901 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1681.000000 0.000000 1681.140000 0.485000 ;
+    END
+  END wbs_adr_i[1]
+  PIN wbs_adr_i[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.8304 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 33.873 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 12.889 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 69.208 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 0.6516 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.416 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 51.4722 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 274.833 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1706.300000 0.000000 1706.440000 0.485000 ;
+    END
+  END wbs_adr_i[0]
+  PIN wbs_ack_o
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 206.089 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1030.2 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2769.360000 0.000000 2769.500000 0.485000 ;
+    END
+  END wbs_ack_o
+  PIN wbs_dat_o[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 46.2894 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 230.965 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 1731.600000 0.000000 1731.740000 0.485000 ;
+    END
+  END wbs_dat_o[31]
+  PIN wbs_dat_o[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 42.8522 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 213.864 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 52.0968 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 278.32 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1756.900000 0.000000 1757.040000 0.485000 ;
+    END
+  END wbs_dat_o[30]
+  PIN wbs_dat_o[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 15.019 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 74.816 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 1.987 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 11.064 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 19.4058 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 103.968 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1782.200000 0.000000 1782.340000 0.485000 ;
+    END
+  END wbs_dat_o[29]
+  PIN wbs_dat_o[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.953 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 59.486 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 43.8618 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 234.4 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1807.500000 0.000000 1807.640000 0.485000 ;
+    END
+  END wbs_dat_o[28]
+  PIN wbs_dat_o[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 117.612 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 587.461 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 1832.800000 0.000000 1832.940000 0.485000 ;
+    END
+  END wbs_dat_o[27]
+  PIN wbs_dat_o[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 115.367 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 576.436 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 43.939 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 234.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 7.6218 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 41.12 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1858.100000 0.000000 1858.240000 0.485000 ;
+    END
+  END wbs_dat_o[26]
+  PIN wbs_dat_o[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 48.4622 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 242.032 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 55.2516 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 295.616 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1883.400000 0.000000 1883.540000 0.485000 ;
+    END
+  END wbs_dat_o[25]
+  PIN wbs_dat_o[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 19.9666 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 99.554 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.814 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 82.8588 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 442.384 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1908.700000 0.000000 1908.840000 0.485000 ;
+    END
+  END wbs_dat_o[24]
+  PIN wbs_dat_o[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 139.525 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 697.263 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 1934.000000 0.000000 1934.140000 0.485000 ;
+    END
+  END wbs_dat_o[23]
+  PIN wbs_dat_o[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 160.179 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 800.177 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 1959.300000 0.000000 1959.440000 0.485000 ;
+    END
+  END wbs_dat_o[22]
+  PIN wbs_dat_o[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.2406 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 70.924 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 94.3108 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 503.928 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 323.162 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1724 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1984.600000 0.000000 1984.740000 0.485000 ;
+    END
+  END wbs_dat_o[21]
+  PIN wbs_dat_o[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.742 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 68.313 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 244.723 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1305.66 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 394.532 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2104.64 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2009.900000 0.000000 2010.040000 0.485000 ;
+    END
+  END wbs_dat_o[20]
+  PIN wbs_dat_o[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 105.099 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 525.014 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2035.200000 0.000000 2035.340000 0.485000 ;
+    END
+  END wbs_dat_o[19]
+  PIN wbs_dat_o[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.5791 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 67.6165 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 231.434 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1235.72 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 206.695 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1103.31 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2060.500000 0.000000 2060.640000 0.485000 ;
+    END
+  END wbs_dat_o[18]
+  PIN wbs_dat_o[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 116.265 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 580.93 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 133.289 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 711.344 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 2085.800000 0.000000 2085.940000 0.485000 ;
+    END
+  END wbs_dat_o[17]
+  PIN wbs_dat_o[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.0034 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 49.777 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.469 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.968 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 129.644 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 691.904 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2111.100000 0.000000 2111.240000 0.485000 ;
+    END
+  END wbs_dat_o[16]
+  PIN wbs_dat_o[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 152.762 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 763.329 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2136.400000 0.000000 2136.540000 0.485000 ;
+    END
+  END wbs_dat_o[15]
+  PIN wbs_dat_o[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.9262 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 44.352 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.6368 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 9.2 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 2162.160000 0.000000 2162.300000 0.485000 ;
+    END
+  END wbs_dat_o[14]
+  PIN wbs_dat_o[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 76.0604 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 380.023 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 13.2948 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 71.376 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2187.460000 0.000000 2187.600000 0.485000 ;
+    END
+  END wbs_dat_o[13]
+  PIN wbs_dat_o[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.2468 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 60.837 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.607 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 3.704 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 394.16 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2102.66 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2212.760000 0.000000 2212.900000 0.485000 ;
+    END
+  END wbs_dat_o[12]
+  PIN wbs_dat_o[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.3772 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 61.607 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.4 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.6 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 373.265 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1991.22 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2238.060000 0.000000 2238.200000 0.485000 ;
+    END
+  END wbs_dat_o[11]
+  PIN wbs_dat_o[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.9582 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 74.431 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 159.19 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 849.472 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 2.3148 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 12.816 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2263.360000 0.000000 2263.500000 0.485000 ;
+    END
+  END wbs_dat_o[10]
+  PIN wbs_dat_o[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.0684 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 70.063 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.4 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.6 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 382.129 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2038.96 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2288.660000 0.000000 2288.800000 0.485000 ;
+    END
+  END wbs_dat_o[9]
+  PIN wbs_dat_o[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.548 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 62.461 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.26895 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.832 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 327.785 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1748.66 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2313.960000 0.000000 2314.100000 0.485000 ;
+    END
+  END wbs_dat_o[8]
+  PIN wbs_dat_o[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.671 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 27.958 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 7.0048 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 38.296 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 443.96 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2368.26 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2339.260000 0.000000 2339.400000 0.485000 ;
+    END
+  END wbs_dat_o[7]
+  PIN wbs_dat_o[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.6754 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 63.098 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.26895 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.832 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 448.04 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2390.02 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2364.560000 0.000000 2364.700000 0.485000 ;
+    END
+  END wbs_dat_o[6]
+  PIN wbs_dat_o[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 14.004 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 69.741 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.607 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 3.704 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 256.964 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1370.94 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2389.860000 0.000000 2390.000000 0.485000 ;
+    END
+  END wbs_dat_o[5]
+  PIN wbs_dat_o[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 15.285 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 76.125 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.2509 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 9.4518 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 50.88 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2415.160000 0.000000 2415.300000 0.485000 ;
+    END
+  END wbs_dat_o[4]
+  PIN wbs_dat_o[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.5848 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 7.763 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 128.83 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 687.56 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 389.432 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2077.44 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2440.460000 0.000000 2440.600000 0.485000 ;
+    END
+  END wbs_dat_o[3]
+  PIN wbs_dat_o[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 19.0412 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 94.927 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.0848 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 6.256 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 2465.760000 0.000000 2465.900000 0.485000 ;
+    END
+  END wbs_dat_o[2]
+  PIN wbs_dat_o[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.9264 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 9.471 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 110.593 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 590.296 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 248.714 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1326.94 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2491.060000 0.000000 2491.200000 0.485000 ;
+    END
+  END wbs_dat_o[1]
+  PIN wbs_dat_o[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.133 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 0.504 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 106.315 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 567.48 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 450.674 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2404.06 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2516.360000 0.000000 2516.500000 0.485000 ;
+    END
+  END wbs_dat_o[0]
+  PIN la_data_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 135.805 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 678.895 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2642.860000 0.000000 2643.000000 0.485000 ;
+    END
+  END la_data_out[2]
+  PIN la_data_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 11.0354 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 55.167 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2668.160000 0.000000 2668.300000 0.485000 ;
+    END
+  END la_data_out[1]
+  PIN la_data_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 7.2818 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 36.281 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2693.460000 0.000000 2693.600000 0.485000 ;
+    END
+  END la_data_out[0]
+  PIN la_data_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 19.9219 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 99.0395 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.6822 LAYER met2  ;
+    ANTENNAMAXAREACAR 34.4472 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 156.783 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.207677 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2541.660000 0.000000 2541.800000 0.485000 ;
+    END
+  END la_data_in[3]
+  PIN la_data_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 33.4514 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 166.978 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.2475 LAYER met4  ;
+    ANTENNAMAXAREACAR 45.3289 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 233.212 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.530909 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2566.960000 0.000000 2567.100000 0.485000 ;
+    END
+  END la_data_in[2]
+  PIN la_data_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 42.2868 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 211.155 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 6.1578 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 33.312 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 91.023 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 479.54 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2592.260000 0.000000 2592.400000 0.485000 ;
+    END
+  END la_data_in[1]
+  PIN la_data_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 19.3854 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 96.53 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 2.7157 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 15.424 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 2.1318 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 11.84 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 31.2349 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 152.746 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2617.560000 0.000000 2617.700000 0.485000 ;
+    END
+  END la_data_in[0]
+  PIN io_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 9.880000 0.800000 10.180000 ;
+    END
+  END io_in[37]
+  PIN io_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 245.950000 0.800000 246.250000 ;
+    END
+  END io_in[36]
+  PIN io_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 482.020000 0.800000 482.320000 ;
+    END
+  END io_in[35]
+  PIN io_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 718.090000 0.800000 718.390000 ;
+    END
+  END io_in[34]
+  PIN io_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 953.550000 0.800000 953.850000 ;
+    END
+  END io_in[33]
+  PIN io_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1189.620000 0.800000 1189.920000 ;
+    END
+  END io_in[32]
+  PIN io_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1425.690000 0.800000 1425.990000 ;
+    END
+  END io_in[31]
+  PIN io_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1661.150000 0.800000 1661.450000 ;
+    END
+  END io_in[30]
+  PIN io_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1897.220000 0.800000 1897.520000 ;
+    END
+  END io_in[29]
+  PIN io_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2133.290000 0.800000 2133.590000 ;
+    END
+  END io_in[28]
+  PIN io_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2369.360000 0.800000 2369.660000 ;
+    END
+  END io_in[27]
+  PIN io_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.5433 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.696 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.1448 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 22.576 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 52.1183 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 264.897 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2604.820000 0.800000 2605.120000 ;
+    END
+  END io_in[26]
+  PIN io_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.0253 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 32.6 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 48.6841 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 246.706 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2840.890000 0.800000 2841.190000 ;
+    END
+  END io_in[25]
+  PIN io_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.5213 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 29.912 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 46.4952 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 235.762 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 3076.960000 0.800000 3077.260000 ;
+    END
+  END io_in[24]
+  PIN io_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 18.6914 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 93.296 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.1448 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 22.576 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.1965 LAYER met4  ;
+    ANTENNAMAXAREACAR 29.1537 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 149.399 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.668702 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 230.160000 3243.455000 230.300000 3243.940000 ;
+    END
+  END io_in[23]
+  PIN io_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 23.366 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 116.669 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.1448 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 22.576 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met4  ;
+    ANTENNAMAXAREACAR 26.2101 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 139.751 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.616901 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 559.980000 3243.455000 560.120000 3243.940000 ;
+    END
+  END io_in[22]
+  PIN io_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 122.078 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 610.113 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.7788 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 20.624 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 96.331 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 487.389 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 890.260000 3243.455000 890.400000 3243.940000 ;
+    END
+  END io_in[21]
+  PIN io_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 17.6804 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 88.123 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.2509 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.9248 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 26.736 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met4  ;
+    ANTENNAMAXAREACAR 42.7791 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 223.596 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.616901 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1220.540000 3243.455000 1220.680000 3243.940000 ;
+    END
+  END io_in[20]
+  PIN io_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 21.3539 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 106.642 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.9297 LAYER met2  ;
+    ANTENNAMAXAREACAR 28.6359 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 124.545 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.090684 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 1550.360000 3243.455000 1550.500000 3243.940000 ;
+    END
+  END io_in[19]
+  PIN io_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 69.4692 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 347.067 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.2509 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 8.1708 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 44.048 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.2475 LAYER met4  ;
+    ANTENNAMAXAREACAR 58.8234 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 306.913 LAYER met4  ;
+    ANTENNAMAXCUTCAR 0.530909 LAYER via4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1880.640000 3243.455000 1880.780000 3243.940000 ;
+    END
+  END io_in[18]
+  PIN io_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.151 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 20.594 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 1.5984 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 9.936 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met3  ;
+    ANTENNAMAXAREACAR 49.4932 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 252.671 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.429108 LAYER via3  ;
+    PORT
+      LAYER met2 ;
+        RECT 2210.460000 3243.455000 2210.600000 3243.940000 ;
+    END
+  END io_in[17]
+  PIN io_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2540.740000 3243.455000 2540.880000 3243.940000 ;
+    END
+  END io_in[16]
+  PIN io_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met2 ;
+        RECT 2870.560000 3243.455000 2870.700000 3243.940000 ;
+    END
+  END io_in[15]
+  PIN io_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 3087.330000 2881.440000 3087.630000 ;
+    END
+  END io_in[14]
+  PIN io_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2867.730000 2881.440000 2868.030000 ;
+    END
+  END io_in[13]
+  PIN io_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2648.130000 2881.440000 2648.430000 ;
+    END
+  END io_in[12]
+  PIN io_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2427.920000 2881.440000 2428.220000 ;
+    END
+  END io_in[11]
+  PIN io_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2208.320000 2881.440000 2208.620000 ;
+    END
+  END io_in[10]
+  PIN io_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.3314 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 23.576 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met3  ;
+    ANTENNAMAXAREACAR 101.757 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 515.249 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.429108 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1988.720000 2881.440000 1989.020000 ;
+    END
+  END io_in[9]
+  PIN io_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.6936 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 73.024 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 4.4304 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 25.04 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 64.3349 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 332.73 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1768.510000 2881.440000 1768.810000 ;
+    END
+  END io_in[8]
+  PIN io_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.4224 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.728 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.213 LAYER met3  ;
+    ANTENNAMAXAREACAR 16.9908 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 83.9249 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.429108 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1548.910000 2881.440000 1549.210000 ;
+    END
+  END io_in[7]
+  PIN io_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 22.2595 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 98.627 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.725397 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1329.310000 2881.440000 1329.610000 ;
+    END
+  END io_in[6]
+  PIN io_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.032 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 39.368 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 103.871 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 537.429 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 7.3986 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.4 LAYER met4  ;
+    ANTENNAGATEAREA 0.8685 LAYER met4  ;
+    ANTENNAMAXAREACAR 112.389 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 583.946 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1109.100000 2881.440000 1109.400000 ;
+    END
+  END io_in[5]
+  PIN io_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.5574 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 3.416 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNAPARTIALMETALAREA 3.9618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met4  ;
+    ANTENNAMAXAREACAR 39.0611 LAYER met4  ;
+    ANTENNAMAXSIDEAREACAR 201.524 LAYER met4  ;
+    ANTENNAMAXCUTCAR 1.04286 LAYER via4  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 889.500000 2881.440000 889.800000 ;
+    END
+  END io_in[4]
+  PIN io_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.126 LAYER met3  ;
+    ANTENNAMAXAREACAR 99.2611 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 484.571 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.725397 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 669.900000 2881.440000 670.200000 ;
+    END
+  END io_in[3]
+  PIN io_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 6.1434 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 32.76 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.6867 LAYER met3  ;
+    ANTENNAMAXAREACAR 130.47 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 642.066 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.262218 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 449.690000 2881.440000 449.990000 ;
+    END
+  END io_in[2]
+  PIN io_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 6.4014 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 34.136 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.6867 LAYER met3  ;
+    ANTENNAMAXAREACAR 62.4647 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 302.18 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.262218 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 230.090000 2881.440000 230.390000 ;
+    END
+  END io_in[1]
+  PIN io_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 8.0274 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 42.808 LAYER met3  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met3  ;
+    ANTENNAMAXAREACAR 33.0643 LAYER met3  ;
+    ANTENNAMAXSIDEAREACAR 155.374 LAYER met3  ;
+    ANTENNAMAXCUTCAR 0.479276 LAYER via3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 10.490000 2881.440000 10.790000 ;
+    END
+  END io_in[0]
+  PIN io_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 88.570000 0.800000 88.870000 ;
+    END
+  END io_out[37]
+  PIN io_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 324.640000 0.800000 324.940000 ;
+    END
+  END io_out[36]
+  PIN io_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 3.0444 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 16.712 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 560.710000 0.800000 561.010000 ;
+    END
+  END io_out[35]
+  PIN io_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 4.8384 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 26.28 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 796.780000 0.800000 797.080000 ;
+    END
+  END io_out[34]
+  PIN io_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.3884 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 7.88 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1032.240000 0.800000 1032.540000 ;
+    END
+  END io_out[33]
+  PIN io_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 4.2864 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 23.336 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1268.310000 0.800000 1268.610000 ;
+    END
+  END io_out[32]
+  PIN io_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1504.380000 0.800000 1504.680000 ;
+    END
+  END io_out[31]
+  PIN io_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1739.840000 0.800000 1740.140000 ;
+    END
+  END io_out[30]
+  PIN io_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1975.910000 0.800000 1976.210000 ;
+    END
+  END io_out[29]
+  PIN io_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 4.5624 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 24.808 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2211.980000 0.800000 2212.280000 ;
+    END
+  END io_out[28]
+  PIN io_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.4224 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.728 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2447.440000 0.800000 2447.740000 ;
+    END
+  END io_out[27]
+  PIN io_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 7.5542 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 40.584 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2683.510000 0.800000 2683.810000 ;
+    END
+  END io_out[26]
+  PIN io_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.2876 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 44.192 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 559.511 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2984.53 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2919.580000 0.800000 2919.880000 ;
+    END
+  END io_out[25]
+  PIN io_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 12.5372 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 67.16 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 3155.650000 0.800000 3155.950000 ;
+    END
+  END io_out[24]
+  PIN io_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 21.3164 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 106.421 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 25.24 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 135.08 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 578.996 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 3088.45 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 120.220000 3243.455000 120.360000 3243.940000 ;
+    END
+  END io_out[23]
+  PIN io_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 279.042 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1394.93 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 2.539 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 14.008 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 201.085 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1073.39 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 450.040000 3243.455000 450.180000 3243.940000 ;
+    END
+  END io_out[22]
+  PIN io_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 327.173 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1635.47 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 3.022 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 16.584 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 95.1198 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 507.776 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 780.320000 3243.455000 780.460000 3243.940000 ;
+    END
+  END io_out[21]
+  PIN io_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 395.933 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1979.15 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 12.9368 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 69.296 LAYER met3  ;
+    PORT
+      LAYER met2 ;
+        RECT 1110.140000 3243.455000 1110.280000 3243.940000 ;
+    END
+  END io_out[20]
+  PIN io_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 24.3318 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 121.38 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 2.056 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 11.432 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 564.308 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 3010.11 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1440.420000 3243.455000 1440.560000 3243.940000 ;
+    END
+  END io_out[19]
+  PIN io_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 18.6408 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 92.925 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.4 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.6 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 772.612 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4121.54 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1770.700000 3243.455000 1770.840000 3243.940000 ;
+    END
+  END io_out[18]
+  PIN io_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 18.6884 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 93.163 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.676 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.072 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 788.842 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4209.04 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2100.520000 3243.455000 2100.660000 3243.940000 ;
+    END
+  END io_out[17]
+  PIN io_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 28.9814 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 144.746 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 46.561 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 248.792 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 221.231 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1180.37 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 2430.800000 3243.455000 2430.940000 3243.940000 ;
+    END
+  END io_out[16]
+  PIN io_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 1.6687 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.3335 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2760.620000 3243.455000 2760.760000 3243.940000 ;
+    END
+  END io_out[15]
+  PIN io_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 3160.530000 2881.440000 3160.830000 ;
+    END
+  END io_out[14]
+  PIN io_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2940.930000 2881.440000 2941.230000 ;
+    END
+  END io_out[13]
+  PIN io_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.8754 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 10.464 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 77.5998 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 414.336 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2721.330000 2881.440000 2721.630000 ;
+    END
+  END io_out[12]
+  PIN io_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 24.0654 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 128.824 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2501.120000 2881.440000 2501.420000 ;
+    END
+  END io_out[11]
+  PIN io_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.2386 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.264 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 188.108 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1003.71 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2281.520000 2881.440000 2281.820000 ;
+    END
+  END io_out[10]
+  PIN io_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2061.920000 2881.440000 2062.220000 ;
+    END
+  END io_out[9]
+  PIN io_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 5.1144 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 27.752 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1841.710000 2881.440000 1842.010000 ;
+    END
+  END io_out[8]
+  PIN io_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1622.110000 2881.440000 1622.410000 ;
+    END
+  END io_out[7]
+  PIN io_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 23.7894 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 127.352 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1402.510000 2881.440000 1402.810000 ;
+    END
+  END io_out[6]
+  PIN io_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1182.300000 2881.440000 1182.600000 ;
+    END
+  END io_out[5]
+  PIN io_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 962.700000 2881.440000 963.000000 ;
+    END
+  END io_out[4]
+  PIN io_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 5.6664 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 30.696 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 743.100000 2881.440000 743.400000 ;
+    END
+  END io_out[3]
+  PIN io_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 522.890000 2881.440000 523.190000 ;
+    END
+  END io_out[2]
+  PIN io_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.5264 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.616 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 303.290000 2881.440000 303.590000 ;
+    END
+  END io_out[1]
+  PIN io_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 83.690000 2881.440000 83.990000 ;
+    END
+  END io_out[0]
+  PIN io_oeb[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.3884 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 7.88 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 167.260000 0.800000 167.560000 ;
+    END
+  END io_oeb[37]
+  PIN io_oeb[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 3.0444 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 16.712 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 403.330000 0.800000 403.630000 ;
+    END
+  END io_oeb[36]
+  PIN io_oeb[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 3.1824 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 17.448 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 639.400000 0.800000 639.700000 ;
+    END
+  END io_oeb[35]
+  PIN io_oeb[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 6.6774 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 36.088 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 874.860000 0.800000 875.160000 ;
+    END
+  END io_oeb[34]
+  PIN io_oeb[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.7434 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.44 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1110.930000 0.800000 1111.230000 ;
+    END
+  END io_oeb[33]
+  PIN io_oeb[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 4.2864 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 23.336 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1347.000000 0.800000 1347.300000 ;
+    END
+  END io_oeb[32]
+  PIN io_oeb[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1583.070000 0.800000 1583.370000 ;
+    END
+  END io_oeb[31]
+  PIN io_oeb[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 1818.530000 0.800000 1818.830000 ;
+    END
+  END io_oeb[30]
+  PIN io_oeb[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.3884 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 7.88 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2054.600000 0.800000 2054.900000 ;
+    END
+  END io_oeb[29]
+  PIN io_oeb[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2290.670000 0.800000 2290.970000 ;
+    END
+  END io_oeb[28]
+  PIN io_oeb[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2526.130000 0.800000 2526.430000 ;
+    END
+  END io_oeb[27]
+  PIN io_oeb[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6636 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.864 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 533.683 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2847.25 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2762.200000 0.800000 2762.500000 ;
+    END
+  END io_oeb[26]
+  PIN io_oeb[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.6236 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 61.984 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 559.75 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 2986.27 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 2998.270000 0.800000 2998.570000 ;
+    END
+  END io_oeb[25]
+  PIN io_oeb[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.2386 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.264 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 617.06 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 3291.46 LAYER met4  ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000000 3233.730000 0.800000 3234.030000 ;
+    END
+  END io_oeb[24]
+  PIN io_oeb[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 262.102 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1310.35 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.26895 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.832 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 63.6678 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 340.032 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 10.280000 3243.455000 10.420000 3243.940000 ;
+    END
+  END io_oeb[23]
+  PIN io_oeb[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 278.927 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1394.24 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 2.608 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 14.376 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 91.4838 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 488.384 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 340.100000 3243.455000 340.240000 3243.940000 ;
+    END
+  END io_oeb[22]
+  PIN io_oeb[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 344.78 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1723.51 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.745 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 4.44 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 63.7398 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 340.416 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 670.380000 3243.455000 670.520000 3243.940000 ;
+    END
+  END io_oeb[21]
+  PIN io_oeb[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 274.363 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1371.42 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.255 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 275.368 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 1469.57 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1000.200000 3243.455000 1000.340000 3243.940000 ;
+    END
+  END io_oeb[20]
+  PIN io_oeb[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 281.951 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1409.48 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 0.469 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 2.968 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 98.1264 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 524.752 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1330.480000 3243.455000 1330.620000 3243.940000 ;
+    END
+  END io_oeb[19]
+  PIN io_oeb[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 24.8372 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 123.907 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 1.504 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.488 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 841.618 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 4489.57 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1660.300000 3243.455000 1660.440000 3243.940000 ;
+    END
+  END io_oeb[18]
+  PIN io_oeb[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 234.942 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 1174.19 LAYER met2  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via2  ;
+    ANTENNAPARTIALMETALAREA 4.354 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 23.688 LAYER met3  ;
+    ANTENNAPARTIALCUTAREA 0.04 LAYER via3  ;
+    ANTENNADIFFAREA 1.782 LAYER met4  ;
+    ANTENNAPARTIALMETALAREA 34.3398 LAYER met4  ;
+    ANTENNAPARTIALMETALSIDEAREA 183.616 LAYER met4  ;
+    PORT
+      LAYER met2 ;
+        RECT 1990.580000 3243.455000 1990.720000 3243.940000 ;
+    END
+  END io_oeb[17]
+  PIN io_oeb[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 1.6687 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.3335 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2320.860000 3243.455000 2321.000000 3243.940000 ;
+    END
+  END io_oeb[16]
+  PIN io_oeb[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 1.6687 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.3335 LAYER met2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2650.680000 3243.455000 2650.820000 3243.940000 ;
+    END
+  END io_oeb[15]
+  PIN io_oeb[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 2.2164 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 12.296 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 3233.730000 2881.440000 3234.030000 ;
+    END
+  END io_oeb[14]
+  PIN io_oeb[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 3014.130000 2881.440000 3014.430000 ;
+    END
+  END io_oeb[13]
+  PIN io_oeb[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.5264 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.616 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2794.530000 2881.440000 2794.830000 ;
+    END
+  END io_oeb[12]
+  PIN io_oeb[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2574.320000 2881.440000 2574.620000 ;
+    END
+  END io_oeb[11]
+  PIN io_oeb[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.5264 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.616 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2354.720000 2881.440000 2355.020000 ;
+    END
+  END io_oeb[10]
+  PIN io_oeb[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 2135.120000 2881.440000 2135.420000 ;
+    END
+  END io_oeb[9]
+  PIN io_oeb[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1914.910000 2881.440000 1915.210000 ;
+    END
+  END io_oeb[8]
+  PIN io_oeb[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1695.310000 2881.440000 1695.610000 ;
+    END
+  END io_oeb[7]
+  PIN io_oeb[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1475.710000 2881.440000 1476.010000 ;
+    END
+  END io_oeb[6]
+  PIN io_oeb[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 8.3784 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 45.16 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1255.500000 2881.440000 1255.800000 ;
+    END
+  END io_oeb[5]
+  PIN io_oeb[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 1035.900000 2881.440000 1036.200000 ;
+    END
+  END io_oeb[4]
+  PIN io_oeb[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 816.300000 2881.440000 816.600000 ;
+    END
+  END io_oeb[3]
+  PIN io_oeb[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 596.090000 2881.440000 596.390000 ;
+    END
+  END io_oeb[2]
+  PIN io_oeb[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 0.2844 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 376.490000 2881.440000 376.790000 ;
+    END
+  END io_oeb[1]
+  PIN io_oeb[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 1.782 LAYER met3  ;
+    ANTENNAPARTIALMETALAREA 1.5264 LAYER met3  ;
+    ANTENNAPARTIALMETALSIDEAREA 8.616 LAYER met3  ;
+    PORT
+      LAYER met3 ;
+        RECT 2880.640000 156.890000 2881.440000 157.190000 ;
+    END
+  END io_oeb[0]
+  PIN user_clock2
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNADIFFAREA 0.4347 LAYER met2  ;
+    ANTENNAPARTIALMETALAREA 6.6383 LAYER met2  ;
+    ANTENNAPARTIALMETALSIDEAREA 32.8475 LAYER met2  ;
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNAGATEAREA 0.5607 LAYER met2  ;
+    ANTENNAMAXAREACAR 30.6587 LAYER met2  ;
+    ANTENNAMAXSIDEAREACAR 134.55 LAYER met2  ;
+    ANTENNAMAXCUTCAR 0.407937 LAYER via2  ;
+    PORT
+      LAYER met2 ;
+        RECT 2718.760000 0.000000 2718.900000 0.485000 ;
+    END
+  END user_clock2
+  PIN vssd1
+    DIRECTION INOUT ;
+    USE GROUND ;
+
+# P/G power stripe data as pin
+    PORT
+      LAYER met3 ;
+        RECT 2.000000 2.000000 2879.440000 5.000000 ;
+        RECT 2.000000 83.720000 2879.440000 84.920000 ;
+        RECT 2.000000 93.720000 2879.440000 94.920000 ;
+        RECT 2.000000 137.420000 2742.060000 138.620000 ;
+        RECT 319.660000 137.420000 2879.440000 138.620000 ;
+        RECT 2.000000 110.970000 2742.060000 112.170000 ;
+        RECT 319.660000 110.970000 2879.440000 112.170000 ;
+        RECT 2.000000 103.720000 2879.440000 104.920000 ;
+        RECT 2.000000 1355.540000 2879.440000 1356.740000 ;
+        RECT 615.280000 1382.790000 2141.760000 1383.990000 ;
+        RECT 2.000000 137.420000 120.760000 138.620000 ;
+        RECT 118.910000 110.970000 120.760000 112.170000 ;
+        RECT 615.280000 1382.790000 726.060000 1383.990000 ;
+        RECT 615.280000 1382.790000 681.040000 1383.990000 ;
+        RECT 615.280000 1578.560000 681.040000 1579.760000 ;
+        RECT 924.960000 942.270000 926.670000 943.470000 ;
+        RECT 724.500000 942.270000 726.060000 943.470000 ;
+        RECT 724.500000 1338.810000 726.060000 1340.010000 ;
+        RECT 720.910000 1382.790000 722.110000 1383.990000 ;
+        RECT 719.860000 1382.790000 721.510000 1383.990000 ;
+        RECT 924.960000 1338.810000 926.670000 1340.010000 ;
+        RECT 929.430000 1382.790000 931.160000 1383.990000 ;
+        RECT 929.430000 1578.560000 931.160000 1579.760000 ;
+        RECT 719.260000 1578.560000 719.860000 1579.760000 ;
+        RECT 1130.060000 1578.560000 1132.290000 1579.760000 ;
+        RECT 1131.690000 1578.560000 1132.890000 1579.760000 ;
+        RECT 1130.060000 1382.790000 1132.290000 1383.990000 ;
+        RECT 1131.690000 1382.790000 1132.890000 1383.990000 ;
+        RECT 2849.770000 141.350000 2879.440000 142.550000 ;
+        RECT 2850.800000 137.420000 2879.440000 138.620000 ;
+        RECT 2850.800000 110.970000 2879.440000 112.170000 ;
+        RECT 2849.170000 141.350000 2850.370000 142.550000 ;
+        RECT 2180.580000 1382.790000 2266.240000 1383.990000 ;
+        RECT 2180.580000 1578.560000 2266.240000 1579.760000 ;
+        RECT 1534.790000 942.270000 1536.460000 943.470000 ;
+        RECT 1534.190000 942.270000 1535.390000 943.470000 ;
+        RECT 1735.360000 942.270000 1737.190000 943.470000 ;
+        RECT 1736.590000 942.270000 1737.790000 943.470000 ;
+        RECT 1534.790000 1382.790000 1536.460000 1383.990000 ;
+        RECT 1534.190000 1382.790000 1535.390000 1383.990000 ;
+        RECT 1534.190000 1338.810000 1535.390000 1340.010000 ;
+        RECT 1534.790000 1338.810000 1536.460000 1340.010000 ;
+        RECT 1735.360000 1338.810000 1737.190000 1340.010000 ;
+        RECT 1736.590000 1338.810000 1737.790000 1340.010000 ;
+        RECT 615.280000 1816.060000 2266.240000 1817.260000 ;
+        RECT 615.280000 2256.580000 2266.240000 2257.780000 ;
+        RECT 615.280000 1823.310000 2141.760000 1824.510000 ;
+        RECT 615.280000 2263.830000 2141.760000 2265.030000 ;
+        RECT 615.280000 2704.350000 2141.760000 2705.550000 ;
+        RECT 615.280000 2697.100000 2266.240000 2698.300000 ;
+        RECT 928.830000 3100.370000 1532.400000 3101.570000 ;
+        RECT 2.000000 3238.940000 2879.440000 3241.940000 ;
+        RECT 615.280000 1782.700000 721.510000 1783.900000 ;
+        RECT 615.280000 1823.310000 681.040000 1824.510000 ;
+        RECT 615.280000 2019.080000 681.040000 2020.280000 ;
+        RECT 615.280000 2223.120000 721.510000 2224.320000 ;
+        RECT 615.280000 2263.830000 681.040000 2265.030000 ;
+        RECT 2.000000 1740.050000 40.720000 1741.250000 ;
+        RECT 589.680000 1740.050000 616.480000 1741.250000 ;
+        RECT 586.320000 1735.270000 616.480000 1736.470000 ;
+        RECT 585.720000 1735.270000 586.920000 1736.470000 ;
+        RECT 2.000000 2331.810000 40.720000 2333.010000 ;
+        RECT 2.000000 2338.770000 44.080000 2339.970000 ;
+        RECT 43.480000 2338.770000 44.680000 2339.970000 ;
+        RECT 589.680000 2331.810000 616.480000 2333.010000 ;
+        RECT 586.320000 2337.070000 616.480000 2338.270000 ;
+        RECT 585.720000 2337.070000 586.920000 2338.270000 ;
+        RECT 720.910000 1782.700000 722.110000 1783.900000 ;
+        RECT 720.910000 1779.330000 722.110000 1780.530000 ;
+        RECT 721.510000 1779.330000 726.060000 1780.530000 ;
+        RECT 719.860000 1823.310000 721.510000 1824.510000 ;
+        RECT 720.910000 1823.310000 722.110000 1824.510000 ;
+        RECT 723.900000 1823.310000 725.100000 1824.510000 ;
+        RECT 724.500000 1823.310000 726.060000 1824.510000 ;
+        RECT 924.960000 1779.330000 928.050000 1780.530000 ;
+        RECT 929.430000 1823.310000 931.160000 1824.510000 ;
+        RECT 924.960000 1823.310000 926.670000 1824.510000 ;
+        RECT 929.430000 2019.080000 931.160000 2020.280000 ;
+        RECT 719.260000 2019.080000 719.860000 2020.280000 ;
+        RECT 1130.060000 2019.080000 1132.290000 2020.280000 ;
+        RECT 1131.690000 2019.080000 1132.890000 2020.280000 ;
+        RECT 1131.690000 1823.310000 1132.890000 1824.510000 ;
+        RECT 1130.060000 1823.310000 1132.290000 1824.510000 ;
+        RECT 721.510000 2219.850000 726.060000 2221.050000 ;
+        RECT 720.910000 2219.850000 722.110000 2221.050000 ;
+        RECT 720.910000 2223.120000 722.110000 2224.320000 ;
+        RECT 924.960000 2219.850000 926.670000 2221.050000 ;
+        RECT 723.900000 2263.830000 725.100000 2265.030000 ;
+        RECT 719.860000 2263.830000 721.510000 2265.030000 ;
+        RECT 720.910000 2263.830000 722.110000 2265.030000 ;
+        RECT 724.500000 2263.830000 726.060000 2265.030000 ;
+        RECT 924.960000 2263.830000 926.670000 2265.030000 ;
+        RECT 929.430000 2263.830000 931.160000 2265.030000 ;
+        RECT 928.830000 2263.830000 930.030000 2265.030000 ;
+        RECT 1131.690000 2263.830000 1132.890000 2265.030000 ;
+        RECT 1130.060000 2263.830000 1132.290000 2265.030000 ;
+        RECT 615.280000 2459.600000 681.040000 2460.800000 ;
+        RECT 615.280000 2665.370000 721.510000 2666.570000 ;
+        RECT 615.280000 2704.350000 681.040000 2705.550000 ;
+        RECT 615.280000 2900.120000 681.040000 2901.320000 ;
+        RECT 615.280000 3131.310000 923.930000 3132.510000 ;
+        RECT 615.280000 3131.310000 727.090000 3132.510000 ;
+        RECT 615.280000 3100.370000 722.110000 3101.570000 ;
+        RECT 615.280000 3100.370000 722.340000 3101.570000 ;
+        RECT 929.430000 2459.600000 931.160000 2460.800000 ;
+        RECT 928.830000 2459.600000 930.030000 2460.800000 ;
+        RECT 719.260000 2459.600000 719.860000 2460.800000 ;
+        RECT 721.510000 2660.370000 726.060000 2661.570000 ;
+        RECT 720.910000 2660.370000 722.110000 2661.570000 ;
+        RECT 720.910000 2665.370000 722.110000 2666.570000 ;
+        RECT 719.860000 2704.350000 721.510000 2705.550000 ;
+        RECT 720.910000 2704.350000 722.110000 2705.550000 ;
+        RECT 724.500000 2704.350000 726.060000 2705.550000 ;
+        RECT 924.960000 2660.370000 928.050000 2661.570000 ;
+        RECT 929.430000 2704.350000 931.160000 2705.550000 ;
+        RECT 924.960000 2704.350000 926.670000 2705.550000 ;
+        RECT 1130.060000 2459.600000 1132.290000 2460.800000 ;
+        RECT 1131.690000 2459.600000 1132.890000 2460.800000 ;
+        RECT 1130.060000 2704.350000 1132.290000 2705.550000 ;
+        RECT 1131.690000 2704.350000 1132.890000 2705.550000 ;
+        RECT 929.430000 2900.120000 931.160000 2901.320000 ;
+        RECT 719.260000 2900.120000 719.860000 2901.320000 ;
+        RECT 721.140000 3100.710000 930.030000 3101.910000 ;
+        RECT 720.910000 3100.370000 722.110000 3102.090000 ;
+        RECT 721.140000 3100.370000 722.340000 3101.910000 ;
+        RECT 721.140000 3100.370000 722.340000 3102.090000 ;
+        RECT 720.910000 3100.890000 726.060000 3102.090000 ;
+        RECT 726.490000 3131.310000 727.690000 3132.510000 ;
+        RECT 923.330000 3131.310000 924.530000 3132.510000 ;
+        RECT 924.360000 3100.890000 924.960000 3102.090000 ;
+        RECT 928.830000 3100.370000 930.030000 3101.910000 ;
+        RECT 1130.060000 2900.120000 1132.290000 2901.320000 ;
+        RECT 1131.690000 2900.120000 1132.890000 2901.320000 ;
+        RECT 2180.580000 2019.080000 2266.240000 2020.280000 ;
+        RECT 1534.790000 1823.310000 1536.460000 1824.510000 ;
+        RECT 1534.190000 1823.310000 1535.390000 1824.510000 ;
+        RECT 1533.410000 1779.330000 1536.460000 1780.530000 ;
+        RECT 1735.360000 1823.310000 1737.190000 1824.510000 ;
+        RECT 1736.590000 1823.310000 1737.790000 1824.510000 ;
+        RECT 1735.360000 1779.330000 1738.570000 1780.530000 ;
+        RECT 2180.580000 1823.310000 2182.470000 1824.510000 ;
+        RECT 2181.870000 1823.310000 2183.070000 1824.510000 ;
+        RECT 1735.360000 2219.850000 1738.570000 2221.050000 ;
+        RECT 1534.790000 2219.850000 1536.460000 2221.050000 ;
+        RECT 1534.790000 2263.830000 1536.460000 2265.030000 ;
+        RECT 1735.360000 2263.830000 1737.190000 2265.030000 ;
+        RECT 1736.590000 2263.830000 1737.790000 2265.030000 ;
+        RECT 2181.870000 2263.830000 2183.070000 2265.030000 ;
+        RECT 2180.580000 2263.830000 2182.470000 2265.030000 ;
+        RECT 2265.040000 1790.030000 2291.840000 1791.230000 ;
+        RECT 2265.040000 1785.250000 2295.200000 1786.450000 ;
+        RECT 2294.600000 1785.250000 2295.800000 1786.450000 ;
+        RECT 2837.440000 1783.550000 2879.440000 1784.750000 ;
+        RECT 2840.800000 1790.030000 2879.440000 1791.230000 ;
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+    END
+# end of P/G power stripe data as pin
+
+
+# P/G pin shape extracted from block 'W_IO'
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+
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+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
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+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
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+    END
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+    END
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 117.930000 140.180000 119.130000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 117.930000 339.240000 119.130000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 337.000000 120.160000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 1941.060000 3104.870000 2141.160000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2139.960000 3131.320000 2141.160000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+
+
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+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+        RECT 2141.160000 141.230000 2341.260000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 140.180000 2143.390000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 339.240000 2143.390000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2339.030000 140.180000 2340.230000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2339.030000 339.240000 2340.230000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 141.230000 2341.260000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 337.000000 2341.260000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 2141.160000 110.970000 2341.260000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 138.980000 2143.390000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2339.030000 109.920000 2340.230000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2339.030000 138.980000 2340.230000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 110.970000 2142.360000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 110.970000 2341.260000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 137.420000 2142.360000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 137.420000 2341.260000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 2178.950000 3019.940000 2180.150000 3020.420000 ;
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+        RECT 2178.950000 3009.060000 2180.150000 3009.540000 ;
+        RECT 2178.950000 3014.500000 2180.150000 3014.980000 ;
+        RECT 2142.190000 3096.100000 2143.390000 3096.580000 ;
+        RECT 2146.055000 3096.100000 2147.420000 3096.580000 ;
+        RECT 2146.055000 3090.660000 2147.420000 3091.140000 ;
+        RECT 2142.190000 3090.660000 2143.390000 3091.140000 ;
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+        RECT 2142.190000 3085.220000 2143.390000 3085.700000 ;
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+        RECT 2146.055000 3079.780000 2147.420000 3080.260000 ;
+        RECT 2146.055000 3074.340000 2147.420000 3074.820000 ;
+        RECT 2142.190000 3074.340000 2143.390000 3074.820000 ;
+        RECT 2146.055000 3068.900000 2147.420000 3069.380000 ;
+        RECT 2142.190000 3068.900000 2143.390000 3069.380000 ;
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+        RECT 2142.190000 3063.460000 2143.390000 3063.940000 ;
+        RECT 2146.055000 3058.020000 2147.420000 3058.500000 ;
+        RECT 2142.190000 3058.020000 2143.390000 3058.500000 ;
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+        RECT 2142.190000 3052.580000 2143.390000 3053.060000 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 3102.620000 2143.390000 3103.820000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 3100.380000 2181.180000 3101.580000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
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+        RECT 2141.160000 2704.350000 2181.180000 2705.550000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 2703.300000 2143.390000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 2902.360000 2143.390000 2903.560000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 2703.300000 2180.150000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 2902.360000 2180.150000 2903.560000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2704.350000 2142.360000 2705.550000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2704.350000 2181.180000 2705.550000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2900.120000 2142.360000 2901.320000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2900.120000 2181.180000 2901.320000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 2662.100000 2180.150000 2663.300000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2659.860000 2181.180000 2661.060000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
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+        RECT 2141.160000 2459.600000 2181.180000 2460.800000 ;
+        RECT 2141.160000 2263.830000 2181.180000 2265.030000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 2461.840000 2143.390000 2463.040000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 2262.780000 2180.150000 2263.980000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 2461.840000 2180.150000 2463.040000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2263.830000 2142.360000 2265.030000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2263.830000 2181.180000 2265.030000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2459.600000 2142.360000 2460.800000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2459.600000 2181.180000 2460.800000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 2021.320000 2143.390000 2022.520000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2019.080000 2181.180000 2020.280000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
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+        RECT 2141.160000 1778.820000 2181.180000 1780.020000 ;
+        RECT 2141.160000 1583.050000 2181.180000 1584.250000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 1781.060000 2143.390000 1782.260000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 1582.000000 2180.150000 1583.200000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 1781.060000 2180.150000 1782.260000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1583.050000 2142.360000 1584.250000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1583.050000 2181.180000 1584.250000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1778.820000 2142.360000 1780.020000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1778.820000 2181.180000 1780.020000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 2142.190000 1438.280000 2143.390000 1438.760000 ;
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+        RECT 2146.055000 1389.320000 2147.420000 1389.800000 ;
+        RECT 2142.190000 1481.800000 2143.390000 1482.280000 ;
+        RECT 2146.055000 1481.800000 2147.420000 1482.280000 ;
+        RECT 2178.950000 1481.800000 2180.150000 1482.280000 ;
+        RECT 2141.160000 1578.560000 2181.180000 1579.760000 ;
+        RECT 2141.160000 1382.790000 2181.180000 1383.990000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 1381.740000 2143.390000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2142.190000 1580.800000 2143.390000 1582.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 1381.740000 2180.150000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2178.950000 1580.800000 2180.150000 1582.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1382.790000 2142.360000 1383.990000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1382.790000 2181.180000 1383.990000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1578.560000 2142.360000 1579.760000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1578.560000 2181.180000 1579.760000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO_bot'
+    PORT
+      LAYER met4 ;
+        RECT 2146.055000 1334.020000 2147.420000 1334.500000 ;
+        RECT 2146.055000 1323.140000 2147.420000 1323.620000 ;
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+        RECT 2146.055000 1306.820000 2147.420000 1307.300000 ;
+        RECT 2146.055000 1301.380000 2147.420000 1301.860000 ;
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+        RECT 2146.055000 1290.500000 2147.420000 1290.980000 ;
+        RECT 2146.055000 1279.620000 2147.420000 1280.100000 ;
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+        RECT 2146.055000 1198.020000 2147.420000 1198.500000 ;
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+        RECT 2146.220000 1142.530000 2147.420000 1339.500000 ;
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+      LAYER met3 ;
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+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO_bot'
+
+
+# P/G pin shape extracted from block 'RegFile'
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+
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+        RECT 2436.320000 240.240000 2437.520000 240.720000 ;
+        RECT 2391.320000 240.240000 2392.520000 240.720000 ;
+        RECT 2346.155000 240.240000 2347.520000 240.720000 ;
+        RECT 2341.260000 337.000000 2541.360000 338.200000 ;
+        RECT 2341.260000 141.230000 2541.360000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 140.180000 2343.490000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 339.240000 2343.490000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 140.180000 2540.330000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 339.240000 2540.330000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 141.230000 2342.460000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 141.230000 2541.360000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 337.000000 2342.460000 338.200000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 337.000000 2541.360000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 2346.155000 133.820000 2347.520000 134.300000 ;
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+        RECT 2346.155000 122.940000 2347.520000 123.420000 ;
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+        RECT 2526.320000 110.970000 2527.520000 138.620000 ;
+      LAYER met3 ;
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+        RECT 2539.130000 128.380000 2540.330000 128.860000 ;
+        RECT 2526.320000 133.820000 2527.520000 134.300000 ;
+        RECT 2526.320000 128.380000 2527.520000 128.860000 ;
+        RECT 2481.320000 128.380000 2482.520000 128.860000 ;
+        RECT 2481.320000 133.820000 2482.520000 134.300000 ;
+        RECT 2436.320000 128.380000 2437.520000 128.860000 ;
+        RECT 2391.320000 128.380000 2392.520000 128.860000 ;
+        RECT 2436.320000 133.820000 2437.520000 134.300000 ;
+        RECT 2391.320000 133.820000 2392.520000 134.300000 ;
+        RECT 2346.155000 133.820000 2347.520000 134.300000 ;
+        RECT 2342.290000 133.820000 2343.490000 134.300000 ;
+        RECT 2346.155000 128.380000 2347.520000 128.860000 ;
+        RECT 2342.290000 128.380000 2343.490000 128.860000 ;
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+        RECT 2526.320000 122.940000 2527.520000 123.420000 ;
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+        RECT 2481.320000 117.500000 2482.520000 117.980000 ;
+        RECT 2481.320000 122.940000 2482.520000 123.420000 ;
+        RECT 2436.320000 117.500000 2437.520000 117.980000 ;
+        RECT 2391.320000 117.500000 2392.520000 117.980000 ;
+        RECT 2436.320000 122.940000 2437.520000 123.420000 ;
+        RECT 2391.320000 122.940000 2392.520000 123.420000 ;
+        RECT 2346.155000 122.940000 2347.520000 123.420000 ;
+        RECT 2342.290000 122.940000 2343.490000 123.420000 ;
+        RECT 2346.155000 117.500000 2347.520000 117.980000 ;
+        RECT 2342.290000 117.500000 2343.490000 117.980000 ;
+        RECT 2341.260000 137.420000 2541.360000 138.620000 ;
+        RECT 2341.260000 110.970000 2541.360000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 109.920000 2343.490000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 138.980000 2343.490000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 109.920000 2540.330000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 138.980000 2540.330000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 110.970000 2342.460000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 110.970000 2541.360000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 137.420000 2342.460000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 137.420000 2541.360000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 2346.155000 1165.380000 2347.520000 1165.860000 ;
+        RECT 2346.155000 1159.940000 2347.520000 1160.420000 ;
+        RECT 2346.155000 1154.500000 2347.520000 1154.980000 ;
+        RECT 2346.155000 1149.060000 2347.520000 1149.540000 ;
+        RECT 2342.290000 1141.480000 2343.490000 1171.740000 ;
+        RECT 2539.130000 1141.480000 2540.330000 1171.740000 ;
+        RECT 2346.320000 1142.530000 2347.520000 1170.180000 ;
+        RECT 2391.320000 1142.530000 2392.520000 1170.180000 ;
+        RECT 2436.320000 1142.530000 2437.520000 1170.180000 ;
+        RECT 2481.320000 1142.530000 2482.520000 1170.180000 ;
+        RECT 2526.320000 1142.530000 2527.520000 1170.180000 ;
+      LAYER met3 ;
+        RECT 2539.130000 1165.380000 2540.330000 1165.860000 ;
+        RECT 2539.130000 1159.940000 2540.330000 1160.420000 ;
+        RECT 2526.320000 1165.380000 2527.520000 1165.860000 ;
+        RECT 2526.320000 1159.940000 2527.520000 1160.420000 ;
+        RECT 2481.320000 1159.940000 2482.520000 1160.420000 ;
+        RECT 2481.320000 1165.380000 2482.520000 1165.860000 ;
+        RECT 2436.320000 1159.940000 2437.520000 1160.420000 ;
+        RECT 2391.320000 1159.940000 2392.520000 1160.420000 ;
+        RECT 2436.320000 1165.380000 2437.520000 1165.860000 ;
+        RECT 2391.320000 1165.380000 2392.520000 1165.860000 ;
+        RECT 2346.155000 1165.380000 2347.520000 1165.860000 ;
+        RECT 2342.290000 1165.380000 2343.490000 1165.860000 ;
+        RECT 2346.155000 1159.940000 2347.520000 1160.420000 ;
+        RECT 2342.290000 1159.940000 2343.490000 1160.420000 ;
+        RECT 2539.130000 1154.500000 2540.330000 1154.980000 ;
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+        RECT 2526.320000 1149.060000 2527.520000 1149.540000 ;
+        RECT 2481.320000 1149.060000 2482.520000 1149.540000 ;
+        RECT 2481.320000 1154.500000 2482.520000 1154.980000 ;
+        RECT 2436.320000 1149.060000 2437.520000 1149.540000 ;
+        RECT 2391.320000 1149.060000 2392.520000 1149.540000 ;
+        RECT 2436.320000 1154.500000 2437.520000 1154.980000 ;
+        RECT 2391.320000 1154.500000 2392.520000 1154.980000 ;
+        RECT 2346.155000 1154.500000 2347.520000 1154.980000 ;
+        RECT 2342.290000 1154.500000 2343.490000 1154.980000 ;
+        RECT 2346.155000 1149.060000 2347.520000 1149.540000 ;
+        RECT 2342.290000 1149.060000 2343.490000 1149.540000 ;
+        RECT 2341.260000 1168.980000 2541.360000 1170.180000 ;
+        RECT 2341.260000 1142.530000 2541.360000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 1141.480000 2343.490000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2342.290000 1170.540000 2343.490000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 1141.480000 2540.330000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2539.130000 1170.540000 2540.330000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 1142.530000 2342.460000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 1142.530000 2541.360000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 1168.980000 2342.460000 1170.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 1168.980000 2541.360000 1170.180000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single2'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 2546.255000 1133.760000 2547.620000 1134.240000 ;
+        RECT 2546.255000 1122.880000 2547.620000 1123.360000 ;
+        RECT 2546.255000 1128.320000 2547.620000 1128.800000 ;
+        RECT 2546.255000 1117.440000 2547.620000 1117.920000 ;
+        RECT 2546.255000 1112.000000 2547.620000 1112.480000 ;
+        RECT 2546.255000 1106.560000 2547.620000 1107.040000 ;
+        RECT 2546.255000 1101.120000 2547.620000 1101.600000 ;
+        RECT 2546.255000 1095.680000 2547.620000 1096.160000 ;
+        RECT 2546.255000 1090.240000 2547.620000 1090.720000 ;
+        RECT 2546.255000 1079.360000 2547.620000 1079.840000 ;
+        RECT 2546.255000 1084.800000 2547.620000 1085.280000 ;
+        RECT 2546.255000 1073.920000 2547.620000 1074.400000 ;
+        RECT 2546.255000 1068.480000 2547.620000 1068.960000 ;
+        RECT 2546.255000 1063.040000 2547.620000 1063.520000 ;
+        RECT 2546.255000 1057.600000 2547.620000 1058.080000 ;
+        RECT 2546.255000 1052.160000 2547.620000 1052.640000 ;
+        RECT 2546.255000 1046.720000 2547.620000 1047.200000 ;
+        RECT 2546.255000 1035.840000 2547.620000 1036.320000 ;
+        RECT 2546.255000 1030.400000 2547.620000 1030.880000 ;
+        RECT 2546.255000 1024.960000 2547.620000 1025.440000 ;
+        RECT 2546.255000 1019.520000 2547.620000 1020.000000 ;
+        RECT 2546.255000 1014.080000 2547.620000 1014.560000 ;
+        RECT 2546.255000 1008.640000 2547.620000 1009.120000 ;
+        RECT 2546.255000 997.760000 2547.620000 998.240000 ;
+        RECT 2546.255000 1003.200000 2547.620000 1003.680000 ;
+        RECT 2546.255000 992.320000 2547.620000 992.800000 ;
+        RECT 2546.255000 986.880000 2547.620000 987.360000 ;
+        RECT 2546.255000 981.440000 2547.620000 981.920000 ;
+        RECT 2546.255000 976.000000 2547.620000 976.480000 ;
+        RECT 2546.255000 970.560000 2547.620000 971.040000 ;
+        RECT 2546.255000 965.120000 2547.620000 965.600000 ;
+        RECT 2546.255000 954.240000 2547.620000 954.720000 ;
+        RECT 2546.255000 959.680000 2547.620000 960.160000 ;
+        RECT 2546.255000 948.800000 2547.620000 949.280000 ;
+        RECT 2546.255000 1041.280000 2547.620000 1041.760000 ;
+        RECT 2726.420000 942.270000 2727.620000 1139.240000 ;
+        RECT 2681.420000 942.270000 2682.620000 1139.240000 ;
+        RECT 2739.230000 941.220000 2740.430000 1141.480000 ;
+        RECT 2636.420000 942.270000 2637.620000 1139.240000 ;
+        RECT 2591.420000 942.270000 2592.620000 1139.240000 ;
+        RECT 2546.420000 942.270000 2547.620000 1139.240000 ;
+        RECT 2542.390000 941.220000 2543.590000 1141.480000 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
+    PORT
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
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+
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+        RECT 2546.255000 180.400000 2547.620000 180.880000 ;
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+        RECT 2546.255000 174.960000 2547.620000 175.440000 ;
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+        RECT 2546.255000 169.520000 2547.620000 170.000000 ;
+        RECT 2542.390000 164.080000 2543.590000 164.560000 ;
+        RECT 2546.255000 164.080000 2547.620000 164.560000 ;
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+        RECT 2546.255000 153.200000 2547.620000 153.680000 ;
+        RECT 2542.390000 158.640000 2543.590000 159.120000 ;
+        RECT 2546.255000 158.640000 2547.620000 159.120000 ;
+        RECT 2542.390000 147.760000 2543.590000 148.240000 ;
+        RECT 2546.255000 147.760000 2547.620000 148.240000 ;
+        RECT 2681.420000 240.240000 2682.620000 240.720000 ;
+        RECT 2726.420000 240.240000 2727.620000 240.720000 ;
+        RECT 2739.230000 240.240000 2740.430000 240.720000 ;
+        RECT 2591.420000 240.240000 2592.620000 240.720000 ;
+        RECT 2636.420000 240.240000 2637.620000 240.720000 ;
+        RECT 2542.390000 240.240000 2543.590000 240.720000 ;
+        RECT 2546.255000 240.240000 2547.620000 240.720000 ;
+        RECT 2541.360000 337.000000 2741.460000 338.200000 ;
+        RECT 2541.360000 141.230000 2741.460000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 140.180000 2543.590000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 339.240000 2543.590000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 140.180000 2740.430000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 339.240000 2740.430000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 141.230000 2542.560000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 141.230000 2741.460000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 337.000000 2542.560000 338.200000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 337.000000 2741.460000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 2546.255000 133.820000 2547.620000 134.300000 ;
+        RECT 2546.255000 128.380000 2547.620000 128.860000 ;
+        RECT 2546.255000 122.940000 2547.620000 123.420000 ;
+        RECT 2546.255000 117.500000 2547.620000 117.980000 ;
+        RECT 2542.390000 109.920000 2543.590000 140.180000 ;
+        RECT 2739.230000 109.920000 2740.430000 140.180000 ;
+        RECT 2546.420000 110.970000 2547.620000 138.620000 ;
+        RECT 2591.420000 110.970000 2592.620000 138.620000 ;
+        RECT 2636.420000 110.970000 2637.620000 138.620000 ;
+        RECT 2681.420000 110.970000 2682.620000 138.620000 ;
+        RECT 2726.420000 110.970000 2727.620000 138.620000 ;
+      LAYER met3 ;
+        RECT 2739.230000 133.820000 2740.430000 134.300000 ;
+        RECT 2739.230000 128.380000 2740.430000 128.860000 ;
+        RECT 2726.420000 133.820000 2727.620000 134.300000 ;
+        RECT 2726.420000 128.380000 2727.620000 128.860000 ;
+        RECT 2681.420000 128.380000 2682.620000 128.860000 ;
+        RECT 2681.420000 133.820000 2682.620000 134.300000 ;
+        RECT 2636.420000 128.380000 2637.620000 128.860000 ;
+        RECT 2591.420000 128.380000 2592.620000 128.860000 ;
+        RECT 2636.420000 133.820000 2637.620000 134.300000 ;
+        RECT 2591.420000 133.820000 2592.620000 134.300000 ;
+        RECT 2546.255000 133.820000 2547.620000 134.300000 ;
+        RECT 2542.390000 133.820000 2543.590000 134.300000 ;
+        RECT 2546.255000 128.380000 2547.620000 128.860000 ;
+        RECT 2542.390000 128.380000 2543.590000 128.860000 ;
+        RECT 2739.230000 122.940000 2740.430000 123.420000 ;
+        RECT 2739.230000 117.500000 2740.430000 117.980000 ;
+        RECT 2726.420000 122.940000 2727.620000 123.420000 ;
+        RECT 2726.420000 117.500000 2727.620000 117.980000 ;
+        RECT 2681.420000 117.500000 2682.620000 117.980000 ;
+        RECT 2681.420000 122.940000 2682.620000 123.420000 ;
+        RECT 2636.420000 117.500000 2637.620000 117.980000 ;
+        RECT 2591.420000 117.500000 2592.620000 117.980000 ;
+        RECT 2636.420000 122.940000 2637.620000 123.420000 ;
+        RECT 2591.420000 122.940000 2592.620000 123.420000 ;
+        RECT 2546.255000 122.940000 2547.620000 123.420000 ;
+        RECT 2542.390000 122.940000 2543.590000 123.420000 ;
+        RECT 2546.255000 117.500000 2547.620000 117.980000 ;
+        RECT 2542.390000 117.500000 2543.590000 117.980000 ;
+        RECT 2541.360000 137.420000 2741.460000 138.620000 ;
+        RECT 2541.360000 110.970000 2741.460000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 109.920000 2543.590000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 138.980000 2543.590000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 109.920000 2740.430000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 138.980000 2740.430000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 110.970000 2542.560000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 110.970000 2741.460000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 137.420000 2542.560000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 137.420000 2741.460000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 2546.255000 1165.380000 2547.620000 1165.860000 ;
+        RECT 2546.255000 1159.940000 2547.620000 1160.420000 ;
+        RECT 2546.255000 1154.500000 2547.620000 1154.980000 ;
+        RECT 2546.255000 1149.060000 2547.620000 1149.540000 ;
+        RECT 2542.390000 1141.480000 2543.590000 1171.740000 ;
+        RECT 2739.230000 1141.480000 2740.430000 1171.740000 ;
+        RECT 2546.420000 1142.530000 2547.620000 1170.180000 ;
+        RECT 2591.420000 1142.530000 2592.620000 1170.180000 ;
+        RECT 2636.420000 1142.530000 2637.620000 1170.180000 ;
+        RECT 2681.420000 1142.530000 2682.620000 1170.180000 ;
+        RECT 2726.420000 1142.530000 2727.620000 1170.180000 ;
+      LAYER met3 ;
+        RECT 2739.230000 1165.380000 2740.430000 1165.860000 ;
+        RECT 2739.230000 1159.940000 2740.430000 1160.420000 ;
+        RECT 2726.420000 1165.380000 2727.620000 1165.860000 ;
+        RECT 2726.420000 1159.940000 2727.620000 1160.420000 ;
+        RECT 2681.420000 1159.940000 2682.620000 1160.420000 ;
+        RECT 2681.420000 1165.380000 2682.620000 1165.860000 ;
+        RECT 2636.420000 1159.940000 2637.620000 1160.420000 ;
+        RECT 2591.420000 1159.940000 2592.620000 1160.420000 ;
+        RECT 2636.420000 1165.380000 2637.620000 1165.860000 ;
+        RECT 2591.420000 1165.380000 2592.620000 1165.860000 ;
+        RECT 2546.255000 1165.380000 2547.620000 1165.860000 ;
+        RECT 2542.390000 1165.380000 2543.590000 1165.860000 ;
+        RECT 2546.255000 1159.940000 2547.620000 1160.420000 ;
+        RECT 2542.390000 1159.940000 2543.590000 1160.420000 ;
+        RECT 2739.230000 1154.500000 2740.430000 1154.980000 ;
+        RECT 2739.230000 1149.060000 2740.430000 1149.540000 ;
+        RECT 2726.420000 1154.500000 2727.620000 1154.980000 ;
+        RECT 2726.420000 1149.060000 2727.620000 1149.540000 ;
+        RECT 2681.420000 1149.060000 2682.620000 1149.540000 ;
+        RECT 2681.420000 1154.500000 2682.620000 1154.980000 ;
+        RECT 2636.420000 1149.060000 2637.620000 1149.540000 ;
+        RECT 2591.420000 1149.060000 2592.620000 1149.540000 ;
+        RECT 2636.420000 1154.500000 2637.620000 1154.980000 ;
+        RECT 2591.420000 1154.500000 2592.620000 1154.980000 ;
+        RECT 2546.255000 1154.500000 2547.620000 1154.980000 ;
+        RECT 2542.390000 1154.500000 2543.590000 1154.980000 ;
+        RECT 2546.255000 1149.060000 2547.620000 1149.540000 ;
+        RECT 2542.390000 1149.060000 2543.590000 1149.540000 ;
+        RECT 2541.360000 1168.980000 2741.460000 1170.180000 ;
+        RECT 2541.360000 1142.530000 2741.460000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 1141.480000 2543.590000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2542.390000 1170.540000 2543.590000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 1141.480000 2740.430000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2739.230000 1170.540000 2740.430000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 1142.530000 2542.560000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 1142.530000 2741.460000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 1168.980000 2542.560000 1170.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 1168.980000 2741.460000 1170.180000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2746.355000 1128.320000 2747.720000 1128.800000 ;
+        RECT 2746.355000 1122.880000 2747.720000 1123.360000 ;
+        RECT 2746.355000 1117.440000 2747.720000 1117.920000 ;
+        RECT 2746.355000 1133.760000 2747.720000 1134.240000 ;
+        RECT 2746.355000 1112.000000 2747.720000 1112.480000 ;
+        RECT 2746.355000 1106.560000 2747.720000 1107.040000 ;
+        RECT 2746.355000 1101.120000 2747.720000 1101.600000 ;
+        RECT 2746.355000 1095.680000 2747.720000 1096.160000 ;
+        RECT 2746.355000 1079.360000 2747.720000 1079.840000 ;
+        RECT 2746.355000 1073.920000 2747.720000 1074.400000 ;
+        RECT 2746.355000 1068.480000 2747.720000 1068.960000 ;
+        RECT 2746.355000 1084.800000 2747.720000 1085.280000 ;
+        RECT 2746.355000 1090.240000 2747.720000 1090.720000 ;
+        RECT 2746.355000 1063.040000 2747.720000 1063.520000 ;
+        RECT 2746.355000 1057.600000 2747.720000 1058.080000 ;
+        RECT 2746.355000 1052.160000 2747.720000 1052.640000 ;
+        RECT 2746.355000 1046.720000 2747.720000 1047.200000 ;
+        RECT 2746.355000 1024.960000 2747.720000 1025.440000 ;
+        RECT 2746.355000 1019.520000 2747.720000 1020.000000 ;
+        RECT 2746.355000 1030.400000 2747.720000 1030.880000 ;
+        RECT 2746.355000 1035.840000 2747.720000 1036.320000 ;
+        RECT 2746.355000 1014.080000 2747.720000 1014.560000 ;
+        RECT 2746.355000 1008.640000 2747.720000 1009.120000 ;
+        RECT 2746.355000 1003.200000 2747.720000 1003.680000 ;
+        RECT 2746.355000 997.760000 2747.720000 998.240000 ;
+        RECT 2746.355000 992.320000 2747.720000 992.800000 ;
+        RECT 2746.355000 981.440000 2747.720000 981.920000 ;
+        RECT 2746.355000 976.000000 2747.720000 976.480000 ;
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+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
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+
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+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
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+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
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+        RECT 2791.520000 240.240000 2792.720000 240.720000 ;
+        RECT 2742.490000 240.240000 2743.690000 240.720000 ;
+        RECT 2746.355000 240.240000 2747.720000 240.720000 ;
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+        RECT 2741.460000 337.000000 2851.400000 338.200000 ;
+        RECT 2741.460000 141.230000 2851.400000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 140.180000 2743.690000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 339.240000 2743.690000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 140.180000 2850.370000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 339.240000 2850.370000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 141.230000 2742.660000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 141.230000 2851.400000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 337.000000 2742.660000 338.200000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 337.000000 2851.400000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'S_term_RAM_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 2849.170000 109.920000 2850.370000 140.180000 ;
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+        RECT 2791.520000 110.970000 2792.720000 138.620000 ;
+        RECT 2836.520000 110.970000 2837.720000 138.620000 ;
+      LAYER met3 ;
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+        RECT 2849.170000 128.380000 2850.370000 128.860000 ;
+        RECT 2836.520000 133.820000 2837.720000 134.300000 ;
+        RECT 2836.520000 128.380000 2837.720000 128.860000 ;
+        RECT 2791.520000 128.380000 2792.720000 128.860000 ;
+        RECT 2791.520000 133.820000 2792.720000 134.300000 ;
+        RECT 2742.490000 133.820000 2743.690000 134.300000 ;
+        RECT 2746.355000 133.820000 2747.720000 134.300000 ;
+        RECT 2746.355000 128.380000 2747.720000 128.860000 ;
+        RECT 2742.490000 128.380000 2743.690000 128.860000 ;
+        RECT 2849.170000 122.940000 2850.370000 123.420000 ;
+        RECT 2849.170000 117.500000 2850.370000 117.980000 ;
+        RECT 2836.520000 122.940000 2837.720000 123.420000 ;
+        RECT 2836.520000 117.500000 2837.720000 117.980000 ;
+        RECT 2791.520000 117.500000 2792.720000 117.980000 ;
+        RECT 2791.520000 122.940000 2792.720000 123.420000 ;
+        RECT 2746.355000 122.940000 2747.720000 123.420000 ;
+        RECT 2742.490000 122.940000 2743.690000 123.420000 ;
+        RECT 2746.355000 117.500000 2747.720000 117.980000 ;
+        RECT 2742.490000 117.500000 2743.690000 117.980000 ;
+        RECT 2741.460000 137.420000 2851.400000 138.620000 ;
+        RECT 2741.460000 110.970000 2851.400000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 109.920000 2743.690000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 138.980000 2743.690000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 109.920000 2850.370000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 138.980000 2850.370000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 110.970000 2742.660000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 110.970000 2851.400000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 137.420000 2742.660000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 137.420000 2851.400000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'N_term_RAM_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2746.355000 1165.380000 2747.720000 1165.860000 ;
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+        RECT 2746.355000 1154.500000 2747.720000 1154.980000 ;
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+        RECT 2742.490000 1141.480000 2743.690000 1171.740000 ;
+        RECT 2849.170000 1141.480000 2850.370000 1171.740000 ;
+        RECT 2746.520000 1142.530000 2747.720000 1170.180000 ;
+        RECT 2791.520000 1142.530000 2792.720000 1170.180000 ;
+        RECT 2836.520000 1142.530000 2837.720000 1170.180000 ;
+      LAYER met3 ;
+        RECT 2849.170000 1165.380000 2850.370000 1165.860000 ;
+        RECT 2849.170000 1159.940000 2850.370000 1160.420000 ;
+        RECT 2836.520000 1165.380000 2837.720000 1165.860000 ;
+        RECT 2836.520000 1159.940000 2837.720000 1160.420000 ;
+        RECT 2791.520000 1159.940000 2792.720000 1160.420000 ;
+        RECT 2791.520000 1165.380000 2792.720000 1165.860000 ;
+        RECT 2742.490000 1165.380000 2743.690000 1165.860000 ;
+        RECT 2746.355000 1165.380000 2747.720000 1165.860000 ;
+        RECT 2746.355000 1159.940000 2747.720000 1160.420000 ;
+        RECT 2742.490000 1159.940000 2743.690000 1160.420000 ;
+        RECT 2849.170000 1154.500000 2850.370000 1154.980000 ;
+        RECT 2849.170000 1149.060000 2850.370000 1149.540000 ;
+        RECT 2836.520000 1154.500000 2837.720000 1154.980000 ;
+        RECT 2836.520000 1149.060000 2837.720000 1149.540000 ;
+        RECT 2791.520000 1149.060000 2792.720000 1149.540000 ;
+        RECT 2791.520000 1154.500000 2792.720000 1154.980000 ;
+        RECT 2746.355000 1154.500000 2747.720000 1154.980000 ;
+        RECT 2742.490000 1154.500000 2743.690000 1154.980000 ;
+        RECT 2746.355000 1149.060000 2747.720000 1149.540000 ;
+        RECT 2742.490000 1149.060000 2743.690000 1149.540000 ;
+        RECT 2741.460000 1168.980000 2851.400000 1170.180000 ;
+        RECT 2741.460000 1142.530000 2851.400000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 1141.480000 2743.690000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2742.490000 1170.540000 2743.690000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 1141.480000 2850.370000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2849.170000 1170.540000 2850.370000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 1142.530000 2742.660000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 1142.530000 2851.400000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 1168.980000 2742.660000 1170.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 1168.980000 2851.400000 1170.180000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+        RECT 125.055000 1068.480000 126.420000 1068.960000 ;
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+        RECT 125.055000 1052.160000 126.420000 1052.640000 ;
+        RECT 125.055000 1046.720000 126.420000 1047.200000 ;
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+        RECT 125.055000 1024.960000 126.420000 1025.440000 ;
+        RECT 125.055000 1019.520000 126.420000 1020.000000 ;
+        RECT 125.055000 1014.080000 126.420000 1014.560000 ;
+        RECT 125.055000 1008.640000 126.420000 1009.120000 ;
+        RECT 125.055000 997.760000 126.420000 998.240000 ;
+        RECT 125.055000 1003.200000 126.420000 1003.680000 ;
+        RECT 125.055000 992.320000 126.420000 992.800000 ;
+        RECT 125.055000 986.880000 126.420000 987.360000 ;
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+        RECT 125.055000 959.680000 126.420000 960.160000 ;
+        RECT 125.055000 948.800000 126.420000 949.280000 ;
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+        RECT 260.220000 942.270000 261.420000 1139.240000 ;
+        RECT 318.030000 941.220000 319.230000 1141.480000 ;
+        RECT 215.220000 942.270000 216.420000 1139.240000 ;
+        RECT 170.220000 942.270000 171.420000 1139.240000 ;
+        RECT 125.220000 942.270000 126.420000 1139.240000 ;
+        RECT 121.190000 941.220000 122.390000 1141.480000 ;
+      LAYER met3 ;
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+        RECT 318.030000 1133.760000 319.230000 1134.240000 ;
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+        RECT 305.220000 1128.320000 306.420000 1128.800000 ;
+        RECT 305.220000 1122.880000 306.420000 1123.360000 ;
+        RECT 305.220000 1117.440000 306.420000 1117.920000 ;
+        RECT 305.220000 1106.560000 306.420000 1107.040000 ;
+        RECT 305.220000 1112.000000 306.420000 1112.480000 ;
+        RECT 318.030000 1106.560000 319.230000 1107.040000 ;
+        RECT 318.030000 1112.000000 319.230000 1112.480000 ;
+        RECT 305.220000 1095.680000 306.420000 1096.160000 ;
+        RECT 305.220000 1101.120000 306.420000 1101.600000 ;
+        RECT 318.030000 1095.680000 319.230000 1096.160000 ;
+        RECT 318.030000 1101.120000 319.230000 1101.600000 ;
+        RECT 260.220000 1117.440000 261.420000 1117.920000 ;
+        RECT 260.220000 1122.880000 261.420000 1123.360000 ;
+        RECT 260.220000 1128.320000 261.420000 1128.800000 ;
+        RECT 260.220000 1133.760000 261.420000 1134.240000 ;
+        RECT 260.220000 1101.120000 261.420000 1101.600000 ;
+        RECT 260.220000 1095.680000 261.420000 1096.160000 ;
+        RECT 260.220000 1106.560000 261.420000 1107.040000 ;
+        RECT 260.220000 1112.000000 261.420000 1112.480000 ;
+        RECT 318.030000 1084.800000 319.230000 1085.280000 ;
+        RECT 318.030000 1079.360000 319.230000 1079.840000 ;
+        RECT 318.030000 1090.240000 319.230000 1090.720000 ;
+        RECT 305.220000 1090.240000 306.420000 1090.720000 ;
+        RECT 305.220000 1084.800000 306.420000 1085.280000 ;
+        RECT 305.220000 1079.360000 306.420000 1079.840000 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+    PORT
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
+
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+        RECT 125.055000 174.960000 126.420000 175.440000 ;
+        RECT 121.190000 169.520000 122.390000 170.000000 ;
+        RECT 125.055000 169.520000 126.420000 170.000000 ;
+        RECT 121.190000 164.080000 122.390000 164.560000 ;
+        RECT 125.055000 164.080000 126.420000 164.560000 ;
+        RECT 121.190000 153.200000 122.390000 153.680000 ;
+        RECT 125.055000 153.200000 126.420000 153.680000 ;
+        RECT 121.190000 158.640000 122.390000 159.120000 ;
+        RECT 125.055000 158.640000 126.420000 159.120000 ;
+        RECT 121.190000 147.760000 122.390000 148.240000 ;
+        RECT 125.055000 147.760000 126.420000 148.240000 ;
+        RECT 260.220000 240.240000 261.420000 240.720000 ;
+        RECT 305.220000 240.240000 306.420000 240.720000 ;
+        RECT 318.030000 240.240000 319.230000 240.720000 ;
+        RECT 170.220000 240.240000 171.420000 240.720000 ;
+        RECT 215.220000 240.240000 216.420000 240.720000 ;
+        RECT 121.190000 240.240000 122.390000 240.720000 ;
+        RECT 125.055000 240.240000 126.420000 240.720000 ;
+        RECT 120.160000 337.000000 320.260000 338.200000 ;
+        RECT 120.160000 141.230000 320.260000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 140.180000 122.390000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 339.240000 122.390000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 140.180000 319.230000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 339.240000 319.230000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 141.230000 121.360000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 141.230000 320.260000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 337.000000 121.360000 338.200000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 337.000000 320.260000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 125.055000 133.820000 126.420000 134.300000 ;
+        RECT 125.055000 128.380000 126.420000 128.860000 ;
+        RECT 125.055000 122.940000 126.420000 123.420000 ;
+        RECT 125.055000 117.500000 126.420000 117.980000 ;
+        RECT 121.190000 109.920000 122.390000 140.180000 ;
+        RECT 318.030000 109.920000 319.230000 140.180000 ;
+        RECT 125.220000 110.970000 126.420000 138.620000 ;
+        RECT 170.220000 110.970000 171.420000 138.620000 ;
+        RECT 215.220000 110.970000 216.420000 138.620000 ;
+        RECT 260.220000 110.970000 261.420000 138.620000 ;
+        RECT 305.220000 110.970000 306.420000 138.620000 ;
+      LAYER met3 ;
+        RECT 318.030000 133.820000 319.230000 134.300000 ;
+        RECT 318.030000 128.380000 319.230000 128.860000 ;
+        RECT 305.220000 133.820000 306.420000 134.300000 ;
+        RECT 305.220000 128.380000 306.420000 128.860000 ;
+        RECT 260.220000 128.380000 261.420000 128.860000 ;
+        RECT 260.220000 133.820000 261.420000 134.300000 ;
+        RECT 215.220000 128.380000 216.420000 128.860000 ;
+        RECT 170.220000 128.380000 171.420000 128.860000 ;
+        RECT 215.220000 133.820000 216.420000 134.300000 ;
+        RECT 170.220000 133.820000 171.420000 134.300000 ;
+        RECT 125.055000 133.820000 126.420000 134.300000 ;
+        RECT 121.190000 133.820000 122.390000 134.300000 ;
+        RECT 125.055000 128.380000 126.420000 128.860000 ;
+        RECT 121.190000 128.380000 122.390000 128.860000 ;
+        RECT 318.030000 122.940000 319.230000 123.420000 ;
+        RECT 318.030000 117.500000 319.230000 117.980000 ;
+        RECT 305.220000 122.940000 306.420000 123.420000 ;
+        RECT 305.220000 117.500000 306.420000 117.980000 ;
+        RECT 260.220000 117.500000 261.420000 117.980000 ;
+        RECT 260.220000 122.940000 261.420000 123.420000 ;
+        RECT 215.220000 117.500000 216.420000 117.980000 ;
+        RECT 170.220000 117.500000 171.420000 117.980000 ;
+        RECT 215.220000 122.940000 216.420000 123.420000 ;
+        RECT 170.220000 122.940000 171.420000 123.420000 ;
+        RECT 125.055000 122.940000 126.420000 123.420000 ;
+        RECT 121.190000 122.940000 122.390000 123.420000 ;
+        RECT 125.055000 117.500000 126.420000 117.980000 ;
+        RECT 121.190000 117.500000 122.390000 117.980000 ;
+        RECT 120.160000 137.420000 320.260000 138.620000 ;
+        RECT 120.160000 110.970000 320.260000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 109.920000 122.390000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 138.980000 122.390000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 109.920000 319.230000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 138.980000 319.230000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 110.970000 121.360000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 110.970000 320.260000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 137.420000 121.360000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 137.420000 320.260000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 125.055000 1165.380000 126.420000 1165.860000 ;
+        RECT 125.055000 1159.940000 126.420000 1160.420000 ;
+        RECT 125.055000 1154.500000 126.420000 1154.980000 ;
+        RECT 125.055000 1149.060000 126.420000 1149.540000 ;
+        RECT 121.190000 1141.480000 122.390000 1171.740000 ;
+        RECT 318.030000 1141.480000 319.230000 1171.740000 ;
+        RECT 125.220000 1142.530000 126.420000 1170.180000 ;
+        RECT 170.220000 1142.530000 171.420000 1170.180000 ;
+        RECT 215.220000 1142.530000 216.420000 1170.180000 ;
+        RECT 260.220000 1142.530000 261.420000 1170.180000 ;
+        RECT 305.220000 1142.530000 306.420000 1170.180000 ;
+      LAYER met3 ;
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+        RECT 318.030000 1159.940000 319.230000 1160.420000 ;
+        RECT 305.220000 1165.380000 306.420000 1165.860000 ;
+        RECT 305.220000 1159.940000 306.420000 1160.420000 ;
+        RECT 260.220000 1159.940000 261.420000 1160.420000 ;
+        RECT 260.220000 1165.380000 261.420000 1165.860000 ;
+        RECT 215.220000 1159.940000 216.420000 1160.420000 ;
+        RECT 170.220000 1159.940000 171.420000 1160.420000 ;
+        RECT 215.220000 1165.380000 216.420000 1165.860000 ;
+        RECT 170.220000 1165.380000 171.420000 1165.860000 ;
+        RECT 125.055000 1165.380000 126.420000 1165.860000 ;
+        RECT 121.190000 1165.380000 122.390000 1165.860000 ;
+        RECT 125.055000 1159.940000 126.420000 1160.420000 ;
+        RECT 121.190000 1159.940000 122.390000 1160.420000 ;
+        RECT 318.030000 1154.500000 319.230000 1154.980000 ;
+        RECT 318.030000 1149.060000 319.230000 1149.540000 ;
+        RECT 305.220000 1154.500000 306.420000 1154.980000 ;
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+        RECT 260.220000 1149.060000 261.420000 1149.540000 ;
+        RECT 260.220000 1154.500000 261.420000 1154.980000 ;
+        RECT 215.220000 1149.060000 216.420000 1149.540000 ;
+        RECT 170.220000 1149.060000 171.420000 1149.540000 ;
+        RECT 215.220000 1154.500000 216.420000 1154.980000 ;
+        RECT 170.220000 1154.500000 171.420000 1154.980000 ;
+        RECT 125.055000 1154.500000 126.420000 1154.980000 ;
+        RECT 121.190000 1154.500000 122.390000 1154.980000 ;
+        RECT 125.055000 1149.060000 126.420000 1149.540000 ;
+        RECT 121.190000 1149.060000 122.390000 1149.540000 ;
+        RECT 120.160000 1168.980000 320.260000 1170.180000 ;
+        RECT 120.160000 1142.530000 320.260000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 1141.480000 122.390000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.190000 1170.540000 122.390000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 1141.480000 319.230000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 318.030000 1170.540000 319.230000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 1142.530000 121.360000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 1142.530000 320.260000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 1168.980000 121.360000 1170.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 1168.980000 320.260000 1170.180000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'RegFile'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+
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+# end of P/G pin shape extracted from block 'RegFile'
+
+
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+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 321.290000 339.240000 322.490000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 337.000000 520.360000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+    PORT
+      LAYER met4 ;
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+        RECT 320.260000 137.420000 520.360000 138.620000 ;
+        RECT 320.260000 110.970000 520.360000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 321.290000 109.920000 322.490000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 321.290000 138.980000 322.490000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 518.130000 109.920000 519.330000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 518.130000 138.980000 519.330000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 110.970000 321.460000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 110.970000 520.360000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 137.420000 321.460000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 137.420000 520.360000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+    PORT
+      LAYER met4 ;
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+        RECT 518.130000 1141.480000 519.330000 1171.740000 ;
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+        RECT 505.320000 1142.530000 506.520000 1170.180000 ;
+      LAYER met3 ;
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+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    PORT
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+    END
+    PORT
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+    PORT
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+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 337.000000 720.460000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 137.420000 720.460000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 681.470000 2902.360000 682.670000 2903.560000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 2703.300000 719.430000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2900.120000 720.460000 2901.320000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2659.860000 720.460000 2661.060000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 681.470000 2461.840000 682.670000 2463.040000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2263.830000 720.460000 2265.030000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2459.600000 720.460000 2460.800000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
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+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
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+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
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+        RECT 680.440000 1583.050000 720.460000 1584.250000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 681.470000 1781.060000 682.670000 1782.260000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1582.000000 719.430000 1583.200000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1781.060000 719.430000 1782.260000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1583.050000 681.640000 1584.250000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1583.050000 720.460000 1584.250000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1778.820000 681.640000 1780.020000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1778.820000 720.460000 1780.020000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 680.440000 1578.560000 720.460000 1579.760000 ;
+        RECT 680.440000 1382.790000 720.460000 1383.990000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 681.470000 1381.740000 682.670000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 681.470000 1580.800000 682.670000 1582.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1381.740000 719.430000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1580.800000 719.430000 1582.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1382.790000 681.640000 1383.990000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1382.790000 720.460000 1383.990000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1578.560000 681.640000 1579.760000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1578.560000 720.460000 1579.760000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO_bot'
+    PORT
+      LAYER met4 ;
+        RECT 525.255000 1334.020000 526.620000 1334.500000 ;
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+        RECT 525.255000 1290.500000 526.620000 1290.980000 ;
+        RECT 525.255000 1279.620000 526.620000 1280.100000 ;
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+      LAYER met3 ;
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+        RECT 525.255000 1159.940000 526.620000 1160.420000 ;
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+        RECT 525.255000 1149.060000 526.620000 1149.540000 ;
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+        RECT 521.390000 1241.540000 522.590000 1242.020000 ;
+        RECT 525.255000 1241.540000 526.620000 1242.020000 ;
+        RECT 520.360000 1338.300000 720.460000 1339.500000 ;
+        RECT 520.360000 1142.530000 720.460000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 521.390000 1141.480000 522.590000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 521.390000 1340.540000 522.590000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1141.480000 719.430000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 718.230000 1340.540000 719.430000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 520.360000 1142.530000 521.560000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1142.530000 720.460000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 520.360000 1338.300000 521.560000 1339.500000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1338.300000 720.460000 1339.500000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO_bot'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+    PORT
+      LAYER met4 ;
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+        RECT 730.355000 3122.280000 731.720000 3122.760000 ;
+        RECT 730.355000 3116.840000 731.720000 3117.320000 ;
+        RECT 730.355000 3111.400000 731.720000 3111.880000 ;
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+        RECT 820.520000 3104.870000 821.720000 3132.520000 ;
+        RECT 865.520000 3104.870000 866.720000 3132.520000 ;
+        RECT 910.520000 3104.870000 911.720000 3132.520000 ;
+      LAYER met3 ;
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+        RECT 923.330000 3122.280000 924.530000 3122.760000 ;
+        RECT 910.520000 3127.720000 911.720000 3128.200000 ;
+        RECT 910.520000 3122.280000 911.720000 3122.760000 ;
+        RECT 865.520000 3122.280000 866.720000 3122.760000 ;
+        RECT 865.520000 3127.720000 866.720000 3128.200000 ;
+        RECT 820.520000 3122.280000 821.720000 3122.760000 ;
+        RECT 775.520000 3122.280000 776.720000 3122.760000 ;
+        RECT 820.520000 3127.720000 821.720000 3128.200000 ;
+        RECT 775.520000 3127.720000 776.720000 3128.200000 ;
+        RECT 730.355000 3127.720000 731.720000 3128.200000 ;
+        RECT 726.490000 3127.720000 727.690000 3128.200000 ;
+        RECT 730.355000 3122.280000 731.720000 3122.760000 ;
+        RECT 726.490000 3122.280000 727.690000 3122.760000 ;
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+        RECT 865.520000 3116.840000 866.720000 3117.320000 ;
+        RECT 820.520000 3111.400000 821.720000 3111.880000 ;
+        RECT 775.520000 3111.400000 776.720000 3111.880000 ;
+        RECT 820.520000 3116.840000 821.720000 3117.320000 ;
+        RECT 775.520000 3116.840000 776.720000 3117.320000 ;
+        RECT 730.355000 3116.840000 731.720000 3117.320000 ;
+        RECT 726.490000 3116.840000 727.690000 3117.320000 ;
+        RECT 730.355000 3111.400000 731.720000 3111.880000 ;
+        RECT 726.490000 3111.400000 727.690000 3111.880000 ;
+        RECT 725.460000 3131.320000 925.560000 3132.520000 ;
+        RECT 725.460000 3104.870000 925.560000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 726.490000 3103.820000 727.690000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 726.490000 3132.880000 727.690000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 923.330000 3103.820000 924.530000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 923.330000 3132.880000 924.530000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 725.460000 3104.870000 726.660000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 3104.870000 925.560000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 725.460000 3131.320000 726.660000 3132.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 3131.320000 925.560000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
+      LAYER met4 ;
+        RECT 730.355000 929.080000 731.720000 929.560000 ;
+        RECT 730.355000 934.520000 731.720000 935.000000 ;
+        RECT 730.355000 918.200000 731.720000 918.680000 ;
+        RECT 730.355000 923.640000 731.720000 924.120000 ;
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+        RECT 730.355000 907.320000 731.720000 907.800000 ;
+        RECT 730.355000 896.440000 731.720000 896.920000 ;
+        RECT 730.355000 901.880000 731.720000 902.360000 ;
+        RECT 730.355000 880.120000 731.720000 880.600000 ;
+        RECT 730.355000 885.560000 731.720000 886.040000 ;
+        RECT 730.355000 874.680000 731.720000 875.160000 ;
+        RECT 730.355000 869.240000 731.720000 869.720000 ;
+        RECT 730.355000 858.360000 731.720000 858.840000 ;
+        RECT 730.355000 863.800000 731.720000 864.280000 ;
+        RECT 730.355000 847.480000 731.720000 847.960000 ;
+        RECT 730.355000 852.920000 731.720000 853.400000 ;
+        RECT 730.355000 842.040000 731.720000 842.520000 ;
+        RECT 730.355000 891.000000 731.720000 891.480000 ;
+        RECT 730.355000 831.160000 731.720000 831.640000 ;
+        RECT 730.355000 836.600000 731.720000 837.080000 ;
+        RECT 730.355000 820.280000 731.720000 820.760000 ;
+        RECT 730.355000 825.720000 731.720000 826.200000 ;
+        RECT 730.355000 814.840000 731.720000 815.320000 ;
+        RECT 730.355000 803.960000 731.720000 804.440000 ;
+        RECT 730.355000 809.400000 731.720000 809.880000 ;
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+# end of P/G pin shape extracted from block 'DSP'
+
+
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 537.770000 925.560000 538.970000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 137.420000 925.560000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
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+
+
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+
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
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+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 137.420000 1130.660000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 931.590000 3102.620000 932.790000 3103.820000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 3100.380000 1130.660000 3101.580000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+    PORT
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+    PORT
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+        RECT 931.590000 1181.700000 932.790000 1182.180000 ;
+        RECT 935.455000 1181.700000 936.820000 1182.180000 ;
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+        RECT 935.455000 1176.260000 936.820000 1176.740000 ;
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+        RECT 935.455000 1170.820000 936.820000 1171.300000 ;
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+        RECT 935.455000 1165.380000 936.820000 1165.860000 ;
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+        RECT 935.455000 1154.500000 936.820000 1154.980000 ;
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+        RECT 935.455000 1159.940000 936.820000 1160.420000 ;
+        RECT 931.590000 1149.060000 932.790000 1149.540000 ;
+        RECT 935.455000 1149.060000 936.820000 1149.540000 ;
+        RECT 1070.620000 1241.540000 1071.820000 1242.020000 ;
+        RECT 1115.620000 1241.540000 1116.820000 1242.020000 ;
+        RECT 1128.430000 1241.540000 1129.630000 1242.020000 ;
+        RECT 980.620000 1241.540000 981.820000 1242.020000 ;
+        RECT 1025.620000 1241.540000 1026.820000 1242.020000 ;
+        RECT 931.590000 1241.540000 932.790000 1242.020000 ;
+        RECT 935.455000 1241.540000 936.820000 1242.020000 ;
+        RECT 930.560000 1338.300000 1130.660000 1339.500000 ;
+        RECT 930.560000 1142.530000 1130.660000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 931.590000 1141.480000 932.790000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 931.590000 1340.540000 932.790000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1128.430000 1141.480000 1129.630000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1128.430000 1340.540000 1129.630000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1142.530000 931.760000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1142.530000 1130.660000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1338.300000 931.760000 1339.500000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1338.300000 1130.660000 1339.500000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1135.555000 3127.720000 1136.920000 3128.200000 ;
+        RECT 1135.555000 3122.280000 1136.920000 3122.760000 ;
+        RECT 1135.555000 3116.840000 1136.920000 3117.320000 ;
+        RECT 1135.555000 3111.400000 1136.920000 3111.880000 ;
+        RECT 1131.690000 3103.820000 1132.890000 3134.080000 ;
+        RECT 1328.530000 3103.820000 1329.730000 3134.080000 ;
+        RECT 1135.720000 3104.870000 1136.920000 3132.520000 ;
+        RECT 1180.720000 3104.870000 1181.920000 3132.520000 ;
+        RECT 1225.720000 3104.870000 1226.920000 3132.520000 ;
+        RECT 1270.720000 3104.870000 1271.920000 3132.520000 ;
+        RECT 1315.720000 3104.870000 1316.920000 3132.520000 ;
+      LAYER met3 ;
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+        RECT 1328.530000 3122.280000 1329.730000 3122.760000 ;
+        RECT 1315.720000 3127.720000 1316.920000 3128.200000 ;
+        RECT 1315.720000 3122.280000 1316.920000 3122.760000 ;
+        RECT 1270.720000 3122.280000 1271.920000 3122.760000 ;
+        RECT 1270.720000 3127.720000 1271.920000 3128.200000 ;
+        RECT 1225.720000 3122.280000 1226.920000 3122.760000 ;
+        RECT 1180.720000 3122.280000 1181.920000 3122.760000 ;
+        RECT 1225.720000 3127.720000 1226.920000 3128.200000 ;
+        RECT 1180.720000 3127.720000 1181.920000 3128.200000 ;
+        RECT 1135.555000 3127.720000 1136.920000 3128.200000 ;
+        RECT 1131.690000 3127.720000 1132.890000 3128.200000 ;
+        RECT 1135.555000 3122.280000 1136.920000 3122.760000 ;
+        RECT 1131.690000 3122.280000 1132.890000 3122.760000 ;
+        RECT 1328.530000 3116.840000 1329.730000 3117.320000 ;
+        RECT 1328.530000 3111.400000 1329.730000 3111.880000 ;
+        RECT 1315.720000 3116.840000 1316.920000 3117.320000 ;
+        RECT 1315.720000 3111.400000 1316.920000 3111.880000 ;
+        RECT 1270.720000 3111.400000 1271.920000 3111.880000 ;
+        RECT 1270.720000 3116.840000 1271.920000 3117.320000 ;
+        RECT 1225.720000 3111.400000 1226.920000 3111.880000 ;
+        RECT 1180.720000 3111.400000 1181.920000 3111.880000 ;
+        RECT 1225.720000 3116.840000 1226.920000 3117.320000 ;
+        RECT 1180.720000 3116.840000 1181.920000 3117.320000 ;
+        RECT 1135.555000 3116.840000 1136.920000 3117.320000 ;
+        RECT 1131.690000 3116.840000 1132.890000 3117.320000 ;
+        RECT 1135.555000 3111.400000 1136.920000 3111.880000 ;
+        RECT 1131.690000 3111.400000 1132.890000 3111.880000 ;
+        RECT 1130.660000 3131.320000 1330.760000 3132.520000 ;
+        RECT 1130.660000 3104.870000 1330.760000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 3103.820000 1132.890000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 3132.880000 1132.890000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 3103.820000 1329.730000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 3132.880000 1329.730000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 3104.870000 1131.860000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 3104.870000 1330.760000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 3131.320000 1131.860000 3132.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 3131.320000 1330.760000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1135.555000 1133.760000 1136.920000 1134.240000 ;
+        RECT 1135.555000 1122.880000 1136.920000 1123.360000 ;
+        RECT 1135.555000 1128.320000 1136.920000 1128.800000 ;
+        RECT 1135.555000 1117.440000 1136.920000 1117.920000 ;
+        RECT 1135.555000 1112.000000 1136.920000 1112.480000 ;
+        RECT 1135.555000 1106.560000 1136.920000 1107.040000 ;
+        RECT 1135.555000 1101.120000 1136.920000 1101.600000 ;
+        RECT 1135.555000 1095.680000 1136.920000 1096.160000 ;
+        RECT 1135.555000 1090.240000 1136.920000 1090.720000 ;
+        RECT 1135.555000 1079.360000 1136.920000 1079.840000 ;
+        RECT 1135.555000 1084.800000 1136.920000 1085.280000 ;
+        RECT 1135.555000 1073.920000 1136.920000 1074.400000 ;
+        RECT 1135.555000 1068.480000 1136.920000 1068.960000 ;
+        RECT 1135.555000 1063.040000 1136.920000 1063.520000 ;
+        RECT 1135.555000 1057.600000 1136.920000 1058.080000 ;
+        RECT 1135.555000 1052.160000 1136.920000 1052.640000 ;
+        RECT 1135.555000 1046.720000 1136.920000 1047.200000 ;
+        RECT 1135.555000 1035.840000 1136.920000 1036.320000 ;
+        RECT 1135.555000 1030.400000 1136.920000 1030.880000 ;
+        RECT 1135.555000 1024.960000 1136.920000 1025.440000 ;
+        RECT 1135.555000 1019.520000 1136.920000 1020.000000 ;
+        RECT 1135.555000 1014.080000 1136.920000 1014.560000 ;
+        RECT 1135.555000 1008.640000 1136.920000 1009.120000 ;
+        RECT 1135.555000 997.760000 1136.920000 998.240000 ;
+        RECT 1135.555000 1003.200000 1136.920000 1003.680000 ;
+        RECT 1135.555000 992.320000 1136.920000 992.800000 ;
+        RECT 1135.555000 986.880000 1136.920000 987.360000 ;
+        RECT 1135.555000 981.440000 1136.920000 981.920000 ;
+        RECT 1135.555000 976.000000 1136.920000 976.480000 ;
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+    PORT
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
+
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+        RECT 1130.660000 141.230000 1330.760000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 140.180000 1132.890000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 339.240000 1132.890000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 140.180000 1329.730000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 339.240000 1329.730000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 337.000000 1330.760000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 1131.690000 122.940000 1132.890000 123.420000 ;
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+        RECT 1130.660000 110.970000 1330.760000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 109.920000 1329.730000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 138.980000 1329.730000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 110.970000 1131.860000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 110.970000 1330.760000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 137.420000 1131.860000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 137.420000 1330.760000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 1328.530000 3068.900000 1329.730000 3069.380000 ;
+        RECT 1328.530000 3074.340000 1329.730000 3074.820000 ;
+        RECT 1315.720000 3058.020000 1316.920000 3058.500000 ;
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+        RECT 1328.530000 3058.020000 1329.730000 3058.500000 ;
+        RECT 1328.530000 3063.460000 1329.730000 3063.940000 ;
+        RECT 1270.720000 3079.780000 1271.920000 3080.260000 ;
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+        RECT 1270.720000 3058.020000 1271.920000 3058.500000 ;
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+        RECT 1315.720000 3052.580000 1316.920000 3053.060000 ;
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+        RECT 1270.720000 1181.700000 1271.920000 1182.180000 ;
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+        RECT 1135.555000 1230.660000 1136.920000 1231.140000 ;
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+        RECT 1131.690000 1219.780000 1132.890000 1220.260000 ;
+        RECT 1135.555000 1219.780000 1136.920000 1220.260000 ;
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+        RECT 1135.555000 1203.460000 1136.920000 1203.940000 ;
+        RECT 1131.690000 1192.580000 1132.890000 1193.060000 ;
+        RECT 1135.555000 1192.580000 1136.920000 1193.060000 ;
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+        RECT 1225.720000 1181.700000 1226.920000 1182.180000 ;
+        RECT 1225.720000 1187.140000 1226.920000 1187.620000 ;
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+        RECT 1180.720000 1181.700000 1181.920000 1182.180000 ;
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+        RECT 1135.555000 1187.140000 1136.920000 1187.620000 ;
+        RECT 1131.690000 1181.700000 1132.890000 1182.180000 ;
+        RECT 1135.555000 1181.700000 1136.920000 1182.180000 ;
+        RECT 1131.690000 1176.260000 1132.890000 1176.740000 ;
+        RECT 1135.555000 1176.260000 1136.920000 1176.740000 ;
+        RECT 1131.690000 1170.820000 1132.890000 1171.300000 ;
+        RECT 1135.555000 1170.820000 1136.920000 1171.300000 ;
+        RECT 1131.690000 1165.380000 1132.890000 1165.860000 ;
+        RECT 1135.555000 1165.380000 1136.920000 1165.860000 ;
+        RECT 1131.690000 1154.500000 1132.890000 1154.980000 ;
+        RECT 1135.555000 1154.500000 1136.920000 1154.980000 ;
+        RECT 1131.690000 1159.940000 1132.890000 1160.420000 ;
+        RECT 1135.555000 1159.940000 1136.920000 1160.420000 ;
+        RECT 1131.690000 1149.060000 1132.890000 1149.540000 ;
+        RECT 1135.555000 1149.060000 1136.920000 1149.540000 ;
+        RECT 1270.720000 1241.540000 1271.920000 1242.020000 ;
+        RECT 1315.720000 1241.540000 1316.920000 1242.020000 ;
+        RECT 1328.530000 1241.540000 1329.730000 1242.020000 ;
+        RECT 1180.720000 1241.540000 1181.920000 1242.020000 ;
+        RECT 1225.720000 1241.540000 1226.920000 1242.020000 ;
+        RECT 1131.690000 1241.540000 1132.890000 1242.020000 ;
+        RECT 1135.555000 1241.540000 1136.920000 1242.020000 ;
+        RECT 1130.660000 1338.300000 1330.760000 1339.500000 ;
+        RECT 1130.660000 1142.530000 1330.760000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 1141.480000 1132.890000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1131.690000 1340.540000 1132.890000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 1141.480000 1329.730000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1328.530000 1340.540000 1329.730000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 1142.530000 1131.860000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 1142.530000 1330.760000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 1338.300000 1131.860000 1339.500000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 1338.300000 1330.760000 1339.500000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1335.655000 3127.720000 1337.020000 3128.200000 ;
+        RECT 1335.655000 3122.280000 1337.020000 3122.760000 ;
+        RECT 1335.655000 3116.840000 1337.020000 3117.320000 ;
+        RECT 1335.655000 3111.400000 1337.020000 3111.880000 ;
+        RECT 1331.790000 3103.820000 1332.990000 3134.080000 ;
+        RECT 1528.630000 3103.820000 1529.830000 3134.080000 ;
+        RECT 1335.820000 3104.870000 1337.020000 3132.520000 ;
+        RECT 1380.820000 3104.870000 1382.020000 3132.520000 ;
+        RECT 1425.820000 3104.870000 1427.020000 3132.520000 ;
+        RECT 1470.820000 3104.870000 1472.020000 3132.520000 ;
+        RECT 1515.820000 3104.870000 1517.020000 3132.520000 ;
+      LAYER met3 ;
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+        RECT 1528.630000 3122.280000 1529.830000 3122.760000 ;
+        RECT 1515.820000 3127.720000 1517.020000 3128.200000 ;
+        RECT 1515.820000 3122.280000 1517.020000 3122.760000 ;
+        RECT 1470.820000 3122.280000 1472.020000 3122.760000 ;
+        RECT 1470.820000 3127.720000 1472.020000 3128.200000 ;
+        RECT 1425.820000 3122.280000 1427.020000 3122.760000 ;
+        RECT 1380.820000 3122.280000 1382.020000 3122.760000 ;
+        RECT 1425.820000 3127.720000 1427.020000 3128.200000 ;
+        RECT 1380.820000 3127.720000 1382.020000 3128.200000 ;
+        RECT 1335.655000 3127.720000 1337.020000 3128.200000 ;
+        RECT 1331.790000 3127.720000 1332.990000 3128.200000 ;
+        RECT 1335.655000 3122.280000 1337.020000 3122.760000 ;
+        RECT 1331.790000 3122.280000 1332.990000 3122.760000 ;
+        RECT 1528.630000 3116.840000 1529.830000 3117.320000 ;
+        RECT 1528.630000 3111.400000 1529.830000 3111.880000 ;
+        RECT 1515.820000 3116.840000 1517.020000 3117.320000 ;
+        RECT 1515.820000 3111.400000 1517.020000 3111.880000 ;
+        RECT 1470.820000 3111.400000 1472.020000 3111.880000 ;
+        RECT 1470.820000 3116.840000 1472.020000 3117.320000 ;
+        RECT 1425.820000 3111.400000 1427.020000 3111.880000 ;
+        RECT 1380.820000 3111.400000 1382.020000 3111.880000 ;
+        RECT 1425.820000 3116.840000 1427.020000 3117.320000 ;
+        RECT 1380.820000 3116.840000 1382.020000 3117.320000 ;
+        RECT 1335.655000 3116.840000 1337.020000 3117.320000 ;
+        RECT 1331.790000 3116.840000 1332.990000 3117.320000 ;
+        RECT 1335.655000 3111.400000 1337.020000 3111.880000 ;
+        RECT 1331.790000 3111.400000 1332.990000 3111.880000 ;
+        RECT 1330.760000 3131.320000 1530.860000 3132.520000 ;
+        RECT 1330.760000 3104.870000 1530.860000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 3103.820000 1332.990000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 3132.880000 1332.990000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 3103.820000 1529.830000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 3132.880000 1529.830000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 3104.870000 1331.960000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 3104.870000 1530.860000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 3131.320000 1331.960000 3132.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 3131.320000 1530.860000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1335.655000 1133.760000 1337.020000 1134.240000 ;
+        RECT 1335.655000 1122.880000 1337.020000 1123.360000 ;
+        RECT 1335.655000 1128.320000 1337.020000 1128.800000 ;
+        RECT 1335.655000 1117.440000 1337.020000 1117.920000 ;
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+        RECT 1335.655000 1106.560000 1337.020000 1107.040000 ;
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+        RECT 1335.655000 1090.240000 1337.020000 1090.720000 ;
+        RECT 1335.655000 1079.360000 1337.020000 1079.840000 ;
+        RECT 1335.655000 1084.800000 1337.020000 1085.280000 ;
+        RECT 1335.655000 1073.920000 1337.020000 1074.400000 ;
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+        RECT 1335.655000 1057.600000 1337.020000 1058.080000 ;
+        RECT 1335.655000 1052.160000 1337.020000 1052.640000 ;
+        RECT 1335.655000 1046.720000 1337.020000 1047.200000 ;
+        RECT 1335.655000 1035.840000 1337.020000 1036.320000 ;
+        RECT 1335.655000 1030.400000 1337.020000 1030.880000 ;
+        RECT 1335.655000 1024.960000 1337.020000 1025.440000 ;
+        RECT 1335.655000 1019.520000 1337.020000 1020.000000 ;
+        RECT 1335.655000 1014.080000 1337.020000 1014.560000 ;
+        RECT 1335.655000 1008.640000 1337.020000 1009.120000 ;
+        RECT 1335.655000 997.760000 1337.020000 998.240000 ;
+        RECT 1335.655000 1003.200000 1337.020000 1003.680000 ;
+        RECT 1335.655000 992.320000 1337.020000 992.800000 ;
+        RECT 1335.655000 986.880000 1337.020000 987.360000 ;
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+        RECT 1335.655000 976.000000 1337.020000 976.480000 ;
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+        RECT 1335.655000 959.680000 1337.020000 960.160000 ;
+        RECT 1335.655000 948.800000 1337.020000 949.280000 ;
+        RECT 1335.655000 1041.280000 1337.020000 1041.760000 ;
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+        RECT 1470.820000 942.270000 1472.020000 1139.240000 ;
+        RECT 1528.630000 941.220000 1529.830000 1141.480000 ;
+        RECT 1425.820000 942.270000 1427.020000 1139.240000 ;
+        RECT 1380.820000 942.270000 1382.020000 1139.240000 ;
+        RECT 1335.820000 942.270000 1337.020000 1139.240000 ;
+        RECT 1331.790000 941.220000 1332.990000 1141.480000 ;
+      LAYER met3 ;
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+        RECT 1528.630000 1133.760000 1529.830000 1134.240000 ;
+        RECT 1528.630000 1122.880000 1529.830000 1123.360000 ;
+        RECT 1528.630000 1117.440000 1529.830000 1117.920000 ;
+        RECT 1528.630000 1128.320000 1529.830000 1128.800000 ;
+        RECT 1515.820000 1128.320000 1517.020000 1128.800000 ;
+        RECT 1515.820000 1122.880000 1517.020000 1123.360000 ;
+        RECT 1515.820000 1117.440000 1517.020000 1117.920000 ;
+        RECT 1515.820000 1106.560000 1517.020000 1107.040000 ;
+        RECT 1515.820000 1112.000000 1517.020000 1112.480000 ;
+        RECT 1528.630000 1106.560000 1529.830000 1107.040000 ;
+        RECT 1528.630000 1112.000000 1529.830000 1112.480000 ;
+        RECT 1515.820000 1095.680000 1517.020000 1096.160000 ;
+        RECT 1515.820000 1101.120000 1517.020000 1101.600000 ;
+        RECT 1528.630000 1095.680000 1529.830000 1096.160000 ;
+        RECT 1528.630000 1101.120000 1529.830000 1101.600000 ;
+        RECT 1470.820000 1117.440000 1472.020000 1117.920000 ;
+        RECT 1470.820000 1122.880000 1472.020000 1123.360000 ;
+        RECT 1470.820000 1128.320000 1472.020000 1128.800000 ;
+        RECT 1470.820000 1133.760000 1472.020000 1134.240000 ;
+        RECT 1470.820000 1101.120000 1472.020000 1101.600000 ;
+        RECT 1470.820000 1095.680000 1472.020000 1096.160000 ;
+        RECT 1470.820000 1106.560000 1472.020000 1107.040000 ;
+        RECT 1470.820000 1112.000000 1472.020000 1112.480000 ;
+        RECT 1528.630000 1084.800000 1529.830000 1085.280000 ;
+        RECT 1528.630000 1079.360000 1529.830000 1079.840000 ;
+        RECT 1528.630000 1090.240000 1529.830000 1090.720000 ;
+        RECT 1515.820000 1090.240000 1517.020000 1090.720000 ;
+        RECT 1515.820000 1084.800000 1517.020000 1085.280000 ;
+        RECT 1515.820000 1079.360000 1517.020000 1079.840000 ;
+        RECT 1515.820000 1068.480000 1517.020000 1068.960000 ;
+        RECT 1515.820000 1073.920000 1517.020000 1074.400000 ;
+        RECT 1528.630000 1068.480000 1529.830000 1068.960000 ;
+        RECT 1528.630000 1073.920000 1529.830000 1074.400000 ;
+        RECT 1528.630000 1057.600000 1529.830000 1058.080000 ;
+        RECT 1528.630000 1063.040000 1529.830000 1063.520000 ;
+        RECT 1515.820000 1063.040000 1517.020000 1063.520000 ;
+        RECT 1515.820000 1057.600000 1517.020000 1058.080000 ;
+        RECT 1515.820000 1046.720000 1517.020000 1047.200000 ;
+        RECT 1515.820000 1052.160000 1517.020000 1052.640000 ;
+        RECT 1528.630000 1046.720000 1529.830000 1047.200000 ;
+        RECT 1528.630000 1052.160000 1529.830000 1052.640000 ;
+        RECT 1470.820000 1068.480000 1472.020000 1068.960000 ;
+        RECT 1470.820000 1073.920000 1472.020000 1074.400000 ;
+        RECT 1470.820000 1079.360000 1472.020000 1079.840000 ;
+        RECT 1470.820000 1084.800000 1472.020000 1085.280000 ;
+        RECT 1470.820000 1090.240000 1472.020000 1090.720000 ;
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+        RECT 1470.820000 1052.160000 1472.020000 1052.640000 ;
+        RECT 1470.820000 1057.600000 1472.020000 1058.080000 ;
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+        RECT 1425.820000 1122.880000 1427.020000 1123.360000 ;
+        RECT 1425.820000 1117.440000 1427.020000 1117.920000 ;
+        RECT 1425.820000 1128.320000 1427.020000 1128.800000 ;
+        RECT 1425.820000 1133.760000 1427.020000 1134.240000 ;
+        RECT 1380.820000 1117.440000 1382.020000 1117.920000 ;
+        RECT 1380.820000 1122.880000 1382.020000 1123.360000 ;
+        RECT 1380.820000 1128.320000 1382.020000 1128.800000 ;
+        RECT 1380.820000 1133.760000 1382.020000 1134.240000 ;
+        RECT 1425.820000 1095.680000 1427.020000 1096.160000 ;
+        RECT 1425.820000 1101.120000 1427.020000 1101.600000 ;
+        RECT 1425.820000 1106.560000 1427.020000 1107.040000 ;
+        RECT 1425.820000 1112.000000 1427.020000 1112.480000 ;
+        RECT 1380.820000 1095.680000 1382.020000 1096.160000 ;
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+        RECT 1335.655000 153.200000 1337.020000 153.680000 ;
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+        RECT 1335.655000 147.760000 1337.020000 148.240000 ;
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+        RECT 1331.790000 240.240000 1332.990000 240.720000 ;
+        RECT 1335.655000 240.240000 1337.020000 240.720000 ;
+        RECT 1330.760000 337.000000 1530.860000 338.200000 ;
+        RECT 1330.760000 141.230000 1530.860000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 140.180000 1332.990000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 339.240000 1332.990000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 140.180000 1529.830000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 339.240000 1529.830000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 141.230000 1331.960000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 141.230000 1530.860000 142.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 337.000000 1331.960000 338.200000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 337.000000 1530.860000 338.200000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1335.655000 133.820000 1337.020000 134.300000 ;
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+        RECT 1515.820000 110.970000 1517.020000 138.620000 ;
+      LAYER met3 ;
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+        RECT 1515.820000 133.820000 1517.020000 134.300000 ;
+        RECT 1515.820000 128.380000 1517.020000 128.860000 ;
+        RECT 1470.820000 128.380000 1472.020000 128.860000 ;
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+        RECT 1380.820000 128.380000 1382.020000 128.860000 ;
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+        RECT 1380.820000 133.820000 1382.020000 134.300000 ;
+        RECT 1335.655000 133.820000 1337.020000 134.300000 ;
+        RECT 1331.790000 133.820000 1332.990000 134.300000 ;
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+        RECT 1331.790000 128.380000 1332.990000 128.860000 ;
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+        RECT 1380.820000 122.940000 1382.020000 123.420000 ;
+        RECT 1335.655000 122.940000 1337.020000 123.420000 ;
+        RECT 1331.790000 122.940000 1332.990000 123.420000 ;
+        RECT 1335.655000 117.500000 1337.020000 117.980000 ;
+        RECT 1331.790000 117.500000 1332.990000 117.980000 ;
+        RECT 1330.760000 137.420000 1530.860000 138.620000 ;
+        RECT 1330.760000 110.970000 1530.860000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 109.920000 1332.990000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 138.980000 1332.990000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 109.920000 1529.830000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 138.980000 1529.830000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 110.970000 1331.960000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 110.970000 1530.860000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 137.420000 1331.960000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 137.420000 1530.860000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+        RECT 1528.630000 3068.900000 1529.830000 3069.380000 ;
+        RECT 1528.630000 3074.340000 1529.830000 3074.820000 ;
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+        RECT 1528.630000 3058.020000 1529.830000 3058.500000 ;
+        RECT 1528.630000 3063.460000 1529.830000 3063.940000 ;
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+        RECT 1380.820000 3068.900000 1382.020000 3069.380000 ;
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+        RECT 1335.655000 3096.100000 1337.020000 3096.580000 ;
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
+
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+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+        RECT 1335.655000 1170.820000 1337.020000 1171.300000 ;
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+        RECT 1335.655000 1154.500000 1337.020000 1154.980000 ;
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+        RECT 1335.655000 1159.940000 1337.020000 1160.420000 ;
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+        RECT 1335.655000 1149.060000 1337.020000 1149.540000 ;
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+        RECT 1515.820000 1241.540000 1517.020000 1242.020000 ;
+        RECT 1528.630000 1241.540000 1529.830000 1242.020000 ;
+        RECT 1380.820000 1241.540000 1382.020000 1242.020000 ;
+        RECT 1425.820000 1241.540000 1427.020000 1242.020000 ;
+        RECT 1331.790000 1241.540000 1332.990000 1242.020000 ;
+        RECT 1335.655000 1241.540000 1337.020000 1242.020000 ;
+        RECT 1330.760000 1338.300000 1530.860000 1339.500000 ;
+        RECT 1330.760000 1142.530000 1530.860000 1143.730000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 1141.480000 1332.990000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1331.790000 1340.540000 1332.990000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 1141.480000 1529.830000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1528.630000 1340.540000 1529.830000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 1142.530000 1331.960000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 1142.530000 1530.860000 1143.730000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 1338.300000 1331.960000 1339.500000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 1338.300000 1530.860000 1339.500000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+    PORT
+      LAYER met4 ;
+        RECT 1540.755000 3127.720000 1542.120000 3128.200000 ;
+        RECT 1540.755000 3122.280000 1542.120000 3122.760000 ;
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+        RECT 1720.920000 3104.870000 1722.120000 3132.520000 ;
+      LAYER met3 ;
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+        RECT 1720.920000 3127.720000 1722.120000 3128.200000 ;
+        RECT 1720.920000 3122.280000 1722.120000 3122.760000 ;
+        RECT 1675.920000 3122.280000 1677.120000 3122.760000 ;
+        RECT 1675.920000 3127.720000 1677.120000 3128.200000 ;
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+        RECT 1585.920000 3122.280000 1587.120000 3122.760000 ;
+        RECT 1630.920000 3127.720000 1632.120000 3128.200000 ;
+        RECT 1585.920000 3127.720000 1587.120000 3128.200000 ;
+        RECT 1540.755000 3127.720000 1542.120000 3128.200000 ;
+        RECT 1536.890000 3127.720000 1538.090000 3128.200000 ;
+        RECT 1540.755000 3122.280000 1542.120000 3122.760000 ;
+        RECT 1536.890000 3122.280000 1538.090000 3122.760000 ;
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+        RECT 1675.920000 3111.400000 1677.120000 3111.880000 ;
+        RECT 1675.920000 3116.840000 1677.120000 3117.320000 ;
+        RECT 1630.920000 3111.400000 1632.120000 3111.880000 ;
+        RECT 1585.920000 3111.400000 1587.120000 3111.880000 ;
+        RECT 1630.920000 3116.840000 1632.120000 3117.320000 ;
+        RECT 1585.920000 3116.840000 1587.120000 3117.320000 ;
+        RECT 1540.755000 3116.840000 1542.120000 3117.320000 ;
+        RECT 1536.890000 3116.840000 1538.090000 3117.320000 ;
+        RECT 1540.755000 3111.400000 1542.120000 3111.880000 ;
+        RECT 1536.890000 3111.400000 1538.090000 3111.880000 ;
+        RECT 1535.860000 3131.320000 1735.960000 3132.520000 ;
+        RECT 1535.860000 3104.870000 1735.960000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1536.890000 3103.820000 1538.090000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1536.890000 3132.880000 1538.090000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 3103.820000 1734.930000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 3132.880000 1734.930000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 3104.870000 1537.060000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 3104.870000 1735.960000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 3131.320000 1537.060000 3132.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 3131.320000 1735.960000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+
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+        RECT 1536.890000 240.240000 1538.090000 240.720000 ;
+        RECT 1540.755000 240.240000 1542.120000 240.720000 ;
+        RECT 1535.860000 537.770000 1735.960000 538.970000 ;
+        RECT 1535.860000 141.230000 1735.960000 142.430000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1536.890000 539.500000 1538.090000 540.700000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 140.180000 1734.930000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 539.500000 1734.930000 540.700000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 537.770000 1735.960000 538.970000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 1585.920000 133.820000 1587.120000 134.300000 ;
+        RECT 1540.755000 133.820000 1542.120000 134.300000 ;
+        RECT 1536.890000 133.820000 1538.090000 134.300000 ;
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+        RECT 1536.890000 128.380000 1538.090000 128.860000 ;
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+        RECT 1540.755000 122.940000 1542.120000 123.420000 ;
+        RECT 1536.890000 122.940000 1538.090000 123.420000 ;
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+        RECT 1536.890000 117.500000 1538.090000 117.980000 ;
+        RECT 1535.860000 137.420000 1735.960000 138.620000 ;
+        RECT 1535.860000 110.970000 1735.960000 112.170000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1536.890000 138.980000 1538.090000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 109.920000 1734.930000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 138.980000 1734.930000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 110.970000 1537.060000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 110.970000 1735.960000 112.170000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 137.420000 1537.060000 138.620000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 137.420000 1735.960000 138.620000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
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+# end of P/G pin shape extracted from block 'DSP'
+
+
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1536.890000 1340.540000 1538.090000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1733.730000 1340.540000 1734.930000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 1338.810000 1735.960000 1340.010000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 1881.020000 3104.870000 1882.220000 3132.520000 ;
+        RECT 1926.020000 3104.870000 1927.220000 3132.520000 ;
+      LAYER met3 ;
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+        RECT 1791.020000 3127.720000 1792.220000 3128.200000 ;
+        RECT 1745.855000 3127.720000 1747.220000 3128.200000 ;
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+        RECT 1741.990000 3122.280000 1743.190000 3122.760000 ;
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+        RECT 1791.020000 3116.840000 1792.220000 3117.320000 ;
+        RECT 1745.855000 3116.840000 1747.220000 3117.320000 ;
+        RECT 1741.990000 3116.840000 1743.190000 3117.320000 ;
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+        RECT 1741.990000 3111.400000 1743.190000 3111.880000 ;
+        RECT 1740.960000 3131.320000 1941.060000 3132.520000 ;
+        RECT 1740.960000 3104.870000 1941.060000 3106.070000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1741.990000 3103.820000 1743.190000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1741.990000 3132.880000 1743.190000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1938.830000 3103.820000 1940.030000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1938.830000 3132.880000 1940.030000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1740.960000 3104.870000 1742.160000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1939.860000 3104.870000 1941.060000 3106.070000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1740.960000 3131.320000 1742.160000 3132.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1939.860000 3131.320000 1941.060000 3132.520000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1745.855000 1133.760000 1747.220000 1134.240000 ;
+        RECT 1745.855000 1122.880000 1747.220000 1123.360000 ;
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+        RECT 1745.855000 1084.800000 1747.220000 1085.280000 ;
+        RECT 1745.855000 1073.920000 1747.220000 1074.400000 ;
+        RECT 1745.855000 1068.480000 1747.220000 1068.960000 ;
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'ibex_top'
+
+
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+        RECT 2836.840000 1804.580000 2838.040000 1805.060000 ;
+        RECT 2830.080000 1810.020000 2831.445000 1810.500000 ;
+        RECT 2836.840000 1810.020000 2838.040000 1810.500000 ;
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+        RECT 2836.840000 1820.900000 2838.040000 1821.380000 ;
+        RECT 2291.240000 2330.960000 2841.400000 2332.160000 ;
+        RECT 2291.240000 1790.030000 2841.400000 1791.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2836.840000 1786.800000 2838.040000 1788.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2836.840000 2335.380000 2838.040000 2336.580000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2294.600000 1786.800000 2295.800000 1788.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2294.600000 2335.380000 2295.800000 2336.580000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2840.200000 1790.030000 2841.400000 1791.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2291.240000 1790.030000 2292.440000 1791.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2840.200000 2330.960000 2841.400000 2332.160000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2291.240000 2330.960000 2292.440000 2332.160000 ;
+    END
+# end of P/G pin shape extracted from block 'flexbex_ibex_core'
+
+
+# P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+    PORT
+      LAYER met4 ;
+        RECT 516.800000 2637.940000 518.540000 3032.720000 ;
+      LAYER met3 ;
+        RECT 41.480000 2637.940000 518.540000 2639.680000 ;
+      LAYER met3 ;
+        RECT 41.480000 3030.980000 518.540000 3032.720000 ;
+      LAYER met4 ;
+        RECT 41.480000 2637.940000 43.220000 3032.720000 ;
+    END
+# end of P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+
+
+# P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+    PORT
+      LAYER met4 ;
+        RECT 2362.980000 2637.940000 2364.720000 3032.720000 ;
+      LAYER met3 ;
+        RECT 2362.980000 2637.940000 2840.040000 2639.680000 ;
+      LAYER met3 ;
+        RECT 2362.980000 3030.980000 2840.040000 3032.720000 ;
+      LAYER met4 ;
+        RECT 2838.300000 2637.940000 2840.040000 3032.720000 ;
+    END
+# end of P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+
+  END vssd1
+  PIN vccd1
+    DIRECTION INOUT ;
+    USE POWER ;
+
+# P/G power stripe data as pin
+    PORT
+      LAYER met3 ;
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+    END
+# end of P/G power stripe data as pin
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 1140.280000 117.330000 1141.480000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 1136.240000 120.160000 1137.440000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 940.020000 44.150000 941.220000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 740.960000 117.330000 742.160000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 940.020000 117.330000 941.220000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 935.980000 120.160000 937.180000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 735.720000 120.160000 736.920000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 40.120000 343.290000 120.160000 344.490000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 340.440000 44.150000 341.640000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 539.500000 44.150000 540.700000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 340.440000 117.330000 341.640000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 539.500000 117.330000 540.700000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 40.120000 535.460000 41.320000 536.660000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 535.460000 120.160000 536.660000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 140.180000 44.150000 340.440000 ;
+        RECT 116.130000 140.180000 117.330000 340.440000 ;
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+      LAYER met3 ;
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+        RECT 40.120000 335.200000 120.160000 336.400000 ;
+        RECT 40.120000 143.030000 120.160000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 140.180000 44.150000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 42.950000 339.240000 44.150000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 140.180000 117.330000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 116.130000 339.240000 117.330000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 40.120000 143.030000 41.320000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 143.030000 120.160000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 40.120000 335.200000 41.320000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 118.960000 335.200000 120.160000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1943.890000 3103.820000 1945.090000 3134.080000 ;
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+# end of P/G pin shape extracted from block 'N_term_single'
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
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+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+
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+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+    PORT
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
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+
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+    END
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 535.460000 2341.260000 536.660000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2337.230000 339.240000 2338.430000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 143.030000 2142.360000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 143.030000 2341.260000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 335.200000 2142.360000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 335.200000 2341.260000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 109.920000 2145.190000 140.180000 ;
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+      LAYER met3 ;
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+        RECT 2193.220000 131.100000 2194.420000 131.580000 ;
+        RECT 2143.990000 125.660000 2145.190000 126.140000 ;
+        RECT 2148.220000 125.660000 2149.420000 126.140000 ;
+        RECT 2148.220000 131.100000 2149.420000 131.580000 ;
+        RECT 2143.990000 131.100000 2145.190000 131.580000 ;
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+        RECT 2283.220000 120.220000 2284.420000 120.700000 ;
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+        RECT 2148.220000 120.220000 2149.420000 120.700000 ;
+        RECT 2143.990000 114.780000 2145.190000 115.260000 ;
+        RECT 2148.220000 114.780000 2149.420000 115.260000 ;
+        RECT 2141.160000 135.620000 2341.260000 136.820000 ;
+        RECT 2141.160000 112.770000 2341.260000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 109.920000 2145.190000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 138.980000 2145.190000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2337.230000 109.920000 2338.430000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2337.230000 138.980000 2338.430000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 112.770000 2142.360000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 112.770000 2341.260000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 135.620000 2142.360000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2340.060000 135.620000 2341.260000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2903.560000 2145.190000 3103.820000 ;
+        RECT 2177.150000 2903.560000 2178.350000 3103.820000 ;
+        RECT 2148.220000 2906.410000 2149.420000 3099.780000 ;
+      LAYER met3 ;
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+        RECT 2177.150000 3082.500000 2178.350000 3082.980000 ;
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+        RECT 2177.150000 3033.540000 2178.350000 3034.020000 ;
+        RECT 2177.150000 3028.100000 2178.350000 3028.580000 ;
+        RECT 2177.150000 3022.660000 2178.350000 3023.140000 ;
+        RECT 2177.150000 3017.220000 2178.350000 3017.700000 ;
+        RECT 2177.150000 3011.780000 2178.350000 3012.260000 ;
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+        RECT 2143.990000 3087.940000 2145.190000 3088.420000 ;
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+        RECT 2148.220000 3082.500000 2149.420000 3082.980000 ;
+        RECT 2148.220000 3087.940000 2149.420000 3088.420000 ;
+        RECT 2143.990000 3071.620000 2145.190000 3072.100000 ;
+        RECT 2143.990000 3077.060000 2145.190000 3077.540000 ;
+        RECT 2148.220000 3071.620000 2149.420000 3072.100000 ;
+        RECT 2148.220000 3077.060000 2149.420000 3077.540000 ;
+        RECT 2143.990000 3055.300000 2145.190000 3055.780000 ;
+        RECT 2143.990000 3060.740000 2145.190000 3061.220000 ;
+        RECT 2148.220000 3055.300000 2149.420000 3055.780000 ;
+        RECT 2148.220000 3060.740000 2149.420000 3061.220000 ;
+        RECT 2148.220000 3066.180000 2149.420000 3066.660000 ;
+        RECT 2143.990000 3066.180000 2145.190000 3066.660000 ;
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+        RECT 2148.220000 3038.980000 2149.420000 3039.460000 ;
+        RECT 2148.220000 3033.540000 2149.420000 3034.020000 ;
+        RECT 2143.990000 3017.220000 2145.190000 3017.700000 ;
+        RECT 2143.990000 3022.660000 2145.190000 3023.140000 ;
+        RECT 2143.990000 3028.100000 2145.190000 3028.580000 ;
+        RECT 2148.220000 3017.220000 2149.420000 3017.700000 ;
+        RECT 2148.220000 3022.660000 2149.420000 3023.140000 ;
+        RECT 2148.220000 3028.100000 2149.420000 3028.580000 ;
+        RECT 2143.990000 3006.340000 2145.190000 3006.820000 ;
+        RECT 2143.990000 3011.780000 2145.190000 3012.260000 ;
+        RECT 2148.220000 3006.340000 2149.420000 3006.820000 ;
+        RECT 2148.220000 3011.780000 2149.420000 3012.260000 ;
+        RECT 2177.150000 2995.460000 2178.350000 2995.940000 ;
+        RECT 2177.150000 3000.900000 2178.350000 3001.380000 ;
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+        RECT 2177.150000 2990.020000 2178.350000 2990.500000 ;
+        RECT 2177.150000 2968.260000 2178.350000 2968.740000 ;
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+        RECT 2177.150000 2962.820000 2178.350000 2963.300000 ;
+        RECT 2177.150000 2957.380000 2178.350000 2957.860000 ;
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+        RECT 2177.150000 2935.620000 2178.350000 2936.100000 ;
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+        RECT 2177.150000 2924.740000 2178.350000 2925.220000 ;
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+        RECT 2148.220000 2995.460000 2149.420000 2995.940000 ;
+        RECT 2148.220000 3000.900000 2149.420000 3001.380000 ;
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+        RECT 2143.990000 2990.020000 2145.190000 2990.500000 ;
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+        RECT 2148.220000 2984.580000 2149.420000 2985.060000 ;
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+        RECT 2148.220000 2973.700000 2149.420000 2974.180000 ;
+        RECT 2143.990000 2962.820000 2145.190000 2963.300000 ;
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+        RECT 2148.220000 2962.820000 2149.420000 2963.300000 ;
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+        RECT 2143.990000 2951.940000 2145.190000 2952.420000 ;
+        RECT 2148.220000 2951.940000 2149.420000 2952.420000 ;
+        RECT 2148.220000 2946.500000 2149.420000 2946.980000 ;
+        RECT 2143.990000 2930.180000 2145.190000 2930.660000 ;
+        RECT 2143.990000 2935.620000 2145.190000 2936.100000 ;
+        RECT 2148.220000 2930.180000 2149.420000 2930.660000 ;
+        RECT 2148.220000 2935.620000 2149.420000 2936.100000 ;
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+        RECT 2143.990000 2941.060000 2145.190000 2941.540000 ;
+        RECT 2143.990000 2924.740000 2145.190000 2925.220000 ;
+        RECT 2143.990000 2919.300000 2145.190000 2919.780000 ;
+        RECT 2148.220000 2919.300000 2149.420000 2919.780000 ;
+        RECT 2148.220000 2924.740000 2149.420000 2925.220000 ;
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+        RECT 2148.220000 2908.420000 2149.420000 2908.900000 ;
+        RECT 2143.990000 2913.860000 2145.190000 2914.340000 ;
+        RECT 2143.990000 2908.420000 2145.190000 2908.900000 ;
+        RECT 2141.160000 3098.580000 2181.180000 3099.780000 ;
+        RECT 2141.160000 2906.410000 2181.180000 2907.610000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2903.560000 2145.190000 2904.760000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 3102.620000 2145.190000 3103.820000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2903.560000 2178.350000 2904.760000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 3102.620000 2178.350000 3103.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2906.410000 2142.360000 2907.610000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2906.410000 2181.180000 2907.610000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 3098.580000 2142.360000 3099.780000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 3098.580000 2181.180000 3099.780000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2703.300000 2145.190000 2903.560000 ;
+        RECT 2177.150000 2703.300000 2178.350000 2903.560000 ;
+        RECT 2148.220000 2706.150000 2149.420000 2899.520000 ;
+      LAYER met3 ;
+        RECT 2177.150000 2893.120000 2178.350000 2893.600000 ;
+        RECT 2177.150000 2887.680000 2178.350000 2888.160000 ;
+        RECT 2177.150000 2882.240000 2178.350000 2882.720000 ;
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+        RECT 2177.150000 2876.800000 2178.350000 2877.280000 ;
+        RECT 2177.150000 2855.040000 2178.350000 2855.520000 ;
+        RECT 2177.150000 2860.480000 2178.350000 2860.960000 ;
+        RECT 2177.150000 2865.920000 2178.350000 2866.400000 ;
+        RECT 2177.150000 2849.600000 2178.350000 2850.080000 ;
+        RECT 2177.150000 2844.160000 2178.350000 2844.640000 ;
+        RECT 2177.150000 2838.720000 2178.350000 2839.200000 ;
+        RECT 2177.150000 2833.280000 2178.350000 2833.760000 ;
+        RECT 2177.150000 2827.840000 2178.350000 2828.320000 ;
+        RECT 2177.150000 2822.400000 2178.350000 2822.880000 ;
+        RECT 2177.150000 2816.960000 2178.350000 2817.440000 ;
+        RECT 2177.150000 2811.520000 2178.350000 2812.000000 ;
+        RECT 2177.150000 2806.080000 2178.350000 2806.560000 ;
+        RECT 2148.220000 2893.120000 2149.420000 2893.600000 ;
+        RECT 2143.990000 2893.120000 2145.190000 2893.600000 ;
+        RECT 2143.990000 2887.680000 2145.190000 2888.160000 ;
+        RECT 2143.990000 2882.240000 2145.190000 2882.720000 ;
+        RECT 2148.220000 2882.240000 2149.420000 2882.720000 ;
+        RECT 2148.220000 2887.680000 2149.420000 2888.160000 ;
+        RECT 2143.990000 2871.360000 2145.190000 2871.840000 ;
+        RECT 2143.990000 2876.800000 2145.190000 2877.280000 ;
+        RECT 2148.220000 2871.360000 2149.420000 2871.840000 ;
+        RECT 2148.220000 2876.800000 2149.420000 2877.280000 ;
+        RECT 2143.990000 2855.040000 2145.190000 2855.520000 ;
+        RECT 2143.990000 2860.480000 2145.190000 2860.960000 ;
+        RECT 2148.220000 2855.040000 2149.420000 2855.520000 ;
+        RECT 2148.220000 2860.480000 2149.420000 2860.960000 ;
+        RECT 2148.220000 2865.920000 2149.420000 2866.400000 ;
+        RECT 2143.990000 2865.920000 2145.190000 2866.400000 ;
+        RECT 2143.990000 2849.600000 2145.190000 2850.080000 ;
+        RECT 2143.990000 2844.160000 2145.190000 2844.640000 ;
+        RECT 2148.220000 2849.600000 2149.420000 2850.080000 ;
+        RECT 2148.220000 2844.160000 2149.420000 2844.640000 ;
+        RECT 2143.990000 2833.280000 2145.190000 2833.760000 ;
+        RECT 2143.990000 2838.720000 2145.190000 2839.200000 ;
+        RECT 2148.220000 2838.720000 2149.420000 2839.200000 ;
+        RECT 2148.220000 2833.280000 2149.420000 2833.760000 ;
+        RECT 2143.990000 2816.960000 2145.190000 2817.440000 ;
+        RECT 2143.990000 2822.400000 2145.190000 2822.880000 ;
+        RECT 2143.990000 2827.840000 2145.190000 2828.320000 ;
+        RECT 2148.220000 2816.960000 2149.420000 2817.440000 ;
+        RECT 2148.220000 2822.400000 2149.420000 2822.880000 ;
+        RECT 2148.220000 2827.840000 2149.420000 2828.320000 ;
+        RECT 2143.990000 2806.080000 2145.190000 2806.560000 ;
+        RECT 2143.990000 2811.520000 2145.190000 2812.000000 ;
+        RECT 2148.220000 2806.080000 2149.420000 2806.560000 ;
+        RECT 2148.220000 2811.520000 2149.420000 2812.000000 ;
+        RECT 2177.150000 2795.200000 2178.350000 2795.680000 ;
+        RECT 2177.150000 2800.640000 2178.350000 2801.120000 ;
+        RECT 2177.150000 2778.880000 2178.350000 2779.360000 ;
+        RECT 2177.150000 2784.320000 2178.350000 2784.800000 ;
+        RECT 2177.150000 2789.760000 2178.350000 2790.240000 ;
+        RECT 2177.150000 2768.000000 2178.350000 2768.480000 ;
+        RECT 2177.150000 2773.440000 2178.350000 2773.920000 ;
+        RECT 2177.150000 2762.560000 2178.350000 2763.040000 ;
+        RECT 2177.150000 2757.120000 2178.350000 2757.600000 ;
+        RECT 2177.150000 2751.680000 2178.350000 2752.160000 ;
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+        RECT 2177.150000 2735.360000 2178.350000 2735.840000 ;
+        RECT 2177.150000 2729.920000 2178.350000 2730.400000 ;
+        RECT 2177.150000 2740.800000 2178.350000 2741.280000 ;
+        RECT 2177.150000 2724.480000 2178.350000 2724.960000 ;
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+        RECT 2177.150000 2713.600000 2178.350000 2714.080000 ;
+        RECT 2177.150000 2708.160000 2178.350000 2708.640000 ;
+        RECT 2143.990000 2795.200000 2145.190000 2795.680000 ;
+        RECT 2143.990000 2800.640000 2145.190000 2801.120000 ;
+        RECT 2148.220000 2795.200000 2149.420000 2795.680000 ;
+        RECT 2148.220000 2800.640000 2149.420000 2801.120000 ;
+        RECT 2143.990000 2778.880000 2145.190000 2779.360000 ;
+        RECT 2143.990000 2784.320000 2145.190000 2784.800000 ;
+        RECT 2143.990000 2789.760000 2145.190000 2790.240000 ;
+        RECT 2148.220000 2778.880000 2149.420000 2779.360000 ;
+        RECT 2148.220000 2784.320000 2149.420000 2784.800000 ;
+        RECT 2148.220000 2789.760000 2149.420000 2790.240000 ;
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+        RECT 2148.220000 2762.560000 2149.420000 2763.040000 ;
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+        RECT 2148.220000 2751.680000 2149.420000 2752.160000 ;
+        RECT 2148.220000 2746.240000 2149.420000 2746.720000 ;
+        RECT 2143.990000 2729.920000 2145.190000 2730.400000 ;
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+        RECT 2148.220000 2729.920000 2149.420000 2730.400000 ;
+        RECT 2148.220000 2735.360000 2149.420000 2735.840000 ;
+        RECT 2148.220000 2740.800000 2149.420000 2741.280000 ;
+        RECT 2143.990000 2740.800000 2145.190000 2741.280000 ;
+        RECT 2143.990000 2724.480000 2145.190000 2724.960000 ;
+        RECT 2143.990000 2719.040000 2145.190000 2719.520000 ;
+        RECT 2148.220000 2719.040000 2149.420000 2719.520000 ;
+        RECT 2148.220000 2724.480000 2149.420000 2724.960000 ;
+        RECT 2148.220000 2713.600000 2149.420000 2714.080000 ;
+        RECT 2148.220000 2708.160000 2149.420000 2708.640000 ;
+        RECT 2143.990000 2713.600000 2145.190000 2714.080000 ;
+        RECT 2143.990000 2708.160000 2145.190000 2708.640000 ;
+        RECT 2141.160000 2898.320000 2181.180000 2899.520000 ;
+        RECT 2141.160000 2706.150000 2181.180000 2707.350000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2703.300000 2145.190000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2902.360000 2145.190000 2903.560000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2703.300000 2178.350000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2902.360000 2178.350000 2903.560000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2706.150000 2142.360000 2707.350000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2706.150000 2181.180000 2707.350000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2898.320000 2142.360000 2899.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2898.320000 2181.180000 2899.520000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2463.040000 2145.190000 2663.300000 ;
+        RECT 2177.150000 2463.040000 2178.350000 2663.300000 ;
+        RECT 2148.220000 2465.890000 2149.420000 2659.260000 ;
+      LAYER met3 ;
+        RECT 2177.150000 2652.860000 2178.350000 2653.340000 ;
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+        RECT 2177.150000 2641.980000 2178.350000 2642.460000 ;
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+        RECT 2177.150000 2620.220000 2178.350000 2620.700000 ;
+        RECT 2177.150000 2625.660000 2178.350000 2626.140000 ;
+        RECT 2177.150000 2609.340000 2178.350000 2609.820000 ;
+        RECT 2177.150000 2603.900000 2178.350000 2604.380000 ;
+        RECT 2177.150000 2598.460000 2178.350000 2598.940000 ;
+        RECT 2177.150000 2593.020000 2178.350000 2593.500000 ;
+        RECT 2177.150000 2587.580000 2178.350000 2588.060000 ;
+        RECT 2177.150000 2582.140000 2178.350000 2582.620000 ;
+        RECT 2177.150000 2576.700000 2178.350000 2577.180000 ;
+        RECT 2177.150000 2571.260000 2178.350000 2571.740000 ;
+        RECT 2177.150000 2565.820000 2178.350000 2566.300000 ;
+        RECT 2148.220000 2652.860000 2149.420000 2653.340000 ;
+        RECT 2143.990000 2652.860000 2145.190000 2653.340000 ;
+        RECT 2143.990000 2647.420000 2145.190000 2647.900000 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2658.060000 2181.180000 2659.260000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2461.840000 2145.190000 2463.040000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2461.840000 2178.350000 2463.040000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2457.800000 2181.180000 2459.000000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 2143.990000 2032.820000 2145.190000 2033.300000 ;
+        RECT 2143.990000 2027.380000 2145.190000 2027.860000 ;
+        RECT 2141.160000 2217.540000 2181.180000 2218.740000 ;
+        RECT 2141.160000 2025.370000 2181.180000 2026.570000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2022.520000 2145.190000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2221.580000 2145.190000 2222.780000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2022.520000 2178.350000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2221.580000 2178.350000 2222.780000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2025.370000 2142.360000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2025.370000 2181.180000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2217.540000 2142.360000 2218.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2217.540000 2181.180000 2218.740000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1822.260000 2145.190000 2022.520000 ;
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+        RECT 2148.220000 1825.110000 2149.420000 2018.480000 ;
+      LAYER met3 ;
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+        RECT 2143.990000 1984.880000 2145.190000 1985.360000 ;
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+        RECT 2177.150000 1903.280000 2178.350000 1903.760000 ;
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+        RECT 2143.990000 1832.560000 2145.190000 1833.040000 ;
+        RECT 2143.990000 1827.120000 2145.190000 1827.600000 ;
+        RECT 2141.160000 2017.280000 2181.180000 2018.480000 ;
+        RECT 2141.160000 1825.110000 2181.180000 1826.310000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1822.260000 2145.190000 1823.460000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 2021.320000 2145.190000 2022.520000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 1822.260000 2178.350000 1823.460000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 2021.320000 2178.350000 2022.520000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1825.110000 2142.360000 1826.310000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1825.110000 2181.180000 1826.310000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 2017.280000 2142.360000 2018.480000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 2017.280000 2181.180000 2018.480000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1582.000000 2145.190000 1782.260000 ;
+        RECT 2177.150000 1582.000000 2178.350000 1782.260000 ;
+        RECT 2148.220000 1584.850000 2149.420000 1778.220000 ;
+      LAYER met3 ;
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+        RECT 2148.220000 1739.180000 2149.420000 1739.660000 ;
+        RECT 2148.220000 1744.620000 2149.420000 1745.100000 ;
+        RECT 2143.990000 1744.620000 2145.190000 1745.100000 ;
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+        RECT 2148.220000 1728.300000 2149.420000 1728.780000 ;
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+        RECT 2143.990000 1706.540000 2145.190000 1707.020000 ;
+        RECT 2148.220000 1695.660000 2149.420000 1696.140000 ;
+        RECT 2148.220000 1701.100000 2149.420000 1701.580000 ;
+        RECT 2148.220000 1706.540000 2149.420000 1707.020000 ;
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+        RECT 2177.150000 1608.620000 2178.350000 1609.100000 ;
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+        RECT 2148.220000 1608.620000 2149.420000 1609.100000 ;
+        RECT 2148.220000 1614.060000 2149.420000 1614.540000 ;
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+        RECT 2143.990000 1619.500000 2145.190000 1619.980000 ;
+        RECT 2143.990000 1603.180000 2145.190000 1603.660000 ;
+        RECT 2143.990000 1597.740000 2145.190000 1598.220000 ;
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+        RECT 2148.220000 1603.180000 2149.420000 1603.660000 ;
+        RECT 2148.220000 1592.300000 2149.420000 1592.780000 ;
+        RECT 2148.220000 1586.860000 2149.420000 1587.340000 ;
+        RECT 2143.990000 1592.300000 2145.190000 1592.780000 ;
+        RECT 2143.990000 1586.860000 2145.190000 1587.340000 ;
+        RECT 2141.160000 1777.020000 2181.180000 1778.220000 ;
+        RECT 2141.160000 1584.850000 2181.180000 1586.050000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1582.000000 2145.190000 1583.200000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1781.060000 2145.190000 1782.260000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 1582.000000 2178.350000 1583.200000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2177.150000 1781.060000 2178.350000 1782.260000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1584.850000 2142.360000 1586.050000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1584.850000 2181.180000 1586.050000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2141.160000 1777.020000 2142.360000 1778.220000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2179.980000 1777.020000 2181.180000 1778.220000 ;
+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
+# P/G pin shape extracted from block 'E_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2143.990000 1381.740000 2145.190000 1582.000000 ;
+        RECT 2177.150000 1381.740000 2178.350000 1582.000000 ;
+        RECT 2148.220000 1384.590000 2149.420000 1577.960000 ;
+      LAYER met3 ;
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+        RECT 2177.150000 1517.160000 2178.350000 1517.640000 ;
+        RECT 2177.150000 1511.720000 2178.350000 1512.200000 ;
+        RECT 2177.150000 1506.280000 2178.350000 1506.760000 ;
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+        RECT 2143.990000 1571.560000 2145.190000 1572.040000 ;
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+    END
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+    END
+# end of P/G pin shape extracted from block 'E_CPU_IO'
+
+
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+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 1140.280000 2538.530000 1141.480000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 1136.240000 2541.360000 1137.440000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
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+    END
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+    PORT
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+        RECT 2438.320000 161.360000 2439.520000 161.840000 ;
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+        RECT 2344.090000 183.120000 2345.290000 183.600000 ;
+        RECT 2344.090000 188.560000 2345.290000 189.040000 ;
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+        RECT 2344.090000 166.800000 2345.290000 167.280000 ;
+        RECT 2344.090000 172.240000 2345.290000 172.720000 ;
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+        RECT 2344.090000 177.680000 2345.290000 178.160000 ;
+        RECT 2348.320000 161.360000 2349.520000 161.840000 ;
+        RECT 2344.090000 161.360000 2345.290000 161.840000 ;
+        RECT 2348.320000 155.920000 2349.520000 156.400000 ;
+        RECT 2344.090000 155.920000 2345.290000 156.400000 ;
+        RECT 2348.320000 145.040000 2349.520000 145.520000 ;
+        RECT 2348.320000 150.480000 2349.520000 150.960000 ;
+        RECT 2344.090000 145.040000 2345.290000 145.520000 ;
+        RECT 2344.090000 150.480000 2345.290000 150.960000 ;
+        RECT 2341.260000 335.200000 2541.360000 336.400000 ;
+        RECT 2341.260000 143.030000 2541.360000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 140.180000 2345.290000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 339.240000 2345.290000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 140.180000 2538.530000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 339.240000 2538.530000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 143.030000 2342.460000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 143.030000 2541.360000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 335.200000 2342.460000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 335.200000 2541.360000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 109.920000 2345.290000 140.180000 ;
+        RECT 2537.330000 109.920000 2538.530000 140.180000 ;
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+        RECT 2393.320000 112.770000 2394.520000 136.820000 ;
+        RECT 2438.320000 112.770000 2439.520000 136.820000 ;
+        RECT 2483.320000 112.770000 2484.520000 136.820000 ;
+        RECT 2528.320000 112.770000 2529.520000 136.820000 ;
+      LAYER met3 ;
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+        RECT 2537.330000 131.100000 2538.530000 131.580000 ;
+        RECT 2528.320000 131.100000 2529.520000 131.580000 ;
+        RECT 2528.320000 125.660000 2529.520000 126.140000 ;
+        RECT 2483.320000 125.660000 2484.520000 126.140000 ;
+        RECT 2483.320000 131.100000 2484.520000 131.580000 ;
+        RECT 2393.320000 125.660000 2394.520000 126.140000 ;
+        RECT 2438.320000 125.660000 2439.520000 126.140000 ;
+        RECT 2438.320000 131.100000 2439.520000 131.580000 ;
+        RECT 2393.320000 131.100000 2394.520000 131.580000 ;
+        RECT 2344.090000 125.660000 2345.290000 126.140000 ;
+        RECT 2348.320000 125.660000 2349.520000 126.140000 ;
+        RECT 2348.320000 131.100000 2349.520000 131.580000 ;
+        RECT 2344.090000 131.100000 2345.290000 131.580000 ;
+        RECT 2537.330000 114.780000 2538.530000 115.260000 ;
+        RECT 2537.330000 120.220000 2538.530000 120.700000 ;
+        RECT 2528.320000 120.220000 2529.520000 120.700000 ;
+        RECT 2528.320000 114.780000 2529.520000 115.260000 ;
+        RECT 2483.320000 114.780000 2484.520000 115.260000 ;
+        RECT 2483.320000 120.220000 2484.520000 120.700000 ;
+        RECT 2393.320000 114.780000 2394.520000 115.260000 ;
+        RECT 2438.320000 114.780000 2439.520000 115.260000 ;
+        RECT 2438.320000 120.220000 2439.520000 120.700000 ;
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+        RECT 2348.320000 120.220000 2349.520000 120.700000 ;
+        RECT 2344.090000 114.780000 2345.290000 115.260000 ;
+        RECT 2348.320000 114.780000 2349.520000 115.260000 ;
+        RECT 2341.260000 135.620000 2541.360000 136.820000 ;
+        RECT 2341.260000 112.770000 2541.360000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 109.920000 2345.290000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 138.980000 2345.290000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 109.920000 2538.530000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 138.980000 2538.530000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 112.770000 2342.460000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 112.770000 2541.360000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 135.620000 2342.460000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 135.620000 2541.360000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 1141.480000 2345.290000 1171.740000 ;
+        RECT 2537.330000 1141.480000 2538.530000 1171.740000 ;
+        RECT 2348.320000 1144.330000 2349.520000 1168.380000 ;
+        RECT 2393.320000 1144.330000 2394.520000 1168.380000 ;
+        RECT 2438.320000 1144.330000 2439.520000 1168.380000 ;
+        RECT 2483.320000 1144.330000 2484.520000 1168.380000 ;
+        RECT 2528.320000 1144.330000 2529.520000 1168.380000 ;
+      LAYER met3 ;
+        RECT 2537.330000 1157.220000 2538.530000 1157.700000 ;
+        RECT 2537.330000 1162.660000 2538.530000 1163.140000 ;
+        RECT 2528.320000 1162.660000 2529.520000 1163.140000 ;
+        RECT 2528.320000 1157.220000 2529.520000 1157.700000 ;
+        RECT 2483.320000 1157.220000 2484.520000 1157.700000 ;
+        RECT 2483.320000 1162.660000 2484.520000 1163.140000 ;
+        RECT 2393.320000 1157.220000 2394.520000 1157.700000 ;
+        RECT 2438.320000 1157.220000 2439.520000 1157.700000 ;
+        RECT 2438.320000 1162.660000 2439.520000 1163.140000 ;
+        RECT 2393.320000 1162.660000 2394.520000 1163.140000 ;
+        RECT 2344.090000 1157.220000 2345.290000 1157.700000 ;
+        RECT 2348.320000 1157.220000 2349.520000 1157.700000 ;
+        RECT 2348.320000 1162.660000 2349.520000 1163.140000 ;
+        RECT 2344.090000 1162.660000 2345.290000 1163.140000 ;
+        RECT 2537.330000 1146.340000 2538.530000 1146.820000 ;
+        RECT 2537.330000 1151.780000 2538.530000 1152.260000 ;
+        RECT 2528.320000 1151.780000 2529.520000 1152.260000 ;
+        RECT 2528.320000 1146.340000 2529.520000 1146.820000 ;
+        RECT 2483.320000 1146.340000 2484.520000 1146.820000 ;
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+        RECT 2438.320000 1146.340000 2439.520000 1146.820000 ;
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+        RECT 2393.320000 1151.780000 2394.520000 1152.260000 ;
+        RECT 2344.090000 1151.780000 2345.290000 1152.260000 ;
+        RECT 2348.320000 1151.780000 2349.520000 1152.260000 ;
+        RECT 2344.090000 1146.340000 2345.290000 1146.820000 ;
+        RECT 2348.320000 1146.340000 2349.520000 1146.820000 ;
+        RECT 2341.260000 1167.180000 2541.360000 1168.380000 ;
+        RECT 2341.260000 1144.330000 2541.360000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 1141.480000 2345.290000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2344.090000 1170.540000 2345.290000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 1141.480000 2538.530000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2537.330000 1170.540000 2538.530000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 1144.330000 2342.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 1144.330000 2541.360000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2341.260000 1167.180000 2342.460000 1168.380000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2540.160000 1167.180000 2541.360000 1168.380000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single2'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 2728.420000 944.070000 2729.620000 1137.440000 ;
+        RECT 2683.420000 944.070000 2684.620000 1137.440000 ;
+        RECT 2737.430000 941.220000 2738.630000 1141.480000 ;
+        RECT 2638.420000 944.070000 2639.620000 1137.440000 ;
+        RECT 2593.420000 944.070000 2594.620000 1137.440000 ;
+        RECT 2548.420000 944.070000 2549.620000 1137.440000 ;
+        RECT 2544.190000 941.220000 2545.390000 1141.480000 ;
+      LAYER met3 ;
+        RECT 2728.420000 1131.040000 2729.620000 1131.520000 ;
+        RECT 2737.430000 1131.040000 2738.630000 1131.520000 ;
+        RECT 2737.430000 1120.160000 2738.630000 1120.640000 ;
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+        RECT 2728.420000 1125.600000 2729.620000 1126.080000 ;
+        RECT 2728.420000 1120.160000 2729.620000 1120.640000 ;
+        RECT 2728.420000 1114.720000 2729.620000 1115.200000 ;
+        RECT 2728.420000 1109.280000 2729.620000 1109.760000 ;
+        RECT 2737.430000 1114.720000 2738.630000 1115.200000 ;
+        RECT 2737.430000 1109.280000 2738.630000 1109.760000 ;
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+        RECT 2737.430000 1098.400000 2738.630000 1098.880000 ;
+        RECT 2737.430000 1092.960000 2738.630000 1093.440000 ;
+        RECT 2728.420000 1103.840000 2729.620000 1104.320000 ;
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+        RECT 2728.420000 1060.320000 2729.620000 1060.800000 ;
+        RECT 2728.420000 1054.880000 2729.620000 1055.360000 ;
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+        RECT 2728.420000 1049.440000 2729.620000 1049.920000 ;
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+        RECT 2737.430000 1049.440000 2738.630000 1049.920000 ;
+        RECT 2737.430000 1044.000000 2738.630000 1044.480000 ;
+        RECT 2683.420000 1087.520000 2684.620000 1088.000000 ;
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+        RECT 2683.420000 1076.640000 2684.620000 1077.120000 ;
+        RECT 2683.420000 1071.200000 2684.620000 1071.680000 ;
+        RECT 2683.420000 1060.320000 2684.620000 1060.800000 ;
+        RECT 2683.420000 1054.880000 2684.620000 1055.360000 ;
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+        RECT 2683.420000 1044.000000 2684.620000 1044.480000 ;
+        RECT 2683.420000 1065.760000 2684.620000 1066.240000 ;
+        RECT 2638.420000 1131.040000 2639.620000 1131.520000 ;
+        RECT 2638.420000 1125.600000 2639.620000 1126.080000 ;
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+        RECT 2593.420000 1131.040000 2594.620000 1131.520000 ;
+        RECT 2593.420000 1125.600000 2594.620000 1126.080000 ;
+        RECT 2593.420000 1120.160000 2594.620000 1120.640000 ;
+        RECT 2638.420000 1103.840000 2639.620000 1104.320000 ;
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+        RECT 2638.420000 1092.960000 2639.620000 1093.440000 ;
+        RECT 2638.420000 1109.280000 2639.620000 1109.760000 ;
+        RECT 2638.420000 1114.720000 2639.620000 1115.200000 ;
+        RECT 2593.420000 1114.720000 2594.620000 1115.200000 ;
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+        RECT 2593.420000 1092.960000 2594.620000 1093.440000 ;
+        RECT 2593.420000 1109.280000 2594.620000 1109.760000 ;
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+        RECT 2548.420000 1114.720000 2549.620000 1115.200000 ;
+        RECT 2544.190000 1114.720000 2545.390000 1115.200000 ;
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+        RECT 2593.420000 1087.520000 2594.620000 1088.000000 ;
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
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+        RECT 2541.360000 343.290000 2542.560000 344.490000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 343.290000 2741.460000 344.490000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 535.460000 2542.560000 536.660000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 535.460000 2741.460000 536.660000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 2544.190000 291.920000 2545.390000 292.400000 ;
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+        RECT 2728.420000 161.360000 2729.620000 161.840000 ;
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+        RECT 2728.420000 145.040000 2729.620000 145.520000 ;
+        RECT 2737.430000 150.480000 2738.630000 150.960000 ;
+        RECT 2737.430000 145.040000 2738.630000 145.520000 ;
+        RECT 2683.420000 188.560000 2684.620000 189.040000 ;
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+        RECT 2683.420000 150.480000 2684.620000 150.960000 ;
+        RECT 2683.420000 145.040000 2684.620000 145.520000 ;
+        RECT 2638.420000 237.520000 2639.620000 238.000000 ;
+        RECT 2638.420000 232.080000 2639.620000 232.560000 ;
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+        RECT 2638.420000 221.200000 2639.620000 221.680000 ;
+        RECT 2638.420000 215.760000 2639.620000 216.240000 ;
+        RECT 2593.420000 237.520000 2594.620000 238.000000 ;
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+        RECT 2593.420000 215.760000 2594.620000 216.240000 ;
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+        RECT 2548.420000 237.520000 2549.620000 238.000000 ;
+        RECT 2544.190000 237.520000 2545.390000 238.000000 ;
+        RECT 2548.420000 232.080000 2549.620000 232.560000 ;
+        RECT 2544.190000 232.080000 2545.390000 232.560000 ;
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+        RECT 2544.190000 226.640000 2545.390000 227.120000 ;
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+        RECT 2544.190000 177.680000 2545.390000 178.160000 ;
+        RECT 2548.420000 161.360000 2549.620000 161.840000 ;
+        RECT 2544.190000 161.360000 2545.390000 161.840000 ;
+        RECT 2548.420000 155.920000 2549.620000 156.400000 ;
+        RECT 2544.190000 155.920000 2545.390000 156.400000 ;
+        RECT 2548.420000 150.480000 2549.620000 150.960000 ;
+        RECT 2548.420000 145.040000 2549.620000 145.520000 ;
+        RECT 2544.190000 150.480000 2545.390000 150.960000 ;
+        RECT 2544.190000 145.040000 2545.390000 145.520000 ;
+        RECT 2541.360000 335.200000 2741.460000 336.400000 ;
+        RECT 2541.360000 143.030000 2741.460000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 140.180000 2545.390000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 339.240000 2545.390000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 140.180000 2738.630000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 339.240000 2738.630000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 143.030000 2542.560000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 143.030000 2741.460000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 335.200000 2542.560000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 335.200000 2741.460000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 109.920000 2545.390000 140.180000 ;
+        RECT 2737.430000 109.920000 2738.630000 140.180000 ;
+        RECT 2548.420000 112.770000 2549.620000 136.820000 ;
+        RECT 2593.420000 112.770000 2594.620000 136.820000 ;
+        RECT 2638.420000 112.770000 2639.620000 136.820000 ;
+        RECT 2683.420000 112.770000 2684.620000 136.820000 ;
+        RECT 2728.420000 112.770000 2729.620000 136.820000 ;
+      LAYER met3 ;
+        RECT 2737.430000 125.660000 2738.630000 126.140000 ;
+        RECT 2737.430000 131.100000 2738.630000 131.580000 ;
+        RECT 2728.420000 131.100000 2729.620000 131.580000 ;
+        RECT 2728.420000 125.660000 2729.620000 126.140000 ;
+        RECT 2683.420000 125.660000 2684.620000 126.140000 ;
+        RECT 2683.420000 131.100000 2684.620000 131.580000 ;
+        RECT 2593.420000 125.660000 2594.620000 126.140000 ;
+        RECT 2638.420000 125.660000 2639.620000 126.140000 ;
+        RECT 2638.420000 131.100000 2639.620000 131.580000 ;
+        RECT 2593.420000 131.100000 2594.620000 131.580000 ;
+        RECT 2544.190000 125.660000 2545.390000 126.140000 ;
+        RECT 2548.420000 125.660000 2549.620000 126.140000 ;
+        RECT 2548.420000 131.100000 2549.620000 131.580000 ;
+        RECT 2544.190000 131.100000 2545.390000 131.580000 ;
+        RECT 2737.430000 114.780000 2738.630000 115.260000 ;
+        RECT 2737.430000 120.220000 2738.630000 120.700000 ;
+        RECT 2728.420000 120.220000 2729.620000 120.700000 ;
+        RECT 2728.420000 114.780000 2729.620000 115.260000 ;
+        RECT 2683.420000 114.780000 2684.620000 115.260000 ;
+        RECT 2683.420000 120.220000 2684.620000 120.700000 ;
+        RECT 2593.420000 114.780000 2594.620000 115.260000 ;
+        RECT 2638.420000 114.780000 2639.620000 115.260000 ;
+        RECT 2638.420000 120.220000 2639.620000 120.700000 ;
+        RECT 2593.420000 120.220000 2594.620000 120.700000 ;
+        RECT 2544.190000 120.220000 2545.390000 120.700000 ;
+        RECT 2548.420000 120.220000 2549.620000 120.700000 ;
+        RECT 2544.190000 114.780000 2545.390000 115.260000 ;
+        RECT 2548.420000 114.780000 2549.620000 115.260000 ;
+        RECT 2541.360000 135.620000 2741.460000 136.820000 ;
+        RECT 2541.360000 112.770000 2741.460000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 109.920000 2545.390000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 138.980000 2545.390000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 109.920000 2738.630000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 138.980000 2738.630000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 112.770000 2542.560000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 112.770000 2741.460000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 135.620000 2542.560000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 135.620000 2741.460000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 1141.480000 2545.390000 1171.740000 ;
+        RECT 2737.430000 1141.480000 2738.630000 1171.740000 ;
+        RECT 2548.420000 1144.330000 2549.620000 1168.380000 ;
+        RECT 2593.420000 1144.330000 2594.620000 1168.380000 ;
+        RECT 2638.420000 1144.330000 2639.620000 1168.380000 ;
+        RECT 2683.420000 1144.330000 2684.620000 1168.380000 ;
+        RECT 2728.420000 1144.330000 2729.620000 1168.380000 ;
+      LAYER met3 ;
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+        RECT 2683.420000 1162.660000 2684.620000 1163.140000 ;
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+        RECT 2638.420000 1162.660000 2639.620000 1163.140000 ;
+        RECT 2593.420000 1162.660000 2594.620000 1163.140000 ;
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+        RECT 2548.420000 1157.220000 2549.620000 1157.700000 ;
+        RECT 2548.420000 1162.660000 2549.620000 1163.140000 ;
+        RECT 2544.190000 1162.660000 2545.390000 1163.140000 ;
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+        RECT 2728.420000 1146.340000 2729.620000 1146.820000 ;
+        RECT 2683.420000 1146.340000 2684.620000 1146.820000 ;
+        RECT 2683.420000 1151.780000 2684.620000 1152.260000 ;
+        RECT 2593.420000 1146.340000 2594.620000 1146.820000 ;
+        RECT 2638.420000 1146.340000 2639.620000 1146.820000 ;
+        RECT 2638.420000 1151.780000 2639.620000 1152.260000 ;
+        RECT 2593.420000 1151.780000 2594.620000 1152.260000 ;
+        RECT 2544.190000 1151.780000 2545.390000 1152.260000 ;
+        RECT 2548.420000 1151.780000 2549.620000 1152.260000 ;
+        RECT 2544.190000 1146.340000 2545.390000 1146.820000 ;
+        RECT 2548.420000 1146.340000 2549.620000 1146.820000 ;
+        RECT 2541.360000 1167.180000 2741.460000 1168.380000 ;
+        RECT 2541.360000 1144.330000 2741.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 1141.480000 2545.390000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2544.190000 1170.540000 2545.390000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 1141.480000 2738.630000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2737.430000 1170.540000 2738.630000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 1144.330000 2542.560000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 1144.330000 2741.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2541.360000 1167.180000 2542.560000 1168.380000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2740.260000 1167.180000 2741.460000 1168.380000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 2748.520000 1103.840000 2749.720000 1104.320000 ;
+        RECT 2748.520000 1098.400000 2749.720000 1098.880000 ;
+        RECT 2748.520000 1092.960000 2749.720000 1093.440000 ;
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+        RECT 2838.520000 1000.480000 2839.720000 1000.960000 ;
+        RECT 2838.520000 1005.920000 2839.720000 1006.400000 ;
+        RECT 2838.520000 1011.360000 2839.720000 1011.840000 ;
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+        RECT 2847.370000 951.520000 2848.570000 952.000000 ;
+        RECT 2847.370000 956.960000 2848.570000 957.440000 ;
+        RECT 2847.370000 962.400000 2848.570000 962.880000 ;
+        RECT 2838.520000 989.600000 2839.720000 990.080000 ;
+        RECT 2838.520000 984.160000 2839.720000 984.640000 ;
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+        RECT 2838.520000 967.840000 2839.720000 968.320000 ;
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+        RECT 2748.520000 1005.920000 2749.720000 1006.400000 ;
+        RECT 2748.520000 1000.480000 2749.720000 1000.960000 ;
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+        RECT 2744.290000 1016.800000 2745.490000 1017.280000 ;
+        RECT 2744.290000 1022.240000 2745.490000 1022.720000 ;
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+        RECT 2744.290000 1000.480000 2745.490000 1000.960000 ;
+        RECT 2744.290000 1005.920000 2745.490000 1006.400000 ;
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+        RECT 2793.520000 978.720000 2794.720000 979.200000 ;
+        RECT 2793.520000 973.280000 2794.720000 973.760000 ;
+        RECT 2793.520000 967.840000 2794.720000 968.320000 ;
+        RECT 2748.520000 989.600000 2749.720000 990.080000 ;
+        RECT 2748.520000 984.160000 2749.720000 984.640000 ;
+        RECT 2748.520000 978.720000 2749.720000 979.200000 ;
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+        RECT 2793.520000 951.520000 2794.720000 952.000000 ;
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+        RECT 2748.520000 956.960000 2749.720000 957.440000 ;
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+        RECT 2744.290000 989.600000 2745.490000 990.080000 ;
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+        RECT 2744.290000 951.520000 2745.490000 952.000000 ;
+        RECT 2744.290000 956.960000 2745.490000 957.440000 ;
+        RECT 2744.290000 962.400000 2745.490000 962.880000 ;
+        RECT 2741.460000 1136.240000 2851.400000 1137.440000 ;
+        RECT 2741.460000 944.070000 2851.400000 945.270000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 941.220000 2745.490000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 1140.280000 2745.490000 1141.480000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 941.220000 2848.570000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 1140.280000 2848.570000 1141.480000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 944.070000 2742.660000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 944.070000 2851.400000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 1136.240000 2742.660000 1137.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 1136.240000 2851.400000 1137.440000 ;
+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 740.960000 2745.490000 941.220000 ;
+        RECT 2847.370000 740.960000 2848.570000 941.220000 ;
+        RECT 2748.520000 743.810000 2749.720000 937.180000 ;
+        RECT 2793.520000 743.810000 2794.720000 937.180000 ;
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+      LAYER met3 ;
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+        RECT 2838.520000 865.500000 2839.720000 865.980000 ;
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+        RECT 2838.520000 854.620000 2839.720000 855.100000 ;
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+        RECT 2793.520000 903.580000 2794.720000 904.060000 ;
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+        RECT 2793.520000 892.700000 2794.720000 893.180000 ;
+        RECT 2793.520000 914.460000 2794.720000 914.940000 ;
+        RECT 2748.520000 914.460000 2749.720000 914.940000 ;
+        RECT 2748.520000 909.020000 2749.720000 909.500000 ;
+        RECT 2748.520000 903.580000 2749.720000 904.060000 ;
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+
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 735.720000 2851.400000 736.920000 ;
+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+    PORT
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+        RECT 2741.460000 535.460000 2851.400000 536.660000 ;
+        RECT 2741.460000 343.290000 2851.400000 344.490000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 340.440000 2745.490000 341.640000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 539.500000 2745.490000 540.700000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 340.440000 2848.570000 341.640000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 535.460000 2851.400000 536.660000 ;
+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 2748.520000 172.240000 2749.720000 172.720000 ;
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+        RECT 2793.520000 155.920000 2794.720000 156.400000 ;
+        RECT 2793.520000 161.360000 2794.720000 161.840000 ;
+        RECT 2748.520000 150.480000 2749.720000 150.960000 ;
+        RECT 2748.520000 145.040000 2749.720000 145.520000 ;
+        RECT 2748.520000 155.920000 2749.720000 156.400000 ;
+        RECT 2748.520000 161.360000 2749.720000 161.840000 ;
+        RECT 2744.290000 166.800000 2745.490000 167.280000 ;
+        RECT 2744.290000 172.240000 2745.490000 172.720000 ;
+        RECT 2744.290000 177.680000 2745.490000 178.160000 ;
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+        RECT 2744.290000 155.920000 2745.490000 156.400000 ;
+        RECT 2744.290000 161.360000 2745.490000 161.840000 ;
+        RECT 2741.460000 335.200000 2851.400000 336.400000 ;
+        RECT 2741.460000 143.030000 2851.400000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 140.180000 2745.490000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 339.240000 2745.490000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 140.180000 2848.570000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 339.240000 2848.570000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 143.030000 2742.660000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 143.030000 2851.400000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 335.200000 2742.660000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 335.200000 2851.400000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'S_term_RAM_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 109.920000 2745.490000 140.180000 ;
+        RECT 2847.370000 109.920000 2848.570000 140.180000 ;
+        RECT 2748.520000 112.770000 2749.720000 136.820000 ;
+        RECT 2793.520000 112.770000 2794.720000 136.820000 ;
+        RECT 2838.520000 112.770000 2839.720000 136.820000 ;
+      LAYER met3 ;
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+        RECT 2847.370000 131.100000 2848.570000 131.580000 ;
+        RECT 2838.520000 125.660000 2839.720000 126.140000 ;
+        RECT 2838.520000 131.100000 2839.720000 131.580000 ;
+        RECT 2793.520000 131.100000 2794.720000 131.580000 ;
+        RECT 2793.520000 125.660000 2794.720000 126.140000 ;
+        RECT 2744.290000 125.660000 2745.490000 126.140000 ;
+        RECT 2744.290000 131.100000 2745.490000 131.580000 ;
+        RECT 2748.520000 125.660000 2749.720000 126.140000 ;
+        RECT 2748.520000 131.100000 2749.720000 131.580000 ;
+        RECT 2847.370000 114.780000 2848.570000 115.260000 ;
+        RECT 2847.370000 120.220000 2848.570000 120.700000 ;
+        RECT 2838.520000 114.780000 2839.720000 115.260000 ;
+        RECT 2838.520000 120.220000 2839.720000 120.700000 ;
+        RECT 2793.520000 120.220000 2794.720000 120.700000 ;
+        RECT 2793.520000 114.780000 2794.720000 115.260000 ;
+        RECT 2744.290000 120.220000 2745.490000 120.700000 ;
+        RECT 2748.520000 120.220000 2749.720000 120.700000 ;
+        RECT 2744.290000 114.780000 2745.490000 115.260000 ;
+        RECT 2748.520000 114.780000 2749.720000 115.260000 ;
+        RECT 2741.460000 135.620000 2851.400000 136.820000 ;
+        RECT 2741.460000 112.770000 2851.400000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 109.920000 2745.490000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 138.980000 2745.490000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 109.920000 2848.570000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 138.980000 2848.570000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 112.770000 2742.660000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 112.770000 2851.400000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 135.620000 2742.660000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 135.620000 2851.400000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'N_term_RAM_IO'
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 1141.480000 2745.490000 1171.740000 ;
+        RECT 2847.370000 1141.480000 2848.570000 1171.740000 ;
+        RECT 2748.520000 1144.330000 2749.720000 1168.380000 ;
+        RECT 2793.520000 1144.330000 2794.720000 1168.380000 ;
+        RECT 2838.520000 1144.330000 2839.720000 1168.380000 ;
+      LAYER met3 ;
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+        RECT 2847.370000 1162.660000 2848.570000 1163.140000 ;
+        RECT 2838.520000 1157.220000 2839.720000 1157.700000 ;
+        RECT 2838.520000 1162.660000 2839.720000 1163.140000 ;
+        RECT 2793.520000 1162.660000 2794.720000 1163.140000 ;
+        RECT 2793.520000 1157.220000 2794.720000 1157.700000 ;
+        RECT 2744.290000 1157.220000 2745.490000 1157.700000 ;
+        RECT 2744.290000 1162.660000 2745.490000 1163.140000 ;
+        RECT 2748.520000 1157.220000 2749.720000 1157.700000 ;
+        RECT 2748.520000 1162.660000 2749.720000 1163.140000 ;
+        RECT 2847.370000 1146.340000 2848.570000 1146.820000 ;
+        RECT 2847.370000 1151.780000 2848.570000 1152.260000 ;
+        RECT 2838.520000 1146.340000 2839.720000 1146.820000 ;
+        RECT 2838.520000 1151.780000 2839.720000 1152.260000 ;
+        RECT 2793.520000 1151.780000 2794.720000 1152.260000 ;
+        RECT 2793.520000 1146.340000 2794.720000 1146.820000 ;
+        RECT 2744.290000 1151.780000 2745.490000 1152.260000 ;
+        RECT 2748.520000 1151.780000 2749.720000 1152.260000 ;
+        RECT 2744.290000 1146.340000 2745.490000 1146.820000 ;
+        RECT 2748.520000 1146.340000 2749.720000 1146.820000 ;
+        RECT 2741.460000 1167.180000 2851.400000 1168.380000 ;
+        RECT 2741.460000 1144.330000 2851.400000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 1141.480000 2745.490000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2744.290000 1170.540000 2745.490000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 1141.480000 2848.570000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2847.370000 1170.540000 2848.570000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 1144.330000 2742.660000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 1144.330000 2851.400000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2741.460000 1167.180000 2742.660000 1168.380000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2850.200000 1167.180000 2851.400000 1168.380000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+        RECT 262.220000 944.070000 263.420000 1137.440000 ;
+        RECT 316.230000 941.220000 317.430000 1141.480000 ;
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+        RECT 127.220000 944.070000 128.420000 1137.440000 ;
+        RECT 122.990000 941.220000 124.190000 1141.480000 ;
+      LAYER met3 ;
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+        RECT 316.230000 1131.040000 317.430000 1131.520000 ;
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+        RECT 307.220000 1125.600000 308.420000 1126.080000 ;
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+        RECT 316.230000 1114.720000 317.430000 1115.200000 ;
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+        RECT 316.230000 1092.960000 317.430000 1093.440000 ;
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+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+
+
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+        RECT 122.990000 204.880000 124.190000 205.360000 ;
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+        RECT 122.990000 199.440000 124.190000 199.920000 ;
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+        RECT 172.220000 166.800000 173.420000 167.280000 ;
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+        RECT 217.220000 161.360000 218.420000 161.840000 ;
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+        RECT 172.220000 150.480000 173.420000 150.960000 ;
+        RECT 172.220000 155.920000 173.420000 156.400000 ;
+        RECT 172.220000 161.360000 173.420000 161.840000 ;
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+        RECT 122.990000 188.560000 124.190000 189.040000 ;
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+        RECT 122.990000 183.120000 124.190000 183.600000 ;
+        RECT 127.220000 172.240000 128.420000 172.720000 ;
+        RECT 122.990000 172.240000 124.190000 172.720000 ;
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+        RECT 122.990000 166.800000 124.190000 167.280000 ;
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+        RECT 122.990000 177.680000 124.190000 178.160000 ;
+        RECT 127.220000 161.360000 128.420000 161.840000 ;
+        RECT 122.990000 161.360000 124.190000 161.840000 ;
+        RECT 127.220000 155.920000 128.420000 156.400000 ;
+        RECT 122.990000 155.920000 124.190000 156.400000 ;
+        RECT 127.220000 150.480000 128.420000 150.960000 ;
+        RECT 127.220000 145.040000 128.420000 145.520000 ;
+        RECT 122.990000 150.480000 124.190000 150.960000 ;
+        RECT 122.990000 145.040000 124.190000 145.520000 ;
+        RECT 120.160000 335.200000 320.260000 336.400000 ;
+        RECT 120.160000 143.030000 320.260000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 140.180000 124.190000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 339.240000 124.190000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 140.180000 317.430000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 339.240000 317.430000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 143.030000 121.360000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 143.030000 320.260000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 335.200000 121.360000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 335.200000 320.260000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 109.920000 124.190000 140.180000 ;
+        RECT 316.230000 109.920000 317.430000 140.180000 ;
+        RECT 127.220000 112.770000 128.420000 136.820000 ;
+        RECT 172.220000 112.770000 173.420000 136.820000 ;
+        RECT 217.220000 112.770000 218.420000 136.820000 ;
+        RECT 262.220000 112.770000 263.420000 136.820000 ;
+        RECT 307.220000 112.770000 308.420000 136.820000 ;
+      LAYER met3 ;
+        RECT 316.230000 125.660000 317.430000 126.140000 ;
+        RECT 316.230000 131.100000 317.430000 131.580000 ;
+        RECT 307.220000 131.100000 308.420000 131.580000 ;
+        RECT 307.220000 125.660000 308.420000 126.140000 ;
+        RECT 262.220000 125.660000 263.420000 126.140000 ;
+        RECT 262.220000 131.100000 263.420000 131.580000 ;
+        RECT 172.220000 125.660000 173.420000 126.140000 ;
+        RECT 217.220000 125.660000 218.420000 126.140000 ;
+        RECT 217.220000 131.100000 218.420000 131.580000 ;
+        RECT 172.220000 131.100000 173.420000 131.580000 ;
+        RECT 122.990000 125.660000 124.190000 126.140000 ;
+        RECT 127.220000 125.660000 128.420000 126.140000 ;
+        RECT 127.220000 131.100000 128.420000 131.580000 ;
+        RECT 122.990000 131.100000 124.190000 131.580000 ;
+        RECT 316.230000 114.780000 317.430000 115.260000 ;
+        RECT 316.230000 120.220000 317.430000 120.700000 ;
+        RECT 307.220000 120.220000 308.420000 120.700000 ;
+        RECT 307.220000 114.780000 308.420000 115.260000 ;
+        RECT 262.220000 114.780000 263.420000 115.260000 ;
+        RECT 262.220000 120.220000 263.420000 120.700000 ;
+        RECT 172.220000 114.780000 173.420000 115.260000 ;
+        RECT 217.220000 114.780000 218.420000 115.260000 ;
+        RECT 217.220000 120.220000 218.420000 120.700000 ;
+        RECT 172.220000 120.220000 173.420000 120.700000 ;
+        RECT 122.990000 120.220000 124.190000 120.700000 ;
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+        RECT 122.990000 114.780000 124.190000 115.260000 ;
+        RECT 127.220000 114.780000 128.420000 115.260000 ;
+        RECT 120.160000 135.620000 320.260000 136.820000 ;
+        RECT 120.160000 112.770000 320.260000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 109.920000 124.190000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 138.980000 124.190000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 109.920000 317.430000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 138.980000 317.430000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 112.770000 121.360000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 112.770000 320.260000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 135.620000 121.360000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 135.620000 320.260000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 1141.480000 124.190000 1171.740000 ;
+        RECT 316.230000 1141.480000 317.430000 1171.740000 ;
+        RECT 127.220000 1144.330000 128.420000 1168.380000 ;
+        RECT 172.220000 1144.330000 173.420000 1168.380000 ;
+        RECT 217.220000 1144.330000 218.420000 1168.380000 ;
+        RECT 262.220000 1144.330000 263.420000 1168.380000 ;
+        RECT 307.220000 1144.330000 308.420000 1168.380000 ;
+      LAYER met3 ;
+        RECT 316.230000 1157.220000 317.430000 1157.700000 ;
+        RECT 316.230000 1162.660000 317.430000 1163.140000 ;
+        RECT 307.220000 1162.660000 308.420000 1163.140000 ;
+        RECT 307.220000 1157.220000 308.420000 1157.700000 ;
+        RECT 262.220000 1157.220000 263.420000 1157.700000 ;
+        RECT 262.220000 1162.660000 263.420000 1163.140000 ;
+        RECT 172.220000 1157.220000 173.420000 1157.700000 ;
+        RECT 217.220000 1157.220000 218.420000 1157.700000 ;
+        RECT 217.220000 1162.660000 218.420000 1163.140000 ;
+        RECT 172.220000 1162.660000 173.420000 1163.140000 ;
+        RECT 122.990000 1157.220000 124.190000 1157.700000 ;
+        RECT 127.220000 1157.220000 128.420000 1157.700000 ;
+        RECT 127.220000 1162.660000 128.420000 1163.140000 ;
+        RECT 122.990000 1162.660000 124.190000 1163.140000 ;
+        RECT 316.230000 1146.340000 317.430000 1146.820000 ;
+        RECT 316.230000 1151.780000 317.430000 1152.260000 ;
+        RECT 307.220000 1151.780000 308.420000 1152.260000 ;
+        RECT 307.220000 1146.340000 308.420000 1146.820000 ;
+        RECT 262.220000 1146.340000 263.420000 1146.820000 ;
+        RECT 262.220000 1151.780000 263.420000 1152.260000 ;
+        RECT 172.220000 1146.340000 173.420000 1146.820000 ;
+        RECT 217.220000 1146.340000 218.420000 1146.820000 ;
+        RECT 217.220000 1151.780000 218.420000 1152.260000 ;
+        RECT 172.220000 1151.780000 173.420000 1152.260000 ;
+        RECT 122.990000 1151.780000 124.190000 1152.260000 ;
+        RECT 127.220000 1151.780000 128.420000 1152.260000 ;
+        RECT 122.990000 1146.340000 124.190000 1146.820000 ;
+        RECT 127.220000 1146.340000 128.420000 1146.820000 ;
+        RECT 120.160000 1167.180000 320.260000 1168.380000 ;
+        RECT 120.160000 1144.330000 320.260000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 1141.480000 124.190000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 122.990000 1170.540000 124.190000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 1141.480000 317.430000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 316.230000 1170.540000 317.430000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 1144.330000 121.360000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 1144.330000 320.260000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 120.160000 1167.180000 121.360000 1168.380000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 319.060000 1167.180000 320.260000 1168.380000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'RegFile'
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 941.220000 517.530000 1141.480000 ;
+        RECT 462.320000 944.070000 463.520000 1137.440000 ;
+        RECT 507.320000 944.070000 508.520000 1137.440000 ;
+        RECT 323.090000 941.220000 324.290000 1141.480000 ;
+        RECT 327.320000 944.070000 328.520000 1137.440000 ;
+        RECT 372.320000 944.070000 373.520000 1137.440000 ;
+        RECT 417.320000 944.070000 418.520000 1137.440000 ;
+      LAYER met3 ;
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+        RECT 516.330000 1131.040000 517.530000 1131.520000 ;
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+        RECT 516.330000 1125.600000 517.530000 1126.080000 ;
+        RECT 507.320000 1120.160000 508.520000 1120.640000 ;
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+        RECT 516.330000 1109.280000 517.530000 1109.760000 ;
+        RECT 516.330000 1114.720000 517.530000 1115.200000 ;
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+        RECT 516.330000 1092.960000 517.530000 1093.440000 ;
+        RECT 516.330000 1098.400000 517.530000 1098.880000 ;
+        RECT 507.320000 1103.840000 508.520000 1104.320000 ;
+        RECT 516.330000 1103.840000 517.530000 1104.320000 ;
+        RECT 462.320000 1120.160000 463.520000 1120.640000 ;
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+        RECT 516.330000 1049.440000 517.530000 1049.920000 ;
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+        RECT 462.320000 1087.520000 463.520000 1088.000000 ;
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+        RECT 462.320000 1054.880000 463.520000 1055.360000 ;
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+        RECT 462.320000 1065.760000 463.520000 1066.240000 ;
+        RECT 417.320000 1120.160000 418.520000 1120.640000 ;
+        RECT 417.320000 1125.600000 418.520000 1126.080000 ;
+        RECT 417.320000 1131.040000 418.520000 1131.520000 ;
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+        RECT 372.320000 1125.600000 373.520000 1126.080000 ;
+        RECT 372.320000 1131.040000 373.520000 1131.520000 ;
+        RECT 417.320000 1092.960000 418.520000 1093.440000 ;
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+        RECT 417.320000 1114.720000 418.520000 1115.200000 ;
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+        RECT 372.320000 1103.840000 373.520000 1104.320000 ;
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+        RECT 372.320000 1114.720000 373.520000 1115.200000 ;
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+        RECT 323.090000 1109.280000 324.290000 1109.760000 ;
+        RECT 323.090000 1114.720000 324.290000 1115.200000 ;
+        RECT 327.320000 1092.960000 328.520000 1093.440000 ;
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+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
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+    END
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 735.720000 520.360000 736.920000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+    PORT
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+# end of P/G pin shape extracted from block 'RegFile'
+
+
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+        RECT 417.320000 155.920000 418.520000 156.400000 ;
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+        RECT 372.320000 145.040000 373.520000 145.520000 ;
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+        RECT 372.320000 155.920000 373.520000 156.400000 ;
+        RECT 372.320000 161.360000 373.520000 161.840000 ;
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+        RECT 323.090000 183.120000 324.290000 183.600000 ;
+        RECT 323.090000 188.560000 324.290000 189.040000 ;
+        RECT 327.320000 166.800000 328.520000 167.280000 ;
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+        RECT 323.090000 166.800000 324.290000 167.280000 ;
+        RECT 323.090000 172.240000 324.290000 172.720000 ;
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+        RECT 323.090000 177.680000 324.290000 178.160000 ;
+        RECT 327.320000 161.360000 328.520000 161.840000 ;
+        RECT 323.090000 161.360000 324.290000 161.840000 ;
+        RECT 327.320000 155.920000 328.520000 156.400000 ;
+        RECT 323.090000 155.920000 324.290000 156.400000 ;
+        RECT 327.320000 145.040000 328.520000 145.520000 ;
+        RECT 327.320000 150.480000 328.520000 150.960000 ;
+        RECT 323.090000 145.040000 324.290000 145.520000 ;
+        RECT 323.090000 150.480000 324.290000 150.960000 ;
+        RECT 320.260000 335.200000 520.360000 336.400000 ;
+        RECT 320.260000 143.030000 520.360000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 140.180000 324.290000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 339.240000 324.290000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 140.180000 517.530000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 339.240000 517.530000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 143.030000 321.460000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 143.030000 520.360000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 335.200000 321.460000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 335.200000 520.360000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 109.920000 324.290000 140.180000 ;
+        RECT 516.330000 109.920000 517.530000 140.180000 ;
+        RECT 327.320000 112.770000 328.520000 136.820000 ;
+        RECT 372.320000 112.770000 373.520000 136.820000 ;
+        RECT 417.320000 112.770000 418.520000 136.820000 ;
+        RECT 462.320000 112.770000 463.520000 136.820000 ;
+        RECT 507.320000 112.770000 508.520000 136.820000 ;
+      LAYER met3 ;
+        RECT 516.330000 125.660000 517.530000 126.140000 ;
+        RECT 516.330000 131.100000 517.530000 131.580000 ;
+        RECT 507.320000 131.100000 508.520000 131.580000 ;
+        RECT 507.320000 125.660000 508.520000 126.140000 ;
+        RECT 462.320000 125.660000 463.520000 126.140000 ;
+        RECT 462.320000 131.100000 463.520000 131.580000 ;
+        RECT 372.320000 125.660000 373.520000 126.140000 ;
+        RECT 417.320000 125.660000 418.520000 126.140000 ;
+        RECT 417.320000 131.100000 418.520000 131.580000 ;
+        RECT 372.320000 131.100000 373.520000 131.580000 ;
+        RECT 323.090000 125.660000 324.290000 126.140000 ;
+        RECT 327.320000 125.660000 328.520000 126.140000 ;
+        RECT 327.320000 131.100000 328.520000 131.580000 ;
+        RECT 323.090000 131.100000 324.290000 131.580000 ;
+        RECT 516.330000 114.780000 517.530000 115.260000 ;
+        RECT 516.330000 120.220000 517.530000 120.700000 ;
+        RECT 507.320000 120.220000 508.520000 120.700000 ;
+        RECT 507.320000 114.780000 508.520000 115.260000 ;
+        RECT 462.320000 114.780000 463.520000 115.260000 ;
+        RECT 462.320000 120.220000 463.520000 120.700000 ;
+        RECT 372.320000 114.780000 373.520000 115.260000 ;
+        RECT 417.320000 114.780000 418.520000 115.260000 ;
+        RECT 417.320000 120.220000 418.520000 120.700000 ;
+        RECT 372.320000 120.220000 373.520000 120.700000 ;
+        RECT 323.090000 120.220000 324.290000 120.700000 ;
+        RECT 327.320000 120.220000 328.520000 120.700000 ;
+        RECT 323.090000 114.780000 324.290000 115.260000 ;
+        RECT 327.320000 114.780000 328.520000 115.260000 ;
+        RECT 320.260000 135.620000 520.360000 136.820000 ;
+        RECT 320.260000 112.770000 520.360000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 109.920000 324.290000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 138.980000 324.290000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 109.920000 517.530000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 138.980000 517.530000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 112.770000 321.460000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 112.770000 520.360000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 135.620000 321.460000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 135.620000 520.360000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 1141.480000 324.290000 1171.740000 ;
+        RECT 516.330000 1141.480000 517.530000 1171.740000 ;
+        RECT 327.320000 1144.330000 328.520000 1168.380000 ;
+        RECT 372.320000 1144.330000 373.520000 1168.380000 ;
+        RECT 417.320000 1144.330000 418.520000 1168.380000 ;
+        RECT 462.320000 1144.330000 463.520000 1168.380000 ;
+        RECT 507.320000 1144.330000 508.520000 1168.380000 ;
+      LAYER met3 ;
+        RECT 516.330000 1157.220000 517.530000 1157.700000 ;
+        RECT 516.330000 1162.660000 517.530000 1163.140000 ;
+        RECT 507.320000 1162.660000 508.520000 1163.140000 ;
+        RECT 507.320000 1157.220000 508.520000 1157.700000 ;
+        RECT 462.320000 1157.220000 463.520000 1157.700000 ;
+        RECT 462.320000 1162.660000 463.520000 1163.140000 ;
+        RECT 372.320000 1157.220000 373.520000 1157.700000 ;
+        RECT 417.320000 1157.220000 418.520000 1157.700000 ;
+        RECT 417.320000 1162.660000 418.520000 1163.140000 ;
+        RECT 372.320000 1162.660000 373.520000 1163.140000 ;
+        RECT 323.090000 1157.220000 324.290000 1157.700000 ;
+        RECT 327.320000 1157.220000 328.520000 1157.700000 ;
+        RECT 327.320000 1162.660000 328.520000 1163.140000 ;
+        RECT 323.090000 1162.660000 324.290000 1163.140000 ;
+        RECT 516.330000 1146.340000 517.530000 1146.820000 ;
+        RECT 516.330000 1151.780000 517.530000 1152.260000 ;
+        RECT 507.320000 1151.780000 508.520000 1152.260000 ;
+        RECT 507.320000 1146.340000 508.520000 1146.820000 ;
+        RECT 462.320000 1146.340000 463.520000 1146.820000 ;
+        RECT 462.320000 1151.780000 463.520000 1152.260000 ;
+        RECT 372.320000 1146.340000 373.520000 1146.820000 ;
+        RECT 417.320000 1146.340000 418.520000 1146.820000 ;
+        RECT 417.320000 1151.780000 418.520000 1152.260000 ;
+        RECT 372.320000 1151.780000 373.520000 1152.260000 ;
+        RECT 323.090000 1151.780000 324.290000 1152.260000 ;
+        RECT 327.320000 1151.780000 328.520000 1152.260000 ;
+        RECT 323.090000 1146.340000 324.290000 1146.820000 ;
+        RECT 327.320000 1146.340000 328.520000 1146.820000 ;
+        RECT 320.260000 1167.180000 520.360000 1168.380000 ;
+        RECT 320.260000 1144.330000 520.360000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 1141.480000 324.290000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 323.090000 1170.540000 324.290000 1171.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 1141.480000 517.530000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 516.330000 1170.540000 517.530000 1171.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 1144.330000 321.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 1144.330000 520.360000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 320.260000 1167.180000 321.460000 1168.380000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 519.160000 1167.180000 520.360000 1168.380000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single2'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 707.420000 944.070000 708.620000 1137.440000 ;
+        RECT 662.420000 944.070000 663.620000 1137.440000 ;
+        RECT 716.430000 941.220000 717.630000 1141.480000 ;
+        RECT 617.420000 944.070000 618.620000 1137.440000 ;
+        RECT 572.420000 944.070000 573.620000 1137.440000 ;
+        RECT 527.420000 944.070000 528.620000 1137.440000 ;
+        RECT 523.190000 941.220000 524.390000 1141.480000 ;
+      LAYER met3 ;
+        RECT 707.420000 1131.040000 708.620000 1131.520000 ;
+        RECT 716.430000 1131.040000 717.630000 1131.520000 ;
+        RECT 716.430000 1120.160000 717.630000 1120.640000 ;
+        RECT 716.430000 1125.600000 717.630000 1126.080000 ;
+        RECT 707.420000 1125.600000 708.620000 1126.080000 ;
+        RECT 707.420000 1120.160000 708.620000 1120.640000 ;
+        RECT 707.420000 1114.720000 708.620000 1115.200000 ;
+        RECT 707.420000 1109.280000 708.620000 1109.760000 ;
+        RECT 716.430000 1114.720000 717.630000 1115.200000 ;
+        RECT 716.430000 1109.280000 717.630000 1109.760000 ;
+        RECT 707.420000 1092.960000 708.620000 1093.440000 ;
+        RECT 707.420000 1098.400000 708.620000 1098.880000 ;
+        RECT 716.430000 1098.400000 717.630000 1098.880000 ;
+        RECT 716.430000 1092.960000 717.630000 1093.440000 ;
+        RECT 707.420000 1103.840000 708.620000 1104.320000 ;
+        RECT 716.430000 1103.840000 717.630000 1104.320000 ;
+        RECT 662.420000 1131.040000 663.620000 1131.520000 ;
+        RECT 662.420000 1125.600000 663.620000 1126.080000 ;
+        RECT 662.420000 1120.160000 663.620000 1120.640000 ;
+        RECT 662.420000 1114.720000 663.620000 1115.200000 ;
+        RECT 662.420000 1092.960000 663.620000 1093.440000 ;
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+        RECT 662.420000 1103.840000 663.620000 1104.320000 ;
+        RECT 662.420000 1109.280000 663.620000 1109.760000 ;
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+        RECT 716.430000 1087.520000 717.630000 1088.000000 ;
+        RECT 707.420000 1087.520000 708.620000 1088.000000 ;
+        RECT 707.420000 1082.080000 708.620000 1082.560000 ;
+        RECT 707.420000 1076.640000 708.620000 1077.120000 ;
+        RECT 707.420000 1071.200000 708.620000 1071.680000 ;
+        RECT 716.430000 1076.640000 717.630000 1077.120000 ;
+        RECT 716.430000 1071.200000 717.630000 1071.680000 ;
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+        RECT 716.430000 1060.320000 717.630000 1060.800000 ;
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+        RECT 707.420000 1060.320000 708.620000 1060.800000 ;
+        RECT 707.420000 1054.880000 708.620000 1055.360000 ;
+        RECT 707.420000 1065.760000 708.620000 1066.240000 ;
+        RECT 707.420000 1049.440000 708.620000 1049.920000 ;
+        RECT 707.420000 1044.000000 708.620000 1044.480000 ;
+        RECT 716.430000 1049.440000 717.630000 1049.920000 ;
+        RECT 716.430000 1044.000000 717.630000 1044.480000 ;
+        RECT 662.420000 1087.520000 663.620000 1088.000000 ;
+        RECT 662.420000 1082.080000 663.620000 1082.560000 ;
+        RECT 662.420000 1076.640000 663.620000 1077.120000 ;
+        RECT 662.420000 1071.200000 663.620000 1071.680000 ;
+        RECT 662.420000 1060.320000 663.620000 1060.800000 ;
+        RECT 662.420000 1054.880000 663.620000 1055.360000 ;
+        RECT 662.420000 1049.440000 663.620000 1049.920000 ;
+        RECT 662.420000 1044.000000 663.620000 1044.480000 ;
+        RECT 662.420000 1065.760000 663.620000 1066.240000 ;
+        RECT 617.420000 1131.040000 618.620000 1131.520000 ;
+        RECT 617.420000 1125.600000 618.620000 1126.080000 ;
+        RECT 617.420000 1120.160000 618.620000 1120.640000 ;
+        RECT 572.420000 1131.040000 573.620000 1131.520000 ;
+        RECT 572.420000 1125.600000 573.620000 1126.080000 ;
+        RECT 572.420000 1120.160000 573.620000 1120.640000 ;
+        RECT 617.420000 1103.840000 618.620000 1104.320000 ;
+        RECT 617.420000 1098.400000 618.620000 1098.880000 ;
+        RECT 617.420000 1092.960000 618.620000 1093.440000 ;
+        RECT 617.420000 1109.280000 618.620000 1109.760000 ;
+        RECT 617.420000 1114.720000 618.620000 1115.200000 ;
+        RECT 572.420000 1114.720000 573.620000 1115.200000 ;
+        RECT 572.420000 1103.840000 573.620000 1104.320000 ;
+        RECT 572.420000 1098.400000 573.620000 1098.880000 ;
+        RECT 572.420000 1092.960000 573.620000 1093.440000 ;
+        RECT 572.420000 1109.280000 573.620000 1109.760000 ;
+        RECT 527.420000 1131.040000 528.620000 1131.520000 ;
+        RECT 523.190000 1131.040000 524.390000 1131.520000 ;
+        RECT 523.190000 1125.600000 524.390000 1126.080000 ;
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+        RECT 520.360000 143.030000 720.460000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 140.180000 717.630000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 339.240000 717.630000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 335.200000 720.460000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 520.360000 112.770000 720.460000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 523.190000 109.920000 524.390000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 523.190000 138.980000 524.390000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 109.920000 717.630000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 138.980000 717.630000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 112.770000 720.460000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 520.360000 135.620000 521.560000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 135.620000 720.460000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 716.430000 2903.560000 717.630000 3103.820000 ;
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+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2902.360000 684.470000 2903.560000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2703.300000 717.630000 2704.500000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2902.360000 717.630000 2903.560000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2898.320000 720.460000 2899.520000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
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+        RECT 680.440000 2465.890000 720.460000 2467.090000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2662.100000 684.470000 2663.300000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2463.040000 717.630000 2464.240000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2662.100000 717.630000 2663.300000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2465.890000 720.460000 2467.090000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 2658.060000 681.640000 2659.260000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2658.060000 720.460000 2659.260000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2262.780000 684.470000 2463.040000 ;
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+        RECT 680.440000 2265.630000 720.460000 2266.830000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2262.780000 684.470000 2263.980000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2461.840000 684.470000 2463.040000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2262.780000 717.630000 2263.980000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2461.840000 717.630000 2463.040000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 2265.630000 681.640000 2266.830000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2265.630000 720.460000 2266.830000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 2457.800000 681.640000 2459.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2457.800000 720.460000 2459.000000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2022.520000 684.470000 2222.780000 ;
+        RECT 716.430000 2022.520000 717.630000 2222.780000 ;
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+      LAYER met3 ;
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+        RECT 683.270000 2125.300000 684.470000 2125.780000 ;
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+        RECT 687.500000 2038.260000 688.700000 2038.740000 ;
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+        RECT 683.270000 2032.820000 684.470000 2033.300000 ;
+        RECT 680.440000 2217.540000 720.460000 2218.740000 ;
+        RECT 680.440000 2025.370000 720.460000 2026.570000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2022.520000 684.470000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 2221.580000 684.470000 2222.780000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2022.520000 717.630000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 2221.580000 717.630000 2222.780000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 2025.370000 681.640000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2025.370000 720.460000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 2217.540000 681.640000 2218.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 2217.540000 720.460000 2218.740000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 1822.260000 684.470000 2022.520000 ;
+        RECT 716.430000 1822.260000 717.630000 2022.520000 ;
+        RECT 687.500000 1825.110000 688.700000 2018.480000 ;
+      LAYER met3 ;
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+        RECT 716.430000 2006.640000 717.630000 2007.120000 ;
+        RECT 716.430000 2001.200000 717.630000 2001.680000 ;
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+        RECT 716.430000 1974.000000 717.630000 1974.480000 ;
+        RECT 716.430000 1979.440000 717.630000 1979.920000 ;
+        RECT 716.430000 1984.880000 717.630000 1985.360000 ;
+        RECT 716.430000 1963.120000 717.630000 1963.600000 ;
+        RECT 716.430000 1968.560000 717.630000 1969.040000 ;
+        RECT 716.430000 1952.240000 717.630000 1952.720000 ;
+        RECT 716.430000 1957.680000 717.630000 1958.160000 ;
+        RECT 716.430000 1935.920000 717.630000 1936.400000 ;
+        RECT 716.430000 1941.360000 717.630000 1941.840000 ;
+        RECT 716.430000 1946.800000 717.630000 1947.280000 ;
+        RECT 716.430000 1925.040000 717.630000 1925.520000 ;
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+        RECT 683.270000 2001.200000 684.470000 2001.680000 ;
+        RECT 683.270000 2006.640000 684.470000 2007.120000 ;
+        RECT 687.500000 2001.200000 688.700000 2001.680000 ;
+        RECT 687.500000 2006.640000 688.700000 2007.120000 ;
+        RECT 687.500000 1990.320000 688.700000 1990.800000 ;
+        RECT 687.500000 1995.760000 688.700000 1996.240000 ;
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+        RECT 683.270000 1995.760000 684.470000 1996.240000 ;
+        RECT 687.500000 1974.000000 688.700000 1974.480000 ;
+        RECT 687.500000 1979.440000 688.700000 1979.920000 ;
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+        RECT 683.270000 1979.440000 684.470000 1979.920000 ;
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+    END
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+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
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+    END
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+    END
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+    PORT
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+    PORT
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+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO'
+    PORT
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+        RECT 683.270000 1402.920000 684.470000 1403.400000 ;
+        RECT 687.500000 1397.480000 688.700000 1397.960000 ;
+        RECT 687.500000 1402.920000 688.700000 1403.400000 ;
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+        RECT 687.500000 1392.040000 688.700000 1392.520000 ;
+        RECT 683.270000 1386.600000 684.470000 1387.080000 ;
+        RECT 683.270000 1392.040000 684.470000 1392.520000 ;
+        RECT 680.440000 1576.760000 720.460000 1577.960000 ;
+        RECT 680.440000 1384.590000 720.460000 1385.790000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 1381.740000 684.470000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 683.270000 1580.800000 684.470000 1582.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 1381.740000 717.630000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 1580.800000 717.630000 1582.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1384.590000 681.640000 1385.790000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1384.590000 720.460000 1385.790000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 680.440000 1576.760000 681.640000 1577.960000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1576.760000 720.460000 1577.960000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO'
+
+
+# P/G pin shape extracted from block 'W_CPU_IO_bot'
+    PORT
+      LAYER met4 ;
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+        RECT 662.420000 1144.330000 663.620000 1337.700000 ;
+        RECT 716.430000 1141.480000 717.630000 1341.740000 ;
+        RECT 617.420000 1144.330000 618.620000 1337.700000 ;
+        RECT 572.420000 1144.330000 573.620000 1337.700000 ;
+        RECT 527.420000 1144.330000 528.620000 1337.700000 ;
+        RECT 523.190000 1141.480000 524.390000 1341.740000 ;
+      LAYER met3 ;
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+        RECT 707.420000 1325.860000 708.620000 1326.340000 ;
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+        RECT 662.420000 1271.460000 663.620000 1271.940000 ;
+        RECT 662.420000 1260.580000 663.620000 1261.060000 ;
+        RECT 662.420000 1255.140000 663.620000 1255.620000 ;
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+        RECT 662.420000 1244.260000 663.620000 1244.740000 ;
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+        RECT 527.420000 1325.860000 528.620000 1326.340000 ;
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+        RECT 523.190000 1309.540000 524.390000 1310.020000 ;
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+        RECT 527.420000 1260.580000 528.620000 1261.060000 ;
+        RECT 523.190000 1266.020000 524.390000 1266.500000 ;
+        RECT 523.190000 1260.580000 524.390000 1261.060000 ;
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+        RECT 527.420000 1249.700000 528.620000 1250.180000 ;
+        RECT 523.190000 1249.700000 524.390000 1250.180000 ;
+        RECT 527.420000 1244.260000 528.620000 1244.740000 ;
+        RECT 523.190000 1244.260000 524.390000 1244.740000 ;
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+        RECT 707.420000 1195.300000 708.620000 1195.780000 ;
+        RECT 707.420000 1200.740000 708.620000 1201.220000 ;
+        RECT 662.420000 1238.820000 663.620000 1239.300000 ;
+        RECT 662.420000 1233.380000 663.620000 1233.860000 ;
+        RECT 662.420000 1227.940000 663.620000 1228.420000 ;
+        RECT 662.420000 1222.500000 663.620000 1222.980000 ;
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+        RECT 662.420000 1211.620000 663.620000 1212.100000 ;
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+        RECT 716.430000 1168.100000 717.630000 1168.580000 ;
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+        RECT 716.430000 1178.980000 717.630000 1179.460000 ;
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+        RECT 662.420000 1168.100000 663.620000 1168.580000 ;
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+        RECT 617.420000 1222.500000 618.620000 1222.980000 ;
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+        RECT 572.420000 1238.820000 573.620000 1239.300000 ;
+        RECT 572.420000 1233.380000 573.620000 1233.860000 ;
+        RECT 572.420000 1227.940000 573.620000 1228.420000 ;
+        RECT 572.420000 1222.500000 573.620000 1222.980000 ;
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+        RECT 617.420000 1211.620000 618.620000 1212.100000 ;
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+        RECT 523.190000 1173.540000 524.390000 1174.020000 ;
+        RECT 527.420000 1168.100000 528.620000 1168.580000 ;
+        RECT 523.190000 1168.100000 524.390000 1168.580000 ;
+        RECT 527.420000 1178.980000 528.620000 1179.460000 ;
+        RECT 523.190000 1178.980000 524.390000 1179.460000 ;
+        RECT 527.420000 1162.660000 528.620000 1163.140000 ;
+        RECT 523.190000 1162.660000 524.390000 1163.140000 ;
+        RECT 527.420000 1157.220000 528.620000 1157.700000 ;
+        RECT 523.190000 1157.220000 524.390000 1157.700000 ;
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+        RECT 523.190000 1151.780000 524.390000 1152.260000 ;
+        RECT 523.190000 1146.340000 524.390000 1146.820000 ;
+        RECT 520.360000 1336.500000 720.460000 1337.700000 ;
+        RECT 520.360000 1144.330000 720.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 523.190000 1141.480000 524.390000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 523.190000 1340.540000 524.390000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 1141.480000 717.630000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 716.430000 1340.540000 717.630000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 520.360000 1144.330000 521.560000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1144.330000 720.460000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 520.360000 1336.500000 521.560000 1337.700000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 719.260000 1336.500000 720.460000 1337.700000 ;
+    END
+# end of P/G pin shape extracted from block 'W_CPU_IO_bot'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+    PORT
+      LAYER met4 ;
+        RECT 728.290000 3103.820000 729.490000 3134.080000 ;
+        RECT 921.530000 3103.820000 922.730000 3134.080000 ;
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+        RECT 777.520000 3106.670000 778.720000 3130.720000 ;
+        RECT 822.520000 3106.670000 823.720000 3130.720000 ;
+        RECT 867.520000 3106.670000 868.720000 3130.720000 ;
+        RECT 912.520000 3106.670000 913.720000 3130.720000 ;
+      LAYER met3 ;
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+        RECT 912.520000 3119.560000 913.720000 3120.040000 ;
+        RECT 867.520000 3119.560000 868.720000 3120.040000 ;
+        RECT 867.520000 3125.000000 868.720000 3125.480000 ;
+        RECT 777.520000 3119.560000 778.720000 3120.040000 ;
+        RECT 822.520000 3119.560000 823.720000 3120.040000 ;
+        RECT 822.520000 3125.000000 823.720000 3125.480000 ;
+        RECT 777.520000 3125.000000 778.720000 3125.480000 ;
+        RECT 728.290000 3119.560000 729.490000 3120.040000 ;
+        RECT 732.520000 3119.560000 733.720000 3120.040000 ;
+        RECT 732.520000 3125.000000 733.720000 3125.480000 ;
+        RECT 728.290000 3125.000000 729.490000 3125.480000 ;
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+        RECT 912.520000 3108.680000 913.720000 3109.160000 ;
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+    END
+    PORT
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+    END
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+    END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+        RECT 725.460000 143.030000 925.560000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 921.530000 539.500000 922.730000 540.700000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 535.970000 925.560000 537.170000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+    PORT
+      LAYER met4 ;
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+        RECT 725.460000 112.770000 925.560000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 135.620000 925.560000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
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+# end of P/G pin shape extracted from block 'DSP'
+
+
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+    END
+    PORT
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+        RECT 725.460000 944.070000 925.560000 945.270000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 728.290000 1340.540000 729.490000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 921.530000 941.220000 922.730000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 921.530000 1340.540000 922.730000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 924.360000 1337.010000 925.560000 1338.210000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 930.560000 3129.520000 1130.660000 3130.720000 ;
+        RECT 930.560000 3106.670000 1130.660000 3107.870000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 3103.820000 934.590000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 3132.880000 934.590000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 3103.820000 1127.830000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 3132.880000 1127.830000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 3106.670000 931.760000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 3106.670000 1130.660000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 3129.520000 931.760000 3130.720000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 3129.520000 1130.660000 3130.720000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1117.620000 944.070000 1118.820000 1137.440000 ;
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+        RECT 937.620000 944.070000 938.820000 1137.440000 ;
+        RECT 933.390000 941.220000 934.590000 1141.480000 ;
+      LAYER met3 ;
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+        RECT 1126.630000 1131.040000 1127.830000 1131.520000 ;
+        RECT 1126.630000 1120.160000 1127.830000 1120.640000 ;
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+        RECT 1117.620000 1125.600000 1118.820000 1126.080000 ;
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+        RECT 1126.630000 1098.400000 1127.830000 1098.880000 ;
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+        RECT 1126.630000 1103.840000 1127.830000 1104.320000 ;
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
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+        RECT 1126.630000 140.180000 1127.830000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 339.240000 1127.830000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 335.200000 1130.660000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 930.560000 135.620000 1130.660000 136.820000 ;
+        RECT 930.560000 112.770000 1130.660000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 138.980000 934.590000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 109.920000 1127.830000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 138.980000 1127.830000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 112.770000 1130.660000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 135.620000 931.760000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 135.620000 1130.660000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+        RECT 937.620000 2906.410000 938.820000 3099.780000 ;
+        RECT 933.390000 2903.560000 934.590000 3103.820000 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 3098.580000 1130.660000 3099.780000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 2898.320000 1130.660000 2899.520000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    PORT
+      LAYER met4 ;
+        RECT 933.390000 1381.740000 934.590000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 1580.800000 934.590000 1582.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 1381.740000 1127.830000 1382.940000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 1580.800000 1127.830000 1582.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1384.590000 931.760000 1385.790000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1384.590000 1130.660000 1385.790000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1576.760000 931.760000 1577.960000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1576.760000 1130.660000 1577.960000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1117.620000 1144.330000 1118.820000 1337.700000 ;
+        RECT 1072.620000 1144.330000 1073.820000 1337.700000 ;
+        RECT 1126.630000 1141.480000 1127.830000 1341.740000 ;
+        RECT 1027.620000 1144.330000 1028.820000 1337.700000 ;
+        RECT 982.620000 1144.330000 983.820000 1337.700000 ;
+        RECT 937.620000 1144.330000 938.820000 1337.700000 ;
+        RECT 933.390000 1141.480000 934.590000 1341.740000 ;
+      LAYER met3 ;
+        RECT 1117.620000 1331.300000 1118.820000 1331.780000 ;
+        RECT 1126.630000 1331.300000 1127.830000 1331.780000 ;
+        RECT 1126.630000 1320.420000 1127.830000 1320.900000 ;
+        RECT 1126.630000 1325.860000 1127.830000 1326.340000 ;
+        RECT 1117.620000 1325.860000 1118.820000 1326.340000 ;
+        RECT 1117.620000 1320.420000 1118.820000 1320.900000 ;
+        RECT 1117.620000 1314.980000 1118.820000 1315.460000 ;
+        RECT 1117.620000 1309.540000 1118.820000 1310.020000 ;
+        RECT 1126.630000 1314.980000 1127.830000 1315.460000 ;
+        RECT 1126.630000 1309.540000 1127.830000 1310.020000 ;
+        RECT 1117.620000 1293.220000 1118.820000 1293.700000 ;
+        RECT 1117.620000 1298.660000 1118.820000 1299.140000 ;
+        RECT 1126.630000 1298.660000 1127.830000 1299.140000 ;
+        RECT 1126.630000 1293.220000 1127.830000 1293.700000 ;
+        RECT 1117.620000 1304.100000 1118.820000 1304.580000 ;
+        RECT 1126.630000 1304.100000 1127.830000 1304.580000 ;
+        RECT 1072.620000 1331.300000 1073.820000 1331.780000 ;
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+        RECT 1072.620000 1320.420000 1073.820000 1320.900000 ;
+        RECT 1072.620000 1314.980000 1073.820000 1315.460000 ;
+        RECT 1072.620000 1293.220000 1073.820000 1293.700000 ;
+        RECT 1072.620000 1298.660000 1073.820000 1299.140000 ;
+        RECT 1072.620000 1304.100000 1073.820000 1304.580000 ;
+        RECT 1072.620000 1309.540000 1073.820000 1310.020000 ;
+        RECT 1126.630000 1282.340000 1127.830000 1282.820000 ;
+        RECT 1126.630000 1287.780000 1127.830000 1288.260000 ;
+        RECT 1117.620000 1287.780000 1118.820000 1288.260000 ;
+        RECT 1117.620000 1282.340000 1118.820000 1282.820000 ;
+        RECT 1117.620000 1276.900000 1118.820000 1277.380000 ;
+        RECT 1117.620000 1271.460000 1118.820000 1271.940000 ;
+        RECT 1126.630000 1276.900000 1127.830000 1277.380000 ;
+        RECT 1126.630000 1271.460000 1127.830000 1271.940000 ;
+        RECT 1126.630000 1255.140000 1127.830000 1255.620000 ;
+        RECT 1126.630000 1260.580000 1127.830000 1261.060000 ;
+        RECT 1126.630000 1266.020000 1127.830000 1266.500000 ;
+        RECT 1117.620000 1260.580000 1118.820000 1261.060000 ;
+        RECT 1117.620000 1255.140000 1118.820000 1255.620000 ;
+        RECT 1117.620000 1266.020000 1118.820000 1266.500000 ;
+        RECT 1117.620000 1249.700000 1118.820000 1250.180000 ;
+        RECT 1117.620000 1244.260000 1118.820000 1244.740000 ;
+        RECT 1126.630000 1249.700000 1127.830000 1250.180000 ;
+        RECT 1126.630000 1244.260000 1127.830000 1244.740000 ;
+        RECT 1072.620000 1287.780000 1073.820000 1288.260000 ;
+        RECT 1072.620000 1282.340000 1073.820000 1282.820000 ;
+        RECT 1072.620000 1276.900000 1073.820000 1277.380000 ;
+        RECT 1072.620000 1271.460000 1073.820000 1271.940000 ;
+        RECT 1072.620000 1260.580000 1073.820000 1261.060000 ;
+        RECT 1072.620000 1255.140000 1073.820000 1255.620000 ;
+        RECT 1072.620000 1249.700000 1073.820000 1250.180000 ;
+        RECT 1072.620000 1244.260000 1073.820000 1244.740000 ;
+        RECT 1072.620000 1266.020000 1073.820000 1266.500000 ;
+        RECT 1027.620000 1331.300000 1028.820000 1331.780000 ;
+        RECT 1027.620000 1325.860000 1028.820000 1326.340000 ;
+        RECT 1027.620000 1320.420000 1028.820000 1320.900000 ;
+        RECT 982.620000 1331.300000 983.820000 1331.780000 ;
+        RECT 982.620000 1325.860000 983.820000 1326.340000 ;
+        RECT 982.620000 1320.420000 983.820000 1320.900000 ;
+        RECT 1027.620000 1304.100000 1028.820000 1304.580000 ;
+        RECT 1027.620000 1298.660000 1028.820000 1299.140000 ;
+        RECT 1027.620000 1293.220000 1028.820000 1293.700000 ;
+        RECT 1027.620000 1309.540000 1028.820000 1310.020000 ;
+        RECT 1027.620000 1314.980000 1028.820000 1315.460000 ;
+        RECT 982.620000 1314.980000 983.820000 1315.460000 ;
+        RECT 982.620000 1304.100000 983.820000 1304.580000 ;
+        RECT 982.620000 1298.660000 983.820000 1299.140000 ;
+        RECT 982.620000 1293.220000 983.820000 1293.700000 ;
+        RECT 982.620000 1309.540000 983.820000 1310.020000 ;
+        RECT 937.620000 1331.300000 938.820000 1331.780000 ;
+        RECT 933.390000 1331.300000 934.590000 1331.780000 ;
+        RECT 933.390000 1325.860000 934.590000 1326.340000 ;
+        RECT 937.620000 1325.860000 938.820000 1326.340000 ;
+        RECT 937.620000 1320.420000 938.820000 1320.900000 ;
+        RECT 933.390000 1320.420000 934.590000 1320.900000 ;
+        RECT 937.620000 1314.980000 938.820000 1315.460000 ;
+        RECT 933.390000 1314.980000 934.590000 1315.460000 ;
+        RECT 937.620000 1309.540000 938.820000 1310.020000 ;
+        RECT 933.390000 1309.540000 934.590000 1310.020000 ;
+        RECT 937.620000 1298.660000 938.820000 1299.140000 ;
+        RECT 933.390000 1298.660000 934.590000 1299.140000 ;
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+        RECT 933.390000 1293.220000 934.590000 1293.700000 ;
+        RECT 937.620000 1304.100000 938.820000 1304.580000 ;
+        RECT 933.390000 1304.100000 934.590000 1304.580000 ;
+        RECT 1027.620000 1287.780000 1028.820000 1288.260000 ;
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+        RECT 1027.620000 1276.900000 1028.820000 1277.380000 ;
+        RECT 1027.620000 1271.460000 1028.820000 1271.940000 ;
+        RECT 982.620000 1287.780000 983.820000 1288.260000 ;
+        RECT 982.620000 1282.340000 983.820000 1282.820000 ;
+        RECT 982.620000 1276.900000 983.820000 1277.380000 ;
+        RECT 982.620000 1271.460000 983.820000 1271.940000 ;
+        RECT 1027.620000 1260.580000 1028.820000 1261.060000 ;
+        RECT 1027.620000 1244.260000 1028.820000 1244.740000 ;
+        RECT 1027.620000 1249.700000 1028.820000 1250.180000 ;
+        RECT 1027.620000 1255.140000 1028.820000 1255.620000 ;
+        RECT 1027.620000 1266.020000 1028.820000 1266.500000 ;
+        RECT 982.620000 1244.260000 983.820000 1244.740000 ;
+        RECT 982.620000 1249.700000 983.820000 1250.180000 ;
+        RECT 982.620000 1255.140000 983.820000 1255.620000 ;
+        RECT 982.620000 1260.580000 983.820000 1261.060000 ;
+        RECT 982.620000 1266.020000 983.820000 1266.500000 ;
+        RECT 937.620000 1287.780000 938.820000 1288.260000 ;
+        RECT 933.390000 1287.780000 934.590000 1288.260000 ;
+        RECT 937.620000 1282.340000 938.820000 1282.820000 ;
+        RECT 933.390000 1282.340000 934.590000 1282.820000 ;
+        RECT 937.620000 1276.900000 938.820000 1277.380000 ;
+        RECT 933.390000 1276.900000 934.590000 1277.380000 ;
+        RECT 937.620000 1271.460000 938.820000 1271.940000 ;
+        RECT 933.390000 1271.460000 934.590000 1271.940000 ;
+        RECT 937.620000 1266.020000 938.820000 1266.500000 ;
+        RECT 937.620000 1260.580000 938.820000 1261.060000 ;
+        RECT 933.390000 1266.020000 934.590000 1266.500000 ;
+        RECT 933.390000 1260.580000 934.590000 1261.060000 ;
+        RECT 937.620000 1255.140000 938.820000 1255.620000 ;
+        RECT 933.390000 1255.140000 934.590000 1255.620000 ;
+        RECT 937.620000 1249.700000 938.820000 1250.180000 ;
+        RECT 933.390000 1249.700000 934.590000 1250.180000 ;
+        RECT 937.620000 1244.260000 938.820000 1244.740000 ;
+        RECT 933.390000 1244.260000 934.590000 1244.740000 ;
+        RECT 1117.620000 1238.820000 1118.820000 1239.300000 ;
+        RECT 1117.620000 1233.380000 1118.820000 1233.860000 ;
+        RECT 1126.630000 1238.820000 1127.830000 1239.300000 ;
+        RECT 1126.630000 1233.380000 1127.830000 1233.860000 ;
+        RECT 1126.630000 1217.060000 1127.830000 1217.540000 ;
+        RECT 1126.630000 1222.500000 1127.830000 1222.980000 ;
+        RECT 1126.630000 1227.940000 1127.830000 1228.420000 ;
+        RECT 1117.620000 1227.940000 1118.820000 1228.420000 ;
+        RECT 1117.620000 1222.500000 1118.820000 1222.980000 ;
+        RECT 1117.620000 1217.060000 1118.820000 1217.540000 ;
+        RECT 1117.620000 1206.180000 1118.820000 1206.660000 ;
+        RECT 1117.620000 1211.620000 1118.820000 1212.100000 ;
+        RECT 1126.630000 1211.620000 1127.830000 1212.100000 ;
+        RECT 1126.630000 1206.180000 1127.830000 1206.660000 ;
+        RECT 1126.630000 1195.300000 1127.830000 1195.780000 ;
+        RECT 1126.630000 1200.740000 1127.830000 1201.220000 ;
+        RECT 1117.620000 1195.300000 1118.820000 1195.780000 ;
+        RECT 1117.620000 1200.740000 1118.820000 1201.220000 ;
+        RECT 1072.620000 1238.820000 1073.820000 1239.300000 ;
+        RECT 1072.620000 1233.380000 1073.820000 1233.860000 ;
+        RECT 1072.620000 1227.940000 1073.820000 1228.420000 ;
+        RECT 1072.620000 1222.500000 1073.820000 1222.980000 ;
+        RECT 1072.620000 1217.060000 1073.820000 1217.540000 ;
+        RECT 1072.620000 1195.300000 1073.820000 1195.780000 ;
+        RECT 1072.620000 1200.740000 1073.820000 1201.220000 ;
+        RECT 1072.620000 1206.180000 1073.820000 1206.660000 ;
+        RECT 1072.620000 1211.620000 1073.820000 1212.100000 ;
+        RECT 1117.620000 1189.860000 1118.820000 1190.340000 ;
+        RECT 1117.620000 1184.420000 1118.820000 1184.900000 ;
+        RECT 1126.630000 1189.860000 1127.830000 1190.340000 ;
+        RECT 1126.630000 1184.420000 1127.830000 1184.900000 ;
+        RECT 1117.620000 1173.540000 1118.820000 1174.020000 ;
+        RECT 1117.620000 1168.100000 1118.820000 1168.580000 ;
+        RECT 1126.630000 1173.540000 1127.830000 1174.020000 ;
+        RECT 1126.630000 1168.100000 1127.830000 1168.580000 ;
+        RECT 1117.620000 1178.980000 1118.820000 1179.460000 ;
+        RECT 1126.630000 1178.980000 1127.830000 1179.460000 ;
+        RECT 1126.630000 1157.220000 1127.830000 1157.700000 ;
+        RECT 1126.630000 1162.660000 1127.830000 1163.140000 ;
+        RECT 1117.620000 1162.660000 1118.820000 1163.140000 ;
+        RECT 1117.620000 1157.220000 1118.820000 1157.700000 ;
+        RECT 1117.620000 1151.780000 1118.820000 1152.260000 ;
+        RECT 1117.620000 1146.340000 1118.820000 1146.820000 ;
+        RECT 1126.630000 1151.780000 1127.830000 1152.260000 ;
+        RECT 1126.630000 1146.340000 1127.830000 1146.820000 ;
+        RECT 1072.620000 1189.860000 1073.820000 1190.340000 ;
+        RECT 1072.620000 1184.420000 1073.820000 1184.900000 ;
+        RECT 1072.620000 1178.980000 1073.820000 1179.460000 ;
+        RECT 1072.620000 1173.540000 1073.820000 1174.020000 ;
+        RECT 1072.620000 1168.100000 1073.820000 1168.580000 ;
+        RECT 1072.620000 1162.660000 1073.820000 1163.140000 ;
+        RECT 1072.620000 1157.220000 1073.820000 1157.700000 ;
+        RECT 1072.620000 1151.780000 1073.820000 1152.260000 ;
+        RECT 1072.620000 1146.340000 1073.820000 1146.820000 ;
+        RECT 1027.620000 1238.820000 1028.820000 1239.300000 ;
+        RECT 1027.620000 1233.380000 1028.820000 1233.860000 ;
+        RECT 1027.620000 1227.940000 1028.820000 1228.420000 ;
+        RECT 1027.620000 1222.500000 1028.820000 1222.980000 ;
+        RECT 1027.620000 1217.060000 1028.820000 1217.540000 ;
+        RECT 982.620000 1238.820000 983.820000 1239.300000 ;
+        RECT 982.620000 1233.380000 983.820000 1233.860000 ;
+        RECT 982.620000 1227.940000 983.820000 1228.420000 ;
+        RECT 982.620000 1222.500000 983.820000 1222.980000 ;
+        RECT 982.620000 1217.060000 983.820000 1217.540000 ;
+        RECT 1027.620000 1211.620000 1028.820000 1212.100000 ;
+        RECT 1027.620000 1206.180000 1028.820000 1206.660000 ;
+        RECT 1027.620000 1200.740000 1028.820000 1201.220000 ;
+        RECT 1027.620000 1195.300000 1028.820000 1195.780000 ;
+        RECT 982.620000 1206.180000 983.820000 1206.660000 ;
+        RECT 982.620000 1200.740000 983.820000 1201.220000 ;
+        RECT 982.620000 1195.300000 983.820000 1195.780000 ;
+        RECT 982.620000 1211.620000 983.820000 1212.100000 ;
+        RECT 937.620000 1238.820000 938.820000 1239.300000 ;
+        RECT 933.390000 1238.820000 934.590000 1239.300000 ;
+        RECT 937.620000 1233.380000 938.820000 1233.860000 ;
+        RECT 933.390000 1233.380000 934.590000 1233.860000 ;
+        RECT 937.620000 1227.940000 938.820000 1228.420000 ;
+        RECT 933.390000 1227.940000 934.590000 1228.420000 ;
+        RECT 937.620000 1217.060000 938.820000 1217.540000 ;
+        RECT 933.390000 1217.060000 934.590000 1217.540000 ;
+        RECT 933.390000 1222.500000 934.590000 1222.980000 ;
+        RECT 937.620000 1222.500000 938.820000 1222.980000 ;
+        RECT 937.620000 1211.620000 938.820000 1212.100000 ;
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+        RECT 937.620000 1206.180000 938.820000 1206.660000 ;
+        RECT 933.390000 1206.180000 934.590000 1206.660000 ;
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+        RECT 1027.620000 1151.780000 1028.820000 1152.260000 ;
+        RECT 1027.620000 1157.220000 1028.820000 1157.700000 ;
+        RECT 1027.620000 1162.660000 1028.820000 1163.140000 ;
+        RECT 982.620000 1146.340000 983.820000 1146.820000 ;
+        RECT 982.620000 1151.780000 983.820000 1152.260000 ;
+        RECT 982.620000 1157.220000 983.820000 1157.700000 ;
+        RECT 982.620000 1162.660000 983.820000 1163.140000 ;
+        RECT 937.620000 1189.860000 938.820000 1190.340000 ;
+        RECT 933.390000 1189.860000 934.590000 1190.340000 ;
+        RECT 937.620000 1184.420000 938.820000 1184.900000 ;
+        RECT 933.390000 1184.420000 934.590000 1184.900000 ;
+        RECT 937.620000 1173.540000 938.820000 1174.020000 ;
+        RECT 933.390000 1173.540000 934.590000 1174.020000 ;
+        RECT 937.620000 1168.100000 938.820000 1168.580000 ;
+        RECT 933.390000 1168.100000 934.590000 1168.580000 ;
+        RECT 937.620000 1178.980000 938.820000 1179.460000 ;
+        RECT 933.390000 1178.980000 934.590000 1179.460000 ;
+        RECT 937.620000 1162.660000 938.820000 1163.140000 ;
+        RECT 933.390000 1162.660000 934.590000 1163.140000 ;
+        RECT 937.620000 1157.220000 938.820000 1157.700000 ;
+        RECT 933.390000 1157.220000 934.590000 1157.700000 ;
+        RECT 937.620000 1151.780000 938.820000 1152.260000 ;
+        RECT 937.620000 1146.340000 938.820000 1146.820000 ;
+        RECT 933.390000 1151.780000 934.590000 1152.260000 ;
+        RECT 933.390000 1146.340000 934.590000 1146.820000 ;
+        RECT 930.560000 1336.500000 1130.660000 1337.700000 ;
+        RECT 930.560000 1144.330000 1130.660000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 1141.480000 934.590000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 933.390000 1340.540000 934.590000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 1141.480000 1127.830000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1126.630000 1340.540000 1127.830000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1144.330000 931.760000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1144.330000 1130.660000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 930.560000 1336.500000 931.760000 1337.700000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1129.460000 1336.500000 1130.660000 1337.700000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 3103.820000 1134.690000 3134.080000 ;
+        RECT 1326.730000 3103.820000 1327.930000 3134.080000 ;
+        RECT 1137.720000 3106.670000 1138.920000 3130.720000 ;
+        RECT 1182.720000 3106.670000 1183.920000 3130.720000 ;
+        RECT 1227.720000 3106.670000 1228.920000 3130.720000 ;
+        RECT 1272.720000 3106.670000 1273.920000 3130.720000 ;
+        RECT 1317.720000 3106.670000 1318.920000 3130.720000 ;
+      LAYER met3 ;
+        RECT 1326.730000 3119.560000 1327.930000 3120.040000 ;
+        RECT 1326.730000 3125.000000 1327.930000 3125.480000 ;
+        RECT 1317.720000 3125.000000 1318.920000 3125.480000 ;
+        RECT 1317.720000 3119.560000 1318.920000 3120.040000 ;
+        RECT 1272.720000 3119.560000 1273.920000 3120.040000 ;
+        RECT 1272.720000 3125.000000 1273.920000 3125.480000 ;
+        RECT 1182.720000 3119.560000 1183.920000 3120.040000 ;
+        RECT 1227.720000 3119.560000 1228.920000 3120.040000 ;
+        RECT 1227.720000 3125.000000 1228.920000 3125.480000 ;
+        RECT 1182.720000 3125.000000 1183.920000 3125.480000 ;
+        RECT 1133.490000 3119.560000 1134.690000 3120.040000 ;
+        RECT 1137.720000 3119.560000 1138.920000 3120.040000 ;
+        RECT 1137.720000 3125.000000 1138.920000 3125.480000 ;
+        RECT 1133.490000 3125.000000 1134.690000 3125.480000 ;
+        RECT 1326.730000 3108.680000 1327.930000 3109.160000 ;
+        RECT 1326.730000 3114.120000 1327.930000 3114.600000 ;
+        RECT 1317.720000 3114.120000 1318.920000 3114.600000 ;
+        RECT 1317.720000 3108.680000 1318.920000 3109.160000 ;
+        RECT 1272.720000 3108.680000 1273.920000 3109.160000 ;
+        RECT 1272.720000 3114.120000 1273.920000 3114.600000 ;
+        RECT 1182.720000 3108.680000 1183.920000 3109.160000 ;
+        RECT 1227.720000 3108.680000 1228.920000 3109.160000 ;
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+        RECT 1137.720000 3108.680000 1138.920000 3109.160000 ;
+        RECT 1130.660000 3129.520000 1330.760000 3130.720000 ;
+        RECT 1130.660000 3106.670000 1330.760000 3107.870000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 3132.880000 1134.690000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 3103.820000 1327.930000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 3132.880000 1327.930000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 3106.670000 1131.860000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 3106.670000 1330.760000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 3129.520000 1131.860000 3130.720000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 3129.520000 1330.760000 3130.720000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+        RECT 1133.490000 962.400000 1134.690000 962.880000 ;
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+        RECT 1130.660000 1136.240000 1330.760000 1137.440000 ;
+        RECT 1130.660000 944.070000 1330.760000 945.270000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 941.220000 1134.690000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 1140.280000 1134.690000 1141.480000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 941.220000 1327.930000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 1140.280000 1327.930000 1141.480000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 944.070000 1131.860000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 944.070000 1330.760000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 1136.240000 1131.860000 1137.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 1136.240000 1330.760000 1137.440000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
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+        RECT 1130.660000 335.200000 1330.760000 336.400000 ;
+        RECT 1130.660000 143.030000 1330.760000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 339.240000 1327.930000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 335.200000 1330.760000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
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+        RECT 1130.660000 112.770000 1330.760000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 135.620000 1330.760000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+        RECT 1137.720000 2906.410000 1138.920000 3099.780000 ;
+        RECT 1133.490000 2903.560000 1134.690000 3103.820000 ;
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+
+
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 2902.360000 1327.930000 2903.560000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 2898.320000 1330.760000 2899.520000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
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+        RECT 1130.660000 2658.060000 1330.760000 2659.260000 ;
+        RECT 1130.660000 2465.890000 1330.760000 2467.090000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 2662.100000 1134.690000 2663.300000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 2662.100000 1327.930000 2663.300000 ;
+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 2658.060000 1330.760000 2659.260000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+        RECT 1137.720000 1184.420000 1138.920000 1184.900000 ;
+        RECT 1133.490000 1184.420000 1134.690000 1184.900000 ;
+        RECT 1137.720000 1173.540000 1138.920000 1174.020000 ;
+        RECT 1133.490000 1173.540000 1134.690000 1174.020000 ;
+        RECT 1137.720000 1168.100000 1138.920000 1168.580000 ;
+        RECT 1133.490000 1168.100000 1134.690000 1168.580000 ;
+        RECT 1137.720000 1178.980000 1138.920000 1179.460000 ;
+        RECT 1133.490000 1178.980000 1134.690000 1179.460000 ;
+        RECT 1137.720000 1162.660000 1138.920000 1163.140000 ;
+        RECT 1133.490000 1162.660000 1134.690000 1163.140000 ;
+        RECT 1137.720000 1157.220000 1138.920000 1157.700000 ;
+        RECT 1133.490000 1157.220000 1134.690000 1157.700000 ;
+        RECT 1137.720000 1151.780000 1138.920000 1152.260000 ;
+        RECT 1137.720000 1146.340000 1138.920000 1146.820000 ;
+        RECT 1133.490000 1151.780000 1134.690000 1152.260000 ;
+        RECT 1133.490000 1146.340000 1134.690000 1146.820000 ;
+        RECT 1130.660000 1336.500000 1330.760000 1337.700000 ;
+        RECT 1130.660000 1144.330000 1330.760000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 1141.480000 1134.690000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1133.490000 1340.540000 1134.690000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 1141.480000 1327.930000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1326.730000 1340.540000 1327.930000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 1144.330000 1131.860000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 1144.330000 1330.760000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1130.660000 1336.500000 1131.860000 1337.700000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1329.560000 1336.500000 1330.760000 1337.700000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 3103.820000 1334.790000 3134.080000 ;
+        RECT 1526.830000 3103.820000 1528.030000 3134.080000 ;
+        RECT 1337.820000 3106.670000 1339.020000 3130.720000 ;
+        RECT 1382.820000 3106.670000 1384.020000 3130.720000 ;
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+        RECT 1472.820000 3106.670000 1474.020000 3130.720000 ;
+        RECT 1517.820000 3106.670000 1519.020000 3130.720000 ;
+      LAYER met3 ;
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+        RECT 1382.820000 3119.560000 1384.020000 3120.040000 ;
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+        RECT 1427.820000 3125.000000 1429.020000 3125.480000 ;
+        RECT 1382.820000 3125.000000 1384.020000 3125.480000 ;
+        RECT 1333.590000 3119.560000 1334.790000 3120.040000 ;
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+        RECT 1333.590000 3114.120000 1334.790000 3114.600000 ;
+        RECT 1337.820000 3114.120000 1339.020000 3114.600000 ;
+        RECT 1333.590000 3108.680000 1334.790000 3109.160000 ;
+        RECT 1337.820000 3108.680000 1339.020000 3109.160000 ;
+        RECT 1330.760000 3129.520000 1530.860000 3130.720000 ;
+        RECT 1330.760000 3106.670000 1530.860000 3107.870000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 3103.820000 1334.790000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 3132.880000 1334.790000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 3103.820000 1528.030000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 3132.880000 1528.030000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 3106.670000 1331.960000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 3106.670000 1530.860000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 3129.520000 1331.960000 3130.720000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 3129.520000 1530.860000 3130.720000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+        RECT 1337.820000 944.070000 1339.020000 1137.440000 ;
+        RECT 1333.590000 941.220000 1334.790000 1141.480000 ;
+      LAYER met3 ;
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+        RECT 1517.820000 1125.600000 1519.020000 1126.080000 ;
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+        RECT 1382.820000 956.960000 1384.020000 957.440000 ;
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+        RECT 1333.590000 984.160000 1334.790000 984.640000 ;
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+        RECT 1333.590000 973.280000 1334.790000 973.760000 ;
+        RECT 1337.820000 967.840000 1339.020000 968.320000 ;
+        RECT 1333.590000 967.840000 1334.790000 968.320000 ;
+        RECT 1337.820000 978.720000 1339.020000 979.200000 ;
+        RECT 1333.590000 978.720000 1334.790000 979.200000 ;
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+        RECT 1333.590000 962.400000 1334.790000 962.880000 ;
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+        RECT 1333.590000 956.960000 1334.790000 957.440000 ;
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+        RECT 1333.590000 946.080000 1334.790000 946.560000 ;
+        RECT 1330.760000 1136.240000 1530.860000 1137.440000 ;
+        RECT 1330.760000 944.070000 1530.860000 945.270000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 941.220000 1334.790000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 1140.280000 1334.790000 1141.480000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 941.220000 1528.030000 942.420000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 1140.280000 1528.030000 1141.480000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 944.070000 1331.960000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 944.070000 1530.860000 945.270000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 1136.240000 1331.960000 1137.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 1136.240000 1530.860000 1137.440000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+        RECT 1337.820000 743.810000 1339.020000 937.180000 ;
+        RECT 1333.590000 740.960000 1334.790000 941.220000 ;
+      LAYER met3 ;
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+        RECT 1333.590000 887.260000 1334.790000 887.740000 ;
+        RECT 1337.820000 881.820000 1339.020000 882.300000 ;
+        RECT 1333.590000 881.820000 1334.790000 882.300000 ;
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+        RECT 1333.590000 876.380000 1334.790000 876.860000 ;
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+        RECT 1333.590000 870.940000 1334.790000 871.420000 ;
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+        RECT 1382.820000 821.980000 1384.020000 822.460000 ;
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+        RECT 1333.590000 832.860000 1334.790000 833.340000 ;
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+        RECT 1333.590000 827.420000 1334.790000 827.900000 ;
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+        RECT 1333.590000 783.900000 1334.790000 784.380000 ;
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+        RECT 1333.590000 773.020000 1334.790000 773.500000 ;
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+        RECT 1333.590000 767.580000 1334.790000 768.060000 ;
+        RECT 1337.820000 778.460000 1339.020000 778.940000 ;
+        RECT 1333.590000 778.460000 1334.790000 778.940000 ;
+        RECT 1337.820000 762.140000 1339.020000 762.620000 ;
+        RECT 1333.590000 762.140000 1334.790000 762.620000 ;
+        RECT 1337.820000 756.700000 1339.020000 757.180000 ;
+        RECT 1333.590000 756.700000 1334.790000 757.180000 ;
+        RECT 1337.820000 751.260000 1339.020000 751.740000 ;
+        RECT 1337.820000 745.820000 1339.020000 746.300000 ;
+        RECT 1333.590000 751.260000 1334.790000 751.740000 ;
+        RECT 1333.590000 745.820000 1334.790000 746.300000 ;
+        RECT 1330.760000 935.980000 1530.860000 937.180000 ;
+        RECT 1330.760000 743.810000 1530.860000 745.010000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 740.960000 1334.790000 742.160000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 940.020000 1334.790000 941.220000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 740.960000 1528.030000 742.160000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 940.020000 1528.030000 941.220000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 743.810000 1331.960000 745.010000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 743.810000 1530.860000 745.010000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 935.980000 1331.960000 937.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 935.980000 1530.860000 937.180000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1517.820000 543.550000 1519.020000 736.920000 ;
+        RECT 1472.820000 543.550000 1474.020000 736.920000 ;
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+        RECT 1337.820000 543.550000 1339.020000 736.920000 ;
+        RECT 1333.590000 540.700000 1334.790000 740.960000 ;
+      LAYER met3 ;
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+        RECT 1330.760000 735.720000 1530.860000 736.920000 ;
+        RECT 1330.760000 543.550000 1530.860000 544.750000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 540.700000 1334.790000 541.900000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 739.760000 1334.790000 740.960000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 540.700000 1528.030000 541.900000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 739.760000 1528.030000 740.960000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 543.550000 1331.960000 544.750000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 543.550000 1530.860000 544.750000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 735.720000 1331.960000 736.920000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 735.720000 1530.860000 736.920000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+
+
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+        RECT 1333.590000 150.480000 1334.790000 150.960000 ;
+        RECT 1333.590000 145.040000 1334.790000 145.520000 ;
+        RECT 1330.760000 335.200000 1530.860000 336.400000 ;
+        RECT 1330.760000 143.030000 1530.860000 144.230000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 140.180000 1334.790000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 339.240000 1334.790000 340.440000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 140.180000 1528.030000 141.380000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 339.240000 1528.030000 340.440000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 143.030000 1331.960000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 143.030000 1530.860000 144.230000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 335.200000 1331.960000 336.400000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 335.200000 1530.860000 336.400000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 109.920000 1334.790000 140.180000 ;
+        RECT 1526.830000 109.920000 1528.030000 140.180000 ;
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+      LAYER met3 ;
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+        RECT 1382.820000 131.100000 1384.020000 131.580000 ;
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+        RECT 1333.590000 131.100000 1334.790000 131.580000 ;
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+        RECT 1337.820000 114.780000 1339.020000 115.260000 ;
+        RECT 1330.760000 135.620000 1530.860000 136.820000 ;
+        RECT 1330.760000 112.770000 1530.860000 113.970000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 109.920000 1334.790000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 138.980000 1334.790000 140.180000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 109.920000 1528.030000 111.120000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 138.980000 1528.030000 140.180000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 112.770000 1331.960000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 112.770000 1530.860000 113.970000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 135.620000 1331.960000 136.820000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 135.620000 1530.860000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1517.820000 2906.410000 1519.020000 3099.780000 ;
+        RECT 1472.820000 2906.410000 1474.020000 3099.780000 ;
+        RECT 1526.830000 2903.560000 1528.030000 3103.820000 ;
+        RECT 1427.820000 2906.410000 1429.020000 3099.780000 ;
+        RECT 1382.820000 2906.410000 1384.020000 3099.780000 ;
+        RECT 1337.820000 2906.410000 1339.020000 3099.780000 ;
+        RECT 1333.590000 2903.560000 1334.790000 3103.820000 ;
+      LAYER met3 ;
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+        RECT 1517.820000 3087.940000 1519.020000 3088.420000 ;
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+        RECT 1526.830000 3071.620000 1528.030000 3072.100000 ;
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+        RECT 1382.820000 3087.940000 1384.020000 3088.420000 ;
+        RECT 1382.820000 3082.500000 1384.020000 3082.980000 ;
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+        RECT 1427.820000 3055.300000 1429.020000 3055.780000 ;
+        RECT 1427.820000 3071.620000 1429.020000 3072.100000 ;
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+        RECT 1382.820000 3077.060000 1384.020000 3077.540000 ;
+        RECT 1382.820000 3066.180000 1384.020000 3066.660000 ;
+        RECT 1382.820000 3060.740000 1384.020000 3061.220000 ;
+        RECT 1382.820000 3055.300000 1384.020000 3055.780000 ;
+        RECT 1382.820000 3071.620000 1384.020000 3072.100000 ;
+        RECT 1337.820000 3093.380000 1339.020000 3093.860000 ;
+        RECT 1333.590000 3093.380000 1334.790000 3093.860000 ;
+        RECT 1333.590000 3087.940000 1334.790000 3088.420000 ;
+        RECT 1337.820000 3087.940000 1339.020000 3088.420000 ;
+        RECT 1337.820000 3082.500000 1339.020000 3082.980000 ;
+        RECT 1333.590000 3082.500000 1334.790000 3082.980000 ;
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+        RECT 1333.590000 3077.060000 1334.790000 3077.540000 ;
+        RECT 1337.820000 3071.620000 1339.020000 3072.100000 ;
+        RECT 1333.590000 3071.620000 1334.790000 3072.100000 ;
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+        RECT 1333.590000 3055.300000 1334.790000 3055.780000 ;
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+        RECT 1382.820000 3049.860000 1384.020000 3050.340000 ;
+        RECT 1382.820000 3044.420000 1384.020000 3044.900000 ;
+        RECT 1382.820000 3038.980000 1384.020000 3039.460000 ;
+        RECT 1382.820000 3033.540000 1384.020000 3034.020000 ;
+        RECT 1427.820000 3022.660000 1429.020000 3023.140000 ;
+        RECT 1427.820000 3006.340000 1429.020000 3006.820000 ;
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+        RECT 1382.820000 3006.340000 1384.020000 3006.820000 ;
+        RECT 1382.820000 3011.780000 1384.020000 3012.260000 ;
+        RECT 1382.820000 3017.220000 1384.020000 3017.700000 ;
+        RECT 1382.820000 3022.660000 1384.020000 3023.140000 ;
+        RECT 1382.820000 3028.100000 1384.020000 3028.580000 ;
+        RECT 1337.820000 3049.860000 1339.020000 3050.340000 ;
+        RECT 1333.590000 3049.860000 1334.790000 3050.340000 ;
+        RECT 1337.820000 3044.420000 1339.020000 3044.900000 ;
+        RECT 1333.590000 3044.420000 1334.790000 3044.900000 ;
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+        RECT 1333.590000 3038.980000 1334.790000 3039.460000 ;
+        RECT 1337.820000 3033.540000 1339.020000 3034.020000 ;
+        RECT 1333.590000 3033.540000 1334.790000 3034.020000 ;
+        RECT 1337.820000 3028.100000 1339.020000 3028.580000 ;
+        RECT 1337.820000 3022.660000 1339.020000 3023.140000 ;
+        RECT 1333.590000 3028.100000 1334.790000 3028.580000 ;
+        RECT 1333.590000 3022.660000 1334.790000 3023.140000 ;
+        RECT 1337.820000 3017.220000 1339.020000 3017.700000 ;
+        RECT 1333.590000 3017.220000 1334.790000 3017.700000 ;
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+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
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+
+
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+        RECT 1333.590000 2461.840000 1334.790000 2463.040000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 2262.780000 1528.030000 2263.980000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 2461.840000 1528.030000 2463.040000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 2265.630000 1331.960000 2266.830000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 2265.630000 1530.860000 2266.830000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 2457.800000 1331.960000 2459.000000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 2457.800000 1530.860000 2459.000000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 1333.590000 2168.820000 1334.790000 2169.300000 ;
+        RECT 1337.820000 2163.380000 1339.020000 2163.860000 ;
+        RECT 1333.590000 2163.380000 1334.790000 2163.860000 ;
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+        RECT 1333.590000 2157.940000 1334.790000 2158.420000 ;
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+        RECT 1333.590000 2152.500000 1334.790000 2152.980000 ;
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+        RECT 1382.820000 2108.980000 1384.020000 2109.460000 ;
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+        RECT 1333.590000 2060.020000 1334.790000 2060.500000 ;
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+        RECT 1333.590000 2043.700000 1334.790000 2044.180000 ;
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+        RECT 1333.590000 2038.260000 1334.790000 2038.740000 ;
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+        RECT 1333.590000 2032.820000 1334.790000 2033.300000 ;
+        RECT 1333.590000 2027.380000 1334.790000 2027.860000 ;
+        RECT 1330.760000 2217.540000 1530.860000 2218.740000 ;
+        RECT 1330.760000 2025.370000 1530.860000 2026.570000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 2022.520000 1334.790000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 2221.580000 1334.790000 2222.780000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 2022.520000 1528.030000 2023.720000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 2221.580000 1528.030000 2222.780000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 2025.370000 1331.960000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 2025.370000 1530.860000 2026.570000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 2217.540000 1331.960000 2218.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 2217.540000 1530.860000 2218.740000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+    PORT
+      LAYER met4 ;
+        RECT 1517.820000 1825.110000 1519.020000 2018.480000 ;
+        RECT 1472.820000 1825.110000 1474.020000 2018.480000 ;
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+        RECT 1337.820000 1825.110000 1339.020000 2018.480000 ;
+        RECT 1333.590000 1822.260000 1334.790000 2022.520000 ;
+      LAYER met3 ;
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+        RECT 1526.830000 2001.200000 1528.030000 2001.680000 ;
+        RECT 1526.830000 2006.640000 1528.030000 2007.120000 ;
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+        RECT 1526.830000 1995.760000 1528.030000 1996.240000 ;
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+    END
+    PORT
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+    END
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+    END
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
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+    END
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+    END
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+    END
+    PORT
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+    END
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+    END
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+    END
+    PORT
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+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+        RECT 1333.590000 1173.540000 1334.790000 1174.020000 ;
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+        RECT 1333.590000 1168.100000 1334.790000 1168.580000 ;
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+        RECT 1333.590000 1178.980000 1334.790000 1179.460000 ;
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+        RECT 1333.590000 1162.660000 1334.790000 1163.140000 ;
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+        RECT 1333.590000 1151.780000 1334.790000 1152.260000 ;
+        RECT 1333.590000 1146.340000 1334.790000 1146.820000 ;
+        RECT 1330.760000 1336.500000 1530.860000 1337.700000 ;
+        RECT 1330.760000 1144.330000 1530.860000 1145.530000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 1141.480000 1334.790000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1333.590000 1340.540000 1334.790000 1341.740000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 1141.480000 1528.030000 1142.680000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1526.830000 1340.540000 1528.030000 1341.740000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 1144.330000 1331.960000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 1144.330000 1530.860000 1145.530000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1330.760000 1336.500000 1331.960000 1337.700000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1529.660000 1336.500000 1530.860000 1337.700000 ;
+    END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+    PORT
+      LAYER met4 ;
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+      LAYER met3 ;
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+        RECT 1538.690000 3108.680000 1539.890000 3109.160000 ;
+        RECT 1542.920000 3108.680000 1544.120000 3109.160000 ;
+        RECT 1535.860000 3129.520000 1735.960000 3130.720000 ;
+        RECT 1535.860000 3106.670000 1735.960000 3107.870000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1538.690000 3103.820000 1539.890000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1538.690000 3132.880000 1539.890000 3134.080000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1731.930000 3103.820000 1733.130000 3105.020000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 1731.930000 3132.880000 1733.130000 3134.080000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 3106.670000 1537.060000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 3106.670000 1735.960000 3107.870000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1535.860000 3129.520000 1537.060000 3130.720000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 3129.520000 1735.960000 3130.720000 ;
+    END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 535.970000 1735.960000 537.170000 ;
+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
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+    END
+    PORT
+      LAYER met3 ;
+        RECT 1734.760000 135.620000 1735.960000 136.820000 ;
+    END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+    PORT
+      LAYER met4 ;
+        RECT 1538.690000 2703.300000 1539.890000 3103.820000 ;
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+      LAYER met3 ;
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+# end of P/G pin shape extracted from block 'DSP'
+
+
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+    END
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+    END
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+    END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
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+# end of P/G pin shape extracted from block 'DSP'
+
+
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+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
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+# end of P/G pin shape extracted from block 'S_term_single'
+
+
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+
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+
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+        RECT 2291.240000 1792.230000 2841.400000 1793.430000 ;
+    END
+    PORT
+      LAYER met4 ;
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+    END
+    PORT
+      LAYER met4 ;
+        RECT 2834.640000 2335.380000 2835.840000 2336.580000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2296.800000 1786.800000 2298.000000 1788.000000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 2296.800000 2335.380000 2298.000000 2336.580000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2840.200000 1792.230000 2841.400000 1793.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2291.240000 1792.230000 2292.440000 1793.430000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2840.200000 2328.760000 2841.400000 2329.960000 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 2291.240000 2328.760000 2292.440000 2329.960000 ;
+    END
+# end of P/G pin shape extracted from block 'flexbex_ibex_core'
+
+
+# P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+    PORT
+      LAYER met3 ;
+        RECT 44.880000 3027.580000 515.140000 3029.320000 ;
+      LAYER met3 ;
+        RECT 44.880000 2641.340000 515.140000 2643.080000 ;
+      LAYER met4 ;
+        RECT 44.880000 2641.340000 46.620000 3029.320000 ;
+      LAYER met4 ;
+        RECT 513.400000 2641.340000 515.140000 3029.320000 ;
+    END
+# end of P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+
+
+# P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+    PORT
+      LAYER met3 ;
+        RECT 2366.380000 3027.580000 2836.640000 3029.320000 ;
+      LAYER met3 ;
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+        RECT 2834.900000 2641.340000 2836.640000 3029.320000 ;
+      LAYER met4 ;
+        RECT 2366.380000 2641.340000 2368.120000 3029.320000 ;
+    END
+# end of P/G pin shape extracted from block 'sky130_sram_1kbyte_1rw1r_32x256_8'
+
+  END vccd1
+  OBS
+    LAYER li1 ;
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+    LAYER met1 ;
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+      RECT 0.000000 1.700000 1.700000 3242.240000 ;
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+END eFPGA_CPU_top
+
+END LIBRARY
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index f5854c3..bca152c 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -4262,6 +4262,234 @@
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   PIN vccd2
     DIRECTION INPUT ;
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   PIN vdda1
     DIRECTION INPUT ;
@@ -4278,6 +4734,226 @@
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-        RECT -14.830 1004.330 2934.450 1007.430 ;
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-        RECT 0.000 54.630 2920.000 70.130 ;
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-        RECT 0.000 36.030 2920.000 51.530 ;
-        RECT -24.430 32.930 2944.050 36.030 ;
-        RECT 0.000 17.430 2920.000 32.930 ;
-        RECT -14.830 14.330 2934.450 17.430 ;
+        RECT 20.000 150.000 2901.440 3393.940 ;
   END
 END user_project_wrapper
 END LIBRARY
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 5006ced..3a7dbfb 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -39,14 +39,15 @@
 
 ## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "inst_eFPGA_CPU_top.wb_clk_i"
+#set ::env(CLOCK_NET) "mprj.clk"
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "40"
 
 ## Internal Macros
 ### Macro PDN Connections
 set ::env(FP_PDN_MACRO_HOOKS) "\
-	mprj vccd1 vssd1"
+	inst_eFPGA_CPU_top vccd1 vssd1"
 
 ### Macro Placement
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -54,13 +55,21 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	../verilog/rtl/eFPGA_CPU_top.v"
+
+#	$script_dir/../../verilog/rtl/user_proj_example.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/../../lef/eFPGA_CPU_top.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/../../gds/eFPGA_CPU_top.gds"
+
+#set ::env(EXTRA_LEFS) "\
+#	$script_dir/../../lef/user_proj_example.lef"
+
+#set ::env(EXTRA_GDS_FILES) "\
+#	$script_dir/../../gds/user_proj_example.gds"
 
 set ::env(GLB_RT_MAXLAYER) 5
 
@@ -83,3 +92,10 @@
 set ::env(FILL_INSERTION) 0
 set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(MAGIC_DRC_USE_GDS) 0
+set ::env(ROUTING_CORES) 12
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(VDD_PIN) "vccd1"
+set ::env(GND_PIN) "vssd1"
+set ::env(FP_PDN_IRDROP) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..884c6b8 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+inst_eFPGA_CPU_top 20 150 R0
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
deleted file mode 120000
index 8797dcd..0000000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..90cde69
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/verilog/dv/wb_test_icesoc/Makefile b/verilog/dv/wb_test_icesoc/Makefile
new file mode 100644
index 0000000..0291c3a
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/Makefile
@@ -0,0 +1,108 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK 
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_BEHAVIOURAL_MODELS = ../
+UPRJ_RTL_PATH      = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_RTL_ICESOC    = $(UPRJ_VERILOG_PATH)/rtl/icesoc
+UPRJ_RTL_IBEXCORE  = $(UPRJ_VERILOG_PATH)/rtl/ibex_core
+UPRJ_RTL_EFPGACORE = $(UPRJ_VERILOG_PATH)/rtl/eFPGA_core
+UPRJ_RTL_EFPGACONF = $(UPRJ_VERILOG_PATH)/rtl/eFPGA_conf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test_icesoc
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(UPRJ_BEHAVIOURAL_MODELS) \
+	-I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_RTL_ICESOC) \
+	-I $(UPRJ_RTL_IBEXCORE) \
+	-I $(UPRJ_RTL_EFPGACORE) \
+	-I $(UPRJ_RTL_EFPGACONF) \
+	$< -o $@ -g2012
+else  
+	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+ibex_prog = ./ibex_prog.h 
+$(ibex_prog): ibex_prog/*.c
+	make -C ./ibex_prog all work_dir=build
+ 
+%.elf: %.c $(ibex_prog) $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env 
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@1000/@0000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/Makefile b/verilog/dv/wb_test_icesoc/ibex_prog/Makefile
new file mode 100644
index 0000000..ade76f2
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/Makefile
@@ -0,0 +1,28 @@
+INC_DIRS = 
+SRCS = test.c rv32zk.S
+
+OUTH    = ../ibex_prog.h
+OUTBIN  = $(work_dir)/test.bin
+OUTPUT  = $(work_dir)/test.elf
+DISASM  = $(work_dir)/test.disasm
+
+all: $(OUTH) $(DISASM)
+
+CCFLAGS+=-Os -march=rv32im -mabi=ilp32 -ffreestanding -nostartfiles -nostdlib -nodefaultlibs -fpic -Wl,-T link.ld crt.s
+
+$(OUTPUT) : $(SRCS)
+	mkdir -p $(work_dir)
+	${GCC_PATH}/${GCC_PREFIX}-gcc  $^ $(CCFLAGS) $(INC_DIRS) -o $@ 
+
+$(OUTBIN): $(OUTPUT)
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< $@
+
+$(OUTH): $(OUTBIN) 
+	python3 gen_program.py $< $@	
+
+$(DISASM) : $(OUTPUT)
+	${GCC_PATH}/${GCC_PREFIX}-objdump -Dt $< > $@
+
+clean:
+	rm -rf $(work_dir)
+.PHONY: clean
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/aes_common.h b/verilog/dv/wb_test_icesoc/ibex_prog/aes_common.h
new file mode 100644
index 0000000..9cc353c
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/aes_common.h
@@ -0,0 +1,156 @@
+
+uint8_t AES_ENC_SBOX[]= {
+  0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
+  0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
+  0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
+  0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
+  0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
+  0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
+  0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
+  0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
+  0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
+  0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
+  0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
+  0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
+  0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
+  0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
+  0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
+  0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
+  0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
+  0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
+  0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
+  0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
+  0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
+  0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
+  0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
+  0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
+  0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
+  0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
+  0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
+  0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
+  0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
+  0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
+  0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
+  0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
+};
+
+uint8_t AES_DEC_SBOX[] = {
+  0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
+  0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
+  0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
+  0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
+  0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
+  0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
+  0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
+  0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
+  0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
+  0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
+  0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
+  0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
+  0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
+  0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
+  0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
+  0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
+  0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
+  0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
+  0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
+  0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
+  0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
+  0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
+  0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
+  0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
+  0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
+  0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
+  0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
+  0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
+  0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
+  0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
+  0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
+  0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
+};
+
+#define AES_UNPACK_BYTES(b0,b1,b2,b3) \
+    uint8_t  b0 = (RS1 >>  0) & 0xFF; \
+    uint8_t  b1 = (RS2 >>  8) & 0xFF; \
+    uint8_t  b2 = (RS1 >> 16) & 0xFF; \
+    uint8_t  b3 = (RS2 >> 24) & 0xFF; \
+
+#define AES_PACK_BYTES(b0,b1,b2,b3) ( \
+    (uint32_t)b0 <<  0  | \
+    (uint32_t)b1 <<  8  | \
+    (uint32_t)b2 << 16  | \
+    (uint32_t)b3 << 24  )
+
+#define AES_SBOX(b0, b1, b2, b3) \
+    b0 = AES_ENC_SBOX[b0]; \
+    b1 = AES_ENC_SBOX[b1]; \
+    b2 = AES_ENC_SBOX[b2]; \
+    b3 = AES_ENC_SBOX[b3]; \
+
+#define AES_RSBOX(b0, b1, b2, b3) \
+    b0 = AES_DEC_SBOX[b0]; \
+    b1 = AES_DEC_SBOX[b1]; \
+    b2 = AES_DEC_SBOX[b2]; \
+    b3 = AES_DEC_SBOX[b3]; \
+
+#define AES_XTIME(a) \
+    ((a << 1) ^ ((a&0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a,b) (( \
+    ( ( (b) & 0x1 ) ?                              (a)   : 0 ) ^ \
+    ( ( (b) & 0x2 ) ?                     AES_XTIME(a)   : 0 ) ^ \
+    ( ( (b) & 0x4 ) ?           AES_XTIME(AES_XTIME(a))  : 0 ) ^ \
+    ( ( (b) & 0x8 ) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0 ) )&0xFF)
+
+#define BY(X,I) ((X >> (8*I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1,RS2) ( \
+    (((RS1 >> 24) & 0xFF) << 56) | \
+    (((RS2 >> 48) & 0xFF) << 48) | \
+    (((RS2 >>  8) & 0xFF) << 40) | \
+    (((RS1 >> 32) & 0xFF) << 32) | \
+    (((RS2 >> 56) & 0xFF) << 24) | \
+    (((RS2 >> 16) & 0xFF) << 16) | \
+    (((RS1 >> 40) & 0xFF) <<  8) | \
+    (((RS1 >>  0) & 0xFF) <<  0) ) 
+
+#define AES_INVSHIFROWS_LO(RS1,RS2) ( \
+    (((RS2 >> 24) & 0xFF) << 56) | \
+    (((RS2 >> 48) & 0xFF) << 48) | \
+    (((RS1 >>  8) & 0xFF) << 40) | \
+    (((RS1 >> 32) & 0xFF) << 32) | \
+    (((RS1 >> 56) & 0xFF) << 24) | \
+    (((RS2 >> 16) & 0xFF) << 16) | \
+    (((RS2 >> 40) & 0xFF) <<  8) | \
+    (((RS1 >>  0) & 0xFF) <<  0) ) 
+
+
+#define AES_MIXBYTE(COL,B0,B1,B2,B3) ( \
+              BY(COL,B3)     ^ \
+              BY(COL,B2)     ^ \
+    AES_GFMUL(BY(COL,B1), 3) ^ \
+    AES_GFMUL(BY(COL,B0), 2)   \
+)
+
+#define AES_MIXCOLUMN(COL) ( \
+    AES_MIXBYTE(COL,3,0,1,2) << 24 | \
+    AES_MIXBYTE(COL,2,3,0,1) << 16 | \
+    AES_MIXBYTE(COL,1,2,3,0) <<  8 | \
+    AES_MIXBYTE(COL,0,1,2,3) <<  0   \
+)
+
+
+#define AES_INVMIXBYTE(COL,B0,B1,B2,B3) ( \
+    AES_GFMUL(BY(COL,B3),0x9) ^ \
+    AES_GFMUL(BY(COL,B2),0xd) ^ \
+    AES_GFMUL(BY(COL,B1),0xb) ^ \
+    AES_GFMUL(BY(COL,B0),0xe)   \
+)
+
+#define AES_INVMIXCOLUMN(COL) ( \
+    AES_INVMIXBYTE(COL,3,0,1,2) << 24 | \
+    AES_INVMIXBYTE(COL,2,3,0,1) << 16 | \
+    AES_INVMIXBYTE(COL,1,2,3,0) <<  8 | \
+    AES_INVMIXBYTE(COL,0,1,2,3) <<  0   \
+)
+
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/crt.s b/verilog/dv/wb_test_icesoc/ibex_prog/crt.s
new file mode 100644
index 0000000..5cdfafa
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/crt.s
@@ -0,0 +1,76 @@
+.section .text
+
+reset_handler:
+  /* set all registers to zero */
+  mv  x1, x0
+  mv  x2, x1
+  mv  x3, x1
+  mv  x4, x1
+  mv  x5, x1
+  mv  x6, x1
+  mv  x7, x1
+  mv  x8, x1
+  mv  x9, x1
+  mv x10, x1
+  mv x11, x1
+  mv x12, x1
+  mv x13, x1
+  mv x14, x1
+  mv x15, x1
+  mv x16, x1
+  mv x17, x1
+  mv x18, x1
+  mv x19, x1
+  mv x20, x1
+  mv x21, x1
+  mv x22, x1
+  mv x23, x1
+  mv x24, x1
+  mv x25, x1
+  mv x26, x1
+  mv x27, x1
+  mv x28, x1
+  mv x29, x1
+  mv x30, x1
+  mv x31, x1
+
+  /* stack initilization */
+  la   x2, _stack_top
+  addi x2, x2, -8
+
+_start:
+  .global _start
+
+  /* clear BSS */
+  la x26, _bss_start
+  la x27, _bss_end
+
+  bge x26, x27, zero_loop_end
+
+zero_loop:
+  sw x0, 0(x26)
+  addi x26, x26, 4
+  ble x26, x27, zero_loop
+zero_loop_end:
+
+
+main_entry:
+  /* jump to main program entry point (argc = argv = 0) */
+  addi x10, x0, 0
+  addi x11, x0, 0
+  jal x1, main
+
+  /* If execution ends up here just put the core to sleep */
+sleep_loop:
+  wfi
+  j sleep_loop
+
+/* =================================================== [ exceptions ] === */
+/* This section has to be down here, since we have to disable rvc for it  */
+
+  .section .vectors, "ax"
+  .option norvc;
+
+/* reset vector */
+  .org 0x80
+  jal x0, reset_handler
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/gen_program.py b/verilog/dv/wb_test_icesoc/ibex_prog/gen_program.py
new file mode 100644
index 0000000..9bc356f
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/gen_program.py
@@ -0,0 +1,25 @@
+import io
+import sys
+import subprocess
+
+binname = str(sys.argv[1])
+#binname ='/home/thinhpham/Documents/SCARV/icesoc_project/verilog/dv/wb_send_riscv_program/ibex_prog/test/test.bin'
+binfile = open(binname, 'rb')
+pro_data = binfile.read()
+pro_len = int(len(pro_data)/4)
+binfile.close()
+
+fileout = str(sys.argv[2])
+#fileout ='/home/thinhpham/Documents/SCARV/icesoc_project/verilog/dv/wb_send_riscv_program/ibex_prog/test.h'
+hfile   = open(fileout, 'w')
+
+hfile.write("uint32_t pro_len = " + str(pro_len) + "; \n")
+hfile.write("const uint32_t pro_data[" + str(pro_len) +'] ={ \n')
+for i in range(pro_len):
+    if i != pro_len-1:
+        hfile.write("       " + hex(int.from_bytes(pro_data[4*i:4*(i+1)], byteorder='little')) + ', \n')
+    else :
+        hfile.write("       " + hex(int.from_bytes(pro_data[4*i:4*(i+1)], byteorder='little')) + ' }; \n')
+
+hfile.close()
+
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/link.ld b/verilog/dv/wb_test_icesoc/ibex_prog/link.ld
new file mode 100644
index 0000000..a30bbd4
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/link.ld
@@ -0,0 +1,74 @@
+/*  */
+
+OUTPUT_ARCH(riscv)
+
+MEMORY
+{
+    ram         : ORIGIN = 0x00000000, LENGTH = 0x800     /* 2  kB */
+    stack       : ORIGIN = 0x00000700, LENGTH = 0x100     /* 256 B */
+}
+
+/* Stack */
+_min_stack      = 0x080;   /* 256 - minimum stack space to reserve */
+_stack_len     = LENGTH(stack);
+_stack_top   = ORIGIN(stack) + LENGTH(stack);
+
+_entry_point = _vectors_start + 0x80;
+ENTRY(_entry_point)
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+		_vectors_start = .;
+        KEEP(*(.vectors))
+		_vectors_end = .;
+    } > ram
+
+    .text : {
+        . = ALIGN(4);
+        *(.text)
+        *(.text.*)
+    }  > ram
+
+    .rodata : {
+        . = ALIGN(4);
+        /* Small RO data before large RO data */
+        *(.srodata)
+        *(.srodata.*)
+        *(.rodata);
+        *(.rodata.*)
+    } > ram
+
+    .data : {
+        . = ALIGN(4);
+        /* Small data before large data */
+        *(.sdata)
+        *(.sdata.*)
+        *(.data);
+        *(.data.*)
+    } > ram
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss_start = .;
+        /* Small BSS before large BSS */
+        *(.sbss)
+        *(.sbss.*)
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        _bss_end = .;
+    } > ram
+
+    /* ensure there is enough room for stack */
+    .stack (NOLOAD): {
+        . = ALIGN(4);
+        . = . + _min_stack ;
+        . = ALIGN(4);
+        stack = . ;
+        _stack = . ;
+    } > stack
+}
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/rv32zk.S b/verilog/dv/wb_test_icesoc/ibex_prog/rv32zk.S
new file mode 100644
index 0000000..5040a3e
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/rv32zk.S
@@ -0,0 +1,218 @@
+#include    "zkn.h"
+.text
+
+/*
+.global test_aes32dsi1
+.func   test_aes32dsi1
+test_aes32dsi1:
+    aes32dsi  a0, a0, a1, 1
+    ret
+.endfunc
+	
+.global test_aes32esi1
+.func   test_aes32esi1
+test_aes32esi1:
+    aes32esi a0, a0, a1, 1
+    ret
+.endfunc
+
+.global test_aes32dsmi1
+.func   test_aes32dsmi1
+test_aes32dsmi1:
+    aes32dsmi a0, a0, a1, 1
+    ret
+.endfunc
+
+
+.global test_aes32esmi1
+.func   test_aes32esmi1
+test_aes32esmi1:
+    aes32esmi a0, a0, a1, 1
+    ret
+.endfunc
+
+
+.global test_sha256sum0
+.func   test_sha256sum0
+test_sha256sum0:
+    sha256sum0 a0, a0
+    ret
+.endfunc
+
+.global test_sha256sum1
+.func   test_sha256sum1
+test_sha256sum1:
+    sha256sum1 a0, a0
+    ret
+.endfunc
+
+.global test_sha256sig0
+.func   test_sha256sig0
+test_sha256sig0:
+    sha256sig0 a0, a0
+    ret
+.endfunc
+
+.global test_sha256sig1
+.func   test_sha256sig1
+test_sha256sig1:
+    sha256sig1 a0, a0
+    ret
+.endfunc
+
+.global test_sha512sum0r
+.func   test_sha512sum0r
+test_sha512sum0r:
+    sha512sum0r a0, a0, a1
+    ret
+.endfunc
+
+.global test_sha512sum1r
+.func   test_sha512sum1r
+test_sha512sum1r:
+    sha512sum1r a0, a0, a1
+    ret
+.endfunc
+
+.global test_sha512sig0l
+.func   test_sha512sig0l
+test_sha512sig0l:
+    sha512sig0l a0, a0, a1
+    ret
+.endfunc
+
+.global test_sha512sig1l
+.func   test_sha512sig1l
+test_sha512sig1l:
+    sha512sig1l a0, a0, a1
+    ret
+.endfunc
+
+.global test_sha512sig0h
+.func   test_sha512sig0h
+test_sha512sig0h:
+    sha512sig0h a0, a0, a1
+    ret
+.endfunc
+
+.global test_sha512sig1h
+.func   test_sha512sig1h
+test_sha512sig1h:
+    sha512sig1h a0, a0, a1
+    ret
+.endfunc
+*/
+
+.global test_ror
+.func   test_ror
+test_ror:
+    ror a0, a0, a1
+    ret
+.endfunc
+	
+.global test_rol
+.func   test_rol
+test_rol:
+    rol a0, a0, a1
+    ret
+.endfunc
+
+.global test_ror7
+.func   test_ror7
+test_ror7:
+    rori a0, a0, 7
+    ret
+.endfunc
+
+.global test_andn
+.func   test_andn
+test_andn:
+    andn a0, a0, a1
+    ret
+.endfunc
+
+.global test_orn
+.func   test_orn
+test_orn:
+    orn a0, a0, a1
+    ret
+.endfunc
+
+.global test_xnor
+.func   test_xnor
+test_xnor:
+    xnor a0, a0, a1
+    ret
+.endfunc
+
+.global test_pack
+.func   test_pack
+test_pack:
+    pack a0, a0, a1
+    ret
+.endfunc
+
+.global test_packh
+.func   test_packh
+test_packh:
+    packh a0, a0, a1
+    ret
+.endfunc
+
+
+.global test_brev8
+.func   test_brev8
+test_brev8:
+    brev8 a0, a0
+    ret
+.endfunc
+
+.global test_rev8
+.func   test_rev8
+test_rev8:
+    rev8 a0, a0
+    ret
+.endfunc
+
+.global test_zip
+.func   test_zip
+test_zip:
+    zip a0, a0
+    ret
+.endfunc
+
+.global test_unzip
+.func   test_unzip
+test_unzip:
+    unzip a0, a0
+    ret
+.endfunc
+/*
+.global test_xperm8
+.func   test_xperm8
+test_xperm8:
+    xperm8 a0, a0, a1
+    ret
+.endfunc
+
+.global test_xperm4
+.func   test_xperm4
+test_xperm4:
+    xperm4 a0, a0,a1
+    ret
+.endfunc
+
+.global test_clmul
+.func   test_clmul
+test_clmul:
+    clmul a0, a0, a1
+    ret
+.endfunc
+
+.global test_clmulh
+.func   test_clmulh
+test_clmulh:
+    clmulh a0, a0,a1
+    ret
+.endfunc
+*/
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/test.c b/verilog/dv/wb_test_icesoc/ibex_prog/test.c
new file mode 100644
index 0000000..bf13a54
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/test.c
@@ -0,0 +1,602 @@
+#include <stdint.h>
+//#include "aes_common.h"
+
+#define ROL32(x,n) (((x) << (n)) | ((x) >> (32 - (n))))
+#define ROR32(x,n) (((x) >> (n)) | ((x) << (32 - (n))))
+#define ROL64(x,n) (((x) << (n)) | ((x) >> (64 - (n))))
+#define ROR64(x,n) (((x) >> (n)) | ((x) << (64 - (n))))
+
+static uint32_t lfsr(uint32_t x)
+{
+  uint32_t bit = (x ^ (x >> 1)) & 1;
+  return (x >> 1) | (bit << 30);
+}
+/*
+extern uint32_t test_aes32dsi1(uint32_t a, uint32_t b);
+extern uint32_t test_aes32esi1(uint32_t a, uint32_t b);
+extern uint32_t test_aes32dsmi1(uint32_t a, uint32_t b);
+extern uint32_t test_aes32esmi1(uint32_t a, uint32_t b);
+
+extern uint32_t test_sha256sum0(uint32_t a);
+extern uint32_t test_sha256sum1(uint32_t a);
+extern uint32_t test_sha256sig0(uint32_t a);
+extern uint32_t test_sha256sig1(uint32_t a);
+
+extern uint32_t test_sha512sum0r(uint32_t a, uint32_t b);
+extern uint32_t test_sha512sum1r(uint32_t a, uint32_t b);
+extern uint32_t test_sha512sig0l(uint32_t a, uint32_t b);
+extern uint32_t test_sha512sig0h(uint32_t a, uint32_t b);
+extern uint32_t test_sha512sig1l(uint32_t a, uint32_t b);
+extern uint32_t test_sha512sig1h(uint32_t a, uint32_t b);
+*/
+
+extern uint32_t test_ror(uint32_t a, uint32_t b);
+extern uint32_t test_rol(uint32_t a, uint32_t b);
+extern uint32_t test_ror7(uint32_t a);
+extern uint32_t test_andn(uint32_t a, uint32_t b);
+extern uint32_t test_orn(uint32_t a, uint32_t b);
+extern uint32_t test_xnor(uint32_t a, uint32_t b);
+
+extern uint32_t test_pack(uint32_t a, uint32_t b);
+extern uint32_t test_packh(uint32_t a, uint32_t b);
+extern uint32_t test_brev8(uint32_t a);
+extern uint32_t test_rev8(uint32_t a);
+extern uint32_t test_zip(uint32_t a);
+extern uint32_t test_unzip(uint32_t a);
+
+/*
+extern uint32_t test_xperm8(uint32_t a, uint32_t b);
+extern uint32_t test_xperm4(uint32_t a, uint32_t b);
+
+extern uint32_t test_clmul(uint32_t a, uint32_t b);
+extern uint32_t test_clmulh(uint32_t a, uint32_t b);
+*/
+
+/*
+uint32_t gold_aes32dsi(uint32_t a, uint32_t b, uint32_t bs){
+
+    uint8_t     t0 = (b >> (8*bs)) & 0xFF;
+    uint8_t      x = AES_DEC_SBOX[t0];
+    uint32_t     r = x;
+
+    r = (r << (8*bs)) | (r >> (32-8*bs));
+
+    return (r ^ a);
+}
+
+uint32_t gold_aes32esi(uint32_t a, uint32_t b, uint32_t bs){
+    uint8_t     t0 = (b >> (8*bs)) & 0xFF;
+    uint8_t      x = AES_ENC_SBOX[t0];
+    uint32_t     r = x;
+
+    r = (r << (8*bs)) | (r >> (32-8*bs));
+
+    return (r ^ a);
+}
+/*
+uint32_t gold_aes32dsmi(uint32_t a, uint32_t b, uint32_t bs){
+
+    uint8_t     t0 = b >> (8*bs);
+    uint8_t      x = AES_DEC_SBOX[t0];
+    uint32_t     r ;
+
+    r = (AES_GFMUL(x,0xb) << 24) |
+        (AES_GFMUL(x,0xd) << 16) |
+        (AES_GFMUL(x,0x9) <<  8) |
+        (AES_GFMUL(x,0xe) <<  0) ;
+
+    r = (r << (8*bs)) | (r >> (32-8*bs));
+
+    return (r ^ a);
+}
+
+uint32_t gold_aes32esmi(uint32_t a, uint32_t b, uint32_t bs){
+    uint8_t     t0 = (b >> (8*bs)) & 0xFF;
+    uint8_t      x = AES_ENC_SBOX[t0];
+    uint32_t     r = x;
+
+    r = (AES_GFMUL(x,3) << 24) |
+        (          x    << 16) |
+        (          x    <<  8) |
+        (AES_GFMUL(x,2) <<  0) ;
+
+    r = (r << (8*bs)) | (r >> (32-8*bs));
+    return (r ^ a);
+}
+
+uint32_t gold_sha256sum0(uint32_t a){
+    uint32_t     r = ROR32(a,  2) ^ ROR32(a,13) ^ ROR32(a, 22);
+    return r;
+}
+uint32_t gold_sha256sum1(uint32_t a){
+    uint32_t     r = ROR32(a,  6) ^ ROR32(a,11) ^ ROR32(a, 25);
+    return r;
+}
+uint32_t gold_sha256sig0(uint32_t a){
+    uint32_t     r = ROR32(a,  7) ^ ROR32(a,18) ^ (a >> 3);
+    return r;
+}
+uint32_t gold_sha256sig1(uint32_t a){
+    uint32_t     r = ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10);
+    return r;
+}
+uint32_t gold_sha512sum0r(uint32_t a, uint32_t b){
+    uint32_t     r = (a << 25) ^ (a << 30) ^ (a >> 28) ^
+                     (b >>  7) ^ (b >>  2) ^ (b <<  4);
+    return r;
+}
+uint32_t gold_sha512sum1r(uint32_t a, uint32_t b){
+    uint32_t     r = (a << 23) ^ (a >> 14) ^ (a >> 18) ^
+                     (b >>  9) ^ (b << 18) ^ (b << 14);
+    return r;
+}
+uint32_t gold_sha512sig0l(uint32_t a, uint32_t b){
+    uint32_t     r = (a >>  1) ^ (a >>  7) ^ (a >>  8) ^
+                     (b << 31) ^ (b << 25) ^ (b << 24);
+    return r;
+}
+uint32_t gold_sha512sig0h(uint32_t a, uint32_t b){
+    uint32_t     r = (a >>  1) ^ (a >>  7) ^ (a >>  8) ^
+                     (b << 31) ^             (b << 24);
+    return r;
+}
+uint32_t gold_sha512sig1l(uint32_t a, uint32_t b){
+    uint32_t     r = (a <<  3) ^ (a >>  6) ^ (a >> 19) ^
+                     (b >> 29) ^ (b << 26) ^ (b << 13);
+    return r;
+}
+uint32_t gold_sha512sig1h(uint32_t a, uint32_t b){
+    uint32_t     r = (a <<  3) ^ (a >>  6) ^ (a >> 19) ^
+                     (b >> 29) ^             (b << 13);
+    return r;
+}
+
+*/
+
+uint32_t gold_ror(uint32_t a, uint32_t b){
+    return ROR32(a, b & 0x0000001F);
+}
+
+uint32_t gold_rol(uint32_t a, uint32_t b){
+    return ROL32(a, b & 0x0000001F);
+}
+
+uint32_t gold_ror7(uint32_t a){
+    return ROR32(a,7);
+}
+
+uint32_t gold_andn(uint32_t a, uint32_t b){
+    return (a & (~b));
+}
+
+uint32_t gold_orn(uint32_t a, uint32_t b){
+    return (a | (~b));
+}
+
+uint32_t gold_xnor(uint32_t a, uint32_t b){
+    return (a ^ (~b));
+}
+
+uint32_t gold_pack(uint32_t a, uint32_t b){
+    return (b << 16) | (a & 0x0000FFFF);
+}
+
+uint32_t gold_packh(uint32_t a, uint32_t b){
+    return ((b << 8) | (a & 0x000000FF)) & 0x0000FFFF;
+}
+
+/*
+uint32_t gold_brev8(uint32_t a){
+    uint32_t  x;
+    x = ((a & 0x55555555) <<  1) | ((a & 0xAAAAAAAA) >>  1);
+    x = ((x & 0x33333333) <<  2) | ((x & 0xCCCCCCCC) >>  2);
+    x = ((x & 0x0F0F0F0F) <<  4) | ((x & 0xF0F0F0F0) >>  4);
+    return x;
+}
+uint32_t gold_rev8(uint32_t a){
+    uint32_t  x;
+    x = ((a & 0x00FF00FF) <<  8) | ((a & 0xFF00FF00) >>  8);
+    x = ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+    return x;
+}
+
+uint32_t shfl_st(uint32_t src, uint32_t maskL, uint32_t maskR, int N)
+{
+    uint32_t x = src & ~(maskL | maskR);
+    x |= ((src << N) & maskL) | ((src >> N) & maskR);
+    return x;
+}
+
+
+uint32_t gold_unzip(uint32_t a){
+    uint32_t  x=a;
+    x = shfl_st(x, 0x44444444, 0x22222222, 1);
+    x = shfl_st(x, 0x30303030, 0x0C0C0C0C, 2);
+    x = shfl_st(x, 0x0F000F00, 0x00F000F0, 4);
+    x = shfl_st(x, 0x00FF0000, 0x0000FF00, 8);
+    return x;
+}
+
+uint32_t gold_zip(uint32_t a){
+    uint32_t  x=a;
+    x = shfl_st(x, 0x00FF0000, 0x0000FF00, 8);
+    x = shfl_st(x, 0x0F000F00, 0x00F000F0, 4);
+    x = shfl_st(x, 0x30303030, 0x0C0C0C0C, 2);
+    x = shfl_st(x, 0x44444444, 0x22222222, 1);
+    return x;
+}
+
+
+uint32_t gold_xperm8(uint32_t a,uint32_t b){
+    uint32_t  lut[256];
+    uint32_t  idx[4];
+ 
+    for (int i =0;i<256;i++){
+        if (i<4){
+        	lut[i] = (a>>(8*i)) & 0xFF;
+        	idx[i] = (b>>(8*i)) & 0xFF;
+		} else {
+            lut[i] = 0;
+		}
+    }
+    uint32_t x = (lut[idx[3]] << 24) | (lut[idx[2]] << 16) | (lut[idx[1]] << 8) | lut[idx[0]];
+    return x;
+}
+
+uint32_t gold_xperm4(uint32_t a,uint32_t b){
+    uint32_t  lut[16];
+    uint32_t  idx[8];
+ 
+    for (int i =0;i<16;i++){
+        if (i<8){
+          lut[i] = (a>>(4*i)) & 0xF;
+          idx[i] = (b>>(4*i)) & 0xF;
+        } else {
+           lut[i] = 0;
+        }
+    }
+    uint32_t x = 0;
+    for (int i =0;i<8;i++) x |= (lut[idx[i]] << (4*i));
+    return x;
+}
+
+uint32_t gold_clmul(uint32_t a,uint32_t b){
+    uint32_t x = 0;
+    for (int i = 0; i < 32; i++)
+        if ((b >> i) & 1) x ^= a << i;
+    return x;
+}
+
+uint32_t gold_clmulh(uint32_t a,uint32_t b){
+    uint32_t x = 0;
+    for (int i = 1; i < 32; i++)
+        if ((b >> i) & 1) x ^= a >> (32-i);
+    return x;
+}
+
+*/
+
+//void error_log(uint32_t expect, uint32_t result){
+//puts("Expected: "); puthex(expect); puts(", got:"); puthex(result); putchar('\n');
+//}
+int fail;
+uint32_t expect, result;
+
+int main() {
+    volatile unsigned int *tohost = (unsigned int*)0x7FC;
+    fail = 0;
+
+    uint32_t lhs = 0x23456789;
+    uint32_t rhs = 0x01020304;
+
+    //puts("# RV32Zkn Instruction Test \n");
+    for (int i=0;i<2;i++){
+    // puts("lhs: "); puthex(lhs); puts(", rhs:"); puthex(rhs); putchar('\n');
+/*
+    // aes32dsi1    
+    result = test_aes32dsi1(lhs, rhs);
+    expect = gold_aes32dsi( lhs, rhs, 1);
+
+    if(result != expect) {
+        //puts("test_aes32dsi1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // aes32esi1
+    result = test_aes32esi1(lhs, rhs);
+    expect = gold_aes32esi( lhs, rhs, 1);
+
+    if(result != expect) {
+        //puts("test_aes32esi1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // aes32dsmi1
+    result = test_aes32dsmi1(lhs, rhs);
+    expect = gold_aes32dsmi( lhs, rhs, 1);
+
+    if(result != expect) {
+        //puts("test_aes32dsmi1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // aes32esmi1
+    result = test_aes32esmi1(lhs, rhs);
+    expect = gold_aes32esmi( lhs, rhs, 1);
+
+    if(result != expect) {
+        //puts("test_aes32esmi1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha256sum0
+    result = test_sha256sum0(lhs);
+    expect = gold_sha256sum0(lhs);
+
+    if(result != expect) {
+        //puts("test_sha256sum0 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha256sum1
+    result = test_sha256sum1(lhs);
+    expect = gold_sha256sum1(lhs);
+
+    if(result != expect) {
+        //puts("test_sha256sum1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha256sig0
+    result = test_sha256sig0(lhs);
+    expect = gold_sha256sig0(lhs);
+
+    if(result != expect) {
+        //puts("test_sha256sig0 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha256sig1
+    result = test_sha256sig1(lhs);
+    expect = gold_sha256sig1(lhs);
+
+    if(result != expect) {
+        //puts("test_sha256sig1 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha512sum0r
+    result = test_sha512sum0r(lhs, rhs);
+    expect = gold_sha512sum0r(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sum0r [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha512sum1r
+    result = test_sha512sum1r(lhs, rhs);
+    expect = gold_sha512sum1r(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sum1r [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha512sig0l
+    result = test_sha512sig0l(lhs, rhs);
+    expect = gold_sha512sig0l(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sig0l [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+    // sha512sig0h
+    result = test_sha512sig0h(lhs, rhs);
+    expect = gold_sha512sig0h(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sig0h [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // sha512sig1l
+    result = test_sha512sig1l(lhs, rhs);
+    expect = gold_sha512sig1l(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sig1l [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+    // sha512sig1h
+    result = test_sha512sig1h(lhs, rhs);
+    expect = gold_sha512sig1h(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_sha512sig1h [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+*/
+    // ror    
+    result = test_ror(lhs, rhs);
+    expect = gold_ror(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_ror [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // rol
+    result = test_rol(lhs, rhs);
+    expect = gold_rol(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_rol [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // ror7
+    result = test_ror7(lhs);
+    expect = gold_ror7(lhs);
+
+    if(result != expect) {
+        //puts("test_ror7 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // andn
+    result = test_andn(lhs, rhs);
+    expect = gold_andn(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_andn [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // orn
+    result = test_orn(lhs, rhs);
+    expect = gold_orn(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_orn [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // xnor
+    result = test_xnor(lhs, rhs);
+    expect = gold_xnor(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_xnor [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // pack
+    result = test_pack(lhs, rhs);
+    expect = gold_pack(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_pack [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // packh
+    result = test_packh(lhs, rhs);
+    expect = gold_packh(lhs, rhs);
+
+    if(result != expect) {
+        //puts("test_packh [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+/*
+    // brev8
+    result = test_brev8(lhs);
+    expect = gold_brev8(lhs);
+
+    if(result != expect) {
+        //puts("test_brev8 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // rev8
+    result = test_rev8(lhs);
+    expect = gold_rev8(lhs);
+
+    if(result != expect) {
+        //puts("test_rev8 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // zip
+    result = test_zip(lhs);
+    expect = gold_zip(lhs);
+
+    if(result != expect) {
+        //puts("test_zip [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // unzip
+    result = test_unzip(lhs);
+    expect = gold_unzip(lhs);
+
+    if(result != expect) {
+        //puts("test_unzip [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // xperm8
+   result = test_xperm8(lhs,rhs);
+   expect = gold_xperm8(lhs,rhs);
+
+    if(result != expect) {
+        //puts("test_xperm8 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+    // xperm4
+    result = test_xperm4(lhs,rhs);
+    expect = gold_xperm4(lhs,rhs);
+
+    if(result != expect) {
+        //puts("test_xperm4 [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+
+    // clmul
+    result = test_clmul(lhs,rhs);
+    expect = gold_clmul(lhs,rhs);
+
+    if(result != expect) {
+        //puts("test_clmul [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+    // clmulh
+    result = test_clmulh(lhs,rhs);
+    expect = gold_clmulh(lhs,rhs);
+
+    if(result != expect) {
+        //puts("test_clmulh [FAIL]\n");
+        //error_log(expect,result);
+        fail = 1;
+    }
+*/
+    rhs = lfsr(lhs);
+    lhs = lfsr(rhs);
+    }
+
+    if (fail == 0) *tohost = 0XCAFEBABE;    //Pass the test
+    else           *tohost = 0XDEADBEEF;    //The test fails
+
+    return fail;
+
+}
+
diff --git a/verilog/dv/wb_test_icesoc/ibex_prog/zkn.h b/verilog/dv/wb_test_icesoc/ibex_prog/zkn.h
new file mode 100644
index 0000000..e3c0d09
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/ibex_prog/zkn.h
@@ -0,0 +1,214 @@
+// Copyright (C) 2021 SCARV project <info@scarv.org>
+//
+// Use of this source code is restricted per the MIT license, a copy of which 
+// can be found at https://opensource.org/licenses/MIT (or should be included 
+// as LICENSE.txt within the associated archive or repository).
+
+#ifndef __ZKN
+#define __ZKN
+
+// Zknh =======================================================================
+
+// 000 1000 | 00000 | rs1 | 001 | rd | 001 0011
+.macro sha256sum0 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x100
+.endm
+// 000 1000 | 00001 | rs1 | 001 | rd | 001 0011
+.macro sha256sum1 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x101
+.endm
+// 000 1000 | 00010 | rs1 | 001 | rd | 001 0011
+.macro sha256sig0 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x102
+.endm
+// 000 1000 | 00011 | rs1 | 001 | rd | 001 0011
+.macro sha256sig1 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x103
+.endm
+// 000 1000 | 00100 | rs1 | 001 | rd | 001 0011
+.macro sha512sum0 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x104
+.endm
+// 000 1000 | 00101 | rs1 | 001 | rd | 001 0011
+.macro sha512sum1 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x105
+.endm
+// 000 1000 | 00110 | rs1 | 001 | rd | 001 0011
+.macro sha512sig0 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x106
+.endm
+// 000 1000 | 00111 | rs1 | 001 | rd | 001 0011
+.macro sha512sig1 rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x107
+.endm
+
+// 010 1000 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sum0r rd, rs1, rs2
+.insn r 0x33, 0x0, 0x28, \rd, \rs1, \rs2
+.endm
+// 010 1001 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sum1r rd, rs1, rs2
+.insn r 0x33, 0x0, 0x29, \rd, \rs1, \rs2
+.endm
+// 010 1010 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sig0l rd, rs1, rs2
+.insn r 0x33, 0x0, 0x2A, \rd, \rs1, \rs2
+.endm
+// 010 1011 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sig1l rd, rs1, rs2
+.insn r 0x33, 0x0, 0x2B, \rd, \rs1, \rs2
+.endm
+// 010 1110 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sig0h rd, rs1, rs2
+.insn r 0x33, 0x0, 0x2E, \rd, \rs1, \rs2
+.endm
+
+// 010 1111 | rs2   | rs1 | 000 | rd | 011 0011
+.macro sha512sig1h rd, rs1, rs2
+.insn r 0x33, 0x0, 0x2F, \rd, \rs1, \rs2
+.endm
+
+// ============================================================================
+
+// Zkne========================================================================
+
+// bs[1:0]1 0001 |  rs2   |  rs1  | 000 | rd | 0110011
+.macro aes32esi    rd, rs1, rs2, bs
+.insn r 0x33, 0x0, (\bs << 5) + 0x11, \rd, \rs1, \rs2
+.endm
+// bs[1:0]1 0011 |  rs2   |  rs1  | 000 | rd | 0110011
+.macro aes32esmi    rd, rs1, rs2, bs
+.insn r 0x33, 0x0, (\bs << 5) + 0x13, \rd, \rs1, \rs2
+.endm
+//      001 1001 |  rs2   |  rs1  | 000 | rd | 0010011 
+.macro aes64es   rd, rs1, rs2
+.insn r 0x33, 0x0,              0x19, \rd, \rs1, \rs2
+.endm
+//      001 1011 |  rs2   |  rs1  | 000 | rd | 0110011 
+.macro aes64esm  rd, rs1, rs2
+.insn r 0x33, 0x0,              0x1B, \rd, \rs1, \rs2
+.endm
+
+//     0011 0001 rnum[3:0]|  rs1  | 001 | rd | 0010011
+.macro aes64ks1i  rd, rs1, rnum
+.insn i 0x13, 0x1,                    \rd, \rs1, (0x31 << 4) + \rnum
+.endm
+//      011 1111 |  rs2   |  rs1  | 000 | rd | 0110011
+.macro aes64ks2 rd, rs1, rs2
+.insn r 0x33, 0x0,              0x3F, \rd, \rs1, \rs2
+.endm
+
+// ============================================================================
+
+// Zknd =======================================================================
+
+// bs[1:0]1 0101 |  rs2   |  rs1  | 000 | rd | 0110011
+.macro aes32dsi    rd, rs1, rs2, bs
+.insn r 0x33, 0x0, (\bs << 5) + 0x15, \rd, \rs1, \rs2
+.endm
+// bs[1:0]1 0111 |  rs2   |  rs1  | 000 | rd | 0110011
+.macro aes32dsmi    rd, rs1, rs2, bs
+.insn r 0x33, 0x0, (\bs << 5) + 0x17, \rd, \rs1, \rs2
+.endm
+//      001 1101 |  rs2   |  rs1  | 000 | rd | 0110011 
+.macro aes64ds   rd, rs1, rs2
+.insn r 0x33, 0x0,              0x1D, \rd, \rs1, \rs2
+.endm
+//      001 1111 |  rs2   |  rs1  | 000 | rd | 0110011 
+.macro aes64dsm  rd, rs1, rs2
+.insn r 0x33, 0x0,              0x1F, \rd, \rs1, \rs2
+.endm
+//      0011 0000 0000    |  rs1  | 001 | rd | 0010011 
+.macro aes64im   rd, rs1
+.insn i 0x13, 0x1,                    \rd, \rs1, 0x300
+.endm
+
+// ============================================================================
+
+// Zkb ========================================================================
+
+// 011 0000 | rs2   | rs1 | 101 | rd | 0110011
+.macro ror    rd, rs1, rs2
+.insn r 0x33, 0x5, 0x30, \rd, \rs1, \rs2
+.endm
+// 011 0000 | rs2   | rs1 | 001 | rd | 0110011
+.macro rol    rd, rs1, rs2
+.insn r 0x33, 0x1, 0x30, \rd, \rs1, \rs2
+.endm
+// 011 0000 | shamt | rs1 | 101 | rd | 0010011 (32-bit)
+.macro rori   rd, rs1, shamt
+.insn i 0x13, 0x5, \rd, \rs1, \shamt + ( 0x30 << 5 )
+.endm
+// 011 0000 | rs2 | rs1   | 101 | rd | 0111011
+.macro rorw  rd, rs1, rs2
+.insn r 0x3B, 0x5, 0x30, \rd, \rs1, \rs2
+.endm
+
+// 010 0000 | rs2 | rs1   | 111 | rd | 0110011
+.macro andn   rd, rs1, rs2
+.insn r 0x33, 0x7, 0x20, \rd, \rs1, \rs2
+.endm
+// 010 0000 | rs2 | rs1   | 111 | rd | 0110011
+.macro  orn   rd, rs1, rs2
+.insn r 0x33, 0x6, 0x20, \rd, \rs1, \rs2
+.endm
+// 010 0000 | rs2 | rs1   | 111 | rd | 0110011
+.macro xnor   rd, rs1, rs2
+.insn r 0x33, 0x4, 0x20, \rd, \rs1, \rs2
+.endm
+// 000 0100 | rs2 | rs1   | 100 | rd | 0110011
+.macro pack   rd, rs1, rs2
+.insn r 0x33, 0x4, 0x04, \rd, \rs1, \rs2
+.endm
+// 000 0100 | rs2 | rs1   | 100 | rd | 0110011
+.macro packh  rd, rs1, rs2
+.insn r 0x33, 0x7, 0x04, \rd, \rs1, \rs2
+.endm
+
+// 0110 1000 0111 | rs1   | 101 | rd | 0010011
+.macro brev8  rd, rs1
+.insn i 0x13, 0x5, \rd, \rs1, 0x687
+.endm
+// 0110 1001 1000 | rs1   | 101 | rd | 0010011 (32-bit)
+.macro  rev8  rd, rs1
+.insn i 0x13, 0x5, \rd, \rs1, 0x698
+.endm
+
+// 0000 1000 1111 | rs1   | 001 | rd | 0010011
+.macro   zip rd, rs1
+.insn i 0x13, 0x1, \rd, \rs1, 0x08F
+.endm
+// 0000 1000 1111 | rs1   | 101 | rd | 0010011
+.macro unzip rd, rs1
+.insn i 0x13, 0x5, \rd, \rs1, 0x08F
+.endm
+
+// ============================================================================
+
+// Zkc ========================================================================
+
+// 000 0101 | rs2   | rs1 | 001 | rd | 011 0011
+.macro clmul rd, rs1, rs2
+.insn r 0x33, 0x1, 0x05, \rd, \rs1, \rs2
+.endm
+// 000 0101 | rs2   | rs1 | 011 | rd | 011 0011
+.macro clmulh rd, rs1, rs2
+.insn r 0x33, 0x3, 0x05, \rd, \rs1, \rs2
+.endm
+
+// ============================================================================
+
+// Zkx ========================================================================
+
+// 001 0100 | rs2   | rs1 | 010 | rd | 011 0011
+.macro xperm4 rd, rs1, rs2
+.insn r 0x33, 0x2, 0x14, \rd, \rs1, \rs2
+.endm
+// 001 0100 | rs2   | rs1 | 100 | rd | 011 0011
+.macro xperm8 rd, rs1, rs2
+.insn r 0x33, 0x4, 0x14, \rd, \rs1, \rs2
+.endm
+
+// ============================================================================
+
+#endif
diff --git a/verilog/dv/wb_test_icesoc/wb_test_icesoc.c b/verilog/dv/wb_test_icesoc/wb_test_icesoc.c
new file mode 100644
index 0000000..77ccdf7
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/wb_test_icesoc.c
@@ -0,0 +1,117 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+#include "ibex_prog.h"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+int i = 0; 
+int chk = 0;
+
+void main()
+{
+
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_1  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_2  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_3  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_4  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_5  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_6  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_7  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	reg_mprj_io_8  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_9  =  GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_10 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_11 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_12 =  GPIO_MODE_USER_STD_OUTPUT;
+
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Flag start of the test
+    reg_mprj_datal = 0x00010000;
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+
+    // Flag stop ibex_core to program
+    reg_mprj_datal = 0x00020000;
+
+    uint32_t * sram = (uint32_t *) &reg_mprj_slave;
+
+    //writting data to sram
+    for (i = 0; i< pro_len-32;i++) {
+        sram[i+32] = pro_data[i+32];
+    }
+    sram[511] =0;
+    // Flag run ibex_core
+    reg_mprj_datal = 0x00030000;
+
+    while (1) {
+       if       (sram[511] == 0xDEADBEEF)  reg_mprj_datal = 0x00040000; // simulation end with failed test
+       else if  (sram[511] == 0xCAFEBABE)  reg_mprj_datal = 0x00050000; // simulation end with successful test
+    }
+}   
diff --git a/verilog/dv/wb_test_icesoc/wb_test_icesoc_tb.v b/verilog/dv/wb_test_icesoc/wb_test_icesoc_tb.v
new file mode 100644
index 0000000..b26d03a
--- /dev/null
+++ b/verilog/dv/wb_test_icesoc/wb_test_icesoc_tb.v
@@ -0,0 +1,174 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module wb_test_icesoc_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+
+	//assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+                $dumpfile("wb_test_icesoc.vcd");
+                $dumpvars(0, wb_test_icesoc_tb.uut.mprj);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+                repeat (700) begin
+			repeat (1000) @(posedge clock);
+                        $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+        reg [31:0] checkpoint;
+        reg [ 7:0] ibex_ctrl;
+	initial begin        
+           ibex_ctrl = 8'b0000_0110;
+	   wait(checkbits == 16'h0001);
+	   $display("Monitor: MPRJ-Logic WB Started");
+	   wait(checkbits == 16'h0002);
+	   $display("Monitor: Program ibex");
+           wait(checkbits == 16'h0003);
+	   $display("Monitor: Start ibex");
+           ibex_ctrl = 8'b0010_0110;
+	end
+
+        initial begin
+           wait(checkbits == 16'h0004);
+           $display ("Monitor: ibex Failed");
+           #7000;
+           $finish;
+        end
+
+        initial begin
+           wait(checkbits == 16'h0005);
+           $display ("Monitor: ibex Passed");
+           #7000;
+           $finish;
+        end
+
+	assign mprj_io[7:0] = ibex_ctrl;
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+        wire wclock =clock;
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (USER_VDD3V3),
+		.vdda2    (USER_VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (USER_VDD1V8),
+		.vccd2	  (USER_VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (wclock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+                .FILENAME("wb_test_icesoc.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_to_sram/Makefile b/verilog/dv/wb_to_sram/Makefile
new file mode 100644
index 0000000..829ad50
--- /dev/null
+++ b/verilog/dv/wb_to_sram/Makefile
@@ -0,0 +1,108 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK 
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_BEHAVIOURAL_MODELS = ../
+UPRJ_RTL_PATH      = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_RTL_ICESOC    = $(UPRJ_VERILOG_PATH)/rtl/icesoc
+UPRJ_RTL_IBEXCORE  = $(UPRJ_VERILOG_PATH)/rtl/ibex_core
+UPRJ_RTL_EFPGACORE = $(UPRJ_VERILOG_PATH)/rtl/eFPGA_core
+UPRJ_RTL_EFPGACONF = $(UPRJ_VERILOG_PATH)/rtl/eFPGA_conf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_to_sram
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(UPRJ_BEHAVIOURAL_MODELS) \
+	-I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_RTL_ICESOC) \
+	-I $(UPRJ_RTL_IBEXCORE) \
+	-I $(UPRJ_RTL_EFPGACORE) \
+	-I $(UPRJ_RTL_EFPGACONF) \
+	$< -o $@ -g2012
+else  
+	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(UPRJ_BEHAVIOURAL_MODELS) \
+	-I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_RTL_ICESOC) \
+	-I $(UPRJ_RTL_IBEXCORE) \
+	-I $(UPRJ_RTL_EFPGACORE) \
+	-I $(UPRJ_RTL_EFPGACONF) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/wb_to_sram/wb_to_sram.c b/verilog/dv/wb_to_sram/wb_to_sram.c
new file mode 100644
index 0000000..fd864c8
--- /dev/null
+++ b/verilog/dv/wb_to_sram/wb_to_sram.c
@@ -0,0 +1,98 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+int i = 0; 
+int chk = 0;
+
+void main()
+{
+
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+
+    // Flag start of the test
+	reg_mprj_datal = 0xAB600000;
+
+    uint32_t * sram = (uint32_t *) &reg_mprj_slave;
+
+    //writting data to sram
+    for (i = 0; i<128;i++) {
+        sram[i] = 0xCAFEBABE;
+    }
+
+    //reading data from sram
+    for (i = 0; i<128;i++) {
+        if (sram[i] != 0xCAFEBABE) {
+            reg_mprj_datal = 0xAB620000;
+            chk = 1;
+        }
+    }
+    if (chk == 0)  reg_mprj_datal = 0xAB610000;
+}   
diff --git a/verilog/dv/wb_to_sram/wb_to_sram.hex b/verilog/dv/wb_to_sram/wb_to_sram.hex
new file mode 100755
index 0000000..38a5cff
--- /dev/null
+++ b/verilog/dv/wb_to_sram/wb_to_sram.hex
@@ -0,0 +1,57 @@
+@00000000
+81 40 81 41 01 42 81 42 01 43 81 43 01 44 81 44
+01 45 81 45 01 46 81 46 01 47 81 47 01 48 81 48
+01 49 81 49 01 4A 81 4A 01 4B 81 4B 01 4C 81 4C
+01 4D 81 4D 01 4E 81 4E 01 4F 81 4F 17 05 00 00
+13 05 85 31 93 05 00 00 13 06 40 00 63 D8 C5 00
+14 41 94 C1 11 05 91 05 E3 CC C5 FE 13 05 40 00
+93 05 C0 00 63 57 B5 00 23 20 05 00 11 05 E3 4D
+B5 FE 19 22 01 A0 01 00 B7 02 00 28 13 03 00 12
+23 90 62 00 A3 81 02 00 05 C6 21 4F 93 73 F6 0F
+93 DE 73 00 23 80 D2 01 93 EE 0E 01 23 80 D2 01
+86 03 93 F3 F3 0F 7D 1F E3 14 0F FE 23 80 62 00
+A1 C9 13 0F 00 02 83 23 05 00 A1 4F 93 DE F3 01
+23 80 D2 01 93 EE 0E 01 23 80 D2 01 83 CE 02 00
+93 FE 2E 00 93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F
+63 17 0F 00 23 20 75 00 11 05 83 23 05 00 FD 1F
+E3 96 0F FC FD 15 F1 F1 63 04 0F 00 23 20 75 00
+13 03 00 08 A3 81 62 00 82 80 01 00 00 00 01 11
+06 CE 22 CC 00 10 AA 87 A3 07 F4 FE 03 47 F4 FE
+A9 47 63 14 F7 00 35 45 DD 37 B7 07 00 20 91 07
+03 47 F4 FE 98 C3 01 00 F2 40 62 44 05 61 82 80
+01 11 06 CE 22 CC 00 10 23 26 A4 FE 19 A8 83 27
+C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00 3E 85
+7D 37 83 27 C4 FE 83 C7 07 00 F5 F3 01 00 01 00
+F2 40 62 44 05 61 82 80 41 11 22 C6 00 08 B7 07
+00 24 29 67 09 07 98 C3 B7 07 00 26 93 87 07 0A
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 09
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 09
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 09
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 09
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 08
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 08
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 08
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 08
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 07
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 07
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 07
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 07
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 06
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 06
+09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 06
+09 67 13 07 97 80 98 C3 B7 07 00 26 05 47 98 C3
+01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07
+00 25 13 87 87 02 FD 57 1C C3 37 07 00 25 61 07
+1C C3 B7 07 00 26 B1 07 37 07 60 AB 98 C3 23 22
+00 00 15 A0 03 27 00 00 83 27 40 00 8A 07 BA 97
+37 C7 FE CA 13 07 E7 AB 98 C3 83 27 40 00 13 87
+17 00 23 22 E0 00 03 27 40 00 A5 47 E3 DC E7 FC
+23 22 00 00 2D A8 03 27 00 00 83 27 40 00 8A 07
+BA 97 98 43 B7 C7 FE CA 93 87 E7 AB 63 0B F7 00
+B7 07 00 26 B1 07 37 07 62 AB 98 C3 05 47 23 24
+E0 00 83 27 40 00 13 87 17 00 23 22 E0 00 03 27
+40 00 A5 47 E3 D1 E7 FC 83 27 80 00 99 E7 B7 07
+00 26 B1 07 37 07 61 AB 98 C3 01 00 32 44 41 01
+82 80 00 00
+@10000354
+00 00 00 30
diff --git a/verilog/dv/wb_to_sram/wb_to_sram_tb.v b/verilog/dv/wb_to_sram/wb_to_sram_tb.v
new file mode 100644
index 0000000..d4d1ee1
--- /dev/null
+++ b/verilog/dv/wb_to_sram/wb_to_sram_tb.v
@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module wb_to_sram_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+
+	//assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+        assign mprj_io[7:0] = 8'b0000_0110;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+                $dumpfile("wb_to_sram.vcd");
+                $dumpvars(0, wb_to_sram_tb.uut.mprj);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+                repeat (300) begin
+			repeat (1000) @(posedge clock);
+                        $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+	   wait(checkbits == 16'h AB60);
+		$display("Monitor: MPRJ-Logic WB Started");
+		wait(checkbits == 16'h AB61);
+		`ifdef GL
+	    	$display("Monitor: Mega-Project WB (GL) Passed");
+		`else
+		    $display("Monitor: Mega-Project WB (RTL) Passed");
+		`endif
+	    $finish;
+	end
+
+        initial begin
+            wait(checkbits == 16'h AB60);
+            //$display("Monitor: MPRJ-Logic WB Started");
+            wait(checkbits == 16'h AB62);
+            `ifdef GL
+                $display("Monitor: Mega-Project WB (GL) reading back Failed");
+            `else
+                $display("Monitor: Mega-Project WB (RTL) reading back Failed");
+            `endif
+            $finish;
+        end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+        wire wclock =clock;
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (USER_VDD3V3),
+		.vdda2    (USER_VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (USER_VDD1V8),
+		.vccd2	  (USER_VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (wclock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+                .FILENAME("wb_to_sram.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/eFPGA_CPU_top.v b/verilog/rtl/eFPGA_CPU_top.v
new file mode 100644
index 0000000..8da90bf
--- /dev/null
+++ b/verilog/rtl/eFPGA_CPU_top.v
@@ -0,0 +1,1157 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+// 2021 Andrew Attwood
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+`ifndef USEeFPGA
+  `define USEeFPGA 0
+`endif
+
+`default_nettype none
+
+module eFPGA_CPU_top (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    output [2:0] la_data_out,
+    input  [3:0] la_data_in,
+
+    // IOs
+    input  [37:0] io_in, //CLK: [2:0] eFPGA: [12:3]
+    output [37:0] io_out, //CLK: [2:0] eFPGA: [12:3]
+    output [37:0] io_oeb, //CLK: [2:0] eFPGA: [12:3]
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2
+);
+
+localparam include_eFPGA    = `USEeFPGA;
+localparam NumberOfRows     = 14;
+localparam NumberOfCols     = 15;
+localparam FrameBitsPerRow  = 32;
+localparam MaxFramesPerCol  = 20;
+localparam desync_flag      = 20;
+localparam FrameSelectWidth =  5;
+localparam RowSelectWidth   =  5;
+
+assign io_oeb[ 7:0] =  8'b00000000; //CLK and configuration
+assign io_oeb[12:8] =  5'b11100; //CPU
+
+wire [1:0]  clk_sel = {io_in[2],io_in[1]};
+wire external_clock = io_in[0];
+// This clock can go to the CPU (connects to the fabric LUT output flops
+wire            CLK = clk_sel[0] ? (clk_sel[1] ? wb_clk_i : user_clock2) : external_clock;
+
+// To CPU
+wire [36-1:0] W_OPA; //from RISCV
+wire [36-1:0] W_OPB; //from RISCV
+wire [36-1:0] W_RES0; //to RISCV
+wire [36-1:0] W_RES1; //to RISCV
+wire [36-1:0] W_RES2; //to RISCV
+
+wire [36-1:0] E_OPA; //from RISCV
+wire [36-1:0] E_OPB; //from RISCV
+wire [36-1:0] E_RES0; //to RISCV
+wire [36-1:0] E_RES1; //to RISCV
+wire [36-1:0] E_RES2; //to RISCV
+
+// CPU configuration port
+wire [31:0] eFPGA_operand_a_1_o;
+wire [31:0] SelfWriteData; // configuration data write port
+wire        SelfWriteStrobe; // must decode address and write enable
+assign W_OPA[34:3]   = eFPGA_operand_a_1_o;
+assign SelfWriteData = eFPGA_operand_a_1_o;
+
+reg debug_req_1;
+reg fetch_enable_1;
+reg debug_req_2;
+reg fetch_enable_2;
+
+always @(*) begin
+	if(io_in[3] == 1'b1 )begin
+		debug_req_1 =  la_data_in[0];
+		fetch_enable_1 = la_data_in[1];
+		debug_req_2 = la_data_in[2];
+		fetch_enable_2 = la_data_in[3];
+	end 
+	else begin
+		debug_req_1 = io_in[4];
+		fetch_enable_1 = io_in[5];
+		debug_req_2 = io_in[6];
+		fetch_enable_2 = io_in[7];
+	end
+end 
+
+//CPU instantiation
+icesoc_top   icesoc_top_i (
+    //core 1
+    .debug_req_1_i(debug_req_1),       //todo needs LA in PIN
+    .fetch_enable_1_i(fetch_enable_1), //todo needs LA in PIN
+    .irq_ack_1_o(W_OPA[0]),
+    .irq_1_i(W_RES1[33]),
+    .irq_id_1_i({W_RES1[32],W_RES0[35:32]}),
+    .irq_id_1_o(W_OPA[2:1]),
+    .eFPGA_operand_a_1_o(eFPGA_operand_a_1_o),
+    .eFPGA_operand_b_1_o(W_OPB[31:0]),
+    .eFPGA_result_a_1_i(W_RES0[31:0]),
+    .eFPGA_result_b_1_i(W_RES1[31:0]),
+    .eFPGA_result_c_1_i(W_RES2[31:0]),
+    .eFPGA_write_strobe_1_o(SelfWriteStrobe),//todo write strobe connection
+    .eFPGA_fpga_done_1_i(W_RES1[34]), 
+    .eFPGA_delay_1_o(W_OPB[33:32]),
+    .eFPGA_en_1_o(W_OPA[35]),
+    .eFPGA_operator_1_o(W_OPB[35:34]),
+
+    //Wishbone to carvel
+    .wb_clk_i(CLK), 
+    .wb_rst_i(wb_rst_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    //core 2
+    .debug_req_2_i(debug_req_2),       //todo needs LA in PIN
+    .fetch_enable_2_i(fetch_enable_2), //todo needs LA in PIN
+    .irq_ack_2_o(E_OPA[0]), 
+    .irq_2_i(E_RES1[33]),
+    .irq_id_2_i({E_RES1[32],E_RES0[35:32]}),
+    .irq_id_2_o(E_OPA[2:1]),
+    .eFPGA_operand_a_2_o(E_OPA[34:3]),
+    .eFPGA_operand_b_2_o(E_OPB[31:0]),
+    .eFPGA_result_a_2_i(E_RES0[31:0]),
+    .eFPGA_result_b_2_i(E_RES1[31:0]),
+    .eFPGA_result_c_2_i(E_RES2[31:0]),
+    .eFPGA_write_strobe_2_o(io_out[16]),
+    .eFPGA_fpga_done_2_i(E_RES1[34]),
+    .eFPGA_delay_2_o(E_OPB[33:32]),
+    .eFPGA_en_2_o(E_OPA[35]),
+    .eFPGA_operator_2_o(E_OPB[35:34]),
+
+    //uart pins to USER area off chip IO
+    .rxd_uart(io_in[8]),
+    .txd_uart(io_out[10]),
+    .rxd_uart_to_mem(io_in[9]),
+    .txd_uart_to_mem(io_out[11]),
+    .error_uart_to_mem(io_out[12])
+);
+generate
+    if (include_eFPGA == 0) begin : gen_eFPGA_tieoff
+        assign la_data_out[2:0] = 3'b000;
+        assign io_out[6]        = 1'b0;
+        assign io_out[26:17]    = 10'd0;
+        assign io_oeb[26:17]    = 10'd0; //eFPGA IO pins
+
+        assign W_RES0           = 36'd0; //to RISCV
+        assign W_RES1           = 36'd0; //to RISCV
+        assign W_RES2           = 36'd0; //to RISCV
+
+        assign E_RES0           = 36'd0; //to RISCV
+        assign E_RES1           = 36'd0; //to RISCV
+        assign E_RES2           = 36'd0; //to RISCV
+        wire [36-1:0] unused0   = W_OPA; //from RISCV
+        wire [36-1:0] unused1   = W_OPB; //from RISCV
+        wire [36-1:0] unused2   = E_OPA; //from RISCV
+        wire [36-1:0] unused3   = E_OPB; //from RISCV
+        wire [31  :0] unused4   = SelfWriteData;
+    end else begin                : gen_eFPGA
+        // UART configuration port
+        wire Rx;
+        wire ComActive;
+        wire ReceiveLED;
+
+        // BitBang configuration port
+        wire s_clk;
+        wire s_data;
+
+        //BlockRAM ports
+        wire [80-1:0] RAM2FAB_D;
+        wire [80-1:0] FAB2RAM_D;
+        wire [40-1:0] FAB2RAM_A;
+        wire [20-1:0] FAB2RAM_C;
+        wire [20-1:0] Config_accessC;
+
+        // External USER ports
+        //inout [16-1:0] PAD; // these are for Dirk and go to the pad ring
+        wire [10-1:0] I_top;
+        wire [10-1:0] T_top;
+        wire [10-1:0] O_top;
+        wire [20-1:0] A_config_C;
+        wire [20-1:0] B_config_C;
+
+        // Signal declarations
+        wire [(NumberOfRows*FrameBitsPerRow)-1:0] FrameRegister;
+        wire [(MaxFramesPerCol*NumberOfCols)-1:0] FrameSelect;
+        wire [(FrameBitsPerRow*(NumberOfRows+2))-1:0] FrameData;
+
+        wire [FrameBitsPerRow-1:0] FrameAddressRegister;
+        wire LongFrameStrobe;
+        wire [31:0] LocalWriteData;
+        wire LocalWriteStrobe;
+        wire [RowSelectWidth-1:0] RowSelect;
+
+        assign s_clk            = io_in[3];
+        assign s_data           = io_in[4];
+        assign Rx               = io_in[5];
+        assign io_out[6]        = ReceiveLED;
+        assign la_data_out[2:0] = {ReceiveLED, Rx, ComActive};
+
+        assign O_top = io_in[26:17];
+        assign io_out[26:17] = I_top;
+        assign io_oeb[26:17] = T_top; //eFPGA IO pins
+
+
+    Config Config_inst (
+        .CLK(CLK),
+	.Rx(Rx),
+	.ComActive(ComActive),
+	.ReceiveLED(ReceiveLED),
+	.s_clk(s_clk),
+	.s_data(s_data),
+	.SelfWriteData(SelfWriteData),
+	.SelfWriteStrobe(SelfWriteStrobe),
+	
+	.ConfigWriteData(LocalWriteData),
+	.ConfigWriteStrobe(LocalWriteStrobe),
+	
+        .FrameAddressRegister(FrameAddressRegister),
+	.LongFrameStrobe(LongFrameStrobe),
+        .RowSelect(RowSelect)
+    );
+
+    Frame_Data_Reg_0 Inst_Frame_Data_Reg_0 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[0*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_1 Inst_Frame_Data_Reg_1 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[1*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_2 Inst_Frame_Data_Reg_2 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[2*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_3 Inst_Frame_Data_Reg_3 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[3*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_4 Inst_Frame_Data_Reg_4 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[4*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_5 Inst_Frame_Data_Reg_5 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[5*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_6 Inst_Frame_Data_Reg_6 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[6*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_7 Inst_Frame_Data_Reg_7 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[7*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_8 Inst_Frame_Data_Reg_8 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[8*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_9 Inst_Frame_Data_Reg_9 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[9*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_10 Inst_Frame_Data_Reg_10 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[10*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_11 Inst_Frame_Data_Reg_11 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[11*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_12 Inst_Frame_Data_Reg_12 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[12*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Data_Reg_13 Inst_Frame_Data_Reg_13 (
+        .FrameData_I(LocalWriteData),
+        .FrameData_O(FrameRegister[13*FrameBitsPerRow+:FrameBitsPerRow]),
+        .RowSelect(RowSelect),
+        .CLK(CLK)
+    );
+
+    Frame_Select_0 Inst_Frame_Select_0 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[0*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_1 Inst_Frame_Select_1 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[1*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_2 Inst_Frame_Select_2 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[2*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_3 Inst_Frame_Select_3 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[3*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_4 Inst_Frame_Select_4 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[4*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_5 Inst_Frame_Select_5 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[5*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_6 Inst_Frame_Select_6 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[6*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_7 Inst_Frame_Select_7 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[7*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_8 Inst_Frame_Select_8 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[8*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_9 Inst_Frame_Select_9 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[9*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_10 Inst_Frame_Select_10 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[10*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_11 Inst_Frame_Select_11 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[11*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_12 Inst_Frame_Select_12 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[12*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_13 Inst_Frame_Select_13 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[13*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    Frame_Select_14 Inst_Frame_Select_14 (
+        .FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),
+        .FrameStrobe_O(FrameSelect[14*MaxFramesPerCol +: MaxFramesPerCol]),
+        .FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),
+        .FrameStrobe(LongFrameStrobe)
+    );
+
+    eFPGA Inst_eFPGA(
+        .Tile_X0Y10_A_I_top(I_top[9]),
+        .Tile_X0Y10_B_I_top(I_top[8]),
+        .Tile_X0Y11_A_I_top(I_top[7]),
+        .Tile_X0Y11_B_I_top(I_top[6]),
+        .Tile_X0Y12_A_I_top(I_top[5]),
+        .Tile_X0Y12_B_I_top(I_top[4]),
+        .Tile_X0Y13_A_I_top(I_top[3]),
+        .Tile_X0Y13_B_I_top(I_top[2]),
+        .Tile_X0Y14_A_I_top(I_top[1]),
+        .Tile_X0Y14_B_I_top(I_top[0]),
+
+        .Tile_X0Y10_A_T_top(T_top[9]),
+        .Tile_X0Y10_B_T_top(T_top[8]),
+        .Tile_X0Y11_A_T_top(T_top[7]),
+        .Tile_X0Y11_B_T_top(T_top[6]),
+        .Tile_X0Y12_A_T_top(T_top[5]),
+        .Tile_X0Y12_B_T_top(T_top[4]),
+        .Tile_X0Y13_A_T_top(T_top[3]),
+        .Tile_X0Y13_B_T_top(T_top[2]),
+        .Tile_X0Y14_A_T_top(T_top[1]),
+        .Tile_X0Y14_B_T_top(T_top[0]),
+
+        .Tile_X0Y10_A_O_top(O_top[9]),
+        .Tile_X0Y10_B_O_top(O_top[8]),
+        .Tile_X0Y11_A_O_top(O_top[7]),
+        .Tile_X0Y11_B_O_top(O_top[6]),
+        .Tile_X0Y12_A_O_top(O_top[5]),
+        .Tile_X0Y12_B_O_top(O_top[4]),
+        .Tile_X0Y13_A_O_top(O_top[3]),
+        .Tile_X0Y13_B_O_top(O_top[2]),
+        .Tile_X0Y14_A_O_top(O_top[1]),
+        .Tile_X0Y14_B_O_top(O_top[0]),
+
+        .Tile_X0Y10_A_config_C_bit0(A_config_C[19]),
+        .Tile_X0Y10_A_config_C_bit1(A_config_C[18]),
+        .Tile_X0Y10_A_config_C_bit2(A_config_C[17]),
+        .Tile_X0Y10_A_config_C_bit3(A_config_C[16]),
+        .Tile_X0Y11_A_config_C_bit0(A_config_C[15]),
+        .Tile_X0Y11_A_config_C_bit1(A_config_C[14]),
+        .Tile_X0Y11_A_config_C_bit2(A_config_C[13]),
+        .Tile_X0Y11_A_config_C_bit3(A_config_C[12]),
+        .Tile_X0Y12_A_config_C_bit0(A_config_C[11]),
+        .Tile_X0Y12_A_config_C_bit1(A_config_C[10]),
+        .Tile_X0Y12_A_config_C_bit2(A_config_C[9]),
+        .Tile_X0Y12_A_config_C_bit3(A_config_C[8]),
+        .Tile_X0Y13_A_config_C_bit0(A_config_C[7]),
+        .Tile_X0Y13_A_config_C_bit1(A_config_C[6]),
+        .Tile_X0Y13_A_config_C_bit2(A_config_C[5]),
+        .Tile_X0Y13_A_config_C_bit3(A_config_C[4]),
+        .Tile_X0Y14_A_config_C_bit0(A_config_C[3]),
+        .Tile_X0Y14_A_config_C_bit1(A_config_C[2]),
+        .Tile_X0Y14_A_config_C_bit2(A_config_C[1]),
+        .Tile_X0Y14_A_config_C_bit3(A_config_C[0]),
+
+        .Tile_X0Y10_B_config_C_bit0(B_config_C[19]),
+        .Tile_X0Y10_B_config_C_bit1(B_config_C[18]),
+        .Tile_X0Y10_B_config_C_bit2(B_config_C[17]),
+        .Tile_X0Y10_B_config_C_bit3(B_config_C[16]),
+        .Tile_X0Y11_B_config_C_bit0(B_config_C[15]),
+        .Tile_X0Y11_B_config_C_bit1(B_config_C[14]),
+        .Tile_X0Y11_B_config_C_bit2(B_config_C[13]),
+        .Tile_X0Y11_B_config_C_bit3(B_config_C[12]),
+        .Tile_X0Y12_B_config_C_bit0(B_config_C[11]),
+        .Tile_X0Y12_B_config_C_bit1(B_config_C[10]),
+        .Tile_X0Y12_B_config_C_bit2(B_config_C[9]),
+        .Tile_X0Y12_B_config_C_bit3(B_config_C[8]),
+        .Tile_X0Y13_B_config_C_bit0(B_config_C[7]),
+        .Tile_X0Y13_B_config_C_bit1(B_config_C[6]),
+        .Tile_X0Y13_B_config_C_bit2(B_config_C[5]),
+        .Tile_X0Y13_B_config_C_bit3(B_config_C[4]),
+        .Tile_X0Y14_B_config_C_bit0(B_config_C[3]),
+        .Tile_X0Y14_B_config_C_bit1(B_config_C[2]),
+        .Tile_X0Y14_B_config_C_bit2(B_config_C[1]),
+        .Tile_X0Y14_B_config_C_bit3(B_config_C[0]),
+
+        .Tile_X3Y1_OPA_I0(W_OPA[35]),
+        .Tile_X3Y1_OPA_I1(W_OPA[34]),
+        .Tile_X3Y1_OPA_I2(W_OPA[33]),
+        .Tile_X3Y1_OPA_I3(W_OPA[32]),
+        .Tile_X3Y2_OPA_I0(W_OPA[31]),
+        .Tile_X3Y2_OPA_I1(W_OPA[30]),
+        .Tile_X3Y2_OPA_I2(W_OPA[29]),
+        .Tile_X3Y2_OPA_I3(W_OPA[28]),
+        .Tile_X3Y3_OPA_I0(W_OPA[27]),
+        .Tile_X3Y3_OPA_I1(W_OPA[26]),
+        .Tile_X3Y3_OPA_I2(W_OPA[25]),
+        .Tile_X3Y3_OPA_I3(W_OPA[24]),
+        .Tile_X3Y4_OPA_I0(W_OPA[23]),
+        .Tile_X3Y4_OPA_I1(W_OPA[22]),
+        .Tile_X3Y4_OPA_I2(W_OPA[21]),
+        .Tile_X3Y4_OPA_I3(W_OPA[20]),
+        .Tile_X3Y5_OPA_I0(W_OPA[19]),
+        .Tile_X3Y5_OPA_I1(W_OPA[18]),
+        .Tile_X3Y5_OPA_I2(W_OPA[17]),
+        .Tile_X3Y5_OPA_I3(W_OPA[16]),
+        .Tile_X3Y6_OPA_I0(W_OPA[15]),
+        .Tile_X3Y6_OPA_I1(W_OPA[14]),
+        .Tile_X3Y6_OPA_I2(W_OPA[13]),
+        .Tile_X3Y6_OPA_I3(W_OPA[12]),
+        .Tile_X3Y7_OPA_I0(W_OPA[11]),
+        .Tile_X3Y7_OPA_I1(W_OPA[10]),
+        .Tile_X3Y7_OPA_I2(W_OPA[9]),
+        .Tile_X3Y7_OPA_I3(W_OPA[8]),
+        .Tile_X3Y8_OPA_I0(W_OPA[7]),
+        .Tile_X3Y8_OPA_I1(W_OPA[6]),
+        .Tile_X3Y8_OPA_I2(W_OPA[5]),
+        .Tile_X3Y8_OPA_I3(W_OPA[4]),
+        .Tile_X3Y9_OPA_I0(W_OPA[3]),
+        .Tile_X3Y9_OPA_I1(W_OPA[2]),
+        .Tile_X3Y9_OPA_I2(W_OPA[1]),
+        .Tile_X3Y9_OPA_I3(W_OPA[0]),
+
+        .Tile_X3Y1_OPB_I0(W_OPB[35]),
+        .Tile_X3Y1_OPB_I1(W_OPB[34]),
+        .Tile_X3Y1_OPB_I2(W_OPB[33]),
+        .Tile_X3Y1_OPB_I3(W_OPB[32]),
+        .Tile_X3Y2_OPB_I0(W_OPB[31]),
+        .Tile_X3Y2_OPB_I1(W_OPB[30]),
+        .Tile_X3Y2_OPB_I2(W_OPB[29]),
+        .Tile_X3Y2_OPB_I3(W_OPB[28]),
+        .Tile_X3Y3_OPB_I0(W_OPB[27]),
+        .Tile_X3Y3_OPB_I1(W_OPB[26]),
+        .Tile_X3Y3_OPB_I2(W_OPB[25]),
+        .Tile_X3Y3_OPB_I3(W_OPB[24]),
+        .Tile_X3Y4_OPB_I0(W_OPB[23]),
+        .Tile_X3Y4_OPB_I1(W_OPB[22]),
+        .Tile_X3Y4_OPB_I2(W_OPB[21]),
+        .Tile_X3Y4_OPB_I3(W_OPB[20]),
+        .Tile_X3Y5_OPB_I0(W_OPB[19]),
+        .Tile_X3Y5_OPB_I1(W_OPB[18]),
+        .Tile_X3Y5_OPB_I2(W_OPB[17]),
+        .Tile_X3Y5_OPB_I3(W_OPB[16]),
+        .Tile_X3Y6_OPB_I0(W_OPB[15]),
+        .Tile_X3Y6_OPB_I1(W_OPB[14]),
+        .Tile_X3Y6_OPB_I2(W_OPB[13]),
+        .Tile_X3Y6_OPB_I3(W_OPB[12]),
+        .Tile_X3Y7_OPB_I0(W_OPB[11]),
+        .Tile_X3Y7_OPB_I1(W_OPB[10]),
+        .Tile_X3Y7_OPB_I2(W_OPB[9]),
+        .Tile_X3Y7_OPB_I3(W_OPB[8]),
+        .Tile_X3Y8_OPB_I0(W_OPB[7]),
+        .Tile_X3Y8_OPB_I1(W_OPB[6]),
+        .Tile_X3Y8_OPB_I2(W_OPB[5]),
+        .Tile_X3Y8_OPB_I3(W_OPB[4]),
+        .Tile_X3Y9_OPB_I0(W_OPB[3]),
+        .Tile_X3Y9_OPB_I1(W_OPB[2]),
+        .Tile_X3Y9_OPB_I2(W_OPB[1]),
+        .Tile_X3Y9_OPB_I3(W_OPB[0]),
+
+        .Tile_X3Y1_RES0_O0(W_RES0[35]),
+        .Tile_X3Y1_RES0_O1(W_RES0[34]),
+        .Tile_X3Y1_RES0_O2(W_RES0[33]),
+        .Tile_X3Y1_RES0_O3(W_RES0[32]),
+        .Tile_X3Y2_RES0_O0(W_RES0[31]),
+        .Tile_X3Y2_RES0_O1(W_RES0[30]),
+        .Tile_X3Y2_RES0_O2(W_RES0[29]),
+        .Tile_X3Y2_RES0_O3(W_RES0[28]),
+        .Tile_X3Y3_RES0_O0(W_RES0[27]),
+        .Tile_X3Y3_RES0_O1(W_RES0[26]),
+        .Tile_X3Y3_RES0_O2(W_RES0[25]),
+        .Tile_X3Y3_RES0_O3(W_RES0[24]),
+        .Tile_X3Y4_RES0_O0(W_RES0[23]),
+        .Tile_X3Y4_RES0_O1(W_RES0[22]),
+        .Tile_X3Y4_RES0_O2(W_RES0[21]),
+        .Tile_X3Y4_RES0_O3(W_RES0[20]),
+        .Tile_X3Y5_RES0_O0(W_RES0[19]),
+        .Tile_X3Y5_RES0_O1(W_RES0[18]),
+        .Tile_X3Y5_RES0_O2(W_RES0[17]),
+        .Tile_X3Y5_RES0_O3(W_RES0[16]),
+        .Tile_X3Y6_RES0_O0(W_RES0[15]),
+        .Tile_X3Y6_RES0_O1(W_RES0[14]),
+        .Tile_X3Y6_RES0_O2(W_RES0[13]),
+        .Tile_X3Y6_RES0_O3(W_RES0[12]),
+        .Tile_X3Y7_RES0_O0(W_RES0[11]),
+        .Tile_X3Y7_RES0_O1(W_RES0[10]),
+        .Tile_X3Y7_RES0_O2(W_RES0[9]),
+        .Tile_X3Y7_RES0_O3(W_RES0[8]),
+        .Tile_X3Y8_RES0_O0(W_RES0[7]),
+        .Tile_X3Y8_RES0_O1(W_RES0[6]),
+        .Tile_X3Y8_RES0_O2(W_RES0[5]),
+        .Tile_X3Y8_RES0_O3(W_RES0[4]),
+        .Tile_X3Y9_RES0_O0(W_RES0[3]),
+        .Tile_X3Y9_RES0_O1(W_RES0[2]),
+        .Tile_X3Y9_RES0_O2(W_RES0[1]),
+        .Tile_X3Y9_RES0_O3(W_RES0[0]),
+	
+        .Tile_X3Y1_RES1_O0(W_RES1[35]),
+        .Tile_X3Y1_RES1_O1(W_RES1[34]),
+        .Tile_X3Y1_RES1_O2(W_RES1[33]),
+        .Tile_X3Y1_RES1_O3(W_RES1[32]),
+        .Tile_X3Y2_RES1_O0(W_RES1[31]),
+        .Tile_X3Y2_RES1_O1(W_RES1[30]),
+        .Tile_X3Y2_RES1_O2(W_RES1[29]),
+        .Tile_X3Y2_RES1_O3(W_RES1[28]),
+        .Tile_X3Y3_RES1_O0(W_RES1[27]),
+        .Tile_X3Y3_RES1_O1(W_RES1[26]),
+        .Tile_X3Y3_RES1_O2(W_RES1[25]),
+        .Tile_X3Y3_RES1_O3(W_RES1[24]),
+        .Tile_X3Y4_RES1_O0(W_RES1[23]),
+        .Tile_X3Y4_RES1_O1(W_RES1[22]),
+        .Tile_X3Y4_RES1_O2(W_RES1[21]),
+        .Tile_X3Y4_RES1_O3(W_RES1[20]),
+        .Tile_X3Y5_RES1_O0(W_RES1[19]),
+        .Tile_X3Y5_RES1_O1(W_RES1[18]),
+        .Tile_X3Y5_RES1_O2(W_RES1[17]),
+        .Tile_X3Y5_RES1_O3(W_RES1[16]),
+        .Tile_X3Y6_RES1_O0(W_RES1[15]),
+        .Tile_X3Y6_RES1_O1(W_RES1[14]),
+        .Tile_X3Y6_RES1_O2(W_RES1[13]),
+        .Tile_X3Y6_RES1_O3(W_RES1[12]),
+        .Tile_X3Y7_RES1_O0(W_RES1[11]),
+        .Tile_X3Y7_RES1_O1(W_RES1[10]),
+        .Tile_X3Y7_RES1_O2(W_RES1[9]),
+        .Tile_X3Y7_RES1_O3(W_RES1[8]),
+        .Tile_X3Y8_RES1_O0(W_RES1[7]),
+        .Tile_X3Y8_RES1_O1(W_RES1[6]),
+        .Tile_X3Y8_RES1_O2(W_RES1[5]),
+        .Tile_X3Y8_RES1_O3(W_RES1[4]),
+        .Tile_X3Y9_RES1_O0(W_RES1[3]),
+        .Tile_X3Y9_RES1_O1(W_RES1[2]),
+        .Tile_X3Y9_RES1_O2(W_RES1[1]),
+        .Tile_X3Y9_RES1_O3(W_RES1[0]),
+	
+        .Tile_X3Y1_RES2_O0(W_RES2[35]),
+        .Tile_X3Y1_RES2_O1(W_RES2[34]),
+        .Tile_X3Y1_RES2_O2(W_RES2[33]),
+        .Tile_X3Y1_RES2_O3(W_RES2[32]),
+        .Tile_X3Y2_RES2_O0(W_RES2[31]),
+        .Tile_X3Y2_RES2_O1(W_RES2[30]),
+        .Tile_X3Y2_RES2_O2(W_RES2[29]),
+        .Tile_X3Y2_RES2_O3(W_RES2[28]),
+        .Tile_X3Y3_RES2_O0(W_RES2[27]),
+        .Tile_X3Y3_RES2_O1(W_RES2[26]),
+        .Tile_X3Y3_RES2_O2(W_RES2[25]),
+        .Tile_X3Y3_RES2_O3(W_RES2[24]),
+        .Tile_X3Y4_RES2_O0(W_RES2[23]),
+        .Tile_X3Y4_RES2_O1(W_RES2[22]),
+        .Tile_X3Y4_RES2_O2(W_RES2[21]),
+        .Tile_X3Y4_RES2_O3(W_RES2[20]),
+        .Tile_X3Y5_RES2_O0(W_RES2[19]),
+        .Tile_X3Y5_RES2_O1(W_RES2[18]),
+        .Tile_X3Y5_RES2_O2(W_RES2[17]),
+        .Tile_X3Y5_RES2_O3(W_RES2[16]),
+        .Tile_X3Y6_RES2_O0(W_RES2[15]),
+        .Tile_X3Y6_RES2_O1(W_RES2[14]),
+        .Tile_X3Y6_RES2_O2(W_RES2[13]),
+        .Tile_X3Y6_RES2_O3(W_RES2[12]),
+        .Tile_X3Y7_RES2_O0(W_RES2[11]),
+        .Tile_X3Y7_RES2_O1(W_RES2[10]),
+        .Tile_X3Y7_RES2_O2(W_RES2[9]),
+        .Tile_X3Y7_RES2_O3(W_RES2[8]),
+        .Tile_X3Y8_RES2_O0(W_RES2[7]),
+        .Tile_X3Y8_RES2_O1(W_RES2[6]),
+        .Tile_X3Y8_RES2_O2(W_RES2[5]),
+        .Tile_X3Y8_RES2_O3(W_RES2[4]),
+        .Tile_X3Y9_RES2_O0(W_RES2[3]),
+        .Tile_X3Y9_RES2_O1(W_RES2[2]),
+        .Tile_X3Y9_RES2_O2(W_RES2[1]),
+        .Tile_X3Y9_RES2_O3(W_RES2[0]),
+
+        .Tile_X11Y1_OPA_I0(E_OPA[35]),
+        .Tile_X11Y1_OPA_I1(E_OPA[34]),
+        .Tile_X11Y1_OPA_I2(E_OPA[33]),
+        .Tile_X11Y1_OPA_I3(E_OPA[32]),
+        .Tile_X11Y2_OPA_I0(E_OPA[31]),
+        .Tile_X11Y2_OPA_I1(E_OPA[30]),
+        .Tile_X11Y2_OPA_I2(E_OPA[29]),
+        .Tile_X11Y2_OPA_I3(E_OPA[28]),
+        .Tile_X11Y3_OPA_I0(E_OPA[27]),
+        .Tile_X11Y3_OPA_I1(E_OPA[26]),
+        .Tile_X11Y3_OPA_I2(E_OPA[25]),
+        .Tile_X11Y3_OPA_I3(E_OPA[24]),
+        .Tile_X11Y4_OPA_I0(E_OPA[23]),
+        .Tile_X11Y4_OPA_I1(E_OPA[22]),
+        .Tile_X11Y4_OPA_I2(E_OPA[21]),
+        .Tile_X11Y4_OPA_I3(E_OPA[20]),
+        .Tile_X11Y5_OPA_I0(E_OPA[19]),
+        .Tile_X11Y5_OPA_I1(E_OPA[18]),
+        .Tile_X11Y5_OPA_I2(E_OPA[17]),
+        .Tile_X11Y5_OPA_I3(E_OPA[16]),
+        .Tile_X11Y6_OPA_I0(E_OPA[15]),
+        .Tile_X11Y6_OPA_I1(E_OPA[14]),
+        .Tile_X11Y6_OPA_I2(E_OPA[13]),
+        .Tile_X11Y6_OPA_I3(E_OPA[12]),
+        .Tile_X11Y7_OPA_I0(E_OPA[11]),
+        .Tile_X11Y7_OPA_I1(E_OPA[10]),
+        .Tile_X11Y7_OPA_I2(E_OPA[9]),
+        .Tile_X11Y7_OPA_I3(E_OPA[8]),
+        .Tile_X11Y8_OPA_I0(E_OPA[7]),
+        .Tile_X11Y8_OPA_I1(E_OPA[6]),
+        .Tile_X11Y8_OPA_I2(E_OPA[5]),
+        .Tile_X11Y8_OPA_I3(E_OPA[4]),
+        .Tile_X11Y9_OPA_I0(E_OPA[3]),
+        .Tile_X11Y9_OPA_I1(E_OPA[2]),
+        .Tile_X11Y9_OPA_I2(E_OPA[1]),
+        .Tile_X11Y9_OPA_I3(E_OPA[0]),
+	
+        .Tile_X11Y1_OPB_I0(E_OPB[35]),
+        .Tile_X11Y1_OPB_I1(E_OPB[34]),
+        .Tile_X11Y1_OPB_I2(E_OPB[33]),
+        .Tile_X11Y1_OPB_I3(E_OPB[32]),
+        .Tile_X11Y2_OPB_I0(E_OPB[31]),
+        .Tile_X11Y2_OPB_I1(E_OPB[30]),
+        .Tile_X11Y2_OPB_I2(E_OPB[29]),
+        .Tile_X11Y2_OPB_I3(E_OPB[28]),
+        .Tile_X11Y3_OPB_I0(E_OPB[27]),
+        .Tile_X11Y3_OPB_I1(E_OPB[26]),
+        .Tile_X11Y3_OPB_I2(E_OPB[25]),
+        .Tile_X11Y3_OPB_I3(E_OPB[24]),
+        .Tile_X11Y4_OPB_I0(E_OPB[23]),
+        .Tile_X11Y4_OPB_I1(E_OPB[22]),
+        .Tile_X11Y4_OPB_I2(E_OPB[21]),
+        .Tile_X11Y4_OPB_I3(E_OPB[20]),
+        .Tile_X11Y5_OPB_I0(E_OPB[19]),
+        .Tile_X11Y5_OPB_I1(E_OPB[18]),
+        .Tile_X11Y5_OPB_I2(E_OPB[17]),
+        .Tile_X11Y5_OPB_I3(E_OPB[16]),
+        .Tile_X11Y6_OPB_I0(E_OPB[15]),
+        .Tile_X11Y6_OPB_I1(E_OPB[14]),
+        .Tile_X11Y6_OPB_I2(E_OPB[13]),
+        .Tile_X11Y6_OPB_I3(E_OPB[12]),
+        .Tile_X11Y7_OPB_I0(E_OPB[11]),
+        .Tile_X11Y7_OPB_I1(E_OPB[10]),
+        .Tile_X11Y7_OPB_I2(E_OPB[9]),
+        .Tile_X11Y7_OPB_I3(E_OPB[8]),
+        .Tile_X11Y8_OPB_I0(E_OPB[7]),
+        .Tile_X11Y8_OPB_I1(E_OPB[6]),
+        .Tile_X11Y8_OPB_I2(E_OPB[5]),
+        .Tile_X11Y8_OPB_I3(E_OPB[4]),
+        .Tile_X11Y9_OPB_I0(E_OPB[3]),
+        .Tile_X11Y9_OPB_I1(E_OPB[2]),
+        .Tile_X11Y9_OPB_I2(E_OPB[1]),
+        .Tile_X11Y9_OPB_I3(E_OPB[0]),
+	
+        .Tile_X11Y1_RES0_O0(E_RES0[35]),
+        .Tile_X11Y1_RES0_O1(E_RES0[34]),
+        .Tile_X11Y1_RES0_O2(E_RES0[33]),
+        .Tile_X11Y1_RES0_O3(E_RES0[32]),
+        .Tile_X11Y2_RES0_O0(E_RES0[31]),
+        .Tile_X11Y2_RES0_O1(E_RES0[30]),
+        .Tile_X11Y2_RES0_O2(E_RES0[29]),
+        .Tile_X11Y2_RES0_O3(E_RES0[28]),
+        .Tile_X11Y3_RES0_O0(E_RES0[27]),
+        .Tile_X11Y3_RES0_O1(E_RES0[26]),
+        .Tile_X11Y3_RES0_O2(E_RES0[25]),
+        .Tile_X11Y3_RES0_O3(E_RES0[24]),
+        .Tile_X11Y4_RES0_O0(E_RES0[23]),
+        .Tile_X11Y4_RES0_O1(E_RES0[22]),
+        .Tile_X11Y4_RES0_O2(E_RES0[21]),
+        .Tile_X11Y4_RES0_O3(E_RES0[20]),
+        .Tile_X11Y5_RES0_O0(E_RES0[19]),
+        .Tile_X11Y5_RES0_O1(E_RES0[18]),
+        .Tile_X11Y5_RES0_O2(E_RES0[17]),
+        .Tile_X11Y5_RES0_O3(E_RES0[16]),
+        .Tile_X11Y6_RES0_O0(E_RES0[15]),
+        .Tile_X11Y6_RES0_O1(E_RES0[14]),
+        .Tile_X11Y6_RES0_O2(E_RES0[13]),
+        .Tile_X11Y6_RES0_O3(E_RES0[12]),
+        .Tile_X11Y7_RES0_O0(E_RES0[11]),
+        .Tile_X11Y7_RES0_O1(E_RES0[10]),
+        .Tile_X11Y7_RES0_O2(E_RES0[9]),
+        .Tile_X11Y7_RES0_O3(E_RES0[8]),
+        .Tile_X11Y8_RES0_O0(E_RES0[7]),
+        .Tile_X11Y8_RES0_O1(E_RES0[6]),
+        .Tile_X11Y8_RES0_O2(E_RES0[5]),
+        .Tile_X11Y8_RES0_O3(E_RES0[4]),
+        .Tile_X11Y9_RES0_O0(E_RES0[3]),
+        .Tile_X11Y9_RES0_O1(E_RES0[2]),
+        .Tile_X11Y9_RES0_O2(E_RES0[1]),
+        .Tile_X11Y9_RES0_O3(E_RES0[0]),
+	
+        .Tile_X11Y1_RES1_O0(E_RES1[35]),
+        .Tile_X11Y1_RES1_O1(E_RES1[34]),
+        .Tile_X11Y1_RES1_O2(E_RES1[33]),
+        .Tile_X11Y1_RES1_O3(E_RES1[32]),
+        .Tile_X11Y2_RES1_O0(E_RES1[31]),
+        .Tile_X11Y2_RES1_O1(E_RES1[30]),
+        .Tile_X11Y2_RES1_O2(E_RES1[29]),
+        .Tile_X11Y2_RES1_O3(E_RES1[28]),
+        .Tile_X11Y3_RES1_O0(E_RES1[27]),
+        .Tile_X11Y3_RES1_O1(E_RES1[26]),
+        .Tile_X11Y3_RES1_O2(E_RES1[25]),
+        .Tile_X11Y3_RES1_O3(E_RES1[24]),
+        .Tile_X11Y4_RES1_O0(E_RES1[23]),
+        .Tile_X11Y4_RES1_O1(E_RES1[22]),
+        .Tile_X11Y4_RES1_O2(E_RES1[21]),
+        .Tile_X11Y4_RES1_O3(E_RES1[20]),
+        .Tile_X11Y5_RES1_O0(E_RES1[19]),
+        .Tile_X11Y5_RES1_O1(E_RES1[18]),
+        .Tile_X11Y5_RES1_O2(E_RES1[17]),
+        .Tile_X11Y5_RES1_O3(E_RES1[16]),
+        .Tile_X11Y6_RES1_O0(E_RES1[15]),
+        .Tile_X11Y6_RES1_O1(E_RES1[14]),
+        .Tile_X11Y6_RES1_O2(E_RES1[13]),
+        .Tile_X11Y6_RES1_O3(E_RES1[12]),
+        .Tile_X11Y7_RES1_O0(E_RES1[11]),
+        .Tile_X11Y7_RES1_O1(E_RES1[10]),
+        .Tile_X11Y7_RES1_O2(E_RES1[9]),
+        .Tile_X11Y7_RES1_O3(E_RES1[8]),
+        .Tile_X11Y8_RES1_O0(E_RES1[7]),
+        .Tile_X11Y8_RES1_O1(E_RES1[6]),
+        .Tile_X11Y8_RES1_O2(E_RES1[5]),
+        .Tile_X11Y8_RES1_O3(E_RES1[4]),
+        .Tile_X11Y9_RES1_O0(E_RES1[3]),
+        .Tile_X11Y9_RES1_O1(E_RES1[2]),
+        .Tile_X11Y9_RES1_O2(E_RES1[1]),
+        .Tile_X11Y9_RES1_O3(E_RES1[0]),
+	
+        .Tile_X11Y1_RES2_O0(E_RES2[35]),
+        .Tile_X11Y1_RES2_O1(E_RES2[34]),
+        .Tile_X11Y1_RES2_O2(E_RES2[33]),
+        .Tile_X11Y1_RES2_O3(E_RES2[32]),
+        .Tile_X11Y2_RES2_O0(E_RES2[31]),
+        .Tile_X11Y2_RES2_O1(E_RES2[30]),
+        .Tile_X11Y2_RES2_O2(E_RES2[29]),
+        .Tile_X11Y2_RES2_O3(E_RES2[28]),
+        .Tile_X11Y3_RES2_O0(E_RES2[27]),
+        .Tile_X11Y3_RES2_O1(E_RES2[26]),
+        .Tile_X11Y3_RES2_O2(E_RES2[25]),
+        .Tile_X11Y3_RES2_O3(E_RES2[24]),
+        .Tile_X11Y4_RES2_O0(E_RES2[23]),
+        .Tile_X11Y4_RES2_O1(E_RES2[22]),
+        .Tile_X11Y4_RES2_O2(E_RES2[21]),
+        .Tile_X11Y4_RES2_O3(E_RES2[20]),
+        .Tile_X11Y5_RES2_O0(E_RES2[19]),
+        .Tile_X11Y5_RES2_O1(E_RES2[18]),
+        .Tile_X11Y5_RES2_O2(E_RES2[17]),
+        .Tile_X11Y5_RES2_O3(E_RES2[16]),
+        .Tile_X11Y6_RES2_O0(E_RES2[15]),
+        .Tile_X11Y6_RES2_O1(E_RES2[14]),
+        .Tile_X11Y6_RES2_O2(E_RES2[13]),
+        .Tile_X11Y6_RES2_O3(E_RES2[12]),
+        .Tile_X11Y7_RES2_O0(E_RES2[11]),
+        .Tile_X11Y7_RES2_O1(E_RES2[10]),
+        .Tile_X11Y7_RES2_O2(E_RES2[9]),
+        .Tile_X11Y7_RES2_O3(E_RES2[8]),
+        .Tile_X11Y8_RES2_O0(E_RES2[7]),
+        .Tile_X11Y8_RES2_O1(E_RES2[6]),
+        .Tile_X11Y8_RES2_O2(E_RES2[5]),
+        .Tile_X11Y8_RES2_O3(E_RES2[4]),
+        .Tile_X11Y9_RES2_O0(E_RES2[3]),
+        .Tile_X11Y9_RES2_O1(E_RES2[2]),
+        .Tile_X11Y9_RES2_O2(E_RES2[1]),
+        .Tile_X11Y9_RES2_O3(E_RES2[0]),
+
+        .Tile_X14Y10_RAM2FAB_D0_I0(RAM2FAB_D[79]),
+        .Tile_X14Y10_RAM2FAB_D0_I1(RAM2FAB_D[78]),
+        .Tile_X14Y10_RAM2FAB_D0_I2(RAM2FAB_D[77]),
+        .Tile_X14Y10_RAM2FAB_D0_I3(RAM2FAB_D[76]),
+        .Tile_X14Y10_RAM2FAB_D1_I0(RAM2FAB_D[75]),
+        .Tile_X14Y10_RAM2FAB_D1_I1(RAM2FAB_D[74]),
+        .Tile_X14Y10_RAM2FAB_D1_I2(RAM2FAB_D[73]),
+        .Tile_X14Y10_RAM2FAB_D1_I3(RAM2FAB_D[72]),
+        .Tile_X14Y10_RAM2FAB_D2_I0(RAM2FAB_D[71]),
+        .Tile_X14Y10_RAM2FAB_D2_I1(RAM2FAB_D[70]),
+        .Tile_X14Y10_RAM2FAB_D2_I2(RAM2FAB_D[69]),
+        .Tile_X14Y10_RAM2FAB_D2_I3(RAM2FAB_D[68]),
+        .Tile_X14Y10_RAM2FAB_D3_I0(RAM2FAB_D[67]),
+        .Tile_X14Y10_RAM2FAB_D3_I1(RAM2FAB_D[66]),
+        .Tile_X14Y10_RAM2FAB_D3_I2(RAM2FAB_D[65]),
+        .Tile_X14Y10_RAM2FAB_D3_I3(RAM2FAB_D[64]),
+        .Tile_X14Y11_RAM2FAB_D0_I0(RAM2FAB_D[63]),
+        .Tile_X14Y11_RAM2FAB_D0_I1(RAM2FAB_D[62]),
+        .Tile_X14Y11_RAM2FAB_D0_I2(RAM2FAB_D[61]),
+        .Tile_X14Y11_RAM2FAB_D0_I3(RAM2FAB_D[60]),
+        .Tile_X14Y11_RAM2FAB_D1_I0(RAM2FAB_D[59]),
+        .Tile_X14Y11_RAM2FAB_D1_I1(RAM2FAB_D[58]),
+        .Tile_X14Y11_RAM2FAB_D1_I2(RAM2FAB_D[57]),
+        .Tile_X14Y11_RAM2FAB_D1_I3(RAM2FAB_D[56]),
+        .Tile_X14Y11_RAM2FAB_D2_I0(RAM2FAB_D[55]),
+        .Tile_X14Y11_RAM2FAB_D2_I1(RAM2FAB_D[54]),
+        .Tile_X14Y11_RAM2FAB_D2_I2(RAM2FAB_D[53]),
+        .Tile_X14Y11_RAM2FAB_D2_I3(RAM2FAB_D[52]),
+        .Tile_X14Y11_RAM2FAB_D3_I0(RAM2FAB_D[51]),
+        .Tile_X14Y11_RAM2FAB_D3_I1(RAM2FAB_D[50]),
+        .Tile_X14Y11_RAM2FAB_D3_I2(RAM2FAB_D[49]),
+        .Tile_X14Y11_RAM2FAB_D3_I3(RAM2FAB_D[48]),
+        .Tile_X14Y12_RAM2FAB_D0_I0(RAM2FAB_D[47]),
+        .Tile_X14Y12_RAM2FAB_D0_I1(RAM2FAB_D[46]),
+        .Tile_X14Y12_RAM2FAB_D0_I2(RAM2FAB_D[45]),
+        .Tile_X14Y12_RAM2FAB_D0_I3(RAM2FAB_D[44]),
+        .Tile_X14Y12_RAM2FAB_D1_I0(RAM2FAB_D[43]),
+        .Tile_X14Y12_RAM2FAB_D1_I1(RAM2FAB_D[42]),
+        .Tile_X14Y12_RAM2FAB_D1_I2(RAM2FAB_D[41]),
+        .Tile_X14Y12_RAM2FAB_D1_I3(RAM2FAB_D[40]),
+        .Tile_X14Y12_RAM2FAB_D2_I0(RAM2FAB_D[39]),
+        .Tile_X14Y12_RAM2FAB_D2_I1(RAM2FAB_D[38]),
+        .Tile_X14Y12_RAM2FAB_D2_I2(RAM2FAB_D[37]),
+        .Tile_X14Y12_RAM2FAB_D2_I3(RAM2FAB_D[36]),
+        .Tile_X14Y12_RAM2FAB_D3_I0(RAM2FAB_D[35]),
+        .Tile_X14Y12_RAM2FAB_D3_I1(RAM2FAB_D[34]),
+        .Tile_X14Y12_RAM2FAB_D3_I2(RAM2FAB_D[33]),
+        .Tile_X14Y12_RAM2FAB_D3_I3(RAM2FAB_D[32]),
+        .Tile_X14Y13_RAM2FAB_D0_I0(RAM2FAB_D[31]),
+        .Tile_X14Y13_RAM2FAB_D0_I1(RAM2FAB_D[30]),
+        .Tile_X14Y13_RAM2FAB_D0_I2(RAM2FAB_D[29]),
+        .Tile_X14Y13_RAM2FAB_D0_I3(RAM2FAB_D[28]),
+        .Tile_X14Y13_RAM2FAB_D1_I0(RAM2FAB_D[27]),
+        .Tile_X14Y13_RAM2FAB_D1_I1(RAM2FAB_D[26]),
+        .Tile_X14Y13_RAM2FAB_D1_I2(RAM2FAB_D[25]),
+        .Tile_X14Y13_RAM2FAB_D1_I3(RAM2FAB_D[24]),
+        .Tile_X14Y13_RAM2FAB_D2_I0(RAM2FAB_D[23]),
+        .Tile_X14Y13_RAM2FAB_D2_I1(RAM2FAB_D[22]),
+        .Tile_X14Y13_RAM2FAB_D2_I2(RAM2FAB_D[21]),
+        .Tile_X14Y13_RAM2FAB_D2_I3(RAM2FAB_D[20]),
+        .Tile_X14Y13_RAM2FAB_D3_I0(RAM2FAB_D[19]),
+        .Tile_X14Y13_RAM2FAB_D3_I1(RAM2FAB_D[18]),
+        .Tile_X14Y13_RAM2FAB_D3_I2(RAM2FAB_D[17]),
+        .Tile_X14Y13_RAM2FAB_D3_I3(RAM2FAB_D[16]),
+        .Tile_X14Y14_RAM2FAB_D0_I0(RAM2FAB_D[15]),
+        .Tile_X14Y14_RAM2FAB_D0_I1(RAM2FAB_D[14]),
+        .Tile_X14Y14_RAM2FAB_D0_I2(RAM2FAB_D[13]),
+        .Tile_X14Y14_RAM2FAB_D0_I3(RAM2FAB_D[12]),
+        .Tile_X14Y14_RAM2FAB_D1_I0(RAM2FAB_D[11]),
+        .Tile_X14Y14_RAM2FAB_D1_I1(RAM2FAB_D[10]),
+        .Tile_X14Y14_RAM2FAB_D1_I2(RAM2FAB_D[9]),
+        .Tile_X14Y14_RAM2FAB_D1_I3(RAM2FAB_D[8]),
+        .Tile_X14Y14_RAM2FAB_D2_I0(RAM2FAB_D[7]),
+        .Tile_X14Y14_RAM2FAB_D2_I1(RAM2FAB_D[6]),
+        .Tile_X14Y14_RAM2FAB_D2_I2(RAM2FAB_D[5]),
+        .Tile_X14Y14_RAM2FAB_D2_I3(RAM2FAB_D[4]),
+        .Tile_X14Y14_RAM2FAB_D3_I0(RAM2FAB_D[3]),
+        .Tile_X14Y14_RAM2FAB_D3_I1(RAM2FAB_D[2]),
+        .Tile_X14Y14_RAM2FAB_D3_I2(RAM2FAB_D[1]),
+        .Tile_X14Y14_RAM2FAB_D3_I3(RAM2FAB_D[0]),
+
+        .Tile_X14Y10_FAB2RAM_D0_O0(FAB2RAM_D[79]),
+        .Tile_X14Y10_FAB2RAM_D0_O1(FAB2RAM_D[78]),
+        .Tile_X14Y10_FAB2RAM_D0_O2(FAB2RAM_D[77]),
+        .Tile_X14Y10_FAB2RAM_D0_O3(FAB2RAM_D[76]),
+        .Tile_X14Y10_FAB2RAM_D1_O0(FAB2RAM_D[75]),
+        .Tile_X14Y10_FAB2RAM_D1_O1(FAB2RAM_D[74]),
+        .Tile_X14Y10_FAB2RAM_D1_O2(FAB2RAM_D[73]),
+        .Tile_X14Y10_FAB2RAM_D1_O3(FAB2RAM_D[72]),
+        .Tile_X14Y10_FAB2RAM_D2_O0(FAB2RAM_D[71]),
+        .Tile_X14Y10_FAB2RAM_D2_O1(FAB2RAM_D[70]),
+        .Tile_X14Y10_FAB2RAM_D2_O2(FAB2RAM_D[69]),
+        .Tile_X14Y10_FAB2RAM_D2_O3(FAB2RAM_D[68]),
+        .Tile_X14Y10_FAB2RAM_D3_O0(FAB2RAM_D[67]),
+        .Tile_X14Y10_FAB2RAM_D3_O1(FAB2RAM_D[66]),
+        .Tile_X14Y10_FAB2RAM_D3_O2(FAB2RAM_D[65]),
+        .Tile_X14Y10_FAB2RAM_D3_O3(FAB2RAM_D[64]),
+        .Tile_X14Y11_FAB2RAM_D0_O0(FAB2RAM_D[63]),
+        .Tile_X14Y11_FAB2RAM_D0_O1(FAB2RAM_D[62]),
+        .Tile_X14Y11_FAB2RAM_D0_O2(FAB2RAM_D[61]),
+        .Tile_X14Y11_FAB2RAM_D0_O3(FAB2RAM_D[60]),
+        .Tile_X14Y11_FAB2RAM_D1_O0(FAB2RAM_D[59]),
+        .Tile_X14Y11_FAB2RAM_D1_O1(FAB2RAM_D[58]),
+        .Tile_X14Y11_FAB2RAM_D1_O2(FAB2RAM_D[57]),
+        .Tile_X14Y11_FAB2RAM_D1_O3(FAB2RAM_D[56]),
+        .Tile_X14Y11_FAB2RAM_D2_O0(FAB2RAM_D[55]),
+        .Tile_X14Y11_FAB2RAM_D2_O1(FAB2RAM_D[54]),
+        .Tile_X14Y11_FAB2RAM_D2_O2(FAB2RAM_D[53]),
+        .Tile_X14Y11_FAB2RAM_D2_O3(FAB2RAM_D[52]),
+        .Tile_X14Y11_FAB2RAM_D3_O0(FAB2RAM_D[51]),
+        .Tile_X14Y11_FAB2RAM_D3_O1(FAB2RAM_D[50]),
+        .Tile_X14Y11_FAB2RAM_D3_O2(FAB2RAM_D[49]),
+        .Tile_X14Y11_FAB2RAM_D3_O3(FAB2RAM_D[48]),
+        .Tile_X14Y12_FAB2RAM_D0_O0(FAB2RAM_D[47]),
+        .Tile_X14Y12_FAB2RAM_D0_O1(FAB2RAM_D[46]),
+        .Tile_X14Y12_FAB2RAM_D0_O2(FAB2RAM_D[45]),
+        .Tile_X14Y12_FAB2RAM_D0_O3(FAB2RAM_D[44]),
+        .Tile_X14Y12_FAB2RAM_D1_O0(FAB2RAM_D[43]),
+        .Tile_X14Y12_FAB2RAM_D1_O1(FAB2RAM_D[42]),
+        .Tile_X14Y12_FAB2RAM_D1_O2(FAB2RAM_D[41]),
+        .Tile_X14Y12_FAB2RAM_D1_O3(FAB2RAM_D[40]),
+        .Tile_X14Y12_FAB2RAM_D2_O0(FAB2RAM_D[39]),
+        .Tile_X14Y12_FAB2RAM_D2_O1(FAB2RAM_D[38]),
+        .Tile_X14Y12_FAB2RAM_D2_O2(FAB2RAM_D[37]),
+        .Tile_X14Y12_FAB2RAM_D2_O3(FAB2RAM_D[36]),
+        .Tile_X14Y12_FAB2RAM_D3_O0(FAB2RAM_D[35]),
+        .Tile_X14Y12_FAB2RAM_D3_O1(FAB2RAM_D[34]),
+        .Tile_X14Y12_FAB2RAM_D3_O2(FAB2RAM_D[33]),
+        .Tile_X14Y12_FAB2RAM_D3_O3(FAB2RAM_D[32]),
+        .Tile_X14Y13_FAB2RAM_D0_O0(FAB2RAM_D[31]),
+        .Tile_X14Y13_FAB2RAM_D0_O1(FAB2RAM_D[30]),
+        .Tile_X14Y13_FAB2RAM_D0_O2(FAB2RAM_D[29]),
+        .Tile_X14Y13_FAB2RAM_D0_O3(FAB2RAM_D[28]),
+        .Tile_X14Y13_FAB2RAM_D1_O0(FAB2RAM_D[27]),
+        .Tile_X14Y13_FAB2RAM_D1_O1(FAB2RAM_D[26]),
+        .Tile_X14Y13_FAB2RAM_D1_O2(FAB2RAM_D[25]),
+        .Tile_X14Y13_FAB2RAM_D1_O3(FAB2RAM_D[24]),
+        .Tile_X14Y13_FAB2RAM_D2_O0(FAB2RAM_D[23]),
+        .Tile_X14Y13_FAB2RAM_D2_O1(FAB2RAM_D[22]),
+        .Tile_X14Y13_FAB2RAM_D2_O2(FAB2RAM_D[21]),
+        .Tile_X14Y13_FAB2RAM_D2_O3(FAB2RAM_D[20]),
+        .Tile_X14Y13_FAB2RAM_D3_O0(FAB2RAM_D[19]),
+        .Tile_X14Y13_FAB2RAM_D3_O1(FAB2RAM_D[18]),
+        .Tile_X14Y13_FAB2RAM_D3_O2(FAB2RAM_D[17]),
+        .Tile_X14Y13_FAB2RAM_D3_O3(FAB2RAM_D[16]),
+        .Tile_X14Y14_FAB2RAM_D0_O0(FAB2RAM_D[15]),
+        .Tile_X14Y14_FAB2RAM_D0_O1(FAB2RAM_D[14]),
+        .Tile_X14Y14_FAB2RAM_D0_O2(FAB2RAM_D[13]),
+        .Tile_X14Y14_FAB2RAM_D0_O3(FAB2RAM_D[12]),
+        .Tile_X14Y14_FAB2RAM_D1_O0(FAB2RAM_D[11]),
+        .Tile_X14Y14_FAB2RAM_D1_O1(FAB2RAM_D[10]),
+        .Tile_X14Y14_FAB2RAM_D1_O2(FAB2RAM_D[9]),
+        .Tile_X14Y14_FAB2RAM_D1_O3(FAB2RAM_D[8]),
+        .Tile_X14Y14_FAB2RAM_D2_O0(FAB2RAM_D[7]),
+        .Tile_X14Y14_FAB2RAM_D2_O1(FAB2RAM_D[6]),
+        .Tile_X14Y14_FAB2RAM_D2_O2(FAB2RAM_D[5]),
+        .Tile_X14Y14_FAB2RAM_D2_O3(FAB2RAM_D[4]),
+        .Tile_X14Y14_FAB2RAM_D3_O0(FAB2RAM_D[3]),
+        .Tile_X14Y14_FAB2RAM_D3_O1(FAB2RAM_D[2]),
+        .Tile_X14Y14_FAB2RAM_D3_O2(FAB2RAM_D[1]),
+        .Tile_X14Y14_FAB2RAM_D3_O3(FAB2RAM_D[0]),
+
+        .Tile_X14Y10_FAB2RAM_A0_O0(FAB2RAM_A[39]),
+        .Tile_X14Y10_FAB2RAM_A0_O1(FAB2RAM_A[38]),
+        .Tile_X14Y10_FAB2RAM_A0_O2(FAB2RAM_A[37]),
+        .Tile_X14Y10_FAB2RAM_A0_O3(FAB2RAM_A[36]),
+        .Tile_X14Y10_FAB2RAM_A1_O0(FAB2RAM_A[35]),
+        .Tile_X14Y10_FAB2RAM_A1_O1(FAB2RAM_A[34]),
+        .Tile_X14Y10_FAB2RAM_A1_O2(FAB2RAM_A[33]),
+        .Tile_X14Y10_FAB2RAM_A1_O3(FAB2RAM_A[32]),
+        .Tile_X14Y11_FAB2RAM_A0_O0(FAB2RAM_A[31]),
+        .Tile_X14Y11_FAB2RAM_A0_O1(FAB2RAM_A[30]),
+        .Tile_X14Y11_FAB2RAM_A0_O2(FAB2RAM_A[29]),
+        .Tile_X14Y11_FAB2RAM_A0_O3(FAB2RAM_A[28]),
+        .Tile_X14Y11_FAB2RAM_A1_O0(FAB2RAM_A[27]),
+        .Tile_X14Y11_FAB2RAM_A1_O1(FAB2RAM_A[26]),
+        .Tile_X14Y11_FAB2RAM_A1_O2(FAB2RAM_A[25]),
+        .Tile_X14Y11_FAB2RAM_A1_O3(FAB2RAM_A[24]),
+        .Tile_X14Y12_FAB2RAM_A0_O0(FAB2RAM_A[23]),
+        .Tile_X14Y12_FAB2RAM_A0_O1(FAB2RAM_A[22]),
+        .Tile_X14Y12_FAB2RAM_A0_O2(FAB2RAM_A[21]),
+        .Tile_X14Y12_FAB2RAM_A0_O3(FAB2RAM_A[20]),
+        .Tile_X14Y12_FAB2RAM_A1_O0(FAB2RAM_A[19]),
+        .Tile_X14Y12_FAB2RAM_A1_O1(FAB2RAM_A[18]),
+        .Tile_X14Y12_FAB2RAM_A1_O2(FAB2RAM_A[17]),
+        .Tile_X14Y12_FAB2RAM_A1_O3(FAB2RAM_A[16]),
+        .Tile_X14Y13_FAB2RAM_A0_O0(FAB2RAM_A[15]),
+        .Tile_X14Y13_FAB2RAM_A0_O1(FAB2RAM_A[14]),
+        .Tile_X14Y13_FAB2RAM_A0_O2(FAB2RAM_A[13]),
+        .Tile_X14Y13_FAB2RAM_A0_O3(FAB2RAM_A[12]),
+        .Tile_X14Y13_FAB2RAM_A1_O0(FAB2RAM_A[11]),
+        .Tile_X14Y13_FAB2RAM_A1_O1(FAB2RAM_A[10]),
+        .Tile_X14Y13_FAB2RAM_A1_O2(FAB2RAM_A[9]),
+        .Tile_X14Y13_FAB2RAM_A1_O3(FAB2RAM_A[8]),
+        .Tile_X14Y14_FAB2RAM_A0_O0(FAB2RAM_A[7]),
+        .Tile_X14Y14_FAB2RAM_A0_O1(FAB2RAM_A[6]),
+        .Tile_X14Y14_FAB2RAM_A0_O2(FAB2RAM_A[5]),
+        .Tile_X14Y14_FAB2RAM_A0_O3(FAB2RAM_A[4]),
+        .Tile_X14Y14_FAB2RAM_A1_O0(FAB2RAM_A[3]),
+        .Tile_X14Y14_FAB2RAM_A1_O1(FAB2RAM_A[2]),
+        .Tile_X14Y14_FAB2RAM_A1_O2(FAB2RAM_A[1]),
+        .Tile_X14Y14_FAB2RAM_A1_O3(FAB2RAM_A[0]),
+
+        .Tile_X14Y10_FAB2RAM_C_O0(FAB2RAM_C[19]),
+        .Tile_X14Y10_FAB2RAM_C_O1(FAB2RAM_C[18]),
+        .Tile_X14Y10_FAB2RAM_C_O2(FAB2RAM_C[17]),
+        .Tile_X14Y10_FAB2RAM_C_O3(FAB2RAM_C[16]),
+        .Tile_X14Y11_FAB2RAM_C_O0(FAB2RAM_C[15]),
+        .Tile_X14Y11_FAB2RAM_C_O1(FAB2RAM_C[14]),
+        .Tile_X14Y11_FAB2RAM_C_O2(FAB2RAM_C[13]),
+        .Tile_X14Y11_FAB2RAM_C_O3(FAB2RAM_C[12]),
+        .Tile_X14Y12_FAB2RAM_C_O0(FAB2RAM_C[11]),
+        .Tile_X14Y12_FAB2RAM_C_O1(FAB2RAM_C[10]),
+        .Tile_X14Y12_FAB2RAM_C_O2(FAB2RAM_C[9]),
+        .Tile_X14Y12_FAB2RAM_C_O3(FAB2RAM_C[8]),
+        .Tile_X14Y13_FAB2RAM_C_O0(FAB2RAM_C[7]),
+        .Tile_X14Y13_FAB2RAM_C_O1(FAB2RAM_C[6]),
+        .Tile_X14Y13_FAB2RAM_C_O2(FAB2RAM_C[5]),
+        .Tile_X14Y13_FAB2RAM_C_O3(FAB2RAM_C[4]),
+        .Tile_X14Y14_FAB2RAM_C_O0(FAB2RAM_C[3]),
+        .Tile_X14Y14_FAB2RAM_C_O1(FAB2RAM_C[2]),
+        .Tile_X14Y14_FAB2RAM_C_O2(FAB2RAM_C[1]),
+        .Tile_X14Y14_FAB2RAM_C_O3(FAB2RAM_C[0]),
+
+        .Tile_X14Y10_Config_accessC_bit0(Config_accessC[19]),
+        .Tile_X14Y10_Config_accessC_bit1(Config_accessC[18]),
+        .Tile_X14Y10_Config_accessC_bit2(Config_accessC[17]),
+        .Tile_X14Y10_Config_accessC_bit3(Config_accessC[16]),
+        .Tile_X14Y11_Config_accessC_bit0(Config_accessC[15]),
+        .Tile_X14Y11_Config_accessC_bit1(Config_accessC[14]),
+        .Tile_X14Y11_Config_accessC_bit2(Config_accessC[13]),
+        .Tile_X14Y11_Config_accessC_bit3(Config_accessC[12]),
+        .Tile_X14Y12_Config_accessC_bit0(Config_accessC[11]),
+        .Tile_X14Y12_Config_accessC_bit1(Config_accessC[10]),
+        .Tile_X14Y12_Config_accessC_bit2(Config_accessC[9]),
+        .Tile_X14Y12_Config_accessC_bit3(Config_accessC[8]),
+        .Tile_X14Y13_Config_accessC_bit0(Config_accessC[7]),
+        .Tile_X14Y13_Config_accessC_bit1(Config_accessC[6]),
+        .Tile_X14Y13_Config_accessC_bit2(Config_accessC[5]),
+        .Tile_X14Y13_Config_accessC_bit3(Config_accessC[4]),
+        .Tile_X14Y14_Config_accessC_bit0(Config_accessC[3]),
+        .Tile_X14Y14_Config_accessC_bit1(Config_accessC[2]),
+        .Tile_X14Y14_Config_accessC_bit2(Config_accessC[1]),
+        .Tile_X14Y14_Config_accessC_bit3(Config_accessC[0]),
+
+        //declarations
+        .UserCLK(CLK),
+        .FrameData(FrameData),
+        .FrameStrobe(FrameSelect)
+    );
+
+        assign FrameData = {32'h12345678,FrameRegister,32'h12345678};
+    end
+endgenerate
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/eFPGA_conf/Config.v b/verilog/rtl/eFPGA_conf/Config.v
new file mode 100644
index 0000000..37cf652
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/Config.v
@@ -0,0 +1,109 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module Config (CLK, Rx, ComActive, ReceiveLED, s_clk, s_data, SelfWriteData, SelfWriteStrobe, ConfigWriteData, ConfigWriteStrobe, FrameAddressRegister, LongFrameStrobe, RowSelect);
+	//parameter NumberOfRows = 16;
+	parameter RowSelectWidth = 5;
+	parameter FrameBitsPerRow = 32;
+	//parameter desync_flag = 20;
+	input CLK;
+	// UART configuration port
+	input Rx;
+	output ComActive;
+	output ReceiveLED;
+	// BitBang configuration port
+	input s_clk;
+	input s_data;
+	// CPU configuration port
+	input [32-1:0] SelfWriteData; // configuration data write port
+	input SelfWriteStrobe; // must decode address and write enable
+	
+	output [32-1:0] ConfigWriteData;
+	output ConfigWriteStrobe;
+	
+	output [FrameBitsPerRow-1:0] FrameAddressRegister;
+	output LongFrameStrobe;
+	output [RowSelectWidth-1:0] RowSelect;
+
+	wire [7:0] Command;
+	wire [31:0] UART_WriteData;
+	wire UART_WriteStrobe;
+	wire [31:0] UART_WriteData_Mux;
+	wire UART_WriteStrobe_Mux;
+	wire UART_ComActive;
+	wire UART_LED;
+
+	wire [31:0] BitBangWriteData;
+	wire BitBangWriteStrobe;
+	wire [31:0] BitBangWriteData_Mux;
+	wire BitBangWriteStrobe_Mux;
+	wire BitBangActive;
+	
+	wire Reset;
+
+	config_UART INST_config_UART (
+	.CLK(CLK),
+	.Rx(Rx),
+	.WriteData(UART_WriteData),
+	.ComActive(UART_ComActive),
+	.WriteStrobe(UART_WriteStrobe),
+	.Command(Command),
+	.ReceiveLED(UART_LED)
+	);
+	
+	//bitbang
+	bitbang Inst_bitbang (
+	.s_clk(s_clk),
+	.s_data(s_data),
+	.strobe(BitBangWriteStrobe),
+	.data(BitBangWriteData),
+	.active(BitBangActive),
+	.clk(CLK)
+	);
+	
+	// BitBangActive is used to switch between bitbang or internal configuration port (BitBang has therefore higher priority)
+	assign BitBangWriteData_Mux = BitBangActive ? BitBangWriteData : SelfWriteData;
+	assign BitBangWriteStrobe_Mux = BitBangActive ? BitBangWriteStrobe : SelfWriteStrobe;	
+
+	// ComActive is used to switch between (bitbang+internal) port or UART (UART has therefore higher priority
+	assign UART_WriteData_Mux = UART_ComActive ? UART_WriteData : BitBangWriteData_Mux;
+	assign UART_WriteStrobe_Mux = UART_ComActive ? UART_WriteStrobe : BitBangWriteStrobe_Mux;	
+	
+	assign ConfigWriteData = UART_WriteData_Mux;
+	assign ConfigWriteStrobe = UART_WriteStrobe_Mux;
+	
+	assign Reset = UART_ComActive || BitBangActive;
+
+	assign ComActive = UART_ComActive;
+	assign ReceiveLED = UART_LED^BitBangWriteStrobe;   
+	
+//	wire [FrameBitsPerRow-1:0] FrameAddressRegister;
+//	wire LongFrameStrobe;
+//	wire [RowSelectWidth-1:0] RowSelect;
+	
+	ConfigFSM ConfigFSM_inst (
+	.CLK(CLK),
+	.WriteData(UART_WriteData_Mux),
+	.WriteStrobe(UART_WriteStrobe_Mux),
+	.Reset(Reset),
+	//outputs
+	.FrameAddressRegister(FrameAddressRegister),
+	.LongFrameStrobe(LongFrameStrobe),
+	.RowSelect(RowSelect)
+	);
+	
+endmodule
diff --git a/verilog/rtl/eFPGA_conf/ConfigFSM.v b/verilog/rtl/eFPGA_conf/ConfigFSM.v
new file mode 100644
index 0000000..fa143ac
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/ConfigFSM.v
@@ -0,0 +1,97 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module ConfigFSM (CLK, WriteData, WriteStrobe, Reset, FrameAddressRegister, LongFrameStrobe, RowSelect);
+	parameter NumberOfRows = 14;
+	parameter RowSelectWidth = 5;
+	parameter FrameBitsPerRow = 32;
+	parameter desync_flag = 20;
+
+	input CLK; 
+	
+	input [31:0] WriteData;
+	input WriteStrobe;
+	input Reset;
+	
+	output reg [FrameBitsPerRow-1:0] FrameAddressRegister;
+	output reg LongFrameStrobe = 0;
+	output reg [RowSelectWidth-1:0] RowSelect;
+	
+	reg FrameStrobe = 0;
+	//signal FrameShiftState : integer range 0 to (NumberOfRows + 2);
+	reg [4:0] FrameShiftState = 0;
+
+	//FSM
+	reg [1:0] state = 0;
+	reg old_reset;
+	always @ (posedge CLK) begin : P_FSM
+		old_reset <= Reset;
+		FrameStrobe <= 1'b0;
+		// we only activate the configuration after detecting a 32-bit aligned pattern "x"FAB0_FAB1"
+		// this allows placing the com-port header into the file and we can use the same file for parallel or UART configuration
+		// this also allows us to place whatever metadata, the only point to remeber is that the pattern/file needs to be 4-byte padded in the header
+		if ((old_reset == 1'b0) && (Reset == 1'b1)) begin // reset all on ComActive posedge
+			state <= 0;
+			FrameShiftState <= 0;
+		end else begin
+			case(state)
+				0: begin // unsynched
+					if(WriteStrobe == 1'b1) begin // if writing enabled
+						if (WriteData == 32'hFAB0_FAB1) begin // fire only after seeing pattern 0xFAB0_FAB1
+							state <= 1; //go to synched state
+						end
+					end
+				end
+				1: begin // SyncState read header
+					if(WriteStrobe == 1'b1) begin// if writing enabled
+						if(WriteData[desync_flag] == 1'b1) begin // desync
+							state <= 0; //desynced
+						end else begin
+							FrameAddressRegister <= WriteData;
+							FrameShiftState <= NumberOfRows  ;
+							state <= 2; //writing frame data
+						end
+					end
+				end
+				2: begin
+					if(WriteStrobe == 1'b1) begin// if writing enabled
+						FrameShiftState <= FrameShiftState -1 ;
+						if(FrameShiftState == 1) begin // on last frame
+							FrameStrobe <= 1'b1; //trigger FrameStrobe
+							state <= 1; // we go to synched state waiting for next frame or desync
+						end
+					end
+				end
+			endcase
+		end
+	end
+	
+	always @ (*) begin
+		if(WriteStrobe) begin // if writing active
+			RowSelect = FrameShiftState; // we write the frame
+		end else begin
+			RowSelect = {RowSelectWidth{1'b1}}; //otherwise, we write an invalid frame
+		end
+	end
+	
+	reg oldFrameStrobe = 0;
+	always @ (posedge CLK) begin : P_StrobeREG
+		oldFrameStrobe <= FrameStrobe;
+		LongFrameStrobe <= (FrameStrobe || oldFrameStrobe);
+	end//CLK
+	
+endmodule
diff --git a/verilog/rtl/eFPGA_conf/Config_access.v b/verilog/rtl/eFPGA_conf/Config_access.v
new file mode 100644
index 0000000..014f33a
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/Config_access.v
@@ -0,0 +1,34 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module Config_access (C_bit0, C_bit1, C_bit2, C_bit3, ConfigBits);
+	parameter NoConfigBits = 4;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// Pin0
+	output C_bit0; // EXTERNAL
+	output C_bit1; // EXTERNAL
+	output C_bit2; // EXTERNAL
+	output C_bit3; // EXTERNAL
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1:0] ConfigBits;
+
+	// we just wire configuration bits to fabric top
+	assign C_bit0 = ConfigBits[0];
+	assign C_bit1 = ConfigBits[1];
+	assign C_bit2 = ConfigBits[2];
+	assign C_bit3 = ConfigBits[3];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_conf/Frame_Data_Reg_Pack.v b/verilog/rtl/eFPGA_conf/Frame_Data_Reg_Pack.v
new file mode 100644
index 0000000..f8b1971
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/Frame_Data_Reg_Pack.v
@@ -0,0 +1,226 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module Frame_Data_Reg_0 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 1;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_1 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 2;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_2 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 3;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_3 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 4;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_4 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 5;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_5 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 6;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_6 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 7;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_7 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 8;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_8 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 9;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_9 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 10;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_10 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 11;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_11 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 12;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_12 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 13;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
+module Frame_Data_Reg_13 (FrameData_I, FrameData_O, RowSelect, CLK);
+	parameter FrameBitsPerRow = 32;
+	parameter RowSelectWidth = 5;
+	parameter Row = 14;
+	input [FrameBitsPerRow-1:0] FrameData_I;
+	output reg [FrameBitsPerRow-1:0] FrameData_O;
+	input [RowSelectWidth-1:0] RowSelect;
+	input CLK;
+	
+	always @ (posedge CLK) begin
+		if (RowSelect==Row)
+			FrameData_O <= FrameData_I;
+	end//CLK
+endmodule
+
diff --git a/verilog/rtl/eFPGA_conf/Frame_Select_Pack.v b/verilog/rtl/eFPGA_conf/Frame_Select_Pack.v
new file mode 100644
index 0000000..7423643
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/Frame_Select_Pack.v
@@ -0,0 +1,286 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module Frame_Select_0 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 0;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_1 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 1;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_2 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 2;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_3 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 3;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_4 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 4;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_5 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 5;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_6 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 6;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_7 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 7;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_8 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 8;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_9 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 9;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_10 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 10;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_11 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 11;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_12 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 12;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_13 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 13;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
+module Frame_Select_14 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameSelectWidth = 5;
+	parameter Col = 14;
+	input [MaxFramesPerCol-1:0] FrameStrobe_I;
+	output reg [MaxFramesPerCol-1:0] FrameStrobe_O;
+	input [FrameSelectWidth-1:0] FrameSelect;
+	input FrameStrobe;
+
+//FrameStrobe_O = 0;
+	always @ (*) begin
+		if (FrameStrobe && (FrameSelect==Col)) 
+			FrameStrobe_O =  FrameStrobe_I;
+		else
+			FrameStrobe_O = 'd0;
+	end
+endmodule
+
diff --git a/verilog/rtl/eFPGA_conf/bitbang.v b/verilog/rtl/eFPGA_conf/bitbang.v
new file mode 100644
index 0000000..17e691d
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/bitbang.v
@@ -0,0 +1,96 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module bitbang (s_clk, s_data, strobe, data, active, clk);
+	localparam on_pattern = 16'hFAB1; 
+	localparam off_pattern = 16'hFAB0; 
+	input s_clk;
+	input s_data;
+	output reg strobe;
+	output reg [31:0] data;
+	output reg active = 1'b0;
+	input clk; 
+
+	reg [3:0] s_data_sample;
+	reg [3:0] s_clk_sample;
+
+	reg [31:0] serial_data;
+	reg [15:0] serial_control;
+
+	reg local_strobe;
+	reg old_local_strobe;
+
+	always @ (posedge clk)
+	begin : p_input_sync
+		s_data_sample <= {s_data_sample[3-1:0],s_data};
+		s_clk_sample  <= {s_clk_sample[3-1:0],s_clk};
+	end
+
+	always @ (posedge clk)
+	begin : p_in_shift
+		// on s_clk_sample rising edge, we sample in a serial_data bit
+		if ((s_clk_sample[3] == 1'b0) && (s_clk_sample[3-1] == 1'b1)) begin
+			serial_data <= {serial_data[31-1:0],s_data_sample[3]};
+		end
+		// on s_clk_sample faling edge, we sample in a serial_data bit
+		if ((s_clk_sample[3] == 1'b1) && (s_clk_sample[3-1] == 1'b0)) begin
+			serial_control <= {serial_control[15-1:0],s_data_sample[3]}; // its data again, but its sampled on the other edge
+		end
+	end
+
+// we could replicate the following 
+	always @ (posedge clk)
+	begin : p_parallel_load
+		local_strobe <= 1'b0; // will be overwritten if next conditional is true
+		if (serial_control == on_pattern) begin// x"FAB1" then      
+			data <= serial_data;
+			local_strobe <= 1'b1;
+		end //else begin
+		//	data <= data;
+		//	local_strobe <= 1'b0;
+		// end
+		old_local_strobe <= local_strobe;
+		strobe <= local_strobe & ~old_local_strobe; // activates strobe for one clock cycle after "FAB0" was detected
+	end
+
+// we could replicate the following 
+	always @ (posedge clk)
+	begin : active_FSM
+		if (serial_control == on_pattern) begin// x"FAB1" then      
+			active <= 1'b1;
+		end
+		if (serial_control == off_pattern) begin// x"FAB0" then      
+			active <= 1'b0;
+		end
+	end
+
+// the following is just copy and past, in case we want use the bitbang interface to shift in other data (let's say to drive CPU port)
+// we can also read back the data by loading the parallel shift and shifting the content to an output pin
+//p_parallel_load2: process(clk)
+//begin
+//    if clk'event and clk=1'b1 then
+//        local_strobe <= 1'b0;       // will be overwritten if next conditional is true
+//        if serial_control = x"FAB1" then      
+//            data2 <= serial_data;  
+//            local_strobe2 <= 1'b1;
+//            old_local_strobe2 <= local_strobe;
+//        end if;
+//      strobe2 <= local_strobe2 and (not old_local_strobe2)   // activates strobe for one clock cycle after "FAB0" was detected
+//    end if;
+//end process;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_conf/config_UART.v b/verilog/rtl/eFPGA_conf/config_UART.v
new file mode 100644
index 0000000..1cf9cd2
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/config_UART.v
@@ -0,0 +1,433 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module config_UART #(
+	parameter Mode = 0, // [0:auto|1:hex|2:bin] auto selects between ASCII-Hex and binary mode and takes a bit more logic, 
+						// bin is for faster binary mode, but might not work on all machines/boards
+						// auto uses the MSB in the command byte (the 8th byte in the comload header) to set the mode
+						// "1//- ////" is for hex mode, "0//- ////" for bin mode
+	parameter ComRate = 174 // ComRate = f_CLK / Boud_rate (e.g., 20 MHz/115200 Boud = 174)
+) (
+	input CLK,
+	input Rx,
+	output reg [31:0] WriteData,
+	output ComActive,
+	output reg WriteStrobe,
+	output [7:0] Command,
+	output reg ReceiveLED
+);
+
+	//constant TimeToSendValue : integer := 16777216-1; //200000000;  
+	localparam TimeToSendValue = 16777-1; //200000000;  
+	//localparam CRC_InitValue = 16'b1111111111111111;
+	localparam TestFileChecksum = 20'h4FB00;
+
+	function [4:0] ASCII2HEX;
+	input [7:0] ASCII;
+	begin
+	case (ASCII)
+		8'h30: ASCII2HEX = 5'b00000;// 0
+		8'h31: ASCII2HEX = 5'b00001;
+		8'h32: ASCII2HEX = 5'b00010;
+		8'h33: ASCII2HEX = 5'b00011;
+		8'h34: ASCII2HEX = 5'b00100;
+		8'h35: ASCII2HEX = 5'b00101;
+		8'h36: ASCII2HEX = 5'b00110;
+		8'h37: ASCII2HEX = 5'b00111;
+		8'h38: ASCII2HEX = 5'b01000;
+		8'h39: ASCII2HEX = 5'b01001;
+		8'h41: ASCII2HEX = 5'b01010;  // A
+		8'h61: ASCII2HEX = 5'b01010;  // a
+		8'h42: ASCII2HEX = 5'b01011;  // B
+		8'h62: ASCII2HEX = 5'b01011;  // b
+		8'h43: ASCII2HEX = 5'b01100;  // C
+		8'h63: ASCII2HEX = 5'b01100;  // c
+		8'h44: ASCII2HEX = 5'b01101;  // D
+		8'h64: ASCII2HEX = 5'b01101;  // d
+		8'h45: ASCII2HEX = 5'b01110;  // E
+		8'h65: ASCII2HEX = 5'b01110;  // e
+		8'h46: ASCII2HEX = 5'b01111;  // F
+		8'h66: ASCII2HEX = 5'b01111;  // f
+		default: ASCII2HEX = 5'b10000;   // The MSB encodes if there was an unknown code -> error
+	endcase
+	end
+	endfunction
+
+	//typedef enum{HighNibble, LowNibble} ReceiveStateType; //systemverilog
+	localparam HighNibble = 1, LowNibble = 0;
+	//ReceiveStateType ReceiveState;
+	reg ReceiveState = HighNibble;
+	reg [3:0] HighReg;
+	wire [4:0] HexValue; // a 1'b0 MSB indicates a valid value on [3..0]
+	reg [7:0] HexData; // the received byte in hexmode mode
+	reg HexWriteStrobe; // we received two hex nibles and have a result byte
+
+	reg [11:0] ComCount;
+	reg ComTick;
+	//typedef enum{WaitForStartBit, DelayAfterStartBit, GetBit0, GetBit1, GetBit2, GetBit3, GetBit4, GetBit5, GetBit6, GetBit7, GetStopBit} ComStateType;
+	//ComStateType ComState;
+	localparam WaitForStartBit=0, DelayAfterStartBit=1, GetBit0=2, GetBit1=3, GetBit2=4, GetBit3=5, GetBit4=6, GetBit5=7, GetBit6=8, GetBit7=9, GetStopBit=10;
+	reg [3:0] ComState = WaitForStartBit;
+	reg [7:0] ReceivedWord;
+	reg RxLocal;
+
+	//signal W0, W1, W2, W3, W4, W5, W6, W7 : std_logic_vector(7 downto 0);
+
+	reg [23:0] ID_Reg;
+	reg [31:0] Start_Reg;
+	reg [15:0] Size_Reg;
+	reg [15:0] CRC_Reg;
+	reg [7:0] Command_Reg;
+	reg [7:0] Data_Reg;
+
+	wire [7:0] ReceivedByte;
+
+	reg TimeToSend;
+	reg [14:0] TimeToSendCounter;
+
+	//typedef enum{Idle, GetID_00, GetID_AA, GetID_FF, GetCommand, EvalCommand, GetData} PresentType;
+	//PresentType PresentState;
+	localparam Idle=0, GetID_00=1, GetID_AA=2, GetID_FF=3, GetCommand=4, EvalCommand=5, GetData=6;
+	reg [2:0] PresentState = Idle;
+
+	//typedef enum{Word0, Word1, Word2, Word3} GetWordType;
+	//GetWordType GetWordState;
+	localparam Word0=0, Word1=1, Word2=2, Word3=3;
+	reg [1:0] GetWordState=Word0;
+
+	reg LocalWriteStrobe;
+
+	reg ByteWriteStrobe;
+
+	//wire [31:0] Data_Reg32;
+
+	//wire [15:0] Word_Count;
+
+	reg [19:0] CRCReg,b_counter;
+	//wire [7:0] ReceivedWordDebug;
+	reg [22:0] blink;
+
+	initial begin
+	CRCReg = TestFileChecksum;
+	b_counter = TestFileChecksum;
+	blink = 23'b00000000000000000000000;
+	end
+
+	always @ (posedge CLK)
+	begin : P_sync
+		RxLocal <= Rx;
+	end// CLK;
+
+	always @ (posedge CLK)
+	begin : P_com_en
+		if (ComState == WaitForStartBit) begin
+			ComCount <= ComRate/2;// @ 25 MHz
+			ComTick <= 1'b0;
+		end else if (ComCount==0) begin
+			ComCount <= ComRate;
+			ComTick <= 1'b1;
+		end else begin
+			ComCount <= ComCount - 1;
+			ComTick <= 1'b0;
+		end
+	end
+
+	always @ (posedge CLK)
+	begin : P_COM
+		case(ComState)
+		WaitForStartBit: begin
+			if (RxLocal==1'b0) begin
+				ComState <= DelayAfterStartBit;
+				ReceivedWord <= 0;
+			end
+		end
+		DelayAfterStartBit: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit0;
+			end
+		end
+		GetBit0: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit1;
+				ReceivedWord[0] <= RxLocal;
+			end
+		end
+		GetBit1: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit2;
+				ReceivedWord[1] <= RxLocal;
+			end
+		end
+		GetBit2: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit3;
+				ReceivedWord[2] <= RxLocal;
+			end
+		end
+		GetBit3: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit4;
+				ReceivedWord[3] <= RxLocal;
+			end
+		end
+		GetBit4: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit5;
+				ReceivedWord[4] <= RxLocal;
+			end
+		end
+		GetBit5: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit6;
+				ReceivedWord[5] <= RxLocal;
+			end
+		end
+		GetBit6: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetBit7;
+				ReceivedWord[6] <= RxLocal;
+			end
+		end
+		GetBit7: begin
+			if (ComTick==1'b1) begin
+				ComState <= GetStopBit;
+				ReceivedWord[7] <= RxLocal;
+			end
+		end
+		GetStopBit: begin
+			if (ComTick==1'b1) begin
+				ComState <= WaitForStartBit;
+			end
+		end
+		endcase
+// scan order:
+// <-to_modules_scan_in <- LSB_W0..MSB_W0 <- LSB_W1.... <- LSB_W7 <- from_modules_scan_out
+// W8(7..1)
+		if (ComState==GetStopBit && ComTick==1'b1) begin
+			case (PresentState)
+				GetID_00: ID_Reg[23:16] <= ReceivedWord;
+				GetID_AA: ID_Reg[15:8] <= ReceivedWord;
+				GetID_FF: ID_Reg[7:0] <= ReceivedWord;
+//         when GetSize0 => Size_Reg(15 downto 8) <= ReceivedWord;
+//         when GetSize1 => Size_Reg(7 downto 0) <= ReceivedWord;
+//         when GetCRC_H => CRC_Reg(15 downto 8) <= ReceivedWord;
+//         when GetCRC_L => CRC_Reg(7 downto 0) <= ReceivedWord;
+				GetCommand: Command_Reg <= ReceivedWord;
+				GetData: Data_Reg <= ReceivedWord;
+			endcase
+		end
+	end//CLK
+
+	always @(posedge CLK)
+	begin : P_FSM
+		case(PresentState)
+		Idle: begin
+			if (ComState==WaitForStartBit && RxLocal==1'b0) begin 
+				PresentState <= GetID_00;
+			end
+		end
+		GetID_00: begin
+			if (TimeToSend==1'b1) begin 
+				PresentState<=Idle;
+			end else if (ComState==GetStopBit && ComTick==1'b1) begin
+				PresentState <= GetID_AA;
+			end
+		end
+		GetID_AA: begin
+			if (TimeToSend==1'b1) begin
+				PresentState<=Idle;
+			end else if (ComState==GetStopBit && ComTick==1'b1) begin
+				PresentState <= GetID_FF;
+			end
+		end
+		GetID_FF: begin
+			if (TimeToSend==1'b1) begin
+				PresentState<=Idle;
+			end else if (ComState==GetStopBit && ComTick==1'b1) begin 
+				PresentState <= GetCommand;
+			end
+		end
+//		GetSize1:
+//        if TimeToSend=1'b1 begin PresentState<=Idle;
+//        elsif ComState=GetStopBit && ComTick=1'b1 begin PresentState <= GetSize0; end if;
+//		GetSize0:
+//        if TimeToSend=1'b1 begin PresentState<=Idle;
+//        elsif ComState=GetStopBit && ComTick=1'b1 begin PresentState <= GetCommand; end if;
+		GetCommand: begin
+			if (TimeToSend==1'b1) begin
+				PresentState<=Idle;
+			end else if (ComState==GetStopBit && ComTick==1'b1) begin 
+				PresentState <= EvalCommand;
+			end
+		end
+		EvalCommand: begin
+			if (ID_Reg==24'h00AAFF && (Command_Reg[6:0]=={3'b000,4'h1} || Command_Reg[6:0]=={3'b000,4'h2})) begin
+				PresentState <= GetData;
+			end else begin
+				PresentState <= Idle;
+			end
+		end
+		GetData: begin
+			if (TimeToSend==1'b1) begin 
+				PresentState<=Idle; 
+			end
+		end
+		endcase
+	end//CLK
+	assign Command = Command_Reg;
+
+	if (Mode==0 || Mode==1) begin : L_hexmode// mode [0:auto|1:hex|2:bin]
+		assign HexValue = ASCII2HEX(ReceivedWord);
+		always @ (posedge CLK)
+		begin
+			if (PresentState!=GetData) begin
+				ReceiveState <= HighNibble;
+			end else if (ComState==GetStopBit && ComTick==1'b1 && HexValue[4]==1'b0) begin
+				if(ReceiveState==HighNibble) begin
+					ReceiveState <= LowNibble;
+				end
+			end else begin
+			  ReceiveState <= HighNibble;
+			end
+		//end// CLK
+			if (ComState==GetStopBit && ComTick==1'b1 && HexValue[4]==1'b0) begin
+				if(ReceiveState==HighNibble) begin
+					HighReg <= HexValue[3:0];
+					HexWriteStrobe <= 1'b0;
+				end else begin// LowNibble
+					HexData <= {HighReg,HexValue[3:0]};
+					HexWriteStrobe <= 1'b1;
+				end
+			end else begin
+				HexWriteStrobe <= 1'b0;
+			end
+		end// CLK
+	end
+
+	always @(posedge CLK)
+	begin : P_checksum
+		if (PresentState==GetCommand) begin // init before data arrives 
+			CRCReg <= 0;
+			b_counter <= 0;
+		end else if (Mode==1 || (Mode==0 && Command_Reg[7]==1'b1)) begin // mode [0:auto|1:hex|2:bin]
+			// if hex mode or if auto mode with detected hex mode in the command register
+			if (ComState==GetStopBit && ComTick==1'b1 && HexValue[4]==1'b0 && PresentState==GetData && ReceiveState==LowNibble) begin
+				CRCReg <= CRCReg + {HighReg,HexValue[3:0]};
+				b_counter <= b_counter+1;
+			end
+		end else begin// binary mode
+			if (ComState==GetStopBit && ComTick==1'b1 && (PresentState==GetData)) begin
+				CRCReg <= CRCReg + ReceivedWord;
+				b_counter <= b_counter +1;
+			end
+		end// checksum computation
+
+		if (PresentState==GetData) begin
+			ReceiveLED <= 1'b1; // receive process in progress
+		end else if ((PresentState==Idle) && (CRCReg!=TestFileChecksum)) begin
+			//ReceiveLED <= blink(blink'high);
+			ReceiveLED <= blink[22];
+		end else begin
+			ReceiveLED <= 1'b0; // receive process was OK
+		end
+
+		blink <= blink-1;
+
+	end //CLK
+
+	always @(posedge CLK)
+	begin : P_bus
+		if (PresentState==EvalCommand) begin
+			LocalWriteStrobe <= 1'b0;
+		end else if (PresentState==GetData && ComState==GetStopBit && ComTick==1'b1) begin
+			LocalWriteStrobe <= 1'b1;
+		end else begin
+			LocalWriteStrobe <= 1'b0;
+		end
+
+		if (Mode==2 || (Mode==0 && Command_Reg[7]==1'b0)) begin // mode [0:auto|1:hex|2:bin]
+		// if binary mode or if auto mode with detected binary mode in the command register
+			ByteWriteStrobe <= LocalWriteStrobe; // delay Strobe to ensure that data is valid when applying CLK
+													// should further prevent glitches in ICAP CLK
+		end else begin
+			ByteWriteStrobe <= HexWriteStrobe;
+		end
+	end// CLK
+
+	always @(posedge CLK)
+	begin : P_WordMode
+		if (PresentState==EvalCommand) begin
+			GetWordState <= Word0;
+			WriteData <= 0;
+		end else begin
+			case(GetWordState)
+			Word0: begin
+				if (ByteWriteStrobe==1'b1) begin
+					WriteData[31:24] <= ReceivedByte;
+					GetWordState <= Word1;
+				end
+			end
+			Word1: begin
+				if (ByteWriteStrobe==1'b1) begin
+					WriteData[23:16] <= ReceivedByte;
+					GetWordState <= Word2;
+				end
+			end
+			Word2: begin
+				if (ByteWriteStrobe==1'b1) begin
+					WriteData[15:8] <= ReceivedByte;
+					GetWordState <= Word3;
+				end
+			end
+			Word3: begin
+				if (ByteWriteStrobe==1'b1) begin
+					WriteData[7:0] <= ReceivedByte;
+					GetWordState <= Word0;
+				end
+			end
+			endcase
+		end
+
+		if (ByteWriteStrobe==1'b1 && GetWordState==Word3) begin
+			WriteStrobe <= 1'b1;
+		end else begin
+			WriteStrobe <= 1'b0;
+		end
+	end// CLK
+
+	//ComLoaderActive <= 1'b0;
+	assign ReceivedByte = (Mode==2 || (Mode==0 && Command_Reg[7]==1'b0)) ? Data_Reg : HexData; // mode [0:auto|1:hex|2:bin]
+	// if binary mode or if auto mode with detected binary mode in the command register
+	// ReceivedWordDebug <= Data_Reg when (Mode="bin" OR (Mode="auto" && Command_Reg(7)=1'b0)) else HexData;
+	assign ComActive = (PresentState==GetData) ? 1'b1 : 1'b0;
+
+	always @(posedge CLK)
+	begin : P_TimeOut
+		if (PresentState==Idle || ComState==GetStopBit) begin
+		//Init TimeOut
+			TimeToSendCounter <= TimeToSendValue;
+			TimeToSend <= 1'b0;
+		end else if (TimeToSendCounter>0) begin
+			TimeToSendCounter <= TimeToSendCounter - 1;
+			TimeToSend <= 1'b0;
+		end else begin
+			TimeToSendCounter <= TimeToSendCounter;
+			TimeToSend <= 1'b1; // force FSM to go back to idle when inactive
+		end
+	end//CLK
+
+endmodule
diff --git a/verilog/rtl/eFPGA_conf/eFPGAconf_netlists.vh b/verilog/rtl/eFPGA_conf/eFPGAconf_netlists.vh
new file mode 100644
index 0000000..25385f9
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/eFPGAconf_netlists.vh
@@ -0,0 +1,13 @@
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+`else
+    `include "bitbang.v"
+    `include "Config_access.v"
+    `include "ConfigFSM.v"
+    `include "config_UART.v"
+    `include "Config.v"
+    `include "fabric_DSP_tile.v"
+    `include "Frame_Data_Reg_Pack.v"
+    `include "Frame_Select_Pack.v"
+`endif
diff --git a/verilog/rtl/eFPGA_conf/fabric_DSP_tile.v b/verilog/rtl/eFPGA_conf/fabric_DSP_tile.v
new file mode 100644
index 0000000..217478b
--- /dev/null
+++ b/verilog/rtl/eFPGA_conf/fabric_DSP_tile.v
@@ -0,0 +1,12450 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0	
+//External IO ports exported directly from the corresponding tiles
+module eFPGA (Tile_X3Y1_OPA_I0, Tile_X3Y1_OPA_I1, Tile_X3Y1_OPA_I2, Tile_X3Y1_OPA_I3, UserCLK, Tile_X3Y1_OPB_I0, Tile_X3Y1_OPB_I1, Tile_X3Y1_OPB_I2, Tile_X3Y1_OPB_I3, Tile_X3Y1_RES0_O0, Tile_X3Y1_RES0_O1, Tile_X3Y1_RES0_O2, Tile_X3Y1_RES0_O3, Tile_X3Y1_RES1_O0, Tile_X3Y1_RES1_O1, Tile_X3Y1_RES1_O2, Tile_X3Y1_RES1_O3, Tile_X3Y1_RES2_O0, Tile_X3Y1_RES2_O1, Tile_X3Y1_RES2_O2, Tile_X3Y1_RES2_O3, Tile_X11Y1_OPA_I0, Tile_X11Y1_OPA_I1, Tile_X11Y1_OPA_I2, Tile_X11Y1_OPA_I3, Tile_X11Y1_OPB_I0, Tile_X11Y1_OPB_I1, Tile_X11Y1_OPB_I2, Tile_X11Y1_OPB_I3, Tile_X11Y1_RES0_O0, Tile_X11Y1_RES0_O1, Tile_X11Y1_RES0_O2, Tile_X11Y1_RES0_O3, Tile_X11Y1_RES1_O0, Tile_X11Y1_RES1_O1, Tile_X11Y1_RES1_O2, Tile_X11Y1_RES1_O3, Tile_X11Y1_RES2_O0, Tile_X11Y1_RES2_O1, Tile_X11Y1_RES2_O2, Tile_X11Y1_RES2_O3, Tile_X3Y2_OPA_I0, Tile_X3Y2_OPA_I1, Tile_X3Y2_OPA_I2, Tile_X3Y2_OPA_I3, Tile_X3Y2_OPB_I0, Tile_X3Y2_OPB_I1, Tile_X3Y2_OPB_I2, Tile_X3Y2_OPB_I3, Tile_X3Y2_RES0_O0, Tile_X3Y2_RES0_O1, Tile_X3Y2_RES0_O2, Tile_X3Y2_RES0_O3, Tile_X3Y2_RES1_O0, Tile_X3Y2_RES1_O1, Tile_X3Y2_RES1_O2, Tile_X3Y2_RES1_O3, Tile_X3Y2_RES2_O0, Tile_X3Y2_RES2_O1, Tile_X3Y2_RES2_O2, Tile_X3Y2_RES2_O3, Tile_X11Y2_OPA_I0, Tile_X11Y2_OPA_I1, Tile_X11Y2_OPA_I2, Tile_X11Y2_OPA_I3, Tile_X11Y2_OPB_I0, Tile_X11Y2_OPB_I1, Tile_X11Y2_OPB_I2, Tile_X11Y2_OPB_I3, Tile_X11Y2_RES0_O0, Tile_X11Y2_RES0_O1, Tile_X11Y2_RES0_O2, Tile_X11Y2_RES0_O3, Tile_X11Y2_RES1_O0, Tile_X11Y2_RES1_O1, Tile_X11Y2_RES1_O2, Tile_X11Y2_RES1_O3, Tile_X11Y2_RES2_O0, Tile_X11Y2_RES2_O1, Tile_X11Y2_RES2_O2, Tile_X11Y2_RES2_O3, Tile_X3Y3_OPA_I0, Tile_X3Y3_OPA_I1, Tile_X3Y3_OPA_I2, Tile_X3Y3_OPA_I3, Tile_X3Y3_OPB_I0, Tile_X3Y3_OPB_I1, Tile_X3Y3_OPB_I2, Tile_X3Y3_OPB_I3, Tile_X3Y3_RES0_O0, Tile_X3Y3_RES0_O1, Tile_X3Y3_RES0_O2, Tile_X3Y3_RES0_O3, Tile_X3Y3_RES1_O0, Tile_X3Y3_RES1_O1, Tile_X3Y3_RES1_O2, Tile_X3Y3_RES1_O3, Tile_X3Y3_RES2_O0, Tile_X3Y3_RES2_O1, Tile_X3Y3_RES2_O2, Tile_X3Y3_RES2_O3, Tile_X11Y3_OPA_I0, Tile_X11Y3_OPA_I1, Tile_X11Y3_OPA_I2, Tile_X11Y3_OPA_I3, Tile_X11Y3_OPB_I0, Tile_X11Y3_OPB_I1, Tile_X11Y3_OPB_I2, Tile_X11Y3_OPB_I3, Tile_X11Y3_RES0_O0, Tile_X11Y3_RES0_O1, Tile_X11Y3_RES0_O2, Tile_X11Y3_RES0_O3, Tile_X11Y3_RES1_O0, Tile_X11Y3_RES1_O1, Tile_X11Y3_RES1_O2, Tile_X11Y3_RES1_O3, Tile_X11Y3_RES2_O0, Tile_X11Y3_RES2_O1, Tile_X11Y3_RES2_O2, Tile_X11Y3_RES2_O3, Tile_X3Y4_OPA_I0, Tile_X3Y4_OPA_I1, Tile_X3Y4_OPA_I2, Tile_X3Y4_OPA_I3, Tile_X3Y4_OPB_I0, Tile_X3Y4_OPB_I1, Tile_X3Y4_OPB_I2, Tile_X3Y4_OPB_I3, Tile_X3Y4_RES0_O0, Tile_X3Y4_RES0_O1, Tile_X3Y4_RES0_O2, Tile_X3Y4_RES0_O3, Tile_X3Y4_RES1_O0, Tile_X3Y4_RES1_O1, Tile_X3Y4_RES1_O2, Tile_X3Y4_RES1_O3, Tile_X3Y4_RES2_O0, Tile_X3Y4_RES2_O1, Tile_X3Y4_RES2_O2, Tile_X3Y4_RES2_O3, Tile_X11Y4_OPA_I0, Tile_X11Y4_OPA_I1, Tile_X11Y4_OPA_I2, Tile_X11Y4_OPA_I3, Tile_X11Y4_OPB_I0, Tile_X11Y4_OPB_I1, Tile_X11Y4_OPB_I2, Tile_X11Y4_OPB_I3, Tile_X11Y4_RES0_O0, Tile_X11Y4_RES0_O1, Tile_X11Y4_RES0_O2, Tile_X11Y4_RES0_O3, Tile_X11Y4_RES1_O0, Tile_X11Y4_RES1_O1, Tile_X11Y4_RES1_O2, Tile_X11Y4_RES1_O3, Tile_X11Y4_RES2_O0, Tile_X11Y4_RES2_O1, Tile_X11Y4_RES2_O2, Tile_X11Y4_RES2_O3, Tile_X3Y5_OPA_I0, Tile_X3Y5_OPA_I1, Tile_X3Y5_OPA_I2, Tile_X3Y5_OPA_I3, Tile_X3Y5_OPB_I0, Tile_X3Y5_OPB_I1, Tile_X3Y5_OPB_I2, Tile_X3Y5_OPB_I3, Tile_X3Y5_RES0_O0, Tile_X3Y5_RES0_O1, Tile_X3Y5_RES0_O2, Tile_X3Y5_RES0_O3, Tile_X3Y5_RES1_O0, Tile_X3Y5_RES1_O1, Tile_X3Y5_RES1_O2, Tile_X3Y5_RES1_O3, Tile_X3Y5_RES2_O0, Tile_X3Y5_RES2_O1, Tile_X3Y5_RES2_O2, Tile_X3Y5_RES2_O3, Tile_X11Y5_OPA_I0, Tile_X11Y5_OPA_I1, Tile_X11Y5_OPA_I2, Tile_X11Y5_OPA_I3, Tile_X11Y5_OPB_I0, Tile_X11Y5_OPB_I1, Tile_X11Y5_OPB_I2, Tile_X11Y5_OPB_I3, Tile_X11Y5_RES0_O0, Tile_X11Y5_RES0_O1, Tile_X11Y5_RES0_O2, Tile_X11Y5_RES0_O3, Tile_X11Y5_RES1_O0, Tile_X11Y5_RES1_O1, Tile_X11Y5_RES1_O2, Tile_X11Y5_RES1_O3, Tile_X11Y5_RES2_O0, Tile_X11Y5_RES2_O1, Tile_X11Y5_RES2_O2, Tile_X11Y5_RES2_O3, Tile_X3Y6_OPA_I0, Tile_X3Y6_OPA_I1, Tile_X3Y6_OPA_I2, Tile_X3Y6_OPA_I3, Tile_X3Y6_OPB_I0, Tile_X3Y6_OPB_I1, Tile_X3Y6_OPB_I2, Tile_X3Y6_OPB_I3, Tile_X3Y6_RES0_O0, Tile_X3Y6_RES0_O1, Tile_X3Y6_RES0_O2, Tile_X3Y6_RES0_O3, Tile_X3Y6_RES1_O0, Tile_X3Y6_RES1_O1, Tile_X3Y6_RES1_O2, Tile_X3Y6_RES1_O3, Tile_X3Y6_RES2_O0, Tile_X3Y6_RES2_O1, Tile_X3Y6_RES2_O2, Tile_X3Y6_RES2_O3, Tile_X11Y6_OPA_I0, Tile_X11Y6_OPA_I1, Tile_X11Y6_OPA_I2, Tile_X11Y6_OPA_I3, Tile_X11Y6_OPB_I0, Tile_X11Y6_OPB_I1, Tile_X11Y6_OPB_I2, Tile_X11Y6_OPB_I3, Tile_X11Y6_RES0_O0, Tile_X11Y6_RES0_O1, Tile_X11Y6_RES0_O2, Tile_X11Y6_RES0_O3, Tile_X11Y6_RES1_O0, Tile_X11Y6_RES1_O1, Tile_X11Y6_RES1_O2, Tile_X11Y6_RES1_O3, Tile_X11Y6_RES2_O0, Tile_X11Y6_RES2_O1, Tile_X11Y6_RES2_O2, Tile_X11Y6_RES2_O3, Tile_X3Y7_OPA_I0, Tile_X3Y7_OPA_I1, Tile_X3Y7_OPA_I2, Tile_X3Y7_OPA_I3, Tile_X3Y7_OPB_I0, Tile_X3Y7_OPB_I1, Tile_X3Y7_OPB_I2, Tile_X3Y7_OPB_I3, Tile_X3Y7_RES0_O0, Tile_X3Y7_RES0_O1, Tile_X3Y7_RES0_O2, Tile_X3Y7_RES0_O3, Tile_X3Y7_RES1_O0, Tile_X3Y7_RES1_O1, Tile_X3Y7_RES1_O2, Tile_X3Y7_RES1_O3, Tile_X3Y7_RES2_O0, Tile_X3Y7_RES2_O1, Tile_X3Y7_RES2_O2, Tile_X3Y7_RES2_O3, Tile_X11Y7_OPA_I0, Tile_X11Y7_OPA_I1, Tile_X11Y7_OPA_I2, Tile_X11Y7_OPA_I3, Tile_X11Y7_OPB_I0, Tile_X11Y7_OPB_I1, Tile_X11Y7_OPB_I2, Tile_X11Y7_OPB_I3, Tile_X11Y7_RES0_O0, Tile_X11Y7_RES0_O1, Tile_X11Y7_RES0_O2, Tile_X11Y7_RES0_O3, Tile_X11Y7_RES1_O0, Tile_X11Y7_RES1_O1, Tile_X11Y7_RES1_O2, Tile_X11Y7_RES1_O3, Tile_X11Y7_RES2_O0, Tile_X11Y7_RES2_O1, Tile_X11Y7_RES2_O2, Tile_X11Y7_RES2_O3, Tile_X3Y8_OPA_I0, Tile_X3Y8_OPA_I1, Tile_X3Y8_OPA_I2, Tile_X3Y8_OPA_I3, Tile_X3Y8_OPB_I0, Tile_X3Y8_OPB_I1, Tile_X3Y8_OPB_I2, Tile_X3Y8_OPB_I3, Tile_X3Y8_RES0_O0, Tile_X3Y8_RES0_O1, Tile_X3Y8_RES0_O2, Tile_X3Y8_RES0_O3, Tile_X3Y8_RES1_O0, Tile_X3Y8_RES1_O1, Tile_X3Y8_RES1_O2, Tile_X3Y8_RES1_O3, Tile_X3Y8_RES2_O0, Tile_X3Y8_RES2_O1, Tile_X3Y8_RES2_O2, Tile_X3Y8_RES2_O3, Tile_X11Y8_OPA_I0, Tile_X11Y8_OPA_I1, Tile_X11Y8_OPA_I2, Tile_X11Y8_OPA_I3, Tile_X11Y8_OPB_I0, Tile_X11Y8_OPB_I1, Tile_X11Y8_OPB_I2, Tile_X11Y8_OPB_I3, Tile_X11Y8_RES0_O0, Tile_X11Y8_RES0_O1, Tile_X11Y8_RES0_O2, Tile_X11Y8_RES0_O3, Tile_X11Y8_RES1_O0, Tile_X11Y8_RES1_O1, Tile_X11Y8_RES1_O2, Tile_X11Y8_RES1_O3, Tile_X11Y8_RES2_O0, Tile_X11Y8_RES2_O1, Tile_X11Y8_RES2_O2, Tile_X11Y8_RES2_O3, Tile_X3Y9_OPA_I0, Tile_X3Y9_OPA_I1, Tile_X3Y9_OPA_I2, Tile_X3Y9_OPA_I3, Tile_X3Y9_OPB_I0, Tile_X3Y9_OPB_I1, Tile_X3Y9_OPB_I2, Tile_X3Y9_OPB_I3, Tile_X3Y9_RES0_O0, Tile_X3Y9_RES0_O1, Tile_X3Y9_RES0_O2, Tile_X3Y9_RES0_O3, Tile_X3Y9_RES1_O0, Tile_X3Y9_RES1_O1, Tile_X3Y9_RES1_O2, Tile_X3Y9_RES1_O3, Tile_X3Y9_RES2_O0, Tile_X3Y9_RES2_O1, Tile_X3Y9_RES2_O2, Tile_X3Y9_RES2_O3, Tile_X11Y9_OPA_I0, Tile_X11Y9_OPA_I1, Tile_X11Y9_OPA_I2, Tile_X11Y9_OPA_I3, Tile_X11Y9_OPB_I0, Tile_X11Y9_OPB_I1, Tile_X11Y9_OPB_I2, Tile_X11Y9_OPB_I3, Tile_X11Y9_RES0_O0, Tile_X11Y9_RES0_O1, Tile_X11Y9_RES0_O2, Tile_X11Y9_RES0_O3, Tile_X11Y9_RES1_O0, Tile_X11Y9_RES1_O1, Tile_X11Y9_RES1_O2, Tile_X11Y9_RES1_O3, Tile_X11Y9_RES2_O0, Tile_X11Y9_RES2_O1, Tile_X11Y9_RES2_O2, Tile_X11Y9_RES2_O3, Tile_X0Y10_A_I_top, Tile_X0Y10_A_T_top, Tile_X0Y10_A_O_top, Tile_X0Y10_B_I_top, Tile_X0Y10_B_T_top, Tile_X0Y10_B_O_top, Tile_X0Y10_A_config_C_bit0, Tile_X0Y10_A_config_C_bit1, Tile_X0Y10_A_config_C_bit2, Tile_X0Y10_A_config_C_bit3, Tile_X0Y10_B_config_C_bit0, Tile_X0Y10_B_config_C_bit1, Tile_X0Y10_B_config_C_bit2, Tile_X0Y10_B_config_C_bit3, Tile_X14Y10_RAM2FAB_D0_I0, Tile_X14Y10_RAM2FAB_D0_I1, Tile_X14Y10_RAM2FAB_D0_I2, Tile_X14Y10_RAM2FAB_D0_I3, Tile_X14Y10_RAM2FAB_D1_I0, Tile_X14Y10_RAM2FAB_D1_I1, Tile_X14Y10_RAM2FAB_D1_I2, Tile_X14Y10_RAM2FAB_D1_I3, Tile_X14Y10_RAM2FAB_D2_I0, Tile_X14Y10_RAM2FAB_D2_I1, Tile_X14Y10_RAM2FAB_D2_I2, Tile_X14Y10_RAM2FAB_D2_I3, Tile_X14Y10_RAM2FAB_D3_I0, Tile_X14Y10_RAM2FAB_D3_I1, Tile_X14Y10_RAM2FAB_D3_I2, Tile_X14Y10_RAM2FAB_D3_I3, Tile_X14Y10_FAB2RAM_D0_O0, Tile_X14Y10_FAB2RAM_D0_O1, Tile_X14Y10_FAB2RAM_D0_O2, Tile_X14Y10_FAB2RAM_D0_O3, Tile_X14Y10_FAB2RAM_D1_O0, Tile_X14Y10_FAB2RAM_D1_O1, Tile_X14Y10_FAB2RAM_D1_O2, Tile_X14Y10_FAB2RAM_D1_O3, Tile_X14Y10_FAB2RAM_D2_O0, Tile_X14Y10_FAB2RAM_D2_O1, Tile_X14Y10_FAB2RAM_D2_O2, Tile_X14Y10_FAB2RAM_D2_O3, Tile_X14Y10_FAB2RAM_D3_O0, Tile_X14Y10_FAB2RAM_D3_O1, Tile_X14Y10_FAB2RAM_D3_O2, Tile_X14Y10_FAB2RAM_D3_O3, Tile_X14Y10_FAB2RAM_A0_O0, Tile_X14Y10_FAB2RAM_A0_O1, Tile_X14Y10_FAB2RAM_A0_O2, Tile_X14Y10_FAB2RAM_A0_O3, Tile_X14Y10_FAB2RAM_A1_O0, Tile_X14Y10_FAB2RAM_A1_O1, Tile_X14Y10_FAB2RAM_A1_O2, Tile_X14Y10_FAB2RAM_A1_O3, Tile_X14Y10_FAB2RAM_C_O0, Tile_X14Y10_FAB2RAM_C_O1, Tile_X14Y10_FAB2RAM_C_O2, Tile_X14Y10_FAB2RAM_C_O3, Tile_X14Y10_Config_accessC_bit0, Tile_X14Y10_Config_accessC_bit1, Tile_X14Y10_Config_accessC_bit2, Tile_X14Y10_Config_accessC_bit3, Tile_X0Y11_A_I_top, Tile_X0Y11_A_T_top, Tile_X0Y11_A_O_top, Tile_X0Y11_B_I_top, Tile_X0Y11_B_T_top, Tile_X0Y11_B_O_top, Tile_X0Y11_A_config_C_bit0, Tile_X0Y11_A_config_C_bit1, Tile_X0Y11_A_config_C_bit2, Tile_X0Y11_A_config_C_bit3, Tile_X0Y11_B_config_C_bit0, Tile_X0Y11_B_config_C_bit1, Tile_X0Y11_B_config_C_bit2, Tile_X0Y11_B_config_C_bit3, Tile_X14Y11_RAM2FAB_D0_I0, Tile_X14Y11_RAM2FAB_D0_I1, Tile_X14Y11_RAM2FAB_D0_I2, Tile_X14Y11_RAM2FAB_D0_I3, Tile_X14Y11_RAM2FAB_D1_I0, Tile_X14Y11_RAM2FAB_D1_I1, Tile_X14Y11_RAM2FAB_D1_I2, Tile_X14Y11_RAM2FAB_D1_I3, Tile_X14Y11_RAM2FAB_D2_I0, Tile_X14Y11_RAM2FAB_D2_I1, Tile_X14Y11_RAM2FAB_D2_I2, Tile_X14Y11_RAM2FAB_D2_I3, Tile_X14Y11_RAM2FAB_D3_I0, Tile_X14Y11_RAM2FAB_D3_I1, Tile_X14Y11_RAM2FAB_D3_I2, Tile_X14Y11_RAM2FAB_D3_I3, Tile_X14Y11_FAB2RAM_D0_O0, Tile_X14Y11_FAB2RAM_D0_O1, Tile_X14Y11_FAB2RAM_D0_O2, Tile_X14Y11_FAB2RAM_D0_O3, Tile_X14Y11_FAB2RAM_D1_O0, Tile_X14Y11_FAB2RAM_D1_O1, Tile_X14Y11_FAB2RAM_D1_O2, Tile_X14Y11_FAB2RAM_D1_O3, Tile_X14Y11_FAB2RAM_D2_O0, Tile_X14Y11_FAB2RAM_D2_O1, Tile_X14Y11_FAB2RAM_D2_O2, Tile_X14Y11_FAB2RAM_D2_O3, Tile_X14Y11_FAB2RAM_D3_O0, Tile_X14Y11_FAB2RAM_D3_O1, Tile_X14Y11_FAB2RAM_D3_O2, Tile_X14Y11_FAB2RAM_D3_O3, Tile_X14Y11_FAB2RAM_A0_O0, Tile_X14Y11_FAB2RAM_A0_O1, Tile_X14Y11_FAB2RAM_A0_O2, Tile_X14Y11_FAB2RAM_A0_O3, Tile_X14Y11_FAB2RAM_A1_O0, Tile_X14Y11_FAB2RAM_A1_O1, Tile_X14Y11_FAB2RAM_A1_O2, Tile_X14Y11_FAB2RAM_A1_O3, Tile_X14Y11_FAB2RAM_C_O0, Tile_X14Y11_FAB2RAM_C_O1, Tile_X14Y11_FAB2RAM_C_O2, Tile_X14Y11_FAB2RAM_C_O3, Tile_X14Y11_Config_accessC_bit0, Tile_X14Y11_Config_accessC_bit1, Tile_X14Y11_Config_accessC_bit2, Tile_X14Y11_Config_accessC_bit3, Tile_X0Y12_A_I_top, Tile_X0Y12_A_T_top, Tile_X0Y12_A_O_top, Tile_X0Y12_B_I_top, Tile_X0Y12_B_T_top, Tile_X0Y12_B_O_top, Tile_X0Y12_A_config_C_bit0, Tile_X0Y12_A_config_C_bit1, Tile_X0Y12_A_config_C_bit2, Tile_X0Y12_A_config_C_bit3, Tile_X0Y12_B_config_C_bit0, Tile_X0Y12_B_config_C_bit1, Tile_X0Y12_B_config_C_bit2, Tile_X0Y12_B_config_C_bit3, Tile_X14Y12_RAM2FAB_D0_I0, Tile_X14Y12_RAM2FAB_D0_I1, Tile_X14Y12_RAM2FAB_D0_I2, Tile_X14Y12_RAM2FAB_D0_I3, Tile_X14Y12_RAM2FAB_D1_I0, Tile_X14Y12_RAM2FAB_D1_I1, Tile_X14Y12_RAM2FAB_D1_I2, Tile_X14Y12_RAM2FAB_D1_I3, Tile_X14Y12_RAM2FAB_D2_I0, Tile_X14Y12_RAM2FAB_D2_I1, Tile_X14Y12_RAM2FAB_D2_I2, Tile_X14Y12_RAM2FAB_D2_I3, Tile_X14Y12_RAM2FAB_D3_I0, Tile_X14Y12_RAM2FAB_D3_I1, Tile_X14Y12_RAM2FAB_D3_I2, Tile_X14Y12_RAM2FAB_D3_I3, Tile_X14Y12_FAB2RAM_D0_O0, Tile_X14Y12_FAB2RAM_D0_O1, Tile_X14Y12_FAB2RAM_D0_O2, Tile_X14Y12_FAB2RAM_D0_O3, Tile_X14Y12_FAB2RAM_D1_O0, Tile_X14Y12_FAB2RAM_D1_O1, Tile_X14Y12_FAB2RAM_D1_O2, Tile_X14Y12_FAB2RAM_D1_O3, Tile_X14Y12_FAB2RAM_D2_O0, Tile_X14Y12_FAB2RAM_D2_O1, Tile_X14Y12_FAB2RAM_D2_O2, Tile_X14Y12_FAB2RAM_D2_O3, Tile_X14Y12_FAB2RAM_D3_O0, Tile_X14Y12_FAB2RAM_D3_O1, Tile_X14Y12_FAB2RAM_D3_O2, Tile_X14Y12_FAB2RAM_D3_O3, Tile_X14Y12_FAB2RAM_A0_O0, Tile_X14Y12_FAB2RAM_A0_O1, Tile_X14Y12_FAB2RAM_A0_O2, Tile_X14Y12_FAB2RAM_A0_O3, Tile_X14Y12_FAB2RAM_A1_O0, Tile_X14Y12_FAB2RAM_A1_O1, Tile_X14Y12_FAB2RAM_A1_O2, Tile_X14Y12_FAB2RAM_A1_O3, Tile_X14Y12_FAB2RAM_C_O0, Tile_X14Y12_FAB2RAM_C_O1, Tile_X14Y12_FAB2RAM_C_O2, Tile_X14Y12_FAB2RAM_C_O3, Tile_X14Y12_Config_accessC_bit0, Tile_X14Y12_Config_accessC_bit1, Tile_X14Y12_Config_accessC_bit2, Tile_X14Y12_Config_accessC_bit3, Tile_X0Y13_A_I_top, Tile_X0Y13_A_T_top, Tile_X0Y13_A_O_top, Tile_X0Y13_B_I_top, Tile_X0Y13_B_T_top, Tile_X0Y13_B_O_top, Tile_X0Y13_A_config_C_bit0, Tile_X0Y13_A_config_C_bit1, Tile_X0Y13_A_config_C_bit2, Tile_X0Y13_A_config_C_bit3, Tile_X0Y13_B_config_C_bit0, Tile_X0Y13_B_config_C_bit1, Tile_X0Y13_B_config_C_bit2, Tile_X0Y13_B_config_C_bit3, Tile_X14Y13_RAM2FAB_D0_I0, Tile_X14Y13_RAM2FAB_D0_I1, Tile_X14Y13_RAM2FAB_D0_I2, Tile_X14Y13_RAM2FAB_D0_I3, Tile_X14Y13_RAM2FAB_D1_I0, Tile_X14Y13_RAM2FAB_D1_I1, Tile_X14Y13_RAM2FAB_D1_I2, Tile_X14Y13_RAM2FAB_D1_I3, Tile_X14Y13_RAM2FAB_D2_I0, Tile_X14Y13_RAM2FAB_D2_I1, Tile_X14Y13_RAM2FAB_D2_I2, Tile_X14Y13_RAM2FAB_D2_I3, Tile_X14Y13_RAM2FAB_D3_I0, Tile_X14Y13_RAM2FAB_D3_I1, Tile_X14Y13_RAM2FAB_D3_I2, Tile_X14Y13_RAM2FAB_D3_I3, Tile_X14Y13_FAB2RAM_D0_O0, Tile_X14Y13_FAB2RAM_D0_O1, Tile_X14Y13_FAB2RAM_D0_O2, Tile_X14Y13_FAB2RAM_D0_O3, Tile_X14Y13_FAB2RAM_D1_O0, Tile_X14Y13_FAB2RAM_D1_O1, Tile_X14Y13_FAB2RAM_D1_O2, Tile_X14Y13_FAB2RAM_D1_O3, Tile_X14Y13_FAB2RAM_D2_O0, Tile_X14Y13_FAB2RAM_D2_O1, Tile_X14Y13_FAB2RAM_D2_O2, Tile_X14Y13_FAB2RAM_D2_O3, Tile_X14Y13_FAB2RAM_D3_O0, Tile_X14Y13_FAB2RAM_D3_O1, Tile_X14Y13_FAB2RAM_D3_O2, Tile_X14Y13_FAB2RAM_D3_O3, Tile_X14Y13_FAB2RAM_A0_O0, Tile_X14Y13_FAB2RAM_A0_O1, Tile_X14Y13_FAB2RAM_A0_O2, Tile_X14Y13_FAB2RAM_A0_O3, Tile_X14Y13_FAB2RAM_A1_O0, Tile_X14Y13_FAB2RAM_A1_O1, Tile_X14Y13_FAB2RAM_A1_O2, Tile_X14Y13_FAB2RAM_A1_O3, Tile_X14Y13_FAB2RAM_C_O0, Tile_X14Y13_FAB2RAM_C_O1, Tile_X14Y13_FAB2RAM_C_O2, Tile_X14Y13_FAB2RAM_C_O3, Tile_X14Y13_Config_accessC_bit0, Tile_X14Y13_Config_accessC_bit1, Tile_X14Y13_Config_accessC_bit2, Tile_X14Y13_Config_accessC_bit3, Tile_X0Y14_A_I_top, Tile_X0Y14_A_T_top, Tile_X0Y14_A_O_top, Tile_X0Y14_B_I_top, Tile_X0Y14_B_T_top, Tile_X0Y14_B_O_top, Tile_X0Y14_A_config_C_bit0, Tile_X0Y14_A_config_C_bit1, Tile_X0Y14_A_config_C_bit2, Tile_X0Y14_A_config_C_bit3, Tile_X0Y14_B_config_C_bit0, Tile_X0Y14_B_config_C_bit1, Tile_X0Y14_B_config_C_bit2, Tile_X0Y14_B_config_C_bit3, Tile_X14Y14_RAM2FAB_D0_I0, Tile_X14Y14_RAM2FAB_D0_I1, Tile_X14Y14_RAM2FAB_D0_I2, Tile_X14Y14_RAM2FAB_D0_I3, Tile_X14Y14_RAM2FAB_D1_I0, Tile_X14Y14_RAM2FAB_D1_I1, Tile_X14Y14_RAM2FAB_D1_I2, Tile_X14Y14_RAM2FAB_D1_I3, Tile_X14Y14_RAM2FAB_D2_I0, Tile_X14Y14_RAM2FAB_D2_I1, Tile_X14Y14_RAM2FAB_D2_I2, Tile_X14Y14_RAM2FAB_D2_I3, Tile_X14Y14_RAM2FAB_D3_I0, Tile_X14Y14_RAM2FAB_D3_I1, Tile_X14Y14_RAM2FAB_D3_I2, Tile_X14Y14_RAM2FAB_D3_I3, Tile_X14Y14_FAB2RAM_D0_O0, Tile_X14Y14_FAB2RAM_D0_O1, Tile_X14Y14_FAB2RAM_D0_O2, Tile_X14Y14_FAB2RAM_D0_O3, Tile_X14Y14_FAB2RAM_D1_O0, Tile_X14Y14_FAB2RAM_D1_O1, Tile_X14Y14_FAB2RAM_D1_O2, Tile_X14Y14_FAB2RAM_D1_O3, Tile_X14Y14_FAB2RAM_D2_O0, Tile_X14Y14_FAB2RAM_D2_O1, Tile_X14Y14_FAB2RAM_D2_O2, Tile_X14Y14_FAB2RAM_D2_O3, Tile_X14Y14_FAB2RAM_D3_O0, Tile_X14Y14_FAB2RAM_D3_O1, Tile_X14Y14_FAB2RAM_D3_O2, Tile_X14Y14_FAB2RAM_D3_O3, Tile_X14Y14_FAB2RAM_A0_O0, Tile_X14Y14_FAB2RAM_A0_O1, Tile_X14Y14_FAB2RAM_A0_O2, Tile_X14Y14_FAB2RAM_A0_O3, Tile_X14Y14_FAB2RAM_A1_O0, Tile_X14Y14_FAB2RAM_A1_O1, Tile_X14Y14_FAB2RAM_A1_O2, Tile_X14Y14_FAB2RAM_A1_O3, Tile_X14Y14_FAB2RAM_C_O0, Tile_X14Y14_FAB2RAM_C_O1, Tile_X14Y14_FAB2RAM_C_O2, Tile_X14Y14_FAB2RAM_C_O3, Tile_X14Y14_Config_accessC_bit0, Tile_X14Y14_Config_accessC_bit1, Tile_X14Y14_Config_accessC_bit2, Tile_X14Y14_Config_accessC_bit3, FrameData, FrameStrobe);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	input Tile_X3Y1_OPA_I0;  //EXTERNAL
+	input Tile_X3Y1_OPA_I1;  //EXTERNAL
+	input Tile_X3Y1_OPA_I2;  //EXTERNAL
+	input Tile_X3Y1_OPA_I3;  //EXTERNAL
+	input UserCLK;  //EXTERNAL //SHARED_PORT //## the EXTERNAL keyword will send this signal all the way to top and the --SHARED Allows multiple BELs usg the same port (e.g. for exportg a clock to the top)
+	input Tile_X3Y1_OPB_I0;  //EXTERNAL
+	input Tile_X3Y1_OPB_I1;  //EXTERNAL
+	input Tile_X3Y1_OPB_I2;  //EXTERNAL
+	input Tile_X3Y1_OPB_I3;  //EXTERNAL
+	output Tile_X3Y1_RES0_O0;  //EXTERNAL
+	output Tile_X3Y1_RES0_O1;  //EXTERNAL
+	output Tile_X3Y1_RES0_O2;  //EXTERNAL
+	output Tile_X3Y1_RES0_O3;  //EXTERNAL
+	output Tile_X3Y1_RES1_O0;  //EXTERNAL
+	output Tile_X3Y1_RES1_O1;  //EXTERNAL
+	output Tile_X3Y1_RES1_O2;  //EXTERNAL
+	output Tile_X3Y1_RES1_O3;  //EXTERNAL
+	output Tile_X3Y1_RES2_O0;  //EXTERNAL
+	output Tile_X3Y1_RES2_O1;  //EXTERNAL
+	output Tile_X3Y1_RES2_O2;  //EXTERNAL
+	output Tile_X3Y1_RES2_O3;  //EXTERNAL
+	input Tile_X11Y1_OPA_I0;  //EXTERNAL
+	input Tile_X11Y1_OPA_I1;  //EXTERNAL
+	input Tile_X11Y1_OPA_I2;  //EXTERNAL
+	input Tile_X11Y1_OPA_I3;  //EXTERNAL
+	input Tile_X11Y1_OPB_I0;  //EXTERNAL
+	input Tile_X11Y1_OPB_I1;  //EXTERNAL
+	input Tile_X11Y1_OPB_I2;  //EXTERNAL
+	input Tile_X11Y1_OPB_I3;  //EXTERNAL
+	output Tile_X11Y1_RES0_O0;  //EXTERNAL
+	output Tile_X11Y1_RES0_O1;  //EXTERNAL
+	output Tile_X11Y1_RES0_O2;  //EXTERNAL
+	output Tile_X11Y1_RES0_O3;  //EXTERNAL
+	output Tile_X11Y1_RES1_O0;  //EXTERNAL
+	output Tile_X11Y1_RES1_O1;  //EXTERNAL
+	output Tile_X11Y1_RES1_O2;  //EXTERNAL
+	output Tile_X11Y1_RES1_O3;  //EXTERNAL
+	output Tile_X11Y1_RES2_O0;  //EXTERNAL
+	output Tile_X11Y1_RES2_O1;  //EXTERNAL
+	output Tile_X11Y1_RES2_O2;  //EXTERNAL
+	output Tile_X11Y1_RES2_O3;  //EXTERNAL
+	input Tile_X3Y2_OPA_I0;  //EXTERNAL
+	input Tile_X3Y2_OPA_I1;  //EXTERNAL
+	input Tile_X3Y2_OPA_I2;  //EXTERNAL
+	input Tile_X3Y2_OPA_I3;  //EXTERNAL
+	input Tile_X3Y2_OPB_I0;  //EXTERNAL
+	input Tile_X3Y2_OPB_I1;  //EXTERNAL
+	input Tile_X3Y2_OPB_I2;  //EXTERNAL
+	input Tile_X3Y2_OPB_I3;  //EXTERNAL
+	output Tile_X3Y2_RES0_O0;  //EXTERNAL
+	output Tile_X3Y2_RES0_O1;  //EXTERNAL
+	output Tile_X3Y2_RES0_O2;  //EXTERNAL
+	output Tile_X3Y2_RES0_O3;  //EXTERNAL
+	output Tile_X3Y2_RES1_O0;  //EXTERNAL
+	output Tile_X3Y2_RES1_O1;  //EXTERNAL
+	output Tile_X3Y2_RES1_O2;  //EXTERNAL
+	output Tile_X3Y2_RES1_O3;  //EXTERNAL
+	output Tile_X3Y2_RES2_O0;  //EXTERNAL
+	output Tile_X3Y2_RES2_O1;  //EXTERNAL
+	output Tile_X3Y2_RES2_O2;  //EXTERNAL
+	output Tile_X3Y2_RES2_O3;  //EXTERNAL
+	input Tile_X11Y2_OPA_I0;  //EXTERNAL
+	input Tile_X11Y2_OPA_I1;  //EXTERNAL
+	input Tile_X11Y2_OPA_I2;  //EXTERNAL
+	input Tile_X11Y2_OPA_I3;  //EXTERNAL
+	input Tile_X11Y2_OPB_I0;  //EXTERNAL
+	input Tile_X11Y2_OPB_I1;  //EXTERNAL
+	input Tile_X11Y2_OPB_I2;  //EXTERNAL
+	input Tile_X11Y2_OPB_I3;  //EXTERNAL
+	output Tile_X11Y2_RES0_O0;  //EXTERNAL
+	output Tile_X11Y2_RES0_O1;  //EXTERNAL
+	output Tile_X11Y2_RES0_O2;  //EXTERNAL
+	output Tile_X11Y2_RES0_O3;  //EXTERNAL
+	output Tile_X11Y2_RES1_O0;  //EXTERNAL
+	output Tile_X11Y2_RES1_O1;  //EXTERNAL
+	output Tile_X11Y2_RES1_O2;  //EXTERNAL
+	output Tile_X11Y2_RES1_O3;  //EXTERNAL
+	output Tile_X11Y2_RES2_O0;  //EXTERNAL
+	output Tile_X11Y2_RES2_O1;  //EXTERNAL
+	output Tile_X11Y2_RES2_O2;  //EXTERNAL
+	output Tile_X11Y2_RES2_O3;  //EXTERNAL
+	input Tile_X3Y3_OPA_I0;  //EXTERNAL
+	input Tile_X3Y3_OPA_I1;  //EXTERNAL
+	input Tile_X3Y3_OPA_I2;  //EXTERNAL
+	input Tile_X3Y3_OPA_I3;  //EXTERNAL
+	input Tile_X3Y3_OPB_I0;  //EXTERNAL
+	input Tile_X3Y3_OPB_I1;  //EXTERNAL
+	input Tile_X3Y3_OPB_I2;  //EXTERNAL
+	input Tile_X3Y3_OPB_I3;  //EXTERNAL
+	output Tile_X3Y3_RES0_O0;  //EXTERNAL
+	output Tile_X3Y3_RES0_O1;  //EXTERNAL
+	output Tile_X3Y3_RES0_O2;  //EXTERNAL
+	output Tile_X3Y3_RES0_O3;  //EXTERNAL
+	output Tile_X3Y3_RES1_O0;  //EXTERNAL
+	output Tile_X3Y3_RES1_O1;  //EXTERNAL
+	output Tile_X3Y3_RES1_O2;  //EXTERNAL
+	output Tile_X3Y3_RES1_O3;  //EXTERNAL
+	output Tile_X3Y3_RES2_O0;  //EXTERNAL
+	output Tile_X3Y3_RES2_O1;  //EXTERNAL
+	output Tile_X3Y3_RES2_O2;  //EXTERNAL
+	output Tile_X3Y3_RES2_O3;  //EXTERNAL
+	input Tile_X11Y3_OPA_I0;  //EXTERNAL
+	input Tile_X11Y3_OPA_I1;  //EXTERNAL
+	input Tile_X11Y3_OPA_I2;  //EXTERNAL
+	input Tile_X11Y3_OPA_I3;  //EXTERNAL
+	input Tile_X11Y3_OPB_I0;  //EXTERNAL
+	input Tile_X11Y3_OPB_I1;  //EXTERNAL
+	input Tile_X11Y3_OPB_I2;  //EXTERNAL
+	input Tile_X11Y3_OPB_I3;  //EXTERNAL
+	output Tile_X11Y3_RES0_O0;  //EXTERNAL
+	output Tile_X11Y3_RES0_O1;  //EXTERNAL
+	output Tile_X11Y3_RES0_O2;  //EXTERNAL
+	output Tile_X11Y3_RES0_O3;  //EXTERNAL
+	output Tile_X11Y3_RES1_O0;  //EXTERNAL
+	output Tile_X11Y3_RES1_O1;  //EXTERNAL
+	output Tile_X11Y3_RES1_O2;  //EXTERNAL
+	output Tile_X11Y3_RES1_O3;  //EXTERNAL
+	output Tile_X11Y3_RES2_O0;  //EXTERNAL
+	output Tile_X11Y3_RES2_O1;  //EXTERNAL
+	output Tile_X11Y3_RES2_O2;  //EXTERNAL
+	output Tile_X11Y3_RES2_O3;  //EXTERNAL
+	input Tile_X3Y4_OPA_I0;  //EXTERNAL
+	input Tile_X3Y4_OPA_I1;  //EXTERNAL
+	input Tile_X3Y4_OPA_I2;  //EXTERNAL
+	input Tile_X3Y4_OPA_I3;  //EXTERNAL
+	input Tile_X3Y4_OPB_I0;  //EXTERNAL
+	input Tile_X3Y4_OPB_I1;  //EXTERNAL
+	input Tile_X3Y4_OPB_I2;  //EXTERNAL
+	input Tile_X3Y4_OPB_I3;  //EXTERNAL
+	output Tile_X3Y4_RES0_O0;  //EXTERNAL
+	output Tile_X3Y4_RES0_O1;  //EXTERNAL
+	output Tile_X3Y4_RES0_O2;  //EXTERNAL
+	output Tile_X3Y4_RES0_O3;  //EXTERNAL
+	output Tile_X3Y4_RES1_O0;  //EXTERNAL
+	output Tile_X3Y4_RES1_O1;  //EXTERNAL
+	output Tile_X3Y4_RES1_O2;  //EXTERNAL
+	output Tile_X3Y4_RES1_O3;  //EXTERNAL
+	output Tile_X3Y4_RES2_O0;  //EXTERNAL
+	output Tile_X3Y4_RES2_O1;  //EXTERNAL
+	output Tile_X3Y4_RES2_O2;  //EXTERNAL
+	output Tile_X3Y4_RES2_O3;  //EXTERNAL
+	input Tile_X11Y4_OPA_I0;  //EXTERNAL
+	input Tile_X11Y4_OPA_I1;  //EXTERNAL
+	input Tile_X11Y4_OPA_I2;  //EXTERNAL
+	input Tile_X11Y4_OPA_I3;  //EXTERNAL
+	input Tile_X11Y4_OPB_I0;  //EXTERNAL
+	input Tile_X11Y4_OPB_I1;  //EXTERNAL
+	input Tile_X11Y4_OPB_I2;  //EXTERNAL
+	input Tile_X11Y4_OPB_I3;  //EXTERNAL
+	output Tile_X11Y4_RES0_O0;  //EXTERNAL
+	output Tile_X11Y4_RES0_O1;  //EXTERNAL
+	output Tile_X11Y4_RES0_O2;  //EXTERNAL
+	output Tile_X11Y4_RES0_O3;  //EXTERNAL
+	output Tile_X11Y4_RES1_O0;  //EXTERNAL
+	output Tile_X11Y4_RES1_O1;  //EXTERNAL
+	output Tile_X11Y4_RES1_O2;  //EXTERNAL
+	output Tile_X11Y4_RES1_O3;  //EXTERNAL
+	output Tile_X11Y4_RES2_O0;  //EXTERNAL
+	output Tile_X11Y4_RES2_O1;  //EXTERNAL
+	output Tile_X11Y4_RES2_O2;  //EXTERNAL
+	output Tile_X11Y4_RES2_O3;  //EXTERNAL
+	input Tile_X3Y5_OPA_I0;  //EXTERNAL
+	input Tile_X3Y5_OPA_I1;  //EXTERNAL
+	input Tile_X3Y5_OPA_I2;  //EXTERNAL
+	input Tile_X3Y5_OPA_I3;  //EXTERNAL
+	input Tile_X3Y5_OPB_I0;  //EXTERNAL
+	input Tile_X3Y5_OPB_I1;  //EXTERNAL
+	input Tile_X3Y5_OPB_I2;  //EXTERNAL
+	input Tile_X3Y5_OPB_I3;  //EXTERNAL
+	output Tile_X3Y5_RES0_O0;  //EXTERNAL
+	output Tile_X3Y5_RES0_O1;  //EXTERNAL
+	output Tile_X3Y5_RES0_O2;  //EXTERNAL
+	output Tile_X3Y5_RES0_O3;  //EXTERNAL
+	output Tile_X3Y5_RES1_O0;  //EXTERNAL
+	output Tile_X3Y5_RES1_O1;  //EXTERNAL
+	output Tile_X3Y5_RES1_O2;  //EXTERNAL
+	output Tile_X3Y5_RES1_O3;  //EXTERNAL
+	output Tile_X3Y5_RES2_O0;  //EXTERNAL
+	output Tile_X3Y5_RES2_O1;  //EXTERNAL
+	output Tile_X3Y5_RES2_O2;  //EXTERNAL
+	output Tile_X3Y5_RES2_O3;  //EXTERNAL
+	input Tile_X11Y5_OPA_I0;  //EXTERNAL
+	input Tile_X11Y5_OPA_I1;  //EXTERNAL
+	input Tile_X11Y5_OPA_I2;  //EXTERNAL
+	input Tile_X11Y5_OPA_I3;  //EXTERNAL
+	input Tile_X11Y5_OPB_I0;  //EXTERNAL
+	input Tile_X11Y5_OPB_I1;  //EXTERNAL
+	input Tile_X11Y5_OPB_I2;  //EXTERNAL
+	input Tile_X11Y5_OPB_I3;  //EXTERNAL
+	output Tile_X11Y5_RES0_O0;  //EXTERNAL
+	output Tile_X11Y5_RES0_O1;  //EXTERNAL
+	output Tile_X11Y5_RES0_O2;  //EXTERNAL
+	output Tile_X11Y5_RES0_O3;  //EXTERNAL
+	output Tile_X11Y5_RES1_O0;  //EXTERNAL
+	output Tile_X11Y5_RES1_O1;  //EXTERNAL
+	output Tile_X11Y5_RES1_O2;  //EXTERNAL
+	output Tile_X11Y5_RES1_O3;  //EXTERNAL
+	output Tile_X11Y5_RES2_O0;  //EXTERNAL
+	output Tile_X11Y5_RES2_O1;  //EXTERNAL
+	output Tile_X11Y5_RES2_O2;  //EXTERNAL
+	output Tile_X11Y5_RES2_O3;  //EXTERNAL
+	input Tile_X3Y6_OPA_I0;  //EXTERNAL
+	input Tile_X3Y6_OPA_I1;  //EXTERNAL
+	input Tile_X3Y6_OPA_I2;  //EXTERNAL
+	input Tile_X3Y6_OPA_I3;  //EXTERNAL
+	input Tile_X3Y6_OPB_I0;  //EXTERNAL
+	input Tile_X3Y6_OPB_I1;  //EXTERNAL
+	input Tile_X3Y6_OPB_I2;  //EXTERNAL
+	input Tile_X3Y6_OPB_I3;  //EXTERNAL
+	output Tile_X3Y6_RES0_O0;  //EXTERNAL
+	output Tile_X3Y6_RES0_O1;  //EXTERNAL
+	output Tile_X3Y6_RES0_O2;  //EXTERNAL
+	output Tile_X3Y6_RES0_O3;  //EXTERNAL
+	output Tile_X3Y6_RES1_O0;  //EXTERNAL
+	output Tile_X3Y6_RES1_O1;  //EXTERNAL
+	output Tile_X3Y6_RES1_O2;  //EXTERNAL
+	output Tile_X3Y6_RES1_O3;  //EXTERNAL
+	output Tile_X3Y6_RES2_O0;  //EXTERNAL
+	output Tile_X3Y6_RES2_O1;  //EXTERNAL
+	output Tile_X3Y6_RES2_O2;  //EXTERNAL
+	output Tile_X3Y6_RES2_O3;  //EXTERNAL
+	input Tile_X11Y6_OPA_I0;  //EXTERNAL
+	input Tile_X11Y6_OPA_I1;  //EXTERNAL
+	input Tile_X11Y6_OPA_I2;  //EXTERNAL
+	input Tile_X11Y6_OPA_I3;  //EXTERNAL
+	input Tile_X11Y6_OPB_I0;  //EXTERNAL
+	input Tile_X11Y6_OPB_I1;  //EXTERNAL
+	input Tile_X11Y6_OPB_I2;  //EXTERNAL
+	input Tile_X11Y6_OPB_I3;  //EXTERNAL
+	output Tile_X11Y6_RES0_O0;  //EXTERNAL
+	output Tile_X11Y6_RES0_O1;  //EXTERNAL
+	output Tile_X11Y6_RES0_O2;  //EXTERNAL
+	output Tile_X11Y6_RES0_O3;  //EXTERNAL
+	output Tile_X11Y6_RES1_O0;  //EXTERNAL
+	output Tile_X11Y6_RES1_O1;  //EXTERNAL
+	output Tile_X11Y6_RES1_O2;  //EXTERNAL
+	output Tile_X11Y6_RES1_O3;  //EXTERNAL
+	output Tile_X11Y6_RES2_O0;  //EXTERNAL
+	output Tile_X11Y6_RES2_O1;  //EXTERNAL
+	output Tile_X11Y6_RES2_O2;  //EXTERNAL
+	output Tile_X11Y6_RES2_O3;  //EXTERNAL
+	input Tile_X3Y7_OPA_I0;  //EXTERNAL
+	input Tile_X3Y7_OPA_I1;  //EXTERNAL
+	input Tile_X3Y7_OPA_I2;  //EXTERNAL
+	input Tile_X3Y7_OPA_I3;  //EXTERNAL
+	input Tile_X3Y7_OPB_I0;  //EXTERNAL
+	input Tile_X3Y7_OPB_I1;  //EXTERNAL
+	input Tile_X3Y7_OPB_I2;  //EXTERNAL
+	input Tile_X3Y7_OPB_I3;  //EXTERNAL
+	output Tile_X3Y7_RES0_O0;  //EXTERNAL
+	output Tile_X3Y7_RES0_O1;  //EXTERNAL
+	output Tile_X3Y7_RES0_O2;  //EXTERNAL
+	output Tile_X3Y7_RES0_O3;  //EXTERNAL
+	output Tile_X3Y7_RES1_O0;  //EXTERNAL
+	output Tile_X3Y7_RES1_O1;  //EXTERNAL
+	output Tile_X3Y7_RES1_O2;  //EXTERNAL
+	output Tile_X3Y7_RES1_O3;  //EXTERNAL
+	output Tile_X3Y7_RES2_O0;  //EXTERNAL
+	output Tile_X3Y7_RES2_O1;  //EXTERNAL
+	output Tile_X3Y7_RES2_O2;  //EXTERNAL
+	output Tile_X3Y7_RES2_O3;  //EXTERNAL
+	input Tile_X11Y7_OPA_I0;  //EXTERNAL
+	input Tile_X11Y7_OPA_I1;  //EXTERNAL
+	input Tile_X11Y7_OPA_I2;  //EXTERNAL
+	input Tile_X11Y7_OPA_I3;  //EXTERNAL
+	input Tile_X11Y7_OPB_I0;  //EXTERNAL
+	input Tile_X11Y7_OPB_I1;  //EXTERNAL
+	input Tile_X11Y7_OPB_I2;  //EXTERNAL
+	input Tile_X11Y7_OPB_I3;  //EXTERNAL
+	output Tile_X11Y7_RES0_O0;  //EXTERNAL
+	output Tile_X11Y7_RES0_O1;  //EXTERNAL
+	output Tile_X11Y7_RES0_O2;  //EXTERNAL
+	output Tile_X11Y7_RES0_O3;  //EXTERNAL
+	output Tile_X11Y7_RES1_O0;  //EXTERNAL
+	output Tile_X11Y7_RES1_O1;  //EXTERNAL
+	output Tile_X11Y7_RES1_O2;  //EXTERNAL
+	output Tile_X11Y7_RES1_O3;  //EXTERNAL
+	output Tile_X11Y7_RES2_O0;  //EXTERNAL
+	output Tile_X11Y7_RES2_O1;  //EXTERNAL
+	output Tile_X11Y7_RES2_O2;  //EXTERNAL
+	output Tile_X11Y7_RES2_O3;  //EXTERNAL
+	input Tile_X3Y8_OPA_I0;  //EXTERNAL
+	input Tile_X3Y8_OPA_I1;  //EXTERNAL
+	input Tile_X3Y8_OPA_I2;  //EXTERNAL
+	input Tile_X3Y8_OPA_I3;  //EXTERNAL
+	input Tile_X3Y8_OPB_I0;  //EXTERNAL
+	input Tile_X3Y8_OPB_I1;  //EXTERNAL
+	input Tile_X3Y8_OPB_I2;  //EXTERNAL
+	input Tile_X3Y8_OPB_I3;  //EXTERNAL
+	output Tile_X3Y8_RES0_O0;  //EXTERNAL
+	output Tile_X3Y8_RES0_O1;  //EXTERNAL
+	output Tile_X3Y8_RES0_O2;  //EXTERNAL
+	output Tile_X3Y8_RES0_O3;  //EXTERNAL
+	output Tile_X3Y8_RES1_O0;  //EXTERNAL
+	output Tile_X3Y8_RES1_O1;  //EXTERNAL
+	output Tile_X3Y8_RES1_O2;  //EXTERNAL
+	output Tile_X3Y8_RES1_O3;  //EXTERNAL
+	output Tile_X3Y8_RES2_O0;  //EXTERNAL
+	output Tile_X3Y8_RES2_O1;  //EXTERNAL
+	output Tile_X3Y8_RES2_O2;  //EXTERNAL
+	output Tile_X3Y8_RES2_O3;  //EXTERNAL
+	input Tile_X11Y8_OPA_I0;  //EXTERNAL
+	input Tile_X11Y8_OPA_I1;  //EXTERNAL
+	input Tile_X11Y8_OPA_I2;  //EXTERNAL
+	input Tile_X11Y8_OPA_I3;  //EXTERNAL
+	input Tile_X11Y8_OPB_I0;  //EXTERNAL
+	input Tile_X11Y8_OPB_I1;  //EXTERNAL
+	input Tile_X11Y8_OPB_I2;  //EXTERNAL
+	input Tile_X11Y8_OPB_I3;  //EXTERNAL
+	output Tile_X11Y8_RES0_O0;  //EXTERNAL
+	output Tile_X11Y8_RES0_O1;  //EXTERNAL
+	output Tile_X11Y8_RES0_O2;  //EXTERNAL
+	output Tile_X11Y8_RES0_O3;  //EXTERNAL
+	output Tile_X11Y8_RES1_O0;  //EXTERNAL
+	output Tile_X11Y8_RES1_O1;  //EXTERNAL
+	output Tile_X11Y8_RES1_O2;  //EXTERNAL
+	output Tile_X11Y8_RES1_O3;  //EXTERNAL
+	output Tile_X11Y8_RES2_O0;  //EXTERNAL
+	output Tile_X11Y8_RES2_O1;  //EXTERNAL
+	output Tile_X11Y8_RES2_O2;  //EXTERNAL
+	output Tile_X11Y8_RES2_O3;  //EXTERNAL
+	input Tile_X3Y9_OPA_I0;  //EXTERNAL
+	input Tile_X3Y9_OPA_I1;  //EXTERNAL
+	input Tile_X3Y9_OPA_I2;  //EXTERNAL
+	input Tile_X3Y9_OPA_I3;  //EXTERNAL
+	input Tile_X3Y9_OPB_I0;  //EXTERNAL
+	input Tile_X3Y9_OPB_I1;  //EXTERNAL
+	input Tile_X3Y9_OPB_I2;  //EXTERNAL
+	input Tile_X3Y9_OPB_I3;  //EXTERNAL
+	output Tile_X3Y9_RES0_O0;  //EXTERNAL
+	output Tile_X3Y9_RES0_O1;  //EXTERNAL
+	output Tile_X3Y9_RES0_O2;  //EXTERNAL
+	output Tile_X3Y9_RES0_O3;  //EXTERNAL
+	output Tile_X3Y9_RES1_O0;  //EXTERNAL
+	output Tile_X3Y9_RES1_O1;  //EXTERNAL
+	output Tile_X3Y9_RES1_O2;  //EXTERNAL
+	output Tile_X3Y9_RES1_O3;  //EXTERNAL
+	output Tile_X3Y9_RES2_O0;  //EXTERNAL
+	output Tile_X3Y9_RES2_O1;  //EXTERNAL
+	output Tile_X3Y9_RES2_O2;  //EXTERNAL
+	output Tile_X3Y9_RES2_O3;  //EXTERNAL
+	input Tile_X11Y9_OPA_I0;  //EXTERNAL
+	input Tile_X11Y9_OPA_I1;  //EXTERNAL
+	input Tile_X11Y9_OPA_I2;  //EXTERNAL
+	input Tile_X11Y9_OPA_I3;  //EXTERNAL
+	input Tile_X11Y9_OPB_I0;  //EXTERNAL
+	input Tile_X11Y9_OPB_I1;  //EXTERNAL
+	input Tile_X11Y9_OPB_I2;  //EXTERNAL
+	input Tile_X11Y9_OPB_I3;  //EXTERNAL
+	output Tile_X11Y9_RES0_O0;  //EXTERNAL
+	output Tile_X11Y9_RES0_O1;  //EXTERNAL
+	output Tile_X11Y9_RES0_O2;  //EXTERNAL
+	output Tile_X11Y9_RES0_O3;  //EXTERNAL
+	output Tile_X11Y9_RES1_O0;  //EXTERNAL
+	output Tile_X11Y9_RES1_O1;  //EXTERNAL
+	output Tile_X11Y9_RES1_O2;  //EXTERNAL
+	output Tile_X11Y9_RES1_O3;  //EXTERNAL
+	output Tile_X11Y9_RES2_O0;  //EXTERNAL
+	output Tile_X11Y9_RES2_O1;  //EXTERNAL
+	output Tile_X11Y9_RES2_O2;  //EXTERNAL
+	output Tile_X11Y9_RES2_O3;  //EXTERNAL
+	output Tile_X0Y10_A_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y10_A_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y10_A_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y10_B_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y10_B_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y10_B_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y10_A_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y10_A_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y10_A_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y10_A_config_C_bit3;  //EXTERNAL
+	output Tile_X0Y10_B_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y10_B_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y10_B_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y10_B_config_C_bit3;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D0_I0;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D0_I1;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D0_I2;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D0_I3;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D1_I0;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D1_I1;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D1_I2;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D1_I3;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D2_I0;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D2_I1;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D2_I2;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D2_I3;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D3_I0;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D3_I1;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D3_I2;  //EXTERNAL
+	input Tile_X14Y10_RAM2FAB_D3_I3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D0_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D0_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D0_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D0_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D1_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D1_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D1_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D1_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D2_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D2_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D2_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D2_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D3_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D3_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D3_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_D3_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A0_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A0_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A0_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A0_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A1_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A1_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A1_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_A1_O3;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_C_O0;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_C_O1;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_C_O2;  //EXTERNAL
+	output Tile_X14Y10_FAB2RAM_C_O3;  //EXTERNAL
+	output Tile_X14Y10_Config_accessC_bit0;  //EXTERNAL
+	output Tile_X14Y10_Config_accessC_bit1;  //EXTERNAL
+	output Tile_X14Y10_Config_accessC_bit2;  //EXTERNAL
+	output Tile_X14Y10_Config_accessC_bit3;  //EXTERNAL
+	output Tile_X0Y11_A_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y11_A_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y11_A_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y11_B_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y11_B_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y11_B_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y11_A_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y11_A_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y11_A_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y11_A_config_C_bit3;  //EXTERNAL
+	output Tile_X0Y11_B_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y11_B_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y11_B_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y11_B_config_C_bit3;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D0_I0;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D0_I1;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D0_I2;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D0_I3;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D1_I0;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D1_I1;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D1_I2;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D1_I3;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D2_I0;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D2_I1;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D2_I2;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D2_I3;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D3_I0;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D3_I1;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D3_I2;  //EXTERNAL
+	input Tile_X14Y11_RAM2FAB_D3_I3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D0_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D0_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D0_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D0_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D1_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D1_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D1_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D1_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D2_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D2_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D2_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D2_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D3_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D3_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D3_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_D3_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A0_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A0_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A0_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A0_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A1_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A1_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A1_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_A1_O3;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_C_O0;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_C_O1;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_C_O2;  //EXTERNAL
+	output Tile_X14Y11_FAB2RAM_C_O3;  //EXTERNAL
+	output Tile_X14Y11_Config_accessC_bit0;  //EXTERNAL
+	output Tile_X14Y11_Config_accessC_bit1;  //EXTERNAL
+	output Tile_X14Y11_Config_accessC_bit2;  //EXTERNAL
+	output Tile_X14Y11_Config_accessC_bit3;  //EXTERNAL
+	output Tile_X0Y12_A_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y12_A_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y12_A_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y12_B_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y12_B_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y12_B_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y12_A_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y12_A_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y12_A_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y12_A_config_C_bit3;  //EXTERNAL
+	output Tile_X0Y12_B_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y12_B_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y12_B_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y12_B_config_C_bit3;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D0_I0;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D0_I1;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D0_I2;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D0_I3;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D1_I0;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D1_I1;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D1_I2;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D1_I3;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D2_I0;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D2_I1;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D2_I2;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D2_I3;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D3_I0;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D3_I1;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D3_I2;  //EXTERNAL
+	input Tile_X14Y12_RAM2FAB_D3_I3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D0_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D0_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D0_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D0_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D1_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D1_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D1_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D1_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D2_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D2_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D2_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D2_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D3_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D3_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D3_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_D3_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A0_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A0_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A0_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A0_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A1_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A1_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A1_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_A1_O3;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_C_O0;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_C_O1;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_C_O2;  //EXTERNAL
+	output Tile_X14Y12_FAB2RAM_C_O3;  //EXTERNAL
+	output Tile_X14Y12_Config_accessC_bit0;  //EXTERNAL
+	output Tile_X14Y12_Config_accessC_bit1;  //EXTERNAL
+	output Tile_X14Y12_Config_accessC_bit2;  //EXTERNAL
+	output Tile_X14Y12_Config_accessC_bit3;  //EXTERNAL
+	output Tile_X0Y13_A_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y13_A_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y13_A_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y13_B_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y13_B_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y13_B_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y13_A_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y13_A_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y13_A_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y13_A_config_C_bit3;  //EXTERNAL
+	output Tile_X0Y13_B_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y13_B_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y13_B_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y13_B_config_C_bit3;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D0_I0;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D0_I1;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D0_I2;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D0_I3;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D1_I0;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D1_I1;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D1_I2;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D1_I3;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D2_I0;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D2_I1;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D2_I2;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D2_I3;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D3_I0;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D3_I1;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D3_I2;  //EXTERNAL
+	input Tile_X14Y13_RAM2FAB_D3_I3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D0_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D0_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D0_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D0_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D1_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D1_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D1_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D1_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D2_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D2_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D2_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D2_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D3_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D3_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D3_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_D3_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A0_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A0_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A0_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A0_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A1_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A1_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A1_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_A1_O3;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_C_O0;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_C_O1;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_C_O2;  //EXTERNAL
+	output Tile_X14Y13_FAB2RAM_C_O3;  //EXTERNAL
+	output Tile_X14Y13_Config_accessC_bit0;  //EXTERNAL
+	output Tile_X14Y13_Config_accessC_bit1;  //EXTERNAL
+	output Tile_X14Y13_Config_accessC_bit2;  //EXTERNAL
+	output Tile_X14Y13_Config_accessC_bit3;  //EXTERNAL
+	output Tile_X0Y14_A_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y14_A_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y14_A_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y14_B_I_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y14_B_T_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	input Tile_X0Y14_B_O_top;   //EXTERNAL has to ge to top-level entity not the switch matrix
+	output Tile_X0Y14_A_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y14_A_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y14_A_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y14_A_config_C_bit3;  //EXTERNAL
+	output Tile_X0Y14_B_config_C_bit0;  //EXTERNAL
+	output Tile_X0Y14_B_config_C_bit1;  //EXTERNAL
+	output Tile_X0Y14_B_config_C_bit2;  //EXTERNAL
+	output Tile_X0Y14_B_config_C_bit3;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D0_I0;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D0_I1;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D0_I2;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D0_I3;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D1_I0;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D1_I1;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D1_I2;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D1_I3;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D2_I0;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D2_I1;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D2_I2;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D2_I3;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D3_I0;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D3_I1;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D3_I2;  //EXTERNAL
+	input Tile_X14Y14_RAM2FAB_D3_I3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D0_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D0_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D0_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D0_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D1_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D1_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D1_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D1_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D2_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D2_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D2_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D2_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D3_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D3_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D3_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_D3_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A0_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A0_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A0_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A0_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A1_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A1_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A1_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_A1_O3;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_C_O0;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_C_O1;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_C_O2;  //EXTERNAL
+	output Tile_X14Y14_FAB2RAM_C_O3;  //EXTERNAL
+	output Tile_X14Y14_Config_accessC_bit0;  //EXTERNAL
+	output Tile_X14Y14_Config_accessC_bit1;  //EXTERNAL
+	output Tile_X14Y14_Config_accessC_bit2;  //EXTERNAL
+	output Tile_X14Y14_Config_accessC_bit3;  //EXTERNAL
+	input [(FrameBitsPerRow*16)-1:0] FrameData;   // CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	input [(MaxFramesPerCol*15)-1:0] FrameStrobe;   // CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register 
+	//global
+
+
+//signal declarations
+	wire Tile_X0Y0_UserCLKo;
+	wire Tile_X1Y0_UserCLKo;
+	wire Tile_X2Y0_UserCLKo;
+	wire Tile_X3Y0_UserCLKo;
+	wire Tile_X4Y0_UserCLKo;
+	wire Tile_X5Y0_UserCLKo;
+	wire Tile_X6Y0_UserCLKo;
+	wire Tile_X7Y0_UserCLKo;
+	wire Tile_X8Y0_UserCLKo;
+	wire Tile_X9Y0_UserCLKo;
+	wire Tile_X10Y0_UserCLKo;
+	wire Tile_X11Y0_UserCLKo;
+	wire Tile_X12Y0_UserCLKo;
+	wire Tile_X13Y0_UserCLKo;
+	wire Tile_X14Y0_UserCLKo;
+	wire Tile_X0Y1_UserCLKo;
+	wire Tile_X1Y1_UserCLKo;
+	wire Tile_X2Y1_UserCLKo;
+	wire Tile_X3Y1_UserCLKo;
+	wire Tile_X4Y1_UserCLKo;
+	wire Tile_X5Y1_UserCLKo;
+	wire Tile_X6Y1_UserCLKo;
+	wire Tile_X7Y1_UserCLKo;
+	wire Tile_X8Y1_UserCLKo;
+	wire Tile_X9Y1_UserCLKo;
+	wire Tile_X10Y1_UserCLKo;
+	wire Tile_X11Y1_UserCLKo;
+	wire Tile_X12Y1_UserCLKo;
+	wire Tile_X13Y1_UserCLKo;
+	wire Tile_X14Y1_UserCLKo;
+	wire Tile_X0Y2_UserCLKo;
+	wire Tile_X1Y2_UserCLKo;
+	wire Tile_X2Y2_UserCLKo;
+	wire Tile_X3Y2_UserCLKo;
+	wire Tile_X4Y2_UserCLKo;
+	wire Tile_X5Y2_UserCLKo;
+	wire Tile_X6Y2_UserCLKo;
+	wire Tile_X7Y2_UserCLKo;
+	wire Tile_X8Y2_UserCLKo;
+	wire Tile_X9Y2_UserCLKo;
+	wire Tile_X10Y2_UserCLKo;
+	wire Tile_X11Y2_UserCLKo;
+	wire Tile_X12Y2_UserCLKo;
+	wire Tile_X13Y2_UserCLKo;
+	wire Tile_X14Y2_UserCLKo;
+	wire Tile_X0Y3_UserCLKo;
+	wire Tile_X1Y3_UserCLKo;
+	wire Tile_X2Y3_UserCLKo;
+	wire Tile_X3Y3_UserCLKo;
+	wire Tile_X4Y3_UserCLKo;
+	wire Tile_X5Y3_UserCLKo;
+	wire Tile_X6Y3_UserCLKo;
+	wire Tile_X7Y3_UserCLKo;
+	wire Tile_X8Y3_UserCLKo;
+	wire Tile_X9Y3_UserCLKo;
+	wire Tile_X10Y3_UserCLKo;
+	wire Tile_X11Y3_UserCLKo;
+	wire Tile_X12Y3_UserCLKo;
+	wire Tile_X13Y3_UserCLKo;
+	wire Tile_X14Y3_UserCLKo;
+	wire Tile_X0Y4_UserCLKo;
+	wire Tile_X1Y4_UserCLKo;
+	wire Tile_X2Y4_UserCLKo;
+	wire Tile_X3Y4_UserCLKo;
+	wire Tile_X4Y4_UserCLKo;
+	wire Tile_X5Y4_UserCLKo;
+	wire Tile_X6Y4_UserCLKo;
+	wire Tile_X7Y4_UserCLKo;
+	wire Tile_X8Y4_UserCLKo;
+	wire Tile_X9Y4_UserCLKo;
+	wire Tile_X10Y4_UserCLKo;
+	wire Tile_X11Y4_UserCLKo;
+	wire Tile_X12Y4_UserCLKo;
+	wire Tile_X13Y4_UserCLKo;
+	wire Tile_X14Y4_UserCLKo;
+	wire Tile_X0Y5_UserCLKo;
+	wire Tile_X1Y5_UserCLKo;
+	wire Tile_X2Y5_UserCLKo;
+	wire Tile_X3Y5_UserCLKo;
+	wire Tile_X4Y5_UserCLKo;
+	wire Tile_X5Y5_UserCLKo;
+	wire Tile_X6Y5_UserCLKo;
+	wire Tile_X7Y5_UserCLKo;
+	wire Tile_X8Y5_UserCLKo;
+	wire Tile_X9Y5_UserCLKo;
+	wire Tile_X10Y5_UserCLKo;
+	wire Tile_X11Y5_UserCLKo;
+	wire Tile_X12Y5_UserCLKo;
+	wire Tile_X13Y5_UserCLKo;
+	wire Tile_X14Y5_UserCLKo;
+	wire Tile_X0Y6_UserCLKo;
+	wire Tile_X1Y6_UserCLKo;
+	wire Tile_X2Y6_UserCLKo;
+	wire Tile_X3Y6_UserCLKo;
+	wire Tile_X4Y6_UserCLKo;
+	wire Tile_X5Y6_UserCLKo;
+	wire Tile_X6Y6_UserCLKo;
+	wire Tile_X7Y6_UserCLKo;
+	wire Tile_X8Y6_UserCLKo;
+	wire Tile_X9Y6_UserCLKo;
+	wire Tile_X10Y6_UserCLKo;
+	wire Tile_X11Y6_UserCLKo;
+	wire Tile_X12Y6_UserCLKo;
+	wire Tile_X13Y6_UserCLKo;
+	wire Tile_X14Y6_UserCLKo;
+	wire Tile_X0Y7_UserCLKo;
+	wire Tile_X1Y7_UserCLKo;
+	wire Tile_X2Y7_UserCLKo;
+	wire Tile_X3Y7_UserCLKo;
+	wire Tile_X4Y7_UserCLKo;
+	wire Tile_X5Y7_UserCLKo;
+	wire Tile_X6Y7_UserCLKo;
+	wire Tile_X7Y7_UserCLKo;
+	wire Tile_X8Y7_UserCLKo;
+	wire Tile_X9Y7_UserCLKo;
+	wire Tile_X10Y7_UserCLKo;
+	wire Tile_X11Y7_UserCLKo;
+	wire Tile_X12Y7_UserCLKo;
+	wire Tile_X13Y7_UserCLKo;
+	wire Tile_X14Y7_UserCLKo;
+	wire Tile_X0Y8_UserCLKo;
+	wire Tile_X1Y8_UserCLKo;
+	wire Tile_X2Y8_UserCLKo;
+	wire Tile_X3Y8_UserCLKo;
+	wire Tile_X4Y8_UserCLKo;
+	wire Tile_X5Y8_UserCLKo;
+	wire Tile_X6Y8_UserCLKo;
+	wire Tile_X7Y8_UserCLKo;
+	wire Tile_X8Y8_UserCLKo;
+	wire Tile_X9Y8_UserCLKo;
+	wire Tile_X10Y8_UserCLKo;
+	wire Tile_X11Y8_UserCLKo;
+	wire Tile_X12Y8_UserCLKo;
+	wire Tile_X13Y8_UserCLKo;
+	wire Tile_X14Y8_UserCLKo;
+	wire Tile_X0Y9_UserCLKo;
+	wire Tile_X1Y9_UserCLKo;
+	wire Tile_X2Y9_UserCLKo;
+	wire Tile_X3Y9_UserCLKo;
+	wire Tile_X4Y9_UserCLKo;
+	wire Tile_X5Y9_UserCLKo;
+	wire Tile_X6Y9_UserCLKo;
+	wire Tile_X7Y9_UserCLKo;
+	wire Tile_X8Y9_UserCLKo;
+	wire Tile_X9Y9_UserCLKo;
+	wire Tile_X10Y9_UserCLKo;
+	wire Tile_X11Y9_UserCLKo;
+	wire Tile_X12Y9_UserCLKo;
+	wire Tile_X13Y9_UserCLKo;
+	wire Tile_X14Y9_UserCLKo;
+	wire Tile_X0Y10_UserCLKo;
+	wire Tile_X1Y10_UserCLKo;
+	wire Tile_X2Y10_UserCLKo;
+	wire Tile_X3Y10_UserCLKo;
+	wire Tile_X4Y10_UserCLKo;
+	wire Tile_X5Y10_UserCLKo;
+	wire Tile_X6Y10_UserCLKo;
+	wire Tile_X7Y10_UserCLKo;
+	wire Tile_X8Y10_UserCLKo;
+	wire Tile_X9Y10_UserCLKo;
+	wire Tile_X10Y10_UserCLKo;
+	wire Tile_X11Y10_UserCLKo;
+	wire Tile_X12Y10_UserCLKo;
+	wire Tile_X13Y10_UserCLKo;
+	wire Tile_X14Y10_UserCLKo;
+	wire Tile_X0Y11_UserCLKo;
+	wire Tile_X1Y11_UserCLKo;
+	wire Tile_X2Y11_UserCLKo;
+	wire Tile_X3Y11_UserCLKo;
+	wire Tile_X4Y11_UserCLKo;
+	wire Tile_X5Y11_UserCLKo;
+	wire Tile_X6Y11_UserCLKo;
+	wire Tile_X7Y11_UserCLKo;
+	wire Tile_X8Y11_UserCLKo;
+	wire Tile_X9Y11_UserCLKo;
+	wire Tile_X10Y11_UserCLKo;
+	wire Tile_X11Y11_UserCLKo;
+	wire Tile_X12Y11_UserCLKo;
+	wire Tile_X13Y11_UserCLKo;
+	wire Tile_X14Y11_UserCLKo;
+	wire Tile_X0Y12_UserCLKo;
+	wire Tile_X1Y12_UserCLKo;
+	wire Tile_X2Y12_UserCLKo;
+	wire Tile_X3Y12_UserCLKo;
+	wire Tile_X4Y12_UserCLKo;
+	wire Tile_X5Y12_UserCLKo;
+	wire Tile_X6Y12_UserCLKo;
+	wire Tile_X7Y12_UserCLKo;
+	wire Tile_X8Y12_UserCLKo;
+	wire Tile_X9Y12_UserCLKo;
+	wire Tile_X10Y12_UserCLKo;
+	wire Tile_X11Y12_UserCLKo;
+	wire Tile_X12Y12_UserCLKo;
+	wire Tile_X13Y12_UserCLKo;
+	wire Tile_X14Y12_UserCLKo;
+	wire Tile_X0Y13_UserCLKo;
+	wire Tile_X1Y13_UserCLKo;
+	wire Tile_X2Y13_UserCLKo;
+	wire Tile_X3Y13_UserCLKo;
+	wire Tile_X4Y13_UserCLKo;
+	wire Tile_X5Y13_UserCLKo;
+	wire Tile_X6Y13_UserCLKo;
+	wire Tile_X7Y13_UserCLKo;
+	wire Tile_X8Y13_UserCLKo;
+	wire Tile_X9Y13_UserCLKo;
+	wire Tile_X10Y13_UserCLKo;
+	wire Tile_X11Y13_UserCLKo;
+	wire Tile_X12Y13_UserCLKo;
+	wire Tile_X13Y13_UserCLKo;
+	wire Tile_X14Y13_UserCLKo;
+	wire Tile_X0Y14_UserCLKo;
+	wire Tile_X1Y14_UserCLKo;
+	wire Tile_X2Y14_UserCLKo;
+	wire Tile_X3Y14_UserCLKo;
+	wire Tile_X4Y14_UserCLKo;
+	wire Tile_X5Y14_UserCLKo;
+	wire Tile_X6Y14_UserCLKo;
+	wire Tile_X7Y14_UserCLKo;
+	wire Tile_X8Y14_UserCLKo;
+	wire Tile_X9Y14_UserCLKo;
+	wire Tile_X10Y14_UserCLKo;
+	wire Tile_X11Y14_UserCLKo;
+	wire Tile_X12Y14_UserCLKo;
+	wire Tile_X13Y14_UserCLKo;
+	wire Tile_X14Y14_UserCLKo;
+	wire Tile_X0Y15_UserCLKo;
+	wire Tile_X1Y15_UserCLKo;
+	wire Tile_X2Y15_UserCLKo;
+	wire Tile_X3Y15_UserCLKo;
+	wire Tile_X4Y15_UserCLKo;
+	wire Tile_X5Y15_UserCLKo;
+	wire Tile_X6Y15_UserCLKo;
+	wire Tile_X7Y15_UserCLKo;
+	wire Tile_X8Y15_UserCLKo;
+	wire Tile_X9Y15_UserCLKo;
+	wire Tile_X10Y15_UserCLKo;
+	wire Tile_X11Y15_UserCLKo;
+	wire Tile_X12Y15_UserCLKo;
+	wire Tile_X13Y15_UserCLKo;
+	wire Tile_X14Y15_UserCLKo;
+//configuration signal declarations
+
+	wire [FrameBitsPerRow-1:0] Tile_Y1_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y2_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y3_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y4_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y5_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y6_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y7_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y8_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y9_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y10_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y11_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y12_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y13_FrameData;
+	wire [FrameBitsPerRow-1:0] Tile_Y14_FrameData;
+	wire [MaxFramesPerCol-1:0] Tile_X0_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X1_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X2_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X3_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X4_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X5_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X6_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X7_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X8_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X9_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X10_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X11_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X12_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X13_FrameStrobe;
+	wire [MaxFramesPerCol-1:0] Tile_X14_FrameStrobe;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y1_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y2_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y3_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y4_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y5_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y6_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y7_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y8_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y9_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y10_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y11_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y12_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y13_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X0Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X1Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X2Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X3Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X4Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X5Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X6Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X7Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X8Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X9Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X10Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X11Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X12Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X13Y14_FrameData_O;
+	wire [FrameBitsPerRow-1:0] Tile_X14Y14_FrameData_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y0_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y1_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y2_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y3_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y4_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y5_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y6_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y7_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y8_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y9_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y10_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y11_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y12_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y13_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y14_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X0Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X1Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X2Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X3Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X4Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X5Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X6Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X7Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X8Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X9Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X10Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X11Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X12Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X13Y15_FrameStrobe_O;
+	wire [MaxFramesPerCol-1:0] Tile_X14Y15_FrameStrobe_O;
+
+//tile-to-tile signal declarations
+
+	wire [3:0] Tile_X4Y0_S1BEG;
+	wire [7:0] Tile_X4Y0_S2BEG;
+	wire [7:0] Tile_X4Y0_S2BEGb;
+	wire [15:0] Tile_X4Y0_S4BEG;
+	wire [15:0] Tile_X4Y0_SS4BEG;
+	wire [3:0] Tile_X5Y0_S1BEG;
+	wire [7:0] Tile_X5Y0_S2BEG;
+	wire [7:0] Tile_X5Y0_S2BEGb;
+	wire [15:0] Tile_X5Y0_S4BEG;
+	wire [15:0] Tile_X5Y0_SS4BEG;
+	wire [3:0] Tile_X6Y0_S1BEG;
+	wire [7:0] Tile_X6Y0_S2BEG;
+	wire [7:0] Tile_X6Y0_S2BEGb;
+	wire [15:0] Tile_X6Y0_S4BEG;
+	wire [15:0] Tile_X6Y0_SS4BEG;
+	wire [3:0] Tile_X7Y0_S1BEG;
+	wire [7:0] Tile_X7Y0_S2BEG;
+	wire [7:0] Tile_X7Y0_S2BEGb;
+	wire [15:0] Tile_X7Y0_S4BEG;
+	wire [15:0] Tile_X7Y0_SS4BEG;
+	wire [3:0] Tile_X8Y0_S1BEG;
+	wire [7:0] Tile_X8Y0_S2BEG;
+	wire [7:0] Tile_X8Y0_S2BEGb;
+	wire [15:0] Tile_X8Y0_S4BEG;
+	wire [15:0] Tile_X8Y0_SS4BEG;
+	wire [3:0] Tile_X9Y0_S1BEG;
+	wire [7:0] Tile_X9Y0_S2BEG;
+	wire [7:0] Tile_X9Y0_S2BEGb;
+	wire [15:0] Tile_X9Y0_S4BEG;
+	wire [15:0] Tile_X9Y0_SS4BEG;
+	wire [3:0] Tile_X10Y0_S1BEG;
+	wire [7:0] Tile_X10Y0_S2BEG;
+	wire [7:0] Tile_X10Y0_S2BEGb;
+	wire [15:0] Tile_X10Y0_S4BEG;
+	wire [15:0] Tile_X10Y0_SS4BEG;
+	wire [3:0] Tile_X3Y1_E1BEG;
+	wire [7:0] Tile_X3Y1_E2BEG;
+	wire [7:0] Tile_X3Y1_E2BEGb;
+	wire [15:0] Tile_X3Y1_EE4BEG;
+	wire [11:0] Tile_X3Y1_E6BEG;
+	wire [3:0] Tile_X4Y1_N1BEG;
+	wire [7:0] Tile_X4Y1_N2BEG;
+	wire [7:0] Tile_X4Y1_N2BEGb;
+	wire [15:0] Tile_X4Y1_N4BEG;
+	wire [15:0] Tile_X4Y1_NN4BEG;
+	wire [3:0] Tile_X4Y1_E1BEG;
+	wire [7:0] Tile_X4Y1_E2BEG;
+	wire [7:0] Tile_X4Y1_E2BEGb;
+	wire [15:0] Tile_X4Y1_EE4BEG;
+	wire [11:0] Tile_X4Y1_E6BEG;
+	wire [3:0] Tile_X4Y1_S1BEG;
+	wire [7:0] Tile_X4Y1_S2BEG;
+	wire [7:0] Tile_X4Y1_S2BEGb;
+	wire [15:0] Tile_X4Y1_S4BEG;
+	wire [15:0] Tile_X4Y1_SS4BEG;
+	wire [17:0] Tile_X4Y1_top2bot;
+	wire [3:0] Tile_X4Y1_W1BEG;
+	wire [7:0] Tile_X4Y1_W2BEG;
+	wire [7:0] Tile_X4Y1_W2BEGb;
+	wire [15:0] Tile_X4Y1_WW4BEG;
+	wire [11:0] Tile_X4Y1_W6BEG;
+	wire [3:0] Tile_X5Y1_N1BEG;
+	wire [7:0] Tile_X5Y1_N2BEG;
+	wire [7:0] Tile_X5Y1_N2BEGb;
+	wire [15:0] Tile_X5Y1_N4BEG;
+	wire [15:0] Tile_X5Y1_NN4BEG;
+	wire [0:0] Tile_X5Y1_Co;
+	wire [3:0] Tile_X5Y1_E1BEG;
+	wire [7:0] Tile_X5Y1_E2BEG;
+	wire [7:0] Tile_X5Y1_E2BEGb;
+	wire [15:0] Tile_X5Y1_EE4BEG;
+	wire [11:0] Tile_X5Y1_E6BEG;
+	wire [3:0] Tile_X5Y1_S1BEG;
+	wire [7:0] Tile_X5Y1_S2BEG;
+	wire [7:0] Tile_X5Y1_S2BEGb;
+	wire [15:0] Tile_X5Y1_S4BEG;
+	wire [15:0] Tile_X5Y1_SS4BEG;
+	wire [3:0] Tile_X5Y1_W1BEG;
+	wire [7:0] Tile_X5Y1_W2BEG;
+	wire [7:0] Tile_X5Y1_W2BEGb;
+	wire [15:0] Tile_X5Y1_WW4BEG;
+	wire [11:0] Tile_X5Y1_W6BEG;
+	wire [3:0] Tile_X6Y1_N1BEG;
+	wire [7:0] Tile_X6Y1_N2BEG;
+	wire [7:0] Tile_X6Y1_N2BEGb;
+	wire [15:0] Tile_X6Y1_N4BEG;
+	wire [15:0] Tile_X6Y1_NN4BEG;
+	wire [0:0] Tile_X6Y1_Co;
+	wire [3:0] Tile_X6Y1_E1BEG;
+	wire [7:0] Tile_X6Y1_E2BEG;
+	wire [7:0] Tile_X6Y1_E2BEGb;
+	wire [15:0] Tile_X6Y1_EE4BEG;
+	wire [11:0] Tile_X6Y1_E6BEG;
+	wire [3:0] Tile_X6Y1_S1BEG;
+	wire [7:0] Tile_X6Y1_S2BEG;
+	wire [7:0] Tile_X6Y1_S2BEGb;
+	wire [15:0] Tile_X6Y1_S4BEG;
+	wire [15:0] Tile_X6Y1_SS4BEG;
+	wire [3:0] Tile_X6Y1_W1BEG;
+	wire [7:0] Tile_X6Y1_W2BEG;
+	wire [7:0] Tile_X6Y1_W2BEGb;
+	wire [15:0] Tile_X6Y1_WW4BEG;
+	wire [11:0] Tile_X6Y1_W6BEG;
+	wire [3:0] Tile_X7Y1_N1BEG;
+	wire [7:0] Tile_X7Y1_N2BEG;
+	wire [7:0] Tile_X7Y1_N2BEGb;
+	wire [15:0] Tile_X7Y1_N4BEG;
+	wire [15:0] Tile_X7Y1_NN4BEG;
+	wire [0:0] Tile_X7Y1_Co;
+	wire [3:0] Tile_X7Y1_E1BEG;
+	wire [7:0] Tile_X7Y1_E2BEG;
+	wire [7:0] Tile_X7Y1_E2BEGb;
+	wire [15:0] Tile_X7Y1_EE4BEG;
+	wire [11:0] Tile_X7Y1_E6BEG;
+	wire [3:0] Tile_X7Y1_S1BEG;
+	wire [7:0] Tile_X7Y1_S2BEG;
+	wire [7:0] Tile_X7Y1_S2BEGb;
+	wire [15:0] Tile_X7Y1_S4BEG;
+	wire [15:0] Tile_X7Y1_SS4BEG;
+	wire [3:0] Tile_X7Y1_W1BEG;
+	wire [7:0] Tile_X7Y1_W2BEG;
+	wire [7:0] Tile_X7Y1_W2BEGb;
+	wire [15:0] Tile_X7Y1_WW4BEG;
+	wire [11:0] Tile_X7Y1_W6BEG;
+	wire [3:0] Tile_X8Y1_N1BEG;
+	wire [7:0] Tile_X8Y1_N2BEG;
+	wire [7:0] Tile_X8Y1_N2BEGb;
+	wire [15:0] Tile_X8Y1_N4BEG;
+	wire [15:0] Tile_X8Y1_NN4BEG;
+	wire [3:0] Tile_X8Y1_E1BEG;
+	wire [7:0] Tile_X8Y1_E2BEG;
+	wire [7:0] Tile_X8Y1_E2BEGb;
+	wire [15:0] Tile_X8Y1_EE4BEG;
+	wire [11:0] Tile_X8Y1_E6BEG;
+	wire [3:0] Tile_X8Y1_S1BEG;
+	wire [7:0] Tile_X8Y1_S2BEG;
+	wire [7:0] Tile_X8Y1_S2BEGb;
+	wire [15:0] Tile_X8Y1_S4BEG;
+	wire [15:0] Tile_X8Y1_SS4BEG;
+	wire [17:0] Tile_X8Y1_top2bot;
+	wire [3:0] Tile_X8Y1_W1BEG;
+	wire [7:0] Tile_X8Y1_W2BEG;
+	wire [7:0] Tile_X8Y1_W2BEGb;
+	wire [15:0] Tile_X8Y1_WW4BEG;
+	wire [11:0] Tile_X8Y1_W6BEG;
+	wire [3:0] Tile_X9Y1_N1BEG;
+	wire [7:0] Tile_X9Y1_N2BEG;
+	wire [7:0] Tile_X9Y1_N2BEGb;
+	wire [15:0] Tile_X9Y1_N4BEG;
+	wire [15:0] Tile_X9Y1_NN4BEG;
+	wire [0:0] Tile_X9Y1_Co;
+	wire [3:0] Tile_X9Y1_E1BEG;
+	wire [7:0] Tile_X9Y1_E2BEG;
+	wire [7:0] Tile_X9Y1_E2BEGb;
+	wire [15:0] Tile_X9Y1_EE4BEG;
+	wire [11:0] Tile_X9Y1_E6BEG;
+	wire [3:0] Tile_X9Y1_S1BEG;
+	wire [7:0] Tile_X9Y1_S2BEG;
+	wire [7:0] Tile_X9Y1_S2BEGb;
+	wire [15:0] Tile_X9Y1_S4BEG;
+	wire [15:0] Tile_X9Y1_SS4BEG;
+	wire [3:0] Tile_X9Y1_W1BEG;
+	wire [7:0] Tile_X9Y1_W2BEG;
+	wire [7:0] Tile_X9Y1_W2BEGb;
+	wire [15:0] Tile_X9Y1_WW4BEG;
+	wire [11:0] Tile_X9Y1_W6BEG;
+	wire [3:0] Tile_X10Y1_N1BEG;
+	wire [7:0] Tile_X10Y1_N2BEG;
+	wire [7:0] Tile_X10Y1_N2BEGb;
+	wire [15:0] Tile_X10Y1_N4BEG;
+	wire [15:0] Tile_X10Y1_NN4BEG;
+	wire [0:0] Tile_X10Y1_Co;
+	wire [3:0] Tile_X10Y1_E1BEG;
+	wire [7:0] Tile_X10Y1_E2BEG;
+	wire [7:0] Tile_X10Y1_E2BEGb;
+	wire [15:0] Tile_X10Y1_EE4BEG;
+	wire [11:0] Tile_X10Y1_E6BEG;
+	wire [3:0] Tile_X10Y1_S1BEG;
+	wire [7:0] Tile_X10Y1_S2BEG;
+	wire [7:0] Tile_X10Y1_S2BEGb;
+	wire [15:0] Tile_X10Y1_S4BEG;
+	wire [15:0] Tile_X10Y1_SS4BEG;
+	wire [3:0] Tile_X10Y1_W1BEG;
+	wire [7:0] Tile_X10Y1_W2BEG;
+	wire [7:0] Tile_X10Y1_W2BEGb;
+	wire [15:0] Tile_X10Y1_WW4BEG;
+	wire [11:0] Tile_X10Y1_W6BEG;
+	wire [3:0] Tile_X11Y1_W1BEG;
+	wire [7:0] Tile_X11Y1_W2BEG;
+	wire [7:0] Tile_X11Y1_W2BEGb;
+	wire [15:0] Tile_X11Y1_WW4BEG;
+	wire [11:0] Tile_X11Y1_W6BEG;
+	wire [3:0] Tile_X3Y2_E1BEG;
+	wire [7:0] Tile_X3Y2_E2BEG;
+	wire [7:0] Tile_X3Y2_E2BEGb;
+	wire [15:0] Tile_X3Y2_EE4BEG;
+	wire [11:0] Tile_X3Y2_E6BEG;
+	wire [3:0] Tile_X4Y2_N1BEG;
+	wire [7:0] Tile_X4Y2_N2BEG;
+	wire [7:0] Tile_X4Y2_N2BEGb;
+	wire [15:0] Tile_X4Y2_N4BEG;
+	wire [15:0] Tile_X4Y2_NN4BEG;
+	wire [9:0] Tile_X4Y2_bot2top;
+	wire [3:0] Tile_X4Y2_E1BEG;
+	wire [7:0] Tile_X4Y2_E2BEG;
+	wire [7:0] Tile_X4Y2_E2BEGb;
+	wire [15:0] Tile_X4Y2_EE4BEG;
+	wire [11:0] Tile_X4Y2_E6BEG;
+	wire [3:0] Tile_X4Y2_S1BEG;
+	wire [7:0] Tile_X4Y2_S2BEG;
+	wire [7:0] Tile_X4Y2_S2BEGb;
+	wire [15:0] Tile_X4Y2_S4BEG;
+	wire [15:0] Tile_X4Y2_SS4BEG;
+	wire [3:0] Tile_X4Y2_W1BEG;
+	wire [7:0] Tile_X4Y2_W2BEG;
+	wire [7:0] Tile_X4Y2_W2BEGb;
+	wire [15:0] Tile_X4Y2_WW4BEG;
+	wire [11:0] Tile_X4Y2_W6BEG;
+	wire [3:0] Tile_X5Y2_N1BEG;
+	wire [7:0] Tile_X5Y2_N2BEG;
+	wire [7:0] Tile_X5Y2_N2BEGb;
+	wire [15:0] Tile_X5Y2_N4BEG;
+	wire [15:0] Tile_X5Y2_NN4BEG;
+	wire [0:0] Tile_X5Y2_Co;
+	wire [3:0] Tile_X5Y2_E1BEG;
+	wire [7:0] Tile_X5Y2_E2BEG;
+	wire [7:0] Tile_X5Y2_E2BEGb;
+	wire [15:0] Tile_X5Y2_EE4BEG;
+	wire [11:0] Tile_X5Y2_E6BEG;
+	wire [3:0] Tile_X5Y2_S1BEG;
+	wire [7:0] Tile_X5Y2_S2BEG;
+	wire [7:0] Tile_X5Y2_S2BEGb;
+	wire [15:0] Tile_X5Y2_S4BEG;
+	wire [15:0] Tile_X5Y2_SS4BEG;
+	wire [3:0] Tile_X5Y2_W1BEG;
+	wire [7:0] Tile_X5Y2_W2BEG;
+	wire [7:0] Tile_X5Y2_W2BEGb;
+	wire [15:0] Tile_X5Y2_WW4BEG;
+	wire [11:0] Tile_X5Y2_W6BEG;
+	wire [3:0] Tile_X6Y2_N1BEG;
+	wire [7:0] Tile_X6Y2_N2BEG;
+	wire [7:0] Tile_X6Y2_N2BEGb;
+	wire [15:0] Tile_X6Y2_N4BEG;
+	wire [15:0] Tile_X6Y2_NN4BEG;
+	wire [0:0] Tile_X6Y2_Co;
+	wire [3:0] Tile_X6Y2_E1BEG;
+	wire [7:0] Tile_X6Y2_E2BEG;
+	wire [7:0] Tile_X6Y2_E2BEGb;
+	wire [15:0] Tile_X6Y2_EE4BEG;
+	wire [11:0] Tile_X6Y2_E6BEG;
+	wire [3:0] Tile_X6Y2_S1BEG;
+	wire [7:0] Tile_X6Y2_S2BEG;
+	wire [7:0] Tile_X6Y2_S2BEGb;
+	wire [15:0] Tile_X6Y2_S4BEG;
+	wire [15:0] Tile_X6Y2_SS4BEG;
+	wire [3:0] Tile_X6Y2_W1BEG;
+	wire [7:0] Tile_X6Y2_W2BEG;
+	wire [7:0] Tile_X6Y2_W2BEGb;
+	wire [15:0] Tile_X6Y2_WW4BEG;
+	wire [11:0] Tile_X6Y2_W6BEG;
+	wire [3:0] Tile_X7Y2_N1BEG;
+	wire [7:0] Tile_X7Y2_N2BEG;
+	wire [7:0] Tile_X7Y2_N2BEGb;
+	wire [15:0] Tile_X7Y2_N4BEG;
+	wire [15:0] Tile_X7Y2_NN4BEG;
+	wire [0:0] Tile_X7Y2_Co;
+	wire [3:0] Tile_X7Y2_E1BEG;
+	wire [7:0] Tile_X7Y2_E2BEG;
+	wire [7:0] Tile_X7Y2_E2BEGb;
+	wire [15:0] Tile_X7Y2_EE4BEG;
+	wire [11:0] Tile_X7Y2_E6BEG;
+	wire [3:0] Tile_X7Y2_S1BEG;
+	wire [7:0] Tile_X7Y2_S2BEG;
+	wire [7:0] Tile_X7Y2_S2BEGb;
+	wire [15:0] Tile_X7Y2_S4BEG;
+	wire [15:0] Tile_X7Y2_SS4BEG;
+	wire [3:0] Tile_X7Y2_W1BEG;
+	wire [7:0] Tile_X7Y2_W2BEG;
+	wire [7:0] Tile_X7Y2_W2BEGb;
+	wire [15:0] Tile_X7Y2_WW4BEG;
+	wire [11:0] Tile_X7Y2_W6BEG;
+	wire [3:0] Tile_X8Y2_N1BEG;
+	wire [7:0] Tile_X8Y2_N2BEG;
+	wire [7:0] Tile_X8Y2_N2BEGb;
+	wire [15:0] Tile_X8Y2_N4BEG;
+	wire [15:0] Tile_X8Y2_NN4BEG;
+	wire [9:0] Tile_X8Y2_bot2top;
+	wire [3:0] Tile_X8Y2_E1BEG;
+	wire [7:0] Tile_X8Y2_E2BEG;
+	wire [7:0] Tile_X8Y2_E2BEGb;
+	wire [15:0] Tile_X8Y2_EE4BEG;
+	wire [11:0] Tile_X8Y2_E6BEG;
+	wire [3:0] Tile_X8Y2_S1BEG;
+	wire [7:0] Tile_X8Y2_S2BEG;
+	wire [7:0] Tile_X8Y2_S2BEGb;
+	wire [15:0] Tile_X8Y2_S4BEG;
+	wire [15:0] Tile_X8Y2_SS4BEG;
+	wire [3:0] Tile_X8Y2_W1BEG;
+	wire [7:0] Tile_X8Y2_W2BEG;
+	wire [7:0] Tile_X8Y2_W2BEGb;
+	wire [15:0] Tile_X8Y2_WW4BEG;
+	wire [11:0] Tile_X8Y2_W6BEG;
+	wire [3:0] Tile_X9Y2_N1BEG;
+	wire [7:0] Tile_X9Y2_N2BEG;
+	wire [7:0] Tile_X9Y2_N2BEGb;
+	wire [15:0] Tile_X9Y2_N4BEG;
+	wire [15:0] Tile_X9Y2_NN4BEG;
+	wire [0:0] Tile_X9Y2_Co;
+	wire [3:0] Tile_X9Y2_E1BEG;
+	wire [7:0] Tile_X9Y2_E2BEG;
+	wire [7:0] Tile_X9Y2_E2BEGb;
+	wire [15:0] Tile_X9Y2_EE4BEG;
+	wire [11:0] Tile_X9Y2_E6BEG;
+	wire [3:0] Tile_X9Y2_S1BEG;
+	wire [7:0] Tile_X9Y2_S2BEG;
+	wire [7:0] Tile_X9Y2_S2BEGb;
+	wire [15:0] Tile_X9Y2_S4BEG;
+	wire [15:0] Tile_X9Y2_SS4BEG;
+	wire [3:0] Tile_X9Y2_W1BEG;
+	wire [7:0] Tile_X9Y2_W2BEG;
+	wire [7:0] Tile_X9Y2_W2BEGb;
+	wire [15:0] Tile_X9Y2_WW4BEG;
+	wire [11:0] Tile_X9Y2_W6BEG;
+	wire [3:0] Tile_X10Y2_N1BEG;
+	wire [7:0] Tile_X10Y2_N2BEG;
+	wire [7:0] Tile_X10Y2_N2BEGb;
+	wire [15:0] Tile_X10Y2_N4BEG;
+	wire [15:0] Tile_X10Y2_NN4BEG;
+	wire [0:0] Tile_X10Y2_Co;
+	wire [3:0] Tile_X10Y2_E1BEG;
+	wire [7:0] Tile_X10Y2_E2BEG;
+	wire [7:0] Tile_X10Y2_E2BEGb;
+	wire [15:0] Tile_X10Y2_EE4BEG;
+	wire [11:0] Tile_X10Y2_E6BEG;
+	wire [3:0] Tile_X10Y2_S1BEG;
+	wire [7:0] Tile_X10Y2_S2BEG;
+	wire [7:0] Tile_X10Y2_S2BEGb;
+	wire [15:0] Tile_X10Y2_S4BEG;
+	wire [15:0] Tile_X10Y2_SS4BEG;
+	wire [3:0] Tile_X10Y2_W1BEG;
+	wire [7:0] Tile_X10Y2_W2BEG;
+	wire [7:0] Tile_X10Y2_W2BEGb;
+	wire [15:0] Tile_X10Y2_WW4BEG;
+	wire [11:0] Tile_X10Y2_W6BEG;
+	wire [3:0] Tile_X11Y2_W1BEG;
+	wire [7:0] Tile_X11Y2_W2BEG;
+	wire [7:0] Tile_X11Y2_W2BEGb;
+	wire [15:0] Tile_X11Y2_WW4BEG;
+	wire [11:0] Tile_X11Y2_W6BEG;
+	wire [3:0] Tile_X3Y3_E1BEG;
+	wire [7:0] Tile_X3Y3_E2BEG;
+	wire [7:0] Tile_X3Y3_E2BEGb;
+	wire [15:0] Tile_X3Y3_EE4BEG;
+	wire [11:0] Tile_X3Y3_E6BEG;
+	wire [3:0] Tile_X4Y3_N1BEG;
+	wire [7:0] Tile_X4Y3_N2BEG;
+	wire [7:0] Tile_X4Y3_N2BEGb;
+	wire [15:0] Tile_X4Y3_N4BEG;
+	wire [15:0] Tile_X4Y3_NN4BEG;
+	wire [3:0] Tile_X4Y3_E1BEG;
+	wire [7:0] Tile_X4Y3_E2BEG;
+	wire [7:0] Tile_X4Y3_E2BEGb;
+	wire [15:0] Tile_X4Y3_EE4BEG;
+	wire [11:0] Tile_X4Y3_E6BEG;
+	wire [3:0] Tile_X4Y3_S1BEG;
+	wire [7:0] Tile_X4Y3_S2BEG;
+	wire [7:0] Tile_X4Y3_S2BEGb;
+	wire [15:0] Tile_X4Y3_S4BEG;
+	wire [15:0] Tile_X4Y3_SS4BEG;
+	wire [17:0] Tile_X4Y3_top2bot;
+	wire [3:0] Tile_X4Y3_W1BEG;
+	wire [7:0] Tile_X4Y3_W2BEG;
+	wire [7:0] Tile_X4Y3_W2BEGb;
+	wire [15:0] Tile_X4Y3_WW4BEG;
+	wire [11:0] Tile_X4Y3_W6BEG;
+	wire [3:0] Tile_X5Y3_N1BEG;
+	wire [7:0] Tile_X5Y3_N2BEG;
+	wire [7:0] Tile_X5Y3_N2BEGb;
+	wire [15:0] Tile_X5Y3_N4BEG;
+	wire [15:0] Tile_X5Y3_NN4BEG;
+	wire [0:0] Tile_X5Y3_Co;
+	wire [3:0] Tile_X5Y3_E1BEG;
+	wire [7:0] Tile_X5Y3_E2BEG;
+	wire [7:0] Tile_X5Y3_E2BEGb;
+	wire [15:0] Tile_X5Y3_EE4BEG;
+	wire [11:0] Tile_X5Y3_E6BEG;
+	wire [3:0] Tile_X5Y3_S1BEG;
+	wire [7:0] Tile_X5Y3_S2BEG;
+	wire [7:0] Tile_X5Y3_S2BEGb;
+	wire [15:0] Tile_X5Y3_S4BEG;
+	wire [15:0] Tile_X5Y3_SS4BEG;
+	wire [3:0] Tile_X5Y3_W1BEG;
+	wire [7:0] Tile_X5Y3_W2BEG;
+	wire [7:0] Tile_X5Y3_W2BEGb;
+	wire [15:0] Tile_X5Y3_WW4BEG;
+	wire [11:0] Tile_X5Y3_W6BEG;
+	wire [3:0] Tile_X6Y3_N1BEG;
+	wire [7:0] Tile_X6Y3_N2BEG;
+	wire [7:0] Tile_X6Y3_N2BEGb;
+	wire [15:0] Tile_X6Y3_N4BEG;
+	wire [15:0] Tile_X6Y3_NN4BEG;
+	wire [0:0] Tile_X6Y3_Co;
+	wire [3:0] Tile_X6Y3_E1BEG;
+	wire [7:0] Tile_X6Y3_E2BEG;
+	wire [7:0] Tile_X6Y3_E2BEGb;
+	wire [15:0] Tile_X6Y3_EE4BEG;
+	wire [11:0] Tile_X6Y3_E6BEG;
+	wire [3:0] Tile_X6Y3_S1BEG;
+	wire [7:0] Tile_X6Y3_S2BEG;
+	wire [7:0] Tile_X6Y3_S2BEGb;
+	wire [15:0] Tile_X6Y3_S4BEG;
+	wire [15:0] Tile_X6Y3_SS4BEG;
+	wire [3:0] Tile_X6Y3_W1BEG;
+	wire [7:0] Tile_X6Y3_W2BEG;
+	wire [7:0] Tile_X6Y3_W2BEGb;
+	wire [15:0] Tile_X6Y3_WW4BEG;
+	wire [11:0] Tile_X6Y3_W6BEG;
+	wire [3:0] Tile_X7Y3_N1BEG;
+	wire [7:0] Tile_X7Y3_N2BEG;
+	wire [7:0] Tile_X7Y3_N2BEGb;
+	wire [15:0] Tile_X7Y3_N4BEG;
+	wire [15:0] Tile_X7Y3_NN4BEG;
+	wire [0:0] Tile_X7Y3_Co;
+	wire [3:0] Tile_X7Y3_E1BEG;
+	wire [7:0] Tile_X7Y3_E2BEG;
+	wire [7:0] Tile_X7Y3_E2BEGb;
+	wire [15:0] Tile_X7Y3_EE4BEG;
+	wire [11:0] Tile_X7Y3_E6BEG;
+	wire [3:0] Tile_X7Y3_S1BEG;
+	wire [7:0] Tile_X7Y3_S2BEG;
+	wire [7:0] Tile_X7Y3_S2BEGb;
+	wire [15:0] Tile_X7Y3_S4BEG;
+	wire [15:0] Tile_X7Y3_SS4BEG;
+	wire [3:0] Tile_X7Y3_W1BEG;
+	wire [7:0] Tile_X7Y3_W2BEG;
+	wire [7:0] Tile_X7Y3_W2BEGb;
+	wire [15:0] Tile_X7Y3_WW4BEG;
+	wire [11:0] Tile_X7Y3_W6BEG;
+	wire [3:0] Tile_X8Y3_N1BEG;
+	wire [7:0] Tile_X8Y3_N2BEG;
+	wire [7:0] Tile_X8Y3_N2BEGb;
+	wire [15:0] Tile_X8Y3_N4BEG;
+	wire [15:0] Tile_X8Y3_NN4BEG;
+	wire [3:0] Tile_X8Y3_E1BEG;
+	wire [7:0] Tile_X8Y3_E2BEG;
+	wire [7:0] Tile_X8Y3_E2BEGb;
+	wire [15:0] Tile_X8Y3_EE4BEG;
+	wire [11:0] Tile_X8Y3_E6BEG;
+	wire [3:0] Tile_X8Y3_S1BEG;
+	wire [7:0] Tile_X8Y3_S2BEG;
+	wire [7:0] Tile_X8Y3_S2BEGb;
+	wire [15:0] Tile_X8Y3_S4BEG;
+	wire [15:0] Tile_X8Y3_SS4BEG;
+	wire [17:0] Tile_X8Y3_top2bot;
+	wire [3:0] Tile_X8Y3_W1BEG;
+	wire [7:0] Tile_X8Y3_W2BEG;
+	wire [7:0] Tile_X8Y3_W2BEGb;
+	wire [15:0] Tile_X8Y3_WW4BEG;
+	wire [11:0] Tile_X8Y3_W6BEG;
+	wire [3:0] Tile_X9Y3_N1BEG;
+	wire [7:0] Tile_X9Y3_N2BEG;
+	wire [7:0] Tile_X9Y3_N2BEGb;
+	wire [15:0] Tile_X9Y3_N4BEG;
+	wire [15:0] Tile_X9Y3_NN4BEG;
+	wire [0:0] Tile_X9Y3_Co;
+	wire [3:0] Tile_X9Y3_E1BEG;
+	wire [7:0] Tile_X9Y3_E2BEG;
+	wire [7:0] Tile_X9Y3_E2BEGb;
+	wire [15:0] Tile_X9Y3_EE4BEG;
+	wire [11:0] Tile_X9Y3_E6BEG;
+	wire [3:0] Tile_X9Y3_S1BEG;
+	wire [7:0] Tile_X9Y3_S2BEG;
+	wire [7:0] Tile_X9Y3_S2BEGb;
+	wire [15:0] Tile_X9Y3_S4BEG;
+	wire [15:0] Tile_X9Y3_SS4BEG;
+	wire [3:0] Tile_X9Y3_W1BEG;
+	wire [7:0] Tile_X9Y3_W2BEG;
+	wire [7:0] Tile_X9Y3_W2BEGb;
+	wire [15:0] Tile_X9Y3_WW4BEG;
+	wire [11:0] Tile_X9Y3_W6BEG;
+	wire [3:0] Tile_X10Y3_N1BEG;
+	wire [7:0] Tile_X10Y3_N2BEG;
+	wire [7:0] Tile_X10Y3_N2BEGb;
+	wire [15:0] Tile_X10Y3_N4BEG;
+	wire [15:0] Tile_X10Y3_NN4BEG;
+	wire [0:0] Tile_X10Y3_Co;
+	wire [3:0] Tile_X10Y3_E1BEG;
+	wire [7:0] Tile_X10Y3_E2BEG;
+	wire [7:0] Tile_X10Y3_E2BEGb;
+	wire [15:0] Tile_X10Y3_EE4BEG;
+	wire [11:0] Tile_X10Y3_E6BEG;
+	wire [3:0] Tile_X10Y3_S1BEG;
+	wire [7:0] Tile_X10Y3_S2BEG;
+	wire [7:0] Tile_X10Y3_S2BEGb;
+	wire [15:0] Tile_X10Y3_S4BEG;
+	wire [15:0] Tile_X10Y3_SS4BEG;
+	wire [3:0] Tile_X10Y3_W1BEG;
+	wire [7:0] Tile_X10Y3_W2BEG;
+	wire [7:0] Tile_X10Y3_W2BEGb;
+	wire [15:0] Tile_X10Y3_WW4BEG;
+	wire [11:0] Tile_X10Y3_W6BEG;
+	wire [3:0] Tile_X11Y3_W1BEG;
+	wire [7:0] Tile_X11Y3_W2BEG;
+	wire [7:0] Tile_X11Y3_W2BEGb;
+	wire [15:0] Tile_X11Y3_WW4BEG;
+	wire [11:0] Tile_X11Y3_W6BEG;
+	wire [3:0] Tile_X3Y4_E1BEG;
+	wire [7:0] Tile_X3Y4_E2BEG;
+	wire [7:0] Tile_X3Y4_E2BEGb;
+	wire [15:0] Tile_X3Y4_EE4BEG;
+	wire [11:0] Tile_X3Y4_E6BEG;
+	wire [3:0] Tile_X4Y4_N1BEG;
+	wire [7:0] Tile_X4Y4_N2BEG;
+	wire [7:0] Tile_X4Y4_N2BEGb;
+	wire [15:0] Tile_X4Y4_N4BEG;
+	wire [15:0] Tile_X4Y4_NN4BEG;
+	wire [9:0] Tile_X4Y4_bot2top;
+	wire [3:0] Tile_X4Y4_E1BEG;
+	wire [7:0] Tile_X4Y4_E2BEG;
+	wire [7:0] Tile_X4Y4_E2BEGb;
+	wire [15:0] Tile_X4Y4_EE4BEG;
+	wire [11:0] Tile_X4Y4_E6BEG;
+	wire [3:0] Tile_X4Y4_S1BEG;
+	wire [7:0] Tile_X4Y4_S2BEG;
+	wire [7:0] Tile_X4Y4_S2BEGb;
+	wire [15:0] Tile_X4Y4_S4BEG;
+	wire [15:0] Tile_X4Y4_SS4BEG;
+	wire [3:0] Tile_X4Y4_W1BEG;
+	wire [7:0] Tile_X4Y4_W2BEG;
+	wire [7:0] Tile_X4Y4_W2BEGb;
+	wire [15:0] Tile_X4Y4_WW4BEG;
+	wire [11:0] Tile_X4Y4_W6BEG;
+	wire [3:0] Tile_X5Y4_N1BEG;
+	wire [7:0] Tile_X5Y4_N2BEG;
+	wire [7:0] Tile_X5Y4_N2BEGb;
+	wire [15:0] Tile_X5Y4_N4BEG;
+	wire [15:0] Tile_X5Y4_NN4BEG;
+	wire [0:0] Tile_X5Y4_Co;
+	wire [3:0] Tile_X5Y4_E1BEG;
+	wire [7:0] Tile_X5Y4_E2BEG;
+	wire [7:0] Tile_X5Y4_E2BEGb;
+	wire [15:0] Tile_X5Y4_EE4BEG;
+	wire [11:0] Tile_X5Y4_E6BEG;
+	wire [3:0] Tile_X5Y4_S1BEG;
+	wire [7:0] Tile_X5Y4_S2BEG;
+	wire [7:0] Tile_X5Y4_S2BEGb;
+	wire [15:0] Tile_X5Y4_S4BEG;
+	wire [15:0] Tile_X5Y4_SS4BEG;
+	wire [3:0] Tile_X5Y4_W1BEG;
+	wire [7:0] Tile_X5Y4_W2BEG;
+	wire [7:0] Tile_X5Y4_W2BEGb;
+	wire [15:0] Tile_X5Y4_WW4BEG;
+	wire [11:0] Tile_X5Y4_W6BEG;
+	wire [3:0] Tile_X6Y4_N1BEG;
+	wire [7:0] Tile_X6Y4_N2BEG;
+	wire [7:0] Tile_X6Y4_N2BEGb;
+	wire [15:0] Tile_X6Y4_N4BEG;
+	wire [15:0] Tile_X6Y4_NN4BEG;
+	wire [0:0] Tile_X6Y4_Co;
+	wire [3:0] Tile_X6Y4_E1BEG;
+	wire [7:0] Tile_X6Y4_E2BEG;
+	wire [7:0] Tile_X6Y4_E2BEGb;
+	wire [15:0] Tile_X6Y4_EE4BEG;
+	wire [11:0] Tile_X6Y4_E6BEG;
+	wire [3:0] Tile_X6Y4_S1BEG;
+	wire [7:0] Tile_X6Y4_S2BEG;
+	wire [7:0] Tile_X6Y4_S2BEGb;
+	wire [15:0] Tile_X6Y4_S4BEG;
+	wire [15:0] Tile_X6Y4_SS4BEG;
+	wire [3:0] Tile_X6Y4_W1BEG;
+	wire [7:0] Tile_X6Y4_W2BEG;
+	wire [7:0] Tile_X6Y4_W2BEGb;
+	wire [15:0] Tile_X6Y4_WW4BEG;
+	wire [11:0] Tile_X6Y4_W6BEG;
+	wire [3:0] Tile_X7Y4_N1BEG;
+	wire [7:0] Tile_X7Y4_N2BEG;
+	wire [7:0] Tile_X7Y4_N2BEGb;
+	wire [15:0] Tile_X7Y4_N4BEG;
+	wire [15:0] Tile_X7Y4_NN4BEG;
+	wire [0:0] Tile_X7Y4_Co;
+	wire [3:0] Tile_X7Y4_E1BEG;
+	wire [7:0] Tile_X7Y4_E2BEG;
+	wire [7:0] Tile_X7Y4_E2BEGb;
+	wire [15:0] Tile_X7Y4_EE4BEG;
+	wire [11:0] Tile_X7Y4_E6BEG;
+	wire [3:0] Tile_X7Y4_S1BEG;
+	wire [7:0] Tile_X7Y4_S2BEG;
+	wire [7:0] Tile_X7Y4_S2BEGb;
+	wire [15:0] Tile_X7Y4_S4BEG;
+	wire [15:0] Tile_X7Y4_SS4BEG;
+	wire [3:0] Tile_X7Y4_W1BEG;
+	wire [7:0] Tile_X7Y4_W2BEG;
+	wire [7:0] Tile_X7Y4_W2BEGb;
+	wire [15:0] Tile_X7Y4_WW4BEG;
+	wire [11:0] Tile_X7Y4_W6BEG;
+	wire [3:0] Tile_X8Y4_N1BEG;
+	wire [7:0] Tile_X8Y4_N2BEG;
+	wire [7:0] Tile_X8Y4_N2BEGb;
+	wire [15:0] Tile_X8Y4_N4BEG;
+	wire [15:0] Tile_X8Y4_NN4BEG;
+	wire [9:0] Tile_X8Y4_bot2top;
+	wire [3:0] Tile_X8Y4_E1BEG;
+	wire [7:0] Tile_X8Y4_E2BEG;
+	wire [7:0] Tile_X8Y4_E2BEGb;
+	wire [15:0] Tile_X8Y4_EE4BEG;
+	wire [11:0] Tile_X8Y4_E6BEG;
+	wire [3:0] Tile_X8Y4_S1BEG;
+	wire [7:0] Tile_X8Y4_S2BEG;
+	wire [7:0] Tile_X8Y4_S2BEGb;
+	wire [15:0] Tile_X8Y4_S4BEG;
+	wire [15:0] Tile_X8Y4_SS4BEG;
+	wire [3:0] Tile_X8Y4_W1BEG;
+	wire [7:0] Tile_X8Y4_W2BEG;
+	wire [7:0] Tile_X8Y4_W2BEGb;
+	wire [15:0] Tile_X8Y4_WW4BEG;
+	wire [11:0] Tile_X8Y4_W6BEG;
+	wire [3:0] Tile_X9Y4_N1BEG;
+	wire [7:0] Tile_X9Y4_N2BEG;
+	wire [7:0] Tile_X9Y4_N2BEGb;
+	wire [15:0] Tile_X9Y4_N4BEG;
+	wire [15:0] Tile_X9Y4_NN4BEG;
+	wire [0:0] Tile_X9Y4_Co;
+	wire [3:0] Tile_X9Y4_E1BEG;
+	wire [7:0] Tile_X9Y4_E2BEG;
+	wire [7:0] Tile_X9Y4_E2BEGb;
+	wire [15:0] Tile_X9Y4_EE4BEG;
+	wire [11:0] Tile_X9Y4_E6BEG;
+	wire [3:0] Tile_X9Y4_S1BEG;
+	wire [7:0] Tile_X9Y4_S2BEG;
+	wire [7:0] Tile_X9Y4_S2BEGb;
+	wire [15:0] Tile_X9Y4_S4BEG;
+	wire [15:0] Tile_X9Y4_SS4BEG;
+	wire [3:0] Tile_X9Y4_W1BEG;
+	wire [7:0] Tile_X9Y4_W2BEG;
+	wire [7:0] Tile_X9Y4_W2BEGb;
+	wire [15:0] Tile_X9Y4_WW4BEG;
+	wire [11:0] Tile_X9Y4_W6BEG;
+	wire [3:0] Tile_X10Y4_N1BEG;
+	wire [7:0] Tile_X10Y4_N2BEG;
+	wire [7:0] Tile_X10Y4_N2BEGb;
+	wire [15:0] Tile_X10Y4_N4BEG;
+	wire [15:0] Tile_X10Y4_NN4BEG;
+	wire [0:0] Tile_X10Y4_Co;
+	wire [3:0] Tile_X10Y4_E1BEG;
+	wire [7:0] Tile_X10Y4_E2BEG;
+	wire [7:0] Tile_X10Y4_E2BEGb;
+	wire [15:0] Tile_X10Y4_EE4BEG;
+	wire [11:0] Tile_X10Y4_E6BEG;
+	wire [3:0] Tile_X10Y4_S1BEG;
+	wire [7:0] Tile_X10Y4_S2BEG;
+	wire [7:0] Tile_X10Y4_S2BEGb;
+	wire [15:0] Tile_X10Y4_S4BEG;
+	wire [15:0] Tile_X10Y4_SS4BEG;
+	wire [3:0] Tile_X10Y4_W1BEG;
+	wire [7:0] Tile_X10Y4_W2BEG;
+	wire [7:0] Tile_X10Y4_W2BEGb;
+	wire [15:0] Tile_X10Y4_WW4BEG;
+	wire [11:0] Tile_X10Y4_W6BEG;
+	wire [3:0] Tile_X11Y4_W1BEG;
+	wire [7:0] Tile_X11Y4_W2BEG;
+	wire [7:0] Tile_X11Y4_W2BEGb;
+	wire [15:0] Tile_X11Y4_WW4BEG;
+	wire [11:0] Tile_X11Y4_W6BEG;
+	wire [3:0] Tile_X3Y5_E1BEG;
+	wire [7:0] Tile_X3Y5_E2BEG;
+	wire [7:0] Tile_X3Y5_E2BEGb;
+	wire [15:0] Tile_X3Y5_EE4BEG;
+	wire [11:0] Tile_X3Y5_E6BEG;
+	wire [3:0] Tile_X4Y5_N1BEG;
+	wire [7:0] Tile_X4Y5_N2BEG;
+	wire [7:0] Tile_X4Y5_N2BEGb;
+	wire [15:0] Tile_X4Y5_N4BEG;
+	wire [15:0] Tile_X4Y5_NN4BEG;
+	wire [3:0] Tile_X4Y5_E1BEG;
+	wire [7:0] Tile_X4Y5_E2BEG;
+	wire [7:0] Tile_X4Y5_E2BEGb;
+	wire [15:0] Tile_X4Y5_EE4BEG;
+	wire [11:0] Tile_X4Y5_E6BEG;
+	wire [3:0] Tile_X4Y5_S1BEG;
+	wire [7:0] Tile_X4Y5_S2BEG;
+	wire [7:0] Tile_X4Y5_S2BEGb;
+	wire [15:0] Tile_X4Y5_S4BEG;
+	wire [15:0] Tile_X4Y5_SS4BEG;
+	wire [17:0] Tile_X4Y5_top2bot;
+	wire [3:0] Tile_X4Y5_W1BEG;
+	wire [7:0] Tile_X4Y5_W2BEG;
+	wire [7:0] Tile_X4Y5_W2BEGb;
+	wire [15:0] Tile_X4Y5_WW4BEG;
+	wire [11:0] Tile_X4Y5_W6BEG;
+	wire [3:0] Tile_X5Y5_N1BEG;
+	wire [7:0] Tile_X5Y5_N2BEG;
+	wire [7:0] Tile_X5Y5_N2BEGb;
+	wire [15:0] Tile_X5Y5_N4BEG;
+	wire [15:0] Tile_X5Y5_NN4BEG;
+	wire [0:0] Tile_X5Y5_Co;
+	wire [3:0] Tile_X5Y5_E1BEG;
+	wire [7:0] Tile_X5Y5_E2BEG;
+	wire [7:0] Tile_X5Y5_E2BEGb;
+	wire [15:0] Tile_X5Y5_EE4BEG;
+	wire [11:0] Tile_X5Y5_E6BEG;
+	wire [3:0] Tile_X5Y5_S1BEG;
+	wire [7:0] Tile_X5Y5_S2BEG;
+	wire [7:0] Tile_X5Y5_S2BEGb;
+	wire [15:0] Tile_X5Y5_S4BEG;
+	wire [15:0] Tile_X5Y5_SS4BEG;
+	wire [3:0] Tile_X5Y5_W1BEG;
+	wire [7:0] Tile_X5Y5_W2BEG;
+	wire [7:0] Tile_X5Y5_W2BEGb;
+	wire [15:0] Tile_X5Y5_WW4BEG;
+	wire [11:0] Tile_X5Y5_W6BEG;
+	wire [3:0] Tile_X6Y5_N1BEG;
+	wire [7:0] Tile_X6Y5_N2BEG;
+	wire [7:0] Tile_X6Y5_N2BEGb;
+	wire [15:0] Tile_X6Y5_N4BEG;
+	wire [15:0] Tile_X6Y5_NN4BEG;
+	wire [0:0] Tile_X6Y5_Co;
+	wire [3:0] Tile_X6Y5_E1BEG;
+	wire [7:0] Tile_X6Y5_E2BEG;
+	wire [7:0] Tile_X6Y5_E2BEGb;
+	wire [15:0] Tile_X6Y5_EE4BEG;
+	wire [11:0] Tile_X6Y5_E6BEG;
+	wire [3:0] Tile_X6Y5_S1BEG;
+	wire [7:0] Tile_X6Y5_S2BEG;
+	wire [7:0] Tile_X6Y5_S2BEGb;
+	wire [15:0] Tile_X6Y5_S4BEG;
+	wire [15:0] Tile_X6Y5_SS4BEG;
+	wire [3:0] Tile_X6Y5_W1BEG;
+	wire [7:0] Tile_X6Y5_W2BEG;
+	wire [7:0] Tile_X6Y5_W2BEGb;
+	wire [15:0] Tile_X6Y5_WW4BEG;
+	wire [11:0] Tile_X6Y5_W6BEG;
+	wire [3:0] Tile_X7Y5_N1BEG;
+	wire [7:0] Tile_X7Y5_N2BEG;
+	wire [7:0] Tile_X7Y5_N2BEGb;
+	wire [15:0] Tile_X7Y5_N4BEG;
+	wire [15:0] Tile_X7Y5_NN4BEG;
+	wire [0:0] Tile_X7Y5_Co;
+	wire [3:0] Tile_X7Y5_E1BEG;
+	wire [7:0] Tile_X7Y5_E2BEG;
+	wire [7:0] Tile_X7Y5_E2BEGb;
+	wire [15:0] Tile_X7Y5_EE4BEG;
+	wire [11:0] Tile_X7Y5_E6BEG;
+	wire [3:0] Tile_X7Y5_S1BEG;
+	wire [7:0] Tile_X7Y5_S2BEG;
+	wire [7:0] Tile_X7Y5_S2BEGb;
+	wire [15:0] Tile_X7Y5_S4BEG;
+	wire [15:0] Tile_X7Y5_SS4BEG;
+	wire [3:0] Tile_X7Y5_W1BEG;
+	wire [7:0] Tile_X7Y5_W2BEG;
+	wire [7:0] Tile_X7Y5_W2BEGb;
+	wire [15:0] Tile_X7Y5_WW4BEG;
+	wire [11:0] Tile_X7Y5_W6BEG;
+	wire [3:0] Tile_X8Y5_N1BEG;
+	wire [7:0] Tile_X8Y5_N2BEG;
+	wire [7:0] Tile_X8Y5_N2BEGb;
+	wire [15:0] Tile_X8Y5_N4BEG;
+	wire [15:0] Tile_X8Y5_NN4BEG;
+	wire [3:0] Tile_X8Y5_E1BEG;
+	wire [7:0] Tile_X8Y5_E2BEG;
+	wire [7:0] Tile_X8Y5_E2BEGb;
+	wire [15:0] Tile_X8Y5_EE4BEG;
+	wire [11:0] Tile_X8Y5_E6BEG;
+	wire [3:0] Tile_X8Y5_S1BEG;
+	wire [7:0] Tile_X8Y5_S2BEG;
+	wire [7:0] Tile_X8Y5_S2BEGb;
+	wire [15:0] Tile_X8Y5_S4BEG;
+	wire [15:0] Tile_X8Y5_SS4BEG;
+	wire [17:0] Tile_X8Y5_top2bot;
+	wire [3:0] Tile_X8Y5_W1BEG;
+	wire [7:0] Tile_X8Y5_W2BEG;
+	wire [7:0] Tile_X8Y5_W2BEGb;
+	wire [15:0] Tile_X8Y5_WW4BEG;
+	wire [11:0] Tile_X8Y5_W6BEG;
+	wire [3:0] Tile_X9Y5_N1BEG;
+	wire [7:0] Tile_X9Y5_N2BEG;
+	wire [7:0] Tile_X9Y5_N2BEGb;
+	wire [15:0] Tile_X9Y5_N4BEG;
+	wire [15:0] Tile_X9Y5_NN4BEG;
+	wire [0:0] Tile_X9Y5_Co;
+	wire [3:0] Tile_X9Y5_E1BEG;
+	wire [7:0] Tile_X9Y5_E2BEG;
+	wire [7:0] Tile_X9Y5_E2BEGb;
+	wire [15:0] Tile_X9Y5_EE4BEG;
+	wire [11:0] Tile_X9Y5_E6BEG;
+	wire [3:0] Tile_X9Y5_S1BEG;
+	wire [7:0] Tile_X9Y5_S2BEG;
+	wire [7:0] Tile_X9Y5_S2BEGb;
+	wire [15:0] Tile_X9Y5_S4BEG;
+	wire [15:0] Tile_X9Y5_SS4BEG;
+	wire [3:0] Tile_X9Y5_W1BEG;
+	wire [7:0] Tile_X9Y5_W2BEG;
+	wire [7:0] Tile_X9Y5_W2BEGb;
+	wire [15:0] Tile_X9Y5_WW4BEG;
+	wire [11:0] Tile_X9Y5_W6BEG;
+	wire [3:0] Tile_X10Y5_N1BEG;
+	wire [7:0] Tile_X10Y5_N2BEG;
+	wire [7:0] Tile_X10Y5_N2BEGb;
+	wire [15:0] Tile_X10Y5_N4BEG;
+	wire [15:0] Tile_X10Y5_NN4BEG;
+	wire [0:0] Tile_X10Y5_Co;
+	wire [3:0] Tile_X10Y5_E1BEG;
+	wire [7:0] Tile_X10Y5_E2BEG;
+	wire [7:0] Tile_X10Y5_E2BEGb;
+	wire [15:0] Tile_X10Y5_EE4BEG;
+	wire [11:0] Tile_X10Y5_E6BEG;
+	wire [3:0] Tile_X10Y5_S1BEG;
+	wire [7:0] Tile_X10Y5_S2BEG;
+	wire [7:0] Tile_X10Y5_S2BEGb;
+	wire [15:0] Tile_X10Y5_S4BEG;
+	wire [15:0] Tile_X10Y5_SS4BEG;
+	wire [3:0] Tile_X10Y5_W1BEG;
+	wire [7:0] Tile_X10Y5_W2BEG;
+	wire [7:0] Tile_X10Y5_W2BEGb;
+	wire [15:0] Tile_X10Y5_WW4BEG;
+	wire [11:0] Tile_X10Y5_W6BEG;
+	wire [3:0] Tile_X11Y5_W1BEG;
+	wire [7:0] Tile_X11Y5_W2BEG;
+	wire [7:0] Tile_X11Y5_W2BEGb;
+	wire [15:0] Tile_X11Y5_WW4BEG;
+	wire [11:0] Tile_X11Y5_W6BEG;
+	wire [3:0] Tile_X3Y6_E1BEG;
+	wire [7:0] Tile_X3Y6_E2BEG;
+	wire [7:0] Tile_X3Y6_E2BEGb;
+	wire [15:0] Tile_X3Y6_EE4BEG;
+	wire [11:0] Tile_X3Y6_E6BEG;
+	wire [3:0] Tile_X4Y6_N1BEG;
+	wire [7:0] Tile_X4Y6_N2BEG;
+	wire [7:0] Tile_X4Y6_N2BEGb;
+	wire [15:0] Tile_X4Y6_N4BEG;
+	wire [15:0] Tile_X4Y6_NN4BEG;
+	wire [9:0] Tile_X4Y6_bot2top;
+	wire [3:0] Tile_X4Y6_E1BEG;
+	wire [7:0] Tile_X4Y6_E2BEG;
+	wire [7:0] Tile_X4Y6_E2BEGb;
+	wire [15:0] Tile_X4Y6_EE4BEG;
+	wire [11:0] Tile_X4Y6_E6BEG;
+	wire [3:0] Tile_X4Y6_S1BEG;
+	wire [7:0] Tile_X4Y6_S2BEG;
+	wire [7:0] Tile_X4Y6_S2BEGb;
+	wire [15:0] Tile_X4Y6_S4BEG;
+	wire [15:0] Tile_X4Y6_SS4BEG;
+	wire [3:0] Tile_X4Y6_W1BEG;
+	wire [7:0] Tile_X4Y6_W2BEG;
+	wire [7:0] Tile_X4Y6_W2BEGb;
+	wire [15:0] Tile_X4Y6_WW4BEG;
+	wire [11:0] Tile_X4Y6_W6BEG;
+	wire [3:0] Tile_X5Y6_N1BEG;
+	wire [7:0] Tile_X5Y6_N2BEG;
+	wire [7:0] Tile_X5Y6_N2BEGb;
+	wire [15:0] Tile_X5Y6_N4BEG;
+	wire [15:0] Tile_X5Y6_NN4BEG;
+	wire [0:0] Tile_X5Y6_Co;
+	wire [3:0] Tile_X5Y6_E1BEG;
+	wire [7:0] Tile_X5Y6_E2BEG;
+	wire [7:0] Tile_X5Y6_E2BEGb;
+	wire [15:0] Tile_X5Y6_EE4BEG;
+	wire [11:0] Tile_X5Y6_E6BEG;
+	wire [3:0] Tile_X5Y6_S1BEG;
+	wire [7:0] Tile_X5Y6_S2BEG;
+	wire [7:0] Tile_X5Y6_S2BEGb;
+	wire [15:0] Tile_X5Y6_S4BEG;
+	wire [15:0] Tile_X5Y6_SS4BEG;
+	wire [3:0] Tile_X5Y6_W1BEG;
+	wire [7:0] Tile_X5Y6_W2BEG;
+	wire [7:0] Tile_X5Y6_W2BEGb;
+	wire [15:0] Tile_X5Y6_WW4BEG;
+	wire [11:0] Tile_X5Y6_W6BEG;
+	wire [3:0] Tile_X6Y6_N1BEG;
+	wire [7:0] Tile_X6Y6_N2BEG;
+	wire [7:0] Tile_X6Y6_N2BEGb;
+	wire [15:0] Tile_X6Y6_N4BEG;
+	wire [15:0] Tile_X6Y6_NN4BEG;
+	wire [0:0] Tile_X6Y6_Co;
+	wire [3:0] Tile_X6Y6_E1BEG;
+	wire [7:0] Tile_X6Y6_E2BEG;
+	wire [7:0] Tile_X6Y6_E2BEGb;
+	wire [15:0] Tile_X6Y6_EE4BEG;
+	wire [11:0] Tile_X6Y6_E6BEG;
+	wire [3:0] Tile_X6Y6_S1BEG;
+	wire [7:0] Tile_X6Y6_S2BEG;
+	wire [7:0] Tile_X6Y6_S2BEGb;
+	wire [15:0] Tile_X6Y6_S4BEG;
+	wire [15:0] Tile_X6Y6_SS4BEG;
+	wire [3:0] Tile_X6Y6_W1BEG;
+	wire [7:0] Tile_X6Y6_W2BEG;
+	wire [7:0] Tile_X6Y6_W2BEGb;
+	wire [15:0] Tile_X6Y6_WW4BEG;
+	wire [11:0] Tile_X6Y6_W6BEG;
+	wire [3:0] Tile_X7Y6_N1BEG;
+	wire [7:0] Tile_X7Y6_N2BEG;
+	wire [7:0] Tile_X7Y6_N2BEGb;
+	wire [15:0] Tile_X7Y6_N4BEG;
+	wire [15:0] Tile_X7Y6_NN4BEG;
+	wire [0:0] Tile_X7Y6_Co;
+	wire [3:0] Tile_X7Y6_E1BEG;
+	wire [7:0] Tile_X7Y6_E2BEG;
+	wire [7:0] Tile_X7Y6_E2BEGb;
+	wire [15:0] Tile_X7Y6_EE4BEG;
+	wire [11:0] Tile_X7Y6_E6BEG;
+	wire [3:0] Tile_X7Y6_S1BEG;
+	wire [7:0] Tile_X7Y6_S2BEG;
+	wire [7:0] Tile_X7Y6_S2BEGb;
+	wire [15:0] Tile_X7Y6_S4BEG;
+	wire [15:0] Tile_X7Y6_SS4BEG;
+	wire [3:0] Tile_X7Y6_W1BEG;
+	wire [7:0] Tile_X7Y6_W2BEG;
+	wire [7:0] Tile_X7Y6_W2BEGb;
+	wire [15:0] Tile_X7Y6_WW4BEG;
+	wire [11:0] Tile_X7Y6_W6BEG;
+	wire [3:0] Tile_X8Y6_N1BEG;
+	wire [7:0] Tile_X8Y6_N2BEG;
+	wire [7:0] Tile_X8Y6_N2BEGb;
+	wire [15:0] Tile_X8Y6_N4BEG;
+	wire [15:0] Tile_X8Y6_NN4BEG;
+	wire [9:0] Tile_X8Y6_bot2top;
+	wire [3:0] Tile_X8Y6_E1BEG;
+	wire [7:0] Tile_X8Y6_E2BEG;
+	wire [7:0] Tile_X8Y6_E2BEGb;
+	wire [15:0] Tile_X8Y6_EE4BEG;
+	wire [11:0] Tile_X8Y6_E6BEG;
+	wire [3:0] Tile_X8Y6_S1BEG;
+	wire [7:0] Tile_X8Y6_S2BEG;
+	wire [7:0] Tile_X8Y6_S2BEGb;
+	wire [15:0] Tile_X8Y6_S4BEG;
+	wire [15:0] Tile_X8Y6_SS4BEG;
+	wire [3:0] Tile_X8Y6_W1BEG;
+	wire [7:0] Tile_X8Y6_W2BEG;
+	wire [7:0] Tile_X8Y6_W2BEGb;
+	wire [15:0] Tile_X8Y6_WW4BEG;
+	wire [11:0] Tile_X8Y6_W6BEG;
+	wire [3:0] Tile_X9Y6_N1BEG;
+	wire [7:0] Tile_X9Y6_N2BEG;
+	wire [7:0] Tile_X9Y6_N2BEGb;
+	wire [15:0] Tile_X9Y6_N4BEG;
+	wire [15:0] Tile_X9Y6_NN4BEG;
+	wire [0:0] Tile_X9Y6_Co;
+	wire [3:0] Tile_X9Y6_E1BEG;
+	wire [7:0] Tile_X9Y6_E2BEG;
+	wire [7:0] Tile_X9Y6_E2BEGb;
+	wire [15:0] Tile_X9Y6_EE4BEG;
+	wire [11:0] Tile_X9Y6_E6BEG;
+	wire [3:0] Tile_X9Y6_S1BEG;
+	wire [7:0] Tile_X9Y6_S2BEG;
+	wire [7:0] Tile_X9Y6_S2BEGb;
+	wire [15:0] Tile_X9Y6_S4BEG;
+	wire [15:0] Tile_X9Y6_SS4BEG;
+	wire [3:0] Tile_X9Y6_W1BEG;
+	wire [7:0] Tile_X9Y6_W2BEG;
+	wire [7:0] Tile_X9Y6_W2BEGb;
+	wire [15:0] Tile_X9Y6_WW4BEG;
+	wire [11:0] Tile_X9Y6_W6BEG;
+	wire [3:0] Tile_X10Y6_N1BEG;
+	wire [7:0] Tile_X10Y6_N2BEG;
+	wire [7:0] Tile_X10Y6_N2BEGb;
+	wire [15:0] Tile_X10Y6_N4BEG;
+	wire [15:0] Tile_X10Y6_NN4BEG;
+	wire [0:0] Tile_X10Y6_Co;
+	wire [3:0] Tile_X10Y6_E1BEG;
+	wire [7:0] Tile_X10Y6_E2BEG;
+	wire [7:0] Tile_X10Y6_E2BEGb;
+	wire [15:0] Tile_X10Y6_EE4BEG;
+	wire [11:0] Tile_X10Y6_E6BEG;
+	wire [3:0] Tile_X10Y6_S1BEG;
+	wire [7:0] Tile_X10Y6_S2BEG;
+	wire [7:0] Tile_X10Y6_S2BEGb;
+	wire [15:0] Tile_X10Y6_S4BEG;
+	wire [15:0] Tile_X10Y6_SS4BEG;
+	wire [3:0] Tile_X10Y6_W1BEG;
+	wire [7:0] Tile_X10Y6_W2BEG;
+	wire [7:0] Tile_X10Y6_W2BEGb;
+	wire [15:0] Tile_X10Y6_WW4BEG;
+	wire [11:0] Tile_X10Y6_W6BEG;
+	wire [3:0] Tile_X11Y6_W1BEG;
+	wire [7:0] Tile_X11Y6_W2BEG;
+	wire [7:0] Tile_X11Y6_W2BEGb;
+	wire [15:0] Tile_X11Y6_WW4BEG;
+	wire [11:0] Tile_X11Y6_W6BEG;
+	wire [3:0] Tile_X3Y7_E1BEG;
+	wire [7:0] Tile_X3Y7_E2BEG;
+	wire [7:0] Tile_X3Y7_E2BEGb;
+	wire [15:0] Tile_X3Y7_EE4BEG;
+	wire [11:0] Tile_X3Y7_E6BEG;
+	wire [3:0] Tile_X4Y7_N1BEG;
+	wire [7:0] Tile_X4Y7_N2BEG;
+	wire [7:0] Tile_X4Y7_N2BEGb;
+	wire [15:0] Tile_X4Y7_N4BEG;
+	wire [15:0] Tile_X4Y7_NN4BEG;
+	wire [3:0] Tile_X4Y7_E1BEG;
+	wire [7:0] Tile_X4Y7_E2BEG;
+	wire [7:0] Tile_X4Y7_E2BEGb;
+	wire [15:0] Tile_X4Y7_EE4BEG;
+	wire [11:0] Tile_X4Y7_E6BEG;
+	wire [3:0] Tile_X4Y7_S1BEG;
+	wire [7:0] Tile_X4Y7_S2BEG;
+	wire [7:0] Tile_X4Y7_S2BEGb;
+	wire [15:0] Tile_X4Y7_S4BEG;
+	wire [15:0] Tile_X4Y7_SS4BEG;
+	wire [17:0] Tile_X4Y7_top2bot;
+	wire [3:0] Tile_X4Y7_W1BEG;
+	wire [7:0] Tile_X4Y7_W2BEG;
+	wire [7:0] Tile_X4Y7_W2BEGb;
+	wire [15:0] Tile_X4Y7_WW4BEG;
+	wire [11:0] Tile_X4Y7_W6BEG;
+	wire [3:0] Tile_X5Y7_N1BEG;
+	wire [7:0] Tile_X5Y7_N2BEG;
+	wire [7:0] Tile_X5Y7_N2BEGb;
+	wire [15:0] Tile_X5Y7_N4BEG;
+	wire [15:0] Tile_X5Y7_NN4BEG;
+	wire [0:0] Tile_X5Y7_Co;
+	wire [3:0] Tile_X5Y7_E1BEG;
+	wire [7:0] Tile_X5Y7_E2BEG;
+	wire [7:0] Tile_X5Y7_E2BEGb;
+	wire [15:0] Tile_X5Y7_EE4BEG;
+	wire [11:0] Tile_X5Y7_E6BEG;
+	wire [3:0] Tile_X5Y7_S1BEG;
+	wire [7:0] Tile_X5Y7_S2BEG;
+	wire [7:0] Tile_X5Y7_S2BEGb;
+	wire [15:0] Tile_X5Y7_S4BEG;
+	wire [15:0] Tile_X5Y7_SS4BEG;
+	wire [3:0] Tile_X5Y7_W1BEG;
+	wire [7:0] Tile_X5Y7_W2BEG;
+	wire [7:0] Tile_X5Y7_W2BEGb;
+	wire [15:0] Tile_X5Y7_WW4BEG;
+	wire [11:0] Tile_X5Y7_W6BEG;
+	wire [3:0] Tile_X6Y7_N1BEG;
+	wire [7:0] Tile_X6Y7_N2BEG;
+	wire [7:0] Tile_X6Y7_N2BEGb;
+	wire [15:0] Tile_X6Y7_N4BEG;
+	wire [15:0] Tile_X6Y7_NN4BEG;
+	wire [0:0] Tile_X6Y7_Co;
+	wire [3:0] Tile_X6Y7_E1BEG;
+	wire [7:0] Tile_X6Y7_E2BEG;
+	wire [7:0] Tile_X6Y7_E2BEGb;
+	wire [15:0] Tile_X6Y7_EE4BEG;
+	wire [11:0] Tile_X6Y7_E6BEG;
+	wire [3:0] Tile_X6Y7_S1BEG;
+	wire [7:0] Tile_X6Y7_S2BEG;
+	wire [7:0] Tile_X6Y7_S2BEGb;
+	wire [15:0] Tile_X6Y7_S4BEG;
+	wire [15:0] Tile_X6Y7_SS4BEG;
+	wire [3:0] Tile_X6Y7_W1BEG;
+	wire [7:0] Tile_X6Y7_W2BEG;
+	wire [7:0] Tile_X6Y7_W2BEGb;
+	wire [15:0] Tile_X6Y7_WW4BEG;
+	wire [11:0] Tile_X6Y7_W6BEG;
+	wire [3:0] Tile_X7Y7_N1BEG;
+	wire [7:0] Tile_X7Y7_N2BEG;
+	wire [7:0] Tile_X7Y7_N2BEGb;
+	wire [15:0] Tile_X7Y7_N4BEG;
+	wire [15:0] Tile_X7Y7_NN4BEG;
+	wire [0:0] Tile_X7Y7_Co;
+	wire [3:0] Tile_X7Y7_E1BEG;
+	wire [7:0] Tile_X7Y7_E2BEG;
+	wire [7:0] Tile_X7Y7_E2BEGb;
+	wire [15:0] Tile_X7Y7_EE4BEG;
+	wire [11:0] Tile_X7Y7_E6BEG;
+	wire [3:0] Tile_X7Y7_S1BEG;
+	wire [7:0] Tile_X7Y7_S2BEG;
+	wire [7:0] Tile_X7Y7_S2BEGb;
+	wire [15:0] Tile_X7Y7_S4BEG;
+	wire [15:0] Tile_X7Y7_SS4BEG;
+	wire [3:0] Tile_X7Y7_W1BEG;
+	wire [7:0] Tile_X7Y7_W2BEG;
+	wire [7:0] Tile_X7Y7_W2BEGb;
+	wire [15:0] Tile_X7Y7_WW4BEG;
+	wire [11:0] Tile_X7Y7_W6BEG;
+	wire [3:0] Tile_X8Y7_N1BEG;
+	wire [7:0] Tile_X8Y7_N2BEG;
+	wire [7:0] Tile_X8Y7_N2BEGb;
+	wire [15:0] Tile_X8Y7_N4BEG;
+	wire [15:0] Tile_X8Y7_NN4BEG;
+	wire [3:0] Tile_X8Y7_E1BEG;
+	wire [7:0] Tile_X8Y7_E2BEG;
+	wire [7:0] Tile_X8Y7_E2BEGb;
+	wire [15:0] Tile_X8Y7_EE4BEG;
+	wire [11:0] Tile_X8Y7_E6BEG;
+	wire [3:0] Tile_X8Y7_S1BEG;
+	wire [7:0] Tile_X8Y7_S2BEG;
+	wire [7:0] Tile_X8Y7_S2BEGb;
+	wire [15:0] Tile_X8Y7_S4BEG;
+	wire [15:0] Tile_X8Y7_SS4BEG;
+	wire [17:0] Tile_X8Y7_top2bot;
+	wire [3:0] Tile_X8Y7_W1BEG;
+	wire [7:0] Tile_X8Y7_W2BEG;
+	wire [7:0] Tile_X8Y7_W2BEGb;
+	wire [15:0] Tile_X8Y7_WW4BEG;
+	wire [11:0] Tile_X8Y7_W6BEG;
+	wire [3:0] Tile_X9Y7_N1BEG;
+	wire [7:0] Tile_X9Y7_N2BEG;
+	wire [7:0] Tile_X9Y7_N2BEGb;
+	wire [15:0] Tile_X9Y7_N4BEG;
+	wire [15:0] Tile_X9Y7_NN4BEG;
+	wire [0:0] Tile_X9Y7_Co;
+	wire [3:0] Tile_X9Y7_E1BEG;
+	wire [7:0] Tile_X9Y7_E2BEG;
+	wire [7:0] Tile_X9Y7_E2BEGb;
+	wire [15:0] Tile_X9Y7_EE4BEG;
+	wire [11:0] Tile_X9Y7_E6BEG;
+	wire [3:0] Tile_X9Y7_S1BEG;
+	wire [7:0] Tile_X9Y7_S2BEG;
+	wire [7:0] Tile_X9Y7_S2BEGb;
+	wire [15:0] Tile_X9Y7_S4BEG;
+	wire [15:0] Tile_X9Y7_SS4BEG;
+	wire [3:0] Tile_X9Y7_W1BEG;
+	wire [7:0] Tile_X9Y7_W2BEG;
+	wire [7:0] Tile_X9Y7_W2BEGb;
+	wire [15:0] Tile_X9Y7_WW4BEG;
+	wire [11:0] Tile_X9Y7_W6BEG;
+	wire [3:0] Tile_X10Y7_N1BEG;
+	wire [7:0] Tile_X10Y7_N2BEG;
+	wire [7:0] Tile_X10Y7_N2BEGb;
+	wire [15:0] Tile_X10Y7_N4BEG;
+	wire [15:0] Tile_X10Y7_NN4BEG;
+	wire [0:0] Tile_X10Y7_Co;
+	wire [3:0] Tile_X10Y7_E1BEG;
+	wire [7:0] Tile_X10Y7_E2BEG;
+	wire [7:0] Tile_X10Y7_E2BEGb;
+	wire [15:0] Tile_X10Y7_EE4BEG;
+	wire [11:0] Tile_X10Y7_E6BEG;
+	wire [3:0] Tile_X10Y7_S1BEG;
+	wire [7:0] Tile_X10Y7_S2BEG;
+	wire [7:0] Tile_X10Y7_S2BEGb;
+	wire [15:0] Tile_X10Y7_S4BEG;
+	wire [15:0] Tile_X10Y7_SS4BEG;
+	wire [3:0] Tile_X10Y7_W1BEG;
+	wire [7:0] Tile_X10Y7_W2BEG;
+	wire [7:0] Tile_X10Y7_W2BEGb;
+	wire [15:0] Tile_X10Y7_WW4BEG;
+	wire [11:0] Tile_X10Y7_W6BEG;
+	wire [3:0] Tile_X11Y7_W1BEG;
+	wire [7:0] Tile_X11Y7_W2BEG;
+	wire [7:0] Tile_X11Y7_W2BEGb;
+	wire [15:0] Tile_X11Y7_WW4BEG;
+	wire [11:0] Tile_X11Y7_W6BEG;
+	wire [3:0] Tile_X3Y8_E1BEG;
+	wire [7:0] Tile_X3Y8_E2BEG;
+	wire [7:0] Tile_X3Y8_E2BEGb;
+	wire [15:0] Tile_X3Y8_EE4BEG;
+	wire [11:0] Tile_X3Y8_E6BEG;
+	wire [3:0] Tile_X4Y8_N1BEG;
+	wire [7:0] Tile_X4Y8_N2BEG;
+	wire [7:0] Tile_X4Y8_N2BEGb;
+	wire [15:0] Tile_X4Y8_N4BEG;
+	wire [15:0] Tile_X4Y8_NN4BEG;
+	wire [9:0] Tile_X4Y8_bot2top;
+	wire [3:0] Tile_X4Y8_E1BEG;
+	wire [7:0] Tile_X4Y8_E2BEG;
+	wire [7:0] Tile_X4Y8_E2BEGb;
+	wire [15:0] Tile_X4Y8_EE4BEG;
+	wire [11:0] Tile_X4Y8_E6BEG;
+	wire [3:0] Tile_X4Y8_S1BEG;
+	wire [7:0] Tile_X4Y8_S2BEG;
+	wire [7:0] Tile_X4Y8_S2BEGb;
+	wire [15:0] Tile_X4Y8_S4BEG;
+	wire [15:0] Tile_X4Y8_SS4BEG;
+	wire [3:0] Tile_X4Y8_W1BEG;
+	wire [7:0] Tile_X4Y8_W2BEG;
+	wire [7:0] Tile_X4Y8_W2BEGb;
+	wire [15:0] Tile_X4Y8_WW4BEG;
+	wire [11:0] Tile_X4Y8_W6BEG;
+	wire [3:0] Tile_X5Y8_N1BEG;
+	wire [7:0] Tile_X5Y8_N2BEG;
+	wire [7:0] Tile_X5Y8_N2BEGb;
+	wire [15:0] Tile_X5Y8_N4BEG;
+	wire [15:0] Tile_X5Y8_NN4BEG;
+	wire [0:0] Tile_X5Y8_Co;
+	wire [3:0] Tile_X5Y8_E1BEG;
+	wire [7:0] Tile_X5Y8_E2BEG;
+	wire [7:0] Tile_X5Y8_E2BEGb;
+	wire [15:0] Tile_X5Y8_EE4BEG;
+	wire [11:0] Tile_X5Y8_E6BEG;
+	wire [3:0] Tile_X5Y8_S1BEG;
+	wire [7:0] Tile_X5Y8_S2BEG;
+	wire [7:0] Tile_X5Y8_S2BEGb;
+	wire [15:0] Tile_X5Y8_S4BEG;
+	wire [15:0] Tile_X5Y8_SS4BEG;
+	wire [3:0] Tile_X5Y8_W1BEG;
+	wire [7:0] Tile_X5Y8_W2BEG;
+	wire [7:0] Tile_X5Y8_W2BEGb;
+	wire [15:0] Tile_X5Y8_WW4BEG;
+	wire [11:0] Tile_X5Y8_W6BEG;
+	wire [3:0] Tile_X6Y8_N1BEG;
+	wire [7:0] Tile_X6Y8_N2BEG;
+	wire [7:0] Tile_X6Y8_N2BEGb;
+	wire [15:0] Tile_X6Y8_N4BEG;
+	wire [15:0] Tile_X6Y8_NN4BEG;
+	wire [0:0] Tile_X6Y8_Co;
+	wire [3:0] Tile_X6Y8_E1BEG;
+	wire [7:0] Tile_X6Y8_E2BEG;
+	wire [7:0] Tile_X6Y8_E2BEGb;
+	wire [15:0] Tile_X6Y8_EE4BEG;
+	wire [11:0] Tile_X6Y8_E6BEG;
+	wire [3:0] Tile_X6Y8_S1BEG;
+	wire [7:0] Tile_X6Y8_S2BEG;
+	wire [7:0] Tile_X6Y8_S2BEGb;
+	wire [15:0] Tile_X6Y8_S4BEG;
+	wire [15:0] Tile_X6Y8_SS4BEG;
+	wire [3:0] Tile_X6Y8_W1BEG;
+	wire [7:0] Tile_X6Y8_W2BEG;
+	wire [7:0] Tile_X6Y8_W2BEGb;
+	wire [15:0] Tile_X6Y8_WW4BEG;
+	wire [11:0] Tile_X6Y8_W6BEG;
+	wire [3:0] Tile_X7Y8_N1BEG;
+	wire [7:0] Tile_X7Y8_N2BEG;
+	wire [7:0] Tile_X7Y8_N2BEGb;
+	wire [15:0] Tile_X7Y8_N4BEG;
+	wire [15:0] Tile_X7Y8_NN4BEG;
+	wire [0:0] Tile_X7Y8_Co;
+	wire [3:0] Tile_X7Y8_E1BEG;
+	wire [7:0] Tile_X7Y8_E2BEG;
+	wire [7:0] Tile_X7Y8_E2BEGb;
+	wire [15:0] Tile_X7Y8_EE4BEG;
+	wire [11:0] Tile_X7Y8_E6BEG;
+	wire [3:0] Tile_X7Y8_S1BEG;
+	wire [7:0] Tile_X7Y8_S2BEG;
+	wire [7:0] Tile_X7Y8_S2BEGb;
+	wire [15:0] Tile_X7Y8_S4BEG;
+	wire [15:0] Tile_X7Y8_SS4BEG;
+	wire [3:0] Tile_X7Y8_W1BEG;
+	wire [7:0] Tile_X7Y8_W2BEG;
+	wire [7:0] Tile_X7Y8_W2BEGb;
+	wire [15:0] Tile_X7Y8_WW4BEG;
+	wire [11:0] Tile_X7Y8_W6BEG;
+	wire [3:0] Tile_X8Y8_N1BEG;
+	wire [7:0] Tile_X8Y8_N2BEG;
+	wire [7:0] Tile_X8Y8_N2BEGb;
+	wire [15:0] Tile_X8Y8_N4BEG;
+	wire [15:0] Tile_X8Y8_NN4BEG;
+	wire [9:0] Tile_X8Y8_bot2top;
+	wire [3:0] Tile_X8Y8_E1BEG;
+	wire [7:0] Tile_X8Y8_E2BEG;
+	wire [7:0] Tile_X8Y8_E2BEGb;
+	wire [15:0] Tile_X8Y8_EE4BEG;
+	wire [11:0] Tile_X8Y8_E6BEG;
+	wire [3:0] Tile_X8Y8_S1BEG;
+	wire [7:0] Tile_X8Y8_S2BEG;
+	wire [7:0] Tile_X8Y8_S2BEGb;
+	wire [15:0] Tile_X8Y8_S4BEG;
+	wire [15:0] Tile_X8Y8_SS4BEG;
+	wire [3:0] Tile_X8Y8_W1BEG;
+	wire [7:0] Tile_X8Y8_W2BEG;
+	wire [7:0] Tile_X8Y8_W2BEGb;
+	wire [15:0] Tile_X8Y8_WW4BEG;
+	wire [11:0] Tile_X8Y8_W6BEG;
+	wire [3:0] Tile_X9Y8_N1BEG;
+	wire [7:0] Tile_X9Y8_N2BEG;
+	wire [7:0] Tile_X9Y8_N2BEGb;
+	wire [15:0] Tile_X9Y8_N4BEG;
+	wire [15:0] Tile_X9Y8_NN4BEG;
+	wire [0:0] Tile_X9Y8_Co;
+	wire [3:0] Tile_X9Y8_E1BEG;
+	wire [7:0] Tile_X9Y8_E2BEG;
+	wire [7:0] Tile_X9Y8_E2BEGb;
+	wire [15:0] Tile_X9Y8_EE4BEG;
+	wire [11:0] Tile_X9Y8_E6BEG;
+	wire [3:0] Tile_X9Y8_S1BEG;
+	wire [7:0] Tile_X9Y8_S2BEG;
+	wire [7:0] Tile_X9Y8_S2BEGb;
+	wire [15:0] Tile_X9Y8_S4BEG;
+	wire [15:0] Tile_X9Y8_SS4BEG;
+	wire [3:0] Tile_X9Y8_W1BEG;
+	wire [7:0] Tile_X9Y8_W2BEG;
+	wire [7:0] Tile_X9Y8_W2BEGb;
+	wire [15:0] Tile_X9Y8_WW4BEG;
+	wire [11:0] Tile_X9Y8_W6BEG;
+	wire [3:0] Tile_X10Y8_N1BEG;
+	wire [7:0] Tile_X10Y8_N2BEG;
+	wire [7:0] Tile_X10Y8_N2BEGb;
+	wire [15:0] Tile_X10Y8_N4BEG;
+	wire [15:0] Tile_X10Y8_NN4BEG;
+	wire [0:0] Tile_X10Y8_Co;
+	wire [3:0] Tile_X10Y8_E1BEG;
+	wire [7:0] Tile_X10Y8_E2BEG;
+	wire [7:0] Tile_X10Y8_E2BEGb;
+	wire [15:0] Tile_X10Y8_EE4BEG;
+	wire [11:0] Tile_X10Y8_E6BEG;
+	wire [3:0] Tile_X10Y8_S1BEG;
+	wire [7:0] Tile_X10Y8_S2BEG;
+	wire [7:0] Tile_X10Y8_S2BEGb;
+	wire [15:0] Tile_X10Y8_S4BEG;
+	wire [15:0] Tile_X10Y8_SS4BEG;
+	wire [3:0] Tile_X10Y8_W1BEG;
+	wire [7:0] Tile_X10Y8_W2BEG;
+	wire [7:0] Tile_X10Y8_W2BEGb;
+	wire [15:0] Tile_X10Y8_WW4BEG;
+	wire [11:0] Tile_X10Y8_W6BEG;
+	wire [3:0] Tile_X11Y8_W1BEG;
+	wire [7:0] Tile_X11Y8_W2BEG;
+	wire [7:0] Tile_X11Y8_W2BEGb;
+	wire [15:0] Tile_X11Y8_WW4BEG;
+	wire [11:0] Tile_X11Y8_W6BEG;
+	wire [3:0] Tile_X1Y9_S1BEG;
+	wire [7:0] Tile_X1Y9_S2BEG;
+	wire [7:0] Tile_X1Y9_S2BEGb;
+	wire [15:0] Tile_X1Y9_S4BEG;
+	wire [15:0] Tile_X1Y9_SS4BEG;
+	wire [3:0] Tile_X2Y9_S1BEG;
+	wire [7:0] Tile_X2Y9_S2BEG;
+	wire [7:0] Tile_X2Y9_S2BEGb;
+	wire [15:0] Tile_X2Y9_S4BEG;
+	wire [15:0] Tile_X2Y9_SS4BEG;
+	wire [3:0] Tile_X3Y9_E1BEG;
+	wire [7:0] Tile_X3Y9_E2BEG;
+	wire [7:0] Tile_X3Y9_E2BEGb;
+	wire [15:0] Tile_X3Y9_EE4BEG;
+	wire [11:0] Tile_X3Y9_E6BEG;
+	wire [3:0] Tile_X3Y9_S1BEG;
+	wire [7:0] Tile_X3Y9_S2BEG;
+	wire [7:0] Tile_X3Y9_S2BEGb;
+	wire [15:0] Tile_X3Y9_S4BEG;
+	wire [15:0] Tile_X3Y9_SS4BEG;
+	wire [3:0] Tile_X4Y9_N1BEG;
+	wire [7:0] Tile_X4Y9_N2BEG;
+	wire [7:0] Tile_X4Y9_N2BEGb;
+	wire [15:0] Tile_X4Y9_N4BEG;
+	wire [15:0] Tile_X4Y9_NN4BEG;
+	wire [3:0] Tile_X4Y9_E1BEG;
+	wire [7:0] Tile_X4Y9_E2BEG;
+	wire [7:0] Tile_X4Y9_E2BEGb;
+	wire [15:0] Tile_X4Y9_EE4BEG;
+	wire [11:0] Tile_X4Y9_E6BEG;
+	wire [3:0] Tile_X4Y9_S1BEG;
+	wire [7:0] Tile_X4Y9_S2BEG;
+	wire [7:0] Tile_X4Y9_S2BEGb;
+	wire [15:0] Tile_X4Y9_S4BEG;
+	wire [15:0] Tile_X4Y9_SS4BEG;
+	wire [17:0] Tile_X4Y9_top2bot;
+	wire [3:0] Tile_X4Y9_W1BEG;
+	wire [7:0] Tile_X4Y9_W2BEG;
+	wire [7:0] Tile_X4Y9_W2BEGb;
+	wire [15:0] Tile_X4Y9_WW4BEG;
+	wire [11:0] Tile_X4Y9_W6BEG;
+	wire [3:0] Tile_X5Y9_N1BEG;
+	wire [7:0] Tile_X5Y9_N2BEG;
+	wire [7:0] Tile_X5Y9_N2BEGb;
+	wire [15:0] Tile_X5Y9_N4BEG;
+	wire [15:0] Tile_X5Y9_NN4BEG;
+	wire [0:0] Tile_X5Y9_Co;
+	wire [3:0] Tile_X5Y9_E1BEG;
+	wire [7:0] Tile_X5Y9_E2BEG;
+	wire [7:0] Tile_X5Y9_E2BEGb;
+	wire [15:0] Tile_X5Y9_EE4BEG;
+	wire [11:0] Tile_X5Y9_E6BEG;
+	wire [3:0] Tile_X5Y9_S1BEG;
+	wire [7:0] Tile_X5Y9_S2BEG;
+	wire [7:0] Tile_X5Y9_S2BEGb;
+	wire [15:0] Tile_X5Y9_S4BEG;
+	wire [15:0] Tile_X5Y9_SS4BEG;
+	wire [3:0] Tile_X5Y9_W1BEG;
+	wire [7:0] Tile_X5Y9_W2BEG;
+	wire [7:0] Tile_X5Y9_W2BEGb;
+	wire [15:0] Tile_X5Y9_WW4BEG;
+	wire [11:0] Tile_X5Y9_W6BEG;
+	wire [3:0] Tile_X6Y9_N1BEG;
+	wire [7:0] Tile_X6Y9_N2BEG;
+	wire [7:0] Tile_X6Y9_N2BEGb;
+	wire [15:0] Tile_X6Y9_N4BEG;
+	wire [15:0] Tile_X6Y9_NN4BEG;
+	wire [0:0] Tile_X6Y9_Co;
+	wire [3:0] Tile_X6Y9_E1BEG;
+	wire [7:0] Tile_X6Y9_E2BEG;
+	wire [7:0] Tile_X6Y9_E2BEGb;
+	wire [15:0] Tile_X6Y9_EE4BEG;
+	wire [11:0] Tile_X6Y9_E6BEG;
+	wire [3:0] Tile_X6Y9_S1BEG;
+	wire [7:0] Tile_X6Y9_S2BEG;
+	wire [7:0] Tile_X6Y9_S2BEGb;
+	wire [15:0] Tile_X6Y9_S4BEG;
+	wire [15:0] Tile_X6Y9_SS4BEG;
+	wire [3:0] Tile_X6Y9_W1BEG;
+	wire [7:0] Tile_X6Y9_W2BEG;
+	wire [7:0] Tile_X6Y9_W2BEGb;
+	wire [15:0] Tile_X6Y9_WW4BEG;
+	wire [11:0] Tile_X6Y9_W6BEG;
+	wire [3:0] Tile_X7Y9_N1BEG;
+	wire [7:0] Tile_X7Y9_N2BEG;
+	wire [7:0] Tile_X7Y9_N2BEGb;
+	wire [15:0] Tile_X7Y9_N4BEG;
+	wire [15:0] Tile_X7Y9_NN4BEG;
+	wire [0:0] Tile_X7Y9_Co;
+	wire [3:0] Tile_X7Y9_E1BEG;
+	wire [7:0] Tile_X7Y9_E2BEG;
+	wire [7:0] Tile_X7Y9_E2BEGb;
+	wire [15:0] Tile_X7Y9_EE4BEG;
+	wire [11:0] Tile_X7Y9_E6BEG;
+	wire [3:0] Tile_X7Y9_S1BEG;
+	wire [7:0] Tile_X7Y9_S2BEG;
+	wire [7:0] Tile_X7Y9_S2BEGb;
+	wire [15:0] Tile_X7Y9_S4BEG;
+	wire [15:0] Tile_X7Y9_SS4BEG;
+	wire [3:0] Tile_X7Y9_W1BEG;
+	wire [7:0] Tile_X7Y9_W2BEG;
+	wire [7:0] Tile_X7Y9_W2BEGb;
+	wire [15:0] Tile_X7Y9_WW4BEG;
+	wire [11:0] Tile_X7Y9_W6BEG;
+	wire [3:0] Tile_X8Y9_N1BEG;
+	wire [7:0] Tile_X8Y9_N2BEG;
+	wire [7:0] Tile_X8Y9_N2BEGb;
+	wire [15:0] Tile_X8Y9_N4BEG;
+	wire [15:0] Tile_X8Y9_NN4BEG;
+	wire [3:0] Tile_X8Y9_E1BEG;
+	wire [7:0] Tile_X8Y9_E2BEG;
+	wire [7:0] Tile_X8Y9_E2BEGb;
+	wire [15:0] Tile_X8Y9_EE4BEG;
+	wire [11:0] Tile_X8Y9_E6BEG;
+	wire [3:0] Tile_X8Y9_S1BEG;
+	wire [7:0] Tile_X8Y9_S2BEG;
+	wire [7:0] Tile_X8Y9_S2BEGb;
+	wire [15:0] Tile_X8Y9_S4BEG;
+	wire [15:0] Tile_X8Y9_SS4BEG;
+	wire [17:0] Tile_X8Y9_top2bot;
+	wire [3:0] Tile_X8Y9_W1BEG;
+	wire [7:0] Tile_X8Y9_W2BEG;
+	wire [7:0] Tile_X8Y9_W2BEGb;
+	wire [15:0] Tile_X8Y9_WW4BEG;
+	wire [11:0] Tile_X8Y9_W6BEG;
+	wire [3:0] Tile_X9Y9_N1BEG;
+	wire [7:0] Tile_X9Y9_N2BEG;
+	wire [7:0] Tile_X9Y9_N2BEGb;
+	wire [15:0] Tile_X9Y9_N4BEG;
+	wire [15:0] Tile_X9Y9_NN4BEG;
+	wire [0:0] Tile_X9Y9_Co;
+	wire [3:0] Tile_X9Y9_E1BEG;
+	wire [7:0] Tile_X9Y9_E2BEG;
+	wire [7:0] Tile_X9Y9_E2BEGb;
+	wire [15:0] Tile_X9Y9_EE4BEG;
+	wire [11:0] Tile_X9Y9_E6BEG;
+	wire [3:0] Tile_X9Y9_S1BEG;
+	wire [7:0] Tile_X9Y9_S2BEG;
+	wire [7:0] Tile_X9Y9_S2BEGb;
+	wire [15:0] Tile_X9Y9_S4BEG;
+	wire [15:0] Tile_X9Y9_SS4BEG;
+	wire [3:0] Tile_X9Y9_W1BEG;
+	wire [7:0] Tile_X9Y9_W2BEG;
+	wire [7:0] Tile_X9Y9_W2BEGb;
+	wire [15:0] Tile_X9Y9_WW4BEG;
+	wire [11:0] Tile_X9Y9_W6BEG;
+	wire [3:0] Tile_X10Y9_N1BEG;
+	wire [7:0] Tile_X10Y9_N2BEG;
+	wire [7:0] Tile_X10Y9_N2BEGb;
+	wire [15:0] Tile_X10Y9_N4BEG;
+	wire [15:0] Tile_X10Y9_NN4BEG;
+	wire [0:0] Tile_X10Y9_Co;
+	wire [3:0] Tile_X10Y9_E1BEG;
+	wire [7:0] Tile_X10Y9_E2BEG;
+	wire [7:0] Tile_X10Y9_E2BEGb;
+	wire [15:0] Tile_X10Y9_EE4BEG;
+	wire [11:0] Tile_X10Y9_E6BEG;
+	wire [3:0] Tile_X10Y9_S1BEG;
+	wire [7:0] Tile_X10Y9_S2BEG;
+	wire [7:0] Tile_X10Y9_S2BEGb;
+	wire [15:0] Tile_X10Y9_S4BEG;
+	wire [15:0] Tile_X10Y9_SS4BEG;
+	wire [3:0] Tile_X10Y9_W1BEG;
+	wire [7:0] Tile_X10Y9_W2BEG;
+	wire [7:0] Tile_X10Y9_W2BEGb;
+	wire [15:0] Tile_X10Y9_WW4BEG;
+	wire [11:0] Tile_X10Y9_W6BEG;
+	wire [3:0] Tile_X11Y9_S1BEG;
+	wire [7:0] Tile_X11Y9_S2BEG;
+	wire [7:0] Tile_X11Y9_S2BEGb;
+	wire [15:0] Tile_X11Y9_S4BEG;
+	wire [15:0] Tile_X11Y9_SS4BEG;
+	wire [3:0] Tile_X11Y9_W1BEG;
+	wire [7:0] Tile_X11Y9_W2BEG;
+	wire [7:0] Tile_X11Y9_W2BEGb;
+	wire [15:0] Tile_X11Y9_WW4BEG;
+	wire [11:0] Tile_X11Y9_W6BEG;
+	wire [3:0] Tile_X12Y9_S1BEG;
+	wire [7:0] Tile_X12Y9_S2BEG;
+	wire [7:0] Tile_X12Y9_S2BEGb;
+	wire [15:0] Tile_X12Y9_S4BEG;
+	wire [15:0] Tile_X12Y9_SS4BEG;
+	wire [3:0] Tile_X13Y9_S1BEG;
+	wire [7:0] Tile_X13Y9_S2BEG;
+	wire [7:0] Tile_X13Y9_S2BEGb;
+	wire [15:0] Tile_X13Y9_S4BEG;
+	wire [15:0] Tile_X13Y9_SS4BEG;
+	wire [3:0] Tile_X14Y9_S1BEG;
+	wire [7:0] Tile_X14Y9_S2BEG;
+	wire [7:0] Tile_X14Y9_S2BEGb;
+	wire [15:0] Tile_X14Y9_S4BEG;
+	wire [3:0] Tile_X0Y10_E1BEG;
+	wire [7:0] Tile_X0Y10_E2BEG;
+	wire [7:0] Tile_X0Y10_E2BEGb;
+	wire [15:0] Tile_X0Y10_EE4BEG;
+	wire [11:0] Tile_X0Y10_E6BEG;
+	wire [3:0] Tile_X1Y10_N1BEG;
+	wire [7:0] Tile_X1Y10_N2BEG;
+	wire [7:0] Tile_X1Y10_N2BEGb;
+	wire [15:0] Tile_X1Y10_N4BEG;
+	wire [15:0] Tile_X1Y10_NN4BEG;
+	wire [0:0] Tile_X1Y10_Co;
+	wire [3:0] Tile_X1Y10_E1BEG;
+	wire [7:0] Tile_X1Y10_E2BEG;
+	wire [7:0] Tile_X1Y10_E2BEGb;
+	wire [15:0] Tile_X1Y10_EE4BEG;
+	wire [11:0] Tile_X1Y10_E6BEG;
+	wire [3:0] Tile_X1Y10_S1BEG;
+	wire [7:0] Tile_X1Y10_S2BEG;
+	wire [7:0] Tile_X1Y10_S2BEGb;
+	wire [15:0] Tile_X1Y10_S4BEG;
+	wire [15:0] Tile_X1Y10_SS4BEG;
+	wire [3:0] Tile_X1Y10_W1BEG;
+	wire [7:0] Tile_X1Y10_W2BEG;
+	wire [7:0] Tile_X1Y10_W2BEGb;
+	wire [15:0] Tile_X1Y10_WW4BEG;
+	wire [11:0] Tile_X1Y10_W6BEG;
+	wire [3:0] Tile_X2Y10_N1BEG;
+	wire [7:0] Tile_X2Y10_N2BEG;
+	wire [7:0] Tile_X2Y10_N2BEGb;
+	wire [15:0] Tile_X2Y10_N4BEG;
+	wire [15:0] Tile_X2Y10_NN4BEG;
+	wire [3:0] Tile_X2Y10_E1BEG;
+	wire [7:0] Tile_X2Y10_E2BEG;
+	wire [7:0] Tile_X2Y10_E2BEGb;
+	wire [15:0] Tile_X2Y10_EE4BEG;
+	wire [11:0] Tile_X2Y10_E6BEG;
+	wire [3:0] Tile_X2Y10_S1BEG;
+	wire [7:0] Tile_X2Y10_S2BEG;
+	wire [7:0] Tile_X2Y10_S2BEGb;
+	wire [15:0] Tile_X2Y10_S4BEG;
+	wire [15:0] Tile_X2Y10_SS4BEG;
+	wire [3:0] Tile_X2Y10_W1BEG;
+	wire [7:0] Tile_X2Y10_W2BEG;
+	wire [7:0] Tile_X2Y10_W2BEGb;
+	wire [15:0] Tile_X2Y10_WW4BEG;
+	wire [11:0] Tile_X2Y10_W6BEG;
+	wire [3:0] Tile_X3Y10_N1BEG;
+	wire [7:0] Tile_X3Y10_N2BEG;
+	wire [7:0] Tile_X3Y10_N2BEGb;
+	wire [15:0] Tile_X3Y10_N4BEG;
+	wire [15:0] Tile_X3Y10_NN4BEG;
+	wire [0:0] Tile_X3Y10_Co;
+	wire [3:0] Tile_X3Y10_E1BEG;
+	wire [7:0] Tile_X3Y10_E2BEG;
+	wire [7:0] Tile_X3Y10_E2BEGb;
+	wire [15:0] Tile_X3Y10_EE4BEG;
+	wire [11:0] Tile_X3Y10_E6BEG;
+	wire [3:0] Tile_X3Y10_S1BEG;
+	wire [7:0] Tile_X3Y10_S2BEG;
+	wire [7:0] Tile_X3Y10_S2BEGb;
+	wire [15:0] Tile_X3Y10_S4BEG;
+	wire [15:0] Tile_X3Y10_SS4BEG;
+	wire [3:0] Tile_X3Y10_W1BEG;
+	wire [7:0] Tile_X3Y10_W2BEG;
+	wire [7:0] Tile_X3Y10_W2BEGb;
+	wire [15:0] Tile_X3Y10_WW4BEG;
+	wire [11:0] Tile_X3Y10_W6BEG;
+	wire [3:0] Tile_X4Y10_N1BEG;
+	wire [7:0] Tile_X4Y10_N2BEG;
+	wire [7:0] Tile_X4Y10_N2BEGb;
+	wire [15:0] Tile_X4Y10_N4BEG;
+	wire [15:0] Tile_X4Y10_NN4BEG;
+	wire [9:0] Tile_X4Y10_bot2top;
+	wire [3:0] Tile_X4Y10_E1BEG;
+	wire [7:0] Tile_X4Y10_E2BEG;
+	wire [7:0] Tile_X4Y10_E2BEGb;
+	wire [15:0] Tile_X4Y10_EE4BEG;
+	wire [11:0] Tile_X4Y10_E6BEG;
+	wire [3:0] Tile_X4Y10_S1BEG;
+	wire [7:0] Tile_X4Y10_S2BEG;
+	wire [7:0] Tile_X4Y10_S2BEGb;
+	wire [15:0] Tile_X4Y10_S4BEG;
+	wire [15:0] Tile_X4Y10_SS4BEG;
+	wire [3:0] Tile_X4Y10_W1BEG;
+	wire [7:0] Tile_X4Y10_W2BEG;
+	wire [7:0] Tile_X4Y10_W2BEGb;
+	wire [15:0] Tile_X4Y10_WW4BEG;
+	wire [11:0] Tile_X4Y10_W6BEG;
+	wire [3:0] Tile_X5Y10_N1BEG;
+	wire [7:0] Tile_X5Y10_N2BEG;
+	wire [7:0] Tile_X5Y10_N2BEGb;
+	wire [15:0] Tile_X5Y10_N4BEG;
+	wire [15:0] Tile_X5Y10_NN4BEG;
+	wire [0:0] Tile_X5Y10_Co;
+	wire [3:0] Tile_X5Y10_E1BEG;
+	wire [7:0] Tile_X5Y10_E2BEG;
+	wire [7:0] Tile_X5Y10_E2BEGb;
+	wire [15:0] Tile_X5Y10_EE4BEG;
+	wire [11:0] Tile_X5Y10_E6BEG;
+	wire [3:0] Tile_X5Y10_S1BEG;
+	wire [7:0] Tile_X5Y10_S2BEG;
+	wire [7:0] Tile_X5Y10_S2BEGb;
+	wire [15:0] Tile_X5Y10_S4BEG;
+	wire [15:0] Tile_X5Y10_SS4BEG;
+	wire [3:0] Tile_X5Y10_W1BEG;
+	wire [7:0] Tile_X5Y10_W2BEG;
+	wire [7:0] Tile_X5Y10_W2BEGb;
+	wire [15:0] Tile_X5Y10_WW4BEG;
+	wire [11:0] Tile_X5Y10_W6BEG;
+	wire [3:0] Tile_X6Y10_N1BEG;
+	wire [7:0] Tile_X6Y10_N2BEG;
+	wire [7:0] Tile_X6Y10_N2BEGb;
+	wire [15:0] Tile_X6Y10_N4BEG;
+	wire [15:0] Tile_X6Y10_NN4BEG;
+	wire [0:0] Tile_X6Y10_Co;
+	wire [3:0] Tile_X6Y10_E1BEG;
+	wire [7:0] Tile_X6Y10_E2BEG;
+	wire [7:0] Tile_X6Y10_E2BEGb;
+	wire [15:0] Tile_X6Y10_EE4BEG;
+	wire [11:0] Tile_X6Y10_E6BEG;
+	wire [3:0] Tile_X6Y10_S1BEG;
+	wire [7:0] Tile_X6Y10_S2BEG;
+	wire [7:0] Tile_X6Y10_S2BEGb;
+	wire [15:0] Tile_X6Y10_S4BEG;
+	wire [15:0] Tile_X6Y10_SS4BEG;
+	wire [3:0] Tile_X6Y10_W1BEG;
+	wire [7:0] Tile_X6Y10_W2BEG;
+	wire [7:0] Tile_X6Y10_W2BEGb;
+	wire [15:0] Tile_X6Y10_WW4BEG;
+	wire [11:0] Tile_X6Y10_W6BEG;
+	wire [3:0] Tile_X7Y10_N1BEG;
+	wire [7:0] Tile_X7Y10_N2BEG;
+	wire [7:0] Tile_X7Y10_N2BEGb;
+	wire [15:0] Tile_X7Y10_N4BEG;
+	wire [15:0] Tile_X7Y10_NN4BEG;
+	wire [0:0] Tile_X7Y10_Co;
+	wire [3:0] Tile_X7Y10_E1BEG;
+	wire [7:0] Tile_X7Y10_E2BEG;
+	wire [7:0] Tile_X7Y10_E2BEGb;
+	wire [15:0] Tile_X7Y10_EE4BEG;
+	wire [11:0] Tile_X7Y10_E6BEG;
+	wire [3:0] Tile_X7Y10_S1BEG;
+	wire [7:0] Tile_X7Y10_S2BEG;
+	wire [7:0] Tile_X7Y10_S2BEGb;
+	wire [15:0] Tile_X7Y10_S4BEG;
+	wire [15:0] Tile_X7Y10_SS4BEG;
+	wire [3:0] Tile_X7Y10_W1BEG;
+	wire [7:0] Tile_X7Y10_W2BEG;
+	wire [7:0] Tile_X7Y10_W2BEGb;
+	wire [15:0] Tile_X7Y10_WW4BEG;
+	wire [11:0] Tile_X7Y10_W6BEG;
+	wire [3:0] Tile_X8Y10_N1BEG;
+	wire [7:0] Tile_X8Y10_N2BEG;
+	wire [7:0] Tile_X8Y10_N2BEGb;
+	wire [15:0] Tile_X8Y10_N4BEG;
+	wire [15:0] Tile_X8Y10_NN4BEG;
+	wire [9:0] Tile_X8Y10_bot2top;
+	wire [3:0] Tile_X8Y10_E1BEG;
+	wire [7:0] Tile_X8Y10_E2BEG;
+	wire [7:0] Tile_X8Y10_E2BEGb;
+	wire [15:0] Tile_X8Y10_EE4BEG;
+	wire [11:0] Tile_X8Y10_E6BEG;
+	wire [3:0] Tile_X8Y10_S1BEG;
+	wire [7:0] Tile_X8Y10_S2BEG;
+	wire [7:0] Tile_X8Y10_S2BEGb;
+	wire [15:0] Tile_X8Y10_S4BEG;
+	wire [15:0] Tile_X8Y10_SS4BEG;
+	wire [3:0] Tile_X8Y10_W1BEG;
+	wire [7:0] Tile_X8Y10_W2BEG;
+	wire [7:0] Tile_X8Y10_W2BEGb;
+	wire [15:0] Tile_X8Y10_WW4BEG;
+	wire [11:0] Tile_X8Y10_W6BEG;
+	wire [3:0] Tile_X9Y10_N1BEG;
+	wire [7:0] Tile_X9Y10_N2BEG;
+	wire [7:0] Tile_X9Y10_N2BEGb;
+	wire [15:0] Tile_X9Y10_N4BEG;
+	wire [15:0] Tile_X9Y10_NN4BEG;
+	wire [0:0] Tile_X9Y10_Co;
+	wire [3:0] Tile_X9Y10_E1BEG;
+	wire [7:0] Tile_X9Y10_E2BEG;
+	wire [7:0] Tile_X9Y10_E2BEGb;
+	wire [15:0] Tile_X9Y10_EE4BEG;
+	wire [11:0] Tile_X9Y10_E6BEG;
+	wire [3:0] Tile_X9Y10_S1BEG;
+	wire [7:0] Tile_X9Y10_S2BEG;
+	wire [7:0] Tile_X9Y10_S2BEGb;
+	wire [15:0] Tile_X9Y10_S4BEG;
+	wire [15:0] Tile_X9Y10_SS4BEG;
+	wire [3:0] Tile_X9Y10_W1BEG;
+	wire [7:0] Tile_X9Y10_W2BEG;
+	wire [7:0] Tile_X9Y10_W2BEGb;
+	wire [15:0] Tile_X9Y10_WW4BEG;
+	wire [11:0] Tile_X9Y10_W6BEG;
+	wire [3:0] Tile_X10Y10_N1BEG;
+	wire [7:0] Tile_X10Y10_N2BEG;
+	wire [7:0] Tile_X10Y10_N2BEGb;
+	wire [15:0] Tile_X10Y10_N4BEG;
+	wire [15:0] Tile_X10Y10_NN4BEG;
+	wire [0:0] Tile_X10Y10_Co;
+	wire [3:0] Tile_X10Y10_E1BEG;
+	wire [7:0] Tile_X10Y10_E2BEG;
+	wire [7:0] Tile_X10Y10_E2BEGb;
+	wire [15:0] Tile_X10Y10_EE4BEG;
+	wire [11:0] Tile_X10Y10_E6BEG;
+	wire [3:0] Tile_X10Y10_S1BEG;
+	wire [7:0] Tile_X10Y10_S2BEG;
+	wire [7:0] Tile_X10Y10_S2BEGb;
+	wire [15:0] Tile_X10Y10_S4BEG;
+	wire [15:0] Tile_X10Y10_SS4BEG;
+	wire [3:0] Tile_X10Y10_W1BEG;
+	wire [7:0] Tile_X10Y10_W2BEG;
+	wire [7:0] Tile_X10Y10_W2BEGb;
+	wire [15:0] Tile_X10Y10_WW4BEG;
+	wire [11:0] Tile_X10Y10_W6BEG;
+	wire [3:0] Tile_X11Y10_N1BEG;
+	wire [7:0] Tile_X11Y10_N2BEG;
+	wire [7:0] Tile_X11Y10_N2BEGb;
+	wire [15:0] Tile_X11Y10_N4BEG;
+	wire [15:0] Tile_X11Y10_NN4BEG;
+	wire [0:0] Tile_X11Y10_Co;
+	wire [3:0] Tile_X11Y10_E1BEG;
+	wire [7:0] Tile_X11Y10_E2BEG;
+	wire [7:0] Tile_X11Y10_E2BEGb;
+	wire [15:0] Tile_X11Y10_EE4BEG;
+	wire [11:0] Tile_X11Y10_E6BEG;
+	wire [3:0] Tile_X11Y10_S1BEG;
+	wire [7:0] Tile_X11Y10_S2BEG;
+	wire [7:0] Tile_X11Y10_S2BEGb;
+	wire [15:0] Tile_X11Y10_S4BEG;
+	wire [15:0] Tile_X11Y10_SS4BEG;
+	wire [3:0] Tile_X11Y10_W1BEG;
+	wire [7:0] Tile_X11Y10_W2BEG;
+	wire [7:0] Tile_X11Y10_W2BEGb;
+	wire [15:0] Tile_X11Y10_WW4BEG;
+	wire [11:0] Tile_X11Y10_W6BEG;
+	wire [3:0] Tile_X12Y10_N1BEG;
+	wire [7:0] Tile_X12Y10_N2BEG;
+	wire [7:0] Tile_X12Y10_N2BEGb;
+	wire [15:0] Tile_X12Y10_N4BEG;
+	wire [15:0] Tile_X12Y10_NN4BEG;
+	wire [3:0] Tile_X12Y10_E1BEG;
+	wire [7:0] Tile_X12Y10_E2BEG;
+	wire [7:0] Tile_X12Y10_E2BEGb;
+	wire [15:0] Tile_X12Y10_EE4BEG;
+	wire [11:0] Tile_X12Y10_E6BEG;
+	wire [3:0] Tile_X12Y10_S1BEG;
+	wire [7:0] Tile_X12Y10_S2BEG;
+	wire [7:0] Tile_X12Y10_S2BEGb;
+	wire [15:0] Tile_X12Y10_S4BEG;
+	wire [15:0] Tile_X12Y10_SS4BEG;
+	wire [3:0] Tile_X12Y10_W1BEG;
+	wire [7:0] Tile_X12Y10_W2BEG;
+	wire [7:0] Tile_X12Y10_W2BEGb;
+	wire [15:0] Tile_X12Y10_WW4BEG;
+	wire [11:0] Tile_X12Y10_W6BEG;
+	wire [3:0] Tile_X13Y10_N1BEG;
+	wire [7:0] Tile_X13Y10_N2BEG;
+	wire [7:0] Tile_X13Y10_N2BEGb;
+	wire [15:0] Tile_X13Y10_N4BEG;
+	wire [15:0] Tile_X13Y10_NN4BEG;
+	wire [0:0] Tile_X13Y10_Co;
+	wire [3:0] Tile_X13Y10_E1BEG;
+	wire [7:0] Tile_X13Y10_E2BEG;
+	wire [7:0] Tile_X13Y10_E2BEGb;
+	wire [15:0] Tile_X13Y10_EE4BEG;
+	wire [11:0] Tile_X13Y10_E6BEG;
+	wire [3:0] Tile_X13Y10_S1BEG;
+	wire [7:0] Tile_X13Y10_S2BEG;
+	wire [7:0] Tile_X13Y10_S2BEGb;
+	wire [15:0] Tile_X13Y10_S4BEG;
+	wire [15:0] Tile_X13Y10_SS4BEG;
+	wire [3:0] Tile_X13Y10_W1BEG;
+	wire [7:0] Tile_X13Y10_W2BEG;
+	wire [7:0] Tile_X13Y10_W2BEGb;
+	wire [15:0] Tile_X13Y10_WW4BEG;
+	wire [11:0] Tile_X13Y10_W6BEG;
+	wire [3:0] Tile_X14Y10_N1BEG;
+	wire [7:0] Tile_X14Y10_N2BEG;
+	wire [7:0] Tile_X14Y10_N2BEGb;
+	wire [15:0] Tile_X14Y10_N4BEG;
+	wire [3:0] Tile_X14Y10_S1BEG;
+	wire [7:0] Tile_X14Y10_S2BEG;
+	wire [7:0] Tile_X14Y10_S2BEGb;
+	wire [15:0] Tile_X14Y10_S4BEG;
+	wire [3:0] Tile_X14Y10_W1BEG;
+	wire [7:0] Tile_X14Y10_W2BEG;
+	wire [7:0] Tile_X14Y10_W2BEGb;
+	wire [15:0] Tile_X14Y10_WW4BEG;
+	wire [11:0] Tile_X14Y10_W6BEG;
+	wire [3:0] Tile_X0Y11_E1BEG;
+	wire [7:0] Tile_X0Y11_E2BEG;
+	wire [7:0] Tile_X0Y11_E2BEGb;
+	wire [15:0] Tile_X0Y11_EE4BEG;
+	wire [11:0] Tile_X0Y11_E6BEG;
+	wire [3:0] Tile_X1Y11_N1BEG;
+	wire [7:0] Tile_X1Y11_N2BEG;
+	wire [7:0] Tile_X1Y11_N2BEGb;
+	wire [15:0] Tile_X1Y11_N4BEG;
+	wire [15:0] Tile_X1Y11_NN4BEG;
+	wire [0:0] Tile_X1Y11_Co;
+	wire [3:0] Tile_X1Y11_E1BEG;
+	wire [7:0] Tile_X1Y11_E2BEG;
+	wire [7:0] Tile_X1Y11_E2BEGb;
+	wire [15:0] Tile_X1Y11_EE4BEG;
+	wire [11:0] Tile_X1Y11_E6BEG;
+	wire [3:0] Tile_X1Y11_S1BEG;
+	wire [7:0] Tile_X1Y11_S2BEG;
+	wire [7:0] Tile_X1Y11_S2BEGb;
+	wire [15:0] Tile_X1Y11_S4BEG;
+	wire [15:0] Tile_X1Y11_SS4BEG;
+	wire [3:0] Tile_X1Y11_W1BEG;
+	wire [7:0] Tile_X1Y11_W2BEG;
+	wire [7:0] Tile_X1Y11_W2BEGb;
+	wire [15:0] Tile_X1Y11_WW4BEG;
+	wire [11:0] Tile_X1Y11_W6BEG;
+	wire [3:0] Tile_X2Y11_N1BEG;
+	wire [7:0] Tile_X2Y11_N2BEG;
+	wire [7:0] Tile_X2Y11_N2BEGb;
+	wire [15:0] Tile_X2Y11_N4BEG;
+	wire [15:0] Tile_X2Y11_NN4BEG;
+	wire [3:0] Tile_X2Y11_E1BEG;
+	wire [7:0] Tile_X2Y11_E2BEG;
+	wire [7:0] Tile_X2Y11_E2BEGb;
+	wire [15:0] Tile_X2Y11_EE4BEG;
+	wire [11:0] Tile_X2Y11_E6BEG;
+	wire [3:0] Tile_X2Y11_S1BEG;
+	wire [7:0] Tile_X2Y11_S2BEG;
+	wire [7:0] Tile_X2Y11_S2BEGb;
+	wire [15:0] Tile_X2Y11_S4BEG;
+	wire [15:0] Tile_X2Y11_SS4BEG;
+	wire [3:0] Tile_X2Y11_W1BEG;
+	wire [7:0] Tile_X2Y11_W2BEG;
+	wire [7:0] Tile_X2Y11_W2BEGb;
+	wire [15:0] Tile_X2Y11_WW4BEG;
+	wire [11:0] Tile_X2Y11_W6BEG;
+	wire [3:0] Tile_X3Y11_N1BEG;
+	wire [7:0] Tile_X3Y11_N2BEG;
+	wire [7:0] Tile_X3Y11_N2BEGb;
+	wire [15:0] Tile_X3Y11_N4BEG;
+	wire [15:0] Tile_X3Y11_NN4BEG;
+	wire [0:0] Tile_X3Y11_Co;
+	wire [3:0] Tile_X3Y11_E1BEG;
+	wire [7:0] Tile_X3Y11_E2BEG;
+	wire [7:0] Tile_X3Y11_E2BEGb;
+	wire [15:0] Tile_X3Y11_EE4BEG;
+	wire [11:0] Tile_X3Y11_E6BEG;
+	wire [3:0] Tile_X3Y11_S1BEG;
+	wire [7:0] Tile_X3Y11_S2BEG;
+	wire [7:0] Tile_X3Y11_S2BEGb;
+	wire [15:0] Tile_X3Y11_S4BEG;
+	wire [15:0] Tile_X3Y11_SS4BEG;
+	wire [3:0] Tile_X3Y11_W1BEG;
+	wire [7:0] Tile_X3Y11_W2BEG;
+	wire [7:0] Tile_X3Y11_W2BEGb;
+	wire [15:0] Tile_X3Y11_WW4BEG;
+	wire [11:0] Tile_X3Y11_W6BEG;
+	wire [3:0] Tile_X4Y11_N1BEG;
+	wire [7:0] Tile_X4Y11_N2BEG;
+	wire [7:0] Tile_X4Y11_N2BEGb;
+	wire [15:0] Tile_X4Y11_N4BEG;
+	wire [15:0] Tile_X4Y11_NN4BEG;
+	wire [3:0] Tile_X4Y11_E1BEG;
+	wire [7:0] Tile_X4Y11_E2BEG;
+	wire [7:0] Tile_X4Y11_E2BEGb;
+	wire [15:0] Tile_X4Y11_EE4BEG;
+	wire [11:0] Tile_X4Y11_E6BEG;
+	wire [3:0] Tile_X4Y11_S1BEG;
+	wire [7:0] Tile_X4Y11_S2BEG;
+	wire [7:0] Tile_X4Y11_S2BEGb;
+	wire [15:0] Tile_X4Y11_S4BEG;
+	wire [15:0] Tile_X4Y11_SS4BEG;
+	wire [17:0] Tile_X4Y11_top2bot;
+	wire [3:0] Tile_X4Y11_W1BEG;
+	wire [7:0] Tile_X4Y11_W2BEG;
+	wire [7:0] Tile_X4Y11_W2BEGb;
+	wire [15:0] Tile_X4Y11_WW4BEG;
+	wire [11:0] Tile_X4Y11_W6BEG;
+	wire [3:0] Tile_X5Y11_N1BEG;
+	wire [7:0] Tile_X5Y11_N2BEG;
+	wire [7:0] Tile_X5Y11_N2BEGb;
+	wire [15:0] Tile_X5Y11_N4BEG;
+	wire [15:0] Tile_X5Y11_NN4BEG;
+	wire [0:0] Tile_X5Y11_Co;
+	wire [3:0] Tile_X5Y11_E1BEG;
+	wire [7:0] Tile_X5Y11_E2BEG;
+	wire [7:0] Tile_X5Y11_E2BEGb;
+	wire [15:0] Tile_X5Y11_EE4BEG;
+	wire [11:0] Tile_X5Y11_E6BEG;
+	wire [3:0] Tile_X5Y11_S1BEG;
+	wire [7:0] Tile_X5Y11_S2BEG;
+	wire [7:0] Tile_X5Y11_S2BEGb;
+	wire [15:0] Tile_X5Y11_S4BEG;
+	wire [15:0] Tile_X5Y11_SS4BEG;
+	wire [3:0] Tile_X5Y11_W1BEG;
+	wire [7:0] Tile_X5Y11_W2BEG;
+	wire [7:0] Tile_X5Y11_W2BEGb;
+	wire [15:0] Tile_X5Y11_WW4BEG;
+	wire [11:0] Tile_X5Y11_W6BEG;
+	wire [3:0] Tile_X6Y11_N1BEG;
+	wire [7:0] Tile_X6Y11_N2BEG;
+	wire [7:0] Tile_X6Y11_N2BEGb;
+	wire [15:0] Tile_X6Y11_N4BEG;
+	wire [15:0] Tile_X6Y11_NN4BEG;
+	wire [0:0] Tile_X6Y11_Co;
+	wire [3:0] Tile_X6Y11_E1BEG;
+	wire [7:0] Tile_X6Y11_E2BEG;
+	wire [7:0] Tile_X6Y11_E2BEGb;
+	wire [15:0] Tile_X6Y11_EE4BEG;
+	wire [11:0] Tile_X6Y11_E6BEG;
+	wire [3:0] Tile_X6Y11_S1BEG;
+	wire [7:0] Tile_X6Y11_S2BEG;
+	wire [7:0] Tile_X6Y11_S2BEGb;
+	wire [15:0] Tile_X6Y11_S4BEG;
+	wire [15:0] Tile_X6Y11_SS4BEG;
+	wire [3:0] Tile_X6Y11_W1BEG;
+	wire [7:0] Tile_X6Y11_W2BEG;
+	wire [7:0] Tile_X6Y11_W2BEGb;
+	wire [15:0] Tile_X6Y11_WW4BEG;
+	wire [11:0] Tile_X6Y11_W6BEG;
+	wire [3:0] Tile_X7Y11_N1BEG;
+	wire [7:0] Tile_X7Y11_N2BEG;
+	wire [7:0] Tile_X7Y11_N2BEGb;
+	wire [15:0] Tile_X7Y11_N4BEG;
+	wire [15:0] Tile_X7Y11_NN4BEG;
+	wire [0:0] Tile_X7Y11_Co;
+	wire [3:0] Tile_X7Y11_E1BEG;
+	wire [7:0] Tile_X7Y11_E2BEG;
+	wire [7:0] Tile_X7Y11_E2BEGb;
+	wire [15:0] Tile_X7Y11_EE4BEG;
+	wire [11:0] Tile_X7Y11_E6BEG;
+	wire [3:0] Tile_X7Y11_S1BEG;
+	wire [7:0] Tile_X7Y11_S2BEG;
+	wire [7:0] Tile_X7Y11_S2BEGb;
+	wire [15:0] Tile_X7Y11_S4BEG;
+	wire [15:0] Tile_X7Y11_SS4BEG;
+	wire [3:0] Tile_X7Y11_W1BEG;
+	wire [7:0] Tile_X7Y11_W2BEG;
+	wire [7:0] Tile_X7Y11_W2BEGb;
+	wire [15:0] Tile_X7Y11_WW4BEG;
+	wire [11:0] Tile_X7Y11_W6BEG;
+	wire [3:0] Tile_X8Y11_N1BEG;
+	wire [7:0] Tile_X8Y11_N2BEG;
+	wire [7:0] Tile_X8Y11_N2BEGb;
+	wire [15:0] Tile_X8Y11_N4BEG;
+	wire [15:0] Tile_X8Y11_NN4BEG;
+	wire [3:0] Tile_X8Y11_E1BEG;
+	wire [7:0] Tile_X8Y11_E2BEG;
+	wire [7:0] Tile_X8Y11_E2BEGb;
+	wire [15:0] Tile_X8Y11_EE4BEG;
+	wire [11:0] Tile_X8Y11_E6BEG;
+	wire [3:0] Tile_X8Y11_S1BEG;
+	wire [7:0] Tile_X8Y11_S2BEG;
+	wire [7:0] Tile_X8Y11_S2BEGb;
+	wire [15:0] Tile_X8Y11_S4BEG;
+	wire [15:0] Tile_X8Y11_SS4BEG;
+	wire [17:0] Tile_X8Y11_top2bot;
+	wire [3:0] Tile_X8Y11_W1BEG;
+	wire [7:0] Tile_X8Y11_W2BEG;
+	wire [7:0] Tile_X8Y11_W2BEGb;
+	wire [15:0] Tile_X8Y11_WW4BEG;
+	wire [11:0] Tile_X8Y11_W6BEG;
+	wire [3:0] Tile_X9Y11_N1BEG;
+	wire [7:0] Tile_X9Y11_N2BEG;
+	wire [7:0] Tile_X9Y11_N2BEGb;
+	wire [15:0] Tile_X9Y11_N4BEG;
+	wire [15:0] Tile_X9Y11_NN4BEG;
+	wire [0:0] Tile_X9Y11_Co;
+	wire [3:0] Tile_X9Y11_E1BEG;
+	wire [7:0] Tile_X9Y11_E2BEG;
+	wire [7:0] Tile_X9Y11_E2BEGb;
+	wire [15:0] Tile_X9Y11_EE4BEG;
+	wire [11:0] Tile_X9Y11_E6BEG;
+	wire [3:0] Tile_X9Y11_S1BEG;
+	wire [7:0] Tile_X9Y11_S2BEG;
+	wire [7:0] Tile_X9Y11_S2BEGb;
+	wire [15:0] Tile_X9Y11_S4BEG;
+	wire [15:0] Tile_X9Y11_SS4BEG;
+	wire [3:0] Tile_X9Y11_W1BEG;
+	wire [7:0] Tile_X9Y11_W2BEG;
+	wire [7:0] Tile_X9Y11_W2BEGb;
+	wire [15:0] Tile_X9Y11_WW4BEG;
+	wire [11:0] Tile_X9Y11_W6BEG;
+	wire [3:0] Tile_X10Y11_N1BEG;
+	wire [7:0] Tile_X10Y11_N2BEG;
+	wire [7:0] Tile_X10Y11_N2BEGb;
+	wire [15:0] Tile_X10Y11_N4BEG;
+	wire [15:0] Tile_X10Y11_NN4BEG;
+	wire [0:0] Tile_X10Y11_Co;
+	wire [3:0] Tile_X10Y11_E1BEG;
+	wire [7:0] Tile_X10Y11_E2BEG;
+	wire [7:0] Tile_X10Y11_E2BEGb;
+	wire [15:0] Tile_X10Y11_EE4BEG;
+	wire [11:0] Tile_X10Y11_E6BEG;
+	wire [3:0] Tile_X10Y11_S1BEG;
+	wire [7:0] Tile_X10Y11_S2BEG;
+	wire [7:0] Tile_X10Y11_S2BEGb;
+	wire [15:0] Tile_X10Y11_S4BEG;
+	wire [15:0] Tile_X10Y11_SS4BEG;
+	wire [3:0] Tile_X10Y11_W1BEG;
+	wire [7:0] Tile_X10Y11_W2BEG;
+	wire [7:0] Tile_X10Y11_W2BEGb;
+	wire [15:0] Tile_X10Y11_WW4BEG;
+	wire [11:0] Tile_X10Y11_W6BEG;
+	wire [3:0] Tile_X11Y11_N1BEG;
+	wire [7:0] Tile_X11Y11_N2BEG;
+	wire [7:0] Tile_X11Y11_N2BEGb;
+	wire [15:0] Tile_X11Y11_N4BEG;
+	wire [15:0] Tile_X11Y11_NN4BEG;
+	wire [0:0] Tile_X11Y11_Co;
+	wire [3:0] Tile_X11Y11_E1BEG;
+	wire [7:0] Tile_X11Y11_E2BEG;
+	wire [7:0] Tile_X11Y11_E2BEGb;
+	wire [15:0] Tile_X11Y11_EE4BEG;
+	wire [11:0] Tile_X11Y11_E6BEG;
+	wire [3:0] Tile_X11Y11_S1BEG;
+	wire [7:0] Tile_X11Y11_S2BEG;
+	wire [7:0] Tile_X11Y11_S2BEGb;
+	wire [15:0] Tile_X11Y11_S4BEG;
+	wire [15:0] Tile_X11Y11_SS4BEG;
+	wire [3:0] Tile_X11Y11_W1BEG;
+	wire [7:0] Tile_X11Y11_W2BEG;
+	wire [7:0] Tile_X11Y11_W2BEGb;
+	wire [15:0] Tile_X11Y11_WW4BEG;
+	wire [11:0] Tile_X11Y11_W6BEG;
+	wire [3:0] Tile_X12Y11_N1BEG;
+	wire [7:0] Tile_X12Y11_N2BEG;
+	wire [7:0] Tile_X12Y11_N2BEGb;
+	wire [15:0] Tile_X12Y11_N4BEG;
+	wire [15:0] Tile_X12Y11_NN4BEG;
+	wire [3:0] Tile_X12Y11_E1BEG;
+	wire [7:0] Tile_X12Y11_E2BEG;
+	wire [7:0] Tile_X12Y11_E2BEGb;
+	wire [15:0] Tile_X12Y11_EE4BEG;
+	wire [11:0] Tile_X12Y11_E6BEG;
+	wire [3:0] Tile_X12Y11_S1BEG;
+	wire [7:0] Tile_X12Y11_S2BEG;
+	wire [7:0] Tile_X12Y11_S2BEGb;
+	wire [15:0] Tile_X12Y11_S4BEG;
+	wire [15:0] Tile_X12Y11_SS4BEG;
+	wire [3:0] Tile_X12Y11_W1BEG;
+	wire [7:0] Tile_X12Y11_W2BEG;
+	wire [7:0] Tile_X12Y11_W2BEGb;
+	wire [15:0] Tile_X12Y11_WW4BEG;
+	wire [11:0] Tile_X12Y11_W6BEG;
+	wire [3:0] Tile_X13Y11_N1BEG;
+	wire [7:0] Tile_X13Y11_N2BEG;
+	wire [7:0] Tile_X13Y11_N2BEGb;
+	wire [15:0] Tile_X13Y11_N4BEG;
+	wire [15:0] Tile_X13Y11_NN4BEG;
+	wire [0:0] Tile_X13Y11_Co;
+	wire [3:0] Tile_X13Y11_E1BEG;
+	wire [7:0] Tile_X13Y11_E2BEG;
+	wire [7:0] Tile_X13Y11_E2BEGb;
+	wire [15:0] Tile_X13Y11_EE4BEG;
+	wire [11:0] Tile_X13Y11_E6BEG;
+	wire [3:0] Tile_X13Y11_S1BEG;
+	wire [7:0] Tile_X13Y11_S2BEG;
+	wire [7:0] Tile_X13Y11_S2BEGb;
+	wire [15:0] Tile_X13Y11_S4BEG;
+	wire [15:0] Tile_X13Y11_SS4BEG;
+	wire [3:0] Tile_X13Y11_W1BEG;
+	wire [7:0] Tile_X13Y11_W2BEG;
+	wire [7:0] Tile_X13Y11_W2BEGb;
+	wire [15:0] Tile_X13Y11_WW4BEG;
+	wire [11:0] Tile_X13Y11_W6BEG;
+	wire [3:0] Tile_X14Y11_N1BEG;
+	wire [7:0] Tile_X14Y11_N2BEG;
+	wire [7:0] Tile_X14Y11_N2BEGb;
+	wire [15:0] Tile_X14Y11_N4BEG;
+	wire [3:0] Tile_X14Y11_S1BEG;
+	wire [7:0] Tile_X14Y11_S2BEG;
+	wire [7:0] Tile_X14Y11_S2BEGb;
+	wire [15:0] Tile_X14Y11_S4BEG;
+	wire [3:0] Tile_X14Y11_W1BEG;
+	wire [7:0] Tile_X14Y11_W2BEG;
+	wire [7:0] Tile_X14Y11_W2BEGb;
+	wire [15:0] Tile_X14Y11_WW4BEG;
+	wire [11:0] Tile_X14Y11_W6BEG;
+	wire [3:0] Tile_X0Y12_E1BEG;
+	wire [7:0] Tile_X0Y12_E2BEG;
+	wire [7:0] Tile_X0Y12_E2BEGb;
+	wire [15:0] Tile_X0Y12_EE4BEG;
+	wire [11:0] Tile_X0Y12_E6BEG;
+	wire [3:0] Tile_X1Y12_N1BEG;
+	wire [7:0] Tile_X1Y12_N2BEG;
+	wire [7:0] Tile_X1Y12_N2BEGb;
+	wire [15:0] Tile_X1Y12_N4BEG;
+	wire [15:0] Tile_X1Y12_NN4BEG;
+	wire [0:0] Tile_X1Y12_Co;
+	wire [3:0] Tile_X1Y12_E1BEG;
+	wire [7:0] Tile_X1Y12_E2BEG;
+	wire [7:0] Tile_X1Y12_E2BEGb;
+	wire [15:0] Tile_X1Y12_EE4BEG;
+	wire [11:0] Tile_X1Y12_E6BEG;
+	wire [3:0] Tile_X1Y12_S1BEG;
+	wire [7:0] Tile_X1Y12_S2BEG;
+	wire [7:0] Tile_X1Y12_S2BEGb;
+	wire [15:0] Tile_X1Y12_S4BEG;
+	wire [15:0] Tile_X1Y12_SS4BEG;
+	wire [3:0] Tile_X1Y12_W1BEG;
+	wire [7:0] Tile_X1Y12_W2BEG;
+	wire [7:0] Tile_X1Y12_W2BEGb;
+	wire [15:0] Tile_X1Y12_WW4BEG;
+	wire [11:0] Tile_X1Y12_W6BEG;
+	wire [3:0] Tile_X2Y12_N1BEG;
+	wire [7:0] Tile_X2Y12_N2BEG;
+	wire [7:0] Tile_X2Y12_N2BEGb;
+	wire [15:0] Tile_X2Y12_N4BEG;
+	wire [15:0] Tile_X2Y12_NN4BEG;
+	wire [3:0] Tile_X2Y12_E1BEG;
+	wire [7:0] Tile_X2Y12_E2BEG;
+	wire [7:0] Tile_X2Y12_E2BEGb;
+	wire [15:0] Tile_X2Y12_EE4BEG;
+	wire [11:0] Tile_X2Y12_E6BEG;
+	wire [3:0] Tile_X2Y12_S1BEG;
+	wire [7:0] Tile_X2Y12_S2BEG;
+	wire [7:0] Tile_X2Y12_S2BEGb;
+	wire [15:0] Tile_X2Y12_S4BEG;
+	wire [15:0] Tile_X2Y12_SS4BEG;
+	wire [3:0] Tile_X2Y12_W1BEG;
+	wire [7:0] Tile_X2Y12_W2BEG;
+	wire [7:0] Tile_X2Y12_W2BEGb;
+	wire [15:0] Tile_X2Y12_WW4BEG;
+	wire [11:0] Tile_X2Y12_W6BEG;
+	wire [3:0] Tile_X3Y12_N1BEG;
+	wire [7:0] Tile_X3Y12_N2BEG;
+	wire [7:0] Tile_X3Y12_N2BEGb;
+	wire [15:0] Tile_X3Y12_N4BEG;
+	wire [15:0] Tile_X3Y12_NN4BEG;
+	wire [0:0] Tile_X3Y12_Co;
+	wire [3:0] Tile_X3Y12_E1BEG;
+	wire [7:0] Tile_X3Y12_E2BEG;
+	wire [7:0] Tile_X3Y12_E2BEGb;
+	wire [15:0] Tile_X3Y12_EE4BEG;
+	wire [11:0] Tile_X3Y12_E6BEG;
+	wire [3:0] Tile_X3Y12_S1BEG;
+	wire [7:0] Tile_X3Y12_S2BEG;
+	wire [7:0] Tile_X3Y12_S2BEGb;
+	wire [15:0] Tile_X3Y12_S4BEG;
+	wire [15:0] Tile_X3Y12_SS4BEG;
+	wire [3:0] Tile_X3Y12_W1BEG;
+	wire [7:0] Tile_X3Y12_W2BEG;
+	wire [7:0] Tile_X3Y12_W2BEGb;
+	wire [15:0] Tile_X3Y12_WW4BEG;
+	wire [11:0] Tile_X3Y12_W6BEG;
+	wire [3:0] Tile_X4Y12_N1BEG;
+	wire [7:0] Tile_X4Y12_N2BEG;
+	wire [7:0] Tile_X4Y12_N2BEGb;
+	wire [15:0] Tile_X4Y12_N4BEG;
+	wire [15:0] Tile_X4Y12_NN4BEG;
+	wire [9:0] Tile_X4Y12_bot2top;
+	wire [3:0] Tile_X4Y12_E1BEG;
+	wire [7:0] Tile_X4Y12_E2BEG;
+	wire [7:0] Tile_X4Y12_E2BEGb;
+	wire [15:0] Tile_X4Y12_EE4BEG;
+	wire [11:0] Tile_X4Y12_E6BEG;
+	wire [3:0] Tile_X4Y12_S1BEG;
+	wire [7:0] Tile_X4Y12_S2BEG;
+	wire [7:0] Tile_X4Y12_S2BEGb;
+	wire [15:0] Tile_X4Y12_S4BEG;
+	wire [15:0] Tile_X4Y12_SS4BEG;
+	wire [3:0] Tile_X4Y12_W1BEG;
+	wire [7:0] Tile_X4Y12_W2BEG;
+	wire [7:0] Tile_X4Y12_W2BEGb;
+	wire [15:0] Tile_X4Y12_WW4BEG;
+	wire [11:0] Tile_X4Y12_W6BEG;
+	wire [3:0] Tile_X5Y12_N1BEG;
+	wire [7:0] Tile_X5Y12_N2BEG;
+	wire [7:0] Tile_X5Y12_N2BEGb;
+	wire [15:0] Tile_X5Y12_N4BEG;
+	wire [15:0] Tile_X5Y12_NN4BEG;
+	wire [0:0] Tile_X5Y12_Co;
+	wire [3:0] Tile_X5Y12_E1BEG;
+	wire [7:0] Tile_X5Y12_E2BEG;
+	wire [7:0] Tile_X5Y12_E2BEGb;
+	wire [15:0] Tile_X5Y12_EE4BEG;
+	wire [11:0] Tile_X5Y12_E6BEG;
+	wire [3:0] Tile_X5Y12_S1BEG;
+	wire [7:0] Tile_X5Y12_S2BEG;
+	wire [7:0] Tile_X5Y12_S2BEGb;
+	wire [15:0] Tile_X5Y12_S4BEG;
+	wire [15:0] Tile_X5Y12_SS4BEG;
+	wire [3:0] Tile_X5Y12_W1BEG;
+	wire [7:0] Tile_X5Y12_W2BEG;
+	wire [7:0] Tile_X5Y12_W2BEGb;
+	wire [15:0] Tile_X5Y12_WW4BEG;
+	wire [11:0] Tile_X5Y12_W6BEG;
+	wire [3:0] Tile_X6Y12_N1BEG;
+	wire [7:0] Tile_X6Y12_N2BEG;
+	wire [7:0] Tile_X6Y12_N2BEGb;
+	wire [15:0] Tile_X6Y12_N4BEG;
+	wire [15:0] Tile_X6Y12_NN4BEG;
+	wire [0:0] Tile_X6Y12_Co;
+	wire [3:0] Tile_X6Y12_E1BEG;
+	wire [7:0] Tile_X6Y12_E2BEG;
+	wire [7:0] Tile_X6Y12_E2BEGb;
+	wire [15:0] Tile_X6Y12_EE4BEG;
+	wire [11:0] Tile_X6Y12_E6BEG;
+	wire [3:0] Tile_X6Y12_S1BEG;
+	wire [7:0] Tile_X6Y12_S2BEG;
+	wire [7:0] Tile_X6Y12_S2BEGb;
+	wire [15:0] Tile_X6Y12_S4BEG;
+	wire [15:0] Tile_X6Y12_SS4BEG;
+	wire [3:0] Tile_X6Y12_W1BEG;
+	wire [7:0] Tile_X6Y12_W2BEG;
+	wire [7:0] Tile_X6Y12_W2BEGb;
+	wire [15:0] Tile_X6Y12_WW4BEG;
+	wire [11:0] Tile_X6Y12_W6BEG;
+	wire [3:0] Tile_X7Y12_N1BEG;
+	wire [7:0] Tile_X7Y12_N2BEG;
+	wire [7:0] Tile_X7Y12_N2BEGb;
+	wire [15:0] Tile_X7Y12_N4BEG;
+	wire [15:0] Tile_X7Y12_NN4BEG;
+	wire [0:0] Tile_X7Y12_Co;
+	wire [3:0] Tile_X7Y12_E1BEG;
+	wire [7:0] Tile_X7Y12_E2BEG;
+	wire [7:0] Tile_X7Y12_E2BEGb;
+	wire [15:0] Tile_X7Y12_EE4BEG;
+	wire [11:0] Tile_X7Y12_E6BEG;
+	wire [3:0] Tile_X7Y12_S1BEG;
+	wire [7:0] Tile_X7Y12_S2BEG;
+	wire [7:0] Tile_X7Y12_S2BEGb;
+	wire [15:0] Tile_X7Y12_S4BEG;
+	wire [15:0] Tile_X7Y12_SS4BEG;
+	wire [3:0] Tile_X7Y12_W1BEG;
+	wire [7:0] Tile_X7Y12_W2BEG;
+	wire [7:0] Tile_X7Y12_W2BEGb;
+	wire [15:0] Tile_X7Y12_WW4BEG;
+	wire [11:0] Tile_X7Y12_W6BEG;
+	wire [3:0] Tile_X8Y12_N1BEG;
+	wire [7:0] Tile_X8Y12_N2BEG;
+	wire [7:0] Tile_X8Y12_N2BEGb;
+	wire [15:0] Tile_X8Y12_N4BEG;
+	wire [15:0] Tile_X8Y12_NN4BEG;
+	wire [9:0] Tile_X8Y12_bot2top;
+	wire [3:0] Tile_X8Y12_E1BEG;
+	wire [7:0] Tile_X8Y12_E2BEG;
+	wire [7:0] Tile_X8Y12_E2BEGb;
+	wire [15:0] Tile_X8Y12_EE4BEG;
+	wire [11:0] Tile_X8Y12_E6BEG;
+	wire [3:0] Tile_X8Y12_S1BEG;
+	wire [7:0] Tile_X8Y12_S2BEG;
+	wire [7:0] Tile_X8Y12_S2BEGb;
+	wire [15:0] Tile_X8Y12_S4BEG;
+	wire [15:0] Tile_X8Y12_SS4BEG;
+	wire [3:0] Tile_X8Y12_W1BEG;
+	wire [7:0] Tile_X8Y12_W2BEG;
+	wire [7:0] Tile_X8Y12_W2BEGb;
+	wire [15:0] Tile_X8Y12_WW4BEG;
+	wire [11:0] Tile_X8Y12_W6BEG;
+	wire [3:0] Tile_X9Y12_N1BEG;
+	wire [7:0] Tile_X9Y12_N2BEG;
+	wire [7:0] Tile_X9Y12_N2BEGb;
+	wire [15:0] Tile_X9Y12_N4BEG;
+	wire [15:0] Tile_X9Y12_NN4BEG;
+	wire [0:0] Tile_X9Y12_Co;
+	wire [3:0] Tile_X9Y12_E1BEG;
+	wire [7:0] Tile_X9Y12_E2BEG;
+	wire [7:0] Tile_X9Y12_E2BEGb;
+	wire [15:0] Tile_X9Y12_EE4BEG;
+	wire [11:0] Tile_X9Y12_E6BEG;
+	wire [3:0] Tile_X9Y12_S1BEG;
+	wire [7:0] Tile_X9Y12_S2BEG;
+	wire [7:0] Tile_X9Y12_S2BEGb;
+	wire [15:0] Tile_X9Y12_S4BEG;
+	wire [15:0] Tile_X9Y12_SS4BEG;
+	wire [3:0] Tile_X9Y12_W1BEG;
+	wire [7:0] Tile_X9Y12_W2BEG;
+	wire [7:0] Tile_X9Y12_W2BEGb;
+	wire [15:0] Tile_X9Y12_WW4BEG;
+	wire [11:0] Tile_X9Y12_W6BEG;
+	wire [3:0] Tile_X10Y12_N1BEG;
+	wire [7:0] Tile_X10Y12_N2BEG;
+	wire [7:0] Tile_X10Y12_N2BEGb;
+	wire [15:0] Tile_X10Y12_N4BEG;
+	wire [15:0] Tile_X10Y12_NN4BEG;
+	wire [0:0] Tile_X10Y12_Co;
+	wire [3:0] Tile_X10Y12_E1BEG;
+	wire [7:0] Tile_X10Y12_E2BEG;
+	wire [7:0] Tile_X10Y12_E2BEGb;
+	wire [15:0] Tile_X10Y12_EE4BEG;
+	wire [11:0] Tile_X10Y12_E6BEG;
+	wire [3:0] Tile_X10Y12_S1BEG;
+	wire [7:0] Tile_X10Y12_S2BEG;
+	wire [7:0] Tile_X10Y12_S2BEGb;
+	wire [15:0] Tile_X10Y12_S4BEG;
+	wire [15:0] Tile_X10Y12_SS4BEG;
+	wire [3:0] Tile_X10Y12_W1BEG;
+	wire [7:0] Tile_X10Y12_W2BEG;
+	wire [7:0] Tile_X10Y12_W2BEGb;
+	wire [15:0] Tile_X10Y12_WW4BEG;
+	wire [11:0] Tile_X10Y12_W6BEG;
+	wire [3:0] Tile_X11Y12_N1BEG;
+	wire [7:0] Tile_X11Y12_N2BEG;
+	wire [7:0] Tile_X11Y12_N2BEGb;
+	wire [15:0] Tile_X11Y12_N4BEG;
+	wire [15:0] Tile_X11Y12_NN4BEG;
+	wire [0:0] Tile_X11Y12_Co;
+	wire [3:0] Tile_X11Y12_E1BEG;
+	wire [7:0] Tile_X11Y12_E2BEG;
+	wire [7:0] Tile_X11Y12_E2BEGb;
+	wire [15:0] Tile_X11Y12_EE4BEG;
+	wire [11:0] Tile_X11Y12_E6BEG;
+	wire [3:0] Tile_X11Y12_S1BEG;
+	wire [7:0] Tile_X11Y12_S2BEG;
+	wire [7:0] Tile_X11Y12_S2BEGb;
+	wire [15:0] Tile_X11Y12_S4BEG;
+	wire [15:0] Tile_X11Y12_SS4BEG;
+	wire [3:0] Tile_X11Y12_W1BEG;
+	wire [7:0] Tile_X11Y12_W2BEG;
+	wire [7:0] Tile_X11Y12_W2BEGb;
+	wire [15:0] Tile_X11Y12_WW4BEG;
+	wire [11:0] Tile_X11Y12_W6BEG;
+	wire [3:0] Tile_X12Y12_N1BEG;
+	wire [7:0] Tile_X12Y12_N2BEG;
+	wire [7:0] Tile_X12Y12_N2BEGb;
+	wire [15:0] Tile_X12Y12_N4BEG;
+	wire [15:0] Tile_X12Y12_NN4BEG;
+	wire [3:0] Tile_X12Y12_E1BEG;
+	wire [7:0] Tile_X12Y12_E2BEG;
+	wire [7:0] Tile_X12Y12_E2BEGb;
+	wire [15:0] Tile_X12Y12_EE4BEG;
+	wire [11:0] Tile_X12Y12_E6BEG;
+	wire [3:0] Tile_X12Y12_S1BEG;
+	wire [7:0] Tile_X12Y12_S2BEG;
+	wire [7:0] Tile_X12Y12_S2BEGb;
+	wire [15:0] Tile_X12Y12_S4BEG;
+	wire [15:0] Tile_X12Y12_SS4BEG;
+	wire [3:0] Tile_X12Y12_W1BEG;
+	wire [7:0] Tile_X12Y12_W2BEG;
+	wire [7:0] Tile_X12Y12_W2BEGb;
+	wire [15:0] Tile_X12Y12_WW4BEG;
+	wire [11:0] Tile_X12Y12_W6BEG;
+	wire [3:0] Tile_X13Y12_N1BEG;
+	wire [7:0] Tile_X13Y12_N2BEG;
+	wire [7:0] Tile_X13Y12_N2BEGb;
+	wire [15:0] Tile_X13Y12_N4BEG;
+	wire [15:0] Tile_X13Y12_NN4BEG;
+	wire [0:0] Tile_X13Y12_Co;
+	wire [3:0] Tile_X13Y12_E1BEG;
+	wire [7:0] Tile_X13Y12_E2BEG;
+	wire [7:0] Tile_X13Y12_E2BEGb;
+	wire [15:0] Tile_X13Y12_EE4BEG;
+	wire [11:0] Tile_X13Y12_E6BEG;
+	wire [3:0] Tile_X13Y12_S1BEG;
+	wire [7:0] Tile_X13Y12_S2BEG;
+	wire [7:0] Tile_X13Y12_S2BEGb;
+	wire [15:0] Tile_X13Y12_S4BEG;
+	wire [15:0] Tile_X13Y12_SS4BEG;
+	wire [3:0] Tile_X13Y12_W1BEG;
+	wire [7:0] Tile_X13Y12_W2BEG;
+	wire [7:0] Tile_X13Y12_W2BEGb;
+	wire [15:0] Tile_X13Y12_WW4BEG;
+	wire [11:0] Tile_X13Y12_W6BEG;
+	wire [3:0] Tile_X14Y12_N1BEG;
+	wire [7:0] Tile_X14Y12_N2BEG;
+	wire [7:0] Tile_X14Y12_N2BEGb;
+	wire [15:0] Tile_X14Y12_N4BEG;
+	wire [3:0] Tile_X14Y12_S1BEG;
+	wire [7:0] Tile_X14Y12_S2BEG;
+	wire [7:0] Tile_X14Y12_S2BEGb;
+	wire [15:0] Tile_X14Y12_S4BEG;
+	wire [3:0] Tile_X14Y12_W1BEG;
+	wire [7:0] Tile_X14Y12_W2BEG;
+	wire [7:0] Tile_X14Y12_W2BEGb;
+	wire [15:0] Tile_X14Y12_WW4BEG;
+	wire [11:0] Tile_X14Y12_W6BEG;
+	wire [3:0] Tile_X0Y13_E1BEG;
+	wire [7:0] Tile_X0Y13_E2BEG;
+	wire [7:0] Tile_X0Y13_E2BEGb;
+	wire [15:0] Tile_X0Y13_EE4BEG;
+	wire [11:0] Tile_X0Y13_E6BEG;
+	wire [3:0] Tile_X1Y13_N1BEG;
+	wire [7:0] Tile_X1Y13_N2BEG;
+	wire [7:0] Tile_X1Y13_N2BEGb;
+	wire [15:0] Tile_X1Y13_N4BEG;
+	wire [15:0] Tile_X1Y13_NN4BEG;
+	wire [0:0] Tile_X1Y13_Co;
+	wire [3:0] Tile_X1Y13_E1BEG;
+	wire [7:0] Tile_X1Y13_E2BEG;
+	wire [7:0] Tile_X1Y13_E2BEGb;
+	wire [15:0] Tile_X1Y13_EE4BEG;
+	wire [11:0] Tile_X1Y13_E6BEG;
+	wire [3:0] Tile_X1Y13_S1BEG;
+	wire [7:0] Tile_X1Y13_S2BEG;
+	wire [7:0] Tile_X1Y13_S2BEGb;
+	wire [15:0] Tile_X1Y13_S4BEG;
+	wire [15:0] Tile_X1Y13_SS4BEG;
+	wire [3:0] Tile_X1Y13_W1BEG;
+	wire [7:0] Tile_X1Y13_W2BEG;
+	wire [7:0] Tile_X1Y13_W2BEGb;
+	wire [15:0] Tile_X1Y13_WW4BEG;
+	wire [11:0] Tile_X1Y13_W6BEG;
+	wire [3:0] Tile_X2Y13_N1BEG;
+	wire [7:0] Tile_X2Y13_N2BEG;
+	wire [7:0] Tile_X2Y13_N2BEGb;
+	wire [15:0] Tile_X2Y13_N4BEG;
+	wire [15:0] Tile_X2Y13_NN4BEG;
+	wire [3:0] Tile_X2Y13_E1BEG;
+	wire [7:0] Tile_X2Y13_E2BEG;
+	wire [7:0] Tile_X2Y13_E2BEGb;
+	wire [15:0] Tile_X2Y13_EE4BEG;
+	wire [11:0] Tile_X2Y13_E6BEG;
+	wire [3:0] Tile_X2Y13_S1BEG;
+	wire [7:0] Tile_X2Y13_S2BEG;
+	wire [7:0] Tile_X2Y13_S2BEGb;
+	wire [15:0] Tile_X2Y13_S4BEG;
+	wire [15:0] Tile_X2Y13_SS4BEG;
+	wire [3:0] Tile_X2Y13_W1BEG;
+	wire [7:0] Tile_X2Y13_W2BEG;
+	wire [7:0] Tile_X2Y13_W2BEGb;
+	wire [15:0] Tile_X2Y13_WW4BEG;
+	wire [11:0] Tile_X2Y13_W6BEG;
+	wire [3:0] Tile_X3Y13_N1BEG;
+	wire [7:0] Tile_X3Y13_N2BEG;
+	wire [7:0] Tile_X3Y13_N2BEGb;
+	wire [15:0] Tile_X3Y13_N4BEG;
+	wire [15:0] Tile_X3Y13_NN4BEG;
+	wire [0:0] Tile_X3Y13_Co;
+	wire [3:0] Tile_X3Y13_E1BEG;
+	wire [7:0] Tile_X3Y13_E2BEG;
+	wire [7:0] Tile_X3Y13_E2BEGb;
+	wire [15:0] Tile_X3Y13_EE4BEG;
+	wire [11:0] Tile_X3Y13_E6BEG;
+	wire [3:0] Tile_X3Y13_S1BEG;
+	wire [7:0] Tile_X3Y13_S2BEG;
+	wire [7:0] Tile_X3Y13_S2BEGb;
+	wire [15:0] Tile_X3Y13_S4BEG;
+	wire [15:0] Tile_X3Y13_SS4BEG;
+	wire [3:0] Tile_X3Y13_W1BEG;
+	wire [7:0] Tile_X3Y13_W2BEG;
+	wire [7:0] Tile_X3Y13_W2BEGb;
+	wire [15:0] Tile_X3Y13_WW4BEG;
+	wire [11:0] Tile_X3Y13_W6BEG;
+	wire [3:0] Tile_X4Y13_N1BEG;
+	wire [7:0] Tile_X4Y13_N2BEG;
+	wire [7:0] Tile_X4Y13_N2BEGb;
+	wire [15:0] Tile_X4Y13_N4BEG;
+	wire [15:0] Tile_X4Y13_NN4BEG;
+	wire [3:0] Tile_X4Y13_E1BEG;
+	wire [7:0] Tile_X4Y13_E2BEG;
+	wire [7:0] Tile_X4Y13_E2BEGb;
+	wire [15:0] Tile_X4Y13_EE4BEG;
+	wire [11:0] Tile_X4Y13_E6BEG;
+	wire [3:0] Tile_X4Y13_S1BEG;
+	wire [7:0] Tile_X4Y13_S2BEG;
+	wire [7:0] Tile_X4Y13_S2BEGb;
+	wire [15:0] Tile_X4Y13_S4BEG;
+	wire [15:0] Tile_X4Y13_SS4BEG;
+	wire [17:0] Tile_X4Y13_top2bot;
+	wire [3:0] Tile_X4Y13_W1BEG;
+	wire [7:0] Tile_X4Y13_W2BEG;
+	wire [7:0] Tile_X4Y13_W2BEGb;
+	wire [15:0] Tile_X4Y13_WW4BEG;
+	wire [11:0] Tile_X4Y13_W6BEG;
+	wire [3:0] Tile_X5Y13_N1BEG;
+	wire [7:0] Tile_X5Y13_N2BEG;
+	wire [7:0] Tile_X5Y13_N2BEGb;
+	wire [15:0] Tile_X5Y13_N4BEG;
+	wire [15:0] Tile_X5Y13_NN4BEG;
+	wire [0:0] Tile_X5Y13_Co;
+	wire [3:0] Tile_X5Y13_E1BEG;
+	wire [7:0] Tile_X5Y13_E2BEG;
+	wire [7:0] Tile_X5Y13_E2BEGb;
+	wire [15:0] Tile_X5Y13_EE4BEG;
+	wire [11:0] Tile_X5Y13_E6BEG;
+	wire [3:0] Tile_X5Y13_S1BEG;
+	wire [7:0] Tile_X5Y13_S2BEG;
+	wire [7:0] Tile_X5Y13_S2BEGb;
+	wire [15:0] Tile_X5Y13_S4BEG;
+	wire [15:0] Tile_X5Y13_SS4BEG;
+	wire [3:0] Tile_X5Y13_W1BEG;
+	wire [7:0] Tile_X5Y13_W2BEG;
+	wire [7:0] Tile_X5Y13_W2BEGb;
+	wire [15:0] Tile_X5Y13_WW4BEG;
+	wire [11:0] Tile_X5Y13_W6BEG;
+	wire [3:0] Tile_X6Y13_N1BEG;
+	wire [7:0] Tile_X6Y13_N2BEG;
+	wire [7:0] Tile_X6Y13_N2BEGb;
+	wire [15:0] Tile_X6Y13_N4BEG;
+	wire [15:0] Tile_X6Y13_NN4BEG;
+	wire [0:0] Tile_X6Y13_Co;
+	wire [3:0] Tile_X6Y13_E1BEG;
+	wire [7:0] Tile_X6Y13_E2BEG;
+	wire [7:0] Tile_X6Y13_E2BEGb;
+	wire [15:0] Tile_X6Y13_EE4BEG;
+	wire [11:0] Tile_X6Y13_E6BEG;
+	wire [3:0] Tile_X6Y13_S1BEG;
+	wire [7:0] Tile_X6Y13_S2BEG;
+	wire [7:0] Tile_X6Y13_S2BEGb;
+	wire [15:0] Tile_X6Y13_S4BEG;
+	wire [15:0] Tile_X6Y13_SS4BEG;
+	wire [3:0] Tile_X6Y13_W1BEG;
+	wire [7:0] Tile_X6Y13_W2BEG;
+	wire [7:0] Tile_X6Y13_W2BEGb;
+	wire [15:0] Tile_X6Y13_WW4BEG;
+	wire [11:0] Tile_X6Y13_W6BEG;
+	wire [3:0] Tile_X7Y13_N1BEG;
+	wire [7:0] Tile_X7Y13_N2BEG;
+	wire [7:0] Tile_X7Y13_N2BEGb;
+	wire [15:0] Tile_X7Y13_N4BEG;
+	wire [15:0] Tile_X7Y13_NN4BEG;
+	wire [0:0] Tile_X7Y13_Co;
+	wire [3:0] Tile_X7Y13_E1BEG;
+	wire [7:0] Tile_X7Y13_E2BEG;
+	wire [7:0] Tile_X7Y13_E2BEGb;
+	wire [15:0] Tile_X7Y13_EE4BEG;
+	wire [11:0] Tile_X7Y13_E6BEG;
+	wire [3:0] Tile_X7Y13_S1BEG;
+	wire [7:0] Tile_X7Y13_S2BEG;
+	wire [7:0] Tile_X7Y13_S2BEGb;
+	wire [15:0] Tile_X7Y13_S4BEG;
+	wire [15:0] Tile_X7Y13_SS4BEG;
+	wire [3:0] Tile_X7Y13_W1BEG;
+	wire [7:0] Tile_X7Y13_W2BEG;
+	wire [7:0] Tile_X7Y13_W2BEGb;
+	wire [15:0] Tile_X7Y13_WW4BEG;
+	wire [11:0] Tile_X7Y13_W6BEG;
+	wire [3:0] Tile_X8Y13_N1BEG;
+	wire [7:0] Tile_X8Y13_N2BEG;
+	wire [7:0] Tile_X8Y13_N2BEGb;
+	wire [15:0] Tile_X8Y13_N4BEG;
+	wire [15:0] Tile_X8Y13_NN4BEG;
+	wire [3:0] Tile_X8Y13_E1BEG;
+	wire [7:0] Tile_X8Y13_E2BEG;
+	wire [7:0] Tile_X8Y13_E2BEGb;
+	wire [15:0] Tile_X8Y13_EE4BEG;
+	wire [11:0] Tile_X8Y13_E6BEG;
+	wire [3:0] Tile_X8Y13_S1BEG;
+	wire [7:0] Tile_X8Y13_S2BEG;
+	wire [7:0] Tile_X8Y13_S2BEGb;
+	wire [15:0] Tile_X8Y13_S4BEG;
+	wire [15:0] Tile_X8Y13_SS4BEG;
+	wire [17:0] Tile_X8Y13_top2bot;
+	wire [3:0] Tile_X8Y13_W1BEG;
+	wire [7:0] Tile_X8Y13_W2BEG;
+	wire [7:0] Tile_X8Y13_W2BEGb;
+	wire [15:0] Tile_X8Y13_WW4BEG;
+	wire [11:0] Tile_X8Y13_W6BEG;
+	wire [3:0] Tile_X9Y13_N1BEG;
+	wire [7:0] Tile_X9Y13_N2BEG;
+	wire [7:0] Tile_X9Y13_N2BEGb;
+	wire [15:0] Tile_X9Y13_N4BEG;
+	wire [15:0] Tile_X9Y13_NN4BEG;
+	wire [0:0] Tile_X9Y13_Co;
+	wire [3:0] Tile_X9Y13_E1BEG;
+	wire [7:0] Tile_X9Y13_E2BEG;
+	wire [7:0] Tile_X9Y13_E2BEGb;
+	wire [15:0] Tile_X9Y13_EE4BEG;
+	wire [11:0] Tile_X9Y13_E6BEG;
+	wire [3:0] Tile_X9Y13_S1BEG;
+	wire [7:0] Tile_X9Y13_S2BEG;
+	wire [7:0] Tile_X9Y13_S2BEGb;
+	wire [15:0] Tile_X9Y13_S4BEG;
+	wire [15:0] Tile_X9Y13_SS4BEG;
+	wire [3:0] Tile_X9Y13_W1BEG;
+	wire [7:0] Tile_X9Y13_W2BEG;
+	wire [7:0] Tile_X9Y13_W2BEGb;
+	wire [15:0] Tile_X9Y13_WW4BEG;
+	wire [11:0] Tile_X9Y13_W6BEG;
+	wire [3:0] Tile_X10Y13_N1BEG;
+	wire [7:0] Tile_X10Y13_N2BEG;
+	wire [7:0] Tile_X10Y13_N2BEGb;
+	wire [15:0] Tile_X10Y13_N4BEG;
+	wire [15:0] Tile_X10Y13_NN4BEG;
+	wire [0:0] Tile_X10Y13_Co;
+	wire [3:0] Tile_X10Y13_E1BEG;
+	wire [7:0] Tile_X10Y13_E2BEG;
+	wire [7:0] Tile_X10Y13_E2BEGb;
+	wire [15:0] Tile_X10Y13_EE4BEG;
+	wire [11:0] Tile_X10Y13_E6BEG;
+	wire [3:0] Tile_X10Y13_S1BEG;
+	wire [7:0] Tile_X10Y13_S2BEG;
+	wire [7:0] Tile_X10Y13_S2BEGb;
+	wire [15:0] Tile_X10Y13_S4BEG;
+	wire [15:0] Tile_X10Y13_SS4BEG;
+	wire [3:0] Tile_X10Y13_W1BEG;
+	wire [7:0] Tile_X10Y13_W2BEG;
+	wire [7:0] Tile_X10Y13_W2BEGb;
+	wire [15:0] Tile_X10Y13_WW4BEG;
+	wire [11:0] Tile_X10Y13_W6BEG;
+	wire [3:0] Tile_X11Y13_N1BEG;
+	wire [7:0] Tile_X11Y13_N2BEG;
+	wire [7:0] Tile_X11Y13_N2BEGb;
+	wire [15:0] Tile_X11Y13_N4BEG;
+	wire [15:0] Tile_X11Y13_NN4BEG;
+	wire [0:0] Tile_X11Y13_Co;
+	wire [3:0] Tile_X11Y13_E1BEG;
+	wire [7:0] Tile_X11Y13_E2BEG;
+	wire [7:0] Tile_X11Y13_E2BEGb;
+	wire [15:0] Tile_X11Y13_EE4BEG;
+	wire [11:0] Tile_X11Y13_E6BEG;
+	wire [3:0] Tile_X11Y13_S1BEG;
+	wire [7:0] Tile_X11Y13_S2BEG;
+	wire [7:0] Tile_X11Y13_S2BEGb;
+	wire [15:0] Tile_X11Y13_S4BEG;
+	wire [15:0] Tile_X11Y13_SS4BEG;
+	wire [3:0] Tile_X11Y13_W1BEG;
+	wire [7:0] Tile_X11Y13_W2BEG;
+	wire [7:0] Tile_X11Y13_W2BEGb;
+	wire [15:0] Tile_X11Y13_WW4BEG;
+	wire [11:0] Tile_X11Y13_W6BEG;
+	wire [3:0] Tile_X12Y13_N1BEG;
+	wire [7:0] Tile_X12Y13_N2BEG;
+	wire [7:0] Tile_X12Y13_N2BEGb;
+	wire [15:0] Tile_X12Y13_N4BEG;
+	wire [15:0] Tile_X12Y13_NN4BEG;
+	wire [3:0] Tile_X12Y13_E1BEG;
+	wire [7:0] Tile_X12Y13_E2BEG;
+	wire [7:0] Tile_X12Y13_E2BEGb;
+	wire [15:0] Tile_X12Y13_EE4BEG;
+	wire [11:0] Tile_X12Y13_E6BEG;
+	wire [3:0] Tile_X12Y13_S1BEG;
+	wire [7:0] Tile_X12Y13_S2BEG;
+	wire [7:0] Tile_X12Y13_S2BEGb;
+	wire [15:0] Tile_X12Y13_S4BEG;
+	wire [15:0] Tile_X12Y13_SS4BEG;
+	wire [3:0] Tile_X12Y13_W1BEG;
+	wire [7:0] Tile_X12Y13_W2BEG;
+	wire [7:0] Tile_X12Y13_W2BEGb;
+	wire [15:0] Tile_X12Y13_WW4BEG;
+	wire [11:0] Tile_X12Y13_W6BEG;
+	wire [3:0] Tile_X13Y13_N1BEG;
+	wire [7:0] Tile_X13Y13_N2BEG;
+	wire [7:0] Tile_X13Y13_N2BEGb;
+	wire [15:0] Tile_X13Y13_N4BEG;
+	wire [15:0] Tile_X13Y13_NN4BEG;
+	wire [0:0] Tile_X13Y13_Co;
+	wire [3:0] Tile_X13Y13_E1BEG;
+	wire [7:0] Tile_X13Y13_E2BEG;
+	wire [7:0] Tile_X13Y13_E2BEGb;
+	wire [15:0] Tile_X13Y13_EE4BEG;
+	wire [11:0] Tile_X13Y13_E6BEG;
+	wire [3:0] Tile_X13Y13_S1BEG;
+	wire [7:0] Tile_X13Y13_S2BEG;
+	wire [7:0] Tile_X13Y13_S2BEGb;
+	wire [15:0] Tile_X13Y13_S4BEG;
+	wire [15:0] Tile_X13Y13_SS4BEG;
+	wire [3:0] Tile_X13Y13_W1BEG;
+	wire [7:0] Tile_X13Y13_W2BEG;
+	wire [7:0] Tile_X13Y13_W2BEGb;
+	wire [15:0] Tile_X13Y13_WW4BEG;
+	wire [11:0] Tile_X13Y13_W6BEG;
+	wire [3:0] Tile_X14Y13_N1BEG;
+	wire [7:0] Tile_X14Y13_N2BEG;
+	wire [7:0] Tile_X14Y13_N2BEGb;
+	wire [15:0] Tile_X14Y13_N4BEG;
+	wire [3:0] Tile_X14Y13_S1BEG;
+	wire [7:0] Tile_X14Y13_S2BEG;
+	wire [7:0] Tile_X14Y13_S2BEGb;
+	wire [15:0] Tile_X14Y13_S4BEG;
+	wire [3:0] Tile_X14Y13_W1BEG;
+	wire [7:0] Tile_X14Y13_W2BEG;
+	wire [7:0] Tile_X14Y13_W2BEGb;
+	wire [15:0] Tile_X14Y13_WW4BEG;
+	wire [11:0] Tile_X14Y13_W6BEG;
+	wire [3:0] Tile_X0Y14_E1BEG;
+	wire [7:0] Tile_X0Y14_E2BEG;
+	wire [7:0] Tile_X0Y14_E2BEGb;
+	wire [15:0] Tile_X0Y14_EE4BEG;
+	wire [11:0] Tile_X0Y14_E6BEG;
+	wire [3:0] Tile_X1Y14_N1BEG;
+	wire [7:0] Tile_X1Y14_N2BEG;
+	wire [7:0] Tile_X1Y14_N2BEGb;
+	wire [15:0] Tile_X1Y14_N4BEG;
+	wire [15:0] Tile_X1Y14_NN4BEG;
+	wire [0:0] Tile_X1Y14_Co;
+	wire [3:0] Tile_X1Y14_E1BEG;
+	wire [7:0] Tile_X1Y14_E2BEG;
+	wire [7:0] Tile_X1Y14_E2BEGb;
+	wire [15:0] Tile_X1Y14_EE4BEG;
+	wire [11:0] Tile_X1Y14_E6BEG;
+	wire [3:0] Tile_X1Y14_S1BEG;
+	wire [7:0] Tile_X1Y14_S2BEG;
+	wire [7:0] Tile_X1Y14_S2BEGb;
+	wire [15:0] Tile_X1Y14_S4BEG;
+	wire [15:0] Tile_X1Y14_SS4BEG;
+	wire [3:0] Tile_X1Y14_W1BEG;
+	wire [7:0] Tile_X1Y14_W2BEG;
+	wire [7:0] Tile_X1Y14_W2BEGb;
+	wire [15:0] Tile_X1Y14_WW4BEG;
+	wire [11:0] Tile_X1Y14_W6BEG;
+	wire [3:0] Tile_X2Y14_N1BEG;
+	wire [7:0] Tile_X2Y14_N2BEG;
+	wire [7:0] Tile_X2Y14_N2BEGb;
+	wire [15:0] Tile_X2Y14_N4BEG;
+	wire [15:0] Tile_X2Y14_NN4BEG;
+	wire [3:0] Tile_X2Y14_E1BEG;
+	wire [7:0] Tile_X2Y14_E2BEG;
+	wire [7:0] Tile_X2Y14_E2BEGb;
+	wire [15:0] Tile_X2Y14_EE4BEG;
+	wire [11:0] Tile_X2Y14_E6BEG;
+	wire [3:0] Tile_X2Y14_S1BEG;
+	wire [7:0] Tile_X2Y14_S2BEG;
+	wire [7:0] Tile_X2Y14_S2BEGb;
+	wire [15:0] Tile_X2Y14_S4BEG;
+	wire [15:0] Tile_X2Y14_SS4BEG;
+	wire [3:0] Tile_X2Y14_W1BEG;
+	wire [7:0] Tile_X2Y14_W2BEG;
+	wire [7:0] Tile_X2Y14_W2BEGb;
+	wire [15:0] Tile_X2Y14_WW4BEG;
+	wire [11:0] Tile_X2Y14_W6BEG;
+	wire [3:0] Tile_X3Y14_N1BEG;
+	wire [7:0] Tile_X3Y14_N2BEG;
+	wire [7:0] Tile_X3Y14_N2BEGb;
+	wire [15:0] Tile_X3Y14_N4BEG;
+	wire [15:0] Tile_X3Y14_NN4BEG;
+	wire [0:0] Tile_X3Y14_Co;
+	wire [3:0] Tile_X3Y14_E1BEG;
+	wire [7:0] Tile_X3Y14_E2BEG;
+	wire [7:0] Tile_X3Y14_E2BEGb;
+	wire [15:0] Tile_X3Y14_EE4BEG;
+	wire [11:0] Tile_X3Y14_E6BEG;
+	wire [3:0] Tile_X3Y14_S1BEG;
+	wire [7:0] Tile_X3Y14_S2BEG;
+	wire [7:0] Tile_X3Y14_S2BEGb;
+	wire [15:0] Tile_X3Y14_S4BEG;
+	wire [15:0] Tile_X3Y14_SS4BEG;
+	wire [3:0] Tile_X3Y14_W1BEG;
+	wire [7:0] Tile_X3Y14_W2BEG;
+	wire [7:0] Tile_X3Y14_W2BEGb;
+	wire [15:0] Tile_X3Y14_WW4BEG;
+	wire [11:0] Tile_X3Y14_W6BEG;
+	wire [3:0] Tile_X4Y14_N1BEG;
+	wire [7:0] Tile_X4Y14_N2BEG;
+	wire [7:0] Tile_X4Y14_N2BEGb;
+	wire [15:0] Tile_X4Y14_N4BEG;
+	wire [15:0] Tile_X4Y14_NN4BEG;
+	wire [9:0] Tile_X4Y14_bot2top;
+	wire [3:0] Tile_X4Y14_E1BEG;
+	wire [7:0] Tile_X4Y14_E2BEG;
+	wire [7:0] Tile_X4Y14_E2BEGb;
+	wire [15:0] Tile_X4Y14_EE4BEG;
+	wire [11:0] Tile_X4Y14_E6BEG;
+	wire [3:0] Tile_X4Y14_S1BEG;
+	wire [7:0] Tile_X4Y14_S2BEG;
+	wire [7:0] Tile_X4Y14_S2BEGb;
+	wire [15:0] Tile_X4Y14_S4BEG;
+	wire [15:0] Tile_X4Y14_SS4BEG;
+	wire [3:0] Tile_X4Y14_W1BEG;
+	wire [7:0] Tile_X4Y14_W2BEG;
+	wire [7:0] Tile_X4Y14_W2BEGb;
+	wire [15:0] Tile_X4Y14_WW4BEG;
+	wire [11:0] Tile_X4Y14_W6BEG;
+	wire [3:0] Tile_X5Y14_N1BEG;
+	wire [7:0] Tile_X5Y14_N2BEG;
+	wire [7:0] Tile_X5Y14_N2BEGb;
+	wire [15:0] Tile_X5Y14_N4BEG;
+	wire [15:0] Tile_X5Y14_NN4BEG;
+	wire [0:0] Tile_X5Y14_Co;
+	wire [3:0] Tile_X5Y14_E1BEG;
+	wire [7:0] Tile_X5Y14_E2BEG;
+	wire [7:0] Tile_X5Y14_E2BEGb;
+	wire [15:0] Tile_X5Y14_EE4BEG;
+	wire [11:0] Tile_X5Y14_E6BEG;
+	wire [3:0] Tile_X5Y14_S1BEG;
+	wire [7:0] Tile_X5Y14_S2BEG;
+	wire [7:0] Tile_X5Y14_S2BEGb;
+	wire [15:0] Tile_X5Y14_S4BEG;
+	wire [15:0] Tile_X5Y14_SS4BEG;
+	wire [3:0] Tile_X5Y14_W1BEG;
+	wire [7:0] Tile_X5Y14_W2BEG;
+	wire [7:0] Tile_X5Y14_W2BEGb;
+	wire [15:0] Tile_X5Y14_WW4BEG;
+	wire [11:0] Tile_X5Y14_W6BEG;
+	wire [3:0] Tile_X6Y14_N1BEG;
+	wire [7:0] Tile_X6Y14_N2BEG;
+	wire [7:0] Tile_X6Y14_N2BEGb;
+	wire [15:0] Tile_X6Y14_N4BEG;
+	wire [15:0] Tile_X6Y14_NN4BEG;
+	wire [0:0] Tile_X6Y14_Co;
+	wire [3:0] Tile_X6Y14_E1BEG;
+	wire [7:0] Tile_X6Y14_E2BEG;
+	wire [7:0] Tile_X6Y14_E2BEGb;
+	wire [15:0] Tile_X6Y14_EE4BEG;
+	wire [11:0] Tile_X6Y14_E6BEG;
+	wire [3:0] Tile_X6Y14_S1BEG;
+	wire [7:0] Tile_X6Y14_S2BEG;
+	wire [7:0] Tile_X6Y14_S2BEGb;
+	wire [15:0] Tile_X6Y14_S4BEG;
+	wire [15:0] Tile_X6Y14_SS4BEG;
+	wire [3:0] Tile_X6Y14_W1BEG;
+	wire [7:0] Tile_X6Y14_W2BEG;
+	wire [7:0] Tile_X6Y14_W2BEGb;
+	wire [15:0] Tile_X6Y14_WW4BEG;
+	wire [11:0] Tile_X6Y14_W6BEG;
+	wire [3:0] Tile_X7Y14_N1BEG;
+	wire [7:0] Tile_X7Y14_N2BEG;
+	wire [7:0] Tile_X7Y14_N2BEGb;
+	wire [15:0] Tile_X7Y14_N4BEG;
+	wire [15:0] Tile_X7Y14_NN4BEG;
+	wire [0:0] Tile_X7Y14_Co;
+	wire [3:0] Tile_X7Y14_E1BEG;
+	wire [7:0] Tile_X7Y14_E2BEG;
+	wire [7:0] Tile_X7Y14_E2BEGb;
+	wire [15:0] Tile_X7Y14_EE4BEG;
+	wire [11:0] Tile_X7Y14_E6BEG;
+	wire [3:0] Tile_X7Y14_S1BEG;
+	wire [7:0] Tile_X7Y14_S2BEG;
+	wire [7:0] Tile_X7Y14_S2BEGb;
+	wire [15:0] Tile_X7Y14_S4BEG;
+	wire [15:0] Tile_X7Y14_SS4BEG;
+	wire [3:0] Tile_X7Y14_W1BEG;
+	wire [7:0] Tile_X7Y14_W2BEG;
+	wire [7:0] Tile_X7Y14_W2BEGb;
+	wire [15:0] Tile_X7Y14_WW4BEG;
+	wire [11:0] Tile_X7Y14_W6BEG;
+	wire [3:0] Tile_X8Y14_N1BEG;
+	wire [7:0] Tile_X8Y14_N2BEG;
+	wire [7:0] Tile_X8Y14_N2BEGb;
+	wire [15:0] Tile_X8Y14_N4BEG;
+	wire [15:0] Tile_X8Y14_NN4BEG;
+	wire [9:0] Tile_X8Y14_bot2top;
+	wire [3:0] Tile_X8Y14_E1BEG;
+	wire [7:0] Tile_X8Y14_E2BEG;
+	wire [7:0] Tile_X8Y14_E2BEGb;
+	wire [15:0] Tile_X8Y14_EE4BEG;
+	wire [11:0] Tile_X8Y14_E6BEG;
+	wire [3:0] Tile_X8Y14_S1BEG;
+	wire [7:0] Tile_X8Y14_S2BEG;
+	wire [7:0] Tile_X8Y14_S2BEGb;
+	wire [15:0] Tile_X8Y14_S4BEG;
+	wire [15:0] Tile_X8Y14_SS4BEG;
+	wire [3:0] Tile_X8Y14_W1BEG;
+	wire [7:0] Tile_X8Y14_W2BEG;
+	wire [7:0] Tile_X8Y14_W2BEGb;
+	wire [15:0] Tile_X8Y14_WW4BEG;
+	wire [11:0] Tile_X8Y14_W6BEG;
+	wire [3:0] Tile_X9Y14_N1BEG;
+	wire [7:0] Tile_X9Y14_N2BEG;
+	wire [7:0] Tile_X9Y14_N2BEGb;
+	wire [15:0] Tile_X9Y14_N4BEG;
+	wire [15:0] Tile_X9Y14_NN4BEG;
+	wire [0:0] Tile_X9Y14_Co;
+	wire [3:0] Tile_X9Y14_E1BEG;
+	wire [7:0] Tile_X9Y14_E2BEG;
+	wire [7:0] Tile_X9Y14_E2BEGb;
+	wire [15:0] Tile_X9Y14_EE4BEG;
+	wire [11:0] Tile_X9Y14_E6BEG;
+	wire [3:0] Tile_X9Y14_S1BEG;
+	wire [7:0] Tile_X9Y14_S2BEG;
+	wire [7:0] Tile_X9Y14_S2BEGb;
+	wire [15:0] Tile_X9Y14_S4BEG;
+	wire [15:0] Tile_X9Y14_SS4BEG;
+	wire [3:0] Tile_X9Y14_W1BEG;
+	wire [7:0] Tile_X9Y14_W2BEG;
+	wire [7:0] Tile_X9Y14_W2BEGb;
+	wire [15:0] Tile_X9Y14_WW4BEG;
+	wire [11:0] Tile_X9Y14_W6BEG;
+	wire [3:0] Tile_X10Y14_N1BEG;
+	wire [7:0] Tile_X10Y14_N2BEG;
+	wire [7:0] Tile_X10Y14_N2BEGb;
+	wire [15:0] Tile_X10Y14_N4BEG;
+	wire [15:0] Tile_X10Y14_NN4BEG;
+	wire [0:0] Tile_X10Y14_Co;
+	wire [3:0] Tile_X10Y14_E1BEG;
+	wire [7:0] Tile_X10Y14_E2BEG;
+	wire [7:0] Tile_X10Y14_E2BEGb;
+	wire [15:0] Tile_X10Y14_EE4BEG;
+	wire [11:0] Tile_X10Y14_E6BEG;
+	wire [3:0] Tile_X10Y14_S1BEG;
+	wire [7:0] Tile_X10Y14_S2BEG;
+	wire [7:0] Tile_X10Y14_S2BEGb;
+	wire [15:0] Tile_X10Y14_S4BEG;
+	wire [15:0] Tile_X10Y14_SS4BEG;
+	wire [3:0] Tile_X10Y14_W1BEG;
+	wire [7:0] Tile_X10Y14_W2BEG;
+	wire [7:0] Tile_X10Y14_W2BEGb;
+	wire [15:0] Tile_X10Y14_WW4BEG;
+	wire [11:0] Tile_X10Y14_W6BEG;
+	wire [3:0] Tile_X11Y14_N1BEG;
+	wire [7:0] Tile_X11Y14_N2BEG;
+	wire [7:0] Tile_X11Y14_N2BEGb;
+	wire [15:0] Tile_X11Y14_N4BEG;
+	wire [15:0] Tile_X11Y14_NN4BEG;
+	wire [0:0] Tile_X11Y14_Co;
+	wire [3:0] Tile_X11Y14_E1BEG;
+	wire [7:0] Tile_X11Y14_E2BEG;
+	wire [7:0] Tile_X11Y14_E2BEGb;
+	wire [15:0] Tile_X11Y14_EE4BEG;
+	wire [11:0] Tile_X11Y14_E6BEG;
+	wire [3:0] Tile_X11Y14_S1BEG;
+	wire [7:0] Tile_X11Y14_S2BEG;
+	wire [7:0] Tile_X11Y14_S2BEGb;
+	wire [15:0] Tile_X11Y14_S4BEG;
+	wire [15:0] Tile_X11Y14_SS4BEG;
+	wire [3:0] Tile_X11Y14_W1BEG;
+	wire [7:0] Tile_X11Y14_W2BEG;
+	wire [7:0] Tile_X11Y14_W2BEGb;
+	wire [15:0] Tile_X11Y14_WW4BEG;
+	wire [11:0] Tile_X11Y14_W6BEG;
+	wire [3:0] Tile_X12Y14_N1BEG;
+	wire [7:0] Tile_X12Y14_N2BEG;
+	wire [7:0] Tile_X12Y14_N2BEGb;
+	wire [15:0] Tile_X12Y14_N4BEG;
+	wire [15:0] Tile_X12Y14_NN4BEG;
+	wire [3:0] Tile_X12Y14_E1BEG;
+	wire [7:0] Tile_X12Y14_E2BEG;
+	wire [7:0] Tile_X12Y14_E2BEGb;
+	wire [15:0] Tile_X12Y14_EE4BEG;
+	wire [11:0] Tile_X12Y14_E6BEG;
+	wire [3:0] Tile_X12Y14_S1BEG;
+	wire [7:0] Tile_X12Y14_S2BEG;
+	wire [7:0] Tile_X12Y14_S2BEGb;
+	wire [15:0] Tile_X12Y14_S4BEG;
+	wire [15:0] Tile_X12Y14_SS4BEG;
+	wire [3:0] Tile_X12Y14_W1BEG;
+	wire [7:0] Tile_X12Y14_W2BEG;
+	wire [7:0] Tile_X12Y14_W2BEGb;
+	wire [15:0] Tile_X12Y14_WW4BEG;
+	wire [11:0] Tile_X12Y14_W6BEG;
+	wire [3:0] Tile_X13Y14_N1BEG;
+	wire [7:0] Tile_X13Y14_N2BEG;
+	wire [7:0] Tile_X13Y14_N2BEGb;
+	wire [15:0] Tile_X13Y14_N4BEG;
+	wire [15:0] Tile_X13Y14_NN4BEG;
+	wire [0:0] Tile_X13Y14_Co;
+	wire [3:0] Tile_X13Y14_E1BEG;
+	wire [7:0] Tile_X13Y14_E2BEG;
+	wire [7:0] Tile_X13Y14_E2BEGb;
+	wire [15:0] Tile_X13Y14_EE4BEG;
+	wire [11:0] Tile_X13Y14_E6BEG;
+	wire [3:0] Tile_X13Y14_S1BEG;
+	wire [7:0] Tile_X13Y14_S2BEG;
+	wire [7:0] Tile_X13Y14_S2BEGb;
+	wire [15:0] Tile_X13Y14_S4BEG;
+	wire [15:0] Tile_X13Y14_SS4BEG;
+	wire [3:0] Tile_X13Y14_W1BEG;
+	wire [7:0] Tile_X13Y14_W2BEG;
+	wire [7:0] Tile_X13Y14_W2BEGb;
+	wire [15:0] Tile_X13Y14_WW4BEG;
+	wire [11:0] Tile_X13Y14_W6BEG;
+	wire [3:0] Tile_X14Y14_N1BEG;
+	wire [7:0] Tile_X14Y14_N2BEG;
+	wire [7:0] Tile_X14Y14_N2BEGb;
+	wire [15:0] Tile_X14Y14_N4BEG;
+	wire [3:0] Tile_X14Y14_S1BEG;
+	wire [7:0] Tile_X14Y14_S2BEG;
+	wire [7:0] Tile_X14Y14_S2BEGb;
+	wire [15:0] Tile_X14Y14_S4BEG;
+	wire [3:0] Tile_X14Y14_W1BEG;
+	wire [7:0] Tile_X14Y14_W2BEG;
+	wire [7:0] Tile_X14Y14_W2BEGb;
+	wire [15:0] Tile_X14Y14_WW4BEG;
+	wire [11:0] Tile_X14Y14_W6BEG;
+	wire [3:0] Tile_X1Y15_N1BEG;
+	wire [7:0] Tile_X1Y15_N2BEG;
+	wire [7:0] Tile_X1Y15_N2BEGb;
+	wire [15:0] Tile_X1Y15_N4BEG;
+	wire [15:0] Tile_X1Y15_NN4BEG;
+	wire [0:0] Tile_X1Y15_Co;
+	wire [3:0] Tile_X2Y15_N1BEG;
+	wire [7:0] Tile_X2Y15_N2BEG;
+	wire [7:0] Tile_X2Y15_N2BEGb;
+	wire [15:0] Tile_X2Y15_N4BEG;
+	wire [15:0] Tile_X2Y15_NN4BEG;
+	wire [3:0] Tile_X3Y15_N1BEG;
+	wire [7:0] Tile_X3Y15_N2BEG;
+	wire [7:0] Tile_X3Y15_N2BEGb;
+	wire [15:0] Tile_X3Y15_N4BEG;
+	wire [15:0] Tile_X3Y15_NN4BEG;
+	wire [0:0] Tile_X3Y15_Co;
+	wire [3:0] Tile_X4Y15_N1BEG;
+	wire [7:0] Tile_X4Y15_N2BEG;
+	wire [7:0] Tile_X4Y15_N2BEGb;
+	wire [15:0] Tile_X4Y15_N4BEG;
+	wire [15:0] Tile_X4Y15_NN4BEG;
+	wire [3:0] Tile_X5Y15_N1BEG;
+	wire [7:0] Tile_X5Y15_N2BEG;
+	wire [7:0] Tile_X5Y15_N2BEGb;
+	wire [15:0] Tile_X5Y15_N4BEG;
+	wire [15:0] Tile_X5Y15_NN4BEG;
+	wire [0:0] Tile_X5Y15_Co;
+	wire [3:0] Tile_X6Y15_N1BEG;
+	wire [7:0] Tile_X6Y15_N2BEG;
+	wire [7:0] Tile_X6Y15_N2BEGb;
+	wire [15:0] Tile_X6Y15_N4BEG;
+	wire [15:0] Tile_X6Y15_NN4BEG;
+	wire [0:0] Tile_X6Y15_Co;
+	wire [3:0] Tile_X7Y15_N1BEG;
+	wire [7:0] Tile_X7Y15_N2BEG;
+	wire [7:0] Tile_X7Y15_N2BEGb;
+	wire [15:0] Tile_X7Y15_N4BEG;
+	wire [15:0] Tile_X7Y15_NN4BEG;
+	wire [0:0] Tile_X7Y15_Co;
+	wire [3:0] Tile_X8Y15_N1BEG;
+	wire [7:0] Tile_X8Y15_N2BEG;
+	wire [7:0] Tile_X8Y15_N2BEGb;
+	wire [15:0] Tile_X8Y15_N4BEG;
+	wire [15:0] Tile_X8Y15_NN4BEG;
+	wire [3:0] Tile_X9Y15_N1BEG;
+	wire [7:0] Tile_X9Y15_N2BEG;
+	wire [7:0] Tile_X9Y15_N2BEGb;
+	wire [15:0] Tile_X9Y15_N4BEG;
+	wire [15:0] Tile_X9Y15_NN4BEG;
+	wire [0:0] Tile_X9Y15_Co;
+	wire [3:0] Tile_X10Y15_N1BEG;
+	wire [7:0] Tile_X10Y15_N2BEG;
+	wire [7:0] Tile_X10Y15_N2BEGb;
+	wire [15:0] Tile_X10Y15_N4BEG;
+	wire [15:0] Tile_X10Y15_NN4BEG;
+	wire [0:0] Tile_X10Y15_Co;
+	wire [3:0] Tile_X11Y15_N1BEG;
+	wire [7:0] Tile_X11Y15_N2BEG;
+	wire [7:0] Tile_X11Y15_N2BEGb;
+	wire [15:0] Tile_X11Y15_N4BEG;
+	wire [15:0] Tile_X11Y15_NN4BEG;
+	wire [0:0] Tile_X11Y15_Co;
+	wire [3:0] Tile_X12Y15_N1BEG;
+	wire [7:0] Tile_X12Y15_N2BEG;
+	wire [7:0] Tile_X12Y15_N2BEGb;
+	wire [15:0] Tile_X12Y15_N4BEG;
+	wire [15:0] Tile_X12Y15_NN4BEG;
+	wire [3:0] Tile_X13Y15_N1BEG;
+	wire [7:0] Tile_X13Y15_N2BEG;
+	wire [7:0] Tile_X13Y15_N2BEGb;
+	wire [15:0] Tile_X13Y15_N4BEG;
+	wire [15:0] Tile_X13Y15_NN4BEG;
+	wire [0:0] Tile_X13Y15_Co;
+	wire [3:0] Tile_X14Y15_N1BEG;
+	wire [7:0] Tile_X14Y15_N2BEG;
+	wire [7:0] Tile_X14Y15_N2BEGb;
+	wire [15:0] Tile_X14Y15_N4BEG;
+
+	assign Tile_Y1_FrameData = FrameData[(FrameBitsPerRow*(1+1))-1:FrameBitsPerRow*1];
+	assign Tile_Y2_FrameData = FrameData[(FrameBitsPerRow*(2+1))-1:FrameBitsPerRow*2];
+	assign Tile_Y3_FrameData = FrameData[(FrameBitsPerRow*(3+1))-1:FrameBitsPerRow*3];
+	assign Tile_Y4_FrameData = FrameData[(FrameBitsPerRow*(4+1))-1:FrameBitsPerRow*4];
+	assign Tile_Y5_FrameData = FrameData[(FrameBitsPerRow*(5+1))-1:FrameBitsPerRow*5];
+	assign Tile_Y6_FrameData = FrameData[(FrameBitsPerRow*(6+1))-1:FrameBitsPerRow*6];
+	assign Tile_Y7_FrameData = FrameData[(FrameBitsPerRow*(7+1))-1:FrameBitsPerRow*7];
+	assign Tile_Y8_FrameData = FrameData[(FrameBitsPerRow*(8+1))-1:FrameBitsPerRow*8];
+	assign Tile_Y9_FrameData = FrameData[(FrameBitsPerRow*(9+1))-1:FrameBitsPerRow*9];
+	assign Tile_Y10_FrameData = FrameData[(FrameBitsPerRow*(10+1))-1:FrameBitsPerRow*10];
+	assign Tile_Y11_FrameData = FrameData[(FrameBitsPerRow*(11+1))-1:FrameBitsPerRow*11];
+	assign Tile_Y12_FrameData = FrameData[(FrameBitsPerRow*(12+1))-1:FrameBitsPerRow*12];
+	assign Tile_Y13_FrameData = FrameData[(FrameBitsPerRow*(13+1))-1:FrameBitsPerRow*13];
+	assign Tile_Y14_FrameData = FrameData[(FrameBitsPerRow*(14+1))-1:FrameBitsPerRow*14];
+	assign Tile_X0_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(0+1))-1:MaxFramesPerCol*0];
+	assign Tile_X1_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(1+1))-1:MaxFramesPerCol*1];
+	assign Tile_X2_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(2+1))-1:MaxFramesPerCol*2];
+	assign Tile_X3_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(3+1))-1:MaxFramesPerCol*3];
+	assign Tile_X4_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(4+1))-1:MaxFramesPerCol*4];
+	assign Tile_X5_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(5+1))-1:MaxFramesPerCol*5];
+	assign Tile_X6_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(6+1))-1:MaxFramesPerCol*6];
+	assign Tile_X7_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(7+1))-1:MaxFramesPerCol*7];
+	assign Tile_X8_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(8+1))-1:MaxFramesPerCol*8];
+	assign Tile_X9_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(9+1))-1:MaxFramesPerCol*9];
+	assign Tile_X10_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(10+1))-1:MaxFramesPerCol*10];
+	assign Tile_X11_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(11+1))-1:MaxFramesPerCol*11];
+	assign Tile_X12_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(12+1))-1:MaxFramesPerCol*12];
+	assign Tile_X13_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(13+1))-1:MaxFramesPerCol*13];
+	assign Tile_X14_FrameStrobe = FrameStrobe[(MaxFramesPerCol*(14+1))-1:MaxFramesPerCol*14];
+
+//tile instantiations
+
+	N_term_DSP Tile_X4Y0_N_term_DSP (
+	.N1END(Tile_X4Y1_N1BEG[3:0]),
+	.N2MID(Tile_X4Y1_N2BEG[7:0]),
+	.N2END(Tile_X4Y1_N2BEGb[7:0]),
+	.N4END(Tile_X4Y1_N4BEG[15:0]),
+	.NN4END(Tile_X4Y1_NN4BEG[15:0]),
+	.S1BEG(Tile_X4Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X4Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X4Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X4Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X4Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X4Y1_UserCLKo),
+	.UserCLKo(Tile_X4Y0_UserCLKo),
+	.FrameStrobe(Tile_X4Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X4Y0_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X5Y0_N_term_single (
+	.N1END(Tile_X5Y1_N1BEG[3:0]),
+	.N2MID(Tile_X5Y1_N2BEG[7:0]),
+	.N2END(Tile_X5Y1_N2BEGb[7:0]),
+	.N4END(Tile_X5Y1_N4BEG[15:0]),
+	.NN4END(Tile_X5Y1_NN4BEG[15:0]),
+	.Ci(Tile_X5Y1_Co[0:0]),
+	.S1BEG(Tile_X5Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X5Y1_UserCLKo),
+	.UserCLKo(Tile_X5Y0_UserCLKo),
+	.FrameStrobe(Tile_X5Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y0_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X6Y0_N_term_single (
+	.N1END(Tile_X6Y1_N1BEG[3:0]),
+	.N2MID(Tile_X6Y1_N2BEG[7:0]),
+	.N2END(Tile_X6Y1_N2BEGb[7:0]),
+	.N4END(Tile_X6Y1_N4BEG[15:0]),
+	.NN4END(Tile_X6Y1_NN4BEG[15:0]),
+	.Ci(Tile_X6Y1_Co[0:0]),
+	.S1BEG(Tile_X6Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X6Y1_UserCLKo),
+	.UserCLKo(Tile_X6Y0_UserCLKo),
+	.FrameStrobe(Tile_X6Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y0_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X7Y0_N_term_single (
+	.N1END(Tile_X7Y1_N1BEG[3:0]),
+	.N2MID(Tile_X7Y1_N2BEG[7:0]),
+	.N2END(Tile_X7Y1_N2BEGb[7:0]),
+	.N4END(Tile_X7Y1_N4BEG[15:0]),
+	.NN4END(Tile_X7Y1_NN4BEG[15:0]),
+	.Ci(Tile_X7Y1_Co[0:0]),
+	.S1BEG(Tile_X7Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X7Y1_UserCLKo),
+	.UserCLKo(Tile_X7Y0_UserCLKo),
+	.FrameStrobe(Tile_X7Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y0_FrameStrobe_O)
+	);
+
+	N_term_DSP Tile_X8Y0_N_term_DSP (
+	.N1END(Tile_X8Y1_N1BEG[3:0]),
+	.N2MID(Tile_X8Y1_N2BEG[7:0]),
+	.N2END(Tile_X8Y1_N2BEGb[7:0]),
+	.N4END(Tile_X8Y1_N4BEG[15:0]),
+	.NN4END(Tile_X8Y1_NN4BEG[15:0]),
+	.S1BEG(Tile_X8Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X8Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X8Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X8Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X8Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X8Y1_UserCLKo),
+	.UserCLKo(Tile_X8Y0_UserCLKo),
+	.FrameStrobe(Tile_X8Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X8Y0_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X9Y0_N_term_single (
+	.N1END(Tile_X9Y1_N1BEG[3:0]),
+	.N2MID(Tile_X9Y1_N2BEG[7:0]),
+	.N2END(Tile_X9Y1_N2BEGb[7:0]),
+	.N4END(Tile_X9Y1_N4BEG[15:0]),
+	.NN4END(Tile_X9Y1_NN4BEG[15:0]),
+	.Ci(Tile_X9Y1_Co[0:0]),
+	.S1BEG(Tile_X9Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X9Y1_UserCLKo),
+	.UserCLKo(Tile_X9Y0_UserCLKo),
+	.FrameStrobe(Tile_X9Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y0_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X10Y0_N_term_single (
+	.N1END(Tile_X10Y1_N1BEG[3:0]),
+	.N2MID(Tile_X10Y1_N2BEG[7:0]),
+	.N2END(Tile_X10Y1_N2BEGb[7:0]),
+	.N4END(Tile_X10Y1_N4BEG[15:0]),
+	.NN4END(Tile_X10Y1_NN4BEG[15:0]),
+	.Ci(Tile_X10Y1_Co[0:0]),
+	.S1BEG(Tile_X10Y0_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y0_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y0_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y0_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y0_SS4BEG[15:0]),
+	.UserCLK(Tile_X10Y1_UserCLKo),
+	.UserCLKo(Tile_X10Y0_UserCLKo),
+	.FrameStrobe(Tile_X10Y1_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y0_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y1_W_CPU_IO (
+	.W1END(Tile_X4Y1_W1BEG[3:0]),
+	.W2MID(Tile_X4Y1_W2BEG[7:0]),
+	.W2END(Tile_X4Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y1_WW4BEG[15:0]),
+	.W6END(Tile_X4Y1_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y1_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y1_OPA_I0),
+	.OPA_I1(Tile_X3Y1_OPA_I1),
+	.OPA_I2(Tile_X3Y1_OPA_I2),
+	.OPA_I3(Tile_X3Y1_OPA_I3),
+	.UserCLK(Tile_X3Y2_UserCLKo),
+	.OPB_I0(Tile_X3Y1_OPB_I0),
+	.OPB_I1(Tile_X3Y1_OPB_I1),
+	.OPB_I2(Tile_X3Y1_OPB_I2),
+	.OPB_I3(Tile_X3Y1_OPB_I3),
+	.RES0_O0(Tile_X3Y1_RES0_O0),
+	.RES0_O1(Tile_X3Y1_RES0_O1),
+	.RES0_O2(Tile_X3Y1_RES0_O2),
+	.RES0_O3(Tile_X3Y1_RES0_O3),
+	.RES1_O0(Tile_X3Y1_RES1_O0),
+	.RES1_O1(Tile_X3Y1_RES1_O1),
+	.RES1_O2(Tile_X3Y1_RES1_O2),
+	.RES1_O3(Tile_X3Y1_RES1_O3),
+	.RES2_O0(Tile_X3Y1_RES2_O0),
+	.RES2_O1(Tile_X3Y1_RES2_O1),
+	.RES2_O2(Tile_X3Y1_RES2_O2),
+	.RES2_O3(Tile_X3Y1_RES2_O3),
+	.UserCLKo(Tile_X3Y1_UserCLKo),
+	.FrameData(Tile_Y1_FrameData), 
+	.FrameData_O(Tile_X3Y1_FrameData_O), 
+	.FrameStrobe(Tile_X3Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y1_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y1_LUT4AB (
+	.N1END(Tile_X5Y2_N1BEG[3:0]),
+	.N2MID(Tile_X5Y2_N2BEG[7:0]),
+	.N2END(Tile_X5Y2_N2BEGb[7:0]),
+	.N4END(Tile_X5Y2_N4BEG[15:0]),
+	.NN4END(Tile_X5Y2_NN4BEG[15:0]),
+	.Ci(Tile_X5Y2_Co[0:0]),
+	.E1END(Tile_X4Y1_E1BEG[3:0]),
+	.E2MID(Tile_X4Y1_E2BEG[7:0]),
+	.E2END(Tile_X4Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y1_EE4BEG[15:0]),
+	.E6END(Tile_X4Y1_E6BEG[11:0]),
+	.S1END(Tile_X5Y0_S1BEG[3:0]),
+	.S2MID(Tile_X5Y0_S2BEG[7:0]),
+	.S2END(Tile_X5Y0_S2BEGb[7:0]),
+	.S4END(Tile_X5Y0_S4BEG[15:0]),
+	.SS4END(Tile_X5Y0_SS4BEG[15:0]),
+	.W1END(Tile_X6Y1_W1BEG[3:0]),
+	.W2MID(Tile_X6Y1_W2BEG[7:0]),
+	.W2END(Tile_X6Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y1_WW4BEG[15:0]),
+	.W6END(Tile_X6Y1_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y1_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y1_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y1_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y1_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y1_NN4BEG[15:0]),
+	.Co(Tile_X5Y1_Co[0:0]),
+	.E1BEG(Tile_X5Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y1_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y1_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y1_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y1_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y1_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y1_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y2_UserCLKo),
+	.UserCLKo(Tile_X5Y1_UserCLKo),
+	.FrameData(Tile_X4Y1_FrameData_O), 
+	.FrameData_O(Tile_X5Y1_FrameData_O), 
+	.FrameStrobe(Tile_X5Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y1_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y1_LUT4AB (
+	.N1END(Tile_X6Y2_N1BEG[3:0]),
+	.N2MID(Tile_X6Y2_N2BEG[7:0]),
+	.N2END(Tile_X6Y2_N2BEGb[7:0]),
+	.N4END(Tile_X6Y2_N4BEG[15:0]),
+	.NN4END(Tile_X6Y2_NN4BEG[15:0]),
+	.Ci(Tile_X6Y2_Co[0:0]),
+	.E1END(Tile_X5Y1_E1BEG[3:0]),
+	.E2MID(Tile_X5Y1_E2BEG[7:0]),
+	.E2END(Tile_X5Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y1_EE4BEG[15:0]),
+	.E6END(Tile_X5Y1_E6BEG[11:0]),
+	.S1END(Tile_X6Y0_S1BEG[3:0]),
+	.S2MID(Tile_X6Y0_S2BEG[7:0]),
+	.S2END(Tile_X6Y0_S2BEGb[7:0]),
+	.S4END(Tile_X6Y0_S4BEG[15:0]),
+	.SS4END(Tile_X6Y0_SS4BEG[15:0]),
+	.W1END(Tile_X7Y1_W1BEG[3:0]),
+	.W2MID(Tile_X7Y1_W2BEG[7:0]),
+	.W2END(Tile_X7Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y1_WW4BEG[15:0]),
+	.W6END(Tile_X7Y1_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y1_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y1_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y1_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y1_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y1_NN4BEG[15:0]),
+	.Co(Tile_X6Y1_Co[0:0]),
+	.E1BEG(Tile_X6Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y1_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y1_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y1_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y1_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y1_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y1_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y2_UserCLKo),
+	.UserCLKo(Tile_X6Y1_UserCLKo),
+	.FrameData(Tile_X5Y1_FrameData_O), 
+	.FrameData_O(Tile_X6Y1_FrameData_O), 
+	.FrameStrobe(Tile_X6Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y1_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y1_LUT4AB (
+	.N1END(Tile_X7Y2_N1BEG[3:0]),
+	.N2MID(Tile_X7Y2_N2BEG[7:0]),
+	.N2END(Tile_X7Y2_N2BEGb[7:0]),
+	.N4END(Tile_X7Y2_N4BEG[15:0]),
+	.NN4END(Tile_X7Y2_NN4BEG[15:0]),
+	.Ci(Tile_X7Y2_Co[0:0]),
+	.E1END(Tile_X6Y1_E1BEG[3:0]),
+	.E2MID(Tile_X6Y1_E2BEG[7:0]),
+	.E2END(Tile_X6Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y1_EE4BEG[15:0]),
+	.E6END(Tile_X6Y1_E6BEG[11:0]),
+	.S1END(Tile_X7Y0_S1BEG[3:0]),
+	.S2MID(Tile_X7Y0_S2BEG[7:0]),
+	.S2END(Tile_X7Y0_S2BEGb[7:0]),
+	.S4END(Tile_X7Y0_S4BEG[15:0]),
+	.SS4END(Tile_X7Y0_SS4BEG[15:0]),
+	.W1END(Tile_X8Y1_W1BEG[3:0]),
+	.W2MID(Tile_X8Y1_W2BEG[7:0]),
+	.W2END(Tile_X8Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y1_WW4BEG[15:0]),
+	.W6END(Tile_X8Y1_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y1_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y1_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y1_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y1_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y1_NN4BEG[15:0]),
+	.Co(Tile_X7Y1_Co[0:0]),
+	.E1BEG(Tile_X7Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y1_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y1_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y1_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y1_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y1_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y1_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y2_UserCLKo),
+	.UserCLKo(Tile_X7Y1_UserCLKo),
+	.FrameData(Tile_X6Y1_FrameData_O), 
+	.FrameData_O(Tile_X7Y1_FrameData_O), 
+	.FrameStrobe(Tile_X7Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y1_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y1_LUT4AB (
+	.N1END(Tile_X9Y2_N1BEG[3:0]),
+	.N2MID(Tile_X9Y2_N2BEG[7:0]),
+	.N2END(Tile_X9Y2_N2BEGb[7:0]),
+	.N4END(Tile_X9Y2_N4BEG[15:0]),
+	.NN4END(Tile_X9Y2_NN4BEG[15:0]),
+	.Ci(Tile_X9Y2_Co[0:0]),
+	.E1END(Tile_X8Y1_E1BEG[3:0]),
+	.E2MID(Tile_X8Y1_E2BEG[7:0]),
+	.E2END(Tile_X8Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y1_EE4BEG[15:0]),
+	.E6END(Tile_X8Y1_E6BEG[11:0]),
+	.S1END(Tile_X9Y0_S1BEG[3:0]),
+	.S2MID(Tile_X9Y0_S2BEG[7:0]),
+	.S2END(Tile_X9Y0_S2BEGb[7:0]),
+	.S4END(Tile_X9Y0_S4BEG[15:0]),
+	.SS4END(Tile_X9Y0_SS4BEG[15:0]),
+	.W1END(Tile_X10Y1_W1BEG[3:0]),
+	.W2MID(Tile_X10Y1_W2BEG[7:0]),
+	.W2END(Tile_X10Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y1_WW4BEG[15:0]),
+	.W6END(Tile_X10Y1_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y1_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y1_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y1_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y1_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y1_NN4BEG[15:0]),
+	.Co(Tile_X9Y1_Co[0:0]),
+	.E1BEG(Tile_X9Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y1_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y1_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y1_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y1_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y1_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y1_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y2_UserCLKo),
+	.UserCLKo(Tile_X9Y1_UserCLKo),
+	.FrameData(Tile_X8Y1_FrameData_O), 
+	.FrameData_O(Tile_X9Y1_FrameData_O), 
+	.FrameStrobe(Tile_X9Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y1_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y1_LUT4AB (
+	.N1END(Tile_X10Y2_N1BEG[3:0]),
+	.N2MID(Tile_X10Y2_N2BEG[7:0]),
+	.N2END(Tile_X10Y2_N2BEGb[7:0]),
+	.N4END(Tile_X10Y2_N4BEG[15:0]),
+	.NN4END(Tile_X10Y2_NN4BEG[15:0]),
+	.Ci(Tile_X10Y2_Co[0:0]),
+	.E1END(Tile_X9Y1_E1BEG[3:0]),
+	.E2MID(Tile_X9Y1_E2BEG[7:0]),
+	.E2END(Tile_X9Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y1_EE4BEG[15:0]),
+	.E6END(Tile_X9Y1_E6BEG[11:0]),
+	.S1END(Tile_X10Y0_S1BEG[3:0]),
+	.S2MID(Tile_X10Y0_S2BEG[7:0]),
+	.S2END(Tile_X10Y0_S2BEGb[7:0]),
+	.S4END(Tile_X10Y0_S4BEG[15:0]),
+	.SS4END(Tile_X10Y0_SS4BEG[15:0]),
+	.W1END(Tile_X11Y1_W1BEG[3:0]),
+	.W2MID(Tile_X11Y1_W2BEG[7:0]),
+	.W2END(Tile_X11Y1_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y1_WW4BEG[15:0]),
+	.W6END(Tile_X11Y1_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y1_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y1_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y1_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y1_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y1_NN4BEG[15:0]),
+	.Co(Tile_X10Y1_Co[0:0]),
+	.E1BEG(Tile_X10Y1_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y1_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y1_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y1_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y1_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y1_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y1_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y1_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y1_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y1_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y2_UserCLKo),
+	.UserCLKo(Tile_X10Y1_UserCLKo),
+	.FrameData(Tile_X9Y1_FrameData_O), 
+	.FrameData_O(Tile_X10Y1_FrameData_O), 
+	.FrameStrobe(Tile_X10Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y1_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y1_E_CPU_IO (
+	.E1END(Tile_X10Y1_E1BEG[3:0]),
+	.E2MID(Tile_X10Y1_E2BEG[7:0]),
+	.E2END(Tile_X10Y1_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y1_EE4BEG[15:0]),
+	.E6END(Tile_X10Y1_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y1_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y1_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y1_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y1_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y1_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y1_OPA_I0),
+	.OPA_I1(Tile_X11Y1_OPA_I1),
+	.OPA_I2(Tile_X11Y1_OPA_I2),
+	.OPA_I3(Tile_X11Y1_OPA_I3),
+	.UserCLK(Tile_X11Y2_UserCLKo),
+	.OPB_I0(Tile_X11Y1_OPB_I0),
+	.OPB_I1(Tile_X11Y1_OPB_I1),
+	.OPB_I2(Tile_X11Y1_OPB_I2),
+	.OPB_I3(Tile_X11Y1_OPB_I3),
+	.RES0_O0(Tile_X11Y1_RES0_O0),
+	.RES0_O1(Tile_X11Y1_RES0_O1),
+	.RES0_O2(Tile_X11Y1_RES0_O2),
+	.RES0_O3(Tile_X11Y1_RES0_O3),
+	.RES1_O0(Tile_X11Y1_RES1_O0),
+	.RES1_O1(Tile_X11Y1_RES1_O1),
+	.RES1_O2(Tile_X11Y1_RES1_O2),
+	.RES1_O3(Tile_X11Y1_RES1_O3),
+	.RES2_O0(Tile_X11Y1_RES2_O0),
+	.RES2_O1(Tile_X11Y1_RES2_O1),
+	.RES2_O2(Tile_X11Y1_RES2_O2),
+	.RES2_O3(Tile_X11Y1_RES2_O3),
+	.UserCLKo(Tile_X11Y1_UserCLKo),
+	.FrameData(Tile_X10Y1_FrameData_O), 
+	.FrameData_O(Tile_X11Y1_FrameData_O), 
+	.FrameStrobe(Tile_X11Y2_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y1_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y2_W_CPU_IO (
+	.W1END(Tile_X4Y2_W1BEG[3:0]),
+	.W2MID(Tile_X4Y2_W2BEG[7:0]),
+	.W2END(Tile_X4Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y2_WW4BEG[15:0]),
+	.W6END(Tile_X4Y2_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y2_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y2_OPA_I0),
+	.OPA_I1(Tile_X3Y2_OPA_I1),
+	.OPA_I2(Tile_X3Y2_OPA_I2),
+	.OPA_I3(Tile_X3Y2_OPA_I3),
+	.UserCLK(Tile_X3Y3_UserCLKo),
+	.OPB_I0(Tile_X3Y2_OPB_I0),
+	.OPB_I1(Tile_X3Y2_OPB_I1),
+	.OPB_I2(Tile_X3Y2_OPB_I2),
+	.OPB_I3(Tile_X3Y2_OPB_I3),
+	.RES0_O0(Tile_X3Y2_RES0_O0),
+	.RES0_O1(Tile_X3Y2_RES0_O1),
+	.RES0_O2(Tile_X3Y2_RES0_O2),
+	.RES0_O3(Tile_X3Y2_RES0_O3),
+	.RES1_O0(Tile_X3Y2_RES1_O0),
+	.RES1_O1(Tile_X3Y2_RES1_O1),
+	.RES1_O2(Tile_X3Y2_RES1_O2),
+	.RES1_O3(Tile_X3Y2_RES1_O3),
+	.RES2_O0(Tile_X3Y2_RES2_O0),
+	.RES2_O1(Tile_X3Y2_RES2_O1),
+	.RES2_O2(Tile_X3Y2_RES2_O2),
+	.RES2_O3(Tile_X3Y2_RES2_O3),
+	.UserCLKo(Tile_X3Y2_UserCLKo),
+	.FrameData(Tile_Y2_FrameData), 
+	.FrameData_O(Tile_X3Y2_FrameData_O), 
+	.FrameStrobe(Tile_X3Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y2_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y2_LUT4AB (
+	.N1END(Tile_X5Y3_N1BEG[3:0]),
+	.N2MID(Tile_X5Y3_N2BEG[7:0]),
+	.N2END(Tile_X5Y3_N2BEGb[7:0]),
+	.N4END(Tile_X5Y3_N4BEG[15:0]),
+	.NN4END(Tile_X5Y3_NN4BEG[15:0]),
+	.Ci(Tile_X5Y3_Co[0:0]),
+	.E1END(Tile_X4Y2_E1BEG[3:0]),
+	.E2MID(Tile_X4Y2_E2BEG[7:0]),
+	.E2END(Tile_X4Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y2_EE4BEG[15:0]),
+	.E6END(Tile_X4Y2_E6BEG[11:0]),
+	.S1END(Tile_X5Y1_S1BEG[3:0]),
+	.S2MID(Tile_X5Y1_S2BEG[7:0]),
+	.S2END(Tile_X5Y1_S2BEGb[7:0]),
+	.S4END(Tile_X5Y1_S4BEG[15:0]),
+	.SS4END(Tile_X5Y1_SS4BEG[15:0]),
+	.W1END(Tile_X6Y2_W1BEG[3:0]),
+	.W2MID(Tile_X6Y2_W2BEG[7:0]),
+	.W2END(Tile_X6Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y2_WW4BEG[15:0]),
+	.W6END(Tile_X6Y2_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y2_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y2_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y2_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y2_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y2_NN4BEG[15:0]),
+	.Co(Tile_X5Y2_Co[0:0]),
+	.E1BEG(Tile_X5Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y2_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y2_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y2_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y2_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y2_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y2_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y3_UserCLKo),
+	.UserCLKo(Tile_X5Y2_UserCLKo),
+	.FrameData(Tile_X4Y2_FrameData_O), 
+	.FrameData_O(Tile_X5Y2_FrameData_O), 
+	.FrameStrobe(Tile_X5Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y2_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y2_LUT4AB (
+	.N1END(Tile_X6Y3_N1BEG[3:0]),
+	.N2MID(Tile_X6Y3_N2BEG[7:0]),
+	.N2END(Tile_X6Y3_N2BEGb[7:0]),
+	.N4END(Tile_X6Y3_N4BEG[15:0]),
+	.NN4END(Tile_X6Y3_NN4BEG[15:0]),
+	.Ci(Tile_X6Y3_Co[0:0]),
+	.E1END(Tile_X5Y2_E1BEG[3:0]),
+	.E2MID(Tile_X5Y2_E2BEG[7:0]),
+	.E2END(Tile_X5Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y2_EE4BEG[15:0]),
+	.E6END(Tile_X5Y2_E6BEG[11:0]),
+	.S1END(Tile_X6Y1_S1BEG[3:0]),
+	.S2MID(Tile_X6Y1_S2BEG[7:0]),
+	.S2END(Tile_X6Y1_S2BEGb[7:0]),
+	.S4END(Tile_X6Y1_S4BEG[15:0]),
+	.SS4END(Tile_X6Y1_SS4BEG[15:0]),
+	.W1END(Tile_X7Y2_W1BEG[3:0]),
+	.W2MID(Tile_X7Y2_W2BEG[7:0]),
+	.W2END(Tile_X7Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y2_WW4BEG[15:0]),
+	.W6END(Tile_X7Y2_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y2_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y2_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y2_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y2_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y2_NN4BEG[15:0]),
+	.Co(Tile_X6Y2_Co[0:0]),
+	.E1BEG(Tile_X6Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y2_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y2_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y2_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y2_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y2_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y2_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y3_UserCLKo),
+	.UserCLKo(Tile_X6Y2_UserCLKo),
+	.FrameData(Tile_X5Y2_FrameData_O), 
+	.FrameData_O(Tile_X6Y2_FrameData_O), 
+	.FrameStrobe(Tile_X6Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y2_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y2_LUT4AB (
+	.N1END(Tile_X7Y3_N1BEG[3:0]),
+	.N2MID(Tile_X7Y3_N2BEG[7:0]),
+	.N2END(Tile_X7Y3_N2BEGb[7:0]),
+	.N4END(Tile_X7Y3_N4BEG[15:0]),
+	.NN4END(Tile_X7Y3_NN4BEG[15:0]),
+	.Ci(Tile_X7Y3_Co[0:0]),
+	.E1END(Tile_X6Y2_E1BEG[3:0]),
+	.E2MID(Tile_X6Y2_E2BEG[7:0]),
+	.E2END(Tile_X6Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y2_EE4BEG[15:0]),
+	.E6END(Tile_X6Y2_E6BEG[11:0]),
+	.S1END(Tile_X7Y1_S1BEG[3:0]),
+	.S2MID(Tile_X7Y1_S2BEG[7:0]),
+	.S2END(Tile_X7Y1_S2BEGb[7:0]),
+	.S4END(Tile_X7Y1_S4BEG[15:0]),
+	.SS4END(Tile_X7Y1_SS4BEG[15:0]),
+	.W1END(Tile_X8Y2_W1BEG[3:0]),
+	.W2MID(Tile_X8Y2_W2BEG[7:0]),
+	.W2END(Tile_X8Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y2_WW4BEG[15:0]),
+	.W6END(Tile_X8Y2_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y2_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y2_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y2_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y2_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y2_NN4BEG[15:0]),
+	.Co(Tile_X7Y2_Co[0:0]),
+	.E1BEG(Tile_X7Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y2_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y2_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y2_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y2_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y2_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y2_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y3_UserCLKo),
+	.UserCLKo(Tile_X7Y2_UserCLKo),
+	.FrameData(Tile_X6Y2_FrameData_O), 
+	.FrameData_O(Tile_X7Y2_FrameData_O), 
+	.FrameStrobe(Tile_X7Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y2_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y2_LUT4AB (
+	.N1END(Tile_X9Y3_N1BEG[3:0]),
+	.N2MID(Tile_X9Y3_N2BEG[7:0]),
+	.N2END(Tile_X9Y3_N2BEGb[7:0]),
+	.N4END(Tile_X9Y3_N4BEG[15:0]),
+	.NN4END(Tile_X9Y3_NN4BEG[15:0]),
+	.Ci(Tile_X9Y3_Co[0:0]),
+	.E1END(Tile_X8Y2_E1BEG[3:0]),
+	.E2MID(Tile_X8Y2_E2BEG[7:0]),
+	.E2END(Tile_X8Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y2_EE4BEG[15:0]),
+	.E6END(Tile_X8Y2_E6BEG[11:0]),
+	.S1END(Tile_X9Y1_S1BEG[3:0]),
+	.S2MID(Tile_X9Y1_S2BEG[7:0]),
+	.S2END(Tile_X9Y1_S2BEGb[7:0]),
+	.S4END(Tile_X9Y1_S4BEG[15:0]),
+	.SS4END(Tile_X9Y1_SS4BEG[15:0]),
+	.W1END(Tile_X10Y2_W1BEG[3:0]),
+	.W2MID(Tile_X10Y2_W2BEG[7:0]),
+	.W2END(Tile_X10Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y2_WW4BEG[15:0]),
+	.W6END(Tile_X10Y2_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y2_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y2_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y2_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y2_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y2_NN4BEG[15:0]),
+	.Co(Tile_X9Y2_Co[0:0]),
+	.E1BEG(Tile_X9Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y2_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y2_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y2_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y2_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y2_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y2_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y3_UserCLKo),
+	.UserCLKo(Tile_X9Y2_UserCLKo),
+	.FrameData(Tile_X8Y2_FrameData_O), 
+	.FrameData_O(Tile_X9Y2_FrameData_O), 
+	.FrameStrobe(Tile_X9Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y2_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y2_LUT4AB (
+	.N1END(Tile_X10Y3_N1BEG[3:0]),
+	.N2MID(Tile_X10Y3_N2BEG[7:0]),
+	.N2END(Tile_X10Y3_N2BEGb[7:0]),
+	.N4END(Tile_X10Y3_N4BEG[15:0]),
+	.NN4END(Tile_X10Y3_NN4BEG[15:0]),
+	.Ci(Tile_X10Y3_Co[0:0]),
+	.E1END(Tile_X9Y2_E1BEG[3:0]),
+	.E2MID(Tile_X9Y2_E2BEG[7:0]),
+	.E2END(Tile_X9Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y2_EE4BEG[15:0]),
+	.E6END(Tile_X9Y2_E6BEG[11:0]),
+	.S1END(Tile_X10Y1_S1BEG[3:0]),
+	.S2MID(Tile_X10Y1_S2BEG[7:0]),
+	.S2END(Tile_X10Y1_S2BEGb[7:0]),
+	.S4END(Tile_X10Y1_S4BEG[15:0]),
+	.SS4END(Tile_X10Y1_SS4BEG[15:0]),
+	.W1END(Tile_X11Y2_W1BEG[3:0]),
+	.W2MID(Tile_X11Y2_W2BEG[7:0]),
+	.W2END(Tile_X11Y2_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y2_WW4BEG[15:0]),
+	.W6END(Tile_X11Y2_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y2_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y2_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y2_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y2_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y2_NN4BEG[15:0]),
+	.Co(Tile_X10Y2_Co[0:0]),
+	.E1BEG(Tile_X10Y2_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y2_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y2_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y2_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y2_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y2_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y2_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y2_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y2_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y2_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y3_UserCLKo),
+	.UserCLKo(Tile_X10Y2_UserCLKo),
+	.FrameData(Tile_X9Y2_FrameData_O), 
+	.FrameData_O(Tile_X10Y2_FrameData_O), 
+	.FrameStrobe(Tile_X10Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y2_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y2_E_CPU_IO (
+	.E1END(Tile_X10Y2_E1BEG[3:0]),
+	.E2MID(Tile_X10Y2_E2BEG[7:0]),
+	.E2END(Tile_X10Y2_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y2_EE4BEG[15:0]),
+	.E6END(Tile_X10Y2_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y2_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y2_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y2_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y2_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y2_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y2_OPA_I0),
+	.OPA_I1(Tile_X11Y2_OPA_I1),
+	.OPA_I2(Tile_X11Y2_OPA_I2),
+	.OPA_I3(Tile_X11Y2_OPA_I3),
+	.UserCLK(Tile_X11Y3_UserCLKo),
+	.OPB_I0(Tile_X11Y2_OPB_I0),
+	.OPB_I1(Tile_X11Y2_OPB_I1),
+	.OPB_I2(Tile_X11Y2_OPB_I2),
+	.OPB_I3(Tile_X11Y2_OPB_I3),
+	.RES0_O0(Tile_X11Y2_RES0_O0),
+	.RES0_O1(Tile_X11Y2_RES0_O1),
+	.RES0_O2(Tile_X11Y2_RES0_O2),
+	.RES0_O3(Tile_X11Y2_RES0_O3),
+	.RES1_O0(Tile_X11Y2_RES1_O0),
+	.RES1_O1(Tile_X11Y2_RES1_O1),
+	.RES1_O2(Tile_X11Y2_RES1_O2),
+	.RES1_O3(Tile_X11Y2_RES1_O3),
+	.RES2_O0(Tile_X11Y2_RES2_O0),
+	.RES2_O1(Tile_X11Y2_RES2_O1),
+	.RES2_O2(Tile_X11Y2_RES2_O2),
+	.RES2_O3(Tile_X11Y2_RES2_O3),
+	.UserCLKo(Tile_X11Y2_UserCLKo),
+	.FrameData(Tile_X10Y2_FrameData_O), 
+	.FrameData_O(Tile_X11Y2_FrameData_O), 
+	.FrameStrobe(Tile_X11Y3_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y2_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y3_W_CPU_IO (
+	.W1END(Tile_X4Y3_W1BEG[3:0]),
+	.W2MID(Tile_X4Y3_W2BEG[7:0]),
+	.W2END(Tile_X4Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y3_WW4BEG[15:0]),
+	.W6END(Tile_X4Y3_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y3_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y3_OPA_I0),
+	.OPA_I1(Tile_X3Y3_OPA_I1),
+	.OPA_I2(Tile_X3Y3_OPA_I2),
+	.OPA_I3(Tile_X3Y3_OPA_I3),
+	.UserCLK(Tile_X3Y4_UserCLKo),
+	.OPB_I0(Tile_X3Y3_OPB_I0),
+	.OPB_I1(Tile_X3Y3_OPB_I1),
+	.OPB_I2(Tile_X3Y3_OPB_I2),
+	.OPB_I3(Tile_X3Y3_OPB_I3),
+	.RES0_O0(Tile_X3Y3_RES0_O0),
+	.RES0_O1(Tile_X3Y3_RES0_O1),
+	.RES0_O2(Tile_X3Y3_RES0_O2),
+	.RES0_O3(Tile_X3Y3_RES0_O3),
+	.RES1_O0(Tile_X3Y3_RES1_O0),
+	.RES1_O1(Tile_X3Y3_RES1_O1),
+	.RES1_O2(Tile_X3Y3_RES1_O2),
+	.RES1_O3(Tile_X3Y3_RES1_O3),
+	.RES2_O0(Tile_X3Y3_RES2_O0),
+	.RES2_O1(Tile_X3Y3_RES2_O1),
+	.RES2_O2(Tile_X3Y3_RES2_O2),
+	.RES2_O3(Tile_X3Y3_RES2_O3),
+	.UserCLKo(Tile_X3Y3_UserCLKo),
+	.FrameData(Tile_Y3_FrameData), 
+	.FrameData_O(Tile_X3Y3_FrameData_O), 
+	.FrameStrobe(Tile_X3Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y3_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y3_LUT4AB (
+	.N1END(Tile_X5Y4_N1BEG[3:0]),
+	.N2MID(Tile_X5Y4_N2BEG[7:0]),
+	.N2END(Tile_X5Y4_N2BEGb[7:0]),
+	.N4END(Tile_X5Y4_N4BEG[15:0]),
+	.NN4END(Tile_X5Y4_NN4BEG[15:0]),
+	.Ci(Tile_X5Y4_Co[0:0]),
+	.E1END(Tile_X4Y3_E1BEG[3:0]),
+	.E2MID(Tile_X4Y3_E2BEG[7:0]),
+	.E2END(Tile_X4Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y3_EE4BEG[15:0]),
+	.E6END(Tile_X4Y3_E6BEG[11:0]),
+	.S1END(Tile_X5Y2_S1BEG[3:0]),
+	.S2MID(Tile_X5Y2_S2BEG[7:0]),
+	.S2END(Tile_X5Y2_S2BEGb[7:0]),
+	.S4END(Tile_X5Y2_S4BEG[15:0]),
+	.SS4END(Tile_X5Y2_SS4BEG[15:0]),
+	.W1END(Tile_X6Y3_W1BEG[3:0]),
+	.W2MID(Tile_X6Y3_W2BEG[7:0]),
+	.W2END(Tile_X6Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y3_WW4BEG[15:0]),
+	.W6END(Tile_X6Y3_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y3_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y3_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y3_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y3_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y3_NN4BEG[15:0]),
+	.Co(Tile_X5Y3_Co[0:0]),
+	.E1BEG(Tile_X5Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y3_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y3_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y3_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y3_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y3_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y3_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y4_UserCLKo),
+	.UserCLKo(Tile_X5Y3_UserCLKo),
+	.FrameData(Tile_X4Y3_FrameData_O), 
+	.FrameData_O(Tile_X5Y3_FrameData_O), 
+	.FrameStrobe(Tile_X5Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y3_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y3_LUT4AB (
+	.N1END(Tile_X6Y4_N1BEG[3:0]),
+	.N2MID(Tile_X6Y4_N2BEG[7:0]),
+	.N2END(Tile_X6Y4_N2BEGb[7:0]),
+	.N4END(Tile_X6Y4_N4BEG[15:0]),
+	.NN4END(Tile_X6Y4_NN4BEG[15:0]),
+	.Ci(Tile_X6Y4_Co[0:0]),
+	.E1END(Tile_X5Y3_E1BEG[3:0]),
+	.E2MID(Tile_X5Y3_E2BEG[7:0]),
+	.E2END(Tile_X5Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y3_EE4BEG[15:0]),
+	.E6END(Tile_X5Y3_E6BEG[11:0]),
+	.S1END(Tile_X6Y2_S1BEG[3:0]),
+	.S2MID(Tile_X6Y2_S2BEG[7:0]),
+	.S2END(Tile_X6Y2_S2BEGb[7:0]),
+	.S4END(Tile_X6Y2_S4BEG[15:0]),
+	.SS4END(Tile_X6Y2_SS4BEG[15:0]),
+	.W1END(Tile_X7Y3_W1BEG[3:0]),
+	.W2MID(Tile_X7Y3_W2BEG[7:0]),
+	.W2END(Tile_X7Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y3_WW4BEG[15:0]),
+	.W6END(Tile_X7Y3_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y3_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y3_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y3_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y3_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y3_NN4BEG[15:0]),
+	.Co(Tile_X6Y3_Co[0:0]),
+	.E1BEG(Tile_X6Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y3_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y3_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y3_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y3_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y3_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y3_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y4_UserCLKo),
+	.UserCLKo(Tile_X6Y3_UserCLKo),
+	.FrameData(Tile_X5Y3_FrameData_O), 
+	.FrameData_O(Tile_X6Y3_FrameData_O), 
+	.FrameStrobe(Tile_X6Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y3_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y3_LUT4AB (
+	.N1END(Tile_X7Y4_N1BEG[3:0]),
+	.N2MID(Tile_X7Y4_N2BEG[7:0]),
+	.N2END(Tile_X7Y4_N2BEGb[7:0]),
+	.N4END(Tile_X7Y4_N4BEG[15:0]),
+	.NN4END(Tile_X7Y4_NN4BEG[15:0]),
+	.Ci(Tile_X7Y4_Co[0:0]),
+	.E1END(Tile_X6Y3_E1BEG[3:0]),
+	.E2MID(Tile_X6Y3_E2BEG[7:0]),
+	.E2END(Tile_X6Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y3_EE4BEG[15:0]),
+	.E6END(Tile_X6Y3_E6BEG[11:0]),
+	.S1END(Tile_X7Y2_S1BEG[3:0]),
+	.S2MID(Tile_X7Y2_S2BEG[7:0]),
+	.S2END(Tile_X7Y2_S2BEGb[7:0]),
+	.S4END(Tile_X7Y2_S4BEG[15:0]),
+	.SS4END(Tile_X7Y2_SS4BEG[15:0]),
+	.W1END(Tile_X8Y3_W1BEG[3:0]),
+	.W2MID(Tile_X8Y3_W2BEG[7:0]),
+	.W2END(Tile_X8Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y3_WW4BEG[15:0]),
+	.W6END(Tile_X8Y3_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y3_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y3_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y3_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y3_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y3_NN4BEG[15:0]),
+	.Co(Tile_X7Y3_Co[0:0]),
+	.E1BEG(Tile_X7Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y3_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y3_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y3_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y3_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y3_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y3_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y4_UserCLKo),
+	.UserCLKo(Tile_X7Y3_UserCLKo),
+	.FrameData(Tile_X6Y3_FrameData_O), 
+	.FrameData_O(Tile_X7Y3_FrameData_O), 
+	.FrameStrobe(Tile_X7Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y3_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y3_LUT4AB (
+	.N1END(Tile_X9Y4_N1BEG[3:0]),
+	.N2MID(Tile_X9Y4_N2BEG[7:0]),
+	.N2END(Tile_X9Y4_N2BEGb[7:0]),
+	.N4END(Tile_X9Y4_N4BEG[15:0]),
+	.NN4END(Tile_X9Y4_NN4BEG[15:0]),
+	.Ci(Tile_X9Y4_Co[0:0]),
+	.E1END(Tile_X8Y3_E1BEG[3:0]),
+	.E2MID(Tile_X8Y3_E2BEG[7:0]),
+	.E2END(Tile_X8Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y3_EE4BEG[15:0]),
+	.E6END(Tile_X8Y3_E6BEG[11:0]),
+	.S1END(Tile_X9Y2_S1BEG[3:0]),
+	.S2MID(Tile_X9Y2_S2BEG[7:0]),
+	.S2END(Tile_X9Y2_S2BEGb[7:0]),
+	.S4END(Tile_X9Y2_S4BEG[15:0]),
+	.SS4END(Tile_X9Y2_SS4BEG[15:0]),
+	.W1END(Tile_X10Y3_W1BEG[3:0]),
+	.W2MID(Tile_X10Y3_W2BEG[7:0]),
+	.W2END(Tile_X10Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y3_WW4BEG[15:0]),
+	.W6END(Tile_X10Y3_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y3_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y3_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y3_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y3_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y3_NN4BEG[15:0]),
+	.Co(Tile_X9Y3_Co[0:0]),
+	.E1BEG(Tile_X9Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y3_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y3_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y3_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y3_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y3_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y3_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y4_UserCLKo),
+	.UserCLKo(Tile_X9Y3_UserCLKo),
+	.FrameData(Tile_X8Y3_FrameData_O), 
+	.FrameData_O(Tile_X9Y3_FrameData_O), 
+	.FrameStrobe(Tile_X9Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y3_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y3_LUT4AB (
+	.N1END(Tile_X10Y4_N1BEG[3:0]),
+	.N2MID(Tile_X10Y4_N2BEG[7:0]),
+	.N2END(Tile_X10Y4_N2BEGb[7:0]),
+	.N4END(Tile_X10Y4_N4BEG[15:0]),
+	.NN4END(Tile_X10Y4_NN4BEG[15:0]),
+	.Ci(Tile_X10Y4_Co[0:0]),
+	.E1END(Tile_X9Y3_E1BEG[3:0]),
+	.E2MID(Tile_X9Y3_E2BEG[7:0]),
+	.E2END(Tile_X9Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y3_EE4BEG[15:0]),
+	.E6END(Tile_X9Y3_E6BEG[11:0]),
+	.S1END(Tile_X10Y2_S1BEG[3:0]),
+	.S2MID(Tile_X10Y2_S2BEG[7:0]),
+	.S2END(Tile_X10Y2_S2BEGb[7:0]),
+	.S4END(Tile_X10Y2_S4BEG[15:0]),
+	.SS4END(Tile_X10Y2_SS4BEG[15:0]),
+	.W1END(Tile_X11Y3_W1BEG[3:0]),
+	.W2MID(Tile_X11Y3_W2BEG[7:0]),
+	.W2END(Tile_X11Y3_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y3_WW4BEG[15:0]),
+	.W6END(Tile_X11Y3_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y3_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y3_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y3_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y3_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y3_NN4BEG[15:0]),
+	.Co(Tile_X10Y3_Co[0:0]),
+	.E1BEG(Tile_X10Y3_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y3_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y3_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y3_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y3_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y3_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y3_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y3_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y3_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y3_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y4_UserCLKo),
+	.UserCLKo(Tile_X10Y3_UserCLKo),
+	.FrameData(Tile_X9Y3_FrameData_O), 
+	.FrameData_O(Tile_X10Y3_FrameData_O), 
+	.FrameStrobe(Tile_X10Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y3_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y3_E_CPU_IO (
+	.E1END(Tile_X10Y3_E1BEG[3:0]),
+	.E2MID(Tile_X10Y3_E2BEG[7:0]),
+	.E2END(Tile_X10Y3_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y3_EE4BEG[15:0]),
+	.E6END(Tile_X10Y3_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y3_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y3_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y3_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y3_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y3_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y3_OPA_I0),
+	.OPA_I1(Tile_X11Y3_OPA_I1),
+	.OPA_I2(Tile_X11Y3_OPA_I2),
+	.OPA_I3(Tile_X11Y3_OPA_I3),
+	.UserCLK(Tile_X11Y4_UserCLKo),
+	.OPB_I0(Tile_X11Y3_OPB_I0),
+	.OPB_I1(Tile_X11Y3_OPB_I1),
+	.OPB_I2(Tile_X11Y3_OPB_I2),
+	.OPB_I3(Tile_X11Y3_OPB_I3),
+	.RES0_O0(Tile_X11Y3_RES0_O0),
+	.RES0_O1(Tile_X11Y3_RES0_O1),
+	.RES0_O2(Tile_X11Y3_RES0_O2),
+	.RES0_O3(Tile_X11Y3_RES0_O3),
+	.RES1_O0(Tile_X11Y3_RES1_O0),
+	.RES1_O1(Tile_X11Y3_RES1_O1),
+	.RES1_O2(Tile_X11Y3_RES1_O2),
+	.RES1_O3(Tile_X11Y3_RES1_O3),
+	.RES2_O0(Tile_X11Y3_RES2_O0),
+	.RES2_O1(Tile_X11Y3_RES2_O1),
+	.RES2_O2(Tile_X11Y3_RES2_O2),
+	.RES2_O3(Tile_X11Y3_RES2_O3),
+	.UserCLKo(Tile_X11Y3_UserCLKo),
+	.FrameData(Tile_X10Y3_FrameData_O), 
+	.FrameData_O(Tile_X11Y3_FrameData_O), 
+	.FrameStrobe(Tile_X11Y4_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y3_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y4_W_CPU_IO (
+	.W1END(Tile_X4Y4_W1BEG[3:0]),
+	.W2MID(Tile_X4Y4_W2BEG[7:0]),
+	.W2END(Tile_X4Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y4_WW4BEG[15:0]),
+	.W6END(Tile_X4Y4_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y4_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y4_OPA_I0),
+	.OPA_I1(Tile_X3Y4_OPA_I1),
+	.OPA_I2(Tile_X3Y4_OPA_I2),
+	.OPA_I3(Tile_X3Y4_OPA_I3),
+	.UserCLK(Tile_X3Y5_UserCLKo),
+	.OPB_I0(Tile_X3Y4_OPB_I0),
+	.OPB_I1(Tile_X3Y4_OPB_I1),
+	.OPB_I2(Tile_X3Y4_OPB_I2),
+	.OPB_I3(Tile_X3Y4_OPB_I3),
+	.RES0_O0(Tile_X3Y4_RES0_O0),
+	.RES0_O1(Tile_X3Y4_RES0_O1),
+	.RES0_O2(Tile_X3Y4_RES0_O2),
+	.RES0_O3(Tile_X3Y4_RES0_O3),
+	.RES1_O0(Tile_X3Y4_RES1_O0),
+	.RES1_O1(Tile_X3Y4_RES1_O1),
+	.RES1_O2(Tile_X3Y4_RES1_O2),
+	.RES1_O3(Tile_X3Y4_RES1_O3),
+	.RES2_O0(Tile_X3Y4_RES2_O0),
+	.RES2_O1(Tile_X3Y4_RES2_O1),
+	.RES2_O2(Tile_X3Y4_RES2_O2),
+	.RES2_O3(Tile_X3Y4_RES2_O3),
+	.UserCLKo(Tile_X3Y4_UserCLKo),
+	.FrameData(Tile_Y4_FrameData), 
+	.FrameData_O(Tile_X3Y4_FrameData_O), 
+	.FrameStrobe(Tile_X3Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y4_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y4_LUT4AB (
+	.N1END(Tile_X5Y5_N1BEG[3:0]),
+	.N2MID(Tile_X5Y5_N2BEG[7:0]),
+	.N2END(Tile_X5Y5_N2BEGb[7:0]),
+	.N4END(Tile_X5Y5_N4BEG[15:0]),
+	.NN4END(Tile_X5Y5_NN4BEG[15:0]),
+	.Ci(Tile_X5Y5_Co[0:0]),
+	.E1END(Tile_X4Y4_E1BEG[3:0]),
+	.E2MID(Tile_X4Y4_E2BEG[7:0]),
+	.E2END(Tile_X4Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y4_EE4BEG[15:0]),
+	.E6END(Tile_X4Y4_E6BEG[11:0]),
+	.S1END(Tile_X5Y3_S1BEG[3:0]),
+	.S2MID(Tile_X5Y3_S2BEG[7:0]),
+	.S2END(Tile_X5Y3_S2BEGb[7:0]),
+	.S4END(Tile_X5Y3_S4BEG[15:0]),
+	.SS4END(Tile_X5Y3_SS4BEG[15:0]),
+	.W1END(Tile_X6Y4_W1BEG[3:0]),
+	.W2MID(Tile_X6Y4_W2BEG[7:0]),
+	.W2END(Tile_X6Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y4_WW4BEG[15:0]),
+	.W6END(Tile_X6Y4_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y4_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y4_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y4_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y4_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y4_NN4BEG[15:0]),
+	.Co(Tile_X5Y4_Co[0:0]),
+	.E1BEG(Tile_X5Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y4_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y4_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y4_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y4_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y4_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y4_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y5_UserCLKo),
+	.UserCLKo(Tile_X5Y4_UserCLKo),
+	.FrameData(Tile_X4Y4_FrameData_O), 
+	.FrameData_O(Tile_X5Y4_FrameData_O), 
+	.FrameStrobe(Tile_X5Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y4_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y4_LUT4AB (
+	.N1END(Tile_X6Y5_N1BEG[3:0]),
+	.N2MID(Tile_X6Y5_N2BEG[7:0]),
+	.N2END(Tile_X6Y5_N2BEGb[7:0]),
+	.N4END(Tile_X6Y5_N4BEG[15:0]),
+	.NN4END(Tile_X6Y5_NN4BEG[15:0]),
+	.Ci(Tile_X6Y5_Co[0:0]),
+	.E1END(Tile_X5Y4_E1BEG[3:0]),
+	.E2MID(Tile_X5Y4_E2BEG[7:0]),
+	.E2END(Tile_X5Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y4_EE4BEG[15:0]),
+	.E6END(Tile_X5Y4_E6BEG[11:0]),
+	.S1END(Tile_X6Y3_S1BEG[3:0]),
+	.S2MID(Tile_X6Y3_S2BEG[7:0]),
+	.S2END(Tile_X6Y3_S2BEGb[7:0]),
+	.S4END(Tile_X6Y3_S4BEG[15:0]),
+	.SS4END(Tile_X6Y3_SS4BEG[15:0]),
+	.W1END(Tile_X7Y4_W1BEG[3:0]),
+	.W2MID(Tile_X7Y4_W2BEG[7:0]),
+	.W2END(Tile_X7Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y4_WW4BEG[15:0]),
+	.W6END(Tile_X7Y4_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y4_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y4_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y4_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y4_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y4_NN4BEG[15:0]),
+	.Co(Tile_X6Y4_Co[0:0]),
+	.E1BEG(Tile_X6Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y4_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y4_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y4_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y4_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y4_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y4_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y5_UserCLKo),
+	.UserCLKo(Tile_X6Y4_UserCLKo),
+	.FrameData(Tile_X5Y4_FrameData_O), 
+	.FrameData_O(Tile_X6Y4_FrameData_O), 
+	.FrameStrobe(Tile_X6Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y4_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y4_LUT4AB (
+	.N1END(Tile_X7Y5_N1BEG[3:0]),
+	.N2MID(Tile_X7Y5_N2BEG[7:0]),
+	.N2END(Tile_X7Y5_N2BEGb[7:0]),
+	.N4END(Tile_X7Y5_N4BEG[15:0]),
+	.NN4END(Tile_X7Y5_NN4BEG[15:0]),
+	.Ci(Tile_X7Y5_Co[0:0]),
+	.E1END(Tile_X6Y4_E1BEG[3:0]),
+	.E2MID(Tile_X6Y4_E2BEG[7:0]),
+	.E2END(Tile_X6Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y4_EE4BEG[15:0]),
+	.E6END(Tile_X6Y4_E6BEG[11:0]),
+	.S1END(Tile_X7Y3_S1BEG[3:0]),
+	.S2MID(Tile_X7Y3_S2BEG[7:0]),
+	.S2END(Tile_X7Y3_S2BEGb[7:0]),
+	.S4END(Tile_X7Y3_S4BEG[15:0]),
+	.SS4END(Tile_X7Y3_SS4BEG[15:0]),
+	.W1END(Tile_X8Y4_W1BEG[3:0]),
+	.W2MID(Tile_X8Y4_W2BEG[7:0]),
+	.W2END(Tile_X8Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y4_WW4BEG[15:0]),
+	.W6END(Tile_X8Y4_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y4_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y4_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y4_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y4_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y4_NN4BEG[15:0]),
+	.Co(Tile_X7Y4_Co[0:0]),
+	.E1BEG(Tile_X7Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y4_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y4_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y4_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y4_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y4_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y4_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y5_UserCLKo),
+	.UserCLKo(Tile_X7Y4_UserCLKo),
+	.FrameData(Tile_X6Y4_FrameData_O), 
+	.FrameData_O(Tile_X7Y4_FrameData_O), 
+	.FrameStrobe(Tile_X7Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y4_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y4_LUT4AB (
+	.N1END(Tile_X9Y5_N1BEG[3:0]),
+	.N2MID(Tile_X9Y5_N2BEG[7:0]),
+	.N2END(Tile_X9Y5_N2BEGb[7:0]),
+	.N4END(Tile_X9Y5_N4BEG[15:0]),
+	.NN4END(Tile_X9Y5_NN4BEG[15:0]),
+	.Ci(Tile_X9Y5_Co[0:0]),
+	.E1END(Tile_X8Y4_E1BEG[3:0]),
+	.E2MID(Tile_X8Y4_E2BEG[7:0]),
+	.E2END(Tile_X8Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y4_EE4BEG[15:0]),
+	.E6END(Tile_X8Y4_E6BEG[11:0]),
+	.S1END(Tile_X9Y3_S1BEG[3:0]),
+	.S2MID(Tile_X9Y3_S2BEG[7:0]),
+	.S2END(Tile_X9Y3_S2BEGb[7:0]),
+	.S4END(Tile_X9Y3_S4BEG[15:0]),
+	.SS4END(Tile_X9Y3_SS4BEG[15:0]),
+	.W1END(Tile_X10Y4_W1BEG[3:0]),
+	.W2MID(Tile_X10Y4_W2BEG[7:0]),
+	.W2END(Tile_X10Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y4_WW4BEG[15:0]),
+	.W6END(Tile_X10Y4_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y4_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y4_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y4_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y4_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y4_NN4BEG[15:0]),
+	.Co(Tile_X9Y4_Co[0:0]),
+	.E1BEG(Tile_X9Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y4_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y4_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y4_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y4_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y4_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y4_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y5_UserCLKo),
+	.UserCLKo(Tile_X9Y4_UserCLKo),
+	.FrameData(Tile_X8Y4_FrameData_O), 
+	.FrameData_O(Tile_X9Y4_FrameData_O), 
+	.FrameStrobe(Tile_X9Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y4_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y4_LUT4AB (
+	.N1END(Tile_X10Y5_N1BEG[3:0]),
+	.N2MID(Tile_X10Y5_N2BEG[7:0]),
+	.N2END(Tile_X10Y5_N2BEGb[7:0]),
+	.N4END(Tile_X10Y5_N4BEG[15:0]),
+	.NN4END(Tile_X10Y5_NN4BEG[15:0]),
+	.Ci(Tile_X10Y5_Co[0:0]),
+	.E1END(Tile_X9Y4_E1BEG[3:0]),
+	.E2MID(Tile_X9Y4_E2BEG[7:0]),
+	.E2END(Tile_X9Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y4_EE4BEG[15:0]),
+	.E6END(Tile_X9Y4_E6BEG[11:0]),
+	.S1END(Tile_X10Y3_S1BEG[3:0]),
+	.S2MID(Tile_X10Y3_S2BEG[7:0]),
+	.S2END(Tile_X10Y3_S2BEGb[7:0]),
+	.S4END(Tile_X10Y3_S4BEG[15:0]),
+	.SS4END(Tile_X10Y3_SS4BEG[15:0]),
+	.W1END(Tile_X11Y4_W1BEG[3:0]),
+	.W2MID(Tile_X11Y4_W2BEG[7:0]),
+	.W2END(Tile_X11Y4_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y4_WW4BEG[15:0]),
+	.W6END(Tile_X11Y4_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y4_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y4_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y4_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y4_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y4_NN4BEG[15:0]),
+	.Co(Tile_X10Y4_Co[0:0]),
+	.E1BEG(Tile_X10Y4_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y4_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y4_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y4_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y4_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y4_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y4_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y4_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y4_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y4_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y5_UserCLKo),
+	.UserCLKo(Tile_X10Y4_UserCLKo),
+	.FrameData(Tile_X9Y4_FrameData_O), 
+	.FrameData_O(Tile_X10Y4_FrameData_O), 
+	.FrameStrobe(Tile_X10Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y4_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y4_E_CPU_IO (
+	.E1END(Tile_X10Y4_E1BEG[3:0]),
+	.E2MID(Tile_X10Y4_E2BEG[7:0]),
+	.E2END(Tile_X10Y4_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y4_EE4BEG[15:0]),
+	.E6END(Tile_X10Y4_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y4_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y4_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y4_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y4_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y4_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y4_OPA_I0),
+	.OPA_I1(Tile_X11Y4_OPA_I1),
+	.OPA_I2(Tile_X11Y4_OPA_I2),
+	.OPA_I3(Tile_X11Y4_OPA_I3),
+	.UserCLK(Tile_X11Y5_UserCLKo),
+	.OPB_I0(Tile_X11Y4_OPB_I0),
+	.OPB_I1(Tile_X11Y4_OPB_I1),
+	.OPB_I2(Tile_X11Y4_OPB_I2),
+	.OPB_I3(Tile_X11Y4_OPB_I3),
+	.RES0_O0(Tile_X11Y4_RES0_O0),
+	.RES0_O1(Tile_X11Y4_RES0_O1),
+	.RES0_O2(Tile_X11Y4_RES0_O2),
+	.RES0_O3(Tile_X11Y4_RES0_O3),
+	.RES1_O0(Tile_X11Y4_RES1_O0),
+	.RES1_O1(Tile_X11Y4_RES1_O1),
+	.RES1_O2(Tile_X11Y4_RES1_O2),
+	.RES1_O3(Tile_X11Y4_RES1_O3),
+	.RES2_O0(Tile_X11Y4_RES2_O0),
+	.RES2_O1(Tile_X11Y4_RES2_O1),
+	.RES2_O2(Tile_X11Y4_RES2_O2),
+	.RES2_O3(Tile_X11Y4_RES2_O3),
+	.UserCLKo(Tile_X11Y4_UserCLKo),
+	.FrameData(Tile_X10Y4_FrameData_O), 
+	.FrameData_O(Tile_X11Y4_FrameData_O), 
+	.FrameStrobe(Tile_X11Y5_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y4_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y5_W_CPU_IO (
+	.W1END(Tile_X4Y5_W1BEG[3:0]),
+	.W2MID(Tile_X4Y5_W2BEG[7:0]),
+	.W2END(Tile_X4Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y5_WW4BEG[15:0]),
+	.W6END(Tile_X4Y5_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y5_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y5_OPA_I0),
+	.OPA_I1(Tile_X3Y5_OPA_I1),
+	.OPA_I2(Tile_X3Y5_OPA_I2),
+	.OPA_I3(Tile_X3Y5_OPA_I3),
+	.UserCLK(Tile_X3Y6_UserCLKo),
+	.OPB_I0(Tile_X3Y5_OPB_I0),
+	.OPB_I1(Tile_X3Y5_OPB_I1),
+	.OPB_I2(Tile_X3Y5_OPB_I2),
+	.OPB_I3(Tile_X3Y5_OPB_I3),
+	.RES0_O0(Tile_X3Y5_RES0_O0),
+	.RES0_O1(Tile_X3Y5_RES0_O1),
+	.RES0_O2(Tile_X3Y5_RES0_O2),
+	.RES0_O3(Tile_X3Y5_RES0_O3),
+	.RES1_O0(Tile_X3Y5_RES1_O0),
+	.RES1_O1(Tile_X3Y5_RES1_O1),
+	.RES1_O2(Tile_X3Y5_RES1_O2),
+	.RES1_O3(Tile_X3Y5_RES1_O3),
+	.RES2_O0(Tile_X3Y5_RES2_O0),
+	.RES2_O1(Tile_X3Y5_RES2_O1),
+	.RES2_O2(Tile_X3Y5_RES2_O2),
+	.RES2_O3(Tile_X3Y5_RES2_O3),
+	.UserCLKo(Tile_X3Y5_UserCLKo),
+	.FrameData(Tile_Y5_FrameData), 
+	.FrameData_O(Tile_X3Y5_FrameData_O), 
+	.FrameStrobe(Tile_X3Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y5_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y5_LUT4AB (
+	.N1END(Tile_X5Y6_N1BEG[3:0]),
+	.N2MID(Tile_X5Y6_N2BEG[7:0]),
+	.N2END(Tile_X5Y6_N2BEGb[7:0]),
+	.N4END(Tile_X5Y6_N4BEG[15:0]),
+	.NN4END(Tile_X5Y6_NN4BEG[15:0]),
+	.Ci(Tile_X5Y6_Co[0:0]),
+	.E1END(Tile_X4Y5_E1BEG[3:0]),
+	.E2MID(Tile_X4Y5_E2BEG[7:0]),
+	.E2END(Tile_X4Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y5_EE4BEG[15:0]),
+	.E6END(Tile_X4Y5_E6BEG[11:0]),
+	.S1END(Tile_X5Y4_S1BEG[3:0]),
+	.S2MID(Tile_X5Y4_S2BEG[7:0]),
+	.S2END(Tile_X5Y4_S2BEGb[7:0]),
+	.S4END(Tile_X5Y4_S4BEG[15:0]),
+	.SS4END(Tile_X5Y4_SS4BEG[15:0]),
+	.W1END(Tile_X6Y5_W1BEG[3:0]),
+	.W2MID(Tile_X6Y5_W2BEG[7:0]),
+	.W2END(Tile_X6Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y5_WW4BEG[15:0]),
+	.W6END(Tile_X6Y5_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y5_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y5_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y5_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y5_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y5_NN4BEG[15:0]),
+	.Co(Tile_X5Y5_Co[0:0]),
+	.E1BEG(Tile_X5Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y5_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y5_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y5_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y5_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y5_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y5_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y6_UserCLKo),
+	.UserCLKo(Tile_X5Y5_UserCLKo),
+	.FrameData(Tile_X4Y5_FrameData_O), 
+	.FrameData_O(Tile_X5Y5_FrameData_O), 
+	.FrameStrobe(Tile_X5Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y5_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y5_LUT4AB (
+	.N1END(Tile_X6Y6_N1BEG[3:0]),
+	.N2MID(Tile_X6Y6_N2BEG[7:0]),
+	.N2END(Tile_X6Y6_N2BEGb[7:0]),
+	.N4END(Tile_X6Y6_N4BEG[15:0]),
+	.NN4END(Tile_X6Y6_NN4BEG[15:0]),
+	.Ci(Tile_X6Y6_Co[0:0]),
+	.E1END(Tile_X5Y5_E1BEG[3:0]),
+	.E2MID(Tile_X5Y5_E2BEG[7:0]),
+	.E2END(Tile_X5Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y5_EE4BEG[15:0]),
+	.E6END(Tile_X5Y5_E6BEG[11:0]),
+	.S1END(Tile_X6Y4_S1BEG[3:0]),
+	.S2MID(Tile_X6Y4_S2BEG[7:0]),
+	.S2END(Tile_X6Y4_S2BEGb[7:0]),
+	.S4END(Tile_X6Y4_S4BEG[15:0]),
+	.SS4END(Tile_X6Y4_SS4BEG[15:0]),
+	.W1END(Tile_X7Y5_W1BEG[3:0]),
+	.W2MID(Tile_X7Y5_W2BEG[7:0]),
+	.W2END(Tile_X7Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y5_WW4BEG[15:0]),
+	.W6END(Tile_X7Y5_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y5_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y5_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y5_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y5_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y5_NN4BEG[15:0]),
+	.Co(Tile_X6Y5_Co[0:0]),
+	.E1BEG(Tile_X6Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y5_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y5_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y5_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y5_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y5_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y5_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y6_UserCLKo),
+	.UserCLKo(Tile_X6Y5_UserCLKo),
+	.FrameData(Tile_X5Y5_FrameData_O), 
+	.FrameData_O(Tile_X6Y5_FrameData_O), 
+	.FrameStrobe(Tile_X6Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y5_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y5_LUT4AB (
+	.N1END(Tile_X7Y6_N1BEG[3:0]),
+	.N2MID(Tile_X7Y6_N2BEG[7:0]),
+	.N2END(Tile_X7Y6_N2BEGb[7:0]),
+	.N4END(Tile_X7Y6_N4BEG[15:0]),
+	.NN4END(Tile_X7Y6_NN4BEG[15:0]),
+	.Ci(Tile_X7Y6_Co[0:0]),
+	.E1END(Tile_X6Y5_E1BEG[3:0]),
+	.E2MID(Tile_X6Y5_E2BEG[7:0]),
+	.E2END(Tile_X6Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y5_EE4BEG[15:0]),
+	.E6END(Tile_X6Y5_E6BEG[11:0]),
+	.S1END(Tile_X7Y4_S1BEG[3:0]),
+	.S2MID(Tile_X7Y4_S2BEG[7:0]),
+	.S2END(Tile_X7Y4_S2BEGb[7:0]),
+	.S4END(Tile_X7Y4_S4BEG[15:0]),
+	.SS4END(Tile_X7Y4_SS4BEG[15:0]),
+	.W1END(Tile_X8Y5_W1BEG[3:0]),
+	.W2MID(Tile_X8Y5_W2BEG[7:0]),
+	.W2END(Tile_X8Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y5_WW4BEG[15:0]),
+	.W6END(Tile_X8Y5_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y5_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y5_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y5_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y5_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y5_NN4BEG[15:0]),
+	.Co(Tile_X7Y5_Co[0:0]),
+	.E1BEG(Tile_X7Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y5_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y5_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y5_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y5_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y5_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y5_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y6_UserCLKo),
+	.UserCLKo(Tile_X7Y5_UserCLKo),
+	.FrameData(Tile_X6Y5_FrameData_O), 
+	.FrameData_O(Tile_X7Y5_FrameData_O), 
+	.FrameStrobe(Tile_X7Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y5_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y5_LUT4AB (
+	.N1END(Tile_X9Y6_N1BEG[3:0]),
+	.N2MID(Tile_X9Y6_N2BEG[7:0]),
+	.N2END(Tile_X9Y6_N2BEGb[7:0]),
+	.N4END(Tile_X9Y6_N4BEG[15:0]),
+	.NN4END(Tile_X9Y6_NN4BEG[15:0]),
+	.Ci(Tile_X9Y6_Co[0:0]),
+	.E1END(Tile_X8Y5_E1BEG[3:0]),
+	.E2MID(Tile_X8Y5_E2BEG[7:0]),
+	.E2END(Tile_X8Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y5_EE4BEG[15:0]),
+	.E6END(Tile_X8Y5_E6BEG[11:0]),
+	.S1END(Tile_X9Y4_S1BEG[3:0]),
+	.S2MID(Tile_X9Y4_S2BEG[7:0]),
+	.S2END(Tile_X9Y4_S2BEGb[7:0]),
+	.S4END(Tile_X9Y4_S4BEG[15:0]),
+	.SS4END(Tile_X9Y4_SS4BEG[15:0]),
+	.W1END(Tile_X10Y5_W1BEG[3:0]),
+	.W2MID(Tile_X10Y5_W2BEG[7:0]),
+	.W2END(Tile_X10Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y5_WW4BEG[15:0]),
+	.W6END(Tile_X10Y5_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y5_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y5_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y5_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y5_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y5_NN4BEG[15:0]),
+	.Co(Tile_X9Y5_Co[0:0]),
+	.E1BEG(Tile_X9Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y5_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y5_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y5_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y5_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y5_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y5_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y6_UserCLKo),
+	.UserCLKo(Tile_X9Y5_UserCLKo),
+	.FrameData(Tile_X8Y5_FrameData_O), 
+	.FrameData_O(Tile_X9Y5_FrameData_O), 
+	.FrameStrobe(Tile_X9Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y5_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y5_LUT4AB (
+	.N1END(Tile_X10Y6_N1BEG[3:0]),
+	.N2MID(Tile_X10Y6_N2BEG[7:0]),
+	.N2END(Tile_X10Y6_N2BEGb[7:0]),
+	.N4END(Tile_X10Y6_N4BEG[15:0]),
+	.NN4END(Tile_X10Y6_NN4BEG[15:0]),
+	.Ci(Tile_X10Y6_Co[0:0]),
+	.E1END(Tile_X9Y5_E1BEG[3:0]),
+	.E2MID(Tile_X9Y5_E2BEG[7:0]),
+	.E2END(Tile_X9Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y5_EE4BEG[15:0]),
+	.E6END(Tile_X9Y5_E6BEG[11:0]),
+	.S1END(Tile_X10Y4_S1BEG[3:0]),
+	.S2MID(Tile_X10Y4_S2BEG[7:0]),
+	.S2END(Tile_X10Y4_S2BEGb[7:0]),
+	.S4END(Tile_X10Y4_S4BEG[15:0]),
+	.SS4END(Tile_X10Y4_SS4BEG[15:0]),
+	.W1END(Tile_X11Y5_W1BEG[3:0]),
+	.W2MID(Tile_X11Y5_W2BEG[7:0]),
+	.W2END(Tile_X11Y5_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y5_WW4BEG[15:0]),
+	.W6END(Tile_X11Y5_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y5_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y5_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y5_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y5_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y5_NN4BEG[15:0]),
+	.Co(Tile_X10Y5_Co[0:0]),
+	.E1BEG(Tile_X10Y5_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y5_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y5_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y5_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y5_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y5_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y5_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y5_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y5_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y5_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y6_UserCLKo),
+	.UserCLKo(Tile_X10Y5_UserCLKo),
+	.FrameData(Tile_X9Y5_FrameData_O), 
+	.FrameData_O(Tile_X10Y5_FrameData_O), 
+	.FrameStrobe(Tile_X10Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y5_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y5_E_CPU_IO (
+	.E1END(Tile_X10Y5_E1BEG[3:0]),
+	.E2MID(Tile_X10Y5_E2BEG[7:0]),
+	.E2END(Tile_X10Y5_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y5_EE4BEG[15:0]),
+	.E6END(Tile_X10Y5_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y5_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y5_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y5_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y5_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y5_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y5_OPA_I0),
+	.OPA_I1(Tile_X11Y5_OPA_I1),
+	.OPA_I2(Tile_X11Y5_OPA_I2),
+	.OPA_I3(Tile_X11Y5_OPA_I3),
+	.UserCLK(Tile_X11Y6_UserCLKo),
+	.OPB_I0(Tile_X11Y5_OPB_I0),
+	.OPB_I1(Tile_X11Y5_OPB_I1),
+	.OPB_I2(Tile_X11Y5_OPB_I2),
+	.OPB_I3(Tile_X11Y5_OPB_I3),
+	.RES0_O0(Tile_X11Y5_RES0_O0),
+	.RES0_O1(Tile_X11Y5_RES0_O1),
+	.RES0_O2(Tile_X11Y5_RES0_O2),
+	.RES0_O3(Tile_X11Y5_RES0_O3),
+	.RES1_O0(Tile_X11Y5_RES1_O0),
+	.RES1_O1(Tile_X11Y5_RES1_O1),
+	.RES1_O2(Tile_X11Y5_RES1_O2),
+	.RES1_O3(Tile_X11Y5_RES1_O3),
+	.RES2_O0(Tile_X11Y5_RES2_O0),
+	.RES2_O1(Tile_X11Y5_RES2_O1),
+	.RES2_O2(Tile_X11Y5_RES2_O2),
+	.RES2_O3(Tile_X11Y5_RES2_O3),
+	.UserCLKo(Tile_X11Y5_UserCLKo),
+	.FrameData(Tile_X10Y5_FrameData_O), 
+	.FrameData_O(Tile_X11Y5_FrameData_O), 
+	.FrameStrobe(Tile_X11Y6_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y5_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y6_W_CPU_IO (
+	.W1END(Tile_X4Y6_W1BEG[3:0]),
+	.W2MID(Tile_X4Y6_W2BEG[7:0]),
+	.W2END(Tile_X4Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y6_WW4BEG[15:0]),
+	.W6END(Tile_X4Y6_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y6_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y6_OPA_I0),
+	.OPA_I1(Tile_X3Y6_OPA_I1),
+	.OPA_I2(Tile_X3Y6_OPA_I2),
+	.OPA_I3(Tile_X3Y6_OPA_I3),
+	.UserCLK(Tile_X3Y7_UserCLKo),
+	.OPB_I0(Tile_X3Y6_OPB_I0),
+	.OPB_I1(Tile_X3Y6_OPB_I1),
+	.OPB_I2(Tile_X3Y6_OPB_I2),
+	.OPB_I3(Tile_X3Y6_OPB_I3),
+	.RES0_O0(Tile_X3Y6_RES0_O0),
+	.RES0_O1(Tile_X3Y6_RES0_O1),
+	.RES0_O2(Tile_X3Y6_RES0_O2),
+	.RES0_O3(Tile_X3Y6_RES0_O3),
+	.RES1_O0(Tile_X3Y6_RES1_O0),
+	.RES1_O1(Tile_X3Y6_RES1_O1),
+	.RES1_O2(Tile_X3Y6_RES1_O2),
+	.RES1_O3(Tile_X3Y6_RES1_O3),
+	.RES2_O0(Tile_X3Y6_RES2_O0),
+	.RES2_O1(Tile_X3Y6_RES2_O1),
+	.RES2_O2(Tile_X3Y6_RES2_O2),
+	.RES2_O3(Tile_X3Y6_RES2_O3),
+	.UserCLKo(Tile_X3Y6_UserCLKo),
+	.FrameData(Tile_Y6_FrameData), 
+	.FrameData_O(Tile_X3Y6_FrameData_O), 
+	.FrameStrobe(Tile_X3Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y6_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y6_LUT4AB (
+	.N1END(Tile_X5Y7_N1BEG[3:0]),
+	.N2MID(Tile_X5Y7_N2BEG[7:0]),
+	.N2END(Tile_X5Y7_N2BEGb[7:0]),
+	.N4END(Tile_X5Y7_N4BEG[15:0]),
+	.NN4END(Tile_X5Y7_NN4BEG[15:0]),
+	.Ci(Tile_X5Y7_Co[0:0]),
+	.E1END(Tile_X4Y6_E1BEG[3:0]),
+	.E2MID(Tile_X4Y6_E2BEG[7:0]),
+	.E2END(Tile_X4Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y6_EE4BEG[15:0]),
+	.E6END(Tile_X4Y6_E6BEG[11:0]),
+	.S1END(Tile_X5Y5_S1BEG[3:0]),
+	.S2MID(Tile_X5Y5_S2BEG[7:0]),
+	.S2END(Tile_X5Y5_S2BEGb[7:0]),
+	.S4END(Tile_X5Y5_S4BEG[15:0]),
+	.SS4END(Tile_X5Y5_SS4BEG[15:0]),
+	.W1END(Tile_X6Y6_W1BEG[3:0]),
+	.W2MID(Tile_X6Y6_W2BEG[7:0]),
+	.W2END(Tile_X6Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y6_WW4BEG[15:0]),
+	.W6END(Tile_X6Y6_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y6_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y6_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y6_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y6_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y6_NN4BEG[15:0]),
+	.Co(Tile_X5Y6_Co[0:0]),
+	.E1BEG(Tile_X5Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y6_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y6_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y6_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y6_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y6_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y6_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y7_UserCLKo),
+	.UserCLKo(Tile_X5Y6_UserCLKo),
+	.FrameData(Tile_X4Y6_FrameData_O), 
+	.FrameData_O(Tile_X5Y6_FrameData_O), 
+	.FrameStrobe(Tile_X5Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y6_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y6_LUT4AB (
+	.N1END(Tile_X6Y7_N1BEG[3:0]),
+	.N2MID(Tile_X6Y7_N2BEG[7:0]),
+	.N2END(Tile_X6Y7_N2BEGb[7:0]),
+	.N4END(Tile_X6Y7_N4BEG[15:0]),
+	.NN4END(Tile_X6Y7_NN4BEG[15:0]),
+	.Ci(Tile_X6Y7_Co[0:0]),
+	.E1END(Tile_X5Y6_E1BEG[3:0]),
+	.E2MID(Tile_X5Y6_E2BEG[7:0]),
+	.E2END(Tile_X5Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y6_EE4BEG[15:0]),
+	.E6END(Tile_X5Y6_E6BEG[11:0]),
+	.S1END(Tile_X6Y5_S1BEG[3:0]),
+	.S2MID(Tile_X6Y5_S2BEG[7:0]),
+	.S2END(Tile_X6Y5_S2BEGb[7:0]),
+	.S4END(Tile_X6Y5_S4BEG[15:0]),
+	.SS4END(Tile_X6Y5_SS4BEG[15:0]),
+	.W1END(Tile_X7Y6_W1BEG[3:0]),
+	.W2MID(Tile_X7Y6_W2BEG[7:0]),
+	.W2END(Tile_X7Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y6_WW4BEG[15:0]),
+	.W6END(Tile_X7Y6_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y6_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y6_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y6_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y6_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y6_NN4BEG[15:0]),
+	.Co(Tile_X6Y6_Co[0:0]),
+	.E1BEG(Tile_X6Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y6_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y6_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y6_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y6_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y6_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y6_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y7_UserCLKo),
+	.UserCLKo(Tile_X6Y6_UserCLKo),
+	.FrameData(Tile_X5Y6_FrameData_O), 
+	.FrameData_O(Tile_X6Y6_FrameData_O), 
+	.FrameStrobe(Tile_X6Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y6_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y6_LUT4AB (
+	.N1END(Tile_X7Y7_N1BEG[3:0]),
+	.N2MID(Tile_X7Y7_N2BEG[7:0]),
+	.N2END(Tile_X7Y7_N2BEGb[7:0]),
+	.N4END(Tile_X7Y7_N4BEG[15:0]),
+	.NN4END(Tile_X7Y7_NN4BEG[15:0]),
+	.Ci(Tile_X7Y7_Co[0:0]),
+	.E1END(Tile_X6Y6_E1BEG[3:0]),
+	.E2MID(Tile_X6Y6_E2BEG[7:0]),
+	.E2END(Tile_X6Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y6_EE4BEG[15:0]),
+	.E6END(Tile_X6Y6_E6BEG[11:0]),
+	.S1END(Tile_X7Y5_S1BEG[3:0]),
+	.S2MID(Tile_X7Y5_S2BEG[7:0]),
+	.S2END(Tile_X7Y5_S2BEGb[7:0]),
+	.S4END(Tile_X7Y5_S4BEG[15:0]),
+	.SS4END(Tile_X7Y5_SS4BEG[15:0]),
+	.W1END(Tile_X8Y6_W1BEG[3:0]),
+	.W2MID(Tile_X8Y6_W2BEG[7:0]),
+	.W2END(Tile_X8Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y6_WW4BEG[15:0]),
+	.W6END(Tile_X8Y6_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y6_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y6_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y6_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y6_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y6_NN4BEG[15:0]),
+	.Co(Tile_X7Y6_Co[0:0]),
+	.E1BEG(Tile_X7Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y6_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y6_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y6_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y6_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y6_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y6_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y7_UserCLKo),
+	.UserCLKo(Tile_X7Y6_UserCLKo),
+	.FrameData(Tile_X6Y6_FrameData_O), 
+	.FrameData_O(Tile_X7Y6_FrameData_O), 
+	.FrameStrobe(Tile_X7Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y6_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y6_LUT4AB (
+	.N1END(Tile_X9Y7_N1BEG[3:0]),
+	.N2MID(Tile_X9Y7_N2BEG[7:0]),
+	.N2END(Tile_X9Y7_N2BEGb[7:0]),
+	.N4END(Tile_X9Y7_N4BEG[15:0]),
+	.NN4END(Tile_X9Y7_NN4BEG[15:0]),
+	.Ci(Tile_X9Y7_Co[0:0]),
+	.E1END(Tile_X8Y6_E1BEG[3:0]),
+	.E2MID(Tile_X8Y6_E2BEG[7:0]),
+	.E2END(Tile_X8Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y6_EE4BEG[15:0]),
+	.E6END(Tile_X8Y6_E6BEG[11:0]),
+	.S1END(Tile_X9Y5_S1BEG[3:0]),
+	.S2MID(Tile_X9Y5_S2BEG[7:0]),
+	.S2END(Tile_X9Y5_S2BEGb[7:0]),
+	.S4END(Tile_X9Y5_S4BEG[15:0]),
+	.SS4END(Tile_X9Y5_SS4BEG[15:0]),
+	.W1END(Tile_X10Y6_W1BEG[3:0]),
+	.W2MID(Tile_X10Y6_W2BEG[7:0]),
+	.W2END(Tile_X10Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y6_WW4BEG[15:0]),
+	.W6END(Tile_X10Y6_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y6_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y6_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y6_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y6_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y6_NN4BEG[15:0]),
+	.Co(Tile_X9Y6_Co[0:0]),
+	.E1BEG(Tile_X9Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y6_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y6_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y6_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y6_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y6_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y6_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y7_UserCLKo),
+	.UserCLKo(Tile_X9Y6_UserCLKo),
+	.FrameData(Tile_X8Y6_FrameData_O), 
+	.FrameData_O(Tile_X9Y6_FrameData_O), 
+	.FrameStrobe(Tile_X9Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y6_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y6_LUT4AB (
+	.N1END(Tile_X10Y7_N1BEG[3:0]),
+	.N2MID(Tile_X10Y7_N2BEG[7:0]),
+	.N2END(Tile_X10Y7_N2BEGb[7:0]),
+	.N4END(Tile_X10Y7_N4BEG[15:0]),
+	.NN4END(Tile_X10Y7_NN4BEG[15:0]),
+	.Ci(Tile_X10Y7_Co[0:0]),
+	.E1END(Tile_X9Y6_E1BEG[3:0]),
+	.E2MID(Tile_X9Y6_E2BEG[7:0]),
+	.E2END(Tile_X9Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y6_EE4BEG[15:0]),
+	.E6END(Tile_X9Y6_E6BEG[11:0]),
+	.S1END(Tile_X10Y5_S1BEG[3:0]),
+	.S2MID(Tile_X10Y5_S2BEG[7:0]),
+	.S2END(Tile_X10Y5_S2BEGb[7:0]),
+	.S4END(Tile_X10Y5_S4BEG[15:0]),
+	.SS4END(Tile_X10Y5_SS4BEG[15:0]),
+	.W1END(Tile_X11Y6_W1BEG[3:0]),
+	.W2MID(Tile_X11Y6_W2BEG[7:0]),
+	.W2END(Tile_X11Y6_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y6_WW4BEG[15:0]),
+	.W6END(Tile_X11Y6_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y6_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y6_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y6_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y6_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y6_NN4BEG[15:0]),
+	.Co(Tile_X10Y6_Co[0:0]),
+	.E1BEG(Tile_X10Y6_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y6_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y6_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y6_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y6_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y6_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y6_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y6_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y6_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y6_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y7_UserCLKo),
+	.UserCLKo(Tile_X10Y6_UserCLKo),
+	.FrameData(Tile_X9Y6_FrameData_O), 
+	.FrameData_O(Tile_X10Y6_FrameData_O), 
+	.FrameStrobe(Tile_X10Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y6_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y6_E_CPU_IO (
+	.E1END(Tile_X10Y6_E1BEG[3:0]),
+	.E2MID(Tile_X10Y6_E2BEG[7:0]),
+	.E2END(Tile_X10Y6_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y6_EE4BEG[15:0]),
+	.E6END(Tile_X10Y6_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y6_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y6_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y6_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y6_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y6_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y6_OPA_I0),
+	.OPA_I1(Tile_X11Y6_OPA_I1),
+	.OPA_I2(Tile_X11Y6_OPA_I2),
+	.OPA_I3(Tile_X11Y6_OPA_I3),
+	.UserCLK(Tile_X11Y7_UserCLKo),
+	.OPB_I0(Tile_X11Y6_OPB_I0),
+	.OPB_I1(Tile_X11Y6_OPB_I1),
+	.OPB_I2(Tile_X11Y6_OPB_I2),
+	.OPB_I3(Tile_X11Y6_OPB_I3),
+	.RES0_O0(Tile_X11Y6_RES0_O0),
+	.RES0_O1(Tile_X11Y6_RES0_O1),
+	.RES0_O2(Tile_X11Y6_RES0_O2),
+	.RES0_O3(Tile_X11Y6_RES0_O3),
+	.RES1_O0(Tile_X11Y6_RES1_O0),
+	.RES1_O1(Tile_X11Y6_RES1_O1),
+	.RES1_O2(Tile_X11Y6_RES1_O2),
+	.RES1_O3(Tile_X11Y6_RES1_O3),
+	.RES2_O0(Tile_X11Y6_RES2_O0),
+	.RES2_O1(Tile_X11Y6_RES2_O1),
+	.RES2_O2(Tile_X11Y6_RES2_O2),
+	.RES2_O3(Tile_X11Y6_RES2_O3),
+	.UserCLKo(Tile_X11Y6_UserCLKo),
+	.FrameData(Tile_X10Y6_FrameData_O), 
+	.FrameData_O(Tile_X11Y6_FrameData_O), 
+	.FrameStrobe(Tile_X11Y7_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y6_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y7_W_CPU_IO (
+	.W1END(Tile_X4Y7_W1BEG[3:0]),
+	.W2MID(Tile_X4Y7_W2BEG[7:0]),
+	.W2END(Tile_X4Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y7_WW4BEG[15:0]),
+	.W6END(Tile_X4Y7_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y7_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y7_OPA_I0),
+	.OPA_I1(Tile_X3Y7_OPA_I1),
+	.OPA_I2(Tile_X3Y7_OPA_I2),
+	.OPA_I3(Tile_X3Y7_OPA_I3),
+	.UserCLK(Tile_X3Y8_UserCLKo),
+	.OPB_I0(Tile_X3Y7_OPB_I0),
+	.OPB_I1(Tile_X3Y7_OPB_I1),
+	.OPB_I2(Tile_X3Y7_OPB_I2),
+	.OPB_I3(Tile_X3Y7_OPB_I3),
+	.RES0_O0(Tile_X3Y7_RES0_O0),
+	.RES0_O1(Tile_X3Y7_RES0_O1),
+	.RES0_O2(Tile_X3Y7_RES0_O2),
+	.RES0_O3(Tile_X3Y7_RES0_O3),
+	.RES1_O0(Tile_X3Y7_RES1_O0),
+	.RES1_O1(Tile_X3Y7_RES1_O1),
+	.RES1_O2(Tile_X3Y7_RES1_O2),
+	.RES1_O3(Tile_X3Y7_RES1_O3),
+	.RES2_O0(Tile_X3Y7_RES2_O0),
+	.RES2_O1(Tile_X3Y7_RES2_O1),
+	.RES2_O2(Tile_X3Y7_RES2_O2),
+	.RES2_O3(Tile_X3Y7_RES2_O3),
+	.UserCLKo(Tile_X3Y7_UserCLKo),
+	.FrameData(Tile_Y7_FrameData), 
+	.FrameData_O(Tile_X3Y7_FrameData_O), 
+	.FrameStrobe(Tile_X3Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y7_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y7_LUT4AB (
+	.N1END(Tile_X5Y8_N1BEG[3:0]),
+	.N2MID(Tile_X5Y8_N2BEG[7:0]),
+	.N2END(Tile_X5Y8_N2BEGb[7:0]),
+	.N4END(Tile_X5Y8_N4BEG[15:0]),
+	.NN4END(Tile_X5Y8_NN4BEG[15:0]),
+	.Ci(Tile_X5Y8_Co[0:0]),
+	.E1END(Tile_X4Y7_E1BEG[3:0]),
+	.E2MID(Tile_X4Y7_E2BEG[7:0]),
+	.E2END(Tile_X4Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y7_EE4BEG[15:0]),
+	.E6END(Tile_X4Y7_E6BEG[11:0]),
+	.S1END(Tile_X5Y6_S1BEG[3:0]),
+	.S2MID(Tile_X5Y6_S2BEG[7:0]),
+	.S2END(Tile_X5Y6_S2BEGb[7:0]),
+	.S4END(Tile_X5Y6_S4BEG[15:0]),
+	.SS4END(Tile_X5Y6_SS4BEG[15:0]),
+	.W1END(Tile_X6Y7_W1BEG[3:0]),
+	.W2MID(Tile_X6Y7_W2BEG[7:0]),
+	.W2END(Tile_X6Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y7_WW4BEG[15:0]),
+	.W6END(Tile_X6Y7_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y7_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y7_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y7_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y7_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y7_NN4BEG[15:0]),
+	.Co(Tile_X5Y7_Co[0:0]),
+	.E1BEG(Tile_X5Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y7_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y7_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y7_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y7_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y7_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y7_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y8_UserCLKo),
+	.UserCLKo(Tile_X5Y7_UserCLKo),
+	.FrameData(Tile_X4Y7_FrameData_O), 
+	.FrameData_O(Tile_X5Y7_FrameData_O), 
+	.FrameStrobe(Tile_X5Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y7_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y7_LUT4AB (
+	.N1END(Tile_X6Y8_N1BEG[3:0]),
+	.N2MID(Tile_X6Y8_N2BEG[7:0]),
+	.N2END(Tile_X6Y8_N2BEGb[7:0]),
+	.N4END(Tile_X6Y8_N4BEG[15:0]),
+	.NN4END(Tile_X6Y8_NN4BEG[15:0]),
+	.Ci(Tile_X6Y8_Co[0:0]),
+	.E1END(Tile_X5Y7_E1BEG[3:0]),
+	.E2MID(Tile_X5Y7_E2BEG[7:0]),
+	.E2END(Tile_X5Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y7_EE4BEG[15:0]),
+	.E6END(Tile_X5Y7_E6BEG[11:0]),
+	.S1END(Tile_X6Y6_S1BEG[3:0]),
+	.S2MID(Tile_X6Y6_S2BEG[7:0]),
+	.S2END(Tile_X6Y6_S2BEGb[7:0]),
+	.S4END(Tile_X6Y6_S4BEG[15:0]),
+	.SS4END(Tile_X6Y6_SS4BEG[15:0]),
+	.W1END(Tile_X7Y7_W1BEG[3:0]),
+	.W2MID(Tile_X7Y7_W2BEG[7:0]),
+	.W2END(Tile_X7Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y7_WW4BEG[15:0]),
+	.W6END(Tile_X7Y7_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y7_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y7_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y7_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y7_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y7_NN4BEG[15:0]),
+	.Co(Tile_X6Y7_Co[0:0]),
+	.E1BEG(Tile_X6Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y7_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y7_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y7_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y7_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y7_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y7_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y8_UserCLKo),
+	.UserCLKo(Tile_X6Y7_UserCLKo),
+	.FrameData(Tile_X5Y7_FrameData_O), 
+	.FrameData_O(Tile_X6Y7_FrameData_O), 
+	.FrameStrobe(Tile_X6Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y7_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y7_LUT4AB (
+	.N1END(Tile_X7Y8_N1BEG[3:0]),
+	.N2MID(Tile_X7Y8_N2BEG[7:0]),
+	.N2END(Tile_X7Y8_N2BEGb[7:0]),
+	.N4END(Tile_X7Y8_N4BEG[15:0]),
+	.NN4END(Tile_X7Y8_NN4BEG[15:0]),
+	.Ci(Tile_X7Y8_Co[0:0]),
+	.E1END(Tile_X6Y7_E1BEG[3:0]),
+	.E2MID(Tile_X6Y7_E2BEG[7:0]),
+	.E2END(Tile_X6Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y7_EE4BEG[15:0]),
+	.E6END(Tile_X6Y7_E6BEG[11:0]),
+	.S1END(Tile_X7Y6_S1BEG[3:0]),
+	.S2MID(Tile_X7Y6_S2BEG[7:0]),
+	.S2END(Tile_X7Y6_S2BEGb[7:0]),
+	.S4END(Tile_X7Y6_S4BEG[15:0]),
+	.SS4END(Tile_X7Y6_SS4BEG[15:0]),
+	.W1END(Tile_X8Y7_W1BEG[3:0]),
+	.W2MID(Tile_X8Y7_W2BEG[7:0]),
+	.W2END(Tile_X8Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y7_WW4BEG[15:0]),
+	.W6END(Tile_X8Y7_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y7_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y7_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y7_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y7_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y7_NN4BEG[15:0]),
+	.Co(Tile_X7Y7_Co[0:0]),
+	.E1BEG(Tile_X7Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y7_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y7_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y7_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y7_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y7_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y7_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y8_UserCLKo),
+	.UserCLKo(Tile_X7Y7_UserCLKo),
+	.FrameData(Tile_X6Y7_FrameData_O), 
+	.FrameData_O(Tile_X7Y7_FrameData_O), 
+	.FrameStrobe(Tile_X7Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y7_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y7_LUT4AB (
+	.N1END(Tile_X9Y8_N1BEG[3:0]),
+	.N2MID(Tile_X9Y8_N2BEG[7:0]),
+	.N2END(Tile_X9Y8_N2BEGb[7:0]),
+	.N4END(Tile_X9Y8_N4BEG[15:0]),
+	.NN4END(Tile_X9Y8_NN4BEG[15:0]),
+	.Ci(Tile_X9Y8_Co[0:0]),
+	.E1END(Tile_X8Y7_E1BEG[3:0]),
+	.E2MID(Tile_X8Y7_E2BEG[7:0]),
+	.E2END(Tile_X8Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y7_EE4BEG[15:0]),
+	.E6END(Tile_X8Y7_E6BEG[11:0]),
+	.S1END(Tile_X9Y6_S1BEG[3:0]),
+	.S2MID(Tile_X9Y6_S2BEG[7:0]),
+	.S2END(Tile_X9Y6_S2BEGb[7:0]),
+	.S4END(Tile_X9Y6_S4BEG[15:0]),
+	.SS4END(Tile_X9Y6_SS4BEG[15:0]),
+	.W1END(Tile_X10Y7_W1BEG[3:0]),
+	.W2MID(Tile_X10Y7_W2BEG[7:0]),
+	.W2END(Tile_X10Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y7_WW4BEG[15:0]),
+	.W6END(Tile_X10Y7_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y7_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y7_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y7_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y7_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y7_NN4BEG[15:0]),
+	.Co(Tile_X9Y7_Co[0:0]),
+	.E1BEG(Tile_X9Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y7_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y7_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y7_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y7_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y7_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y7_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y8_UserCLKo),
+	.UserCLKo(Tile_X9Y7_UserCLKo),
+	.FrameData(Tile_X8Y7_FrameData_O), 
+	.FrameData_O(Tile_X9Y7_FrameData_O), 
+	.FrameStrobe(Tile_X9Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y7_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y7_LUT4AB (
+	.N1END(Tile_X10Y8_N1BEG[3:0]),
+	.N2MID(Tile_X10Y8_N2BEG[7:0]),
+	.N2END(Tile_X10Y8_N2BEGb[7:0]),
+	.N4END(Tile_X10Y8_N4BEG[15:0]),
+	.NN4END(Tile_X10Y8_NN4BEG[15:0]),
+	.Ci(Tile_X10Y8_Co[0:0]),
+	.E1END(Tile_X9Y7_E1BEG[3:0]),
+	.E2MID(Tile_X9Y7_E2BEG[7:0]),
+	.E2END(Tile_X9Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y7_EE4BEG[15:0]),
+	.E6END(Tile_X9Y7_E6BEG[11:0]),
+	.S1END(Tile_X10Y6_S1BEG[3:0]),
+	.S2MID(Tile_X10Y6_S2BEG[7:0]),
+	.S2END(Tile_X10Y6_S2BEGb[7:0]),
+	.S4END(Tile_X10Y6_S4BEG[15:0]),
+	.SS4END(Tile_X10Y6_SS4BEG[15:0]),
+	.W1END(Tile_X11Y7_W1BEG[3:0]),
+	.W2MID(Tile_X11Y7_W2BEG[7:0]),
+	.W2END(Tile_X11Y7_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y7_WW4BEG[15:0]),
+	.W6END(Tile_X11Y7_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y7_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y7_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y7_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y7_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y7_NN4BEG[15:0]),
+	.Co(Tile_X10Y7_Co[0:0]),
+	.E1BEG(Tile_X10Y7_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y7_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y7_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y7_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y7_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y7_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y7_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y7_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y7_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y7_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y8_UserCLKo),
+	.UserCLKo(Tile_X10Y7_UserCLKo),
+	.FrameData(Tile_X9Y7_FrameData_O), 
+	.FrameData_O(Tile_X10Y7_FrameData_O), 
+	.FrameStrobe(Tile_X10Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y7_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y7_E_CPU_IO (
+	.E1END(Tile_X10Y7_E1BEG[3:0]),
+	.E2MID(Tile_X10Y7_E2BEG[7:0]),
+	.E2END(Tile_X10Y7_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y7_EE4BEG[15:0]),
+	.E6END(Tile_X10Y7_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y7_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y7_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y7_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y7_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y7_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y7_OPA_I0),
+	.OPA_I1(Tile_X11Y7_OPA_I1),
+	.OPA_I2(Tile_X11Y7_OPA_I2),
+	.OPA_I3(Tile_X11Y7_OPA_I3),
+	.UserCLK(Tile_X11Y8_UserCLKo),
+	.OPB_I0(Tile_X11Y7_OPB_I0),
+	.OPB_I1(Tile_X11Y7_OPB_I1),
+	.OPB_I2(Tile_X11Y7_OPB_I2),
+	.OPB_I3(Tile_X11Y7_OPB_I3),
+	.RES0_O0(Tile_X11Y7_RES0_O0),
+	.RES0_O1(Tile_X11Y7_RES0_O1),
+	.RES0_O2(Tile_X11Y7_RES0_O2),
+	.RES0_O3(Tile_X11Y7_RES0_O3),
+	.RES1_O0(Tile_X11Y7_RES1_O0),
+	.RES1_O1(Tile_X11Y7_RES1_O1),
+	.RES1_O2(Tile_X11Y7_RES1_O2),
+	.RES1_O3(Tile_X11Y7_RES1_O3),
+	.RES2_O0(Tile_X11Y7_RES2_O0),
+	.RES2_O1(Tile_X11Y7_RES2_O1),
+	.RES2_O2(Tile_X11Y7_RES2_O2),
+	.RES2_O3(Tile_X11Y7_RES2_O3),
+	.UserCLKo(Tile_X11Y7_UserCLKo),
+	.FrameData(Tile_X10Y7_FrameData_O), 
+	.FrameData_O(Tile_X11Y7_FrameData_O), 
+	.FrameStrobe(Tile_X11Y8_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y7_FrameStrobe_O)
+	);
+
+	W_CPU_IO Tile_X3Y8_W_CPU_IO (
+	.W1END(Tile_X4Y8_W1BEG[3:0]),
+	.W2MID(Tile_X4Y8_W2BEG[7:0]),
+	.W2END(Tile_X4Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y8_WW4BEG[15:0]),
+	.W6END(Tile_X4Y8_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y8_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y8_OPA_I0),
+	.OPA_I1(Tile_X3Y8_OPA_I1),
+	.OPA_I2(Tile_X3Y8_OPA_I2),
+	.OPA_I3(Tile_X3Y8_OPA_I3),
+	.UserCLK(Tile_X3Y9_UserCLKo),
+	.OPB_I0(Tile_X3Y8_OPB_I0),
+	.OPB_I1(Tile_X3Y8_OPB_I1),
+	.OPB_I2(Tile_X3Y8_OPB_I2),
+	.OPB_I3(Tile_X3Y8_OPB_I3),
+	.RES0_O0(Tile_X3Y8_RES0_O0),
+	.RES0_O1(Tile_X3Y8_RES0_O1),
+	.RES0_O2(Tile_X3Y8_RES0_O2),
+	.RES0_O3(Tile_X3Y8_RES0_O3),
+	.RES1_O0(Tile_X3Y8_RES1_O0),
+	.RES1_O1(Tile_X3Y8_RES1_O1),
+	.RES1_O2(Tile_X3Y8_RES1_O2),
+	.RES1_O3(Tile_X3Y8_RES1_O3),
+	.RES2_O0(Tile_X3Y8_RES2_O0),
+	.RES2_O1(Tile_X3Y8_RES2_O1),
+	.RES2_O2(Tile_X3Y8_RES2_O2),
+	.RES2_O3(Tile_X3Y8_RES2_O3),
+	.UserCLKo(Tile_X3Y8_UserCLKo),
+	.FrameData(Tile_Y8_FrameData), 
+	.FrameData_O(Tile_X3Y8_FrameData_O), 
+	.FrameStrobe(Tile_X3Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y8_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y8_LUT4AB (
+	.N1END(Tile_X5Y9_N1BEG[3:0]),
+	.N2MID(Tile_X5Y9_N2BEG[7:0]),
+	.N2END(Tile_X5Y9_N2BEGb[7:0]),
+	.N4END(Tile_X5Y9_N4BEG[15:0]),
+	.NN4END(Tile_X5Y9_NN4BEG[15:0]),
+	.Ci(Tile_X5Y9_Co[0:0]),
+	.E1END(Tile_X4Y8_E1BEG[3:0]),
+	.E2MID(Tile_X4Y8_E2BEG[7:0]),
+	.E2END(Tile_X4Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y8_EE4BEG[15:0]),
+	.E6END(Tile_X4Y8_E6BEG[11:0]),
+	.S1END(Tile_X5Y7_S1BEG[3:0]),
+	.S2MID(Tile_X5Y7_S2BEG[7:0]),
+	.S2END(Tile_X5Y7_S2BEGb[7:0]),
+	.S4END(Tile_X5Y7_S4BEG[15:0]),
+	.SS4END(Tile_X5Y7_SS4BEG[15:0]),
+	.W1END(Tile_X6Y8_W1BEG[3:0]),
+	.W2MID(Tile_X6Y8_W2BEG[7:0]),
+	.W2END(Tile_X6Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y8_WW4BEG[15:0]),
+	.W6END(Tile_X6Y8_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y8_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y8_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y8_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y8_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y8_NN4BEG[15:0]),
+	.Co(Tile_X5Y8_Co[0:0]),
+	.E1BEG(Tile_X5Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y8_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y8_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y8_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y8_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y8_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y8_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y9_UserCLKo),
+	.UserCLKo(Tile_X5Y8_UserCLKo),
+	.FrameData(Tile_X4Y8_FrameData_O), 
+	.FrameData_O(Tile_X5Y8_FrameData_O), 
+	.FrameStrobe(Tile_X5Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y8_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y8_LUT4AB (
+	.N1END(Tile_X6Y9_N1BEG[3:0]),
+	.N2MID(Tile_X6Y9_N2BEG[7:0]),
+	.N2END(Tile_X6Y9_N2BEGb[7:0]),
+	.N4END(Tile_X6Y9_N4BEG[15:0]),
+	.NN4END(Tile_X6Y9_NN4BEG[15:0]),
+	.Ci(Tile_X6Y9_Co[0:0]),
+	.E1END(Tile_X5Y8_E1BEG[3:0]),
+	.E2MID(Tile_X5Y8_E2BEG[7:0]),
+	.E2END(Tile_X5Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y8_EE4BEG[15:0]),
+	.E6END(Tile_X5Y8_E6BEG[11:0]),
+	.S1END(Tile_X6Y7_S1BEG[3:0]),
+	.S2MID(Tile_X6Y7_S2BEG[7:0]),
+	.S2END(Tile_X6Y7_S2BEGb[7:0]),
+	.S4END(Tile_X6Y7_S4BEG[15:0]),
+	.SS4END(Tile_X6Y7_SS4BEG[15:0]),
+	.W1END(Tile_X7Y8_W1BEG[3:0]),
+	.W2MID(Tile_X7Y8_W2BEG[7:0]),
+	.W2END(Tile_X7Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y8_WW4BEG[15:0]),
+	.W6END(Tile_X7Y8_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y8_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y8_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y8_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y8_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y8_NN4BEG[15:0]),
+	.Co(Tile_X6Y8_Co[0:0]),
+	.E1BEG(Tile_X6Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y8_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y8_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y8_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y8_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y8_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y8_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y9_UserCLKo),
+	.UserCLKo(Tile_X6Y8_UserCLKo),
+	.FrameData(Tile_X5Y8_FrameData_O), 
+	.FrameData_O(Tile_X6Y8_FrameData_O), 
+	.FrameStrobe(Tile_X6Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y8_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y8_LUT4AB (
+	.N1END(Tile_X7Y9_N1BEG[3:0]),
+	.N2MID(Tile_X7Y9_N2BEG[7:0]),
+	.N2END(Tile_X7Y9_N2BEGb[7:0]),
+	.N4END(Tile_X7Y9_N4BEG[15:0]),
+	.NN4END(Tile_X7Y9_NN4BEG[15:0]),
+	.Ci(Tile_X7Y9_Co[0:0]),
+	.E1END(Tile_X6Y8_E1BEG[3:0]),
+	.E2MID(Tile_X6Y8_E2BEG[7:0]),
+	.E2END(Tile_X6Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y8_EE4BEG[15:0]),
+	.E6END(Tile_X6Y8_E6BEG[11:0]),
+	.S1END(Tile_X7Y7_S1BEG[3:0]),
+	.S2MID(Tile_X7Y7_S2BEG[7:0]),
+	.S2END(Tile_X7Y7_S2BEGb[7:0]),
+	.S4END(Tile_X7Y7_S4BEG[15:0]),
+	.SS4END(Tile_X7Y7_SS4BEG[15:0]),
+	.W1END(Tile_X8Y8_W1BEG[3:0]),
+	.W2MID(Tile_X8Y8_W2BEG[7:0]),
+	.W2END(Tile_X8Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y8_WW4BEG[15:0]),
+	.W6END(Tile_X8Y8_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y8_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y8_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y8_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y8_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y8_NN4BEG[15:0]),
+	.Co(Tile_X7Y8_Co[0:0]),
+	.E1BEG(Tile_X7Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y8_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y8_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y8_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y8_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y8_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y8_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y9_UserCLKo),
+	.UserCLKo(Tile_X7Y8_UserCLKo),
+	.FrameData(Tile_X6Y8_FrameData_O), 
+	.FrameData_O(Tile_X7Y8_FrameData_O), 
+	.FrameStrobe(Tile_X7Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y8_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y8_LUT4AB (
+	.N1END(Tile_X9Y9_N1BEG[3:0]),
+	.N2MID(Tile_X9Y9_N2BEG[7:0]),
+	.N2END(Tile_X9Y9_N2BEGb[7:0]),
+	.N4END(Tile_X9Y9_N4BEG[15:0]),
+	.NN4END(Tile_X9Y9_NN4BEG[15:0]),
+	.Ci(Tile_X9Y9_Co[0:0]),
+	.E1END(Tile_X8Y8_E1BEG[3:0]),
+	.E2MID(Tile_X8Y8_E2BEG[7:0]),
+	.E2END(Tile_X8Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y8_EE4BEG[15:0]),
+	.E6END(Tile_X8Y8_E6BEG[11:0]),
+	.S1END(Tile_X9Y7_S1BEG[3:0]),
+	.S2MID(Tile_X9Y7_S2BEG[7:0]),
+	.S2END(Tile_X9Y7_S2BEGb[7:0]),
+	.S4END(Tile_X9Y7_S4BEG[15:0]),
+	.SS4END(Tile_X9Y7_SS4BEG[15:0]),
+	.W1END(Tile_X10Y8_W1BEG[3:0]),
+	.W2MID(Tile_X10Y8_W2BEG[7:0]),
+	.W2END(Tile_X10Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y8_WW4BEG[15:0]),
+	.W6END(Tile_X10Y8_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y8_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y8_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y8_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y8_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y8_NN4BEG[15:0]),
+	.Co(Tile_X9Y8_Co[0:0]),
+	.E1BEG(Tile_X9Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y8_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y8_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y8_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y8_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y8_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y8_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y9_UserCLKo),
+	.UserCLKo(Tile_X9Y8_UserCLKo),
+	.FrameData(Tile_X8Y8_FrameData_O), 
+	.FrameData_O(Tile_X9Y8_FrameData_O), 
+	.FrameStrobe(Tile_X9Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y8_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y8_LUT4AB (
+	.N1END(Tile_X10Y9_N1BEG[3:0]),
+	.N2MID(Tile_X10Y9_N2BEG[7:0]),
+	.N2END(Tile_X10Y9_N2BEGb[7:0]),
+	.N4END(Tile_X10Y9_N4BEG[15:0]),
+	.NN4END(Tile_X10Y9_NN4BEG[15:0]),
+	.Ci(Tile_X10Y9_Co[0:0]),
+	.E1END(Tile_X9Y8_E1BEG[3:0]),
+	.E2MID(Tile_X9Y8_E2BEG[7:0]),
+	.E2END(Tile_X9Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y8_EE4BEG[15:0]),
+	.E6END(Tile_X9Y8_E6BEG[11:0]),
+	.S1END(Tile_X10Y7_S1BEG[3:0]),
+	.S2MID(Tile_X10Y7_S2BEG[7:0]),
+	.S2END(Tile_X10Y7_S2BEGb[7:0]),
+	.S4END(Tile_X10Y7_S4BEG[15:0]),
+	.SS4END(Tile_X10Y7_SS4BEG[15:0]),
+	.W1END(Tile_X11Y8_W1BEG[3:0]),
+	.W2MID(Tile_X11Y8_W2BEG[7:0]),
+	.W2END(Tile_X11Y8_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y8_WW4BEG[15:0]),
+	.W6END(Tile_X11Y8_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y8_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y8_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y8_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y8_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y8_NN4BEG[15:0]),
+	.Co(Tile_X10Y8_Co[0:0]),
+	.E1BEG(Tile_X10Y8_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y8_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y8_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y8_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y8_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y8_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y8_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y8_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y8_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y8_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y9_UserCLKo),
+	.UserCLKo(Tile_X10Y8_UserCLKo),
+	.FrameData(Tile_X9Y8_FrameData_O), 
+	.FrameData_O(Tile_X10Y8_FrameData_O), 
+	.FrameStrobe(Tile_X10Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y8_FrameStrobe_O)
+	);
+
+	E_CPU_IO Tile_X11Y8_E_CPU_IO (
+	.E1END(Tile_X10Y8_E1BEG[3:0]),
+	.E2MID(Tile_X10Y8_E2BEG[7:0]),
+	.E2END(Tile_X10Y8_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y8_EE4BEG[15:0]),
+	.E6END(Tile_X10Y8_E6BEG[11:0]),
+	.W1BEG(Tile_X11Y8_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y8_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y8_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y8_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y8_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y8_OPA_I0),
+	.OPA_I1(Tile_X11Y8_OPA_I1),
+	.OPA_I2(Tile_X11Y8_OPA_I2),
+	.OPA_I3(Tile_X11Y8_OPA_I3),
+	.UserCLK(Tile_X11Y9_UserCLKo),
+	.OPB_I0(Tile_X11Y8_OPB_I0),
+	.OPB_I1(Tile_X11Y8_OPB_I1),
+	.OPB_I2(Tile_X11Y8_OPB_I2),
+	.OPB_I3(Tile_X11Y8_OPB_I3),
+	.RES0_O0(Tile_X11Y8_RES0_O0),
+	.RES0_O1(Tile_X11Y8_RES0_O1),
+	.RES0_O2(Tile_X11Y8_RES0_O2),
+	.RES0_O3(Tile_X11Y8_RES0_O3),
+	.RES1_O0(Tile_X11Y8_RES1_O0),
+	.RES1_O1(Tile_X11Y8_RES1_O1),
+	.RES1_O2(Tile_X11Y8_RES1_O2),
+	.RES1_O3(Tile_X11Y8_RES1_O3),
+	.RES2_O0(Tile_X11Y8_RES2_O0),
+	.RES2_O1(Tile_X11Y8_RES2_O1),
+	.RES2_O2(Tile_X11Y8_RES2_O2),
+	.RES2_O3(Tile_X11Y8_RES2_O3),
+	.UserCLKo(Tile_X11Y8_UserCLKo),
+	.FrameData(Tile_X10Y8_FrameData_O), 
+	.FrameData_O(Tile_X11Y8_FrameData_O), 
+	.FrameStrobe(Tile_X11Y9_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y8_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X1Y9_N_term_single (
+	.N1END(Tile_X1Y10_N1BEG[3:0]),
+	.N2MID(Tile_X1Y10_N2BEG[7:0]),
+	.N2END(Tile_X1Y10_N2BEGb[7:0]),
+	.N4END(Tile_X1Y10_N4BEG[15:0]),
+	.NN4END(Tile_X1Y10_NN4BEG[15:0]),
+	.Ci(Tile_X1Y10_Co[0:0]),
+	.S1BEG(Tile_X1Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y9_SS4BEG[15:0]),
+	.UserCLK(Tile_X1Y10_UserCLKo),
+	.UserCLKo(Tile_X1Y9_UserCLKo),
+	.FrameStrobe(Tile_X1Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y9_FrameStrobe_O)
+	);
+
+	N_term_single2 Tile_X2Y9_N_term_single2 (
+	.N1END(Tile_X2Y10_N1BEG[3:0]),
+	.N2MID(Tile_X2Y10_N2BEG[7:0]),
+	.N2END(Tile_X2Y10_N2BEGb[7:0]),
+	.N4END(Tile_X2Y10_N4BEG[15:0]),
+	.NN4END(Tile_X2Y10_NN4BEG[15:0]),
+	.S1BEG(Tile_X2Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y9_SS4BEG[15:0]),
+	.UserCLK(Tile_X2Y10_UserCLKo),
+	.UserCLKo(Tile_X2Y9_UserCLKo),
+	.FrameStrobe(Tile_X2Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y9_FrameStrobe_O)
+	);
+
+	W_CPU_IO_bot Tile_X3Y9_W_CPU_IO_bot (
+	.N1END(Tile_X3Y10_N1BEG[3:0]),
+	.N2MID(Tile_X3Y10_N2BEG[7:0]),
+	.N2END(Tile_X3Y10_N2BEGb[7:0]),
+	.N4END(Tile_X3Y10_N4BEG[15:0]),
+	.NN4END(Tile_X3Y10_NN4BEG[15:0]),
+	.Ci(Tile_X3Y10_Co[0:0]),
+	.W1END(Tile_X4Y9_W1BEG[3:0]),
+	.W2MID(Tile_X4Y9_W2BEG[7:0]),
+	.W2END(Tile_X4Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y9_WW4BEG[15:0]),
+	.W6END(Tile_X4Y9_W6BEG[11:0]),
+	.E1BEG(Tile_X3Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y9_SS4BEG[15:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X3Y9_OPA_I0),
+	.OPA_I1(Tile_X3Y9_OPA_I1),
+	.OPA_I2(Tile_X3Y9_OPA_I2),
+	.OPA_I3(Tile_X3Y9_OPA_I3),
+	.UserCLK(Tile_X3Y10_UserCLKo),
+	.OPB_I0(Tile_X3Y9_OPB_I0),
+	.OPB_I1(Tile_X3Y9_OPB_I1),
+	.OPB_I2(Tile_X3Y9_OPB_I2),
+	.OPB_I3(Tile_X3Y9_OPB_I3),
+	.RES0_O0(Tile_X3Y9_RES0_O0),
+	.RES0_O1(Tile_X3Y9_RES0_O1),
+	.RES0_O2(Tile_X3Y9_RES0_O2),
+	.RES0_O3(Tile_X3Y9_RES0_O3),
+	.RES1_O0(Tile_X3Y9_RES1_O0),
+	.RES1_O1(Tile_X3Y9_RES1_O1),
+	.RES1_O2(Tile_X3Y9_RES1_O2),
+	.RES1_O3(Tile_X3Y9_RES1_O3),
+	.RES2_O0(Tile_X3Y9_RES2_O0),
+	.RES2_O1(Tile_X3Y9_RES2_O1),
+	.RES2_O2(Tile_X3Y9_RES2_O2),
+	.RES2_O3(Tile_X3Y9_RES2_O3),
+	.UserCLKo(Tile_X3Y9_UserCLKo),
+	.FrameData(Tile_Y9_FrameData), 
+	.FrameData_O(Tile_X3Y9_FrameData_O), 
+	.FrameStrobe(Tile_X3Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y9_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y9_LUT4AB (
+	.N1END(Tile_X5Y10_N1BEG[3:0]),
+	.N2MID(Tile_X5Y10_N2BEG[7:0]),
+	.N2END(Tile_X5Y10_N2BEGb[7:0]),
+	.N4END(Tile_X5Y10_N4BEG[15:0]),
+	.NN4END(Tile_X5Y10_NN4BEG[15:0]),
+	.Ci(Tile_X5Y10_Co[0:0]),
+	.E1END(Tile_X4Y9_E1BEG[3:0]),
+	.E2MID(Tile_X4Y9_E2BEG[7:0]),
+	.E2END(Tile_X4Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y9_EE4BEG[15:0]),
+	.E6END(Tile_X4Y9_E6BEG[11:0]),
+	.S1END(Tile_X5Y8_S1BEG[3:0]),
+	.S2MID(Tile_X5Y8_S2BEG[7:0]),
+	.S2END(Tile_X5Y8_S2BEGb[7:0]),
+	.S4END(Tile_X5Y8_S4BEG[15:0]),
+	.SS4END(Tile_X5Y8_SS4BEG[15:0]),
+	.W1END(Tile_X6Y9_W1BEG[3:0]),
+	.W2MID(Tile_X6Y9_W2BEG[7:0]),
+	.W2END(Tile_X6Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y9_WW4BEG[15:0]),
+	.W6END(Tile_X6Y9_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y9_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y9_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y9_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y9_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y9_NN4BEG[15:0]),
+	.Co(Tile_X5Y9_Co[0:0]),
+	.E1BEG(Tile_X5Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y10_UserCLKo),
+	.UserCLKo(Tile_X5Y9_UserCLKo),
+	.FrameData(Tile_X4Y9_FrameData_O), 
+	.FrameData_O(Tile_X5Y9_FrameData_O), 
+	.FrameStrobe(Tile_X5Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y9_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y9_LUT4AB (
+	.N1END(Tile_X6Y10_N1BEG[3:0]),
+	.N2MID(Tile_X6Y10_N2BEG[7:0]),
+	.N2END(Tile_X6Y10_N2BEGb[7:0]),
+	.N4END(Tile_X6Y10_N4BEG[15:0]),
+	.NN4END(Tile_X6Y10_NN4BEG[15:0]),
+	.Ci(Tile_X6Y10_Co[0:0]),
+	.E1END(Tile_X5Y9_E1BEG[3:0]),
+	.E2MID(Tile_X5Y9_E2BEG[7:0]),
+	.E2END(Tile_X5Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y9_EE4BEG[15:0]),
+	.E6END(Tile_X5Y9_E6BEG[11:0]),
+	.S1END(Tile_X6Y8_S1BEG[3:0]),
+	.S2MID(Tile_X6Y8_S2BEG[7:0]),
+	.S2END(Tile_X6Y8_S2BEGb[7:0]),
+	.S4END(Tile_X6Y8_S4BEG[15:0]),
+	.SS4END(Tile_X6Y8_SS4BEG[15:0]),
+	.W1END(Tile_X7Y9_W1BEG[3:0]),
+	.W2MID(Tile_X7Y9_W2BEG[7:0]),
+	.W2END(Tile_X7Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y9_WW4BEG[15:0]),
+	.W6END(Tile_X7Y9_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y9_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y9_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y9_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y9_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y9_NN4BEG[15:0]),
+	.Co(Tile_X6Y9_Co[0:0]),
+	.E1BEG(Tile_X6Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y10_UserCLKo),
+	.UserCLKo(Tile_X6Y9_UserCLKo),
+	.FrameData(Tile_X5Y9_FrameData_O), 
+	.FrameData_O(Tile_X6Y9_FrameData_O), 
+	.FrameStrobe(Tile_X6Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y9_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y9_LUT4AB (
+	.N1END(Tile_X7Y10_N1BEG[3:0]),
+	.N2MID(Tile_X7Y10_N2BEG[7:0]),
+	.N2END(Tile_X7Y10_N2BEGb[7:0]),
+	.N4END(Tile_X7Y10_N4BEG[15:0]),
+	.NN4END(Tile_X7Y10_NN4BEG[15:0]),
+	.Ci(Tile_X7Y10_Co[0:0]),
+	.E1END(Tile_X6Y9_E1BEG[3:0]),
+	.E2MID(Tile_X6Y9_E2BEG[7:0]),
+	.E2END(Tile_X6Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y9_EE4BEG[15:0]),
+	.E6END(Tile_X6Y9_E6BEG[11:0]),
+	.S1END(Tile_X7Y8_S1BEG[3:0]),
+	.S2MID(Tile_X7Y8_S2BEG[7:0]),
+	.S2END(Tile_X7Y8_S2BEGb[7:0]),
+	.S4END(Tile_X7Y8_S4BEG[15:0]),
+	.SS4END(Tile_X7Y8_SS4BEG[15:0]),
+	.W1END(Tile_X8Y9_W1BEG[3:0]),
+	.W2MID(Tile_X8Y9_W2BEG[7:0]),
+	.W2END(Tile_X8Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y9_WW4BEG[15:0]),
+	.W6END(Tile_X8Y9_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y9_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y9_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y9_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y9_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y9_NN4BEG[15:0]),
+	.Co(Tile_X7Y9_Co[0:0]),
+	.E1BEG(Tile_X7Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y10_UserCLKo),
+	.UserCLKo(Tile_X7Y9_UserCLKo),
+	.FrameData(Tile_X6Y9_FrameData_O), 
+	.FrameData_O(Tile_X7Y9_FrameData_O), 
+	.FrameStrobe(Tile_X7Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y9_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y9_LUT4AB (
+	.N1END(Tile_X9Y10_N1BEG[3:0]),
+	.N2MID(Tile_X9Y10_N2BEG[7:0]),
+	.N2END(Tile_X9Y10_N2BEGb[7:0]),
+	.N4END(Tile_X9Y10_N4BEG[15:0]),
+	.NN4END(Tile_X9Y10_NN4BEG[15:0]),
+	.Ci(Tile_X9Y10_Co[0:0]),
+	.E1END(Tile_X8Y9_E1BEG[3:0]),
+	.E2MID(Tile_X8Y9_E2BEG[7:0]),
+	.E2END(Tile_X8Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y9_EE4BEG[15:0]),
+	.E6END(Tile_X8Y9_E6BEG[11:0]),
+	.S1END(Tile_X9Y8_S1BEG[3:0]),
+	.S2MID(Tile_X9Y8_S2BEG[7:0]),
+	.S2END(Tile_X9Y8_S2BEGb[7:0]),
+	.S4END(Tile_X9Y8_S4BEG[15:0]),
+	.SS4END(Tile_X9Y8_SS4BEG[15:0]),
+	.W1END(Tile_X10Y9_W1BEG[3:0]),
+	.W2MID(Tile_X10Y9_W2BEG[7:0]),
+	.W2END(Tile_X10Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y9_WW4BEG[15:0]),
+	.W6END(Tile_X10Y9_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y9_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y9_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y9_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y9_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y9_NN4BEG[15:0]),
+	.Co(Tile_X9Y9_Co[0:0]),
+	.E1BEG(Tile_X9Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y10_UserCLKo),
+	.UserCLKo(Tile_X9Y9_UserCLKo),
+	.FrameData(Tile_X8Y9_FrameData_O), 
+	.FrameData_O(Tile_X9Y9_FrameData_O), 
+	.FrameStrobe(Tile_X9Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y9_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y9_LUT4AB (
+	.N1END(Tile_X10Y10_N1BEG[3:0]),
+	.N2MID(Tile_X10Y10_N2BEG[7:0]),
+	.N2END(Tile_X10Y10_N2BEGb[7:0]),
+	.N4END(Tile_X10Y10_N4BEG[15:0]),
+	.NN4END(Tile_X10Y10_NN4BEG[15:0]),
+	.Ci(Tile_X10Y10_Co[0:0]),
+	.E1END(Tile_X9Y9_E1BEG[3:0]),
+	.E2MID(Tile_X9Y9_E2BEG[7:0]),
+	.E2END(Tile_X9Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y9_EE4BEG[15:0]),
+	.E6END(Tile_X9Y9_E6BEG[11:0]),
+	.S1END(Tile_X10Y8_S1BEG[3:0]),
+	.S2MID(Tile_X10Y8_S2BEG[7:0]),
+	.S2END(Tile_X10Y8_S2BEGb[7:0]),
+	.S4END(Tile_X10Y8_S4BEG[15:0]),
+	.SS4END(Tile_X10Y8_SS4BEG[15:0]),
+	.W1END(Tile_X11Y9_W1BEG[3:0]),
+	.W2MID(Tile_X11Y9_W2BEG[7:0]),
+	.W2END(Tile_X11Y9_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y9_WW4BEG[15:0]),
+	.W6END(Tile_X11Y9_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y9_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y9_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y9_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y9_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y9_NN4BEG[15:0]),
+	.Co(Tile_X10Y9_Co[0:0]),
+	.E1BEG(Tile_X10Y9_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y9_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y9_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y9_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y10_UserCLKo),
+	.UserCLKo(Tile_X10Y9_UserCLKo),
+	.FrameData(Tile_X9Y9_FrameData_O), 
+	.FrameData_O(Tile_X10Y9_FrameData_O), 
+	.FrameStrobe(Tile_X10Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y9_FrameStrobe_O)
+	);
+
+	E_CPU_IO_bot Tile_X11Y9_E_CPU_IO_bot (
+	.N1END(Tile_X11Y10_N1BEG[3:0]),
+	.N2MID(Tile_X11Y10_N2BEG[7:0]),
+	.N2END(Tile_X11Y10_N2BEGb[7:0]),
+	.N4END(Tile_X11Y10_N4BEG[15:0]),
+	.NN4END(Tile_X11Y10_NN4BEG[15:0]),
+	.Ci(Tile_X11Y10_Co[0:0]),
+	.E1END(Tile_X10Y9_E1BEG[3:0]),
+	.E2MID(Tile_X10Y9_E2BEG[7:0]),
+	.E2END(Tile_X10Y9_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y9_EE4BEG[15:0]),
+	.E6END(Tile_X10Y9_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y9_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y9_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y9_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y9_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y9_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y9_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.OPA_I0(Tile_X11Y9_OPA_I0),
+	.OPA_I1(Tile_X11Y9_OPA_I1),
+	.OPA_I2(Tile_X11Y9_OPA_I2),
+	.OPA_I3(Tile_X11Y9_OPA_I3),
+	.UserCLK(Tile_X11Y10_UserCLKo),
+	.OPB_I0(Tile_X11Y9_OPB_I0),
+	.OPB_I1(Tile_X11Y9_OPB_I1),
+	.OPB_I2(Tile_X11Y9_OPB_I2),
+	.OPB_I3(Tile_X11Y9_OPB_I3),
+	.RES0_O0(Tile_X11Y9_RES0_O0),
+	.RES0_O1(Tile_X11Y9_RES0_O1),
+	.RES0_O2(Tile_X11Y9_RES0_O2),
+	.RES0_O3(Tile_X11Y9_RES0_O3),
+	.RES1_O0(Tile_X11Y9_RES1_O0),
+	.RES1_O1(Tile_X11Y9_RES1_O1),
+	.RES1_O2(Tile_X11Y9_RES1_O2),
+	.RES1_O3(Tile_X11Y9_RES1_O3),
+	.RES2_O0(Tile_X11Y9_RES2_O0),
+	.RES2_O1(Tile_X11Y9_RES2_O1),
+	.RES2_O2(Tile_X11Y9_RES2_O2),
+	.RES2_O3(Tile_X11Y9_RES2_O3),
+	.UserCLKo(Tile_X11Y9_UserCLKo),
+	.FrameData(Tile_X10Y9_FrameData_O), 
+	.FrameData_O(Tile_X11Y9_FrameData_O), 
+	.FrameStrobe(Tile_X11Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y9_FrameStrobe_O)
+	);
+
+	N_term_single2 Tile_X12Y9_N_term_single2 (
+	.N1END(Tile_X12Y10_N1BEG[3:0]),
+	.N2MID(Tile_X12Y10_N2BEG[7:0]),
+	.N2END(Tile_X12Y10_N2BEGb[7:0]),
+	.N4END(Tile_X12Y10_N4BEG[15:0]),
+	.NN4END(Tile_X12Y10_NN4BEG[15:0]),
+	.S1BEG(Tile_X12Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y9_SS4BEG[15:0]),
+	.UserCLK(Tile_X12Y10_UserCLKo),
+	.UserCLKo(Tile_X12Y9_UserCLKo),
+	.FrameStrobe(Tile_X12Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y9_FrameStrobe_O)
+	);
+
+	N_term_single Tile_X13Y9_N_term_single (
+	.N1END(Tile_X13Y10_N1BEG[3:0]),
+	.N2MID(Tile_X13Y10_N2BEG[7:0]),
+	.N2END(Tile_X13Y10_N2BEGb[7:0]),
+	.N4END(Tile_X13Y10_N4BEG[15:0]),
+	.NN4END(Tile_X13Y10_NN4BEG[15:0]),
+	.Ci(Tile_X13Y10_Co[0:0]),
+	.S1BEG(Tile_X13Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y9_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y9_SS4BEG[15:0]),
+	.UserCLK(Tile_X13Y10_UserCLKo),
+	.UserCLKo(Tile_X13Y9_UserCLKo),
+	.FrameStrobe(Tile_X13Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y9_FrameStrobe_O)
+	);
+
+	N_term_RAM_IO Tile_X14Y9_N_term_RAM_IO (
+	.N1END(Tile_X14Y10_N1BEG[3:0]),
+	.N2MID(Tile_X14Y10_N2BEG[7:0]),
+	.N2END(Tile_X14Y10_N2BEGb[7:0]),
+	.N4END(Tile_X14Y10_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y9_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y9_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y9_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y9_S4BEG[15:0]),
+	.UserCLK(Tile_X14Y10_UserCLKo),
+	.UserCLKo(Tile_X14Y9_UserCLKo),
+	.FrameStrobe(Tile_X14Y10_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y9_FrameStrobe_O)
+	);
+
+	W_IO Tile_X0Y10_W_IO (
+	.W1END(Tile_X1Y10_W1BEG[3:0]),
+	.W2MID(Tile_X1Y10_W2BEG[7:0]),
+	.W2END(Tile_X1Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X1Y10_WW4BEG[15:0]),
+	.W6END(Tile_X1Y10_W6BEG[11:0]),
+	.E1BEG(Tile_X0Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X0Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X0Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X0Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X0Y10_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.A_I_top(Tile_X0Y10_A_I_top),
+	.A_T_top(Tile_X0Y10_A_T_top),
+	.A_O_top(Tile_X0Y10_A_O_top),
+	.UserCLK(Tile_X0Y11_UserCLKo),
+	.B_I_top(Tile_X0Y10_B_I_top),
+	.B_T_top(Tile_X0Y10_B_T_top),
+	.B_O_top(Tile_X0Y10_B_O_top),
+	.A_config_C_bit0(Tile_X0Y10_A_config_C_bit0),
+	.A_config_C_bit1(Tile_X0Y10_A_config_C_bit1),
+	.A_config_C_bit2(Tile_X0Y10_A_config_C_bit2),
+	.A_config_C_bit3(Tile_X0Y10_A_config_C_bit3),
+	.B_config_C_bit0(Tile_X0Y10_B_config_C_bit0),
+	.B_config_C_bit1(Tile_X0Y10_B_config_C_bit1),
+	.B_config_C_bit2(Tile_X0Y10_B_config_C_bit2),
+	.B_config_C_bit3(Tile_X0Y10_B_config_C_bit3),
+	.UserCLKo(Tile_X0Y10_UserCLKo),
+	.FrameData(Tile_Y10_FrameData), 
+	.FrameData_O(Tile_X0Y10_FrameData_O), 
+	.FrameStrobe(Tile_X0Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X0Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X1Y10_LUT4AB (
+	.N1END(Tile_X1Y11_N1BEG[3:0]),
+	.N2MID(Tile_X1Y11_N2BEG[7:0]),
+	.N2END(Tile_X1Y11_N2BEGb[7:0]),
+	.N4END(Tile_X1Y11_N4BEG[15:0]),
+	.NN4END(Tile_X1Y11_NN4BEG[15:0]),
+	.Ci(Tile_X1Y11_Co[0:0]),
+	.E1END(Tile_X0Y10_E1BEG[3:0]),
+	.E2MID(Tile_X0Y10_E2BEG[7:0]),
+	.E2END(Tile_X0Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X0Y10_EE4BEG[15:0]),
+	.E6END(Tile_X0Y10_E6BEG[11:0]),
+	.S1END(Tile_X1Y9_S1BEG[3:0]),
+	.S2MID(Tile_X1Y9_S2BEG[7:0]),
+	.S2END(Tile_X1Y9_S2BEGb[7:0]),
+	.S4END(Tile_X1Y9_S4BEG[15:0]),
+	.SS4END(Tile_X1Y9_SS4BEG[15:0]),
+	.W1END(Tile_X2Y10_W1BEG[3:0]),
+	.W2MID(Tile_X2Y10_W2BEG[7:0]),
+	.W2END(Tile_X2Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X2Y10_WW4BEG[15:0]),
+	.W6END(Tile_X2Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X1Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y10_NN4BEG[15:0]),
+	.Co(Tile_X1Y10_Co[0:0]),
+	.E1BEG(Tile_X1Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X1Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X1Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X1Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X1Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X1Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X1Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X1Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X1Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X1Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X1Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X1Y11_UserCLKo),
+	.UserCLKo(Tile_X1Y10_UserCLKo),
+	.FrameData(Tile_X0Y10_FrameData_O), 
+	.FrameData_O(Tile_X1Y10_FrameData_O), 
+	.FrameStrobe(Tile_X1Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y10_FrameStrobe_O)
+	);
+
+	RegFile Tile_X2Y10_RegFile (
+	.N1END(Tile_X2Y11_N1BEG[3:0]),
+	.N2MID(Tile_X2Y11_N2BEG[7:0]),
+	.N2END(Tile_X2Y11_N2BEGb[7:0]),
+	.N4END(Tile_X2Y11_N4BEG[15:0]),
+	.NN4END(Tile_X2Y11_NN4BEG[15:0]),
+	.E1END(Tile_X1Y10_E1BEG[3:0]),
+	.E2MID(Tile_X1Y10_E2BEG[7:0]),
+	.E2END(Tile_X1Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X1Y10_EE4BEG[15:0]),
+	.E6END(Tile_X1Y10_E6BEG[11:0]),
+	.S1END(Tile_X2Y9_S1BEG[3:0]),
+	.S2MID(Tile_X2Y9_S2BEG[7:0]),
+	.S2END(Tile_X2Y9_S2BEGb[7:0]),
+	.S4END(Tile_X2Y9_S4BEG[15:0]),
+	.SS4END(Tile_X2Y9_SS4BEG[15:0]),
+	.W1END(Tile_X3Y10_W1BEG[3:0]),
+	.W2MID(Tile_X3Y10_W2BEG[7:0]),
+	.W2END(Tile_X3Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X3Y10_WW4BEG[15:0]),
+	.W6END(Tile_X3Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X2Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y10_NN4BEG[15:0]),
+	.E1BEG(Tile_X2Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X2Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X2Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X2Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X2Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X2Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X2Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X2Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X2Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X2Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X2Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X2Y11_UserCLKo),
+	.UserCLKo(Tile_X2Y10_UserCLKo),
+	.FrameData(Tile_X1Y10_FrameData_O), 
+	.FrameData_O(Tile_X2Y10_FrameData_O), 
+	.FrameStrobe(Tile_X2Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X3Y10_LUT4AB (
+	.N1END(Tile_X3Y11_N1BEG[3:0]),
+	.N2MID(Tile_X3Y11_N2BEG[7:0]),
+	.N2END(Tile_X3Y11_N2BEGb[7:0]),
+	.N4END(Tile_X3Y11_N4BEG[15:0]),
+	.NN4END(Tile_X3Y11_NN4BEG[15:0]),
+	.Ci(Tile_X3Y11_Co[0:0]),
+	.E1END(Tile_X2Y10_E1BEG[3:0]),
+	.E2MID(Tile_X2Y10_E2BEG[7:0]),
+	.E2END(Tile_X2Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X2Y10_EE4BEG[15:0]),
+	.E6END(Tile_X2Y10_E6BEG[11:0]),
+	.S1END(Tile_X3Y9_S1BEG[3:0]),
+	.S2MID(Tile_X3Y9_S2BEG[7:0]),
+	.S2END(Tile_X3Y9_S2BEGb[7:0]),
+	.S4END(Tile_X3Y9_S4BEG[15:0]),
+	.SS4END(Tile_X3Y9_SS4BEG[15:0]),
+	.W1END(Tile_X4Y10_W1BEG[3:0]),
+	.W2MID(Tile_X4Y10_W2BEG[7:0]),
+	.W2END(Tile_X4Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y10_WW4BEG[15:0]),
+	.W6END(Tile_X4Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X3Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y10_NN4BEG[15:0]),
+	.Co(Tile_X3Y10_Co[0:0]),
+	.E1BEG(Tile_X3Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X3Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X3Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X3Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X3Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X3Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X3Y11_UserCLKo),
+	.UserCLKo(Tile_X3Y10_UserCLKo),
+	.FrameData(Tile_X2Y10_FrameData_O), 
+	.FrameData_O(Tile_X3Y10_FrameData_O), 
+	.FrameStrobe(Tile_X3Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y10_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y10_LUT4AB (
+	.N1END(Tile_X5Y11_N1BEG[3:0]),
+	.N2MID(Tile_X5Y11_N2BEG[7:0]),
+	.N2END(Tile_X5Y11_N2BEGb[7:0]),
+	.N4END(Tile_X5Y11_N4BEG[15:0]),
+	.NN4END(Tile_X5Y11_NN4BEG[15:0]),
+	.Ci(Tile_X5Y11_Co[0:0]),
+	.E1END(Tile_X4Y10_E1BEG[3:0]),
+	.E2MID(Tile_X4Y10_E2BEG[7:0]),
+	.E2END(Tile_X4Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y10_EE4BEG[15:0]),
+	.E6END(Tile_X4Y10_E6BEG[11:0]),
+	.S1END(Tile_X5Y9_S1BEG[3:0]),
+	.S2MID(Tile_X5Y9_S2BEG[7:0]),
+	.S2END(Tile_X5Y9_S2BEGb[7:0]),
+	.S4END(Tile_X5Y9_S4BEG[15:0]),
+	.SS4END(Tile_X5Y9_SS4BEG[15:0]),
+	.W1END(Tile_X6Y10_W1BEG[3:0]),
+	.W2MID(Tile_X6Y10_W2BEG[7:0]),
+	.W2END(Tile_X6Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y10_WW4BEG[15:0]),
+	.W6END(Tile_X6Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y10_NN4BEG[15:0]),
+	.Co(Tile_X5Y10_Co[0:0]),
+	.E1BEG(Tile_X5Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y11_UserCLKo),
+	.UserCLKo(Tile_X5Y10_UserCLKo),
+	.FrameData(Tile_X4Y10_FrameData_O), 
+	.FrameData_O(Tile_X5Y10_FrameData_O), 
+	.FrameStrobe(Tile_X5Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y10_LUT4AB (
+	.N1END(Tile_X6Y11_N1BEG[3:0]),
+	.N2MID(Tile_X6Y11_N2BEG[7:0]),
+	.N2END(Tile_X6Y11_N2BEGb[7:0]),
+	.N4END(Tile_X6Y11_N4BEG[15:0]),
+	.NN4END(Tile_X6Y11_NN4BEG[15:0]),
+	.Ci(Tile_X6Y11_Co[0:0]),
+	.E1END(Tile_X5Y10_E1BEG[3:0]),
+	.E2MID(Tile_X5Y10_E2BEG[7:0]),
+	.E2END(Tile_X5Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y10_EE4BEG[15:0]),
+	.E6END(Tile_X5Y10_E6BEG[11:0]),
+	.S1END(Tile_X6Y9_S1BEG[3:0]),
+	.S2MID(Tile_X6Y9_S2BEG[7:0]),
+	.S2END(Tile_X6Y9_S2BEGb[7:0]),
+	.S4END(Tile_X6Y9_S4BEG[15:0]),
+	.SS4END(Tile_X6Y9_SS4BEG[15:0]),
+	.W1END(Tile_X7Y10_W1BEG[3:0]),
+	.W2MID(Tile_X7Y10_W2BEG[7:0]),
+	.W2END(Tile_X7Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y10_WW4BEG[15:0]),
+	.W6END(Tile_X7Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y10_NN4BEG[15:0]),
+	.Co(Tile_X6Y10_Co[0:0]),
+	.E1BEG(Tile_X6Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y11_UserCLKo),
+	.UserCLKo(Tile_X6Y10_UserCLKo),
+	.FrameData(Tile_X5Y10_FrameData_O), 
+	.FrameData_O(Tile_X6Y10_FrameData_O), 
+	.FrameStrobe(Tile_X6Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y10_LUT4AB (
+	.N1END(Tile_X7Y11_N1BEG[3:0]),
+	.N2MID(Tile_X7Y11_N2BEG[7:0]),
+	.N2END(Tile_X7Y11_N2BEGb[7:0]),
+	.N4END(Tile_X7Y11_N4BEG[15:0]),
+	.NN4END(Tile_X7Y11_NN4BEG[15:0]),
+	.Ci(Tile_X7Y11_Co[0:0]),
+	.E1END(Tile_X6Y10_E1BEG[3:0]),
+	.E2MID(Tile_X6Y10_E2BEG[7:0]),
+	.E2END(Tile_X6Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y10_EE4BEG[15:0]),
+	.E6END(Tile_X6Y10_E6BEG[11:0]),
+	.S1END(Tile_X7Y9_S1BEG[3:0]),
+	.S2MID(Tile_X7Y9_S2BEG[7:0]),
+	.S2END(Tile_X7Y9_S2BEGb[7:0]),
+	.S4END(Tile_X7Y9_S4BEG[15:0]),
+	.SS4END(Tile_X7Y9_SS4BEG[15:0]),
+	.W1END(Tile_X8Y10_W1BEG[3:0]),
+	.W2MID(Tile_X8Y10_W2BEG[7:0]),
+	.W2END(Tile_X8Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y10_WW4BEG[15:0]),
+	.W6END(Tile_X8Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y10_NN4BEG[15:0]),
+	.Co(Tile_X7Y10_Co[0:0]),
+	.E1BEG(Tile_X7Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y11_UserCLKo),
+	.UserCLKo(Tile_X7Y10_UserCLKo),
+	.FrameData(Tile_X6Y10_FrameData_O), 
+	.FrameData_O(Tile_X7Y10_FrameData_O), 
+	.FrameStrobe(Tile_X7Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y10_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y10_LUT4AB (
+	.N1END(Tile_X9Y11_N1BEG[3:0]),
+	.N2MID(Tile_X9Y11_N2BEG[7:0]),
+	.N2END(Tile_X9Y11_N2BEGb[7:0]),
+	.N4END(Tile_X9Y11_N4BEG[15:0]),
+	.NN4END(Tile_X9Y11_NN4BEG[15:0]),
+	.Ci(Tile_X9Y11_Co[0:0]),
+	.E1END(Tile_X8Y10_E1BEG[3:0]),
+	.E2MID(Tile_X8Y10_E2BEG[7:0]),
+	.E2END(Tile_X8Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y10_EE4BEG[15:0]),
+	.E6END(Tile_X8Y10_E6BEG[11:0]),
+	.S1END(Tile_X9Y9_S1BEG[3:0]),
+	.S2MID(Tile_X9Y9_S2BEG[7:0]),
+	.S2END(Tile_X9Y9_S2BEGb[7:0]),
+	.S4END(Tile_X9Y9_S4BEG[15:0]),
+	.SS4END(Tile_X9Y9_SS4BEG[15:0]),
+	.W1END(Tile_X10Y10_W1BEG[3:0]),
+	.W2MID(Tile_X10Y10_W2BEG[7:0]),
+	.W2END(Tile_X10Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y10_WW4BEG[15:0]),
+	.W6END(Tile_X10Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y10_NN4BEG[15:0]),
+	.Co(Tile_X9Y10_Co[0:0]),
+	.E1BEG(Tile_X9Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y11_UserCLKo),
+	.UserCLKo(Tile_X9Y10_UserCLKo),
+	.FrameData(Tile_X8Y10_FrameData_O), 
+	.FrameData_O(Tile_X9Y10_FrameData_O), 
+	.FrameStrobe(Tile_X9Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y10_LUT4AB (
+	.N1END(Tile_X10Y11_N1BEG[3:0]),
+	.N2MID(Tile_X10Y11_N2BEG[7:0]),
+	.N2END(Tile_X10Y11_N2BEGb[7:0]),
+	.N4END(Tile_X10Y11_N4BEG[15:0]),
+	.NN4END(Tile_X10Y11_NN4BEG[15:0]),
+	.Ci(Tile_X10Y11_Co[0:0]),
+	.E1END(Tile_X9Y10_E1BEG[3:0]),
+	.E2MID(Tile_X9Y10_E2BEG[7:0]),
+	.E2END(Tile_X9Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y10_EE4BEG[15:0]),
+	.E6END(Tile_X9Y10_E6BEG[11:0]),
+	.S1END(Tile_X10Y9_S1BEG[3:0]),
+	.S2MID(Tile_X10Y9_S2BEG[7:0]),
+	.S2END(Tile_X10Y9_S2BEGb[7:0]),
+	.S4END(Tile_X10Y9_S4BEG[15:0]),
+	.SS4END(Tile_X10Y9_SS4BEG[15:0]),
+	.W1END(Tile_X11Y10_W1BEG[3:0]),
+	.W2MID(Tile_X11Y10_W2BEG[7:0]),
+	.W2END(Tile_X11Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y10_WW4BEG[15:0]),
+	.W6END(Tile_X11Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y10_NN4BEG[15:0]),
+	.Co(Tile_X10Y10_Co[0:0]),
+	.E1BEG(Tile_X10Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y11_UserCLKo),
+	.UserCLKo(Tile_X10Y10_UserCLKo),
+	.FrameData(Tile_X9Y10_FrameData_O), 
+	.FrameData_O(Tile_X10Y10_FrameData_O), 
+	.FrameStrobe(Tile_X10Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X11Y10_LUT4AB (
+	.N1END(Tile_X11Y11_N1BEG[3:0]),
+	.N2MID(Tile_X11Y11_N2BEG[7:0]),
+	.N2END(Tile_X11Y11_N2BEGb[7:0]),
+	.N4END(Tile_X11Y11_N4BEG[15:0]),
+	.NN4END(Tile_X11Y11_NN4BEG[15:0]),
+	.Ci(Tile_X11Y11_Co[0:0]),
+	.E1END(Tile_X10Y10_E1BEG[3:0]),
+	.E2MID(Tile_X10Y10_E2BEG[7:0]),
+	.E2END(Tile_X10Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y10_EE4BEG[15:0]),
+	.E6END(Tile_X10Y10_E6BEG[11:0]),
+	.S1END(Tile_X11Y9_S1BEG[3:0]),
+	.S2MID(Tile_X11Y9_S2BEG[7:0]),
+	.S2END(Tile_X11Y9_S2BEGb[7:0]),
+	.S4END(Tile_X11Y9_S4BEG[15:0]),
+	.SS4END(Tile_X11Y9_SS4BEG[15:0]),
+	.W1END(Tile_X12Y10_W1BEG[3:0]),
+	.W2MID(Tile_X12Y10_W2BEG[7:0]),
+	.W2END(Tile_X12Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X12Y10_WW4BEG[15:0]),
+	.W6END(Tile_X12Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X11Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y10_NN4BEG[15:0]),
+	.Co(Tile_X11Y10_Co[0:0]),
+	.E1BEG(Tile_X11Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X11Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X11Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X11Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X11Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X11Y11_UserCLKo),
+	.UserCLKo(Tile_X11Y10_UserCLKo),
+	.FrameData(Tile_X10Y10_FrameData_O), 
+	.FrameData_O(Tile_X11Y10_FrameData_O), 
+	.FrameStrobe(Tile_X11Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y10_FrameStrobe_O)
+	);
+
+	RegFile Tile_X12Y10_RegFile (
+	.N1END(Tile_X12Y11_N1BEG[3:0]),
+	.N2MID(Tile_X12Y11_N2BEG[7:0]),
+	.N2END(Tile_X12Y11_N2BEGb[7:0]),
+	.N4END(Tile_X12Y11_N4BEG[15:0]),
+	.NN4END(Tile_X12Y11_NN4BEG[15:0]),
+	.E1END(Tile_X11Y10_E1BEG[3:0]),
+	.E2MID(Tile_X11Y10_E2BEG[7:0]),
+	.E2END(Tile_X11Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X11Y10_EE4BEG[15:0]),
+	.E6END(Tile_X11Y10_E6BEG[11:0]),
+	.S1END(Tile_X12Y9_S1BEG[3:0]),
+	.S2MID(Tile_X12Y9_S2BEG[7:0]),
+	.S2END(Tile_X12Y9_S2BEGb[7:0]),
+	.S4END(Tile_X12Y9_S4BEG[15:0]),
+	.SS4END(Tile_X12Y9_SS4BEG[15:0]),
+	.W1END(Tile_X13Y10_W1BEG[3:0]),
+	.W2MID(Tile_X13Y10_W2BEG[7:0]),
+	.W2END(Tile_X13Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X13Y10_WW4BEG[15:0]),
+	.W6END(Tile_X13Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X12Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y10_NN4BEG[15:0]),
+	.E1BEG(Tile_X12Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X12Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X12Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X12Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X12Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X12Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X12Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X12Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X12Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X12Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X12Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X12Y11_UserCLKo),
+	.UserCLKo(Tile_X12Y10_UserCLKo),
+	.FrameData(Tile_X11Y10_FrameData_O), 
+	.FrameData_O(Tile_X12Y10_FrameData_O), 
+	.FrameStrobe(Tile_X12Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y10_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X13Y10_LUT4AB (
+	.N1END(Tile_X13Y11_N1BEG[3:0]),
+	.N2MID(Tile_X13Y11_N2BEG[7:0]),
+	.N2END(Tile_X13Y11_N2BEGb[7:0]),
+	.N4END(Tile_X13Y11_N4BEG[15:0]),
+	.NN4END(Tile_X13Y11_NN4BEG[15:0]),
+	.Ci(Tile_X13Y11_Co[0:0]),
+	.E1END(Tile_X12Y10_E1BEG[3:0]),
+	.E2MID(Tile_X12Y10_E2BEG[7:0]),
+	.E2END(Tile_X12Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X12Y10_EE4BEG[15:0]),
+	.E6END(Tile_X12Y10_E6BEG[11:0]),
+	.S1END(Tile_X13Y9_S1BEG[3:0]),
+	.S2MID(Tile_X13Y9_S2BEG[7:0]),
+	.S2END(Tile_X13Y9_S2BEGb[7:0]),
+	.S4END(Tile_X13Y9_S4BEG[15:0]),
+	.SS4END(Tile_X13Y9_SS4BEG[15:0]),
+	.W1END(Tile_X14Y10_W1BEG[3:0]),
+	.W2MID(Tile_X14Y10_W2BEG[7:0]),
+	.W2END(Tile_X14Y10_W2BEGb[7:0]),
+	.WW4END(Tile_X14Y10_WW4BEG[15:0]),
+	.W6END(Tile_X14Y10_W6BEG[11:0]),
+	.N1BEG(Tile_X13Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y10_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y10_NN4BEG[15:0]),
+	.Co(Tile_X13Y10_Co[0:0]),
+	.E1BEG(Tile_X13Y10_E1BEG[3:0]),
+	.E2BEG(Tile_X13Y10_E2BEG[7:0]),
+	.E2BEGb(Tile_X13Y10_E2BEGb[7:0]),
+	.EE4BEG(Tile_X13Y10_EE4BEG[15:0]),
+	.E6BEG(Tile_X13Y10_E6BEG[11:0]),
+	.S1BEG(Tile_X13Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y10_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y10_SS4BEG[15:0]),
+	.W1BEG(Tile_X13Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X13Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X13Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X13Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X13Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X13Y11_UserCLKo),
+	.UserCLKo(Tile_X13Y10_UserCLKo),
+	.FrameData(Tile_X12Y10_FrameData_O), 
+	.FrameData_O(Tile_X13Y10_FrameData_O), 
+	.FrameStrobe(Tile_X13Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y10_FrameStrobe_O)
+	);
+
+	RAM_IO Tile_X14Y10_RAM_IO (
+	.N1END(Tile_X14Y11_N1BEG[3:0]),
+	.N2MID(Tile_X14Y11_N2BEG[7:0]),
+	.N2END(Tile_X14Y11_N2BEGb[7:0]),
+	.N4END(Tile_X14Y11_N4BEG[15:0]),
+	.E1END(Tile_X13Y10_E1BEG[3:0]),
+	.E2MID(Tile_X13Y10_E2BEG[7:0]),
+	.E2END(Tile_X13Y10_E2BEGb[7:0]),
+	.EE4END(Tile_X13Y10_EE4BEG[15:0]),
+	.E6END(Tile_X13Y10_E6BEG[11:0]),
+	.S1END(Tile_X14Y9_S1BEG[3:0]),
+	.S2MID(Tile_X14Y9_S2BEG[7:0]),
+	.S2END(Tile_X14Y9_S2BEGb[7:0]),
+	.S4END(Tile_X14Y9_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y10_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y10_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y10_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y10_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y10_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y10_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y10_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y10_S4BEG[15:0]),
+	.W1BEG(Tile_X14Y10_W1BEG[3:0]),
+	.W2BEG(Tile_X14Y10_W2BEG[7:0]),
+	.W2BEGb(Tile_X14Y10_W2BEGb[7:0]),
+	.WW4BEG(Tile_X14Y10_WW4BEG[15:0]),
+	.W6BEG(Tile_X14Y10_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.RAM2FAB_D0_I0(Tile_X14Y10_RAM2FAB_D0_I0),
+	.RAM2FAB_D0_I1(Tile_X14Y10_RAM2FAB_D0_I1),
+	.RAM2FAB_D0_I2(Tile_X14Y10_RAM2FAB_D0_I2),
+	.RAM2FAB_D0_I3(Tile_X14Y10_RAM2FAB_D0_I3),
+	.UserCLK(Tile_X14Y11_UserCLKo),
+	.RAM2FAB_D1_I0(Tile_X14Y10_RAM2FAB_D1_I0),
+	.RAM2FAB_D1_I1(Tile_X14Y10_RAM2FAB_D1_I1),
+	.RAM2FAB_D1_I2(Tile_X14Y10_RAM2FAB_D1_I2),
+	.RAM2FAB_D1_I3(Tile_X14Y10_RAM2FAB_D1_I3),
+	.RAM2FAB_D2_I0(Tile_X14Y10_RAM2FAB_D2_I0),
+	.RAM2FAB_D2_I1(Tile_X14Y10_RAM2FAB_D2_I1),
+	.RAM2FAB_D2_I2(Tile_X14Y10_RAM2FAB_D2_I2),
+	.RAM2FAB_D2_I3(Tile_X14Y10_RAM2FAB_D2_I3),
+	.RAM2FAB_D3_I0(Tile_X14Y10_RAM2FAB_D3_I0),
+	.RAM2FAB_D3_I1(Tile_X14Y10_RAM2FAB_D3_I1),
+	.RAM2FAB_D3_I2(Tile_X14Y10_RAM2FAB_D3_I2),
+	.RAM2FAB_D3_I3(Tile_X14Y10_RAM2FAB_D3_I3),
+	.FAB2RAM_D0_O0(Tile_X14Y10_FAB2RAM_D0_O0),
+	.FAB2RAM_D0_O1(Tile_X14Y10_FAB2RAM_D0_O1),
+	.FAB2RAM_D0_O2(Tile_X14Y10_FAB2RAM_D0_O2),
+	.FAB2RAM_D0_O3(Tile_X14Y10_FAB2RAM_D0_O3),
+	.FAB2RAM_D1_O0(Tile_X14Y10_FAB2RAM_D1_O0),
+	.FAB2RAM_D1_O1(Tile_X14Y10_FAB2RAM_D1_O1),
+	.FAB2RAM_D1_O2(Tile_X14Y10_FAB2RAM_D1_O2),
+	.FAB2RAM_D1_O3(Tile_X14Y10_FAB2RAM_D1_O3),
+	.FAB2RAM_D2_O0(Tile_X14Y10_FAB2RAM_D2_O0),
+	.FAB2RAM_D2_O1(Tile_X14Y10_FAB2RAM_D2_O1),
+	.FAB2RAM_D2_O2(Tile_X14Y10_FAB2RAM_D2_O2),
+	.FAB2RAM_D2_O3(Tile_X14Y10_FAB2RAM_D2_O3),
+	.FAB2RAM_D3_O0(Tile_X14Y10_FAB2RAM_D3_O0),
+	.FAB2RAM_D3_O1(Tile_X14Y10_FAB2RAM_D3_O1),
+	.FAB2RAM_D3_O2(Tile_X14Y10_FAB2RAM_D3_O2),
+	.FAB2RAM_D3_O3(Tile_X14Y10_FAB2RAM_D3_O3),
+	.FAB2RAM_A0_O0(Tile_X14Y10_FAB2RAM_A0_O0),
+	.FAB2RAM_A0_O1(Tile_X14Y10_FAB2RAM_A0_O1),
+	.FAB2RAM_A0_O2(Tile_X14Y10_FAB2RAM_A0_O2),
+	.FAB2RAM_A0_O3(Tile_X14Y10_FAB2RAM_A0_O3),
+	.FAB2RAM_A1_O0(Tile_X14Y10_FAB2RAM_A1_O0),
+	.FAB2RAM_A1_O1(Tile_X14Y10_FAB2RAM_A1_O1),
+	.FAB2RAM_A1_O2(Tile_X14Y10_FAB2RAM_A1_O2),
+	.FAB2RAM_A1_O3(Tile_X14Y10_FAB2RAM_A1_O3),
+	.FAB2RAM_C_O0(Tile_X14Y10_FAB2RAM_C_O0),
+	.FAB2RAM_C_O1(Tile_X14Y10_FAB2RAM_C_O1),
+	.FAB2RAM_C_O2(Tile_X14Y10_FAB2RAM_C_O2),
+	.FAB2RAM_C_O3(Tile_X14Y10_FAB2RAM_C_O3),
+	.Config_accessC_bit0(Tile_X14Y10_Config_accessC_bit0),
+	.Config_accessC_bit1(Tile_X14Y10_Config_accessC_bit1),
+	.Config_accessC_bit2(Tile_X14Y10_Config_accessC_bit2),
+	.Config_accessC_bit3(Tile_X14Y10_Config_accessC_bit3),
+	.UserCLKo(Tile_X14Y10_UserCLKo),
+	.FrameData(Tile_X13Y10_FrameData_O), 
+	.FrameData_O(Tile_X14Y10_FrameData_O), 
+	.FrameStrobe(Tile_X14Y11_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y10_FrameStrobe_O)
+	);
+
+	W_IO Tile_X0Y11_W_IO (
+	.W1END(Tile_X1Y11_W1BEG[3:0]),
+	.W2MID(Tile_X1Y11_W2BEG[7:0]),
+	.W2END(Tile_X1Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X1Y11_WW4BEG[15:0]),
+	.W6END(Tile_X1Y11_W6BEG[11:0]),
+	.E1BEG(Tile_X0Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X0Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X0Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X0Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X0Y11_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.A_I_top(Tile_X0Y11_A_I_top),
+	.A_T_top(Tile_X0Y11_A_T_top),
+	.A_O_top(Tile_X0Y11_A_O_top),
+	.UserCLK(Tile_X0Y12_UserCLKo),
+	.B_I_top(Tile_X0Y11_B_I_top),
+	.B_T_top(Tile_X0Y11_B_T_top),
+	.B_O_top(Tile_X0Y11_B_O_top),
+	.A_config_C_bit0(Tile_X0Y11_A_config_C_bit0),
+	.A_config_C_bit1(Tile_X0Y11_A_config_C_bit1),
+	.A_config_C_bit2(Tile_X0Y11_A_config_C_bit2),
+	.A_config_C_bit3(Tile_X0Y11_A_config_C_bit3),
+	.B_config_C_bit0(Tile_X0Y11_B_config_C_bit0),
+	.B_config_C_bit1(Tile_X0Y11_B_config_C_bit1),
+	.B_config_C_bit2(Tile_X0Y11_B_config_C_bit2),
+	.B_config_C_bit3(Tile_X0Y11_B_config_C_bit3),
+	.UserCLKo(Tile_X0Y11_UserCLKo),
+	.FrameData(Tile_Y11_FrameData), 
+	.FrameData_O(Tile_X0Y11_FrameData_O), 
+	.FrameStrobe(Tile_X0Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X0Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X1Y11_LUT4AB (
+	.N1END(Tile_X1Y12_N1BEG[3:0]),
+	.N2MID(Tile_X1Y12_N2BEG[7:0]),
+	.N2END(Tile_X1Y12_N2BEGb[7:0]),
+	.N4END(Tile_X1Y12_N4BEG[15:0]),
+	.NN4END(Tile_X1Y12_NN4BEG[15:0]),
+	.Ci(Tile_X1Y12_Co[0:0]),
+	.E1END(Tile_X0Y11_E1BEG[3:0]),
+	.E2MID(Tile_X0Y11_E2BEG[7:0]),
+	.E2END(Tile_X0Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X0Y11_EE4BEG[15:0]),
+	.E6END(Tile_X0Y11_E6BEG[11:0]),
+	.S1END(Tile_X1Y10_S1BEG[3:0]),
+	.S2MID(Tile_X1Y10_S2BEG[7:0]),
+	.S2END(Tile_X1Y10_S2BEGb[7:0]),
+	.S4END(Tile_X1Y10_S4BEG[15:0]),
+	.SS4END(Tile_X1Y10_SS4BEG[15:0]),
+	.W1END(Tile_X2Y11_W1BEG[3:0]),
+	.W2MID(Tile_X2Y11_W2BEG[7:0]),
+	.W2END(Tile_X2Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X2Y11_WW4BEG[15:0]),
+	.W6END(Tile_X2Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X1Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y11_NN4BEG[15:0]),
+	.Co(Tile_X1Y11_Co[0:0]),
+	.E1BEG(Tile_X1Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X1Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X1Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X1Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X1Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X1Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X1Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X1Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X1Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X1Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X1Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X1Y12_UserCLKo),
+	.UserCLKo(Tile_X1Y11_UserCLKo),
+	.FrameData(Tile_X0Y11_FrameData_O), 
+	.FrameData_O(Tile_X1Y11_FrameData_O), 
+	.FrameStrobe(Tile_X1Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y11_FrameStrobe_O)
+	);
+
+	RegFile Tile_X2Y11_RegFile (
+	.N1END(Tile_X2Y12_N1BEG[3:0]),
+	.N2MID(Tile_X2Y12_N2BEG[7:0]),
+	.N2END(Tile_X2Y12_N2BEGb[7:0]),
+	.N4END(Tile_X2Y12_N4BEG[15:0]),
+	.NN4END(Tile_X2Y12_NN4BEG[15:0]),
+	.E1END(Tile_X1Y11_E1BEG[3:0]),
+	.E2MID(Tile_X1Y11_E2BEG[7:0]),
+	.E2END(Tile_X1Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X1Y11_EE4BEG[15:0]),
+	.E6END(Tile_X1Y11_E6BEG[11:0]),
+	.S1END(Tile_X2Y10_S1BEG[3:0]),
+	.S2MID(Tile_X2Y10_S2BEG[7:0]),
+	.S2END(Tile_X2Y10_S2BEGb[7:0]),
+	.S4END(Tile_X2Y10_S4BEG[15:0]),
+	.SS4END(Tile_X2Y10_SS4BEG[15:0]),
+	.W1END(Tile_X3Y11_W1BEG[3:0]),
+	.W2MID(Tile_X3Y11_W2BEG[7:0]),
+	.W2END(Tile_X3Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X3Y11_WW4BEG[15:0]),
+	.W6END(Tile_X3Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X2Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y11_NN4BEG[15:0]),
+	.E1BEG(Tile_X2Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X2Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X2Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X2Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X2Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X2Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X2Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X2Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X2Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X2Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X2Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X2Y12_UserCLKo),
+	.UserCLKo(Tile_X2Y11_UserCLKo),
+	.FrameData(Tile_X1Y11_FrameData_O), 
+	.FrameData_O(Tile_X2Y11_FrameData_O), 
+	.FrameStrobe(Tile_X2Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X3Y11_LUT4AB (
+	.N1END(Tile_X3Y12_N1BEG[3:0]),
+	.N2MID(Tile_X3Y12_N2BEG[7:0]),
+	.N2END(Tile_X3Y12_N2BEGb[7:0]),
+	.N4END(Tile_X3Y12_N4BEG[15:0]),
+	.NN4END(Tile_X3Y12_NN4BEG[15:0]),
+	.Ci(Tile_X3Y12_Co[0:0]),
+	.E1END(Tile_X2Y11_E1BEG[3:0]),
+	.E2MID(Tile_X2Y11_E2BEG[7:0]),
+	.E2END(Tile_X2Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X2Y11_EE4BEG[15:0]),
+	.E6END(Tile_X2Y11_E6BEG[11:0]),
+	.S1END(Tile_X3Y10_S1BEG[3:0]),
+	.S2MID(Tile_X3Y10_S2BEG[7:0]),
+	.S2END(Tile_X3Y10_S2BEGb[7:0]),
+	.S4END(Tile_X3Y10_S4BEG[15:0]),
+	.SS4END(Tile_X3Y10_SS4BEG[15:0]),
+	.W1END(Tile_X4Y11_W1BEG[3:0]),
+	.W2MID(Tile_X4Y11_W2BEG[7:0]),
+	.W2END(Tile_X4Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y11_WW4BEG[15:0]),
+	.W6END(Tile_X4Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X3Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y11_NN4BEG[15:0]),
+	.Co(Tile_X3Y11_Co[0:0]),
+	.E1BEG(Tile_X3Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X3Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X3Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X3Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X3Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X3Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X3Y12_UserCLKo),
+	.UserCLKo(Tile_X3Y11_UserCLKo),
+	.FrameData(Tile_X2Y11_FrameData_O), 
+	.FrameData_O(Tile_X3Y11_FrameData_O), 
+	.FrameStrobe(Tile_X3Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y11_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y11_LUT4AB (
+	.N1END(Tile_X5Y12_N1BEG[3:0]),
+	.N2MID(Tile_X5Y12_N2BEG[7:0]),
+	.N2END(Tile_X5Y12_N2BEGb[7:0]),
+	.N4END(Tile_X5Y12_N4BEG[15:0]),
+	.NN4END(Tile_X5Y12_NN4BEG[15:0]),
+	.Ci(Tile_X5Y12_Co[0:0]),
+	.E1END(Tile_X4Y11_E1BEG[3:0]),
+	.E2MID(Tile_X4Y11_E2BEG[7:0]),
+	.E2END(Tile_X4Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y11_EE4BEG[15:0]),
+	.E6END(Tile_X4Y11_E6BEG[11:0]),
+	.S1END(Tile_X5Y10_S1BEG[3:0]),
+	.S2MID(Tile_X5Y10_S2BEG[7:0]),
+	.S2END(Tile_X5Y10_S2BEGb[7:0]),
+	.S4END(Tile_X5Y10_S4BEG[15:0]),
+	.SS4END(Tile_X5Y10_SS4BEG[15:0]),
+	.W1END(Tile_X6Y11_W1BEG[3:0]),
+	.W2MID(Tile_X6Y11_W2BEG[7:0]),
+	.W2END(Tile_X6Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y11_WW4BEG[15:0]),
+	.W6END(Tile_X6Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y11_NN4BEG[15:0]),
+	.Co(Tile_X5Y11_Co[0:0]),
+	.E1BEG(Tile_X5Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y12_UserCLKo),
+	.UserCLKo(Tile_X5Y11_UserCLKo),
+	.FrameData(Tile_X4Y11_FrameData_O), 
+	.FrameData_O(Tile_X5Y11_FrameData_O), 
+	.FrameStrobe(Tile_X5Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y11_LUT4AB (
+	.N1END(Tile_X6Y12_N1BEG[3:0]),
+	.N2MID(Tile_X6Y12_N2BEG[7:0]),
+	.N2END(Tile_X6Y12_N2BEGb[7:0]),
+	.N4END(Tile_X6Y12_N4BEG[15:0]),
+	.NN4END(Tile_X6Y12_NN4BEG[15:0]),
+	.Ci(Tile_X6Y12_Co[0:0]),
+	.E1END(Tile_X5Y11_E1BEG[3:0]),
+	.E2MID(Tile_X5Y11_E2BEG[7:0]),
+	.E2END(Tile_X5Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y11_EE4BEG[15:0]),
+	.E6END(Tile_X5Y11_E6BEG[11:0]),
+	.S1END(Tile_X6Y10_S1BEG[3:0]),
+	.S2MID(Tile_X6Y10_S2BEG[7:0]),
+	.S2END(Tile_X6Y10_S2BEGb[7:0]),
+	.S4END(Tile_X6Y10_S4BEG[15:0]),
+	.SS4END(Tile_X6Y10_SS4BEG[15:0]),
+	.W1END(Tile_X7Y11_W1BEG[3:0]),
+	.W2MID(Tile_X7Y11_W2BEG[7:0]),
+	.W2END(Tile_X7Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y11_WW4BEG[15:0]),
+	.W6END(Tile_X7Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y11_NN4BEG[15:0]),
+	.Co(Tile_X6Y11_Co[0:0]),
+	.E1BEG(Tile_X6Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y12_UserCLKo),
+	.UserCLKo(Tile_X6Y11_UserCLKo),
+	.FrameData(Tile_X5Y11_FrameData_O), 
+	.FrameData_O(Tile_X6Y11_FrameData_O), 
+	.FrameStrobe(Tile_X6Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y11_LUT4AB (
+	.N1END(Tile_X7Y12_N1BEG[3:0]),
+	.N2MID(Tile_X7Y12_N2BEG[7:0]),
+	.N2END(Tile_X7Y12_N2BEGb[7:0]),
+	.N4END(Tile_X7Y12_N4BEG[15:0]),
+	.NN4END(Tile_X7Y12_NN4BEG[15:0]),
+	.Ci(Tile_X7Y12_Co[0:0]),
+	.E1END(Tile_X6Y11_E1BEG[3:0]),
+	.E2MID(Tile_X6Y11_E2BEG[7:0]),
+	.E2END(Tile_X6Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y11_EE4BEG[15:0]),
+	.E6END(Tile_X6Y11_E6BEG[11:0]),
+	.S1END(Tile_X7Y10_S1BEG[3:0]),
+	.S2MID(Tile_X7Y10_S2BEG[7:0]),
+	.S2END(Tile_X7Y10_S2BEGb[7:0]),
+	.S4END(Tile_X7Y10_S4BEG[15:0]),
+	.SS4END(Tile_X7Y10_SS4BEG[15:0]),
+	.W1END(Tile_X8Y11_W1BEG[3:0]),
+	.W2MID(Tile_X8Y11_W2BEG[7:0]),
+	.W2END(Tile_X8Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y11_WW4BEG[15:0]),
+	.W6END(Tile_X8Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y11_NN4BEG[15:0]),
+	.Co(Tile_X7Y11_Co[0:0]),
+	.E1BEG(Tile_X7Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y12_UserCLKo),
+	.UserCLKo(Tile_X7Y11_UserCLKo),
+	.FrameData(Tile_X6Y11_FrameData_O), 
+	.FrameData_O(Tile_X7Y11_FrameData_O), 
+	.FrameStrobe(Tile_X7Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y11_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y11_LUT4AB (
+	.N1END(Tile_X9Y12_N1BEG[3:0]),
+	.N2MID(Tile_X9Y12_N2BEG[7:0]),
+	.N2END(Tile_X9Y12_N2BEGb[7:0]),
+	.N4END(Tile_X9Y12_N4BEG[15:0]),
+	.NN4END(Tile_X9Y12_NN4BEG[15:0]),
+	.Ci(Tile_X9Y12_Co[0:0]),
+	.E1END(Tile_X8Y11_E1BEG[3:0]),
+	.E2MID(Tile_X8Y11_E2BEG[7:0]),
+	.E2END(Tile_X8Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y11_EE4BEG[15:0]),
+	.E6END(Tile_X8Y11_E6BEG[11:0]),
+	.S1END(Tile_X9Y10_S1BEG[3:0]),
+	.S2MID(Tile_X9Y10_S2BEG[7:0]),
+	.S2END(Tile_X9Y10_S2BEGb[7:0]),
+	.S4END(Tile_X9Y10_S4BEG[15:0]),
+	.SS4END(Tile_X9Y10_SS4BEG[15:0]),
+	.W1END(Tile_X10Y11_W1BEG[3:0]),
+	.W2MID(Tile_X10Y11_W2BEG[7:0]),
+	.W2END(Tile_X10Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y11_WW4BEG[15:0]),
+	.W6END(Tile_X10Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y11_NN4BEG[15:0]),
+	.Co(Tile_X9Y11_Co[0:0]),
+	.E1BEG(Tile_X9Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y12_UserCLKo),
+	.UserCLKo(Tile_X9Y11_UserCLKo),
+	.FrameData(Tile_X8Y11_FrameData_O), 
+	.FrameData_O(Tile_X9Y11_FrameData_O), 
+	.FrameStrobe(Tile_X9Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y11_LUT4AB (
+	.N1END(Tile_X10Y12_N1BEG[3:0]),
+	.N2MID(Tile_X10Y12_N2BEG[7:0]),
+	.N2END(Tile_X10Y12_N2BEGb[7:0]),
+	.N4END(Tile_X10Y12_N4BEG[15:0]),
+	.NN4END(Tile_X10Y12_NN4BEG[15:0]),
+	.Ci(Tile_X10Y12_Co[0:0]),
+	.E1END(Tile_X9Y11_E1BEG[3:0]),
+	.E2MID(Tile_X9Y11_E2BEG[7:0]),
+	.E2END(Tile_X9Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y11_EE4BEG[15:0]),
+	.E6END(Tile_X9Y11_E6BEG[11:0]),
+	.S1END(Tile_X10Y10_S1BEG[3:0]),
+	.S2MID(Tile_X10Y10_S2BEG[7:0]),
+	.S2END(Tile_X10Y10_S2BEGb[7:0]),
+	.S4END(Tile_X10Y10_S4BEG[15:0]),
+	.SS4END(Tile_X10Y10_SS4BEG[15:0]),
+	.W1END(Tile_X11Y11_W1BEG[3:0]),
+	.W2MID(Tile_X11Y11_W2BEG[7:0]),
+	.W2END(Tile_X11Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y11_WW4BEG[15:0]),
+	.W6END(Tile_X11Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y11_NN4BEG[15:0]),
+	.Co(Tile_X10Y11_Co[0:0]),
+	.E1BEG(Tile_X10Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y12_UserCLKo),
+	.UserCLKo(Tile_X10Y11_UserCLKo),
+	.FrameData(Tile_X9Y11_FrameData_O), 
+	.FrameData_O(Tile_X10Y11_FrameData_O), 
+	.FrameStrobe(Tile_X10Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X11Y11_LUT4AB (
+	.N1END(Tile_X11Y12_N1BEG[3:0]),
+	.N2MID(Tile_X11Y12_N2BEG[7:0]),
+	.N2END(Tile_X11Y12_N2BEGb[7:0]),
+	.N4END(Tile_X11Y12_N4BEG[15:0]),
+	.NN4END(Tile_X11Y12_NN4BEG[15:0]),
+	.Ci(Tile_X11Y12_Co[0:0]),
+	.E1END(Tile_X10Y11_E1BEG[3:0]),
+	.E2MID(Tile_X10Y11_E2BEG[7:0]),
+	.E2END(Tile_X10Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y11_EE4BEG[15:0]),
+	.E6END(Tile_X10Y11_E6BEG[11:0]),
+	.S1END(Tile_X11Y10_S1BEG[3:0]),
+	.S2MID(Tile_X11Y10_S2BEG[7:0]),
+	.S2END(Tile_X11Y10_S2BEGb[7:0]),
+	.S4END(Tile_X11Y10_S4BEG[15:0]),
+	.SS4END(Tile_X11Y10_SS4BEG[15:0]),
+	.W1END(Tile_X12Y11_W1BEG[3:0]),
+	.W2MID(Tile_X12Y11_W2BEG[7:0]),
+	.W2END(Tile_X12Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X12Y11_WW4BEG[15:0]),
+	.W6END(Tile_X12Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X11Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y11_NN4BEG[15:0]),
+	.Co(Tile_X11Y11_Co[0:0]),
+	.E1BEG(Tile_X11Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X11Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X11Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X11Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X11Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X11Y12_UserCLKo),
+	.UserCLKo(Tile_X11Y11_UserCLKo),
+	.FrameData(Tile_X10Y11_FrameData_O), 
+	.FrameData_O(Tile_X11Y11_FrameData_O), 
+	.FrameStrobe(Tile_X11Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y11_FrameStrobe_O)
+	);
+
+	RegFile Tile_X12Y11_RegFile (
+	.N1END(Tile_X12Y12_N1BEG[3:0]),
+	.N2MID(Tile_X12Y12_N2BEG[7:0]),
+	.N2END(Tile_X12Y12_N2BEGb[7:0]),
+	.N4END(Tile_X12Y12_N4BEG[15:0]),
+	.NN4END(Tile_X12Y12_NN4BEG[15:0]),
+	.E1END(Tile_X11Y11_E1BEG[3:0]),
+	.E2MID(Tile_X11Y11_E2BEG[7:0]),
+	.E2END(Tile_X11Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X11Y11_EE4BEG[15:0]),
+	.E6END(Tile_X11Y11_E6BEG[11:0]),
+	.S1END(Tile_X12Y10_S1BEG[3:0]),
+	.S2MID(Tile_X12Y10_S2BEG[7:0]),
+	.S2END(Tile_X12Y10_S2BEGb[7:0]),
+	.S4END(Tile_X12Y10_S4BEG[15:0]),
+	.SS4END(Tile_X12Y10_SS4BEG[15:0]),
+	.W1END(Tile_X13Y11_W1BEG[3:0]),
+	.W2MID(Tile_X13Y11_W2BEG[7:0]),
+	.W2END(Tile_X13Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X13Y11_WW4BEG[15:0]),
+	.W6END(Tile_X13Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X12Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y11_NN4BEG[15:0]),
+	.E1BEG(Tile_X12Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X12Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X12Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X12Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X12Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X12Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X12Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X12Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X12Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X12Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X12Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X12Y12_UserCLKo),
+	.UserCLKo(Tile_X12Y11_UserCLKo),
+	.FrameData(Tile_X11Y11_FrameData_O), 
+	.FrameData_O(Tile_X12Y11_FrameData_O), 
+	.FrameStrobe(Tile_X12Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y11_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X13Y11_LUT4AB (
+	.N1END(Tile_X13Y12_N1BEG[3:0]),
+	.N2MID(Tile_X13Y12_N2BEG[7:0]),
+	.N2END(Tile_X13Y12_N2BEGb[7:0]),
+	.N4END(Tile_X13Y12_N4BEG[15:0]),
+	.NN4END(Tile_X13Y12_NN4BEG[15:0]),
+	.Ci(Tile_X13Y12_Co[0:0]),
+	.E1END(Tile_X12Y11_E1BEG[3:0]),
+	.E2MID(Tile_X12Y11_E2BEG[7:0]),
+	.E2END(Tile_X12Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X12Y11_EE4BEG[15:0]),
+	.E6END(Tile_X12Y11_E6BEG[11:0]),
+	.S1END(Tile_X13Y10_S1BEG[3:0]),
+	.S2MID(Tile_X13Y10_S2BEG[7:0]),
+	.S2END(Tile_X13Y10_S2BEGb[7:0]),
+	.S4END(Tile_X13Y10_S4BEG[15:0]),
+	.SS4END(Tile_X13Y10_SS4BEG[15:0]),
+	.W1END(Tile_X14Y11_W1BEG[3:0]),
+	.W2MID(Tile_X14Y11_W2BEG[7:0]),
+	.W2END(Tile_X14Y11_W2BEGb[7:0]),
+	.WW4END(Tile_X14Y11_WW4BEG[15:0]),
+	.W6END(Tile_X14Y11_W6BEG[11:0]),
+	.N1BEG(Tile_X13Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y11_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y11_NN4BEG[15:0]),
+	.Co(Tile_X13Y11_Co[0:0]),
+	.E1BEG(Tile_X13Y11_E1BEG[3:0]),
+	.E2BEG(Tile_X13Y11_E2BEG[7:0]),
+	.E2BEGb(Tile_X13Y11_E2BEGb[7:0]),
+	.EE4BEG(Tile_X13Y11_EE4BEG[15:0]),
+	.E6BEG(Tile_X13Y11_E6BEG[11:0]),
+	.S1BEG(Tile_X13Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y11_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y11_SS4BEG[15:0]),
+	.W1BEG(Tile_X13Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X13Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X13Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X13Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X13Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X13Y12_UserCLKo),
+	.UserCLKo(Tile_X13Y11_UserCLKo),
+	.FrameData(Tile_X12Y11_FrameData_O), 
+	.FrameData_O(Tile_X13Y11_FrameData_O), 
+	.FrameStrobe(Tile_X13Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y11_FrameStrobe_O)
+	);
+
+	RAM_IO Tile_X14Y11_RAM_IO (
+	.N1END(Tile_X14Y12_N1BEG[3:0]),
+	.N2MID(Tile_X14Y12_N2BEG[7:0]),
+	.N2END(Tile_X14Y12_N2BEGb[7:0]),
+	.N4END(Tile_X14Y12_N4BEG[15:0]),
+	.E1END(Tile_X13Y11_E1BEG[3:0]),
+	.E2MID(Tile_X13Y11_E2BEG[7:0]),
+	.E2END(Tile_X13Y11_E2BEGb[7:0]),
+	.EE4END(Tile_X13Y11_EE4BEG[15:0]),
+	.E6END(Tile_X13Y11_E6BEG[11:0]),
+	.S1END(Tile_X14Y10_S1BEG[3:0]),
+	.S2MID(Tile_X14Y10_S2BEG[7:0]),
+	.S2END(Tile_X14Y10_S2BEGb[7:0]),
+	.S4END(Tile_X14Y10_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y11_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y11_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y11_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y11_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y11_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y11_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y11_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y11_S4BEG[15:0]),
+	.W1BEG(Tile_X14Y11_W1BEG[3:0]),
+	.W2BEG(Tile_X14Y11_W2BEG[7:0]),
+	.W2BEGb(Tile_X14Y11_W2BEGb[7:0]),
+	.WW4BEG(Tile_X14Y11_WW4BEG[15:0]),
+	.W6BEG(Tile_X14Y11_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.RAM2FAB_D0_I0(Tile_X14Y11_RAM2FAB_D0_I0),
+	.RAM2FAB_D0_I1(Tile_X14Y11_RAM2FAB_D0_I1),
+	.RAM2FAB_D0_I2(Tile_X14Y11_RAM2FAB_D0_I2),
+	.RAM2FAB_D0_I3(Tile_X14Y11_RAM2FAB_D0_I3),
+	.UserCLK(Tile_X14Y12_UserCLKo),
+	.RAM2FAB_D1_I0(Tile_X14Y11_RAM2FAB_D1_I0),
+	.RAM2FAB_D1_I1(Tile_X14Y11_RAM2FAB_D1_I1),
+	.RAM2FAB_D1_I2(Tile_X14Y11_RAM2FAB_D1_I2),
+	.RAM2FAB_D1_I3(Tile_X14Y11_RAM2FAB_D1_I3),
+	.RAM2FAB_D2_I0(Tile_X14Y11_RAM2FAB_D2_I0),
+	.RAM2FAB_D2_I1(Tile_X14Y11_RAM2FAB_D2_I1),
+	.RAM2FAB_D2_I2(Tile_X14Y11_RAM2FAB_D2_I2),
+	.RAM2FAB_D2_I3(Tile_X14Y11_RAM2FAB_D2_I3),
+	.RAM2FAB_D3_I0(Tile_X14Y11_RAM2FAB_D3_I0),
+	.RAM2FAB_D3_I1(Tile_X14Y11_RAM2FAB_D3_I1),
+	.RAM2FAB_D3_I2(Tile_X14Y11_RAM2FAB_D3_I2),
+	.RAM2FAB_D3_I3(Tile_X14Y11_RAM2FAB_D3_I3),
+	.FAB2RAM_D0_O0(Tile_X14Y11_FAB2RAM_D0_O0),
+	.FAB2RAM_D0_O1(Tile_X14Y11_FAB2RAM_D0_O1),
+	.FAB2RAM_D0_O2(Tile_X14Y11_FAB2RAM_D0_O2),
+	.FAB2RAM_D0_O3(Tile_X14Y11_FAB2RAM_D0_O3),
+	.FAB2RAM_D1_O0(Tile_X14Y11_FAB2RAM_D1_O0),
+	.FAB2RAM_D1_O1(Tile_X14Y11_FAB2RAM_D1_O1),
+	.FAB2RAM_D1_O2(Tile_X14Y11_FAB2RAM_D1_O2),
+	.FAB2RAM_D1_O3(Tile_X14Y11_FAB2RAM_D1_O3),
+	.FAB2RAM_D2_O0(Tile_X14Y11_FAB2RAM_D2_O0),
+	.FAB2RAM_D2_O1(Tile_X14Y11_FAB2RAM_D2_O1),
+	.FAB2RAM_D2_O2(Tile_X14Y11_FAB2RAM_D2_O2),
+	.FAB2RAM_D2_O3(Tile_X14Y11_FAB2RAM_D2_O3),
+	.FAB2RAM_D3_O0(Tile_X14Y11_FAB2RAM_D3_O0),
+	.FAB2RAM_D3_O1(Tile_X14Y11_FAB2RAM_D3_O1),
+	.FAB2RAM_D3_O2(Tile_X14Y11_FAB2RAM_D3_O2),
+	.FAB2RAM_D3_O3(Tile_X14Y11_FAB2RAM_D3_O3),
+	.FAB2RAM_A0_O0(Tile_X14Y11_FAB2RAM_A0_O0),
+	.FAB2RAM_A0_O1(Tile_X14Y11_FAB2RAM_A0_O1),
+	.FAB2RAM_A0_O2(Tile_X14Y11_FAB2RAM_A0_O2),
+	.FAB2RAM_A0_O3(Tile_X14Y11_FAB2RAM_A0_O3),
+	.FAB2RAM_A1_O0(Tile_X14Y11_FAB2RAM_A1_O0),
+	.FAB2RAM_A1_O1(Tile_X14Y11_FAB2RAM_A1_O1),
+	.FAB2RAM_A1_O2(Tile_X14Y11_FAB2RAM_A1_O2),
+	.FAB2RAM_A1_O3(Tile_X14Y11_FAB2RAM_A1_O3),
+	.FAB2RAM_C_O0(Tile_X14Y11_FAB2RAM_C_O0),
+	.FAB2RAM_C_O1(Tile_X14Y11_FAB2RAM_C_O1),
+	.FAB2RAM_C_O2(Tile_X14Y11_FAB2RAM_C_O2),
+	.FAB2RAM_C_O3(Tile_X14Y11_FAB2RAM_C_O3),
+	.Config_accessC_bit0(Tile_X14Y11_Config_accessC_bit0),
+	.Config_accessC_bit1(Tile_X14Y11_Config_accessC_bit1),
+	.Config_accessC_bit2(Tile_X14Y11_Config_accessC_bit2),
+	.Config_accessC_bit3(Tile_X14Y11_Config_accessC_bit3),
+	.UserCLKo(Tile_X14Y11_UserCLKo),
+	.FrameData(Tile_X13Y11_FrameData_O), 
+	.FrameData_O(Tile_X14Y11_FrameData_O), 
+	.FrameStrobe(Tile_X14Y12_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y11_FrameStrobe_O)
+	);
+
+	W_IO Tile_X0Y12_W_IO (
+	.W1END(Tile_X1Y12_W1BEG[3:0]),
+	.W2MID(Tile_X1Y12_W2BEG[7:0]),
+	.W2END(Tile_X1Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X1Y12_WW4BEG[15:0]),
+	.W6END(Tile_X1Y12_W6BEG[11:0]),
+	.E1BEG(Tile_X0Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X0Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X0Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X0Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X0Y12_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.A_I_top(Tile_X0Y12_A_I_top),
+	.A_T_top(Tile_X0Y12_A_T_top),
+	.A_O_top(Tile_X0Y12_A_O_top),
+	.UserCLK(Tile_X0Y13_UserCLKo),
+	.B_I_top(Tile_X0Y12_B_I_top),
+	.B_T_top(Tile_X0Y12_B_T_top),
+	.B_O_top(Tile_X0Y12_B_O_top),
+	.A_config_C_bit0(Tile_X0Y12_A_config_C_bit0),
+	.A_config_C_bit1(Tile_X0Y12_A_config_C_bit1),
+	.A_config_C_bit2(Tile_X0Y12_A_config_C_bit2),
+	.A_config_C_bit3(Tile_X0Y12_A_config_C_bit3),
+	.B_config_C_bit0(Tile_X0Y12_B_config_C_bit0),
+	.B_config_C_bit1(Tile_X0Y12_B_config_C_bit1),
+	.B_config_C_bit2(Tile_X0Y12_B_config_C_bit2),
+	.B_config_C_bit3(Tile_X0Y12_B_config_C_bit3),
+	.UserCLKo(Tile_X0Y12_UserCLKo),
+	.FrameData(Tile_Y12_FrameData), 
+	.FrameData_O(Tile_X0Y12_FrameData_O), 
+	.FrameStrobe(Tile_X0Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X0Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X1Y12_LUT4AB (
+	.N1END(Tile_X1Y13_N1BEG[3:0]),
+	.N2MID(Tile_X1Y13_N2BEG[7:0]),
+	.N2END(Tile_X1Y13_N2BEGb[7:0]),
+	.N4END(Tile_X1Y13_N4BEG[15:0]),
+	.NN4END(Tile_X1Y13_NN4BEG[15:0]),
+	.Ci(Tile_X1Y13_Co[0:0]),
+	.E1END(Tile_X0Y12_E1BEG[3:0]),
+	.E2MID(Tile_X0Y12_E2BEG[7:0]),
+	.E2END(Tile_X0Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X0Y12_EE4BEG[15:0]),
+	.E6END(Tile_X0Y12_E6BEG[11:0]),
+	.S1END(Tile_X1Y11_S1BEG[3:0]),
+	.S2MID(Tile_X1Y11_S2BEG[7:0]),
+	.S2END(Tile_X1Y11_S2BEGb[7:0]),
+	.S4END(Tile_X1Y11_S4BEG[15:0]),
+	.SS4END(Tile_X1Y11_SS4BEG[15:0]),
+	.W1END(Tile_X2Y12_W1BEG[3:0]),
+	.W2MID(Tile_X2Y12_W2BEG[7:0]),
+	.W2END(Tile_X2Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X2Y12_WW4BEG[15:0]),
+	.W6END(Tile_X2Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X1Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y12_NN4BEG[15:0]),
+	.Co(Tile_X1Y12_Co[0:0]),
+	.E1BEG(Tile_X1Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X1Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X1Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X1Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X1Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X1Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X1Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X1Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X1Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X1Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X1Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X1Y13_UserCLKo),
+	.UserCLKo(Tile_X1Y12_UserCLKo),
+	.FrameData(Tile_X0Y12_FrameData_O), 
+	.FrameData_O(Tile_X1Y12_FrameData_O), 
+	.FrameStrobe(Tile_X1Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y12_FrameStrobe_O)
+	);
+
+	RegFile Tile_X2Y12_RegFile (
+	.N1END(Tile_X2Y13_N1BEG[3:0]),
+	.N2MID(Tile_X2Y13_N2BEG[7:0]),
+	.N2END(Tile_X2Y13_N2BEGb[7:0]),
+	.N4END(Tile_X2Y13_N4BEG[15:0]),
+	.NN4END(Tile_X2Y13_NN4BEG[15:0]),
+	.E1END(Tile_X1Y12_E1BEG[3:0]),
+	.E2MID(Tile_X1Y12_E2BEG[7:0]),
+	.E2END(Tile_X1Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X1Y12_EE4BEG[15:0]),
+	.E6END(Tile_X1Y12_E6BEG[11:0]),
+	.S1END(Tile_X2Y11_S1BEG[3:0]),
+	.S2MID(Tile_X2Y11_S2BEG[7:0]),
+	.S2END(Tile_X2Y11_S2BEGb[7:0]),
+	.S4END(Tile_X2Y11_S4BEG[15:0]),
+	.SS4END(Tile_X2Y11_SS4BEG[15:0]),
+	.W1END(Tile_X3Y12_W1BEG[3:0]),
+	.W2MID(Tile_X3Y12_W2BEG[7:0]),
+	.W2END(Tile_X3Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X3Y12_WW4BEG[15:0]),
+	.W6END(Tile_X3Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X2Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y12_NN4BEG[15:0]),
+	.E1BEG(Tile_X2Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X2Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X2Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X2Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X2Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X2Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X2Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X2Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X2Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X2Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X2Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X2Y13_UserCLKo),
+	.UserCLKo(Tile_X2Y12_UserCLKo),
+	.FrameData(Tile_X1Y12_FrameData_O), 
+	.FrameData_O(Tile_X2Y12_FrameData_O), 
+	.FrameStrobe(Tile_X2Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X3Y12_LUT4AB (
+	.N1END(Tile_X3Y13_N1BEG[3:0]),
+	.N2MID(Tile_X3Y13_N2BEG[7:0]),
+	.N2END(Tile_X3Y13_N2BEGb[7:0]),
+	.N4END(Tile_X3Y13_N4BEG[15:0]),
+	.NN4END(Tile_X3Y13_NN4BEG[15:0]),
+	.Ci(Tile_X3Y13_Co[0:0]),
+	.E1END(Tile_X2Y12_E1BEG[3:0]),
+	.E2MID(Tile_X2Y12_E2BEG[7:0]),
+	.E2END(Tile_X2Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X2Y12_EE4BEG[15:0]),
+	.E6END(Tile_X2Y12_E6BEG[11:0]),
+	.S1END(Tile_X3Y11_S1BEG[3:0]),
+	.S2MID(Tile_X3Y11_S2BEG[7:0]),
+	.S2END(Tile_X3Y11_S2BEGb[7:0]),
+	.S4END(Tile_X3Y11_S4BEG[15:0]),
+	.SS4END(Tile_X3Y11_SS4BEG[15:0]),
+	.W1END(Tile_X4Y12_W1BEG[3:0]),
+	.W2MID(Tile_X4Y12_W2BEG[7:0]),
+	.W2END(Tile_X4Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y12_WW4BEG[15:0]),
+	.W6END(Tile_X4Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X3Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y12_NN4BEG[15:0]),
+	.Co(Tile_X3Y12_Co[0:0]),
+	.E1BEG(Tile_X3Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X3Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X3Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X3Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X3Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X3Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X3Y13_UserCLKo),
+	.UserCLKo(Tile_X3Y12_UserCLKo),
+	.FrameData(Tile_X2Y12_FrameData_O), 
+	.FrameData_O(Tile_X3Y12_FrameData_O), 
+	.FrameStrobe(Tile_X3Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y12_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y12_LUT4AB (
+	.N1END(Tile_X5Y13_N1BEG[3:0]),
+	.N2MID(Tile_X5Y13_N2BEG[7:0]),
+	.N2END(Tile_X5Y13_N2BEGb[7:0]),
+	.N4END(Tile_X5Y13_N4BEG[15:0]),
+	.NN4END(Tile_X5Y13_NN4BEG[15:0]),
+	.Ci(Tile_X5Y13_Co[0:0]),
+	.E1END(Tile_X4Y12_E1BEG[3:0]),
+	.E2MID(Tile_X4Y12_E2BEG[7:0]),
+	.E2END(Tile_X4Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y12_EE4BEG[15:0]),
+	.E6END(Tile_X4Y12_E6BEG[11:0]),
+	.S1END(Tile_X5Y11_S1BEG[3:0]),
+	.S2MID(Tile_X5Y11_S2BEG[7:0]),
+	.S2END(Tile_X5Y11_S2BEGb[7:0]),
+	.S4END(Tile_X5Y11_S4BEG[15:0]),
+	.SS4END(Tile_X5Y11_SS4BEG[15:0]),
+	.W1END(Tile_X6Y12_W1BEG[3:0]),
+	.W2MID(Tile_X6Y12_W2BEG[7:0]),
+	.W2END(Tile_X6Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y12_WW4BEG[15:0]),
+	.W6END(Tile_X6Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y12_NN4BEG[15:0]),
+	.Co(Tile_X5Y12_Co[0:0]),
+	.E1BEG(Tile_X5Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y13_UserCLKo),
+	.UserCLKo(Tile_X5Y12_UserCLKo),
+	.FrameData(Tile_X4Y12_FrameData_O), 
+	.FrameData_O(Tile_X5Y12_FrameData_O), 
+	.FrameStrobe(Tile_X5Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y12_LUT4AB (
+	.N1END(Tile_X6Y13_N1BEG[3:0]),
+	.N2MID(Tile_X6Y13_N2BEG[7:0]),
+	.N2END(Tile_X6Y13_N2BEGb[7:0]),
+	.N4END(Tile_X6Y13_N4BEG[15:0]),
+	.NN4END(Tile_X6Y13_NN4BEG[15:0]),
+	.Ci(Tile_X6Y13_Co[0:0]),
+	.E1END(Tile_X5Y12_E1BEG[3:0]),
+	.E2MID(Tile_X5Y12_E2BEG[7:0]),
+	.E2END(Tile_X5Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y12_EE4BEG[15:0]),
+	.E6END(Tile_X5Y12_E6BEG[11:0]),
+	.S1END(Tile_X6Y11_S1BEG[3:0]),
+	.S2MID(Tile_X6Y11_S2BEG[7:0]),
+	.S2END(Tile_X6Y11_S2BEGb[7:0]),
+	.S4END(Tile_X6Y11_S4BEG[15:0]),
+	.SS4END(Tile_X6Y11_SS4BEG[15:0]),
+	.W1END(Tile_X7Y12_W1BEG[3:0]),
+	.W2MID(Tile_X7Y12_W2BEG[7:0]),
+	.W2END(Tile_X7Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y12_WW4BEG[15:0]),
+	.W6END(Tile_X7Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y12_NN4BEG[15:0]),
+	.Co(Tile_X6Y12_Co[0:0]),
+	.E1BEG(Tile_X6Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y13_UserCLKo),
+	.UserCLKo(Tile_X6Y12_UserCLKo),
+	.FrameData(Tile_X5Y12_FrameData_O), 
+	.FrameData_O(Tile_X6Y12_FrameData_O), 
+	.FrameStrobe(Tile_X6Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y12_LUT4AB (
+	.N1END(Tile_X7Y13_N1BEG[3:0]),
+	.N2MID(Tile_X7Y13_N2BEG[7:0]),
+	.N2END(Tile_X7Y13_N2BEGb[7:0]),
+	.N4END(Tile_X7Y13_N4BEG[15:0]),
+	.NN4END(Tile_X7Y13_NN4BEG[15:0]),
+	.Ci(Tile_X7Y13_Co[0:0]),
+	.E1END(Tile_X6Y12_E1BEG[3:0]),
+	.E2MID(Tile_X6Y12_E2BEG[7:0]),
+	.E2END(Tile_X6Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y12_EE4BEG[15:0]),
+	.E6END(Tile_X6Y12_E6BEG[11:0]),
+	.S1END(Tile_X7Y11_S1BEG[3:0]),
+	.S2MID(Tile_X7Y11_S2BEG[7:0]),
+	.S2END(Tile_X7Y11_S2BEGb[7:0]),
+	.S4END(Tile_X7Y11_S4BEG[15:0]),
+	.SS4END(Tile_X7Y11_SS4BEG[15:0]),
+	.W1END(Tile_X8Y12_W1BEG[3:0]),
+	.W2MID(Tile_X8Y12_W2BEG[7:0]),
+	.W2END(Tile_X8Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y12_WW4BEG[15:0]),
+	.W6END(Tile_X8Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y12_NN4BEG[15:0]),
+	.Co(Tile_X7Y12_Co[0:0]),
+	.E1BEG(Tile_X7Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y13_UserCLKo),
+	.UserCLKo(Tile_X7Y12_UserCLKo),
+	.FrameData(Tile_X6Y12_FrameData_O), 
+	.FrameData_O(Tile_X7Y12_FrameData_O), 
+	.FrameStrobe(Tile_X7Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y12_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y12_LUT4AB (
+	.N1END(Tile_X9Y13_N1BEG[3:0]),
+	.N2MID(Tile_X9Y13_N2BEG[7:0]),
+	.N2END(Tile_X9Y13_N2BEGb[7:0]),
+	.N4END(Tile_X9Y13_N4BEG[15:0]),
+	.NN4END(Tile_X9Y13_NN4BEG[15:0]),
+	.Ci(Tile_X9Y13_Co[0:0]),
+	.E1END(Tile_X8Y12_E1BEG[3:0]),
+	.E2MID(Tile_X8Y12_E2BEG[7:0]),
+	.E2END(Tile_X8Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y12_EE4BEG[15:0]),
+	.E6END(Tile_X8Y12_E6BEG[11:0]),
+	.S1END(Tile_X9Y11_S1BEG[3:0]),
+	.S2MID(Tile_X9Y11_S2BEG[7:0]),
+	.S2END(Tile_X9Y11_S2BEGb[7:0]),
+	.S4END(Tile_X9Y11_S4BEG[15:0]),
+	.SS4END(Tile_X9Y11_SS4BEG[15:0]),
+	.W1END(Tile_X10Y12_W1BEG[3:0]),
+	.W2MID(Tile_X10Y12_W2BEG[7:0]),
+	.W2END(Tile_X10Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y12_WW4BEG[15:0]),
+	.W6END(Tile_X10Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y12_NN4BEG[15:0]),
+	.Co(Tile_X9Y12_Co[0:0]),
+	.E1BEG(Tile_X9Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y13_UserCLKo),
+	.UserCLKo(Tile_X9Y12_UserCLKo),
+	.FrameData(Tile_X8Y12_FrameData_O), 
+	.FrameData_O(Tile_X9Y12_FrameData_O), 
+	.FrameStrobe(Tile_X9Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y12_LUT4AB (
+	.N1END(Tile_X10Y13_N1BEG[3:0]),
+	.N2MID(Tile_X10Y13_N2BEG[7:0]),
+	.N2END(Tile_X10Y13_N2BEGb[7:0]),
+	.N4END(Tile_X10Y13_N4BEG[15:0]),
+	.NN4END(Tile_X10Y13_NN4BEG[15:0]),
+	.Ci(Tile_X10Y13_Co[0:0]),
+	.E1END(Tile_X9Y12_E1BEG[3:0]),
+	.E2MID(Tile_X9Y12_E2BEG[7:0]),
+	.E2END(Tile_X9Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y12_EE4BEG[15:0]),
+	.E6END(Tile_X9Y12_E6BEG[11:0]),
+	.S1END(Tile_X10Y11_S1BEG[3:0]),
+	.S2MID(Tile_X10Y11_S2BEG[7:0]),
+	.S2END(Tile_X10Y11_S2BEGb[7:0]),
+	.S4END(Tile_X10Y11_S4BEG[15:0]),
+	.SS4END(Tile_X10Y11_SS4BEG[15:0]),
+	.W1END(Tile_X11Y12_W1BEG[3:0]),
+	.W2MID(Tile_X11Y12_W2BEG[7:0]),
+	.W2END(Tile_X11Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y12_WW4BEG[15:0]),
+	.W6END(Tile_X11Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y12_NN4BEG[15:0]),
+	.Co(Tile_X10Y12_Co[0:0]),
+	.E1BEG(Tile_X10Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y13_UserCLKo),
+	.UserCLKo(Tile_X10Y12_UserCLKo),
+	.FrameData(Tile_X9Y12_FrameData_O), 
+	.FrameData_O(Tile_X10Y12_FrameData_O), 
+	.FrameStrobe(Tile_X10Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X11Y12_LUT4AB (
+	.N1END(Tile_X11Y13_N1BEG[3:0]),
+	.N2MID(Tile_X11Y13_N2BEG[7:0]),
+	.N2END(Tile_X11Y13_N2BEGb[7:0]),
+	.N4END(Tile_X11Y13_N4BEG[15:0]),
+	.NN4END(Tile_X11Y13_NN4BEG[15:0]),
+	.Ci(Tile_X11Y13_Co[0:0]),
+	.E1END(Tile_X10Y12_E1BEG[3:0]),
+	.E2MID(Tile_X10Y12_E2BEG[7:0]),
+	.E2END(Tile_X10Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y12_EE4BEG[15:0]),
+	.E6END(Tile_X10Y12_E6BEG[11:0]),
+	.S1END(Tile_X11Y11_S1BEG[3:0]),
+	.S2MID(Tile_X11Y11_S2BEG[7:0]),
+	.S2END(Tile_X11Y11_S2BEGb[7:0]),
+	.S4END(Tile_X11Y11_S4BEG[15:0]),
+	.SS4END(Tile_X11Y11_SS4BEG[15:0]),
+	.W1END(Tile_X12Y12_W1BEG[3:0]),
+	.W2MID(Tile_X12Y12_W2BEG[7:0]),
+	.W2END(Tile_X12Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X12Y12_WW4BEG[15:0]),
+	.W6END(Tile_X12Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X11Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y12_NN4BEG[15:0]),
+	.Co(Tile_X11Y12_Co[0:0]),
+	.E1BEG(Tile_X11Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X11Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X11Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X11Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X11Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X11Y13_UserCLKo),
+	.UserCLKo(Tile_X11Y12_UserCLKo),
+	.FrameData(Tile_X10Y12_FrameData_O), 
+	.FrameData_O(Tile_X11Y12_FrameData_O), 
+	.FrameStrobe(Tile_X11Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y12_FrameStrobe_O)
+	);
+
+	RegFile Tile_X12Y12_RegFile (
+	.N1END(Tile_X12Y13_N1BEG[3:0]),
+	.N2MID(Tile_X12Y13_N2BEG[7:0]),
+	.N2END(Tile_X12Y13_N2BEGb[7:0]),
+	.N4END(Tile_X12Y13_N4BEG[15:0]),
+	.NN4END(Tile_X12Y13_NN4BEG[15:0]),
+	.E1END(Tile_X11Y12_E1BEG[3:0]),
+	.E2MID(Tile_X11Y12_E2BEG[7:0]),
+	.E2END(Tile_X11Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X11Y12_EE4BEG[15:0]),
+	.E6END(Tile_X11Y12_E6BEG[11:0]),
+	.S1END(Tile_X12Y11_S1BEG[3:0]),
+	.S2MID(Tile_X12Y11_S2BEG[7:0]),
+	.S2END(Tile_X12Y11_S2BEGb[7:0]),
+	.S4END(Tile_X12Y11_S4BEG[15:0]),
+	.SS4END(Tile_X12Y11_SS4BEG[15:0]),
+	.W1END(Tile_X13Y12_W1BEG[3:0]),
+	.W2MID(Tile_X13Y12_W2BEG[7:0]),
+	.W2END(Tile_X13Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X13Y12_WW4BEG[15:0]),
+	.W6END(Tile_X13Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X12Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y12_NN4BEG[15:0]),
+	.E1BEG(Tile_X12Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X12Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X12Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X12Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X12Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X12Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X12Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X12Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X12Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X12Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X12Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X12Y13_UserCLKo),
+	.UserCLKo(Tile_X12Y12_UserCLKo),
+	.FrameData(Tile_X11Y12_FrameData_O), 
+	.FrameData_O(Tile_X12Y12_FrameData_O), 
+	.FrameStrobe(Tile_X12Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y12_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X13Y12_LUT4AB (
+	.N1END(Tile_X13Y13_N1BEG[3:0]),
+	.N2MID(Tile_X13Y13_N2BEG[7:0]),
+	.N2END(Tile_X13Y13_N2BEGb[7:0]),
+	.N4END(Tile_X13Y13_N4BEG[15:0]),
+	.NN4END(Tile_X13Y13_NN4BEG[15:0]),
+	.Ci(Tile_X13Y13_Co[0:0]),
+	.E1END(Tile_X12Y12_E1BEG[3:0]),
+	.E2MID(Tile_X12Y12_E2BEG[7:0]),
+	.E2END(Tile_X12Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X12Y12_EE4BEG[15:0]),
+	.E6END(Tile_X12Y12_E6BEG[11:0]),
+	.S1END(Tile_X13Y11_S1BEG[3:0]),
+	.S2MID(Tile_X13Y11_S2BEG[7:0]),
+	.S2END(Tile_X13Y11_S2BEGb[7:0]),
+	.S4END(Tile_X13Y11_S4BEG[15:0]),
+	.SS4END(Tile_X13Y11_SS4BEG[15:0]),
+	.W1END(Tile_X14Y12_W1BEG[3:0]),
+	.W2MID(Tile_X14Y12_W2BEG[7:0]),
+	.W2END(Tile_X14Y12_W2BEGb[7:0]),
+	.WW4END(Tile_X14Y12_WW4BEG[15:0]),
+	.W6END(Tile_X14Y12_W6BEG[11:0]),
+	.N1BEG(Tile_X13Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y12_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y12_NN4BEG[15:0]),
+	.Co(Tile_X13Y12_Co[0:0]),
+	.E1BEG(Tile_X13Y12_E1BEG[3:0]),
+	.E2BEG(Tile_X13Y12_E2BEG[7:0]),
+	.E2BEGb(Tile_X13Y12_E2BEGb[7:0]),
+	.EE4BEG(Tile_X13Y12_EE4BEG[15:0]),
+	.E6BEG(Tile_X13Y12_E6BEG[11:0]),
+	.S1BEG(Tile_X13Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y12_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y12_SS4BEG[15:0]),
+	.W1BEG(Tile_X13Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X13Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X13Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X13Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X13Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X13Y13_UserCLKo),
+	.UserCLKo(Tile_X13Y12_UserCLKo),
+	.FrameData(Tile_X12Y12_FrameData_O), 
+	.FrameData_O(Tile_X13Y12_FrameData_O), 
+	.FrameStrobe(Tile_X13Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y12_FrameStrobe_O)
+	);
+
+	RAM_IO Tile_X14Y12_RAM_IO (
+	.N1END(Tile_X14Y13_N1BEG[3:0]),
+	.N2MID(Tile_X14Y13_N2BEG[7:0]),
+	.N2END(Tile_X14Y13_N2BEGb[7:0]),
+	.N4END(Tile_X14Y13_N4BEG[15:0]),
+	.E1END(Tile_X13Y12_E1BEG[3:0]),
+	.E2MID(Tile_X13Y12_E2BEG[7:0]),
+	.E2END(Tile_X13Y12_E2BEGb[7:0]),
+	.EE4END(Tile_X13Y12_EE4BEG[15:0]),
+	.E6END(Tile_X13Y12_E6BEG[11:0]),
+	.S1END(Tile_X14Y11_S1BEG[3:0]),
+	.S2MID(Tile_X14Y11_S2BEG[7:0]),
+	.S2END(Tile_X14Y11_S2BEGb[7:0]),
+	.S4END(Tile_X14Y11_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y12_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y12_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y12_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y12_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y12_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y12_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y12_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y12_S4BEG[15:0]),
+	.W1BEG(Tile_X14Y12_W1BEG[3:0]),
+	.W2BEG(Tile_X14Y12_W2BEG[7:0]),
+	.W2BEGb(Tile_X14Y12_W2BEGb[7:0]),
+	.WW4BEG(Tile_X14Y12_WW4BEG[15:0]),
+	.W6BEG(Tile_X14Y12_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.RAM2FAB_D0_I0(Tile_X14Y12_RAM2FAB_D0_I0),
+	.RAM2FAB_D0_I1(Tile_X14Y12_RAM2FAB_D0_I1),
+	.RAM2FAB_D0_I2(Tile_X14Y12_RAM2FAB_D0_I2),
+	.RAM2FAB_D0_I3(Tile_X14Y12_RAM2FAB_D0_I3),
+	.UserCLK(Tile_X14Y13_UserCLKo),
+	.RAM2FAB_D1_I0(Tile_X14Y12_RAM2FAB_D1_I0),
+	.RAM2FAB_D1_I1(Tile_X14Y12_RAM2FAB_D1_I1),
+	.RAM2FAB_D1_I2(Tile_X14Y12_RAM2FAB_D1_I2),
+	.RAM2FAB_D1_I3(Tile_X14Y12_RAM2FAB_D1_I3),
+	.RAM2FAB_D2_I0(Tile_X14Y12_RAM2FAB_D2_I0),
+	.RAM2FAB_D2_I1(Tile_X14Y12_RAM2FAB_D2_I1),
+	.RAM2FAB_D2_I2(Tile_X14Y12_RAM2FAB_D2_I2),
+	.RAM2FAB_D2_I3(Tile_X14Y12_RAM2FAB_D2_I3),
+	.RAM2FAB_D3_I0(Tile_X14Y12_RAM2FAB_D3_I0),
+	.RAM2FAB_D3_I1(Tile_X14Y12_RAM2FAB_D3_I1),
+	.RAM2FAB_D3_I2(Tile_X14Y12_RAM2FAB_D3_I2),
+	.RAM2FAB_D3_I3(Tile_X14Y12_RAM2FAB_D3_I3),
+	.FAB2RAM_D0_O0(Tile_X14Y12_FAB2RAM_D0_O0),
+	.FAB2RAM_D0_O1(Tile_X14Y12_FAB2RAM_D0_O1),
+	.FAB2RAM_D0_O2(Tile_X14Y12_FAB2RAM_D0_O2),
+	.FAB2RAM_D0_O3(Tile_X14Y12_FAB2RAM_D0_O3),
+	.FAB2RAM_D1_O0(Tile_X14Y12_FAB2RAM_D1_O0),
+	.FAB2RAM_D1_O1(Tile_X14Y12_FAB2RAM_D1_O1),
+	.FAB2RAM_D1_O2(Tile_X14Y12_FAB2RAM_D1_O2),
+	.FAB2RAM_D1_O3(Tile_X14Y12_FAB2RAM_D1_O3),
+	.FAB2RAM_D2_O0(Tile_X14Y12_FAB2RAM_D2_O0),
+	.FAB2RAM_D2_O1(Tile_X14Y12_FAB2RAM_D2_O1),
+	.FAB2RAM_D2_O2(Tile_X14Y12_FAB2RAM_D2_O2),
+	.FAB2RAM_D2_O3(Tile_X14Y12_FAB2RAM_D2_O3),
+	.FAB2RAM_D3_O0(Tile_X14Y12_FAB2RAM_D3_O0),
+	.FAB2RAM_D3_O1(Tile_X14Y12_FAB2RAM_D3_O1),
+	.FAB2RAM_D3_O2(Tile_X14Y12_FAB2RAM_D3_O2),
+	.FAB2RAM_D3_O3(Tile_X14Y12_FAB2RAM_D3_O3),
+	.FAB2RAM_A0_O0(Tile_X14Y12_FAB2RAM_A0_O0),
+	.FAB2RAM_A0_O1(Tile_X14Y12_FAB2RAM_A0_O1),
+	.FAB2RAM_A0_O2(Tile_X14Y12_FAB2RAM_A0_O2),
+	.FAB2RAM_A0_O3(Tile_X14Y12_FAB2RAM_A0_O3),
+	.FAB2RAM_A1_O0(Tile_X14Y12_FAB2RAM_A1_O0),
+	.FAB2RAM_A1_O1(Tile_X14Y12_FAB2RAM_A1_O1),
+	.FAB2RAM_A1_O2(Tile_X14Y12_FAB2RAM_A1_O2),
+	.FAB2RAM_A1_O3(Tile_X14Y12_FAB2RAM_A1_O3),
+	.FAB2RAM_C_O0(Tile_X14Y12_FAB2RAM_C_O0),
+	.FAB2RAM_C_O1(Tile_X14Y12_FAB2RAM_C_O1),
+	.FAB2RAM_C_O2(Tile_X14Y12_FAB2RAM_C_O2),
+	.FAB2RAM_C_O3(Tile_X14Y12_FAB2RAM_C_O3),
+	.Config_accessC_bit0(Tile_X14Y12_Config_accessC_bit0),
+	.Config_accessC_bit1(Tile_X14Y12_Config_accessC_bit1),
+	.Config_accessC_bit2(Tile_X14Y12_Config_accessC_bit2),
+	.Config_accessC_bit3(Tile_X14Y12_Config_accessC_bit3),
+	.UserCLKo(Tile_X14Y12_UserCLKo),
+	.FrameData(Tile_X13Y12_FrameData_O), 
+	.FrameData_O(Tile_X14Y12_FrameData_O), 
+	.FrameStrobe(Tile_X14Y13_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y12_FrameStrobe_O)
+	);
+
+	W_IO Tile_X0Y13_W_IO (
+	.W1END(Tile_X1Y13_W1BEG[3:0]),
+	.W2MID(Tile_X1Y13_W2BEG[7:0]),
+	.W2END(Tile_X1Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X1Y13_WW4BEG[15:0]),
+	.W6END(Tile_X1Y13_W6BEG[11:0]),
+	.E1BEG(Tile_X0Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X0Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X0Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X0Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X0Y13_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.A_I_top(Tile_X0Y13_A_I_top),
+	.A_T_top(Tile_X0Y13_A_T_top),
+	.A_O_top(Tile_X0Y13_A_O_top),
+	.UserCLK(Tile_X0Y14_UserCLKo),
+	.B_I_top(Tile_X0Y13_B_I_top),
+	.B_T_top(Tile_X0Y13_B_T_top),
+	.B_O_top(Tile_X0Y13_B_O_top),
+	.A_config_C_bit0(Tile_X0Y13_A_config_C_bit0),
+	.A_config_C_bit1(Tile_X0Y13_A_config_C_bit1),
+	.A_config_C_bit2(Tile_X0Y13_A_config_C_bit2),
+	.A_config_C_bit3(Tile_X0Y13_A_config_C_bit3),
+	.B_config_C_bit0(Tile_X0Y13_B_config_C_bit0),
+	.B_config_C_bit1(Tile_X0Y13_B_config_C_bit1),
+	.B_config_C_bit2(Tile_X0Y13_B_config_C_bit2),
+	.B_config_C_bit3(Tile_X0Y13_B_config_C_bit3),
+	.UserCLKo(Tile_X0Y13_UserCLKo),
+	.FrameData(Tile_Y13_FrameData), 
+	.FrameData_O(Tile_X0Y13_FrameData_O), 
+	.FrameStrobe(Tile_X0Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X0Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X1Y13_LUT4AB (
+	.N1END(Tile_X1Y14_N1BEG[3:0]),
+	.N2MID(Tile_X1Y14_N2BEG[7:0]),
+	.N2END(Tile_X1Y14_N2BEGb[7:0]),
+	.N4END(Tile_X1Y14_N4BEG[15:0]),
+	.NN4END(Tile_X1Y14_NN4BEG[15:0]),
+	.Ci(Tile_X1Y14_Co[0:0]),
+	.E1END(Tile_X0Y13_E1BEG[3:0]),
+	.E2MID(Tile_X0Y13_E2BEG[7:0]),
+	.E2END(Tile_X0Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X0Y13_EE4BEG[15:0]),
+	.E6END(Tile_X0Y13_E6BEG[11:0]),
+	.S1END(Tile_X1Y12_S1BEG[3:0]),
+	.S2MID(Tile_X1Y12_S2BEG[7:0]),
+	.S2END(Tile_X1Y12_S2BEGb[7:0]),
+	.S4END(Tile_X1Y12_S4BEG[15:0]),
+	.SS4END(Tile_X1Y12_SS4BEG[15:0]),
+	.W1END(Tile_X2Y13_W1BEG[3:0]),
+	.W2MID(Tile_X2Y13_W2BEG[7:0]),
+	.W2END(Tile_X2Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X2Y13_WW4BEG[15:0]),
+	.W6END(Tile_X2Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X1Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y13_NN4BEG[15:0]),
+	.Co(Tile_X1Y13_Co[0:0]),
+	.E1BEG(Tile_X1Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X1Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X1Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X1Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X1Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X1Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X1Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X1Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X1Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X1Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X1Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X1Y14_UserCLKo),
+	.UserCLKo(Tile_X1Y13_UserCLKo),
+	.FrameData(Tile_X0Y13_FrameData_O), 
+	.FrameData_O(Tile_X1Y13_FrameData_O), 
+	.FrameStrobe(Tile_X1Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y13_FrameStrobe_O)
+	);
+
+	RegFile Tile_X2Y13_RegFile (
+	.N1END(Tile_X2Y14_N1BEG[3:0]),
+	.N2MID(Tile_X2Y14_N2BEG[7:0]),
+	.N2END(Tile_X2Y14_N2BEGb[7:0]),
+	.N4END(Tile_X2Y14_N4BEG[15:0]),
+	.NN4END(Tile_X2Y14_NN4BEG[15:0]),
+	.E1END(Tile_X1Y13_E1BEG[3:0]),
+	.E2MID(Tile_X1Y13_E2BEG[7:0]),
+	.E2END(Tile_X1Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X1Y13_EE4BEG[15:0]),
+	.E6END(Tile_X1Y13_E6BEG[11:0]),
+	.S1END(Tile_X2Y12_S1BEG[3:0]),
+	.S2MID(Tile_X2Y12_S2BEG[7:0]),
+	.S2END(Tile_X2Y12_S2BEGb[7:0]),
+	.S4END(Tile_X2Y12_S4BEG[15:0]),
+	.SS4END(Tile_X2Y12_SS4BEG[15:0]),
+	.W1END(Tile_X3Y13_W1BEG[3:0]),
+	.W2MID(Tile_X3Y13_W2BEG[7:0]),
+	.W2END(Tile_X3Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X3Y13_WW4BEG[15:0]),
+	.W6END(Tile_X3Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X2Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y13_NN4BEG[15:0]),
+	.E1BEG(Tile_X2Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X2Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X2Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X2Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X2Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X2Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X2Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X2Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X2Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X2Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X2Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X2Y14_UserCLKo),
+	.UserCLKo(Tile_X2Y13_UserCLKo),
+	.FrameData(Tile_X1Y13_FrameData_O), 
+	.FrameData_O(Tile_X2Y13_FrameData_O), 
+	.FrameStrobe(Tile_X2Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X3Y13_LUT4AB (
+	.N1END(Tile_X3Y14_N1BEG[3:0]),
+	.N2MID(Tile_X3Y14_N2BEG[7:0]),
+	.N2END(Tile_X3Y14_N2BEGb[7:0]),
+	.N4END(Tile_X3Y14_N4BEG[15:0]),
+	.NN4END(Tile_X3Y14_NN4BEG[15:0]),
+	.Ci(Tile_X3Y14_Co[0:0]),
+	.E1END(Tile_X2Y13_E1BEG[3:0]),
+	.E2MID(Tile_X2Y13_E2BEG[7:0]),
+	.E2END(Tile_X2Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X2Y13_EE4BEG[15:0]),
+	.E6END(Tile_X2Y13_E6BEG[11:0]),
+	.S1END(Tile_X3Y12_S1BEG[3:0]),
+	.S2MID(Tile_X3Y12_S2BEG[7:0]),
+	.S2END(Tile_X3Y12_S2BEGb[7:0]),
+	.S4END(Tile_X3Y12_S4BEG[15:0]),
+	.SS4END(Tile_X3Y12_SS4BEG[15:0]),
+	.W1END(Tile_X4Y13_W1BEG[3:0]),
+	.W2MID(Tile_X4Y13_W2BEG[7:0]),
+	.W2END(Tile_X4Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y13_WW4BEG[15:0]),
+	.W6END(Tile_X4Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X3Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y13_NN4BEG[15:0]),
+	.Co(Tile_X3Y13_Co[0:0]),
+	.E1BEG(Tile_X3Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X3Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X3Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X3Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X3Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X3Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X3Y14_UserCLKo),
+	.UserCLKo(Tile_X3Y13_UserCLKo),
+	.FrameData(Tile_X2Y13_FrameData_O), 
+	.FrameData_O(Tile_X3Y13_FrameData_O), 
+	.FrameStrobe(Tile_X3Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y13_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y13_LUT4AB (
+	.N1END(Tile_X5Y14_N1BEG[3:0]),
+	.N2MID(Tile_X5Y14_N2BEG[7:0]),
+	.N2END(Tile_X5Y14_N2BEGb[7:0]),
+	.N4END(Tile_X5Y14_N4BEG[15:0]),
+	.NN4END(Tile_X5Y14_NN4BEG[15:0]),
+	.Ci(Tile_X5Y14_Co[0:0]),
+	.E1END(Tile_X4Y13_E1BEG[3:0]),
+	.E2MID(Tile_X4Y13_E2BEG[7:0]),
+	.E2END(Tile_X4Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y13_EE4BEG[15:0]),
+	.E6END(Tile_X4Y13_E6BEG[11:0]),
+	.S1END(Tile_X5Y12_S1BEG[3:0]),
+	.S2MID(Tile_X5Y12_S2BEG[7:0]),
+	.S2END(Tile_X5Y12_S2BEGb[7:0]),
+	.S4END(Tile_X5Y12_S4BEG[15:0]),
+	.SS4END(Tile_X5Y12_SS4BEG[15:0]),
+	.W1END(Tile_X6Y13_W1BEG[3:0]),
+	.W2MID(Tile_X6Y13_W2BEG[7:0]),
+	.W2END(Tile_X6Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y13_WW4BEG[15:0]),
+	.W6END(Tile_X6Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y13_NN4BEG[15:0]),
+	.Co(Tile_X5Y13_Co[0:0]),
+	.E1BEG(Tile_X5Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y14_UserCLKo),
+	.UserCLKo(Tile_X5Y13_UserCLKo),
+	.FrameData(Tile_X4Y13_FrameData_O), 
+	.FrameData_O(Tile_X5Y13_FrameData_O), 
+	.FrameStrobe(Tile_X5Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y13_LUT4AB (
+	.N1END(Tile_X6Y14_N1BEG[3:0]),
+	.N2MID(Tile_X6Y14_N2BEG[7:0]),
+	.N2END(Tile_X6Y14_N2BEGb[7:0]),
+	.N4END(Tile_X6Y14_N4BEG[15:0]),
+	.NN4END(Tile_X6Y14_NN4BEG[15:0]),
+	.Ci(Tile_X6Y14_Co[0:0]),
+	.E1END(Tile_X5Y13_E1BEG[3:0]),
+	.E2MID(Tile_X5Y13_E2BEG[7:0]),
+	.E2END(Tile_X5Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y13_EE4BEG[15:0]),
+	.E6END(Tile_X5Y13_E6BEG[11:0]),
+	.S1END(Tile_X6Y12_S1BEG[3:0]),
+	.S2MID(Tile_X6Y12_S2BEG[7:0]),
+	.S2END(Tile_X6Y12_S2BEGb[7:0]),
+	.S4END(Tile_X6Y12_S4BEG[15:0]),
+	.SS4END(Tile_X6Y12_SS4BEG[15:0]),
+	.W1END(Tile_X7Y13_W1BEG[3:0]),
+	.W2MID(Tile_X7Y13_W2BEG[7:0]),
+	.W2END(Tile_X7Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y13_WW4BEG[15:0]),
+	.W6END(Tile_X7Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y13_NN4BEG[15:0]),
+	.Co(Tile_X6Y13_Co[0:0]),
+	.E1BEG(Tile_X6Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y14_UserCLKo),
+	.UserCLKo(Tile_X6Y13_UserCLKo),
+	.FrameData(Tile_X5Y13_FrameData_O), 
+	.FrameData_O(Tile_X6Y13_FrameData_O), 
+	.FrameStrobe(Tile_X6Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y13_LUT4AB (
+	.N1END(Tile_X7Y14_N1BEG[3:0]),
+	.N2MID(Tile_X7Y14_N2BEG[7:0]),
+	.N2END(Tile_X7Y14_N2BEGb[7:0]),
+	.N4END(Tile_X7Y14_N4BEG[15:0]),
+	.NN4END(Tile_X7Y14_NN4BEG[15:0]),
+	.Ci(Tile_X7Y14_Co[0:0]),
+	.E1END(Tile_X6Y13_E1BEG[3:0]),
+	.E2MID(Tile_X6Y13_E2BEG[7:0]),
+	.E2END(Tile_X6Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y13_EE4BEG[15:0]),
+	.E6END(Tile_X6Y13_E6BEG[11:0]),
+	.S1END(Tile_X7Y12_S1BEG[3:0]),
+	.S2MID(Tile_X7Y12_S2BEG[7:0]),
+	.S2END(Tile_X7Y12_S2BEGb[7:0]),
+	.S4END(Tile_X7Y12_S4BEG[15:0]),
+	.SS4END(Tile_X7Y12_SS4BEG[15:0]),
+	.W1END(Tile_X8Y13_W1BEG[3:0]),
+	.W2MID(Tile_X8Y13_W2BEG[7:0]),
+	.W2END(Tile_X8Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y13_WW4BEG[15:0]),
+	.W6END(Tile_X8Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y13_NN4BEG[15:0]),
+	.Co(Tile_X7Y13_Co[0:0]),
+	.E1BEG(Tile_X7Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y14_UserCLKo),
+	.UserCLKo(Tile_X7Y13_UserCLKo),
+	.FrameData(Tile_X6Y13_FrameData_O), 
+	.FrameData_O(Tile_X7Y13_FrameData_O), 
+	.FrameStrobe(Tile_X7Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y13_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y13_LUT4AB (
+	.N1END(Tile_X9Y14_N1BEG[3:0]),
+	.N2MID(Tile_X9Y14_N2BEG[7:0]),
+	.N2END(Tile_X9Y14_N2BEGb[7:0]),
+	.N4END(Tile_X9Y14_N4BEG[15:0]),
+	.NN4END(Tile_X9Y14_NN4BEG[15:0]),
+	.Ci(Tile_X9Y14_Co[0:0]),
+	.E1END(Tile_X8Y13_E1BEG[3:0]),
+	.E2MID(Tile_X8Y13_E2BEG[7:0]),
+	.E2END(Tile_X8Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y13_EE4BEG[15:0]),
+	.E6END(Tile_X8Y13_E6BEG[11:0]),
+	.S1END(Tile_X9Y12_S1BEG[3:0]),
+	.S2MID(Tile_X9Y12_S2BEG[7:0]),
+	.S2END(Tile_X9Y12_S2BEGb[7:0]),
+	.S4END(Tile_X9Y12_S4BEG[15:0]),
+	.SS4END(Tile_X9Y12_SS4BEG[15:0]),
+	.W1END(Tile_X10Y13_W1BEG[3:0]),
+	.W2MID(Tile_X10Y13_W2BEG[7:0]),
+	.W2END(Tile_X10Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y13_WW4BEG[15:0]),
+	.W6END(Tile_X10Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y13_NN4BEG[15:0]),
+	.Co(Tile_X9Y13_Co[0:0]),
+	.E1BEG(Tile_X9Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y14_UserCLKo),
+	.UserCLKo(Tile_X9Y13_UserCLKo),
+	.FrameData(Tile_X8Y13_FrameData_O), 
+	.FrameData_O(Tile_X9Y13_FrameData_O), 
+	.FrameStrobe(Tile_X9Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y13_LUT4AB (
+	.N1END(Tile_X10Y14_N1BEG[3:0]),
+	.N2MID(Tile_X10Y14_N2BEG[7:0]),
+	.N2END(Tile_X10Y14_N2BEGb[7:0]),
+	.N4END(Tile_X10Y14_N4BEG[15:0]),
+	.NN4END(Tile_X10Y14_NN4BEG[15:0]),
+	.Ci(Tile_X10Y14_Co[0:0]),
+	.E1END(Tile_X9Y13_E1BEG[3:0]),
+	.E2MID(Tile_X9Y13_E2BEG[7:0]),
+	.E2END(Tile_X9Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y13_EE4BEG[15:0]),
+	.E6END(Tile_X9Y13_E6BEG[11:0]),
+	.S1END(Tile_X10Y12_S1BEG[3:0]),
+	.S2MID(Tile_X10Y12_S2BEG[7:0]),
+	.S2END(Tile_X10Y12_S2BEGb[7:0]),
+	.S4END(Tile_X10Y12_S4BEG[15:0]),
+	.SS4END(Tile_X10Y12_SS4BEG[15:0]),
+	.W1END(Tile_X11Y13_W1BEG[3:0]),
+	.W2MID(Tile_X11Y13_W2BEG[7:0]),
+	.W2END(Tile_X11Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y13_WW4BEG[15:0]),
+	.W6END(Tile_X11Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y13_NN4BEG[15:0]),
+	.Co(Tile_X10Y13_Co[0:0]),
+	.E1BEG(Tile_X10Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y14_UserCLKo),
+	.UserCLKo(Tile_X10Y13_UserCLKo),
+	.FrameData(Tile_X9Y13_FrameData_O), 
+	.FrameData_O(Tile_X10Y13_FrameData_O), 
+	.FrameStrobe(Tile_X10Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X11Y13_LUT4AB (
+	.N1END(Tile_X11Y14_N1BEG[3:0]),
+	.N2MID(Tile_X11Y14_N2BEG[7:0]),
+	.N2END(Tile_X11Y14_N2BEGb[7:0]),
+	.N4END(Tile_X11Y14_N4BEG[15:0]),
+	.NN4END(Tile_X11Y14_NN4BEG[15:0]),
+	.Ci(Tile_X11Y14_Co[0:0]),
+	.E1END(Tile_X10Y13_E1BEG[3:0]),
+	.E2MID(Tile_X10Y13_E2BEG[7:0]),
+	.E2END(Tile_X10Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y13_EE4BEG[15:0]),
+	.E6END(Tile_X10Y13_E6BEG[11:0]),
+	.S1END(Tile_X11Y12_S1BEG[3:0]),
+	.S2MID(Tile_X11Y12_S2BEG[7:0]),
+	.S2END(Tile_X11Y12_S2BEGb[7:0]),
+	.S4END(Tile_X11Y12_S4BEG[15:0]),
+	.SS4END(Tile_X11Y12_SS4BEG[15:0]),
+	.W1END(Tile_X12Y13_W1BEG[3:0]),
+	.W2MID(Tile_X12Y13_W2BEG[7:0]),
+	.W2END(Tile_X12Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X12Y13_WW4BEG[15:0]),
+	.W6END(Tile_X12Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X11Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y13_NN4BEG[15:0]),
+	.Co(Tile_X11Y13_Co[0:0]),
+	.E1BEG(Tile_X11Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X11Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X11Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X11Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X11Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X11Y14_UserCLKo),
+	.UserCLKo(Tile_X11Y13_UserCLKo),
+	.FrameData(Tile_X10Y13_FrameData_O), 
+	.FrameData_O(Tile_X11Y13_FrameData_O), 
+	.FrameStrobe(Tile_X11Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y13_FrameStrobe_O)
+	);
+
+	RegFile Tile_X12Y13_RegFile (
+	.N1END(Tile_X12Y14_N1BEG[3:0]),
+	.N2MID(Tile_X12Y14_N2BEG[7:0]),
+	.N2END(Tile_X12Y14_N2BEGb[7:0]),
+	.N4END(Tile_X12Y14_N4BEG[15:0]),
+	.NN4END(Tile_X12Y14_NN4BEG[15:0]),
+	.E1END(Tile_X11Y13_E1BEG[3:0]),
+	.E2MID(Tile_X11Y13_E2BEG[7:0]),
+	.E2END(Tile_X11Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X11Y13_EE4BEG[15:0]),
+	.E6END(Tile_X11Y13_E6BEG[11:0]),
+	.S1END(Tile_X12Y12_S1BEG[3:0]),
+	.S2MID(Tile_X12Y12_S2BEG[7:0]),
+	.S2END(Tile_X12Y12_S2BEGb[7:0]),
+	.S4END(Tile_X12Y12_S4BEG[15:0]),
+	.SS4END(Tile_X12Y12_SS4BEG[15:0]),
+	.W1END(Tile_X13Y13_W1BEG[3:0]),
+	.W2MID(Tile_X13Y13_W2BEG[7:0]),
+	.W2END(Tile_X13Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X13Y13_WW4BEG[15:0]),
+	.W6END(Tile_X13Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X12Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y13_NN4BEG[15:0]),
+	.E1BEG(Tile_X12Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X12Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X12Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X12Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X12Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X12Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X12Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X12Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X12Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X12Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X12Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X12Y14_UserCLKo),
+	.UserCLKo(Tile_X12Y13_UserCLKo),
+	.FrameData(Tile_X11Y13_FrameData_O), 
+	.FrameData_O(Tile_X12Y13_FrameData_O), 
+	.FrameStrobe(Tile_X12Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y13_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X13Y13_LUT4AB (
+	.N1END(Tile_X13Y14_N1BEG[3:0]),
+	.N2MID(Tile_X13Y14_N2BEG[7:0]),
+	.N2END(Tile_X13Y14_N2BEGb[7:0]),
+	.N4END(Tile_X13Y14_N4BEG[15:0]),
+	.NN4END(Tile_X13Y14_NN4BEG[15:0]),
+	.Ci(Tile_X13Y14_Co[0:0]),
+	.E1END(Tile_X12Y13_E1BEG[3:0]),
+	.E2MID(Tile_X12Y13_E2BEG[7:0]),
+	.E2END(Tile_X12Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X12Y13_EE4BEG[15:0]),
+	.E6END(Tile_X12Y13_E6BEG[11:0]),
+	.S1END(Tile_X13Y12_S1BEG[3:0]),
+	.S2MID(Tile_X13Y12_S2BEG[7:0]),
+	.S2END(Tile_X13Y12_S2BEGb[7:0]),
+	.S4END(Tile_X13Y12_S4BEG[15:0]),
+	.SS4END(Tile_X13Y12_SS4BEG[15:0]),
+	.W1END(Tile_X14Y13_W1BEG[3:0]),
+	.W2MID(Tile_X14Y13_W2BEG[7:0]),
+	.W2END(Tile_X14Y13_W2BEGb[7:0]),
+	.WW4END(Tile_X14Y13_WW4BEG[15:0]),
+	.W6END(Tile_X14Y13_W6BEG[11:0]),
+	.N1BEG(Tile_X13Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y13_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y13_NN4BEG[15:0]),
+	.Co(Tile_X13Y13_Co[0:0]),
+	.E1BEG(Tile_X13Y13_E1BEG[3:0]),
+	.E2BEG(Tile_X13Y13_E2BEG[7:0]),
+	.E2BEGb(Tile_X13Y13_E2BEGb[7:0]),
+	.EE4BEG(Tile_X13Y13_EE4BEG[15:0]),
+	.E6BEG(Tile_X13Y13_E6BEG[11:0]),
+	.S1BEG(Tile_X13Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y13_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y13_SS4BEG[15:0]),
+	.W1BEG(Tile_X13Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X13Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X13Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X13Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X13Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X13Y14_UserCLKo),
+	.UserCLKo(Tile_X13Y13_UserCLKo),
+	.FrameData(Tile_X12Y13_FrameData_O), 
+	.FrameData_O(Tile_X13Y13_FrameData_O), 
+	.FrameStrobe(Tile_X13Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y13_FrameStrobe_O)
+	);
+
+	RAM_IO Tile_X14Y13_RAM_IO (
+	.N1END(Tile_X14Y14_N1BEG[3:0]),
+	.N2MID(Tile_X14Y14_N2BEG[7:0]),
+	.N2END(Tile_X14Y14_N2BEGb[7:0]),
+	.N4END(Tile_X14Y14_N4BEG[15:0]),
+	.E1END(Tile_X13Y13_E1BEG[3:0]),
+	.E2MID(Tile_X13Y13_E2BEG[7:0]),
+	.E2END(Tile_X13Y13_E2BEGb[7:0]),
+	.EE4END(Tile_X13Y13_EE4BEG[15:0]),
+	.E6END(Tile_X13Y13_E6BEG[11:0]),
+	.S1END(Tile_X14Y12_S1BEG[3:0]),
+	.S2MID(Tile_X14Y12_S2BEG[7:0]),
+	.S2END(Tile_X14Y12_S2BEGb[7:0]),
+	.S4END(Tile_X14Y12_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y13_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y13_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y13_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y13_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y13_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y13_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y13_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y13_S4BEG[15:0]),
+	.W1BEG(Tile_X14Y13_W1BEG[3:0]),
+	.W2BEG(Tile_X14Y13_W2BEG[7:0]),
+	.W2BEGb(Tile_X14Y13_W2BEGb[7:0]),
+	.WW4BEG(Tile_X14Y13_WW4BEG[15:0]),
+	.W6BEG(Tile_X14Y13_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.RAM2FAB_D0_I0(Tile_X14Y13_RAM2FAB_D0_I0),
+	.RAM2FAB_D0_I1(Tile_X14Y13_RAM2FAB_D0_I1),
+	.RAM2FAB_D0_I2(Tile_X14Y13_RAM2FAB_D0_I2),
+	.RAM2FAB_D0_I3(Tile_X14Y13_RAM2FAB_D0_I3),
+	.UserCLK(Tile_X14Y14_UserCLKo),
+	.RAM2FAB_D1_I0(Tile_X14Y13_RAM2FAB_D1_I0),
+	.RAM2FAB_D1_I1(Tile_X14Y13_RAM2FAB_D1_I1),
+	.RAM2FAB_D1_I2(Tile_X14Y13_RAM2FAB_D1_I2),
+	.RAM2FAB_D1_I3(Tile_X14Y13_RAM2FAB_D1_I3),
+	.RAM2FAB_D2_I0(Tile_X14Y13_RAM2FAB_D2_I0),
+	.RAM2FAB_D2_I1(Tile_X14Y13_RAM2FAB_D2_I1),
+	.RAM2FAB_D2_I2(Tile_X14Y13_RAM2FAB_D2_I2),
+	.RAM2FAB_D2_I3(Tile_X14Y13_RAM2FAB_D2_I3),
+	.RAM2FAB_D3_I0(Tile_X14Y13_RAM2FAB_D3_I0),
+	.RAM2FAB_D3_I1(Tile_X14Y13_RAM2FAB_D3_I1),
+	.RAM2FAB_D3_I2(Tile_X14Y13_RAM2FAB_D3_I2),
+	.RAM2FAB_D3_I3(Tile_X14Y13_RAM2FAB_D3_I3),
+	.FAB2RAM_D0_O0(Tile_X14Y13_FAB2RAM_D0_O0),
+	.FAB2RAM_D0_O1(Tile_X14Y13_FAB2RAM_D0_O1),
+	.FAB2RAM_D0_O2(Tile_X14Y13_FAB2RAM_D0_O2),
+	.FAB2RAM_D0_O3(Tile_X14Y13_FAB2RAM_D0_O3),
+	.FAB2RAM_D1_O0(Tile_X14Y13_FAB2RAM_D1_O0),
+	.FAB2RAM_D1_O1(Tile_X14Y13_FAB2RAM_D1_O1),
+	.FAB2RAM_D1_O2(Tile_X14Y13_FAB2RAM_D1_O2),
+	.FAB2RAM_D1_O3(Tile_X14Y13_FAB2RAM_D1_O3),
+	.FAB2RAM_D2_O0(Tile_X14Y13_FAB2RAM_D2_O0),
+	.FAB2RAM_D2_O1(Tile_X14Y13_FAB2RAM_D2_O1),
+	.FAB2RAM_D2_O2(Tile_X14Y13_FAB2RAM_D2_O2),
+	.FAB2RAM_D2_O3(Tile_X14Y13_FAB2RAM_D2_O3),
+	.FAB2RAM_D3_O0(Tile_X14Y13_FAB2RAM_D3_O0),
+	.FAB2RAM_D3_O1(Tile_X14Y13_FAB2RAM_D3_O1),
+	.FAB2RAM_D3_O2(Tile_X14Y13_FAB2RAM_D3_O2),
+	.FAB2RAM_D3_O3(Tile_X14Y13_FAB2RAM_D3_O3),
+	.FAB2RAM_A0_O0(Tile_X14Y13_FAB2RAM_A0_O0),
+	.FAB2RAM_A0_O1(Tile_X14Y13_FAB2RAM_A0_O1),
+	.FAB2RAM_A0_O2(Tile_X14Y13_FAB2RAM_A0_O2),
+	.FAB2RAM_A0_O3(Tile_X14Y13_FAB2RAM_A0_O3),
+	.FAB2RAM_A1_O0(Tile_X14Y13_FAB2RAM_A1_O0),
+	.FAB2RAM_A1_O1(Tile_X14Y13_FAB2RAM_A1_O1),
+	.FAB2RAM_A1_O2(Tile_X14Y13_FAB2RAM_A1_O2),
+	.FAB2RAM_A1_O3(Tile_X14Y13_FAB2RAM_A1_O3),
+	.FAB2RAM_C_O0(Tile_X14Y13_FAB2RAM_C_O0),
+	.FAB2RAM_C_O1(Tile_X14Y13_FAB2RAM_C_O1),
+	.FAB2RAM_C_O2(Tile_X14Y13_FAB2RAM_C_O2),
+	.FAB2RAM_C_O3(Tile_X14Y13_FAB2RAM_C_O3),
+	.Config_accessC_bit0(Tile_X14Y13_Config_accessC_bit0),
+	.Config_accessC_bit1(Tile_X14Y13_Config_accessC_bit1),
+	.Config_accessC_bit2(Tile_X14Y13_Config_accessC_bit2),
+	.Config_accessC_bit3(Tile_X14Y13_Config_accessC_bit3),
+	.UserCLKo(Tile_X14Y13_UserCLKo),
+	.FrameData(Tile_X13Y13_FrameData_O), 
+	.FrameData_O(Tile_X14Y13_FrameData_O), 
+	.FrameStrobe(Tile_X14Y14_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y13_FrameStrobe_O)
+	);
+
+	W_IO Tile_X0Y14_W_IO (
+	.W1END(Tile_X1Y14_W1BEG[3:0]),
+	.W2MID(Tile_X1Y14_W2BEG[7:0]),
+	.W2END(Tile_X1Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X1Y14_WW4BEG[15:0]),
+	.W6END(Tile_X1Y14_W6BEG[11:0]),
+	.E1BEG(Tile_X0Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X0Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X0Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X0Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X0Y14_E6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.A_I_top(Tile_X0Y14_A_I_top),
+	.A_T_top(Tile_X0Y14_A_T_top),
+	.A_O_top(Tile_X0Y14_A_O_top),
+	.UserCLK(UserCLK),
+	.B_I_top(Tile_X0Y14_B_I_top),
+	.B_T_top(Tile_X0Y14_B_T_top),
+	.B_O_top(Tile_X0Y14_B_O_top),
+	.A_config_C_bit0(Tile_X0Y14_A_config_C_bit0),
+	.A_config_C_bit1(Tile_X0Y14_A_config_C_bit1),
+	.A_config_C_bit2(Tile_X0Y14_A_config_C_bit2),
+	.A_config_C_bit3(Tile_X0Y14_A_config_C_bit3),
+	.B_config_C_bit0(Tile_X0Y14_B_config_C_bit0),
+	.B_config_C_bit1(Tile_X0Y14_B_config_C_bit1),
+	.B_config_C_bit2(Tile_X0Y14_B_config_C_bit2),
+	.B_config_C_bit3(Tile_X0Y14_B_config_C_bit3),
+	.UserCLKo(Tile_X0Y14_UserCLKo),
+	.FrameData(Tile_Y14_FrameData), 
+	.FrameData_O(Tile_X0Y14_FrameData_O), 
+	.FrameStrobe(Tile_X0_FrameStrobe),
+	.FrameStrobe_O(Tile_X0Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X1Y14_LUT4AB (
+	.N1END(Tile_X1Y15_N1BEG[3:0]),
+	.N2MID(Tile_X1Y15_N2BEG[7:0]),
+	.N2END(Tile_X1Y15_N2BEGb[7:0]),
+	.N4END(Tile_X1Y15_N4BEG[15:0]),
+	.NN4END(Tile_X1Y15_NN4BEG[15:0]),
+	.Ci(Tile_X1Y15_Co[0:0]),
+	.E1END(Tile_X0Y14_E1BEG[3:0]),
+	.E2MID(Tile_X0Y14_E2BEG[7:0]),
+	.E2END(Tile_X0Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X0Y14_EE4BEG[15:0]),
+	.E6END(Tile_X0Y14_E6BEG[11:0]),
+	.S1END(Tile_X1Y13_S1BEG[3:0]),
+	.S2MID(Tile_X1Y13_S2BEG[7:0]),
+	.S2END(Tile_X1Y13_S2BEGb[7:0]),
+	.S4END(Tile_X1Y13_S4BEG[15:0]),
+	.SS4END(Tile_X1Y13_SS4BEG[15:0]),
+	.W1END(Tile_X2Y14_W1BEG[3:0]),
+	.W2MID(Tile_X2Y14_W2BEG[7:0]),
+	.W2END(Tile_X2Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X2Y14_WW4BEG[15:0]),
+	.W6END(Tile_X2Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X1Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y14_NN4BEG[15:0]),
+	.Co(Tile_X1Y14_Co[0:0]),
+	.E1BEG(Tile_X1Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X1Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X1Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X1Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X1Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X1Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X1Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X1Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X1Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X1Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X1Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X1Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X1Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X1Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X1Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X1Y15_UserCLKo),
+	.UserCLKo(Tile_X1Y14_UserCLKo),
+	.FrameData(Tile_X0Y14_FrameData_O), 
+	.FrameData_O(Tile_X1Y14_FrameData_O), 
+	.FrameStrobe(Tile_X1Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X1Y14_FrameStrobe_O)
+	);
+
+	RegFile Tile_X2Y14_RegFile (
+	.N1END(Tile_X2Y15_N1BEG[3:0]),
+	.N2MID(Tile_X2Y15_N2BEG[7:0]),
+	.N2END(Tile_X2Y15_N2BEGb[7:0]),
+	.N4END(Tile_X2Y15_N4BEG[15:0]),
+	.NN4END(Tile_X2Y15_NN4BEG[15:0]),
+	.E1END(Tile_X1Y14_E1BEG[3:0]),
+	.E2MID(Tile_X1Y14_E2BEG[7:0]),
+	.E2END(Tile_X1Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X1Y14_EE4BEG[15:0]),
+	.E6END(Tile_X1Y14_E6BEG[11:0]),
+	.S1END(Tile_X2Y13_S1BEG[3:0]),
+	.S2MID(Tile_X2Y13_S2BEG[7:0]),
+	.S2END(Tile_X2Y13_S2BEGb[7:0]),
+	.S4END(Tile_X2Y13_S4BEG[15:0]),
+	.SS4END(Tile_X2Y13_SS4BEG[15:0]),
+	.W1END(Tile_X3Y14_W1BEG[3:0]),
+	.W2MID(Tile_X3Y14_W2BEG[7:0]),
+	.W2END(Tile_X3Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X3Y14_WW4BEG[15:0]),
+	.W6END(Tile_X3Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X2Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y14_NN4BEG[15:0]),
+	.E1BEG(Tile_X2Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X2Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X2Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X2Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X2Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X2Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X2Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X2Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X2Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X2Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X2Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X2Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X2Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X2Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X2Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X2Y15_UserCLKo),
+	.UserCLKo(Tile_X2Y14_UserCLKo),
+	.FrameData(Tile_X1Y14_FrameData_O), 
+	.FrameData_O(Tile_X2Y14_FrameData_O), 
+	.FrameStrobe(Tile_X2Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X2Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X3Y14_LUT4AB (
+	.N1END(Tile_X3Y15_N1BEG[3:0]),
+	.N2MID(Tile_X3Y15_N2BEG[7:0]),
+	.N2END(Tile_X3Y15_N2BEGb[7:0]),
+	.N4END(Tile_X3Y15_N4BEG[15:0]),
+	.NN4END(Tile_X3Y15_NN4BEG[15:0]),
+	.Ci(Tile_X3Y15_Co[0:0]),
+	.E1END(Tile_X2Y14_E1BEG[3:0]),
+	.E2MID(Tile_X2Y14_E2BEG[7:0]),
+	.E2END(Tile_X2Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X2Y14_EE4BEG[15:0]),
+	.E6END(Tile_X2Y14_E6BEG[11:0]),
+	.S1END(Tile_X3Y13_S1BEG[3:0]),
+	.S2MID(Tile_X3Y13_S2BEG[7:0]),
+	.S2END(Tile_X3Y13_S2BEGb[7:0]),
+	.S4END(Tile_X3Y13_S4BEG[15:0]),
+	.SS4END(Tile_X3Y13_SS4BEG[15:0]),
+	.W1END(Tile_X4Y14_W1BEG[3:0]),
+	.W2MID(Tile_X4Y14_W2BEG[7:0]),
+	.W2END(Tile_X4Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X4Y14_WW4BEG[15:0]),
+	.W6END(Tile_X4Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X3Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y14_NN4BEG[15:0]),
+	.Co(Tile_X3Y14_Co[0:0]),
+	.E1BEG(Tile_X3Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X3Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X3Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X3Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X3Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X3Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X3Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X3Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X3Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X3Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X3Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X3Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X3Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X3Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X3Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X3Y15_UserCLKo),
+	.UserCLKo(Tile_X3Y14_UserCLKo),
+	.FrameData(Tile_X2Y14_FrameData_O), 
+	.FrameData_O(Tile_X3Y14_FrameData_O), 
+	.FrameStrobe(Tile_X3Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X3Y14_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X5Y14_LUT4AB (
+	.N1END(Tile_X5Y15_N1BEG[3:0]),
+	.N2MID(Tile_X5Y15_N2BEG[7:0]),
+	.N2END(Tile_X5Y15_N2BEGb[7:0]),
+	.N4END(Tile_X5Y15_N4BEG[15:0]),
+	.NN4END(Tile_X5Y15_NN4BEG[15:0]),
+	.Ci(Tile_X5Y15_Co[0:0]),
+	.E1END(Tile_X4Y14_E1BEG[3:0]),
+	.E2MID(Tile_X4Y14_E2BEG[7:0]),
+	.E2END(Tile_X4Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X4Y14_EE4BEG[15:0]),
+	.E6END(Tile_X4Y14_E6BEG[11:0]),
+	.S1END(Tile_X5Y13_S1BEG[3:0]),
+	.S2MID(Tile_X5Y13_S2BEG[7:0]),
+	.S2END(Tile_X5Y13_S2BEGb[7:0]),
+	.S4END(Tile_X5Y13_S4BEG[15:0]),
+	.SS4END(Tile_X5Y13_SS4BEG[15:0]),
+	.W1END(Tile_X6Y14_W1BEG[3:0]),
+	.W2MID(Tile_X6Y14_W2BEG[7:0]),
+	.W2END(Tile_X6Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X6Y14_WW4BEG[15:0]),
+	.W6END(Tile_X6Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X5Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y14_NN4BEG[15:0]),
+	.Co(Tile_X5Y14_Co[0:0]),
+	.E1BEG(Tile_X5Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X5Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X5Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X5Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X5Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X5Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X5Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X5Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X5Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X5Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X5Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X5Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X5Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X5Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X5Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X5Y15_UserCLKo),
+	.UserCLKo(Tile_X5Y14_UserCLKo),
+	.FrameData(Tile_X4Y14_FrameData_O), 
+	.FrameData_O(Tile_X5Y14_FrameData_O), 
+	.FrameStrobe(Tile_X5Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X5Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X6Y14_LUT4AB (
+	.N1END(Tile_X6Y15_N1BEG[3:0]),
+	.N2MID(Tile_X6Y15_N2BEG[7:0]),
+	.N2END(Tile_X6Y15_N2BEGb[7:0]),
+	.N4END(Tile_X6Y15_N4BEG[15:0]),
+	.NN4END(Tile_X6Y15_NN4BEG[15:0]),
+	.Ci(Tile_X6Y15_Co[0:0]),
+	.E1END(Tile_X5Y14_E1BEG[3:0]),
+	.E2MID(Tile_X5Y14_E2BEG[7:0]),
+	.E2END(Tile_X5Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X5Y14_EE4BEG[15:0]),
+	.E6END(Tile_X5Y14_E6BEG[11:0]),
+	.S1END(Tile_X6Y13_S1BEG[3:0]),
+	.S2MID(Tile_X6Y13_S2BEG[7:0]),
+	.S2END(Tile_X6Y13_S2BEGb[7:0]),
+	.S4END(Tile_X6Y13_S4BEG[15:0]),
+	.SS4END(Tile_X6Y13_SS4BEG[15:0]),
+	.W1END(Tile_X7Y14_W1BEG[3:0]),
+	.W2MID(Tile_X7Y14_W2BEG[7:0]),
+	.W2END(Tile_X7Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X7Y14_WW4BEG[15:0]),
+	.W6END(Tile_X7Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X6Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y14_NN4BEG[15:0]),
+	.Co(Tile_X6Y14_Co[0:0]),
+	.E1BEG(Tile_X6Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X6Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X6Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X6Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X6Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X6Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X6Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X6Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X6Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X6Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X6Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X6Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X6Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X6Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X6Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X6Y15_UserCLKo),
+	.UserCLKo(Tile_X6Y14_UserCLKo),
+	.FrameData(Tile_X5Y14_FrameData_O), 
+	.FrameData_O(Tile_X6Y14_FrameData_O), 
+	.FrameStrobe(Tile_X6Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X6Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X7Y14_LUT4AB (
+	.N1END(Tile_X7Y15_N1BEG[3:0]),
+	.N2MID(Tile_X7Y15_N2BEG[7:0]),
+	.N2END(Tile_X7Y15_N2BEGb[7:0]),
+	.N4END(Tile_X7Y15_N4BEG[15:0]),
+	.NN4END(Tile_X7Y15_NN4BEG[15:0]),
+	.Ci(Tile_X7Y15_Co[0:0]),
+	.E1END(Tile_X6Y14_E1BEG[3:0]),
+	.E2MID(Tile_X6Y14_E2BEG[7:0]),
+	.E2END(Tile_X6Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X6Y14_EE4BEG[15:0]),
+	.E6END(Tile_X6Y14_E6BEG[11:0]),
+	.S1END(Tile_X7Y13_S1BEG[3:0]),
+	.S2MID(Tile_X7Y13_S2BEG[7:0]),
+	.S2END(Tile_X7Y13_S2BEGb[7:0]),
+	.S4END(Tile_X7Y13_S4BEG[15:0]),
+	.SS4END(Tile_X7Y13_SS4BEG[15:0]),
+	.W1END(Tile_X8Y14_W1BEG[3:0]),
+	.W2MID(Tile_X8Y14_W2BEG[7:0]),
+	.W2END(Tile_X8Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X8Y14_WW4BEG[15:0]),
+	.W6END(Tile_X8Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X7Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y14_NN4BEG[15:0]),
+	.Co(Tile_X7Y14_Co[0:0]),
+	.E1BEG(Tile_X7Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X7Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X7Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X7Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X7Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X7Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X7Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X7Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X7Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X7Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X7Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X7Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X7Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X7Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X7Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X7Y15_UserCLKo),
+	.UserCLKo(Tile_X7Y14_UserCLKo),
+	.FrameData(Tile_X6Y14_FrameData_O), 
+	.FrameData_O(Tile_X7Y14_FrameData_O), 
+	.FrameStrobe(Tile_X7Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X7Y14_FrameStrobe_O)
+	);
+
+
+	LUT4AB Tile_X9Y14_LUT4AB (
+	.N1END(Tile_X9Y15_N1BEG[3:0]),
+	.N2MID(Tile_X9Y15_N2BEG[7:0]),
+	.N2END(Tile_X9Y15_N2BEGb[7:0]),
+	.N4END(Tile_X9Y15_N4BEG[15:0]),
+	.NN4END(Tile_X9Y15_NN4BEG[15:0]),
+	.Ci(Tile_X9Y15_Co[0:0]),
+	.E1END(Tile_X8Y14_E1BEG[3:0]),
+	.E2MID(Tile_X8Y14_E2BEG[7:0]),
+	.E2END(Tile_X8Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X8Y14_EE4BEG[15:0]),
+	.E6END(Tile_X8Y14_E6BEG[11:0]),
+	.S1END(Tile_X9Y13_S1BEG[3:0]),
+	.S2MID(Tile_X9Y13_S2BEG[7:0]),
+	.S2END(Tile_X9Y13_S2BEGb[7:0]),
+	.S4END(Tile_X9Y13_S4BEG[15:0]),
+	.SS4END(Tile_X9Y13_SS4BEG[15:0]),
+	.W1END(Tile_X10Y14_W1BEG[3:0]),
+	.W2MID(Tile_X10Y14_W2BEG[7:0]),
+	.W2END(Tile_X10Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X10Y14_WW4BEG[15:0]),
+	.W6END(Tile_X10Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X9Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y14_NN4BEG[15:0]),
+	.Co(Tile_X9Y14_Co[0:0]),
+	.E1BEG(Tile_X9Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X9Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X9Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X9Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X9Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X9Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X9Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X9Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X9Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X9Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X9Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X9Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X9Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X9Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X9Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X9Y15_UserCLKo),
+	.UserCLKo(Tile_X9Y14_UserCLKo),
+	.FrameData(Tile_X8Y14_FrameData_O), 
+	.FrameData_O(Tile_X9Y14_FrameData_O), 
+	.FrameStrobe(Tile_X9Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X9Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X10Y14_LUT4AB (
+	.N1END(Tile_X10Y15_N1BEG[3:0]),
+	.N2MID(Tile_X10Y15_N2BEG[7:0]),
+	.N2END(Tile_X10Y15_N2BEGb[7:0]),
+	.N4END(Tile_X10Y15_N4BEG[15:0]),
+	.NN4END(Tile_X10Y15_NN4BEG[15:0]),
+	.Ci(Tile_X10Y15_Co[0:0]),
+	.E1END(Tile_X9Y14_E1BEG[3:0]),
+	.E2MID(Tile_X9Y14_E2BEG[7:0]),
+	.E2END(Tile_X9Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X9Y14_EE4BEG[15:0]),
+	.E6END(Tile_X9Y14_E6BEG[11:0]),
+	.S1END(Tile_X10Y13_S1BEG[3:0]),
+	.S2MID(Tile_X10Y13_S2BEG[7:0]),
+	.S2END(Tile_X10Y13_S2BEGb[7:0]),
+	.S4END(Tile_X10Y13_S4BEG[15:0]),
+	.SS4END(Tile_X10Y13_SS4BEG[15:0]),
+	.W1END(Tile_X11Y14_W1BEG[3:0]),
+	.W2MID(Tile_X11Y14_W2BEG[7:0]),
+	.W2END(Tile_X11Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X11Y14_WW4BEG[15:0]),
+	.W6END(Tile_X11Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X10Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y14_NN4BEG[15:0]),
+	.Co(Tile_X10Y14_Co[0:0]),
+	.E1BEG(Tile_X10Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X10Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X10Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X10Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X10Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X10Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X10Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X10Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X10Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X10Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X10Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X10Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X10Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X10Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X10Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X10Y15_UserCLKo),
+	.UserCLKo(Tile_X10Y14_UserCLKo),
+	.FrameData(Tile_X9Y14_FrameData_O), 
+	.FrameData_O(Tile_X10Y14_FrameData_O), 
+	.FrameStrobe(Tile_X10Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X10Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X11Y14_LUT4AB (
+	.N1END(Tile_X11Y15_N1BEG[3:0]),
+	.N2MID(Tile_X11Y15_N2BEG[7:0]),
+	.N2END(Tile_X11Y15_N2BEGb[7:0]),
+	.N4END(Tile_X11Y15_N4BEG[15:0]),
+	.NN4END(Tile_X11Y15_NN4BEG[15:0]),
+	.Ci(Tile_X11Y15_Co[0:0]),
+	.E1END(Tile_X10Y14_E1BEG[3:0]),
+	.E2MID(Tile_X10Y14_E2BEG[7:0]),
+	.E2END(Tile_X10Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X10Y14_EE4BEG[15:0]),
+	.E6END(Tile_X10Y14_E6BEG[11:0]),
+	.S1END(Tile_X11Y13_S1BEG[3:0]),
+	.S2MID(Tile_X11Y13_S2BEG[7:0]),
+	.S2END(Tile_X11Y13_S2BEGb[7:0]),
+	.S4END(Tile_X11Y13_S4BEG[15:0]),
+	.SS4END(Tile_X11Y13_SS4BEG[15:0]),
+	.W1END(Tile_X12Y14_W1BEG[3:0]),
+	.W2MID(Tile_X12Y14_W2BEG[7:0]),
+	.W2END(Tile_X12Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X12Y14_WW4BEG[15:0]),
+	.W6END(Tile_X12Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X11Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y14_NN4BEG[15:0]),
+	.Co(Tile_X11Y14_Co[0:0]),
+	.E1BEG(Tile_X11Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X11Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X11Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X11Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X11Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X11Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X11Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X11Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X11Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X11Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X11Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X11Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X11Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X11Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X11Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X11Y15_UserCLKo),
+	.UserCLKo(Tile_X11Y14_UserCLKo),
+	.FrameData(Tile_X10Y14_FrameData_O), 
+	.FrameData_O(Tile_X11Y14_FrameData_O), 
+	.FrameStrobe(Tile_X11Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X11Y14_FrameStrobe_O)
+	);
+
+	RegFile Tile_X12Y14_RegFile (
+	.N1END(Tile_X12Y15_N1BEG[3:0]),
+	.N2MID(Tile_X12Y15_N2BEG[7:0]),
+	.N2END(Tile_X12Y15_N2BEGb[7:0]),
+	.N4END(Tile_X12Y15_N4BEG[15:0]),
+	.NN4END(Tile_X12Y15_NN4BEG[15:0]),
+	.E1END(Tile_X11Y14_E1BEG[3:0]),
+	.E2MID(Tile_X11Y14_E2BEG[7:0]),
+	.E2END(Tile_X11Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X11Y14_EE4BEG[15:0]),
+	.E6END(Tile_X11Y14_E6BEG[11:0]),
+	.S1END(Tile_X12Y13_S1BEG[3:0]),
+	.S2MID(Tile_X12Y13_S2BEG[7:0]),
+	.S2END(Tile_X12Y13_S2BEGb[7:0]),
+	.S4END(Tile_X12Y13_S4BEG[15:0]),
+	.SS4END(Tile_X12Y13_SS4BEG[15:0]),
+	.W1END(Tile_X13Y14_W1BEG[3:0]),
+	.W2MID(Tile_X13Y14_W2BEG[7:0]),
+	.W2END(Tile_X13Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X13Y14_WW4BEG[15:0]),
+	.W6END(Tile_X13Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X12Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y14_NN4BEG[15:0]),
+	.E1BEG(Tile_X12Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X12Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X12Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X12Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X12Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X12Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X12Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X12Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X12Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X12Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X12Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X12Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X12Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X12Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X12Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X12Y15_UserCLKo),
+	.UserCLKo(Tile_X12Y14_UserCLKo),
+	.FrameData(Tile_X11Y14_FrameData_O), 
+	.FrameData_O(Tile_X12Y14_FrameData_O), 
+	.FrameStrobe(Tile_X12Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X12Y14_FrameStrobe_O)
+	);
+
+	LUT4AB Tile_X13Y14_LUT4AB (
+	.N1END(Tile_X13Y15_N1BEG[3:0]),
+	.N2MID(Tile_X13Y15_N2BEG[7:0]),
+	.N2END(Tile_X13Y15_N2BEGb[7:0]),
+	.N4END(Tile_X13Y15_N4BEG[15:0]),
+	.NN4END(Tile_X13Y15_NN4BEG[15:0]),
+	.Ci(Tile_X13Y15_Co[0:0]),
+	.E1END(Tile_X12Y14_E1BEG[3:0]),
+	.E2MID(Tile_X12Y14_E2BEG[7:0]),
+	.E2END(Tile_X12Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X12Y14_EE4BEG[15:0]),
+	.E6END(Tile_X12Y14_E6BEG[11:0]),
+	.S1END(Tile_X13Y13_S1BEG[3:0]),
+	.S2MID(Tile_X13Y13_S2BEG[7:0]),
+	.S2END(Tile_X13Y13_S2BEGb[7:0]),
+	.S4END(Tile_X13Y13_S4BEG[15:0]),
+	.SS4END(Tile_X13Y13_SS4BEG[15:0]),
+	.W1END(Tile_X14Y14_W1BEG[3:0]),
+	.W2MID(Tile_X14Y14_W2BEG[7:0]),
+	.W2END(Tile_X14Y14_W2BEGb[7:0]),
+	.WW4END(Tile_X14Y14_WW4BEG[15:0]),
+	.W6END(Tile_X14Y14_W6BEG[11:0]),
+	.N1BEG(Tile_X13Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y14_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y14_NN4BEG[15:0]),
+	.Co(Tile_X13Y14_Co[0:0]),
+	.E1BEG(Tile_X13Y14_E1BEG[3:0]),
+	.E2BEG(Tile_X13Y14_E2BEG[7:0]),
+	.E2BEGb(Tile_X13Y14_E2BEGb[7:0]),
+	.EE4BEG(Tile_X13Y14_EE4BEG[15:0]),
+	.E6BEG(Tile_X13Y14_E6BEG[11:0]),
+	.S1BEG(Tile_X13Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X13Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X13Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X13Y14_S4BEG[15:0]),
+	.SS4BEG(Tile_X13Y14_SS4BEG[15:0]),
+	.W1BEG(Tile_X13Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X13Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X13Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X13Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X13Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.UserCLK(Tile_X13Y15_UserCLKo),
+	.UserCLKo(Tile_X13Y14_UserCLKo),
+	.FrameData(Tile_X12Y14_FrameData_O), 
+	.FrameData_O(Tile_X13Y14_FrameData_O), 
+	.FrameStrobe(Tile_X13Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X13Y14_FrameStrobe_O)
+	);
+
+	RAM_IO Tile_X14Y14_RAM_IO (
+	.N1END(Tile_X14Y15_N1BEG[3:0]),
+	.N2MID(Tile_X14Y15_N2BEG[7:0]),
+	.N2END(Tile_X14Y15_N2BEGb[7:0]),
+	.N4END(Tile_X14Y15_N4BEG[15:0]),
+	.E1END(Tile_X13Y14_E1BEG[3:0]),
+	.E2MID(Tile_X13Y14_E2BEG[7:0]),
+	.E2END(Tile_X13Y14_E2BEGb[7:0]),
+	.EE4END(Tile_X13Y14_EE4BEG[15:0]),
+	.E6END(Tile_X13Y14_E6BEG[11:0]),
+	.S1END(Tile_X14Y13_S1BEG[3:0]),
+	.S2MID(Tile_X14Y13_S2BEG[7:0]),
+	.S2END(Tile_X14Y13_S2BEGb[7:0]),
+	.S4END(Tile_X14Y13_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y14_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y14_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y14_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y14_N4BEG[15:0]),
+	.S1BEG(Tile_X14Y14_S1BEG[3:0]),
+	.S2BEG(Tile_X14Y14_S2BEG[7:0]),
+	.S2BEGb(Tile_X14Y14_S2BEGb[7:0]),
+	.S4BEG(Tile_X14Y14_S4BEG[15:0]),
+	.W1BEG(Tile_X14Y14_W1BEG[3:0]),
+	.W2BEG(Tile_X14Y14_W2BEG[7:0]),
+	.W2BEGb(Tile_X14Y14_W2BEGb[7:0]),
+	.WW4BEG(Tile_X14Y14_WW4BEG[15:0]),
+	.W6BEG(Tile_X14Y14_W6BEG[11:0]),
+	//tile IO port which gets directly connected to top-level tile module
+	.RAM2FAB_D0_I0(Tile_X14Y14_RAM2FAB_D0_I0),
+	.RAM2FAB_D0_I1(Tile_X14Y14_RAM2FAB_D0_I1),
+	.RAM2FAB_D0_I2(Tile_X14Y14_RAM2FAB_D0_I2),
+	.RAM2FAB_D0_I3(Tile_X14Y14_RAM2FAB_D0_I3),
+	.UserCLK(Tile_X14Y15_UserCLKo),
+	.RAM2FAB_D1_I0(Tile_X14Y14_RAM2FAB_D1_I0),
+	.RAM2FAB_D1_I1(Tile_X14Y14_RAM2FAB_D1_I1),
+	.RAM2FAB_D1_I2(Tile_X14Y14_RAM2FAB_D1_I2),
+	.RAM2FAB_D1_I3(Tile_X14Y14_RAM2FAB_D1_I3),
+	.RAM2FAB_D2_I0(Tile_X14Y14_RAM2FAB_D2_I0),
+	.RAM2FAB_D2_I1(Tile_X14Y14_RAM2FAB_D2_I1),
+	.RAM2FAB_D2_I2(Tile_X14Y14_RAM2FAB_D2_I2),
+	.RAM2FAB_D2_I3(Tile_X14Y14_RAM2FAB_D2_I3),
+	.RAM2FAB_D3_I0(Tile_X14Y14_RAM2FAB_D3_I0),
+	.RAM2FAB_D3_I1(Tile_X14Y14_RAM2FAB_D3_I1),
+	.RAM2FAB_D3_I2(Tile_X14Y14_RAM2FAB_D3_I2),
+	.RAM2FAB_D3_I3(Tile_X14Y14_RAM2FAB_D3_I3),
+	.FAB2RAM_D0_O0(Tile_X14Y14_FAB2RAM_D0_O0),
+	.FAB2RAM_D0_O1(Tile_X14Y14_FAB2RAM_D0_O1),
+	.FAB2RAM_D0_O2(Tile_X14Y14_FAB2RAM_D0_O2),
+	.FAB2RAM_D0_O3(Tile_X14Y14_FAB2RAM_D0_O3),
+	.FAB2RAM_D1_O0(Tile_X14Y14_FAB2RAM_D1_O0),
+	.FAB2RAM_D1_O1(Tile_X14Y14_FAB2RAM_D1_O1),
+	.FAB2RAM_D1_O2(Tile_X14Y14_FAB2RAM_D1_O2),
+	.FAB2RAM_D1_O3(Tile_X14Y14_FAB2RAM_D1_O3),
+	.FAB2RAM_D2_O0(Tile_X14Y14_FAB2RAM_D2_O0),
+	.FAB2RAM_D2_O1(Tile_X14Y14_FAB2RAM_D2_O1),
+	.FAB2RAM_D2_O2(Tile_X14Y14_FAB2RAM_D2_O2),
+	.FAB2RAM_D2_O3(Tile_X14Y14_FAB2RAM_D2_O3),
+	.FAB2RAM_D3_O0(Tile_X14Y14_FAB2RAM_D3_O0),
+	.FAB2RAM_D3_O1(Tile_X14Y14_FAB2RAM_D3_O1),
+	.FAB2RAM_D3_O2(Tile_X14Y14_FAB2RAM_D3_O2),
+	.FAB2RAM_D3_O3(Tile_X14Y14_FAB2RAM_D3_O3),
+	.FAB2RAM_A0_O0(Tile_X14Y14_FAB2RAM_A0_O0),
+	.FAB2RAM_A0_O1(Tile_X14Y14_FAB2RAM_A0_O1),
+	.FAB2RAM_A0_O2(Tile_X14Y14_FAB2RAM_A0_O2),
+	.FAB2RAM_A0_O3(Tile_X14Y14_FAB2RAM_A0_O3),
+	.FAB2RAM_A1_O0(Tile_X14Y14_FAB2RAM_A1_O0),
+	.FAB2RAM_A1_O1(Tile_X14Y14_FAB2RAM_A1_O1),
+	.FAB2RAM_A1_O2(Tile_X14Y14_FAB2RAM_A1_O2),
+	.FAB2RAM_A1_O3(Tile_X14Y14_FAB2RAM_A1_O3),
+	.FAB2RAM_C_O0(Tile_X14Y14_FAB2RAM_C_O0),
+	.FAB2RAM_C_O1(Tile_X14Y14_FAB2RAM_C_O1),
+	.FAB2RAM_C_O2(Tile_X14Y14_FAB2RAM_C_O2),
+	.FAB2RAM_C_O3(Tile_X14Y14_FAB2RAM_C_O3),
+	.Config_accessC_bit0(Tile_X14Y14_Config_accessC_bit0),
+	.Config_accessC_bit1(Tile_X14Y14_Config_accessC_bit1),
+	.Config_accessC_bit2(Tile_X14Y14_Config_accessC_bit2),
+	.Config_accessC_bit3(Tile_X14Y14_Config_accessC_bit3),
+	.UserCLKo(Tile_X14Y14_UserCLKo),
+	.FrameData(Tile_X13Y14_FrameData_O), 
+	.FrameData_O(Tile_X14Y14_FrameData_O), 
+	.FrameStrobe(Tile_X14Y15_FrameStrobe_O),
+	.FrameStrobe_O(Tile_X14Y14_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X1Y15_S_term_single (
+	.S1END(Tile_X1Y14_S1BEG[3:0]),
+	.S2MID(Tile_X1Y14_S2BEG[7:0]),
+	.S2END(Tile_X1Y14_S2BEGb[7:0]),
+	.S4END(Tile_X1Y14_S4BEG[15:0]),
+	.SS4END(Tile_X1Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X1Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X1Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X1Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X1Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X1Y15_NN4BEG[15:0]),
+	.Co(Tile_X1Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X1Y15_UserCLKo),
+	.FrameStrobe(Tile_X1_FrameStrobe),
+	.FrameStrobe_O(Tile_X1Y15_FrameStrobe_O)
+	);
+
+	S_term_single2 Tile_X2Y15_S_term_single2 (
+	.S1END(Tile_X2Y14_S1BEG[3:0]),
+	.S2MID(Tile_X2Y14_S2BEG[7:0]),
+	.S2END(Tile_X2Y14_S2BEGb[7:0]),
+	.S4END(Tile_X2Y14_S4BEG[15:0]),
+	.SS4END(Tile_X2Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X2Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X2Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X2Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X2Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X2Y15_NN4BEG[15:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X2Y15_UserCLKo),
+	.FrameStrobe(Tile_X2_FrameStrobe),
+	.FrameStrobe_O(Tile_X2Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X3Y15_S_term_single (
+	.S1END(Tile_X3Y14_S1BEG[3:0]),
+	.S2MID(Tile_X3Y14_S2BEG[7:0]),
+	.S2END(Tile_X3Y14_S2BEGb[7:0]),
+	.S4END(Tile_X3Y14_S4BEG[15:0]),
+	.SS4END(Tile_X3Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X3Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X3Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X3Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X3Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X3Y15_NN4BEG[15:0]),
+	.Co(Tile_X3Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X3Y15_UserCLKo),
+	.FrameStrobe(Tile_X3_FrameStrobe),
+	.FrameStrobe_O(Tile_X3Y15_FrameStrobe_O)
+	);
+
+	S_term_DSP Tile_X4Y15_S_term_DSP (
+	.S1END(Tile_X4Y14_S1BEG[3:0]),
+	.S2MID(Tile_X4Y14_S2BEG[7:0]),
+	.S2END(Tile_X4Y14_S2BEGb[7:0]),
+	.S4END(Tile_X4Y14_S4BEG[15:0]),
+	.SS4END(Tile_X4Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X4Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X4Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X4Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X4Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X4Y15_NN4BEG[15:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X4Y15_UserCLKo),
+	.FrameStrobe(Tile_X4_FrameStrobe),
+	.FrameStrobe_O(Tile_X4Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X5Y15_S_term_single (
+	.S1END(Tile_X5Y14_S1BEG[3:0]),
+	.S2MID(Tile_X5Y14_S2BEG[7:0]),
+	.S2END(Tile_X5Y14_S2BEGb[7:0]),
+	.S4END(Tile_X5Y14_S4BEG[15:0]),
+	.SS4END(Tile_X5Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X5Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X5Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X5Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X5Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X5Y15_NN4BEG[15:0]),
+	.Co(Tile_X5Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X5Y15_UserCLKo),
+	.FrameStrobe(Tile_X5_FrameStrobe),
+	.FrameStrobe_O(Tile_X5Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X6Y15_S_term_single (
+	.S1END(Tile_X6Y14_S1BEG[3:0]),
+	.S2MID(Tile_X6Y14_S2BEG[7:0]),
+	.S2END(Tile_X6Y14_S2BEGb[7:0]),
+	.S4END(Tile_X6Y14_S4BEG[15:0]),
+	.SS4END(Tile_X6Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X6Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X6Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X6Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X6Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X6Y15_NN4BEG[15:0]),
+	.Co(Tile_X6Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X6Y15_UserCLKo),
+	.FrameStrobe(Tile_X6_FrameStrobe),
+	.FrameStrobe_O(Tile_X6Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X7Y15_S_term_single (
+	.S1END(Tile_X7Y14_S1BEG[3:0]),
+	.S2MID(Tile_X7Y14_S2BEG[7:0]),
+	.S2END(Tile_X7Y14_S2BEGb[7:0]),
+	.S4END(Tile_X7Y14_S4BEG[15:0]),
+	.SS4END(Tile_X7Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X7Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X7Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X7Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X7Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X7Y15_NN4BEG[15:0]),
+	.Co(Tile_X7Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X7Y15_UserCLKo),
+	.FrameStrobe(Tile_X7_FrameStrobe),
+	.FrameStrobe_O(Tile_X7Y15_FrameStrobe_O)
+	);
+
+	S_term_DSP Tile_X8Y15_S_term_DSP (
+	.S1END(Tile_X8Y14_S1BEG[3:0]),
+	.S2MID(Tile_X8Y14_S2BEG[7:0]),
+	.S2END(Tile_X8Y14_S2BEGb[7:0]),
+	.S4END(Tile_X8Y14_S4BEG[15:0]),
+	.SS4END(Tile_X8Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X8Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X8Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X8Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X8Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X8Y15_NN4BEG[15:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X8Y15_UserCLKo),
+	.FrameStrobe(Tile_X8_FrameStrobe),
+	.FrameStrobe_O(Tile_X8Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X9Y15_S_term_single (
+	.S1END(Tile_X9Y14_S1BEG[3:0]),
+	.S2MID(Tile_X9Y14_S2BEG[7:0]),
+	.S2END(Tile_X9Y14_S2BEGb[7:0]),
+	.S4END(Tile_X9Y14_S4BEG[15:0]),
+	.SS4END(Tile_X9Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X9Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X9Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X9Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X9Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X9Y15_NN4BEG[15:0]),
+	.Co(Tile_X9Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X9Y15_UserCLKo),
+	.FrameStrobe(Tile_X9_FrameStrobe),
+	.FrameStrobe_O(Tile_X9Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X10Y15_S_term_single (
+	.S1END(Tile_X10Y14_S1BEG[3:0]),
+	.S2MID(Tile_X10Y14_S2BEG[7:0]),
+	.S2END(Tile_X10Y14_S2BEGb[7:0]),
+	.S4END(Tile_X10Y14_S4BEG[15:0]),
+	.SS4END(Tile_X10Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X10Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X10Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X10Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X10Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X10Y15_NN4BEG[15:0]),
+	.Co(Tile_X10Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X10Y15_UserCLKo),
+	.FrameStrobe(Tile_X10_FrameStrobe),
+	.FrameStrobe_O(Tile_X10Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X11Y15_S_term_single (
+	.S1END(Tile_X11Y14_S1BEG[3:0]),
+	.S2MID(Tile_X11Y14_S2BEG[7:0]),
+	.S2END(Tile_X11Y14_S2BEGb[7:0]),
+	.S4END(Tile_X11Y14_S4BEG[15:0]),
+	.SS4END(Tile_X11Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X11Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X11Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X11Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X11Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X11Y15_NN4BEG[15:0]),
+	.Co(Tile_X11Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X11Y15_UserCLKo),
+	.FrameStrobe(Tile_X11_FrameStrobe),
+	.FrameStrobe_O(Tile_X11Y15_FrameStrobe_O)
+	);
+
+	S_term_single2 Tile_X12Y15_S_term_single2 (
+	.S1END(Tile_X12Y14_S1BEG[3:0]),
+	.S2MID(Tile_X12Y14_S2BEG[7:0]),
+	.S2END(Tile_X12Y14_S2BEGb[7:0]),
+	.S4END(Tile_X12Y14_S4BEG[15:0]),
+	.SS4END(Tile_X12Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X12Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X12Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X12Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X12Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X12Y15_NN4BEG[15:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X12Y15_UserCLKo),
+	.FrameStrobe(Tile_X12_FrameStrobe),
+	.FrameStrobe_O(Tile_X12Y15_FrameStrobe_O)
+	);
+
+	S_term_single Tile_X13Y15_S_term_single (
+	.S1END(Tile_X13Y14_S1BEG[3:0]),
+	.S2MID(Tile_X13Y14_S2BEG[7:0]),
+	.S2END(Tile_X13Y14_S2BEGb[7:0]),
+	.S4END(Tile_X13Y14_S4BEG[15:0]),
+	.SS4END(Tile_X13Y14_SS4BEG[15:0]),
+	.N1BEG(Tile_X13Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X13Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X13Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X13Y15_N4BEG[15:0]),
+	.NN4BEG(Tile_X13Y15_NN4BEG[15:0]),
+	.Co(Tile_X13Y15_Co[0:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X13Y15_UserCLKo),
+	.FrameStrobe(Tile_X13_FrameStrobe),
+	.FrameStrobe_O(Tile_X13Y15_FrameStrobe_O)
+	);
+
+	S_term_RAM_IO Tile_X14Y15_S_term_RAM_IO (
+	.S1END(Tile_X14Y14_S1BEG[3:0]),
+	.S2MID(Tile_X14Y14_S2BEG[7:0]),
+	.S2END(Tile_X14Y14_S2BEGb[7:0]),
+	.S4END(Tile_X14Y14_S4BEG[15:0]),
+	.N1BEG(Tile_X14Y15_N1BEG[3:0]),
+	.N2BEG(Tile_X14Y15_N2BEG[7:0]),
+	.N2BEGb(Tile_X14Y15_N2BEGb[7:0]),
+	.N4BEG(Tile_X14Y15_N4BEG[15:0]),
+	.UserCLK(UserCLK),
+	.UserCLKo(Tile_X14Y15_UserCLKo),
+	.FrameStrobe(Tile_X14_FrameStrobe),
+	.FrameStrobe_O(Tile_X14Y15_FrameStrobe_O)
+	);
+
+
+	DSP Tile_X4Y1_X4Y2_DSP_tile (
+	.top_E1END(Tile_X3Y1_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y1_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y1_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y1_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y1_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y0_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y0_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y0_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y0_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y0_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y1_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y1_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y1_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y1_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y1_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y1_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y1_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y1_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y1_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y1_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y1_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y1_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y1_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y1_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y1_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y1_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y1_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y1_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y1_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y1_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y1_FrameData_O),
+	.top_FrameData_O(Tile_X4Y1_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y1_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y1_UserCLKo),
+	.bot_N1END(Tile_X4Y3_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y3_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y3_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y3_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y3_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y2_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y2_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y2_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y2_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y2_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y2_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y2_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y2_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y2_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y2_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y2_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y2_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y2_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y2_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y2_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y2_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y2_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y2_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y2_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y2_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y2_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y2_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y2_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y2_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y2_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y3_UserCLKo),
+	.bot_FrameData(Tile_X3Y2_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y2_FrameData_O),
+	.FrameStrobe(Tile_X4Y3_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y1_X8Y2_DSP_tile (
+	.top_E1END(Tile_X7Y1_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y1_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y1_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y1_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y1_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y0_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y0_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y0_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y0_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y0_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y1_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y1_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y1_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y1_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y1_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y1_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y1_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y1_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y1_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y1_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y1_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y1_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y1_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y1_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y1_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y1_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y1_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y1_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y1_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y1_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y1_FrameData_O),
+	.top_FrameData_O(Tile_X8Y1_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y1_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y1_UserCLKo),
+	.bot_N1END(Tile_X8Y3_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y3_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y3_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y3_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y3_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y2_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y2_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y2_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y2_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y2_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y2_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y2_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y2_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y2_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y2_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y2_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y2_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y2_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y2_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y2_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y2_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y2_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y2_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y2_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y2_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y2_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y2_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y2_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y2_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y2_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y3_UserCLKo),
+	.bot_FrameData(Tile_X7Y2_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y2_FrameData_O),
+	.FrameStrobe(Tile_X8Y3_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y3_X4Y4_DSP_tile (
+	.top_E1END(Tile_X3Y3_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y3_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y3_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y3_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y3_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y2_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y2_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y2_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y2_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y2_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y3_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y3_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y3_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y3_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y3_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y3_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y3_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y3_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y3_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y3_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y3_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y3_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y3_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y3_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y3_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y3_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y3_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y3_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y3_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y3_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y3_FrameData_O),
+	.top_FrameData_O(Tile_X4Y3_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y3_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y3_UserCLKo),
+	.bot_N1END(Tile_X4Y5_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y5_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y5_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y5_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y5_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y4_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y4_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y4_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y4_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y4_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y4_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y4_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y4_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y4_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y4_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y4_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y4_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y4_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y4_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y4_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y4_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y4_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y4_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y4_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y4_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y4_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y4_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y4_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y4_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y4_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y5_UserCLKo),
+	.bot_FrameData(Tile_X3Y4_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y4_FrameData_O),
+	.FrameStrobe(Tile_X4Y5_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y3_X8Y4_DSP_tile (
+	.top_E1END(Tile_X7Y3_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y3_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y3_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y3_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y3_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y2_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y2_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y2_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y2_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y2_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y3_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y3_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y3_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y3_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y3_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y3_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y3_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y3_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y3_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y3_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y3_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y3_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y3_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y3_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y3_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y3_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y3_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y3_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y3_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y3_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y3_FrameData_O),
+	.top_FrameData_O(Tile_X8Y3_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y3_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y3_UserCLKo),
+	.bot_N1END(Tile_X8Y5_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y5_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y5_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y5_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y5_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y4_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y4_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y4_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y4_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y4_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y4_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y4_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y4_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y4_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y4_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y4_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y4_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y4_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y4_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y4_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y4_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y4_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y4_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y4_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y4_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y4_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y4_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y4_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y4_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y4_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y5_UserCLKo),
+	.bot_FrameData(Tile_X7Y4_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y4_FrameData_O),
+	.FrameStrobe(Tile_X8Y5_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y5_X4Y6_DSP_tile (
+	.top_E1END(Tile_X3Y5_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y5_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y5_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y5_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y5_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y4_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y4_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y4_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y4_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y4_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y5_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y5_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y5_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y5_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y5_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y5_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y5_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y5_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y5_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y5_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y5_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y5_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y5_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y5_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y5_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y5_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y5_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y5_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y5_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y5_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y5_FrameData_O),
+	.top_FrameData_O(Tile_X4Y5_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y5_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y5_UserCLKo),
+	.bot_N1END(Tile_X4Y7_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y7_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y7_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y7_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y7_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y6_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y6_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y6_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y6_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y6_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y6_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y6_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y6_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y6_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y6_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y6_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y6_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y6_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y6_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y6_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y6_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y6_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y6_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y6_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y6_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y6_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y6_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y6_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y6_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y6_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y7_UserCLKo),
+	.bot_FrameData(Tile_X3Y6_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y6_FrameData_O),
+	.FrameStrobe(Tile_X4Y7_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y5_X8Y6_DSP_tile (
+	.top_E1END(Tile_X7Y5_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y5_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y5_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y5_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y5_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y4_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y4_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y4_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y4_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y4_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y5_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y5_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y5_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y5_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y5_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y5_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y5_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y5_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y5_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y5_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y5_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y5_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y5_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y5_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y5_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y5_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y5_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y5_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y5_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y5_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y5_FrameData_O),
+	.top_FrameData_O(Tile_X8Y5_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y5_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y5_UserCLKo),
+	.bot_N1END(Tile_X8Y7_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y7_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y7_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y7_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y7_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y6_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y6_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y6_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y6_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y6_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y6_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y6_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y6_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y6_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y6_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y6_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y6_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y6_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y6_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y6_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y6_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y6_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y6_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y6_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y6_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y6_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y6_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y6_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y6_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y6_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y7_UserCLKo),
+	.bot_FrameData(Tile_X7Y6_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y6_FrameData_O),
+	.FrameStrobe(Tile_X8Y7_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y7_X4Y8_DSP_tile (
+	.top_E1END(Tile_X3Y7_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y7_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y7_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y7_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y7_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y6_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y6_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y6_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y6_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y6_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y7_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y7_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y7_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y7_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y7_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y7_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y7_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y7_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y7_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y7_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y7_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y7_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y7_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y7_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y7_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y7_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y7_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y7_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y7_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y7_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y7_FrameData_O),
+	.top_FrameData_O(Tile_X4Y7_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y7_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y7_UserCLKo),
+	.bot_N1END(Tile_X4Y9_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y9_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y9_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y9_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y9_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y8_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y8_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y8_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y8_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y8_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y8_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y8_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y8_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y8_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y8_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y8_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y8_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y8_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y8_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y8_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y8_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y8_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y8_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y8_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y8_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y8_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y8_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y8_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y8_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y8_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y9_UserCLKo),
+	.bot_FrameData(Tile_X3Y8_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y8_FrameData_O),
+	.FrameStrobe(Tile_X4Y9_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y7_X8Y8_DSP_tile (
+	.top_E1END(Tile_X7Y7_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y7_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y7_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y7_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y7_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y6_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y6_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y6_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y6_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y6_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y7_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y7_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y7_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y7_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y7_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y7_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y7_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y7_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y7_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y7_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y7_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y7_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y7_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y7_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y7_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y7_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y7_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y7_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y7_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y7_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y7_FrameData_O),
+	.top_FrameData_O(Tile_X8Y7_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y7_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y7_UserCLKo),
+	.bot_N1END(Tile_X8Y9_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y9_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y9_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y9_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y9_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y8_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y8_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y8_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y8_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y8_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y8_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y8_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y8_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y8_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y8_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y8_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y8_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y8_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y8_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y8_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y8_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y8_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y8_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y8_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y8_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y8_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y8_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y8_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y8_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y8_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y9_UserCLKo),
+	.bot_FrameData(Tile_X7Y8_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y8_FrameData_O),
+	.FrameStrobe(Tile_X8Y9_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y9_X4Y10_DSP_tile (
+	.top_E1END(Tile_X3Y9_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y9_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y9_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y9_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y9_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y8_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y8_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y8_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y8_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y8_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y9_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y9_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y9_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y9_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y9_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y9_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y9_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y9_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y9_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y9_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y9_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y9_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y9_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y9_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y9_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y9_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y9_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y9_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y9_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y9_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y9_FrameData_O),
+	.top_FrameData_O(Tile_X4Y9_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y9_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y9_UserCLKo),
+	.bot_N1END(Tile_X4Y11_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y11_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y11_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y11_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y11_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y10_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y10_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y10_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y10_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y10_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y10_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y10_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y10_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y10_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y10_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y10_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y10_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y10_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y10_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y10_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y10_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y10_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y10_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y10_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y10_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y10_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y10_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y10_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y10_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y10_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y11_UserCLKo),
+	.bot_FrameData(Tile_X3Y10_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y10_FrameData_O),
+	.FrameStrobe(Tile_X4Y11_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y9_X8Y10_DSP_tile (
+	.top_E1END(Tile_X7Y9_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y9_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y9_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y9_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y9_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y8_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y8_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y8_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y8_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y8_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y9_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y9_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y9_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y9_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y9_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y9_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y9_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y9_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y9_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y9_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y9_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y9_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y9_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y9_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y9_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y9_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y9_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y9_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y9_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y9_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y9_FrameData_O),
+	.top_FrameData_O(Tile_X8Y9_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y9_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y9_UserCLKo),
+	.bot_N1END(Tile_X8Y11_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y11_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y11_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y11_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y11_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y10_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y10_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y10_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y10_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y10_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y10_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y10_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y10_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y10_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y10_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y10_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y10_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y10_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y10_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y10_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y10_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y10_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y10_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y10_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y10_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y10_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y10_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y10_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y10_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y10_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y11_UserCLKo),
+	.bot_FrameData(Tile_X7Y10_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y10_FrameData_O),
+	.FrameStrobe(Tile_X8Y11_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y11_X4Y12_DSP_tile (
+	.top_E1END(Tile_X3Y11_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y11_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y11_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y11_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y11_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y10_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y10_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y10_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y10_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y10_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y11_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y11_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y11_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y11_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y11_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y11_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y11_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y11_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y11_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y11_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y11_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y11_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y11_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y11_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y11_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y11_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y11_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y11_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y11_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y11_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y11_FrameData_O),
+	.top_FrameData_O(Tile_X4Y11_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y11_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y11_UserCLKo),
+	.bot_N1END(Tile_X4Y13_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y13_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y13_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y13_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y13_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y12_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y12_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y12_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y12_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y12_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y12_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y12_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y12_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y12_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y12_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y12_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y12_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y12_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y12_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y12_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y12_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y12_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y12_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y12_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y12_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y12_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y12_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y12_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y12_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y12_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y13_UserCLKo),
+	.bot_FrameData(Tile_X3Y12_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y12_FrameData_O),
+	.FrameStrobe(Tile_X4Y13_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y11_X8Y12_DSP_tile (
+	.top_E1END(Tile_X7Y11_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y11_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y11_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y11_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y11_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y10_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y10_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y10_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y10_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y10_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y11_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y11_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y11_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y11_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y11_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y11_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y11_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y11_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y11_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y11_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y11_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y11_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y11_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y11_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y11_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y11_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y11_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y11_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y11_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y11_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y11_FrameData_O),
+	.top_FrameData_O(Tile_X8Y11_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y11_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y11_UserCLKo),
+	.bot_N1END(Tile_X8Y13_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y13_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y13_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y13_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y13_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y12_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y12_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y12_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y12_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y12_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y12_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y12_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y12_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y12_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y12_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y12_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y12_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y12_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y12_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y12_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y12_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y12_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y12_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y12_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y12_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y12_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y12_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y12_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y12_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y12_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y13_UserCLKo),
+	.bot_FrameData(Tile_X7Y12_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y12_FrameData_O),
+	.FrameStrobe(Tile_X8Y13_FrameStrobe_O)
+	);
+
+	DSP Tile_X4Y13_X4Y14_DSP_tile (
+	.top_E1END(Tile_X3Y13_E1BEG[3:0]),
+	.top_E2MID(Tile_X3Y13_E2BEG[7:0]),
+	.top_E2END(Tile_X3Y13_E2BEGb[7:0]),
+	.top_EE4END(Tile_X3Y13_EE4BEG[15:0]),
+	.top_E6END(Tile_X3Y13_E6BEG[11:0]),
+	.top_S1END(Tile_X4Y12_S1BEG[3:0]),
+	.top_S2MID(Tile_X4Y12_S2BEG[7:0]),
+	.top_S2END(Tile_X4Y12_S2BEGb[7:0]),
+	.top_S4END(Tile_X4Y12_S4BEG[15:0]),
+	.top_SS4END(Tile_X4Y12_SS4BEG[15:0]),
+	.top_W1END(Tile_X5Y13_W1BEG[3:0]),
+	.top_W2MID(Tile_X5Y13_W2BEG[7:0]),
+	.top_W2END(Tile_X5Y13_W2BEGb[7:0]),
+	.top_WW4END(Tile_X5Y13_WW4BEG[15:0]),
+	.top_W6END(Tile_X5Y13_W6BEG[11:0]),
+	.top_N1BEG(Tile_X4Y13_N1BEG[3:0]),
+	.top_N2BEG(Tile_X4Y13_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X4Y13_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X4Y13_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X4Y13_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X4Y13_E1BEG[3:0]),
+	.top_E2BEG(Tile_X4Y13_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X4Y13_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X4Y13_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X4Y13_E6BEG[11:0]),
+	.top_W1BEG(Tile_X4Y13_W1BEG[3:0]),
+	.top_W2BEG(Tile_X4Y13_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X4Y13_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X4Y13_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X4Y13_W6BEG[11:0]),
+	.top_FrameData(Tile_X3Y13_FrameData_O),
+	.top_FrameData_O(Tile_X4Y13_FrameData_O),
+	.FrameStrobe_O(Tile_X4Y13_FrameStrobe_O),
+	.UserCLKo(Tile_X4Y13_UserCLKo),
+	.bot_N1END(Tile_X4Y15_N1BEG[3:0]),
+	.bot_N2MID(Tile_X4Y15_N2BEG[7:0]),
+	.bot_N2END(Tile_X4Y15_N2BEGb[7:0]),
+	.bot_N4END(Tile_X4Y15_N4BEG[15:0]),
+	.bot_NN4END(Tile_X4Y15_NN4BEG[15:0]),
+	.bot_E1END(Tile_X3Y14_E1BEG[3:0]),
+	.bot_E2MID(Tile_X3Y14_E2BEG[7:0]),
+	.bot_E2END(Tile_X3Y14_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X3Y14_EE4BEG[15:0]),
+	.bot_E6END(Tile_X3Y14_E6BEG[11:0]),
+	.bot_W1END(Tile_X5Y14_W1BEG[3:0]),
+	.bot_W2MID(Tile_X5Y14_W2BEG[7:0]),
+	.bot_W2END(Tile_X5Y14_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X5Y14_WW4BEG[15:0]),
+	.bot_W6END(Tile_X5Y14_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X4Y14_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X4Y14_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X4Y14_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X4Y14_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X4Y14_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X4Y14_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X4Y14_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X4Y14_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X4Y14_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X4Y14_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X4Y14_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X4Y14_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X4Y14_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X4Y14_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X4Y14_W6BEG[11:0]),
+	.UserCLK(Tile_X4Y15_UserCLKo),
+	.bot_FrameData(Tile_X3Y14_FrameData_O),
+	.bot_FrameData_O(Tile_X4Y14_FrameData_O),
+	.FrameStrobe(Tile_X4Y15_FrameStrobe_O)
+	);
+
+	DSP Tile_X8Y13_X8Y14_DSP_tile (
+	.top_E1END(Tile_X7Y13_E1BEG[3:0]),
+	.top_E2MID(Tile_X7Y13_E2BEG[7:0]),
+	.top_E2END(Tile_X7Y13_E2BEGb[7:0]),
+	.top_EE4END(Tile_X7Y13_EE4BEG[15:0]),
+	.top_E6END(Tile_X7Y13_E6BEG[11:0]),
+	.top_S1END(Tile_X8Y12_S1BEG[3:0]),
+	.top_S2MID(Tile_X8Y12_S2BEG[7:0]),
+	.top_S2END(Tile_X8Y12_S2BEGb[7:0]),
+	.top_S4END(Tile_X8Y12_S4BEG[15:0]),
+	.top_SS4END(Tile_X8Y12_SS4BEG[15:0]),
+	.top_W1END(Tile_X9Y13_W1BEG[3:0]),
+	.top_W2MID(Tile_X9Y13_W2BEG[7:0]),
+	.top_W2END(Tile_X9Y13_W2BEGb[7:0]),
+	.top_WW4END(Tile_X9Y13_WW4BEG[15:0]),
+	.top_W6END(Tile_X9Y13_W6BEG[11:0]),
+	.top_N1BEG(Tile_X8Y13_N1BEG[3:0]),
+	.top_N2BEG(Tile_X8Y13_N2BEG[7:0]),
+	.top_N2BEGb(Tile_X8Y13_N2BEGb[7:0]),
+	.top_N4BEG(Tile_X8Y13_N4BEG[15:0]),
+	.top_NN4BEG(Tile_X8Y13_NN4BEG[15:0]),
+	.top_E1BEG(Tile_X8Y13_E1BEG[3:0]),
+	.top_E2BEG(Tile_X8Y13_E2BEG[7:0]),
+	.top_E2BEGb(Tile_X8Y13_E2BEGb[7:0]),
+	.top_EE4BEG(Tile_X8Y13_EE4BEG[15:0]),
+	.top_E6BEG(Tile_X8Y13_E6BEG[11:0]),
+	.top_W1BEG(Tile_X8Y13_W1BEG[3:0]),
+	.top_W2BEG(Tile_X8Y13_W2BEG[7:0]),
+	.top_W2BEGb(Tile_X8Y13_W2BEGb[7:0]),
+	.top_WW4BEG(Tile_X8Y13_WW4BEG[15:0]),
+	.top_W6BEG(Tile_X8Y13_W6BEG[11:0]),
+	.top_FrameData(Tile_X7Y13_FrameData_O),
+	.top_FrameData_O(Tile_X8Y13_FrameData_O),
+	.FrameStrobe_O(Tile_X8Y13_FrameStrobe_O),
+	.UserCLKo(Tile_X8Y13_UserCLKo),
+	.bot_N1END(Tile_X8Y15_N1BEG[3:0]),
+	.bot_N2MID(Tile_X8Y15_N2BEG[7:0]),
+	.bot_N2END(Tile_X8Y15_N2BEGb[7:0]),
+	.bot_N4END(Tile_X8Y15_N4BEG[15:0]),
+	.bot_NN4END(Tile_X8Y15_NN4BEG[15:0]),
+	.bot_E1END(Tile_X7Y14_E1BEG[3:0]),
+	.bot_E2MID(Tile_X7Y14_E2BEG[7:0]),
+	.bot_E2END(Tile_X7Y14_E2BEGb[7:0]),
+	.bot_EE4END(Tile_X7Y14_EE4BEG[15:0]),
+	.bot_E6END(Tile_X7Y14_E6BEG[11:0]),
+	.bot_W1END(Tile_X9Y14_W1BEG[3:0]),
+	.bot_W2MID(Tile_X9Y14_W2BEG[7:0]),
+	.bot_W2END(Tile_X9Y14_W2BEGb[7:0]),
+	.bot_WW4END(Tile_X9Y14_WW4BEG[15:0]),
+	.bot_W6END(Tile_X9Y14_W6BEG[11:0]),
+	.bot_E1BEG(Tile_X8Y14_E1BEG[3:0]),
+	.bot_E2BEG(Tile_X8Y14_E2BEG[7:0]),
+	.bot_E2BEGb(Tile_X8Y14_E2BEGb[7:0]),
+	.bot_EE4BEG(Tile_X8Y14_EE4BEG[15:0]),
+	.bot_E6BEG(Tile_X8Y14_E6BEG[11:0]),
+	.bot_S1BEG(Tile_X8Y14_S1BEG[3:0]),
+	.bot_S2BEG(Tile_X8Y14_S2BEG[7:0]),
+	.bot_S2BEGb(Tile_X8Y14_S2BEGb[7:0]),
+	.bot_S4BEG(Tile_X8Y14_S4BEG[15:0]),
+	.bot_SS4BEG(Tile_X8Y14_SS4BEG[15:0]),
+	.bot_W1BEG(Tile_X8Y14_W1BEG[3:0]),
+	.bot_W2BEG(Tile_X8Y14_W2BEG[7:0]),
+	.bot_W2BEGb(Tile_X8Y14_W2BEGb[7:0]),
+	.bot_WW4BEG(Tile_X8Y14_WW4BEG[15:0]),
+	.bot_W6BEG(Tile_X8Y14_W6BEG[11:0]),
+	.UserCLK(Tile_X8Y15_UserCLKo),
+	.bot_FrameData(Tile_X7Y14_FrameData_O),
+	.bot_FrameData_O(Tile_X8Y14_FrameData_O),
+	.FrameStrobe(Tile_X8Y15_FrameStrobe_O)
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_bot_ConfigMem.v b/verilog/rtl/eFPGA_core/DSP_bot_ConfigMem.v
new file mode 100644
index 0000000..71d4e0d
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_bot_ConfigMem.v
@@ -0,0 +1,2953 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module DSP_bot_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 416;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [32-1:0] frame0;
+	wire [32-1:0] frame1;
+	wire [32-1:0] frame2;
+	wire [32-1:0] frame3;
+	wire [32-1:0] frame4;
+	wire [32-1:0] frame5;
+	wire [32-1:0] frame6;
+	wire [32-1:0] frame7;
+	wire [32-1:0] frame8;
+	wire [32-1:0] frame9;
+	wire [32-1:0] frame10;
+	wire [32-1:0] frame11;
+	wire [32-1:0] frame12;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[415]),
+	.QN(ConfigBits_N[415])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[414]),
+	.QN(ConfigBits_N[414])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[413]),
+	.QN(ConfigBits_N[413])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[412]),
+	.QN(ConfigBits_N[412])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[411]),
+	.QN(ConfigBits_N[411])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[410]),
+	.QN(ConfigBits_N[410])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[409]),
+	.QN(ConfigBits_N[409])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[408]),
+	.QN(ConfigBits_N[408])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[407]),
+	.QN(ConfigBits_N[407])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[406]),
+	.QN(ConfigBits_N[406])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[405]),
+	.QN(ConfigBits_N[405])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[404]),
+	.QN(ConfigBits_N[404])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[403]),
+	.QN(ConfigBits_N[403])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[402]),
+	.QN(ConfigBits_N[402])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[401]),
+	.QN(ConfigBits_N[401])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[400]),
+	.QN(ConfigBits_N[400])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[399]),
+	.QN(ConfigBits_N[399])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[398]),
+	.QN(ConfigBits_N[398])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[397]),
+	.QN(ConfigBits_N[397])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[396]),
+	.QN(ConfigBits_N[396])
+	);
+
+	LHQD1 Inst_frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[395]),
+	.QN(ConfigBits_N[395])
+	);
+
+	LHQD1 Inst_frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[394]),
+	.QN(ConfigBits_N[394])
+	);
+
+	LHQD1 Inst_frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[393]),
+	.QN(ConfigBits_N[393])
+	);
+
+	LHQD1 Inst_frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[392]),
+	.QN(ConfigBits_N[392])
+	);
+
+	LHQD1 Inst_frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[391]),
+	.QN(ConfigBits_N[391])
+	);
+
+	LHQD1 Inst_frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[390]),
+	.QN(ConfigBits_N[390])
+	);
+
+	LHQD1 Inst_frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[389]),
+	.QN(ConfigBits_N[389])
+	);
+
+	LHQD1 Inst_frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[388]),
+	.QN(ConfigBits_N[388])
+	);
+
+	LHQD1 Inst_frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[387]),
+	.QN(ConfigBits_N[387])
+	);
+
+	LHQD1 Inst_frame0_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[386]),
+	.QN(ConfigBits_N[386])
+	);
+
+	LHQD1 Inst_frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[385]),
+	.QN(ConfigBits_N[385])
+	);
+
+	LHQD1 Inst_frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[384]),
+	.QN(ConfigBits_N[384])
+	);
+
+	LHQD1 Inst_frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[383]),
+	.QN(ConfigBits_N[383])
+	);
+
+	LHQD1 Inst_frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[382]),
+	.QN(ConfigBits_N[382])
+	);
+
+	LHQD1 Inst_frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[381]),
+	.QN(ConfigBits_N[381])
+	);
+
+	LHQD1 Inst_frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[380]),
+	.QN(ConfigBits_N[380])
+	);
+
+	LHQD1 Inst_frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[379]),
+	.QN(ConfigBits_N[379])
+	);
+
+	LHQD1 Inst_frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[378]),
+	.QN(ConfigBits_N[378])
+	);
+
+	LHQD1 Inst_frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[377]),
+	.QN(ConfigBits_N[377])
+	);
+
+	LHQD1 Inst_frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[376]),
+	.QN(ConfigBits_N[376])
+	);
+
+	LHQD1 Inst_frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[375]),
+	.QN(ConfigBits_N[375])
+	);
+
+	LHQD1 Inst_frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[374]),
+	.QN(ConfigBits_N[374])
+	);
+
+	LHQD1 Inst_frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[373]),
+	.QN(ConfigBits_N[373])
+	);
+
+	LHQD1 Inst_frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[372]),
+	.QN(ConfigBits_N[372])
+	);
+
+	LHQD1 Inst_frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[371]),
+	.QN(ConfigBits_N[371])
+	);
+
+	LHQD1 Inst_frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[370]),
+	.QN(ConfigBits_N[370])
+	);
+
+	LHQD1 Inst_frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[369]),
+	.QN(ConfigBits_N[369])
+	);
+
+	LHQD1 Inst_frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[368]),
+	.QN(ConfigBits_N[368])
+	);
+
+	LHQD1 Inst_frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[367]),
+	.QN(ConfigBits_N[367])
+	);
+
+	LHQD1 Inst_frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[366]),
+	.QN(ConfigBits_N[366])
+	);
+
+	LHQD1 Inst_frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[365]),
+	.QN(ConfigBits_N[365])
+	);
+
+	LHQD1 Inst_frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[364]),
+	.QN(ConfigBits_N[364])
+	);
+
+	LHQD1 Inst_frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[363]),
+	.QN(ConfigBits_N[363])
+	);
+
+	LHQD1 Inst_frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[362]),
+	.QN(ConfigBits_N[362])
+	);
+
+	LHQD1 Inst_frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[361]),
+	.QN(ConfigBits_N[361])
+	);
+
+	LHQD1 Inst_frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[360]),
+	.QN(ConfigBits_N[360])
+	);
+
+	LHQD1 Inst_frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[359]),
+	.QN(ConfigBits_N[359])
+	);
+
+	LHQD1 Inst_frame1_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[358]),
+	.QN(ConfigBits_N[358])
+	);
+
+	LHQD1 Inst_frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[357]),
+	.QN(ConfigBits_N[357])
+	);
+
+	LHQD1 Inst_frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[356]),
+	.QN(ConfigBits_N[356])
+	);
+
+	LHQD1 Inst_frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[355]),
+	.QN(ConfigBits_N[355])
+	);
+
+	LHQD1 Inst_frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[354]),
+	.QN(ConfigBits_N[354])
+	);
+
+	LHQD1 Inst_frame1_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[353]),
+	.QN(ConfigBits_N[353])
+	);
+
+	LHQD1 Inst_frame1_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[352]),
+	.QN(ConfigBits_N[352])
+	);
+
+	LHQD1 Inst_frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[351]),
+	.QN(ConfigBits_N[351])
+	);
+
+	LHQD1 Inst_frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[350]),
+	.QN(ConfigBits_N[350])
+	);
+
+	LHQD1 Inst_frame2_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[349]),
+	.QN(ConfigBits_N[349])
+	);
+
+	LHQD1 Inst_frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[348]),
+	.QN(ConfigBits_N[348])
+	);
+
+	LHQD1 Inst_frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[347]),
+	.QN(ConfigBits_N[347])
+	);
+
+	LHQD1 Inst_frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[346]),
+	.QN(ConfigBits_N[346])
+	);
+
+	LHQD1 Inst_frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[345]),
+	.QN(ConfigBits_N[345])
+	);
+
+	LHQD1 Inst_frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[344]),
+	.QN(ConfigBits_N[344])
+	);
+
+	LHQD1 Inst_frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[343]),
+	.QN(ConfigBits_N[343])
+	);
+
+	LHQD1 Inst_frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[342]),
+	.QN(ConfigBits_N[342])
+	);
+
+	LHQD1 Inst_frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[341]),
+	.QN(ConfigBits_N[341])
+	);
+
+	LHQD1 Inst_frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[340]),
+	.QN(ConfigBits_N[340])
+	);
+
+	LHQD1 Inst_frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[339]),
+	.QN(ConfigBits_N[339])
+	);
+
+	LHQD1 Inst_frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[338]),
+	.QN(ConfigBits_N[338])
+	);
+
+	LHQD1 Inst_frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[337]),
+	.QN(ConfigBits_N[337])
+	);
+
+	LHQD1 Inst_frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[336]),
+	.QN(ConfigBits_N[336])
+	);
+
+	LHQD1 Inst_frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[335]),
+	.QN(ConfigBits_N[335])
+	);
+
+	LHQD1 Inst_frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[334]),
+	.QN(ConfigBits_N[334])
+	);
+
+	LHQD1 Inst_frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[333]),
+	.QN(ConfigBits_N[333])
+	);
+
+	LHQD1 Inst_frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[332]),
+	.QN(ConfigBits_N[332])
+	);
+
+	LHQD1 Inst_frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[331]),
+	.QN(ConfigBits_N[331])
+	);
+
+	LHQD1 Inst_frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[330]),
+	.QN(ConfigBits_N[330])
+	);
+
+	LHQD1 Inst_frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[329]),
+	.QN(ConfigBits_N[329])
+	);
+
+	LHQD1 Inst_frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[328]),
+	.QN(ConfigBits_N[328])
+	);
+
+	LHQD1 Inst_frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[327]),
+	.QN(ConfigBits_N[327])
+	);
+
+	LHQD1 Inst_frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[326]),
+	.QN(ConfigBits_N[326])
+	);
+
+	LHQD1 Inst_frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[325]),
+	.QN(ConfigBits_N[325])
+	);
+
+	LHQD1 Inst_frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[324]),
+	.QN(ConfigBits_N[324])
+	);
+
+	LHQD1 Inst_frame2_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[323]),
+	.QN(ConfigBits_N[323])
+	);
+
+	LHQD1 Inst_frame2_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[322]),
+	.QN(ConfigBits_N[322])
+	);
+
+	LHQD1 Inst_frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[321]),
+	.QN(ConfigBits_N[321])
+	);
+
+	LHQD1 Inst_frame2_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[320]),
+	.QN(ConfigBits_N[320])
+	);
+
+	LHQD1 Inst_frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[319]),
+	.QN(ConfigBits_N[319])
+	);
+
+	LHQD1 Inst_frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[318]),
+	.QN(ConfigBits_N[318])
+	);
+
+	LHQD1 Inst_frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[317]),
+	.QN(ConfigBits_N[317])
+	);
+
+	LHQD1 Inst_frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[316]),
+	.QN(ConfigBits_N[316])
+	);
+
+	LHQD1 Inst_frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[315]),
+	.QN(ConfigBits_N[315])
+	);
+
+	LHQD1 Inst_frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[314]),
+	.QN(ConfigBits_N[314])
+	);
+
+	LHQD1 Inst_frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[313]),
+	.QN(ConfigBits_N[313])
+	);
+
+	LHQD1 Inst_frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[312]),
+	.QN(ConfigBits_N[312])
+	);
+
+	LHQD1 Inst_frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[311]),
+	.QN(ConfigBits_N[311])
+	);
+
+	LHQD1 Inst_frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[310]),
+	.QN(ConfigBits_N[310])
+	);
+
+	LHQD1 Inst_frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[309]),
+	.QN(ConfigBits_N[309])
+	);
+
+	LHQD1 Inst_frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[308]),
+	.QN(ConfigBits_N[308])
+	);
+
+	LHQD1 Inst_frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[307]),
+	.QN(ConfigBits_N[307])
+	);
+
+	LHQD1 Inst_frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[306]),
+	.QN(ConfigBits_N[306])
+	);
+
+	LHQD1 Inst_frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[305]),
+	.QN(ConfigBits_N[305])
+	);
+
+	LHQD1 Inst_frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[304]),
+	.QN(ConfigBits_N[304])
+	);
+
+	LHQD1 Inst_frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[303]),
+	.QN(ConfigBits_N[303])
+	);
+
+	LHQD1 Inst_frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[302]),
+	.QN(ConfigBits_N[302])
+	);
+
+	LHQD1 Inst_frame3_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[301]),
+	.QN(ConfigBits_N[301])
+	);
+
+	LHQD1 Inst_frame3_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[300]),
+	.QN(ConfigBits_N[300])
+	);
+
+	LHQD1 Inst_frame3_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[299]),
+	.QN(ConfigBits_N[299])
+	);
+
+	LHQD1 Inst_frame3_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[298]),
+	.QN(ConfigBits_N[298])
+	);
+
+	LHQD1 Inst_frame3_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[297]),
+	.QN(ConfigBits_N[297])
+	);
+
+	LHQD1 Inst_frame3_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[296]),
+	.QN(ConfigBits_N[296])
+	);
+
+	LHQD1 Inst_frame3_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[295]),
+	.QN(ConfigBits_N[295])
+	);
+
+	LHQD1 Inst_frame3_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[294]),
+	.QN(ConfigBits_N[294])
+	);
+
+	LHQD1 Inst_frame3_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[293]),
+	.QN(ConfigBits_N[293])
+	);
+
+	LHQD1 Inst_frame3_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[292]),
+	.QN(ConfigBits_N[292])
+	);
+
+	LHQD1 Inst_frame3_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[291]),
+	.QN(ConfigBits_N[291])
+	);
+
+	LHQD1 Inst_frame3_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[290]),
+	.QN(ConfigBits_N[290])
+	);
+
+	LHQD1 Inst_frame3_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[289]),
+	.QN(ConfigBits_N[289])
+	);
+
+	LHQD1 Inst_frame3_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[288]),
+	.QN(ConfigBits_N[288])
+	);
+
+	LHQD1 Inst_frame4_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[287]),
+	.QN(ConfigBits_N[287])
+	);
+
+	LHQD1 Inst_frame4_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[286]),
+	.QN(ConfigBits_N[286])
+	);
+
+	LHQD1 Inst_frame4_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[285]),
+	.QN(ConfigBits_N[285])
+	);
+
+	LHQD1 Inst_frame4_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[284]),
+	.QN(ConfigBits_N[284])
+	);
+
+	LHQD1 Inst_frame4_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[283]),
+	.QN(ConfigBits_N[283])
+	);
+
+	LHQD1 Inst_frame4_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[282]),
+	.QN(ConfigBits_N[282])
+	);
+
+	LHQD1 Inst_frame4_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[281]),
+	.QN(ConfigBits_N[281])
+	);
+
+	LHQD1 Inst_frame4_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[280]),
+	.QN(ConfigBits_N[280])
+	);
+
+	LHQD1 Inst_frame4_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[279]),
+	.QN(ConfigBits_N[279])
+	);
+
+	LHQD1 Inst_frame4_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[278]),
+	.QN(ConfigBits_N[278])
+	);
+
+	LHQD1 Inst_frame4_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[277]),
+	.QN(ConfigBits_N[277])
+	);
+
+	LHQD1 Inst_frame4_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[276]),
+	.QN(ConfigBits_N[276])
+	);
+
+	LHQD1 Inst_frame4_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[275]),
+	.QN(ConfigBits_N[275])
+	);
+
+	LHQD1 Inst_frame4_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[274]),
+	.QN(ConfigBits_N[274])
+	);
+
+	LHQD1 Inst_frame4_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[273]),
+	.QN(ConfigBits_N[273])
+	);
+
+	LHQD1 Inst_frame4_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[272]),
+	.QN(ConfigBits_N[272])
+	);
+
+	LHQD1 Inst_frame4_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[271]),
+	.QN(ConfigBits_N[271])
+	);
+
+	LHQD1 Inst_frame4_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[270]),
+	.QN(ConfigBits_N[270])
+	);
+
+	LHQD1 Inst_frame4_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[269]),
+	.QN(ConfigBits_N[269])
+	);
+
+	LHQD1 Inst_frame4_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[268]),
+	.QN(ConfigBits_N[268])
+	);
+
+	LHQD1 Inst_frame4_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[267]),
+	.QN(ConfigBits_N[267])
+	);
+
+	LHQD1 Inst_frame4_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[266]),
+	.QN(ConfigBits_N[266])
+	);
+
+	LHQD1 Inst_frame4_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[265]),
+	.QN(ConfigBits_N[265])
+	);
+
+	LHQD1 Inst_frame4_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[264]),
+	.QN(ConfigBits_N[264])
+	);
+
+	LHQD1 Inst_frame4_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[263]),
+	.QN(ConfigBits_N[263])
+	);
+
+	LHQD1 Inst_frame4_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[262]),
+	.QN(ConfigBits_N[262])
+	);
+
+	LHQD1 Inst_frame4_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[261]),
+	.QN(ConfigBits_N[261])
+	);
+
+	LHQD1 Inst_frame4_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[260]),
+	.QN(ConfigBits_N[260])
+	);
+
+	LHQD1 Inst_frame4_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[259]),
+	.QN(ConfigBits_N[259])
+	);
+
+	LHQD1 Inst_frame4_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[258]),
+	.QN(ConfigBits_N[258])
+	);
+
+	LHQD1 Inst_frame4_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[257]),
+	.QN(ConfigBits_N[257])
+	);
+
+	LHQD1 Inst_frame4_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[256]),
+	.QN(ConfigBits_N[256])
+	);
+
+	LHQD1 Inst_frame5_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[255]),
+	.QN(ConfigBits_N[255])
+	);
+
+	LHQD1 Inst_frame5_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[254]),
+	.QN(ConfigBits_N[254])
+	);
+
+	LHQD1 Inst_frame5_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[253]),
+	.QN(ConfigBits_N[253])
+	);
+
+	LHQD1 Inst_frame5_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[252]),
+	.QN(ConfigBits_N[252])
+	);
+
+	LHQD1 Inst_frame5_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[251]),
+	.QN(ConfigBits_N[251])
+	);
+
+	LHQD1 Inst_frame5_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[250]),
+	.QN(ConfigBits_N[250])
+	);
+
+	LHQD1 Inst_frame5_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[249]),
+	.QN(ConfigBits_N[249])
+	);
+
+	LHQD1 Inst_frame5_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[248]),
+	.QN(ConfigBits_N[248])
+	);
+
+	LHQD1 Inst_frame5_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[247]),
+	.QN(ConfigBits_N[247])
+	);
+
+	LHQD1 Inst_frame5_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[246]),
+	.QN(ConfigBits_N[246])
+	);
+
+	LHQD1 Inst_frame5_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[245]),
+	.QN(ConfigBits_N[245])
+	);
+
+	LHQD1 Inst_frame5_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[244]),
+	.QN(ConfigBits_N[244])
+	);
+
+	LHQD1 Inst_frame5_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[243]),
+	.QN(ConfigBits_N[243])
+	);
+
+	LHQD1 Inst_frame5_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[242]),
+	.QN(ConfigBits_N[242])
+	);
+
+	LHQD1 Inst_frame5_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[241]),
+	.QN(ConfigBits_N[241])
+	);
+
+	LHQD1 Inst_frame5_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[240]),
+	.QN(ConfigBits_N[240])
+	);
+
+	LHQD1 Inst_frame5_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[239]),
+	.QN(ConfigBits_N[239])
+	);
+
+	LHQD1 Inst_frame5_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[238]),
+	.QN(ConfigBits_N[238])
+	);
+
+	LHQD1 Inst_frame5_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[237]),
+	.QN(ConfigBits_N[237])
+	);
+
+	LHQD1 Inst_frame5_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[236]),
+	.QN(ConfigBits_N[236])
+	);
+
+	LHQD1 Inst_frame5_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[235]),
+	.QN(ConfigBits_N[235])
+	);
+
+	LHQD1 Inst_frame5_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[234]),
+	.QN(ConfigBits_N[234])
+	);
+
+	LHQD1 Inst_frame5_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[233]),
+	.QN(ConfigBits_N[233])
+	);
+
+	LHQD1 Inst_frame5_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[232]),
+	.QN(ConfigBits_N[232])
+	);
+
+	LHQD1 Inst_frame5_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[231]),
+	.QN(ConfigBits_N[231])
+	);
+
+	LHQD1 Inst_frame5_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[230]),
+	.QN(ConfigBits_N[230])
+	);
+
+	LHQD1 Inst_frame5_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[229]),
+	.QN(ConfigBits_N[229])
+	);
+
+	LHQD1 Inst_frame5_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[228]),
+	.QN(ConfigBits_N[228])
+	);
+
+	LHQD1 Inst_frame5_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[227]),
+	.QN(ConfigBits_N[227])
+	);
+
+	LHQD1 Inst_frame5_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[226]),
+	.QN(ConfigBits_N[226])
+	);
+
+	LHQD1 Inst_frame5_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[225]),
+	.QN(ConfigBits_N[225])
+	);
+
+	LHQD1 Inst_frame5_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[224]),
+	.QN(ConfigBits_N[224])
+	);
+
+	LHQD1 Inst_frame6_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[223]),
+	.QN(ConfigBits_N[223])
+	);
+
+	LHQD1 Inst_frame6_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[222]),
+	.QN(ConfigBits_N[222])
+	);
+
+	LHQD1 Inst_frame6_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[221]),
+	.QN(ConfigBits_N[221])
+	);
+
+	LHQD1 Inst_frame6_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[220]),
+	.QN(ConfigBits_N[220])
+	);
+
+	LHQD1 Inst_frame6_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[219]),
+	.QN(ConfigBits_N[219])
+	);
+
+	LHQD1 Inst_frame6_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[218]),
+	.QN(ConfigBits_N[218])
+	);
+
+	LHQD1 Inst_frame6_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[217]),
+	.QN(ConfigBits_N[217])
+	);
+
+	LHQD1 Inst_frame6_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[216]),
+	.QN(ConfigBits_N[216])
+	);
+
+	LHQD1 Inst_frame6_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[215]),
+	.QN(ConfigBits_N[215])
+	);
+
+	LHQD1 Inst_frame6_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[214]),
+	.QN(ConfigBits_N[214])
+	);
+
+	LHQD1 Inst_frame6_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[213]),
+	.QN(ConfigBits_N[213])
+	);
+
+	LHQD1 Inst_frame6_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[212]),
+	.QN(ConfigBits_N[212])
+	);
+
+	LHQD1 Inst_frame6_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[211]),
+	.QN(ConfigBits_N[211])
+	);
+
+	LHQD1 Inst_frame6_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[210]),
+	.QN(ConfigBits_N[210])
+	);
+
+	LHQD1 Inst_frame6_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[209]),
+	.QN(ConfigBits_N[209])
+	);
+
+	LHQD1 Inst_frame6_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[208]),
+	.QN(ConfigBits_N[208])
+	);
+
+	LHQD1 Inst_frame6_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[207]),
+	.QN(ConfigBits_N[207])
+	);
+
+	LHQD1 Inst_frame6_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[206]),
+	.QN(ConfigBits_N[206])
+	);
+
+	LHQD1 Inst_frame6_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[205]),
+	.QN(ConfigBits_N[205])
+	);
+
+	LHQD1 Inst_frame6_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[204]),
+	.QN(ConfigBits_N[204])
+	);
+
+	LHQD1 Inst_frame6_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[203]),
+	.QN(ConfigBits_N[203])
+	);
+
+	LHQD1 Inst_frame6_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[202]),
+	.QN(ConfigBits_N[202])
+	);
+
+	LHQD1 Inst_frame6_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[201]),
+	.QN(ConfigBits_N[201])
+	);
+
+	LHQD1 Inst_frame6_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[200]),
+	.QN(ConfigBits_N[200])
+	);
+
+	LHQD1 Inst_frame6_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[199]),
+	.QN(ConfigBits_N[199])
+	);
+
+	LHQD1 Inst_frame6_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[198]),
+	.QN(ConfigBits_N[198])
+	);
+
+	LHQD1 Inst_frame6_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[197]),
+	.QN(ConfigBits_N[197])
+	);
+
+	LHQD1 Inst_frame6_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[196]),
+	.QN(ConfigBits_N[196])
+	);
+
+	LHQD1 Inst_frame6_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[195]),
+	.QN(ConfigBits_N[195])
+	);
+
+	LHQD1 Inst_frame6_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[194]),
+	.QN(ConfigBits_N[194])
+	);
+
+	LHQD1 Inst_frame6_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[193]),
+	.QN(ConfigBits_N[193])
+	);
+
+	LHQD1 Inst_frame6_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[192]),
+	.QN(ConfigBits_N[192])
+	);
+
+	LHQD1 Inst_frame7_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[191]),
+	.QN(ConfigBits_N[191])
+	);
+
+	LHQD1 Inst_frame7_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[190]),
+	.QN(ConfigBits_N[190])
+	);
+
+	LHQD1 Inst_frame7_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[189]),
+	.QN(ConfigBits_N[189])
+	);
+
+	LHQD1 Inst_frame7_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[188]),
+	.QN(ConfigBits_N[188])
+	);
+
+	LHQD1 Inst_frame7_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[187]),
+	.QN(ConfigBits_N[187])
+	);
+
+	LHQD1 Inst_frame7_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[186]),
+	.QN(ConfigBits_N[186])
+	);
+
+	LHQD1 Inst_frame7_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[185]),
+	.QN(ConfigBits_N[185])
+	);
+
+	LHQD1 Inst_frame7_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[184]),
+	.QN(ConfigBits_N[184])
+	);
+
+	LHQD1 Inst_frame7_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[183]),
+	.QN(ConfigBits_N[183])
+	);
+
+	LHQD1 Inst_frame7_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[182]),
+	.QN(ConfigBits_N[182])
+	);
+
+	LHQD1 Inst_frame7_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[181]),
+	.QN(ConfigBits_N[181])
+	);
+
+	LHQD1 Inst_frame7_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[180]),
+	.QN(ConfigBits_N[180])
+	);
+
+	LHQD1 Inst_frame7_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[179]),
+	.QN(ConfigBits_N[179])
+	);
+
+	LHQD1 Inst_frame7_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[178]),
+	.QN(ConfigBits_N[178])
+	);
+
+	LHQD1 Inst_frame7_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[177]),
+	.QN(ConfigBits_N[177])
+	);
+
+	LHQD1 Inst_frame7_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[176]),
+	.QN(ConfigBits_N[176])
+	);
+
+	LHQD1 Inst_frame7_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[175]),
+	.QN(ConfigBits_N[175])
+	);
+
+	LHQD1 Inst_frame7_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[174]),
+	.QN(ConfigBits_N[174])
+	);
+
+	LHQD1 Inst_frame7_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[173]),
+	.QN(ConfigBits_N[173])
+	);
+
+	LHQD1 Inst_frame7_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[172]),
+	.QN(ConfigBits_N[172])
+	);
+
+	LHQD1 Inst_frame7_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[171]),
+	.QN(ConfigBits_N[171])
+	);
+
+	LHQD1 Inst_frame7_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[170]),
+	.QN(ConfigBits_N[170])
+	);
+
+	LHQD1 Inst_frame7_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[169]),
+	.QN(ConfigBits_N[169])
+	);
+
+	LHQD1 Inst_frame7_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[168]),
+	.QN(ConfigBits_N[168])
+	);
+
+	LHQD1 Inst_frame7_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[167]),
+	.QN(ConfigBits_N[167])
+	);
+
+	LHQD1 Inst_frame7_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[166]),
+	.QN(ConfigBits_N[166])
+	);
+
+	LHQD1 Inst_frame7_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[165]),
+	.QN(ConfigBits_N[165])
+	);
+
+	LHQD1 Inst_frame7_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[164]),
+	.QN(ConfigBits_N[164])
+	);
+
+	LHQD1 Inst_frame7_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[163]),
+	.QN(ConfigBits_N[163])
+	);
+
+	LHQD1 Inst_frame7_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[162]),
+	.QN(ConfigBits_N[162])
+	);
+
+	LHQD1 Inst_frame7_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[161]),
+	.QN(ConfigBits_N[161])
+	);
+
+	LHQD1 Inst_frame7_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[160]),
+	.QN(ConfigBits_N[160])
+	);
+
+	LHQD1 Inst_frame8_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[159]),
+	.QN(ConfigBits_N[159])
+	);
+
+	LHQD1 Inst_frame8_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[158]),
+	.QN(ConfigBits_N[158])
+	);
+
+	LHQD1 Inst_frame8_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[157]),
+	.QN(ConfigBits_N[157])
+	);
+
+	LHQD1 Inst_frame8_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[156]),
+	.QN(ConfigBits_N[156])
+	);
+
+	LHQD1 Inst_frame8_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[155]),
+	.QN(ConfigBits_N[155])
+	);
+
+	LHQD1 Inst_frame8_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[154]),
+	.QN(ConfigBits_N[154])
+	);
+
+	LHQD1 Inst_frame8_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[153]),
+	.QN(ConfigBits_N[153])
+	);
+
+	LHQD1 Inst_frame8_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[152]),
+	.QN(ConfigBits_N[152])
+	);
+
+	LHQD1 Inst_frame8_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[151]),
+	.QN(ConfigBits_N[151])
+	);
+
+	LHQD1 Inst_frame8_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[150]),
+	.QN(ConfigBits_N[150])
+	);
+
+	LHQD1 Inst_frame8_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[149]),
+	.QN(ConfigBits_N[149])
+	);
+
+	LHQD1 Inst_frame8_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[148]),
+	.QN(ConfigBits_N[148])
+	);
+
+	LHQD1 Inst_frame8_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[147]),
+	.QN(ConfigBits_N[147])
+	);
+
+	LHQD1 Inst_frame8_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[146]),
+	.QN(ConfigBits_N[146])
+	);
+
+	LHQD1 Inst_frame8_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[145]),
+	.QN(ConfigBits_N[145])
+	);
+
+	LHQD1 Inst_frame8_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[144]),
+	.QN(ConfigBits_N[144])
+	);
+
+	LHQD1 Inst_frame8_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[143]),
+	.QN(ConfigBits_N[143])
+	);
+
+	LHQD1 Inst_frame8_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[142]),
+	.QN(ConfigBits_N[142])
+	);
+
+	LHQD1 Inst_frame8_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[141]),
+	.QN(ConfigBits_N[141])
+	);
+
+	LHQD1 Inst_frame8_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[140]),
+	.QN(ConfigBits_N[140])
+	);
+
+	LHQD1 Inst_frame8_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[139]),
+	.QN(ConfigBits_N[139])
+	);
+
+	LHQD1 Inst_frame8_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[138]),
+	.QN(ConfigBits_N[138])
+	);
+
+	LHQD1 Inst_frame8_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[137]),
+	.QN(ConfigBits_N[137])
+	);
+
+	LHQD1 Inst_frame8_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[136]),
+	.QN(ConfigBits_N[136])
+	);
+
+	LHQD1 Inst_frame8_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[135]),
+	.QN(ConfigBits_N[135])
+	);
+
+	LHQD1 Inst_frame8_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[134]),
+	.QN(ConfigBits_N[134])
+	);
+
+	LHQD1 Inst_frame8_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[133]),
+	.QN(ConfigBits_N[133])
+	);
+
+	LHQD1 Inst_frame8_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[132]),
+	.QN(ConfigBits_N[132])
+	);
+
+	LHQD1 Inst_frame8_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[131]),
+	.QN(ConfigBits_N[131])
+	);
+
+	LHQD1 Inst_frame8_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[130]),
+	.QN(ConfigBits_N[130])
+	);
+
+	LHQD1 Inst_frame8_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[129]),
+	.QN(ConfigBits_N[129])
+	);
+
+	LHQD1 Inst_frame8_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[128]),
+	.QN(ConfigBits_N[128])
+	);
+
+	LHQD1 Inst_frame9_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[127]),
+	.QN(ConfigBits_N[127])
+	);
+
+	LHQD1 Inst_frame9_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[126]),
+	.QN(ConfigBits_N[126])
+	);
+
+	LHQD1 Inst_frame9_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[125]),
+	.QN(ConfigBits_N[125])
+	);
+
+	LHQD1 Inst_frame9_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[124]),
+	.QN(ConfigBits_N[124])
+	);
+
+	LHQD1 Inst_frame9_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[123]),
+	.QN(ConfigBits_N[123])
+	);
+
+	LHQD1 Inst_frame9_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[122]),
+	.QN(ConfigBits_N[122])
+	);
+
+	LHQD1 Inst_frame9_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[121]),
+	.QN(ConfigBits_N[121])
+	);
+
+	LHQD1 Inst_frame9_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[120]),
+	.QN(ConfigBits_N[120])
+	);
+
+	LHQD1 Inst_frame9_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[119]),
+	.QN(ConfigBits_N[119])
+	);
+
+	LHQD1 Inst_frame9_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[118]),
+	.QN(ConfigBits_N[118])
+	);
+
+	LHQD1 Inst_frame9_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[117]),
+	.QN(ConfigBits_N[117])
+	);
+
+	LHQD1 Inst_frame9_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[116]),
+	.QN(ConfigBits_N[116])
+	);
+
+	LHQD1 Inst_frame9_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[115]),
+	.QN(ConfigBits_N[115])
+	);
+
+	LHQD1 Inst_frame9_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[114]),
+	.QN(ConfigBits_N[114])
+	);
+
+	LHQD1 Inst_frame9_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_frame9_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_frame9_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_frame9_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_frame9_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_frame9_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_frame9_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_frame9_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_frame9_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_frame9_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_frame9_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_frame9_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_frame9_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_frame9_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_frame9_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_frame9_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_frame9_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_frame9_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_frame10_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_frame10_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_frame10_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_frame10_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_frame10_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_frame10_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_frame10_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_frame10_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_frame10_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_frame10_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_frame10_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_frame10_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_frame10_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_frame10_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_frame10_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_frame10_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_frame10_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_frame10_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_frame10_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_frame10_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_frame10_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_frame10_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_frame10_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_frame10_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_frame10_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_frame10_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_frame10_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_frame10_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_frame10_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_frame10_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_frame10_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_frame10_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_frame11_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_frame11_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_frame11_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_frame11_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_frame11_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_frame11_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_frame11_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_frame11_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_frame11_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_frame11_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_frame11_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_frame11_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_frame11_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_frame11_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_frame11_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_frame11_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_frame11_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_frame11_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_frame11_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_frame11_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_frame11_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_frame11_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_frame11_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_frame11_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_frame11_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_frame11_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_frame11_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_frame11_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_frame11_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_frame11_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_frame11_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_frame11_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_frame12_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_frame12_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_frame12_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_frame12_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_frame12_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_frame12_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_frame12_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_frame12_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_frame12_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_frame12_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_frame12_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_frame12_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_frame12_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame12_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame12_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame12_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame12_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame12_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame12_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame12_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame12_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame12_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame12_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame12_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame12_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame12_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame12_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame12_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame12_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame12_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame12_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame12_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_bot_switch_matrix.v b/verilog/rtl/eFPGA_core/DSP_bot_switch_matrix.v
new file mode 100644
index 0000000..26f4e78
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_bot_switch_matrix.v
@@ -0,0 +1,4210 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:410
+module DSP_bot_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, NN4END0, NN4END1, NN4END2, NN4END3, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, E6END0, E6END1, S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, SS4END0, SS4END1, SS4END2, SS4END3, top2bot0, top2bot1, top2bot2, top2bot3, top2bot4, top2bot5, top2bot6, top2bot7, top2bot8, top2bot9, top2bot10, top2bot11, top2bot12, top2bot13, top2bot14, top2bot15, top2bot16, top2bot17, W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, W6END0, W6END1, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, J2MID_ABa_END0, J2MID_ABa_END1, J2MID_ABa_END2, J2MID_ABa_END3, J2MID_CDa_END0, J2MID_CDa_END1, J2MID_CDa_END2, J2MID_CDa_END3, J2MID_EFa_END0, J2MID_EFa_END1, J2MID_EFa_END2, J2MID_EFa_END3, J2MID_GHa_END0, J2MID_GHa_END1, J2MID_GHa_END2, J2MID_GHa_END3, J2MID_ABb_END0, J2MID_ABb_END1, J2MID_ABb_END2, J2MID_ABb_END3, J2MID_CDb_END0, J2MID_CDb_END1, J2MID_CDb_END2, J2MID_CDb_END3, J2MID_EFb_END0, J2MID_EFb_END1, J2MID_EFb_END2, J2MID_EFb_END3, J2MID_GHb_END0, J2MID_GHb_END1, J2MID_GHb_END2, J2MID_GHb_END3, J2END_AB_END0, J2END_AB_END1, J2END_AB_END2, J2END_AB_END3, J2END_CD_END0, J2END_CD_END1, J2END_CD_END2, J2END_CD_END3, J2END_EF_END0, J2END_EF_END1, J2END_EF_END2, J2END_EF_END3, J2END_GH_END0, J2END_GH_END1, J2END_GH_END2, J2END_GH_END3, JN2END0, JN2END1, JN2END2, JN2END3, JN2END4, JN2END5, JN2END6, JN2END7, JE2END0, JE2END1, JE2END2, JE2END3, JE2END4, JE2END5, JE2END6, JE2END7, JS2END0, JS2END1, JS2END2, JS2END3, JS2END4, JS2END5, JS2END6, JS2END7, JW2END0, JW2END1, JW2END2, JW2END3, JW2END4, JW2END5, JW2END6, JW2END7, J_l_AB_END0, J_l_AB_END1, J_l_AB_END2, J_l_AB_END3, J_l_CD_END0, J_l_CD_END1, J_l_CD_END2, J_l_CD_END3, J_l_EF_END0, J_l_EF_END1, J_l_EF_END2, J_l_EF_END3, J_l_GH_END0, J_l_GH_END1, J_l_GH_END2, J_l_GH_END3, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, bot2top0, bot2top1, bot2top2, bot2top3, bot2top4, bot2top5, bot2top6, bot2top7, bot2top8, bot2top9, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, E6BEG0, E6BEG1, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, W6BEG0, W6BEG1, A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, clr, J2MID_ABa_BEG0, J2MID_ABa_BEG1, J2MID_ABa_BEG2, J2MID_ABa_BEG3, J2MID_CDa_BEG0, J2MID_CDa_BEG1, J2MID_CDa_BEG2, J2MID_CDa_BEG3, J2MID_EFa_BEG0, J2MID_EFa_BEG1, J2MID_EFa_BEG2, J2MID_EFa_BEG3, J2MID_GHa_BEG0, J2MID_GHa_BEG1, J2MID_GHa_BEG2, J2MID_GHa_BEG3, J2MID_ABb_BEG0, J2MID_ABb_BEG1, J2MID_ABb_BEG2, J2MID_ABb_BEG3, J2MID_CDb_BEG0, J2MID_CDb_BEG1, J2MID_CDb_BEG2, J2MID_CDb_BEG3, J2MID_EFb_BEG0, J2MID_EFb_BEG1, J2MID_EFb_BEG2, J2MID_EFb_BEG3, J2MID_GHb_BEG0, J2MID_GHb_BEG1, J2MID_GHb_BEG2, J2MID_GHb_BEG3, J2END_AB_BEG0, J2END_AB_BEG1, J2END_AB_BEG2, J2END_AB_BEG3, J2END_CD_BEG0, J2END_CD_BEG1, J2END_CD_BEG2, J2END_CD_BEG3, J2END_EF_BEG0, J2END_EF_BEG1, J2END_EF_BEG2, J2END_EF_BEG3, J2END_GH_BEG0, J2END_GH_BEG1, J2END_GH_BEG2, J2END_GH_BEG3, JN2BEG0, JN2BEG1, JN2BEG2, JN2BEG3, JN2BEG4, JN2BEG5, JN2BEG6, JN2BEG7, JE2BEG0, JE2BEG1, JE2BEG2, JE2BEG3, JE2BEG4, JE2BEG5, JE2BEG6, JE2BEG7, JS2BEG0, JS2BEG1, JS2BEG2, JS2BEG3, JS2BEG4, JS2BEG5, JS2BEG6, JS2BEG7, JW2BEG0, JW2BEG1, JW2BEG2, JW2BEG3, JW2BEG4, JW2BEG5, JW2BEG6, JW2BEG7, J_l_AB_BEG0, J_l_AB_BEG1, J_l_AB_BEG2, J_l_AB_BEG3, J_l_CD_BEG0, J_l_CD_BEG1, J_l_CD_BEG2, J_l_CD_BEG3, J_l_EF_BEG0, J_l_EF_BEG1, J_l_EF_BEG2, J_l_EF_BEG3, J_l_GH_BEG0, J_l_GH_BEG1, J_l_GH_BEG2, J_l_GH_BEG3, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 410;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input E6END0;
+	input E6END1;
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input top2bot0;
+	input top2bot1;
+	input top2bot2;
+	input top2bot3;
+	input top2bot4;
+	input top2bot5;
+	input top2bot6;
+	input top2bot7;
+	input top2bot8;
+	input top2bot9;
+	input top2bot10;
+	input top2bot11;
+	input top2bot12;
+	input top2bot13;
+	input top2bot14;
+	input top2bot15;
+	input top2bot16;
+	input top2bot17;
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input W6END0;
+	input W6END1;
+	input Q19;
+	input Q18;
+	input Q17;
+	input Q16;
+	input Q15;
+	input Q14;
+	input Q13;
+	input Q12;
+	input Q11;
+	input Q10;
+	input Q9;
+	input Q8;
+	input Q7;
+	input Q6;
+	input Q5;
+	input Q4;
+	input Q3;
+	input Q2;
+	input Q1;
+	input Q0;
+	input J2MID_ABa_END0;
+	input J2MID_ABa_END1;
+	input J2MID_ABa_END2;
+	input J2MID_ABa_END3;
+	input J2MID_CDa_END0;
+	input J2MID_CDa_END1;
+	input J2MID_CDa_END2;
+	input J2MID_CDa_END3;
+	input J2MID_EFa_END0;
+	input J2MID_EFa_END1;
+	input J2MID_EFa_END2;
+	input J2MID_EFa_END3;
+	input J2MID_GHa_END0;
+	input J2MID_GHa_END1;
+	input J2MID_GHa_END2;
+	input J2MID_GHa_END3;
+	input J2MID_ABb_END0;
+	input J2MID_ABb_END1;
+	input J2MID_ABb_END2;
+	input J2MID_ABb_END3;
+	input J2MID_CDb_END0;
+	input J2MID_CDb_END1;
+	input J2MID_CDb_END2;
+	input J2MID_CDb_END3;
+	input J2MID_EFb_END0;
+	input J2MID_EFb_END1;
+	input J2MID_EFb_END2;
+	input J2MID_EFb_END3;
+	input J2MID_GHb_END0;
+	input J2MID_GHb_END1;
+	input J2MID_GHb_END2;
+	input J2MID_GHb_END3;
+	input J2END_AB_END0;
+	input J2END_AB_END1;
+	input J2END_AB_END2;
+	input J2END_AB_END3;
+	input J2END_CD_END0;
+	input J2END_CD_END1;
+	input J2END_CD_END2;
+	input J2END_CD_END3;
+	input J2END_EF_END0;
+	input J2END_EF_END1;
+	input J2END_EF_END2;
+	input J2END_EF_END3;
+	input J2END_GH_END0;
+	input J2END_GH_END1;
+	input J2END_GH_END2;
+	input J2END_GH_END3;
+	input JN2END0;
+	input JN2END1;
+	input JN2END2;
+	input JN2END3;
+	input JN2END4;
+	input JN2END5;
+	input JN2END6;
+	input JN2END7;
+	input JE2END0;
+	input JE2END1;
+	input JE2END2;
+	input JE2END3;
+	input JE2END4;
+	input JE2END5;
+	input JE2END6;
+	input JE2END7;
+	input JS2END0;
+	input JS2END1;
+	input JS2END2;
+	input JS2END3;
+	input JS2END4;
+	input JS2END5;
+	input JS2END6;
+	input JS2END7;
+	input JW2END0;
+	input JW2END1;
+	input JW2END2;
+	input JW2END3;
+	input JW2END4;
+	input JW2END5;
+	input JW2END6;
+	input JW2END7;
+	input J_l_AB_END0;
+	input J_l_AB_END1;
+	input J_l_AB_END2;
+	input J_l_AB_END3;
+	input J_l_CD_END0;
+	input J_l_CD_END1;
+	input J_l_CD_END2;
+	input J_l_CD_END3;
+	input J_l_EF_END0;
+	input J_l_EF_END1;
+	input J_l_EF_END2;
+	input J_l_EF_END3;
+	input J_l_GH_END0;
+	input J_l_GH_END1;
+	input J_l_GH_END2;
+	input J_l_GH_END3;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output bot2top0;
+	output bot2top1;
+	output bot2top2;
+	output bot2top3;
+	output bot2top4;
+	output bot2top5;
+	output bot2top6;
+	output bot2top7;
+	output bot2top8;
+	output bot2top9;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output E6BEG0;
+	output E6BEG1;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output W6BEG0;
+	output W6BEG1;
+	output A7;
+	output A6;
+	output A5;
+	output A4;
+	output A3;
+	output A2;
+	output A1;
+	output A0;
+	output B7;
+	output B6;
+	output B5;
+	output B4;
+	output B3;
+	output B2;
+	output B1;
+	output B0;
+	output C19;
+	output C18;
+	output C17;
+	output C16;
+	output C15;
+	output C14;
+	output C13;
+	output C12;
+	output C11;
+	output C10;
+	output C9;
+	output C8;
+	output C7;
+	output C6;
+	output C5;
+	output C4;
+	output C3;
+	output C2;
+	output C1;
+	output C0;
+	output clr;
+	output J2MID_ABa_BEG0;
+	output J2MID_ABa_BEG1;
+	output J2MID_ABa_BEG2;
+	output J2MID_ABa_BEG3;
+	output J2MID_CDa_BEG0;
+	output J2MID_CDa_BEG1;
+	output J2MID_CDa_BEG2;
+	output J2MID_CDa_BEG3;
+	output J2MID_EFa_BEG0;
+	output J2MID_EFa_BEG1;
+	output J2MID_EFa_BEG2;
+	output J2MID_EFa_BEG3;
+	output J2MID_GHa_BEG0;
+	output J2MID_GHa_BEG1;
+	output J2MID_GHa_BEG2;
+	output J2MID_GHa_BEG3;
+	output J2MID_ABb_BEG0;
+	output J2MID_ABb_BEG1;
+	output J2MID_ABb_BEG2;
+	output J2MID_ABb_BEG3;
+	output J2MID_CDb_BEG0;
+	output J2MID_CDb_BEG1;
+	output J2MID_CDb_BEG2;
+	output J2MID_CDb_BEG3;
+	output J2MID_EFb_BEG0;
+	output J2MID_EFb_BEG1;
+	output J2MID_EFb_BEG2;
+	output J2MID_EFb_BEG3;
+	output J2MID_GHb_BEG0;
+	output J2MID_GHb_BEG1;
+	output J2MID_GHb_BEG2;
+	output J2MID_GHb_BEG3;
+	output J2END_AB_BEG0;
+	output J2END_AB_BEG1;
+	output J2END_AB_BEG2;
+	output J2END_AB_BEG3;
+	output J2END_CD_BEG0;
+	output J2END_CD_BEG1;
+	output J2END_CD_BEG2;
+	output J2END_CD_BEG3;
+	output J2END_EF_BEG0;
+	output J2END_EF_BEG1;
+	output J2END_EF_BEG2;
+	output J2END_EF_BEG3;
+	output J2END_GH_BEG0;
+	output J2END_GH_BEG1;
+	output J2END_GH_BEG2;
+	output J2END_GH_BEG3;
+	output JN2BEG0;
+	output JN2BEG1;
+	output JN2BEG2;
+	output JN2BEG3;
+	output JN2BEG4;
+	output JN2BEG5;
+	output JN2BEG6;
+	output JN2BEG7;
+	output JE2BEG0;
+	output JE2BEG1;
+	output JE2BEG2;
+	output JE2BEG3;
+	output JE2BEG4;
+	output JE2BEG5;
+	output JE2BEG6;
+	output JE2BEG7;
+	output JS2BEG0;
+	output JS2BEG1;
+	output JS2BEG2;
+	output JS2BEG3;
+	output JS2BEG4;
+	output JS2BEG5;
+	output JS2BEG6;
+	output JS2BEG7;
+	output JW2BEG0;
+	output JW2BEG1;
+	output JW2BEG2;
+	output JW2BEG3;
+	output JW2BEG4;
+	output JW2BEG5;
+	output JW2BEG6;
+	output JW2BEG7;
+	output J_l_AB_BEG0;
+	output J_l_AB_BEG1;
+	output J_l_AB_BEG2;
+	output J_l_AB_BEG3;
+	output J_l_CD_BEG0;
+	output J_l_CD_BEG1;
+	output J_l_CD_BEG2;
+	output J_l_CD_BEG3;
+	output J_l_EF_BEG0;
+	output J_l_EF_BEG1;
+	output J_l_EF_BEG2;
+	output J_l_EF_BEG3;
+	output J_l_GH_BEG0;
+	output J_l_GH_BEG1;
+	output J_l_GH_BEG2;
+	output J_l_GH_BEG3;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [4-1:0] N1BEG0_input;
+	wire [4-1:0] N1BEG1_input;
+	wire [4-1:0] N1BEG2_input;
+	wire [4-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [4-1:0] N4BEG0_input;
+	wire [4-1:0] N4BEG1_input;
+	wire [4-1:0] N4BEG2_input;
+	wire [4-1:0] N4BEG3_input;
+	wire [8-1:0] NN4BEG0_input;
+	wire [8-1:0] NN4BEG1_input;
+	wire [8-1:0] NN4BEG2_input;
+	wire [8-1:0] NN4BEG3_input;
+	wire [1-1:0] bot2top0_input;
+	wire [1-1:0] bot2top1_input;
+	wire [1-1:0] bot2top2_input;
+	wire [1-1:0] bot2top3_input;
+	wire [1-1:0] bot2top4_input;
+	wire [1-1:0] bot2top5_input;
+	wire [1-1:0] bot2top6_input;
+	wire [1-1:0] bot2top7_input;
+	wire [1-1:0] bot2top8_input;
+	wire [1-1:0] bot2top9_input;
+	wire [4-1:0] E1BEG0_input;
+	wire [4-1:0] E1BEG1_input;
+	wire [4-1:0] E1BEG2_input;
+	wire [4-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [8-1:0] EE4BEG0_input;
+	wire [8-1:0] EE4BEG1_input;
+	wire [8-1:0] EE4BEG2_input;
+	wire [8-1:0] EE4BEG3_input;
+	wire [16-1:0] E6BEG0_input;
+	wire [16-1:0] E6BEG1_input;
+	wire [4-1:0] S1BEG0_input;
+	wire [4-1:0] S1BEG1_input;
+	wire [4-1:0] S1BEG2_input;
+	wire [4-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [4-1:0] S4BEG0_input;
+	wire [4-1:0] S4BEG1_input;
+	wire [4-1:0] S4BEG2_input;
+	wire [4-1:0] S4BEG3_input;
+	wire [8-1:0] SS4BEG0_input;
+	wire [8-1:0] SS4BEG1_input;
+	wire [8-1:0] SS4BEG2_input;
+	wire [8-1:0] SS4BEG3_input;
+	wire [4-1:0] W1BEG0_input;
+	wire [4-1:0] W1BEG1_input;
+	wire [4-1:0] W1BEG2_input;
+	wire [4-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [8-1:0] WW4BEG0_input;
+	wire [8-1:0] WW4BEG1_input;
+	wire [8-1:0] WW4BEG2_input;
+	wire [8-1:0] WW4BEG3_input;
+	wire [16-1:0] W6BEG0_input;
+	wire [16-1:0] W6BEG1_input;
+	wire [1-1:0] A7_input;
+	wire [1-1:0] A6_input;
+	wire [1-1:0] A5_input;
+	wire [1-1:0] A4_input;
+	wire [4-1:0] A3_input;
+	wire [4-1:0] A2_input;
+	wire [4-1:0] A1_input;
+	wire [4-1:0] A0_input;
+	wire [1-1:0] B7_input;
+	wire [1-1:0] B6_input;
+	wire [1-1:0] B5_input;
+	wire [1-1:0] B4_input;
+	wire [4-1:0] B3_input;
+	wire [4-1:0] B2_input;
+	wire [4-1:0] B1_input;
+	wire [4-1:0] B0_input;
+	wire [1-1:0] C19_input;
+	wire [1-1:0] C18_input;
+	wire [1-1:0] C17_input;
+	wire [1-1:0] C16_input;
+	wire [1-1:0] C15_input;
+	wire [1-1:0] C14_input;
+	wire [1-1:0] C13_input;
+	wire [1-1:0] C12_input;
+	wire [1-1:0] C11_input;
+	wire [1-1:0] C10_input;
+	wire [8-1:0] C9_input;
+	wire [8-1:0] C8_input;
+	wire [4-1:0] C7_input;
+	wire [4-1:0] C6_input;
+	wire [4-1:0] C5_input;
+	wire [4-1:0] C4_input;
+	wire [4-1:0] C3_input;
+	wire [4-1:0] C2_input;
+	wire [4-1:0] C1_input;
+	wire [4-1:0] C0_input;
+	wire [16-1:0] clr_input;
+	wire [4-1:0] J2MID_ABa_BEG0_input;
+	wire [4-1:0] J2MID_ABa_BEG1_input;
+	wire [4-1:0] J2MID_ABa_BEG2_input;
+	wire [4-1:0] J2MID_ABa_BEG3_input;
+	wire [4-1:0] J2MID_CDa_BEG0_input;
+	wire [4-1:0] J2MID_CDa_BEG1_input;
+	wire [4-1:0] J2MID_CDa_BEG2_input;
+	wire [4-1:0] J2MID_CDa_BEG3_input;
+	wire [4-1:0] J2MID_EFa_BEG0_input;
+	wire [4-1:0] J2MID_EFa_BEG1_input;
+	wire [4-1:0] J2MID_EFa_BEG2_input;
+	wire [4-1:0] J2MID_EFa_BEG3_input;
+	wire [4-1:0] J2MID_GHa_BEG0_input;
+	wire [4-1:0] J2MID_GHa_BEG1_input;
+	wire [4-1:0] J2MID_GHa_BEG2_input;
+	wire [4-1:0] J2MID_GHa_BEG3_input;
+	wire [4-1:0] J2MID_ABb_BEG0_input;
+	wire [4-1:0] J2MID_ABb_BEG1_input;
+	wire [4-1:0] J2MID_ABb_BEG2_input;
+	wire [4-1:0] J2MID_ABb_BEG3_input;
+	wire [4-1:0] J2MID_CDb_BEG0_input;
+	wire [4-1:0] J2MID_CDb_BEG1_input;
+	wire [4-1:0] J2MID_CDb_BEG2_input;
+	wire [4-1:0] J2MID_CDb_BEG3_input;
+	wire [4-1:0] J2MID_EFb_BEG0_input;
+	wire [4-1:0] J2MID_EFb_BEG1_input;
+	wire [4-1:0] J2MID_EFb_BEG2_input;
+	wire [4-1:0] J2MID_EFb_BEG3_input;
+	wire [4-1:0] J2MID_GHb_BEG0_input;
+	wire [4-1:0] J2MID_GHb_BEG1_input;
+	wire [4-1:0] J2MID_GHb_BEG2_input;
+	wire [4-1:0] J2MID_GHb_BEG3_input;
+	wire [4-1:0] J2END_AB_BEG0_input;
+	wire [4-1:0] J2END_AB_BEG1_input;
+	wire [4-1:0] J2END_AB_BEG2_input;
+	wire [4-1:0] J2END_AB_BEG3_input;
+	wire [4-1:0] J2END_CD_BEG0_input;
+	wire [4-1:0] J2END_CD_BEG1_input;
+	wire [4-1:0] J2END_CD_BEG2_input;
+	wire [4-1:0] J2END_CD_BEG3_input;
+	wire [4-1:0] J2END_EF_BEG0_input;
+	wire [4-1:0] J2END_EF_BEG1_input;
+	wire [4-1:0] J2END_EF_BEG2_input;
+	wire [4-1:0] J2END_EF_BEG3_input;
+	wire [4-1:0] J2END_GH_BEG0_input;
+	wire [4-1:0] J2END_GH_BEG1_input;
+	wire [4-1:0] J2END_GH_BEG2_input;
+	wire [4-1:0] J2END_GH_BEG3_input;
+	wire [16-1:0] JN2BEG0_input;
+	wire [16-1:0] JN2BEG1_input;
+	wire [16-1:0] JN2BEG2_input;
+	wire [16-1:0] JN2BEG3_input;
+	wire [16-1:0] JN2BEG4_input;
+	wire [16-1:0] JN2BEG5_input;
+	wire [16-1:0] JN2BEG6_input;
+	wire [16-1:0] JN2BEG7_input;
+	wire [16-1:0] JE2BEG0_input;
+	wire [16-1:0] JE2BEG1_input;
+	wire [16-1:0] JE2BEG2_input;
+	wire [16-1:0] JE2BEG3_input;
+	wire [16-1:0] JE2BEG4_input;
+	wire [16-1:0] JE2BEG5_input;
+	wire [16-1:0] JE2BEG6_input;
+	wire [16-1:0] JE2BEG7_input;
+	wire [16-1:0] JS2BEG0_input;
+	wire [16-1:0] JS2BEG1_input;
+	wire [16-1:0] JS2BEG2_input;
+	wire [16-1:0] JS2BEG3_input;
+	wire [16-1:0] JS2BEG4_input;
+	wire [16-1:0] JS2BEG5_input;
+	wire [16-1:0] JS2BEG6_input;
+	wire [16-1:0] JS2BEG7_input;
+	wire [16-1:0] JW2BEG0_input;
+	wire [16-1:0] JW2BEG1_input;
+	wire [16-1:0] JW2BEG2_input;
+	wire [16-1:0] JW2BEG3_input;
+	wire [16-1:0] JW2BEG4_input;
+	wire [16-1:0] JW2BEG5_input;
+	wire [16-1:0] JW2BEG6_input;
+	wire [16-1:0] JW2BEG7_input;
+	wire [4-1:0] J_l_AB_BEG0_input;
+	wire [4-1:0] J_l_AB_BEG1_input;
+	wire [4-1:0] J_l_AB_BEG2_input;
+	wire [4-1:0] J_l_AB_BEG3_input;
+	wire [4-1:0] J_l_CD_BEG0_input;
+	wire [4-1:0] J_l_CD_BEG1_input;
+	wire [4-1:0] J_l_CD_BEG2_input;
+	wire [4-1:0] J_l_CD_BEG3_input;
+	wire [4-1:0] J_l_EF_BEG0_input;
+	wire [4-1:0] J_l_EF_BEG1_input;
+	wire [4-1:0] J_l_EF_BEG2_input;
+	wire [4-1:0] J_l_EF_BEG3_input;
+	wire [4-1:0] J_l_GH_BEG0_input;
+	wire [4-1:0] J_l_GH_BEG1_input;
+	wire [4-1:0] J_l_GH_BEG2_input;
+	wire [4-1:0] J_l_GH_BEG3_input;
+
+	wire [2-1:0] DEBUG_select_N1BEG0;
+	wire [2-1:0] DEBUG_select_N1BEG1;
+	wire [2-1:0] DEBUG_select_N1BEG2;
+	wire [2-1:0] DEBUG_select_N1BEG3;
+	wire [2-1:0] DEBUG_select_N4BEG0;
+	wire [2-1:0] DEBUG_select_N4BEG1;
+	wire [2-1:0] DEBUG_select_N4BEG2;
+	wire [2-1:0] DEBUG_select_N4BEG3;
+	wire [3-1:0] DEBUG_select_NN4BEG0;
+	wire [3-1:0] DEBUG_select_NN4BEG1;
+	wire [3-1:0] DEBUG_select_NN4BEG2;
+	wire [3-1:0] DEBUG_select_NN4BEG3;
+	wire [2-1:0] DEBUG_select_E1BEG0;
+	wire [2-1:0] DEBUG_select_E1BEG1;
+	wire [2-1:0] DEBUG_select_E1BEG2;
+	wire [2-1:0] DEBUG_select_E1BEG3;
+	wire [3-1:0] DEBUG_select_EE4BEG0;
+	wire [3-1:0] DEBUG_select_EE4BEG1;
+	wire [3-1:0] DEBUG_select_EE4BEG2;
+	wire [3-1:0] DEBUG_select_EE4BEG3;
+	wire [4-1:0] DEBUG_select_E6BEG0;
+	wire [4-1:0] DEBUG_select_E6BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG0;
+	wire [2-1:0] DEBUG_select_S1BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG2;
+	wire [2-1:0] DEBUG_select_S1BEG3;
+	wire [2-1:0] DEBUG_select_S4BEG0;
+	wire [2-1:0] DEBUG_select_S4BEG1;
+	wire [2-1:0] DEBUG_select_S4BEG2;
+	wire [2-1:0] DEBUG_select_S4BEG3;
+	wire [3-1:0] DEBUG_select_SS4BEG0;
+	wire [3-1:0] DEBUG_select_SS4BEG1;
+	wire [3-1:0] DEBUG_select_SS4BEG2;
+	wire [3-1:0] DEBUG_select_SS4BEG3;
+	wire [2-1:0] DEBUG_select_W1BEG0;
+	wire [2-1:0] DEBUG_select_W1BEG1;
+	wire [2-1:0] DEBUG_select_W1BEG2;
+	wire [2-1:0] DEBUG_select_W1BEG3;
+	wire [3-1:0] DEBUG_select_WW4BEG0;
+	wire [3-1:0] DEBUG_select_WW4BEG1;
+	wire [3-1:0] DEBUG_select_WW4BEG2;
+	wire [3-1:0] DEBUG_select_WW4BEG3;
+	wire [4-1:0] DEBUG_select_W6BEG0;
+	wire [4-1:0] DEBUG_select_W6BEG1;
+	wire [2-1:0] DEBUG_select_A3;
+	wire [2-1:0] DEBUG_select_A2;
+	wire [2-1:0] DEBUG_select_A1;
+	wire [2-1:0] DEBUG_select_A0;
+	wire [2-1:0] DEBUG_select_B3;
+	wire [2-1:0] DEBUG_select_B2;
+	wire [2-1:0] DEBUG_select_B1;
+	wire [2-1:0] DEBUG_select_B0;
+	wire [3-1:0] DEBUG_select_C9;
+	wire [3-1:0] DEBUG_select_C8;
+	wire [2-1:0] DEBUG_select_C7;
+	wire [2-1:0] DEBUG_select_C6;
+	wire [2-1:0] DEBUG_select_C5;
+	wire [2-1:0] DEBUG_select_C4;
+	wire [2-1:0] DEBUG_select_C3;
+	wire [2-1:0] DEBUG_select_C2;
+	wire [2-1:0] DEBUG_select_C1;
+	wire [2-1:0] DEBUG_select_C0;
+	wire [4-1:0] DEBUG_select_clr;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG0;
+	wire [4-1:0] DEBUG_select_JN2BEG1;
+	wire [4-1:0] DEBUG_select_JN2BEG2;
+	wire [4-1:0] DEBUG_select_JN2BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG4;
+	wire [4-1:0] DEBUG_select_JN2BEG5;
+	wire [4-1:0] DEBUG_select_JN2BEG6;
+	wire [4-1:0] DEBUG_select_JN2BEG7;
+	wire [4-1:0] DEBUG_select_JE2BEG0;
+	wire [4-1:0] DEBUG_select_JE2BEG1;
+	wire [4-1:0] DEBUG_select_JE2BEG2;
+	wire [4-1:0] DEBUG_select_JE2BEG3;
+	wire [4-1:0] DEBUG_select_JE2BEG4;
+	wire [4-1:0] DEBUG_select_JE2BEG5;
+	wire [4-1:0] DEBUG_select_JE2BEG6;
+	wire [4-1:0] DEBUG_select_JE2BEG7;
+	wire [4-1:0] DEBUG_select_JS2BEG0;
+	wire [4-1:0] DEBUG_select_JS2BEG1;
+	wire [4-1:0] DEBUG_select_JS2BEG2;
+	wire [4-1:0] DEBUG_select_JS2BEG3;
+	wire [4-1:0] DEBUG_select_JS2BEG4;
+	wire [4-1:0] DEBUG_select_JS2BEG5;
+	wire [4-1:0] DEBUG_select_JS2BEG6;
+	wire [4-1:0] DEBUG_select_JS2BEG7;
+	wire [4-1:0] DEBUG_select_JW2BEG0;
+	wire [4-1:0] DEBUG_select_JW2BEG1;
+	wire [4-1:0] DEBUG_select_JW2BEG2;
+	wire [4-1:0] DEBUG_select_JW2BEG3;
+	wire [4-1:0] DEBUG_select_JW2BEG4;
+	wire [4-1:0] DEBUG_select_JW2BEG5;
+	wire [4-1:0] DEBUG_select_JW2BEG6;
+	wire [4-1:0] DEBUG_select_JW2BEG7;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG3;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-4
+	assign N1BEG0_input = {J_l_CD_END1,JW2END3,J2MID_CDb_END3,Q2};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG0 (
+	.A0 (N1BEG0_input[0]),
+	.A1 (N1BEG0_input[1]),
+	.A2 (N1BEG0_input[2]),
+	.A3 (N1BEG0_input[3]),
+	.S0 (ConfigBits[0+0]),
+	.S0N (ConfigBits_N[0+0]),
+	.S1 (ConfigBits[0+1]),
+	.S1N (ConfigBits_N[0+1]),
+	.X (N1BEG0)
+	);
+
+// switch matrix multiplexer  N1BEG1 		MUX-4
+	assign N1BEG1_input = {J_l_EF_END2,JW2END0,J2MID_EFb_END0,Q3};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG1 (
+	.A0 (N1BEG1_input[0]),
+	.A1 (N1BEG1_input[1]),
+	.A2 (N1BEG1_input[2]),
+	.A3 (N1BEG1_input[3]),
+	.S0 (ConfigBits[2+0]),
+	.S0N (ConfigBits_N[2+0]),
+	.S1 (ConfigBits[2+1]),
+	.S1N (ConfigBits_N[2+1]),
+	.X (N1BEG1)
+	);
+
+// switch matrix multiplexer  N1BEG2 		MUX-4
+	assign N1BEG2_input = {J_l_GH_END3,JW2END1,J2MID_GHb_END1,Q4};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG2 (
+	.A0 (N1BEG2_input[0]),
+	.A1 (N1BEG2_input[1]),
+	.A2 (N1BEG2_input[2]),
+	.A3 (N1BEG2_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (N1BEG2)
+	);
+
+// switch matrix multiplexer  N1BEG3 		MUX-4
+	assign N1BEG3_input = {J_l_AB_END0,JW2END2,J2MID_ABb_END2,Q5};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG3 (
+	.A0 (N1BEG3_input[0]),
+	.A1 (N1BEG3_input[1]),
+	.A2 (N1BEG3_input[2]),
+	.A3 (N1BEG3_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (N1BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = JN2END0;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = JN2END1;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = JN2END2;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = JN2END3;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = JN2END4;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = JN2END5;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = JN2END6;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = JN2END7;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = N2MID0;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = N2MID1;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = N2MID2;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = N2MID3;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = N2MID4;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = N2MID5;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = N2MID6;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = N2MID7;
+// switch matrix multiplexer  N4BEG0 		MUX-4
+	assign N4BEG0_input = {Q4,E6END1,N4END1,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG0 (
+	.A0 (N4BEG0_input[0]),
+	.A1 (N4BEG0_input[1]),
+	.A2 (N4BEG0_input[2]),
+	.A3 (N4BEG0_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (N4BEG0)
+	);
+
+// switch matrix multiplexer  N4BEG1 		MUX-4
+	assign N4BEG1_input = {Q5,E6END0,N4END2,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG1 (
+	.A0 (N4BEG1_input[0]),
+	.A1 (N4BEG1_input[1]),
+	.A2 (N4BEG1_input[2]),
+	.A3 (N4BEG1_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (N4BEG1)
+	);
+
+// switch matrix multiplexer  N4BEG2 		MUX-4
+	assign N4BEG2_input = {Q6,W6END1,N4END3,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG2 (
+	.A0 (N4BEG2_input[0]),
+	.A1 (N4BEG2_input[1]),
+	.A2 (N4BEG2_input[2]),
+	.A3 (N4BEG2_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (N4BEG2)
+	);
+
+// switch matrix multiplexer  N4BEG3 		MUX-4
+	assign N4BEG3_input = {Q7,W6END0,N4END0,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG3 (
+	.A0 (N4BEG3_input[0]),
+	.A1 (N4BEG3_input[1]),
+	.A2 (N4BEG3_input[2]),
+	.A3 (N4BEG3_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (N4BEG3)
+	);
+
+// switch matrix multiplexer  NN4BEG0 		MUX-8
+	assign NN4BEG0_input = {J2END_GH_END1,J2MID_CDb_END1,J2MID_ABb_END1,Q2,Q6,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG0 (
+	.A0 (NN4BEG0_input[0]),
+	.A1 (NN4BEG0_input[1]),
+	.A2 (NN4BEG0_input[2]),
+	.A3 (NN4BEG0_input[3]),
+	.A4 (NN4BEG0_input[4]),
+	.A5 (NN4BEG0_input[5]),
+	.A6 (NN4BEG0_input[6]),
+	.A7 (NN4BEG0_input[7]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.S2 (ConfigBits[16+2]),
+	.S2N (ConfigBits_N[16+2]),
+	.X (NN4BEG0)
+	);
+
+// switch matrix multiplexer  NN4BEG1 		MUX-8
+	assign NN4BEG1_input = {J2END_EF_END1,J2MID_CDa_END2,J2MID_ABa_END2,Q3,Q7,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG1 (
+	.A0 (NN4BEG1_input[0]),
+	.A1 (NN4BEG1_input[1]),
+	.A2 (NN4BEG1_input[2]),
+	.A3 (NN4BEG1_input[3]),
+	.A4 (NN4BEG1_input[4]),
+	.A5 (NN4BEG1_input[5]),
+	.A6 (NN4BEG1_input[6]),
+	.A7 (NN4BEG1_input[7]),
+	.S0 (ConfigBits[19+0]),
+	.S0N (ConfigBits_N[19+0]),
+	.S1 (ConfigBits[19+1]),
+	.S1N (ConfigBits_N[19+1]),
+	.S2 (ConfigBits[19+2]),
+	.S2N (ConfigBits_N[19+2]),
+	.X (NN4BEG1)
+	);
+
+// switch matrix multiplexer  NN4BEG2 		MUX-8
+	assign NN4BEG2_input = {J2END_CD_END1,J2MID_GHb_END1,J2MID_EFb_END1,Q4,Q8,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG2 (
+	.A0 (NN4BEG2_input[0]),
+	.A1 (NN4BEG2_input[1]),
+	.A2 (NN4BEG2_input[2]),
+	.A3 (NN4BEG2_input[3]),
+	.A4 (NN4BEG2_input[4]),
+	.A5 (NN4BEG2_input[5]),
+	.A6 (NN4BEG2_input[6]),
+	.A7 (NN4BEG2_input[7]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.S2 (ConfigBits[22+2]),
+	.S2N (ConfigBits_N[22+2]),
+	.X (NN4BEG2)
+	);
+
+// switch matrix multiplexer  NN4BEG3 		MUX-8
+	assign NN4BEG3_input = {J2END_AB_END1,J2MID_GHa_END2,J2MID_EFa_END2,Q5,Q9,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG3 (
+	.A0 (NN4BEG3_input[0]),
+	.A1 (NN4BEG3_input[1]),
+	.A2 (NN4BEG3_input[2]),
+	.A3 (NN4BEG3_input[3]),
+	.A4 (NN4BEG3_input[4]),
+	.A5 (NN4BEG3_input[5]),
+	.A6 (NN4BEG3_input[6]),
+	.A7 (NN4BEG3_input[7]),
+	.S0 (ConfigBits[25+0]),
+	.S0N (ConfigBits_N[25+0]),
+	.S1 (ConfigBits[25+1]),
+	.S1N (ConfigBits_N[25+1]),
+	.S2 (ConfigBits[25+2]),
+	.S2N (ConfigBits_N[25+2]),
+	.X (NN4BEG3)
+	);
+
+// switch matrix multiplexer  bot2top0 		MUX-1
+	assign bot2top0 = Q10;
+// switch matrix multiplexer  bot2top1 		MUX-1
+	assign bot2top1 = Q11;
+// switch matrix multiplexer  bot2top2 		MUX-1
+	assign bot2top2 = Q12;
+// switch matrix multiplexer  bot2top3 		MUX-1
+	assign bot2top3 = Q13;
+// switch matrix multiplexer  bot2top4 		MUX-1
+	assign bot2top4 = Q14;
+// switch matrix multiplexer  bot2top5 		MUX-1
+	assign bot2top5 = Q15;
+// switch matrix multiplexer  bot2top6 		MUX-1
+	assign bot2top6 = Q16;
+// switch matrix multiplexer  bot2top7 		MUX-1
+	assign bot2top7 = Q17;
+// switch matrix multiplexer  bot2top8 		MUX-1
+	assign bot2top8 = Q18;
+// switch matrix multiplexer  bot2top9 		MUX-1
+	assign bot2top9 = Q19;
+// switch matrix multiplexer  E1BEG0 		MUX-4
+	assign E1BEG0_input = {J_l_CD_END1,JN2END3,J2MID_CDb_END3,Q3};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG0 (
+	.A0 (E1BEG0_input[0]),
+	.A1 (E1BEG0_input[1]),
+	.A2 (E1BEG0_input[2]),
+	.A3 (E1BEG0_input[3]),
+	.S0 (ConfigBits[28+0]),
+	.S0N (ConfigBits_N[28+0]),
+	.S1 (ConfigBits[28+1]),
+	.S1N (ConfigBits_N[28+1]),
+	.X (E1BEG0)
+	);
+
+// switch matrix multiplexer  E1BEG1 		MUX-4
+	assign E1BEG1_input = {J_l_EF_END2,JN2END0,J2MID_EFb_END0,Q4};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG1 (
+	.A0 (E1BEG1_input[0]),
+	.A1 (E1BEG1_input[1]),
+	.A2 (E1BEG1_input[2]),
+	.A3 (E1BEG1_input[3]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.X (E1BEG1)
+	);
+
+// switch matrix multiplexer  E1BEG2 		MUX-4
+	assign E1BEG2_input = {J_l_GH_END3,JN2END1,J2MID_GHb_END1,Q5};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG2 (
+	.A0 (E1BEG2_input[0]),
+	.A1 (E1BEG2_input[1]),
+	.A2 (E1BEG2_input[2]),
+	.A3 (E1BEG2_input[3]),
+	.S0 (ConfigBits[32+0]),
+	.S0N (ConfigBits_N[32+0]),
+	.S1 (ConfigBits[32+1]),
+	.S1N (ConfigBits_N[32+1]),
+	.X (E1BEG2)
+	);
+
+// switch matrix multiplexer  E1BEG3 		MUX-4
+	assign E1BEG3_input = {J_l_AB_END0,JN2END2,J2MID_ABb_END2,Q6};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG3 (
+	.A0 (E1BEG3_input[0]),
+	.A1 (E1BEG3_input[1]),
+	.A2 (E1BEG3_input[2]),
+	.A3 (E1BEG3_input[3]),
+	.S0 (ConfigBits[34+0]),
+	.S0N (ConfigBits_N[34+0]),
+	.S1 (ConfigBits[34+1]),
+	.S1N (ConfigBits_N[34+1]),
+	.X (E1BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = JE2END0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = JE2END1;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = JE2END2;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = JE2END3;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = JE2END4;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = JE2END5;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = JE2END6;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = JE2END7;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = E2MID0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = E2MID1;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = E2MID2;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = E2MID3;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = E2MID4;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = E2MID5;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = E2MID6;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = E2MID7;
+// switch matrix multiplexer  EE4BEG0 		MUX-8
+	assign EE4BEG0_input = {J2END_GH_END0,J2MID_CDb_END1,J2MID_ABb_END1,Q2,Q6,S1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG0 (
+	.A0 (EE4BEG0_input[0]),
+	.A1 (EE4BEG0_input[1]),
+	.A2 (EE4BEG0_input[2]),
+	.A3 (EE4BEG0_input[3]),
+	.A4 (EE4BEG0_input[4]),
+	.A5 (EE4BEG0_input[5]),
+	.A6 (EE4BEG0_input[6]),
+	.A7 (EE4BEG0_input[7]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.S2 (ConfigBits[36+2]),
+	.S2N (ConfigBits_N[36+2]),
+	.X (EE4BEG0)
+	);
+
+// switch matrix multiplexer  EE4BEG1 		MUX-8
+	assign EE4BEG1_input = {J2END_EF_END0,J2MID_CDa_END2,J2MID_ABa_END2,Q3,Q7,S1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG1 (
+	.A0 (EE4BEG1_input[0]),
+	.A1 (EE4BEG1_input[1]),
+	.A2 (EE4BEG1_input[2]),
+	.A3 (EE4BEG1_input[3]),
+	.A4 (EE4BEG1_input[4]),
+	.A5 (EE4BEG1_input[5]),
+	.A6 (EE4BEG1_input[6]),
+	.A7 (EE4BEG1_input[7]),
+	.S0 (ConfigBits[39+0]),
+	.S0N (ConfigBits_N[39+0]),
+	.S1 (ConfigBits[39+1]),
+	.S1N (ConfigBits_N[39+1]),
+	.S2 (ConfigBits[39+2]),
+	.S2N (ConfigBits_N[39+2]),
+	.X (EE4BEG1)
+	);
+
+// switch matrix multiplexer  EE4BEG2 		MUX-8
+	assign EE4BEG2_input = {J2END_CD_END0,J2MID_GHb_END1,J2MID_EFb_END1,Q4,Q8,S1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG2 (
+	.A0 (EE4BEG2_input[0]),
+	.A1 (EE4BEG2_input[1]),
+	.A2 (EE4BEG2_input[2]),
+	.A3 (EE4BEG2_input[3]),
+	.A4 (EE4BEG2_input[4]),
+	.A5 (EE4BEG2_input[5]),
+	.A6 (EE4BEG2_input[6]),
+	.A7 (EE4BEG2_input[7]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.S2 (ConfigBits[42+2]),
+	.S2N (ConfigBits_N[42+2]),
+	.X (EE4BEG2)
+	);
+
+// switch matrix multiplexer  EE4BEG3 		MUX-8
+	assign EE4BEG3_input = {J2END_AB_END0,J2MID_GHa_END2,J2MID_EFa_END2,Q5,Q9,S1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG3 (
+	.A0 (EE4BEG3_input[0]),
+	.A1 (EE4BEG3_input[1]),
+	.A2 (EE4BEG3_input[2]),
+	.A3 (EE4BEG3_input[3]),
+	.A4 (EE4BEG3_input[4]),
+	.A5 (EE4BEG3_input[5]),
+	.A6 (EE4BEG3_input[6]),
+	.A7 (EE4BEG3_input[7]),
+	.S0 (ConfigBits[45+0]),
+	.S0N (ConfigBits_N[45+0]),
+	.S1 (ConfigBits[45+1]),
+	.S1N (ConfigBits_N[45+1]),
+	.S2 (ConfigBits[45+2]),
+	.S2N (ConfigBits_N[45+2]),
+	.X (EE4BEG3)
+	);
+
+// switch matrix multiplexer  E6BEG0 		MUX-16
+	assign E6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,W1END3,E1END3};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG0 (
+	.A0 (E6BEG0_input[0]),
+	.A1 (E6BEG0_input[1]),
+	.A2 (E6BEG0_input[2]),
+	.A3 (E6BEG0_input[3]),
+	.A4 (E6BEG0_input[4]),
+	.A5 (E6BEG0_input[5]),
+	.A6 (E6BEG0_input[6]),
+	.A7 (E6BEG0_input[7]),
+	.A8 (E6BEG0_input[8]),
+	.A9 (E6BEG0_input[9]),
+	.A10 (E6BEG0_input[10]),
+	.A11 (E6BEG0_input[11]),
+	.A12 (E6BEG0_input[12]),
+	.A13 (E6BEG0_input[13]),
+	.A14 (E6BEG0_input[14]),
+	.A15 (E6BEG0_input[15]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.S2 (ConfigBits[48+2]),
+	.S2N (ConfigBits_N[48+2]),
+	.S3 (ConfigBits[48+3]),
+	.S3N (ConfigBits_N[48+3]),
+	.X (E6BEG0)
+	);
+
+// switch matrix multiplexer  E6BEG1 		MUX-16
+	assign E6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,W1END2,E1END2};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG1 (
+	.A0 (E6BEG1_input[0]),
+	.A1 (E6BEG1_input[1]),
+	.A2 (E6BEG1_input[2]),
+	.A3 (E6BEG1_input[3]),
+	.A4 (E6BEG1_input[4]),
+	.A5 (E6BEG1_input[5]),
+	.A6 (E6BEG1_input[6]),
+	.A7 (E6BEG1_input[7]),
+	.A8 (E6BEG1_input[8]),
+	.A9 (E6BEG1_input[9]),
+	.A10 (E6BEG1_input[10]),
+	.A11 (E6BEG1_input[11]),
+	.A12 (E6BEG1_input[12]),
+	.A13 (E6BEG1_input[13]),
+	.A14 (E6BEG1_input[14]),
+	.A15 (E6BEG1_input[15]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.S2 (ConfigBits[52+2]),
+	.S2N (ConfigBits_N[52+2]),
+	.S3 (ConfigBits[52+3]),
+	.S3N (ConfigBits_N[52+3]),
+	.X (E6BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG0 		MUX-4
+	assign S1BEG0_input = {J_l_CD_END1,JE2END3,J2MID_CDb_END3,Q4};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG0 (
+	.A0 (S1BEG0_input[0]),
+	.A1 (S1BEG0_input[1]),
+	.A2 (S1BEG0_input[2]),
+	.A3 (S1BEG0_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (S1BEG0)
+	);
+
+// switch matrix multiplexer  S1BEG1 		MUX-4
+	assign S1BEG1_input = {J_l_EF_END2,JE2END0,J2MID_EFb_END0,Q5};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG1 (
+	.A0 (S1BEG1_input[0]),
+	.A1 (S1BEG1_input[1]),
+	.A2 (S1BEG1_input[2]),
+	.A3 (S1BEG1_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (S1BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG2 		MUX-4
+	assign S1BEG2_input = {J_l_GH_END3,JE2END1,J2MID_GHb_END1,Q6};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG2 (
+	.A0 (S1BEG2_input[0]),
+	.A1 (S1BEG2_input[1]),
+	.A2 (S1BEG2_input[2]),
+	.A3 (S1BEG2_input[3]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.X (S1BEG2)
+	);
+
+// switch matrix multiplexer  S1BEG3 		MUX-4
+	assign S1BEG3_input = {J_l_AB_END0,JE2END2,J2MID_ABb_END2,Q7};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG3 (
+	.A0 (S1BEG3_input[0]),
+	.A1 (S1BEG3_input[1]),
+	.A2 (S1BEG3_input[2]),
+	.A3 (S1BEG3_input[3]),
+	.S0 (ConfigBits[62+0]),
+	.S0N (ConfigBits_N[62+0]),
+	.S1 (ConfigBits[62+1]),
+	.S1N (ConfigBits_N[62+1]),
+	.X (S1BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = JS2END0;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = JS2END1;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = JS2END2;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = JS2END3;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = JS2END4;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = JS2END5;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = JS2END6;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = JS2END7;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = S2MID0;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = S2MID1;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = S2MID2;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = S2MID3;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = S2MID4;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = S2MID5;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = S2MID6;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = S2MID7;
+// switch matrix multiplexer  S4BEG0 		MUX-4
+	assign S4BEG0_input = {Q0,S4END1,S2END2,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG0 (
+	.A0 (S4BEG0_input[0]),
+	.A1 (S4BEG0_input[1]),
+	.A2 (S4BEG0_input[2]),
+	.A3 (S4BEG0_input[3]),
+	.S0 (ConfigBits[64+0]),
+	.S0N (ConfigBits_N[64+0]),
+	.S1 (ConfigBits[64+1]),
+	.S1N (ConfigBits_N[64+1]),
+	.X (S4BEG0)
+	);
+
+// switch matrix multiplexer  S4BEG1 		MUX-4
+	assign S4BEG1_input = {Q1,S4END2,S2END3,E6END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG1 (
+	.A0 (S4BEG1_input[0]),
+	.A1 (S4BEG1_input[1]),
+	.A2 (S4BEG1_input[2]),
+	.A3 (S4BEG1_input[3]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.X (S4BEG1)
+	);
+
+// switch matrix multiplexer  S4BEG2 		MUX-4
+	assign S4BEG2_input = {Q2,W6END1,S4END3,S2END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG2 (
+	.A0 (S4BEG2_input[0]),
+	.A1 (S4BEG2_input[1]),
+	.A2 (S4BEG2_input[2]),
+	.A3 (S4BEG2_input[3]),
+	.S0 (ConfigBits[68+0]),
+	.S0N (ConfigBits_N[68+0]),
+	.S1 (ConfigBits[68+1]),
+	.S1N (ConfigBits_N[68+1]),
+	.X (S4BEG2)
+	);
+
+// switch matrix multiplexer  S4BEG3 		MUX-4
+	assign S4BEG3_input = {Q3,W6END0,S4END0,S2END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG3 (
+	.A0 (S4BEG3_input[0]),
+	.A1 (S4BEG3_input[1]),
+	.A2 (S4BEG3_input[2]),
+	.A3 (S4BEG3_input[3]),
+	.S0 (ConfigBits[70+0]),
+	.S0N (ConfigBits_N[70+0]),
+	.S1 (ConfigBits[70+1]),
+	.S1N (ConfigBits_N[70+1]),
+	.X (S4BEG3)
+	);
+
+// switch matrix multiplexer  SS4BEG0 		MUX-8
+	assign SS4BEG0_input = {J2END_GH_END3,J2MID_CDb_END1,J2MID_ABb_END1,Q2,Q6,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG0 (
+	.A0 (SS4BEG0_input[0]),
+	.A1 (SS4BEG0_input[1]),
+	.A2 (SS4BEG0_input[2]),
+	.A3 (SS4BEG0_input[3]),
+	.A4 (SS4BEG0_input[4]),
+	.A5 (SS4BEG0_input[5]),
+	.A6 (SS4BEG0_input[6]),
+	.A7 (SS4BEG0_input[7]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.S2 (ConfigBits[72+2]),
+	.S2N (ConfigBits_N[72+2]),
+	.X (SS4BEG0)
+	);
+
+// switch matrix multiplexer  SS4BEG1 		MUX-8
+	assign SS4BEG1_input = {J2END_EF_END3,J2MID_CDa_END2,J2MID_ABa_END2,Q3,Q7,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG1 (
+	.A0 (SS4BEG1_input[0]),
+	.A1 (SS4BEG1_input[1]),
+	.A2 (SS4BEG1_input[2]),
+	.A3 (SS4BEG1_input[3]),
+	.A4 (SS4BEG1_input[4]),
+	.A5 (SS4BEG1_input[5]),
+	.A6 (SS4BEG1_input[6]),
+	.A7 (SS4BEG1_input[7]),
+	.S0 (ConfigBits[75+0]),
+	.S0N (ConfigBits_N[75+0]),
+	.S1 (ConfigBits[75+1]),
+	.S1N (ConfigBits_N[75+1]),
+	.S2 (ConfigBits[75+2]),
+	.S2N (ConfigBits_N[75+2]),
+	.X (SS4BEG1)
+	);
+
+// switch matrix multiplexer  SS4BEG2 		MUX-8
+	assign SS4BEG2_input = {J2END_CD_END3,J2MID_GHb_END1,J2MID_EFb_END1,Q4,Q8,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG2 (
+	.A0 (SS4BEG2_input[0]),
+	.A1 (SS4BEG2_input[1]),
+	.A2 (SS4BEG2_input[2]),
+	.A3 (SS4BEG2_input[3]),
+	.A4 (SS4BEG2_input[4]),
+	.A5 (SS4BEG2_input[5]),
+	.A6 (SS4BEG2_input[6]),
+	.A7 (SS4BEG2_input[7]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.S2 (ConfigBits[78+2]),
+	.S2N (ConfigBits_N[78+2]),
+	.X (SS4BEG2)
+	);
+
+// switch matrix multiplexer  SS4BEG3 		MUX-8
+	assign SS4BEG3_input = {J2END_AB_END3,J2MID_GHa_END2,J2MID_EFa_END2,Q5,Q9,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG3 (
+	.A0 (SS4BEG3_input[0]),
+	.A1 (SS4BEG3_input[1]),
+	.A2 (SS4BEG3_input[2]),
+	.A3 (SS4BEG3_input[3]),
+	.A4 (SS4BEG3_input[4]),
+	.A5 (SS4BEG3_input[5]),
+	.A6 (SS4BEG3_input[6]),
+	.A7 (SS4BEG3_input[7]),
+	.S0 (ConfigBits[81+0]),
+	.S0N (ConfigBits_N[81+0]),
+	.S1 (ConfigBits[81+1]),
+	.S1N (ConfigBits_N[81+1]),
+	.S2 (ConfigBits[81+2]),
+	.S2N (ConfigBits_N[81+2]),
+	.X (SS4BEG3)
+	);
+
+// switch matrix multiplexer  W1BEG0 		MUX-4
+	assign W1BEG0_input = {J_l_CD_END1,JS2END3,J2MID_CDb_END3,Q5};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG0 (
+	.A0 (W1BEG0_input[0]),
+	.A1 (W1BEG0_input[1]),
+	.A2 (W1BEG0_input[2]),
+	.A3 (W1BEG0_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (W1BEG0)
+	);
+
+// switch matrix multiplexer  W1BEG1 		MUX-4
+	assign W1BEG1_input = {J_l_EF_END2,JS2END0,J2MID_EFb_END0,Q6};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG1 (
+	.A0 (W1BEG1_input[0]),
+	.A1 (W1BEG1_input[1]),
+	.A2 (W1BEG1_input[2]),
+	.A3 (W1BEG1_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (W1BEG1)
+	);
+
+// switch matrix multiplexer  W1BEG2 		MUX-4
+	assign W1BEG2_input = {J_l_GH_END3,JS2END1,J2MID_GHb_END1,Q7};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG2 (
+	.A0 (W1BEG2_input[0]),
+	.A1 (W1BEG2_input[1]),
+	.A2 (W1BEG2_input[2]),
+	.A3 (W1BEG2_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (W1BEG2)
+	);
+
+// switch matrix multiplexer  W1BEG3 		MUX-4
+	assign W1BEG3_input = {J_l_AB_END0,JS2END2,J2MID_ABb_END2,Q0};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG3 (
+	.A0 (W1BEG3_input[0]),
+	.A1 (W1BEG3_input[1]),
+	.A2 (W1BEG3_input[2]),
+	.A3 (W1BEG3_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (W1BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = W2END0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = JW2END1;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = JW2END2;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = W2END3;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = W2END4;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = JW2END5;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = JW2END6;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = W2END7;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = W2MID0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = W2MID1;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = W2MID2;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = W2MID3;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = W2MID4;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = W2MID5;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = W2MID6;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = W2MID7;
+// switch matrix multiplexer  WW4BEG0 		MUX-8
+	assign WW4BEG0_input = {J2END_GH_END2,J2MID_CDb_END1,J2MID_ABb_END1,Q2,Q6,W1END2,S1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG0 (
+	.A0 (WW4BEG0_input[0]),
+	.A1 (WW4BEG0_input[1]),
+	.A2 (WW4BEG0_input[2]),
+	.A3 (WW4BEG0_input[3]),
+	.A4 (WW4BEG0_input[4]),
+	.A5 (WW4BEG0_input[5]),
+	.A6 (WW4BEG0_input[6]),
+	.A7 (WW4BEG0_input[7]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.S2 (ConfigBits[92+2]),
+	.S2N (ConfigBits_N[92+2]),
+	.X (WW4BEG0)
+	);
+
+// switch matrix multiplexer  WW4BEG1 		MUX-8
+	assign WW4BEG1_input = {J2END_EF_END2,J2MID_CDa_END2,J2MID_ABa_END2,Q3,Q7,W1END3,S1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG1 (
+	.A0 (WW4BEG1_input[0]),
+	.A1 (WW4BEG1_input[1]),
+	.A2 (WW4BEG1_input[2]),
+	.A3 (WW4BEG1_input[3]),
+	.A4 (WW4BEG1_input[4]),
+	.A5 (WW4BEG1_input[5]),
+	.A6 (WW4BEG1_input[6]),
+	.A7 (WW4BEG1_input[7]),
+	.S0 (ConfigBits[95+0]),
+	.S0N (ConfigBits_N[95+0]),
+	.S1 (ConfigBits[95+1]),
+	.S1N (ConfigBits_N[95+1]),
+	.S2 (ConfigBits[95+2]),
+	.S2N (ConfigBits_N[95+2]),
+	.X (WW4BEG1)
+	);
+
+// switch matrix multiplexer  WW4BEG2 		MUX-8
+	assign WW4BEG2_input = {J2END_CD_END2,J2MID_GHb_END1,J2MID_EFb_END1,Q4,Q8,W1END0,S1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG2 (
+	.A0 (WW4BEG2_input[0]),
+	.A1 (WW4BEG2_input[1]),
+	.A2 (WW4BEG2_input[2]),
+	.A3 (WW4BEG2_input[3]),
+	.A4 (WW4BEG2_input[4]),
+	.A5 (WW4BEG2_input[5]),
+	.A6 (WW4BEG2_input[6]),
+	.A7 (WW4BEG2_input[7]),
+	.S0 (ConfigBits[98+0]),
+	.S0N (ConfigBits_N[98+0]),
+	.S1 (ConfigBits[98+1]),
+	.S1N (ConfigBits_N[98+1]),
+	.S2 (ConfigBits[98+2]),
+	.S2N (ConfigBits_N[98+2]),
+	.X (WW4BEG2)
+	);
+
+// switch matrix multiplexer  WW4BEG3 		MUX-8
+	assign WW4BEG3_input = {J2END_AB_END2,J2MID_GHa_END2,J2MID_EFa_END2,Q5,Q9,W1END1,S1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG3 (
+	.A0 (WW4BEG3_input[0]),
+	.A1 (WW4BEG3_input[1]),
+	.A2 (WW4BEG3_input[2]),
+	.A3 (WW4BEG3_input[3]),
+	.A4 (WW4BEG3_input[4]),
+	.A5 (WW4BEG3_input[5]),
+	.A6 (WW4BEG3_input[6]),
+	.A7 (WW4BEG3_input[7]),
+	.S0 (ConfigBits[101+0]),
+	.S0N (ConfigBits_N[101+0]),
+	.S1 (ConfigBits[101+1]),
+	.S1N (ConfigBits_N[101+1]),
+	.S2 (ConfigBits[101+2]),
+	.S2N (ConfigBits_N[101+2]),
+	.X (WW4BEG3)
+	);
+
+// switch matrix multiplexer  W6BEG0 		MUX-16
+	assign W6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,W1END3,E1END3};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG0 (
+	.A0 (W6BEG0_input[0]),
+	.A1 (W6BEG0_input[1]),
+	.A2 (W6BEG0_input[2]),
+	.A3 (W6BEG0_input[3]),
+	.A4 (W6BEG0_input[4]),
+	.A5 (W6BEG0_input[5]),
+	.A6 (W6BEG0_input[6]),
+	.A7 (W6BEG0_input[7]),
+	.A8 (W6BEG0_input[8]),
+	.A9 (W6BEG0_input[9]),
+	.A10 (W6BEG0_input[10]),
+	.A11 (W6BEG0_input[11]),
+	.A12 (W6BEG0_input[12]),
+	.A13 (W6BEG0_input[13]),
+	.A14 (W6BEG0_input[14]),
+	.A15 (W6BEG0_input[15]),
+	.S0 (ConfigBits[104+0]),
+	.S0N (ConfigBits_N[104+0]),
+	.S1 (ConfigBits[104+1]),
+	.S1N (ConfigBits_N[104+1]),
+	.S2 (ConfigBits[104+2]),
+	.S2N (ConfigBits_N[104+2]),
+	.S3 (ConfigBits[104+3]),
+	.S3N (ConfigBits_N[104+3]),
+	.X (W6BEG0)
+	);
+
+// switch matrix multiplexer  W6BEG1 		MUX-16
+	assign W6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,W1END2,E1END2};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG1 (
+	.A0 (W6BEG1_input[0]),
+	.A1 (W6BEG1_input[1]),
+	.A2 (W6BEG1_input[2]),
+	.A3 (W6BEG1_input[3]),
+	.A4 (W6BEG1_input[4]),
+	.A5 (W6BEG1_input[5]),
+	.A6 (W6BEG1_input[6]),
+	.A7 (W6BEG1_input[7]),
+	.A8 (W6BEG1_input[8]),
+	.A9 (W6BEG1_input[9]),
+	.A10 (W6BEG1_input[10]),
+	.A11 (W6BEG1_input[11]),
+	.A12 (W6BEG1_input[12]),
+	.A13 (W6BEG1_input[13]),
+	.A14 (W6BEG1_input[14]),
+	.A15 (W6BEG1_input[15]),
+	.S0 (ConfigBits[108+0]),
+	.S0N (ConfigBits_N[108+0]),
+	.S1 (ConfigBits[108+1]),
+	.S1N (ConfigBits_N[108+1]),
+	.S2 (ConfigBits[108+2]),
+	.S2N (ConfigBits_N[108+2]),
+	.S3 (ConfigBits[108+3]),
+	.S3N (ConfigBits_N[108+3]),
+	.X (W6BEG1)
+	);
+
+// switch matrix multiplexer  A7 		MUX-1
+	assign A7 = top2bot3;
+// switch matrix multiplexer  A6 		MUX-1
+	assign A6 = top2bot2;
+// switch matrix multiplexer  A5 		MUX-1
+	assign A5 = top2bot1;
+// switch matrix multiplexer  A4 		MUX-1
+	assign A4 = top2bot0;
+// switch matrix multiplexer  A3 		MUX-4
+	assign A3_input = {J_l_AB_END3,J2END_AB_END3,J2MID_ABb_END3,J2MID_ABa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_A3 (
+	.A0 (A3_input[0]),
+	.A1 (A3_input[1]),
+	.A2 (A3_input[2]),
+	.A3 (A3_input[3]),
+	.S0 (ConfigBits[112+0]),
+	.S0N (ConfigBits_N[112+0]),
+	.S1 (ConfigBits[112+1]),
+	.S1N (ConfigBits_N[112+1]),
+	.X (A3)
+	);
+
+// switch matrix multiplexer  A2 		MUX-4
+	assign A2_input = {J_l_AB_END2,J2END_AB_END2,J2MID_ABb_END2,J2MID_ABa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_A2 (
+	.A0 (A2_input[0]),
+	.A1 (A2_input[1]),
+	.A2 (A2_input[2]),
+	.A3 (A2_input[3]),
+	.S0 (ConfigBits[114+0]),
+	.S0N (ConfigBits_N[114+0]),
+	.S1 (ConfigBits[114+1]),
+	.S1N (ConfigBits_N[114+1]),
+	.X (A2)
+	);
+
+// switch matrix multiplexer  A1 		MUX-4
+	assign A1_input = {J_l_AB_END1,J2END_AB_END1,J2MID_ABb_END1,J2MID_ABa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_A1 (
+	.A0 (A1_input[0]),
+	.A1 (A1_input[1]),
+	.A2 (A1_input[2]),
+	.A3 (A1_input[3]),
+	.S0 (ConfigBits[116+0]),
+	.S0N (ConfigBits_N[116+0]),
+	.S1 (ConfigBits[116+1]),
+	.S1N (ConfigBits_N[116+1]),
+	.X (A1)
+	);
+
+// switch matrix multiplexer  A0 		MUX-4
+	assign A0_input = {J_l_AB_END0,J2END_AB_END0,J2MID_ABb_END0,J2MID_ABa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_A0 (
+	.A0 (A0_input[0]),
+	.A1 (A0_input[1]),
+	.A2 (A0_input[2]),
+	.A3 (A0_input[3]),
+	.S0 (ConfigBits[118+0]),
+	.S0N (ConfigBits_N[118+0]),
+	.S1 (ConfigBits[118+1]),
+	.S1N (ConfigBits_N[118+1]),
+	.X (A0)
+	);
+
+// switch matrix multiplexer  B7 		MUX-1
+	assign B7 = top2bot7;
+// switch matrix multiplexer  B6 		MUX-1
+	assign B6 = top2bot6;
+// switch matrix multiplexer  B5 		MUX-1
+	assign B5 = top2bot5;
+// switch matrix multiplexer  B4 		MUX-1
+	assign B4 = top2bot4;
+// switch matrix multiplexer  B3 		MUX-4
+	assign B3_input = {J_l_CD_END3,J2END_CD_END3,J2MID_CDb_END3,J2MID_CDa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_B3 (
+	.A0 (B3_input[0]),
+	.A1 (B3_input[1]),
+	.A2 (B3_input[2]),
+	.A3 (B3_input[3]),
+	.S0 (ConfigBits[120+0]),
+	.S0N (ConfigBits_N[120+0]),
+	.S1 (ConfigBits[120+1]),
+	.S1N (ConfigBits_N[120+1]),
+	.X (B3)
+	);
+
+// switch matrix multiplexer  B2 		MUX-4
+	assign B2_input = {J_l_CD_END2,J2END_CD_END2,J2MID_CDb_END2,J2MID_CDa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_B2 (
+	.A0 (B2_input[0]),
+	.A1 (B2_input[1]),
+	.A2 (B2_input[2]),
+	.A3 (B2_input[3]),
+	.S0 (ConfigBits[122+0]),
+	.S0N (ConfigBits_N[122+0]),
+	.S1 (ConfigBits[122+1]),
+	.S1N (ConfigBits_N[122+1]),
+	.X (B2)
+	);
+
+// switch matrix multiplexer  B1 		MUX-4
+	assign B1_input = {J_l_CD_END1,J2END_CD_END1,J2MID_CDb_END1,J2MID_CDa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_B1 (
+	.A0 (B1_input[0]),
+	.A1 (B1_input[1]),
+	.A2 (B1_input[2]),
+	.A3 (B1_input[3]),
+	.S0 (ConfigBits[124+0]),
+	.S0N (ConfigBits_N[124+0]),
+	.S1 (ConfigBits[124+1]),
+	.S1N (ConfigBits_N[124+1]),
+	.X (B1)
+	);
+
+// switch matrix multiplexer  B0 		MUX-4
+	assign B0_input = {J_l_CD_END0,J2END_CD_END0,J2MID_CDb_END0,J2MID_CDa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_B0 (
+	.A0 (B0_input[0]),
+	.A1 (B0_input[1]),
+	.A2 (B0_input[2]),
+	.A3 (B0_input[3]),
+	.S0 (ConfigBits[126+0]),
+	.S0N (ConfigBits_N[126+0]),
+	.S1 (ConfigBits[126+1]),
+	.S1N (ConfigBits_N[126+1]),
+	.X (B0)
+	);
+
+// switch matrix multiplexer  C19 		MUX-1
+	assign C19 = top2bot17;
+// switch matrix multiplexer  C18 		MUX-1
+	assign C18 = top2bot16;
+// switch matrix multiplexer  C17 		MUX-1
+	assign C17 = top2bot15;
+// switch matrix multiplexer  C16 		MUX-1
+	assign C16 = top2bot14;
+// switch matrix multiplexer  C15 		MUX-1
+	assign C15 = top2bot13;
+// switch matrix multiplexer  C14 		MUX-1
+	assign C14 = top2bot12;
+// switch matrix multiplexer  C13 		MUX-1
+	assign C13 = top2bot11;
+// switch matrix multiplexer  C12 		MUX-1
+	assign C12 = top2bot10;
+// switch matrix multiplexer  C11 		MUX-1
+	assign C11 = top2bot9;
+// switch matrix multiplexer  C10 		MUX-1
+	assign C10 = top2bot8;
+// switch matrix multiplexer  C9 		MUX-8
+	assign C9_input = {JW2END7,JW2END5,JS2END7,JS2END5,JE2END7,JE2END5,JN2END7,JN2END5};
+	cus_mux81_buf inst_cus_mux81_buf_C9 (
+	.A0 (C9_input[0]),
+	.A1 (C9_input[1]),
+	.A2 (C9_input[2]),
+	.A3 (C9_input[3]),
+	.A4 (C9_input[4]),
+	.A5 (C9_input[5]),
+	.A6 (C9_input[6]),
+	.A7 (C9_input[7]),
+	.S0 (ConfigBits[128+0]),
+	.S0N (ConfigBits_N[128+0]),
+	.S1 (ConfigBits[128+1]),
+	.S1N (ConfigBits_N[128+1]),
+	.S2 (ConfigBits[128+2]),
+	.S2N (ConfigBits_N[128+2]),
+	.X (C9)
+	);
+
+// switch matrix multiplexer  C8 		MUX-8
+	assign C8_input = {JW2END6,JW2END4,JS2END6,JS2END4,JE2END6,JE2END4,JN2END6,JN2END4};
+	cus_mux81_buf inst_cus_mux81_buf_C8 (
+	.A0 (C8_input[0]),
+	.A1 (C8_input[1]),
+	.A2 (C8_input[2]),
+	.A3 (C8_input[3]),
+	.A4 (C8_input[4]),
+	.A5 (C8_input[5]),
+	.A6 (C8_input[6]),
+	.A7 (C8_input[7]),
+	.S0 (ConfigBits[131+0]),
+	.S0N (ConfigBits_N[131+0]),
+	.S1 (ConfigBits[131+1]),
+	.S1N (ConfigBits_N[131+1]),
+	.S2 (ConfigBits[131+2]),
+	.S2N (ConfigBits_N[131+2]),
+	.X (C8)
+	);
+
+// switch matrix multiplexer  C7 		MUX-4
+	assign C7_input = {J_l_GH_END3,J2END_GH_END3,J2MID_GHb_END3,J2MID_GHa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_C7 (
+	.A0 (C7_input[0]),
+	.A1 (C7_input[1]),
+	.A2 (C7_input[2]),
+	.A3 (C7_input[3]),
+	.S0 (ConfigBits[134+0]),
+	.S0N (ConfigBits_N[134+0]),
+	.S1 (ConfigBits[134+1]),
+	.S1N (ConfigBits_N[134+1]),
+	.X (C7)
+	);
+
+// switch matrix multiplexer  C6 		MUX-4
+	assign C6_input = {J_l_GH_END2,J2END_GH_END2,J2MID_GHb_END2,J2MID_GHa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_C6 (
+	.A0 (C6_input[0]),
+	.A1 (C6_input[1]),
+	.A2 (C6_input[2]),
+	.A3 (C6_input[3]),
+	.S0 (ConfigBits[136+0]),
+	.S0N (ConfigBits_N[136+0]),
+	.S1 (ConfigBits[136+1]),
+	.S1N (ConfigBits_N[136+1]),
+	.X (C6)
+	);
+
+// switch matrix multiplexer  C5 		MUX-4
+	assign C5_input = {J_l_GH_END1,J2END_GH_END1,J2MID_GHb_END1,J2MID_GHa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_C5 (
+	.A0 (C5_input[0]),
+	.A1 (C5_input[1]),
+	.A2 (C5_input[2]),
+	.A3 (C5_input[3]),
+	.S0 (ConfigBits[138+0]),
+	.S0N (ConfigBits_N[138+0]),
+	.S1 (ConfigBits[138+1]),
+	.S1N (ConfigBits_N[138+1]),
+	.X (C5)
+	);
+
+// switch matrix multiplexer  C4 		MUX-4
+	assign C4_input = {J_l_GH_END0,J2END_GH_END0,J2MID_GHb_END0,J2MID_GHa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_C4 (
+	.A0 (C4_input[0]),
+	.A1 (C4_input[1]),
+	.A2 (C4_input[2]),
+	.A3 (C4_input[3]),
+	.S0 (ConfigBits[140+0]),
+	.S0N (ConfigBits_N[140+0]),
+	.S1 (ConfigBits[140+1]),
+	.S1N (ConfigBits_N[140+1]),
+	.X (C4)
+	);
+
+// switch matrix multiplexer  C3 		MUX-4
+	assign C3_input = {J_l_EF_END3,J2END_EF_END3,J2MID_EFb_END3,J2MID_EFa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_C3 (
+	.A0 (C3_input[0]),
+	.A1 (C3_input[1]),
+	.A2 (C3_input[2]),
+	.A3 (C3_input[3]),
+	.S0 (ConfigBits[142+0]),
+	.S0N (ConfigBits_N[142+0]),
+	.S1 (ConfigBits[142+1]),
+	.S1N (ConfigBits_N[142+1]),
+	.X (C3)
+	);
+
+// switch matrix multiplexer  C2 		MUX-4
+	assign C2_input = {J_l_EF_END2,J2END_EF_END2,J2MID_EFb_END2,J2MID_EFa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_C2 (
+	.A0 (C2_input[0]),
+	.A1 (C2_input[1]),
+	.A2 (C2_input[2]),
+	.A3 (C2_input[3]),
+	.S0 (ConfigBits[144+0]),
+	.S0N (ConfigBits_N[144+0]),
+	.S1 (ConfigBits[144+1]),
+	.S1N (ConfigBits_N[144+1]),
+	.X (C2)
+	);
+
+// switch matrix multiplexer  C1 		MUX-4
+	assign C1_input = {J_l_EF_END1,J2END_EF_END1,J2MID_EFb_END1,J2MID_EFa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_C1 (
+	.A0 (C1_input[0]),
+	.A1 (C1_input[1]),
+	.A2 (C1_input[2]),
+	.A3 (C1_input[3]),
+	.S0 (ConfigBits[146+0]),
+	.S0N (ConfigBits_N[146+0]),
+	.S1 (ConfigBits[146+1]),
+	.S1N (ConfigBits_N[146+1]),
+	.X (C1)
+	);
+
+// switch matrix multiplexer  C0 		MUX-4
+	assign C0_input = {J_l_EF_END0,J2END_EF_END0,J2MID_EFb_END0,J2MID_EFa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_C0 (
+	.A0 (C0_input[0]),
+	.A1 (C0_input[1]),
+	.A2 (C0_input[2]),
+	.A3 (C0_input[3]),
+	.S0 (ConfigBits[148+0]),
+	.S0N (ConfigBits_N[148+0]),
+	.S1 (ConfigBits[148+1]),
+	.S1N (ConfigBits_N[148+1]),
+	.X (C0)
+	);
+
+// switch matrix multiplexer  clr 		MUX-16
+	assign clr_input = {VCC0,GND0,JW2END5,JW2END3,JW2END2,JS2END3,JS2END2,JE2END3,JE2END2,JN2END3,JN2END2,W2MID0,S2MID0,E2MID6,E2MID0,N2MID6};
+	cus_mux161_buf inst_cus_mux161_buf_clr (
+	.A0 (clr_input[0]),
+	.A1 (clr_input[1]),
+	.A2 (clr_input[2]),
+	.A3 (clr_input[3]),
+	.A4 (clr_input[4]),
+	.A5 (clr_input[5]),
+	.A6 (clr_input[6]),
+	.A7 (clr_input[7]),
+	.A8 (clr_input[8]),
+	.A9 (clr_input[9]),
+	.A10 (clr_input[10]),
+	.A11 (clr_input[11]),
+	.A12 (clr_input[12]),
+	.A13 (clr_input[13]),
+	.A14 (clr_input[14]),
+	.A15 (clr_input[15]),
+	.S0 (ConfigBits[150+0]),
+	.S0N (ConfigBits_N[150+0]),
+	.S1 (ConfigBits[150+1]),
+	.S1N (ConfigBits_N[150+1]),
+	.S2 (ConfigBits[150+2]),
+	.S2N (ConfigBits_N[150+2]),
+	.S3 (ConfigBits[150+3]),
+	.S3N (ConfigBits_N[150+3]),
+	.X (clr)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG0 		MUX-4
+	assign J2MID_ABa_BEG0_input = {JN2END3,W2MID6,S2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG0 (
+	.A0 (J2MID_ABa_BEG0_input[0]),
+	.A1 (J2MID_ABa_BEG0_input[1]),
+	.A2 (J2MID_ABa_BEG0_input[2]),
+	.A3 (J2MID_ABa_BEG0_input[3]),
+	.S0 (ConfigBits[154+0]),
+	.S0N (ConfigBits_N[154+0]),
+	.S1 (ConfigBits[154+1]),
+	.S1N (ConfigBits_N[154+1]),
+	.X (J2MID_ABa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG1 		MUX-4
+	assign J2MID_ABa_BEG1_input = {JE2END3,W2MID2,S2MID2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG1 (
+	.A0 (J2MID_ABa_BEG1_input[0]),
+	.A1 (J2MID_ABa_BEG1_input[1]),
+	.A2 (J2MID_ABa_BEG1_input[2]),
+	.A3 (J2MID_ABa_BEG1_input[3]),
+	.S0 (ConfigBits[156+0]),
+	.S0N (ConfigBits_N[156+0]),
+	.S1 (ConfigBits[156+1]),
+	.S1N (ConfigBits_N[156+1]),
+	.X (J2MID_ABa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG2 		MUX-4
+	assign J2MID_ABa_BEG2_input = {JS2END3,W2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG2 (
+	.A0 (J2MID_ABa_BEG2_input[0]),
+	.A1 (J2MID_ABa_BEG2_input[1]),
+	.A2 (J2MID_ABa_BEG2_input[2]),
+	.A3 (J2MID_ABa_BEG2_input[3]),
+	.S0 (ConfigBits[158+0]),
+	.S0N (ConfigBits_N[158+0]),
+	.S1 (ConfigBits[158+1]),
+	.S1N (ConfigBits_N[158+1]),
+	.X (J2MID_ABa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG3 		MUX-4
+	assign J2MID_ABa_BEG3_input = {JW2END3,S2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG3 (
+	.A0 (J2MID_ABa_BEG3_input[0]),
+	.A1 (J2MID_ABa_BEG3_input[1]),
+	.A2 (J2MID_ABa_BEG3_input[2]),
+	.A3 (J2MID_ABa_BEG3_input[3]),
+	.S0 (ConfigBits[160+0]),
+	.S0N (ConfigBits_N[160+0]),
+	.S1 (ConfigBits[160+1]),
+	.S1N (ConfigBits_N[160+1]),
+	.X (J2MID_ABa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG0 		MUX-4
+	assign J2MID_CDa_BEG0_input = {JN2END4,W2MID6,S2MID6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG0 (
+	.A0 (J2MID_CDa_BEG0_input[0]),
+	.A1 (J2MID_CDa_BEG0_input[1]),
+	.A2 (J2MID_CDa_BEG0_input[2]),
+	.A3 (J2MID_CDa_BEG0_input[3]),
+	.S0 (ConfigBits[162+0]),
+	.S0N (ConfigBits_N[162+0]),
+	.S1 (ConfigBits[162+1]),
+	.S1N (ConfigBits_N[162+1]),
+	.X (J2MID_CDa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG1 		MUX-4
+	assign J2MID_CDa_BEG1_input = {JE2END4,W2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG1 (
+	.A0 (J2MID_CDa_BEG1_input[0]),
+	.A1 (J2MID_CDa_BEG1_input[1]),
+	.A2 (J2MID_CDa_BEG1_input[2]),
+	.A3 (J2MID_CDa_BEG1_input[3]),
+	.S0 (ConfigBits[164+0]),
+	.S0N (ConfigBits_N[164+0]),
+	.S1 (ConfigBits[164+1]),
+	.S1N (ConfigBits_N[164+1]),
+	.X (J2MID_CDa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG2 		MUX-4
+	assign J2MID_CDa_BEG2_input = {JS2END4,S2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG2 (
+	.A0 (J2MID_CDa_BEG2_input[0]),
+	.A1 (J2MID_CDa_BEG2_input[1]),
+	.A2 (J2MID_CDa_BEG2_input[2]),
+	.A3 (J2MID_CDa_BEG2_input[3]),
+	.S0 (ConfigBits[166+0]),
+	.S0N (ConfigBits_N[166+0]),
+	.S1 (ConfigBits[166+1]),
+	.S1N (ConfigBits_N[166+1]),
+	.X (J2MID_CDa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG3 		MUX-4
+	assign J2MID_CDa_BEG3_input = {JW2END4,W2MID0,S2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG3 (
+	.A0 (J2MID_CDa_BEG3_input[0]),
+	.A1 (J2MID_CDa_BEG3_input[1]),
+	.A2 (J2MID_CDa_BEG3_input[2]),
+	.A3 (J2MID_CDa_BEG3_input[3]),
+	.S0 (ConfigBits[168+0]),
+	.S0N (ConfigBits_N[168+0]),
+	.S1 (ConfigBits[168+1]),
+	.S1N (ConfigBits_N[168+1]),
+	.X (J2MID_CDa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG0 		MUX-4
+	assign J2MID_EFa_BEG0_input = {JN2END5,W2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG0 (
+	.A0 (J2MID_EFa_BEG0_input[0]),
+	.A1 (J2MID_EFa_BEG0_input[1]),
+	.A2 (J2MID_EFa_BEG0_input[2]),
+	.A3 (J2MID_EFa_BEG0_input[3]),
+	.S0 (ConfigBits[170+0]),
+	.S0N (ConfigBits_N[170+0]),
+	.S1 (ConfigBits[170+1]),
+	.S1N (ConfigBits_N[170+1]),
+	.X (J2MID_EFa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG1 		MUX-4
+	assign J2MID_EFa_BEG1_input = {JE2END5,S2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG1 (
+	.A0 (J2MID_EFa_BEG1_input[0]),
+	.A1 (J2MID_EFa_BEG1_input[1]),
+	.A2 (J2MID_EFa_BEG1_input[2]),
+	.A3 (J2MID_EFa_BEG1_input[3]),
+	.S0 (ConfigBits[172+0]),
+	.S0N (ConfigBits_N[172+0]),
+	.S1 (ConfigBits[172+1]),
+	.S1N (ConfigBits_N[172+1]),
+	.X (J2MID_EFa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG2 		MUX-4
+	assign J2MID_EFa_BEG2_input = {JS2END5,W2MID4,S2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG2 (
+	.A0 (J2MID_EFa_BEG2_input[0]),
+	.A1 (J2MID_EFa_BEG2_input[1]),
+	.A2 (J2MID_EFa_BEG2_input[2]),
+	.A3 (J2MID_EFa_BEG2_input[3]),
+	.S0 (ConfigBits[174+0]),
+	.S0N (ConfigBits_N[174+0]),
+	.S1 (ConfigBits[174+1]),
+	.S1N (ConfigBits_N[174+1]),
+	.X (J2MID_EFa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG3 		MUX-4
+	assign J2MID_EFa_BEG3_input = {JW2END5,W2MID0,S2MID0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG3 (
+	.A0 (J2MID_EFa_BEG3_input[0]),
+	.A1 (J2MID_EFa_BEG3_input[1]),
+	.A2 (J2MID_EFa_BEG3_input[2]),
+	.A3 (J2MID_EFa_BEG3_input[3]),
+	.S0 (ConfigBits[176+0]),
+	.S0N (ConfigBits_N[176+0]),
+	.S1 (ConfigBits[176+1]),
+	.S1N (ConfigBits_N[176+1]),
+	.X (J2MID_EFa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG0 		MUX-4
+	assign J2MID_GHa_BEG0_input = {JN2END6,S2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG0 (
+	.A0 (J2MID_GHa_BEG0_input[0]),
+	.A1 (J2MID_GHa_BEG0_input[1]),
+	.A2 (J2MID_GHa_BEG0_input[2]),
+	.A3 (J2MID_GHa_BEG0_input[3]),
+	.S0 (ConfigBits[178+0]),
+	.S0N (ConfigBits_N[178+0]),
+	.S1 (ConfigBits[178+1]),
+	.S1N (ConfigBits_N[178+1]),
+	.X (J2MID_GHa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG1 		MUX-4
+	assign J2MID_GHa_BEG1_input = {JE2END6,W2MID2,S2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG1 (
+	.A0 (J2MID_GHa_BEG1_input[0]),
+	.A1 (J2MID_GHa_BEG1_input[1]),
+	.A2 (J2MID_GHa_BEG1_input[2]),
+	.A3 (J2MID_GHa_BEG1_input[3]),
+	.S0 (ConfigBits[180+0]),
+	.S0N (ConfigBits_N[180+0]),
+	.S1 (ConfigBits[180+1]),
+	.S1N (ConfigBits_N[180+1]),
+	.X (J2MID_GHa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG2 		MUX-4
+	assign J2MID_GHa_BEG2_input = {JS2END6,W2MID4,S2MID4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG2 (
+	.A0 (J2MID_GHa_BEG2_input[0]),
+	.A1 (J2MID_GHa_BEG2_input[1]),
+	.A2 (J2MID_GHa_BEG2_input[2]),
+	.A3 (J2MID_GHa_BEG2_input[3]),
+	.S0 (ConfigBits[182+0]),
+	.S0N (ConfigBits_N[182+0]),
+	.S1 (ConfigBits[182+1]),
+	.S1N (ConfigBits_N[182+1]),
+	.X (J2MID_GHa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG3 		MUX-4
+	assign J2MID_GHa_BEG3_input = {JW2END6,W2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG3 (
+	.A0 (J2MID_GHa_BEG3_input[0]),
+	.A1 (J2MID_GHa_BEG3_input[1]),
+	.A2 (J2MID_GHa_BEG3_input[2]),
+	.A3 (J2MID_GHa_BEG3_input[3]),
+	.S0 (ConfigBits[184+0]),
+	.S0N (ConfigBits_N[184+0]),
+	.S1 (ConfigBits[184+1]),
+	.S1N (ConfigBits_N[184+1]),
+	.X (J2MID_GHa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG0 		MUX-4
+	assign J2MID_ABb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG0 (
+	.A0 (J2MID_ABb_BEG0_input[0]),
+	.A1 (J2MID_ABb_BEG0_input[1]),
+	.A2 (J2MID_ABb_BEG0_input[2]),
+	.A3 (J2MID_ABb_BEG0_input[3]),
+	.S0 (ConfigBits[186+0]),
+	.S0N (ConfigBits_N[186+0]),
+	.S1 (ConfigBits[186+1]),
+	.S1N (ConfigBits_N[186+1]),
+	.X (J2MID_ABb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG1 		MUX-4
+	assign J2MID_ABb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG1 (
+	.A0 (J2MID_ABb_BEG1_input[0]),
+	.A1 (J2MID_ABb_BEG1_input[1]),
+	.A2 (J2MID_ABb_BEG1_input[2]),
+	.A3 (J2MID_ABb_BEG1_input[3]),
+	.S0 (ConfigBits[188+0]),
+	.S0N (ConfigBits_N[188+0]),
+	.S1 (ConfigBits[188+1]),
+	.S1N (ConfigBits_N[188+1]),
+	.X (J2MID_ABb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG2 		MUX-4
+	assign J2MID_ABb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG2 (
+	.A0 (J2MID_ABb_BEG2_input[0]),
+	.A1 (J2MID_ABb_BEG2_input[1]),
+	.A2 (J2MID_ABb_BEG2_input[2]),
+	.A3 (J2MID_ABb_BEG2_input[3]),
+	.S0 (ConfigBits[190+0]),
+	.S0N (ConfigBits_N[190+0]),
+	.S1 (ConfigBits[190+1]),
+	.S1N (ConfigBits_N[190+1]),
+	.X (J2MID_ABb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG3 		MUX-4
+	assign J2MID_ABb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG3 (
+	.A0 (J2MID_ABb_BEG3_input[0]),
+	.A1 (J2MID_ABb_BEG3_input[1]),
+	.A2 (J2MID_ABb_BEG3_input[2]),
+	.A3 (J2MID_ABb_BEG3_input[3]),
+	.S0 (ConfigBits[192+0]),
+	.S0N (ConfigBits_N[192+0]),
+	.S1 (ConfigBits[192+1]),
+	.S1N (ConfigBits_N[192+1]),
+	.X (J2MID_ABb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG0 		MUX-4
+	assign J2MID_CDb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG0 (
+	.A0 (J2MID_CDb_BEG0_input[0]),
+	.A1 (J2MID_CDb_BEG0_input[1]),
+	.A2 (J2MID_CDb_BEG0_input[2]),
+	.A3 (J2MID_CDb_BEG0_input[3]),
+	.S0 (ConfigBits[194+0]),
+	.S0N (ConfigBits_N[194+0]),
+	.S1 (ConfigBits[194+1]),
+	.S1N (ConfigBits_N[194+1]),
+	.X (J2MID_CDb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG1 		MUX-4
+	assign J2MID_CDb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG1 (
+	.A0 (J2MID_CDb_BEG1_input[0]),
+	.A1 (J2MID_CDb_BEG1_input[1]),
+	.A2 (J2MID_CDb_BEG1_input[2]),
+	.A3 (J2MID_CDb_BEG1_input[3]),
+	.S0 (ConfigBits[196+0]),
+	.S0N (ConfigBits_N[196+0]),
+	.S1 (ConfigBits[196+1]),
+	.S1N (ConfigBits_N[196+1]),
+	.X (J2MID_CDb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG2 		MUX-4
+	assign J2MID_CDb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG2 (
+	.A0 (J2MID_CDb_BEG2_input[0]),
+	.A1 (J2MID_CDb_BEG2_input[1]),
+	.A2 (J2MID_CDb_BEG2_input[2]),
+	.A3 (J2MID_CDb_BEG2_input[3]),
+	.S0 (ConfigBits[198+0]),
+	.S0N (ConfigBits_N[198+0]),
+	.S1 (ConfigBits[198+1]),
+	.S1N (ConfigBits_N[198+1]),
+	.X (J2MID_CDb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG3 		MUX-4
+	assign J2MID_CDb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG3 (
+	.A0 (J2MID_CDb_BEG3_input[0]),
+	.A1 (J2MID_CDb_BEG3_input[1]),
+	.A2 (J2MID_CDb_BEG3_input[2]),
+	.A3 (J2MID_CDb_BEG3_input[3]),
+	.S0 (ConfigBits[200+0]),
+	.S0N (ConfigBits_N[200+0]),
+	.S1 (ConfigBits[200+1]),
+	.S1N (ConfigBits_N[200+1]),
+	.X (J2MID_CDb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG0 		MUX-4
+	assign J2MID_EFb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG0 (
+	.A0 (J2MID_EFb_BEG0_input[0]),
+	.A1 (J2MID_EFb_BEG0_input[1]),
+	.A2 (J2MID_EFb_BEG0_input[2]),
+	.A3 (J2MID_EFb_BEG0_input[3]),
+	.S0 (ConfigBits[202+0]),
+	.S0N (ConfigBits_N[202+0]),
+	.S1 (ConfigBits[202+1]),
+	.S1N (ConfigBits_N[202+1]),
+	.X (J2MID_EFb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG1 		MUX-4
+	assign J2MID_EFb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG1 (
+	.A0 (J2MID_EFb_BEG1_input[0]),
+	.A1 (J2MID_EFb_BEG1_input[1]),
+	.A2 (J2MID_EFb_BEG1_input[2]),
+	.A3 (J2MID_EFb_BEG1_input[3]),
+	.S0 (ConfigBits[204+0]),
+	.S0N (ConfigBits_N[204+0]),
+	.S1 (ConfigBits[204+1]),
+	.S1N (ConfigBits_N[204+1]),
+	.X (J2MID_EFb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG2 		MUX-4
+	assign J2MID_EFb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG2 (
+	.A0 (J2MID_EFb_BEG2_input[0]),
+	.A1 (J2MID_EFb_BEG2_input[1]),
+	.A2 (J2MID_EFb_BEG2_input[2]),
+	.A3 (J2MID_EFb_BEG2_input[3]),
+	.S0 (ConfigBits[206+0]),
+	.S0N (ConfigBits_N[206+0]),
+	.S1 (ConfigBits[206+1]),
+	.S1N (ConfigBits_N[206+1]),
+	.X (J2MID_EFb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG3 		MUX-4
+	assign J2MID_EFb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG3 (
+	.A0 (J2MID_EFb_BEG3_input[0]),
+	.A1 (J2MID_EFb_BEG3_input[1]),
+	.A2 (J2MID_EFb_BEG3_input[2]),
+	.A3 (J2MID_EFb_BEG3_input[3]),
+	.S0 (ConfigBits[208+0]),
+	.S0N (ConfigBits_N[208+0]),
+	.S1 (ConfigBits[208+1]),
+	.S1N (ConfigBits_N[208+1]),
+	.X (J2MID_EFb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG0 		MUX-4
+	assign J2MID_GHb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG0 (
+	.A0 (J2MID_GHb_BEG0_input[0]),
+	.A1 (J2MID_GHb_BEG0_input[1]),
+	.A2 (J2MID_GHb_BEG0_input[2]),
+	.A3 (J2MID_GHb_BEG0_input[3]),
+	.S0 (ConfigBits[210+0]),
+	.S0N (ConfigBits_N[210+0]),
+	.S1 (ConfigBits[210+1]),
+	.S1N (ConfigBits_N[210+1]),
+	.X (J2MID_GHb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG1 		MUX-4
+	assign J2MID_GHb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG1 (
+	.A0 (J2MID_GHb_BEG1_input[0]),
+	.A1 (J2MID_GHb_BEG1_input[1]),
+	.A2 (J2MID_GHb_BEG1_input[2]),
+	.A3 (J2MID_GHb_BEG1_input[3]),
+	.S0 (ConfigBits[212+0]),
+	.S0N (ConfigBits_N[212+0]),
+	.S1 (ConfigBits[212+1]),
+	.S1N (ConfigBits_N[212+1]),
+	.X (J2MID_GHb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG2 		MUX-4
+	assign J2MID_GHb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG2 (
+	.A0 (J2MID_GHb_BEG2_input[0]),
+	.A1 (J2MID_GHb_BEG2_input[1]),
+	.A2 (J2MID_GHb_BEG2_input[2]),
+	.A3 (J2MID_GHb_BEG2_input[3]),
+	.S0 (ConfigBits[214+0]),
+	.S0N (ConfigBits_N[214+0]),
+	.S1 (ConfigBits[214+1]),
+	.S1N (ConfigBits_N[214+1]),
+	.X (J2MID_GHb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG3 		MUX-4
+	assign J2MID_GHb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG3 (
+	.A0 (J2MID_GHb_BEG3_input[0]),
+	.A1 (J2MID_GHb_BEG3_input[1]),
+	.A2 (J2MID_GHb_BEG3_input[2]),
+	.A3 (J2MID_GHb_BEG3_input[3]),
+	.S0 (ConfigBits[216+0]),
+	.S0N (ConfigBits_N[216+0]),
+	.S1 (ConfigBits[216+1]),
+	.S1N (ConfigBits_N[216+1]),
+	.X (J2MID_GHb_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG0 		MUX-4
+	assign J2END_AB_BEG0_input = {W2END6,SS4END3,E2END6,N2END6};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG0 (
+	.A0 (J2END_AB_BEG0_input[0]),
+	.A1 (J2END_AB_BEG0_input[1]),
+	.A2 (J2END_AB_BEG0_input[2]),
+	.A3 (J2END_AB_BEG0_input[3]),
+	.S0 (ConfigBits[218+0]),
+	.S0N (ConfigBits_N[218+0]),
+	.S1 (ConfigBits[218+1]),
+	.S1N (ConfigBits_N[218+1]),
+	.X (J2END_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG1 		MUX-4
+	assign J2END_AB_BEG1_input = {W2END2,S2END2,E2END2,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG1 (
+	.A0 (J2END_AB_BEG1_input[0]),
+	.A1 (J2END_AB_BEG1_input[1]),
+	.A2 (J2END_AB_BEG1_input[2]),
+	.A3 (J2END_AB_BEG1_input[3]),
+	.S0 (ConfigBits[220+0]),
+	.S0N (ConfigBits_N[220+0]),
+	.S1 (ConfigBits[220+1]),
+	.S1N (ConfigBits_N[220+1]),
+	.X (J2END_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG2 		MUX-4
+	assign J2END_AB_BEG2_input = {W2END4,S2END4,EE4END0,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG2 (
+	.A0 (J2END_AB_BEG2_input[0]),
+	.A1 (J2END_AB_BEG2_input[1]),
+	.A2 (J2END_AB_BEG2_input[2]),
+	.A3 (J2END_AB_BEG2_input[3]),
+	.S0 (ConfigBits[222+0]),
+	.S0N (ConfigBits_N[222+0]),
+	.S1 (ConfigBits[222+1]),
+	.S1N (ConfigBits_N[222+1]),
+	.X (J2END_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG3 		MUX-4
+	assign J2END_AB_BEG3_input = {WW4END3,S2END0,E2END0,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG3 (
+	.A0 (J2END_AB_BEG3_input[0]),
+	.A1 (J2END_AB_BEG3_input[1]),
+	.A2 (J2END_AB_BEG3_input[2]),
+	.A3 (J2END_AB_BEG3_input[3]),
+	.S0 (ConfigBits[224+0]),
+	.S0N (ConfigBits_N[224+0]),
+	.S1 (ConfigBits[224+1]),
+	.S1N (ConfigBits_N[224+1]),
+	.X (J2END_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG0 		MUX-4
+	assign J2END_CD_BEG0_input = {W2END6,S2END6,E2END6,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG0 (
+	.A0 (J2END_CD_BEG0_input[0]),
+	.A1 (J2END_CD_BEG0_input[1]),
+	.A2 (J2END_CD_BEG0_input[2]),
+	.A3 (J2END_CD_BEG0_input[3]),
+	.S0 (ConfigBits[226+0]),
+	.S0N (ConfigBits_N[226+0]),
+	.S1 (ConfigBits[226+1]),
+	.S1N (ConfigBits_N[226+1]),
+	.X (J2END_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG1 		MUX-4
+	assign J2END_CD_BEG1_input = {WW4END2,S2END2,E2END2,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG1 (
+	.A0 (J2END_CD_BEG1_input[0]),
+	.A1 (J2END_CD_BEG1_input[1]),
+	.A2 (J2END_CD_BEG1_input[2]),
+	.A3 (J2END_CD_BEG1_input[3]),
+	.S0 (ConfigBits[228+0]),
+	.S0N (ConfigBits_N[228+0]),
+	.S1 (ConfigBits[228+1]),
+	.S1N (ConfigBits_N[228+1]),
+	.X (J2END_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG2 		MUX-4
+	assign J2END_CD_BEG2_input = {W2END4,SS4END2,E2END4,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG2 (
+	.A0 (J2END_CD_BEG2_input[0]),
+	.A1 (J2END_CD_BEG2_input[1]),
+	.A2 (J2END_CD_BEG2_input[2]),
+	.A3 (J2END_CD_BEG2_input[3]),
+	.S0 (ConfigBits[230+0]),
+	.S0N (ConfigBits_N[230+0]),
+	.S1 (ConfigBits[230+1]),
+	.S1N (ConfigBits_N[230+1]),
+	.X (J2END_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG3 		MUX-4
+	assign J2END_CD_BEG3_input = {W2END0,S2END0,EE4END1,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG3 (
+	.A0 (J2END_CD_BEG3_input[0]),
+	.A1 (J2END_CD_BEG3_input[1]),
+	.A2 (J2END_CD_BEG3_input[2]),
+	.A3 (J2END_CD_BEG3_input[3]),
+	.S0 (ConfigBits[232+0]),
+	.S0N (ConfigBits_N[232+0]),
+	.S1 (ConfigBits[232+1]),
+	.S1N (ConfigBits_N[232+1]),
+	.X (J2END_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG0 		MUX-4
+	assign J2END_EF_BEG0_input = {W2END7,S2END7,EE4END2,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG0 (
+	.A0 (J2END_EF_BEG0_input[0]),
+	.A1 (J2END_EF_BEG0_input[1]),
+	.A2 (J2END_EF_BEG0_input[2]),
+	.A3 (J2END_EF_BEG0_input[3]),
+	.S0 (ConfigBits[234+0]),
+	.S0N (ConfigBits_N[234+0]),
+	.S1 (ConfigBits[234+1]),
+	.S1N (ConfigBits_N[234+1]),
+	.X (J2END_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG1 		MUX-4
+	assign J2END_EF_BEG1_input = {WW4END1,S2END3,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG1 (
+	.A0 (J2END_EF_BEG1_input[0]),
+	.A1 (J2END_EF_BEG1_input[1]),
+	.A2 (J2END_EF_BEG1_input[2]),
+	.A3 (J2END_EF_BEG1_input[3]),
+	.S0 (ConfigBits[236+0]),
+	.S0N (ConfigBits_N[236+0]),
+	.S1 (ConfigBits[236+1]),
+	.S1N (ConfigBits_N[236+1]),
+	.X (J2END_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG2 		MUX-4
+	assign J2END_EF_BEG2_input = {W2END5,SS4END1,E2END5,N2END5};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG2 (
+	.A0 (J2END_EF_BEG2_input[0]),
+	.A1 (J2END_EF_BEG2_input[1]),
+	.A2 (J2END_EF_BEG2_input[2]),
+	.A3 (J2END_EF_BEG2_input[3]),
+	.S0 (ConfigBits[238+0]),
+	.S0N (ConfigBits_N[238+0]),
+	.S1 (ConfigBits[238+1]),
+	.S1N (ConfigBits_N[238+1]),
+	.X (J2END_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG3 		MUX-4
+	assign J2END_EF_BEG3_input = {W2END1,S2END1,E2END1,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG3 (
+	.A0 (J2END_EF_BEG3_input[0]),
+	.A1 (J2END_EF_BEG3_input[1]),
+	.A2 (J2END_EF_BEG3_input[2]),
+	.A3 (J2END_EF_BEG3_input[3]),
+	.S0 (ConfigBits[240+0]),
+	.S0N (ConfigBits_N[240+0]),
+	.S1 (ConfigBits[240+1]),
+	.S1N (ConfigBits_N[240+1]),
+	.X (J2END_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG0 		MUX-4
+	assign J2END_GH_BEG0_input = {WW4END0,S2END7,E2END7,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG0 (
+	.A0 (J2END_GH_BEG0_input[0]),
+	.A1 (J2END_GH_BEG0_input[1]),
+	.A2 (J2END_GH_BEG0_input[2]),
+	.A3 (J2END_GH_BEG0_input[3]),
+	.S0 (ConfigBits[242+0]),
+	.S0N (ConfigBits_N[242+0]),
+	.S1 (ConfigBits[242+1]),
+	.S1N (ConfigBits_N[242+1]),
+	.X (J2END_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG1 		MUX-4
+	assign J2END_GH_BEG1_input = {W2END3,SS4END0,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG1 (
+	.A0 (J2END_GH_BEG1_input[0]),
+	.A1 (J2END_GH_BEG1_input[1]),
+	.A2 (J2END_GH_BEG1_input[2]),
+	.A3 (J2END_GH_BEG1_input[3]),
+	.S0 (ConfigBits[244+0]),
+	.S0N (ConfigBits_N[244+0]),
+	.S1 (ConfigBits[244+1]),
+	.S1N (ConfigBits_N[244+1]),
+	.X (J2END_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG2 		MUX-4
+	assign J2END_GH_BEG2_input = {W2END5,S2END5,E2END5,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG2 (
+	.A0 (J2END_GH_BEG2_input[0]),
+	.A1 (J2END_GH_BEG2_input[1]),
+	.A2 (J2END_GH_BEG2_input[2]),
+	.A3 (J2END_GH_BEG2_input[3]),
+	.S0 (ConfigBits[246+0]),
+	.S0N (ConfigBits_N[246+0]),
+	.S1 (ConfigBits[246+1]),
+	.S1N (ConfigBits_N[246+1]),
+	.X (J2END_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG3 		MUX-4
+	assign J2END_GH_BEG3_input = {W2END1,S2END1,EE4END3,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG3 (
+	.A0 (J2END_GH_BEG3_input[0]),
+	.A1 (J2END_GH_BEG3_input[1]),
+	.A2 (J2END_GH_BEG3_input[2]),
+	.A3 (J2END_GH_BEG3_input[3]),
+	.S0 (ConfigBits[248+0]),
+	.S0N (ConfigBits_N[248+0]),
+	.S1 (ConfigBits[248+1]),
+	.S1N (ConfigBits_N[248+1]),
+	.X (J2END_GH_BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG0 		MUX-16
+	assign JN2BEG0_input = {Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,W6END1,W2END1,SS4END1,E6END1,E2END1,E1END3,N4END1,N2END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG0 (
+	.A0 (JN2BEG0_input[0]),
+	.A1 (JN2BEG0_input[1]),
+	.A2 (JN2BEG0_input[2]),
+	.A3 (JN2BEG0_input[3]),
+	.A4 (JN2BEG0_input[4]),
+	.A5 (JN2BEG0_input[5]),
+	.A6 (JN2BEG0_input[6]),
+	.A7 (JN2BEG0_input[7]),
+	.A8 (JN2BEG0_input[8]),
+	.A9 (JN2BEG0_input[9]),
+	.A10 (JN2BEG0_input[10]),
+	.A11 (JN2BEG0_input[11]),
+	.A12 (JN2BEG0_input[12]),
+	.A13 (JN2BEG0_input[13]),
+	.A14 (JN2BEG0_input[14]),
+	.A15 (JN2BEG0_input[15]),
+	.S0 (ConfigBits[250+0]),
+	.S0N (ConfigBits_N[250+0]),
+	.S1 (ConfigBits[250+1]),
+	.S1N (ConfigBits_N[250+1]),
+	.S2 (ConfigBits[250+2]),
+	.S2N (ConfigBits_N[250+2]),
+	.S3 (ConfigBits[250+3]),
+	.S3N (ConfigBits_N[250+3]),
+	.X (JN2BEG0)
+	);
+
+// switch matrix multiplexer  JN2BEG1 		MUX-16
+	assign JN2BEG1_input = {Q0,Q2,Q3,Q4,Q5,Q6,Q7,Q9,W6END0,W2END2,S2END2,E6END0,E2END2,E1END0,N4END2,N2END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG1 (
+	.A0 (JN2BEG1_input[0]),
+	.A1 (JN2BEG1_input[1]),
+	.A2 (JN2BEG1_input[2]),
+	.A3 (JN2BEG1_input[3]),
+	.A4 (JN2BEG1_input[4]),
+	.A5 (JN2BEG1_input[5]),
+	.A6 (JN2BEG1_input[6]),
+	.A7 (JN2BEG1_input[7]),
+	.A8 (JN2BEG1_input[8]),
+	.A9 (JN2BEG1_input[9]),
+	.A10 (JN2BEG1_input[10]),
+	.A11 (JN2BEG1_input[11]),
+	.A12 (JN2BEG1_input[12]),
+	.A13 (JN2BEG1_input[13]),
+	.A14 (JN2BEG1_input[14]),
+	.A15 (JN2BEG1_input[15]),
+	.S0 (ConfigBits[254+0]),
+	.S0N (ConfigBits_N[254+0]),
+	.S1 (ConfigBits[254+1]),
+	.S1N (ConfigBits_N[254+1]),
+	.S2 (ConfigBits[254+2]),
+	.S2N (ConfigBits_N[254+2]),
+	.S3 (ConfigBits[254+3]),
+	.S3N (ConfigBits_N[254+3]),
+	.X (JN2BEG1)
+	);
+
+// switch matrix multiplexer  JN2BEG2 		MUX-16
+	assign JN2BEG2_input = {Q0,Q1,Q3,Q4,Q5,Q6,Q7,Q8,WW4END1,W2END3,S2END3,E6END1,E2END3,E1END1,N4END3,N2END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG2 (
+	.A0 (JN2BEG2_input[0]),
+	.A1 (JN2BEG2_input[1]),
+	.A2 (JN2BEG2_input[2]),
+	.A3 (JN2BEG2_input[3]),
+	.A4 (JN2BEG2_input[4]),
+	.A5 (JN2BEG2_input[5]),
+	.A6 (JN2BEG2_input[6]),
+	.A7 (JN2BEG2_input[7]),
+	.A8 (JN2BEG2_input[8]),
+	.A9 (JN2BEG2_input[9]),
+	.A10 (JN2BEG2_input[10]),
+	.A11 (JN2BEG2_input[11]),
+	.A12 (JN2BEG2_input[12]),
+	.A13 (JN2BEG2_input[13]),
+	.A14 (JN2BEG2_input[14]),
+	.A15 (JN2BEG2_input[15]),
+	.S0 (ConfigBits[258+0]),
+	.S0N (ConfigBits_N[258+0]),
+	.S1 (ConfigBits[258+1]),
+	.S1N (ConfigBits_N[258+1]),
+	.S2 (ConfigBits[258+2]),
+	.S2N (ConfigBits_N[258+2]),
+	.S3 (ConfigBits[258+3]),
+	.S3N (ConfigBits_N[258+3]),
+	.X (JN2BEG2)
+	);
+
+// switch matrix multiplexer  JN2BEG3 		MUX-16
+	assign JN2BEG3_input = {Q0,Q1,Q2,Q4,Q5,Q6,Q7,Q9,W6END0,W2END4,S2END4,E6END0,E2END4,E1END2,N4END0,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG3 (
+	.A0 (JN2BEG3_input[0]),
+	.A1 (JN2BEG3_input[1]),
+	.A2 (JN2BEG3_input[2]),
+	.A3 (JN2BEG3_input[3]),
+	.A4 (JN2BEG3_input[4]),
+	.A5 (JN2BEG3_input[5]),
+	.A6 (JN2BEG3_input[6]),
+	.A7 (JN2BEG3_input[7]),
+	.A8 (JN2BEG3_input[8]),
+	.A9 (JN2BEG3_input[9]),
+	.A10 (JN2BEG3_input[10]),
+	.A11 (JN2BEG3_input[11]),
+	.A12 (JN2BEG3_input[12]),
+	.A13 (JN2BEG3_input[13]),
+	.A14 (JN2BEG3_input[14]),
+	.A15 (JN2BEG3_input[15]),
+	.S0 (ConfigBits[262+0]),
+	.S0N (ConfigBits_N[262+0]),
+	.S1 (ConfigBits[262+1]),
+	.S1N (ConfigBits_N[262+1]),
+	.S2 (ConfigBits[262+2]),
+	.S2N (ConfigBits_N[262+2]),
+	.S3 (ConfigBits[262+3]),
+	.S3N (ConfigBits_N[262+3]),
+	.X (JN2BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG4 		MUX-16
+	assign JN2BEG4_input = {Q0,Q1,Q2,Q3,Q5,Q6,Q7,Q8,W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG4 (
+	.A0 (JN2BEG4_input[0]),
+	.A1 (JN2BEG4_input[1]),
+	.A2 (JN2BEG4_input[2]),
+	.A3 (JN2BEG4_input[3]),
+	.A4 (JN2BEG4_input[4]),
+	.A5 (JN2BEG4_input[5]),
+	.A6 (JN2BEG4_input[6]),
+	.A7 (JN2BEG4_input[7]),
+	.A8 (JN2BEG4_input[8]),
+	.A9 (JN2BEG4_input[9]),
+	.A10 (JN2BEG4_input[10]),
+	.A11 (JN2BEG4_input[11]),
+	.A12 (JN2BEG4_input[12]),
+	.A13 (JN2BEG4_input[13]),
+	.A14 (JN2BEG4_input[14]),
+	.A15 (JN2BEG4_input[15]),
+	.S0 (ConfigBits[266+0]),
+	.S0N (ConfigBits_N[266+0]),
+	.S1 (ConfigBits[266+1]),
+	.S1N (ConfigBits_N[266+1]),
+	.S2 (ConfigBits[266+2]),
+	.S2N (ConfigBits_N[266+2]),
+	.S3 (ConfigBits[266+3]),
+	.S3N (ConfigBits_N[266+3]),
+	.X (JN2BEG4)
+	);
+
+// switch matrix multiplexer  JN2BEG5 		MUX-16
+	assign JN2BEG5_input = {Q0,Q1,Q2,Q3,Q4,Q6,Q7,Q9,W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG5 (
+	.A0 (JN2BEG5_input[0]),
+	.A1 (JN2BEG5_input[1]),
+	.A2 (JN2BEG5_input[2]),
+	.A3 (JN2BEG5_input[3]),
+	.A4 (JN2BEG5_input[4]),
+	.A5 (JN2BEG5_input[5]),
+	.A6 (JN2BEG5_input[6]),
+	.A7 (JN2BEG5_input[7]),
+	.A8 (JN2BEG5_input[8]),
+	.A9 (JN2BEG5_input[9]),
+	.A10 (JN2BEG5_input[10]),
+	.A11 (JN2BEG5_input[11]),
+	.A12 (JN2BEG5_input[12]),
+	.A13 (JN2BEG5_input[13]),
+	.A14 (JN2BEG5_input[14]),
+	.A15 (JN2BEG5_input[15]),
+	.S0 (ConfigBits[270+0]),
+	.S0N (ConfigBits_N[270+0]),
+	.S1 (ConfigBits[270+1]),
+	.S1N (ConfigBits_N[270+1]),
+	.S2 (ConfigBits[270+2]),
+	.S2N (ConfigBits_N[270+2]),
+	.S3 (ConfigBits[270+3]),
+	.S3N (ConfigBits_N[270+3]),
+	.X (JN2BEG5)
+	);
+
+// switch matrix multiplexer  JN2BEG6 		MUX-16
+	assign JN2BEG6_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q7,Q8,W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG6 (
+	.A0 (JN2BEG6_input[0]),
+	.A1 (JN2BEG6_input[1]),
+	.A2 (JN2BEG6_input[2]),
+	.A3 (JN2BEG6_input[3]),
+	.A4 (JN2BEG6_input[4]),
+	.A5 (JN2BEG6_input[5]),
+	.A6 (JN2BEG6_input[6]),
+	.A7 (JN2BEG6_input[7]),
+	.A8 (JN2BEG6_input[8]),
+	.A9 (JN2BEG6_input[9]),
+	.A10 (JN2BEG6_input[10]),
+	.A11 (JN2BEG6_input[11]),
+	.A12 (JN2BEG6_input[12]),
+	.A13 (JN2BEG6_input[13]),
+	.A14 (JN2BEG6_input[14]),
+	.A15 (JN2BEG6_input[15]),
+	.S0 (ConfigBits[274+0]),
+	.S0N (ConfigBits_N[274+0]),
+	.S1 (ConfigBits[274+1]),
+	.S1N (ConfigBits_N[274+1]),
+	.S2 (ConfigBits[274+2]),
+	.S2N (ConfigBits_N[274+2]),
+	.S3 (ConfigBits[274+3]),
+	.S3N (ConfigBits_N[274+3]),
+	.X (JN2BEG6)
+	);
+
+// switch matrix multiplexer  JN2BEG7 		MUX-16
+	assign JN2BEG7_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q9,W1END2,W1END0,S2END0,S1END0,EE4END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG7 (
+	.A0 (JN2BEG7_input[0]),
+	.A1 (JN2BEG7_input[1]),
+	.A2 (JN2BEG7_input[2]),
+	.A3 (JN2BEG7_input[3]),
+	.A4 (JN2BEG7_input[4]),
+	.A5 (JN2BEG7_input[5]),
+	.A6 (JN2BEG7_input[6]),
+	.A7 (JN2BEG7_input[7]),
+	.A8 (JN2BEG7_input[8]),
+	.A9 (JN2BEG7_input[9]),
+	.A10 (JN2BEG7_input[10]),
+	.A11 (JN2BEG7_input[11]),
+	.A12 (JN2BEG7_input[12]),
+	.A13 (JN2BEG7_input[13]),
+	.A14 (JN2BEG7_input[14]),
+	.A15 (JN2BEG7_input[15]),
+	.S0 (ConfigBits[278+0]),
+	.S0N (ConfigBits_N[278+0]),
+	.S1 (ConfigBits[278+1]),
+	.S1N (ConfigBits_N[278+1]),
+	.S2 (ConfigBits[278+2]),
+	.S2N (ConfigBits_N[278+2]),
+	.S3 (ConfigBits[278+3]),
+	.S3N (ConfigBits_N[278+3]),
+	.X (JN2BEG7)
+	);
+
+// switch matrix multiplexer  JE2BEG0 		MUX-16
+	assign JE2BEG0_input = {Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q9,W6END1,W2END1,S2END1,E6END1,EE4END1,N4END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG0 (
+	.A0 (JE2BEG0_input[0]),
+	.A1 (JE2BEG0_input[1]),
+	.A2 (JE2BEG0_input[2]),
+	.A3 (JE2BEG0_input[3]),
+	.A4 (JE2BEG0_input[4]),
+	.A5 (JE2BEG0_input[5]),
+	.A6 (JE2BEG0_input[6]),
+	.A7 (JE2BEG0_input[7]),
+	.A8 (JE2BEG0_input[8]),
+	.A9 (JE2BEG0_input[9]),
+	.A10 (JE2BEG0_input[10]),
+	.A11 (JE2BEG0_input[11]),
+	.A12 (JE2BEG0_input[12]),
+	.A13 (JE2BEG0_input[13]),
+	.A14 (JE2BEG0_input[14]),
+	.A15 (JE2BEG0_input[15]),
+	.S0 (ConfigBits[282+0]),
+	.S0N (ConfigBits_N[282+0]),
+	.S1 (ConfigBits[282+1]),
+	.S1N (ConfigBits_N[282+1]),
+	.S2 (ConfigBits[282+2]),
+	.S2N (ConfigBits_N[282+2]),
+	.S3 (ConfigBits[282+3]),
+	.S3N (ConfigBits_N[282+3]),
+	.X (JE2BEG0)
+	);
+
+// switch matrix multiplexer  JE2BEG1 		MUX-16
+	assign JE2BEG1_input = {Q0,Q2,Q3,Q4,Q5,Q6,Q7,Q8,WW4END3,W2END2,S2END2,E6END0,E2END2,N4END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG1 (
+	.A0 (JE2BEG1_input[0]),
+	.A1 (JE2BEG1_input[1]),
+	.A2 (JE2BEG1_input[2]),
+	.A3 (JE2BEG1_input[3]),
+	.A4 (JE2BEG1_input[4]),
+	.A5 (JE2BEG1_input[5]),
+	.A6 (JE2BEG1_input[6]),
+	.A7 (JE2BEG1_input[7]),
+	.A8 (JE2BEG1_input[8]),
+	.A9 (JE2BEG1_input[9]),
+	.A10 (JE2BEG1_input[10]),
+	.A11 (JE2BEG1_input[11]),
+	.A12 (JE2BEG1_input[12]),
+	.A13 (JE2BEG1_input[13]),
+	.A14 (JE2BEG1_input[14]),
+	.A15 (JE2BEG1_input[15]),
+	.S0 (ConfigBits[286+0]),
+	.S0N (ConfigBits_N[286+0]),
+	.S1 (ConfigBits[286+1]),
+	.S1N (ConfigBits_N[286+1]),
+	.S2 (ConfigBits[286+2]),
+	.S2N (ConfigBits_N[286+2]),
+	.S3 (ConfigBits[286+3]),
+	.S3N (ConfigBits_N[286+3]),
+	.X (JE2BEG1)
+	);
+
+// switch matrix multiplexer  JE2BEG2 		MUX-16
+	assign JE2BEG2_input = {Q0,Q1,Q3,Q4,Q5,Q6,Q7,Q9,W6END1,W2END3,S2END3,E6END1,E2END3,N4END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG2 (
+	.A0 (JE2BEG2_input[0]),
+	.A1 (JE2BEG2_input[1]),
+	.A2 (JE2BEG2_input[2]),
+	.A3 (JE2BEG2_input[3]),
+	.A4 (JE2BEG2_input[4]),
+	.A5 (JE2BEG2_input[5]),
+	.A6 (JE2BEG2_input[6]),
+	.A7 (JE2BEG2_input[7]),
+	.A8 (JE2BEG2_input[8]),
+	.A9 (JE2BEG2_input[9]),
+	.A10 (JE2BEG2_input[10]),
+	.A11 (JE2BEG2_input[11]),
+	.A12 (JE2BEG2_input[12]),
+	.A13 (JE2BEG2_input[13]),
+	.A14 (JE2BEG2_input[14]),
+	.A15 (JE2BEG2_input[15]),
+	.S0 (ConfigBits[290+0]),
+	.S0N (ConfigBits_N[290+0]),
+	.S1 (ConfigBits[290+1]),
+	.S1N (ConfigBits_N[290+1]),
+	.S2 (ConfigBits[290+2]),
+	.S2N (ConfigBits_N[290+2]),
+	.S3 (ConfigBits[290+3]),
+	.S3N (ConfigBits_N[290+3]),
+	.X (JE2BEG2)
+	);
+
+// switch matrix multiplexer  JE2BEG3 		MUX-16
+	assign JE2BEG3_input = {Q0,Q1,Q2,Q4,Q5,Q6,Q7,Q8,W6END0,W2END4,S2END4,E6END0,E2END4,N4END0,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG3 (
+	.A0 (JE2BEG3_input[0]),
+	.A1 (JE2BEG3_input[1]),
+	.A2 (JE2BEG3_input[2]),
+	.A3 (JE2BEG3_input[3]),
+	.A4 (JE2BEG3_input[4]),
+	.A5 (JE2BEG3_input[5]),
+	.A6 (JE2BEG3_input[6]),
+	.A7 (JE2BEG3_input[7]),
+	.A8 (JE2BEG3_input[8]),
+	.A9 (JE2BEG3_input[9]),
+	.A10 (JE2BEG3_input[10]),
+	.A11 (JE2BEG3_input[11]),
+	.A12 (JE2BEG3_input[12]),
+	.A13 (JE2BEG3_input[13]),
+	.A14 (JE2BEG3_input[14]),
+	.A15 (JE2BEG3_input[15]),
+	.S0 (ConfigBits[294+0]),
+	.S0N (ConfigBits_N[294+0]),
+	.S1 (ConfigBits[294+1]),
+	.S1N (ConfigBits_N[294+1]),
+	.S2 (ConfigBits[294+2]),
+	.S2N (ConfigBits_N[294+2]),
+	.S3 (ConfigBits[294+3]),
+	.S3N (ConfigBits_N[294+3]),
+	.X (JE2BEG3)
+	);
+
+// switch matrix multiplexer  JE2BEG4 		MUX-16
+	assign JE2BEG4_input = {Q0,Q1,Q2,Q3,Q5,Q6,Q7,Q9,W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG4 (
+	.A0 (JE2BEG4_input[0]),
+	.A1 (JE2BEG4_input[1]),
+	.A2 (JE2BEG4_input[2]),
+	.A3 (JE2BEG4_input[3]),
+	.A4 (JE2BEG4_input[4]),
+	.A5 (JE2BEG4_input[5]),
+	.A6 (JE2BEG4_input[6]),
+	.A7 (JE2BEG4_input[7]),
+	.A8 (JE2BEG4_input[8]),
+	.A9 (JE2BEG4_input[9]),
+	.A10 (JE2BEG4_input[10]),
+	.A11 (JE2BEG4_input[11]),
+	.A12 (JE2BEG4_input[12]),
+	.A13 (JE2BEG4_input[13]),
+	.A14 (JE2BEG4_input[14]),
+	.A15 (JE2BEG4_input[15]),
+	.S0 (ConfigBits[298+0]),
+	.S0N (ConfigBits_N[298+0]),
+	.S1 (ConfigBits[298+1]),
+	.S1N (ConfigBits_N[298+1]),
+	.S2 (ConfigBits[298+2]),
+	.S2N (ConfigBits_N[298+2]),
+	.S3 (ConfigBits[298+3]),
+	.S3N (ConfigBits_N[298+3]),
+	.X (JE2BEG4)
+	);
+
+// switch matrix multiplexer  JE2BEG5 		MUX-16
+	assign JE2BEG5_input = {Q0,Q1,Q2,Q3,Q4,Q6,Q7,Q8,W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG5 (
+	.A0 (JE2BEG5_input[0]),
+	.A1 (JE2BEG5_input[1]),
+	.A2 (JE2BEG5_input[2]),
+	.A3 (JE2BEG5_input[3]),
+	.A4 (JE2BEG5_input[4]),
+	.A5 (JE2BEG5_input[5]),
+	.A6 (JE2BEG5_input[6]),
+	.A7 (JE2BEG5_input[7]),
+	.A8 (JE2BEG5_input[8]),
+	.A9 (JE2BEG5_input[9]),
+	.A10 (JE2BEG5_input[10]),
+	.A11 (JE2BEG5_input[11]),
+	.A12 (JE2BEG5_input[12]),
+	.A13 (JE2BEG5_input[13]),
+	.A14 (JE2BEG5_input[14]),
+	.A15 (JE2BEG5_input[15]),
+	.S0 (ConfigBits[302+0]),
+	.S0N (ConfigBits_N[302+0]),
+	.S1 (ConfigBits[302+1]),
+	.S1N (ConfigBits_N[302+1]),
+	.S2 (ConfigBits[302+2]),
+	.S2N (ConfigBits_N[302+2]),
+	.S3 (ConfigBits[302+3]),
+	.S3N (ConfigBits_N[302+3]),
+	.X (JE2BEG5)
+	);
+
+// switch matrix multiplexer  JE2BEG6 		MUX-16
+	assign JE2BEG6_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q7,Q9,W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG6 (
+	.A0 (JE2BEG6_input[0]),
+	.A1 (JE2BEG6_input[1]),
+	.A2 (JE2BEG6_input[2]),
+	.A3 (JE2BEG6_input[3]),
+	.A4 (JE2BEG6_input[4]),
+	.A5 (JE2BEG6_input[5]),
+	.A6 (JE2BEG6_input[6]),
+	.A7 (JE2BEG6_input[7]),
+	.A8 (JE2BEG6_input[8]),
+	.A9 (JE2BEG6_input[9]),
+	.A10 (JE2BEG6_input[10]),
+	.A11 (JE2BEG6_input[11]),
+	.A12 (JE2BEG6_input[12]),
+	.A13 (JE2BEG6_input[13]),
+	.A14 (JE2BEG6_input[14]),
+	.A15 (JE2BEG6_input[15]),
+	.S0 (ConfigBits[306+0]),
+	.S0N (ConfigBits_N[306+0]),
+	.S1 (ConfigBits[306+1]),
+	.S1N (ConfigBits_N[306+1]),
+	.S2 (ConfigBits[306+2]),
+	.S2N (ConfigBits_N[306+2]),
+	.S3 (ConfigBits[306+3]),
+	.S3N (ConfigBits_N[306+3]),
+	.X (JE2BEG6)
+	);
+
+// switch matrix multiplexer  JE2BEG7 		MUX-16
+	assign JE2BEG7_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q8,WW4END0,SS4END0,S1END2,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG7 (
+	.A0 (JE2BEG7_input[0]),
+	.A1 (JE2BEG7_input[1]),
+	.A2 (JE2BEG7_input[2]),
+	.A3 (JE2BEG7_input[3]),
+	.A4 (JE2BEG7_input[4]),
+	.A5 (JE2BEG7_input[5]),
+	.A6 (JE2BEG7_input[6]),
+	.A7 (JE2BEG7_input[7]),
+	.A8 (JE2BEG7_input[8]),
+	.A9 (JE2BEG7_input[9]),
+	.A10 (JE2BEG7_input[10]),
+	.A11 (JE2BEG7_input[11]),
+	.A12 (JE2BEG7_input[12]),
+	.A13 (JE2BEG7_input[13]),
+	.A14 (JE2BEG7_input[14]),
+	.A15 (JE2BEG7_input[15]),
+	.S0 (ConfigBits[310+0]),
+	.S0N (ConfigBits_N[310+0]),
+	.S1 (ConfigBits[310+1]),
+	.S1N (ConfigBits_N[310+1]),
+	.S2 (ConfigBits[310+2]),
+	.S2N (ConfigBits_N[310+2]),
+	.S3 (ConfigBits[310+3]),
+	.S3N (ConfigBits_N[310+3]),
+	.X (JE2BEG7)
+	);
+
+// switch matrix multiplexer  JS2BEG0 		MUX-16
+	assign JS2BEG0_input = {Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,E1END3,NN4END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG0 (
+	.A0 (JS2BEG0_input[0]),
+	.A1 (JS2BEG0_input[1]),
+	.A2 (JS2BEG0_input[2]),
+	.A3 (JS2BEG0_input[3]),
+	.A4 (JS2BEG0_input[4]),
+	.A5 (JS2BEG0_input[5]),
+	.A6 (JS2BEG0_input[6]),
+	.A7 (JS2BEG0_input[7]),
+	.A8 (JS2BEG0_input[8]),
+	.A9 (JS2BEG0_input[9]),
+	.A10 (JS2BEG0_input[10]),
+	.A11 (JS2BEG0_input[11]),
+	.A12 (JS2BEG0_input[12]),
+	.A13 (JS2BEG0_input[13]),
+	.A14 (JS2BEG0_input[14]),
+	.A15 (JS2BEG0_input[15]),
+	.S0 (ConfigBits[314+0]),
+	.S0N (ConfigBits_N[314+0]),
+	.S1 (ConfigBits[314+1]),
+	.S1N (ConfigBits_N[314+1]),
+	.S2 (ConfigBits[314+2]),
+	.S2N (ConfigBits_N[314+2]),
+	.S3 (ConfigBits[314+3]),
+	.S3N (ConfigBits_N[314+3]),
+	.X (JS2BEG0)
+	);
+
+// switch matrix multiplexer  JS2BEG1 		MUX-16
+	assign JS2BEG1_input = {Q0,Q2,Q3,Q4,Q5,Q6,Q7,Q9,W6END0,W2END2,SS4END2,S4END2,E6END0,EE4END2,E1END0,NN4END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG1 (
+	.A0 (JS2BEG1_input[0]),
+	.A1 (JS2BEG1_input[1]),
+	.A2 (JS2BEG1_input[2]),
+	.A3 (JS2BEG1_input[3]),
+	.A4 (JS2BEG1_input[4]),
+	.A5 (JS2BEG1_input[5]),
+	.A6 (JS2BEG1_input[6]),
+	.A7 (JS2BEG1_input[7]),
+	.A8 (JS2BEG1_input[8]),
+	.A9 (JS2BEG1_input[9]),
+	.A10 (JS2BEG1_input[10]),
+	.A11 (JS2BEG1_input[11]),
+	.A12 (JS2BEG1_input[12]),
+	.A13 (JS2BEG1_input[13]),
+	.A14 (JS2BEG1_input[14]),
+	.A15 (JS2BEG1_input[15]),
+	.S0 (ConfigBits[318+0]),
+	.S0N (ConfigBits_N[318+0]),
+	.S1 (ConfigBits[318+1]),
+	.S1N (ConfigBits_N[318+1]),
+	.S2 (ConfigBits[318+2]),
+	.S2N (ConfigBits_N[318+2]),
+	.S3 (ConfigBits[318+3]),
+	.S3N (ConfigBits_N[318+3]),
+	.X (JS2BEG1)
+	);
+
+// switch matrix multiplexer  JS2BEG2 		MUX-16
+	assign JS2BEG2_input = {Q0,Q1,Q3,Q4,Q5,Q6,Q7,Q8,W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,E1END1,NN4END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG2 (
+	.A0 (JS2BEG2_input[0]),
+	.A1 (JS2BEG2_input[1]),
+	.A2 (JS2BEG2_input[2]),
+	.A3 (JS2BEG2_input[3]),
+	.A4 (JS2BEG2_input[4]),
+	.A5 (JS2BEG2_input[5]),
+	.A6 (JS2BEG2_input[6]),
+	.A7 (JS2BEG2_input[7]),
+	.A8 (JS2BEG2_input[8]),
+	.A9 (JS2BEG2_input[9]),
+	.A10 (JS2BEG2_input[10]),
+	.A11 (JS2BEG2_input[11]),
+	.A12 (JS2BEG2_input[12]),
+	.A13 (JS2BEG2_input[13]),
+	.A14 (JS2BEG2_input[14]),
+	.A15 (JS2BEG2_input[15]),
+	.S0 (ConfigBits[322+0]),
+	.S0N (ConfigBits_N[322+0]),
+	.S1 (ConfigBits[322+1]),
+	.S1N (ConfigBits_N[322+1]),
+	.S2 (ConfigBits[322+2]),
+	.S2N (ConfigBits_N[322+2]),
+	.S3 (ConfigBits[322+3]),
+	.S3N (ConfigBits_N[322+3]),
+	.X (JS2BEG2)
+	);
+
+// switch matrix multiplexer  JS2BEG3 		MUX-16
+	assign JS2BEG3_input = {Q0,Q1,Q2,Q4,Q5,Q6,Q7,Q9,WW4END2,W2END4,S4END0,S2END4,E6END0,E2END4,E1END2,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG3 (
+	.A0 (JS2BEG3_input[0]),
+	.A1 (JS2BEG3_input[1]),
+	.A2 (JS2BEG3_input[2]),
+	.A3 (JS2BEG3_input[3]),
+	.A4 (JS2BEG3_input[4]),
+	.A5 (JS2BEG3_input[5]),
+	.A6 (JS2BEG3_input[6]),
+	.A7 (JS2BEG3_input[7]),
+	.A8 (JS2BEG3_input[8]),
+	.A9 (JS2BEG3_input[9]),
+	.A10 (JS2BEG3_input[10]),
+	.A11 (JS2BEG3_input[11]),
+	.A12 (JS2BEG3_input[12]),
+	.A13 (JS2BEG3_input[13]),
+	.A14 (JS2BEG3_input[14]),
+	.A15 (JS2BEG3_input[15]),
+	.S0 (ConfigBits[326+0]),
+	.S0N (ConfigBits_N[326+0]),
+	.S1 (ConfigBits[326+1]),
+	.S1N (ConfigBits_N[326+1]),
+	.S2 (ConfigBits[326+2]),
+	.S2N (ConfigBits_N[326+2]),
+	.S3 (ConfigBits[326+3]),
+	.S3N (ConfigBits_N[326+3]),
+	.X (JS2BEG3)
+	);
+
+// switch matrix multiplexer  JS2BEG4 		MUX-16
+	assign JS2BEG4_input = {Q0,Q1,Q2,Q3,Q5,Q6,Q7,Q8,W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG4 (
+	.A0 (JS2BEG4_input[0]),
+	.A1 (JS2BEG4_input[1]),
+	.A2 (JS2BEG4_input[2]),
+	.A3 (JS2BEG4_input[3]),
+	.A4 (JS2BEG4_input[4]),
+	.A5 (JS2BEG4_input[5]),
+	.A6 (JS2BEG4_input[6]),
+	.A7 (JS2BEG4_input[7]),
+	.A8 (JS2BEG4_input[8]),
+	.A9 (JS2BEG4_input[9]),
+	.A10 (JS2BEG4_input[10]),
+	.A11 (JS2BEG4_input[11]),
+	.A12 (JS2BEG4_input[12]),
+	.A13 (JS2BEG4_input[13]),
+	.A14 (JS2BEG4_input[14]),
+	.A15 (JS2BEG4_input[15]),
+	.S0 (ConfigBits[330+0]),
+	.S0N (ConfigBits_N[330+0]),
+	.S1 (ConfigBits[330+1]),
+	.S1N (ConfigBits_N[330+1]),
+	.S2 (ConfigBits[330+2]),
+	.S2N (ConfigBits_N[330+2]),
+	.S3 (ConfigBits[330+3]),
+	.S3N (ConfigBits_N[330+3]),
+	.X (JS2BEG4)
+	);
+
+// switch matrix multiplexer  JS2BEG5 		MUX-16
+	assign JS2BEG5_input = {Q0,Q1,Q2,Q3,Q4,Q6,Q7,Q9,W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG5 (
+	.A0 (JS2BEG5_input[0]),
+	.A1 (JS2BEG5_input[1]),
+	.A2 (JS2BEG5_input[2]),
+	.A3 (JS2BEG5_input[3]),
+	.A4 (JS2BEG5_input[4]),
+	.A5 (JS2BEG5_input[5]),
+	.A6 (JS2BEG5_input[6]),
+	.A7 (JS2BEG5_input[7]),
+	.A8 (JS2BEG5_input[8]),
+	.A9 (JS2BEG5_input[9]),
+	.A10 (JS2BEG5_input[10]),
+	.A11 (JS2BEG5_input[11]),
+	.A12 (JS2BEG5_input[12]),
+	.A13 (JS2BEG5_input[13]),
+	.A14 (JS2BEG5_input[14]),
+	.A15 (JS2BEG5_input[15]),
+	.S0 (ConfigBits[334+0]),
+	.S0N (ConfigBits_N[334+0]),
+	.S1 (ConfigBits[334+1]),
+	.S1N (ConfigBits_N[334+1]),
+	.S2 (ConfigBits[334+2]),
+	.S2N (ConfigBits_N[334+2]),
+	.S3 (ConfigBits[334+3]),
+	.S3N (ConfigBits_N[334+3]),
+	.X (JS2BEG5)
+	);
+
+// switch matrix multiplexer  JS2BEG6 		MUX-16
+	assign JS2BEG6_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q7,Q8,W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG6 (
+	.A0 (JS2BEG6_input[0]),
+	.A1 (JS2BEG6_input[1]),
+	.A2 (JS2BEG6_input[2]),
+	.A3 (JS2BEG6_input[3]),
+	.A4 (JS2BEG6_input[4]),
+	.A5 (JS2BEG6_input[5]),
+	.A6 (JS2BEG6_input[6]),
+	.A7 (JS2BEG6_input[7]),
+	.A8 (JS2BEG6_input[8]),
+	.A9 (JS2BEG6_input[9]),
+	.A10 (JS2BEG6_input[10]),
+	.A11 (JS2BEG6_input[11]),
+	.A12 (JS2BEG6_input[12]),
+	.A13 (JS2BEG6_input[13]),
+	.A14 (JS2BEG6_input[14]),
+	.A15 (JS2BEG6_input[15]),
+	.S0 (ConfigBits[338+0]),
+	.S0N (ConfigBits_N[338+0]),
+	.S1 (ConfigBits[338+1]),
+	.S1N (ConfigBits_N[338+1]),
+	.S2 (ConfigBits[338+2]),
+	.S2N (ConfigBits_N[338+2]),
+	.S3 (ConfigBits[338+3]),
+	.S3N (ConfigBits_N[338+3]),
+	.X (JS2BEG6)
+	);
+
+// switch matrix multiplexer  JS2BEG7 		MUX-16
+	assign JS2BEG7_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q9,W1END2,W1END0,S2END0,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG7 (
+	.A0 (JS2BEG7_input[0]),
+	.A1 (JS2BEG7_input[1]),
+	.A2 (JS2BEG7_input[2]),
+	.A3 (JS2BEG7_input[3]),
+	.A4 (JS2BEG7_input[4]),
+	.A5 (JS2BEG7_input[5]),
+	.A6 (JS2BEG7_input[6]),
+	.A7 (JS2BEG7_input[7]),
+	.A8 (JS2BEG7_input[8]),
+	.A9 (JS2BEG7_input[9]),
+	.A10 (JS2BEG7_input[10]),
+	.A11 (JS2BEG7_input[11]),
+	.A12 (JS2BEG7_input[12]),
+	.A13 (JS2BEG7_input[13]),
+	.A14 (JS2BEG7_input[14]),
+	.A15 (JS2BEG7_input[15]),
+	.S0 (ConfigBits[342+0]),
+	.S0N (ConfigBits_N[342+0]),
+	.S1 (ConfigBits[342+1]),
+	.S1N (ConfigBits_N[342+1]),
+	.S2 (ConfigBits[342+2]),
+	.S2N (ConfigBits_N[342+2]),
+	.S3 (ConfigBits[342+3]),
+	.S3N (ConfigBits_N[342+3]),
+	.X (JS2BEG7)
+	);
+
+// switch matrix multiplexer  JW2BEG0 		MUX-16
+	assign JW2BEG0_input = {Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q9,W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG0 (
+	.A0 (JW2BEG0_input[0]),
+	.A1 (JW2BEG0_input[1]),
+	.A2 (JW2BEG0_input[2]),
+	.A3 (JW2BEG0_input[3]),
+	.A4 (JW2BEG0_input[4]),
+	.A5 (JW2BEG0_input[5]),
+	.A6 (JW2BEG0_input[6]),
+	.A7 (JW2BEG0_input[7]),
+	.A8 (JW2BEG0_input[8]),
+	.A9 (JW2BEG0_input[9]),
+	.A10 (JW2BEG0_input[10]),
+	.A11 (JW2BEG0_input[11]),
+	.A12 (JW2BEG0_input[12]),
+	.A13 (JW2BEG0_input[13]),
+	.A14 (JW2BEG0_input[14]),
+	.A15 (JW2BEG0_input[15]),
+	.S0 (ConfigBits[346+0]),
+	.S0N (ConfigBits_N[346+0]),
+	.S1 (ConfigBits[346+1]),
+	.S1N (ConfigBits_N[346+1]),
+	.S2 (ConfigBits[346+2]),
+	.S2N (ConfigBits_N[346+2]),
+	.S3 (ConfigBits[346+3]),
+	.S3N (ConfigBits_N[346+3]),
+	.X (JW2BEG0)
+	);
+
+// switch matrix multiplexer  JW2BEG1 		MUX-16
+	assign JW2BEG1_input = {Q0,Q2,Q3,Q4,Q5,Q6,Q7,Q8,W6END0,W2END2,S4END2,S2END2,E6END0,E2END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG1 (
+	.A0 (JW2BEG1_input[0]),
+	.A1 (JW2BEG1_input[1]),
+	.A2 (JW2BEG1_input[2]),
+	.A3 (JW2BEG1_input[3]),
+	.A4 (JW2BEG1_input[4]),
+	.A5 (JW2BEG1_input[5]),
+	.A6 (JW2BEG1_input[6]),
+	.A7 (JW2BEG1_input[7]),
+	.A8 (JW2BEG1_input[8]),
+	.A9 (JW2BEG1_input[9]),
+	.A10 (JW2BEG1_input[10]),
+	.A11 (JW2BEG1_input[11]),
+	.A12 (JW2BEG1_input[12]),
+	.A13 (JW2BEG1_input[13]),
+	.A14 (JW2BEG1_input[14]),
+	.A15 (JW2BEG1_input[15]),
+	.S0 (ConfigBits[350+0]),
+	.S0N (ConfigBits_N[350+0]),
+	.S1 (ConfigBits[350+1]),
+	.S1N (ConfigBits_N[350+1]),
+	.S2 (ConfigBits[350+2]),
+	.S2N (ConfigBits_N[350+2]),
+	.S3 (ConfigBits[350+3]),
+	.S3N (ConfigBits_N[350+3]),
+	.X (JW2BEG1)
+	);
+
+// switch matrix multiplexer  JW2BEG2 		MUX-16
+	assign JW2BEG2_input = {Q0,Q1,Q3,Q4,Q5,Q6,Q7,Q9,W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG2 (
+	.A0 (JW2BEG2_input[0]),
+	.A1 (JW2BEG2_input[1]),
+	.A2 (JW2BEG2_input[2]),
+	.A3 (JW2BEG2_input[3]),
+	.A4 (JW2BEG2_input[4]),
+	.A5 (JW2BEG2_input[5]),
+	.A6 (JW2BEG2_input[6]),
+	.A7 (JW2BEG2_input[7]),
+	.A8 (JW2BEG2_input[8]),
+	.A9 (JW2BEG2_input[9]),
+	.A10 (JW2BEG2_input[10]),
+	.A11 (JW2BEG2_input[11]),
+	.A12 (JW2BEG2_input[12]),
+	.A13 (JW2BEG2_input[13]),
+	.A14 (JW2BEG2_input[14]),
+	.A15 (JW2BEG2_input[15]),
+	.S0 (ConfigBits[354+0]),
+	.S0N (ConfigBits_N[354+0]),
+	.S1 (ConfigBits[354+1]),
+	.S1N (ConfigBits_N[354+1]),
+	.S2 (ConfigBits[354+2]),
+	.S2N (ConfigBits_N[354+2]),
+	.S3 (ConfigBits[354+3]),
+	.S3N (ConfigBits_N[354+3]),
+	.X (JW2BEG2)
+	);
+
+// switch matrix multiplexer  JW2BEG3 		MUX-16
+	assign JW2BEG3_input = {Q0,Q1,Q2,Q4,Q5,Q6,Q7,Q8,W6END0,W2END4,S4END0,S2END4,E6END0,E2END4,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG3 (
+	.A0 (JW2BEG3_input[0]),
+	.A1 (JW2BEG3_input[1]),
+	.A2 (JW2BEG3_input[2]),
+	.A3 (JW2BEG3_input[3]),
+	.A4 (JW2BEG3_input[4]),
+	.A5 (JW2BEG3_input[5]),
+	.A6 (JW2BEG3_input[6]),
+	.A7 (JW2BEG3_input[7]),
+	.A8 (JW2BEG3_input[8]),
+	.A9 (JW2BEG3_input[9]),
+	.A10 (JW2BEG3_input[10]),
+	.A11 (JW2BEG3_input[11]),
+	.A12 (JW2BEG3_input[12]),
+	.A13 (JW2BEG3_input[13]),
+	.A14 (JW2BEG3_input[14]),
+	.A15 (JW2BEG3_input[15]),
+	.S0 (ConfigBits[358+0]),
+	.S0N (ConfigBits_N[358+0]),
+	.S1 (ConfigBits[358+1]),
+	.S1N (ConfigBits_N[358+1]),
+	.S2 (ConfigBits[358+2]),
+	.S2N (ConfigBits_N[358+2]),
+	.S3 (ConfigBits[358+3]),
+	.S3N (ConfigBits_N[358+3]),
+	.X (JW2BEG3)
+	);
+
+// switch matrix multiplexer  JW2BEG4 		MUX-16
+	assign JW2BEG4_input = {Q0,Q1,Q2,Q3,Q5,Q6,Q7,Q9,W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG4 (
+	.A0 (JW2BEG4_input[0]),
+	.A1 (JW2BEG4_input[1]),
+	.A2 (JW2BEG4_input[2]),
+	.A3 (JW2BEG4_input[3]),
+	.A4 (JW2BEG4_input[4]),
+	.A5 (JW2BEG4_input[5]),
+	.A6 (JW2BEG4_input[6]),
+	.A7 (JW2BEG4_input[7]),
+	.A8 (JW2BEG4_input[8]),
+	.A9 (JW2BEG4_input[9]),
+	.A10 (JW2BEG4_input[10]),
+	.A11 (JW2BEG4_input[11]),
+	.A12 (JW2BEG4_input[12]),
+	.A13 (JW2BEG4_input[13]),
+	.A14 (JW2BEG4_input[14]),
+	.A15 (JW2BEG4_input[15]),
+	.S0 (ConfigBits[362+0]),
+	.S0N (ConfigBits_N[362+0]),
+	.S1 (ConfigBits[362+1]),
+	.S1N (ConfigBits_N[362+1]),
+	.S2 (ConfigBits[362+2]),
+	.S2N (ConfigBits_N[362+2]),
+	.S3 (ConfigBits[362+3]),
+	.S3N (ConfigBits_N[362+3]),
+	.X (JW2BEG4)
+	);
+
+// switch matrix multiplexer  JW2BEG5 		MUX-16
+	assign JW2BEG5_input = {Q0,Q1,Q2,Q3,Q4,Q6,Q7,Q8,W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG5 (
+	.A0 (JW2BEG5_input[0]),
+	.A1 (JW2BEG5_input[1]),
+	.A2 (JW2BEG5_input[2]),
+	.A3 (JW2BEG5_input[3]),
+	.A4 (JW2BEG5_input[4]),
+	.A5 (JW2BEG5_input[5]),
+	.A6 (JW2BEG5_input[6]),
+	.A7 (JW2BEG5_input[7]),
+	.A8 (JW2BEG5_input[8]),
+	.A9 (JW2BEG5_input[9]),
+	.A10 (JW2BEG5_input[10]),
+	.A11 (JW2BEG5_input[11]),
+	.A12 (JW2BEG5_input[12]),
+	.A13 (JW2BEG5_input[13]),
+	.A14 (JW2BEG5_input[14]),
+	.A15 (JW2BEG5_input[15]),
+	.S0 (ConfigBits[366+0]),
+	.S0N (ConfigBits_N[366+0]),
+	.S1 (ConfigBits[366+1]),
+	.S1N (ConfigBits_N[366+1]),
+	.S2 (ConfigBits[366+2]),
+	.S2N (ConfigBits_N[366+2]),
+	.S3 (ConfigBits[366+3]),
+	.S3N (ConfigBits_N[366+3]),
+	.X (JW2BEG5)
+	);
+
+// switch matrix multiplexer  JW2BEG6 		MUX-16
+	assign JW2BEG6_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q7,Q9,W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG6 (
+	.A0 (JW2BEG6_input[0]),
+	.A1 (JW2BEG6_input[1]),
+	.A2 (JW2BEG6_input[2]),
+	.A3 (JW2BEG6_input[3]),
+	.A4 (JW2BEG6_input[4]),
+	.A5 (JW2BEG6_input[5]),
+	.A6 (JW2BEG6_input[6]),
+	.A7 (JW2BEG6_input[7]),
+	.A8 (JW2BEG6_input[8]),
+	.A9 (JW2BEG6_input[9]),
+	.A10 (JW2BEG6_input[10]),
+	.A11 (JW2BEG6_input[11]),
+	.A12 (JW2BEG6_input[12]),
+	.A13 (JW2BEG6_input[13]),
+	.A14 (JW2BEG6_input[14]),
+	.A15 (JW2BEG6_input[15]),
+	.S0 (ConfigBits[370+0]),
+	.S0N (ConfigBits_N[370+0]),
+	.S1 (ConfigBits[370+1]),
+	.S1N (ConfigBits_N[370+1]),
+	.S2 (ConfigBits[370+2]),
+	.S2N (ConfigBits_N[370+2]),
+	.S3 (ConfigBits[370+3]),
+	.S3N (ConfigBits_N[370+3]),
+	.X (JW2BEG6)
+	);
+
+// switch matrix multiplexer  JW2BEG7 		MUX-16
+	assign JW2BEG7_input = {Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q8,W1END0,S2END0,S1END2,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG7 (
+	.A0 (JW2BEG7_input[0]),
+	.A1 (JW2BEG7_input[1]),
+	.A2 (JW2BEG7_input[2]),
+	.A3 (JW2BEG7_input[3]),
+	.A4 (JW2BEG7_input[4]),
+	.A5 (JW2BEG7_input[5]),
+	.A6 (JW2BEG7_input[6]),
+	.A7 (JW2BEG7_input[7]),
+	.A8 (JW2BEG7_input[8]),
+	.A9 (JW2BEG7_input[9]),
+	.A10 (JW2BEG7_input[10]),
+	.A11 (JW2BEG7_input[11]),
+	.A12 (JW2BEG7_input[12]),
+	.A13 (JW2BEG7_input[13]),
+	.A14 (JW2BEG7_input[14]),
+	.A15 (JW2BEG7_input[15]),
+	.S0 (ConfigBits[374+0]),
+	.S0N (ConfigBits_N[374+0]),
+	.S1 (ConfigBits[374+1]),
+	.S1N (ConfigBits_N[374+1]),
+	.S2 (ConfigBits[374+2]),
+	.S2N (ConfigBits_N[374+2]),
+	.S3 (ConfigBits[374+3]),
+	.S3N (ConfigBits_N[374+3]),
+	.X (JW2BEG7)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG0 		MUX-4
+	assign J_l_AB_BEG0_input = {JN2END1,WW4END0,S4END3,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG0 (
+	.A0 (J_l_AB_BEG0_input[0]),
+	.A1 (J_l_AB_BEG0_input[1]),
+	.A2 (J_l_AB_BEG0_input[2]),
+	.A3 (J_l_AB_BEG0_input[3]),
+	.S0 (ConfigBits[378+0]),
+	.S0N (ConfigBits_N[378+0]),
+	.S1 (ConfigBits[378+1]),
+	.S1N (ConfigBits_N[378+1]),
+	.X (J_l_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG1 		MUX-4
+	assign J_l_AB_BEG1_input = {JE2END1,W2END7,S4END2,EE4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG1 (
+	.A0 (J_l_AB_BEG1_input[0]),
+	.A1 (J_l_AB_BEG1_input[1]),
+	.A2 (J_l_AB_BEG1_input[2]),
+	.A3 (J_l_AB_BEG1_input[3]),
+	.S0 (ConfigBits[380+0]),
+	.S0N (ConfigBits_N[380+0]),
+	.S1 (ConfigBits[380+1]),
+	.S1N (ConfigBits_N[380+1]),
+	.X (J_l_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG2 		MUX-4
+	assign J_l_AB_BEG2_input = {JS2END1,W6END1,E6END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG2 (
+	.A0 (J_l_AB_BEG2_input[0]),
+	.A1 (J_l_AB_BEG2_input[1]),
+	.A2 (J_l_AB_BEG2_input[2]),
+	.A3 (J_l_AB_BEG2_input[3]),
+	.S0 (ConfigBits[382+0]),
+	.S0N (ConfigBits_N[382+0]),
+	.S1 (ConfigBits[382+1]),
+	.S1N (ConfigBits_N[382+1]),
+	.X (J_l_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG3 		MUX-4
+	assign J_l_AB_BEG3_input = {JW2END1,S4END0,E6END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG3 (
+	.A0 (J_l_AB_BEG3_input[0]),
+	.A1 (J_l_AB_BEG3_input[1]),
+	.A2 (J_l_AB_BEG3_input[2]),
+	.A3 (J_l_AB_BEG3_input[3]),
+	.S0 (ConfigBits[384+0]),
+	.S0N (ConfigBits_N[384+0]),
+	.S1 (ConfigBits[384+1]),
+	.S1N (ConfigBits_N[384+1]),
+	.X (J_l_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG0 		MUX-4
+	assign J_l_CD_BEG0_input = {JN2END2,WW4END2,SS4END3,E2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG0 (
+	.A0 (J_l_CD_BEG0_input[0]),
+	.A1 (J_l_CD_BEG0_input[1]),
+	.A2 (J_l_CD_BEG0_input[2]),
+	.A3 (J_l_CD_BEG0_input[3]),
+	.S0 (ConfigBits[386+0]),
+	.S0N (ConfigBits_N[386+0]),
+	.S1 (ConfigBits[386+1]),
+	.S1N (ConfigBits_N[386+1]),
+	.X (J_l_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG1 		MUX-4
+	assign J_l_CD_BEG1_input = {JE2END2,W2END7,E2END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG1 (
+	.A0 (J_l_CD_BEG1_input[0]),
+	.A1 (J_l_CD_BEG1_input[1]),
+	.A2 (J_l_CD_BEG1_input[2]),
+	.A3 (J_l_CD_BEG1_input[3]),
+	.S0 (ConfigBits[388+0]),
+	.S0N (ConfigBits_N[388+0]),
+	.S1 (ConfigBits[388+1]),
+	.S1N (ConfigBits_N[388+1]),
+	.X (J_l_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG2 		MUX-4
+	assign J_l_CD_BEG2_input = {JS2END2,S4END1,EE4END1,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG2 (
+	.A0 (J_l_CD_BEG2_input[0]),
+	.A1 (J_l_CD_BEG2_input[1]),
+	.A2 (J_l_CD_BEG2_input[2]),
+	.A3 (J_l_CD_BEG2_input[3]),
+	.S0 (ConfigBits[390+0]),
+	.S0N (ConfigBits_N[390+0]),
+	.S1 (ConfigBits[390+1]),
+	.S1N (ConfigBits_N[390+1]),
+	.X (J_l_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG3 		MUX-4
+	assign J_l_CD_BEG3_input = {JW2END2,W6END0,SS4END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG3 (
+	.A0 (J_l_CD_BEG3_input[0]),
+	.A1 (J_l_CD_BEG3_input[1]),
+	.A2 (J_l_CD_BEG3_input[2]),
+	.A3 (J_l_CD_BEG3_input[3]),
+	.S0 (ConfigBits[392+0]),
+	.S0N (ConfigBits_N[392+0]),
+	.S1 (ConfigBits[392+1]),
+	.S1N (ConfigBits_N[392+1]),
+	.X (J_l_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG0 		MUX-4
+	assign J_l_EF_BEG0_input = {JN2END3,W2END3,E2END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG0 (
+	.A0 (J_l_EF_BEG0_input[0]),
+	.A1 (J_l_EF_BEG0_input[1]),
+	.A2 (J_l_EF_BEG0_input[2]),
+	.A3 (J_l_EF_BEG0_input[3]),
+	.S0 (ConfigBits[394+0]),
+	.S0N (ConfigBits_N[394+0]),
+	.S1 (ConfigBits[394+1]),
+	.S1N (ConfigBits_N[394+1]),
+	.X (J_l_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG1 		MUX-4
+	assign J_l_EF_BEG1_input = {JE2END3,S4END2,E2END2,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG1 (
+	.A0 (J_l_EF_BEG1_input[0]),
+	.A1 (J_l_EF_BEG1_input[1]),
+	.A2 (J_l_EF_BEG1_input[2]),
+	.A3 (J_l_EF_BEG1_input[3]),
+	.S0 (ConfigBits[396+0]),
+	.S0N (ConfigBits_N[396+0]),
+	.S1 (ConfigBits[396+1]),
+	.S1N (ConfigBits_N[396+1]),
+	.X (J_l_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG2 		MUX-4
+	assign J_l_EF_BEG2_input = {JS2END3,W2END4,SS4END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG2 (
+	.A0 (J_l_EF_BEG2_input[0]),
+	.A1 (J_l_EF_BEG2_input[1]),
+	.A2 (J_l_EF_BEG2_input[2]),
+	.A3 (J_l_EF_BEG2_input[3]),
+	.S0 (ConfigBits[398+0]),
+	.S0N (ConfigBits_N[398+0]),
+	.S1 (ConfigBits[398+1]),
+	.S1N (ConfigBits_N[398+1]),
+	.X (J_l_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG3 		MUX-4
+	assign J_l_EF_BEG3_input = {JW2END3,WW4END1,S4END0,EE4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG3 (
+	.A0 (J_l_EF_BEG3_input[0]),
+	.A1 (J_l_EF_BEG3_input[1]),
+	.A2 (J_l_EF_BEG3_input[2]),
+	.A3 (J_l_EF_BEG3_input[3]),
+	.S0 (ConfigBits[400+0]),
+	.S0N (ConfigBits_N[400+0]),
+	.S1 (ConfigBits[400+1]),
+	.S1N (ConfigBits_N[400+1]),
+	.X (J_l_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG0 		MUX-4
+	assign J_l_GH_BEG0_input = {JN2END4,S4END3,EE4END0,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG0 (
+	.A0 (J_l_GH_BEG0_input[0]),
+	.A1 (J_l_GH_BEG0_input[1]),
+	.A2 (J_l_GH_BEG0_input[2]),
+	.A3 (J_l_GH_BEG0_input[3]),
+	.S0 (ConfigBits[402+0]),
+	.S0N (ConfigBits_N[402+0]),
+	.S1 (ConfigBits[402+1]),
+	.S1N (ConfigBits_N[402+1]),
+	.X (J_l_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG1 		MUX-4
+	assign J_l_GH_BEG1_input = {JE2END4,W2END2,SS4END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG1 (
+	.A0 (J_l_GH_BEG1_input[0]),
+	.A1 (J_l_GH_BEG1_input[1]),
+	.A2 (J_l_GH_BEG1_input[2]),
+	.A3 (J_l_GH_BEG1_input[3]),
+	.S0 (ConfigBits[404+0]),
+	.S0N (ConfigBits_N[404+0]),
+	.S1 (ConfigBits[404+1]),
+	.S1N (ConfigBits_N[404+1]),
+	.X (J_l_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG2 		MUX-4
+	assign J_l_GH_BEG2_input = {JS2END4,WW4END3,S4END1,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG2 (
+	.A0 (J_l_GH_BEG2_input[0]),
+	.A1 (J_l_GH_BEG2_input[1]),
+	.A2 (J_l_GH_BEG2_input[2]),
+	.A3 (J_l_GH_BEG2_input[3]),
+	.S0 (ConfigBits[406+0]),
+	.S0N (ConfigBits_N[406+0]),
+	.S1 (ConfigBits[406+1]),
+	.S1N (ConfigBits_N[406+1]),
+	.X (J_l_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG3 		MUX-4
+	assign J_l_GH_BEG3_input = {JW2END4,W2END0,E6END0,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG3 (
+	.A0 (J_l_GH_BEG3_input[0]),
+	.A1 (J_l_GH_BEG3_input[1]),
+	.A2 (J_l_GH_BEG3_input[2]),
+	.A3 (J_l_GH_BEG3_input[3]),
+	.S0 (ConfigBits[408+0]),
+	.S0N (ConfigBits_N[408+0]),
+	.S1 (ConfigBits[408+1]),
+	.S1N (ConfigBits_N[408+1]),
+	.X (J_l_GH_BEG3)
+	);
+
+	assign DEBUG_select_N1BEG0 = ConfigBits[1:0];
+	assign DEBUG_select_N1BEG1 = ConfigBits[3:2];
+	assign DEBUG_select_N1BEG2 = ConfigBits[5:4];
+	assign DEBUG_select_N1BEG3 = ConfigBits[7:6];
+	assign DEBUG_select_N4BEG0 = ConfigBits[9:8];
+	assign DEBUG_select_N4BEG1 = ConfigBits[11:10];
+	assign DEBUG_select_N4BEG2 = ConfigBits[13:12];
+	assign DEBUG_select_N4BEG3 = ConfigBits[15:14];
+	assign DEBUG_select_NN4BEG0 = ConfigBits[18:16];
+	assign DEBUG_select_NN4BEG1 = ConfigBits[21:19];
+	assign DEBUG_select_NN4BEG2 = ConfigBits[24:22];
+	assign DEBUG_select_NN4BEG3 = ConfigBits[27:25];
+	assign DEBUG_select_E1BEG0 = ConfigBits[29:28];
+	assign DEBUG_select_E1BEG1 = ConfigBits[31:30];
+	assign DEBUG_select_E1BEG2 = ConfigBits[33:32];
+	assign DEBUG_select_E1BEG3 = ConfigBits[35:34];
+	assign DEBUG_select_EE4BEG0 = ConfigBits[38:36];
+	assign DEBUG_select_EE4BEG1 = ConfigBits[41:39];
+	assign DEBUG_select_EE4BEG2 = ConfigBits[44:42];
+	assign DEBUG_select_EE4BEG3 = ConfigBits[47:45];
+	assign DEBUG_select_E6BEG0 = ConfigBits[51:48];
+	assign DEBUG_select_E6BEG1 = ConfigBits[55:52];
+	assign DEBUG_select_S1BEG0 = ConfigBits[57:56];
+	assign DEBUG_select_S1BEG1 = ConfigBits[59:58];
+	assign DEBUG_select_S1BEG2 = ConfigBits[61:60];
+	assign DEBUG_select_S1BEG3 = ConfigBits[63:62];
+	assign DEBUG_select_S4BEG0 = ConfigBits[65:64];
+	assign DEBUG_select_S4BEG1 = ConfigBits[67:66];
+	assign DEBUG_select_S4BEG2 = ConfigBits[69:68];
+	assign DEBUG_select_S4BEG3 = ConfigBits[71:70];
+	assign DEBUG_select_SS4BEG0 = ConfigBits[74:72];
+	assign DEBUG_select_SS4BEG1 = ConfigBits[77:75];
+	assign DEBUG_select_SS4BEG2 = ConfigBits[80:78];
+	assign DEBUG_select_SS4BEG3 = ConfigBits[83:81];
+	assign DEBUG_select_W1BEG0 = ConfigBits[85:84];
+	assign DEBUG_select_W1BEG1 = ConfigBits[87:86];
+	assign DEBUG_select_W1BEG2 = ConfigBits[89:88];
+	assign DEBUG_select_W1BEG3 = ConfigBits[91:90];
+	assign DEBUG_select_WW4BEG0 = ConfigBits[94:92];
+	assign DEBUG_select_WW4BEG1 = ConfigBits[97:95];
+	assign DEBUG_select_WW4BEG2 = ConfigBits[100:98];
+	assign DEBUG_select_WW4BEG3 = ConfigBits[103:101];
+	assign DEBUG_select_W6BEG0 = ConfigBits[107:104];
+	assign DEBUG_select_W6BEG1 = ConfigBits[111:108];
+	assign DEBUG_select_A3 = ConfigBits[113:112];
+	assign DEBUG_select_A2 = ConfigBits[115:114];
+	assign DEBUG_select_A1 = ConfigBits[117:116];
+	assign DEBUG_select_A0 = ConfigBits[119:118];
+	assign DEBUG_select_B3 = ConfigBits[121:120];
+	assign DEBUG_select_B2 = ConfigBits[123:122];
+	assign DEBUG_select_B1 = ConfigBits[125:124];
+	assign DEBUG_select_B0 = ConfigBits[127:126];
+	assign DEBUG_select_C9 = ConfigBits[130:128];
+	assign DEBUG_select_C8 = ConfigBits[133:131];
+	assign DEBUG_select_C7 = ConfigBits[135:134];
+	assign DEBUG_select_C6 = ConfigBits[137:136];
+	assign DEBUG_select_C5 = ConfigBits[139:138];
+	assign DEBUG_select_C4 = ConfigBits[141:140];
+	assign DEBUG_select_C3 = ConfigBits[143:142];
+	assign DEBUG_select_C2 = ConfigBits[145:144];
+	assign DEBUG_select_C1 = ConfigBits[147:146];
+	assign DEBUG_select_C0 = ConfigBits[149:148];
+	assign DEBUG_select_clr = ConfigBits[153:150];
+	assign DEBUG_select_J2MID_ABa_BEG0 = ConfigBits[155:154];
+	assign DEBUG_select_J2MID_ABa_BEG1 = ConfigBits[157:156];
+	assign DEBUG_select_J2MID_ABa_BEG2 = ConfigBits[159:158];
+	assign DEBUG_select_J2MID_ABa_BEG3 = ConfigBits[161:160];
+	assign DEBUG_select_J2MID_CDa_BEG0 = ConfigBits[163:162];
+	assign DEBUG_select_J2MID_CDa_BEG1 = ConfigBits[165:164];
+	assign DEBUG_select_J2MID_CDa_BEG2 = ConfigBits[167:166];
+	assign DEBUG_select_J2MID_CDa_BEG3 = ConfigBits[169:168];
+	assign DEBUG_select_J2MID_EFa_BEG0 = ConfigBits[171:170];
+	assign DEBUG_select_J2MID_EFa_BEG1 = ConfigBits[173:172];
+	assign DEBUG_select_J2MID_EFa_BEG2 = ConfigBits[175:174];
+	assign DEBUG_select_J2MID_EFa_BEG3 = ConfigBits[177:176];
+	assign DEBUG_select_J2MID_GHa_BEG0 = ConfigBits[179:178];
+	assign DEBUG_select_J2MID_GHa_BEG1 = ConfigBits[181:180];
+	assign DEBUG_select_J2MID_GHa_BEG2 = ConfigBits[183:182];
+	assign DEBUG_select_J2MID_GHa_BEG3 = ConfigBits[185:184];
+	assign DEBUG_select_J2MID_ABb_BEG0 = ConfigBits[187:186];
+	assign DEBUG_select_J2MID_ABb_BEG1 = ConfigBits[189:188];
+	assign DEBUG_select_J2MID_ABb_BEG2 = ConfigBits[191:190];
+	assign DEBUG_select_J2MID_ABb_BEG3 = ConfigBits[193:192];
+	assign DEBUG_select_J2MID_CDb_BEG0 = ConfigBits[195:194];
+	assign DEBUG_select_J2MID_CDb_BEG1 = ConfigBits[197:196];
+	assign DEBUG_select_J2MID_CDb_BEG2 = ConfigBits[199:198];
+	assign DEBUG_select_J2MID_CDb_BEG3 = ConfigBits[201:200];
+	assign DEBUG_select_J2MID_EFb_BEG0 = ConfigBits[203:202];
+	assign DEBUG_select_J2MID_EFb_BEG1 = ConfigBits[205:204];
+	assign DEBUG_select_J2MID_EFb_BEG2 = ConfigBits[207:206];
+	assign DEBUG_select_J2MID_EFb_BEG3 = ConfigBits[209:208];
+	assign DEBUG_select_J2MID_GHb_BEG0 = ConfigBits[211:210];
+	assign DEBUG_select_J2MID_GHb_BEG1 = ConfigBits[213:212];
+	assign DEBUG_select_J2MID_GHb_BEG2 = ConfigBits[215:214];
+	assign DEBUG_select_J2MID_GHb_BEG3 = ConfigBits[217:216];
+	assign DEBUG_select_J2END_AB_BEG0 = ConfigBits[219:218];
+	assign DEBUG_select_J2END_AB_BEG1 = ConfigBits[221:220];
+	assign DEBUG_select_J2END_AB_BEG2 = ConfigBits[223:222];
+	assign DEBUG_select_J2END_AB_BEG3 = ConfigBits[225:224];
+	assign DEBUG_select_J2END_CD_BEG0 = ConfigBits[227:226];
+	assign DEBUG_select_J2END_CD_BEG1 = ConfigBits[229:228];
+	assign DEBUG_select_J2END_CD_BEG2 = ConfigBits[231:230];
+	assign DEBUG_select_J2END_CD_BEG3 = ConfigBits[233:232];
+	assign DEBUG_select_J2END_EF_BEG0 = ConfigBits[235:234];
+	assign DEBUG_select_J2END_EF_BEG1 = ConfigBits[237:236];
+	assign DEBUG_select_J2END_EF_BEG2 = ConfigBits[239:238];
+	assign DEBUG_select_J2END_EF_BEG3 = ConfigBits[241:240];
+	assign DEBUG_select_J2END_GH_BEG0 = ConfigBits[243:242];
+	assign DEBUG_select_J2END_GH_BEG1 = ConfigBits[245:244];
+	assign DEBUG_select_J2END_GH_BEG2 = ConfigBits[247:246];
+	assign DEBUG_select_J2END_GH_BEG3 = ConfigBits[249:248];
+	assign DEBUG_select_JN2BEG0 = ConfigBits[253:250];
+	assign DEBUG_select_JN2BEG1 = ConfigBits[257:254];
+	assign DEBUG_select_JN2BEG2 = ConfigBits[261:258];
+	assign DEBUG_select_JN2BEG3 = ConfigBits[265:262];
+	assign DEBUG_select_JN2BEG4 = ConfigBits[269:266];
+	assign DEBUG_select_JN2BEG5 = ConfigBits[273:270];
+	assign DEBUG_select_JN2BEG6 = ConfigBits[277:274];
+	assign DEBUG_select_JN2BEG7 = ConfigBits[281:278];
+	assign DEBUG_select_JE2BEG0 = ConfigBits[285:282];
+	assign DEBUG_select_JE2BEG1 = ConfigBits[289:286];
+	assign DEBUG_select_JE2BEG2 = ConfigBits[293:290];
+	assign DEBUG_select_JE2BEG3 = ConfigBits[297:294];
+	assign DEBUG_select_JE2BEG4 = ConfigBits[301:298];
+	assign DEBUG_select_JE2BEG5 = ConfigBits[305:302];
+	assign DEBUG_select_JE2BEG6 = ConfigBits[309:306];
+	assign DEBUG_select_JE2BEG7 = ConfigBits[313:310];
+	assign DEBUG_select_JS2BEG0 = ConfigBits[317:314];
+	assign DEBUG_select_JS2BEG1 = ConfigBits[321:318];
+	assign DEBUG_select_JS2BEG2 = ConfigBits[325:322];
+	assign DEBUG_select_JS2BEG3 = ConfigBits[329:326];
+	assign DEBUG_select_JS2BEG4 = ConfigBits[333:330];
+	assign DEBUG_select_JS2BEG5 = ConfigBits[337:334];
+	assign DEBUG_select_JS2BEG6 = ConfigBits[341:338];
+	assign DEBUG_select_JS2BEG7 = ConfigBits[345:342];
+	assign DEBUG_select_JW2BEG0 = ConfigBits[349:346];
+	assign DEBUG_select_JW2BEG1 = ConfigBits[353:350];
+	assign DEBUG_select_JW2BEG2 = ConfigBits[357:354];
+	assign DEBUG_select_JW2BEG3 = ConfigBits[361:358];
+	assign DEBUG_select_JW2BEG4 = ConfigBits[365:362];
+	assign DEBUG_select_JW2BEG5 = ConfigBits[369:366];
+	assign DEBUG_select_JW2BEG6 = ConfigBits[373:370];
+	assign DEBUG_select_JW2BEG7 = ConfigBits[377:374];
+	assign DEBUG_select_J_l_AB_BEG0 = ConfigBits[379:378];
+	assign DEBUG_select_J_l_AB_BEG1 = ConfigBits[381:380];
+	assign DEBUG_select_J_l_AB_BEG2 = ConfigBits[383:382];
+	assign DEBUG_select_J_l_AB_BEG3 = ConfigBits[385:384];
+	assign DEBUG_select_J_l_CD_BEG0 = ConfigBits[387:386];
+	assign DEBUG_select_J_l_CD_BEG1 = ConfigBits[389:388];
+	assign DEBUG_select_J_l_CD_BEG2 = ConfigBits[391:390];
+	assign DEBUG_select_J_l_CD_BEG3 = ConfigBits[393:392];
+	assign DEBUG_select_J_l_EF_BEG0 = ConfigBits[395:394];
+	assign DEBUG_select_J_l_EF_BEG1 = ConfigBits[397:396];
+	assign DEBUG_select_J_l_EF_BEG2 = ConfigBits[399:398];
+	assign DEBUG_select_J_l_EF_BEG3 = ConfigBits[401:400];
+	assign DEBUG_select_J_l_GH_BEG0 = ConfigBits[403:402];
+	assign DEBUG_select_J_l_GH_BEG1 = ConfigBits[405:404];
+	assign DEBUG_select_J_l_GH_BEG2 = ConfigBits[407:406];
+	assign DEBUG_select_J_l_GH_BEG3 = ConfigBits[409:408];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_bot_tile.v b/verilog/rtl/eFPGA_core/DSP_bot_tile.v
new file mode 100644
index 0000000..d14f814
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_bot_tile.v
@@ -0,0 +1,2216 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module DSP_bot (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, bot2top, N1END, N2MID, N2END, N4END, NN4END, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, top2bot, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 416;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	output [9:0] bot2top; //wires:10 X_offset:0 Y_offset:1  source_name:bot2top destination_name:NULL  
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	input [17:0] top2bot; //wires:18 X_offset:0 Y_offset:-1  source_name:NULL destination_name:top2bot  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	// Tile IO ports from BELs
+	input UserCLK;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire A7;
+	wire A6;
+	wire A5;
+	wire A4;
+	wire A3;
+	wire A2;
+	wire A1;
+	wire A0;
+	wire B7;
+	wire B6;
+	wire B5;
+	wire B4;
+	wire B3;
+	wire B2;
+	wire B1;
+	wire B0;
+	wire C19;
+	wire C18;
+	wire C17;
+	wire C16;
+	wire C15;
+	wire C14;
+	wire C13;
+	wire C12;
+	wire C11;
+	wire C10;
+	wire C9;
+	wire C8;
+	wire C7;
+	wire C6;
+	wire C5;
+	wire C4;
+	wire C3;
+	wire C2;
+	wire C1;
+	wire C0;
+	wire clr;
+	wire Q19;
+	wire Q18;
+	wire Q17;
+	wire Q16;
+	wire Q15;
+	wire Q14;
+	wire Q13;
+	wire Q12;
+	wire Q11;
+	wire Q10;
+	wire Q9;
+	wire Q8;
+	wire Q7;
+	wire Q6;
+	wire Q5;
+	wire Q4;
+	wire Q3;
+	wire Q2;
+	wire Q1;
+	wire Q0;
+//jump wires
+	wire [4-1:0] J2MID_ABa_BEG;
+	wire [4-1:0] J2MID_CDa_BEG;
+	wire [4-1:0] J2MID_EFa_BEG;
+	wire [4-1:0] J2MID_GHa_BEG;
+	wire [4-1:0] J2MID_ABb_BEG;
+	wire [4-1:0] J2MID_CDb_BEG;
+	wire [4-1:0] J2MID_EFb_BEG;
+	wire [4-1:0] J2MID_GHb_BEG;
+	wire [4-1:0] J2END_AB_BEG;
+	wire [4-1:0] J2END_CD_BEG;
+	wire [4-1:0] J2END_EF_BEG;
+	wire [4-1:0] J2END_GH_BEG;
+	wire [8-1:0] JN2BEG;
+	wire [8-1:0] JE2BEG;
+	wire [8-1:0] JS2BEG;
+	wire [8-1:0] JW2BEG;
+	wire [4-1:0] J_l_AB_BEG;
+	wire [4-1:0] J_l_CD_BEG;
+	wire [4-1:0] J_l_EF_BEG;
+	wire [4-1:0] J_l_GH_BEG;
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	wire [15:0] N4END_i;
+	wire [11:0] N4BEG_i;
+	assign N4BEG_i[15-4:0] = N4END_i[15:4];
+
+	my_buf N4END_inbuf_0 (
+	.A(N4END[4]),
+	.X(N4END_i[4])
+	);
+
+	my_buf N4END_inbuf_1 (
+	.A(N4END[5]),
+	.X(N4END_i[5])
+	);
+
+	my_buf N4END_inbuf_2 (
+	.A(N4END[6]),
+	.X(N4END_i[6])
+	);
+
+	my_buf N4END_inbuf_3 (
+	.A(N4END[7]),
+	.X(N4END_i[7])
+	);
+
+	my_buf N4END_inbuf_4 (
+	.A(N4END[8]),
+	.X(N4END_i[8])
+	);
+
+	my_buf N4END_inbuf_5 (
+	.A(N4END[9]),
+	.X(N4END_i[9])
+	);
+
+	my_buf N4END_inbuf_6 (
+	.A(N4END[10]),
+	.X(N4END_i[10])
+	);
+
+	my_buf N4END_inbuf_7 (
+	.A(N4END[11]),
+	.X(N4END_i[11])
+	);
+
+	my_buf N4END_inbuf_8 (
+	.A(N4END[12]),
+	.X(N4END_i[12])
+	);
+
+	my_buf N4END_inbuf_9 (
+	.A(N4END[13]),
+	.X(N4END_i[13])
+	);
+
+	my_buf N4END_inbuf_10 (
+	.A(N4END[14]),
+	.X(N4END_i[14])
+	);
+
+	my_buf N4END_inbuf_11 (
+	.A(N4END[15]),
+	.X(N4END_i[15])
+	);
+
+	my_buf N4BEG_outbuf_0 (
+	.A(N4BEG_i[0]),
+	.X(N4BEG[0])
+	);
+
+	my_buf N4BEG_outbuf_1 (
+	.A(N4BEG_i[1]),
+	.X(N4BEG[1])
+	);
+
+	my_buf N4BEG_outbuf_2 (
+	.A(N4BEG_i[2]),
+	.X(N4BEG[2])
+	);
+
+	my_buf N4BEG_outbuf_3 (
+	.A(N4BEG_i[3]),
+	.X(N4BEG[3])
+	);
+
+	my_buf N4BEG_outbuf_4 (
+	.A(N4BEG_i[4]),
+	.X(N4BEG[4])
+	);
+
+	my_buf N4BEG_outbuf_5 (
+	.A(N4BEG_i[5]),
+	.X(N4BEG[5])
+	);
+
+	my_buf N4BEG_outbuf_6 (
+	.A(N4BEG_i[6]),
+	.X(N4BEG[6])
+	);
+
+	my_buf N4BEG_outbuf_7 (
+	.A(N4BEG_i[7]),
+	.X(N4BEG[7])
+	);
+
+	my_buf N4BEG_outbuf_8 (
+	.A(N4BEG_i[8]),
+	.X(N4BEG[8])
+	);
+
+	my_buf N4BEG_outbuf_9 (
+	.A(N4BEG_i[9]),
+	.X(N4BEG[9])
+	);
+
+	my_buf N4BEG_outbuf_10 (
+	.A(N4BEG_i[10]),
+	.X(N4BEG[10])
+	);
+
+	my_buf N4BEG_outbuf_11 (
+	.A(N4BEG_i[11]),
+	.X(N4BEG[11])
+	);
+
+	wire [15:0] NN4END_i;
+	wire [11:0] NN4BEG_i;
+	assign NN4BEG_i[15-4:0] = NN4END_i[15:4];
+
+	my_buf NN4END_inbuf_0 (
+	.A(NN4END[4]),
+	.X(NN4END_i[4])
+	);
+
+	my_buf NN4END_inbuf_1 (
+	.A(NN4END[5]),
+	.X(NN4END_i[5])
+	);
+
+	my_buf NN4END_inbuf_2 (
+	.A(NN4END[6]),
+	.X(NN4END_i[6])
+	);
+
+	my_buf NN4END_inbuf_3 (
+	.A(NN4END[7]),
+	.X(NN4END_i[7])
+	);
+
+	my_buf NN4END_inbuf_4 (
+	.A(NN4END[8]),
+	.X(NN4END_i[8])
+	);
+
+	my_buf NN4END_inbuf_5 (
+	.A(NN4END[9]),
+	.X(NN4END_i[9])
+	);
+
+	my_buf NN4END_inbuf_6 (
+	.A(NN4END[10]),
+	.X(NN4END_i[10])
+	);
+
+	my_buf NN4END_inbuf_7 (
+	.A(NN4END[11]),
+	.X(NN4END_i[11])
+	);
+
+	my_buf NN4END_inbuf_8 (
+	.A(NN4END[12]),
+	.X(NN4END_i[12])
+	);
+
+	my_buf NN4END_inbuf_9 (
+	.A(NN4END[13]),
+	.X(NN4END_i[13])
+	);
+
+	my_buf NN4END_inbuf_10 (
+	.A(NN4END[14]),
+	.X(NN4END_i[14])
+	);
+
+	my_buf NN4END_inbuf_11 (
+	.A(NN4END[15]),
+	.X(NN4END_i[15])
+	);
+
+	my_buf NN4BEG_outbuf_0 (
+	.A(NN4BEG_i[0]),
+	.X(NN4BEG[0])
+	);
+
+	my_buf NN4BEG_outbuf_1 (
+	.A(NN4BEG_i[1]),
+	.X(NN4BEG[1])
+	);
+
+	my_buf NN4BEG_outbuf_2 (
+	.A(NN4BEG_i[2]),
+	.X(NN4BEG[2])
+	);
+
+	my_buf NN4BEG_outbuf_3 (
+	.A(NN4BEG_i[3]),
+	.X(NN4BEG[3])
+	);
+
+	my_buf NN4BEG_outbuf_4 (
+	.A(NN4BEG_i[4]),
+	.X(NN4BEG[4])
+	);
+
+	my_buf NN4BEG_outbuf_5 (
+	.A(NN4BEG_i[5]),
+	.X(NN4BEG[5])
+	);
+
+	my_buf NN4BEG_outbuf_6 (
+	.A(NN4BEG_i[6]),
+	.X(NN4BEG[6])
+	);
+
+	my_buf NN4BEG_outbuf_7 (
+	.A(NN4BEG_i[7]),
+	.X(NN4BEG[7])
+	);
+
+	my_buf NN4BEG_outbuf_8 (
+	.A(NN4BEG_i[8]),
+	.X(NN4BEG[8])
+	);
+
+	my_buf NN4BEG_outbuf_9 (
+	.A(NN4BEG_i[9]),
+	.X(NN4BEG[9])
+	);
+
+	my_buf NN4BEG_outbuf_10 (
+	.A(NN4BEG_i[10]),
+	.X(NN4BEG[10])
+	);
+
+	my_buf NN4BEG_outbuf_11 (
+	.A(NN4BEG_i[11]),
+	.X(NN4BEG[11])
+	);
+
+	wire [15:0] EE4END_i;
+	wire [11:0] EE4BEG_i;
+	assign EE4BEG_i[15-4:0] = EE4END_i[15:4];
+
+	my_buf EE4END_inbuf_0 (
+	.A(EE4END[4]),
+	.X(EE4END_i[4])
+	);
+
+	my_buf EE4END_inbuf_1 (
+	.A(EE4END[5]),
+	.X(EE4END_i[5])
+	);
+
+	my_buf EE4END_inbuf_2 (
+	.A(EE4END[6]),
+	.X(EE4END_i[6])
+	);
+
+	my_buf EE4END_inbuf_3 (
+	.A(EE4END[7]),
+	.X(EE4END_i[7])
+	);
+
+	my_buf EE4END_inbuf_4 (
+	.A(EE4END[8]),
+	.X(EE4END_i[8])
+	);
+
+	my_buf EE4END_inbuf_5 (
+	.A(EE4END[9]),
+	.X(EE4END_i[9])
+	);
+
+	my_buf EE4END_inbuf_6 (
+	.A(EE4END[10]),
+	.X(EE4END_i[10])
+	);
+
+	my_buf EE4END_inbuf_7 (
+	.A(EE4END[11]),
+	.X(EE4END_i[11])
+	);
+
+	my_buf EE4END_inbuf_8 (
+	.A(EE4END[12]),
+	.X(EE4END_i[12])
+	);
+
+	my_buf EE4END_inbuf_9 (
+	.A(EE4END[13]),
+	.X(EE4END_i[13])
+	);
+
+	my_buf EE4END_inbuf_10 (
+	.A(EE4END[14]),
+	.X(EE4END_i[14])
+	);
+
+	my_buf EE4END_inbuf_11 (
+	.A(EE4END[15]),
+	.X(EE4END_i[15])
+	);
+
+	my_buf EE4BEG_outbuf_0 (
+	.A(EE4BEG_i[0]),
+	.X(EE4BEG[0])
+	);
+
+	my_buf EE4BEG_outbuf_1 (
+	.A(EE4BEG_i[1]),
+	.X(EE4BEG[1])
+	);
+
+	my_buf EE4BEG_outbuf_2 (
+	.A(EE4BEG_i[2]),
+	.X(EE4BEG[2])
+	);
+
+	my_buf EE4BEG_outbuf_3 (
+	.A(EE4BEG_i[3]),
+	.X(EE4BEG[3])
+	);
+
+	my_buf EE4BEG_outbuf_4 (
+	.A(EE4BEG_i[4]),
+	.X(EE4BEG[4])
+	);
+
+	my_buf EE4BEG_outbuf_5 (
+	.A(EE4BEG_i[5]),
+	.X(EE4BEG[5])
+	);
+
+	my_buf EE4BEG_outbuf_6 (
+	.A(EE4BEG_i[6]),
+	.X(EE4BEG[6])
+	);
+
+	my_buf EE4BEG_outbuf_7 (
+	.A(EE4BEG_i[7]),
+	.X(EE4BEG[7])
+	);
+
+	my_buf EE4BEG_outbuf_8 (
+	.A(EE4BEG_i[8]),
+	.X(EE4BEG[8])
+	);
+
+	my_buf EE4BEG_outbuf_9 (
+	.A(EE4BEG_i[9]),
+	.X(EE4BEG[9])
+	);
+
+	my_buf EE4BEG_outbuf_10 (
+	.A(EE4BEG_i[10]),
+	.X(EE4BEG[10])
+	);
+
+	my_buf EE4BEG_outbuf_11 (
+	.A(EE4BEG_i[11]),
+	.X(EE4BEG[11])
+	);
+
+	wire [11:0] E6END_i;
+	wire [9:0] E6BEG_i;
+	assign E6BEG_i[11-2:0] = E6END_i[11:2];
+
+	my_buf E6END_inbuf_0 (
+	.A(E6END[2]),
+	.X(E6END_i[2])
+	);
+
+	my_buf E6END_inbuf_1 (
+	.A(E6END[3]),
+	.X(E6END_i[3])
+	);
+
+	my_buf E6END_inbuf_2 (
+	.A(E6END[4]),
+	.X(E6END_i[4])
+	);
+
+	my_buf E6END_inbuf_3 (
+	.A(E6END[5]),
+	.X(E6END_i[5])
+	);
+
+	my_buf E6END_inbuf_4 (
+	.A(E6END[6]),
+	.X(E6END_i[6])
+	);
+
+	my_buf E6END_inbuf_5 (
+	.A(E6END[7]),
+	.X(E6END_i[7])
+	);
+
+	my_buf E6END_inbuf_6 (
+	.A(E6END[8]),
+	.X(E6END_i[8])
+	);
+
+	my_buf E6END_inbuf_7 (
+	.A(E6END[9]),
+	.X(E6END_i[9])
+	);
+
+	my_buf E6END_inbuf_8 (
+	.A(E6END[10]),
+	.X(E6END_i[10])
+	);
+
+	my_buf E6END_inbuf_9 (
+	.A(E6END[11]),
+	.X(E6END_i[11])
+	);
+
+	my_buf E6BEG_outbuf_0 (
+	.A(E6BEG_i[0]),
+	.X(E6BEG[0])
+	);
+
+	my_buf E6BEG_outbuf_1 (
+	.A(E6BEG_i[1]),
+	.X(E6BEG[1])
+	);
+
+	my_buf E6BEG_outbuf_2 (
+	.A(E6BEG_i[2]),
+	.X(E6BEG[2])
+	);
+
+	my_buf E6BEG_outbuf_3 (
+	.A(E6BEG_i[3]),
+	.X(E6BEG[3])
+	);
+
+	my_buf E6BEG_outbuf_4 (
+	.A(E6BEG_i[4]),
+	.X(E6BEG[4])
+	);
+
+	my_buf E6BEG_outbuf_5 (
+	.A(E6BEG_i[5]),
+	.X(E6BEG[5])
+	);
+
+	my_buf E6BEG_outbuf_6 (
+	.A(E6BEG_i[6]),
+	.X(E6BEG[6])
+	);
+
+	my_buf E6BEG_outbuf_7 (
+	.A(E6BEG_i[7]),
+	.X(E6BEG[7])
+	);
+
+	my_buf E6BEG_outbuf_8 (
+	.A(E6BEG_i[8]),
+	.X(E6BEG[8])
+	);
+
+	my_buf E6BEG_outbuf_9 (
+	.A(E6BEG_i[9]),
+	.X(E6BEG[9])
+	);
+
+	wire [15:0] S4END_i;
+	wire [11:0] S4BEG_i;
+	assign S4BEG_i[15-4:0] = S4END_i[15:4];
+
+	my_buf S4END_inbuf_0 (
+	.A(S4END[4]),
+	.X(S4END_i[4])
+	);
+
+	my_buf S4END_inbuf_1 (
+	.A(S4END[5]),
+	.X(S4END_i[5])
+	);
+
+	my_buf S4END_inbuf_2 (
+	.A(S4END[6]),
+	.X(S4END_i[6])
+	);
+
+	my_buf S4END_inbuf_3 (
+	.A(S4END[7]),
+	.X(S4END_i[7])
+	);
+
+	my_buf S4END_inbuf_4 (
+	.A(S4END[8]),
+	.X(S4END_i[8])
+	);
+
+	my_buf S4END_inbuf_5 (
+	.A(S4END[9]),
+	.X(S4END_i[9])
+	);
+
+	my_buf S4END_inbuf_6 (
+	.A(S4END[10]),
+	.X(S4END_i[10])
+	);
+
+	my_buf S4END_inbuf_7 (
+	.A(S4END[11]),
+	.X(S4END_i[11])
+	);
+
+	my_buf S4END_inbuf_8 (
+	.A(S4END[12]),
+	.X(S4END_i[12])
+	);
+
+	my_buf S4END_inbuf_9 (
+	.A(S4END[13]),
+	.X(S4END_i[13])
+	);
+
+	my_buf S4END_inbuf_10 (
+	.A(S4END[14]),
+	.X(S4END_i[14])
+	);
+
+	my_buf S4END_inbuf_11 (
+	.A(S4END[15]),
+	.X(S4END_i[15])
+	);
+
+	my_buf S4BEG_outbuf_0 (
+	.A(S4BEG_i[0]),
+	.X(S4BEG[0])
+	);
+
+	my_buf S4BEG_outbuf_1 (
+	.A(S4BEG_i[1]),
+	.X(S4BEG[1])
+	);
+
+	my_buf S4BEG_outbuf_2 (
+	.A(S4BEG_i[2]),
+	.X(S4BEG[2])
+	);
+
+	my_buf S4BEG_outbuf_3 (
+	.A(S4BEG_i[3]),
+	.X(S4BEG[3])
+	);
+
+	my_buf S4BEG_outbuf_4 (
+	.A(S4BEG_i[4]),
+	.X(S4BEG[4])
+	);
+
+	my_buf S4BEG_outbuf_5 (
+	.A(S4BEG_i[5]),
+	.X(S4BEG[5])
+	);
+
+	my_buf S4BEG_outbuf_6 (
+	.A(S4BEG_i[6]),
+	.X(S4BEG[6])
+	);
+
+	my_buf S4BEG_outbuf_7 (
+	.A(S4BEG_i[7]),
+	.X(S4BEG[7])
+	);
+
+	my_buf S4BEG_outbuf_8 (
+	.A(S4BEG_i[8]),
+	.X(S4BEG[8])
+	);
+
+	my_buf S4BEG_outbuf_9 (
+	.A(S4BEG_i[9]),
+	.X(S4BEG[9])
+	);
+
+	my_buf S4BEG_outbuf_10 (
+	.A(S4BEG_i[10]),
+	.X(S4BEG[10])
+	);
+
+	my_buf S4BEG_outbuf_11 (
+	.A(S4BEG_i[11]),
+	.X(S4BEG[11])
+	);
+
+	wire [15:0] SS4END_i;
+	wire [11:0] SS4BEG_i;
+	assign SS4BEG_i[15-4:0] = SS4END_i[15:4];
+
+	my_buf SS4END_inbuf_0 (
+	.A(SS4END[4]),
+	.X(SS4END_i[4])
+	);
+
+	my_buf SS4END_inbuf_1 (
+	.A(SS4END[5]),
+	.X(SS4END_i[5])
+	);
+
+	my_buf SS4END_inbuf_2 (
+	.A(SS4END[6]),
+	.X(SS4END_i[6])
+	);
+
+	my_buf SS4END_inbuf_3 (
+	.A(SS4END[7]),
+	.X(SS4END_i[7])
+	);
+
+	my_buf SS4END_inbuf_4 (
+	.A(SS4END[8]),
+	.X(SS4END_i[8])
+	);
+
+	my_buf SS4END_inbuf_5 (
+	.A(SS4END[9]),
+	.X(SS4END_i[9])
+	);
+
+	my_buf SS4END_inbuf_6 (
+	.A(SS4END[10]),
+	.X(SS4END_i[10])
+	);
+
+	my_buf SS4END_inbuf_7 (
+	.A(SS4END[11]),
+	.X(SS4END_i[11])
+	);
+
+	my_buf SS4END_inbuf_8 (
+	.A(SS4END[12]),
+	.X(SS4END_i[12])
+	);
+
+	my_buf SS4END_inbuf_9 (
+	.A(SS4END[13]),
+	.X(SS4END_i[13])
+	);
+
+	my_buf SS4END_inbuf_10 (
+	.A(SS4END[14]),
+	.X(SS4END_i[14])
+	);
+
+	my_buf SS4END_inbuf_11 (
+	.A(SS4END[15]),
+	.X(SS4END_i[15])
+	);
+
+	my_buf SS4BEG_outbuf_0 (
+	.A(SS4BEG_i[0]),
+	.X(SS4BEG[0])
+	);
+
+	my_buf SS4BEG_outbuf_1 (
+	.A(SS4BEG_i[1]),
+	.X(SS4BEG[1])
+	);
+
+	my_buf SS4BEG_outbuf_2 (
+	.A(SS4BEG_i[2]),
+	.X(SS4BEG[2])
+	);
+
+	my_buf SS4BEG_outbuf_3 (
+	.A(SS4BEG_i[3]),
+	.X(SS4BEG[3])
+	);
+
+	my_buf SS4BEG_outbuf_4 (
+	.A(SS4BEG_i[4]),
+	.X(SS4BEG[4])
+	);
+
+	my_buf SS4BEG_outbuf_5 (
+	.A(SS4BEG_i[5]),
+	.X(SS4BEG[5])
+	);
+
+	my_buf SS4BEG_outbuf_6 (
+	.A(SS4BEG_i[6]),
+	.X(SS4BEG[6])
+	);
+
+	my_buf SS4BEG_outbuf_7 (
+	.A(SS4BEG_i[7]),
+	.X(SS4BEG[7])
+	);
+
+	my_buf SS4BEG_outbuf_8 (
+	.A(SS4BEG_i[8]),
+	.X(SS4BEG[8])
+	);
+
+	my_buf SS4BEG_outbuf_9 (
+	.A(SS4BEG_i[9]),
+	.X(SS4BEG[9])
+	);
+
+	my_buf SS4BEG_outbuf_10 (
+	.A(SS4BEG_i[10]),
+	.X(SS4BEG[10])
+	);
+
+	my_buf SS4BEG_outbuf_11 (
+	.A(SS4BEG_i[11]),
+	.X(SS4BEG[11])
+	);
+
+	wire [15:0] WW4END_i;
+	wire [11:0] WW4BEG_i;
+	assign WW4BEG_i[15-4:0] = WW4END_i[15:4];
+
+	my_buf WW4END_inbuf_0 (
+	.A(WW4END[4]),
+	.X(WW4END_i[4])
+	);
+
+	my_buf WW4END_inbuf_1 (
+	.A(WW4END[5]),
+	.X(WW4END_i[5])
+	);
+
+	my_buf WW4END_inbuf_2 (
+	.A(WW4END[6]),
+	.X(WW4END_i[6])
+	);
+
+	my_buf WW4END_inbuf_3 (
+	.A(WW4END[7]),
+	.X(WW4END_i[7])
+	);
+
+	my_buf WW4END_inbuf_4 (
+	.A(WW4END[8]),
+	.X(WW4END_i[8])
+	);
+
+	my_buf WW4END_inbuf_5 (
+	.A(WW4END[9]),
+	.X(WW4END_i[9])
+	);
+
+	my_buf WW4END_inbuf_6 (
+	.A(WW4END[10]),
+	.X(WW4END_i[10])
+	);
+
+	my_buf WW4END_inbuf_7 (
+	.A(WW4END[11]),
+	.X(WW4END_i[11])
+	);
+
+	my_buf WW4END_inbuf_8 (
+	.A(WW4END[12]),
+	.X(WW4END_i[12])
+	);
+
+	my_buf WW4END_inbuf_9 (
+	.A(WW4END[13]),
+	.X(WW4END_i[13])
+	);
+
+	my_buf WW4END_inbuf_10 (
+	.A(WW4END[14]),
+	.X(WW4END_i[14])
+	);
+
+	my_buf WW4END_inbuf_11 (
+	.A(WW4END[15]),
+	.X(WW4END_i[15])
+	);
+
+	my_buf WW4BEG_outbuf_0 (
+	.A(WW4BEG_i[0]),
+	.X(WW4BEG[0])
+	);
+
+	my_buf WW4BEG_outbuf_1 (
+	.A(WW4BEG_i[1]),
+	.X(WW4BEG[1])
+	);
+
+	my_buf WW4BEG_outbuf_2 (
+	.A(WW4BEG_i[2]),
+	.X(WW4BEG[2])
+	);
+
+	my_buf WW4BEG_outbuf_3 (
+	.A(WW4BEG_i[3]),
+	.X(WW4BEG[3])
+	);
+
+	my_buf WW4BEG_outbuf_4 (
+	.A(WW4BEG_i[4]),
+	.X(WW4BEG[4])
+	);
+
+	my_buf WW4BEG_outbuf_5 (
+	.A(WW4BEG_i[5]),
+	.X(WW4BEG[5])
+	);
+
+	my_buf WW4BEG_outbuf_6 (
+	.A(WW4BEG_i[6]),
+	.X(WW4BEG[6])
+	);
+
+	my_buf WW4BEG_outbuf_7 (
+	.A(WW4BEG_i[7]),
+	.X(WW4BEG[7])
+	);
+
+	my_buf WW4BEG_outbuf_8 (
+	.A(WW4BEG_i[8]),
+	.X(WW4BEG[8])
+	);
+
+	my_buf WW4BEG_outbuf_9 (
+	.A(WW4BEG_i[9]),
+	.X(WW4BEG[9])
+	);
+
+	my_buf WW4BEG_outbuf_10 (
+	.A(WW4BEG_i[10]),
+	.X(WW4BEG[10])
+	);
+
+	my_buf WW4BEG_outbuf_11 (
+	.A(WW4BEG_i[11]),
+	.X(WW4BEG[11])
+	);
+
+	wire [11:0] W6END_i;
+	wire [9:0] W6BEG_i;
+	assign W6BEG_i[11-2:0] = W6END_i[11:2];
+
+	my_buf W6END_inbuf_0 (
+	.A(W6END[2]),
+	.X(W6END_i[2])
+	);
+
+	my_buf W6END_inbuf_1 (
+	.A(W6END[3]),
+	.X(W6END_i[3])
+	);
+
+	my_buf W6END_inbuf_2 (
+	.A(W6END[4]),
+	.X(W6END_i[4])
+	);
+
+	my_buf W6END_inbuf_3 (
+	.A(W6END[5]),
+	.X(W6END_i[5])
+	);
+
+	my_buf W6END_inbuf_4 (
+	.A(W6END[6]),
+	.X(W6END_i[6])
+	);
+
+	my_buf W6END_inbuf_5 (
+	.A(W6END[7]),
+	.X(W6END_i[7])
+	);
+
+	my_buf W6END_inbuf_6 (
+	.A(W6END[8]),
+	.X(W6END_i[8])
+	);
+
+	my_buf W6END_inbuf_7 (
+	.A(W6END[9]),
+	.X(W6END_i[9])
+	);
+
+	my_buf W6END_inbuf_8 (
+	.A(W6END[10]),
+	.X(W6END_i[10])
+	);
+
+	my_buf W6END_inbuf_9 (
+	.A(W6END[11]),
+	.X(W6END_i[11])
+	);
+
+	my_buf W6BEG_outbuf_0 (
+	.A(W6BEG_i[0]),
+	.X(W6BEG[0])
+	);
+
+	my_buf W6BEG_outbuf_1 (
+	.A(W6BEG_i[1]),
+	.X(W6BEG[1])
+	);
+
+	my_buf W6BEG_outbuf_2 (
+	.A(W6BEG_i[2]),
+	.X(W6BEG[2])
+	);
+
+	my_buf W6BEG_outbuf_3 (
+	.A(W6BEG_i[3]),
+	.X(W6BEG[3])
+	);
+
+	my_buf W6BEG_outbuf_4 (
+	.A(W6BEG_i[4]),
+	.X(W6BEG[4])
+	);
+
+	my_buf W6BEG_outbuf_5 (
+	.A(W6BEG_i[5]),
+	.X(W6BEG[5])
+	);
+
+	my_buf W6BEG_outbuf_6 (
+	.A(W6BEG_i[6]),
+	.X(W6BEG[6])
+	);
+
+	my_buf W6BEG_outbuf_7 (
+	.A(W6BEG_i[7]),
+	.X(W6BEG[7])
+	);
+
+	my_buf W6BEG_outbuf_8 (
+	.A(W6BEG_i[8]),
+	.X(W6BEG[8])
+	);
+
+	my_buf W6BEG_outbuf_9 (
+	.A(W6BEG_i[9]),
+	.X(W6BEG[9])
+	);
+
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	DSP_bot_ConfigMem Inst_DSP_bot_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	MULADD Inst_MULADD (
+	.A7(A7),
+	.A6(A6),
+	.A5(A5),
+	.A4(A4),
+	.A3(A3),
+	.A2(A2),
+	.A1(A1),
+	.A0(A0),
+	.B7(B7),
+	.B6(B6),
+	.B5(B5),
+	.B4(B4),
+	.B3(B3),
+	.B2(B2),
+	.B1(B1),
+	.B0(B0),
+	.C19(C19),
+	.C18(C18),
+	.C17(C17),
+	.C16(C16),
+	.C15(C15),
+	.C14(C14),
+	.C13(C13),
+	.C12(C12),
+	.C11(C11),
+	.C10(C10),
+	.C9(C9),
+	.C8(C8),
+	.C7(C7),
+	.C6(C6),
+	.C5(C5),
+	.C4(C4),
+	.C3(C3),
+	.C2(C2),
+	.C1(C1),
+	.C0(C0),
+	.clr(clr),
+	.Q19(Q19),
+	.Q18(Q18),
+	.Q17(Q17),
+	.Q16(Q16),
+	.Q15(Q15),
+	.Q14(Q14),
+	.Q13(Q13),
+	.Q12(Q12),
+	.Q11(Q11),
+	.Q10(Q10),
+	.Q9(Q9),
+	.Q8(Q8),
+	.Q7(Q7),
+	.Q6(Q6),
+	.Q5(Q5),
+	.Q4(Q4),
+	.Q3(Q3),
+	.Q2(Q2),
+	.Q1(Q1),
+	.Q0(Q0),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[6-1:0])
+	);
+
+
+//switch matrix component instantiation
+	DSP_bot_switch_matrix Inst_DSP_bot_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.top2bot0(top2bot[0]),
+	.top2bot1(top2bot[1]),
+	.top2bot2(top2bot[2]),
+	.top2bot3(top2bot[3]),
+	.top2bot4(top2bot[4]),
+	.top2bot5(top2bot[5]),
+	.top2bot6(top2bot[6]),
+	.top2bot7(top2bot[7]),
+	.top2bot8(top2bot[8]),
+	.top2bot9(top2bot[9]),
+	.top2bot10(top2bot[10]),
+	.top2bot11(top2bot[11]),
+	.top2bot12(top2bot[12]),
+	.top2bot13(top2bot[13]),
+	.top2bot14(top2bot[14]),
+	.top2bot15(top2bot[15]),
+	.top2bot16(top2bot[16]),
+	.top2bot17(top2bot[17]),
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.Q19(Q19),
+	.Q18(Q18),
+	.Q17(Q17),
+	.Q16(Q16),
+	.Q15(Q15),
+	.Q14(Q14),
+	.Q13(Q13),
+	.Q12(Q12),
+	.Q11(Q11),
+	.Q10(Q10),
+	.Q9(Q9),
+	.Q8(Q8),
+	.Q7(Q7),
+	.Q6(Q6),
+	.Q5(Q5),
+	.Q4(Q4),
+	.Q3(Q3),
+	.Q2(Q2),
+	.Q1(Q1),
+	.Q0(Q0),
+	.J2MID_ABa_END0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_END1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_END2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_END3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_END0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_END1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_END2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_END3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_END0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_END1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_END2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_END3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_END0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_END1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_END2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_END3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_END0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_END1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_END2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_END3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_END0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_END1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_END2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_END3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_END0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_END1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_END2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_END3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_END0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_END1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_END2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_END3(J2MID_GHb_BEG[3]),
+	.J2END_AB_END0(J2END_AB_BEG[0]),
+	.J2END_AB_END1(J2END_AB_BEG[1]),
+	.J2END_AB_END2(J2END_AB_BEG[2]),
+	.J2END_AB_END3(J2END_AB_BEG[3]),
+	.J2END_CD_END0(J2END_CD_BEG[0]),
+	.J2END_CD_END1(J2END_CD_BEG[1]),
+	.J2END_CD_END2(J2END_CD_BEG[2]),
+	.J2END_CD_END3(J2END_CD_BEG[3]),
+	.J2END_EF_END0(J2END_EF_BEG[0]),
+	.J2END_EF_END1(J2END_EF_BEG[1]),
+	.J2END_EF_END2(J2END_EF_BEG[2]),
+	.J2END_EF_END3(J2END_EF_BEG[3]),
+	.J2END_GH_END0(J2END_GH_BEG[0]),
+	.J2END_GH_END1(J2END_GH_BEG[1]),
+	.J2END_GH_END2(J2END_GH_BEG[2]),
+	.J2END_GH_END3(J2END_GH_BEG[3]),
+	.JN2END0(JN2BEG[0]),
+	.JN2END1(JN2BEG[1]),
+	.JN2END2(JN2BEG[2]),
+	.JN2END3(JN2BEG[3]),
+	.JN2END4(JN2BEG[4]),
+	.JN2END5(JN2BEG[5]),
+	.JN2END6(JN2BEG[6]),
+	.JN2END7(JN2BEG[7]),
+	.JE2END0(JE2BEG[0]),
+	.JE2END1(JE2BEG[1]),
+	.JE2END2(JE2BEG[2]),
+	.JE2END3(JE2BEG[3]),
+	.JE2END4(JE2BEG[4]),
+	.JE2END5(JE2BEG[5]),
+	.JE2END6(JE2BEG[6]),
+	.JE2END7(JE2BEG[7]),
+	.JS2END0(JS2BEG[0]),
+	.JS2END1(JS2BEG[1]),
+	.JS2END2(JS2BEG[2]),
+	.JS2END3(JS2BEG[3]),
+	.JS2END4(JS2BEG[4]),
+	.JS2END5(JS2BEG[5]),
+	.JS2END6(JS2BEG[6]),
+	.JS2END7(JS2BEG[7]),
+	.JW2END0(JW2BEG[0]),
+	.JW2END1(JW2BEG[1]),
+	.JW2END2(JW2BEG[2]),
+	.JW2END3(JW2BEG[3]),
+	.JW2END4(JW2BEG[4]),
+	.JW2END5(JW2BEG[5]),
+	.JW2END6(JW2BEG[6]),
+	.JW2END7(JW2BEG[7]),
+	.J_l_AB_END0(J_l_AB_BEG[0]),
+	.J_l_AB_END1(J_l_AB_BEG[1]),
+	.J_l_AB_END2(J_l_AB_BEG[2]),
+	.J_l_AB_END3(J_l_AB_BEG[3]),
+	.J_l_CD_END0(J_l_CD_BEG[0]),
+	.J_l_CD_END1(J_l_CD_BEG[1]),
+	.J_l_CD_END2(J_l_CD_BEG[2]),
+	.J_l_CD_END3(J_l_CD_BEG[3]),
+	.J_l_EF_END0(J_l_EF_BEG[0]),
+	.J_l_EF_END1(J_l_EF_BEG[1]),
+	.J_l_EF_END2(J_l_EF_BEG[2]),
+	.J_l_EF_END3(J_l_EF_BEG[3]),
+	.J_l_GH_END0(J_l_GH_BEG[0]),
+	.J_l_GH_END1(J_l_GH_BEG[1]),
+	.J_l_GH_END2(J_l_GH_BEG[2]),
+	.J_l_GH_END3(J_l_GH_BEG[3]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[12]),
+	.N4BEG1(N4BEG[13]),
+	.N4BEG2(N4BEG[14]),
+	.N4BEG3(N4BEG[15]),
+	.NN4BEG0(NN4BEG[12]),
+	.NN4BEG1(NN4BEG[13]),
+	.NN4BEG2(NN4BEG[14]),
+	.NN4BEG3(NN4BEG[15]),
+	.bot2top0(bot2top[0]),
+	.bot2top1(bot2top[1]),
+	.bot2top2(bot2top[2]),
+	.bot2top3(bot2top[3]),
+	.bot2top4(bot2top[4]),
+	.bot2top5(bot2top[5]),
+	.bot2top6(bot2top[6]),
+	.bot2top7(bot2top[7]),
+	.bot2top8(bot2top[8]),
+	.bot2top9(bot2top[9]),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[12]),
+	.EE4BEG1(EE4BEG[13]),
+	.EE4BEG2(EE4BEG[14]),
+	.EE4BEG3(EE4BEG[15]),
+	.E6BEG0(E6BEG[10]),
+	.E6BEG1(E6BEG[11]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[12]),
+	.S4BEG1(S4BEG[13]),
+	.S4BEG2(S4BEG[14]),
+	.S4BEG3(S4BEG[15]),
+	.SS4BEG0(SS4BEG[12]),
+	.SS4BEG1(SS4BEG[13]),
+	.SS4BEG2(SS4BEG[14]),
+	.SS4BEG3(SS4BEG[15]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[12]),
+	.WW4BEG1(WW4BEG[13]),
+	.WW4BEG2(WW4BEG[14]),
+	.WW4BEG3(WW4BEG[15]),
+	.W6BEG0(W6BEG[10]),
+	.W6BEG1(W6BEG[11]),
+	.A7(A7),
+	.A6(A6),
+	.A5(A5),
+	.A4(A4),
+	.A3(A3),
+	.A2(A2),
+	.A1(A1),
+	.A0(A0),
+	.B7(B7),
+	.B6(B6),
+	.B5(B5),
+	.B4(B4),
+	.B3(B3),
+	.B2(B2),
+	.B1(B1),
+	.B0(B0),
+	.C19(C19),
+	.C18(C18),
+	.C17(C17),
+	.C16(C16),
+	.C15(C15),
+	.C14(C14),
+	.C13(C13),
+	.C12(C12),
+	.C11(C11),
+	.C10(C10),
+	.C9(C9),
+	.C8(C8),
+	.C7(C7),
+	.C6(C6),
+	.C5(C5),
+	.C4(C4),
+	.C3(C3),
+	.C2(C2),
+	.C1(C1),
+	.C0(C0),
+	.clr(clr),
+	.J2MID_ABa_BEG0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_BEG1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_BEG2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_BEG3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_BEG0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_BEG1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_BEG2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_BEG3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_BEG0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_BEG1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_BEG2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_BEG3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_BEG0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_BEG1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_BEG2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_BEG3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_BEG0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_BEG1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_BEG2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_BEG3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_BEG0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_BEG1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_BEG2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_BEG3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_BEG0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_BEG1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_BEG2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_BEG3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_BEG0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_BEG1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_BEG2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_BEG3(J2MID_GHb_BEG[3]),
+	.J2END_AB_BEG0(J2END_AB_BEG[0]),
+	.J2END_AB_BEG1(J2END_AB_BEG[1]),
+	.J2END_AB_BEG2(J2END_AB_BEG[2]),
+	.J2END_AB_BEG3(J2END_AB_BEG[3]),
+	.J2END_CD_BEG0(J2END_CD_BEG[0]),
+	.J2END_CD_BEG1(J2END_CD_BEG[1]),
+	.J2END_CD_BEG2(J2END_CD_BEG[2]),
+	.J2END_CD_BEG3(J2END_CD_BEG[3]),
+	.J2END_EF_BEG0(J2END_EF_BEG[0]),
+	.J2END_EF_BEG1(J2END_EF_BEG[1]),
+	.J2END_EF_BEG2(J2END_EF_BEG[2]),
+	.J2END_EF_BEG3(J2END_EF_BEG[3]),
+	.J2END_GH_BEG0(J2END_GH_BEG[0]),
+	.J2END_GH_BEG1(J2END_GH_BEG[1]),
+	.J2END_GH_BEG2(J2END_GH_BEG[2]),
+	.J2END_GH_BEG3(J2END_GH_BEG[3]),
+	.JN2BEG0(JN2BEG[0]),
+	.JN2BEG1(JN2BEG[1]),
+	.JN2BEG2(JN2BEG[2]),
+	.JN2BEG3(JN2BEG[3]),
+	.JN2BEG4(JN2BEG[4]),
+	.JN2BEG5(JN2BEG[5]),
+	.JN2BEG6(JN2BEG[6]),
+	.JN2BEG7(JN2BEG[7]),
+	.JE2BEG0(JE2BEG[0]),
+	.JE2BEG1(JE2BEG[1]),
+	.JE2BEG2(JE2BEG[2]),
+	.JE2BEG3(JE2BEG[3]),
+	.JE2BEG4(JE2BEG[4]),
+	.JE2BEG5(JE2BEG[5]),
+	.JE2BEG6(JE2BEG[6]),
+	.JE2BEG7(JE2BEG[7]),
+	.JS2BEG0(JS2BEG[0]),
+	.JS2BEG1(JS2BEG[1]),
+	.JS2BEG2(JS2BEG[2]),
+	.JS2BEG3(JS2BEG[3]),
+	.JS2BEG4(JS2BEG[4]),
+	.JS2BEG5(JS2BEG[5]),
+	.JS2BEG6(JS2BEG[6]),
+	.JS2BEG7(JS2BEG[7]),
+	.JW2BEG0(JW2BEG[0]),
+	.JW2BEG1(JW2BEG[1]),
+	.JW2BEG2(JW2BEG[2]),
+	.JW2BEG3(JW2BEG[3]),
+	.JW2BEG4(JW2BEG[4]),
+	.JW2BEG5(JW2BEG[5]),
+	.JW2BEG6(JW2BEG[6]),
+	.JW2BEG7(JW2BEG[7]),
+	.J_l_AB_BEG0(J_l_AB_BEG[0]),
+	.J_l_AB_BEG1(J_l_AB_BEG[1]),
+	.J_l_AB_BEG2(J_l_AB_BEG[2]),
+	.J_l_AB_BEG3(J_l_AB_BEG[3]),
+	.J_l_CD_BEG0(J_l_CD_BEG[0]),
+	.J_l_CD_BEG1(J_l_CD_BEG[1]),
+	.J_l_CD_BEG2(J_l_CD_BEG[2]),
+	.J_l_CD_BEG3(J_l_CD_BEG[3]),
+	.J_l_EF_BEG0(J_l_EF_BEG[0]),
+	.J_l_EF_BEG1(J_l_EF_BEG[1]),
+	.J_l_EF_BEG2(J_l_EF_BEG[2]),
+	.J_l_EF_BEG3(J_l_EF_BEG[3]),
+	.J_l_GH_BEG0(J_l_GH_BEG[0]),
+	.J_l_GH_BEG1(J_l_GH_BEG[1]),
+	.J_l_GH_BEG2(J_l_GH_BEG[2]),
+	.J_l_GH_BEG3(J_l_GH_BEG[3]),
+	.ConfigBits(ConfigBits[416-1:6]),
+	.ConfigBits_N(ConfigBits_N[416-1:6])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_tile.v b/verilog/rtl/eFPGA_core/DSP_tile.v
new file mode 100644
index 0000000..abd773c
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_tile.v
@@ -0,0 +1,260 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module DSP (top_N1BEG, top_N2BEG, top_N2BEGb, top_N4BEG, top_NN4BEG, top_S1END, top_S2MID, top_S2END, top_S4END, top_SS4END, top_E1BEG, top_E2BEG, top_E2BEGb, top_EE4BEG, top_E6BEG, top_E1END, top_E2MID, top_E2END, top_EE4END, top_E6END, top_W1BEG, top_W2BEG, top_W2BEGb, top_WW4BEG, top_W6BEG, top_W1END, top_W2MID, top_W2END, top_WW4END, top_W6END, bot_E1BEG, bot_E2BEG, bot_E2BEGb, bot_EE4BEG, bot_E6BEG, bot_E1END, bot_E2MID, bot_E2END, bot_EE4END, bot_E6END, bot_W1BEG, bot_W2BEG, bot_W2BEGb, bot_WW4BEG, bot_W6BEG, bot_W1END, bot_W2MID, bot_W2END, bot_WW4END, bot_W6END, bot_S1BEG, bot_S2BEG, bot_S2BEGb, bot_S4BEG, bot_SS4BEG, bot_N1END, bot_N2MID, bot_N2END, bot_N4END, bot_NN4END, UserCLK, UserCLKo, top_FrameData, top_FrameData_O, bot_FrameData, bot_FrameData_O, FrameStrobe, FrameStrobe_O);
+
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter top_NoConfigBits = 406;  // NOT 100% SURE HOW THIS WILL WORK OUT
+	parameter bot_NoConfigBits = 416;  // NOT 100% SURE HOW THIS WILL WORK OUT
+	
+	//top_NORTH
+	output [3:0] top_N1BEG;	 // wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] top_N2BEG;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] top_N2BEGb;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] top_N4BEG;	 // wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	output [15:0] top_NN4BEG;	 // wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	// These do not exist in top wrapper		 top_bot2top[9:0];	 // wires:10 X_offset:0 Y_offset:1  source_name:bot2top destination_name:NULL  
+	// These do not exist in top wrapper	input [3:0] top_N1END;	 // wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	// These do not exist in top wrapper	input [7:0] top_N2MID;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	// These do not exist in top wrapper	input [7:0] top_N2END;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	// These do not exist in top wrapper	input [15:0] top_N4END;	 // wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	// These do not exist in top wrapper	input [15:0] top_NN4END;	 // wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	
+	//top_SOUTH
+	// These do not exist in top wrapper		 top_S1BEG[3:0];	 // wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	// These do not exist in top wrapper		 top_S2BEG[7:0];	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	// These do not exist in top wrapper		 top_S2BEGb[7:0];	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	// These do not exist in top wrapper		 top_S4BEG[15:0];	 // wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	// These do not exist in top wrapper		 top_SS4BEG[15:0];	 // wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	input [3:0] top_S1END;	 // wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] top_S2MID;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] top_S2END;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] top_S4END;	 // wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [15:0] top_SS4END;	 // wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	// These do not exist in top wrapper		 top_top2bot[17:0];	 // wires:18 X_offset:0 Y_offset:-1  source_name:NULL destination_name:top2bot  
+	
+	//top_EAST
+	output [3:0] top_E1BEG;	 // wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] top_E2BEG;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] top_E2BEGb;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] top_EE4BEG;	 // wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] top_E6BEG;	 // wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] top_E1END;	 // wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] top_E2MID;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] top_E2END;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] top_EE4END;	 // wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] top_E6END;	 // wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	
+	//top_WEST
+	output [3:0] top_W1BEG;	 // wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] top_W2BEG;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] top_W2BEGb;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] top_WW4BEG;	 // wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] top_W6BEG;	 // wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] top_W1END;	 // wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] top_W2MID;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] top_W2END;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] top_WW4END;	 // wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] top_W6END;	 // wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	
+	//bot_NORTH
+	// These do not exist in top wrapper	output [3:0] bot_N1BEG;	 // wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	// These do not exist in top wrapper	output [7:0] bot_N2BEG;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	// These do not exist in top wrapper	output [7:0] bot_N2BEGb;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	// These do not exist in top wrapper	output [15:0] bot_N4BEG;	 // wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	// These do not exist in top wrapper	output [15:0] bot_NN4BEG;	 // wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	// These do not exist in top wrapper	// These do not exist in top wrapper		 bot_bot2top[9:0];	 // wires:10 X_offset:0 Y_offset:1  source_name:bot2top destination_name:NULL  
+	input [3:0] bot_N1END;	 // wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] bot_N2MID;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] bot_N2END;	 // wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] bot_N4END;	 // wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [15:0] bot_NN4END;	 // wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	
+	//bot_SOUTH
+	output [3:0] bot_S1BEG;	 // wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] bot_S2BEG;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] bot_S2BEGb;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] bot_S4BEG;	 // wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	output [15:0] bot_SS4BEG;	 // wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	// These do not exist in top wrapper	input [3:0] bot_S1END;	 // wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	// These do not exist in top wrapper	input [7:0] bot_S2MID;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	// These do not exist in top wrapper	input [7:0] bot_S2END;	 // wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	// These do not exist in top wrapper	input [15:0] bot_S4END;	 // wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	// These do not exist in top wrapper	input [15:0] bot_SS4END;	 // wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	// These do not exist in top wrapper		 bot_top2bot[17:0];	 // wires:18 X_offset:0 Y_offset:-1  source_name:NULL destination_name:top2bot  
+
+	//   bot_EAST
+	output [3:0] bot_E1BEG;	 // wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] bot_E2BEG;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] bot_E2BEGb;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] bot_EE4BEG;	 // wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] bot_E6BEG;	 // wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] bot_E1END;	 // wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] bot_E2MID;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] bot_E2END;	 // wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] bot_EE4END;	 // wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] bot_E6END;	 // wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	
+	//bot_WEST
+	output [3:0] bot_W1BEG;	 // wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] bot_W2BEG;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] bot_W2BEGb;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] bot_WW4BEG;	 // wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] bot_W6BEG;	 // wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] bot_W1END;	 // wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] bot_W2MID;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] bot_W2END;	 // wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] bot_WW4END;	 // wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] bot_W6END;	 // wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	
+	// Tile IO ports from BELs
+	input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	output UserCLKo; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+
+	input [FrameBitsPerRow-1:0] top_FrameData;   // CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] top_FrameData_O;
+	input [FrameBitsPerRow-1:0] bot_FrameData;   // CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] bot_FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe;    // CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register 
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	
+	// global
+
+	// signal declarations
+	
+	wire [3:0] N1BEG;
+	wire [7:0] N2BEG;
+	wire [7:0] N2BEGb;
+	wire [15:0] N4BEG;
+	wire [15:0] NN4BEG;
+	wire [9:0] bot2top;
+	
+	wire [3:0] S1BEG;
+	wire [7:0] S2BEG;
+	wire [7:0] S2BEGb;
+	wire [15:0] S4BEG;
+	wire [15:0] SS4BEG;
+	wire [17:0] top2bot;
+	
+	wire bot_UserCLKo;
+	
+	wire [MaxFramesPerCol-1:0] bot2top_FrameStrobe;
+	
+	DSP_top Inst_DSP_top(
+	.N1END(N1BEG),		// internal
+	.N2MID(N2BEG),		// internal
+	.N2END(N2BEGb),		// internal
+	.N4END(N4BEG),		// internal
+	.NN4END(NN4BEG),	// internal
+	.bot2top(bot2top),	// internal
+	.E1END(top_E1END),
+	.E2MID(top_E2MID),
+	.E2END(top_E2END),
+	.EE4END(top_EE4END),
+	.E6END(top_E6END),
+	.S1END(top_S1END),
+	.S2MID(top_S2MID),
+	.S2END(top_S2END),
+	.S4END(top_S4END),
+	.SS4END(top_SS4END),
+	.W1END(top_W1END),
+	.W2MID(top_W2MID),
+	.W2END(top_W2END),
+	.WW4END(top_WW4END),
+	.W6END(top_W6END),
+	.N1BEG(top_N1BEG),
+	.N2BEG(top_N2BEG),
+	.N2BEGb(top_N2BEGb),
+	.N4BEG(top_N4BEG),
+	.NN4BEG(top_NN4BEG),
+	.E1BEG(top_E1BEG),
+	.E2BEG(top_E2BEG),
+	.E2BEGb(top_E2BEGb),
+	.EE4BEG(top_EE4BEG),
+	.E6BEG(top_E6BEG),
+	.S1BEG(S1BEG),		// internal
+	.S2BEG(S2BEG),		// internal
+	.S2BEGb(S2BEGb),	// internal
+	.S4BEG(S4BEG),		// internal
+	.SS4BEG(SS4BEG),	// internal
+	.top2bot(top2bot),	// internal
+	.W1BEG(top_W1BEG),
+	.W2BEG(top_W2BEG),
+	.W2BEGb(top_W2BEGb),
+	.WW4BEG(top_WW4BEG),
+	.W6BEG(top_W6BEG),
+	.UserCLK(bot_UserCLKo),
+	.UserCLKo(UserCLKo),
+	.FrameData(top_FrameData),
+	.FrameData_O(top_FrameData_O),
+	.FrameStrobe(bot2top_FrameStrobe),
+	.FrameStrobe_O(FrameStrobe_O)
+	); 
+
+	DSP_bot Inst_DSP_bot(
+	.N1END(bot_N1END),
+	.N2MID(bot_N2MID),
+	.N2END(bot_N2END),
+	.N4END(bot_N4END),
+	.NN4END(bot_NN4END),
+	.E1END(bot_E1END),
+	.E2MID(bot_E2MID),
+	.E2END(bot_E2END),
+	.EE4END(bot_EE4END),
+	.E6END(bot_E6END),
+	.S1END(S1BEG),		// internal
+	.S2MID(S2BEG),		// internal
+	.S2END(S2BEGb),		// internal
+	.S4END(S4BEG),		// internal
+	.SS4END(SS4BEG),	// internal
+	.top2bot(top2bot),	// internal
+	.W1END(bot_W1END),
+	.W2MID(bot_W2MID),
+	.W2END(bot_W2END),
+	.WW4END(bot_WW4END),
+	.W6END(bot_W6END),
+	.N1BEG(N1BEG),		// internal
+	.N2BEG(N2BEG),		// internal
+	.N2BEGb(N2BEGb),	// internal
+	.N4BEG(N4BEG),		// internal
+	.NN4BEG(NN4BEG),	// internal
+	.bot2top(bot2top),	// internal
+	.E1BEG(bot_E1BEG),
+	.E2BEG(bot_E2BEG),
+	.E2BEGb(bot_E2BEGb),
+	.EE4BEG(bot_EE4BEG),
+	.E6BEG(bot_E6BEG),
+	.S1BEG(bot_S1BEG),
+	.S2BEG(bot_S2BEG),
+	.S2BEGb(bot_S2BEGb),
+	.S4BEG(bot_S4BEG),
+	.SS4BEG(bot_SS4BEG),
+	.W1BEG(bot_W1BEG),
+	.W2BEG(bot_W2BEG),
+	.W2BEGb(bot_W2BEGb),
+	.WW4BEG(bot_WW4BEG),
+	.W6BEG(bot_W6BEG),
+	// tile IO port which gets directly connected to top-level tile entity
+	.UserCLK(UserCLK),
+	.UserCLKo(bot_UserCLKo),
+	.FrameData(bot_FrameData),
+	.FrameData_O(bot_FrameData_O),
+	.FrameStrobe(FrameStrobe),
+	.FrameStrobe_O(bot2top_FrameStrobe)
+	);
+	
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_top_ConfigMem.v b/verilog/rtl/eFPGA_core/DSP_top_ConfigMem.v
new file mode 100644
index 0000000..b933548
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_top_ConfigMem.v
@@ -0,0 +1,2882 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module DSP_top_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 406;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [32-1:0] frame0;
+	wire [32-1:0] frame1;
+	wire [32-1:0] frame2;
+	wire [32-1:0] frame3;
+	wire [32-1:0] frame4;
+	wire [32-1:0] frame5;
+	wire [32-1:0] frame6;
+	wire [32-1:0] frame7;
+	wire [32-1:0] frame8;
+	wire [32-1:0] frame9;
+	wire [32-1:0] frame10;
+	wire [32-1:0] frame11;
+	wire [22-1:0] frame12;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[405]),
+	.QN(ConfigBits_N[405])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[404]),
+	.QN(ConfigBits_N[404])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[403]),
+	.QN(ConfigBits_N[403])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[402]),
+	.QN(ConfigBits_N[402])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[401]),
+	.QN(ConfigBits_N[401])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[400]),
+	.QN(ConfigBits_N[400])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[399]),
+	.QN(ConfigBits_N[399])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[398]),
+	.QN(ConfigBits_N[398])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[397]),
+	.QN(ConfigBits_N[397])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[396]),
+	.QN(ConfigBits_N[396])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[395]),
+	.QN(ConfigBits_N[395])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[394]),
+	.QN(ConfigBits_N[394])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[393]),
+	.QN(ConfigBits_N[393])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[392]),
+	.QN(ConfigBits_N[392])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[391]),
+	.QN(ConfigBits_N[391])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[390]),
+	.QN(ConfigBits_N[390])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[389]),
+	.QN(ConfigBits_N[389])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[388]),
+	.QN(ConfigBits_N[388])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[387]),
+	.QN(ConfigBits_N[387])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[386]),
+	.QN(ConfigBits_N[386])
+	);
+
+	LHQD1 Inst_frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[385]),
+	.QN(ConfigBits_N[385])
+	);
+
+	LHQD1 Inst_frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[384]),
+	.QN(ConfigBits_N[384])
+	);
+
+	LHQD1 Inst_frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[383]),
+	.QN(ConfigBits_N[383])
+	);
+
+	LHQD1 Inst_frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[382]),
+	.QN(ConfigBits_N[382])
+	);
+
+	LHQD1 Inst_frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[381]),
+	.QN(ConfigBits_N[381])
+	);
+
+	LHQD1 Inst_frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[380]),
+	.QN(ConfigBits_N[380])
+	);
+
+	LHQD1 Inst_frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[379]),
+	.QN(ConfigBits_N[379])
+	);
+
+	LHQD1 Inst_frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[378]),
+	.QN(ConfigBits_N[378])
+	);
+
+	LHQD1 Inst_frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[377]),
+	.QN(ConfigBits_N[377])
+	);
+
+	LHQD1 Inst_frame0_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[376]),
+	.QN(ConfigBits_N[376])
+	);
+
+	LHQD1 Inst_frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[375]),
+	.QN(ConfigBits_N[375])
+	);
+
+	LHQD1 Inst_frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[374]),
+	.QN(ConfigBits_N[374])
+	);
+
+	LHQD1 Inst_frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[373]),
+	.QN(ConfigBits_N[373])
+	);
+
+	LHQD1 Inst_frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[372]),
+	.QN(ConfigBits_N[372])
+	);
+
+	LHQD1 Inst_frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[371]),
+	.QN(ConfigBits_N[371])
+	);
+
+	LHQD1 Inst_frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[370]),
+	.QN(ConfigBits_N[370])
+	);
+
+	LHQD1 Inst_frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[369]),
+	.QN(ConfigBits_N[369])
+	);
+
+	LHQD1 Inst_frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[368]),
+	.QN(ConfigBits_N[368])
+	);
+
+	LHQD1 Inst_frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[367]),
+	.QN(ConfigBits_N[367])
+	);
+
+	LHQD1 Inst_frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[366]),
+	.QN(ConfigBits_N[366])
+	);
+
+	LHQD1 Inst_frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[365]),
+	.QN(ConfigBits_N[365])
+	);
+
+	LHQD1 Inst_frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[364]),
+	.QN(ConfigBits_N[364])
+	);
+
+	LHQD1 Inst_frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[363]),
+	.QN(ConfigBits_N[363])
+	);
+
+	LHQD1 Inst_frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[362]),
+	.QN(ConfigBits_N[362])
+	);
+
+	LHQD1 Inst_frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[361]),
+	.QN(ConfigBits_N[361])
+	);
+
+	LHQD1 Inst_frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[360]),
+	.QN(ConfigBits_N[360])
+	);
+
+	LHQD1 Inst_frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[359]),
+	.QN(ConfigBits_N[359])
+	);
+
+	LHQD1 Inst_frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[358]),
+	.QN(ConfigBits_N[358])
+	);
+
+	LHQD1 Inst_frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[357]),
+	.QN(ConfigBits_N[357])
+	);
+
+	LHQD1 Inst_frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[356]),
+	.QN(ConfigBits_N[356])
+	);
+
+	LHQD1 Inst_frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[355]),
+	.QN(ConfigBits_N[355])
+	);
+
+	LHQD1 Inst_frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[354]),
+	.QN(ConfigBits_N[354])
+	);
+
+	LHQD1 Inst_frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[353]),
+	.QN(ConfigBits_N[353])
+	);
+
+	LHQD1 Inst_frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[352]),
+	.QN(ConfigBits_N[352])
+	);
+
+	LHQD1 Inst_frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[351]),
+	.QN(ConfigBits_N[351])
+	);
+
+	LHQD1 Inst_frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[350]),
+	.QN(ConfigBits_N[350])
+	);
+
+	LHQD1 Inst_frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[349]),
+	.QN(ConfigBits_N[349])
+	);
+
+	LHQD1 Inst_frame1_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[348]),
+	.QN(ConfigBits_N[348])
+	);
+
+	LHQD1 Inst_frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[347]),
+	.QN(ConfigBits_N[347])
+	);
+
+	LHQD1 Inst_frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[346]),
+	.QN(ConfigBits_N[346])
+	);
+
+	LHQD1 Inst_frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[345]),
+	.QN(ConfigBits_N[345])
+	);
+
+	LHQD1 Inst_frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[344]),
+	.QN(ConfigBits_N[344])
+	);
+
+	LHQD1 Inst_frame1_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[343]),
+	.QN(ConfigBits_N[343])
+	);
+
+	LHQD1 Inst_frame1_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[342]),
+	.QN(ConfigBits_N[342])
+	);
+
+	LHQD1 Inst_frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[341]),
+	.QN(ConfigBits_N[341])
+	);
+
+	LHQD1 Inst_frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[340]),
+	.QN(ConfigBits_N[340])
+	);
+
+	LHQD1 Inst_frame2_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[339]),
+	.QN(ConfigBits_N[339])
+	);
+
+	LHQD1 Inst_frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[338]),
+	.QN(ConfigBits_N[338])
+	);
+
+	LHQD1 Inst_frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[337]),
+	.QN(ConfigBits_N[337])
+	);
+
+	LHQD1 Inst_frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[336]),
+	.QN(ConfigBits_N[336])
+	);
+
+	LHQD1 Inst_frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[335]),
+	.QN(ConfigBits_N[335])
+	);
+
+	LHQD1 Inst_frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[334]),
+	.QN(ConfigBits_N[334])
+	);
+
+	LHQD1 Inst_frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[333]),
+	.QN(ConfigBits_N[333])
+	);
+
+	LHQD1 Inst_frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[332]),
+	.QN(ConfigBits_N[332])
+	);
+
+	LHQD1 Inst_frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[331]),
+	.QN(ConfigBits_N[331])
+	);
+
+	LHQD1 Inst_frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[330]),
+	.QN(ConfigBits_N[330])
+	);
+
+	LHQD1 Inst_frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[329]),
+	.QN(ConfigBits_N[329])
+	);
+
+	LHQD1 Inst_frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[328]),
+	.QN(ConfigBits_N[328])
+	);
+
+	LHQD1 Inst_frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[327]),
+	.QN(ConfigBits_N[327])
+	);
+
+	LHQD1 Inst_frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[326]),
+	.QN(ConfigBits_N[326])
+	);
+
+	LHQD1 Inst_frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[325]),
+	.QN(ConfigBits_N[325])
+	);
+
+	LHQD1 Inst_frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[324]),
+	.QN(ConfigBits_N[324])
+	);
+
+	LHQD1 Inst_frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[323]),
+	.QN(ConfigBits_N[323])
+	);
+
+	LHQD1 Inst_frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[322]),
+	.QN(ConfigBits_N[322])
+	);
+
+	LHQD1 Inst_frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[321]),
+	.QN(ConfigBits_N[321])
+	);
+
+	LHQD1 Inst_frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[320]),
+	.QN(ConfigBits_N[320])
+	);
+
+	LHQD1 Inst_frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[319]),
+	.QN(ConfigBits_N[319])
+	);
+
+	LHQD1 Inst_frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[318]),
+	.QN(ConfigBits_N[318])
+	);
+
+	LHQD1 Inst_frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[317]),
+	.QN(ConfigBits_N[317])
+	);
+
+	LHQD1 Inst_frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[316]),
+	.QN(ConfigBits_N[316])
+	);
+
+	LHQD1 Inst_frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[315]),
+	.QN(ConfigBits_N[315])
+	);
+
+	LHQD1 Inst_frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[314]),
+	.QN(ConfigBits_N[314])
+	);
+
+	LHQD1 Inst_frame2_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[313]),
+	.QN(ConfigBits_N[313])
+	);
+
+	LHQD1 Inst_frame2_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[312]),
+	.QN(ConfigBits_N[312])
+	);
+
+	LHQD1 Inst_frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[311]),
+	.QN(ConfigBits_N[311])
+	);
+
+	LHQD1 Inst_frame2_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[310]),
+	.QN(ConfigBits_N[310])
+	);
+
+	LHQD1 Inst_frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[309]),
+	.QN(ConfigBits_N[309])
+	);
+
+	LHQD1 Inst_frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[308]),
+	.QN(ConfigBits_N[308])
+	);
+
+	LHQD1 Inst_frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[307]),
+	.QN(ConfigBits_N[307])
+	);
+
+	LHQD1 Inst_frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[306]),
+	.QN(ConfigBits_N[306])
+	);
+
+	LHQD1 Inst_frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[305]),
+	.QN(ConfigBits_N[305])
+	);
+
+	LHQD1 Inst_frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[304]),
+	.QN(ConfigBits_N[304])
+	);
+
+	LHQD1 Inst_frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[303]),
+	.QN(ConfigBits_N[303])
+	);
+
+	LHQD1 Inst_frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[302]),
+	.QN(ConfigBits_N[302])
+	);
+
+	LHQD1 Inst_frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[301]),
+	.QN(ConfigBits_N[301])
+	);
+
+	LHQD1 Inst_frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[300]),
+	.QN(ConfigBits_N[300])
+	);
+
+	LHQD1 Inst_frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[299]),
+	.QN(ConfigBits_N[299])
+	);
+
+	LHQD1 Inst_frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[298]),
+	.QN(ConfigBits_N[298])
+	);
+
+	LHQD1 Inst_frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[297]),
+	.QN(ConfigBits_N[297])
+	);
+
+	LHQD1 Inst_frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[296]),
+	.QN(ConfigBits_N[296])
+	);
+
+	LHQD1 Inst_frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[295]),
+	.QN(ConfigBits_N[295])
+	);
+
+	LHQD1 Inst_frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[294]),
+	.QN(ConfigBits_N[294])
+	);
+
+	LHQD1 Inst_frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[293]),
+	.QN(ConfigBits_N[293])
+	);
+
+	LHQD1 Inst_frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[292]),
+	.QN(ConfigBits_N[292])
+	);
+
+	LHQD1 Inst_frame3_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[291]),
+	.QN(ConfigBits_N[291])
+	);
+
+	LHQD1 Inst_frame3_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[290]),
+	.QN(ConfigBits_N[290])
+	);
+
+	LHQD1 Inst_frame3_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[289]),
+	.QN(ConfigBits_N[289])
+	);
+
+	LHQD1 Inst_frame3_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[288]),
+	.QN(ConfigBits_N[288])
+	);
+
+	LHQD1 Inst_frame3_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[287]),
+	.QN(ConfigBits_N[287])
+	);
+
+	LHQD1 Inst_frame3_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[286]),
+	.QN(ConfigBits_N[286])
+	);
+
+	LHQD1 Inst_frame3_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[285]),
+	.QN(ConfigBits_N[285])
+	);
+
+	LHQD1 Inst_frame3_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[284]),
+	.QN(ConfigBits_N[284])
+	);
+
+	LHQD1 Inst_frame3_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[283]),
+	.QN(ConfigBits_N[283])
+	);
+
+	LHQD1 Inst_frame3_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[282]),
+	.QN(ConfigBits_N[282])
+	);
+
+	LHQD1 Inst_frame3_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[281]),
+	.QN(ConfigBits_N[281])
+	);
+
+	LHQD1 Inst_frame3_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[280]),
+	.QN(ConfigBits_N[280])
+	);
+
+	LHQD1 Inst_frame3_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[279]),
+	.QN(ConfigBits_N[279])
+	);
+
+	LHQD1 Inst_frame3_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[278]),
+	.QN(ConfigBits_N[278])
+	);
+
+	LHQD1 Inst_frame4_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[277]),
+	.QN(ConfigBits_N[277])
+	);
+
+	LHQD1 Inst_frame4_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[276]),
+	.QN(ConfigBits_N[276])
+	);
+
+	LHQD1 Inst_frame4_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[275]),
+	.QN(ConfigBits_N[275])
+	);
+
+	LHQD1 Inst_frame4_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[274]),
+	.QN(ConfigBits_N[274])
+	);
+
+	LHQD1 Inst_frame4_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[273]),
+	.QN(ConfigBits_N[273])
+	);
+
+	LHQD1 Inst_frame4_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[272]),
+	.QN(ConfigBits_N[272])
+	);
+
+	LHQD1 Inst_frame4_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[271]),
+	.QN(ConfigBits_N[271])
+	);
+
+	LHQD1 Inst_frame4_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[270]),
+	.QN(ConfigBits_N[270])
+	);
+
+	LHQD1 Inst_frame4_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[269]),
+	.QN(ConfigBits_N[269])
+	);
+
+	LHQD1 Inst_frame4_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[268]),
+	.QN(ConfigBits_N[268])
+	);
+
+	LHQD1 Inst_frame4_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[267]),
+	.QN(ConfigBits_N[267])
+	);
+
+	LHQD1 Inst_frame4_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[266]),
+	.QN(ConfigBits_N[266])
+	);
+
+	LHQD1 Inst_frame4_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[265]),
+	.QN(ConfigBits_N[265])
+	);
+
+	LHQD1 Inst_frame4_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[264]),
+	.QN(ConfigBits_N[264])
+	);
+
+	LHQD1 Inst_frame4_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[263]),
+	.QN(ConfigBits_N[263])
+	);
+
+	LHQD1 Inst_frame4_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[262]),
+	.QN(ConfigBits_N[262])
+	);
+
+	LHQD1 Inst_frame4_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[261]),
+	.QN(ConfigBits_N[261])
+	);
+
+	LHQD1 Inst_frame4_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[260]),
+	.QN(ConfigBits_N[260])
+	);
+
+	LHQD1 Inst_frame4_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[259]),
+	.QN(ConfigBits_N[259])
+	);
+
+	LHQD1 Inst_frame4_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[258]),
+	.QN(ConfigBits_N[258])
+	);
+
+	LHQD1 Inst_frame4_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[257]),
+	.QN(ConfigBits_N[257])
+	);
+
+	LHQD1 Inst_frame4_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[256]),
+	.QN(ConfigBits_N[256])
+	);
+
+	LHQD1 Inst_frame4_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[255]),
+	.QN(ConfigBits_N[255])
+	);
+
+	LHQD1 Inst_frame4_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[254]),
+	.QN(ConfigBits_N[254])
+	);
+
+	LHQD1 Inst_frame4_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[253]),
+	.QN(ConfigBits_N[253])
+	);
+
+	LHQD1 Inst_frame4_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[252]),
+	.QN(ConfigBits_N[252])
+	);
+
+	LHQD1 Inst_frame4_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[251]),
+	.QN(ConfigBits_N[251])
+	);
+
+	LHQD1 Inst_frame4_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[250]),
+	.QN(ConfigBits_N[250])
+	);
+
+	LHQD1 Inst_frame4_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[249]),
+	.QN(ConfigBits_N[249])
+	);
+
+	LHQD1 Inst_frame4_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[248]),
+	.QN(ConfigBits_N[248])
+	);
+
+	LHQD1 Inst_frame4_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[247]),
+	.QN(ConfigBits_N[247])
+	);
+
+	LHQD1 Inst_frame4_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[246]),
+	.QN(ConfigBits_N[246])
+	);
+
+	LHQD1 Inst_frame5_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[245]),
+	.QN(ConfigBits_N[245])
+	);
+
+	LHQD1 Inst_frame5_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[244]),
+	.QN(ConfigBits_N[244])
+	);
+
+	LHQD1 Inst_frame5_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[243]),
+	.QN(ConfigBits_N[243])
+	);
+
+	LHQD1 Inst_frame5_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[242]),
+	.QN(ConfigBits_N[242])
+	);
+
+	LHQD1 Inst_frame5_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[241]),
+	.QN(ConfigBits_N[241])
+	);
+
+	LHQD1 Inst_frame5_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[240]),
+	.QN(ConfigBits_N[240])
+	);
+
+	LHQD1 Inst_frame5_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[239]),
+	.QN(ConfigBits_N[239])
+	);
+
+	LHQD1 Inst_frame5_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[238]),
+	.QN(ConfigBits_N[238])
+	);
+
+	LHQD1 Inst_frame5_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[237]),
+	.QN(ConfigBits_N[237])
+	);
+
+	LHQD1 Inst_frame5_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[236]),
+	.QN(ConfigBits_N[236])
+	);
+
+	LHQD1 Inst_frame5_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[235]),
+	.QN(ConfigBits_N[235])
+	);
+
+	LHQD1 Inst_frame5_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[234]),
+	.QN(ConfigBits_N[234])
+	);
+
+	LHQD1 Inst_frame5_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[233]),
+	.QN(ConfigBits_N[233])
+	);
+
+	LHQD1 Inst_frame5_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[232]),
+	.QN(ConfigBits_N[232])
+	);
+
+	LHQD1 Inst_frame5_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[231]),
+	.QN(ConfigBits_N[231])
+	);
+
+	LHQD1 Inst_frame5_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[230]),
+	.QN(ConfigBits_N[230])
+	);
+
+	LHQD1 Inst_frame5_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[229]),
+	.QN(ConfigBits_N[229])
+	);
+
+	LHQD1 Inst_frame5_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[228]),
+	.QN(ConfigBits_N[228])
+	);
+
+	LHQD1 Inst_frame5_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[227]),
+	.QN(ConfigBits_N[227])
+	);
+
+	LHQD1 Inst_frame5_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[226]),
+	.QN(ConfigBits_N[226])
+	);
+
+	LHQD1 Inst_frame5_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[225]),
+	.QN(ConfigBits_N[225])
+	);
+
+	LHQD1 Inst_frame5_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[224]),
+	.QN(ConfigBits_N[224])
+	);
+
+	LHQD1 Inst_frame5_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[223]),
+	.QN(ConfigBits_N[223])
+	);
+
+	LHQD1 Inst_frame5_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[222]),
+	.QN(ConfigBits_N[222])
+	);
+
+	LHQD1 Inst_frame5_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[221]),
+	.QN(ConfigBits_N[221])
+	);
+
+	LHQD1 Inst_frame5_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[220]),
+	.QN(ConfigBits_N[220])
+	);
+
+	LHQD1 Inst_frame5_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[219]),
+	.QN(ConfigBits_N[219])
+	);
+
+	LHQD1 Inst_frame5_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[218]),
+	.QN(ConfigBits_N[218])
+	);
+
+	LHQD1 Inst_frame5_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[217]),
+	.QN(ConfigBits_N[217])
+	);
+
+	LHQD1 Inst_frame5_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[216]),
+	.QN(ConfigBits_N[216])
+	);
+
+	LHQD1 Inst_frame5_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[215]),
+	.QN(ConfigBits_N[215])
+	);
+
+	LHQD1 Inst_frame5_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[214]),
+	.QN(ConfigBits_N[214])
+	);
+
+	LHQD1 Inst_frame6_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[213]),
+	.QN(ConfigBits_N[213])
+	);
+
+	LHQD1 Inst_frame6_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[212]),
+	.QN(ConfigBits_N[212])
+	);
+
+	LHQD1 Inst_frame6_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[211]),
+	.QN(ConfigBits_N[211])
+	);
+
+	LHQD1 Inst_frame6_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[210]),
+	.QN(ConfigBits_N[210])
+	);
+
+	LHQD1 Inst_frame6_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[209]),
+	.QN(ConfigBits_N[209])
+	);
+
+	LHQD1 Inst_frame6_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[208]),
+	.QN(ConfigBits_N[208])
+	);
+
+	LHQD1 Inst_frame6_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[207]),
+	.QN(ConfigBits_N[207])
+	);
+
+	LHQD1 Inst_frame6_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[206]),
+	.QN(ConfigBits_N[206])
+	);
+
+	LHQD1 Inst_frame6_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[205]),
+	.QN(ConfigBits_N[205])
+	);
+
+	LHQD1 Inst_frame6_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[204]),
+	.QN(ConfigBits_N[204])
+	);
+
+	LHQD1 Inst_frame6_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[203]),
+	.QN(ConfigBits_N[203])
+	);
+
+	LHQD1 Inst_frame6_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[202]),
+	.QN(ConfigBits_N[202])
+	);
+
+	LHQD1 Inst_frame6_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[201]),
+	.QN(ConfigBits_N[201])
+	);
+
+	LHQD1 Inst_frame6_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[200]),
+	.QN(ConfigBits_N[200])
+	);
+
+	LHQD1 Inst_frame6_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[199]),
+	.QN(ConfigBits_N[199])
+	);
+
+	LHQD1 Inst_frame6_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[198]),
+	.QN(ConfigBits_N[198])
+	);
+
+	LHQD1 Inst_frame6_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[197]),
+	.QN(ConfigBits_N[197])
+	);
+
+	LHQD1 Inst_frame6_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[196]),
+	.QN(ConfigBits_N[196])
+	);
+
+	LHQD1 Inst_frame6_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[195]),
+	.QN(ConfigBits_N[195])
+	);
+
+	LHQD1 Inst_frame6_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[194]),
+	.QN(ConfigBits_N[194])
+	);
+
+	LHQD1 Inst_frame6_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[193]),
+	.QN(ConfigBits_N[193])
+	);
+
+	LHQD1 Inst_frame6_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[192]),
+	.QN(ConfigBits_N[192])
+	);
+
+	LHQD1 Inst_frame6_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[191]),
+	.QN(ConfigBits_N[191])
+	);
+
+	LHQD1 Inst_frame6_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[190]),
+	.QN(ConfigBits_N[190])
+	);
+
+	LHQD1 Inst_frame6_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[189]),
+	.QN(ConfigBits_N[189])
+	);
+
+	LHQD1 Inst_frame6_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[188]),
+	.QN(ConfigBits_N[188])
+	);
+
+	LHQD1 Inst_frame6_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[187]),
+	.QN(ConfigBits_N[187])
+	);
+
+	LHQD1 Inst_frame6_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[186]),
+	.QN(ConfigBits_N[186])
+	);
+
+	LHQD1 Inst_frame6_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[185]),
+	.QN(ConfigBits_N[185])
+	);
+
+	LHQD1 Inst_frame6_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[184]),
+	.QN(ConfigBits_N[184])
+	);
+
+	LHQD1 Inst_frame6_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[183]),
+	.QN(ConfigBits_N[183])
+	);
+
+	LHQD1 Inst_frame6_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[182]),
+	.QN(ConfigBits_N[182])
+	);
+
+	LHQD1 Inst_frame7_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[181]),
+	.QN(ConfigBits_N[181])
+	);
+
+	LHQD1 Inst_frame7_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[180]),
+	.QN(ConfigBits_N[180])
+	);
+
+	LHQD1 Inst_frame7_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[179]),
+	.QN(ConfigBits_N[179])
+	);
+
+	LHQD1 Inst_frame7_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[178]),
+	.QN(ConfigBits_N[178])
+	);
+
+	LHQD1 Inst_frame7_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[177]),
+	.QN(ConfigBits_N[177])
+	);
+
+	LHQD1 Inst_frame7_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[176]),
+	.QN(ConfigBits_N[176])
+	);
+
+	LHQD1 Inst_frame7_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[175]),
+	.QN(ConfigBits_N[175])
+	);
+
+	LHQD1 Inst_frame7_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[174]),
+	.QN(ConfigBits_N[174])
+	);
+
+	LHQD1 Inst_frame7_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[173]),
+	.QN(ConfigBits_N[173])
+	);
+
+	LHQD1 Inst_frame7_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[172]),
+	.QN(ConfigBits_N[172])
+	);
+
+	LHQD1 Inst_frame7_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[171]),
+	.QN(ConfigBits_N[171])
+	);
+
+	LHQD1 Inst_frame7_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[170]),
+	.QN(ConfigBits_N[170])
+	);
+
+	LHQD1 Inst_frame7_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[169]),
+	.QN(ConfigBits_N[169])
+	);
+
+	LHQD1 Inst_frame7_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[168]),
+	.QN(ConfigBits_N[168])
+	);
+
+	LHQD1 Inst_frame7_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[167]),
+	.QN(ConfigBits_N[167])
+	);
+
+	LHQD1 Inst_frame7_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[166]),
+	.QN(ConfigBits_N[166])
+	);
+
+	LHQD1 Inst_frame7_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[165]),
+	.QN(ConfigBits_N[165])
+	);
+
+	LHQD1 Inst_frame7_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[164]),
+	.QN(ConfigBits_N[164])
+	);
+
+	LHQD1 Inst_frame7_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[163]),
+	.QN(ConfigBits_N[163])
+	);
+
+	LHQD1 Inst_frame7_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[162]),
+	.QN(ConfigBits_N[162])
+	);
+
+	LHQD1 Inst_frame7_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[161]),
+	.QN(ConfigBits_N[161])
+	);
+
+	LHQD1 Inst_frame7_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[160]),
+	.QN(ConfigBits_N[160])
+	);
+
+	LHQD1 Inst_frame7_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[159]),
+	.QN(ConfigBits_N[159])
+	);
+
+	LHQD1 Inst_frame7_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[158]),
+	.QN(ConfigBits_N[158])
+	);
+
+	LHQD1 Inst_frame7_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[157]),
+	.QN(ConfigBits_N[157])
+	);
+
+	LHQD1 Inst_frame7_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[156]),
+	.QN(ConfigBits_N[156])
+	);
+
+	LHQD1 Inst_frame7_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[155]),
+	.QN(ConfigBits_N[155])
+	);
+
+	LHQD1 Inst_frame7_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[154]),
+	.QN(ConfigBits_N[154])
+	);
+
+	LHQD1 Inst_frame7_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[153]),
+	.QN(ConfigBits_N[153])
+	);
+
+	LHQD1 Inst_frame7_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[152]),
+	.QN(ConfigBits_N[152])
+	);
+
+	LHQD1 Inst_frame7_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[151]),
+	.QN(ConfigBits_N[151])
+	);
+
+	LHQD1 Inst_frame7_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[150]),
+	.QN(ConfigBits_N[150])
+	);
+
+	LHQD1 Inst_frame8_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[149]),
+	.QN(ConfigBits_N[149])
+	);
+
+	LHQD1 Inst_frame8_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[148]),
+	.QN(ConfigBits_N[148])
+	);
+
+	LHQD1 Inst_frame8_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[147]),
+	.QN(ConfigBits_N[147])
+	);
+
+	LHQD1 Inst_frame8_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[146]),
+	.QN(ConfigBits_N[146])
+	);
+
+	LHQD1 Inst_frame8_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[145]),
+	.QN(ConfigBits_N[145])
+	);
+
+	LHQD1 Inst_frame8_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[144]),
+	.QN(ConfigBits_N[144])
+	);
+
+	LHQD1 Inst_frame8_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[143]),
+	.QN(ConfigBits_N[143])
+	);
+
+	LHQD1 Inst_frame8_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[142]),
+	.QN(ConfigBits_N[142])
+	);
+
+	LHQD1 Inst_frame8_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[141]),
+	.QN(ConfigBits_N[141])
+	);
+
+	LHQD1 Inst_frame8_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[140]),
+	.QN(ConfigBits_N[140])
+	);
+
+	LHQD1 Inst_frame8_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[139]),
+	.QN(ConfigBits_N[139])
+	);
+
+	LHQD1 Inst_frame8_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[138]),
+	.QN(ConfigBits_N[138])
+	);
+
+	LHQD1 Inst_frame8_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[137]),
+	.QN(ConfigBits_N[137])
+	);
+
+	LHQD1 Inst_frame8_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[136]),
+	.QN(ConfigBits_N[136])
+	);
+
+	LHQD1 Inst_frame8_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[135]),
+	.QN(ConfigBits_N[135])
+	);
+
+	LHQD1 Inst_frame8_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[134]),
+	.QN(ConfigBits_N[134])
+	);
+
+	LHQD1 Inst_frame8_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[133]),
+	.QN(ConfigBits_N[133])
+	);
+
+	LHQD1 Inst_frame8_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[132]),
+	.QN(ConfigBits_N[132])
+	);
+
+	LHQD1 Inst_frame8_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[131]),
+	.QN(ConfigBits_N[131])
+	);
+
+	LHQD1 Inst_frame8_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[130]),
+	.QN(ConfigBits_N[130])
+	);
+
+	LHQD1 Inst_frame8_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[129]),
+	.QN(ConfigBits_N[129])
+	);
+
+	LHQD1 Inst_frame8_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[128]),
+	.QN(ConfigBits_N[128])
+	);
+
+	LHQD1 Inst_frame8_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[127]),
+	.QN(ConfigBits_N[127])
+	);
+
+	LHQD1 Inst_frame8_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[126]),
+	.QN(ConfigBits_N[126])
+	);
+
+	LHQD1 Inst_frame8_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[125]),
+	.QN(ConfigBits_N[125])
+	);
+
+	LHQD1 Inst_frame8_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[124]),
+	.QN(ConfigBits_N[124])
+	);
+
+	LHQD1 Inst_frame8_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[123]),
+	.QN(ConfigBits_N[123])
+	);
+
+	LHQD1 Inst_frame8_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[122]),
+	.QN(ConfigBits_N[122])
+	);
+
+	LHQD1 Inst_frame8_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[121]),
+	.QN(ConfigBits_N[121])
+	);
+
+	LHQD1 Inst_frame8_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[120]),
+	.QN(ConfigBits_N[120])
+	);
+
+	LHQD1 Inst_frame8_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[119]),
+	.QN(ConfigBits_N[119])
+	);
+
+	LHQD1 Inst_frame8_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[118]),
+	.QN(ConfigBits_N[118])
+	);
+
+	LHQD1 Inst_frame9_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[117]),
+	.QN(ConfigBits_N[117])
+	);
+
+	LHQD1 Inst_frame9_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[116]),
+	.QN(ConfigBits_N[116])
+	);
+
+	LHQD1 Inst_frame9_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[115]),
+	.QN(ConfigBits_N[115])
+	);
+
+	LHQD1 Inst_frame9_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[114]),
+	.QN(ConfigBits_N[114])
+	);
+
+	LHQD1 Inst_frame9_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_frame9_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_frame9_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_frame9_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_frame9_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_frame9_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_frame9_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_frame9_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_frame9_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_frame9_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_frame9_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_frame9_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_frame9_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_frame9_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_frame9_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_frame9_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_frame9_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_frame9_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_frame9_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_frame9_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_frame9_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_frame9_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_frame9_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_frame9_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_frame9_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_frame9_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_frame9_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_frame9_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_frame10_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_frame10_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_frame10_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_frame10_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_frame10_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_frame10_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_frame10_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_frame10_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_frame10_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_frame10_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_frame10_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_frame10_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_frame10_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_frame10_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_frame10_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_frame10_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_frame10_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_frame10_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_frame10_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_frame10_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_frame10_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_frame10_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_frame10_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_frame10_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_frame10_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_frame10_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_frame10_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_frame10_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_frame10_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_frame10_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_frame10_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_frame10_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_frame11_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_frame11_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_frame11_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_frame11_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_frame11_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_frame11_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_frame11_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_frame11_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_frame11_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_frame11_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_frame11_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_frame11_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_frame11_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_frame11_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_frame11_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_frame11_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_frame11_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_frame11_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_frame11_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_frame11_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_frame11_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_frame11_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_frame11_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_frame11_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_frame11_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_frame11_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_frame11_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_frame11_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_frame11_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_frame11_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_frame11_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_frame11_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_frame12_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_frame12_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_frame12_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame12_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame12_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame12_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame12_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame12_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame12_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame12_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame12_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame12_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame12_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame12_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame12_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame12_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame12_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame12_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame12_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame12_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame12_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame12_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_top_switch_matrix.v b/verilog/rtl/eFPGA_core/DSP_top_switch_matrix.v
new file mode 100644
index 0000000..b2402de
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_top_switch_matrix.v
@@ -0,0 +1,4036 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:406
+module DSP_top_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, NN4END0, NN4END1, NN4END2, NN4END3, bot2top0, bot2top1, bot2top2, bot2top3, bot2top4, bot2top5, bot2top6, bot2top7, bot2top8, bot2top9, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, E6END0, E6END1, S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, SS4END0, SS4END1, SS4END2, SS4END3, W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, W6END0, W6END1, J2MID_ABa_END0, J2MID_ABa_END1, J2MID_ABa_END2, J2MID_ABa_END3, J2MID_CDa_END0, J2MID_CDa_END1, J2MID_CDa_END2, J2MID_CDa_END3, J2MID_EFa_END0, J2MID_EFa_END1, J2MID_EFa_END2, J2MID_EFa_END3, J2MID_GHa_END0, J2MID_GHa_END1, J2MID_GHa_END2, J2MID_GHa_END3, J2MID_ABb_END0, J2MID_ABb_END1, J2MID_ABb_END2, J2MID_ABb_END3, J2MID_CDb_END0, J2MID_CDb_END1, J2MID_CDb_END2, J2MID_CDb_END3, J2MID_EFb_END0, J2MID_EFb_END1, J2MID_EFb_END2, J2MID_EFb_END3, J2MID_GHb_END0, J2MID_GHb_END1, J2MID_GHb_END2, J2MID_GHb_END3, J2END_AB_END0, J2END_AB_END1, J2END_AB_END2, J2END_AB_END3, J2END_CD_END0, J2END_CD_END1, J2END_CD_END2, J2END_CD_END3, J2END_EF_END0, J2END_EF_END1, J2END_EF_END2, J2END_EF_END3, J2END_GH_END0, J2END_GH_END1, J2END_GH_END2, J2END_GH_END3, JN2END0, JN2END1, JN2END2, JN2END3, JN2END4, JN2END5, JN2END6, JN2END7, JE2END0, JE2END1, JE2END2, JE2END3, JE2END4, JE2END5, JE2END6, JE2END7, JS2END0, JS2END1, JS2END2, JS2END3, JS2END4, JS2END5, JS2END6, JS2END7, JW2END0, JW2END1, JW2END2, JW2END3, JW2END4, JW2END5, JW2END6, JW2END7, J_l_AB_END0, J_l_AB_END1, J_l_AB_END2, J_l_AB_END3, J_l_CD_END0, J_l_CD_END1, J_l_CD_END2, J_l_CD_END3, J_l_EF_END0, J_l_EF_END1, J_l_EF_END2, J_l_EF_END3, J_l_GH_END0, J_l_GH_END1, J_l_GH_END2, J_l_GH_END3, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, E6BEG0, E6BEG1, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, top2bot0, top2bot1, top2bot2, top2bot3, top2bot4, top2bot5, top2bot6, top2bot7, top2bot8, top2bot9, top2bot10, top2bot11, top2bot12, top2bot13, top2bot14, top2bot15, top2bot16, top2bot17, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, W6BEG0, W6BEG1, J2MID_ABa_BEG0, J2MID_ABa_BEG1, J2MID_ABa_BEG2, J2MID_ABa_BEG3, J2MID_CDa_BEG0, J2MID_CDa_BEG1, J2MID_CDa_BEG2, J2MID_CDa_BEG3, J2MID_EFa_BEG0, J2MID_EFa_BEG1, J2MID_EFa_BEG2, J2MID_EFa_BEG3, J2MID_GHa_BEG0, J2MID_GHa_BEG1, J2MID_GHa_BEG2, J2MID_GHa_BEG3, J2MID_ABb_BEG0, J2MID_ABb_BEG1, J2MID_ABb_BEG2, J2MID_ABb_BEG3, J2MID_CDb_BEG0, J2MID_CDb_BEG1, J2MID_CDb_BEG2, J2MID_CDb_BEG3, J2MID_EFb_BEG0, J2MID_EFb_BEG1, J2MID_EFb_BEG2, J2MID_EFb_BEG3, J2MID_GHb_BEG0, J2MID_GHb_BEG1, J2MID_GHb_BEG2, J2MID_GHb_BEG3, J2END_AB_BEG0, J2END_AB_BEG1, J2END_AB_BEG2, J2END_AB_BEG3, J2END_CD_BEG0, J2END_CD_BEG1, J2END_CD_BEG2, J2END_CD_BEG3, J2END_EF_BEG0, J2END_EF_BEG1, J2END_EF_BEG2, J2END_EF_BEG3, J2END_GH_BEG0, J2END_GH_BEG1, J2END_GH_BEG2, J2END_GH_BEG3, JN2BEG0, JN2BEG1, JN2BEG2, JN2BEG3, JN2BEG4, JN2BEG5, JN2BEG6, JN2BEG7, JE2BEG0, JE2BEG1, JE2BEG2, JE2BEG3, JE2BEG4, JE2BEG5, JE2BEG6, JE2BEG7, JS2BEG0, JS2BEG1, JS2BEG2, JS2BEG3, JS2BEG4, JS2BEG5, JS2BEG6, JS2BEG7, JW2BEG0, JW2BEG1, JW2BEG2, JW2BEG3, JW2BEG4, JW2BEG5, JW2BEG6, JW2BEG7, J_l_AB_BEG0, J_l_AB_BEG1, J_l_AB_BEG2, J_l_AB_BEG3, J_l_CD_BEG0, J_l_CD_BEG1, J_l_CD_BEG2, J_l_CD_BEG3, J_l_EF_BEG0, J_l_EF_BEG1, J_l_EF_BEG2, J_l_EF_BEG3, J_l_GH_BEG0, J_l_GH_BEG1, J_l_GH_BEG2, J_l_GH_BEG3, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 406;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input bot2top0;
+	input bot2top1;
+	input bot2top2;
+	input bot2top3;
+	input bot2top4;
+	input bot2top5;
+	input bot2top6;
+	input bot2top7;
+	input bot2top8;
+	input bot2top9;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input E6END0;
+	input E6END1;
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input W6END0;
+	input W6END1;
+	input J2MID_ABa_END0;
+	input J2MID_ABa_END1;
+	input J2MID_ABa_END2;
+	input J2MID_ABa_END3;
+	input J2MID_CDa_END0;
+	input J2MID_CDa_END1;
+	input J2MID_CDa_END2;
+	input J2MID_CDa_END3;
+	input J2MID_EFa_END0;
+	input J2MID_EFa_END1;
+	input J2MID_EFa_END2;
+	input J2MID_EFa_END3;
+	input J2MID_GHa_END0;
+	input J2MID_GHa_END1;
+	input J2MID_GHa_END2;
+	input J2MID_GHa_END3;
+	input J2MID_ABb_END0;
+	input J2MID_ABb_END1;
+	input J2MID_ABb_END2;
+	input J2MID_ABb_END3;
+	input J2MID_CDb_END0;
+	input J2MID_CDb_END1;
+	input J2MID_CDb_END2;
+	input J2MID_CDb_END3;
+	input J2MID_EFb_END0;
+	input J2MID_EFb_END1;
+	input J2MID_EFb_END2;
+	input J2MID_EFb_END3;
+	input J2MID_GHb_END0;
+	input J2MID_GHb_END1;
+	input J2MID_GHb_END2;
+	input J2MID_GHb_END3;
+	input J2END_AB_END0;
+	input J2END_AB_END1;
+	input J2END_AB_END2;
+	input J2END_AB_END3;
+	input J2END_CD_END0;
+	input J2END_CD_END1;
+	input J2END_CD_END2;
+	input J2END_CD_END3;
+	input J2END_EF_END0;
+	input J2END_EF_END1;
+	input J2END_EF_END2;
+	input J2END_EF_END3;
+	input J2END_GH_END0;
+	input J2END_GH_END1;
+	input J2END_GH_END2;
+	input J2END_GH_END3;
+	input JN2END0;
+	input JN2END1;
+	input JN2END2;
+	input JN2END3;
+	input JN2END4;
+	input JN2END5;
+	input JN2END6;
+	input JN2END7;
+	input JE2END0;
+	input JE2END1;
+	input JE2END2;
+	input JE2END3;
+	input JE2END4;
+	input JE2END5;
+	input JE2END6;
+	input JE2END7;
+	input JS2END0;
+	input JS2END1;
+	input JS2END2;
+	input JS2END3;
+	input JS2END4;
+	input JS2END5;
+	input JS2END6;
+	input JS2END7;
+	input JW2END0;
+	input JW2END1;
+	input JW2END2;
+	input JW2END3;
+	input JW2END4;
+	input JW2END5;
+	input JW2END6;
+	input JW2END7;
+	input J_l_AB_END0;
+	input J_l_AB_END1;
+	input J_l_AB_END2;
+	input J_l_AB_END3;
+	input J_l_CD_END0;
+	input J_l_CD_END1;
+	input J_l_CD_END2;
+	input J_l_CD_END3;
+	input J_l_EF_END0;
+	input J_l_EF_END1;
+	input J_l_EF_END2;
+	input J_l_EF_END3;
+	input J_l_GH_END0;
+	input J_l_GH_END1;
+	input J_l_GH_END2;
+	input J_l_GH_END3;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output E6BEG0;
+	output E6BEG1;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output top2bot0;
+	output top2bot1;
+	output top2bot2;
+	output top2bot3;
+	output top2bot4;
+	output top2bot5;
+	output top2bot6;
+	output top2bot7;
+	output top2bot8;
+	output top2bot9;
+	output top2bot10;
+	output top2bot11;
+	output top2bot12;
+	output top2bot13;
+	output top2bot14;
+	output top2bot15;
+	output top2bot16;
+	output top2bot17;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output W6BEG0;
+	output W6BEG1;
+	output J2MID_ABa_BEG0;
+	output J2MID_ABa_BEG1;
+	output J2MID_ABa_BEG2;
+	output J2MID_ABa_BEG3;
+	output J2MID_CDa_BEG0;
+	output J2MID_CDa_BEG1;
+	output J2MID_CDa_BEG2;
+	output J2MID_CDa_BEG3;
+	output J2MID_EFa_BEG0;
+	output J2MID_EFa_BEG1;
+	output J2MID_EFa_BEG2;
+	output J2MID_EFa_BEG3;
+	output J2MID_GHa_BEG0;
+	output J2MID_GHa_BEG1;
+	output J2MID_GHa_BEG2;
+	output J2MID_GHa_BEG3;
+	output J2MID_ABb_BEG0;
+	output J2MID_ABb_BEG1;
+	output J2MID_ABb_BEG2;
+	output J2MID_ABb_BEG3;
+	output J2MID_CDb_BEG0;
+	output J2MID_CDb_BEG1;
+	output J2MID_CDb_BEG2;
+	output J2MID_CDb_BEG3;
+	output J2MID_EFb_BEG0;
+	output J2MID_EFb_BEG1;
+	output J2MID_EFb_BEG2;
+	output J2MID_EFb_BEG3;
+	output J2MID_GHb_BEG0;
+	output J2MID_GHb_BEG1;
+	output J2MID_GHb_BEG2;
+	output J2MID_GHb_BEG3;
+	output J2END_AB_BEG0;
+	output J2END_AB_BEG1;
+	output J2END_AB_BEG2;
+	output J2END_AB_BEG3;
+	output J2END_CD_BEG0;
+	output J2END_CD_BEG1;
+	output J2END_CD_BEG2;
+	output J2END_CD_BEG3;
+	output J2END_EF_BEG0;
+	output J2END_EF_BEG1;
+	output J2END_EF_BEG2;
+	output J2END_EF_BEG3;
+	output J2END_GH_BEG0;
+	output J2END_GH_BEG1;
+	output J2END_GH_BEG2;
+	output J2END_GH_BEG3;
+	output JN2BEG0;
+	output JN2BEG1;
+	output JN2BEG2;
+	output JN2BEG3;
+	output JN2BEG4;
+	output JN2BEG5;
+	output JN2BEG6;
+	output JN2BEG7;
+	output JE2BEG0;
+	output JE2BEG1;
+	output JE2BEG2;
+	output JE2BEG3;
+	output JE2BEG4;
+	output JE2BEG5;
+	output JE2BEG6;
+	output JE2BEG7;
+	output JS2BEG0;
+	output JS2BEG1;
+	output JS2BEG2;
+	output JS2BEG3;
+	output JS2BEG4;
+	output JS2BEG5;
+	output JS2BEG6;
+	output JS2BEG7;
+	output JW2BEG0;
+	output JW2BEG1;
+	output JW2BEG2;
+	output JW2BEG3;
+	output JW2BEG4;
+	output JW2BEG5;
+	output JW2BEG6;
+	output JW2BEG7;
+	output J_l_AB_BEG0;
+	output J_l_AB_BEG1;
+	output J_l_AB_BEG2;
+	output J_l_AB_BEG3;
+	output J_l_CD_BEG0;
+	output J_l_CD_BEG1;
+	output J_l_CD_BEG2;
+	output J_l_CD_BEG3;
+	output J_l_EF_BEG0;
+	output J_l_EF_BEG1;
+	output J_l_EF_BEG2;
+	output J_l_EF_BEG3;
+	output J_l_GH_BEG0;
+	output J_l_GH_BEG1;
+	output J_l_GH_BEG2;
+	output J_l_GH_BEG3;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [4-1:0] N1BEG0_input;
+	wire [4-1:0] N1BEG1_input;
+	wire [4-1:0] N1BEG2_input;
+	wire [4-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [4-1:0] N4BEG0_input;
+	wire [4-1:0] N4BEG1_input;
+	wire [4-1:0] N4BEG2_input;
+	wire [4-1:0] N4BEG3_input;
+	wire [8-1:0] NN4BEG0_input;
+	wire [8-1:0] NN4BEG1_input;
+	wire [8-1:0] NN4BEG2_input;
+	wire [8-1:0] NN4BEG3_input;
+	wire [4-1:0] E1BEG0_input;
+	wire [4-1:0] E1BEG1_input;
+	wire [4-1:0] E1BEG2_input;
+	wire [4-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [8-1:0] EE4BEG0_input;
+	wire [8-1:0] EE4BEG1_input;
+	wire [8-1:0] EE4BEG2_input;
+	wire [8-1:0] EE4BEG3_input;
+	wire [16-1:0] E6BEG0_input;
+	wire [16-1:0] E6BEG1_input;
+	wire [4-1:0] S1BEG0_input;
+	wire [4-1:0] S1BEG1_input;
+	wire [4-1:0] S1BEG2_input;
+	wire [4-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [4-1:0] S4BEG0_input;
+	wire [4-1:0] S4BEG1_input;
+	wire [4-1:0] S4BEG2_input;
+	wire [4-1:0] S4BEG3_input;
+	wire [8-1:0] SS4BEG0_input;
+	wire [8-1:0] SS4BEG1_input;
+	wire [8-1:0] SS4BEG2_input;
+	wire [8-1:0] SS4BEG3_input;
+	wire [4-1:0] top2bot0_input;
+	wire [4-1:0] top2bot1_input;
+	wire [4-1:0] top2bot2_input;
+	wire [4-1:0] top2bot3_input;
+	wire [4-1:0] top2bot4_input;
+	wire [4-1:0] top2bot5_input;
+	wire [4-1:0] top2bot6_input;
+	wire [4-1:0] top2bot7_input;
+	wire [4-1:0] top2bot8_input;
+	wire [4-1:0] top2bot9_input;
+	wire [4-1:0] top2bot10_input;
+	wire [4-1:0] top2bot11_input;
+	wire [4-1:0] top2bot12_input;
+	wire [4-1:0] top2bot13_input;
+	wire [4-1:0] top2bot14_input;
+	wire [4-1:0] top2bot15_input;
+	wire [8-1:0] top2bot16_input;
+	wire [8-1:0] top2bot17_input;
+	wire [4-1:0] W1BEG0_input;
+	wire [4-1:0] W1BEG1_input;
+	wire [4-1:0] W1BEG2_input;
+	wire [4-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [8-1:0] WW4BEG0_input;
+	wire [8-1:0] WW4BEG1_input;
+	wire [8-1:0] WW4BEG2_input;
+	wire [8-1:0] WW4BEG3_input;
+	wire [16-1:0] W6BEG0_input;
+	wire [16-1:0] W6BEG1_input;
+	wire [4-1:0] J2MID_ABa_BEG0_input;
+	wire [4-1:0] J2MID_ABa_BEG1_input;
+	wire [4-1:0] J2MID_ABa_BEG2_input;
+	wire [4-1:0] J2MID_ABa_BEG3_input;
+	wire [4-1:0] J2MID_CDa_BEG0_input;
+	wire [4-1:0] J2MID_CDa_BEG1_input;
+	wire [4-1:0] J2MID_CDa_BEG2_input;
+	wire [4-1:0] J2MID_CDa_BEG3_input;
+	wire [4-1:0] J2MID_EFa_BEG0_input;
+	wire [4-1:0] J2MID_EFa_BEG1_input;
+	wire [4-1:0] J2MID_EFa_BEG2_input;
+	wire [4-1:0] J2MID_EFa_BEG3_input;
+	wire [4-1:0] J2MID_GHa_BEG0_input;
+	wire [4-1:0] J2MID_GHa_BEG1_input;
+	wire [4-1:0] J2MID_GHa_BEG2_input;
+	wire [4-1:0] J2MID_GHa_BEG3_input;
+	wire [4-1:0] J2MID_ABb_BEG0_input;
+	wire [4-1:0] J2MID_ABb_BEG1_input;
+	wire [4-1:0] J2MID_ABb_BEG2_input;
+	wire [4-1:0] J2MID_ABb_BEG3_input;
+	wire [4-1:0] J2MID_CDb_BEG0_input;
+	wire [4-1:0] J2MID_CDb_BEG1_input;
+	wire [4-1:0] J2MID_CDb_BEG2_input;
+	wire [4-1:0] J2MID_CDb_BEG3_input;
+	wire [4-1:0] J2MID_EFb_BEG0_input;
+	wire [4-1:0] J2MID_EFb_BEG1_input;
+	wire [4-1:0] J2MID_EFb_BEG2_input;
+	wire [4-1:0] J2MID_EFb_BEG3_input;
+	wire [4-1:0] J2MID_GHb_BEG0_input;
+	wire [4-1:0] J2MID_GHb_BEG1_input;
+	wire [4-1:0] J2MID_GHb_BEG2_input;
+	wire [4-1:0] J2MID_GHb_BEG3_input;
+	wire [4-1:0] J2END_AB_BEG0_input;
+	wire [4-1:0] J2END_AB_BEG1_input;
+	wire [4-1:0] J2END_AB_BEG2_input;
+	wire [4-1:0] J2END_AB_BEG3_input;
+	wire [4-1:0] J2END_CD_BEG0_input;
+	wire [4-1:0] J2END_CD_BEG1_input;
+	wire [4-1:0] J2END_CD_BEG2_input;
+	wire [4-1:0] J2END_CD_BEG3_input;
+	wire [4-1:0] J2END_EF_BEG0_input;
+	wire [4-1:0] J2END_EF_BEG1_input;
+	wire [4-1:0] J2END_EF_BEG2_input;
+	wire [4-1:0] J2END_EF_BEG3_input;
+	wire [4-1:0] J2END_GH_BEG0_input;
+	wire [4-1:0] J2END_GH_BEG1_input;
+	wire [4-1:0] J2END_GH_BEG2_input;
+	wire [4-1:0] J2END_GH_BEG3_input;
+	wire [16-1:0] JN2BEG0_input;
+	wire [16-1:0] JN2BEG1_input;
+	wire [16-1:0] JN2BEG2_input;
+	wire [16-1:0] JN2BEG3_input;
+	wire [16-1:0] JN2BEG4_input;
+	wire [16-1:0] JN2BEG5_input;
+	wire [16-1:0] JN2BEG6_input;
+	wire [16-1:0] JN2BEG7_input;
+	wire [16-1:0] JE2BEG0_input;
+	wire [16-1:0] JE2BEG1_input;
+	wire [16-1:0] JE2BEG2_input;
+	wire [16-1:0] JE2BEG3_input;
+	wire [16-1:0] JE2BEG4_input;
+	wire [16-1:0] JE2BEG5_input;
+	wire [16-1:0] JE2BEG6_input;
+	wire [16-1:0] JE2BEG7_input;
+	wire [16-1:0] JS2BEG0_input;
+	wire [16-1:0] JS2BEG1_input;
+	wire [16-1:0] JS2BEG2_input;
+	wire [16-1:0] JS2BEG3_input;
+	wire [16-1:0] JS2BEG4_input;
+	wire [16-1:0] JS2BEG5_input;
+	wire [16-1:0] JS2BEG6_input;
+	wire [16-1:0] JS2BEG7_input;
+	wire [16-1:0] JW2BEG0_input;
+	wire [16-1:0] JW2BEG1_input;
+	wire [16-1:0] JW2BEG2_input;
+	wire [16-1:0] JW2BEG3_input;
+	wire [16-1:0] JW2BEG4_input;
+	wire [16-1:0] JW2BEG5_input;
+	wire [16-1:0] JW2BEG6_input;
+	wire [16-1:0] JW2BEG7_input;
+	wire [4-1:0] J_l_AB_BEG0_input;
+	wire [4-1:0] J_l_AB_BEG1_input;
+	wire [4-1:0] J_l_AB_BEG2_input;
+	wire [4-1:0] J_l_AB_BEG3_input;
+	wire [4-1:0] J_l_CD_BEG0_input;
+	wire [4-1:0] J_l_CD_BEG1_input;
+	wire [4-1:0] J_l_CD_BEG2_input;
+	wire [4-1:0] J_l_CD_BEG3_input;
+	wire [4-1:0] J_l_EF_BEG0_input;
+	wire [4-1:0] J_l_EF_BEG1_input;
+	wire [4-1:0] J_l_EF_BEG2_input;
+	wire [4-1:0] J_l_EF_BEG3_input;
+	wire [4-1:0] J_l_GH_BEG0_input;
+	wire [4-1:0] J_l_GH_BEG1_input;
+	wire [4-1:0] J_l_GH_BEG2_input;
+	wire [4-1:0] J_l_GH_BEG3_input;
+
+	wire [2-1:0] DEBUG_select_N1BEG0;
+	wire [2-1:0] DEBUG_select_N1BEG1;
+	wire [2-1:0] DEBUG_select_N1BEG2;
+	wire [2-1:0] DEBUG_select_N1BEG3;
+	wire [2-1:0] DEBUG_select_N4BEG0;
+	wire [2-1:0] DEBUG_select_N4BEG1;
+	wire [2-1:0] DEBUG_select_N4BEG2;
+	wire [2-1:0] DEBUG_select_N4BEG3;
+	wire [3-1:0] DEBUG_select_NN4BEG0;
+	wire [3-1:0] DEBUG_select_NN4BEG1;
+	wire [3-1:0] DEBUG_select_NN4BEG2;
+	wire [3-1:0] DEBUG_select_NN4BEG3;
+	wire [2-1:0] DEBUG_select_E1BEG0;
+	wire [2-1:0] DEBUG_select_E1BEG1;
+	wire [2-1:0] DEBUG_select_E1BEG2;
+	wire [2-1:0] DEBUG_select_E1BEG3;
+	wire [3-1:0] DEBUG_select_EE4BEG0;
+	wire [3-1:0] DEBUG_select_EE4BEG1;
+	wire [3-1:0] DEBUG_select_EE4BEG2;
+	wire [3-1:0] DEBUG_select_EE4BEG3;
+	wire [4-1:0] DEBUG_select_E6BEG0;
+	wire [4-1:0] DEBUG_select_E6BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG0;
+	wire [2-1:0] DEBUG_select_S1BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG2;
+	wire [2-1:0] DEBUG_select_S1BEG3;
+	wire [2-1:0] DEBUG_select_S4BEG0;
+	wire [2-1:0] DEBUG_select_S4BEG1;
+	wire [2-1:0] DEBUG_select_S4BEG2;
+	wire [2-1:0] DEBUG_select_S4BEG3;
+	wire [3-1:0] DEBUG_select_SS4BEG0;
+	wire [3-1:0] DEBUG_select_SS4BEG1;
+	wire [3-1:0] DEBUG_select_SS4BEG2;
+	wire [3-1:0] DEBUG_select_SS4BEG3;
+	wire [2-1:0] DEBUG_select_top2bot0;
+	wire [2-1:0] DEBUG_select_top2bot1;
+	wire [2-1:0] DEBUG_select_top2bot2;
+	wire [2-1:0] DEBUG_select_top2bot3;
+	wire [2-1:0] DEBUG_select_top2bot4;
+	wire [2-1:0] DEBUG_select_top2bot5;
+	wire [2-1:0] DEBUG_select_top2bot6;
+	wire [2-1:0] DEBUG_select_top2bot7;
+	wire [2-1:0] DEBUG_select_top2bot8;
+	wire [2-1:0] DEBUG_select_top2bot9;
+	wire [2-1:0] DEBUG_select_top2bot10;
+	wire [2-1:0] DEBUG_select_top2bot11;
+	wire [2-1:0] DEBUG_select_top2bot12;
+	wire [2-1:0] DEBUG_select_top2bot13;
+	wire [2-1:0] DEBUG_select_top2bot14;
+	wire [2-1:0] DEBUG_select_top2bot15;
+	wire [3-1:0] DEBUG_select_top2bot16;
+	wire [3-1:0] DEBUG_select_top2bot17;
+	wire [2-1:0] DEBUG_select_W1BEG0;
+	wire [2-1:0] DEBUG_select_W1BEG1;
+	wire [2-1:0] DEBUG_select_W1BEG2;
+	wire [2-1:0] DEBUG_select_W1BEG3;
+	wire [3-1:0] DEBUG_select_WW4BEG0;
+	wire [3-1:0] DEBUG_select_WW4BEG1;
+	wire [3-1:0] DEBUG_select_WW4BEG2;
+	wire [3-1:0] DEBUG_select_WW4BEG3;
+	wire [4-1:0] DEBUG_select_W6BEG0;
+	wire [4-1:0] DEBUG_select_W6BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG0;
+	wire [4-1:0] DEBUG_select_JN2BEG1;
+	wire [4-1:0] DEBUG_select_JN2BEG2;
+	wire [4-1:0] DEBUG_select_JN2BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG4;
+	wire [4-1:0] DEBUG_select_JN2BEG5;
+	wire [4-1:0] DEBUG_select_JN2BEG6;
+	wire [4-1:0] DEBUG_select_JN2BEG7;
+	wire [4-1:0] DEBUG_select_JE2BEG0;
+	wire [4-1:0] DEBUG_select_JE2BEG1;
+	wire [4-1:0] DEBUG_select_JE2BEG2;
+	wire [4-1:0] DEBUG_select_JE2BEG3;
+	wire [4-1:0] DEBUG_select_JE2BEG4;
+	wire [4-1:0] DEBUG_select_JE2BEG5;
+	wire [4-1:0] DEBUG_select_JE2BEG6;
+	wire [4-1:0] DEBUG_select_JE2BEG7;
+	wire [4-1:0] DEBUG_select_JS2BEG0;
+	wire [4-1:0] DEBUG_select_JS2BEG1;
+	wire [4-1:0] DEBUG_select_JS2BEG2;
+	wire [4-1:0] DEBUG_select_JS2BEG3;
+	wire [4-1:0] DEBUG_select_JS2BEG4;
+	wire [4-1:0] DEBUG_select_JS2BEG5;
+	wire [4-1:0] DEBUG_select_JS2BEG6;
+	wire [4-1:0] DEBUG_select_JS2BEG7;
+	wire [4-1:0] DEBUG_select_JW2BEG0;
+	wire [4-1:0] DEBUG_select_JW2BEG1;
+	wire [4-1:0] DEBUG_select_JW2BEG2;
+	wire [4-1:0] DEBUG_select_JW2BEG3;
+	wire [4-1:0] DEBUG_select_JW2BEG4;
+	wire [4-1:0] DEBUG_select_JW2BEG5;
+	wire [4-1:0] DEBUG_select_JW2BEG6;
+	wire [4-1:0] DEBUG_select_JW2BEG7;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG3;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-4
+	assign N1BEG0_input = {J_l_CD_END1,JW2END3,J2MID_CDb_END3,bot2top2};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG0 (
+	.A0 (N1BEG0_input[0]),
+	.A1 (N1BEG0_input[1]),
+	.A2 (N1BEG0_input[2]),
+	.A3 (N1BEG0_input[3]),
+	.S0 (ConfigBits[0+0]),
+	.S0N (ConfigBits_N[0+0]),
+	.S1 (ConfigBits[0+1]),
+	.S1N (ConfigBits_N[0+1]),
+	.X (N1BEG0)
+	);
+
+// switch matrix multiplexer  N1BEG1 		MUX-4
+	assign N1BEG1_input = {J_l_EF_END2,JW2END0,J2MID_EFb_END0,bot2top3};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG1 (
+	.A0 (N1BEG1_input[0]),
+	.A1 (N1BEG1_input[1]),
+	.A2 (N1BEG1_input[2]),
+	.A3 (N1BEG1_input[3]),
+	.S0 (ConfigBits[2+0]),
+	.S0N (ConfigBits_N[2+0]),
+	.S1 (ConfigBits[2+1]),
+	.S1N (ConfigBits_N[2+1]),
+	.X (N1BEG1)
+	);
+
+// switch matrix multiplexer  N1BEG2 		MUX-4
+	assign N1BEG2_input = {J_l_GH_END3,JW2END1,J2MID_GHb_END1,bot2top4};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG2 (
+	.A0 (N1BEG2_input[0]),
+	.A1 (N1BEG2_input[1]),
+	.A2 (N1BEG2_input[2]),
+	.A3 (N1BEG2_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (N1BEG2)
+	);
+
+// switch matrix multiplexer  N1BEG3 		MUX-4
+	assign N1BEG3_input = {J_l_AB_END0,JW2END2,J2MID_ABb_END2,bot2top5};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG3 (
+	.A0 (N1BEG3_input[0]),
+	.A1 (N1BEG3_input[1]),
+	.A2 (N1BEG3_input[2]),
+	.A3 (N1BEG3_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (N1BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = JN2END0;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = JN2END1;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = JN2END2;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = JN2END3;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = JN2END4;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = JN2END5;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = JN2END6;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = JN2END7;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = N2MID0;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = N2MID1;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = N2MID2;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = N2MID3;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = N2MID4;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = N2MID5;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = N2MID6;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = N2MID7;
+// switch matrix multiplexer  N4BEG0 		MUX-4
+	assign N4BEG0_input = {E6END1,bot2top4,N4END1,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG0 (
+	.A0 (N4BEG0_input[0]),
+	.A1 (N4BEG0_input[1]),
+	.A2 (N4BEG0_input[2]),
+	.A3 (N4BEG0_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (N4BEG0)
+	);
+
+// switch matrix multiplexer  N4BEG1 		MUX-4
+	assign N4BEG1_input = {E6END0,bot2top5,N4END2,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG1 (
+	.A0 (N4BEG1_input[0]),
+	.A1 (N4BEG1_input[1]),
+	.A2 (N4BEG1_input[2]),
+	.A3 (N4BEG1_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (N4BEG1)
+	);
+
+// switch matrix multiplexer  N4BEG2 		MUX-4
+	assign N4BEG2_input = {W6END1,bot2top6,N4END3,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG2 (
+	.A0 (N4BEG2_input[0]),
+	.A1 (N4BEG2_input[1]),
+	.A2 (N4BEG2_input[2]),
+	.A3 (N4BEG2_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (N4BEG2)
+	);
+
+// switch matrix multiplexer  N4BEG3 		MUX-4
+	assign N4BEG3_input = {W6END0,bot2top7,N4END0,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG3 (
+	.A0 (N4BEG3_input[0]),
+	.A1 (N4BEG3_input[1]),
+	.A2 (N4BEG3_input[2]),
+	.A3 (N4BEG3_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (N4BEG3)
+	);
+
+// switch matrix multiplexer  NN4BEG0 		MUX-8
+	assign NN4BEG0_input = {J2END_GH_END1,J2MID_CDb_END1,J2MID_ABb_END1,W1END2,E1END2,bot2top6,bot2top2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG0 (
+	.A0 (NN4BEG0_input[0]),
+	.A1 (NN4BEG0_input[1]),
+	.A2 (NN4BEG0_input[2]),
+	.A3 (NN4BEG0_input[3]),
+	.A4 (NN4BEG0_input[4]),
+	.A5 (NN4BEG0_input[5]),
+	.A6 (NN4BEG0_input[6]),
+	.A7 (NN4BEG0_input[7]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.S2 (ConfigBits[16+2]),
+	.S2N (ConfigBits_N[16+2]),
+	.X (NN4BEG0)
+	);
+
+// switch matrix multiplexer  NN4BEG1 		MUX-8
+	assign NN4BEG1_input = {J2END_EF_END1,J2MID_CDa_END2,J2MID_ABa_END2,W1END3,E1END3,bot2top7,bot2top3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG1 (
+	.A0 (NN4BEG1_input[0]),
+	.A1 (NN4BEG1_input[1]),
+	.A2 (NN4BEG1_input[2]),
+	.A3 (NN4BEG1_input[3]),
+	.A4 (NN4BEG1_input[4]),
+	.A5 (NN4BEG1_input[5]),
+	.A6 (NN4BEG1_input[6]),
+	.A7 (NN4BEG1_input[7]),
+	.S0 (ConfigBits[19+0]),
+	.S0N (ConfigBits_N[19+0]),
+	.S1 (ConfigBits[19+1]),
+	.S1N (ConfigBits_N[19+1]),
+	.S2 (ConfigBits[19+2]),
+	.S2N (ConfigBits_N[19+2]),
+	.X (NN4BEG1)
+	);
+
+// switch matrix multiplexer  NN4BEG2 		MUX-8
+	assign NN4BEG2_input = {J2END_CD_END1,J2MID_GHb_END1,J2MID_EFb_END1,W1END0,E1END0,bot2top8,bot2top4,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG2 (
+	.A0 (NN4BEG2_input[0]),
+	.A1 (NN4BEG2_input[1]),
+	.A2 (NN4BEG2_input[2]),
+	.A3 (NN4BEG2_input[3]),
+	.A4 (NN4BEG2_input[4]),
+	.A5 (NN4BEG2_input[5]),
+	.A6 (NN4BEG2_input[6]),
+	.A7 (NN4BEG2_input[7]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.S2 (ConfigBits[22+2]),
+	.S2N (ConfigBits_N[22+2]),
+	.X (NN4BEG2)
+	);
+
+// switch matrix multiplexer  NN4BEG3 		MUX-8
+	assign NN4BEG3_input = {J2END_AB_END1,J2MID_GHa_END2,J2MID_EFa_END2,W1END1,E1END1,bot2top9,bot2top5,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG3 (
+	.A0 (NN4BEG3_input[0]),
+	.A1 (NN4BEG3_input[1]),
+	.A2 (NN4BEG3_input[2]),
+	.A3 (NN4BEG3_input[3]),
+	.A4 (NN4BEG3_input[4]),
+	.A5 (NN4BEG3_input[5]),
+	.A6 (NN4BEG3_input[6]),
+	.A7 (NN4BEG3_input[7]),
+	.S0 (ConfigBits[25+0]),
+	.S0N (ConfigBits_N[25+0]),
+	.S1 (ConfigBits[25+1]),
+	.S1N (ConfigBits_N[25+1]),
+	.S2 (ConfigBits[25+2]),
+	.S2N (ConfigBits_N[25+2]),
+	.X (NN4BEG3)
+	);
+
+// switch matrix multiplexer  E1BEG0 		MUX-4
+	assign E1BEG0_input = {J_l_CD_END1,JN2END3,J2MID_CDb_END3,bot2top3};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG0 (
+	.A0 (E1BEG0_input[0]),
+	.A1 (E1BEG0_input[1]),
+	.A2 (E1BEG0_input[2]),
+	.A3 (E1BEG0_input[3]),
+	.S0 (ConfigBits[28+0]),
+	.S0N (ConfigBits_N[28+0]),
+	.S1 (ConfigBits[28+1]),
+	.S1N (ConfigBits_N[28+1]),
+	.X (E1BEG0)
+	);
+
+// switch matrix multiplexer  E1BEG1 		MUX-4
+	assign E1BEG1_input = {J_l_EF_END2,JN2END0,J2MID_EFb_END0,bot2top4};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG1 (
+	.A0 (E1BEG1_input[0]),
+	.A1 (E1BEG1_input[1]),
+	.A2 (E1BEG1_input[2]),
+	.A3 (E1BEG1_input[3]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.X (E1BEG1)
+	);
+
+// switch matrix multiplexer  E1BEG2 		MUX-4
+	assign E1BEG2_input = {J_l_GH_END3,JN2END1,J2MID_GHb_END1,bot2top5};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG2 (
+	.A0 (E1BEG2_input[0]),
+	.A1 (E1BEG2_input[1]),
+	.A2 (E1BEG2_input[2]),
+	.A3 (E1BEG2_input[3]),
+	.S0 (ConfigBits[32+0]),
+	.S0N (ConfigBits_N[32+0]),
+	.S1 (ConfigBits[32+1]),
+	.S1N (ConfigBits_N[32+1]),
+	.X (E1BEG2)
+	);
+
+// switch matrix multiplexer  E1BEG3 		MUX-4
+	assign E1BEG3_input = {J_l_AB_END0,JN2END2,J2MID_ABb_END2,bot2top6};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG3 (
+	.A0 (E1BEG3_input[0]),
+	.A1 (E1BEG3_input[1]),
+	.A2 (E1BEG3_input[2]),
+	.A3 (E1BEG3_input[3]),
+	.S0 (ConfigBits[34+0]),
+	.S0N (ConfigBits_N[34+0]),
+	.S1 (ConfigBits[34+1]),
+	.S1N (ConfigBits_N[34+1]),
+	.X (E1BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = JE2END0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = JE2END1;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = JE2END2;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = JE2END3;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = JE2END4;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = JE2END5;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = JE2END6;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = JE2END7;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = E2MID0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = E2MID1;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = E2MID2;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = E2MID3;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = E2MID4;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = E2MID5;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = E2MID6;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = E2MID7;
+// switch matrix multiplexer  EE4BEG0 		MUX-8
+	assign EE4BEG0_input = {J2END_GH_END0,J2MID_CDb_END1,J2MID_ABb_END1,S1END2,E1END2,bot2top6,bot2top2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG0 (
+	.A0 (EE4BEG0_input[0]),
+	.A1 (EE4BEG0_input[1]),
+	.A2 (EE4BEG0_input[2]),
+	.A3 (EE4BEG0_input[3]),
+	.A4 (EE4BEG0_input[4]),
+	.A5 (EE4BEG0_input[5]),
+	.A6 (EE4BEG0_input[6]),
+	.A7 (EE4BEG0_input[7]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.S2 (ConfigBits[36+2]),
+	.S2N (ConfigBits_N[36+2]),
+	.X (EE4BEG0)
+	);
+
+// switch matrix multiplexer  EE4BEG1 		MUX-8
+	assign EE4BEG1_input = {J2END_EF_END0,J2MID_CDa_END2,J2MID_ABa_END2,S1END3,E1END3,bot2top7,bot2top3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG1 (
+	.A0 (EE4BEG1_input[0]),
+	.A1 (EE4BEG1_input[1]),
+	.A2 (EE4BEG1_input[2]),
+	.A3 (EE4BEG1_input[3]),
+	.A4 (EE4BEG1_input[4]),
+	.A5 (EE4BEG1_input[5]),
+	.A6 (EE4BEG1_input[6]),
+	.A7 (EE4BEG1_input[7]),
+	.S0 (ConfigBits[39+0]),
+	.S0N (ConfigBits_N[39+0]),
+	.S1 (ConfigBits[39+1]),
+	.S1N (ConfigBits_N[39+1]),
+	.S2 (ConfigBits[39+2]),
+	.S2N (ConfigBits_N[39+2]),
+	.X (EE4BEG1)
+	);
+
+// switch matrix multiplexer  EE4BEG2 		MUX-8
+	assign EE4BEG2_input = {J2END_CD_END0,J2MID_GHb_END1,J2MID_EFb_END1,S1END0,E1END0,bot2top8,bot2top4,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG2 (
+	.A0 (EE4BEG2_input[0]),
+	.A1 (EE4BEG2_input[1]),
+	.A2 (EE4BEG2_input[2]),
+	.A3 (EE4BEG2_input[3]),
+	.A4 (EE4BEG2_input[4]),
+	.A5 (EE4BEG2_input[5]),
+	.A6 (EE4BEG2_input[6]),
+	.A7 (EE4BEG2_input[7]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.S2 (ConfigBits[42+2]),
+	.S2N (ConfigBits_N[42+2]),
+	.X (EE4BEG2)
+	);
+
+// switch matrix multiplexer  EE4BEG3 		MUX-8
+	assign EE4BEG3_input = {J2END_AB_END0,J2MID_GHa_END2,J2MID_EFa_END2,S1END1,E1END1,bot2top9,bot2top5,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG3 (
+	.A0 (EE4BEG3_input[0]),
+	.A1 (EE4BEG3_input[1]),
+	.A2 (EE4BEG3_input[2]),
+	.A3 (EE4BEG3_input[3]),
+	.A4 (EE4BEG3_input[4]),
+	.A5 (EE4BEG3_input[5]),
+	.A6 (EE4BEG3_input[6]),
+	.A7 (EE4BEG3_input[7]),
+	.S0 (ConfigBits[45+0]),
+	.S0N (ConfigBits_N[45+0]),
+	.S1 (ConfigBits[45+1]),
+	.S1N (ConfigBits_N[45+1]),
+	.S2 (ConfigBits[45+2]),
+	.S2N (ConfigBits_N[45+2]),
+	.X (EE4BEG3)
+	);
+
+// switch matrix multiplexer  E6BEG0 		MUX-16
+	assign E6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,W1END3,E1END3,bot2top9,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG0 (
+	.A0 (E6BEG0_input[0]),
+	.A1 (E6BEG0_input[1]),
+	.A2 (E6BEG0_input[2]),
+	.A3 (E6BEG0_input[3]),
+	.A4 (E6BEG0_input[4]),
+	.A5 (E6BEG0_input[5]),
+	.A6 (E6BEG0_input[6]),
+	.A7 (E6BEG0_input[7]),
+	.A8 (E6BEG0_input[8]),
+	.A9 (E6BEG0_input[9]),
+	.A10 (E6BEG0_input[10]),
+	.A11 (E6BEG0_input[11]),
+	.A12 (E6BEG0_input[12]),
+	.A13 (E6BEG0_input[13]),
+	.A14 (E6BEG0_input[14]),
+	.A15 (E6BEG0_input[15]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.S2 (ConfigBits[48+2]),
+	.S2N (ConfigBits_N[48+2]),
+	.S3 (ConfigBits[48+3]),
+	.S3N (ConfigBits_N[48+3]),
+	.X (E6BEG0)
+	);
+
+// switch matrix multiplexer  E6BEG1 		MUX-16
+	assign E6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,W1END2,E1END2,bot2top9,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG1 (
+	.A0 (E6BEG1_input[0]),
+	.A1 (E6BEG1_input[1]),
+	.A2 (E6BEG1_input[2]),
+	.A3 (E6BEG1_input[3]),
+	.A4 (E6BEG1_input[4]),
+	.A5 (E6BEG1_input[5]),
+	.A6 (E6BEG1_input[6]),
+	.A7 (E6BEG1_input[7]),
+	.A8 (E6BEG1_input[8]),
+	.A9 (E6BEG1_input[9]),
+	.A10 (E6BEG1_input[10]),
+	.A11 (E6BEG1_input[11]),
+	.A12 (E6BEG1_input[12]),
+	.A13 (E6BEG1_input[13]),
+	.A14 (E6BEG1_input[14]),
+	.A15 (E6BEG1_input[15]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.S2 (ConfigBits[52+2]),
+	.S2N (ConfigBits_N[52+2]),
+	.S3 (ConfigBits[52+3]),
+	.S3N (ConfigBits_N[52+3]),
+	.X (E6BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG0 		MUX-4
+	assign S1BEG0_input = {J_l_CD_END1,JE2END3,J2MID_CDb_END3,bot2top4};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG0 (
+	.A0 (S1BEG0_input[0]),
+	.A1 (S1BEG0_input[1]),
+	.A2 (S1BEG0_input[2]),
+	.A3 (S1BEG0_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (S1BEG0)
+	);
+
+// switch matrix multiplexer  S1BEG1 		MUX-4
+	assign S1BEG1_input = {J_l_EF_END2,JE2END0,J2MID_EFb_END0,bot2top5};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG1 (
+	.A0 (S1BEG1_input[0]),
+	.A1 (S1BEG1_input[1]),
+	.A2 (S1BEG1_input[2]),
+	.A3 (S1BEG1_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (S1BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG2 		MUX-4
+	assign S1BEG2_input = {J_l_GH_END3,JE2END1,J2MID_GHb_END1,bot2top6};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG2 (
+	.A0 (S1BEG2_input[0]),
+	.A1 (S1BEG2_input[1]),
+	.A2 (S1BEG2_input[2]),
+	.A3 (S1BEG2_input[3]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.X (S1BEG2)
+	);
+
+// switch matrix multiplexer  S1BEG3 		MUX-4
+	assign S1BEG3_input = {J_l_AB_END0,JE2END2,J2MID_ABb_END2,bot2top7};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG3 (
+	.A0 (S1BEG3_input[0]),
+	.A1 (S1BEG3_input[1]),
+	.A2 (S1BEG3_input[2]),
+	.A3 (S1BEG3_input[3]),
+	.S0 (ConfigBits[62+0]),
+	.S0N (ConfigBits_N[62+0]),
+	.S1 (ConfigBits[62+1]),
+	.S1N (ConfigBits_N[62+1]),
+	.X (S1BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = JS2END0;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = JS2END1;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = JS2END2;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = JS2END3;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = JS2END4;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = JS2END5;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = JS2END6;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = JS2END7;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = S2MID0;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = S2MID1;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = S2MID2;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = S2MID3;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = S2MID4;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = S2MID5;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = S2MID6;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = S2MID7;
+// switch matrix multiplexer  S4BEG0 		MUX-4
+	assign S4BEG0_input = {S4END1,S2END2,E6END1,bot2top0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG0 (
+	.A0 (S4BEG0_input[0]),
+	.A1 (S4BEG0_input[1]),
+	.A2 (S4BEG0_input[2]),
+	.A3 (S4BEG0_input[3]),
+	.S0 (ConfigBits[64+0]),
+	.S0N (ConfigBits_N[64+0]),
+	.S1 (ConfigBits[64+1]),
+	.S1N (ConfigBits_N[64+1]),
+	.X (S4BEG0)
+	);
+
+// switch matrix multiplexer  S4BEG1 		MUX-4
+	assign S4BEG1_input = {S4END2,S2END3,E6END0,bot2top1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG1 (
+	.A0 (S4BEG1_input[0]),
+	.A1 (S4BEG1_input[1]),
+	.A2 (S4BEG1_input[2]),
+	.A3 (S4BEG1_input[3]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.X (S4BEG1)
+	);
+
+// switch matrix multiplexer  S4BEG2 		MUX-4
+	assign S4BEG2_input = {W6END1,S4END3,S2END0,bot2top2};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG2 (
+	.A0 (S4BEG2_input[0]),
+	.A1 (S4BEG2_input[1]),
+	.A2 (S4BEG2_input[2]),
+	.A3 (S4BEG2_input[3]),
+	.S0 (ConfigBits[68+0]),
+	.S0N (ConfigBits_N[68+0]),
+	.S1 (ConfigBits[68+1]),
+	.S1N (ConfigBits_N[68+1]),
+	.X (S4BEG2)
+	);
+
+// switch matrix multiplexer  S4BEG3 		MUX-4
+	assign S4BEG3_input = {W6END0,S4END0,S2END1,bot2top3};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG3 (
+	.A0 (S4BEG3_input[0]),
+	.A1 (S4BEG3_input[1]),
+	.A2 (S4BEG3_input[2]),
+	.A3 (S4BEG3_input[3]),
+	.S0 (ConfigBits[70+0]),
+	.S0N (ConfigBits_N[70+0]),
+	.S1 (ConfigBits[70+1]),
+	.S1N (ConfigBits_N[70+1]),
+	.X (S4BEG3)
+	);
+
+// switch matrix multiplexer  SS4BEG0 		MUX-8
+	assign SS4BEG0_input = {J2END_GH_END3,J2MID_CDb_END1,J2MID_ABb_END1,W1END2,E1END2,bot2top6,bot2top2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG0 (
+	.A0 (SS4BEG0_input[0]),
+	.A1 (SS4BEG0_input[1]),
+	.A2 (SS4BEG0_input[2]),
+	.A3 (SS4BEG0_input[3]),
+	.A4 (SS4BEG0_input[4]),
+	.A5 (SS4BEG0_input[5]),
+	.A6 (SS4BEG0_input[6]),
+	.A7 (SS4BEG0_input[7]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.S2 (ConfigBits[72+2]),
+	.S2N (ConfigBits_N[72+2]),
+	.X (SS4BEG0)
+	);
+
+// switch matrix multiplexer  SS4BEG1 		MUX-8
+	assign SS4BEG1_input = {J2END_EF_END3,J2MID_CDa_END2,J2MID_ABa_END2,W1END3,E1END3,bot2top7,bot2top3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG1 (
+	.A0 (SS4BEG1_input[0]),
+	.A1 (SS4BEG1_input[1]),
+	.A2 (SS4BEG1_input[2]),
+	.A3 (SS4BEG1_input[3]),
+	.A4 (SS4BEG1_input[4]),
+	.A5 (SS4BEG1_input[5]),
+	.A6 (SS4BEG1_input[6]),
+	.A7 (SS4BEG1_input[7]),
+	.S0 (ConfigBits[75+0]),
+	.S0N (ConfigBits_N[75+0]),
+	.S1 (ConfigBits[75+1]),
+	.S1N (ConfigBits_N[75+1]),
+	.S2 (ConfigBits[75+2]),
+	.S2N (ConfigBits_N[75+2]),
+	.X (SS4BEG1)
+	);
+
+// switch matrix multiplexer  SS4BEG2 		MUX-8
+	assign SS4BEG2_input = {J2END_CD_END3,J2MID_GHb_END1,J2MID_EFb_END1,W1END0,E1END0,bot2top8,bot2top4,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG2 (
+	.A0 (SS4BEG2_input[0]),
+	.A1 (SS4BEG2_input[1]),
+	.A2 (SS4BEG2_input[2]),
+	.A3 (SS4BEG2_input[3]),
+	.A4 (SS4BEG2_input[4]),
+	.A5 (SS4BEG2_input[5]),
+	.A6 (SS4BEG2_input[6]),
+	.A7 (SS4BEG2_input[7]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.S2 (ConfigBits[78+2]),
+	.S2N (ConfigBits_N[78+2]),
+	.X (SS4BEG2)
+	);
+
+// switch matrix multiplexer  SS4BEG3 		MUX-8
+	assign SS4BEG3_input = {J2END_AB_END3,J2MID_GHa_END2,J2MID_EFa_END2,W1END1,E1END1,bot2top9,bot2top5,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG3 (
+	.A0 (SS4BEG3_input[0]),
+	.A1 (SS4BEG3_input[1]),
+	.A2 (SS4BEG3_input[2]),
+	.A3 (SS4BEG3_input[3]),
+	.A4 (SS4BEG3_input[4]),
+	.A5 (SS4BEG3_input[5]),
+	.A6 (SS4BEG3_input[6]),
+	.A7 (SS4BEG3_input[7]),
+	.S0 (ConfigBits[81+0]),
+	.S0N (ConfigBits_N[81+0]),
+	.S1 (ConfigBits[81+1]),
+	.S1N (ConfigBits_N[81+1]),
+	.S2 (ConfigBits[81+2]),
+	.S2N (ConfigBits_N[81+2]),
+	.X (SS4BEG3)
+	);
+
+// switch matrix multiplexer  top2bot0 		MUX-4
+	assign top2bot0_input = {J_l_AB_END0,J2END_AB_END0,J2MID_ABb_END0,J2MID_ABa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot0 (
+	.A0 (top2bot0_input[0]),
+	.A1 (top2bot0_input[1]),
+	.A2 (top2bot0_input[2]),
+	.A3 (top2bot0_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (top2bot0)
+	);
+
+// switch matrix multiplexer  top2bot1 		MUX-4
+	assign top2bot1_input = {J_l_AB_END1,J2END_AB_END1,J2MID_ABb_END1,J2MID_ABa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot1 (
+	.A0 (top2bot1_input[0]),
+	.A1 (top2bot1_input[1]),
+	.A2 (top2bot1_input[2]),
+	.A3 (top2bot1_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (top2bot1)
+	);
+
+// switch matrix multiplexer  top2bot2 		MUX-4
+	assign top2bot2_input = {J_l_AB_END2,J2END_AB_END2,J2MID_ABb_END2,J2MID_ABa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot2 (
+	.A0 (top2bot2_input[0]),
+	.A1 (top2bot2_input[1]),
+	.A2 (top2bot2_input[2]),
+	.A3 (top2bot2_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (top2bot2)
+	);
+
+// switch matrix multiplexer  top2bot3 		MUX-4
+	assign top2bot3_input = {J_l_AB_END3,J2END_AB_END3,J2MID_ABb_END3,J2MID_ABa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot3 (
+	.A0 (top2bot3_input[0]),
+	.A1 (top2bot3_input[1]),
+	.A2 (top2bot3_input[2]),
+	.A3 (top2bot3_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (top2bot3)
+	);
+
+// switch matrix multiplexer  top2bot4 		MUX-4
+	assign top2bot4_input = {J_l_CD_END0,J2END_CD_END0,J2MID_CDb_END0,J2MID_CDa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot4 (
+	.A0 (top2bot4_input[0]),
+	.A1 (top2bot4_input[1]),
+	.A2 (top2bot4_input[2]),
+	.A3 (top2bot4_input[3]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.X (top2bot4)
+	);
+
+// switch matrix multiplexer  top2bot5 		MUX-4
+	assign top2bot5_input = {J_l_CD_END1,J2END_CD_END1,J2MID_CDb_END1,J2MID_CDa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot5 (
+	.A0 (top2bot5_input[0]),
+	.A1 (top2bot5_input[1]),
+	.A2 (top2bot5_input[2]),
+	.A3 (top2bot5_input[3]),
+	.S0 (ConfigBits[94+0]),
+	.S0N (ConfigBits_N[94+0]),
+	.S1 (ConfigBits[94+1]),
+	.S1N (ConfigBits_N[94+1]),
+	.X (top2bot5)
+	);
+
+// switch matrix multiplexer  top2bot6 		MUX-4
+	assign top2bot6_input = {J_l_CD_END2,J2END_CD_END2,J2MID_CDb_END2,J2MID_CDa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot6 (
+	.A0 (top2bot6_input[0]),
+	.A1 (top2bot6_input[1]),
+	.A2 (top2bot6_input[2]),
+	.A3 (top2bot6_input[3]),
+	.S0 (ConfigBits[96+0]),
+	.S0N (ConfigBits_N[96+0]),
+	.S1 (ConfigBits[96+1]),
+	.S1N (ConfigBits_N[96+1]),
+	.X (top2bot6)
+	);
+
+// switch matrix multiplexer  top2bot7 		MUX-4
+	assign top2bot7_input = {J_l_CD_END3,J2END_CD_END3,J2MID_CDb_END3,J2MID_CDa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot7 (
+	.A0 (top2bot7_input[0]),
+	.A1 (top2bot7_input[1]),
+	.A2 (top2bot7_input[2]),
+	.A3 (top2bot7_input[3]),
+	.S0 (ConfigBits[98+0]),
+	.S0N (ConfigBits_N[98+0]),
+	.S1 (ConfigBits[98+1]),
+	.S1N (ConfigBits_N[98+1]),
+	.X (top2bot7)
+	);
+
+// switch matrix multiplexer  top2bot8 		MUX-4
+	assign top2bot8_input = {J_l_EF_END0,J2END_EF_END0,J2MID_EFb_END0,J2MID_EFa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot8 (
+	.A0 (top2bot8_input[0]),
+	.A1 (top2bot8_input[1]),
+	.A2 (top2bot8_input[2]),
+	.A3 (top2bot8_input[3]),
+	.S0 (ConfigBits[100+0]),
+	.S0N (ConfigBits_N[100+0]),
+	.S1 (ConfigBits[100+1]),
+	.S1N (ConfigBits_N[100+1]),
+	.X (top2bot8)
+	);
+
+// switch matrix multiplexer  top2bot9 		MUX-4
+	assign top2bot9_input = {J_l_EF_END1,J2END_EF_END1,J2MID_EFb_END1,J2MID_EFa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot9 (
+	.A0 (top2bot9_input[0]),
+	.A1 (top2bot9_input[1]),
+	.A2 (top2bot9_input[2]),
+	.A3 (top2bot9_input[3]),
+	.S0 (ConfigBits[102+0]),
+	.S0N (ConfigBits_N[102+0]),
+	.S1 (ConfigBits[102+1]),
+	.S1N (ConfigBits_N[102+1]),
+	.X (top2bot9)
+	);
+
+// switch matrix multiplexer  top2bot10 		MUX-4
+	assign top2bot10_input = {J_l_EF_END2,J2END_EF_END2,J2MID_EFb_END2,J2MID_EFa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot10 (
+	.A0 (top2bot10_input[0]),
+	.A1 (top2bot10_input[1]),
+	.A2 (top2bot10_input[2]),
+	.A3 (top2bot10_input[3]),
+	.S0 (ConfigBits[104+0]),
+	.S0N (ConfigBits_N[104+0]),
+	.S1 (ConfigBits[104+1]),
+	.S1N (ConfigBits_N[104+1]),
+	.X (top2bot10)
+	);
+
+// switch matrix multiplexer  top2bot11 		MUX-4
+	assign top2bot11_input = {J_l_EF_END3,J2END_EF_END3,J2MID_EFb_END3,J2MID_EFa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot11 (
+	.A0 (top2bot11_input[0]),
+	.A1 (top2bot11_input[1]),
+	.A2 (top2bot11_input[2]),
+	.A3 (top2bot11_input[3]),
+	.S0 (ConfigBits[106+0]),
+	.S0N (ConfigBits_N[106+0]),
+	.S1 (ConfigBits[106+1]),
+	.S1N (ConfigBits_N[106+1]),
+	.X (top2bot11)
+	);
+
+// switch matrix multiplexer  top2bot12 		MUX-4
+	assign top2bot12_input = {J_l_GH_END0,J2END_GH_END0,J2MID_GHb_END0,J2MID_GHa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot12 (
+	.A0 (top2bot12_input[0]),
+	.A1 (top2bot12_input[1]),
+	.A2 (top2bot12_input[2]),
+	.A3 (top2bot12_input[3]),
+	.S0 (ConfigBits[108+0]),
+	.S0N (ConfigBits_N[108+0]),
+	.S1 (ConfigBits[108+1]),
+	.S1N (ConfigBits_N[108+1]),
+	.X (top2bot12)
+	);
+
+// switch matrix multiplexer  top2bot13 		MUX-4
+	assign top2bot13_input = {J_l_GH_END1,J2END_GH_END1,J2MID_GHb_END1,J2MID_GHa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot13 (
+	.A0 (top2bot13_input[0]),
+	.A1 (top2bot13_input[1]),
+	.A2 (top2bot13_input[2]),
+	.A3 (top2bot13_input[3]),
+	.S0 (ConfigBits[110+0]),
+	.S0N (ConfigBits_N[110+0]),
+	.S1 (ConfigBits[110+1]),
+	.S1N (ConfigBits_N[110+1]),
+	.X (top2bot13)
+	);
+
+// switch matrix multiplexer  top2bot14 		MUX-4
+	assign top2bot14_input = {J_l_GH_END2,J2END_GH_END2,J2MID_GHb_END2,J2MID_GHa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot14 (
+	.A0 (top2bot14_input[0]),
+	.A1 (top2bot14_input[1]),
+	.A2 (top2bot14_input[2]),
+	.A3 (top2bot14_input[3]),
+	.S0 (ConfigBits[112+0]),
+	.S0N (ConfigBits_N[112+0]),
+	.S1 (ConfigBits[112+1]),
+	.S1N (ConfigBits_N[112+1]),
+	.X (top2bot14)
+	);
+
+// switch matrix multiplexer  top2bot15 		MUX-4
+	assign top2bot15_input = {J_l_GH_END3,J2END_GH_END3,J2MID_GHb_END3,J2MID_GHa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_top2bot15 (
+	.A0 (top2bot15_input[0]),
+	.A1 (top2bot15_input[1]),
+	.A2 (top2bot15_input[2]),
+	.A3 (top2bot15_input[3]),
+	.S0 (ConfigBits[114+0]),
+	.S0N (ConfigBits_N[114+0]),
+	.S1 (ConfigBits[114+1]),
+	.S1N (ConfigBits_N[114+1]),
+	.X (top2bot15)
+	);
+
+// switch matrix multiplexer  top2bot16 		MUX-8
+	assign top2bot16_input = {JW2END6,JW2END4,JS2END6,JS2END4,JE2END6,JE2END4,JN2END6,JN2END4};
+	cus_mux81_buf inst_cus_mux81_buf_top2bot16 (
+	.A0 (top2bot16_input[0]),
+	.A1 (top2bot16_input[1]),
+	.A2 (top2bot16_input[2]),
+	.A3 (top2bot16_input[3]),
+	.A4 (top2bot16_input[4]),
+	.A5 (top2bot16_input[5]),
+	.A6 (top2bot16_input[6]),
+	.A7 (top2bot16_input[7]),
+	.S0 (ConfigBits[116+0]),
+	.S0N (ConfigBits_N[116+0]),
+	.S1 (ConfigBits[116+1]),
+	.S1N (ConfigBits_N[116+1]),
+	.S2 (ConfigBits[116+2]),
+	.S2N (ConfigBits_N[116+2]),
+	.X (top2bot16)
+	);
+
+// switch matrix multiplexer  top2bot17 		MUX-8
+	assign top2bot17_input = {JW2END7,JW2END5,JS2END7,JS2END5,JE2END7,JE2END5,JN2END7,JN2END5};
+	cus_mux81_buf inst_cus_mux81_buf_top2bot17 (
+	.A0 (top2bot17_input[0]),
+	.A1 (top2bot17_input[1]),
+	.A2 (top2bot17_input[2]),
+	.A3 (top2bot17_input[3]),
+	.A4 (top2bot17_input[4]),
+	.A5 (top2bot17_input[5]),
+	.A6 (top2bot17_input[6]),
+	.A7 (top2bot17_input[7]),
+	.S0 (ConfigBits[119+0]),
+	.S0N (ConfigBits_N[119+0]),
+	.S1 (ConfigBits[119+1]),
+	.S1N (ConfigBits_N[119+1]),
+	.S2 (ConfigBits[119+2]),
+	.S2N (ConfigBits_N[119+2]),
+	.X (top2bot17)
+	);
+
+// switch matrix multiplexer  W1BEG0 		MUX-4
+	assign W1BEG0_input = {J_l_CD_END1,JS2END3,J2MID_CDb_END3,bot2top5};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG0 (
+	.A0 (W1BEG0_input[0]),
+	.A1 (W1BEG0_input[1]),
+	.A2 (W1BEG0_input[2]),
+	.A3 (W1BEG0_input[3]),
+	.S0 (ConfigBits[122+0]),
+	.S0N (ConfigBits_N[122+0]),
+	.S1 (ConfigBits[122+1]),
+	.S1N (ConfigBits_N[122+1]),
+	.X (W1BEG0)
+	);
+
+// switch matrix multiplexer  W1BEG1 		MUX-4
+	assign W1BEG1_input = {J_l_EF_END2,JS2END0,J2MID_EFb_END0,bot2top6};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG1 (
+	.A0 (W1BEG1_input[0]),
+	.A1 (W1BEG1_input[1]),
+	.A2 (W1BEG1_input[2]),
+	.A3 (W1BEG1_input[3]),
+	.S0 (ConfigBits[124+0]),
+	.S0N (ConfigBits_N[124+0]),
+	.S1 (ConfigBits[124+1]),
+	.S1N (ConfigBits_N[124+1]),
+	.X (W1BEG1)
+	);
+
+// switch matrix multiplexer  W1BEG2 		MUX-4
+	assign W1BEG2_input = {J_l_GH_END3,JS2END1,J2MID_GHb_END1,bot2top7};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG2 (
+	.A0 (W1BEG2_input[0]),
+	.A1 (W1BEG2_input[1]),
+	.A2 (W1BEG2_input[2]),
+	.A3 (W1BEG2_input[3]),
+	.S0 (ConfigBits[126+0]),
+	.S0N (ConfigBits_N[126+0]),
+	.S1 (ConfigBits[126+1]),
+	.S1N (ConfigBits_N[126+1]),
+	.X (W1BEG2)
+	);
+
+// switch matrix multiplexer  W1BEG3 		MUX-4
+	assign W1BEG3_input = {J_l_AB_END0,JS2END2,J2MID_ABb_END2,bot2top0};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG3 (
+	.A0 (W1BEG3_input[0]),
+	.A1 (W1BEG3_input[1]),
+	.A2 (W1BEG3_input[2]),
+	.A3 (W1BEG3_input[3]),
+	.S0 (ConfigBits[128+0]),
+	.S0N (ConfigBits_N[128+0]),
+	.S1 (ConfigBits[128+1]),
+	.S1N (ConfigBits_N[128+1]),
+	.X (W1BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = W2END0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = JW2END1;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = JW2END2;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = W2END3;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = W2END4;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = JW2END5;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = JW2END6;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = W2END7;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = W2MID0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = W2MID1;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = W2MID2;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = W2MID3;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = W2MID4;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = W2MID5;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = W2MID6;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = W2MID7;
+// switch matrix multiplexer  WW4BEG0 		MUX-8
+	assign WW4BEG0_input = {J2END_GH_END2,J2MID_CDb_END1,J2MID_ABb_END1,W1END2,S1END2,bot2top6,bot2top2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG0 (
+	.A0 (WW4BEG0_input[0]),
+	.A1 (WW4BEG0_input[1]),
+	.A2 (WW4BEG0_input[2]),
+	.A3 (WW4BEG0_input[3]),
+	.A4 (WW4BEG0_input[4]),
+	.A5 (WW4BEG0_input[5]),
+	.A6 (WW4BEG0_input[6]),
+	.A7 (WW4BEG0_input[7]),
+	.S0 (ConfigBits[130+0]),
+	.S0N (ConfigBits_N[130+0]),
+	.S1 (ConfigBits[130+1]),
+	.S1N (ConfigBits_N[130+1]),
+	.S2 (ConfigBits[130+2]),
+	.S2N (ConfigBits_N[130+2]),
+	.X (WW4BEG0)
+	);
+
+// switch matrix multiplexer  WW4BEG1 		MUX-8
+	assign WW4BEG1_input = {J2END_EF_END2,J2MID_CDa_END2,J2MID_ABa_END2,W1END3,S1END3,bot2top7,bot2top3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG1 (
+	.A0 (WW4BEG1_input[0]),
+	.A1 (WW4BEG1_input[1]),
+	.A2 (WW4BEG1_input[2]),
+	.A3 (WW4BEG1_input[3]),
+	.A4 (WW4BEG1_input[4]),
+	.A5 (WW4BEG1_input[5]),
+	.A6 (WW4BEG1_input[6]),
+	.A7 (WW4BEG1_input[7]),
+	.S0 (ConfigBits[133+0]),
+	.S0N (ConfigBits_N[133+0]),
+	.S1 (ConfigBits[133+1]),
+	.S1N (ConfigBits_N[133+1]),
+	.S2 (ConfigBits[133+2]),
+	.S2N (ConfigBits_N[133+2]),
+	.X (WW4BEG1)
+	);
+
+// switch matrix multiplexer  WW4BEG2 		MUX-8
+	assign WW4BEG2_input = {J2END_CD_END2,J2MID_GHb_END1,J2MID_EFb_END1,W1END0,S1END0,bot2top8,bot2top4,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG2 (
+	.A0 (WW4BEG2_input[0]),
+	.A1 (WW4BEG2_input[1]),
+	.A2 (WW4BEG2_input[2]),
+	.A3 (WW4BEG2_input[3]),
+	.A4 (WW4BEG2_input[4]),
+	.A5 (WW4BEG2_input[5]),
+	.A6 (WW4BEG2_input[6]),
+	.A7 (WW4BEG2_input[7]),
+	.S0 (ConfigBits[136+0]),
+	.S0N (ConfigBits_N[136+0]),
+	.S1 (ConfigBits[136+1]),
+	.S1N (ConfigBits_N[136+1]),
+	.S2 (ConfigBits[136+2]),
+	.S2N (ConfigBits_N[136+2]),
+	.X (WW4BEG2)
+	);
+
+// switch matrix multiplexer  WW4BEG3 		MUX-8
+	assign WW4BEG3_input = {J2END_AB_END2,J2MID_GHa_END2,J2MID_EFa_END2,W1END1,S1END1,bot2top9,bot2top5,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG3 (
+	.A0 (WW4BEG3_input[0]),
+	.A1 (WW4BEG3_input[1]),
+	.A2 (WW4BEG3_input[2]),
+	.A3 (WW4BEG3_input[3]),
+	.A4 (WW4BEG3_input[4]),
+	.A5 (WW4BEG3_input[5]),
+	.A6 (WW4BEG3_input[6]),
+	.A7 (WW4BEG3_input[7]),
+	.S0 (ConfigBits[139+0]),
+	.S0N (ConfigBits_N[139+0]),
+	.S1 (ConfigBits[139+1]),
+	.S1N (ConfigBits_N[139+1]),
+	.S2 (ConfigBits[139+2]),
+	.S2N (ConfigBits_N[139+2]),
+	.X (WW4BEG3)
+	);
+
+// switch matrix multiplexer  W6BEG0 		MUX-16
+	assign W6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,W1END3,E1END3,bot2top9,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG0 (
+	.A0 (W6BEG0_input[0]),
+	.A1 (W6BEG0_input[1]),
+	.A2 (W6BEG0_input[2]),
+	.A3 (W6BEG0_input[3]),
+	.A4 (W6BEG0_input[4]),
+	.A5 (W6BEG0_input[5]),
+	.A6 (W6BEG0_input[6]),
+	.A7 (W6BEG0_input[7]),
+	.A8 (W6BEG0_input[8]),
+	.A9 (W6BEG0_input[9]),
+	.A10 (W6BEG0_input[10]),
+	.A11 (W6BEG0_input[11]),
+	.A12 (W6BEG0_input[12]),
+	.A13 (W6BEG0_input[13]),
+	.A14 (W6BEG0_input[14]),
+	.A15 (W6BEG0_input[15]),
+	.S0 (ConfigBits[142+0]),
+	.S0N (ConfigBits_N[142+0]),
+	.S1 (ConfigBits[142+1]),
+	.S1N (ConfigBits_N[142+1]),
+	.S2 (ConfigBits[142+2]),
+	.S2N (ConfigBits_N[142+2]),
+	.S3 (ConfigBits[142+3]),
+	.S3N (ConfigBits_N[142+3]),
+	.X (W6BEG0)
+	);
+
+// switch matrix multiplexer  W6BEG1 		MUX-16
+	assign W6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,W1END2,E1END2,bot2top9,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG1 (
+	.A0 (W6BEG1_input[0]),
+	.A1 (W6BEG1_input[1]),
+	.A2 (W6BEG1_input[2]),
+	.A3 (W6BEG1_input[3]),
+	.A4 (W6BEG1_input[4]),
+	.A5 (W6BEG1_input[5]),
+	.A6 (W6BEG1_input[6]),
+	.A7 (W6BEG1_input[7]),
+	.A8 (W6BEG1_input[8]),
+	.A9 (W6BEG1_input[9]),
+	.A10 (W6BEG1_input[10]),
+	.A11 (W6BEG1_input[11]),
+	.A12 (W6BEG1_input[12]),
+	.A13 (W6BEG1_input[13]),
+	.A14 (W6BEG1_input[14]),
+	.A15 (W6BEG1_input[15]),
+	.S0 (ConfigBits[146+0]),
+	.S0N (ConfigBits_N[146+0]),
+	.S1 (ConfigBits[146+1]),
+	.S1N (ConfigBits_N[146+1]),
+	.S2 (ConfigBits[146+2]),
+	.S2N (ConfigBits_N[146+2]),
+	.S3 (ConfigBits[146+3]),
+	.S3N (ConfigBits_N[146+3]),
+	.X (W6BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG0 		MUX-4
+	assign J2MID_ABa_BEG0_input = {JN2END3,W2MID6,S2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG0 (
+	.A0 (J2MID_ABa_BEG0_input[0]),
+	.A1 (J2MID_ABa_BEG0_input[1]),
+	.A2 (J2MID_ABa_BEG0_input[2]),
+	.A3 (J2MID_ABa_BEG0_input[3]),
+	.S0 (ConfigBits[150+0]),
+	.S0N (ConfigBits_N[150+0]),
+	.S1 (ConfigBits[150+1]),
+	.S1N (ConfigBits_N[150+1]),
+	.X (J2MID_ABa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG1 		MUX-4
+	assign J2MID_ABa_BEG1_input = {JE2END3,W2MID2,S2MID2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG1 (
+	.A0 (J2MID_ABa_BEG1_input[0]),
+	.A1 (J2MID_ABa_BEG1_input[1]),
+	.A2 (J2MID_ABa_BEG1_input[2]),
+	.A3 (J2MID_ABa_BEG1_input[3]),
+	.S0 (ConfigBits[152+0]),
+	.S0N (ConfigBits_N[152+0]),
+	.S1 (ConfigBits[152+1]),
+	.S1N (ConfigBits_N[152+1]),
+	.X (J2MID_ABa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG2 		MUX-4
+	assign J2MID_ABa_BEG2_input = {JS2END3,W2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG2 (
+	.A0 (J2MID_ABa_BEG2_input[0]),
+	.A1 (J2MID_ABa_BEG2_input[1]),
+	.A2 (J2MID_ABa_BEG2_input[2]),
+	.A3 (J2MID_ABa_BEG2_input[3]),
+	.S0 (ConfigBits[154+0]),
+	.S0N (ConfigBits_N[154+0]),
+	.S1 (ConfigBits[154+1]),
+	.S1N (ConfigBits_N[154+1]),
+	.X (J2MID_ABa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG3 		MUX-4
+	assign J2MID_ABa_BEG3_input = {JW2END3,S2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG3 (
+	.A0 (J2MID_ABa_BEG3_input[0]),
+	.A1 (J2MID_ABa_BEG3_input[1]),
+	.A2 (J2MID_ABa_BEG3_input[2]),
+	.A3 (J2MID_ABa_BEG3_input[3]),
+	.S0 (ConfigBits[156+0]),
+	.S0N (ConfigBits_N[156+0]),
+	.S1 (ConfigBits[156+1]),
+	.S1N (ConfigBits_N[156+1]),
+	.X (J2MID_ABa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG0 		MUX-4
+	assign J2MID_CDa_BEG0_input = {JN2END4,W2MID6,S2MID6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG0 (
+	.A0 (J2MID_CDa_BEG0_input[0]),
+	.A1 (J2MID_CDa_BEG0_input[1]),
+	.A2 (J2MID_CDa_BEG0_input[2]),
+	.A3 (J2MID_CDa_BEG0_input[3]),
+	.S0 (ConfigBits[158+0]),
+	.S0N (ConfigBits_N[158+0]),
+	.S1 (ConfigBits[158+1]),
+	.S1N (ConfigBits_N[158+1]),
+	.X (J2MID_CDa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG1 		MUX-4
+	assign J2MID_CDa_BEG1_input = {JE2END4,W2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG1 (
+	.A0 (J2MID_CDa_BEG1_input[0]),
+	.A1 (J2MID_CDa_BEG1_input[1]),
+	.A2 (J2MID_CDa_BEG1_input[2]),
+	.A3 (J2MID_CDa_BEG1_input[3]),
+	.S0 (ConfigBits[160+0]),
+	.S0N (ConfigBits_N[160+0]),
+	.S1 (ConfigBits[160+1]),
+	.S1N (ConfigBits_N[160+1]),
+	.X (J2MID_CDa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG2 		MUX-4
+	assign J2MID_CDa_BEG2_input = {JS2END4,S2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG2 (
+	.A0 (J2MID_CDa_BEG2_input[0]),
+	.A1 (J2MID_CDa_BEG2_input[1]),
+	.A2 (J2MID_CDa_BEG2_input[2]),
+	.A3 (J2MID_CDa_BEG2_input[3]),
+	.S0 (ConfigBits[162+0]),
+	.S0N (ConfigBits_N[162+0]),
+	.S1 (ConfigBits[162+1]),
+	.S1N (ConfigBits_N[162+1]),
+	.X (J2MID_CDa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG3 		MUX-4
+	assign J2MID_CDa_BEG3_input = {JW2END4,W2MID0,S2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG3 (
+	.A0 (J2MID_CDa_BEG3_input[0]),
+	.A1 (J2MID_CDa_BEG3_input[1]),
+	.A2 (J2MID_CDa_BEG3_input[2]),
+	.A3 (J2MID_CDa_BEG3_input[3]),
+	.S0 (ConfigBits[164+0]),
+	.S0N (ConfigBits_N[164+0]),
+	.S1 (ConfigBits[164+1]),
+	.S1N (ConfigBits_N[164+1]),
+	.X (J2MID_CDa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG0 		MUX-4
+	assign J2MID_EFa_BEG0_input = {JN2END5,W2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG0 (
+	.A0 (J2MID_EFa_BEG0_input[0]),
+	.A1 (J2MID_EFa_BEG0_input[1]),
+	.A2 (J2MID_EFa_BEG0_input[2]),
+	.A3 (J2MID_EFa_BEG0_input[3]),
+	.S0 (ConfigBits[166+0]),
+	.S0N (ConfigBits_N[166+0]),
+	.S1 (ConfigBits[166+1]),
+	.S1N (ConfigBits_N[166+1]),
+	.X (J2MID_EFa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG1 		MUX-4
+	assign J2MID_EFa_BEG1_input = {JE2END5,S2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG1 (
+	.A0 (J2MID_EFa_BEG1_input[0]),
+	.A1 (J2MID_EFa_BEG1_input[1]),
+	.A2 (J2MID_EFa_BEG1_input[2]),
+	.A3 (J2MID_EFa_BEG1_input[3]),
+	.S0 (ConfigBits[168+0]),
+	.S0N (ConfigBits_N[168+0]),
+	.S1 (ConfigBits[168+1]),
+	.S1N (ConfigBits_N[168+1]),
+	.X (J2MID_EFa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG2 		MUX-4
+	assign J2MID_EFa_BEG2_input = {JS2END5,W2MID4,S2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG2 (
+	.A0 (J2MID_EFa_BEG2_input[0]),
+	.A1 (J2MID_EFa_BEG2_input[1]),
+	.A2 (J2MID_EFa_BEG2_input[2]),
+	.A3 (J2MID_EFa_BEG2_input[3]),
+	.S0 (ConfigBits[170+0]),
+	.S0N (ConfigBits_N[170+0]),
+	.S1 (ConfigBits[170+1]),
+	.S1N (ConfigBits_N[170+1]),
+	.X (J2MID_EFa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG3 		MUX-4
+	assign J2MID_EFa_BEG3_input = {JW2END5,W2MID0,S2MID0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG3 (
+	.A0 (J2MID_EFa_BEG3_input[0]),
+	.A1 (J2MID_EFa_BEG3_input[1]),
+	.A2 (J2MID_EFa_BEG3_input[2]),
+	.A3 (J2MID_EFa_BEG3_input[3]),
+	.S0 (ConfigBits[172+0]),
+	.S0N (ConfigBits_N[172+0]),
+	.S1 (ConfigBits[172+1]),
+	.S1N (ConfigBits_N[172+1]),
+	.X (J2MID_EFa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG0 		MUX-4
+	assign J2MID_GHa_BEG0_input = {JN2END6,S2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG0 (
+	.A0 (J2MID_GHa_BEG0_input[0]),
+	.A1 (J2MID_GHa_BEG0_input[1]),
+	.A2 (J2MID_GHa_BEG0_input[2]),
+	.A3 (J2MID_GHa_BEG0_input[3]),
+	.S0 (ConfigBits[174+0]),
+	.S0N (ConfigBits_N[174+0]),
+	.S1 (ConfigBits[174+1]),
+	.S1N (ConfigBits_N[174+1]),
+	.X (J2MID_GHa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG1 		MUX-4
+	assign J2MID_GHa_BEG1_input = {JE2END6,W2MID2,S2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG1 (
+	.A0 (J2MID_GHa_BEG1_input[0]),
+	.A1 (J2MID_GHa_BEG1_input[1]),
+	.A2 (J2MID_GHa_BEG1_input[2]),
+	.A3 (J2MID_GHa_BEG1_input[3]),
+	.S0 (ConfigBits[176+0]),
+	.S0N (ConfigBits_N[176+0]),
+	.S1 (ConfigBits[176+1]),
+	.S1N (ConfigBits_N[176+1]),
+	.X (J2MID_GHa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG2 		MUX-4
+	assign J2MID_GHa_BEG2_input = {JS2END6,W2MID4,S2MID4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG2 (
+	.A0 (J2MID_GHa_BEG2_input[0]),
+	.A1 (J2MID_GHa_BEG2_input[1]),
+	.A2 (J2MID_GHa_BEG2_input[2]),
+	.A3 (J2MID_GHa_BEG2_input[3]),
+	.S0 (ConfigBits[178+0]),
+	.S0N (ConfigBits_N[178+0]),
+	.S1 (ConfigBits[178+1]),
+	.S1N (ConfigBits_N[178+1]),
+	.X (J2MID_GHa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG3 		MUX-4
+	assign J2MID_GHa_BEG3_input = {JW2END6,W2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG3 (
+	.A0 (J2MID_GHa_BEG3_input[0]),
+	.A1 (J2MID_GHa_BEG3_input[1]),
+	.A2 (J2MID_GHa_BEG3_input[2]),
+	.A3 (J2MID_GHa_BEG3_input[3]),
+	.S0 (ConfigBits[180+0]),
+	.S0N (ConfigBits_N[180+0]),
+	.S1 (ConfigBits[180+1]),
+	.S1N (ConfigBits_N[180+1]),
+	.X (J2MID_GHa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG0 		MUX-4
+	assign J2MID_ABb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG0 (
+	.A0 (J2MID_ABb_BEG0_input[0]),
+	.A1 (J2MID_ABb_BEG0_input[1]),
+	.A2 (J2MID_ABb_BEG0_input[2]),
+	.A3 (J2MID_ABb_BEG0_input[3]),
+	.S0 (ConfigBits[182+0]),
+	.S0N (ConfigBits_N[182+0]),
+	.S1 (ConfigBits[182+1]),
+	.S1N (ConfigBits_N[182+1]),
+	.X (J2MID_ABb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG1 		MUX-4
+	assign J2MID_ABb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG1 (
+	.A0 (J2MID_ABb_BEG1_input[0]),
+	.A1 (J2MID_ABb_BEG1_input[1]),
+	.A2 (J2MID_ABb_BEG1_input[2]),
+	.A3 (J2MID_ABb_BEG1_input[3]),
+	.S0 (ConfigBits[184+0]),
+	.S0N (ConfigBits_N[184+0]),
+	.S1 (ConfigBits[184+1]),
+	.S1N (ConfigBits_N[184+1]),
+	.X (J2MID_ABb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG2 		MUX-4
+	assign J2MID_ABb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG2 (
+	.A0 (J2MID_ABb_BEG2_input[0]),
+	.A1 (J2MID_ABb_BEG2_input[1]),
+	.A2 (J2MID_ABb_BEG2_input[2]),
+	.A3 (J2MID_ABb_BEG2_input[3]),
+	.S0 (ConfigBits[186+0]),
+	.S0N (ConfigBits_N[186+0]),
+	.S1 (ConfigBits[186+1]),
+	.S1N (ConfigBits_N[186+1]),
+	.X (J2MID_ABb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG3 		MUX-4
+	assign J2MID_ABb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG3 (
+	.A0 (J2MID_ABb_BEG3_input[0]),
+	.A1 (J2MID_ABb_BEG3_input[1]),
+	.A2 (J2MID_ABb_BEG3_input[2]),
+	.A3 (J2MID_ABb_BEG3_input[3]),
+	.S0 (ConfigBits[188+0]),
+	.S0N (ConfigBits_N[188+0]),
+	.S1 (ConfigBits[188+1]),
+	.S1N (ConfigBits_N[188+1]),
+	.X (J2MID_ABb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG0 		MUX-4
+	assign J2MID_CDb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG0 (
+	.A0 (J2MID_CDb_BEG0_input[0]),
+	.A1 (J2MID_CDb_BEG0_input[1]),
+	.A2 (J2MID_CDb_BEG0_input[2]),
+	.A3 (J2MID_CDb_BEG0_input[3]),
+	.S0 (ConfigBits[190+0]),
+	.S0N (ConfigBits_N[190+0]),
+	.S1 (ConfigBits[190+1]),
+	.S1N (ConfigBits_N[190+1]),
+	.X (J2MID_CDb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG1 		MUX-4
+	assign J2MID_CDb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG1 (
+	.A0 (J2MID_CDb_BEG1_input[0]),
+	.A1 (J2MID_CDb_BEG1_input[1]),
+	.A2 (J2MID_CDb_BEG1_input[2]),
+	.A3 (J2MID_CDb_BEG1_input[3]),
+	.S0 (ConfigBits[192+0]),
+	.S0N (ConfigBits_N[192+0]),
+	.S1 (ConfigBits[192+1]),
+	.S1N (ConfigBits_N[192+1]),
+	.X (J2MID_CDb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG2 		MUX-4
+	assign J2MID_CDb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG2 (
+	.A0 (J2MID_CDb_BEG2_input[0]),
+	.A1 (J2MID_CDb_BEG2_input[1]),
+	.A2 (J2MID_CDb_BEG2_input[2]),
+	.A3 (J2MID_CDb_BEG2_input[3]),
+	.S0 (ConfigBits[194+0]),
+	.S0N (ConfigBits_N[194+0]),
+	.S1 (ConfigBits[194+1]),
+	.S1N (ConfigBits_N[194+1]),
+	.X (J2MID_CDb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG3 		MUX-4
+	assign J2MID_CDb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG3 (
+	.A0 (J2MID_CDb_BEG3_input[0]),
+	.A1 (J2MID_CDb_BEG3_input[1]),
+	.A2 (J2MID_CDb_BEG3_input[2]),
+	.A3 (J2MID_CDb_BEG3_input[3]),
+	.S0 (ConfigBits[196+0]),
+	.S0N (ConfigBits_N[196+0]),
+	.S1 (ConfigBits[196+1]),
+	.S1N (ConfigBits_N[196+1]),
+	.X (J2MID_CDb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG0 		MUX-4
+	assign J2MID_EFb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG0 (
+	.A0 (J2MID_EFb_BEG0_input[0]),
+	.A1 (J2MID_EFb_BEG0_input[1]),
+	.A2 (J2MID_EFb_BEG0_input[2]),
+	.A3 (J2MID_EFb_BEG0_input[3]),
+	.S0 (ConfigBits[198+0]),
+	.S0N (ConfigBits_N[198+0]),
+	.S1 (ConfigBits[198+1]),
+	.S1N (ConfigBits_N[198+1]),
+	.X (J2MID_EFb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG1 		MUX-4
+	assign J2MID_EFb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG1 (
+	.A0 (J2MID_EFb_BEG1_input[0]),
+	.A1 (J2MID_EFb_BEG1_input[1]),
+	.A2 (J2MID_EFb_BEG1_input[2]),
+	.A3 (J2MID_EFb_BEG1_input[3]),
+	.S0 (ConfigBits[200+0]),
+	.S0N (ConfigBits_N[200+0]),
+	.S1 (ConfigBits[200+1]),
+	.S1N (ConfigBits_N[200+1]),
+	.X (J2MID_EFb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG2 		MUX-4
+	assign J2MID_EFb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG2 (
+	.A0 (J2MID_EFb_BEG2_input[0]),
+	.A1 (J2MID_EFb_BEG2_input[1]),
+	.A2 (J2MID_EFb_BEG2_input[2]),
+	.A3 (J2MID_EFb_BEG2_input[3]),
+	.S0 (ConfigBits[202+0]),
+	.S0N (ConfigBits_N[202+0]),
+	.S1 (ConfigBits[202+1]),
+	.S1N (ConfigBits_N[202+1]),
+	.X (J2MID_EFb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG3 		MUX-4
+	assign J2MID_EFb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG3 (
+	.A0 (J2MID_EFb_BEG3_input[0]),
+	.A1 (J2MID_EFb_BEG3_input[1]),
+	.A2 (J2MID_EFb_BEG3_input[2]),
+	.A3 (J2MID_EFb_BEG3_input[3]),
+	.S0 (ConfigBits[204+0]),
+	.S0N (ConfigBits_N[204+0]),
+	.S1 (ConfigBits[204+1]),
+	.S1N (ConfigBits_N[204+1]),
+	.X (J2MID_EFb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG0 		MUX-4
+	assign J2MID_GHb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG0 (
+	.A0 (J2MID_GHb_BEG0_input[0]),
+	.A1 (J2MID_GHb_BEG0_input[1]),
+	.A2 (J2MID_GHb_BEG0_input[2]),
+	.A3 (J2MID_GHb_BEG0_input[3]),
+	.S0 (ConfigBits[206+0]),
+	.S0N (ConfigBits_N[206+0]),
+	.S1 (ConfigBits[206+1]),
+	.S1N (ConfigBits_N[206+1]),
+	.X (J2MID_GHb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG1 		MUX-4
+	assign J2MID_GHb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG1 (
+	.A0 (J2MID_GHb_BEG1_input[0]),
+	.A1 (J2MID_GHb_BEG1_input[1]),
+	.A2 (J2MID_GHb_BEG1_input[2]),
+	.A3 (J2MID_GHb_BEG1_input[3]),
+	.S0 (ConfigBits[208+0]),
+	.S0N (ConfigBits_N[208+0]),
+	.S1 (ConfigBits[208+1]),
+	.S1N (ConfigBits_N[208+1]),
+	.X (J2MID_GHb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG2 		MUX-4
+	assign J2MID_GHb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG2 (
+	.A0 (J2MID_GHb_BEG2_input[0]),
+	.A1 (J2MID_GHb_BEG2_input[1]),
+	.A2 (J2MID_GHb_BEG2_input[2]),
+	.A3 (J2MID_GHb_BEG2_input[3]),
+	.S0 (ConfigBits[210+0]),
+	.S0N (ConfigBits_N[210+0]),
+	.S1 (ConfigBits[210+1]),
+	.S1N (ConfigBits_N[210+1]),
+	.X (J2MID_GHb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG3 		MUX-4
+	assign J2MID_GHb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG3 (
+	.A0 (J2MID_GHb_BEG3_input[0]),
+	.A1 (J2MID_GHb_BEG3_input[1]),
+	.A2 (J2MID_GHb_BEG3_input[2]),
+	.A3 (J2MID_GHb_BEG3_input[3]),
+	.S0 (ConfigBits[212+0]),
+	.S0N (ConfigBits_N[212+0]),
+	.S1 (ConfigBits[212+1]),
+	.S1N (ConfigBits_N[212+1]),
+	.X (J2MID_GHb_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG0 		MUX-4
+	assign J2END_AB_BEG0_input = {W2END6,SS4END3,E2END6,N2END6};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG0 (
+	.A0 (J2END_AB_BEG0_input[0]),
+	.A1 (J2END_AB_BEG0_input[1]),
+	.A2 (J2END_AB_BEG0_input[2]),
+	.A3 (J2END_AB_BEG0_input[3]),
+	.S0 (ConfigBits[214+0]),
+	.S0N (ConfigBits_N[214+0]),
+	.S1 (ConfigBits[214+1]),
+	.S1N (ConfigBits_N[214+1]),
+	.X (J2END_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG1 		MUX-4
+	assign J2END_AB_BEG1_input = {W2END2,S2END2,E2END2,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG1 (
+	.A0 (J2END_AB_BEG1_input[0]),
+	.A1 (J2END_AB_BEG1_input[1]),
+	.A2 (J2END_AB_BEG1_input[2]),
+	.A3 (J2END_AB_BEG1_input[3]),
+	.S0 (ConfigBits[216+0]),
+	.S0N (ConfigBits_N[216+0]),
+	.S1 (ConfigBits[216+1]),
+	.S1N (ConfigBits_N[216+1]),
+	.X (J2END_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG2 		MUX-4
+	assign J2END_AB_BEG2_input = {W2END4,S2END4,EE4END0,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG2 (
+	.A0 (J2END_AB_BEG2_input[0]),
+	.A1 (J2END_AB_BEG2_input[1]),
+	.A2 (J2END_AB_BEG2_input[2]),
+	.A3 (J2END_AB_BEG2_input[3]),
+	.S0 (ConfigBits[218+0]),
+	.S0N (ConfigBits_N[218+0]),
+	.S1 (ConfigBits[218+1]),
+	.S1N (ConfigBits_N[218+1]),
+	.X (J2END_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG3 		MUX-4
+	assign J2END_AB_BEG3_input = {WW4END3,S2END0,E2END0,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG3 (
+	.A0 (J2END_AB_BEG3_input[0]),
+	.A1 (J2END_AB_BEG3_input[1]),
+	.A2 (J2END_AB_BEG3_input[2]),
+	.A3 (J2END_AB_BEG3_input[3]),
+	.S0 (ConfigBits[220+0]),
+	.S0N (ConfigBits_N[220+0]),
+	.S1 (ConfigBits[220+1]),
+	.S1N (ConfigBits_N[220+1]),
+	.X (J2END_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG0 		MUX-4
+	assign J2END_CD_BEG0_input = {W2END6,S2END6,E2END6,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG0 (
+	.A0 (J2END_CD_BEG0_input[0]),
+	.A1 (J2END_CD_BEG0_input[1]),
+	.A2 (J2END_CD_BEG0_input[2]),
+	.A3 (J2END_CD_BEG0_input[3]),
+	.S0 (ConfigBits[222+0]),
+	.S0N (ConfigBits_N[222+0]),
+	.S1 (ConfigBits[222+1]),
+	.S1N (ConfigBits_N[222+1]),
+	.X (J2END_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG1 		MUX-4
+	assign J2END_CD_BEG1_input = {WW4END2,S2END2,E2END2,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG1 (
+	.A0 (J2END_CD_BEG1_input[0]),
+	.A1 (J2END_CD_BEG1_input[1]),
+	.A2 (J2END_CD_BEG1_input[2]),
+	.A3 (J2END_CD_BEG1_input[3]),
+	.S0 (ConfigBits[224+0]),
+	.S0N (ConfigBits_N[224+0]),
+	.S1 (ConfigBits[224+1]),
+	.S1N (ConfigBits_N[224+1]),
+	.X (J2END_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG2 		MUX-4
+	assign J2END_CD_BEG2_input = {W2END4,SS4END2,E2END4,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG2 (
+	.A0 (J2END_CD_BEG2_input[0]),
+	.A1 (J2END_CD_BEG2_input[1]),
+	.A2 (J2END_CD_BEG2_input[2]),
+	.A3 (J2END_CD_BEG2_input[3]),
+	.S0 (ConfigBits[226+0]),
+	.S0N (ConfigBits_N[226+0]),
+	.S1 (ConfigBits[226+1]),
+	.S1N (ConfigBits_N[226+1]),
+	.X (J2END_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG3 		MUX-4
+	assign J2END_CD_BEG3_input = {W2END0,S2END0,EE4END1,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG3 (
+	.A0 (J2END_CD_BEG3_input[0]),
+	.A1 (J2END_CD_BEG3_input[1]),
+	.A2 (J2END_CD_BEG3_input[2]),
+	.A3 (J2END_CD_BEG3_input[3]),
+	.S0 (ConfigBits[228+0]),
+	.S0N (ConfigBits_N[228+0]),
+	.S1 (ConfigBits[228+1]),
+	.S1N (ConfigBits_N[228+1]),
+	.X (J2END_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG0 		MUX-4
+	assign J2END_EF_BEG0_input = {W2END7,S2END7,EE4END2,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG0 (
+	.A0 (J2END_EF_BEG0_input[0]),
+	.A1 (J2END_EF_BEG0_input[1]),
+	.A2 (J2END_EF_BEG0_input[2]),
+	.A3 (J2END_EF_BEG0_input[3]),
+	.S0 (ConfigBits[230+0]),
+	.S0N (ConfigBits_N[230+0]),
+	.S1 (ConfigBits[230+1]),
+	.S1N (ConfigBits_N[230+1]),
+	.X (J2END_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG1 		MUX-4
+	assign J2END_EF_BEG1_input = {WW4END1,S2END3,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG1 (
+	.A0 (J2END_EF_BEG1_input[0]),
+	.A1 (J2END_EF_BEG1_input[1]),
+	.A2 (J2END_EF_BEG1_input[2]),
+	.A3 (J2END_EF_BEG1_input[3]),
+	.S0 (ConfigBits[232+0]),
+	.S0N (ConfigBits_N[232+0]),
+	.S1 (ConfigBits[232+1]),
+	.S1N (ConfigBits_N[232+1]),
+	.X (J2END_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG2 		MUX-4
+	assign J2END_EF_BEG2_input = {W2END5,SS4END1,E2END5,N2END5};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG2 (
+	.A0 (J2END_EF_BEG2_input[0]),
+	.A1 (J2END_EF_BEG2_input[1]),
+	.A2 (J2END_EF_BEG2_input[2]),
+	.A3 (J2END_EF_BEG2_input[3]),
+	.S0 (ConfigBits[234+0]),
+	.S0N (ConfigBits_N[234+0]),
+	.S1 (ConfigBits[234+1]),
+	.S1N (ConfigBits_N[234+1]),
+	.X (J2END_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG3 		MUX-4
+	assign J2END_EF_BEG3_input = {W2END1,S2END1,E2END1,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG3 (
+	.A0 (J2END_EF_BEG3_input[0]),
+	.A1 (J2END_EF_BEG3_input[1]),
+	.A2 (J2END_EF_BEG3_input[2]),
+	.A3 (J2END_EF_BEG3_input[3]),
+	.S0 (ConfigBits[236+0]),
+	.S0N (ConfigBits_N[236+0]),
+	.S1 (ConfigBits[236+1]),
+	.S1N (ConfigBits_N[236+1]),
+	.X (J2END_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG0 		MUX-4
+	assign J2END_GH_BEG0_input = {WW4END0,S2END7,E2END7,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG0 (
+	.A0 (J2END_GH_BEG0_input[0]),
+	.A1 (J2END_GH_BEG0_input[1]),
+	.A2 (J2END_GH_BEG0_input[2]),
+	.A3 (J2END_GH_BEG0_input[3]),
+	.S0 (ConfigBits[238+0]),
+	.S0N (ConfigBits_N[238+0]),
+	.S1 (ConfigBits[238+1]),
+	.S1N (ConfigBits_N[238+1]),
+	.X (J2END_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG1 		MUX-4
+	assign J2END_GH_BEG1_input = {W2END3,SS4END0,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG1 (
+	.A0 (J2END_GH_BEG1_input[0]),
+	.A1 (J2END_GH_BEG1_input[1]),
+	.A2 (J2END_GH_BEG1_input[2]),
+	.A3 (J2END_GH_BEG1_input[3]),
+	.S0 (ConfigBits[240+0]),
+	.S0N (ConfigBits_N[240+0]),
+	.S1 (ConfigBits[240+1]),
+	.S1N (ConfigBits_N[240+1]),
+	.X (J2END_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG2 		MUX-4
+	assign J2END_GH_BEG2_input = {W2END5,S2END5,E2END5,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG2 (
+	.A0 (J2END_GH_BEG2_input[0]),
+	.A1 (J2END_GH_BEG2_input[1]),
+	.A2 (J2END_GH_BEG2_input[2]),
+	.A3 (J2END_GH_BEG2_input[3]),
+	.S0 (ConfigBits[242+0]),
+	.S0N (ConfigBits_N[242+0]),
+	.S1 (ConfigBits[242+1]),
+	.S1N (ConfigBits_N[242+1]),
+	.X (J2END_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG3 		MUX-4
+	assign J2END_GH_BEG3_input = {W2END1,S2END1,EE4END3,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG3 (
+	.A0 (J2END_GH_BEG3_input[0]),
+	.A1 (J2END_GH_BEG3_input[1]),
+	.A2 (J2END_GH_BEG3_input[2]),
+	.A3 (J2END_GH_BEG3_input[3]),
+	.S0 (ConfigBits[244+0]),
+	.S0N (ConfigBits_N[244+0]),
+	.S1 (ConfigBits[244+1]),
+	.S1N (ConfigBits_N[244+1]),
+	.X (J2END_GH_BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG0 		MUX-16
+	assign JN2BEG0_input = {W6END1,W2END1,SS4END1,E6END1,E2END1,E1END3,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,N4END1,N2END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG0 (
+	.A0 (JN2BEG0_input[0]),
+	.A1 (JN2BEG0_input[1]),
+	.A2 (JN2BEG0_input[2]),
+	.A3 (JN2BEG0_input[3]),
+	.A4 (JN2BEG0_input[4]),
+	.A5 (JN2BEG0_input[5]),
+	.A6 (JN2BEG0_input[6]),
+	.A7 (JN2BEG0_input[7]),
+	.A8 (JN2BEG0_input[8]),
+	.A9 (JN2BEG0_input[9]),
+	.A10 (JN2BEG0_input[10]),
+	.A11 (JN2BEG0_input[11]),
+	.A12 (JN2BEG0_input[12]),
+	.A13 (JN2BEG0_input[13]),
+	.A14 (JN2BEG0_input[14]),
+	.A15 (JN2BEG0_input[15]),
+	.S0 (ConfigBits[246+0]),
+	.S0N (ConfigBits_N[246+0]),
+	.S1 (ConfigBits[246+1]),
+	.S1N (ConfigBits_N[246+1]),
+	.S2 (ConfigBits[246+2]),
+	.S2N (ConfigBits_N[246+2]),
+	.S3 (ConfigBits[246+3]),
+	.S3N (ConfigBits_N[246+3]),
+	.X (JN2BEG0)
+	);
+
+// switch matrix multiplexer  JN2BEG1 		MUX-16
+	assign JN2BEG1_input = {W6END0,W2END2,S2END2,E6END0,E2END2,E1END0,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top0,N4END2,N2END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG1 (
+	.A0 (JN2BEG1_input[0]),
+	.A1 (JN2BEG1_input[1]),
+	.A2 (JN2BEG1_input[2]),
+	.A3 (JN2BEG1_input[3]),
+	.A4 (JN2BEG1_input[4]),
+	.A5 (JN2BEG1_input[5]),
+	.A6 (JN2BEG1_input[6]),
+	.A7 (JN2BEG1_input[7]),
+	.A8 (JN2BEG1_input[8]),
+	.A9 (JN2BEG1_input[9]),
+	.A10 (JN2BEG1_input[10]),
+	.A11 (JN2BEG1_input[11]),
+	.A12 (JN2BEG1_input[12]),
+	.A13 (JN2BEG1_input[13]),
+	.A14 (JN2BEG1_input[14]),
+	.A15 (JN2BEG1_input[15]),
+	.S0 (ConfigBits[250+0]),
+	.S0N (ConfigBits_N[250+0]),
+	.S1 (ConfigBits[250+1]),
+	.S1N (ConfigBits_N[250+1]),
+	.S2 (ConfigBits[250+2]),
+	.S2N (ConfigBits_N[250+2]),
+	.S3 (ConfigBits[250+3]),
+	.S3N (ConfigBits_N[250+3]),
+	.X (JN2BEG1)
+	);
+
+// switch matrix multiplexer  JN2BEG2 		MUX-16
+	assign JN2BEG2_input = {WW4END1,W2END3,S2END3,E6END1,E2END3,E1END1,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top1,bot2top0,N4END3,N2END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG2 (
+	.A0 (JN2BEG2_input[0]),
+	.A1 (JN2BEG2_input[1]),
+	.A2 (JN2BEG2_input[2]),
+	.A3 (JN2BEG2_input[3]),
+	.A4 (JN2BEG2_input[4]),
+	.A5 (JN2BEG2_input[5]),
+	.A6 (JN2BEG2_input[6]),
+	.A7 (JN2BEG2_input[7]),
+	.A8 (JN2BEG2_input[8]),
+	.A9 (JN2BEG2_input[9]),
+	.A10 (JN2BEG2_input[10]),
+	.A11 (JN2BEG2_input[11]),
+	.A12 (JN2BEG2_input[12]),
+	.A13 (JN2BEG2_input[13]),
+	.A14 (JN2BEG2_input[14]),
+	.A15 (JN2BEG2_input[15]),
+	.S0 (ConfigBits[254+0]),
+	.S0N (ConfigBits_N[254+0]),
+	.S1 (ConfigBits[254+1]),
+	.S1N (ConfigBits_N[254+1]),
+	.S2 (ConfigBits[254+2]),
+	.S2N (ConfigBits_N[254+2]),
+	.S3 (ConfigBits[254+3]),
+	.S3N (ConfigBits_N[254+3]),
+	.X (JN2BEG2)
+	);
+
+// switch matrix multiplexer  JN2BEG3 		MUX-16
+	assign JN2BEG3_input = {W6END0,W2END4,S2END4,E6END0,E2END4,E1END2,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top2,bot2top1,bot2top0,N4END0,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG3 (
+	.A0 (JN2BEG3_input[0]),
+	.A1 (JN2BEG3_input[1]),
+	.A2 (JN2BEG3_input[2]),
+	.A3 (JN2BEG3_input[3]),
+	.A4 (JN2BEG3_input[4]),
+	.A5 (JN2BEG3_input[5]),
+	.A6 (JN2BEG3_input[6]),
+	.A7 (JN2BEG3_input[7]),
+	.A8 (JN2BEG3_input[8]),
+	.A9 (JN2BEG3_input[9]),
+	.A10 (JN2BEG3_input[10]),
+	.A11 (JN2BEG3_input[11]),
+	.A12 (JN2BEG3_input[12]),
+	.A13 (JN2BEG3_input[13]),
+	.A14 (JN2BEG3_input[14]),
+	.A15 (JN2BEG3_input[15]),
+	.S0 (ConfigBits[258+0]),
+	.S0N (ConfigBits_N[258+0]),
+	.S1 (ConfigBits[258+1]),
+	.S1N (ConfigBits_N[258+1]),
+	.S2 (ConfigBits[258+2]),
+	.S2N (ConfigBits_N[258+2]),
+	.S3 (ConfigBits[258+3]),
+	.S3N (ConfigBits_N[258+3]),
+	.X (JN2BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG4 		MUX-16
+	assign JN2BEG4_input = {W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,bot2top9,bot2top7,bot2top6,bot2top5,bot2top3,bot2top2,bot2top1,bot2top0,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG4 (
+	.A0 (JN2BEG4_input[0]),
+	.A1 (JN2BEG4_input[1]),
+	.A2 (JN2BEG4_input[2]),
+	.A3 (JN2BEG4_input[3]),
+	.A4 (JN2BEG4_input[4]),
+	.A5 (JN2BEG4_input[5]),
+	.A6 (JN2BEG4_input[6]),
+	.A7 (JN2BEG4_input[7]),
+	.A8 (JN2BEG4_input[8]),
+	.A9 (JN2BEG4_input[9]),
+	.A10 (JN2BEG4_input[10]),
+	.A11 (JN2BEG4_input[11]),
+	.A12 (JN2BEG4_input[12]),
+	.A13 (JN2BEG4_input[13]),
+	.A14 (JN2BEG4_input[14]),
+	.A15 (JN2BEG4_input[15]),
+	.S0 (ConfigBits[262+0]),
+	.S0N (ConfigBits_N[262+0]),
+	.S1 (ConfigBits[262+1]),
+	.S1N (ConfigBits_N[262+1]),
+	.S2 (ConfigBits[262+2]),
+	.S2N (ConfigBits_N[262+2]),
+	.S3 (ConfigBits[262+3]),
+	.S3N (ConfigBits_N[262+3]),
+	.X (JN2BEG4)
+	);
+
+// switch matrix multiplexer  JN2BEG5 		MUX-16
+	assign JN2BEG5_input = {W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,bot2top8,bot2top7,bot2top6,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG5 (
+	.A0 (JN2BEG5_input[0]),
+	.A1 (JN2BEG5_input[1]),
+	.A2 (JN2BEG5_input[2]),
+	.A3 (JN2BEG5_input[3]),
+	.A4 (JN2BEG5_input[4]),
+	.A5 (JN2BEG5_input[5]),
+	.A6 (JN2BEG5_input[6]),
+	.A7 (JN2BEG5_input[7]),
+	.A8 (JN2BEG5_input[8]),
+	.A9 (JN2BEG5_input[9]),
+	.A10 (JN2BEG5_input[10]),
+	.A11 (JN2BEG5_input[11]),
+	.A12 (JN2BEG5_input[12]),
+	.A13 (JN2BEG5_input[13]),
+	.A14 (JN2BEG5_input[14]),
+	.A15 (JN2BEG5_input[15]),
+	.S0 (ConfigBits[266+0]),
+	.S0N (ConfigBits_N[266+0]),
+	.S1 (ConfigBits[266+1]),
+	.S1N (ConfigBits_N[266+1]),
+	.S2 (ConfigBits[266+2]),
+	.S2N (ConfigBits_N[266+2]),
+	.S3 (ConfigBits[266+3]),
+	.S3N (ConfigBits_N[266+3]),
+	.X (JN2BEG5)
+	);
+
+// switch matrix multiplexer  JN2BEG6 		MUX-16
+	assign JN2BEG6_input = {W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,bot2top9,bot2top7,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG6 (
+	.A0 (JN2BEG6_input[0]),
+	.A1 (JN2BEG6_input[1]),
+	.A2 (JN2BEG6_input[2]),
+	.A3 (JN2BEG6_input[3]),
+	.A4 (JN2BEG6_input[4]),
+	.A5 (JN2BEG6_input[5]),
+	.A6 (JN2BEG6_input[6]),
+	.A7 (JN2BEG6_input[7]),
+	.A8 (JN2BEG6_input[8]),
+	.A9 (JN2BEG6_input[9]),
+	.A10 (JN2BEG6_input[10]),
+	.A11 (JN2BEG6_input[11]),
+	.A12 (JN2BEG6_input[12]),
+	.A13 (JN2BEG6_input[13]),
+	.A14 (JN2BEG6_input[14]),
+	.A15 (JN2BEG6_input[15]),
+	.S0 (ConfigBits[270+0]),
+	.S0N (ConfigBits_N[270+0]),
+	.S1 (ConfigBits[270+1]),
+	.S1N (ConfigBits_N[270+1]),
+	.S2 (ConfigBits[270+2]),
+	.S2N (ConfigBits_N[270+2]),
+	.S3 (ConfigBits[270+3]),
+	.S3N (ConfigBits_N[270+3]),
+	.X (JN2BEG6)
+	);
+
+// switch matrix multiplexer  JN2BEG7 		MUX-16
+	assign JN2BEG7_input = {W1END2,W1END0,S2END0,S1END0,EE4END0,E1END0,bot2top8,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG7 (
+	.A0 (JN2BEG7_input[0]),
+	.A1 (JN2BEG7_input[1]),
+	.A2 (JN2BEG7_input[2]),
+	.A3 (JN2BEG7_input[3]),
+	.A4 (JN2BEG7_input[4]),
+	.A5 (JN2BEG7_input[5]),
+	.A6 (JN2BEG7_input[6]),
+	.A7 (JN2BEG7_input[7]),
+	.A8 (JN2BEG7_input[8]),
+	.A9 (JN2BEG7_input[9]),
+	.A10 (JN2BEG7_input[10]),
+	.A11 (JN2BEG7_input[11]),
+	.A12 (JN2BEG7_input[12]),
+	.A13 (JN2BEG7_input[13]),
+	.A14 (JN2BEG7_input[14]),
+	.A15 (JN2BEG7_input[15]),
+	.S0 (ConfigBits[274+0]),
+	.S0N (ConfigBits_N[274+0]),
+	.S1 (ConfigBits[274+1]),
+	.S1N (ConfigBits_N[274+1]),
+	.S2 (ConfigBits[274+2]),
+	.S2N (ConfigBits_N[274+2]),
+	.S3 (ConfigBits[274+3]),
+	.S3N (ConfigBits_N[274+3]),
+	.X (JN2BEG7)
+	);
+
+// switch matrix multiplexer  JE2BEG0 		MUX-16
+	assign JE2BEG0_input = {W6END1,W2END1,S2END1,E6END1,EE4END1,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,N4END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG0 (
+	.A0 (JE2BEG0_input[0]),
+	.A1 (JE2BEG0_input[1]),
+	.A2 (JE2BEG0_input[2]),
+	.A3 (JE2BEG0_input[3]),
+	.A4 (JE2BEG0_input[4]),
+	.A5 (JE2BEG0_input[5]),
+	.A6 (JE2BEG0_input[6]),
+	.A7 (JE2BEG0_input[7]),
+	.A8 (JE2BEG0_input[8]),
+	.A9 (JE2BEG0_input[9]),
+	.A10 (JE2BEG0_input[10]),
+	.A11 (JE2BEG0_input[11]),
+	.A12 (JE2BEG0_input[12]),
+	.A13 (JE2BEG0_input[13]),
+	.A14 (JE2BEG0_input[14]),
+	.A15 (JE2BEG0_input[15]),
+	.S0 (ConfigBits[278+0]),
+	.S0N (ConfigBits_N[278+0]),
+	.S1 (ConfigBits[278+1]),
+	.S1N (ConfigBits_N[278+1]),
+	.S2 (ConfigBits[278+2]),
+	.S2N (ConfigBits_N[278+2]),
+	.S3 (ConfigBits[278+3]),
+	.S3N (ConfigBits_N[278+3]),
+	.X (JE2BEG0)
+	);
+
+// switch matrix multiplexer  JE2BEG1 		MUX-16
+	assign JE2BEG1_input = {WW4END3,W2END2,S2END2,E6END0,E2END2,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top0,N4END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG1 (
+	.A0 (JE2BEG1_input[0]),
+	.A1 (JE2BEG1_input[1]),
+	.A2 (JE2BEG1_input[2]),
+	.A3 (JE2BEG1_input[3]),
+	.A4 (JE2BEG1_input[4]),
+	.A5 (JE2BEG1_input[5]),
+	.A6 (JE2BEG1_input[6]),
+	.A7 (JE2BEG1_input[7]),
+	.A8 (JE2BEG1_input[8]),
+	.A9 (JE2BEG1_input[9]),
+	.A10 (JE2BEG1_input[10]),
+	.A11 (JE2BEG1_input[11]),
+	.A12 (JE2BEG1_input[12]),
+	.A13 (JE2BEG1_input[13]),
+	.A14 (JE2BEG1_input[14]),
+	.A15 (JE2BEG1_input[15]),
+	.S0 (ConfigBits[282+0]),
+	.S0N (ConfigBits_N[282+0]),
+	.S1 (ConfigBits[282+1]),
+	.S1N (ConfigBits_N[282+1]),
+	.S2 (ConfigBits[282+2]),
+	.S2N (ConfigBits_N[282+2]),
+	.S3 (ConfigBits[282+3]),
+	.S3N (ConfigBits_N[282+3]),
+	.X (JE2BEG1)
+	);
+
+// switch matrix multiplexer  JE2BEG2 		MUX-16
+	assign JE2BEG2_input = {W6END1,W2END3,S2END3,E6END1,E2END3,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top1,bot2top0,N4END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG2 (
+	.A0 (JE2BEG2_input[0]),
+	.A1 (JE2BEG2_input[1]),
+	.A2 (JE2BEG2_input[2]),
+	.A3 (JE2BEG2_input[3]),
+	.A4 (JE2BEG2_input[4]),
+	.A5 (JE2BEG2_input[5]),
+	.A6 (JE2BEG2_input[6]),
+	.A7 (JE2BEG2_input[7]),
+	.A8 (JE2BEG2_input[8]),
+	.A9 (JE2BEG2_input[9]),
+	.A10 (JE2BEG2_input[10]),
+	.A11 (JE2BEG2_input[11]),
+	.A12 (JE2BEG2_input[12]),
+	.A13 (JE2BEG2_input[13]),
+	.A14 (JE2BEG2_input[14]),
+	.A15 (JE2BEG2_input[15]),
+	.S0 (ConfigBits[286+0]),
+	.S0N (ConfigBits_N[286+0]),
+	.S1 (ConfigBits[286+1]),
+	.S1N (ConfigBits_N[286+1]),
+	.S2 (ConfigBits[286+2]),
+	.S2N (ConfigBits_N[286+2]),
+	.S3 (ConfigBits[286+3]),
+	.S3N (ConfigBits_N[286+3]),
+	.X (JE2BEG2)
+	);
+
+// switch matrix multiplexer  JE2BEG3 		MUX-16
+	assign JE2BEG3_input = {W6END0,W2END4,S2END4,E6END0,E2END4,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top2,bot2top1,bot2top0,N4END0,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG3 (
+	.A0 (JE2BEG3_input[0]),
+	.A1 (JE2BEG3_input[1]),
+	.A2 (JE2BEG3_input[2]),
+	.A3 (JE2BEG3_input[3]),
+	.A4 (JE2BEG3_input[4]),
+	.A5 (JE2BEG3_input[5]),
+	.A6 (JE2BEG3_input[6]),
+	.A7 (JE2BEG3_input[7]),
+	.A8 (JE2BEG3_input[8]),
+	.A9 (JE2BEG3_input[9]),
+	.A10 (JE2BEG3_input[10]),
+	.A11 (JE2BEG3_input[11]),
+	.A12 (JE2BEG3_input[12]),
+	.A13 (JE2BEG3_input[13]),
+	.A14 (JE2BEG3_input[14]),
+	.A15 (JE2BEG3_input[15]),
+	.S0 (ConfigBits[290+0]),
+	.S0N (ConfigBits_N[290+0]),
+	.S1 (ConfigBits[290+1]),
+	.S1N (ConfigBits_N[290+1]),
+	.S2 (ConfigBits[290+2]),
+	.S2N (ConfigBits_N[290+2]),
+	.S3 (ConfigBits[290+3]),
+	.S3N (ConfigBits_N[290+3]),
+	.X (JE2BEG3)
+	);
+
+// switch matrix multiplexer  JE2BEG4 		MUX-16
+	assign JE2BEG4_input = {W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,bot2top8,bot2top7,bot2top6,bot2top5,bot2top3,bot2top2,bot2top1,bot2top0,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG4 (
+	.A0 (JE2BEG4_input[0]),
+	.A1 (JE2BEG4_input[1]),
+	.A2 (JE2BEG4_input[2]),
+	.A3 (JE2BEG4_input[3]),
+	.A4 (JE2BEG4_input[4]),
+	.A5 (JE2BEG4_input[5]),
+	.A6 (JE2BEG4_input[6]),
+	.A7 (JE2BEG4_input[7]),
+	.A8 (JE2BEG4_input[8]),
+	.A9 (JE2BEG4_input[9]),
+	.A10 (JE2BEG4_input[10]),
+	.A11 (JE2BEG4_input[11]),
+	.A12 (JE2BEG4_input[12]),
+	.A13 (JE2BEG4_input[13]),
+	.A14 (JE2BEG4_input[14]),
+	.A15 (JE2BEG4_input[15]),
+	.S0 (ConfigBits[294+0]),
+	.S0N (ConfigBits_N[294+0]),
+	.S1 (ConfigBits[294+1]),
+	.S1N (ConfigBits_N[294+1]),
+	.S2 (ConfigBits[294+2]),
+	.S2N (ConfigBits_N[294+2]),
+	.S3 (ConfigBits[294+3]),
+	.S3N (ConfigBits_N[294+3]),
+	.X (JE2BEG4)
+	);
+
+// switch matrix multiplexer  JE2BEG5 		MUX-16
+	assign JE2BEG5_input = {W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,bot2top9,bot2top7,bot2top6,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG5 (
+	.A0 (JE2BEG5_input[0]),
+	.A1 (JE2BEG5_input[1]),
+	.A2 (JE2BEG5_input[2]),
+	.A3 (JE2BEG5_input[3]),
+	.A4 (JE2BEG5_input[4]),
+	.A5 (JE2BEG5_input[5]),
+	.A6 (JE2BEG5_input[6]),
+	.A7 (JE2BEG5_input[7]),
+	.A8 (JE2BEG5_input[8]),
+	.A9 (JE2BEG5_input[9]),
+	.A10 (JE2BEG5_input[10]),
+	.A11 (JE2BEG5_input[11]),
+	.A12 (JE2BEG5_input[12]),
+	.A13 (JE2BEG5_input[13]),
+	.A14 (JE2BEG5_input[14]),
+	.A15 (JE2BEG5_input[15]),
+	.S0 (ConfigBits[298+0]),
+	.S0N (ConfigBits_N[298+0]),
+	.S1 (ConfigBits[298+1]),
+	.S1N (ConfigBits_N[298+1]),
+	.S2 (ConfigBits[298+2]),
+	.S2N (ConfigBits_N[298+2]),
+	.S3 (ConfigBits[298+3]),
+	.S3N (ConfigBits_N[298+3]),
+	.X (JE2BEG5)
+	);
+
+// switch matrix multiplexer  JE2BEG6 		MUX-16
+	assign JE2BEG6_input = {W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,bot2top8,bot2top7,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG6 (
+	.A0 (JE2BEG6_input[0]),
+	.A1 (JE2BEG6_input[1]),
+	.A2 (JE2BEG6_input[2]),
+	.A3 (JE2BEG6_input[3]),
+	.A4 (JE2BEG6_input[4]),
+	.A5 (JE2BEG6_input[5]),
+	.A6 (JE2BEG6_input[6]),
+	.A7 (JE2BEG6_input[7]),
+	.A8 (JE2BEG6_input[8]),
+	.A9 (JE2BEG6_input[9]),
+	.A10 (JE2BEG6_input[10]),
+	.A11 (JE2BEG6_input[11]),
+	.A12 (JE2BEG6_input[12]),
+	.A13 (JE2BEG6_input[13]),
+	.A14 (JE2BEG6_input[14]),
+	.A15 (JE2BEG6_input[15]),
+	.S0 (ConfigBits[302+0]),
+	.S0N (ConfigBits_N[302+0]),
+	.S1 (ConfigBits[302+1]),
+	.S1N (ConfigBits_N[302+1]),
+	.S2 (ConfigBits[302+2]),
+	.S2N (ConfigBits_N[302+2]),
+	.S3 (ConfigBits[302+3]),
+	.S3N (ConfigBits_N[302+3]),
+	.X (JE2BEG6)
+	);
+
+// switch matrix multiplexer  JE2BEG7 		MUX-16
+	assign JE2BEG7_input = {WW4END0,SS4END0,S1END2,S1END0,E2END0,E1END0,bot2top9,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG7 (
+	.A0 (JE2BEG7_input[0]),
+	.A1 (JE2BEG7_input[1]),
+	.A2 (JE2BEG7_input[2]),
+	.A3 (JE2BEG7_input[3]),
+	.A4 (JE2BEG7_input[4]),
+	.A5 (JE2BEG7_input[5]),
+	.A6 (JE2BEG7_input[6]),
+	.A7 (JE2BEG7_input[7]),
+	.A8 (JE2BEG7_input[8]),
+	.A9 (JE2BEG7_input[9]),
+	.A10 (JE2BEG7_input[10]),
+	.A11 (JE2BEG7_input[11]),
+	.A12 (JE2BEG7_input[12]),
+	.A13 (JE2BEG7_input[13]),
+	.A14 (JE2BEG7_input[14]),
+	.A15 (JE2BEG7_input[15]),
+	.S0 (ConfigBits[306+0]),
+	.S0N (ConfigBits_N[306+0]),
+	.S1 (ConfigBits[306+1]),
+	.S1N (ConfigBits_N[306+1]),
+	.S2 (ConfigBits[306+2]),
+	.S2N (ConfigBits_N[306+2]),
+	.S3 (ConfigBits[306+3]),
+	.S3N (ConfigBits_N[306+3]),
+	.X (JE2BEG7)
+	);
+
+// switch matrix multiplexer  JS2BEG0 		MUX-16
+	assign JS2BEG0_input = {W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,E1END3,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,NN4END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG0 (
+	.A0 (JS2BEG0_input[0]),
+	.A1 (JS2BEG0_input[1]),
+	.A2 (JS2BEG0_input[2]),
+	.A3 (JS2BEG0_input[3]),
+	.A4 (JS2BEG0_input[4]),
+	.A5 (JS2BEG0_input[5]),
+	.A6 (JS2BEG0_input[6]),
+	.A7 (JS2BEG0_input[7]),
+	.A8 (JS2BEG0_input[8]),
+	.A9 (JS2BEG0_input[9]),
+	.A10 (JS2BEG0_input[10]),
+	.A11 (JS2BEG0_input[11]),
+	.A12 (JS2BEG0_input[12]),
+	.A13 (JS2BEG0_input[13]),
+	.A14 (JS2BEG0_input[14]),
+	.A15 (JS2BEG0_input[15]),
+	.S0 (ConfigBits[310+0]),
+	.S0N (ConfigBits_N[310+0]),
+	.S1 (ConfigBits[310+1]),
+	.S1N (ConfigBits_N[310+1]),
+	.S2 (ConfigBits[310+2]),
+	.S2N (ConfigBits_N[310+2]),
+	.S3 (ConfigBits[310+3]),
+	.S3N (ConfigBits_N[310+3]),
+	.X (JS2BEG0)
+	);
+
+// switch matrix multiplexer  JS2BEG1 		MUX-16
+	assign JS2BEG1_input = {W6END0,W2END2,SS4END2,S4END2,E6END0,EE4END2,E1END0,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top0,NN4END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG1 (
+	.A0 (JS2BEG1_input[0]),
+	.A1 (JS2BEG1_input[1]),
+	.A2 (JS2BEG1_input[2]),
+	.A3 (JS2BEG1_input[3]),
+	.A4 (JS2BEG1_input[4]),
+	.A5 (JS2BEG1_input[5]),
+	.A6 (JS2BEG1_input[6]),
+	.A7 (JS2BEG1_input[7]),
+	.A8 (JS2BEG1_input[8]),
+	.A9 (JS2BEG1_input[9]),
+	.A10 (JS2BEG1_input[10]),
+	.A11 (JS2BEG1_input[11]),
+	.A12 (JS2BEG1_input[12]),
+	.A13 (JS2BEG1_input[13]),
+	.A14 (JS2BEG1_input[14]),
+	.A15 (JS2BEG1_input[15]),
+	.S0 (ConfigBits[314+0]),
+	.S0N (ConfigBits_N[314+0]),
+	.S1 (ConfigBits[314+1]),
+	.S1N (ConfigBits_N[314+1]),
+	.S2 (ConfigBits[314+2]),
+	.S2N (ConfigBits_N[314+2]),
+	.S3 (ConfigBits[314+3]),
+	.S3N (ConfigBits_N[314+3]),
+	.X (JS2BEG1)
+	);
+
+// switch matrix multiplexer  JS2BEG2 		MUX-16
+	assign JS2BEG2_input = {W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,E1END1,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top1,bot2top0,NN4END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG2 (
+	.A0 (JS2BEG2_input[0]),
+	.A1 (JS2BEG2_input[1]),
+	.A2 (JS2BEG2_input[2]),
+	.A3 (JS2BEG2_input[3]),
+	.A4 (JS2BEG2_input[4]),
+	.A5 (JS2BEG2_input[5]),
+	.A6 (JS2BEG2_input[6]),
+	.A7 (JS2BEG2_input[7]),
+	.A8 (JS2BEG2_input[8]),
+	.A9 (JS2BEG2_input[9]),
+	.A10 (JS2BEG2_input[10]),
+	.A11 (JS2BEG2_input[11]),
+	.A12 (JS2BEG2_input[12]),
+	.A13 (JS2BEG2_input[13]),
+	.A14 (JS2BEG2_input[14]),
+	.A15 (JS2BEG2_input[15]),
+	.S0 (ConfigBits[318+0]),
+	.S0N (ConfigBits_N[318+0]),
+	.S1 (ConfigBits[318+1]),
+	.S1N (ConfigBits_N[318+1]),
+	.S2 (ConfigBits[318+2]),
+	.S2N (ConfigBits_N[318+2]),
+	.S3 (ConfigBits[318+3]),
+	.S3N (ConfigBits_N[318+3]),
+	.X (JS2BEG2)
+	);
+
+// switch matrix multiplexer  JS2BEG3 		MUX-16
+	assign JS2BEG3_input = {WW4END2,W2END4,S4END0,S2END4,E6END0,E2END4,E1END2,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top2,bot2top1,bot2top0,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG3 (
+	.A0 (JS2BEG3_input[0]),
+	.A1 (JS2BEG3_input[1]),
+	.A2 (JS2BEG3_input[2]),
+	.A3 (JS2BEG3_input[3]),
+	.A4 (JS2BEG3_input[4]),
+	.A5 (JS2BEG3_input[5]),
+	.A6 (JS2BEG3_input[6]),
+	.A7 (JS2BEG3_input[7]),
+	.A8 (JS2BEG3_input[8]),
+	.A9 (JS2BEG3_input[9]),
+	.A10 (JS2BEG3_input[10]),
+	.A11 (JS2BEG3_input[11]),
+	.A12 (JS2BEG3_input[12]),
+	.A13 (JS2BEG3_input[13]),
+	.A14 (JS2BEG3_input[14]),
+	.A15 (JS2BEG3_input[15]),
+	.S0 (ConfigBits[322+0]),
+	.S0N (ConfigBits_N[322+0]),
+	.S1 (ConfigBits[322+1]),
+	.S1N (ConfigBits_N[322+1]),
+	.S2 (ConfigBits[322+2]),
+	.S2N (ConfigBits_N[322+2]),
+	.S3 (ConfigBits[322+3]),
+	.S3N (ConfigBits_N[322+3]),
+	.X (JS2BEG3)
+	);
+
+// switch matrix multiplexer  JS2BEG4 		MUX-16
+	assign JS2BEG4_input = {W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,bot2top9,bot2top7,bot2top6,bot2top5,bot2top3,bot2top2,bot2top1,bot2top0,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG4 (
+	.A0 (JS2BEG4_input[0]),
+	.A1 (JS2BEG4_input[1]),
+	.A2 (JS2BEG4_input[2]),
+	.A3 (JS2BEG4_input[3]),
+	.A4 (JS2BEG4_input[4]),
+	.A5 (JS2BEG4_input[5]),
+	.A6 (JS2BEG4_input[6]),
+	.A7 (JS2BEG4_input[7]),
+	.A8 (JS2BEG4_input[8]),
+	.A9 (JS2BEG4_input[9]),
+	.A10 (JS2BEG4_input[10]),
+	.A11 (JS2BEG4_input[11]),
+	.A12 (JS2BEG4_input[12]),
+	.A13 (JS2BEG4_input[13]),
+	.A14 (JS2BEG4_input[14]),
+	.A15 (JS2BEG4_input[15]),
+	.S0 (ConfigBits[326+0]),
+	.S0N (ConfigBits_N[326+0]),
+	.S1 (ConfigBits[326+1]),
+	.S1N (ConfigBits_N[326+1]),
+	.S2 (ConfigBits[326+2]),
+	.S2N (ConfigBits_N[326+2]),
+	.S3 (ConfigBits[326+3]),
+	.S3N (ConfigBits_N[326+3]),
+	.X (JS2BEG4)
+	);
+
+// switch matrix multiplexer  JS2BEG5 		MUX-16
+	assign JS2BEG5_input = {W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,bot2top8,bot2top7,bot2top6,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG5 (
+	.A0 (JS2BEG5_input[0]),
+	.A1 (JS2BEG5_input[1]),
+	.A2 (JS2BEG5_input[2]),
+	.A3 (JS2BEG5_input[3]),
+	.A4 (JS2BEG5_input[4]),
+	.A5 (JS2BEG5_input[5]),
+	.A6 (JS2BEG5_input[6]),
+	.A7 (JS2BEG5_input[7]),
+	.A8 (JS2BEG5_input[8]),
+	.A9 (JS2BEG5_input[9]),
+	.A10 (JS2BEG5_input[10]),
+	.A11 (JS2BEG5_input[11]),
+	.A12 (JS2BEG5_input[12]),
+	.A13 (JS2BEG5_input[13]),
+	.A14 (JS2BEG5_input[14]),
+	.A15 (JS2BEG5_input[15]),
+	.S0 (ConfigBits[330+0]),
+	.S0N (ConfigBits_N[330+0]),
+	.S1 (ConfigBits[330+1]),
+	.S1N (ConfigBits_N[330+1]),
+	.S2 (ConfigBits[330+2]),
+	.S2N (ConfigBits_N[330+2]),
+	.S3 (ConfigBits[330+3]),
+	.S3N (ConfigBits_N[330+3]),
+	.X (JS2BEG5)
+	);
+
+// switch matrix multiplexer  JS2BEG6 		MUX-16
+	assign JS2BEG6_input = {W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,bot2top9,bot2top7,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG6 (
+	.A0 (JS2BEG6_input[0]),
+	.A1 (JS2BEG6_input[1]),
+	.A2 (JS2BEG6_input[2]),
+	.A3 (JS2BEG6_input[3]),
+	.A4 (JS2BEG6_input[4]),
+	.A5 (JS2BEG6_input[5]),
+	.A6 (JS2BEG6_input[6]),
+	.A7 (JS2BEG6_input[7]),
+	.A8 (JS2BEG6_input[8]),
+	.A9 (JS2BEG6_input[9]),
+	.A10 (JS2BEG6_input[10]),
+	.A11 (JS2BEG6_input[11]),
+	.A12 (JS2BEG6_input[12]),
+	.A13 (JS2BEG6_input[13]),
+	.A14 (JS2BEG6_input[14]),
+	.A15 (JS2BEG6_input[15]),
+	.S0 (ConfigBits[334+0]),
+	.S0N (ConfigBits_N[334+0]),
+	.S1 (ConfigBits[334+1]),
+	.S1N (ConfigBits_N[334+1]),
+	.S2 (ConfigBits[334+2]),
+	.S2N (ConfigBits_N[334+2]),
+	.S3 (ConfigBits[334+3]),
+	.S3N (ConfigBits_N[334+3]),
+	.X (JS2BEG6)
+	);
+
+// switch matrix multiplexer  JS2BEG7 		MUX-16
+	assign JS2BEG7_input = {W1END2,W1END0,S2END0,S1END0,E2END0,E1END0,bot2top8,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG7 (
+	.A0 (JS2BEG7_input[0]),
+	.A1 (JS2BEG7_input[1]),
+	.A2 (JS2BEG7_input[2]),
+	.A3 (JS2BEG7_input[3]),
+	.A4 (JS2BEG7_input[4]),
+	.A5 (JS2BEG7_input[5]),
+	.A6 (JS2BEG7_input[6]),
+	.A7 (JS2BEG7_input[7]),
+	.A8 (JS2BEG7_input[8]),
+	.A9 (JS2BEG7_input[9]),
+	.A10 (JS2BEG7_input[10]),
+	.A11 (JS2BEG7_input[11]),
+	.A12 (JS2BEG7_input[12]),
+	.A13 (JS2BEG7_input[13]),
+	.A14 (JS2BEG7_input[14]),
+	.A15 (JS2BEG7_input[15]),
+	.S0 (ConfigBits[338+0]),
+	.S0N (ConfigBits_N[338+0]),
+	.S1 (ConfigBits[338+1]),
+	.S1N (ConfigBits_N[338+1]),
+	.S2 (ConfigBits[338+2]),
+	.S2N (ConfigBits_N[338+2]),
+	.S3 (ConfigBits[338+3]),
+	.S3N (ConfigBits_N[338+3]),
+	.X (JS2BEG7)
+	);
+
+// switch matrix multiplexer  JW2BEG0 		MUX-16
+	assign JW2BEG0_input = {W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG0 (
+	.A0 (JW2BEG0_input[0]),
+	.A1 (JW2BEG0_input[1]),
+	.A2 (JW2BEG0_input[2]),
+	.A3 (JW2BEG0_input[3]),
+	.A4 (JW2BEG0_input[4]),
+	.A5 (JW2BEG0_input[5]),
+	.A6 (JW2BEG0_input[6]),
+	.A7 (JW2BEG0_input[7]),
+	.A8 (JW2BEG0_input[8]),
+	.A9 (JW2BEG0_input[9]),
+	.A10 (JW2BEG0_input[10]),
+	.A11 (JW2BEG0_input[11]),
+	.A12 (JW2BEG0_input[12]),
+	.A13 (JW2BEG0_input[13]),
+	.A14 (JW2BEG0_input[14]),
+	.A15 (JW2BEG0_input[15]),
+	.S0 (ConfigBits[342+0]),
+	.S0N (ConfigBits_N[342+0]),
+	.S1 (ConfigBits[342+1]),
+	.S1N (ConfigBits_N[342+1]),
+	.S2 (ConfigBits[342+2]),
+	.S2N (ConfigBits_N[342+2]),
+	.S3 (ConfigBits[342+3]),
+	.S3N (ConfigBits_N[342+3]),
+	.X (JW2BEG0)
+	);
+
+// switch matrix multiplexer  JW2BEG1 		MUX-16
+	assign JW2BEG1_input = {W6END0,W2END2,S4END2,S2END2,E6END0,E2END2,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top0,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG1 (
+	.A0 (JW2BEG1_input[0]),
+	.A1 (JW2BEG1_input[1]),
+	.A2 (JW2BEG1_input[2]),
+	.A3 (JW2BEG1_input[3]),
+	.A4 (JW2BEG1_input[4]),
+	.A5 (JW2BEG1_input[5]),
+	.A6 (JW2BEG1_input[6]),
+	.A7 (JW2BEG1_input[7]),
+	.A8 (JW2BEG1_input[8]),
+	.A9 (JW2BEG1_input[9]),
+	.A10 (JW2BEG1_input[10]),
+	.A11 (JW2BEG1_input[11]),
+	.A12 (JW2BEG1_input[12]),
+	.A13 (JW2BEG1_input[13]),
+	.A14 (JW2BEG1_input[14]),
+	.A15 (JW2BEG1_input[15]),
+	.S0 (ConfigBits[346+0]),
+	.S0N (ConfigBits_N[346+0]),
+	.S1 (ConfigBits[346+1]),
+	.S1N (ConfigBits_N[346+1]),
+	.S2 (ConfigBits[346+2]),
+	.S2N (ConfigBits_N[346+2]),
+	.S3 (ConfigBits[346+3]),
+	.S3N (ConfigBits_N[346+3]),
+	.X (JW2BEG1)
+	);
+
+// switch matrix multiplexer  JW2BEG2 		MUX-16
+	assign JW2BEG2_input = {W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,bot2top8,bot2top7,bot2top6,bot2top5,bot2top4,bot2top3,bot2top1,bot2top0,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG2 (
+	.A0 (JW2BEG2_input[0]),
+	.A1 (JW2BEG2_input[1]),
+	.A2 (JW2BEG2_input[2]),
+	.A3 (JW2BEG2_input[3]),
+	.A4 (JW2BEG2_input[4]),
+	.A5 (JW2BEG2_input[5]),
+	.A6 (JW2BEG2_input[6]),
+	.A7 (JW2BEG2_input[7]),
+	.A8 (JW2BEG2_input[8]),
+	.A9 (JW2BEG2_input[9]),
+	.A10 (JW2BEG2_input[10]),
+	.A11 (JW2BEG2_input[11]),
+	.A12 (JW2BEG2_input[12]),
+	.A13 (JW2BEG2_input[13]),
+	.A14 (JW2BEG2_input[14]),
+	.A15 (JW2BEG2_input[15]),
+	.S0 (ConfigBits[350+0]),
+	.S0N (ConfigBits_N[350+0]),
+	.S1 (ConfigBits[350+1]),
+	.S1N (ConfigBits_N[350+1]),
+	.S2 (ConfigBits[350+2]),
+	.S2N (ConfigBits_N[350+2]),
+	.S3 (ConfigBits[350+3]),
+	.S3N (ConfigBits_N[350+3]),
+	.X (JW2BEG2)
+	);
+
+// switch matrix multiplexer  JW2BEG3 		MUX-16
+	assign JW2BEG3_input = {W6END0,W2END4,S4END0,S2END4,E6END0,E2END4,bot2top9,bot2top7,bot2top6,bot2top5,bot2top4,bot2top2,bot2top1,bot2top0,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG3 (
+	.A0 (JW2BEG3_input[0]),
+	.A1 (JW2BEG3_input[1]),
+	.A2 (JW2BEG3_input[2]),
+	.A3 (JW2BEG3_input[3]),
+	.A4 (JW2BEG3_input[4]),
+	.A5 (JW2BEG3_input[5]),
+	.A6 (JW2BEG3_input[6]),
+	.A7 (JW2BEG3_input[7]),
+	.A8 (JW2BEG3_input[8]),
+	.A9 (JW2BEG3_input[9]),
+	.A10 (JW2BEG3_input[10]),
+	.A11 (JW2BEG3_input[11]),
+	.A12 (JW2BEG3_input[12]),
+	.A13 (JW2BEG3_input[13]),
+	.A14 (JW2BEG3_input[14]),
+	.A15 (JW2BEG3_input[15]),
+	.S0 (ConfigBits[354+0]),
+	.S0N (ConfigBits_N[354+0]),
+	.S1 (ConfigBits[354+1]),
+	.S1N (ConfigBits_N[354+1]),
+	.S2 (ConfigBits[354+2]),
+	.S2N (ConfigBits_N[354+2]),
+	.S3 (ConfigBits[354+3]),
+	.S3N (ConfigBits_N[354+3]),
+	.X (JW2BEG3)
+	);
+
+// switch matrix multiplexer  JW2BEG4 		MUX-16
+	assign JW2BEG4_input = {W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,bot2top8,bot2top7,bot2top6,bot2top5,bot2top3,bot2top2,bot2top1,bot2top0,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG4 (
+	.A0 (JW2BEG4_input[0]),
+	.A1 (JW2BEG4_input[1]),
+	.A2 (JW2BEG4_input[2]),
+	.A3 (JW2BEG4_input[3]),
+	.A4 (JW2BEG4_input[4]),
+	.A5 (JW2BEG4_input[5]),
+	.A6 (JW2BEG4_input[6]),
+	.A7 (JW2BEG4_input[7]),
+	.A8 (JW2BEG4_input[8]),
+	.A9 (JW2BEG4_input[9]),
+	.A10 (JW2BEG4_input[10]),
+	.A11 (JW2BEG4_input[11]),
+	.A12 (JW2BEG4_input[12]),
+	.A13 (JW2BEG4_input[13]),
+	.A14 (JW2BEG4_input[14]),
+	.A15 (JW2BEG4_input[15]),
+	.S0 (ConfigBits[358+0]),
+	.S0N (ConfigBits_N[358+0]),
+	.S1 (ConfigBits[358+1]),
+	.S1N (ConfigBits_N[358+1]),
+	.S2 (ConfigBits[358+2]),
+	.S2N (ConfigBits_N[358+2]),
+	.S3 (ConfigBits[358+3]),
+	.S3N (ConfigBits_N[358+3]),
+	.X (JW2BEG4)
+	);
+
+// switch matrix multiplexer  JW2BEG5 		MUX-16
+	assign JW2BEG5_input = {W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,bot2top9,bot2top7,bot2top6,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG5 (
+	.A0 (JW2BEG5_input[0]),
+	.A1 (JW2BEG5_input[1]),
+	.A2 (JW2BEG5_input[2]),
+	.A3 (JW2BEG5_input[3]),
+	.A4 (JW2BEG5_input[4]),
+	.A5 (JW2BEG5_input[5]),
+	.A6 (JW2BEG5_input[6]),
+	.A7 (JW2BEG5_input[7]),
+	.A8 (JW2BEG5_input[8]),
+	.A9 (JW2BEG5_input[9]),
+	.A10 (JW2BEG5_input[10]),
+	.A11 (JW2BEG5_input[11]),
+	.A12 (JW2BEG5_input[12]),
+	.A13 (JW2BEG5_input[13]),
+	.A14 (JW2BEG5_input[14]),
+	.A15 (JW2BEG5_input[15]),
+	.S0 (ConfigBits[362+0]),
+	.S0N (ConfigBits_N[362+0]),
+	.S1 (ConfigBits[362+1]),
+	.S1N (ConfigBits_N[362+1]),
+	.S2 (ConfigBits[362+2]),
+	.S2N (ConfigBits_N[362+2]),
+	.S3 (ConfigBits[362+3]),
+	.S3N (ConfigBits_N[362+3]),
+	.X (JW2BEG5)
+	);
+
+// switch matrix multiplexer  JW2BEG6 		MUX-16
+	assign JW2BEG6_input = {W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,bot2top8,bot2top7,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG6 (
+	.A0 (JW2BEG6_input[0]),
+	.A1 (JW2BEG6_input[1]),
+	.A2 (JW2BEG6_input[2]),
+	.A3 (JW2BEG6_input[3]),
+	.A4 (JW2BEG6_input[4]),
+	.A5 (JW2BEG6_input[5]),
+	.A6 (JW2BEG6_input[6]),
+	.A7 (JW2BEG6_input[7]),
+	.A8 (JW2BEG6_input[8]),
+	.A9 (JW2BEG6_input[9]),
+	.A10 (JW2BEG6_input[10]),
+	.A11 (JW2BEG6_input[11]),
+	.A12 (JW2BEG6_input[12]),
+	.A13 (JW2BEG6_input[13]),
+	.A14 (JW2BEG6_input[14]),
+	.A15 (JW2BEG6_input[15]),
+	.S0 (ConfigBits[366+0]),
+	.S0N (ConfigBits_N[366+0]),
+	.S1 (ConfigBits[366+1]),
+	.S1N (ConfigBits_N[366+1]),
+	.S2 (ConfigBits[366+2]),
+	.S2N (ConfigBits_N[366+2]),
+	.S3 (ConfigBits[366+3]),
+	.S3N (ConfigBits_N[366+3]),
+	.X (JW2BEG6)
+	);
+
+// switch matrix multiplexer  JW2BEG7 		MUX-16
+	assign JW2BEG7_input = {W1END0,S2END0,S1END2,S1END0,E2END0,E1END0,bot2top9,bot2top6,bot2top5,bot2top4,bot2top3,bot2top2,bot2top1,bot2top0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG7 (
+	.A0 (JW2BEG7_input[0]),
+	.A1 (JW2BEG7_input[1]),
+	.A2 (JW2BEG7_input[2]),
+	.A3 (JW2BEG7_input[3]),
+	.A4 (JW2BEG7_input[4]),
+	.A5 (JW2BEG7_input[5]),
+	.A6 (JW2BEG7_input[6]),
+	.A7 (JW2BEG7_input[7]),
+	.A8 (JW2BEG7_input[8]),
+	.A9 (JW2BEG7_input[9]),
+	.A10 (JW2BEG7_input[10]),
+	.A11 (JW2BEG7_input[11]),
+	.A12 (JW2BEG7_input[12]),
+	.A13 (JW2BEG7_input[13]),
+	.A14 (JW2BEG7_input[14]),
+	.A15 (JW2BEG7_input[15]),
+	.S0 (ConfigBits[370+0]),
+	.S0N (ConfigBits_N[370+0]),
+	.S1 (ConfigBits[370+1]),
+	.S1N (ConfigBits_N[370+1]),
+	.S2 (ConfigBits[370+2]),
+	.S2N (ConfigBits_N[370+2]),
+	.S3 (ConfigBits[370+3]),
+	.S3N (ConfigBits_N[370+3]),
+	.X (JW2BEG7)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG0 		MUX-4
+	assign J_l_AB_BEG0_input = {JN2END1,WW4END0,S4END3,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG0 (
+	.A0 (J_l_AB_BEG0_input[0]),
+	.A1 (J_l_AB_BEG0_input[1]),
+	.A2 (J_l_AB_BEG0_input[2]),
+	.A3 (J_l_AB_BEG0_input[3]),
+	.S0 (ConfigBits[374+0]),
+	.S0N (ConfigBits_N[374+0]),
+	.S1 (ConfigBits[374+1]),
+	.S1N (ConfigBits_N[374+1]),
+	.X (J_l_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG1 		MUX-4
+	assign J_l_AB_BEG1_input = {JE2END1,W2END7,S4END2,EE4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG1 (
+	.A0 (J_l_AB_BEG1_input[0]),
+	.A1 (J_l_AB_BEG1_input[1]),
+	.A2 (J_l_AB_BEG1_input[2]),
+	.A3 (J_l_AB_BEG1_input[3]),
+	.S0 (ConfigBits[376+0]),
+	.S0N (ConfigBits_N[376+0]),
+	.S1 (ConfigBits[376+1]),
+	.S1N (ConfigBits_N[376+1]),
+	.X (J_l_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG2 		MUX-4
+	assign J_l_AB_BEG2_input = {JS2END1,W6END1,E6END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG2 (
+	.A0 (J_l_AB_BEG2_input[0]),
+	.A1 (J_l_AB_BEG2_input[1]),
+	.A2 (J_l_AB_BEG2_input[2]),
+	.A3 (J_l_AB_BEG2_input[3]),
+	.S0 (ConfigBits[378+0]),
+	.S0N (ConfigBits_N[378+0]),
+	.S1 (ConfigBits[378+1]),
+	.S1N (ConfigBits_N[378+1]),
+	.X (J_l_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG3 		MUX-4
+	assign J_l_AB_BEG3_input = {JW2END1,S4END0,E6END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG3 (
+	.A0 (J_l_AB_BEG3_input[0]),
+	.A1 (J_l_AB_BEG3_input[1]),
+	.A2 (J_l_AB_BEG3_input[2]),
+	.A3 (J_l_AB_BEG3_input[3]),
+	.S0 (ConfigBits[380+0]),
+	.S0N (ConfigBits_N[380+0]),
+	.S1 (ConfigBits[380+1]),
+	.S1N (ConfigBits_N[380+1]),
+	.X (J_l_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG0 		MUX-4
+	assign J_l_CD_BEG0_input = {JN2END2,WW4END2,SS4END3,E2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG0 (
+	.A0 (J_l_CD_BEG0_input[0]),
+	.A1 (J_l_CD_BEG0_input[1]),
+	.A2 (J_l_CD_BEG0_input[2]),
+	.A3 (J_l_CD_BEG0_input[3]),
+	.S0 (ConfigBits[382+0]),
+	.S0N (ConfigBits_N[382+0]),
+	.S1 (ConfigBits[382+1]),
+	.S1N (ConfigBits_N[382+1]),
+	.X (J_l_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG1 		MUX-4
+	assign J_l_CD_BEG1_input = {JE2END2,W2END7,E2END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG1 (
+	.A0 (J_l_CD_BEG1_input[0]),
+	.A1 (J_l_CD_BEG1_input[1]),
+	.A2 (J_l_CD_BEG1_input[2]),
+	.A3 (J_l_CD_BEG1_input[3]),
+	.S0 (ConfigBits[384+0]),
+	.S0N (ConfigBits_N[384+0]),
+	.S1 (ConfigBits[384+1]),
+	.S1N (ConfigBits_N[384+1]),
+	.X (J_l_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG2 		MUX-4
+	assign J_l_CD_BEG2_input = {JS2END2,S4END1,EE4END1,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG2 (
+	.A0 (J_l_CD_BEG2_input[0]),
+	.A1 (J_l_CD_BEG2_input[1]),
+	.A2 (J_l_CD_BEG2_input[2]),
+	.A3 (J_l_CD_BEG2_input[3]),
+	.S0 (ConfigBits[386+0]),
+	.S0N (ConfigBits_N[386+0]),
+	.S1 (ConfigBits[386+1]),
+	.S1N (ConfigBits_N[386+1]),
+	.X (J_l_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG3 		MUX-4
+	assign J_l_CD_BEG3_input = {JW2END2,W6END0,SS4END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG3 (
+	.A0 (J_l_CD_BEG3_input[0]),
+	.A1 (J_l_CD_BEG3_input[1]),
+	.A2 (J_l_CD_BEG3_input[2]),
+	.A3 (J_l_CD_BEG3_input[3]),
+	.S0 (ConfigBits[388+0]),
+	.S0N (ConfigBits_N[388+0]),
+	.S1 (ConfigBits[388+1]),
+	.S1N (ConfigBits_N[388+1]),
+	.X (J_l_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG0 		MUX-4
+	assign J_l_EF_BEG0_input = {JN2END3,W2END3,E2END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG0 (
+	.A0 (J_l_EF_BEG0_input[0]),
+	.A1 (J_l_EF_BEG0_input[1]),
+	.A2 (J_l_EF_BEG0_input[2]),
+	.A3 (J_l_EF_BEG0_input[3]),
+	.S0 (ConfigBits[390+0]),
+	.S0N (ConfigBits_N[390+0]),
+	.S1 (ConfigBits[390+1]),
+	.S1N (ConfigBits_N[390+1]),
+	.X (J_l_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG1 		MUX-4
+	assign J_l_EF_BEG1_input = {JE2END3,S4END2,E2END2,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG1 (
+	.A0 (J_l_EF_BEG1_input[0]),
+	.A1 (J_l_EF_BEG1_input[1]),
+	.A2 (J_l_EF_BEG1_input[2]),
+	.A3 (J_l_EF_BEG1_input[3]),
+	.S0 (ConfigBits[392+0]),
+	.S0N (ConfigBits_N[392+0]),
+	.S1 (ConfigBits[392+1]),
+	.S1N (ConfigBits_N[392+1]),
+	.X (J_l_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG2 		MUX-4
+	assign J_l_EF_BEG2_input = {JS2END3,W2END4,SS4END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG2 (
+	.A0 (J_l_EF_BEG2_input[0]),
+	.A1 (J_l_EF_BEG2_input[1]),
+	.A2 (J_l_EF_BEG2_input[2]),
+	.A3 (J_l_EF_BEG2_input[3]),
+	.S0 (ConfigBits[394+0]),
+	.S0N (ConfigBits_N[394+0]),
+	.S1 (ConfigBits[394+1]),
+	.S1N (ConfigBits_N[394+1]),
+	.X (J_l_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG3 		MUX-4
+	assign J_l_EF_BEG3_input = {JW2END3,WW4END1,S4END0,EE4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG3 (
+	.A0 (J_l_EF_BEG3_input[0]),
+	.A1 (J_l_EF_BEG3_input[1]),
+	.A2 (J_l_EF_BEG3_input[2]),
+	.A3 (J_l_EF_BEG3_input[3]),
+	.S0 (ConfigBits[396+0]),
+	.S0N (ConfigBits_N[396+0]),
+	.S1 (ConfigBits[396+1]),
+	.S1N (ConfigBits_N[396+1]),
+	.X (J_l_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG0 		MUX-4
+	assign J_l_GH_BEG0_input = {JN2END4,S4END3,EE4END0,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG0 (
+	.A0 (J_l_GH_BEG0_input[0]),
+	.A1 (J_l_GH_BEG0_input[1]),
+	.A2 (J_l_GH_BEG0_input[2]),
+	.A3 (J_l_GH_BEG0_input[3]),
+	.S0 (ConfigBits[398+0]),
+	.S0N (ConfigBits_N[398+0]),
+	.S1 (ConfigBits[398+1]),
+	.S1N (ConfigBits_N[398+1]),
+	.X (J_l_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG1 		MUX-4
+	assign J_l_GH_BEG1_input = {JE2END4,W2END2,SS4END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG1 (
+	.A0 (J_l_GH_BEG1_input[0]),
+	.A1 (J_l_GH_BEG1_input[1]),
+	.A2 (J_l_GH_BEG1_input[2]),
+	.A3 (J_l_GH_BEG1_input[3]),
+	.S0 (ConfigBits[400+0]),
+	.S0N (ConfigBits_N[400+0]),
+	.S1 (ConfigBits[400+1]),
+	.S1N (ConfigBits_N[400+1]),
+	.X (J_l_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG2 		MUX-4
+	assign J_l_GH_BEG2_input = {JS2END4,WW4END3,S4END1,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG2 (
+	.A0 (J_l_GH_BEG2_input[0]),
+	.A1 (J_l_GH_BEG2_input[1]),
+	.A2 (J_l_GH_BEG2_input[2]),
+	.A3 (J_l_GH_BEG2_input[3]),
+	.S0 (ConfigBits[402+0]),
+	.S0N (ConfigBits_N[402+0]),
+	.S1 (ConfigBits[402+1]),
+	.S1N (ConfigBits_N[402+1]),
+	.X (J_l_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG3 		MUX-4
+	assign J_l_GH_BEG3_input = {JW2END4,W2END0,E6END0,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG3 (
+	.A0 (J_l_GH_BEG3_input[0]),
+	.A1 (J_l_GH_BEG3_input[1]),
+	.A2 (J_l_GH_BEG3_input[2]),
+	.A3 (J_l_GH_BEG3_input[3]),
+	.S0 (ConfigBits[404+0]),
+	.S0N (ConfigBits_N[404+0]),
+	.S1 (ConfigBits[404+1]),
+	.S1N (ConfigBits_N[404+1]),
+	.X (J_l_GH_BEG3)
+	);
+
+	assign DEBUG_select_N1BEG0 = ConfigBits[1:0];
+	assign DEBUG_select_N1BEG1 = ConfigBits[3:2];
+	assign DEBUG_select_N1BEG2 = ConfigBits[5:4];
+	assign DEBUG_select_N1BEG3 = ConfigBits[7:6];
+	assign DEBUG_select_N4BEG0 = ConfigBits[9:8];
+	assign DEBUG_select_N4BEG1 = ConfigBits[11:10];
+	assign DEBUG_select_N4BEG2 = ConfigBits[13:12];
+	assign DEBUG_select_N4BEG3 = ConfigBits[15:14];
+	assign DEBUG_select_NN4BEG0 = ConfigBits[18:16];
+	assign DEBUG_select_NN4BEG1 = ConfigBits[21:19];
+	assign DEBUG_select_NN4BEG2 = ConfigBits[24:22];
+	assign DEBUG_select_NN4BEG3 = ConfigBits[27:25];
+	assign DEBUG_select_E1BEG0 = ConfigBits[29:28];
+	assign DEBUG_select_E1BEG1 = ConfigBits[31:30];
+	assign DEBUG_select_E1BEG2 = ConfigBits[33:32];
+	assign DEBUG_select_E1BEG3 = ConfigBits[35:34];
+	assign DEBUG_select_EE4BEG0 = ConfigBits[38:36];
+	assign DEBUG_select_EE4BEG1 = ConfigBits[41:39];
+	assign DEBUG_select_EE4BEG2 = ConfigBits[44:42];
+	assign DEBUG_select_EE4BEG3 = ConfigBits[47:45];
+	assign DEBUG_select_E6BEG0 = ConfigBits[51:48];
+	assign DEBUG_select_E6BEG1 = ConfigBits[55:52];
+	assign DEBUG_select_S1BEG0 = ConfigBits[57:56];
+	assign DEBUG_select_S1BEG1 = ConfigBits[59:58];
+	assign DEBUG_select_S1BEG2 = ConfigBits[61:60];
+	assign DEBUG_select_S1BEG3 = ConfigBits[63:62];
+	assign DEBUG_select_S4BEG0 = ConfigBits[65:64];
+	assign DEBUG_select_S4BEG1 = ConfigBits[67:66];
+	assign DEBUG_select_S4BEG2 = ConfigBits[69:68];
+	assign DEBUG_select_S4BEG3 = ConfigBits[71:70];
+	assign DEBUG_select_SS4BEG0 = ConfigBits[74:72];
+	assign DEBUG_select_SS4BEG1 = ConfigBits[77:75];
+	assign DEBUG_select_SS4BEG2 = ConfigBits[80:78];
+	assign DEBUG_select_SS4BEG3 = ConfigBits[83:81];
+	assign DEBUG_select_top2bot0 = ConfigBits[85:84];
+	assign DEBUG_select_top2bot1 = ConfigBits[87:86];
+	assign DEBUG_select_top2bot2 = ConfigBits[89:88];
+	assign DEBUG_select_top2bot3 = ConfigBits[91:90];
+	assign DEBUG_select_top2bot4 = ConfigBits[93:92];
+	assign DEBUG_select_top2bot5 = ConfigBits[95:94];
+	assign DEBUG_select_top2bot6 = ConfigBits[97:96];
+	assign DEBUG_select_top2bot7 = ConfigBits[99:98];
+	assign DEBUG_select_top2bot8 = ConfigBits[101:100];
+	assign DEBUG_select_top2bot9 = ConfigBits[103:102];
+	assign DEBUG_select_top2bot10 = ConfigBits[105:104];
+	assign DEBUG_select_top2bot11 = ConfigBits[107:106];
+	assign DEBUG_select_top2bot12 = ConfigBits[109:108];
+	assign DEBUG_select_top2bot13 = ConfigBits[111:110];
+	assign DEBUG_select_top2bot14 = ConfigBits[113:112];
+	assign DEBUG_select_top2bot15 = ConfigBits[115:114];
+	assign DEBUG_select_top2bot16 = ConfigBits[118:116];
+	assign DEBUG_select_top2bot17 = ConfigBits[121:119];
+	assign DEBUG_select_W1BEG0 = ConfigBits[123:122];
+	assign DEBUG_select_W1BEG1 = ConfigBits[125:124];
+	assign DEBUG_select_W1BEG2 = ConfigBits[127:126];
+	assign DEBUG_select_W1BEG3 = ConfigBits[129:128];
+	assign DEBUG_select_WW4BEG0 = ConfigBits[132:130];
+	assign DEBUG_select_WW4BEG1 = ConfigBits[135:133];
+	assign DEBUG_select_WW4BEG2 = ConfigBits[138:136];
+	assign DEBUG_select_WW4BEG3 = ConfigBits[141:139];
+	assign DEBUG_select_W6BEG0 = ConfigBits[145:142];
+	assign DEBUG_select_W6BEG1 = ConfigBits[149:146];
+	assign DEBUG_select_J2MID_ABa_BEG0 = ConfigBits[151:150];
+	assign DEBUG_select_J2MID_ABa_BEG1 = ConfigBits[153:152];
+	assign DEBUG_select_J2MID_ABa_BEG2 = ConfigBits[155:154];
+	assign DEBUG_select_J2MID_ABa_BEG3 = ConfigBits[157:156];
+	assign DEBUG_select_J2MID_CDa_BEG0 = ConfigBits[159:158];
+	assign DEBUG_select_J2MID_CDa_BEG1 = ConfigBits[161:160];
+	assign DEBUG_select_J2MID_CDa_BEG2 = ConfigBits[163:162];
+	assign DEBUG_select_J2MID_CDa_BEG3 = ConfigBits[165:164];
+	assign DEBUG_select_J2MID_EFa_BEG0 = ConfigBits[167:166];
+	assign DEBUG_select_J2MID_EFa_BEG1 = ConfigBits[169:168];
+	assign DEBUG_select_J2MID_EFa_BEG2 = ConfigBits[171:170];
+	assign DEBUG_select_J2MID_EFa_BEG3 = ConfigBits[173:172];
+	assign DEBUG_select_J2MID_GHa_BEG0 = ConfigBits[175:174];
+	assign DEBUG_select_J2MID_GHa_BEG1 = ConfigBits[177:176];
+	assign DEBUG_select_J2MID_GHa_BEG2 = ConfigBits[179:178];
+	assign DEBUG_select_J2MID_GHa_BEG3 = ConfigBits[181:180];
+	assign DEBUG_select_J2MID_ABb_BEG0 = ConfigBits[183:182];
+	assign DEBUG_select_J2MID_ABb_BEG1 = ConfigBits[185:184];
+	assign DEBUG_select_J2MID_ABb_BEG2 = ConfigBits[187:186];
+	assign DEBUG_select_J2MID_ABb_BEG3 = ConfigBits[189:188];
+	assign DEBUG_select_J2MID_CDb_BEG0 = ConfigBits[191:190];
+	assign DEBUG_select_J2MID_CDb_BEG1 = ConfigBits[193:192];
+	assign DEBUG_select_J2MID_CDb_BEG2 = ConfigBits[195:194];
+	assign DEBUG_select_J2MID_CDb_BEG3 = ConfigBits[197:196];
+	assign DEBUG_select_J2MID_EFb_BEG0 = ConfigBits[199:198];
+	assign DEBUG_select_J2MID_EFb_BEG1 = ConfigBits[201:200];
+	assign DEBUG_select_J2MID_EFb_BEG2 = ConfigBits[203:202];
+	assign DEBUG_select_J2MID_EFb_BEG3 = ConfigBits[205:204];
+	assign DEBUG_select_J2MID_GHb_BEG0 = ConfigBits[207:206];
+	assign DEBUG_select_J2MID_GHb_BEG1 = ConfigBits[209:208];
+	assign DEBUG_select_J2MID_GHb_BEG2 = ConfigBits[211:210];
+	assign DEBUG_select_J2MID_GHb_BEG3 = ConfigBits[213:212];
+	assign DEBUG_select_J2END_AB_BEG0 = ConfigBits[215:214];
+	assign DEBUG_select_J2END_AB_BEG1 = ConfigBits[217:216];
+	assign DEBUG_select_J2END_AB_BEG2 = ConfigBits[219:218];
+	assign DEBUG_select_J2END_AB_BEG3 = ConfigBits[221:220];
+	assign DEBUG_select_J2END_CD_BEG0 = ConfigBits[223:222];
+	assign DEBUG_select_J2END_CD_BEG1 = ConfigBits[225:224];
+	assign DEBUG_select_J2END_CD_BEG2 = ConfigBits[227:226];
+	assign DEBUG_select_J2END_CD_BEG3 = ConfigBits[229:228];
+	assign DEBUG_select_J2END_EF_BEG0 = ConfigBits[231:230];
+	assign DEBUG_select_J2END_EF_BEG1 = ConfigBits[233:232];
+	assign DEBUG_select_J2END_EF_BEG2 = ConfigBits[235:234];
+	assign DEBUG_select_J2END_EF_BEG3 = ConfigBits[237:236];
+	assign DEBUG_select_J2END_GH_BEG0 = ConfigBits[239:238];
+	assign DEBUG_select_J2END_GH_BEG1 = ConfigBits[241:240];
+	assign DEBUG_select_J2END_GH_BEG2 = ConfigBits[243:242];
+	assign DEBUG_select_J2END_GH_BEG3 = ConfigBits[245:244];
+	assign DEBUG_select_JN2BEG0 = ConfigBits[249:246];
+	assign DEBUG_select_JN2BEG1 = ConfigBits[253:250];
+	assign DEBUG_select_JN2BEG2 = ConfigBits[257:254];
+	assign DEBUG_select_JN2BEG3 = ConfigBits[261:258];
+	assign DEBUG_select_JN2BEG4 = ConfigBits[265:262];
+	assign DEBUG_select_JN2BEG5 = ConfigBits[269:266];
+	assign DEBUG_select_JN2BEG6 = ConfigBits[273:270];
+	assign DEBUG_select_JN2BEG7 = ConfigBits[277:274];
+	assign DEBUG_select_JE2BEG0 = ConfigBits[281:278];
+	assign DEBUG_select_JE2BEG1 = ConfigBits[285:282];
+	assign DEBUG_select_JE2BEG2 = ConfigBits[289:286];
+	assign DEBUG_select_JE2BEG3 = ConfigBits[293:290];
+	assign DEBUG_select_JE2BEG4 = ConfigBits[297:294];
+	assign DEBUG_select_JE2BEG5 = ConfigBits[301:298];
+	assign DEBUG_select_JE2BEG6 = ConfigBits[305:302];
+	assign DEBUG_select_JE2BEG7 = ConfigBits[309:306];
+	assign DEBUG_select_JS2BEG0 = ConfigBits[313:310];
+	assign DEBUG_select_JS2BEG1 = ConfigBits[317:314];
+	assign DEBUG_select_JS2BEG2 = ConfigBits[321:318];
+	assign DEBUG_select_JS2BEG3 = ConfigBits[325:322];
+	assign DEBUG_select_JS2BEG4 = ConfigBits[329:326];
+	assign DEBUG_select_JS2BEG5 = ConfigBits[333:330];
+	assign DEBUG_select_JS2BEG6 = ConfigBits[337:334];
+	assign DEBUG_select_JS2BEG7 = ConfigBits[341:338];
+	assign DEBUG_select_JW2BEG0 = ConfigBits[345:342];
+	assign DEBUG_select_JW2BEG1 = ConfigBits[349:346];
+	assign DEBUG_select_JW2BEG2 = ConfigBits[353:350];
+	assign DEBUG_select_JW2BEG3 = ConfigBits[357:354];
+	assign DEBUG_select_JW2BEG4 = ConfigBits[361:358];
+	assign DEBUG_select_JW2BEG5 = ConfigBits[365:362];
+	assign DEBUG_select_JW2BEG6 = ConfigBits[369:366];
+	assign DEBUG_select_JW2BEG7 = ConfigBits[373:370];
+	assign DEBUG_select_J_l_AB_BEG0 = ConfigBits[375:374];
+	assign DEBUG_select_J_l_AB_BEG1 = ConfigBits[377:376];
+	assign DEBUG_select_J_l_AB_BEG2 = ConfigBits[379:378];
+	assign DEBUG_select_J_l_AB_BEG3 = ConfigBits[381:380];
+	assign DEBUG_select_J_l_CD_BEG0 = ConfigBits[383:382];
+	assign DEBUG_select_J_l_CD_BEG1 = ConfigBits[385:384];
+	assign DEBUG_select_J_l_CD_BEG2 = ConfigBits[387:386];
+	assign DEBUG_select_J_l_CD_BEG3 = ConfigBits[389:388];
+	assign DEBUG_select_J_l_EF_BEG0 = ConfigBits[391:390];
+	assign DEBUG_select_J_l_EF_BEG1 = ConfigBits[393:392];
+	assign DEBUG_select_J_l_EF_BEG2 = ConfigBits[395:394];
+	assign DEBUG_select_J_l_EF_BEG3 = ConfigBits[397:396];
+	assign DEBUG_select_J_l_GH_BEG0 = ConfigBits[399:398];
+	assign DEBUG_select_J_l_GH_BEG1 = ConfigBits[401:400];
+	assign DEBUG_select_J_l_GH_BEG2 = ConfigBits[403:402];
+	assign DEBUG_select_J_l_GH_BEG3 = ConfigBits[405:404];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/DSP_top_tile.v b/verilog/rtl/eFPGA_core/DSP_top_tile.v
new file mode 100644
index 0000000..cd3f310
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/DSP_top_tile.v
@@ -0,0 +1,2038 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module DSP_top (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, N1END, N2MID, N2END, N4END, NN4END, bot2top, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, top2bot, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 406;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	input [9:0] bot2top; //wires:10 X_offset:0 Y_offset:1  source_name:NULL destination_name:bot2top  
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	output [17:0] top2bot; //wires:18 X_offset:0 Y_offset:-1  source_name:top2bot destination_name:NULL  
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input UserCLK;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+	wire [4-1:0] J2MID_ABa_BEG;
+	wire [4-1:0] J2MID_CDa_BEG;
+	wire [4-1:0] J2MID_EFa_BEG;
+	wire [4-1:0] J2MID_GHa_BEG;
+	wire [4-1:0] J2MID_ABb_BEG;
+	wire [4-1:0] J2MID_CDb_BEG;
+	wire [4-1:0] J2MID_EFb_BEG;
+	wire [4-1:0] J2MID_GHb_BEG;
+	wire [4-1:0] J2END_AB_BEG;
+	wire [4-1:0] J2END_CD_BEG;
+	wire [4-1:0] J2END_EF_BEG;
+	wire [4-1:0] J2END_GH_BEG;
+	wire [8-1:0] JN2BEG;
+	wire [8-1:0] JE2BEG;
+	wire [8-1:0] JS2BEG;
+	wire [8-1:0] JW2BEG;
+	wire [4-1:0] J_l_AB_BEG;
+	wire [4-1:0] J_l_CD_BEG;
+	wire [4-1:0] J_l_EF_BEG;
+	wire [4-1:0] J_l_GH_BEG;
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	wire [15:0] N4END_i;
+	wire [11:0] N4BEG_i;
+	assign N4BEG_i[15-4:0] = N4END_i[15:4];
+
+	my_buf N4END_inbuf_0 (
+	.A(N4END[4]),
+	.X(N4END_i[4])
+	);
+
+	my_buf N4END_inbuf_1 (
+	.A(N4END[5]),
+	.X(N4END_i[5])
+	);
+
+	my_buf N4END_inbuf_2 (
+	.A(N4END[6]),
+	.X(N4END_i[6])
+	);
+
+	my_buf N4END_inbuf_3 (
+	.A(N4END[7]),
+	.X(N4END_i[7])
+	);
+
+	my_buf N4END_inbuf_4 (
+	.A(N4END[8]),
+	.X(N4END_i[8])
+	);
+
+	my_buf N4END_inbuf_5 (
+	.A(N4END[9]),
+	.X(N4END_i[9])
+	);
+
+	my_buf N4END_inbuf_6 (
+	.A(N4END[10]),
+	.X(N4END_i[10])
+	);
+
+	my_buf N4END_inbuf_7 (
+	.A(N4END[11]),
+	.X(N4END_i[11])
+	);
+
+	my_buf N4END_inbuf_8 (
+	.A(N4END[12]),
+	.X(N4END_i[12])
+	);
+
+	my_buf N4END_inbuf_9 (
+	.A(N4END[13]),
+	.X(N4END_i[13])
+	);
+
+	my_buf N4END_inbuf_10 (
+	.A(N4END[14]),
+	.X(N4END_i[14])
+	);
+
+	my_buf N4END_inbuf_11 (
+	.A(N4END[15]),
+	.X(N4END_i[15])
+	);
+
+	my_buf N4BEG_outbuf_0 (
+	.A(N4BEG_i[0]),
+	.X(N4BEG[0])
+	);
+
+	my_buf N4BEG_outbuf_1 (
+	.A(N4BEG_i[1]),
+	.X(N4BEG[1])
+	);
+
+	my_buf N4BEG_outbuf_2 (
+	.A(N4BEG_i[2]),
+	.X(N4BEG[2])
+	);
+
+	my_buf N4BEG_outbuf_3 (
+	.A(N4BEG_i[3]),
+	.X(N4BEG[3])
+	);
+
+	my_buf N4BEG_outbuf_4 (
+	.A(N4BEG_i[4]),
+	.X(N4BEG[4])
+	);
+
+	my_buf N4BEG_outbuf_5 (
+	.A(N4BEG_i[5]),
+	.X(N4BEG[5])
+	);
+
+	my_buf N4BEG_outbuf_6 (
+	.A(N4BEG_i[6]),
+	.X(N4BEG[6])
+	);
+
+	my_buf N4BEG_outbuf_7 (
+	.A(N4BEG_i[7]),
+	.X(N4BEG[7])
+	);
+
+	my_buf N4BEG_outbuf_8 (
+	.A(N4BEG_i[8]),
+	.X(N4BEG[8])
+	);
+
+	my_buf N4BEG_outbuf_9 (
+	.A(N4BEG_i[9]),
+	.X(N4BEG[9])
+	);
+
+	my_buf N4BEG_outbuf_10 (
+	.A(N4BEG_i[10]),
+	.X(N4BEG[10])
+	);
+
+	my_buf N4BEG_outbuf_11 (
+	.A(N4BEG_i[11]),
+	.X(N4BEG[11])
+	);
+
+	wire [15:0] NN4END_i;
+	wire [11:0] NN4BEG_i;
+	assign NN4BEG_i[15-4:0] = NN4END_i[15:4];
+
+	my_buf NN4END_inbuf_0 (
+	.A(NN4END[4]),
+	.X(NN4END_i[4])
+	);
+
+	my_buf NN4END_inbuf_1 (
+	.A(NN4END[5]),
+	.X(NN4END_i[5])
+	);
+
+	my_buf NN4END_inbuf_2 (
+	.A(NN4END[6]),
+	.X(NN4END_i[6])
+	);
+
+	my_buf NN4END_inbuf_3 (
+	.A(NN4END[7]),
+	.X(NN4END_i[7])
+	);
+
+	my_buf NN4END_inbuf_4 (
+	.A(NN4END[8]),
+	.X(NN4END_i[8])
+	);
+
+	my_buf NN4END_inbuf_5 (
+	.A(NN4END[9]),
+	.X(NN4END_i[9])
+	);
+
+	my_buf NN4END_inbuf_6 (
+	.A(NN4END[10]),
+	.X(NN4END_i[10])
+	);
+
+	my_buf NN4END_inbuf_7 (
+	.A(NN4END[11]),
+	.X(NN4END_i[11])
+	);
+
+	my_buf NN4END_inbuf_8 (
+	.A(NN4END[12]),
+	.X(NN4END_i[12])
+	);
+
+	my_buf NN4END_inbuf_9 (
+	.A(NN4END[13]),
+	.X(NN4END_i[13])
+	);
+
+	my_buf NN4END_inbuf_10 (
+	.A(NN4END[14]),
+	.X(NN4END_i[14])
+	);
+
+	my_buf NN4END_inbuf_11 (
+	.A(NN4END[15]),
+	.X(NN4END_i[15])
+	);
+
+	my_buf NN4BEG_outbuf_0 (
+	.A(NN4BEG_i[0]),
+	.X(NN4BEG[0])
+	);
+
+	my_buf NN4BEG_outbuf_1 (
+	.A(NN4BEG_i[1]),
+	.X(NN4BEG[1])
+	);
+
+	my_buf NN4BEG_outbuf_2 (
+	.A(NN4BEG_i[2]),
+	.X(NN4BEG[2])
+	);
+
+	my_buf NN4BEG_outbuf_3 (
+	.A(NN4BEG_i[3]),
+	.X(NN4BEG[3])
+	);
+
+	my_buf NN4BEG_outbuf_4 (
+	.A(NN4BEG_i[4]),
+	.X(NN4BEG[4])
+	);
+
+	my_buf NN4BEG_outbuf_5 (
+	.A(NN4BEG_i[5]),
+	.X(NN4BEG[5])
+	);
+
+	my_buf NN4BEG_outbuf_6 (
+	.A(NN4BEG_i[6]),
+	.X(NN4BEG[6])
+	);
+
+	my_buf NN4BEG_outbuf_7 (
+	.A(NN4BEG_i[7]),
+	.X(NN4BEG[7])
+	);
+
+	my_buf NN4BEG_outbuf_8 (
+	.A(NN4BEG_i[8]),
+	.X(NN4BEG[8])
+	);
+
+	my_buf NN4BEG_outbuf_9 (
+	.A(NN4BEG_i[9]),
+	.X(NN4BEG[9])
+	);
+
+	my_buf NN4BEG_outbuf_10 (
+	.A(NN4BEG_i[10]),
+	.X(NN4BEG[10])
+	);
+
+	my_buf NN4BEG_outbuf_11 (
+	.A(NN4BEG_i[11]),
+	.X(NN4BEG[11])
+	);
+
+	wire [15:0] EE4END_i;
+	wire [11:0] EE4BEG_i;
+	assign EE4BEG_i[15-4:0] = EE4END_i[15:4];
+
+	my_buf EE4END_inbuf_0 (
+	.A(EE4END[4]),
+	.X(EE4END_i[4])
+	);
+
+	my_buf EE4END_inbuf_1 (
+	.A(EE4END[5]),
+	.X(EE4END_i[5])
+	);
+
+	my_buf EE4END_inbuf_2 (
+	.A(EE4END[6]),
+	.X(EE4END_i[6])
+	);
+
+	my_buf EE4END_inbuf_3 (
+	.A(EE4END[7]),
+	.X(EE4END_i[7])
+	);
+
+	my_buf EE4END_inbuf_4 (
+	.A(EE4END[8]),
+	.X(EE4END_i[8])
+	);
+
+	my_buf EE4END_inbuf_5 (
+	.A(EE4END[9]),
+	.X(EE4END_i[9])
+	);
+
+	my_buf EE4END_inbuf_6 (
+	.A(EE4END[10]),
+	.X(EE4END_i[10])
+	);
+
+	my_buf EE4END_inbuf_7 (
+	.A(EE4END[11]),
+	.X(EE4END_i[11])
+	);
+
+	my_buf EE4END_inbuf_8 (
+	.A(EE4END[12]),
+	.X(EE4END_i[12])
+	);
+
+	my_buf EE4END_inbuf_9 (
+	.A(EE4END[13]),
+	.X(EE4END_i[13])
+	);
+
+	my_buf EE4END_inbuf_10 (
+	.A(EE4END[14]),
+	.X(EE4END_i[14])
+	);
+
+	my_buf EE4END_inbuf_11 (
+	.A(EE4END[15]),
+	.X(EE4END_i[15])
+	);
+
+	my_buf EE4BEG_outbuf_0 (
+	.A(EE4BEG_i[0]),
+	.X(EE4BEG[0])
+	);
+
+	my_buf EE4BEG_outbuf_1 (
+	.A(EE4BEG_i[1]),
+	.X(EE4BEG[1])
+	);
+
+	my_buf EE4BEG_outbuf_2 (
+	.A(EE4BEG_i[2]),
+	.X(EE4BEG[2])
+	);
+
+	my_buf EE4BEG_outbuf_3 (
+	.A(EE4BEG_i[3]),
+	.X(EE4BEG[3])
+	);
+
+	my_buf EE4BEG_outbuf_4 (
+	.A(EE4BEG_i[4]),
+	.X(EE4BEG[4])
+	);
+
+	my_buf EE4BEG_outbuf_5 (
+	.A(EE4BEG_i[5]),
+	.X(EE4BEG[5])
+	);
+
+	my_buf EE4BEG_outbuf_6 (
+	.A(EE4BEG_i[6]),
+	.X(EE4BEG[6])
+	);
+
+	my_buf EE4BEG_outbuf_7 (
+	.A(EE4BEG_i[7]),
+	.X(EE4BEG[7])
+	);
+
+	my_buf EE4BEG_outbuf_8 (
+	.A(EE4BEG_i[8]),
+	.X(EE4BEG[8])
+	);
+
+	my_buf EE4BEG_outbuf_9 (
+	.A(EE4BEG_i[9]),
+	.X(EE4BEG[9])
+	);
+
+	my_buf EE4BEG_outbuf_10 (
+	.A(EE4BEG_i[10]),
+	.X(EE4BEG[10])
+	);
+
+	my_buf EE4BEG_outbuf_11 (
+	.A(EE4BEG_i[11]),
+	.X(EE4BEG[11])
+	);
+
+	wire [11:0] E6END_i;
+	wire [9:0] E6BEG_i;
+	assign E6BEG_i[11-2:0] = E6END_i[11:2];
+
+	my_buf E6END_inbuf_0 (
+	.A(E6END[2]),
+	.X(E6END_i[2])
+	);
+
+	my_buf E6END_inbuf_1 (
+	.A(E6END[3]),
+	.X(E6END_i[3])
+	);
+
+	my_buf E6END_inbuf_2 (
+	.A(E6END[4]),
+	.X(E6END_i[4])
+	);
+
+	my_buf E6END_inbuf_3 (
+	.A(E6END[5]),
+	.X(E6END_i[5])
+	);
+
+	my_buf E6END_inbuf_4 (
+	.A(E6END[6]),
+	.X(E6END_i[6])
+	);
+
+	my_buf E6END_inbuf_5 (
+	.A(E6END[7]),
+	.X(E6END_i[7])
+	);
+
+	my_buf E6END_inbuf_6 (
+	.A(E6END[8]),
+	.X(E6END_i[8])
+	);
+
+	my_buf E6END_inbuf_7 (
+	.A(E6END[9]),
+	.X(E6END_i[9])
+	);
+
+	my_buf E6END_inbuf_8 (
+	.A(E6END[10]),
+	.X(E6END_i[10])
+	);
+
+	my_buf E6END_inbuf_9 (
+	.A(E6END[11]),
+	.X(E6END_i[11])
+	);
+
+	my_buf E6BEG_outbuf_0 (
+	.A(E6BEG_i[0]),
+	.X(E6BEG[0])
+	);
+
+	my_buf E6BEG_outbuf_1 (
+	.A(E6BEG_i[1]),
+	.X(E6BEG[1])
+	);
+
+	my_buf E6BEG_outbuf_2 (
+	.A(E6BEG_i[2]),
+	.X(E6BEG[2])
+	);
+
+	my_buf E6BEG_outbuf_3 (
+	.A(E6BEG_i[3]),
+	.X(E6BEG[3])
+	);
+
+	my_buf E6BEG_outbuf_4 (
+	.A(E6BEG_i[4]),
+	.X(E6BEG[4])
+	);
+
+	my_buf E6BEG_outbuf_5 (
+	.A(E6BEG_i[5]),
+	.X(E6BEG[5])
+	);
+
+	my_buf E6BEG_outbuf_6 (
+	.A(E6BEG_i[6]),
+	.X(E6BEG[6])
+	);
+
+	my_buf E6BEG_outbuf_7 (
+	.A(E6BEG_i[7]),
+	.X(E6BEG[7])
+	);
+
+	my_buf E6BEG_outbuf_8 (
+	.A(E6BEG_i[8]),
+	.X(E6BEG[8])
+	);
+
+	my_buf E6BEG_outbuf_9 (
+	.A(E6BEG_i[9]),
+	.X(E6BEG[9])
+	);
+
+	wire [15:0] S4END_i;
+	wire [11:0] S4BEG_i;
+	assign S4BEG_i[15-4:0] = S4END_i[15:4];
+
+	my_buf S4END_inbuf_0 (
+	.A(S4END[4]),
+	.X(S4END_i[4])
+	);
+
+	my_buf S4END_inbuf_1 (
+	.A(S4END[5]),
+	.X(S4END_i[5])
+	);
+
+	my_buf S4END_inbuf_2 (
+	.A(S4END[6]),
+	.X(S4END_i[6])
+	);
+
+	my_buf S4END_inbuf_3 (
+	.A(S4END[7]),
+	.X(S4END_i[7])
+	);
+
+	my_buf S4END_inbuf_4 (
+	.A(S4END[8]),
+	.X(S4END_i[8])
+	);
+
+	my_buf S4END_inbuf_5 (
+	.A(S4END[9]),
+	.X(S4END_i[9])
+	);
+
+	my_buf S4END_inbuf_6 (
+	.A(S4END[10]),
+	.X(S4END_i[10])
+	);
+
+	my_buf S4END_inbuf_7 (
+	.A(S4END[11]),
+	.X(S4END_i[11])
+	);
+
+	my_buf S4END_inbuf_8 (
+	.A(S4END[12]),
+	.X(S4END_i[12])
+	);
+
+	my_buf S4END_inbuf_9 (
+	.A(S4END[13]),
+	.X(S4END_i[13])
+	);
+
+	my_buf S4END_inbuf_10 (
+	.A(S4END[14]),
+	.X(S4END_i[14])
+	);
+
+	my_buf S4END_inbuf_11 (
+	.A(S4END[15]),
+	.X(S4END_i[15])
+	);
+
+	my_buf S4BEG_outbuf_0 (
+	.A(S4BEG_i[0]),
+	.X(S4BEG[0])
+	);
+
+	my_buf S4BEG_outbuf_1 (
+	.A(S4BEG_i[1]),
+	.X(S4BEG[1])
+	);
+
+	my_buf S4BEG_outbuf_2 (
+	.A(S4BEG_i[2]),
+	.X(S4BEG[2])
+	);
+
+	my_buf S4BEG_outbuf_3 (
+	.A(S4BEG_i[3]),
+	.X(S4BEG[3])
+	);
+
+	my_buf S4BEG_outbuf_4 (
+	.A(S4BEG_i[4]),
+	.X(S4BEG[4])
+	);
+
+	my_buf S4BEG_outbuf_5 (
+	.A(S4BEG_i[5]),
+	.X(S4BEG[5])
+	);
+
+	my_buf S4BEG_outbuf_6 (
+	.A(S4BEG_i[6]),
+	.X(S4BEG[6])
+	);
+
+	my_buf S4BEG_outbuf_7 (
+	.A(S4BEG_i[7]),
+	.X(S4BEG[7])
+	);
+
+	my_buf S4BEG_outbuf_8 (
+	.A(S4BEG_i[8]),
+	.X(S4BEG[8])
+	);
+
+	my_buf S4BEG_outbuf_9 (
+	.A(S4BEG_i[9]),
+	.X(S4BEG[9])
+	);
+
+	my_buf S4BEG_outbuf_10 (
+	.A(S4BEG_i[10]),
+	.X(S4BEG[10])
+	);
+
+	my_buf S4BEG_outbuf_11 (
+	.A(S4BEG_i[11]),
+	.X(S4BEG[11])
+	);
+
+	wire [15:0] SS4END_i;
+	wire [11:0] SS4BEG_i;
+	assign SS4BEG_i[15-4:0] = SS4END_i[15:4];
+
+	my_buf SS4END_inbuf_0 (
+	.A(SS4END[4]),
+	.X(SS4END_i[4])
+	);
+
+	my_buf SS4END_inbuf_1 (
+	.A(SS4END[5]),
+	.X(SS4END_i[5])
+	);
+
+	my_buf SS4END_inbuf_2 (
+	.A(SS4END[6]),
+	.X(SS4END_i[6])
+	);
+
+	my_buf SS4END_inbuf_3 (
+	.A(SS4END[7]),
+	.X(SS4END_i[7])
+	);
+
+	my_buf SS4END_inbuf_4 (
+	.A(SS4END[8]),
+	.X(SS4END_i[8])
+	);
+
+	my_buf SS4END_inbuf_5 (
+	.A(SS4END[9]),
+	.X(SS4END_i[9])
+	);
+
+	my_buf SS4END_inbuf_6 (
+	.A(SS4END[10]),
+	.X(SS4END_i[10])
+	);
+
+	my_buf SS4END_inbuf_7 (
+	.A(SS4END[11]),
+	.X(SS4END_i[11])
+	);
+
+	my_buf SS4END_inbuf_8 (
+	.A(SS4END[12]),
+	.X(SS4END_i[12])
+	);
+
+	my_buf SS4END_inbuf_9 (
+	.A(SS4END[13]),
+	.X(SS4END_i[13])
+	);
+
+	my_buf SS4END_inbuf_10 (
+	.A(SS4END[14]),
+	.X(SS4END_i[14])
+	);
+
+	my_buf SS4END_inbuf_11 (
+	.A(SS4END[15]),
+	.X(SS4END_i[15])
+	);
+
+	my_buf SS4BEG_outbuf_0 (
+	.A(SS4BEG_i[0]),
+	.X(SS4BEG[0])
+	);
+
+	my_buf SS4BEG_outbuf_1 (
+	.A(SS4BEG_i[1]),
+	.X(SS4BEG[1])
+	);
+
+	my_buf SS4BEG_outbuf_2 (
+	.A(SS4BEG_i[2]),
+	.X(SS4BEG[2])
+	);
+
+	my_buf SS4BEG_outbuf_3 (
+	.A(SS4BEG_i[3]),
+	.X(SS4BEG[3])
+	);
+
+	my_buf SS4BEG_outbuf_4 (
+	.A(SS4BEG_i[4]),
+	.X(SS4BEG[4])
+	);
+
+	my_buf SS4BEG_outbuf_5 (
+	.A(SS4BEG_i[5]),
+	.X(SS4BEG[5])
+	);
+
+	my_buf SS4BEG_outbuf_6 (
+	.A(SS4BEG_i[6]),
+	.X(SS4BEG[6])
+	);
+
+	my_buf SS4BEG_outbuf_7 (
+	.A(SS4BEG_i[7]),
+	.X(SS4BEG[7])
+	);
+
+	my_buf SS4BEG_outbuf_8 (
+	.A(SS4BEG_i[8]),
+	.X(SS4BEG[8])
+	);
+
+	my_buf SS4BEG_outbuf_9 (
+	.A(SS4BEG_i[9]),
+	.X(SS4BEG[9])
+	);
+
+	my_buf SS4BEG_outbuf_10 (
+	.A(SS4BEG_i[10]),
+	.X(SS4BEG[10])
+	);
+
+	my_buf SS4BEG_outbuf_11 (
+	.A(SS4BEG_i[11]),
+	.X(SS4BEG[11])
+	);
+
+	wire [15:0] WW4END_i;
+	wire [11:0] WW4BEG_i;
+	assign WW4BEG_i[15-4:0] = WW4END_i[15:4];
+
+	my_buf WW4END_inbuf_0 (
+	.A(WW4END[4]),
+	.X(WW4END_i[4])
+	);
+
+	my_buf WW4END_inbuf_1 (
+	.A(WW4END[5]),
+	.X(WW4END_i[5])
+	);
+
+	my_buf WW4END_inbuf_2 (
+	.A(WW4END[6]),
+	.X(WW4END_i[6])
+	);
+
+	my_buf WW4END_inbuf_3 (
+	.A(WW4END[7]),
+	.X(WW4END_i[7])
+	);
+
+	my_buf WW4END_inbuf_4 (
+	.A(WW4END[8]),
+	.X(WW4END_i[8])
+	);
+
+	my_buf WW4END_inbuf_5 (
+	.A(WW4END[9]),
+	.X(WW4END_i[9])
+	);
+
+	my_buf WW4END_inbuf_6 (
+	.A(WW4END[10]),
+	.X(WW4END_i[10])
+	);
+
+	my_buf WW4END_inbuf_7 (
+	.A(WW4END[11]),
+	.X(WW4END_i[11])
+	);
+
+	my_buf WW4END_inbuf_8 (
+	.A(WW4END[12]),
+	.X(WW4END_i[12])
+	);
+
+	my_buf WW4END_inbuf_9 (
+	.A(WW4END[13]),
+	.X(WW4END_i[13])
+	);
+
+	my_buf WW4END_inbuf_10 (
+	.A(WW4END[14]),
+	.X(WW4END_i[14])
+	);
+
+	my_buf WW4END_inbuf_11 (
+	.A(WW4END[15]),
+	.X(WW4END_i[15])
+	);
+
+	my_buf WW4BEG_outbuf_0 (
+	.A(WW4BEG_i[0]),
+	.X(WW4BEG[0])
+	);
+
+	my_buf WW4BEG_outbuf_1 (
+	.A(WW4BEG_i[1]),
+	.X(WW4BEG[1])
+	);
+
+	my_buf WW4BEG_outbuf_2 (
+	.A(WW4BEG_i[2]),
+	.X(WW4BEG[2])
+	);
+
+	my_buf WW4BEG_outbuf_3 (
+	.A(WW4BEG_i[3]),
+	.X(WW4BEG[3])
+	);
+
+	my_buf WW4BEG_outbuf_4 (
+	.A(WW4BEG_i[4]),
+	.X(WW4BEG[4])
+	);
+
+	my_buf WW4BEG_outbuf_5 (
+	.A(WW4BEG_i[5]),
+	.X(WW4BEG[5])
+	);
+
+	my_buf WW4BEG_outbuf_6 (
+	.A(WW4BEG_i[6]),
+	.X(WW4BEG[6])
+	);
+
+	my_buf WW4BEG_outbuf_7 (
+	.A(WW4BEG_i[7]),
+	.X(WW4BEG[7])
+	);
+
+	my_buf WW4BEG_outbuf_8 (
+	.A(WW4BEG_i[8]),
+	.X(WW4BEG[8])
+	);
+
+	my_buf WW4BEG_outbuf_9 (
+	.A(WW4BEG_i[9]),
+	.X(WW4BEG[9])
+	);
+
+	my_buf WW4BEG_outbuf_10 (
+	.A(WW4BEG_i[10]),
+	.X(WW4BEG[10])
+	);
+
+	my_buf WW4BEG_outbuf_11 (
+	.A(WW4BEG_i[11]),
+	.X(WW4BEG[11])
+	);
+
+	wire [11:0] W6END_i;
+	wire [9:0] W6BEG_i;
+	assign W6BEG_i[11-2:0] = W6END_i[11:2];
+
+	my_buf W6END_inbuf_0 (
+	.A(W6END[2]),
+	.X(W6END_i[2])
+	);
+
+	my_buf W6END_inbuf_1 (
+	.A(W6END[3]),
+	.X(W6END_i[3])
+	);
+
+	my_buf W6END_inbuf_2 (
+	.A(W6END[4]),
+	.X(W6END_i[4])
+	);
+
+	my_buf W6END_inbuf_3 (
+	.A(W6END[5]),
+	.X(W6END_i[5])
+	);
+
+	my_buf W6END_inbuf_4 (
+	.A(W6END[6]),
+	.X(W6END_i[6])
+	);
+
+	my_buf W6END_inbuf_5 (
+	.A(W6END[7]),
+	.X(W6END_i[7])
+	);
+
+	my_buf W6END_inbuf_6 (
+	.A(W6END[8]),
+	.X(W6END_i[8])
+	);
+
+	my_buf W6END_inbuf_7 (
+	.A(W6END[9]),
+	.X(W6END_i[9])
+	);
+
+	my_buf W6END_inbuf_8 (
+	.A(W6END[10]),
+	.X(W6END_i[10])
+	);
+
+	my_buf W6END_inbuf_9 (
+	.A(W6END[11]),
+	.X(W6END_i[11])
+	);
+
+	my_buf W6BEG_outbuf_0 (
+	.A(W6BEG_i[0]),
+	.X(W6BEG[0])
+	);
+
+	my_buf W6BEG_outbuf_1 (
+	.A(W6BEG_i[1]),
+	.X(W6BEG[1])
+	);
+
+	my_buf W6BEG_outbuf_2 (
+	.A(W6BEG_i[2]),
+	.X(W6BEG[2])
+	);
+
+	my_buf W6BEG_outbuf_3 (
+	.A(W6BEG_i[3]),
+	.X(W6BEG[3])
+	);
+
+	my_buf W6BEG_outbuf_4 (
+	.A(W6BEG_i[4]),
+	.X(W6BEG[4])
+	);
+
+	my_buf W6BEG_outbuf_5 (
+	.A(W6BEG_i[5]),
+	.X(W6BEG[5])
+	);
+
+	my_buf W6BEG_outbuf_6 (
+	.A(W6BEG_i[6]),
+	.X(W6BEG[6])
+	);
+
+	my_buf W6BEG_outbuf_7 (
+	.A(W6BEG_i[7]),
+	.X(W6BEG[7])
+	);
+
+	my_buf W6BEG_outbuf_8 (
+	.A(W6BEG_i[8]),
+	.X(W6BEG[8])
+	);
+
+	my_buf W6BEG_outbuf_9 (
+	.A(W6BEG_i[9]),
+	.X(W6BEG[9])
+	);
+
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	DSP_top_ConfigMem Inst_DSP_top_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	DSP_top_switch_matrix Inst_DSP_top_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.bot2top0(bot2top[0]),
+	.bot2top1(bot2top[1]),
+	.bot2top2(bot2top[2]),
+	.bot2top3(bot2top[3]),
+	.bot2top4(bot2top[4]),
+	.bot2top5(bot2top[5]),
+	.bot2top6(bot2top[6]),
+	.bot2top7(bot2top[7]),
+	.bot2top8(bot2top[8]),
+	.bot2top9(bot2top[9]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.J2MID_ABa_END0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_END1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_END2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_END3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_END0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_END1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_END2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_END3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_END0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_END1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_END2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_END3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_END0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_END1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_END2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_END3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_END0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_END1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_END2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_END3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_END0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_END1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_END2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_END3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_END0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_END1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_END2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_END3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_END0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_END1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_END2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_END3(J2MID_GHb_BEG[3]),
+	.J2END_AB_END0(J2END_AB_BEG[0]),
+	.J2END_AB_END1(J2END_AB_BEG[1]),
+	.J2END_AB_END2(J2END_AB_BEG[2]),
+	.J2END_AB_END3(J2END_AB_BEG[3]),
+	.J2END_CD_END0(J2END_CD_BEG[0]),
+	.J2END_CD_END1(J2END_CD_BEG[1]),
+	.J2END_CD_END2(J2END_CD_BEG[2]),
+	.J2END_CD_END3(J2END_CD_BEG[3]),
+	.J2END_EF_END0(J2END_EF_BEG[0]),
+	.J2END_EF_END1(J2END_EF_BEG[1]),
+	.J2END_EF_END2(J2END_EF_BEG[2]),
+	.J2END_EF_END3(J2END_EF_BEG[3]),
+	.J2END_GH_END0(J2END_GH_BEG[0]),
+	.J2END_GH_END1(J2END_GH_BEG[1]),
+	.J2END_GH_END2(J2END_GH_BEG[2]),
+	.J2END_GH_END3(J2END_GH_BEG[3]),
+	.JN2END0(JN2BEG[0]),
+	.JN2END1(JN2BEG[1]),
+	.JN2END2(JN2BEG[2]),
+	.JN2END3(JN2BEG[3]),
+	.JN2END4(JN2BEG[4]),
+	.JN2END5(JN2BEG[5]),
+	.JN2END6(JN2BEG[6]),
+	.JN2END7(JN2BEG[7]),
+	.JE2END0(JE2BEG[0]),
+	.JE2END1(JE2BEG[1]),
+	.JE2END2(JE2BEG[2]),
+	.JE2END3(JE2BEG[3]),
+	.JE2END4(JE2BEG[4]),
+	.JE2END5(JE2BEG[5]),
+	.JE2END6(JE2BEG[6]),
+	.JE2END7(JE2BEG[7]),
+	.JS2END0(JS2BEG[0]),
+	.JS2END1(JS2BEG[1]),
+	.JS2END2(JS2BEG[2]),
+	.JS2END3(JS2BEG[3]),
+	.JS2END4(JS2BEG[4]),
+	.JS2END5(JS2BEG[5]),
+	.JS2END6(JS2BEG[6]),
+	.JS2END7(JS2BEG[7]),
+	.JW2END0(JW2BEG[0]),
+	.JW2END1(JW2BEG[1]),
+	.JW2END2(JW2BEG[2]),
+	.JW2END3(JW2BEG[3]),
+	.JW2END4(JW2BEG[4]),
+	.JW2END5(JW2BEG[5]),
+	.JW2END6(JW2BEG[6]),
+	.JW2END7(JW2BEG[7]),
+	.J_l_AB_END0(J_l_AB_BEG[0]),
+	.J_l_AB_END1(J_l_AB_BEG[1]),
+	.J_l_AB_END2(J_l_AB_BEG[2]),
+	.J_l_AB_END3(J_l_AB_BEG[3]),
+	.J_l_CD_END0(J_l_CD_BEG[0]),
+	.J_l_CD_END1(J_l_CD_BEG[1]),
+	.J_l_CD_END2(J_l_CD_BEG[2]),
+	.J_l_CD_END3(J_l_CD_BEG[3]),
+	.J_l_EF_END0(J_l_EF_BEG[0]),
+	.J_l_EF_END1(J_l_EF_BEG[1]),
+	.J_l_EF_END2(J_l_EF_BEG[2]),
+	.J_l_EF_END3(J_l_EF_BEG[3]),
+	.J_l_GH_END0(J_l_GH_BEG[0]),
+	.J_l_GH_END1(J_l_GH_BEG[1]),
+	.J_l_GH_END2(J_l_GH_BEG[2]),
+	.J_l_GH_END3(J_l_GH_BEG[3]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[12]),
+	.N4BEG1(N4BEG[13]),
+	.N4BEG2(N4BEG[14]),
+	.N4BEG3(N4BEG[15]),
+	.NN4BEG0(NN4BEG[12]),
+	.NN4BEG1(NN4BEG[13]),
+	.NN4BEG2(NN4BEG[14]),
+	.NN4BEG3(NN4BEG[15]),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[12]),
+	.EE4BEG1(EE4BEG[13]),
+	.EE4BEG2(EE4BEG[14]),
+	.EE4BEG3(EE4BEG[15]),
+	.E6BEG0(E6BEG[10]),
+	.E6BEG1(E6BEG[11]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[12]),
+	.S4BEG1(S4BEG[13]),
+	.S4BEG2(S4BEG[14]),
+	.S4BEG3(S4BEG[15]),
+	.SS4BEG0(SS4BEG[12]),
+	.SS4BEG1(SS4BEG[13]),
+	.SS4BEG2(SS4BEG[14]),
+	.SS4BEG3(SS4BEG[15]),
+	.top2bot0(top2bot[0]),
+	.top2bot1(top2bot[1]),
+	.top2bot2(top2bot[2]),
+	.top2bot3(top2bot[3]),
+	.top2bot4(top2bot[4]),
+	.top2bot5(top2bot[5]),
+	.top2bot6(top2bot[6]),
+	.top2bot7(top2bot[7]),
+	.top2bot8(top2bot[8]),
+	.top2bot9(top2bot[9]),
+	.top2bot10(top2bot[10]),
+	.top2bot11(top2bot[11]),
+	.top2bot12(top2bot[12]),
+	.top2bot13(top2bot[13]),
+	.top2bot14(top2bot[14]),
+	.top2bot15(top2bot[15]),
+	.top2bot16(top2bot[16]),
+	.top2bot17(top2bot[17]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[12]),
+	.WW4BEG1(WW4BEG[13]),
+	.WW4BEG2(WW4BEG[14]),
+	.WW4BEG3(WW4BEG[15]),
+	.W6BEG0(W6BEG[10]),
+	.W6BEG1(W6BEG[11]),
+	.J2MID_ABa_BEG0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_BEG1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_BEG2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_BEG3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_BEG0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_BEG1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_BEG2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_BEG3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_BEG0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_BEG1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_BEG2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_BEG3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_BEG0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_BEG1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_BEG2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_BEG3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_BEG0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_BEG1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_BEG2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_BEG3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_BEG0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_BEG1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_BEG2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_BEG3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_BEG0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_BEG1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_BEG2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_BEG3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_BEG0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_BEG1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_BEG2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_BEG3(J2MID_GHb_BEG[3]),
+	.J2END_AB_BEG0(J2END_AB_BEG[0]),
+	.J2END_AB_BEG1(J2END_AB_BEG[1]),
+	.J2END_AB_BEG2(J2END_AB_BEG[2]),
+	.J2END_AB_BEG3(J2END_AB_BEG[3]),
+	.J2END_CD_BEG0(J2END_CD_BEG[0]),
+	.J2END_CD_BEG1(J2END_CD_BEG[1]),
+	.J2END_CD_BEG2(J2END_CD_BEG[2]),
+	.J2END_CD_BEG3(J2END_CD_BEG[3]),
+	.J2END_EF_BEG0(J2END_EF_BEG[0]),
+	.J2END_EF_BEG1(J2END_EF_BEG[1]),
+	.J2END_EF_BEG2(J2END_EF_BEG[2]),
+	.J2END_EF_BEG3(J2END_EF_BEG[3]),
+	.J2END_GH_BEG0(J2END_GH_BEG[0]),
+	.J2END_GH_BEG1(J2END_GH_BEG[1]),
+	.J2END_GH_BEG2(J2END_GH_BEG[2]),
+	.J2END_GH_BEG3(J2END_GH_BEG[3]),
+	.JN2BEG0(JN2BEG[0]),
+	.JN2BEG1(JN2BEG[1]),
+	.JN2BEG2(JN2BEG[2]),
+	.JN2BEG3(JN2BEG[3]),
+	.JN2BEG4(JN2BEG[4]),
+	.JN2BEG5(JN2BEG[5]),
+	.JN2BEG6(JN2BEG[6]),
+	.JN2BEG7(JN2BEG[7]),
+	.JE2BEG0(JE2BEG[0]),
+	.JE2BEG1(JE2BEG[1]),
+	.JE2BEG2(JE2BEG[2]),
+	.JE2BEG3(JE2BEG[3]),
+	.JE2BEG4(JE2BEG[4]),
+	.JE2BEG5(JE2BEG[5]),
+	.JE2BEG6(JE2BEG[6]),
+	.JE2BEG7(JE2BEG[7]),
+	.JS2BEG0(JS2BEG[0]),
+	.JS2BEG1(JS2BEG[1]),
+	.JS2BEG2(JS2BEG[2]),
+	.JS2BEG3(JS2BEG[3]),
+	.JS2BEG4(JS2BEG[4]),
+	.JS2BEG5(JS2BEG[5]),
+	.JS2BEG6(JS2BEG[6]),
+	.JS2BEG7(JS2BEG[7]),
+	.JW2BEG0(JW2BEG[0]),
+	.JW2BEG1(JW2BEG[1]),
+	.JW2BEG2(JW2BEG[2]),
+	.JW2BEG3(JW2BEG[3]),
+	.JW2BEG4(JW2BEG[4]),
+	.JW2BEG5(JW2BEG[5]),
+	.JW2BEG6(JW2BEG[6]),
+	.JW2BEG7(JW2BEG[7]),
+	.J_l_AB_BEG0(J_l_AB_BEG[0]),
+	.J_l_AB_BEG1(J_l_AB_BEG[1]),
+	.J_l_AB_BEG2(J_l_AB_BEG[2]),
+	.J_l_AB_BEG3(J_l_AB_BEG[3]),
+	.J_l_CD_BEG0(J_l_CD_BEG[0]),
+	.J_l_CD_BEG1(J_l_CD_BEG[1]),
+	.J_l_CD_BEG2(J_l_CD_BEG[2]),
+	.J_l_CD_BEG3(J_l_CD_BEG[3]),
+	.J_l_EF_BEG0(J_l_EF_BEG[0]),
+	.J_l_EF_BEG1(J_l_EF_BEG[1]),
+	.J_l_EF_BEG2(J_l_EF_BEG[2]),
+	.J_l_EF_BEG3(J_l_EF_BEG[3]),
+	.J_l_GH_BEG0(J_l_GH_BEG[0]),
+	.J_l_GH_BEG1(J_l_GH_BEG[1]),
+	.J_l_GH_BEG2(J_l_GH_BEG[2]),
+	.J_l_GH_BEG3(J_l_GH_BEG[3]),
+	.ConfigBits(ConfigBits[406-1:0]),
+	.ConfigBits_N(ConfigBits_N[406-1:0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_ConfigMem.v b/verilog/rtl/eFPGA_core/E_CPU_IO_ConfigMem.v
new file mode 100644
index 0000000..56b07d6
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_ConfigMem.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module E_CPU_IO_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [20-1:0] frame0;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_bot_ConfigMem.v b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_ConfigMem.v
new file mode 100644
index 0000000..727f867
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_ConfigMem.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module E_CPU_IO_bot_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [20-1:0] frame0;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_bot_switch_matrix.v b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_switch_matrix.v
new file mode 100644
index 0000000..05ccd10
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_switch_matrix.v
@@ -0,0 +1,594 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module E_CPU_IO_bot_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, NN4END0, NN4END1, NN4END2, NN4END3, NN4END4, NN4END5, NN4END6, NN4END7, NN4END8, NN4END9, NN4END10, NN4END11, NN4END12, NN4END13, NN4END14, NN4END15, Ci0, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, EE4END4, EE4END5, EE4END6, EE4END7, EE4END8, EE4END9, EE4END10, EE4END11, EE4END12, EE4END13, EE4END14, EE4END15, E6END0, E6END1, E6END2, E6END3, E6END4, E6END5, E6END6, E6END7, E6END8, E6END9, E6END10, E6END11, OPA_O0, OPA_O1, OPA_O2, OPA_O3, OPB_O0, OPB_O1, OPB_O2, OPB_O3, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, SS4BEG4, SS4BEG5, SS4BEG6, SS4BEG7, SS4BEG8, SS4BEG9, SS4BEG10, SS4BEG11, SS4BEG12, SS4BEG13, SS4BEG14, SS4BEG15, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, WW4BEG4, WW4BEG5, WW4BEG6, WW4BEG7, WW4BEG8, WW4BEG9, WW4BEG10, WW4BEG11, WW4BEG12, WW4BEG13, WW4BEG14, WW4BEG15, W6BEG0, W6BEG1, W6BEG2, W6BEG3, W6BEG4, W6BEG5, W6BEG6, W6BEG7, W6BEG8, W6BEG9, W6BEG10, W6BEG11, RES0_I0, RES0_I1, RES0_I2, RES0_I3, RES1_I0, RES1_I1, RES1_I2, RES1_I3, RES2_I0, RES2_I1, RES2_I2, RES2_I3);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input NN4END4;
+	input NN4END5;
+	input NN4END6;
+	input NN4END7;
+	input NN4END8;
+	input NN4END9;
+	input NN4END10;
+	input NN4END11;
+	input NN4END12;
+	input NN4END13;
+	input NN4END14;
+	input NN4END15;
+	input Ci0;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input EE4END4;
+	input EE4END5;
+	input EE4END6;
+	input EE4END7;
+	input EE4END8;
+	input EE4END9;
+	input EE4END10;
+	input EE4END11;
+	input EE4END12;
+	input EE4END13;
+	input EE4END14;
+	input EE4END15;
+	input E6END0;
+	input E6END1;
+	input E6END2;
+	input E6END3;
+	input E6END4;
+	input E6END5;
+	input E6END6;
+	input E6END7;
+	input E6END8;
+	input E6END9;
+	input E6END10;
+	input E6END11;
+	input OPA_O0;
+	input OPA_O1;
+	input OPA_O2;
+	input OPA_O3;
+	input OPB_O0;
+	input OPB_O1;
+	input OPB_O2;
+	input OPB_O3;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output SS4BEG4;
+	output SS4BEG5;
+	output SS4BEG6;
+	output SS4BEG7;
+	output SS4BEG8;
+	output SS4BEG9;
+	output SS4BEG10;
+	output SS4BEG11;
+	output SS4BEG12;
+	output SS4BEG13;
+	output SS4BEG14;
+	output SS4BEG15;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output WW4BEG4;
+	output WW4BEG5;
+	output WW4BEG6;
+	output WW4BEG7;
+	output WW4BEG8;
+	output WW4BEG9;
+	output WW4BEG10;
+	output WW4BEG11;
+	output WW4BEG12;
+	output WW4BEG13;
+	output WW4BEG14;
+	output WW4BEG15;
+	output W6BEG0;
+	output W6BEG1;
+	output W6BEG2;
+	output W6BEG3;
+	output W6BEG4;
+	output W6BEG5;
+	output W6BEG6;
+	output W6BEG7;
+	output W6BEG8;
+	output W6BEG9;
+	output W6BEG10;
+	output W6BEG11;
+	output RES0_I0;
+	output RES0_I1;
+	output RES0_I2;
+	output RES0_I3;
+	output RES1_I0;
+	output RES1_I1;
+	output RES1_I2;
+	output RES1_I3;
+	output RES2_I0;
+	output RES2_I1;
+	output RES2_I2;
+	output RES2_I3;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+	wire [1-1:0] SS4BEG0_input;
+	wire [1-1:0] SS4BEG1_input;
+	wire [1-1:0] SS4BEG2_input;
+	wire [1-1:0] SS4BEG3_input;
+	wire [1-1:0] SS4BEG4_input;
+	wire [1-1:0] SS4BEG5_input;
+	wire [1-1:0] SS4BEG6_input;
+	wire [1-1:0] SS4BEG7_input;
+	wire [1-1:0] SS4BEG8_input;
+	wire [1-1:0] SS4BEG9_input;
+	wire [1-1:0] SS4BEG10_input;
+	wire [1-1:0] SS4BEG11_input;
+	wire [1-1:0] SS4BEG12_input;
+	wire [1-1:0] SS4BEG13_input;
+	wire [1-1:0] SS4BEG14_input;
+	wire [1-1:0] SS4BEG15_input;
+	wire [1-1:0] W1BEG0_input;
+	wire [1-1:0] W1BEG1_input;
+	wire [1-1:0] W1BEG2_input;
+	wire [1-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [0-1:0] WW4BEG0_input;
+	wire [0-1:0] WW4BEG1_input;
+	wire [0-1:0] WW4BEG2_input;
+	wire [0-1:0] WW4BEG3_input;
+	wire [0-1:0] WW4BEG4_input;
+	wire [0-1:0] WW4BEG5_input;
+	wire [0-1:0] WW4BEG6_input;
+	wire [0-1:0] WW4BEG7_input;
+	wire [0-1:0] WW4BEG8_input;
+	wire [0-1:0] WW4BEG9_input;
+	wire [0-1:0] WW4BEG10_input;
+	wire [0-1:0] WW4BEG11_input;
+	wire [0-1:0] WW4BEG12_input;
+	wire [0-1:0] WW4BEG13_input;
+	wire [0-1:0] WW4BEG14_input;
+	wire [0-1:0] WW4BEG15_input;
+	wire [1-1:0] W6BEG0_input;
+	wire [1-1:0] W6BEG1_input;
+	wire [1-1:0] W6BEG2_input;
+	wire [1-1:0] W6BEG3_input;
+	wire [1-1:0] W6BEG4_input;
+	wire [1-1:0] W6BEG5_input;
+	wire [1-1:0] W6BEG6_input;
+	wire [1-1:0] W6BEG7_input;
+	wire [1-1:0] W6BEG8_input;
+	wire [1-1:0] W6BEG9_input;
+	wire [1-1:0] W6BEG10_input;
+	wire [1-1:0] W6BEG11_input;
+	wire [1-1:0] RES0_I0_input;
+	wire [1-1:0] RES0_I1_input;
+	wire [1-1:0] RES0_I2_input;
+	wire [1-1:0] RES0_I3_input;
+	wire [1-1:0] RES1_I0_input;
+	wire [1-1:0] RES1_I1_input;
+	wire [1-1:0] RES1_I2_input;
+	wire [1-1:0] RES1_I3_input;
+	wire [1-1:0] RES2_I0_input;
+	wire [1-1:0] RES2_I1_input;
+	wire [1-1:0] RES2_I2_input;
+	wire [1-1:0] RES2_I3_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+// switch matrix multiplexer  SS4BEG0 		MUX-1
+	assign SS4BEG0 = NN4END15;
+// switch matrix multiplexer  SS4BEG1 		MUX-1
+	assign SS4BEG1 = NN4END14;
+// switch matrix multiplexer  SS4BEG2 		MUX-1
+	assign SS4BEG2 = NN4END13;
+// switch matrix multiplexer  SS4BEG3 		MUX-1
+	assign SS4BEG3 = NN4END12;
+// switch matrix multiplexer  SS4BEG4 		MUX-1
+	assign SS4BEG4 = NN4END11;
+// switch matrix multiplexer  SS4BEG5 		MUX-1
+	assign SS4BEG5 = NN4END10;
+// switch matrix multiplexer  SS4BEG6 		MUX-1
+	assign SS4BEG6 = NN4END9;
+// switch matrix multiplexer  SS4BEG7 		MUX-1
+	assign SS4BEG7 = NN4END8;
+// switch matrix multiplexer  SS4BEG8 		MUX-1
+	assign SS4BEG8 = NN4END7;
+// switch matrix multiplexer  SS4BEG9 		MUX-1
+	assign SS4BEG9 = NN4END6;
+// switch matrix multiplexer  SS4BEG10 		MUX-1
+	assign SS4BEG10 = NN4END5;
+// switch matrix multiplexer  SS4BEG11 		MUX-1
+	assign SS4BEG11 = NN4END4;
+// switch matrix multiplexer  SS4BEG12 		MUX-1
+	assign SS4BEG12 = NN4END3;
+// switch matrix multiplexer  SS4BEG13 		MUX-1
+	assign SS4BEG13 = NN4END2;
+// switch matrix multiplexer  SS4BEG14 		MUX-1
+	assign SS4BEG14 = NN4END1;
+// switch matrix multiplexer  SS4BEG15 		MUX-1
+	assign SS4BEG15 = NN4END0;
+// switch matrix multiplexer  W1BEG0 		MUX-1
+	assign W1BEG0 = E1END3;
+// switch matrix multiplexer  W1BEG1 		MUX-1
+	assign W1BEG1 = E1END2;
+// switch matrix multiplexer  W1BEG2 		MUX-1
+	assign W1BEG2 = E1END1;
+// switch matrix multiplexer  W1BEG3 		MUX-1
+	assign W1BEG3 = E1END0;
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = OPB_O0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = E2MID6;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = E2MID5;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = OPB_O1;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = OPB_O2;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = E2MID2;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = E2MID1;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = OPB_O3;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = OPA_O0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = E2END6;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = E2END5;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = OPA_O1;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = OPA_O2;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = E2END2;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = E2END1;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = OPA_O3;
+// switch matrix multiplexer  WW4BEG0 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG0
+// switch matrix multiplexer  WW4BEG1 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG1
+// switch matrix multiplexer  WW4BEG2 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG2
+// switch matrix multiplexer  WW4BEG3 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG3
+// switch matrix multiplexer  WW4BEG4 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG4
+// switch matrix multiplexer  WW4BEG5 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG5
+// switch matrix multiplexer  WW4BEG6 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG6
+// switch matrix multiplexer  WW4BEG7 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG7
+// switch matrix multiplexer  WW4BEG8 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG8
+// switch matrix multiplexer  WW4BEG9 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG9
+// switch matrix multiplexer  WW4BEG10 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG10
+// switch matrix multiplexer  WW4BEG11 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG11
+// switch matrix multiplexer  WW4BEG12 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG12
+// switch matrix multiplexer  WW4BEG13 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG13
+// switch matrix multiplexer  WW4BEG14 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG14
+// switch matrix multiplexer  WW4BEG15 		MUX-0
+// WARNING unused multiplexer MUX-WW4BEG15
+// switch matrix multiplexer  W6BEG0 		MUX-1
+	assign W6BEG0 = OPA_O0;
+// switch matrix multiplexer  W6BEG1 		MUX-1
+	assign W6BEG1 = OPA_O1;
+// switch matrix multiplexer  W6BEG2 		MUX-1
+	assign W6BEG2 = OPB_O0;
+// switch matrix multiplexer  W6BEG3 		MUX-1
+	assign W6BEG3 = OPB_O1;
+// switch matrix multiplexer  W6BEG4 		MUX-1
+	assign W6BEG4 = GND0;
+// switch matrix multiplexer  W6BEG5 		MUX-1
+	assign W6BEG5 = GND0;
+// switch matrix multiplexer  W6BEG6 		MUX-1
+	assign W6BEG6 = OPA_O2;
+// switch matrix multiplexer  W6BEG7 		MUX-1
+	assign W6BEG7 = OPA_O3;
+// switch matrix multiplexer  W6BEG8 		MUX-1
+	assign W6BEG8 = OPB_O2;
+// switch matrix multiplexer  W6BEG9 		MUX-1
+	assign W6BEG9 = OPB_O3;
+// switch matrix multiplexer  W6BEG10 		MUX-1
+	assign W6BEG10 = GND0;
+// switch matrix multiplexer  W6BEG11 		MUX-1
+	assign W6BEG11 = GND0;
+// switch matrix multiplexer  RES0_I0 		MUX-1
+	assign RES0_I0 = E6END0;
+// switch matrix multiplexer  RES0_I1 		MUX-1
+	assign RES0_I1 = E6END1;
+// switch matrix multiplexer  RES0_I2 		MUX-1
+	assign RES0_I2 = E6END2;
+// switch matrix multiplexer  RES0_I3 		MUX-1
+	assign RES0_I3 = E6END3;
+// switch matrix multiplexer  RES1_I0 		MUX-1
+	assign RES1_I0 = E6END4;
+// switch matrix multiplexer  RES1_I1 		MUX-1
+	assign RES1_I1 = E6END5;
+// switch matrix multiplexer  RES1_I2 		MUX-1
+	assign RES1_I2 = E6END6;
+// switch matrix multiplexer  RES1_I3 		MUX-1
+	assign RES1_I3 = E6END7;
+// switch matrix multiplexer  RES2_I0 		MUX-1
+	assign RES2_I0 = E6END8;
+// switch matrix multiplexer  RES2_I1 		MUX-1
+	assign RES2_I1 = E6END9;
+// switch matrix multiplexer  RES2_I2 		MUX-1
+	assign RES2_I2 = E6END10;
+// switch matrix multiplexer  RES2_I3 		MUX-1
+	assign RES2_I3 = E6END11;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_bot_tile.v b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_tile.v
new file mode 100644
index 0000000..9e3731f
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_bot_tile.v
@@ -0,0 +1,939 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module E_CPU_IO_bot (N1END, N2MID, N2END, N4END, NN4END, Ci, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, OPA_I0, OPA_I1, OPA_I2, OPA_I3, UserCLK, OPB_I0, OPB_I1, OPB_I2, OPB_I3, RES0_O0, RES0_O1, RES0_O2, RES0_O3, RES1_O0, RES1_O1, RES1_O2, RES1_O3, RES2_O0, RES2_O1, RES2_O2, RES2_O3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:NN4END  
+	input [0:0] Ci; //wires:1 X_offset:0 Y_offset:1  source_name:NULL destination_name:Ci  
+	//  EAST
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:NULL destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:NULL destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:NULL destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:NULL  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:NULL  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:NULL  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:NULL  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:NULL  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:NULL  
+	// Tile IO ports from BELs
+	input OPA_I0;
+	input OPA_I1;
+	input OPA_I2;
+	input OPA_I3;
+	input UserCLK;
+	input OPB_I0;
+	input OPB_I1;
+	input OPB_I2;
+	input OPB_I3;
+	output RES0_O0;
+	output RES0_O1;
+	output RES0_O2;
+	output RES0_O3;
+	output RES1_O0;
+	output RES1_O1;
+	output RES1_O2;
+	output RES1_O3;
+	output RES2_O0;
+	output RES2_O1;
+	output RES2_O2;
+	output RES2_O3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire RES0_I0;
+	wire RES0_I1;
+	wire RES0_I2;
+	wire RES0_I3;
+	wire RES1_I0;
+	wire RES1_I1;
+	wire RES1_I2;
+	wire RES1_I3;
+	wire RES2_I0;
+	wire RES2_I1;
+	wire RES2_I2;
+	wire RES2_I3;
+	wire OPA_O0;
+	wire OPA_O1;
+	wire OPA_O2;
+	wire OPA_O3;
+	wire OPB_O0;
+	wire OPB_O1;
+	wire OPB_O2;
+	wire OPB_O3;
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	E_CPU_IO_bot_ConfigMem Inst_E_CPU_IO_bot_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	InPass4_frame_config Inst_OPA_InPass4_frame_config (
+	.O0(OPA_O0),
+	.O1(OPA_O1),
+	.O2(OPA_O2),
+	.O3(OPA_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPA_I0),
+	.I1(OPA_I1),
+	.I2(OPA_I2),
+	.I3(OPA_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	InPass4_frame_config Inst_OPB_InPass4_frame_config (
+	.O0(OPB_O0),
+	.O1(OPB_O1),
+	.O2(OPB_O2),
+	.O3(OPB_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPB_I0),
+	.I1(OPB_I1),
+	.I2(OPB_I2),
+	.I3(OPB_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+	OutPass4_frame_config Inst_RES0_OutPass4_frame_config (
+	.I0(RES0_I0),
+	.I1(RES0_I1),
+	.I2(RES0_I2),
+	.I3(RES0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES0_O0),
+	.O1(RES0_O1),
+	.O2(RES0_O2),
+	.O3(RES0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[12-1:8])
+	);
+
+	OutPass4_frame_config Inst_RES1_OutPass4_frame_config (
+	.I0(RES1_I0),
+	.I1(RES1_I1),
+	.I2(RES1_I2),
+	.I3(RES1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES1_O0),
+	.O1(RES1_O1),
+	.O2(RES1_O2),
+	.O3(RES1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[16-1:12])
+	);
+
+	OutPass4_frame_config Inst_RES2_OutPass4_frame_config (
+	.I0(RES2_I0),
+	.I1(RES2_I1),
+	.I2(RES2_I2),
+	.I3(RES2_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES2_O0),
+	.O1(RES2_O1),
+	.O2(RES2_O2),
+	.O3(RES2_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[20-1:16])
+	);
+
+
+//switch matrix component instantiation
+	E_CPU_IO_bot_switch_matrix Inst_E_CPU_IO_bot_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.NN4END4(NN4END[4]),
+	.NN4END5(NN4END[5]),
+	.NN4END6(NN4END[6]),
+	.NN4END7(NN4END[7]),
+	.NN4END8(NN4END[8]),
+	.NN4END9(NN4END[9]),
+	.NN4END10(NN4END[10]),
+	.NN4END11(NN4END[11]),
+	.NN4END12(NN4END[12]),
+	.NN4END13(NN4END[13]),
+	.NN4END14(NN4END[14]),
+	.NN4END15(NN4END[15]),
+	.Ci0(Ci[0]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.EE4END4(EE4END[4]),
+	.EE4END5(EE4END[5]),
+	.EE4END6(EE4END[6]),
+	.EE4END7(EE4END[7]),
+	.EE4END8(EE4END[8]),
+	.EE4END9(EE4END[9]),
+	.EE4END10(EE4END[10]),
+	.EE4END11(EE4END[11]),
+	.EE4END12(EE4END[12]),
+	.EE4END13(EE4END[13]),
+	.EE4END14(EE4END[14]),
+	.EE4END15(EE4END[15]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.E6END2(E6END[2]),
+	.E6END3(E6END[3]),
+	.E6END4(E6END[4]),
+	.E6END5(E6END[5]),
+	.E6END6(E6END[6]),
+	.E6END7(E6END[7]),
+	.E6END8(E6END[8]),
+	.E6END9(E6END[9]),
+	.E6END10(E6END[10]),
+	.E6END11(E6END[11]),
+	.OPA_O0(OPA_O0),
+	.OPA_O1(OPA_O1),
+	.OPA_O2(OPA_O2),
+	.OPA_O3(OPA_O3),
+	.OPB_O0(OPB_O0),
+	.OPB_O1(OPB_O1),
+	.OPB_O2(OPB_O2),
+	.OPB_O3(OPB_O3),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15]),
+	.SS4BEG0(SS4BEG[0]),
+	.SS4BEG1(SS4BEG[1]),
+	.SS4BEG2(SS4BEG[2]),
+	.SS4BEG3(SS4BEG[3]),
+	.SS4BEG4(SS4BEG[4]),
+	.SS4BEG5(SS4BEG[5]),
+	.SS4BEG6(SS4BEG[6]),
+	.SS4BEG7(SS4BEG[7]),
+	.SS4BEG8(SS4BEG[8]),
+	.SS4BEG9(SS4BEG[9]),
+	.SS4BEG10(SS4BEG[10]),
+	.SS4BEG11(SS4BEG[11]),
+	.SS4BEG12(SS4BEG[12]),
+	.SS4BEG13(SS4BEG[13]),
+	.SS4BEG14(SS4BEG[14]),
+	.SS4BEG15(SS4BEG[15]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[0]),
+	.WW4BEG1(WW4BEG[1]),
+	.WW4BEG2(WW4BEG[2]),
+	.WW4BEG3(WW4BEG[3]),
+	.WW4BEG4(WW4BEG[4]),
+	.WW4BEG5(WW4BEG[5]),
+	.WW4BEG6(WW4BEG[6]),
+	.WW4BEG7(WW4BEG[7]),
+	.WW4BEG8(WW4BEG[8]),
+	.WW4BEG9(WW4BEG[9]),
+	.WW4BEG10(WW4BEG[10]),
+	.WW4BEG11(WW4BEG[11]),
+	.WW4BEG12(WW4BEG[12]),
+	.WW4BEG13(WW4BEG[13]),
+	.WW4BEG14(WW4BEG[14]),
+	.WW4BEG15(WW4BEG[15]),
+	.W6BEG0(W6BEG[0]),
+	.W6BEG1(W6BEG[1]),
+	.W6BEG2(W6BEG[2]),
+	.W6BEG3(W6BEG[3]),
+	.W6BEG4(W6BEG[4]),
+	.W6BEG5(W6BEG[5]),
+	.W6BEG6(W6BEG[6]),
+	.W6BEG7(W6BEG[7]),
+	.W6BEG8(W6BEG[8]),
+	.W6BEG9(W6BEG[9]),
+	.W6BEG10(W6BEG[10]),
+	.W6BEG11(W6BEG[11]),
+	.RES0_I0(RES0_I0),
+	.RES0_I1(RES0_I1),
+	.RES0_I2(RES0_I2),
+	.RES0_I3(RES0_I3),
+	.RES1_I0(RES1_I0),
+	.RES1_I1(RES1_I1),
+	.RES1_I2(RES1_I2),
+	.RES1_I3(RES1_I3),
+	.RES2_I0(RES2_I0),
+	.RES2_I1(RES2_I1),
+	.RES2_I2(RES2_I2),
+	.RES2_I3(RES2_I3)
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/E_CPU_IO_switch_matrix.v
new file mode 100644
index 0000000..dd9a908
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_switch_matrix.v
@@ -0,0 +1,333 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module E_CPU_IO_switch_matrix (E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, EE4END4, EE4END5, EE4END6, EE4END7, EE4END8, EE4END9, EE4END10, EE4END11, EE4END12, EE4END13, EE4END14, EE4END15, E6END0, E6END1, E6END2, E6END3, E6END4, E6END5, E6END6, E6END7, E6END8, E6END9, E6END10, E6END11, OPA_O0, OPA_O1, OPA_O2, OPA_O3, OPB_O0, OPB_O1, OPB_O2, OPB_O3, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, WW4BEG4, WW4BEG5, WW4BEG6, WW4BEG7, WW4BEG8, WW4BEG9, WW4BEG10, WW4BEG11, WW4BEG12, WW4BEG13, WW4BEG14, WW4BEG15, W6BEG0, W6BEG1, W6BEG2, W6BEG3, W6BEG4, W6BEG5, W6BEG6, W6BEG7, W6BEG8, W6BEG9, W6BEG10, W6BEG11, RES0_I0, RES0_I1, RES0_I2, RES0_I3, RES1_I0, RES1_I1, RES1_I2, RES1_I3, RES2_I0, RES2_I1, RES2_I2, RES2_I3);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input EE4END4;
+	input EE4END5;
+	input EE4END6;
+	input EE4END7;
+	input EE4END8;
+	input EE4END9;
+	input EE4END10;
+	input EE4END11;
+	input EE4END12;
+	input EE4END13;
+	input EE4END14;
+	input EE4END15;
+	input E6END0;
+	input E6END1;
+	input E6END2;
+	input E6END3;
+	input E6END4;
+	input E6END5;
+	input E6END6;
+	input E6END7;
+	input E6END8;
+	input E6END9;
+	input E6END10;
+	input E6END11;
+	input OPA_O0;
+	input OPA_O1;
+	input OPA_O2;
+	input OPA_O3;
+	input OPB_O0;
+	input OPB_O1;
+	input OPB_O2;
+	input OPB_O3;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output WW4BEG4;
+	output WW4BEG5;
+	output WW4BEG6;
+	output WW4BEG7;
+	output WW4BEG8;
+	output WW4BEG9;
+	output WW4BEG10;
+	output WW4BEG11;
+	output WW4BEG12;
+	output WW4BEG13;
+	output WW4BEG14;
+	output WW4BEG15;
+	output W6BEG0;
+	output W6BEG1;
+	output W6BEG2;
+	output W6BEG3;
+	output W6BEG4;
+	output W6BEG5;
+	output W6BEG6;
+	output W6BEG7;
+	output W6BEG8;
+	output W6BEG9;
+	output W6BEG10;
+	output W6BEG11;
+	output RES0_I0;
+	output RES0_I1;
+	output RES0_I2;
+	output RES0_I3;
+	output RES1_I0;
+	output RES1_I1;
+	output RES1_I2;
+	output RES1_I3;
+	output RES2_I0;
+	output RES2_I1;
+	output RES2_I2;
+	output RES2_I3;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] W1BEG0_input;
+	wire [1-1:0] W1BEG1_input;
+	wire [1-1:0] W1BEG2_input;
+	wire [1-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [1-1:0] WW4BEG0_input;
+	wire [1-1:0] WW4BEG1_input;
+	wire [1-1:0] WW4BEG2_input;
+	wire [1-1:0] WW4BEG3_input;
+	wire [1-1:0] WW4BEG4_input;
+	wire [1-1:0] WW4BEG5_input;
+	wire [1-1:0] WW4BEG6_input;
+	wire [1-1:0] WW4BEG7_input;
+	wire [1-1:0] WW4BEG8_input;
+	wire [1-1:0] WW4BEG9_input;
+	wire [1-1:0] WW4BEG10_input;
+	wire [1-1:0] WW4BEG11_input;
+	wire [1-1:0] WW4BEG12_input;
+	wire [1-1:0] WW4BEG13_input;
+	wire [1-1:0] WW4BEG14_input;
+	wire [1-1:0] WW4BEG15_input;
+	wire [1-1:0] W6BEG0_input;
+	wire [1-1:0] W6BEG1_input;
+	wire [1-1:0] W6BEG2_input;
+	wire [1-1:0] W6BEG3_input;
+	wire [1-1:0] W6BEG4_input;
+	wire [1-1:0] W6BEG5_input;
+	wire [1-1:0] W6BEG6_input;
+	wire [1-1:0] W6BEG7_input;
+	wire [1-1:0] W6BEG8_input;
+	wire [1-1:0] W6BEG9_input;
+	wire [1-1:0] W6BEG10_input;
+	wire [1-1:0] W6BEG11_input;
+	wire [1-1:0] RES0_I0_input;
+	wire [1-1:0] RES0_I1_input;
+	wire [1-1:0] RES0_I2_input;
+	wire [1-1:0] RES0_I3_input;
+	wire [1-1:0] RES1_I0_input;
+	wire [1-1:0] RES1_I1_input;
+	wire [1-1:0] RES1_I2_input;
+	wire [1-1:0] RES1_I3_input;
+	wire [1-1:0] RES2_I0_input;
+	wire [1-1:0] RES2_I1_input;
+	wire [1-1:0] RES2_I2_input;
+	wire [1-1:0] RES2_I3_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  W1BEG0 		MUX-1
+	assign W1BEG0 = E1END3;
+// switch matrix multiplexer  W1BEG1 		MUX-1
+	assign W1BEG1 = E1END2;
+// switch matrix multiplexer  W1BEG2 		MUX-1
+	assign W1BEG2 = E1END1;
+// switch matrix multiplexer  W1BEG3 		MUX-1
+	assign W1BEG3 = E1END0;
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = OPB_O0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = E2MID6;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = E2MID5;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = OPB_O1;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = OPB_O2;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = E2MID2;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = E2MID1;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = OPB_O3;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = OPA_O0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = E2END6;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = E2END5;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = OPA_O1;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = OPA_O2;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = E2END2;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = E2END1;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = OPA_O3;
+// switch matrix multiplexer  WW4BEG0 		MUX-1
+	assign WW4BEG0 = EE4END15;
+// switch matrix multiplexer  WW4BEG1 		MUX-1
+	assign WW4BEG1 = EE4END14;
+// switch matrix multiplexer  WW4BEG2 		MUX-1
+	assign WW4BEG2 = EE4END13;
+// switch matrix multiplexer  WW4BEG3 		MUX-1
+	assign WW4BEG3 = EE4END12;
+// switch matrix multiplexer  WW4BEG4 		MUX-1
+	assign WW4BEG4 = EE4END11;
+// switch matrix multiplexer  WW4BEG5 		MUX-1
+	assign WW4BEG5 = EE4END10;
+// switch matrix multiplexer  WW4BEG6 		MUX-1
+	assign WW4BEG6 = EE4END9;
+// switch matrix multiplexer  WW4BEG7 		MUX-1
+	assign WW4BEG7 = EE4END8;
+// switch matrix multiplexer  WW4BEG8 		MUX-1
+	assign WW4BEG8 = EE4END7;
+// switch matrix multiplexer  WW4BEG9 		MUX-1
+	assign WW4BEG9 = EE4END6;
+// switch matrix multiplexer  WW4BEG10 		MUX-1
+	assign WW4BEG10 = EE4END5;
+// switch matrix multiplexer  WW4BEG11 		MUX-1
+	assign WW4BEG11 = EE4END4;
+// switch matrix multiplexer  WW4BEG12 		MUX-1
+	assign WW4BEG12 = EE4END3;
+// switch matrix multiplexer  WW4BEG13 		MUX-1
+	assign WW4BEG13 = EE4END2;
+// switch matrix multiplexer  WW4BEG14 		MUX-1
+	assign WW4BEG14 = EE4END1;
+// switch matrix multiplexer  WW4BEG15 		MUX-1
+	assign WW4BEG15 = EE4END0;
+// switch matrix multiplexer  W6BEG0 		MUX-1
+	assign W6BEG0 = OPA_O0;
+// switch matrix multiplexer  W6BEG1 		MUX-1
+	assign W6BEG1 = OPA_O1;
+// switch matrix multiplexer  W6BEG2 		MUX-1
+	assign W6BEG2 = OPB_O0;
+// switch matrix multiplexer  W6BEG3 		MUX-1
+	assign W6BEG3 = OPB_O1;
+// switch matrix multiplexer  W6BEG4 		MUX-1
+	assign W6BEG4 = GND0;
+// switch matrix multiplexer  W6BEG5 		MUX-1
+	assign W6BEG5 = GND0;
+// switch matrix multiplexer  W6BEG6 		MUX-1
+	assign W6BEG6 = OPA_O2;
+// switch matrix multiplexer  W6BEG7 		MUX-1
+	assign W6BEG7 = OPA_O3;
+// switch matrix multiplexer  W6BEG8 		MUX-1
+	assign W6BEG8 = OPB_O2;
+// switch matrix multiplexer  W6BEG9 		MUX-1
+	assign W6BEG9 = OPB_O3;
+// switch matrix multiplexer  W6BEG10 		MUX-1
+	assign W6BEG10 = GND0;
+// switch matrix multiplexer  W6BEG11 		MUX-1
+	assign W6BEG11 = GND0;
+// switch matrix multiplexer  RES0_I0 		MUX-1
+	assign RES0_I0 = E6END0;
+// switch matrix multiplexer  RES0_I1 		MUX-1
+	assign RES0_I1 = E6END1;
+// switch matrix multiplexer  RES0_I2 		MUX-1
+	assign RES0_I2 = E6END2;
+// switch matrix multiplexer  RES0_I3 		MUX-1
+	assign RES0_I3 = E6END3;
+// switch matrix multiplexer  RES1_I0 		MUX-1
+	assign RES1_I0 = E6END4;
+// switch matrix multiplexer  RES1_I1 		MUX-1
+	assign RES1_I1 = E6END5;
+// switch matrix multiplexer  RES1_I2 		MUX-1
+	assign RES1_I2 = E6END6;
+// switch matrix multiplexer  RES1_I3 		MUX-1
+	assign RES1_I3 = E6END7;
+// switch matrix multiplexer  RES2_I0 		MUX-1
+	assign RES2_I0 = E6END8;
+// switch matrix multiplexer  RES2_I1 		MUX-1
+	assign RES2_I1 = E6END9;
+// switch matrix multiplexer  RES2_I2 		MUX-1
+	assign RES2_I2 = E6END10;
+// switch matrix multiplexer  RES2_I3 		MUX-1
+	assign RES2_I3 = E6END11;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/E_CPU_IO_tile.v b/verilog/rtl/eFPGA_core/E_CPU_IO_tile.v
new file mode 100644
index 0000000..da84af6
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/E_CPU_IO_tile.v
@@ -0,0 +1,823 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module E_CPU_IO (E1END, E2MID, E2END, EE4END, E6END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, OPA_I0, OPA_I1, OPA_I2, OPA_I3, UserCLK, OPB_I0, OPB_I1, OPB_I2, OPB_I3, RES0_O0, RES0_O1, RES0_O2, RES0_O3, RES1_O0, RES1_O1, RES1_O2, RES1_O3, RES2_O0, RES2_O1, RES2_O2, RES2_O3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	//  NORTH
+	//  EAST
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:NULL destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:NULL destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:NULL destination_name:E6END  
+	//  SOUTH
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:NULL  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:NULL  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:NULL  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:NULL  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:NULL  
+	// Tile IO ports from BELs
+	input OPA_I0;
+	input OPA_I1;
+	input OPA_I2;
+	input OPA_I3;
+	input UserCLK;
+	input OPB_I0;
+	input OPB_I1;
+	input OPB_I2;
+	input OPB_I3;
+	output RES0_O0;
+	output RES0_O1;
+	output RES0_O2;
+	output RES0_O3;
+	output RES1_O0;
+	output RES1_O1;
+	output RES1_O2;
+	output RES1_O3;
+	output RES2_O0;
+	output RES2_O1;
+	output RES2_O2;
+	output RES2_O3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire RES0_I0;
+	wire RES0_I1;
+	wire RES0_I2;
+	wire RES0_I3;
+	wire RES1_I0;
+	wire RES1_I1;
+	wire RES1_I2;
+	wire RES1_I3;
+	wire RES2_I0;
+	wire RES2_I1;
+	wire RES2_I2;
+	wire RES2_I3;
+	wire OPA_O0;
+	wire OPA_O1;
+	wire OPA_O2;
+	wire OPA_O3;
+	wire OPB_O0;
+	wire OPB_O1;
+	wire OPB_O2;
+	wire OPB_O3;
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	E_CPU_IO_ConfigMem Inst_E_CPU_IO_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	InPass4_frame_config Inst_OPA_InPass4_frame_config (
+	.O0(OPA_O0),
+	.O1(OPA_O1),
+	.O2(OPA_O2),
+	.O3(OPA_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPA_I0),
+	.I1(OPA_I1),
+	.I2(OPA_I2),
+	.I3(OPA_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	InPass4_frame_config Inst_OPB_InPass4_frame_config (
+	.O0(OPB_O0),
+	.O1(OPB_O1),
+	.O2(OPB_O2),
+	.O3(OPB_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPB_I0),
+	.I1(OPB_I1),
+	.I2(OPB_I2),
+	.I3(OPB_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+	OutPass4_frame_config Inst_RES0_OutPass4_frame_config (
+	.I0(RES0_I0),
+	.I1(RES0_I1),
+	.I2(RES0_I2),
+	.I3(RES0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES0_O0),
+	.O1(RES0_O1),
+	.O2(RES0_O2),
+	.O3(RES0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[12-1:8])
+	);
+
+	OutPass4_frame_config Inst_RES1_OutPass4_frame_config (
+	.I0(RES1_I0),
+	.I1(RES1_I1),
+	.I2(RES1_I2),
+	.I3(RES1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES1_O0),
+	.O1(RES1_O1),
+	.O2(RES1_O2),
+	.O3(RES1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[16-1:12])
+	);
+
+	OutPass4_frame_config Inst_RES2_OutPass4_frame_config (
+	.I0(RES2_I0),
+	.I1(RES2_I1),
+	.I2(RES2_I2),
+	.I3(RES2_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES2_O0),
+	.O1(RES2_O1),
+	.O2(RES2_O2),
+	.O3(RES2_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[20-1:16])
+	);
+
+
+//switch matrix component instantiation
+	E_CPU_IO_switch_matrix Inst_E_CPU_IO_switch_matrix (
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.EE4END4(EE4END[4]),
+	.EE4END5(EE4END[5]),
+	.EE4END6(EE4END[6]),
+	.EE4END7(EE4END[7]),
+	.EE4END8(EE4END[8]),
+	.EE4END9(EE4END[9]),
+	.EE4END10(EE4END[10]),
+	.EE4END11(EE4END[11]),
+	.EE4END12(EE4END[12]),
+	.EE4END13(EE4END[13]),
+	.EE4END14(EE4END[14]),
+	.EE4END15(EE4END[15]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.E6END2(E6END[2]),
+	.E6END3(E6END[3]),
+	.E6END4(E6END[4]),
+	.E6END5(E6END[5]),
+	.E6END6(E6END[6]),
+	.E6END7(E6END[7]),
+	.E6END8(E6END[8]),
+	.E6END9(E6END[9]),
+	.E6END10(E6END[10]),
+	.E6END11(E6END[11]),
+	.OPA_O0(OPA_O0),
+	.OPA_O1(OPA_O1),
+	.OPA_O2(OPA_O2),
+	.OPA_O3(OPA_O3),
+	.OPB_O0(OPB_O0),
+	.OPB_O1(OPB_O1),
+	.OPB_O2(OPB_O2),
+	.OPB_O3(OPB_O3),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[0]),
+	.WW4BEG1(WW4BEG[1]),
+	.WW4BEG2(WW4BEG[2]),
+	.WW4BEG3(WW4BEG[3]),
+	.WW4BEG4(WW4BEG[4]),
+	.WW4BEG5(WW4BEG[5]),
+	.WW4BEG6(WW4BEG[6]),
+	.WW4BEG7(WW4BEG[7]),
+	.WW4BEG8(WW4BEG[8]),
+	.WW4BEG9(WW4BEG[9]),
+	.WW4BEG10(WW4BEG[10]),
+	.WW4BEG11(WW4BEG[11]),
+	.WW4BEG12(WW4BEG[12]),
+	.WW4BEG13(WW4BEG[13]),
+	.WW4BEG14(WW4BEG[14]),
+	.WW4BEG15(WW4BEG[15]),
+	.W6BEG0(W6BEG[0]),
+	.W6BEG1(W6BEG[1]),
+	.W6BEG2(W6BEG[2]),
+	.W6BEG3(W6BEG[3]),
+	.W6BEG4(W6BEG[4]),
+	.W6BEG5(W6BEG[5]),
+	.W6BEG6(W6BEG[6]),
+	.W6BEG7(W6BEG[7]),
+	.W6BEG8(W6BEG[8]),
+	.W6BEG9(W6BEG[9]),
+	.W6BEG10(W6BEG[10]),
+	.W6BEG11(W6BEG[11]),
+	.RES0_I0(RES0_I0),
+	.RES0_I1(RES0_I1),
+	.RES0_I2(RES0_I2),
+	.RES0_I3(RES0_I3),
+	.RES1_I0(RES1_I0),
+	.RES1_I1(RES1_I1),
+	.RES1_I2(RES1_I2),
+	.RES1_I3(RES1_I3),
+	.RES2_I0(RES2_I0),
+	.RES2_I1(RES2_I1),
+	.RES2_I2(RES2_I2),
+	.RES2_I3(RES2_I3)
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/IO_1_bidirectional_frame_config_pass.v b/verilog/rtl/eFPGA_core/IO_1_bidirectional_frame_config_pass.v
new file mode 100644
index 0000000..1c48e55
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/IO_1_bidirectional_frame_config_pass.v
@@ -0,0 +1,61 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//Library UNISIM;
+//use UNISIM.vcomponents.all;
+
+module IO_1_bidirectional_frame_config_pass (I, T, O, Q, I_top, T_top, O_top, UserCLK);//, ConfigBits);
+	//parameter NoConfigBits = 0; // has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// Pin0
+	input I; // from fabric to external pin
+	input T; // tristate control
+	output O; // from external pin to fabric
+	output Q; // from external pin to fabric (registered)
+	output I_top; // EXTERNAL has to ge to top-level entity not the switch matrix
+	output T_top; // EXTERNAL has to ge to top-level entity not the switch matrix
+	input O_top; // EXTERNAL has to ge to top-level entity not the switch matrix
+	// Tile IO ports from BELs
+	input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this signal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	//input [NoConfigBits-1 : 0] ConfigBits;
+//                        _____
+//    I////-T_DRIVER////->|PAD|//+//////-> O
+//              |         ////-  |
+//    T////////-+                +//>FF//> Q
+
+// I am instantiating an IOBUF primitive.
+// However, it is possible to connect corresponding pins all the way to top, just by adding an "// EXTERNAL" comment (see PAD in the entity)
+	reg Q;
+// wire fromPad;
+// Slice outputs
+	assign O = O_top;
+
+	always @ (posedge UserCLK)
+	begin
+		Q <= O_top;
+	end
+
+	assign I_top = I;
+	assign T_top = ~T;
+
+// IOBUF IOBUF_inst0(
+// .O(fromPad), // 1-bit output: Buffer output
+// .I(I), // 1-bit input: Buffer input
+// .IO(PAD), // 1-bit inout: Buffer inout (connect directly to top-level port)
+// .T(T) // 1-bit input: 3-state enable input
+// );
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/InPass4_frame_config_mux.v b/verilog/rtl/eFPGA_core/InPass4_frame_config_mux.v
new file mode 100644
index 0000000..c008ce3
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/InPass4_frame_config_mux.v
@@ -0,0 +1,80 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module InPass4_frame_config (I0, I1, I2, I3, O0, O1, O2, O3, UserCLK, ConfigBits);
+	parameter NoConfigBits = 4;
+	// Pin0
+	input I0; //EXTERNAL
+	input I1; //EXTERNAL
+	input I2; //EXTERNAL
+	input I3; //EXTERNAL
+	output O0; //EXTERNAL
+	output O1; //EXTERNAL
+	output O2; //EXTERNAL
+	output O3; //EXTERNAL
+	// Tile IO ports from BELs
+	input UserCLK; //EXTERNAL -- SHARED_PORT -- ## the EXTERNAL keyword will send this signal all the way to top and the --SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits - 1 : 0] ConfigBits;
+	//_____   ______
+	//    I----+--->|FLOP|-Q-|1 M |
+	//         |             |  U |-------> O
+	//         +-------------|0 X |               
+	// I am instantiating an IOBUF primitive.
+	// However, it is possible to connect corresponding pins all the way to top, just by adding an "-- EXTERNAL" comment (see PAD in the entity)
+	reg Q0, Q1, Q2, Q3; // FLOPs
+	
+	always @ (posedge UserCLK)
+	begin
+		Q0 <= I0;
+		Q1 <= I1;
+		Q2 <= I2;
+		Q3 <= I3;
+	end
+	// ConfigBits ( '0' combinatorial; '1' registered )
+	//assign O0 = ConfigBits[0] ? Q0 : I0;
+	//assign O1 = ConfigBits[1] ? Q1 : I1;
+	//assign O2 = ConfigBits[2] ? Q2 : I2;
+	//assign O3 = ConfigBits[3] ? Q3 : I3;
+
+    my_mux2 my_mux2_inst0(
+    .A0(I0),
+    .A1(Q0),
+    .S(ConfigBits[0]),
+    .X(O0)
+    );
+
+    my_mux2 my_mux2_inst1(
+    .A0(I1),
+    .A1(Q1),
+    .S(ConfigBits[1]),
+    .X(O1)
+    );
+
+    my_mux2 my_mux2_inst2(
+    .A0(I2),
+    .A1(Q2),
+    .S(ConfigBits[2]),
+    .X(O2)
+    );
+
+    my_mux2 my_mux2_inst3(
+    .A0(I3),
+    .A1(Q3),
+    .S(ConfigBits[3]),
+    .X(O3)
+    );	
+endmodule
diff --git a/verilog/rtl/eFPGA_core/LUT4AB_ConfigMem.v b/verilog/rtl/eFPGA_core/LUT4AB_ConfigMem.v
new file mode 100644
index 0000000..76d0dd6
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/LUT4AB_ConfigMem.v
@@ -0,0 +1,4359 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module LUT4AB_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 616;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [24-1:0] Frame0;
+	wire [29-1:0] Frame1;
+	wire [28-1:0] Frame2;
+	wire [31-1:0] Frame3;
+	wire [32-1:0] Frame4;
+	wire [32-1:0] Frame5;
+	wire [32-1:0] Frame6;
+	wire [32-1:0] Frame7;
+	wire [32-1:0] Frame8;
+	wire [32-1:0] Frame9;
+	wire [32-1:0] Frame10;
+	wire [32-1:0] Frame11;
+	wire [32-1:0] Frame12;
+	wire [32-1:0] Frame13;
+	wire [32-1:0] Frame14;
+	wire [32-1:0] Frame15;
+	wire [32-1:0] Frame16;
+	wire [32-1:0] Frame17;
+	wire [32-1:0] Frame18;
+	wire [24-1:0] Frame19;
+
+//instantiate frame latches
+	LHQD1 Inst_Frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[242]),
+	.QN(ConfigBits_N[242])
+	);
+
+	LHQD1 Inst_Frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[243]),
+	.QN(ConfigBits_N[243])
+	);
+
+	LHQD1 Inst_Frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[247]),
+	.QN(ConfigBits_N[247])
+	);
+
+	LHQD1 Inst_Frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[248]),
+	.QN(ConfigBits_N[248])
+	);
+
+	LHQD1 Inst_Frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[259]),
+	.QN(ConfigBits_N[259])
+	);
+
+	LHQD1 Inst_Frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[261]),
+	.QN(ConfigBits_N[261])
+	);
+
+	LHQD1 Inst_Frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[263]),
+	.QN(ConfigBits_N[263])
+	);
+
+	LHQD1 Inst_Frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[240]),
+	.QN(ConfigBits_N[240])
+	);
+
+	LHQD1 Inst_Frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[241]),
+	.QN(ConfigBits_N[241])
+	);
+
+	LHQD1 Inst_Frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[157]),
+	.QN(ConfigBits_N[157])
+	);
+
+	LHQD1 Inst_Frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[158]),
+	.QN(ConfigBits_N[158])
+	);
+
+	LHQD1 Inst_Frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[159]),
+	.QN(ConfigBits_N[159])
+	);
+
+	LHQD1 Inst_Frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[568]),
+	.QN(ConfigBits_N[568])
+	);
+
+	LHQD1 Inst_Frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[576]),
+	.QN(ConfigBits_N[576])
+	);
+
+	LHQD1 Inst_Frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[577]),
+	.QN(ConfigBits_N[577])
+	);
+
+	LHQD1 Inst_Frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[558]),
+	.QN(ConfigBits_N[558])
+	);
+
+	LHQD1 Inst_Frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[502]),
+	.QN(ConfigBits_N[502])
+	);
+
+	LHQD1 Inst_Frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[472]),
+	.QN(ConfigBits_N[472])
+	);
+
+	LHQD1 Inst_Frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[473]),
+	.QN(ConfigBits_N[473])
+	);
+
+	LHQD1 Inst_Frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[481]),
+	.QN(ConfigBits_N[481])
+	);
+
+	LHQD1 Inst_Frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[462]),
+	.QN(ConfigBits_N[462])
+	);
+
+	LHQD1 Inst_Frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[413]),
+	.QN(ConfigBits_N[413])
+	);
+
+	LHQD1 Inst_Frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[397]),
+	.QN(ConfigBits_N[397])
+	);
+
+	LHQD1 Inst_Frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[389]),
+	.QN(ConfigBits_N[389])
+	);
+
+	LHQD1 Inst_Frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[249]),
+	.QN(ConfigBits_N[249])
+	);
+
+	LHQD1 Inst_Frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[250]),
+	.QN(ConfigBits_N[250])
+	);
+
+	LHQD1 Inst_Frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[255]),
+	.QN(ConfigBits_N[255])
+	);
+
+	LHQD1 Inst_Frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[256]),
+	.QN(ConfigBits_N[256])
+	);
+
+	LHQD1 Inst_Frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[260]),
+	.QN(ConfigBits_N[260])
+	);
+
+	LHQD1 Inst_Frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[262]),
+	.QN(ConfigBits_N[262])
+	);
+
+	LHQD1 Inst_Frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[563]),
+	.QN(ConfigBits_N[563])
+	);
+
+	LHQD1 Inst_Frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[565]),
+	.QN(ConfigBits_N[565])
+	);
+
+	LHQD1 Inst_Frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[569]),
+	.QN(ConfigBits_N[569])
+	);
+
+	LHQD1 Inst_Frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[570]),
+	.QN(ConfigBits_N[570])
+	);
+
+	LHQD1 Inst_Frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[571]),
+	.QN(ConfigBits_N[571])
+	);
+
+	LHQD1 Inst_Frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[572]),
+	.QN(ConfigBits_N[572])
+	);
+
+	LHQD1 Inst_Frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[573]),
+	.QN(ConfigBits_N[573])
+	);
+
+	LHQD1 Inst_Frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[578]),
+	.QN(ConfigBits_N[578])
+	);
+
+	LHQD1 Inst_Frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[559]),
+	.QN(ConfigBits_N[559])
+	);
+
+	LHQD1 Inst_Frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[560]),
+	.QN(ConfigBits_N[560])
+	);
+
+	LHQD1 Inst_Frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[530]),
+	.QN(ConfigBits_N[530])
+	);
+
+	LHQD1 Inst_Frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[534]),
+	.QN(ConfigBits_N[534])
+	);
+
+	LHQD1 Inst_Frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[537]),
+	.QN(ConfigBits_N[537])
+	);
+
+	LHQD1 Inst_Frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[542]),
+	.QN(ConfigBits_N[542])
+	);
+
+	LHQD1 Inst_Frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[543]),
+	.QN(ConfigBits_N[543])
+	);
+
+	LHQD1 Inst_Frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[526]),
+	.QN(ConfigBits_N[526])
+	);
+
+	LHQD1 Inst_Frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[527]),
+	.QN(ConfigBits_N[527])
+	);
+
+	LHQD1 Inst_Frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[504]),
+	.QN(ConfigBits_N[504])
+	);
+
+	LHQD1 Inst_Frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[480]),
+	.QN(ConfigBits_N[480])
+	);
+
+	LHQD1 Inst_Frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[463]),
+	.QN(ConfigBits_N[463])
+	);
+
+	LHQD1 Inst_Frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[422]),
+	.QN(ConfigBits_N[422])
+	);
+
+	LHQD1 Inst_Frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[386]),
+	.QN(ConfigBits_N[386])
+	);
+
+	LHQD1 Inst_Frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[388]),
+	.QN(ConfigBits_N[388])
+	);
+
+	LHQD1 Inst_Frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[264]),
+	.QN(ConfigBits_N[264])
+	);
+
+	LHQD1 Inst_Frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[265]),
+	.QN(ConfigBits_N[265])
+	);
+
+	LHQD1 Inst_Frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[251]),
+	.QN(ConfigBits_N[251])
+	);
+
+	LHQD1 Inst_Frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[257]),
+	.QN(ConfigBits_N[257])
+	);
+
+	LHQD1 Inst_Frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[163]),
+	.QN(ConfigBits_N[163])
+	);
+
+	LHQD1 Inst_Frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[167]),
+	.QN(ConfigBits_N[167])
+	);
+
+	LHQD1 Inst_Frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[564]),
+	.QN(ConfigBits_N[564])
+	);
+
+	LHQD1 Inst_Frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[561]),
+	.QN(ConfigBits_N[561])
+	);
+
+	LHQD1 Inst_Frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[531]),
+	.QN(ConfigBits_N[531])
+	);
+
+	LHQD1 Inst_Frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[535]),
+	.QN(ConfigBits_N[535])
+	);
+
+	LHQD1 Inst_Frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[536]),
+	.QN(ConfigBits_N[536])
+	);
+
+	LHQD1 Inst_Frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[544]),
+	.QN(ConfigBits_N[544])
+	);
+
+	LHQD1 Inst_Frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[528]),
+	.QN(ConfigBits_N[528])
+	);
+
+	LHQD1 Inst_Frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[529]),
+	.QN(ConfigBits_N[529])
+	);
+
+	LHQD1 Inst_Frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[498]),
+	.QN(ConfigBits_N[498])
+	);
+
+	LHQD1 Inst_Frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[499]),
+	.QN(ConfigBits_N[499])
+	);
+
+	LHQD1 Inst_Frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[503]),
+	.QN(ConfigBits_N[503])
+	);
+
+	LHQD1 Inst_Frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[494]),
+	.QN(ConfigBits_N[494])
+	);
+
+	LHQD1 Inst_Frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[474]),
+	.QN(ConfigBits_N[474])
+	);
+
+	LHQD1 Inst_Frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[475]),
+	.QN(ConfigBits_N[475])
+	);
+
+	LHQD1 Inst_Frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[483]),
+	.QN(ConfigBits_N[483])
+	);
+
+	LHQD1 Inst_Frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[461]),
+	.QN(ConfigBits_N[461])
+	);
+
+	LHQD1 Inst_Frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[464]),
+	.QN(ConfigBits_N[464])
+	);
+
+	LHQD1 Inst_Frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[439]),
+	.QN(ConfigBits_N[439])
+	);
+
+	LHQD1 Inst_Frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[423]),
+	.QN(ConfigBits_N[423])
+	);
+
+	LHQD1 Inst_Frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[374]),
+	.QN(ConfigBits_N[374])
+	);
+
+	LHQD1 Inst_Frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[366]),
+	.QN(ConfigBits_N[366])
+	);
+
+	LHQD1 Inst_Frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[348]),
+	.QN(ConfigBits_N[348])
+	);
+
+	LHQD1 Inst_Frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[168]),
+	.QN(ConfigBits_N[168])
+	);
+
+	LHQD1 Inst_Frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[186]),
+	.QN(ConfigBits_N[186])
+	);
+
+	LHQD1 Inst_Frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[153]),
+	.QN(ConfigBits_N[153])
+	);
+
+	LHQD1 Inst_Frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[162]),
+	.QN(ConfigBits_N[162])
+	);
+
+	LHQD1 Inst_Frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[164]),
+	.QN(ConfigBits_N[164])
+	);
+
+	LHQD1 Inst_Frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[166]),
+	.QN(ConfigBits_N[166])
+	);
+
+	LHQD1 Inst_Frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_Frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[533]),
+	.QN(ConfigBits_N[533])
+	);
+
+	LHQD1 Inst_Frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[545]),
+	.QN(ConfigBits_N[545])
+	);
+
+	LHQD1 Inst_Frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[546]),
+	.QN(ConfigBits_N[546])
+	);
+
+	LHQD1 Inst_Frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[547]),
+	.QN(ConfigBits_N[547])
+	);
+
+	LHQD1 Inst_Frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[500]),
+	.QN(ConfigBits_N[500])
+	);
+
+	LHQD1 Inst_Frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[501]),
+	.QN(ConfigBits_N[501])
+	);
+
+	LHQD1 Inst_Frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[505]),
+	.QN(ConfigBits_N[505])
+	);
+
+	LHQD1 Inst_Frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[491]),
+	.QN(ConfigBits_N[491])
+	);
+
+	LHQD1 Inst_Frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[495]),
+	.QN(ConfigBits_N[495])
+	);
+
+	LHQD1 Inst_Frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[496]),
+	.QN(ConfigBits_N[496])
+	);
+
+	LHQD1 Inst_Frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[497]),
+	.QN(ConfigBits_N[497])
+	);
+
+	LHQD1 Inst_Frame3_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[476]),
+	.QN(ConfigBits_N[476])
+	);
+
+	LHQD1 Inst_Frame3_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[477]),
+	.QN(ConfigBits_N[477])
+	);
+
+	LHQD1 Inst_Frame3_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[465]),
+	.QN(ConfigBits_N[465])
+	);
+
+	LHQD1 Inst_Frame3_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[438]),
+	.QN(ConfigBits_N[438])
+	);
+
+	LHQD1 Inst_Frame3_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[446]),
+	.QN(ConfigBits_N[446])
+	);
+
+	LHQD1 Inst_Frame3_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[450]),
+	.QN(ConfigBits_N[450])
+	);
+
+	LHQD1 Inst_Frame3_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[451]),
+	.QN(ConfigBits_N[451])
+	);
+
+	LHQD1 Inst_Frame3_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[430]),
+	.QN(ConfigBits_N[430])
+	);
+
+	LHQD1 Inst_Frame3_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[431]),
+	.QN(ConfigBits_N[431])
+	);
+
+	LHQD1 Inst_Frame3_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[367]),
+	.QN(ConfigBits_N[367])
+	);
+
+	LHQD1 Inst_Frame3_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[349]),
+	.QN(ConfigBits_N[349])
+	);
+
+	LHQD1 Inst_Frame3_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[353]),
+	.QN(ConfigBits_N[353])
+	);
+
+	LHQD1 Inst_Frame3_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[336]),
+	.QN(ConfigBits_N[336])
+	);
+
+	LHQD1 Inst_Frame4_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[604]),
+	.QN(ConfigBits_N[604])
+	);
+
+	LHQD1 Inst_Frame4_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[216]),
+	.QN(ConfigBits_N[216])
+	);
+
+	LHQD1 Inst_Frame4_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[203]),
+	.QN(ConfigBits_N[203])
+	);
+
+	LHQD1 Inst_Frame4_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[169]),
+	.QN(ConfigBits_N[169])
+	);
+
+	LHQD1 Inst_Frame4_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[179]),
+	.QN(ConfigBits_N[179])
+	);
+
+	LHQD1 Inst_Frame4_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[184]),
+	.QN(ConfigBits_N[184])
+	);
+
+	LHQD1 Inst_Frame4_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[176]),
+	.QN(ConfigBits_N[176])
+	);
+
+	LHQD1 Inst_Frame4_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[152]),
+	.QN(ConfigBits_N[152])
+	);
+
+	LHQD1 Inst_Frame4_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[165]),
+	.QN(ConfigBits_N[165])
+	);
+
+	LHQD1 Inst_Frame4_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[532]),
+	.QN(ConfigBits_N[532])
+	);
+
+	LHQD1 Inst_Frame4_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[549]),
+	.QN(ConfigBits_N[549])
+	);
+
+	LHQD1 Inst_Frame4_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[550]),
+	.QN(ConfigBits_N[550])
+	);
+
+	LHQD1 Inst_Frame4_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[489]),
+	.QN(ConfigBits_N[489])
+	);
+
+	LHQD1 Inst_Frame4_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[509]),
+	.QN(ConfigBits_N[509])
+	);
+
+	LHQD1 Inst_Frame4_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[514]),
+	.QN(ConfigBits_N[514])
+	);
+
+	LHQD1 Inst_Frame4_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[515]),
+	.QN(ConfigBits_N[515])
+	);
+
+	LHQD1 Inst_Frame4_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[517]),
+	.QN(ConfigBits_N[517])
+	);
+
+	LHQD1 Inst_Frame4_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[466]),
+	.QN(ConfigBits_N[466])
+	);
+
+	LHQD1 Inst_Frame4_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[468]),
+	.QN(ConfigBits_N[468])
+	);
+
+	LHQD1 Inst_Frame4_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[469]),
+	.QN(ConfigBits_N[469])
+	);
+
+	LHQD1 Inst_Frame4_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[482]),
+	.QN(ConfigBits_N[482])
+	);
+
+	LHQD1 Inst_Frame4_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[486]),
+	.QN(ConfigBits_N[486])
+	);
+
+	LHQD1 Inst_Frame4_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[447]),
+	.QN(ConfigBits_N[447])
+	);
+
+	LHQD1 Inst_Frame4_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[452]),
+	.QN(ConfigBits_N[452])
+	);
+
+	LHQD1 Inst_Frame4_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[455]),
+	.QN(ConfigBits_N[455])
+	);
+
+	LHQD1 Inst_Frame4_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[428]),
+	.QN(ConfigBits_N[428])
+	);
+
+	LHQD1 Inst_Frame4_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[370]),
+	.QN(ConfigBits_N[370])
+	);
+
+	LHQD1 Inst_Frame4_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[371]),
+	.QN(ConfigBits_N[371])
+	);
+
+	LHQD1 Inst_Frame4_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[375]),
+	.QN(ConfigBits_N[375])
+	);
+
+	LHQD1 Inst_Frame4_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[363]),
+	.QN(ConfigBits_N[363])
+	);
+
+	LHQD1 Inst_Frame4_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[352]),
+	.QN(ConfigBits_N[352])
+	);
+
+	LHQD1 Inst_Frame4_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[358]),
+	.QN(ConfigBits_N[358])
+	);
+
+	LHQD1 Inst_Frame5_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[589]),
+	.QN(ConfigBits_N[589])
+	);
+
+	LHQD1 Inst_Frame5_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[210]),
+	.QN(ConfigBits_N[210])
+	);
+
+	LHQD1 Inst_Frame5_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[202]),
+	.QN(ConfigBits_N[202])
+	);
+
+	LHQD1 Inst_Frame5_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[229]),
+	.QN(ConfigBits_N[229])
+	);
+
+	LHQD1 Inst_Frame5_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[205]),
+	.QN(ConfigBits_N[205])
+	);
+
+	LHQD1 Inst_Frame5_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[178]),
+	.QN(ConfigBits_N[178])
+	);
+
+	LHQD1 Inst_Frame5_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[185]),
+	.QN(ConfigBits_N[185])
+	);
+
+	LHQD1 Inst_Frame5_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[173]),
+	.QN(ConfigBits_N[173])
+	);
+
+	LHQD1 Inst_Frame5_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[174]),
+	.QN(ConfigBits_N[174])
+	);
+
+	LHQD1 Inst_Frame5_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[175]),
+	.QN(ConfigBits_N[175])
+	);
+
+	LHQD1 Inst_Frame5_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[177]),
+	.QN(ConfigBits_N[177])
+	);
+
+	LHQD1 Inst_Frame5_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[126]),
+	.QN(ConfigBits_N[126])
+	);
+
+	LHQD1 Inst_Frame5_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[548]),
+	.QN(ConfigBits_N[548])
+	);
+
+	LHQD1 Inst_Frame5_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[551]),
+	.QN(ConfigBits_N[551])
+	);
+
+	LHQD1 Inst_Frame5_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[506]),
+	.QN(ConfigBits_N[506])
+	);
+
+	LHQD1 Inst_Frame5_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[510]),
+	.QN(ConfigBits_N[510])
+	);
+
+	LHQD1 Inst_Frame5_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[511]),
+	.QN(ConfigBits_N[511])
+	);
+
+	LHQD1 Inst_Frame5_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[516]),
+	.QN(ConfigBits_N[516])
+	);
+
+	LHQD1 Inst_Frame5_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[457]),
+	.QN(ConfigBits_N[457])
+	);
+
+	LHQD1 Inst_Frame5_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[458]),
+	.QN(ConfigBits_N[458])
+	);
+
+	LHQD1 Inst_Frame5_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[436]),
+	.QN(ConfigBits_N[436])
+	);
+
+	LHQD1 Inst_Frame5_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[437]),
+	.QN(ConfigBits_N[437])
+	);
+
+	LHQD1 Inst_Frame5_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[440]),
+	.QN(ConfigBits_N[440])
+	);
+
+	LHQD1 Inst_Frame5_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[441]),
+	.QN(ConfigBits_N[441])
+	);
+
+	LHQD1 Inst_Frame5_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[444]),
+	.QN(ConfigBits_N[444])
+	);
+
+	LHQD1 Inst_Frame5_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[448]),
+	.QN(ConfigBits_N[448])
+	);
+
+	LHQD1 Inst_Frame5_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[453]),
+	.QN(ConfigBits_N[453])
+	);
+
+	LHQD1 Inst_Frame5_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[454]),
+	.QN(ConfigBits_N[454])
+	);
+
+	LHQD1 Inst_Frame5_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[429]),
+	.QN(ConfigBits_N[429])
+	);
+
+	LHQD1 Inst_Frame5_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[421]),
+	.QN(ConfigBits_N[421])
+	);
+
+	LHQD1 Inst_Frame5_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[346]),
+	.QN(ConfigBits_N[346])
+	);
+
+	LHQD1 Inst_Frame5_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[359]),
+	.QN(ConfigBits_N[359])
+	);
+
+	LHQD1 Inst_Frame6_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[605]),
+	.QN(ConfigBits_N[605])
+	);
+
+	LHQD1 Inst_Frame6_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[606]),
+	.QN(ConfigBits_N[606])
+	);
+
+	LHQD1 Inst_Frame6_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[211]),
+	.QN(ConfigBits_N[211])
+	);
+
+	LHQD1 Inst_Frame6_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[212]),
+	.QN(ConfigBits_N[212])
+	);
+
+	LHQD1 Inst_Frame6_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[213]),
+	.QN(ConfigBits_N[213])
+	);
+
+	LHQD1 Inst_Frame6_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[214]),
+	.QN(ConfigBits_N[214])
+	);
+
+	LHQD1 Inst_Frame6_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[231]),
+	.QN(ConfigBits_N[231])
+	);
+
+	LHQD1 Inst_Frame6_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[204]),
+	.QN(ConfigBits_N[204])
+	);
+
+	LHQD1 Inst_Frame6_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[206]),
+	.QN(ConfigBits_N[206])
+	);
+
+	LHQD1 Inst_Frame6_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[208]),
+	.QN(ConfigBits_N[208])
+	);
+
+	LHQD1 Inst_Frame6_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[181]),
+	.QN(ConfigBits_N[181])
+	);
+
+	LHQD1 Inst_Frame6_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[170]),
+	.QN(ConfigBits_N[170])
+	);
+
+	LHQD1 Inst_Frame6_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[119]),
+	.QN(ConfigBits_N[119])
+	);
+
+	LHQD1 Inst_Frame6_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_Frame6_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_Frame6_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[553]),
+	.QN(ConfigBits_N[553])
+	);
+
+	LHQD1 Inst_Frame6_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[507]),
+	.QN(ConfigBits_N[507])
+	);
+
+	LHQD1 Inst_Frame6_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[490]),
+	.QN(ConfigBits_N[490])
+	);
+
+	LHQD1 Inst_Frame6_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[513]),
+	.QN(ConfigBits_N[513])
+	);
+
+	LHQD1 Inst_Frame6_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[492]),
+	.QN(ConfigBits_N[492])
+	);
+
+	LHQD1 Inst_Frame6_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[456]),
+	.QN(ConfigBits_N[456])
+	);
+
+	LHQD1 Inst_Frame6_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[484]),
+	.QN(ConfigBits_N[484])
+	);
+
+	LHQD1 Inst_Frame6_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[485]),
+	.QN(ConfigBits_N[485])
+	);
+
+	LHQD1 Inst_Frame6_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[459]),
+	.QN(ConfigBits_N[459])
+	);
+
+	LHQD1 Inst_Frame6_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[487]),
+	.QN(ConfigBits_N[487])
+	);
+
+	LHQD1 Inst_Frame6_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[424]),
+	.QN(ConfigBits_N[424])
+	);
+
+	LHQD1 Inst_Frame6_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[425]),
+	.QN(ConfigBits_N[425])
+	);
+
+	LHQD1 Inst_Frame6_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[449]),
+	.QN(ConfigBits_N[449])
+	);
+
+	LHQD1 Inst_Frame6_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[433]),
+	.QN(ConfigBits_N[433])
+	);
+
+	LHQD1 Inst_Frame6_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[420]),
+	.QN(ConfigBits_N[420])
+	);
+
+	LHQD1 Inst_Frame6_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[347]),
+	.QN(ConfigBits_N[347])
+	);
+
+	LHQD1 Inst_Frame6_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[311]),
+	.QN(ConfigBits_N[311])
+	);
+
+	LHQD1 Inst_Frame7_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[596]),
+	.QN(ConfigBits_N[596])
+	);
+
+	LHQD1 Inst_Frame7_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[608]),
+	.QN(ConfigBits_N[608])
+	);
+
+	LHQD1 Inst_Frame7_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[609]),
+	.QN(ConfigBits_N[609])
+	);
+
+	LHQD1 Inst_Frame7_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[588]),
+	.QN(ConfigBits_N[588])
+	);
+
+	LHQD1 Inst_Frame7_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[590]),
+	.QN(ConfigBits_N[590])
+	);
+
+	LHQD1 Inst_Frame7_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[280]),
+	.QN(ConfigBits_N[280])
+	);
+
+	LHQD1 Inst_Frame7_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[236]),
+	.QN(ConfigBits_N[236])
+	);
+
+	LHQD1 Inst_Frame7_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[217]),
+	.QN(ConfigBits_N[217])
+	);
+
+	LHQD1 Inst_Frame7_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[180]),
+	.QN(ConfigBits_N[180])
+	);
+
+	LHQD1 Inst_Frame7_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[171]),
+	.QN(ConfigBits_N[171])
+	);
+
+	LHQD1 Inst_Frame7_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[172]),
+	.QN(ConfigBits_N[172])
+	);
+
+	LHQD1 Inst_Frame7_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[146]),
+	.QN(ConfigBits_N[146])
+	);
+
+	LHQD1 Inst_Frame7_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[160]),
+	.QN(ConfigBits_N[160])
+	);
+
+	LHQD1 Inst_Frame7_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[121]),
+	.QN(ConfigBits_N[121])
+	);
+
+	LHQD1 Inst_Frame7_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[552]),
+	.QN(ConfigBits_N[552])
+	);
+
+	LHQD1 Inst_Frame7_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[555]),
+	.QN(ConfigBits_N[555])
+	);
+
+	LHQD1 Inst_Frame7_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[582]),
+	.QN(ConfigBits_N[582])
+	);
+
+	LHQD1 Inst_Frame7_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[522]),
+	.QN(ConfigBits_N[522])
+	);
+
+	LHQD1 Inst_Frame7_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[540]),
+	.QN(ConfigBits_N[540])
+	);
+
+	LHQD1 Inst_Frame7_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[488]),
+	.QN(ConfigBits_N[488])
+	);
+
+	LHQD1 Inst_Frame7_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[508]),
+	.QN(ConfigBits_N[508])
+	);
+
+	LHQD1 Inst_Frame7_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[512]),
+	.QN(ConfigBits_N[512])
+	);
+
+	LHQD1 Inst_Frame7_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[519]),
+	.QN(ConfigBits_N[519])
+	);
+
+	LHQD1 Inst_Frame7_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[493]),
+	.QN(ConfigBits_N[493])
+	);
+
+	LHQD1 Inst_Frame7_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[460]),
+	.QN(ConfigBits_N[460])
+	);
+
+	LHQD1 Inst_Frame7_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[434]),
+	.QN(ConfigBits_N[434])
+	);
+
+	LHQD1 Inst_Frame7_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[435]),
+	.QN(ConfigBits_N[435])
+	);
+
+	LHQD1 Inst_Frame7_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[442]),
+	.QN(ConfigBits_N[442])
+	);
+
+	LHQD1 Inst_Frame7_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[402]),
+	.QN(ConfigBits_N[402])
+	);
+
+	LHQD1 Inst_Frame7_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[415]),
+	.QN(ConfigBits_N[415])
+	);
+
+	LHQD1 Inst_Frame7_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[385]),
+	.QN(ConfigBits_N[385])
+	);
+
+	LHQD1 Inst_Frame7_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[340]),
+	.QN(ConfigBits_N[340])
+	);
+
+	LHQD1 Inst_Frame8_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[597]),
+	.QN(ConfigBits_N[597])
+	);
+
+	LHQD1 Inst_Frame8_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[598]),
+	.QN(ConfigBits_N[598])
+	);
+
+	LHQD1 Inst_Frame8_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[600]),
+	.QN(ConfigBits_N[600])
+	);
+
+	LHQD1 Inst_Frame8_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[607]),
+	.QN(ConfigBits_N[607])
+	);
+
+	LHQD1 Inst_Frame8_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[286]),
+	.QN(ConfigBits_N[286])
+	);
+
+	LHQD1 Inst_Frame8_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[290]),
+	.QN(ConfigBits_N[290])
+	);
+
+	LHQD1 Inst_Frame8_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[244]),
+	.QN(ConfigBits_N[244])
+	);
+
+	LHQD1 Inst_Frame8_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[235]),
+	.QN(ConfigBits_N[235])
+	);
+
+	LHQD1 Inst_Frame8_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[215]),
+	.QN(ConfigBits_N[215])
+	);
+
+	LHQD1 Inst_Frame8_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[219]),
+	.QN(ConfigBits_N[219])
+	);
+
+	LHQD1 Inst_Frame8_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[230]),
+	.QN(ConfigBits_N[230])
+	);
+
+	LHQD1 Inst_Frame8_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[207]),
+	.QN(ConfigBits_N[207])
+	);
+
+	LHQD1 Inst_Frame8_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[209]),
+	.QN(ConfigBits_N[209])
+	);
+
+	LHQD1 Inst_Frame8_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[193]),
+	.QN(ConfigBits_N[193])
+	);
+
+	LHQD1 Inst_Frame8_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[194]),
+	.QN(ConfigBits_N[194])
+	);
+
+	LHQD1 Inst_Frame8_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[137]),
+	.QN(ConfigBits_N[137])
+	);
+
+	LHQD1 Inst_Frame8_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[161]),
+	.QN(ConfigBits_N[161])
+	);
+
+	LHQD1 Inst_Frame8_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[129]),
+	.QN(ConfigBits_N[129])
+	);
+
+	LHQD1 Inst_Frame8_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[554]),
+	.QN(ConfigBits_N[554])
+	);
+
+	LHQD1 Inst_Frame8_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[580]),
+	.QN(ConfigBits_N[580])
+	);
+
+	LHQD1 Inst_Frame8_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[520]),
+	.QN(ConfigBits_N[520])
+	);
+
+	LHQD1 Inst_Frame8_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[538]),
+	.QN(ConfigBits_N[538])
+	);
+
+	LHQD1 Inst_Frame8_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[539]),
+	.QN(ConfigBits_N[539])
+	);
+
+	LHQD1 Inst_Frame8_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[523]),
+	.QN(ConfigBits_N[523])
+	);
+
+	LHQD1 Inst_Frame8_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[518]),
+	.QN(ConfigBits_N[518])
+	);
+
+	LHQD1 Inst_Frame8_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[443]),
+	.QN(ConfigBits_N[443])
+	);
+
+	LHQD1 Inst_Frame8_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[426]),
+	.QN(ConfigBits_N[426])
+	);
+
+	LHQD1 Inst_Frame8_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[427]),
+	.QN(ConfigBits_N[427])
+	);
+
+	LHQD1 Inst_Frame8_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[432]),
+	.QN(ConfigBits_N[432])
+	);
+
+	LHQD1 Inst_Frame8_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[369]),
+	.QN(ConfigBits_N[369])
+	);
+
+	LHQD1 Inst_Frame8_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[329]),
+	.QN(ConfigBits_N[329])
+	);
+
+	LHQD1 Inst_Frame8_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[351]),
+	.QN(ConfigBits_N[351])
+	);
+
+	LHQD1 Inst_Frame9_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[599]),
+	.QN(ConfigBits_N[599])
+	);
+
+	LHQD1 Inst_Frame9_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[603]),
+	.QN(ConfigBits_N[603])
+	);
+
+	LHQD1 Inst_Frame9_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[591]),
+	.QN(ConfigBits_N[591])
+	);
+
+	LHQD1 Inst_Frame9_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[281]),
+	.QN(ConfigBits_N[281])
+	);
+
+	LHQD1 Inst_Frame9_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[292]),
+	.QN(ConfigBits_N[292])
+	);
+
+	LHQD1 Inst_Frame9_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[245]),
+	.QN(ConfigBits_N[245])
+	);
+
+	LHQD1 Inst_Frame9_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[237]),
+	.QN(ConfigBits_N[237])
+	);
+
+	LHQD1 Inst_Frame9_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[218]),
+	.QN(ConfigBits_N[218])
+	);
+
+	LHQD1 Inst_Frame9_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[195]),
+	.QN(ConfigBits_N[195])
+	);
+
+	LHQD1 Inst_Frame9_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[197]),
+	.QN(ConfigBits_N[197])
+	);
+
+	LHQD1 Inst_Frame9_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[136]),
+	.QN(ConfigBits_N[136])
+	);
+
+	LHQD1 Inst_Frame9_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[579]),
+	.QN(ConfigBits_N[579])
+	);
+
+	LHQD1 Inst_Frame9_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[583]),
+	.QN(ConfigBits_N[583])
+	);
+
+	LHQD1 Inst_Frame9_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[556]),
+	.QN(ConfigBits_N[556])
+	);
+
+	LHQD1 Inst_Frame9_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[541]),
+	.QN(ConfigBits_N[541])
+	);
+
+	LHQD1 Inst_Frame9_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[524]),
+	.QN(ConfigBits_N[524])
+	);
+
+	LHQD1 Inst_Frame9_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[525]),
+	.QN(ConfigBits_N[525])
+	);
+
+	LHQD1 Inst_Frame9_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[445]),
+	.QN(ConfigBits_N[445])
+	);
+
+	LHQD1 Inst_Frame9_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[414]),
+	.QN(ConfigBits_N[414])
+	);
+
+	LHQD1 Inst_Frame9_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[418]),
+	.QN(ConfigBits_N[418])
+	);
+
+	LHQD1 Inst_Frame9_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[419]),
+	.QN(ConfigBits_N[419])
+	);
+
+	LHQD1 Inst_Frame9_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[361]),
+	.QN(ConfigBits_N[361])
+	);
+
+	LHQD1 Inst_Frame9_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[378]),
+	.QN(ConfigBits_N[378])
+	);
+
+	LHQD1 Inst_Frame9_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[379]),
+	.QN(ConfigBits_N[379])
+	);
+
+	LHQD1 Inst_Frame9_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[382]),
+	.QN(ConfigBits_N[382])
+	);
+
+	LHQD1 Inst_Frame9_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[383]),
+	.QN(ConfigBits_N[383])
+	);
+
+	LHQD1 Inst_Frame9_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[384]),
+	.QN(ConfigBits_N[384])
+	);
+
+	LHQD1 Inst_Frame9_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[368]),
+	.QN(ConfigBits_N[368])
+	);
+
+	LHQD1 Inst_Frame9_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[328]),
+	.QN(ConfigBits_N[328])
+	);
+
+	LHQD1 Inst_Frame9_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[341]),
+	.QN(ConfigBits_N[341])
+	);
+
+	LHQD1 Inst_Frame9_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[350]),
+	.QN(ConfigBits_N[350])
+	);
+
+	LHQD1 Inst_Frame9_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[354]),
+	.QN(ConfigBits_N[354])
+	);
+
+	LHQD1 Inst_Frame10_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[601]),
+	.QN(ConfigBits_N[601])
+	);
+
+	LHQD1 Inst_Frame10_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[615]),
+	.QN(ConfigBits_N[615])
+	);
+
+	LHQD1 Inst_Frame10_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[270]),
+	.QN(ConfigBits_N[270])
+	);
+
+	LHQD1 Inst_Frame10_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[271]),
+	.QN(ConfigBits_N[271])
+	);
+
+	LHQD1 Inst_Frame10_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[232]),
+	.QN(ConfigBits_N[232])
+	);
+
+	LHQD1 Inst_Frame10_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[200]),
+	.QN(ConfigBits_N[200])
+	);
+
+	LHQD1 Inst_Frame10_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[220]),
+	.QN(ConfigBits_N[220])
+	);
+
+	LHQD1 Inst_Frame10_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[221]),
+	.QN(ConfigBits_N[221])
+	);
+
+	LHQD1 Inst_Frame10_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[222]),
+	.QN(ConfigBits_N[222])
+	);
+
+	LHQD1 Inst_Frame10_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[196]),
+	.QN(ConfigBits_N[196])
+	);
+
+	LHQD1 Inst_Frame10_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[199]),
+	.QN(ConfigBits_N[199])
+	);
+
+	LHQD1 Inst_Frame10_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[139]),
+	.QN(ConfigBits_N[139])
+	);
+
+	LHQD1 Inst_Frame10_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[115]),
+	.QN(ConfigBits_N[115])
+	);
+
+	LHQD1 Inst_Frame10_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[117]),
+	.QN(ConfigBits_N[117])
+	);
+
+	LHQD1 Inst_Frame10_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[118]),
+	.QN(ConfigBits_N[118])
+	);
+
+	LHQD1 Inst_Frame10_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[127]),
+	.QN(ConfigBits_N[127])
+	);
+
+	LHQD1 Inst_Frame10_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[133]),
+	.QN(ConfigBits_N[133])
+	);
+
+	LHQD1 Inst_Frame10_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_Frame10_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[581]),
+	.QN(ConfigBits_N[581])
+	);
+
+	LHQD1 Inst_Frame10_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[557]),
+	.QN(ConfigBits_N[557])
+	);
+
+	LHQD1 Inst_Frame10_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[411]),
+	.QN(ConfigBits_N[411])
+	);
+
+	LHQD1 Inst_Frame10_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[395]),
+	.QN(ConfigBits_N[395])
+	);
+
+	LHQD1 Inst_Frame10_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[398]),
+	.QN(ConfigBits_N[398])
+	);
+
+	LHQD1 Inst_Frame10_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[360]),
+	.QN(ConfigBits_N[360])
+	);
+
+	LHQD1 Inst_Frame10_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[376]),
+	.QN(ConfigBits_N[376])
+	);
+
+	LHQD1 Inst_Frame10_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[377]),
+	.QN(ConfigBits_N[377])
+	);
+
+	LHQD1 Inst_Frame10_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[380]),
+	.QN(ConfigBits_N[380])
+	);
+
+	LHQD1 Inst_Frame10_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[381]),
+	.QN(ConfigBits_N[381])
+	);
+
+	LHQD1 Inst_Frame10_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[390]),
+	.QN(ConfigBits_N[390])
+	);
+
+	LHQD1 Inst_Frame10_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[391]),
+	.QN(ConfigBits_N[391])
+	);
+
+	LHQD1 Inst_Frame10_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[338]),
+	.QN(ConfigBits_N[338])
+	);
+
+	LHQD1 Inst_Frame10_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[330]),
+	.QN(ConfigBits_N[330])
+	);
+
+	LHQD1 Inst_Frame11_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[584]),
+	.QN(ConfigBits_N[584])
+	);
+
+	LHQD1 Inst_Frame11_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[585]),
+	.QN(ConfigBits_N[585])
+	);
+
+	LHQD1 Inst_Frame11_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[602]),
+	.QN(ConfigBits_N[602])
+	);
+
+	LHQD1 Inst_Frame11_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[610]),
+	.QN(ConfigBits_N[610])
+	);
+
+	LHQD1 Inst_Frame11_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[233]),
+	.QN(ConfigBits_N[233])
+	);
+
+	LHQD1 Inst_Frame11_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[234]),
+	.QN(ConfigBits_N[234])
+	);
+
+	LHQD1 Inst_Frame11_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[201]),
+	.QN(ConfigBits_N[201])
+	);
+
+	LHQD1 Inst_Frame11_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[187]),
+	.QN(ConfigBits_N[187])
+	);
+
+	LHQD1 Inst_Frame11_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[188]),
+	.QN(ConfigBits_N[188])
+	);
+
+	LHQD1 Inst_Frame11_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[198]),
+	.QN(ConfigBits_N[198])
+	);
+
+	LHQD1 Inst_Frame11_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[151]),
+	.QN(ConfigBits_N[151])
+	);
+
+	LHQD1 Inst_Frame11_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[138]),
+	.QN(ConfigBits_N[138])
+	);
+
+	LHQD1 Inst_Frame11_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[140]),
+	.QN(ConfigBits_N[140])
+	);
+
+	LHQD1 Inst_Frame11_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[114]),
+	.QN(ConfigBits_N[114])
+	);
+
+	LHQD1 Inst_Frame11_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[120]),
+	.QN(ConfigBits_N[120])
+	);
+
+	LHQD1 Inst_Frame11_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[128]),
+	.QN(ConfigBits_N[128])
+	);
+
+	LHQD1 Inst_Frame11_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[134]),
+	.QN(ConfigBits_N[134])
+	);
+
+	LHQD1 Inst_Frame11_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[521]),
+	.QN(ConfigBits_N[521])
+	);
+
+	LHQD1 Inst_Frame11_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[403]),
+	.QN(ConfigBits_N[403])
+	);
+
+	LHQD1 Inst_Frame11_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[410]),
+	.QN(ConfigBits_N[410])
+	);
+
+	LHQD1 Inst_Frame11_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[394]),
+	.QN(ConfigBits_N[394])
+	);
+
+	LHQD1 Inst_Frame11_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[416]),
+	.QN(ConfigBits_N[416])
+	);
+
+	LHQD1 Inst_Frame11_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[417]),
+	.QN(ConfigBits_N[417])
+	);
+
+	LHQD1 Inst_Frame11_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[400]),
+	.QN(ConfigBits_N[400])
+	);
+
+	LHQD1 Inst_Frame11_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[387]),
+	.QN(ConfigBits_N[387])
+	);
+
+	LHQD1 Inst_Frame11_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[339]),
+	.QN(ConfigBits_N[339])
+	);
+
+	LHQD1 Inst_Frame11_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[355]),
+	.QN(ConfigBits_N[355])
+	);
+
+	LHQD1 Inst_Frame11_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[331]),
+	.QN(ConfigBits_N[331])
+	);
+
+	LHQD1 Inst_Frame11_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[332]),
+	.QN(ConfigBits_N[332])
+	);
+
+	LHQD1 Inst_Frame11_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[296]),
+	.QN(ConfigBits_N[296])
+	);
+
+	LHQD1 Inst_Frame11_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[318]),
+	.QN(ConfigBits_N[318])
+	);
+
+	LHQD1 Inst_Frame11_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[322]),
+	.QN(ConfigBits_N[322])
+	);
+
+	LHQD1 Inst_Frame12_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[594]),
+	.QN(ConfigBits_N[594])
+	);
+
+	LHQD1 Inst_Frame12_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[586]),
+	.QN(ConfigBits_N[586])
+	);
+
+	LHQD1 Inst_Frame12_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[612]),
+	.QN(ConfigBits_N[612])
+	);
+
+	LHQD1 Inst_Frame12_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[587]),
+	.QN(ConfigBits_N[587])
+	);
+
+	LHQD1 Inst_Frame12_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[593]),
+	.QN(ConfigBits_N[593])
+	);
+
+	LHQD1 Inst_Frame12_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[266]),
+	.QN(ConfigBits_N[266])
+	);
+
+	LHQD1 Inst_Frame12_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[269]),
+	.QN(ConfigBits_N[269])
+	);
+
+	LHQD1 Inst_Frame12_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[223]),
+	.QN(ConfigBits_N[223])
+	);
+
+	LHQD1 Inst_Frame12_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[224]),
+	.QN(ConfigBits_N[224])
+	);
+
+	LHQD1 Inst_Frame12_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[225]),
+	.QN(ConfigBits_N[225])
+	);
+
+	LHQD1 Inst_Frame12_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[227]),
+	.QN(ConfigBits_N[227])
+	);
+
+	LHQD1 Inst_Frame12_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[191]),
+	.QN(ConfigBits_N[191])
+	);
+
+	LHQD1 Inst_Frame12_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[148]),
+	.QN(ConfigBits_N[148])
+	);
+
+	LHQD1 Inst_Frame12_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[150]),
+	.QN(ConfigBits_N[150])
+	);
+
+	LHQD1 Inst_Frame12_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[143]),
+	.QN(ConfigBits_N[143])
+	);
+
+	LHQD1 Inst_Frame12_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[116]),
+	.QN(ConfigBits_N[116])
+	);
+
+	LHQD1 Inst_Frame12_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[122]),
+	.QN(ConfigBits_N[122])
+	);
+
+	LHQD1 Inst_Frame12_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[123]),
+	.QN(ConfigBits_N[123])
+	);
+
+	LHQD1 Inst_Frame12_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[131]),
+	.QN(ConfigBits_N[131])
+	);
+
+	LHQD1 Inst_Frame12_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[135]),
+	.QN(ConfigBits_N[135])
+	);
+
+	LHQD1 Inst_Frame12_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_Frame12_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_Frame12_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[392]),
+	.QN(ConfigBits_N[392])
+	);
+
+	LHQD1 Inst_Frame12_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[408]),
+	.QN(ConfigBits_N[408])
+	);
+
+	LHQD1 Inst_Frame12_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[401]),
+	.QN(ConfigBits_N[401])
+	);
+
+	LHQD1 Inst_Frame12_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[372]),
+	.QN(ConfigBits_N[372])
+	);
+
+	LHQD1 Inst_Frame12_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[362]),
+	.QN(ConfigBits_N[362])
+	);
+
+	LHQD1 Inst_Frame12_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[342]),
+	.QN(ConfigBits_N[342])
+	);
+
+	LHQD1 Inst_Frame12_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[333]),
+	.QN(ConfigBits_N[333])
+	);
+
+	LHQD1 Inst_Frame12_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[337]),
+	.QN(ConfigBits_N[337])
+	);
+
+	LHQD1 Inst_Frame12_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[297]),
+	.QN(ConfigBits_N[297])
+	);
+
+	LHQD1 Inst_Frame12_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[327]),
+	.QN(ConfigBits_N[327])
+	);
+
+	LHQD1 Inst_Frame13_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[595]),
+	.QN(ConfigBits_N[595])
+	);
+
+	LHQD1 Inst_Frame13_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[611]),
+	.QN(ConfigBits_N[611])
+	);
+
+	LHQD1 Inst_Frame13_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[613]),
+	.QN(ConfigBits_N[613])
+	);
+
+	LHQD1 Inst_Frame13_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[592]),
+	.QN(ConfigBits_N[592])
+	);
+
+	LHQD1 Inst_Frame13_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[276]),
+	.QN(ConfigBits_N[276])
+	);
+
+	LHQD1 Inst_Frame13_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[277]),
+	.QN(ConfigBits_N[277])
+	);
+
+	LHQD1 Inst_Frame13_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[287]),
+	.QN(ConfigBits_N[287])
+	);
+
+	LHQD1 Inst_Frame13_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[288]),
+	.QN(ConfigBits_N[288])
+	);
+
+	LHQD1 Inst_Frame13_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[267]),
+	.QN(ConfigBits_N[267])
+	);
+
+	LHQD1 Inst_Frame13_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[226]),
+	.QN(ConfigBits_N[226])
+	);
+
+	LHQD1 Inst_Frame13_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[189]),
+	.QN(ConfigBits_N[189])
+	);
+
+	LHQD1 Inst_Frame13_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[190]),
+	.QN(ConfigBits_N[190])
+	);
+
+	LHQD1 Inst_Frame13_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[149]),
+	.QN(ConfigBits_N[149])
+	);
+
+	LHQD1 Inst_Frame13_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[141]),
+	.QN(ConfigBits_N[141])
+	);
+
+	LHQD1 Inst_Frame13_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[142]),
+	.QN(ConfigBits_N[142])
+	);
+
+	LHQD1 Inst_Frame13_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[145]),
+	.QN(ConfigBits_N[145])
+	);
+
+	LHQD1 Inst_Frame13_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[124]),
+	.QN(ConfigBits_N[124])
+	);
+
+	LHQD1 Inst_Frame13_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[125]),
+	.QN(ConfigBits_N[125])
+	);
+
+	LHQD1 Inst_Frame13_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_Frame13_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_Frame13_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[393]),
+	.QN(ConfigBits_N[393])
+	);
+
+	LHQD1 Inst_Frame13_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[406]),
+	.QN(ConfigBits_N[406])
+	);
+
+	LHQD1 Inst_Frame13_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[407]),
+	.QN(ConfigBits_N[407])
+	);
+
+	LHQD1 Inst_Frame13_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[409]),
+	.QN(ConfigBits_N[409])
+	);
+
+	LHQD1 Inst_Frame13_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[373]),
+	.QN(ConfigBits_N[373])
+	);
+
+	LHQD1 Inst_Frame13_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[365]),
+	.QN(ConfigBits_N[365])
+	);
+
+	LHQD1 Inst_Frame13_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[343]),
+	.QN(ConfigBits_N[343])
+	);
+
+	LHQD1 Inst_Frame13_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[306]),
+	.QN(ConfigBits_N[306])
+	);
+
+	LHQD1 Inst_Frame13_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[313]),
+	.QN(ConfigBits_N[313])
+	);
+
+	LHQD1 Inst_Frame13_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[321]),
+	.QN(ConfigBits_N[321])
+	);
+
+	LHQD1 Inst_Frame13_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[326]),
+	.QN(ConfigBits_N[326])
+	);
+
+	LHQD1 Inst_Frame13_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[13]),
+	.Q(ConfigBits[302]),
+	.QN(ConfigBits_N[302])
+	);
+
+	LHQD1 Inst_Frame14_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[614]),
+	.QN(ConfigBits_N[614])
+	);
+
+	LHQD1 Inst_Frame14_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[278]),
+	.QN(ConfigBits_N[278])
+	);
+
+	LHQD1 Inst_Frame14_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[291]),
+	.QN(ConfigBits_N[291])
+	);
+
+	LHQD1 Inst_Frame14_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[293]),
+	.QN(ConfigBits_N[293])
+	);
+
+	LHQD1 Inst_Frame14_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[272]),
+	.QN(ConfigBits_N[272])
+	);
+
+	LHQD1 Inst_Frame14_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[228]),
+	.QN(ConfigBits_N[228])
+	);
+
+	LHQD1 Inst_Frame14_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[182]),
+	.QN(ConfigBits_N[182])
+	);
+
+	LHQD1 Inst_Frame14_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[183]),
+	.QN(ConfigBits_N[183])
+	);
+
+	LHQD1 Inst_Frame14_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[192]),
+	.QN(ConfigBits_N[192])
+	);
+
+	LHQD1 Inst_Frame14_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[147]),
+	.QN(ConfigBits_N[147])
+	);
+
+	LHQD1 Inst_Frame14_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[144]),
+	.QN(ConfigBits_N[144])
+	);
+
+	LHQD1 Inst_Frame14_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[130]),
+	.QN(ConfigBits_N[130])
+	);
+
+	LHQD1 Inst_Frame14_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_Frame14_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_Frame14_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_Frame14_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_Frame14_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_Frame14_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[399]),
+	.QN(ConfigBits_N[399])
+	);
+
+	LHQD1 Inst_Frame14_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[364]),
+	.QN(ConfigBits_N[364])
+	);
+
+	LHQD1 Inst_Frame14_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[344]),
+	.QN(ConfigBits_N[344])
+	);
+
+	LHQD1 Inst_Frame14_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[356]),
+	.QN(ConfigBits_N[356])
+	);
+
+	LHQD1 Inst_Frame14_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[357]),
+	.QN(ConfigBits_N[357])
+	);
+
+	LHQD1 Inst_Frame14_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[334]),
+	.QN(ConfigBits_N[334])
+	);
+
+	LHQD1 Inst_Frame14_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[307]),
+	.QN(ConfigBits_N[307])
+	);
+
+	LHQD1 Inst_Frame14_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[308]),
+	.QN(ConfigBits_N[308])
+	);
+
+	LHQD1 Inst_Frame14_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[310]),
+	.QN(ConfigBits_N[310])
+	);
+
+	LHQD1 Inst_Frame14_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[312]),
+	.QN(ConfigBits_N[312])
+	);
+
+	LHQD1 Inst_Frame14_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[316]),
+	.QN(ConfigBits_N[316])
+	);
+
+	LHQD1 Inst_Frame14_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[320]),
+	.QN(ConfigBits_N[320])
+	);
+
+	LHQD1 Inst_Frame14_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[323]),
+	.QN(ConfigBits_N[323])
+	);
+
+	LHQD1 Inst_Frame14_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[303]),
+	.QN(ConfigBits_N[303])
+	);
+
+	LHQD1 Inst_Frame14_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[14]),
+	.Q(ConfigBits[305]),
+	.QN(ConfigBits_N[305])
+	);
+
+	LHQD1 Inst_Frame15_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[275]),
+	.QN(ConfigBits_N[275])
+	);
+
+	LHQD1 Inst_Frame15_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[279]),
+	.QN(ConfigBits_N[279])
+	);
+
+	LHQD1 Inst_Frame15_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[282]),
+	.QN(ConfigBits_N[282])
+	);
+
+	LHQD1 Inst_Frame15_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[289]),
+	.QN(ConfigBits_N[289])
+	);
+
+	LHQD1 Inst_Frame15_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[268]),
+	.QN(ConfigBits_N[268])
+	);
+
+	LHQD1 Inst_Frame15_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[273]),
+	.QN(ConfigBits_N[273])
+	);
+
+	LHQD1 Inst_Frame15_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[132]),
+	.QN(ConfigBits_N[132])
+	);
+
+	LHQD1 Inst_Frame15_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_Frame15_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_Frame15_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_Frame15_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_Frame15_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_Frame15_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_Frame15_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_Frame15_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_Frame15_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_Frame15_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_Frame15_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_Frame15_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_Frame15_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_Frame15_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_Frame15_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_Frame15_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_Frame15_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_Frame15_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_Frame15_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_Frame15_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[309]),
+	.QN(ConfigBits_N[309])
+	);
+
+	LHQD1 Inst_Frame15_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[298]),
+	.QN(ConfigBits_N[298])
+	);
+
+	LHQD1 Inst_Frame15_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[317]),
+	.QN(ConfigBits_N[317])
+	);
+
+	LHQD1 Inst_Frame15_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[319]),
+	.QN(ConfigBits_N[319])
+	);
+
+	LHQD1 Inst_Frame15_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[300]),
+	.QN(ConfigBits_N[300])
+	);
+
+	LHQD1 Inst_Frame15_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[15]),
+	.Q(ConfigBits[301]),
+	.QN(ConfigBits_N[301])
+	);
+
+	LHQD1 Inst_Frame16_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[274]),
+	.QN(ConfigBits_N[274])
+	);
+
+	LHQD1 Inst_Frame16_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[283]),
+	.QN(ConfigBits_N[283])
+	);
+
+	LHQD1 Inst_Frame16_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_Frame16_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_Frame16_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_Frame16_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_Frame16_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_Frame16_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_Frame16_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_Frame16_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_Frame16_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_Frame16_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_Frame16_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_Frame16_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_Frame16_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_Frame16_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_Frame16_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_Frame16_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_Frame16_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_Frame16_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_Frame16_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_Frame16_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_Frame16_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_Frame16_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_Frame16_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_Frame16_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_Frame16_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_Frame16_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_Frame16_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_Frame16_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_Frame16_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[345]),
+	.QN(ConfigBits_N[345])
+	);
+
+	LHQD1 Inst_Frame16_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[16]),
+	.Q(ConfigBits[335]),
+	.QN(ConfigBits_N[335])
+	);
+
+	LHQD1 Inst_Frame17_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[285]),
+	.QN(ConfigBits_N[285])
+	);
+
+	LHQD1 Inst_Frame17_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[295]),
+	.QN(ConfigBits_N[295])
+	);
+
+	LHQD1 Inst_Frame17_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_Frame17_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_Frame17_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_Frame17_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_Frame17_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_Frame17_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_Frame17_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_Frame17_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_Frame17_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_Frame17_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_Frame17_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_Frame17_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_Frame17_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_Frame17_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_Frame17_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_Frame17_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_Frame17_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_Frame17_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_Frame17_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_Frame17_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_Frame17_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_Frame17_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_Frame17_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+	LHQD1 Inst_Frame17_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_Frame17_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_Frame17_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_Frame17_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_Frame17_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[325]),
+	.QN(ConfigBits_N[325])
+	);
+
+	LHQD1 Inst_Frame17_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[299]),
+	.QN(ConfigBits_N[299])
+	);
+
+	LHQD1 Inst_Frame17_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[17]),
+	.Q(ConfigBits[304]),
+	.QN(ConfigBits_N[304])
+	);
+
+	LHQD1 Inst_Frame18_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[284]),
+	.QN(ConfigBits_N[284])
+	);
+
+	LHQD1 Inst_Frame18_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[294]),
+	.QN(ConfigBits_N[294])
+	);
+
+	LHQD1 Inst_Frame18_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_Frame18_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_Frame18_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_Frame18_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_Frame18_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_Frame18_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_Frame18_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_Frame18_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_Frame18_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_Frame18_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_Frame18_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_Frame18_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_Frame18_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_Frame18_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_Frame18_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_Frame18_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_Frame18_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_Frame18_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_Frame18_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_Frame18_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_Frame18_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_Frame18_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_Frame18_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_Frame18_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_Frame18_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_Frame18_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_Frame18_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_Frame18_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[314]),
+	.QN(ConfigBits_N[314])
+	);
+
+	LHQD1 Inst_Frame18_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[315]),
+	.QN(ConfigBits_N[315])
+	);
+
+	LHQD1 Inst_Frame18_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[18]),
+	.Q(ConfigBits[324]),
+	.QN(ConfigBits_N[324])
+	);
+
+	LHQD1 Inst_Frame19_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[246]),
+	.QN(ConfigBits_N[246])
+	);
+
+	LHQD1 Inst_Frame19_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[252]),
+	.QN(ConfigBits_N[252])
+	);
+
+	LHQD1 Inst_Frame19_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[253]),
+	.QN(ConfigBits_N[253])
+	);
+
+	LHQD1 Inst_Frame19_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[254]),
+	.QN(ConfigBits_N[254])
+	);
+
+	LHQD1 Inst_Frame19_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[258]),
+	.QN(ConfigBits_N[258])
+	);
+
+	LHQD1 Inst_Frame19_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[238]),
+	.QN(ConfigBits_N[238])
+	);
+
+	LHQD1 Inst_Frame19_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[239]),
+	.QN(ConfigBits_N[239])
+	);
+
+	LHQD1 Inst_Frame19_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[154]),
+	.QN(ConfigBits_N[154])
+	);
+
+	LHQD1 Inst_Frame19_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[155]),
+	.QN(ConfigBits_N[155])
+	);
+
+	LHQD1 Inst_Frame19_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[156]),
+	.QN(ConfigBits_N[156])
+	);
+
+	LHQD1 Inst_Frame19_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[562]),
+	.QN(ConfigBits_N[562])
+	);
+
+	LHQD1 Inst_Frame19_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[566]),
+	.QN(ConfigBits_N[566])
+	);
+
+	LHQD1 Inst_Frame19_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[567]),
+	.QN(ConfigBits_N[567])
+	);
+
+	LHQD1 Inst_Frame19_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[574]),
+	.QN(ConfigBits_N[574])
+	);
+
+	LHQD1 Inst_Frame19_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[575]),
+	.QN(ConfigBits_N[575])
+	);
+
+	LHQD1 Inst_Frame19_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[467]),
+	.QN(ConfigBits_N[467])
+	);
+
+	LHQD1 Inst_Frame19_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[470]),
+	.QN(ConfigBits_N[470])
+	);
+
+	LHQD1 Inst_Frame19_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[471]),
+	.QN(ConfigBits_N[471])
+	);
+
+	LHQD1 Inst_Frame19_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[478]),
+	.QN(ConfigBits_N[478])
+	);
+
+	LHQD1 Inst_Frame19_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[479]),
+	.QN(ConfigBits_N[479])
+	);
+
+	LHQD1 Inst_Frame19_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[404]),
+	.QN(ConfigBits_N[404])
+	);
+
+	LHQD1 Inst_Frame19_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[405]),
+	.QN(ConfigBits_N[405])
+	);
+
+	LHQD1 Inst_Frame19_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[412]),
+	.QN(ConfigBits_N[412])
+	);
+
+	LHQD1 Inst_Frame19_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[19]),
+	.Q(ConfigBits[396]),
+	.QN(ConfigBits_N[396])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/LUT4AB_switch_matrix.v b/verilog/rtl/eFPGA_core/LUT4AB_switch_matrix.v
new file mode 100644
index 0000000..c229ab1
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/LUT4AB_switch_matrix.v
@@ -0,0 +1,4685 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:462
+module LUT4AB_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, NN4END0, NN4END1, NN4END2, NN4END3, Ci0, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, E6END0, E6END1, S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, SS4END0, SS4END1, SS4END2, SS4END3, W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, W6END0, W6END1, LA_O, LA_Co, LB_O, LB_Co, LC_O, LC_Co, LD_O, LD_Co, LE_O, LE_Co, LF_O, LF_Co, LG_O, LG_Co, LH_O, LH_Co, M_AB, M_AD, M_AH, M_EF, J2MID_ABa_END0, J2MID_ABa_END1, J2MID_ABa_END2, J2MID_ABa_END3, J2MID_CDa_END0, J2MID_CDa_END1, J2MID_CDa_END2, J2MID_CDa_END3, J2MID_EFa_END0, J2MID_EFa_END1, J2MID_EFa_END2, J2MID_EFa_END3, J2MID_GHa_END0, J2MID_GHa_END1, J2MID_GHa_END2, J2MID_GHa_END3, J2MID_ABb_END0, J2MID_ABb_END1, J2MID_ABb_END2, J2MID_ABb_END3, J2MID_CDb_END0, J2MID_CDb_END1, J2MID_CDb_END2, J2MID_CDb_END3, J2MID_EFb_END0, J2MID_EFb_END1, J2MID_EFb_END2, J2MID_EFb_END3, J2MID_GHb_END0, J2MID_GHb_END1, J2MID_GHb_END2, J2MID_GHb_END3, J2END_AB_END0, J2END_AB_END1, J2END_AB_END2, J2END_AB_END3, J2END_CD_END0, J2END_CD_END1, J2END_CD_END2, J2END_CD_END3, J2END_EF_END0, J2END_EF_END1, J2END_EF_END2, J2END_EF_END3, J2END_GH_END0, J2END_GH_END1, J2END_GH_END2, J2END_GH_END3, JN2END0, JN2END1, JN2END2, JN2END3, JN2END4, JN2END5, JN2END6, JN2END7, JE2END0, JE2END1, JE2END2, JE2END3, JE2END4, JE2END5, JE2END6, JE2END7, JS2END0, JS2END1, JS2END2, JS2END3, JS2END4, JS2END5, JS2END6, JS2END7, JW2END0, JW2END1, JW2END2, JW2END3, JW2END4, JW2END5, JW2END6, JW2END7, J_l_AB_END0, J_l_AB_END1, J_l_AB_END2, J_l_AB_END3, J_l_CD_END0, J_l_CD_END1, J_l_CD_END2, J_l_CD_END3, J_l_EF_END0, J_l_EF_END1, J_l_EF_END2, J_l_EF_END3, J_l_GH_END0, J_l_GH_END1, J_l_GH_END2, J_l_GH_END3, J_SR_END0, J_EN_END0, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, Co0, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, E6BEG0, E6BEG1, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, W6BEG0, W6BEG1, LA_I0, LA_I1, LA_I2, LA_I3, LA_Ci, LA_SR, LA_EN, LB_I0, LB_I1, LB_I2, LB_I3, LB_Ci, LB_SR, LB_EN, LC_I0, LC_I1, LC_I2, LC_I3, LC_Ci, LC_SR, LC_EN, LD_I0, LD_I1, LD_I2, LD_I3, LD_Ci, LD_SR, LD_EN, LE_I0, LE_I1, LE_I2, LE_I3, LE_Ci, LE_SR, LE_EN, LF_I0, LF_I1, LF_I2, LF_I3, LF_Ci, LF_SR, LF_EN, LG_I0, LG_I1, LG_I2, LG_I3, LG_Ci, LG_SR, LG_EN, LH_I0, LH_I1, LH_I2, LH_I3, LH_Ci, LH_SR, LH_EN, A, B, C, D, E, F, G, H, S0, S1, S2, S3, J2MID_ABa_BEG0, J2MID_ABa_BEG1, J2MID_ABa_BEG2, J2MID_ABa_BEG3, J2MID_CDa_BEG0, J2MID_CDa_BEG1, J2MID_CDa_BEG2, J2MID_CDa_BEG3, J2MID_EFa_BEG0, J2MID_EFa_BEG1, J2MID_EFa_BEG2, J2MID_EFa_BEG3, J2MID_GHa_BEG0, J2MID_GHa_BEG1, J2MID_GHa_BEG2, J2MID_GHa_BEG3, J2MID_ABb_BEG0, J2MID_ABb_BEG1, J2MID_ABb_BEG2, J2MID_ABb_BEG3, J2MID_CDb_BEG0, J2MID_CDb_BEG1, J2MID_CDb_BEG2, J2MID_CDb_BEG3, J2MID_EFb_BEG0, J2MID_EFb_BEG1, J2MID_EFb_BEG2, J2MID_EFb_BEG3, J2MID_GHb_BEG0, J2MID_GHb_BEG1, J2MID_GHb_BEG2, J2MID_GHb_BEG3, J2END_AB_BEG0, J2END_AB_BEG1, J2END_AB_BEG2, J2END_AB_BEG3, J2END_CD_BEG0, J2END_CD_BEG1, J2END_CD_BEG2, J2END_CD_BEG3, J2END_EF_BEG0, J2END_EF_BEG1, J2END_EF_BEG2, J2END_EF_BEG3, J2END_GH_BEG0, J2END_GH_BEG1, J2END_GH_BEG2, J2END_GH_BEG3, JN2BEG0, JN2BEG1, JN2BEG2, JN2BEG3, JN2BEG4, JN2BEG5, JN2BEG6, JN2BEG7, JE2BEG0, JE2BEG1, JE2BEG2, JE2BEG3, JE2BEG4, JE2BEG5, JE2BEG6, JE2BEG7, JS2BEG0, JS2BEG1, JS2BEG2, JS2BEG3, JS2BEG4, JS2BEG5, JS2BEG6, JS2BEG7, JW2BEG0, JW2BEG1, JW2BEG2, JW2BEG3, JW2BEG4, JW2BEG5, JW2BEG6, JW2BEG7, J_l_AB_BEG0, J_l_AB_BEG1, J_l_AB_BEG2, J_l_AB_BEG3, J_l_CD_BEG0, J_l_CD_BEG1, J_l_CD_BEG2, J_l_CD_BEG3, J_l_EF_BEG0, J_l_EF_BEG1, J_l_EF_BEG2, J_l_EF_BEG3, J_l_GH_BEG0, J_l_GH_BEG1, J_l_GH_BEG2, J_l_GH_BEG3, J_SR_BEG0, J_EN_BEG0, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 462;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input Ci0;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input E6END0;
+	input E6END1;
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input W6END0;
+	input W6END1;
+	input LA_O;
+	input LA_Co;
+	input LB_O;
+	input LB_Co;
+	input LC_O;
+	input LC_Co;
+	input LD_O;
+	input LD_Co;
+	input LE_O;
+	input LE_Co;
+	input LF_O;
+	input LF_Co;
+	input LG_O;
+	input LG_Co;
+	input LH_O;
+	input LH_Co;
+	input M_AB;
+	input M_AD;
+	input M_AH;
+	input M_EF;
+	input J2MID_ABa_END0;
+	input J2MID_ABa_END1;
+	input J2MID_ABa_END2;
+	input J2MID_ABa_END3;
+	input J2MID_CDa_END0;
+	input J2MID_CDa_END1;
+	input J2MID_CDa_END2;
+	input J2MID_CDa_END3;
+	input J2MID_EFa_END0;
+	input J2MID_EFa_END1;
+	input J2MID_EFa_END2;
+	input J2MID_EFa_END3;
+	input J2MID_GHa_END0;
+	input J2MID_GHa_END1;
+	input J2MID_GHa_END2;
+	input J2MID_GHa_END3;
+	input J2MID_ABb_END0;
+	input J2MID_ABb_END1;
+	input J2MID_ABb_END2;
+	input J2MID_ABb_END3;
+	input J2MID_CDb_END0;
+	input J2MID_CDb_END1;
+	input J2MID_CDb_END2;
+	input J2MID_CDb_END3;
+	input J2MID_EFb_END0;
+	input J2MID_EFb_END1;
+	input J2MID_EFb_END2;
+	input J2MID_EFb_END3;
+	input J2MID_GHb_END0;
+	input J2MID_GHb_END1;
+	input J2MID_GHb_END2;
+	input J2MID_GHb_END3;
+	input J2END_AB_END0;
+	input J2END_AB_END1;
+	input J2END_AB_END2;
+	input J2END_AB_END3;
+	input J2END_CD_END0;
+	input J2END_CD_END1;
+	input J2END_CD_END2;
+	input J2END_CD_END3;
+	input J2END_EF_END0;
+	input J2END_EF_END1;
+	input J2END_EF_END2;
+	input J2END_EF_END3;
+	input J2END_GH_END0;
+	input J2END_GH_END1;
+	input J2END_GH_END2;
+	input J2END_GH_END3;
+	input JN2END0;
+	input JN2END1;
+	input JN2END2;
+	input JN2END3;
+	input JN2END4;
+	input JN2END5;
+	input JN2END6;
+	input JN2END7;
+	input JE2END0;
+	input JE2END1;
+	input JE2END2;
+	input JE2END3;
+	input JE2END4;
+	input JE2END5;
+	input JE2END6;
+	input JE2END7;
+	input JS2END0;
+	input JS2END1;
+	input JS2END2;
+	input JS2END3;
+	input JS2END4;
+	input JS2END5;
+	input JS2END6;
+	input JS2END7;
+	input JW2END0;
+	input JW2END1;
+	input JW2END2;
+	input JW2END3;
+	input JW2END4;
+	input JW2END5;
+	input JW2END6;
+	input JW2END7;
+	input J_l_AB_END0;
+	input J_l_AB_END1;
+	input J_l_AB_END2;
+	input J_l_AB_END3;
+	input J_l_CD_END0;
+	input J_l_CD_END1;
+	input J_l_CD_END2;
+	input J_l_CD_END3;
+	input J_l_EF_END0;
+	input J_l_EF_END1;
+	input J_l_EF_END2;
+	input J_l_EF_END3;
+	input J_l_GH_END0;
+	input J_l_GH_END1;
+	input J_l_GH_END2;
+	input J_l_GH_END3;
+	input J_SR_END0;
+	input J_EN_END0;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output Co0;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output E6BEG0;
+	output E6BEG1;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output W6BEG0;
+	output W6BEG1;
+	output LA_I0;
+	output LA_I1;
+	output LA_I2;
+	output LA_I3;
+	output LA_Ci;
+	output LA_SR;
+	output LA_EN;
+	output LB_I0;
+	output LB_I1;
+	output LB_I2;
+	output LB_I3;
+	output LB_Ci;
+	output LB_SR;
+	output LB_EN;
+	output LC_I0;
+	output LC_I1;
+	output LC_I2;
+	output LC_I3;
+	output LC_Ci;
+	output LC_SR;
+	output LC_EN;
+	output LD_I0;
+	output LD_I1;
+	output LD_I2;
+	output LD_I3;
+	output LD_Ci;
+	output LD_SR;
+	output LD_EN;
+	output LE_I0;
+	output LE_I1;
+	output LE_I2;
+	output LE_I3;
+	output LE_Ci;
+	output LE_SR;
+	output LE_EN;
+	output LF_I0;
+	output LF_I1;
+	output LF_I2;
+	output LF_I3;
+	output LF_Ci;
+	output LF_SR;
+	output LF_EN;
+	output LG_I0;
+	output LG_I1;
+	output LG_I2;
+	output LG_I3;
+	output LG_Ci;
+	output LG_SR;
+	output LG_EN;
+	output LH_I0;
+	output LH_I1;
+	output LH_I2;
+	output LH_I3;
+	output LH_Ci;
+	output LH_SR;
+	output LH_EN;
+	output A;
+	output B;
+	output C;
+	output D;
+	output E;
+	output F;
+	output G;
+	output H;
+	output S0;
+	output S1;
+	output S2;
+	output S3;
+	output J2MID_ABa_BEG0;
+	output J2MID_ABa_BEG1;
+	output J2MID_ABa_BEG2;
+	output J2MID_ABa_BEG3;
+	output J2MID_CDa_BEG0;
+	output J2MID_CDa_BEG1;
+	output J2MID_CDa_BEG2;
+	output J2MID_CDa_BEG3;
+	output J2MID_EFa_BEG0;
+	output J2MID_EFa_BEG1;
+	output J2MID_EFa_BEG2;
+	output J2MID_EFa_BEG3;
+	output J2MID_GHa_BEG0;
+	output J2MID_GHa_BEG1;
+	output J2MID_GHa_BEG2;
+	output J2MID_GHa_BEG3;
+	output J2MID_ABb_BEG0;
+	output J2MID_ABb_BEG1;
+	output J2MID_ABb_BEG2;
+	output J2MID_ABb_BEG3;
+	output J2MID_CDb_BEG0;
+	output J2MID_CDb_BEG1;
+	output J2MID_CDb_BEG2;
+	output J2MID_CDb_BEG3;
+	output J2MID_EFb_BEG0;
+	output J2MID_EFb_BEG1;
+	output J2MID_EFb_BEG2;
+	output J2MID_EFb_BEG3;
+	output J2MID_GHb_BEG0;
+	output J2MID_GHb_BEG1;
+	output J2MID_GHb_BEG2;
+	output J2MID_GHb_BEG3;
+	output J2END_AB_BEG0;
+	output J2END_AB_BEG1;
+	output J2END_AB_BEG2;
+	output J2END_AB_BEG3;
+	output J2END_CD_BEG0;
+	output J2END_CD_BEG1;
+	output J2END_CD_BEG2;
+	output J2END_CD_BEG3;
+	output J2END_EF_BEG0;
+	output J2END_EF_BEG1;
+	output J2END_EF_BEG2;
+	output J2END_EF_BEG3;
+	output J2END_GH_BEG0;
+	output J2END_GH_BEG1;
+	output J2END_GH_BEG2;
+	output J2END_GH_BEG3;
+	output JN2BEG0;
+	output JN2BEG1;
+	output JN2BEG2;
+	output JN2BEG3;
+	output JN2BEG4;
+	output JN2BEG5;
+	output JN2BEG6;
+	output JN2BEG7;
+	output JE2BEG0;
+	output JE2BEG1;
+	output JE2BEG2;
+	output JE2BEG3;
+	output JE2BEG4;
+	output JE2BEG5;
+	output JE2BEG6;
+	output JE2BEG7;
+	output JS2BEG0;
+	output JS2BEG1;
+	output JS2BEG2;
+	output JS2BEG3;
+	output JS2BEG4;
+	output JS2BEG5;
+	output JS2BEG6;
+	output JS2BEG7;
+	output JW2BEG0;
+	output JW2BEG1;
+	output JW2BEG2;
+	output JW2BEG3;
+	output JW2BEG4;
+	output JW2BEG5;
+	output JW2BEG6;
+	output JW2BEG7;
+	output J_l_AB_BEG0;
+	output J_l_AB_BEG1;
+	output J_l_AB_BEG2;
+	output J_l_AB_BEG3;
+	output J_l_CD_BEG0;
+	output J_l_CD_BEG1;
+	output J_l_CD_BEG2;
+	output J_l_CD_BEG3;
+	output J_l_EF_BEG0;
+	output J_l_EF_BEG1;
+	output J_l_EF_BEG2;
+	output J_l_EF_BEG3;
+	output J_l_GH_BEG0;
+	output J_l_GH_BEG1;
+	output J_l_GH_BEG2;
+	output J_l_GH_BEG3;
+	output J_SR_BEG0;
+	output J_EN_BEG0;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [4-1:0] N1BEG0_input;
+	wire [4-1:0] N1BEG1_input;
+	wire [4-1:0] N1BEG2_input;
+	wire [4-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [4-1:0] N4BEG0_input;
+	wire [4-1:0] N4BEG1_input;
+	wire [4-1:0] N4BEG2_input;
+	wire [4-1:0] N4BEG3_input;
+	wire [8-1:0] NN4BEG0_input;
+	wire [8-1:0] NN4BEG1_input;
+	wire [8-1:0] NN4BEG2_input;
+	wire [8-1:0] NN4BEG3_input;
+	wire [1-1:0] Co0_input;
+	wire [4-1:0] E1BEG0_input;
+	wire [4-1:0] E1BEG1_input;
+	wire [4-1:0] E1BEG2_input;
+	wire [4-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [8-1:0] EE4BEG0_input;
+	wire [8-1:0] EE4BEG1_input;
+	wire [8-1:0] EE4BEG2_input;
+	wire [8-1:0] EE4BEG3_input;
+	wire [16-1:0] E6BEG0_input;
+	wire [16-1:0] E6BEG1_input;
+	wire [4-1:0] S1BEG0_input;
+	wire [4-1:0] S1BEG1_input;
+	wire [4-1:0] S1BEG2_input;
+	wire [4-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [4-1:0] S4BEG0_input;
+	wire [4-1:0] S4BEG1_input;
+	wire [4-1:0] S4BEG2_input;
+	wire [4-1:0] S4BEG3_input;
+	wire [8-1:0] SS4BEG0_input;
+	wire [8-1:0] SS4BEG1_input;
+	wire [8-1:0] SS4BEG2_input;
+	wire [8-1:0] SS4BEG3_input;
+	wire [4-1:0] W1BEG0_input;
+	wire [4-1:0] W1BEG1_input;
+	wire [4-1:0] W1BEG2_input;
+	wire [4-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [8-1:0] WW4BEG0_input;
+	wire [8-1:0] WW4BEG1_input;
+	wire [8-1:0] WW4BEG2_input;
+	wire [8-1:0] WW4BEG3_input;
+	wire [16-1:0] W6BEG0_input;
+	wire [16-1:0] W6BEG1_input;
+	wire [4-1:0] LA_I0_input;
+	wire [4-1:0] LA_I1_input;
+	wire [4-1:0] LA_I2_input;
+	wire [4-1:0] LA_I3_input;
+	wire [1-1:0] LA_Ci_input;
+	wire [2-1:0] LA_SR_input;
+	wire [2-1:0] LA_EN_input;
+	wire [4-1:0] LB_I0_input;
+	wire [4-1:0] LB_I1_input;
+	wire [4-1:0] LB_I2_input;
+	wire [4-1:0] LB_I3_input;
+	wire [1-1:0] LB_Ci_input;
+	wire [2-1:0] LB_SR_input;
+	wire [2-1:0] LB_EN_input;
+	wire [4-1:0] LC_I0_input;
+	wire [4-1:0] LC_I1_input;
+	wire [4-1:0] LC_I2_input;
+	wire [4-1:0] LC_I3_input;
+	wire [1-1:0] LC_Ci_input;
+	wire [2-1:0] LC_SR_input;
+	wire [2-1:0] LC_EN_input;
+	wire [4-1:0] LD_I0_input;
+	wire [4-1:0] LD_I1_input;
+	wire [4-1:0] LD_I2_input;
+	wire [4-1:0] LD_I3_input;
+	wire [1-1:0] LD_Ci_input;
+	wire [2-1:0] LD_SR_input;
+	wire [2-1:0] LD_EN_input;
+	wire [4-1:0] LE_I0_input;
+	wire [4-1:0] LE_I1_input;
+	wire [4-1:0] LE_I2_input;
+	wire [4-1:0] LE_I3_input;
+	wire [1-1:0] LE_Ci_input;
+	wire [2-1:0] LE_SR_input;
+	wire [2-1:0] LE_EN_input;
+	wire [4-1:0] LF_I0_input;
+	wire [4-1:0] LF_I1_input;
+	wire [4-1:0] LF_I2_input;
+	wire [4-1:0] LF_I3_input;
+	wire [1-1:0] LF_Ci_input;
+	wire [2-1:0] LF_SR_input;
+	wire [2-1:0] LF_EN_input;
+	wire [4-1:0] LG_I0_input;
+	wire [4-1:0] LG_I1_input;
+	wire [4-1:0] LG_I2_input;
+	wire [4-1:0] LG_I3_input;
+	wire [1-1:0] LG_Ci_input;
+	wire [2-1:0] LG_SR_input;
+	wire [2-1:0] LG_EN_input;
+	wire [4-1:0] LH_I0_input;
+	wire [4-1:0] LH_I1_input;
+	wire [4-1:0] LH_I2_input;
+	wire [4-1:0] LH_I3_input;
+	wire [1-1:0] LH_Ci_input;
+	wire [2-1:0] LH_SR_input;
+	wire [2-1:0] LH_EN_input;
+	wire [1-1:0] A_input;
+	wire [1-1:0] B_input;
+	wire [1-1:0] C_input;
+	wire [1-1:0] D_input;
+	wire [1-1:0] E_input;
+	wire [1-1:0] F_input;
+	wire [1-1:0] G_input;
+	wire [1-1:0] H_input;
+	wire [4-1:0] S0_input;
+	wire [4-1:0] S1_input;
+	wire [4-1:0] S2_input;
+	wire [4-1:0] S3_input;
+	wire [4-1:0] J2MID_ABa_BEG0_input;
+	wire [4-1:0] J2MID_ABa_BEG1_input;
+	wire [4-1:0] J2MID_ABa_BEG2_input;
+	wire [4-1:0] J2MID_ABa_BEG3_input;
+	wire [4-1:0] J2MID_CDa_BEG0_input;
+	wire [4-1:0] J2MID_CDa_BEG1_input;
+	wire [4-1:0] J2MID_CDa_BEG2_input;
+	wire [4-1:0] J2MID_CDa_BEG3_input;
+	wire [4-1:0] J2MID_EFa_BEG0_input;
+	wire [4-1:0] J2MID_EFa_BEG1_input;
+	wire [4-1:0] J2MID_EFa_BEG2_input;
+	wire [4-1:0] J2MID_EFa_BEG3_input;
+	wire [4-1:0] J2MID_GHa_BEG0_input;
+	wire [4-1:0] J2MID_GHa_BEG1_input;
+	wire [4-1:0] J2MID_GHa_BEG2_input;
+	wire [4-1:0] J2MID_GHa_BEG3_input;
+	wire [4-1:0] J2MID_ABb_BEG0_input;
+	wire [4-1:0] J2MID_ABb_BEG1_input;
+	wire [4-1:0] J2MID_ABb_BEG2_input;
+	wire [4-1:0] J2MID_ABb_BEG3_input;
+	wire [4-1:0] J2MID_CDb_BEG0_input;
+	wire [4-1:0] J2MID_CDb_BEG1_input;
+	wire [4-1:0] J2MID_CDb_BEG2_input;
+	wire [4-1:0] J2MID_CDb_BEG3_input;
+	wire [4-1:0] J2MID_EFb_BEG0_input;
+	wire [4-1:0] J2MID_EFb_BEG1_input;
+	wire [4-1:0] J2MID_EFb_BEG2_input;
+	wire [4-1:0] J2MID_EFb_BEG3_input;
+	wire [4-1:0] J2MID_GHb_BEG0_input;
+	wire [4-1:0] J2MID_GHb_BEG1_input;
+	wire [4-1:0] J2MID_GHb_BEG2_input;
+	wire [4-1:0] J2MID_GHb_BEG3_input;
+	wire [4-1:0] J2END_AB_BEG0_input;
+	wire [4-1:0] J2END_AB_BEG1_input;
+	wire [4-1:0] J2END_AB_BEG2_input;
+	wire [4-1:0] J2END_AB_BEG3_input;
+	wire [4-1:0] J2END_CD_BEG0_input;
+	wire [4-1:0] J2END_CD_BEG1_input;
+	wire [4-1:0] J2END_CD_BEG2_input;
+	wire [4-1:0] J2END_CD_BEG3_input;
+	wire [4-1:0] J2END_EF_BEG0_input;
+	wire [4-1:0] J2END_EF_BEG1_input;
+	wire [4-1:0] J2END_EF_BEG2_input;
+	wire [4-1:0] J2END_EF_BEG3_input;
+	wire [4-1:0] J2END_GH_BEG0_input;
+	wire [4-1:0] J2END_GH_BEG1_input;
+	wire [4-1:0] J2END_GH_BEG2_input;
+	wire [4-1:0] J2END_GH_BEG3_input;
+	wire [16-1:0] JN2BEG0_input;
+	wire [16-1:0] JN2BEG1_input;
+	wire [16-1:0] JN2BEG2_input;
+	wire [16-1:0] JN2BEG3_input;
+	wire [16-1:0] JN2BEG4_input;
+	wire [16-1:0] JN2BEG5_input;
+	wire [16-1:0] JN2BEG6_input;
+	wire [16-1:0] JN2BEG7_input;
+	wire [16-1:0] JE2BEG0_input;
+	wire [16-1:0] JE2BEG1_input;
+	wire [16-1:0] JE2BEG2_input;
+	wire [16-1:0] JE2BEG3_input;
+	wire [16-1:0] JE2BEG4_input;
+	wire [16-1:0] JE2BEG5_input;
+	wire [16-1:0] JE2BEG6_input;
+	wire [16-1:0] JE2BEG7_input;
+	wire [16-1:0] JS2BEG0_input;
+	wire [16-1:0] JS2BEG1_input;
+	wire [16-1:0] JS2BEG2_input;
+	wire [16-1:0] JS2BEG3_input;
+	wire [16-1:0] JS2BEG4_input;
+	wire [16-1:0] JS2BEG5_input;
+	wire [16-1:0] JS2BEG6_input;
+	wire [16-1:0] JS2BEG7_input;
+	wire [16-1:0] JW2BEG0_input;
+	wire [16-1:0] JW2BEG1_input;
+	wire [16-1:0] JW2BEG2_input;
+	wire [16-1:0] JW2BEG3_input;
+	wire [16-1:0] JW2BEG4_input;
+	wire [16-1:0] JW2BEG5_input;
+	wire [16-1:0] JW2BEG6_input;
+	wire [16-1:0] JW2BEG7_input;
+	wire [4-1:0] J_l_AB_BEG0_input;
+	wire [4-1:0] J_l_AB_BEG1_input;
+	wire [4-1:0] J_l_AB_BEG2_input;
+	wire [4-1:0] J_l_AB_BEG3_input;
+	wire [4-1:0] J_l_CD_BEG0_input;
+	wire [4-1:0] J_l_CD_BEG1_input;
+	wire [4-1:0] J_l_CD_BEG2_input;
+	wire [4-1:0] J_l_CD_BEG3_input;
+	wire [4-1:0] J_l_EF_BEG0_input;
+	wire [4-1:0] J_l_EF_BEG1_input;
+	wire [4-1:0] J_l_EF_BEG2_input;
+	wire [4-1:0] J_l_EF_BEG3_input;
+	wire [4-1:0] J_l_GH_BEG0_input;
+	wire [4-1:0] J_l_GH_BEG1_input;
+	wire [4-1:0] J_l_GH_BEG2_input;
+	wire [4-1:0] J_l_GH_BEG3_input;
+	wire [8-1:0] J_SR_BEG0_input;
+	wire [8-1:0] J_EN_BEG0_input;
+
+	wire [2-1:0] DEBUG_select_N1BEG0;
+	wire [2-1:0] DEBUG_select_N1BEG1;
+	wire [2-1:0] DEBUG_select_N1BEG2;
+	wire [2-1:0] DEBUG_select_N1BEG3;
+	wire [2-1:0] DEBUG_select_N4BEG0;
+	wire [2-1:0] DEBUG_select_N4BEG1;
+	wire [2-1:0] DEBUG_select_N4BEG2;
+	wire [2-1:0] DEBUG_select_N4BEG3;
+	wire [3-1:0] DEBUG_select_NN4BEG0;
+	wire [3-1:0] DEBUG_select_NN4BEG1;
+	wire [3-1:0] DEBUG_select_NN4BEG2;
+	wire [3-1:0] DEBUG_select_NN4BEG3;
+	wire [2-1:0] DEBUG_select_E1BEG0;
+	wire [2-1:0] DEBUG_select_E1BEG1;
+	wire [2-1:0] DEBUG_select_E1BEG2;
+	wire [2-1:0] DEBUG_select_E1BEG3;
+	wire [3-1:0] DEBUG_select_EE4BEG0;
+	wire [3-1:0] DEBUG_select_EE4BEG1;
+	wire [3-1:0] DEBUG_select_EE4BEG2;
+	wire [3-1:0] DEBUG_select_EE4BEG3;
+	wire [4-1:0] DEBUG_select_E6BEG0;
+	wire [4-1:0] DEBUG_select_E6BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG0;
+	wire [2-1:0] DEBUG_select_S1BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG2;
+	wire [2-1:0] DEBUG_select_S1BEG3;
+	wire [2-1:0] DEBUG_select_S4BEG0;
+	wire [2-1:0] DEBUG_select_S4BEG1;
+	wire [2-1:0] DEBUG_select_S4BEG2;
+	wire [2-1:0] DEBUG_select_S4BEG3;
+	wire [3-1:0] DEBUG_select_SS4BEG0;
+	wire [3-1:0] DEBUG_select_SS4BEG1;
+	wire [3-1:0] DEBUG_select_SS4BEG2;
+	wire [3-1:0] DEBUG_select_SS4BEG3;
+	wire [2-1:0] DEBUG_select_W1BEG0;
+	wire [2-1:0] DEBUG_select_W1BEG1;
+	wire [2-1:0] DEBUG_select_W1BEG2;
+	wire [2-1:0] DEBUG_select_W1BEG3;
+	wire [3-1:0] DEBUG_select_WW4BEG0;
+	wire [3-1:0] DEBUG_select_WW4BEG1;
+	wire [3-1:0] DEBUG_select_WW4BEG2;
+	wire [3-1:0] DEBUG_select_WW4BEG3;
+	wire [4-1:0] DEBUG_select_W6BEG0;
+	wire [4-1:0] DEBUG_select_W6BEG1;
+	wire [2-1:0] DEBUG_select_LA_I0;
+	wire [2-1:0] DEBUG_select_LA_I1;
+	wire [2-1:0] DEBUG_select_LA_I2;
+	wire [2-1:0] DEBUG_select_LA_I3;
+	wire [1-1:0] DEBUG_select_LA_SR;
+	wire [1-1:0] DEBUG_select_LA_EN;
+	wire [2-1:0] DEBUG_select_LB_I0;
+	wire [2-1:0] DEBUG_select_LB_I1;
+	wire [2-1:0] DEBUG_select_LB_I2;
+	wire [2-1:0] DEBUG_select_LB_I3;
+	wire [1-1:0] DEBUG_select_LB_SR;
+	wire [1-1:0] DEBUG_select_LB_EN;
+	wire [2-1:0] DEBUG_select_LC_I0;
+	wire [2-1:0] DEBUG_select_LC_I1;
+	wire [2-1:0] DEBUG_select_LC_I2;
+	wire [2-1:0] DEBUG_select_LC_I3;
+	wire [1-1:0] DEBUG_select_LC_SR;
+	wire [1-1:0] DEBUG_select_LC_EN;
+	wire [2-1:0] DEBUG_select_LD_I0;
+	wire [2-1:0] DEBUG_select_LD_I1;
+	wire [2-1:0] DEBUG_select_LD_I2;
+	wire [2-1:0] DEBUG_select_LD_I3;
+	wire [1-1:0] DEBUG_select_LD_SR;
+	wire [1-1:0] DEBUG_select_LD_EN;
+	wire [2-1:0] DEBUG_select_LE_I0;
+	wire [2-1:0] DEBUG_select_LE_I1;
+	wire [2-1:0] DEBUG_select_LE_I2;
+	wire [2-1:0] DEBUG_select_LE_I3;
+	wire [1-1:0] DEBUG_select_LE_SR;
+	wire [1-1:0] DEBUG_select_LE_EN;
+	wire [2-1:0] DEBUG_select_LF_I0;
+	wire [2-1:0] DEBUG_select_LF_I1;
+	wire [2-1:0] DEBUG_select_LF_I2;
+	wire [2-1:0] DEBUG_select_LF_I3;
+	wire [1-1:0] DEBUG_select_LF_SR;
+	wire [1-1:0] DEBUG_select_LF_EN;
+	wire [2-1:0] DEBUG_select_LG_I0;
+	wire [2-1:0] DEBUG_select_LG_I1;
+	wire [2-1:0] DEBUG_select_LG_I2;
+	wire [2-1:0] DEBUG_select_LG_I3;
+	wire [1-1:0] DEBUG_select_LG_SR;
+	wire [1-1:0] DEBUG_select_LG_EN;
+	wire [2-1:0] DEBUG_select_LH_I0;
+	wire [2-1:0] DEBUG_select_LH_I1;
+	wire [2-1:0] DEBUG_select_LH_I2;
+	wire [2-1:0] DEBUG_select_LH_I3;
+	wire [1-1:0] DEBUG_select_LH_SR;
+	wire [1-1:0] DEBUG_select_LH_EN;
+	wire [2-1:0] DEBUG_select_S0;
+	wire [2-1:0] DEBUG_select_S1;
+	wire [2-1:0] DEBUG_select_S2;
+	wire [2-1:0] DEBUG_select_S3;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG0;
+	wire [4-1:0] DEBUG_select_JN2BEG1;
+	wire [4-1:0] DEBUG_select_JN2BEG2;
+	wire [4-1:0] DEBUG_select_JN2BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG4;
+	wire [4-1:0] DEBUG_select_JN2BEG5;
+	wire [4-1:0] DEBUG_select_JN2BEG6;
+	wire [4-1:0] DEBUG_select_JN2BEG7;
+	wire [4-1:0] DEBUG_select_JE2BEG0;
+	wire [4-1:0] DEBUG_select_JE2BEG1;
+	wire [4-1:0] DEBUG_select_JE2BEG2;
+	wire [4-1:0] DEBUG_select_JE2BEG3;
+	wire [4-1:0] DEBUG_select_JE2BEG4;
+	wire [4-1:0] DEBUG_select_JE2BEG5;
+	wire [4-1:0] DEBUG_select_JE2BEG6;
+	wire [4-1:0] DEBUG_select_JE2BEG7;
+	wire [4-1:0] DEBUG_select_JS2BEG0;
+	wire [4-1:0] DEBUG_select_JS2BEG1;
+	wire [4-1:0] DEBUG_select_JS2BEG2;
+	wire [4-1:0] DEBUG_select_JS2BEG3;
+	wire [4-1:0] DEBUG_select_JS2BEG4;
+	wire [4-1:0] DEBUG_select_JS2BEG5;
+	wire [4-1:0] DEBUG_select_JS2BEG6;
+	wire [4-1:0] DEBUG_select_JS2BEG7;
+	wire [4-1:0] DEBUG_select_JW2BEG0;
+	wire [4-1:0] DEBUG_select_JW2BEG1;
+	wire [4-1:0] DEBUG_select_JW2BEG2;
+	wire [4-1:0] DEBUG_select_JW2BEG3;
+	wire [4-1:0] DEBUG_select_JW2BEG4;
+	wire [4-1:0] DEBUG_select_JW2BEG5;
+	wire [4-1:0] DEBUG_select_JW2BEG6;
+	wire [4-1:0] DEBUG_select_JW2BEG7;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG3;
+	wire [3-1:0] DEBUG_select_J_SR_BEG0;
+	wire [3-1:0] DEBUG_select_J_EN_BEG0;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-4
+	assign N1BEG0_input = {J_l_CD_END1,JW2END3,J2MID_CDb_END3,LC_O};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG0 (
+	.A0 (N1BEG0_input[0]),
+	.A1 (N1BEG0_input[1]),
+	.A2 (N1BEG0_input[2]),
+	.A3 (N1BEG0_input[3]),
+	.S0 (ConfigBits[0+0]),
+	.S0N (ConfigBits_N[0+0]),
+	.S1 (ConfigBits[0+1]),
+	.S1N (ConfigBits_N[0+1]),
+	.X (N1BEG0)
+	);
+
+// switch matrix multiplexer  N1BEG1 		MUX-4
+	assign N1BEG1_input = {J_l_EF_END2,JW2END0,J2MID_EFb_END0,LD_O};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG1 (
+	.A0 (N1BEG1_input[0]),
+	.A1 (N1BEG1_input[1]),
+	.A2 (N1BEG1_input[2]),
+	.A3 (N1BEG1_input[3]),
+	.S0 (ConfigBits[2+0]),
+	.S0N (ConfigBits_N[2+0]),
+	.S1 (ConfigBits[2+1]),
+	.S1N (ConfigBits_N[2+1]),
+	.X (N1BEG1)
+	);
+
+// switch matrix multiplexer  N1BEG2 		MUX-4
+	assign N1BEG2_input = {J_l_GH_END3,JW2END1,J2MID_GHb_END1,LE_O};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG2 (
+	.A0 (N1BEG2_input[0]),
+	.A1 (N1BEG2_input[1]),
+	.A2 (N1BEG2_input[2]),
+	.A3 (N1BEG2_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (N1BEG2)
+	);
+
+// switch matrix multiplexer  N1BEG3 		MUX-4
+	assign N1BEG3_input = {J_l_AB_END0,JW2END2,J2MID_ABb_END2,LF_O};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG3 (
+	.A0 (N1BEG3_input[0]),
+	.A1 (N1BEG3_input[1]),
+	.A2 (N1BEG3_input[2]),
+	.A3 (N1BEG3_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (N1BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = JN2END0;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = JN2END1;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = JN2END2;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = JN2END3;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = JN2END4;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = JN2END5;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = JN2END6;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = JN2END7;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = N2MID0;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = N2MID1;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = N2MID2;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = N2MID3;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = N2MID4;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = N2MID5;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = N2MID6;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = N2MID7;
+// switch matrix multiplexer  N4BEG0 		MUX-4
+	assign N4BEG0_input = {LE_O,E6END1,N4END1,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG0 (
+	.A0 (N4BEG0_input[0]),
+	.A1 (N4BEG0_input[1]),
+	.A2 (N4BEG0_input[2]),
+	.A3 (N4BEG0_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (N4BEG0)
+	);
+
+// switch matrix multiplexer  N4BEG1 		MUX-4
+	assign N4BEG1_input = {LF_O,E6END0,N4END2,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG1 (
+	.A0 (N4BEG1_input[0]),
+	.A1 (N4BEG1_input[1]),
+	.A2 (N4BEG1_input[2]),
+	.A3 (N4BEG1_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (N4BEG1)
+	);
+
+// switch matrix multiplexer  N4BEG2 		MUX-4
+	assign N4BEG2_input = {LG_O,W6END1,N4END3,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG2 (
+	.A0 (N4BEG2_input[0]),
+	.A1 (N4BEG2_input[1]),
+	.A2 (N4BEG2_input[2]),
+	.A3 (N4BEG2_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (N4BEG2)
+	);
+
+// switch matrix multiplexer  N4BEG3 		MUX-4
+	assign N4BEG3_input = {LH_O,W6END0,N4END0,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG3 (
+	.A0 (N4BEG3_input[0]),
+	.A1 (N4BEG3_input[1]),
+	.A2 (N4BEG3_input[2]),
+	.A3 (N4BEG3_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (N4BEG3)
+	);
+
+// switch matrix multiplexer  NN4BEG0 		MUX-8
+	assign NN4BEG0_input = {J2END_GH_END1,J2MID_CDb_END1,J2MID_ABb_END1,LG_O,LF_O,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG0 (
+	.A0 (NN4BEG0_input[0]),
+	.A1 (NN4BEG0_input[1]),
+	.A2 (NN4BEG0_input[2]),
+	.A3 (NN4BEG0_input[3]),
+	.A4 (NN4BEG0_input[4]),
+	.A5 (NN4BEG0_input[5]),
+	.A6 (NN4BEG0_input[6]),
+	.A7 (NN4BEG0_input[7]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.S2 (ConfigBits[16+2]),
+	.S2N (ConfigBits_N[16+2]),
+	.X (NN4BEG0)
+	);
+
+// switch matrix multiplexer  NN4BEG1 		MUX-8
+	assign NN4BEG1_input = {J2END_EF_END1,J2MID_CDa_END2,J2MID_ABa_END2,LH_O,LA_O,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG1 (
+	.A0 (NN4BEG1_input[0]),
+	.A1 (NN4BEG1_input[1]),
+	.A2 (NN4BEG1_input[2]),
+	.A3 (NN4BEG1_input[3]),
+	.A4 (NN4BEG1_input[4]),
+	.A5 (NN4BEG1_input[5]),
+	.A6 (NN4BEG1_input[6]),
+	.A7 (NN4BEG1_input[7]),
+	.S0 (ConfigBits[19+0]),
+	.S0N (ConfigBits_N[19+0]),
+	.S1 (ConfigBits[19+1]),
+	.S1N (ConfigBits_N[19+1]),
+	.S2 (ConfigBits[19+2]),
+	.S2N (ConfigBits_N[19+2]),
+	.X (NN4BEG1)
+	);
+
+// switch matrix multiplexer  NN4BEG2 		MUX-8
+	assign NN4BEG2_input = {J2END_CD_END1,J2MID_GHb_END1,J2MID_EFb_END1,LC_O,LB_O,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG2 (
+	.A0 (NN4BEG2_input[0]),
+	.A1 (NN4BEG2_input[1]),
+	.A2 (NN4BEG2_input[2]),
+	.A3 (NN4BEG2_input[3]),
+	.A4 (NN4BEG2_input[4]),
+	.A5 (NN4BEG2_input[5]),
+	.A6 (NN4BEG2_input[6]),
+	.A7 (NN4BEG2_input[7]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.S2 (ConfigBits[22+2]),
+	.S2N (ConfigBits_N[22+2]),
+	.X (NN4BEG2)
+	);
+
+// switch matrix multiplexer  NN4BEG3 		MUX-8
+	assign NN4BEG3_input = {J2END_AB_END1,J2MID_GHa_END2,J2MID_EFa_END2,LE_O,LD_O,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG3 (
+	.A0 (NN4BEG3_input[0]),
+	.A1 (NN4BEG3_input[1]),
+	.A2 (NN4BEG3_input[2]),
+	.A3 (NN4BEG3_input[3]),
+	.A4 (NN4BEG3_input[4]),
+	.A5 (NN4BEG3_input[5]),
+	.A6 (NN4BEG3_input[6]),
+	.A7 (NN4BEG3_input[7]),
+	.S0 (ConfigBits[25+0]),
+	.S0N (ConfigBits_N[25+0]),
+	.S1 (ConfigBits[25+1]),
+	.S1N (ConfigBits_N[25+1]),
+	.S2 (ConfigBits[25+2]),
+	.S2N (ConfigBits_N[25+2]),
+	.X (NN4BEG3)
+	);
+
+// switch matrix multiplexer  Co0 		MUX-1
+	assign Co0 = LH_Co;
+// switch matrix multiplexer  E1BEG0 		MUX-4
+	assign E1BEG0_input = {J_l_CD_END1,JN2END3,J2MID_CDb_END3,LD_O};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG0 (
+	.A0 (E1BEG0_input[0]),
+	.A1 (E1BEG0_input[1]),
+	.A2 (E1BEG0_input[2]),
+	.A3 (E1BEG0_input[3]),
+	.S0 (ConfigBits[28+0]),
+	.S0N (ConfigBits_N[28+0]),
+	.S1 (ConfigBits[28+1]),
+	.S1N (ConfigBits_N[28+1]),
+	.X (E1BEG0)
+	);
+
+// switch matrix multiplexer  E1BEG1 		MUX-4
+	assign E1BEG1_input = {J_l_EF_END2,JN2END0,J2MID_EFb_END0,LE_O};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG1 (
+	.A0 (E1BEG1_input[0]),
+	.A1 (E1BEG1_input[1]),
+	.A2 (E1BEG1_input[2]),
+	.A3 (E1BEG1_input[3]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.X (E1BEG1)
+	);
+
+// switch matrix multiplexer  E1BEG2 		MUX-4
+	assign E1BEG2_input = {J_l_GH_END3,JN2END1,J2MID_GHb_END1,LF_O};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG2 (
+	.A0 (E1BEG2_input[0]),
+	.A1 (E1BEG2_input[1]),
+	.A2 (E1BEG2_input[2]),
+	.A3 (E1BEG2_input[3]),
+	.S0 (ConfigBits[32+0]),
+	.S0N (ConfigBits_N[32+0]),
+	.S1 (ConfigBits[32+1]),
+	.S1N (ConfigBits_N[32+1]),
+	.X (E1BEG2)
+	);
+
+// switch matrix multiplexer  E1BEG3 		MUX-4
+	assign E1BEG3_input = {J_l_AB_END0,JN2END2,J2MID_ABb_END2,LG_O};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG3 (
+	.A0 (E1BEG3_input[0]),
+	.A1 (E1BEG3_input[1]),
+	.A2 (E1BEG3_input[2]),
+	.A3 (E1BEG3_input[3]),
+	.S0 (ConfigBits[34+0]),
+	.S0N (ConfigBits_N[34+0]),
+	.S1 (ConfigBits[34+1]),
+	.S1N (ConfigBits_N[34+1]),
+	.X (E1BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = JE2END0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = JE2END1;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = JE2END2;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = JE2END3;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = JE2END4;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = JE2END5;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = JE2END6;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = JE2END7;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = E2MID0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = E2MID1;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = E2MID2;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = E2MID3;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = E2MID4;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = E2MID5;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = E2MID6;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = E2MID7;
+// switch matrix multiplexer  EE4BEG0 		MUX-8
+	assign EE4BEG0_input = {J2END_GH_END0,J2MID_CDb_END1,J2MID_ABb_END1,LG_O,LF_O,S1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG0 (
+	.A0 (EE4BEG0_input[0]),
+	.A1 (EE4BEG0_input[1]),
+	.A2 (EE4BEG0_input[2]),
+	.A3 (EE4BEG0_input[3]),
+	.A4 (EE4BEG0_input[4]),
+	.A5 (EE4BEG0_input[5]),
+	.A6 (EE4BEG0_input[6]),
+	.A7 (EE4BEG0_input[7]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.S2 (ConfigBits[36+2]),
+	.S2N (ConfigBits_N[36+2]),
+	.X (EE4BEG0)
+	);
+
+// switch matrix multiplexer  EE4BEG1 		MUX-8
+	assign EE4BEG1_input = {J2END_EF_END0,J2MID_CDa_END2,J2MID_ABa_END2,LH_O,LA_O,S1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG1 (
+	.A0 (EE4BEG1_input[0]),
+	.A1 (EE4BEG1_input[1]),
+	.A2 (EE4BEG1_input[2]),
+	.A3 (EE4BEG1_input[3]),
+	.A4 (EE4BEG1_input[4]),
+	.A5 (EE4BEG1_input[5]),
+	.A6 (EE4BEG1_input[6]),
+	.A7 (EE4BEG1_input[7]),
+	.S0 (ConfigBits[39+0]),
+	.S0N (ConfigBits_N[39+0]),
+	.S1 (ConfigBits[39+1]),
+	.S1N (ConfigBits_N[39+1]),
+	.S2 (ConfigBits[39+2]),
+	.S2N (ConfigBits_N[39+2]),
+	.X (EE4BEG1)
+	);
+
+// switch matrix multiplexer  EE4BEG2 		MUX-8
+	assign EE4BEG2_input = {J2END_CD_END0,J2MID_GHb_END1,J2MID_EFb_END1,LC_O,LB_O,S1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG2 (
+	.A0 (EE4BEG2_input[0]),
+	.A1 (EE4BEG2_input[1]),
+	.A2 (EE4BEG2_input[2]),
+	.A3 (EE4BEG2_input[3]),
+	.A4 (EE4BEG2_input[4]),
+	.A5 (EE4BEG2_input[5]),
+	.A6 (EE4BEG2_input[6]),
+	.A7 (EE4BEG2_input[7]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.S2 (ConfigBits[42+2]),
+	.S2N (ConfigBits_N[42+2]),
+	.X (EE4BEG2)
+	);
+
+// switch matrix multiplexer  EE4BEG3 		MUX-8
+	assign EE4BEG3_input = {J2END_AB_END0,J2MID_GHa_END2,J2MID_EFa_END2,LE_O,LD_O,S1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG3 (
+	.A0 (EE4BEG3_input[0]),
+	.A1 (EE4BEG3_input[1]),
+	.A2 (EE4BEG3_input[2]),
+	.A3 (EE4BEG3_input[3]),
+	.A4 (EE4BEG3_input[4]),
+	.A5 (EE4BEG3_input[5]),
+	.A6 (EE4BEG3_input[6]),
+	.A7 (EE4BEG3_input[7]),
+	.S0 (ConfigBits[45+0]),
+	.S0N (ConfigBits_N[45+0]),
+	.S1 (ConfigBits[45+1]),
+	.S1N (ConfigBits_N[45+1]),
+	.S2 (ConfigBits[45+2]),
+	.S2N (ConfigBits_N[45+2]),
+	.X (EE4BEG3)
+	);
+
+// switch matrix multiplexer  E6BEG0 		MUX-16
+	assign E6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,M_AH,M_AB,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,E1END3};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG0 (
+	.A0 (E6BEG0_input[0]),
+	.A1 (E6BEG0_input[1]),
+	.A2 (E6BEG0_input[2]),
+	.A3 (E6BEG0_input[3]),
+	.A4 (E6BEG0_input[4]),
+	.A5 (E6BEG0_input[5]),
+	.A6 (E6BEG0_input[6]),
+	.A7 (E6BEG0_input[7]),
+	.A8 (E6BEG0_input[8]),
+	.A9 (E6BEG0_input[9]),
+	.A10 (E6BEG0_input[10]),
+	.A11 (E6BEG0_input[11]),
+	.A12 (E6BEG0_input[12]),
+	.A13 (E6BEG0_input[13]),
+	.A14 (E6BEG0_input[14]),
+	.A15 (E6BEG0_input[15]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.S2 (ConfigBits[48+2]),
+	.S2N (ConfigBits_N[48+2]),
+	.S3 (ConfigBits[48+3]),
+	.S3N (ConfigBits_N[48+3]),
+	.X (E6BEG0)
+	);
+
+// switch matrix multiplexer  E6BEG1 		MUX-16
+	assign E6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,M_EF,M_AD,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,E1END2};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG1 (
+	.A0 (E6BEG1_input[0]),
+	.A1 (E6BEG1_input[1]),
+	.A2 (E6BEG1_input[2]),
+	.A3 (E6BEG1_input[3]),
+	.A4 (E6BEG1_input[4]),
+	.A5 (E6BEG1_input[5]),
+	.A6 (E6BEG1_input[6]),
+	.A7 (E6BEG1_input[7]),
+	.A8 (E6BEG1_input[8]),
+	.A9 (E6BEG1_input[9]),
+	.A10 (E6BEG1_input[10]),
+	.A11 (E6BEG1_input[11]),
+	.A12 (E6BEG1_input[12]),
+	.A13 (E6BEG1_input[13]),
+	.A14 (E6BEG1_input[14]),
+	.A15 (E6BEG1_input[15]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.S2 (ConfigBits[52+2]),
+	.S2N (ConfigBits_N[52+2]),
+	.S3 (ConfigBits[52+3]),
+	.S3N (ConfigBits_N[52+3]),
+	.X (E6BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG0 		MUX-4
+	assign S1BEG0_input = {J_l_CD_END1,JE2END3,J2MID_CDb_END3,LE_O};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG0 (
+	.A0 (S1BEG0_input[0]),
+	.A1 (S1BEG0_input[1]),
+	.A2 (S1BEG0_input[2]),
+	.A3 (S1BEG0_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (S1BEG0)
+	);
+
+// switch matrix multiplexer  S1BEG1 		MUX-4
+	assign S1BEG1_input = {J_l_EF_END2,JE2END0,J2MID_EFb_END0,LF_O};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG1 (
+	.A0 (S1BEG1_input[0]),
+	.A1 (S1BEG1_input[1]),
+	.A2 (S1BEG1_input[2]),
+	.A3 (S1BEG1_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (S1BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG2 		MUX-4
+	assign S1BEG2_input = {J_l_GH_END3,JE2END1,J2MID_GHb_END1,LG_O};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG2 (
+	.A0 (S1BEG2_input[0]),
+	.A1 (S1BEG2_input[1]),
+	.A2 (S1BEG2_input[2]),
+	.A3 (S1BEG2_input[3]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.X (S1BEG2)
+	);
+
+// switch matrix multiplexer  S1BEG3 		MUX-4
+	assign S1BEG3_input = {J_l_AB_END0,JE2END2,J2MID_ABb_END2,LH_O};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG3 (
+	.A0 (S1BEG3_input[0]),
+	.A1 (S1BEG3_input[1]),
+	.A2 (S1BEG3_input[2]),
+	.A3 (S1BEG3_input[3]),
+	.S0 (ConfigBits[62+0]),
+	.S0N (ConfigBits_N[62+0]),
+	.S1 (ConfigBits[62+1]),
+	.S1N (ConfigBits_N[62+1]),
+	.X (S1BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = JS2END0;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = JS2END1;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = JS2END2;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = JS2END3;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = JS2END4;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = JS2END5;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = JS2END6;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = JS2END7;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = S2MID0;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = S2MID1;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = S2MID2;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = S2MID3;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = S2MID4;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = S2MID5;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = S2MID6;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = S2MID7;
+// switch matrix multiplexer  S4BEG0 		MUX-4
+	assign S4BEG0_input = {LA_O,S4END1,S2END2,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG0 (
+	.A0 (S4BEG0_input[0]),
+	.A1 (S4BEG0_input[1]),
+	.A2 (S4BEG0_input[2]),
+	.A3 (S4BEG0_input[3]),
+	.S0 (ConfigBits[64+0]),
+	.S0N (ConfigBits_N[64+0]),
+	.S1 (ConfigBits[64+1]),
+	.S1N (ConfigBits_N[64+1]),
+	.X (S4BEG0)
+	);
+
+// switch matrix multiplexer  S4BEG1 		MUX-4
+	assign S4BEG1_input = {LB_O,S4END2,S2END3,E6END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG1 (
+	.A0 (S4BEG1_input[0]),
+	.A1 (S4BEG1_input[1]),
+	.A2 (S4BEG1_input[2]),
+	.A3 (S4BEG1_input[3]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.X (S4BEG1)
+	);
+
+// switch matrix multiplexer  S4BEG2 		MUX-4
+	assign S4BEG2_input = {LC_O,W6END1,S4END3,S2END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG2 (
+	.A0 (S4BEG2_input[0]),
+	.A1 (S4BEG2_input[1]),
+	.A2 (S4BEG2_input[2]),
+	.A3 (S4BEG2_input[3]),
+	.S0 (ConfigBits[68+0]),
+	.S0N (ConfigBits_N[68+0]),
+	.S1 (ConfigBits[68+1]),
+	.S1N (ConfigBits_N[68+1]),
+	.X (S4BEG2)
+	);
+
+// switch matrix multiplexer  S4BEG3 		MUX-4
+	assign S4BEG3_input = {LD_O,W6END0,S4END0,S2END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG3 (
+	.A0 (S4BEG3_input[0]),
+	.A1 (S4BEG3_input[1]),
+	.A2 (S4BEG3_input[2]),
+	.A3 (S4BEG3_input[3]),
+	.S0 (ConfigBits[70+0]),
+	.S0N (ConfigBits_N[70+0]),
+	.S1 (ConfigBits[70+1]),
+	.S1N (ConfigBits_N[70+1]),
+	.X (S4BEG3)
+	);
+
+// switch matrix multiplexer  SS4BEG0 		MUX-8
+	assign SS4BEG0_input = {J2END_GH_END3,J2MID_CDb_END1,J2MID_ABb_END1,LG_O,LF_O,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG0 (
+	.A0 (SS4BEG0_input[0]),
+	.A1 (SS4BEG0_input[1]),
+	.A2 (SS4BEG0_input[2]),
+	.A3 (SS4BEG0_input[3]),
+	.A4 (SS4BEG0_input[4]),
+	.A5 (SS4BEG0_input[5]),
+	.A6 (SS4BEG0_input[6]),
+	.A7 (SS4BEG0_input[7]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.S2 (ConfigBits[72+2]),
+	.S2N (ConfigBits_N[72+2]),
+	.X (SS4BEG0)
+	);
+
+// switch matrix multiplexer  SS4BEG1 		MUX-8
+	assign SS4BEG1_input = {J2END_EF_END3,J2MID_CDa_END2,J2MID_ABa_END2,LH_O,LA_O,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG1 (
+	.A0 (SS4BEG1_input[0]),
+	.A1 (SS4BEG1_input[1]),
+	.A2 (SS4BEG1_input[2]),
+	.A3 (SS4BEG1_input[3]),
+	.A4 (SS4BEG1_input[4]),
+	.A5 (SS4BEG1_input[5]),
+	.A6 (SS4BEG1_input[6]),
+	.A7 (SS4BEG1_input[7]),
+	.S0 (ConfigBits[75+0]),
+	.S0N (ConfigBits_N[75+0]),
+	.S1 (ConfigBits[75+1]),
+	.S1N (ConfigBits_N[75+1]),
+	.S2 (ConfigBits[75+2]),
+	.S2N (ConfigBits_N[75+2]),
+	.X (SS4BEG1)
+	);
+
+// switch matrix multiplexer  SS4BEG2 		MUX-8
+	assign SS4BEG2_input = {J2END_CD_END3,J2MID_GHb_END1,J2MID_EFb_END1,LC_O,LB_O,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG2 (
+	.A0 (SS4BEG2_input[0]),
+	.A1 (SS4BEG2_input[1]),
+	.A2 (SS4BEG2_input[2]),
+	.A3 (SS4BEG2_input[3]),
+	.A4 (SS4BEG2_input[4]),
+	.A5 (SS4BEG2_input[5]),
+	.A6 (SS4BEG2_input[6]),
+	.A7 (SS4BEG2_input[7]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.S2 (ConfigBits[78+2]),
+	.S2N (ConfigBits_N[78+2]),
+	.X (SS4BEG2)
+	);
+
+// switch matrix multiplexer  SS4BEG3 		MUX-8
+	assign SS4BEG3_input = {J2END_AB_END3,J2MID_GHa_END2,J2MID_EFa_END2,LE_O,LD_O,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG3 (
+	.A0 (SS4BEG3_input[0]),
+	.A1 (SS4BEG3_input[1]),
+	.A2 (SS4BEG3_input[2]),
+	.A3 (SS4BEG3_input[3]),
+	.A4 (SS4BEG3_input[4]),
+	.A5 (SS4BEG3_input[5]),
+	.A6 (SS4BEG3_input[6]),
+	.A7 (SS4BEG3_input[7]),
+	.S0 (ConfigBits[81+0]),
+	.S0N (ConfigBits_N[81+0]),
+	.S1 (ConfigBits[81+1]),
+	.S1N (ConfigBits_N[81+1]),
+	.S2 (ConfigBits[81+2]),
+	.S2N (ConfigBits_N[81+2]),
+	.X (SS4BEG3)
+	);
+
+// switch matrix multiplexer  W1BEG0 		MUX-4
+	assign W1BEG0_input = {J_l_CD_END1,JS2END3,J2MID_CDb_END3,LF_O};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG0 (
+	.A0 (W1BEG0_input[0]),
+	.A1 (W1BEG0_input[1]),
+	.A2 (W1BEG0_input[2]),
+	.A3 (W1BEG0_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (W1BEG0)
+	);
+
+// switch matrix multiplexer  W1BEG1 		MUX-4
+	assign W1BEG1_input = {J_l_EF_END2,JS2END0,J2MID_EFb_END0,LG_O};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG1 (
+	.A0 (W1BEG1_input[0]),
+	.A1 (W1BEG1_input[1]),
+	.A2 (W1BEG1_input[2]),
+	.A3 (W1BEG1_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (W1BEG1)
+	);
+
+// switch matrix multiplexer  W1BEG2 		MUX-4
+	assign W1BEG2_input = {J_l_GH_END3,JS2END1,J2MID_GHb_END1,LH_O};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG2 (
+	.A0 (W1BEG2_input[0]),
+	.A1 (W1BEG2_input[1]),
+	.A2 (W1BEG2_input[2]),
+	.A3 (W1BEG2_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (W1BEG2)
+	);
+
+// switch matrix multiplexer  W1BEG3 		MUX-4
+	assign W1BEG3_input = {J_l_AB_END0,JS2END2,J2MID_ABb_END2,LA_O};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG3 (
+	.A0 (W1BEG3_input[0]),
+	.A1 (W1BEG3_input[1]),
+	.A2 (W1BEG3_input[2]),
+	.A3 (W1BEG3_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (W1BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = JW2END0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = JW2END1;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = JW2END2;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = JW2END3;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = JW2END4;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = JW2END5;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = JW2END6;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = JW2END7;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = W2MID0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = W2MID1;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = W2MID2;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = W2MID3;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = W2MID4;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = W2MID5;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = W2MID6;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = W2MID7;
+// switch matrix multiplexer  WW4BEG0 		MUX-8
+	assign WW4BEG0_input = {J2END_GH_END2,J2MID_CDb_END1,J2MID_ABb_END1,LG_O,LF_O,W1END2,S1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG0 (
+	.A0 (WW4BEG0_input[0]),
+	.A1 (WW4BEG0_input[1]),
+	.A2 (WW4BEG0_input[2]),
+	.A3 (WW4BEG0_input[3]),
+	.A4 (WW4BEG0_input[4]),
+	.A5 (WW4BEG0_input[5]),
+	.A6 (WW4BEG0_input[6]),
+	.A7 (WW4BEG0_input[7]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.S2 (ConfigBits[92+2]),
+	.S2N (ConfigBits_N[92+2]),
+	.X (WW4BEG0)
+	);
+
+// switch matrix multiplexer  WW4BEG1 		MUX-8
+	assign WW4BEG1_input = {J2END_EF_END2,J2MID_CDa_END2,J2MID_ABa_END2,LH_O,LA_O,W1END3,S1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG1 (
+	.A0 (WW4BEG1_input[0]),
+	.A1 (WW4BEG1_input[1]),
+	.A2 (WW4BEG1_input[2]),
+	.A3 (WW4BEG1_input[3]),
+	.A4 (WW4BEG1_input[4]),
+	.A5 (WW4BEG1_input[5]),
+	.A6 (WW4BEG1_input[6]),
+	.A7 (WW4BEG1_input[7]),
+	.S0 (ConfigBits[95+0]),
+	.S0N (ConfigBits_N[95+0]),
+	.S1 (ConfigBits[95+1]),
+	.S1N (ConfigBits_N[95+1]),
+	.S2 (ConfigBits[95+2]),
+	.S2N (ConfigBits_N[95+2]),
+	.X (WW4BEG1)
+	);
+
+// switch matrix multiplexer  WW4BEG2 		MUX-8
+	assign WW4BEG2_input = {J2END_CD_END2,J2MID_GHb_END1,J2MID_EFb_END1,LC_O,LB_O,W1END0,S1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG2 (
+	.A0 (WW4BEG2_input[0]),
+	.A1 (WW4BEG2_input[1]),
+	.A2 (WW4BEG2_input[2]),
+	.A3 (WW4BEG2_input[3]),
+	.A4 (WW4BEG2_input[4]),
+	.A5 (WW4BEG2_input[5]),
+	.A6 (WW4BEG2_input[6]),
+	.A7 (WW4BEG2_input[7]),
+	.S0 (ConfigBits[98+0]),
+	.S0N (ConfigBits_N[98+0]),
+	.S1 (ConfigBits[98+1]),
+	.S1N (ConfigBits_N[98+1]),
+	.S2 (ConfigBits[98+2]),
+	.S2N (ConfigBits_N[98+2]),
+	.X (WW4BEG2)
+	);
+
+// switch matrix multiplexer  WW4BEG3 		MUX-8
+	assign WW4BEG3_input = {J2END_AB_END2,J2MID_GHa_END2,J2MID_EFa_END2,LE_O,LD_O,W1END1,S1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG3 (
+	.A0 (WW4BEG3_input[0]),
+	.A1 (WW4BEG3_input[1]),
+	.A2 (WW4BEG3_input[2]),
+	.A3 (WW4BEG3_input[3]),
+	.A4 (WW4BEG3_input[4]),
+	.A5 (WW4BEG3_input[5]),
+	.A6 (WW4BEG3_input[6]),
+	.A7 (WW4BEG3_input[7]),
+	.S0 (ConfigBits[101+0]),
+	.S0N (ConfigBits_N[101+0]),
+	.S1 (ConfigBits[101+1]),
+	.S1N (ConfigBits_N[101+1]),
+	.S2 (ConfigBits[101+2]),
+	.S2N (ConfigBits_N[101+2]),
+	.X (WW4BEG3)
+	);
+
+// switch matrix multiplexer  W6BEG0 		MUX-16
+	assign W6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,M_AH,M_AB,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,E1END3};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG0 (
+	.A0 (W6BEG0_input[0]),
+	.A1 (W6BEG0_input[1]),
+	.A2 (W6BEG0_input[2]),
+	.A3 (W6BEG0_input[3]),
+	.A4 (W6BEG0_input[4]),
+	.A5 (W6BEG0_input[5]),
+	.A6 (W6BEG0_input[6]),
+	.A7 (W6BEG0_input[7]),
+	.A8 (W6BEG0_input[8]),
+	.A9 (W6BEG0_input[9]),
+	.A10 (W6BEG0_input[10]),
+	.A11 (W6BEG0_input[11]),
+	.A12 (W6BEG0_input[12]),
+	.A13 (W6BEG0_input[13]),
+	.A14 (W6BEG0_input[14]),
+	.A15 (W6BEG0_input[15]),
+	.S0 (ConfigBits[104+0]),
+	.S0N (ConfigBits_N[104+0]),
+	.S1 (ConfigBits[104+1]),
+	.S1N (ConfigBits_N[104+1]),
+	.S2 (ConfigBits[104+2]),
+	.S2N (ConfigBits_N[104+2]),
+	.S3 (ConfigBits[104+3]),
+	.S3N (ConfigBits_N[104+3]),
+	.X (W6BEG0)
+	);
+
+// switch matrix multiplexer  W6BEG1 		MUX-16
+	assign W6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,M_EF,M_AD,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,E1END2};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG1 (
+	.A0 (W6BEG1_input[0]),
+	.A1 (W6BEG1_input[1]),
+	.A2 (W6BEG1_input[2]),
+	.A3 (W6BEG1_input[3]),
+	.A4 (W6BEG1_input[4]),
+	.A5 (W6BEG1_input[5]),
+	.A6 (W6BEG1_input[6]),
+	.A7 (W6BEG1_input[7]),
+	.A8 (W6BEG1_input[8]),
+	.A9 (W6BEG1_input[9]),
+	.A10 (W6BEG1_input[10]),
+	.A11 (W6BEG1_input[11]),
+	.A12 (W6BEG1_input[12]),
+	.A13 (W6BEG1_input[13]),
+	.A14 (W6BEG1_input[14]),
+	.A15 (W6BEG1_input[15]),
+	.S0 (ConfigBits[108+0]),
+	.S0N (ConfigBits_N[108+0]),
+	.S1 (ConfigBits[108+1]),
+	.S1N (ConfigBits_N[108+1]),
+	.S2 (ConfigBits[108+2]),
+	.S2N (ConfigBits_N[108+2]),
+	.S3 (ConfigBits[108+3]),
+	.S3N (ConfigBits_N[108+3]),
+	.X (W6BEG1)
+	);
+
+// switch matrix multiplexer  LA_I0 		MUX-4
+	assign LA_I0_input = {J_l_AB_END0,J2END_AB_END0,J2MID_ABb_END0,J2MID_ABa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LA_I0 (
+	.A0 (LA_I0_input[0]),
+	.A1 (LA_I0_input[1]),
+	.A2 (LA_I0_input[2]),
+	.A3 (LA_I0_input[3]),
+	.S0 (ConfigBits[112+0]),
+	.S0N (ConfigBits_N[112+0]),
+	.S1 (ConfigBits[112+1]),
+	.S1N (ConfigBits_N[112+1]),
+	.X (LA_I0)
+	);
+
+// switch matrix multiplexer  LA_I1 		MUX-4
+	assign LA_I1_input = {J_l_AB_END1,J2END_AB_END1,J2MID_ABb_END1,J2MID_ABa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LA_I1 (
+	.A0 (LA_I1_input[0]),
+	.A1 (LA_I1_input[1]),
+	.A2 (LA_I1_input[2]),
+	.A3 (LA_I1_input[3]),
+	.S0 (ConfigBits[114+0]),
+	.S0N (ConfigBits_N[114+0]),
+	.S1 (ConfigBits[114+1]),
+	.S1N (ConfigBits_N[114+1]),
+	.X (LA_I1)
+	);
+
+// switch matrix multiplexer  LA_I2 		MUX-4
+	assign LA_I2_input = {J_l_AB_END2,J2END_AB_END2,J2MID_ABb_END2,J2MID_ABa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LA_I2 (
+	.A0 (LA_I2_input[0]),
+	.A1 (LA_I2_input[1]),
+	.A2 (LA_I2_input[2]),
+	.A3 (LA_I2_input[3]),
+	.S0 (ConfigBits[116+0]),
+	.S0N (ConfigBits_N[116+0]),
+	.S1 (ConfigBits[116+1]),
+	.S1N (ConfigBits_N[116+1]),
+	.X (LA_I2)
+	);
+
+// switch matrix multiplexer  LA_I3 		MUX-4
+	assign LA_I3_input = {J_l_AB_END3,J2END_AB_END3,J2MID_ABb_END3,J2MID_ABa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LA_I3 (
+	.A0 (LA_I3_input[0]),
+	.A1 (LA_I3_input[1]),
+	.A2 (LA_I3_input[2]),
+	.A3 (LA_I3_input[3]),
+	.S0 (ConfigBits[118+0]),
+	.S0N (ConfigBits_N[118+0]),
+	.S1 (ConfigBits[118+1]),
+	.S1N (ConfigBits_N[118+1]),
+	.X (LA_I3)
+	);
+
+// switch matrix multiplexer  LA_Ci 		MUX-1
+	assign LA_Ci = Ci0;
+// switch matrix multiplexer  LA_SR 		MUX-2
+	assign LA_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LA_SR (
+	.A0 (LA_SR_input[0]),
+	.A1 (LA_SR_input[1]),
+	.S (ConfigBits[120+0]),
+	.X (LA_SR)
+	);
+
+// switch matrix multiplexer  LA_EN 		MUX-2
+	assign LA_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LA_EN (
+	.A0 (LA_EN_input[0]),
+	.A1 (LA_EN_input[1]),
+	.S (ConfigBits[121+0]),
+	.X (LA_EN)
+	);
+
+// switch matrix multiplexer  LB_I0 		MUX-4
+	assign LB_I0_input = {J_l_AB_END0,J2END_AB_END0,J2MID_ABb_END0,J2MID_ABa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LB_I0 (
+	.A0 (LB_I0_input[0]),
+	.A1 (LB_I0_input[1]),
+	.A2 (LB_I0_input[2]),
+	.A3 (LB_I0_input[3]),
+	.S0 (ConfigBits[122+0]),
+	.S0N (ConfigBits_N[122+0]),
+	.S1 (ConfigBits[122+1]),
+	.S1N (ConfigBits_N[122+1]),
+	.X (LB_I0)
+	);
+
+// switch matrix multiplexer  LB_I1 		MUX-4
+	assign LB_I1_input = {J_l_AB_END1,J2END_AB_END1,J2MID_ABb_END1,J2MID_ABa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LB_I1 (
+	.A0 (LB_I1_input[0]),
+	.A1 (LB_I1_input[1]),
+	.A2 (LB_I1_input[2]),
+	.A3 (LB_I1_input[3]),
+	.S0 (ConfigBits[124+0]),
+	.S0N (ConfigBits_N[124+0]),
+	.S1 (ConfigBits[124+1]),
+	.S1N (ConfigBits_N[124+1]),
+	.X (LB_I1)
+	);
+
+// switch matrix multiplexer  LB_I2 		MUX-4
+	assign LB_I2_input = {J_l_AB_END2,J2END_AB_END2,J2MID_ABb_END2,J2MID_ABa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LB_I2 (
+	.A0 (LB_I2_input[0]),
+	.A1 (LB_I2_input[1]),
+	.A2 (LB_I2_input[2]),
+	.A3 (LB_I2_input[3]),
+	.S0 (ConfigBits[126+0]),
+	.S0N (ConfigBits_N[126+0]),
+	.S1 (ConfigBits[126+1]),
+	.S1N (ConfigBits_N[126+1]),
+	.X (LB_I2)
+	);
+
+// switch matrix multiplexer  LB_I3 		MUX-4
+	assign LB_I3_input = {J_l_AB_END3,J2END_AB_END3,J2MID_ABb_END3,J2MID_ABa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LB_I3 (
+	.A0 (LB_I3_input[0]),
+	.A1 (LB_I3_input[1]),
+	.A2 (LB_I3_input[2]),
+	.A3 (LB_I3_input[3]),
+	.S0 (ConfigBits[128+0]),
+	.S0N (ConfigBits_N[128+0]),
+	.S1 (ConfigBits[128+1]),
+	.S1N (ConfigBits_N[128+1]),
+	.X (LB_I3)
+	);
+
+// switch matrix multiplexer  LB_Ci 		MUX-1
+	assign LB_Ci = LA_Co;
+// switch matrix multiplexer  LB_SR 		MUX-2
+	assign LB_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LB_SR (
+	.A0 (LB_SR_input[0]),
+	.A1 (LB_SR_input[1]),
+	.S (ConfigBits[130+0]),
+	.X (LB_SR)
+	);
+
+// switch matrix multiplexer  LB_EN 		MUX-2
+	assign LB_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LB_EN (
+	.A0 (LB_EN_input[0]),
+	.A1 (LB_EN_input[1]),
+	.S (ConfigBits[131+0]),
+	.X (LB_EN)
+	);
+
+// switch matrix multiplexer  LC_I0 		MUX-4
+	assign LC_I0_input = {J_l_CD_END0,J2END_CD_END0,J2MID_CDb_END0,J2MID_CDa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LC_I0 (
+	.A0 (LC_I0_input[0]),
+	.A1 (LC_I0_input[1]),
+	.A2 (LC_I0_input[2]),
+	.A3 (LC_I0_input[3]),
+	.S0 (ConfigBits[132+0]),
+	.S0N (ConfigBits_N[132+0]),
+	.S1 (ConfigBits[132+1]),
+	.S1N (ConfigBits_N[132+1]),
+	.X (LC_I0)
+	);
+
+// switch matrix multiplexer  LC_I1 		MUX-4
+	assign LC_I1_input = {J_l_CD_END1,J2END_CD_END1,J2MID_CDb_END1,J2MID_CDa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LC_I1 (
+	.A0 (LC_I1_input[0]),
+	.A1 (LC_I1_input[1]),
+	.A2 (LC_I1_input[2]),
+	.A3 (LC_I1_input[3]),
+	.S0 (ConfigBits[134+0]),
+	.S0N (ConfigBits_N[134+0]),
+	.S1 (ConfigBits[134+1]),
+	.S1N (ConfigBits_N[134+1]),
+	.X (LC_I1)
+	);
+
+// switch matrix multiplexer  LC_I2 		MUX-4
+	assign LC_I2_input = {J_l_CD_END2,J2END_CD_END2,J2MID_CDb_END2,J2MID_CDa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LC_I2 (
+	.A0 (LC_I2_input[0]),
+	.A1 (LC_I2_input[1]),
+	.A2 (LC_I2_input[2]),
+	.A3 (LC_I2_input[3]),
+	.S0 (ConfigBits[136+0]),
+	.S0N (ConfigBits_N[136+0]),
+	.S1 (ConfigBits[136+1]),
+	.S1N (ConfigBits_N[136+1]),
+	.X (LC_I2)
+	);
+
+// switch matrix multiplexer  LC_I3 		MUX-4
+	assign LC_I3_input = {J_l_CD_END3,J2END_CD_END3,J2MID_CDb_END3,J2MID_CDa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LC_I3 (
+	.A0 (LC_I3_input[0]),
+	.A1 (LC_I3_input[1]),
+	.A2 (LC_I3_input[2]),
+	.A3 (LC_I3_input[3]),
+	.S0 (ConfigBits[138+0]),
+	.S0N (ConfigBits_N[138+0]),
+	.S1 (ConfigBits[138+1]),
+	.S1N (ConfigBits_N[138+1]),
+	.X (LC_I3)
+	);
+
+// switch matrix multiplexer  LC_Ci 		MUX-1
+	assign LC_Ci = LB_Co;
+// switch matrix multiplexer  LC_SR 		MUX-2
+	assign LC_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LC_SR (
+	.A0 (LC_SR_input[0]),
+	.A1 (LC_SR_input[1]),
+	.S (ConfigBits[140+0]),
+	.X (LC_SR)
+	);
+
+// switch matrix multiplexer  LC_EN 		MUX-2
+	assign LC_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LC_EN (
+	.A0 (LC_EN_input[0]),
+	.A1 (LC_EN_input[1]),
+	.S (ConfigBits[141+0]),
+	.X (LC_EN)
+	);
+
+// switch matrix multiplexer  LD_I0 		MUX-4
+	assign LD_I0_input = {J_l_CD_END0,J2END_CD_END0,J2MID_CDb_END0,J2MID_CDa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LD_I0 (
+	.A0 (LD_I0_input[0]),
+	.A1 (LD_I0_input[1]),
+	.A2 (LD_I0_input[2]),
+	.A3 (LD_I0_input[3]),
+	.S0 (ConfigBits[142+0]),
+	.S0N (ConfigBits_N[142+0]),
+	.S1 (ConfigBits[142+1]),
+	.S1N (ConfigBits_N[142+1]),
+	.X (LD_I0)
+	);
+
+// switch matrix multiplexer  LD_I1 		MUX-4
+	assign LD_I1_input = {J_l_CD_END1,J2END_CD_END1,J2MID_CDb_END1,J2MID_CDa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LD_I1 (
+	.A0 (LD_I1_input[0]),
+	.A1 (LD_I1_input[1]),
+	.A2 (LD_I1_input[2]),
+	.A3 (LD_I1_input[3]),
+	.S0 (ConfigBits[144+0]),
+	.S0N (ConfigBits_N[144+0]),
+	.S1 (ConfigBits[144+1]),
+	.S1N (ConfigBits_N[144+1]),
+	.X (LD_I1)
+	);
+
+// switch matrix multiplexer  LD_I2 		MUX-4
+	assign LD_I2_input = {J_l_CD_END2,J2END_CD_END2,J2MID_CDb_END2,J2MID_CDa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LD_I2 (
+	.A0 (LD_I2_input[0]),
+	.A1 (LD_I2_input[1]),
+	.A2 (LD_I2_input[2]),
+	.A3 (LD_I2_input[3]),
+	.S0 (ConfigBits[146+0]),
+	.S0N (ConfigBits_N[146+0]),
+	.S1 (ConfigBits[146+1]),
+	.S1N (ConfigBits_N[146+1]),
+	.X (LD_I2)
+	);
+
+// switch matrix multiplexer  LD_I3 		MUX-4
+	assign LD_I3_input = {J_l_CD_END3,J2END_CD_END3,J2MID_CDb_END3,J2MID_CDa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LD_I3 (
+	.A0 (LD_I3_input[0]),
+	.A1 (LD_I3_input[1]),
+	.A2 (LD_I3_input[2]),
+	.A3 (LD_I3_input[3]),
+	.S0 (ConfigBits[148+0]),
+	.S0N (ConfigBits_N[148+0]),
+	.S1 (ConfigBits[148+1]),
+	.S1N (ConfigBits_N[148+1]),
+	.X (LD_I3)
+	);
+
+// switch matrix multiplexer  LD_Ci 		MUX-1
+	assign LD_Ci = LC_Co;
+// switch matrix multiplexer  LD_SR 		MUX-2
+	assign LD_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LD_SR (
+	.A0 (LD_SR_input[0]),
+	.A1 (LD_SR_input[1]),
+	.S (ConfigBits[150+0]),
+	.X (LD_SR)
+	);
+
+// switch matrix multiplexer  LD_EN 		MUX-2
+	assign LD_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LD_EN (
+	.A0 (LD_EN_input[0]),
+	.A1 (LD_EN_input[1]),
+	.S (ConfigBits[151+0]),
+	.X (LD_EN)
+	);
+
+// switch matrix multiplexer  LE_I0 		MUX-4
+	assign LE_I0_input = {J_l_EF_END0,J2END_EF_END0,J2MID_EFb_END0,J2MID_EFa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LE_I0 (
+	.A0 (LE_I0_input[0]),
+	.A1 (LE_I0_input[1]),
+	.A2 (LE_I0_input[2]),
+	.A3 (LE_I0_input[3]),
+	.S0 (ConfigBits[152+0]),
+	.S0N (ConfigBits_N[152+0]),
+	.S1 (ConfigBits[152+1]),
+	.S1N (ConfigBits_N[152+1]),
+	.X (LE_I0)
+	);
+
+// switch matrix multiplexer  LE_I1 		MUX-4
+	assign LE_I1_input = {J_l_EF_END1,J2END_EF_END1,J2MID_EFb_END1,J2MID_EFa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LE_I1 (
+	.A0 (LE_I1_input[0]),
+	.A1 (LE_I1_input[1]),
+	.A2 (LE_I1_input[2]),
+	.A3 (LE_I1_input[3]),
+	.S0 (ConfigBits[154+0]),
+	.S0N (ConfigBits_N[154+0]),
+	.S1 (ConfigBits[154+1]),
+	.S1N (ConfigBits_N[154+1]),
+	.X (LE_I1)
+	);
+
+// switch matrix multiplexer  LE_I2 		MUX-4
+	assign LE_I2_input = {J_l_EF_END2,J2END_EF_END2,J2MID_EFb_END2,J2MID_EFa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LE_I2 (
+	.A0 (LE_I2_input[0]),
+	.A1 (LE_I2_input[1]),
+	.A2 (LE_I2_input[2]),
+	.A3 (LE_I2_input[3]),
+	.S0 (ConfigBits[156+0]),
+	.S0N (ConfigBits_N[156+0]),
+	.S1 (ConfigBits[156+1]),
+	.S1N (ConfigBits_N[156+1]),
+	.X (LE_I2)
+	);
+
+// switch matrix multiplexer  LE_I3 		MUX-4
+	assign LE_I3_input = {J_l_EF_END3,J2END_EF_END3,J2MID_EFb_END3,J2MID_EFa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LE_I3 (
+	.A0 (LE_I3_input[0]),
+	.A1 (LE_I3_input[1]),
+	.A2 (LE_I3_input[2]),
+	.A3 (LE_I3_input[3]),
+	.S0 (ConfigBits[158+0]),
+	.S0N (ConfigBits_N[158+0]),
+	.S1 (ConfigBits[158+1]),
+	.S1N (ConfigBits_N[158+1]),
+	.X (LE_I3)
+	);
+
+// switch matrix multiplexer  LE_Ci 		MUX-1
+	assign LE_Ci = LD_Co;
+// switch matrix multiplexer  LE_SR 		MUX-2
+	assign LE_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LE_SR (
+	.A0 (LE_SR_input[0]),
+	.A1 (LE_SR_input[1]),
+	.S (ConfigBits[160+0]),
+	.X (LE_SR)
+	);
+
+// switch matrix multiplexer  LE_EN 		MUX-2
+	assign LE_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LE_EN (
+	.A0 (LE_EN_input[0]),
+	.A1 (LE_EN_input[1]),
+	.S (ConfigBits[161+0]),
+	.X (LE_EN)
+	);
+
+// switch matrix multiplexer  LF_I0 		MUX-4
+	assign LF_I0_input = {J_l_EF_END0,J2END_EF_END0,J2MID_EFb_END0,J2MID_EFa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LF_I0 (
+	.A0 (LF_I0_input[0]),
+	.A1 (LF_I0_input[1]),
+	.A2 (LF_I0_input[2]),
+	.A3 (LF_I0_input[3]),
+	.S0 (ConfigBits[162+0]),
+	.S0N (ConfigBits_N[162+0]),
+	.S1 (ConfigBits[162+1]),
+	.S1N (ConfigBits_N[162+1]),
+	.X (LF_I0)
+	);
+
+// switch matrix multiplexer  LF_I1 		MUX-4
+	assign LF_I1_input = {J_l_EF_END1,J2END_EF_END1,J2MID_EFb_END1,J2MID_EFa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LF_I1 (
+	.A0 (LF_I1_input[0]),
+	.A1 (LF_I1_input[1]),
+	.A2 (LF_I1_input[2]),
+	.A3 (LF_I1_input[3]),
+	.S0 (ConfigBits[164+0]),
+	.S0N (ConfigBits_N[164+0]),
+	.S1 (ConfigBits[164+1]),
+	.S1N (ConfigBits_N[164+1]),
+	.X (LF_I1)
+	);
+
+// switch matrix multiplexer  LF_I2 		MUX-4
+	assign LF_I2_input = {J_l_EF_END2,J2END_EF_END2,J2MID_EFb_END2,J2MID_EFa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LF_I2 (
+	.A0 (LF_I2_input[0]),
+	.A1 (LF_I2_input[1]),
+	.A2 (LF_I2_input[2]),
+	.A3 (LF_I2_input[3]),
+	.S0 (ConfigBits[166+0]),
+	.S0N (ConfigBits_N[166+0]),
+	.S1 (ConfigBits[166+1]),
+	.S1N (ConfigBits_N[166+1]),
+	.X (LF_I2)
+	);
+
+// switch matrix multiplexer  LF_I3 		MUX-4
+	assign LF_I3_input = {J_l_EF_END3,J2END_EF_END3,J2MID_EFb_END3,J2MID_EFa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LF_I3 (
+	.A0 (LF_I3_input[0]),
+	.A1 (LF_I3_input[1]),
+	.A2 (LF_I3_input[2]),
+	.A3 (LF_I3_input[3]),
+	.S0 (ConfigBits[168+0]),
+	.S0N (ConfigBits_N[168+0]),
+	.S1 (ConfigBits[168+1]),
+	.S1N (ConfigBits_N[168+1]),
+	.X (LF_I3)
+	);
+
+// switch matrix multiplexer  LF_Ci 		MUX-1
+	assign LF_Ci = LE_Co;
+// switch matrix multiplexer  LF_SR 		MUX-2
+	assign LF_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LF_SR (
+	.A0 (LF_SR_input[0]),
+	.A1 (LF_SR_input[1]),
+	.S (ConfigBits[170+0]),
+	.X (LF_SR)
+	);
+
+// switch matrix multiplexer  LF_EN 		MUX-2
+	assign LF_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LF_EN (
+	.A0 (LF_EN_input[0]),
+	.A1 (LF_EN_input[1]),
+	.S (ConfigBits[171+0]),
+	.X (LF_EN)
+	);
+
+// switch matrix multiplexer  LG_I0 		MUX-4
+	assign LG_I0_input = {J_l_GH_END0,J2END_GH_END0,J2MID_GHb_END0,J2MID_GHa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LG_I0 (
+	.A0 (LG_I0_input[0]),
+	.A1 (LG_I0_input[1]),
+	.A2 (LG_I0_input[2]),
+	.A3 (LG_I0_input[3]),
+	.S0 (ConfigBits[172+0]),
+	.S0N (ConfigBits_N[172+0]),
+	.S1 (ConfigBits[172+1]),
+	.S1N (ConfigBits_N[172+1]),
+	.X (LG_I0)
+	);
+
+// switch matrix multiplexer  LG_I1 		MUX-4
+	assign LG_I1_input = {J_l_GH_END1,J2END_GH_END1,J2MID_GHb_END1,J2MID_GHa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LG_I1 (
+	.A0 (LG_I1_input[0]),
+	.A1 (LG_I1_input[1]),
+	.A2 (LG_I1_input[2]),
+	.A3 (LG_I1_input[3]),
+	.S0 (ConfigBits[174+0]),
+	.S0N (ConfigBits_N[174+0]),
+	.S1 (ConfigBits[174+1]),
+	.S1N (ConfigBits_N[174+1]),
+	.X (LG_I1)
+	);
+
+// switch matrix multiplexer  LG_I2 		MUX-4
+	assign LG_I2_input = {J_l_GH_END2,J2END_GH_END2,J2MID_GHb_END2,J2MID_GHa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LG_I2 (
+	.A0 (LG_I2_input[0]),
+	.A1 (LG_I2_input[1]),
+	.A2 (LG_I2_input[2]),
+	.A3 (LG_I2_input[3]),
+	.S0 (ConfigBits[176+0]),
+	.S0N (ConfigBits_N[176+0]),
+	.S1 (ConfigBits[176+1]),
+	.S1N (ConfigBits_N[176+1]),
+	.X (LG_I2)
+	);
+
+// switch matrix multiplexer  LG_I3 		MUX-4
+	assign LG_I3_input = {J_l_GH_END3,J2END_GH_END3,J2MID_GHb_END3,J2MID_GHa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LG_I3 (
+	.A0 (LG_I3_input[0]),
+	.A1 (LG_I3_input[1]),
+	.A2 (LG_I3_input[2]),
+	.A3 (LG_I3_input[3]),
+	.S0 (ConfigBits[178+0]),
+	.S0N (ConfigBits_N[178+0]),
+	.S1 (ConfigBits[178+1]),
+	.S1N (ConfigBits_N[178+1]),
+	.X (LG_I3)
+	);
+
+// switch matrix multiplexer  LG_Ci 		MUX-1
+	assign LG_Ci = LF_Co;
+// switch matrix multiplexer  LG_SR 		MUX-2
+	assign LG_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LG_SR (
+	.A0 (LG_SR_input[0]),
+	.A1 (LG_SR_input[1]),
+	.S (ConfigBits[180+0]),
+	.X (LG_SR)
+	);
+
+// switch matrix multiplexer  LG_EN 		MUX-2
+	assign LG_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LG_EN (
+	.A0 (LG_EN_input[0]),
+	.A1 (LG_EN_input[1]),
+	.S (ConfigBits[181+0]),
+	.X (LG_EN)
+	);
+
+// switch matrix multiplexer  LH_I0 		MUX-4
+	assign LH_I0_input = {J_l_GH_END0,J2END_GH_END0,J2MID_GHb_END0,J2MID_GHa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_LH_I0 (
+	.A0 (LH_I0_input[0]),
+	.A1 (LH_I0_input[1]),
+	.A2 (LH_I0_input[2]),
+	.A3 (LH_I0_input[3]),
+	.S0 (ConfigBits[182+0]),
+	.S0N (ConfigBits_N[182+0]),
+	.S1 (ConfigBits[182+1]),
+	.S1N (ConfigBits_N[182+1]),
+	.X (LH_I0)
+	);
+
+// switch matrix multiplexer  LH_I1 		MUX-4
+	assign LH_I1_input = {J_l_GH_END1,J2END_GH_END1,J2MID_GHb_END1,J2MID_GHa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_LH_I1 (
+	.A0 (LH_I1_input[0]),
+	.A1 (LH_I1_input[1]),
+	.A2 (LH_I1_input[2]),
+	.A3 (LH_I1_input[3]),
+	.S0 (ConfigBits[184+0]),
+	.S0N (ConfigBits_N[184+0]),
+	.S1 (ConfigBits[184+1]),
+	.S1N (ConfigBits_N[184+1]),
+	.X (LH_I1)
+	);
+
+// switch matrix multiplexer  LH_I2 		MUX-4
+	assign LH_I2_input = {J_l_GH_END2,J2END_GH_END2,J2MID_GHb_END2,J2MID_GHa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_LH_I2 (
+	.A0 (LH_I2_input[0]),
+	.A1 (LH_I2_input[1]),
+	.A2 (LH_I2_input[2]),
+	.A3 (LH_I2_input[3]),
+	.S0 (ConfigBits[186+0]),
+	.S0N (ConfigBits_N[186+0]),
+	.S1 (ConfigBits[186+1]),
+	.S1N (ConfigBits_N[186+1]),
+	.X (LH_I2)
+	);
+
+// switch matrix multiplexer  LH_I3 		MUX-4
+	assign LH_I3_input = {J_l_GH_END3,J2END_GH_END3,J2MID_GHb_END3,J2MID_GHa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_LH_I3 (
+	.A0 (LH_I3_input[0]),
+	.A1 (LH_I3_input[1]),
+	.A2 (LH_I3_input[2]),
+	.A3 (LH_I3_input[3]),
+	.S0 (ConfigBits[188+0]),
+	.S0N (ConfigBits_N[188+0]),
+	.S1 (ConfigBits[188+1]),
+	.S1N (ConfigBits_N[188+1]),
+	.X (LH_I3)
+	);
+
+// switch matrix multiplexer  LH_Ci 		MUX-1
+	assign LH_Ci = LG_Co;
+// switch matrix multiplexer  LH_SR 		MUX-2
+	assign LH_SR_input = {J_SR_END0,GND0};
+	my_mux2 inst_my_mux2_LH_SR (
+	.A0 (LH_SR_input[0]),
+	.A1 (LH_SR_input[1]),
+	.S (ConfigBits[190+0]),
+	.X (LH_SR)
+	);
+
+// switch matrix multiplexer  LH_EN 		MUX-2
+	assign LH_EN_input = {J_EN_END0,VCC0};
+	my_mux2 inst_my_mux2_LH_EN (
+	.A0 (LH_EN_input[0]),
+	.A1 (LH_EN_input[1]),
+	.S (ConfigBits[191+0]),
+	.X (LH_EN)
+	);
+
+// switch matrix multiplexer  A 		MUX-1
+	assign A = LA_O;
+// switch matrix multiplexer  B 		MUX-1
+	assign B = LB_O;
+// switch matrix multiplexer  C 		MUX-1
+	assign C = LC_O;
+// switch matrix multiplexer  D 		MUX-1
+	assign D = LD_O;
+// switch matrix multiplexer  E 		MUX-1
+	assign E = LE_O;
+// switch matrix multiplexer  F 		MUX-1
+	assign F = LF_O;
+// switch matrix multiplexer  G 		MUX-1
+	assign G = LG_O;
+// switch matrix multiplexer  H 		MUX-1
+	assign H = LH_O;
+// switch matrix multiplexer  S0 		MUX-4
+	assign S0_input = {JW2END4,JS2END4,JE2END4,JN2END4};
+	cus_mux41_buf inst_cus_mux41_buf_S0 (
+	.A0 (S0_input[0]),
+	.A1 (S0_input[1]),
+	.A2 (S0_input[2]),
+	.A3 (S0_input[3]),
+	.S0 (ConfigBits[192+0]),
+	.S0N (ConfigBits_N[192+0]),
+	.S1 (ConfigBits[192+1]),
+	.S1N (ConfigBits_N[192+1]),
+	.X (S0)
+	);
+
+// switch matrix multiplexer  S1 		MUX-4
+	assign S1_input = {JW2END5,JS2END5,JE2END5,JN2END5};
+	cus_mux41_buf inst_cus_mux41_buf_S1 (
+	.A0 (S1_input[0]),
+	.A1 (S1_input[1]),
+	.A2 (S1_input[2]),
+	.A3 (S1_input[3]),
+	.S0 (ConfigBits[194+0]),
+	.S0N (ConfigBits_N[194+0]),
+	.S1 (ConfigBits[194+1]),
+	.S1N (ConfigBits_N[194+1]),
+	.X (S1)
+	);
+
+// switch matrix multiplexer  S2 		MUX-4
+	assign S2_input = {JW2END6,JS2END6,JE2END6,JN2END6};
+	cus_mux41_buf inst_cus_mux41_buf_S2 (
+	.A0 (S2_input[0]),
+	.A1 (S2_input[1]),
+	.A2 (S2_input[2]),
+	.A3 (S2_input[3]),
+	.S0 (ConfigBits[196+0]),
+	.S0N (ConfigBits_N[196+0]),
+	.S1 (ConfigBits[196+1]),
+	.S1N (ConfigBits_N[196+1]),
+	.X (S2)
+	);
+
+// switch matrix multiplexer  S3 		MUX-4
+	assign S3_input = {JW2END7,JS2END7,JE2END7,JN2END7};
+	cus_mux41_buf inst_cus_mux41_buf_S3 (
+	.A0 (S3_input[0]),
+	.A1 (S3_input[1]),
+	.A2 (S3_input[2]),
+	.A3 (S3_input[3]),
+	.S0 (ConfigBits[198+0]),
+	.S0N (ConfigBits_N[198+0]),
+	.S1 (ConfigBits[198+1]),
+	.S1N (ConfigBits_N[198+1]),
+	.X (S3)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG0 		MUX-4
+	assign J2MID_ABa_BEG0_input = {JN2END3,W2MID6,S2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG0 (
+	.A0 (J2MID_ABa_BEG0_input[0]),
+	.A1 (J2MID_ABa_BEG0_input[1]),
+	.A2 (J2MID_ABa_BEG0_input[2]),
+	.A3 (J2MID_ABa_BEG0_input[3]),
+	.S0 (ConfigBits[200+0]),
+	.S0N (ConfigBits_N[200+0]),
+	.S1 (ConfigBits[200+1]),
+	.S1N (ConfigBits_N[200+1]),
+	.X (J2MID_ABa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG1 		MUX-4
+	assign J2MID_ABa_BEG1_input = {JE2END3,W2MID2,S2MID2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG1 (
+	.A0 (J2MID_ABa_BEG1_input[0]),
+	.A1 (J2MID_ABa_BEG1_input[1]),
+	.A2 (J2MID_ABa_BEG1_input[2]),
+	.A3 (J2MID_ABa_BEG1_input[3]),
+	.S0 (ConfigBits[202+0]),
+	.S0N (ConfigBits_N[202+0]),
+	.S1 (ConfigBits[202+1]),
+	.S1N (ConfigBits_N[202+1]),
+	.X (J2MID_ABa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG2 		MUX-4
+	assign J2MID_ABa_BEG2_input = {JS2END3,W2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG2 (
+	.A0 (J2MID_ABa_BEG2_input[0]),
+	.A1 (J2MID_ABa_BEG2_input[1]),
+	.A2 (J2MID_ABa_BEG2_input[2]),
+	.A3 (J2MID_ABa_BEG2_input[3]),
+	.S0 (ConfigBits[204+0]),
+	.S0N (ConfigBits_N[204+0]),
+	.S1 (ConfigBits[204+1]),
+	.S1N (ConfigBits_N[204+1]),
+	.X (J2MID_ABa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG3 		MUX-4
+	assign J2MID_ABa_BEG3_input = {JW2END3,S2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG3 (
+	.A0 (J2MID_ABa_BEG3_input[0]),
+	.A1 (J2MID_ABa_BEG3_input[1]),
+	.A2 (J2MID_ABa_BEG3_input[2]),
+	.A3 (J2MID_ABa_BEG3_input[3]),
+	.S0 (ConfigBits[206+0]),
+	.S0N (ConfigBits_N[206+0]),
+	.S1 (ConfigBits[206+1]),
+	.S1N (ConfigBits_N[206+1]),
+	.X (J2MID_ABa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG0 		MUX-4
+	assign J2MID_CDa_BEG0_input = {JN2END4,W2MID6,S2MID6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG0 (
+	.A0 (J2MID_CDa_BEG0_input[0]),
+	.A1 (J2MID_CDa_BEG0_input[1]),
+	.A2 (J2MID_CDa_BEG0_input[2]),
+	.A3 (J2MID_CDa_BEG0_input[3]),
+	.S0 (ConfigBits[208+0]),
+	.S0N (ConfigBits_N[208+0]),
+	.S1 (ConfigBits[208+1]),
+	.S1N (ConfigBits_N[208+1]),
+	.X (J2MID_CDa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG1 		MUX-4
+	assign J2MID_CDa_BEG1_input = {JE2END4,W2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG1 (
+	.A0 (J2MID_CDa_BEG1_input[0]),
+	.A1 (J2MID_CDa_BEG1_input[1]),
+	.A2 (J2MID_CDa_BEG1_input[2]),
+	.A3 (J2MID_CDa_BEG1_input[3]),
+	.S0 (ConfigBits[210+0]),
+	.S0N (ConfigBits_N[210+0]),
+	.S1 (ConfigBits[210+1]),
+	.S1N (ConfigBits_N[210+1]),
+	.X (J2MID_CDa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG2 		MUX-4
+	assign J2MID_CDa_BEG2_input = {JS2END4,S2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG2 (
+	.A0 (J2MID_CDa_BEG2_input[0]),
+	.A1 (J2MID_CDa_BEG2_input[1]),
+	.A2 (J2MID_CDa_BEG2_input[2]),
+	.A3 (J2MID_CDa_BEG2_input[3]),
+	.S0 (ConfigBits[212+0]),
+	.S0N (ConfigBits_N[212+0]),
+	.S1 (ConfigBits[212+1]),
+	.S1N (ConfigBits_N[212+1]),
+	.X (J2MID_CDa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG3 		MUX-4
+	assign J2MID_CDa_BEG3_input = {JW2END4,W2MID0,S2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG3 (
+	.A0 (J2MID_CDa_BEG3_input[0]),
+	.A1 (J2MID_CDa_BEG3_input[1]),
+	.A2 (J2MID_CDa_BEG3_input[2]),
+	.A3 (J2MID_CDa_BEG3_input[3]),
+	.S0 (ConfigBits[214+0]),
+	.S0N (ConfigBits_N[214+0]),
+	.S1 (ConfigBits[214+1]),
+	.S1N (ConfigBits_N[214+1]),
+	.X (J2MID_CDa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG0 		MUX-4
+	assign J2MID_EFa_BEG0_input = {JN2END5,W2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG0 (
+	.A0 (J2MID_EFa_BEG0_input[0]),
+	.A1 (J2MID_EFa_BEG0_input[1]),
+	.A2 (J2MID_EFa_BEG0_input[2]),
+	.A3 (J2MID_EFa_BEG0_input[3]),
+	.S0 (ConfigBits[216+0]),
+	.S0N (ConfigBits_N[216+0]),
+	.S1 (ConfigBits[216+1]),
+	.S1N (ConfigBits_N[216+1]),
+	.X (J2MID_EFa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG1 		MUX-4
+	assign J2MID_EFa_BEG1_input = {JE2END5,S2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG1 (
+	.A0 (J2MID_EFa_BEG1_input[0]),
+	.A1 (J2MID_EFa_BEG1_input[1]),
+	.A2 (J2MID_EFa_BEG1_input[2]),
+	.A3 (J2MID_EFa_BEG1_input[3]),
+	.S0 (ConfigBits[218+0]),
+	.S0N (ConfigBits_N[218+0]),
+	.S1 (ConfigBits[218+1]),
+	.S1N (ConfigBits_N[218+1]),
+	.X (J2MID_EFa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG2 		MUX-4
+	assign J2MID_EFa_BEG2_input = {JS2END5,W2MID4,S2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG2 (
+	.A0 (J2MID_EFa_BEG2_input[0]),
+	.A1 (J2MID_EFa_BEG2_input[1]),
+	.A2 (J2MID_EFa_BEG2_input[2]),
+	.A3 (J2MID_EFa_BEG2_input[3]),
+	.S0 (ConfigBits[220+0]),
+	.S0N (ConfigBits_N[220+0]),
+	.S1 (ConfigBits[220+1]),
+	.S1N (ConfigBits_N[220+1]),
+	.X (J2MID_EFa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG3 		MUX-4
+	assign J2MID_EFa_BEG3_input = {JW2END5,W2MID0,S2MID0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG3 (
+	.A0 (J2MID_EFa_BEG3_input[0]),
+	.A1 (J2MID_EFa_BEG3_input[1]),
+	.A2 (J2MID_EFa_BEG3_input[2]),
+	.A3 (J2MID_EFa_BEG3_input[3]),
+	.S0 (ConfigBits[222+0]),
+	.S0N (ConfigBits_N[222+0]),
+	.S1 (ConfigBits[222+1]),
+	.S1N (ConfigBits_N[222+1]),
+	.X (J2MID_EFa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG0 		MUX-4
+	assign J2MID_GHa_BEG0_input = {JN2END6,S2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG0 (
+	.A0 (J2MID_GHa_BEG0_input[0]),
+	.A1 (J2MID_GHa_BEG0_input[1]),
+	.A2 (J2MID_GHa_BEG0_input[2]),
+	.A3 (J2MID_GHa_BEG0_input[3]),
+	.S0 (ConfigBits[224+0]),
+	.S0N (ConfigBits_N[224+0]),
+	.S1 (ConfigBits[224+1]),
+	.S1N (ConfigBits_N[224+1]),
+	.X (J2MID_GHa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG1 		MUX-4
+	assign J2MID_GHa_BEG1_input = {JE2END6,W2MID2,S2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG1 (
+	.A0 (J2MID_GHa_BEG1_input[0]),
+	.A1 (J2MID_GHa_BEG1_input[1]),
+	.A2 (J2MID_GHa_BEG1_input[2]),
+	.A3 (J2MID_GHa_BEG1_input[3]),
+	.S0 (ConfigBits[226+0]),
+	.S0N (ConfigBits_N[226+0]),
+	.S1 (ConfigBits[226+1]),
+	.S1N (ConfigBits_N[226+1]),
+	.X (J2MID_GHa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG2 		MUX-4
+	assign J2MID_GHa_BEG2_input = {JS2END6,W2MID4,S2MID4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG2 (
+	.A0 (J2MID_GHa_BEG2_input[0]),
+	.A1 (J2MID_GHa_BEG2_input[1]),
+	.A2 (J2MID_GHa_BEG2_input[2]),
+	.A3 (J2MID_GHa_BEG2_input[3]),
+	.S0 (ConfigBits[228+0]),
+	.S0N (ConfigBits_N[228+0]),
+	.S1 (ConfigBits[228+1]),
+	.S1N (ConfigBits_N[228+1]),
+	.X (J2MID_GHa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG3 		MUX-4
+	assign J2MID_GHa_BEG3_input = {JW2END6,W2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG3 (
+	.A0 (J2MID_GHa_BEG3_input[0]),
+	.A1 (J2MID_GHa_BEG3_input[1]),
+	.A2 (J2MID_GHa_BEG3_input[2]),
+	.A3 (J2MID_GHa_BEG3_input[3]),
+	.S0 (ConfigBits[230+0]),
+	.S0N (ConfigBits_N[230+0]),
+	.S1 (ConfigBits[230+1]),
+	.S1N (ConfigBits_N[230+1]),
+	.X (J2MID_GHa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG0 		MUX-4
+	assign J2MID_ABb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG0 (
+	.A0 (J2MID_ABb_BEG0_input[0]),
+	.A1 (J2MID_ABb_BEG0_input[1]),
+	.A2 (J2MID_ABb_BEG0_input[2]),
+	.A3 (J2MID_ABb_BEG0_input[3]),
+	.S0 (ConfigBits[232+0]),
+	.S0N (ConfigBits_N[232+0]),
+	.S1 (ConfigBits[232+1]),
+	.S1N (ConfigBits_N[232+1]),
+	.X (J2MID_ABb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG1 		MUX-4
+	assign J2MID_ABb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG1 (
+	.A0 (J2MID_ABb_BEG1_input[0]),
+	.A1 (J2MID_ABb_BEG1_input[1]),
+	.A2 (J2MID_ABb_BEG1_input[2]),
+	.A3 (J2MID_ABb_BEG1_input[3]),
+	.S0 (ConfigBits[234+0]),
+	.S0N (ConfigBits_N[234+0]),
+	.S1 (ConfigBits[234+1]),
+	.S1N (ConfigBits_N[234+1]),
+	.X (J2MID_ABb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG2 		MUX-4
+	assign J2MID_ABb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG2 (
+	.A0 (J2MID_ABb_BEG2_input[0]),
+	.A1 (J2MID_ABb_BEG2_input[1]),
+	.A2 (J2MID_ABb_BEG2_input[2]),
+	.A3 (J2MID_ABb_BEG2_input[3]),
+	.S0 (ConfigBits[236+0]),
+	.S0N (ConfigBits_N[236+0]),
+	.S1 (ConfigBits[236+1]),
+	.S1N (ConfigBits_N[236+1]),
+	.X (J2MID_ABb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG3 		MUX-4
+	assign J2MID_ABb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG3 (
+	.A0 (J2MID_ABb_BEG3_input[0]),
+	.A1 (J2MID_ABb_BEG3_input[1]),
+	.A2 (J2MID_ABb_BEG3_input[2]),
+	.A3 (J2MID_ABb_BEG3_input[3]),
+	.S0 (ConfigBits[238+0]),
+	.S0N (ConfigBits_N[238+0]),
+	.S1 (ConfigBits[238+1]),
+	.S1N (ConfigBits_N[238+1]),
+	.X (J2MID_ABb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG0 		MUX-4
+	assign J2MID_CDb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG0 (
+	.A0 (J2MID_CDb_BEG0_input[0]),
+	.A1 (J2MID_CDb_BEG0_input[1]),
+	.A2 (J2MID_CDb_BEG0_input[2]),
+	.A3 (J2MID_CDb_BEG0_input[3]),
+	.S0 (ConfigBits[240+0]),
+	.S0N (ConfigBits_N[240+0]),
+	.S1 (ConfigBits[240+1]),
+	.S1N (ConfigBits_N[240+1]),
+	.X (J2MID_CDb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG1 		MUX-4
+	assign J2MID_CDb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG1 (
+	.A0 (J2MID_CDb_BEG1_input[0]),
+	.A1 (J2MID_CDb_BEG1_input[1]),
+	.A2 (J2MID_CDb_BEG1_input[2]),
+	.A3 (J2MID_CDb_BEG1_input[3]),
+	.S0 (ConfigBits[242+0]),
+	.S0N (ConfigBits_N[242+0]),
+	.S1 (ConfigBits[242+1]),
+	.S1N (ConfigBits_N[242+1]),
+	.X (J2MID_CDb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG2 		MUX-4
+	assign J2MID_CDb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG2 (
+	.A0 (J2MID_CDb_BEG2_input[0]),
+	.A1 (J2MID_CDb_BEG2_input[1]),
+	.A2 (J2MID_CDb_BEG2_input[2]),
+	.A3 (J2MID_CDb_BEG2_input[3]),
+	.S0 (ConfigBits[244+0]),
+	.S0N (ConfigBits_N[244+0]),
+	.S1 (ConfigBits[244+1]),
+	.S1N (ConfigBits_N[244+1]),
+	.X (J2MID_CDb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG3 		MUX-4
+	assign J2MID_CDb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG3 (
+	.A0 (J2MID_CDb_BEG3_input[0]),
+	.A1 (J2MID_CDb_BEG3_input[1]),
+	.A2 (J2MID_CDb_BEG3_input[2]),
+	.A3 (J2MID_CDb_BEG3_input[3]),
+	.S0 (ConfigBits[246+0]),
+	.S0N (ConfigBits_N[246+0]),
+	.S1 (ConfigBits[246+1]),
+	.S1N (ConfigBits_N[246+1]),
+	.X (J2MID_CDb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG0 		MUX-4
+	assign J2MID_EFb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG0 (
+	.A0 (J2MID_EFb_BEG0_input[0]),
+	.A1 (J2MID_EFb_BEG0_input[1]),
+	.A2 (J2MID_EFb_BEG0_input[2]),
+	.A3 (J2MID_EFb_BEG0_input[3]),
+	.S0 (ConfigBits[248+0]),
+	.S0N (ConfigBits_N[248+0]),
+	.S1 (ConfigBits[248+1]),
+	.S1N (ConfigBits_N[248+1]),
+	.X (J2MID_EFb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG1 		MUX-4
+	assign J2MID_EFb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG1 (
+	.A0 (J2MID_EFb_BEG1_input[0]),
+	.A1 (J2MID_EFb_BEG1_input[1]),
+	.A2 (J2MID_EFb_BEG1_input[2]),
+	.A3 (J2MID_EFb_BEG1_input[3]),
+	.S0 (ConfigBits[250+0]),
+	.S0N (ConfigBits_N[250+0]),
+	.S1 (ConfigBits[250+1]),
+	.S1N (ConfigBits_N[250+1]),
+	.X (J2MID_EFb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG2 		MUX-4
+	assign J2MID_EFb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG2 (
+	.A0 (J2MID_EFb_BEG2_input[0]),
+	.A1 (J2MID_EFb_BEG2_input[1]),
+	.A2 (J2MID_EFb_BEG2_input[2]),
+	.A3 (J2MID_EFb_BEG2_input[3]),
+	.S0 (ConfigBits[252+0]),
+	.S0N (ConfigBits_N[252+0]),
+	.S1 (ConfigBits[252+1]),
+	.S1N (ConfigBits_N[252+1]),
+	.X (J2MID_EFb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG3 		MUX-4
+	assign J2MID_EFb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG3 (
+	.A0 (J2MID_EFb_BEG3_input[0]),
+	.A1 (J2MID_EFb_BEG3_input[1]),
+	.A2 (J2MID_EFb_BEG3_input[2]),
+	.A3 (J2MID_EFb_BEG3_input[3]),
+	.S0 (ConfigBits[254+0]),
+	.S0N (ConfigBits_N[254+0]),
+	.S1 (ConfigBits[254+1]),
+	.S1N (ConfigBits_N[254+1]),
+	.X (J2MID_EFb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG0 		MUX-4
+	assign J2MID_GHb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG0 (
+	.A0 (J2MID_GHb_BEG0_input[0]),
+	.A1 (J2MID_GHb_BEG0_input[1]),
+	.A2 (J2MID_GHb_BEG0_input[2]),
+	.A3 (J2MID_GHb_BEG0_input[3]),
+	.S0 (ConfigBits[256+0]),
+	.S0N (ConfigBits_N[256+0]),
+	.S1 (ConfigBits[256+1]),
+	.S1N (ConfigBits_N[256+1]),
+	.X (J2MID_GHb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG1 		MUX-4
+	assign J2MID_GHb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG1 (
+	.A0 (J2MID_GHb_BEG1_input[0]),
+	.A1 (J2MID_GHb_BEG1_input[1]),
+	.A2 (J2MID_GHb_BEG1_input[2]),
+	.A3 (J2MID_GHb_BEG1_input[3]),
+	.S0 (ConfigBits[258+0]),
+	.S0N (ConfigBits_N[258+0]),
+	.S1 (ConfigBits[258+1]),
+	.S1N (ConfigBits_N[258+1]),
+	.X (J2MID_GHb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG2 		MUX-4
+	assign J2MID_GHb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG2 (
+	.A0 (J2MID_GHb_BEG2_input[0]),
+	.A1 (J2MID_GHb_BEG2_input[1]),
+	.A2 (J2MID_GHb_BEG2_input[2]),
+	.A3 (J2MID_GHb_BEG2_input[3]),
+	.S0 (ConfigBits[260+0]),
+	.S0N (ConfigBits_N[260+0]),
+	.S1 (ConfigBits[260+1]),
+	.S1N (ConfigBits_N[260+1]),
+	.X (J2MID_GHb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG3 		MUX-4
+	assign J2MID_GHb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG3 (
+	.A0 (J2MID_GHb_BEG3_input[0]),
+	.A1 (J2MID_GHb_BEG3_input[1]),
+	.A2 (J2MID_GHb_BEG3_input[2]),
+	.A3 (J2MID_GHb_BEG3_input[3]),
+	.S0 (ConfigBits[262+0]),
+	.S0N (ConfigBits_N[262+0]),
+	.S1 (ConfigBits[262+1]),
+	.S1N (ConfigBits_N[262+1]),
+	.X (J2MID_GHb_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG0 		MUX-4
+	assign J2END_AB_BEG0_input = {W2END6,SS4END3,E2END6,N2END6};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG0 (
+	.A0 (J2END_AB_BEG0_input[0]),
+	.A1 (J2END_AB_BEG0_input[1]),
+	.A2 (J2END_AB_BEG0_input[2]),
+	.A3 (J2END_AB_BEG0_input[3]),
+	.S0 (ConfigBits[264+0]),
+	.S0N (ConfigBits_N[264+0]),
+	.S1 (ConfigBits[264+1]),
+	.S1N (ConfigBits_N[264+1]),
+	.X (J2END_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG1 		MUX-4
+	assign J2END_AB_BEG1_input = {W2END2,S2END2,E2END2,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG1 (
+	.A0 (J2END_AB_BEG1_input[0]),
+	.A1 (J2END_AB_BEG1_input[1]),
+	.A2 (J2END_AB_BEG1_input[2]),
+	.A3 (J2END_AB_BEG1_input[3]),
+	.S0 (ConfigBits[266+0]),
+	.S0N (ConfigBits_N[266+0]),
+	.S1 (ConfigBits[266+1]),
+	.S1N (ConfigBits_N[266+1]),
+	.X (J2END_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG2 		MUX-4
+	assign J2END_AB_BEG2_input = {W2END4,S2END4,EE4END0,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG2 (
+	.A0 (J2END_AB_BEG2_input[0]),
+	.A1 (J2END_AB_BEG2_input[1]),
+	.A2 (J2END_AB_BEG2_input[2]),
+	.A3 (J2END_AB_BEG2_input[3]),
+	.S0 (ConfigBits[268+0]),
+	.S0N (ConfigBits_N[268+0]),
+	.S1 (ConfigBits[268+1]),
+	.S1N (ConfigBits_N[268+1]),
+	.X (J2END_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG3 		MUX-4
+	assign J2END_AB_BEG3_input = {WW4END3,S2END0,E2END0,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG3 (
+	.A0 (J2END_AB_BEG3_input[0]),
+	.A1 (J2END_AB_BEG3_input[1]),
+	.A2 (J2END_AB_BEG3_input[2]),
+	.A3 (J2END_AB_BEG3_input[3]),
+	.S0 (ConfigBits[270+0]),
+	.S0N (ConfigBits_N[270+0]),
+	.S1 (ConfigBits[270+1]),
+	.S1N (ConfigBits_N[270+1]),
+	.X (J2END_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG0 		MUX-4
+	assign J2END_CD_BEG0_input = {W2END6,S2END6,E2END6,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG0 (
+	.A0 (J2END_CD_BEG0_input[0]),
+	.A1 (J2END_CD_BEG0_input[1]),
+	.A2 (J2END_CD_BEG0_input[2]),
+	.A3 (J2END_CD_BEG0_input[3]),
+	.S0 (ConfigBits[272+0]),
+	.S0N (ConfigBits_N[272+0]),
+	.S1 (ConfigBits[272+1]),
+	.S1N (ConfigBits_N[272+1]),
+	.X (J2END_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG1 		MUX-4
+	assign J2END_CD_BEG1_input = {WW4END2,S2END2,E2END2,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG1 (
+	.A0 (J2END_CD_BEG1_input[0]),
+	.A1 (J2END_CD_BEG1_input[1]),
+	.A2 (J2END_CD_BEG1_input[2]),
+	.A3 (J2END_CD_BEG1_input[3]),
+	.S0 (ConfigBits[274+0]),
+	.S0N (ConfigBits_N[274+0]),
+	.S1 (ConfigBits[274+1]),
+	.S1N (ConfigBits_N[274+1]),
+	.X (J2END_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG2 		MUX-4
+	assign J2END_CD_BEG2_input = {W2END4,SS4END2,E2END4,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG2 (
+	.A0 (J2END_CD_BEG2_input[0]),
+	.A1 (J2END_CD_BEG2_input[1]),
+	.A2 (J2END_CD_BEG2_input[2]),
+	.A3 (J2END_CD_BEG2_input[3]),
+	.S0 (ConfigBits[276+0]),
+	.S0N (ConfigBits_N[276+0]),
+	.S1 (ConfigBits[276+1]),
+	.S1N (ConfigBits_N[276+1]),
+	.X (J2END_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG3 		MUX-4
+	assign J2END_CD_BEG3_input = {W2END0,S2END0,EE4END1,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG3 (
+	.A0 (J2END_CD_BEG3_input[0]),
+	.A1 (J2END_CD_BEG3_input[1]),
+	.A2 (J2END_CD_BEG3_input[2]),
+	.A3 (J2END_CD_BEG3_input[3]),
+	.S0 (ConfigBits[278+0]),
+	.S0N (ConfigBits_N[278+0]),
+	.S1 (ConfigBits[278+1]),
+	.S1N (ConfigBits_N[278+1]),
+	.X (J2END_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG0 		MUX-4
+	assign J2END_EF_BEG0_input = {W2END7,S2END7,EE4END2,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG0 (
+	.A0 (J2END_EF_BEG0_input[0]),
+	.A1 (J2END_EF_BEG0_input[1]),
+	.A2 (J2END_EF_BEG0_input[2]),
+	.A3 (J2END_EF_BEG0_input[3]),
+	.S0 (ConfigBits[280+0]),
+	.S0N (ConfigBits_N[280+0]),
+	.S1 (ConfigBits[280+1]),
+	.S1N (ConfigBits_N[280+1]),
+	.X (J2END_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG1 		MUX-4
+	assign J2END_EF_BEG1_input = {WW4END1,S2END3,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG1 (
+	.A0 (J2END_EF_BEG1_input[0]),
+	.A1 (J2END_EF_BEG1_input[1]),
+	.A2 (J2END_EF_BEG1_input[2]),
+	.A3 (J2END_EF_BEG1_input[3]),
+	.S0 (ConfigBits[282+0]),
+	.S0N (ConfigBits_N[282+0]),
+	.S1 (ConfigBits[282+1]),
+	.S1N (ConfigBits_N[282+1]),
+	.X (J2END_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG2 		MUX-4
+	assign J2END_EF_BEG2_input = {W2END5,SS4END1,E2END5,N2END5};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG2 (
+	.A0 (J2END_EF_BEG2_input[0]),
+	.A1 (J2END_EF_BEG2_input[1]),
+	.A2 (J2END_EF_BEG2_input[2]),
+	.A3 (J2END_EF_BEG2_input[3]),
+	.S0 (ConfigBits[284+0]),
+	.S0N (ConfigBits_N[284+0]),
+	.S1 (ConfigBits[284+1]),
+	.S1N (ConfigBits_N[284+1]),
+	.X (J2END_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG3 		MUX-4
+	assign J2END_EF_BEG3_input = {W2END1,S2END1,E2END1,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG3 (
+	.A0 (J2END_EF_BEG3_input[0]),
+	.A1 (J2END_EF_BEG3_input[1]),
+	.A2 (J2END_EF_BEG3_input[2]),
+	.A3 (J2END_EF_BEG3_input[3]),
+	.S0 (ConfigBits[286+0]),
+	.S0N (ConfigBits_N[286+0]),
+	.S1 (ConfigBits[286+1]),
+	.S1N (ConfigBits_N[286+1]),
+	.X (J2END_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG0 		MUX-4
+	assign J2END_GH_BEG0_input = {WW4END0,S2END7,E2END7,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG0 (
+	.A0 (J2END_GH_BEG0_input[0]),
+	.A1 (J2END_GH_BEG0_input[1]),
+	.A2 (J2END_GH_BEG0_input[2]),
+	.A3 (J2END_GH_BEG0_input[3]),
+	.S0 (ConfigBits[288+0]),
+	.S0N (ConfigBits_N[288+0]),
+	.S1 (ConfigBits[288+1]),
+	.S1N (ConfigBits_N[288+1]),
+	.X (J2END_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG1 		MUX-4
+	assign J2END_GH_BEG1_input = {W2END3,SS4END0,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG1 (
+	.A0 (J2END_GH_BEG1_input[0]),
+	.A1 (J2END_GH_BEG1_input[1]),
+	.A2 (J2END_GH_BEG1_input[2]),
+	.A3 (J2END_GH_BEG1_input[3]),
+	.S0 (ConfigBits[290+0]),
+	.S0N (ConfigBits_N[290+0]),
+	.S1 (ConfigBits[290+1]),
+	.S1N (ConfigBits_N[290+1]),
+	.X (J2END_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG2 		MUX-4
+	assign J2END_GH_BEG2_input = {W2END5,S2END5,E2END5,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG2 (
+	.A0 (J2END_GH_BEG2_input[0]),
+	.A1 (J2END_GH_BEG2_input[1]),
+	.A2 (J2END_GH_BEG2_input[2]),
+	.A3 (J2END_GH_BEG2_input[3]),
+	.S0 (ConfigBits[292+0]),
+	.S0N (ConfigBits_N[292+0]),
+	.S1 (ConfigBits[292+1]),
+	.S1N (ConfigBits_N[292+1]),
+	.X (J2END_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG3 		MUX-4
+	assign J2END_GH_BEG3_input = {W2END1,S2END1,EE4END3,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG3 (
+	.A0 (J2END_GH_BEG3_input[0]),
+	.A1 (J2END_GH_BEG3_input[1]),
+	.A2 (J2END_GH_BEG3_input[2]),
+	.A3 (J2END_GH_BEG3_input[3]),
+	.S0 (ConfigBits[294+0]),
+	.S0N (ConfigBits_N[294+0]),
+	.S1 (ConfigBits[294+1]),
+	.S1N (ConfigBits_N[294+1]),
+	.X (J2END_GH_BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG0 		MUX-16
+	assign JN2BEG0_input = {M_AB,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,W6END1,W2END1,SS4END1,E6END1,E2END1,E1END3,N4END1,N2END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG0 (
+	.A0 (JN2BEG0_input[0]),
+	.A1 (JN2BEG0_input[1]),
+	.A2 (JN2BEG0_input[2]),
+	.A3 (JN2BEG0_input[3]),
+	.A4 (JN2BEG0_input[4]),
+	.A5 (JN2BEG0_input[5]),
+	.A6 (JN2BEG0_input[6]),
+	.A7 (JN2BEG0_input[7]),
+	.A8 (JN2BEG0_input[8]),
+	.A9 (JN2BEG0_input[9]),
+	.A10 (JN2BEG0_input[10]),
+	.A11 (JN2BEG0_input[11]),
+	.A12 (JN2BEG0_input[12]),
+	.A13 (JN2BEG0_input[13]),
+	.A14 (JN2BEG0_input[14]),
+	.A15 (JN2BEG0_input[15]),
+	.S0 (ConfigBits[296+0]),
+	.S0N (ConfigBits_N[296+0]),
+	.S1 (ConfigBits[296+1]),
+	.S1N (ConfigBits_N[296+1]),
+	.S2 (ConfigBits[296+2]),
+	.S2N (ConfigBits_N[296+2]),
+	.S3 (ConfigBits[296+3]),
+	.S3N (ConfigBits_N[296+3]),
+	.X (JN2BEG0)
+	);
+
+// switch matrix multiplexer  JN2BEG1 		MUX-16
+	assign JN2BEG1_input = {M_AD,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LA_O,W6END0,W2END2,S2END2,E6END0,E2END2,E1END0,N4END2,N2END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG1 (
+	.A0 (JN2BEG1_input[0]),
+	.A1 (JN2BEG1_input[1]),
+	.A2 (JN2BEG1_input[2]),
+	.A3 (JN2BEG1_input[3]),
+	.A4 (JN2BEG1_input[4]),
+	.A5 (JN2BEG1_input[5]),
+	.A6 (JN2BEG1_input[6]),
+	.A7 (JN2BEG1_input[7]),
+	.A8 (JN2BEG1_input[8]),
+	.A9 (JN2BEG1_input[9]),
+	.A10 (JN2BEG1_input[10]),
+	.A11 (JN2BEG1_input[11]),
+	.A12 (JN2BEG1_input[12]),
+	.A13 (JN2BEG1_input[13]),
+	.A14 (JN2BEG1_input[14]),
+	.A15 (JN2BEG1_input[15]),
+	.S0 (ConfigBits[300+0]),
+	.S0N (ConfigBits_N[300+0]),
+	.S1 (ConfigBits[300+1]),
+	.S1N (ConfigBits_N[300+1]),
+	.S2 (ConfigBits[300+2]),
+	.S2N (ConfigBits_N[300+2]),
+	.S3 (ConfigBits[300+3]),
+	.S3N (ConfigBits_N[300+3]),
+	.X (JN2BEG1)
+	);
+
+// switch matrix multiplexer  JN2BEG2 		MUX-16
+	assign JN2BEG2_input = {M_AH,LH_O,LG_O,LF_O,LE_O,LD_O,LB_O,LA_O,WW4END1,W2END3,S2END3,E6END1,E2END3,E1END1,N4END3,N2END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG2 (
+	.A0 (JN2BEG2_input[0]),
+	.A1 (JN2BEG2_input[1]),
+	.A2 (JN2BEG2_input[2]),
+	.A3 (JN2BEG2_input[3]),
+	.A4 (JN2BEG2_input[4]),
+	.A5 (JN2BEG2_input[5]),
+	.A6 (JN2BEG2_input[6]),
+	.A7 (JN2BEG2_input[7]),
+	.A8 (JN2BEG2_input[8]),
+	.A9 (JN2BEG2_input[9]),
+	.A10 (JN2BEG2_input[10]),
+	.A11 (JN2BEG2_input[11]),
+	.A12 (JN2BEG2_input[12]),
+	.A13 (JN2BEG2_input[13]),
+	.A14 (JN2BEG2_input[14]),
+	.A15 (JN2BEG2_input[15]),
+	.S0 (ConfigBits[304+0]),
+	.S0N (ConfigBits_N[304+0]),
+	.S1 (ConfigBits[304+1]),
+	.S1N (ConfigBits_N[304+1]),
+	.S2 (ConfigBits[304+2]),
+	.S2N (ConfigBits_N[304+2]),
+	.S3 (ConfigBits[304+3]),
+	.S3N (ConfigBits_N[304+3]),
+	.X (JN2BEG2)
+	);
+
+// switch matrix multiplexer  JN2BEG3 		MUX-16
+	assign JN2BEG3_input = {M_EF,LH_O,LG_O,LF_O,LE_O,LC_O,LB_O,LA_O,W6END0,W2END4,S2END4,E6END0,E2END4,E1END2,N4END0,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG3 (
+	.A0 (JN2BEG3_input[0]),
+	.A1 (JN2BEG3_input[1]),
+	.A2 (JN2BEG3_input[2]),
+	.A3 (JN2BEG3_input[3]),
+	.A4 (JN2BEG3_input[4]),
+	.A5 (JN2BEG3_input[5]),
+	.A6 (JN2BEG3_input[6]),
+	.A7 (JN2BEG3_input[7]),
+	.A8 (JN2BEG3_input[8]),
+	.A9 (JN2BEG3_input[9]),
+	.A10 (JN2BEG3_input[10]),
+	.A11 (JN2BEG3_input[11]),
+	.A12 (JN2BEG3_input[12]),
+	.A13 (JN2BEG3_input[13]),
+	.A14 (JN2BEG3_input[14]),
+	.A15 (JN2BEG3_input[15]),
+	.S0 (ConfigBits[308+0]),
+	.S0N (ConfigBits_N[308+0]),
+	.S1 (ConfigBits[308+1]),
+	.S1N (ConfigBits_N[308+1]),
+	.S2 (ConfigBits[308+2]),
+	.S2N (ConfigBits_N[308+2]),
+	.S3 (ConfigBits[308+3]),
+	.S3N (ConfigBits_N[308+3]),
+	.X (JN2BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG4 		MUX-16
+	assign JN2BEG4_input = {M_AB,LH_O,LG_O,LF_O,LD_O,LC_O,LB_O,LA_O,W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG4 (
+	.A0 (JN2BEG4_input[0]),
+	.A1 (JN2BEG4_input[1]),
+	.A2 (JN2BEG4_input[2]),
+	.A3 (JN2BEG4_input[3]),
+	.A4 (JN2BEG4_input[4]),
+	.A5 (JN2BEG4_input[5]),
+	.A6 (JN2BEG4_input[6]),
+	.A7 (JN2BEG4_input[7]),
+	.A8 (JN2BEG4_input[8]),
+	.A9 (JN2BEG4_input[9]),
+	.A10 (JN2BEG4_input[10]),
+	.A11 (JN2BEG4_input[11]),
+	.A12 (JN2BEG4_input[12]),
+	.A13 (JN2BEG4_input[13]),
+	.A14 (JN2BEG4_input[14]),
+	.A15 (JN2BEG4_input[15]),
+	.S0 (ConfigBits[312+0]),
+	.S0N (ConfigBits_N[312+0]),
+	.S1 (ConfigBits[312+1]),
+	.S1N (ConfigBits_N[312+1]),
+	.S2 (ConfigBits[312+2]),
+	.S2N (ConfigBits_N[312+2]),
+	.S3 (ConfigBits[312+3]),
+	.S3N (ConfigBits_N[312+3]),
+	.X (JN2BEG4)
+	);
+
+// switch matrix multiplexer  JN2BEG5 		MUX-16
+	assign JN2BEG5_input = {M_AD,LH_O,LG_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG5 (
+	.A0 (JN2BEG5_input[0]),
+	.A1 (JN2BEG5_input[1]),
+	.A2 (JN2BEG5_input[2]),
+	.A3 (JN2BEG5_input[3]),
+	.A4 (JN2BEG5_input[4]),
+	.A5 (JN2BEG5_input[5]),
+	.A6 (JN2BEG5_input[6]),
+	.A7 (JN2BEG5_input[7]),
+	.A8 (JN2BEG5_input[8]),
+	.A9 (JN2BEG5_input[9]),
+	.A10 (JN2BEG5_input[10]),
+	.A11 (JN2BEG5_input[11]),
+	.A12 (JN2BEG5_input[12]),
+	.A13 (JN2BEG5_input[13]),
+	.A14 (JN2BEG5_input[14]),
+	.A15 (JN2BEG5_input[15]),
+	.S0 (ConfigBits[316+0]),
+	.S0N (ConfigBits_N[316+0]),
+	.S1 (ConfigBits[316+1]),
+	.S1N (ConfigBits_N[316+1]),
+	.S2 (ConfigBits[316+2]),
+	.S2N (ConfigBits_N[316+2]),
+	.S3 (ConfigBits[316+3]),
+	.S3N (ConfigBits_N[316+3]),
+	.X (JN2BEG5)
+	);
+
+// switch matrix multiplexer  JN2BEG6 		MUX-16
+	assign JN2BEG6_input = {M_AH,LH_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG6 (
+	.A0 (JN2BEG6_input[0]),
+	.A1 (JN2BEG6_input[1]),
+	.A2 (JN2BEG6_input[2]),
+	.A3 (JN2BEG6_input[3]),
+	.A4 (JN2BEG6_input[4]),
+	.A5 (JN2BEG6_input[5]),
+	.A6 (JN2BEG6_input[6]),
+	.A7 (JN2BEG6_input[7]),
+	.A8 (JN2BEG6_input[8]),
+	.A9 (JN2BEG6_input[9]),
+	.A10 (JN2BEG6_input[10]),
+	.A11 (JN2BEG6_input[11]),
+	.A12 (JN2BEG6_input[12]),
+	.A13 (JN2BEG6_input[13]),
+	.A14 (JN2BEG6_input[14]),
+	.A15 (JN2BEG6_input[15]),
+	.S0 (ConfigBits[320+0]),
+	.S0N (ConfigBits_N[320+0]),
+	.S1 (ConfigBits[320+1]),
+	.S1N (ConfigBits_N[320+1]),
+	.S2 (ConfigBits[320+2]),
+	.S2N (ConfigBits_N[320+2]),
+	.S3 (ConfigBits[320+3]),
+	.S3N (ConfigBits_N[320+3]),
+	.X (JN2BEG6)
+	);
+
+// switch matrix multiplexer  JN2BEG7 		MUX-16
+	assign JN2BEG7_input = {M_EF,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,W1END0,S2END0,S1END0,EE4END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG7 (
+	.A0 (JN2BEG7_input[0]),
+	.A1 (JN2BEG7_input[1]),
+	.A2 (JN2BEG7_input[2]),
+	.A3 (JN2BEG7_input[3]),
+	.A4 (JN2BEG7_input[4]),
+	.A5 (JN2BEG7_input[5]),
+	.A6 (JN2BEG7_input[6]),
+	.A7 (JN2BEG7_input[7]),
+	.A8 (JN2BEG7_input[8]),
+	.A9 (JN2BEG7_input[9]),
+	.A10 (JN2BEG7_input[10]),
+	.A11 (JN2BEG7_input[11]),
+	.A12 (JN2BEG7_input[12]),
+	.A13 (JN2BEG7_input[13]),
+	.A14 (JN2BEG7_input[14]),
+	.A15 (JN2BEG7_input[15]),
+	.S0 (ConfigBits[324+0]),
+	.S0N (ConfigBits_N[324+0]),
+	.S1 (ConfigBits[324+1]),
+	.S1N (ConfigBits_N[324+1]),
+	.S2 (ConfigBits[324+2]),
+	.S2N (ConfigBits_N[324+2]),
+	.S3 (ConfigBits[324+3]),
+	.S3N (ConfigBits_N[324+3]),
+	.X (JN2BEG7)
+	);
+
+// switch matrix multiplexer  JE2BEG0 		MUX-16
+	assign JE2BEG0_input = {M_EF,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,W6END1,W2END1,S2END1,E6END1,EE4END1,N4END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG0 (
+	.A0 (JE2BEG0_input[0]),
+	.A1 (JE2BEG0_input[1]),
+	.A2 (JE2BEG0_input[2]),
+	.A3 (JE2BEG0_input[3]),
+	.A4 (JE2BEG0_input[4]),
+	.A5 (JE2BEG0_input[5]),
+	.A6 (JE2BEG0_input[6]),
+	.A7 (JE2BEG0_input[7]),
+	.A8 (JE2BEG0_input[8]),
+	.A9 (JE2BEG0_input[9]),
+	.A10 (JE2BEG0_input[10]),
+	.A11 (JE2BEG0_input[11]),
+	.A12 (JE2BEG0_input[12]),
+	.A13 (JE2BEG0_input[13]),
+	.A14 (JE2BEG0_input[14]),
+	.A15 (JE2BEG0_input[15]),
+	.S0 (ConfigBits[328+0]),
+	.S0N (ConfigBits_N[328+0]),
+	.S1 (ConfigBits[328+1]),
+	.S1N (ConfigBits_N[328+1]),
+	.S2 (ConfigBits[328+2]),
+	.S2N (ConfigBits_N[328+2]),
+	.S3 (ConfigBits[328+3]),
+	.S3N (ConfigBits_N[328+3]),
+	.X (JE2BEG0)
+	);
+
+// switch matrix multiplexer  JE2BEG1 		MUX-16
+	assign JE2BEG1_input = {M_AB,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LA_O,WW4END3,W2END2,S2END2,E6END0,E2END2,N4END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG1 (
+	.A0 (JE2BEG1_input[0]),
+	.A1 (JE2BEG1_input[1]),
+	.A2 (JE2BEG1_input[2]),
+	.A3 (JE2BEG1_input[3]),
+	.A4 (JE2BEG1_input[4]),
+	.A5 (JE2BEG1_input[5]),
+	.A6 (JE2BEG1_input[6]),
+	.A7 (JE2BEG1_input[7]),
+	.A8 (JE2BEG1_input[8]),
+	.A9 (JE2BEG1_input[9]),
+	.A10 (JE2BEG1_input[10]),
+	.A11 (JE2BEG1_input[11]),
+	.A12 (JE2BEG1_input[12]),
+	.A13 (JE2BEG1_input[13]),
+	.A14 (JE2BEG1_input[14]),
+	.A15 (JE2BEG1_input[15]),
+	.S0 (ConfigBits[332+0]),
+	.S0N (ConfigBits_N[332+0]),
+	.S1 (ConfigBits[332+1]),
+	.S1N (ConfigBits_N[332+1]),
+	.S2 (ConfigBits[332+2]),
+	.S2N (ConfigBits_N[332+2]),
+	.S3 (ConfigBits[332+3]),
+	.S3N (ConfigBits_N[332+3]),
+	.X (JE2BEG1)
+	);
+
+// switch matrix multiplexer  JE2BEG2 		MUX-16
+	assign JE2BEG2_input = {M_AD,LH_O,LG_O,LF_O,LE_O,LD_O,LB_O,LA_O,W6END1,W2END3,S2END3,E6END1,E2END3,N4END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG2 (
+	.A0 (JE2BEG2_input[0]),
+	.A1 (JE2BEG2_input[1]),
+	.A2 (JE2BEG2_input[2]),
+	.A3 (JE2BEG2_input[3]),
+	.A4 (JE2BEG2_input[4]),
+	.A5 (JE2BEG2_input[5]),
+	.A6 (JE2BEG2_input[6]),
+	.A7 (JE2BEG2_input[7]),
+	.A8 (JE2BEG2_input[8]),
+	.A9 (JE2BEG2_input[9]),
+	.A10 (JE2BEG2_input[10]),
+	.A11 (JE2BEG2_input[11]),
+	.A12 (JE2BEG2_input[12]),
+	.A13 (JE2BEG2_input[13]),
+	.A14 (JE2BEG2_input[14]),
+	.A15 (JE2BEG2_input[15]),
+	.S0 (ConfigBits[336+0]),
+	.S0N (ConfigBits_N[336+0]),
+	.S1 (ConfigBits[336+1]),
+	.S1N (ConfigBits_N[336+1]),
+	.S2 (ConfigBits[336+2]),
+	.S2N (ConfigBits_N[336+2]),
+	.S3 (ConfigBits[336+3]),
+	.S3N (ConfigBits_N[336+3]),
+	.X (JE2BEG2)
+	);
+
+// switch matrix multiplexer  JE2BEG3 		MUX-16
+	assign JE2BEG3_input = {M_AH,LH_O,LG_O,LF_O,LE_O,LC_O,LB_O,LA_O,W6END0,W2END4,S2END4,E6END0,E2END4,N4END0,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG3 (
+	.A0 (JE2BEG3_input[0]),
+	.A1 (JE2BEG3_input[1]),
+	.A2 (JE2BEG3_input[2]),
+	.A3 (JE2BEG3_input[3]),
+	.A4 (JE2BEG3_input[4]),
+	.A5 (JE2BEG3_input[5]),
+	.A6 (JE2BEG3_input[6]),
+	.A7 (JE2BEG3_input[7]),
+	.A8 (JE2BEG3_input[8]),
+	.A9 (JE2BEG3_input[9]),
+	.A10 (JE2BEG3_input[10]),
+	.A11 (JE2BEG3_input[11]),
+	.A12 (JE2BEG3_input[12]),
+	.A13 (JE2BEG3_input[13]),
+	.A14 (JE2BEG3_input[14]),
+	.A15 (JE2BEG3_input[15]),
+	.S0 (ConfigBits[340+0]),
+	.S0N (ConfigBits_N[340+0]),
+	.S1 (ConfigBits[340+1]),
+	.S1N (ConfigBits_N[340+1]),
+	.S2 (ConfigBits[340+2]),
+	.S2N (ConfigBits_N[340+2]),
+	.S3 (ConfigBits[340+3]),
+	.S3N (ConfigBits_N[340+3]),
+	.X (JE2BEG3)
+	);
+
+// switch matrix multiplexer  JE2BEG4 		MUX-16
+	assign JE2BEG4_input = {M_EF,LH_O,LG_O,LF_O,LD_O,LC_O,LB_O,LA_O,W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG4 (
+	.A0 (JE2BEG4_input[0]),
+	.A1 (JE2BEG4_input[1]),
+	.A2 (JE2BEG4_input[2]),
+	.A3 (JE2BEG4_input[3]),
+	.A4 (JE2BEG4_input[4]),
+	.A5 (JE2BEG4_input[5]),
+	.A6 (JE2BEG4_input[6]),
+	.A7 (JE2BEG4_input[7]),
+	.A8 (JE2BEG4_input[8]),
+	.A9 (JE2BEG4_input[9]),
+	.A10 (JE2BEG4_input[10]),
+	.A11 (JE2BEG4_input[11]),
+	.A12 (JE2BEG4_input[12]),
+	.A13 (JE2BEG4_input[13]),
+	.A14 (JE2BEG4_input[14]),
+	.A15 (JE2BEG4_input[15]),
+	.S0 (ConfigBits[344+0]),
+	.S0N (ConfigBits_N[344+0]),
+	.S1 (ConfigBits[344+1]),
+	.S1N (ConfigBits_N[344+1]),
+	.S2 (ConfigBits[344+2]),
+	.S2N (ConfigBits_N[344+2]),
+	.S3 (ConfigBits[344+3]),
+	.S3N (ConfigBits_N[344+3]),
+	.X (JE2BEG4)
+	);
+
+// switch matrix multiplexer  JE2BEG5 		MUX-16
+	assign JE2BEG5_input = {M_AB,LH_O,LG_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG5 (
+	.A0 (JE2BEG5_input[0]),
+	.A1 (JE2BEG5_input[1]),
+	.A2 (JE2BEG5_input[2]),
+	.A3 (JE2BEG5_input[3]),
+	.A4 (JE2BEG5_input[4]),
+	.A5 (JE2BEG5_input[5]),
+	.A6 (JE2BEG5_input[6]),
+	.A7 (JE2BEG5_input[7]),
+	.A8 (JE2BEG5_input[8]),
+	.A9 (JE2BEG5_input[9]),
+	.A10 (JE2BEG5_input[10]),
+	.A11 (JE2BEG5_input[11]),
+	.A12 (JE2BEG5_input[12]),
+	.A13 (JE2BEG5_input[13]),
+	.A14 (JE2BEG5_input[14]),
+	.A15 (JE2BEG5_input[15]),
+	.S0 (ConfigBits[348+0]),
+	.S0N (ConfigBits_N[348+0]),
+	.S1 (ConfigBits[348+1]),
+	.S1N (ConfigBits_N[348+1]),
+	.S2 (ConfigBits[348+2]),
+	.S2N (ConfigBits_N[348+2]),
+	.S3 (ConfigBits[348+3]),
+	.S3N (ConfigBits_N[348+3]),
+	.X (JE2BEG5)
+	);
+
+// switch matrix multiplexer  JE2BEG6 		MUX-16
+	assign JE2BEG6_input = {M_AD,LH_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG6 (
+	.A0 (JE2BEG6_input[0]),
+	.A1 (JE2BEG6_input[1]),
+	.A2 (JE2BEG6_input[2]),
+	.A3 (JE2BEG6_input[3]),
+	.A4 (JE2BEG6_input[4]),
+	.A5 (JE2BEG6_input[5]),
+	.A6 (JE2BEG6_input[6]),
+	.A7 (JE2BEG6_input[7]),
+	.A8 (JE2BEG6_input[8]),
+	.A9 (JE2BEG6_input[9]),
+	.A10 (JE2BEG6_input[10]),
+	.A11 (JE2BEG6_input[11]),
+	.A12 (JE2BEG6_input[12]),
+	.A13 (JE2BEG6_input[13]),
+	.A14 (JE2BEG6_input[14]),
+	.A15 (JE2BEG6_input[15]),
+	.S0 (ConfigBits[352+0]),
+	.S0N (ConfigBits_N[352+0]),
+	.S1 (ConfigBits[352+1]),
+	.S1N (ConfigBits_N[352+1]),
+	.S2 (ConfigBits[352+2]),
+	.S2N (ConfigBits_N[352+2]),
+	.S3 (ConfigBits[352+3]),
+	.S3N (ConfigBits_N[352+3]),
+	.X (JE2BEG6)
+	);
+
+// switch matrix multiplexer  JE2BEG7 		MUX-16
+	assign JE2BEG7_input = {M_AH,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,WW4END0,SS4END0,S1END2,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG7 (
+	.A0 (JE2BEG7_input[0]),
+	.A1 (JE2BEG7_input[1]),
+	.A2 (JE2BEG7_input[2]),
+	.A3 (JE2BEG7_input[3]),
+	.A4 (JE2BEG7_input[4]),
+	.A5 (JE2BEG7_input[5]),
+	.A6 (JE2BEG7_input[6]),
+	.A7 (JE2BEG7_input[7]),
+	.A8 (JE2BEG7_input[8]),
+	.A9 (JE2BEG7_input[9]),
+	.A10 (JE2BEG7_input[10]),
+	.A11 (JE2BEG7_input[11]),
+	.A12 (JE2BEG7_input[12]),
+	.A13 (JE2BEG7_input[13]),
+	.A14 (JE2BEG7_input[14]),
+	.A15 (JE2BEG7_input[15]),
+	.S0 (ConfigBits[356+0]),
+	.S0N (ConfigBits_N[356+0]),
+	.S1 (ConfigBits[356+1]),
+	.S1N (ConfigBits_N[356+1]),
+	.S2 (ConfigBits[356+2]),
+	.S2N (ConfigBits_N[356+2]),
+	.S3 (ConfigBits[356+3]),
+	.S3N (ConfigBits_N[356+3]),
+	.X (JE2BEG7)
+	);
+
+// switch matrix multiplexer  JS2BEG0 		MUX-16
+	assign JS2BEG0_input = {M_AH,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,E1END3,NN4END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG0 (
+	.A0 (JS2BEG0_input[0]),
+	.A1 (JS2BEG0_input[1]),
+	.A2 (JS2BEG0_input[2]),
+	.A3 (JS2BEG0_input[3]),
+	.A4 (JS2BEG0_input[4]),
+	.A5 (JS2BEG0_input[5]),
+	.A6 (JS2BEG0_input[6]),
+	.A7 (JS2BEG0_input[7]),
+	.A8 (JS2BEG0_input[8]),
+	.A9 (JS2BEG0_input[9]),
+	.A10 (JS2BEG0_input[10]),
+	.A11 (JS2BEG0_input[11]),
+	.A12 (JS2BEG0_input[12]),
+	.A13 (JS2BEG0_input[13]),
+	.A14 (JS2BEG0_input[14]),
+	.A15 (JS2BEG0_input[15]),
+	.S0 (ConfigBits[360+0]),
+	.S0N (ConfigBits_N[360+0]),
+	.S1 (ConfigBits[360+1]),
+	.S1N (ConfigBits_N[360+1]),
+	.S2 (ConfigBits[360+2]),
+	.S2N (ConfigBits_N[360+2]),
+	.S3 (ConfigBits[360+3]),
+	.S3N (ConfigBits_N[360+3]),
+	.X (JS2BEG0)
+	);
+
+// switch matrix multiplexer  JS2BEG1 		MUX-16
+	assign JS2BEG1_input = {M_EF,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LA_O,W6END0,W2END2,SS4END2,S4END2,E6END0,EE4END2,E1END0,NN4END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG1 (
+	.A0 (JS2BEG1_input[0]),
+	.A1 (JS2BEG1_input[1]),
+	.A2 (JS2BEG1_input[2]),
+	.A3 (JS2BEG1_input[3]),
+	.A4 (JS2BEG1_input[4]),
+	.A5 (JS2BEG1_input[5]),
+	.A6 (JS2BEG1_input[6]),
+	.A7 (JS2BEG1_input[7]),
+	.A8 (JS2BEG1_input[8]),
+	.A9 (JS2BEG1_input[9]),
+	.A10 (JS2BEG1_input[10]),
+	.A11 (JS2BEG1_input[11]),
+	.A12 (JS2BEG1_input[12]),
+	.A13 (JS2BEG1_input[13]),
+	.A14 (JS2BEG1_input[14]),
+	.A15 (JS2BEG1_input[15]),
+	.S0 (ConfigBits[364+0]),
+	.S0N (ConfigBits_N[364+0]),
+	.S1 (ConfigBits[364+1]),
+	.S1N (ConfigBits_N[364+1]),
+	.S2 (ConfigBits[364+2]),
+	.S2N (ConfigBits_N[364+2]),
+	.S3 (ConfigBits[364+3]),
+	.S3N (ConfigBits_N[364+3]),
+	.X (JS2BEG1)
+	);
+
+// switch matrix multiplexer  JS2BEG2 		MUX-16
+	assign JS2BEG2_input = {M_AB,LH_O,LG_O,LF_O,LE_O,LD_O,LB_O,LA_O,W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,E1END1,NN4END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG2 (
+	.A0 (JS2BEG2_input[0]),
+	.A1 (JS2BEG2_input[1]),
+	.A2 (JS2BEG2_input[2]),
+	.A3 (JS2BEG2_input[3]),
+	.A4 (JS2BEG2_input[4]),
+	.A5 (JS2BEG2_input[5]),
+	.A6 (JS2BEG2_input[6]),
+	.A7 (JS2BEG2_input[7]),
+	.A8 (JS2BEG2_input[8]),
+	.A9 (JS2BEG2_input[9]),
+	.A10 (JS2BEG2_input[10]),
+	.A11 (JS2BEG2_input[11]),
+	.A12 (JS2BEG2_input[12]),
+	.A13 (JS2BEG2_input[13]),
+	.A14 (JS2BEG2_input[14]),
+	.A15 (JS2BEG2_input[15]),
+	.S0 (ConfigBits[368+0]),
+	.S0N (ConfigBits_N[368+0]),
+	.S1 (ConfigBits[368+1]),
+	.S1N (ConfigBits_N[368+1]),
+	.S2 (ConfigBits[368+2]),
+	.S2N (ConfigBits_N[368+2]),
+	.S3 (ConfigBits[368+3]),
+	.S3N (ConfigBits_N[368+3]),
+	.X (JS2BEG2)
+	);
+
+// switch matrix multiplexer  JS2BEG3 		MUX-16
+	assign JS2BEG3_input = {M_AD,LH_O,LG_O,LF_O,LE_O,LC_O,LB_O,LA_O,WW4END2,W2END4,S4END0,S2END4,E6END0,E2END4,E1END2,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG3 (
+	.A0 (JS2BEG3_input[0]),
+	.A1 (JS2BEG3_input[1]),
+	.A2 (JS2BEG3_input[2]),
+	.A3 (JS2BEG3_input[3]),
+	.A4 (JS2BEG3_input[4]),
+	.A5 (JS2BEG3_input[5]),
+	.A6 (JS2BEG3_input[6]),
+	.A7 (JS2BEG3_input[7]),
+	.A8 (JS2BEG3_input[8]),
+	.A9 (JS2BEG3_input[9]),
+	.A10 (JS2BEG3_input[10]),
+	.A11 (JS2BEG3_input[11]),
+	.A12 (JS2BEG3_input[12]),
+	.A13 (JS2BEG3_input[13]),
+	.A14 (JS2BEG3_input[14]),
+	.A15 (JS2BEG3_input[15]),
+	.S0 (ConfigBits[372+0]),
+	.S0N (ConfigBits_N[372+0]),
+	.S1 (ConfigBits[372+1]),
+	.S1N (ConfigBits_N[372+1]),
+	.S2 (ConfigBits[372+2]),
+	.S2N (ConfigBits_N[372+2]),
+	.S3 (ConfigBits[372+3]),
+	.S3N (ConfigBits_N[372+3]),
+	.X (JS2BEG3)
+	);
+
+// switch matrix multiplexer  JS2BEG4 		MUX-16
+	assign JS2BEG4_input = {M_AH,LH_O,LG_O,LF_O,LD_O,LC_O,LB_O,LA_O,W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG4 (
+	.A0 (JS2BEG4_input[0]),
+	.A1 (JS2BEG4_input[1]),
+	.A2 (JS2BEG4_input[2]),
+	.A3 (JS2BEG4_input[3]),
+	.A4 (JS2BEG4_input[4]),
+	.A5 (JS2BEG4_input[5]),
+	.A6 (JS2BEG4_input[6]),
+	.A7 (JS2BEG4_input[7]),
+	.A8 (JS2BEG4_input[8]),
+	.A9 (JS2BEG4_input[9]),
+	.A10 (JS2BEG4_input[10]),
+	.A11 (JS2BEG4_input[11]),
+	.A12 (JS2BEG4_input[12]),
+	.A13 (JS2BEG4_input[13]),
+	.A14 (JS2BEG4_input[14]),
+	.A15 (JS2BEG4_input[15]),
+	.S0 (ConfigBits[376+0]),
+	.S0N (ConfigBits_N[376+0]),
+	.S1 (ConfigBits[376+1]),
+	.S1N (ConfigBits_N[376+1]),
+	.S2 (ConfigBits[376+2]),
+	.S2N (ConfigBits_N[376+2]),
+	.S3 (ConfigBits[376+3]),
+	.S3N (ConfigBits_N[376+3]),
+	.X (JS2BEG4)
+	);
+
+// switch matrix multiplexer  JS2BEG5 		MUX-16
+	assign JS2BEG5_input = {M_EF,LH_O,LG_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG5 (
+	.A0 (JS2BEG5_input[0]),
+	.A1 (JS2BEG5_input[1]),
+	.A2 (JS2BEG5_input[2]),
+	.A3 (JS2BEG5_input[3]),
+	.A4 (JS2BEG5_input[4]),
+	.A5 (JS2BEG5_input[5]),
+	.A6 (JS2BEG5_input[6]),
+	.A7 (JS2BEG5_input[7]),
+	.A8 (JS2BEG5_input[8]),
+	.A9 (JS2BEG5_input[9]),
+	.A10 (JS2BEG5_input[10]),
+	.A11 (JS2BEG5_input[11]),
+	.A12 (JS2BEG5_input[12]),
+	.A13 (JS2BEG5_input[13]),
+	.A14 (JS2BEG5_input[14]),
+	.A15 (JS2BEG5_input[15]),
+	.S0 (ConfigBits[380+0]),
+	.S0N (ConfigBits_N[380+0]),
+	.S1 (ConfigBits[380+1]),
+	.S1N (ConfigBits_N[380+1]),
+	.S2 (ConfigBits[380+2]),
+	.S2N (ConfigBits_N[380+2]),
+	.S3 (ConfigBits[380+3]),
+	.S3N (ConfigBits_N[380+3]),
+	.X (JS2BEG5)
+	);
+
+// switch matrix multiplexer  JS2BEG6 		MUX-16
+	assign JS2BEG6_input = {M_AB,LH_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG6 (
+	.A0 (JS2BEG6_input[0]),
+	.A1 (JS2BEG6_input[1]),
+	.A2 (JS2BEG6_input[2]),
+	.A3 (JS2BEG6_input[3]),
+	.A4 (JS2BEG6_input[4]),
+	.A5 (JS2BEG6_input[5]),
+	.A6 (JS2BEG6_input[6]),
+	.A7 (JS2BEG6_input[7]),
+	.A8 (JS2BEG6_input[8]),
+	.A9 (JS2BEG6_input[9]),
+	.A10 (JS2BEG6_input[10]),
+	.A11 (JS2BEG6_input[11]),
+	.A12 (JS2BEG6_input[12]),
+	.A13 (JS2BEG6_input[13]),
+	.A14 (JS2BEG6_input[14]),
+	.A15 (JS2BEG6_input[15]),
+	.S0 (ConfigBits[384+0]),
+	.S0N (ConfigBits_N[384+0]),
+	.S1 (ConfigBits[384+1]),
+	.S1N (ConfigBits_N[384+1]),
+	.S2 (ConfigBits[384+2]),
+	.S2N (ConfigBits_N[384+2]),
+	.S3 (ConfigBits[384+3]),
+	.S3N (ConfigBits_N[384+3]),
+	.X (JS2BEG6)
+	);
+
+// switch matrix multiplexer  JS2BEG7 		MUX-16
+	assign JS2BEG7_input = {M_AD,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,W1END0,S2END0,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG7 (
+	.A0 (JS2BEG7_input[0]),
+	.A1 (JS2BEG7_input[1]),
+	.A2 (JS2BEG7_input[2]),
+	.A3 (JS2BEG7_input[3]),
+	.A4 (JS2BEG7_input[4]),
+	.A5 (JS2BEG7_input[5]),
+	.A6 (JS2BEG7_input[6]),
+	.A7 (JS2BEG7_input[7]),
+	.A8 (JS2BEG7_input[8]),
+	.A9 (JS2BEG7_input[9]),
+	.A10 (JS2BEG7_input[10]),
+	.A11 (JS2BEG7_input[11]),
+	.A12 (JS2BEG7_input[12]),
+	.A13 (JS2BEG7_input[13]),
+	.A14 (JS2BEG7_input[14]),
+	.A15 (JS2BEG7_input[15]),
+	.S0 (ConfigBits[388+0]),
+	.S0N (ConfigBits_N[388+0]),
+	.S1 (ConfigBits[388+1]),
+	.S1N (ConfigBits_N[388+1]),
+	.S2 (ConfigBits[388+2]),
+	.S2N (ConfigBits_N[388+2]),
+	.S3 (ConfigBits[388+3]),
+	.S3N (ConfigBits_N[388+3]),
+	.X (JS2BEG7)
+	);
+
+// switch matrix multiplexer  JW2BEG0 		MUX-16
+	assign JW2BEG0_input = {M_AD,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,W6END1,W2END1,S4END1,S2END1,E6END1,E2END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG0 (
+	.A0 (JW2BEG0_input[0]),
+	.A1 (JW2BEG0_input[1]),
+	.A2 (JW2BEG0_input[2]),
+	.A3 (JW2BEG0_input[3]),
+	.A4 (JW2BEG0_input[4]),
+	.A5 (JW2BEG0_input[5]),
+	.A6 (JW2BEG0_input[6]),
+	.A7 (JW2BEG0_input[7]),
+	.A8 (JW2BEG0_input[8]),
+	.A9 (JW2BEG0_input[9]),
+	.A10 (JW2BEG0_input[10]),
+	.A11 (JW2BEG0_input[11]),
+	.A12 (JW2BEG0_input[12]),
+	.A13 (JW2BEG0_input[13]),
+	.A14 (JW2BEG0_input[14]),
+	.A15 (JW2BEG0_input[15]),
+	.S0 (ConfigBits[392+0]),
+	.S0N (ConfigBits_N[392+0]),
+	.S1 (ConfigBits[392+1]),
+	.S1N (ConfigBits_N[392+1]),
+	.S2 (ConfigBits[392+2]),
+	.S2N (ConfigBits_N[392+2]),
+	.S3 (ConfigBits[392+3]),
+	.S3N (ConfigBits_N[392+3]),
+	.X (JW2BEG0)
+	);
+
+// switch matrix multiplexer  JW2BEG1 		MUX-16
+	assign JW2BEG1_input = {M_AH,LH_O,LG_O,LF_O,LE_O,LD_O,LC_O,LA_O,W6END0,W2END2,S4END2,S2END2,E6END0,E2END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG1 (
+	.A0 (JW2BEG1_input[0]),
+	.A1 (JW2BEG1_input[1]),
+	.A2 (JW2BEG1_input[2]),
+	.A3 (JW2BEG1_input[3]),
+	.A4 (JW2BEG1_input[4]),
+	.A5 (JW2BEG1_input[5]),
+	.A6 (JW2BEG1_input[6]),
+	.A7 (JW2BEG1_input[7]),
+	.A8 (JW2BEG1_input[8]),
+	.A9 (JW2BEG1_input[9]),
+	.A10 (JW2BEG1_input[10]),
+	.A11 (JW2BEG1_input[11]),
+	.A12 (JW2BEG1_input[12]),
+	.A13 (JW2BEG1_input[13]),
+	.A14 (JW2BEG1_input[14]),
+	.A15 (JW2BEG1_input[15]),
+	.S0 (ConfigBits[396+0]),
+	.S0N (ConfigBits_N[396+0]),
+	.S1 (ConfigBits[396+1]),
+	.S1N (ConfigBits_N[396+1]),
+	.S2 (ConfigBits[396+2]),
+	.S2N (ConfigBits_N[396+2]),
+	.S3 (ConfigBits[396+3]),
+	.S3N (ConfigBits_N[396+3]),
+	.X (JW2BEG1)
+	);
+
+// switch matrix multiplexer  JW2BEG2 		MUX-16
+	assign JW2BEG2_input = {M_EF,LH_O,LG_O,LF_O,LE_O,LD_O,LB_O,LA_O,W6END1,W2END3,SS4END3,S4END3,E6END1,EE4END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG2 (
+	.A0 (JW2BEG2_input[0]),
+	.A1 (JW2BEG2_input[1]),
+	.A2 (JW2BEG2_input[2]),
+	.A3 (JW2BEG2_input[3]),
+	.A4 (JW2BEG2_input[4]),
+	.A5 (JW2BEG2_input[5]),
+	.A6 (JW2BEG2_input[6]),
+	.A7 (JW2BEG2_input[7]),
+	.A8 (JW2BEG2_input[8]),
+	.A9 (JW2BEG2_input[9]),
+	.A10 (JW2BEG2_input[10]),
+	.A11 (JW2BEG2_input[11]),
+	.A12 (JW2BEG2_input[12]),
+	.A13 (JW2BEG2_input[13]),
+	.A14 (JW2BEG2_input[14]),
+	.A15 (JW2BEG2_input[15]),
+	.S0 (ConfigBits[400+0]),
+	.S0N (ConfigBits_N[400+0]),
+	.S1 (ConfigBits[400+1]),
+	.S1N (ConfigBits_N[400+1]),
+	.S2 (ConfigBits[400+2]),
+	.S2N (ConfigBits_N[400+2]),
+	.S3 (ConfigBits[400+3]),
+	.S3N (ConfigBits_N[400+3]),
+	.X (JW2BEG2)
+	);
+
+// switch matrix multiplexer  JW2BEG3 		MUX-16
+	assign JW2BEG3_input = {M_AB,LH_O,LG_O,LF_O,LE_O,LC_O,LB_O,LA_O,WW4END2,W2END4,S4END0,S2END4,E6END0,E2END4,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG3 (
+	.A0 (JW2BEG3_input[0]),
+	.A1 (JW2BEG3_input[1]),
+	.A2 (JW2BEG3_input[2]),
+	.A3 (JW2BEG3_input[3]),
+	.A4 (JW2BEG3_input[4]),
+	.A5 (JW2BEG3_input[5]),
+	.A6 (JW2BEG3_input[6]),
+	.A7 (JW2BEG3_input[7]),
+	.A8 (JW2BEG3_input[8]),
+	.A9 (JW2BEG3_input[9]),
+	.A10 (JW2BEG3_input[10]),
+	.A11 (JW2BEG3_input[11]),
+	.A12 (JW2BEG3_input[12]),
+	.A13 (JW2BEG3_input[13]),
+	.A14 (JW2BEG3_input[14]),
+	.A15 (JW2BEG3_input[15]),
+	.S0 (ConfigBits[404+0]),
+	.S0N (ConfigBits_N[404+0]),
+	.S1 (ConfigBits[404+1]),
+	.S1N (ConfigBits_N[404+1]),
+	.S2 (ConfigBits[404+2]),
+	.S2N (ConfigBits_N[404+2]),
+	.S3 (ConfigBits[404+3]),
+	.S3N (ConfigBits_N[404+3]),
+	.X (JW2BEG3)
+	);
+
+// switch matrix multiplexer  JW2BEG4 		MUX-16
+	assign JW2BEG4_input = {M_AD,LH_O,LG_O,LF_O,LD_O,LC_O,LB_O,LA_O,W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG4 (
+	.A0 (JW2BEG4_input[0]),
+	.A1 (JW2BEG4_input[1]),
+	.A2 (JW2BEG4_input[2]),
+	.A3 (JW2BEG4_input[3]),
+	.A4 (JW2BEG4_input[4]),
+	.A5 (JW2BEG4_input[5]),
+	.A6 (JW2BEG4_input[6]),
+	.A7 (JW2BEG4_input[7]),
+	.A8 (JW2BEG4_input[8]),
+	.A9 (JW2BEG4_input[9]),
+	.A10 (JW2BEG4_input[10]),
+	.A11 (JW2BEG4_input[11]),
+	.A12 (JW2BEG4_input[12]),
+	.A13 (JW2BEG4_input[13]),
+	.A14 (JW2BEG4_input[14]),
+	.A15 (JW2BEG4_input[15]),
+	.S0 (ConfigBits[408+0]),
+	.S0N (ConfigBits_N[408+0]),
+	.S1 (ConfigBits[408+1]),
+	.S1N (ConfigBits_N[408+1]),
+	.S2 (ConfigBits[408+2]),
+	.S2N (ConfigBits_N[408+2]),
+	.S3 (ConfigBits[408+3]),
+	.S3N (ConfigBits_N[408+3]),
+	.X (JW2BEG4)
+	);
+
+// switch matrix multiplexer  JW2BEG5 		MUX-16
+	assign JW2BEG5_input = {M_AH,LH_O,LG_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG5 (
+	.A0 (JW2BEG5_input[0]),
+	.A1 (JW2BEG5_input[1]),
+	.A2 (JW2BEG5_input[2]),
+	.A3 (JW2BEG5_input[3]),
+	.A4 (JW2BEG5_input[4]),
+	.A5 (JW2BEG5_input[5]),
+	.A6 (JW2BEG5_input[6]),
+	.A7 (JW2BEG5_input[7]),
+	.A8 (JW2BEG5_input[8]),
+	.A9 (JW2BEG5_input[9]),
+	.A10 (JW2BEG5_input[10]),
+	.A11 (JW2BEG5_input[11]),
+	.A12 (JW2BEG5_input[12]),
+	.A13 (JW2BEG5_input[13]),
+	.A14 (JW2BEG5_input[14]),
+	.A15 (JW2BEG5_input[15]),
+	.S0 (ConfigBits[412+0]),
+	.S0N (ConfigBits_N[412+0]),
+	.S1 (ConfigBits[412+1]),
+	.S1N (ConfigBits_N[412+1]),
+	.S2 (ConfigBits[412+2]),
+	.S2N (ConfigBits_N[412+2]),
+	.S3 (ConfigBits[412+3]),
+	.S3N (ConfigBits_N[412+3]),
+	.X (JW2BEG5)
+	);
+
+// switch matrix multiplexer  JW2BEG6 		MUX-16
+	assign JW2BEG6_input = {M_EF,LH_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG6 (
+	.A0 (JW2BEG6_input[0]),
+	.A1 (JW2BEG6_input[1]),
+	.A2 (JW2BEG6_input[2]),
+	.A3 (JW2BEG6_input[3]),
+	.A4 (JW2BEG6_input[4]),
+	.A5 (JW2BEG6_input[5]),
+	.A6 (JW2BEG6_input[6]),
+	.A7 (JW2BEG6_input[7]),
+	.A8 (JW2BEG6_input[8]),
+	.A9 (JW2BEG6_input[9]),
+	.A10 (JW2BEG6_input[10]),
+	.A11 (JW2BEG6_input[11]),
+	.A12 (JW2BEG6_input[12]),
+	.A13 (JW2BEG6_input[13]),
+	.A14 (JW2BEG6_input[14]),
+	.A15 (JW2BEG6_input[15]),
+	.S0 (ConfigBits[416+0]),
+	.S0N (ConfigBits_N[416+0]),
+	.S1 (ConfigBits[416+1]),
+	.S1N (ConfigBits_N[416+1]),
+	.S2 (ConfigBits[416+2]),
+	.S2N (ConfigBits_N[416+2]),
+	.S3 (ConfigBits[416+3]),
+	.S3N (ConfigBits_N[416+3]),
+	.X (JW2BEG6)
+	);
+
+// switch matrix multiplexer  JW2BEG7 		MUX-16
+	assign JW2BEG7_input = {M_AB,LG_O,LF_O,LE_O,LD_O,LC_O,LB_O,LA_O,W1END0,S2END0,S1END2,S1END0,E2END0,E1END0,NN4END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG7 (
+	.A0 (JW2BEG7_input[0]),
+	.A1 (JW2BEG7_input[1]),
+	.A2 (JW2BEG7_input[2]),
+	.A3 (JW2BEG7_input[3]),
+	.A4 (JW2BEG7_input[4]),
+	.A5 (JW2BEG7_input[5]),
+	.A6 (JW2BEG7_input[6]),
+	.A7 (JW2BEG7_input[7]),
+	.A8 (JW2BEG7_input[8]),
+	.A9 (JW2BEG7_input[9]),
+	.A10 (JW2BEG7_input[10]),
+	.A11 (JW2BEG7_input[11]),
+	.A12 (JW2BEG7_input[12]),
+	.A13 (JW2BEG7_input[13]),
+	.A14 (JW2BEG7_input[14]),
+	.A15 (JW2BEG7_input[15]),
+	.S0 (ConfigBits[420+0]),
+	.S0N (ConfigBits_N[420+0]),
+	.S1 (ConfigBits[420+1]),
+	.S1N (ConfigBits_N[420+1]),
+	.S2 (ConfigBits[420+2]),
+	.S2N (ConfigBits_N[420+2]),
+	.S3 (ConfigBits[420+3]),
+	.S3N (ConfigBits_N[420+3]),
+	.X (JW2BEG7)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG0 		MUX-4
+	assign J_l_AB_BEG0_input = {JN2END1,WW4END0,S4END3,NN4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG0 (
+	.A0 (J_l_AB_BEG0_input[0]),
+	.A1 (J_l_AB_BEG0_input[1]),
+	.A2 (J_l_AB_BEG0_input[2]),
+	.A3 (J_l_AB_BEG0_input[3]),
+	.S0 (ConfigBits[424+0]),
+	.S0N (ConfigBits_N[424+0]),
+	.S1 (ConfigBits[424+1]),
+	.S1N (ConfigBits_N[424+1]),
+	.X (J_l_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG1 		MUX-4
+	assign J_l_AB_BEG1_input = {JE2END1,W2END7,S4END2,EE4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG1 (
+	.A0 (J_l_AB_BEG1_input[0]),
+	.A1 (J_l_AB_BEG1_input[1]),
+	.A2 (J_l_AB_BEG1_input[2]),
+	.A3 (J_l_AB_BEG1_input[3]),
+	.S0 (ConfigBits[426+0]),
+	.S0N (ConfigBits_N[426+0]),
+	.S1 (ConfigBits[426+1]),
+	.S1N (ConfigBits_N[426+1]),
+	.X (J_l_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG2 		MUX-4
+	assign J_l_AB_BEG2_input = {JS2END1,W6END1,E6END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG2 (
+	.A0 (J_l_AB_BEG2_input[0]),
+	.A1 (J_l_AB_BEG2_input[1]),
+	.A2 (J_l_AB_BEG2_input[2]),
+	.A3 (J_l_AB_BEG2_input[3]),
+	.S0 (ConfigBits[428+0]),
+	.S0N (ConfigBits_N[428+0]),
+	.S1 (ConfigBits[428+1]),
+	.S1N (ConfigBits_N[428+1]),
+	.X (J_l_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG3 		MUX-4
+	assign J_l_AB_BEG3_input = {JW2END1,S4END0,E6END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG3 (
+	.A0 (J_l_AB_BEG3_input[0]),
+	.A1 (J_l_AB_BEG3_input[1]),
+	.A2 (J_l_AB_BEG3_input[2]),
+	.A3 (J_l_AB_BEG3_input[3]),
+	.S0 (ConfigBits[430+0]),
+	.S0N (ConfigBits_N[430+0]),
+	.S1 (ConfigBits[430+1]),
+	.S1N (ConfigBits_N[430+1]),
+	.X (J_l_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG0 		MUX-4
+	assign J_l_CD_BEG0_input = {JN2END2,WW4END2,SS4END3,E2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG0 (
+	.A0 (J_l_CD_BEG0_input[0]),
+	.A1 (J_l_CD_BEG0_input[1]),
+	.A2 (J_l_CD_BEG0_input[2]),
+	.A3 (J_l_CD_BEG0_input[3]),
+	.S0 (ConfigBits[432+0]),
+	.S0N (ConfigBits_N[432+0]),
+	.S1 (ConfigBits[432+1]),
+	.S1N (ConfigBits_N[432+1]),
+	.X (J_l_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG1 		MUX-4
+	assign J_l_CD_BEG1_input = {JE2END2,W2END7,E2END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG1 (
+	.A0 (J_l_CD_BEG1_input[0]),
+	.A1 (J_l_CD_BEG1_input[1]),
+	.A2 (J_l_CD_BEG1_input[2]),
+	.A3 (J_l_CD_BEG1_input[3]),
+	.S0 (ConfigBits[434+0]),
+	.S0N (ConfigBits_N[434+0]),
+	.S1 (ConfigBits[434+1]),
+	.S1N (ConfigBits_N[434+1]),
+	.X (J_l_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG2 		MUX-4
+	assign J_l_CD_BEG2_input = {JS2END2,S4END1,EE4END1,NN4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG2 (
+	.A0 (J_l_CD_BEG2_input[0]),
+	.A1 (J_l_CD_BEG2_input[1]),
+	.A2 (J_l_CD_BEG2_input[2]),
+	.A3 (J_l_CD_BEG2_input[3]),
+	.S0 (ConfigBits[436+0]),
+	.S0N (ConfigBits_N[436+0]),
+	.S1 (ConfigBits[436+1]),
+	.S1N (ConfigBits_N[436+1]),
+	.X (J_l_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG3 		MUX-4
+	assign J_l_CD_BEG3_input = {JW2END2,W6END0,SS4END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG3 (
+	.A0 (J_l_CD_BEG3_input[0]),
+	.A1 (J_l_CD_BEG3_input[1]),
+	.A2 (J_l_CD_BEG3_input[2]),
+	.A3 (J_l_CD_BEG3_input[3]),
+	.S0 (ConfigBits[438+0]),
+	.S0N (ConfigBits_N[438+0]),
+	.S1 (ConfigBits[438+1]),
+	.S1N (ConfigBits_N[438+1]),
+	.X (J_l_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG0 		MUX-4
+	assign J_l_EF_BEG0_input = {JN2END3,W2END3,E2END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG0 (
+	.A0 (J_l_EF_BEG0_input[0]),
+	.A1 (J_l_EF_BEG0_input[1]),
+	.A2 (J_l_EF_BEG0_input[2]),
+	.A3 (J_l_EF_BEG0_input[3]),
+	.S0 (ConfigBits[440+0]),
+	.S0N (ConfigBits_N[440+0]),
+	.S1 (ConfigBits[440+1]),
+	.S1N (ConfigBits_N[440+1]),
+	.X (J_l_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG1 		MUX-4
+	assign J_l_EF_BEG1_input = {JE2END3,S4END2,E2END2,NN4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG1 (
+	.A0 (J_l_EF_BEG1_input[0]),
+	.A1 (J_l_EF_BEG1_input[1]),
+	.A2 (J_l_EF_BEG1_input[2]),
+	.A3 (J_l_EF_BEG1_input[3]),
+	.S0 (ConfigBits[442+0]),
+	.S0N (ConfigBits_N[442+0]),
+	.S1 (ConfigBits[442+1]),
+	.S1N (ConfigBits_N[442+1]),
+	.X (J_l_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG2 		MUX-4
+	assign J_l_EF_BEG2_input = {JS2END3,W2END4,SS4END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG2 (
+	.A0 (J_l_EF_BEG2_input[0]),
+	.A1 (J_l_EF_BEG2_input[1]),
+	.A2 (J_l_EF_BEG2_input[2]),
+	.A3 (J_l_EF_BEG2_input[3]),
+	.S0 (ConfigBits[444+0]),
+	.S0N (ConfigBits_N[444+0]),
+	.S1 (ConfigBits[444+1]),
+	.S1N (ConfigBits_N[444+1]),
+	.X (J_l_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG3 		MUX-4
+	assign J_l_EF_BEG3_input = {JW2END3,WW4END1,S4END0,EE4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG3 (
+	.A0 (J_l_EF_BEG3_input[0]),
+	.A1 (J_l_EF_BEG3_input[1]),
+	.A2 (J_l_EF_BEG3_input[2]),
+	.A3 (J_l_EF_BEG3_input[3]),
+	.S0 (ConfigBits[446+0]),
+	.S0N (ConfigBits_N[446+0]),
+	.S1 (ConfigBits[446+1]),
+	.S1N (ConfigBits_N[446+1]),
+	.X (J_l_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG0 		MUX-4
+	assign J_l_GH_BEG0_input = {JN2END4,S4END3,EE4END0,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG0 (
+	.A0 (J_l_GH_BEG0_input[0]),
+	.A1 (J_l_GH_BEG0_input[1]),
+	.A2 (J_l_GH_BEG0_input[2]),
+	.A3 (J_l_GH_BEG0_input[3]),
+	.S0 (ConfigBits[448+0]),
+	.S0N (ConfigBits_N[448+0]),
+	.S1 (ConfigBits[448+1]),
+	.S1N (ConfigBits_N[448+1]),
+	.X (J_l_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG1 		MUX-4
+	assign J_l_GH_BEG1_input = {JE2END4,W2END2,SS4END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG1 (
+	.A0 (J_l_GH_BEG1_input[0]),
+	.A1 (J_l_GH_BEG1_input[1]),
+	.A2 (J_l_GH_BEG1_input[2]),
+	.A3 (J_l_GH_BEG1_input[3]),
+	.S0 (ConfigBits[450+0]),
+	.S0N (ConfigBits_N[450+0]),
+	.S1 (ConfigBits[450+1]),
+	.S1N (ConfigBits_N[450+1]),
+	.X (J_l_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG2 		MUX-4
+	assign J_l_GH_BEG2_input = {JS2END4,WW4END3,S4END1,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG2 (
+	.A0 (J_l_GH_BEG2_input[0]),
+	.A1 (J_l_GH_BEG2_input[1]),
+	.A2 (J_l_GH_BEG2_input[2]),
+	.A3 (J_l_GH_BEG2_input[3]),
+	.S0 (ConfigBits[452+0]),
+	.S0N (ConfigBits_N[452+0]),
+	.S1 (ConfigBits[452+1]),
+	.S1N (ConfigBits_N[452+1]),
+	.X (J_l_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG3 		MUX-4
+	assign J_l_GH_BEG3_input = {JW2END4,W2END0,E6END0,NN4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG3 (
+	.A0 (J_l_GH_BEG3_input[0]),
+	.A1 (J_l_GH_BEG3_input[1]),
+	.A2 (J_l_GH_BEG3_input[2]),
+	.A3 (J_l_GH_BEG3_input[3]),
+	.S0 (ConfigBits[454+0]),
+	.S0N (ConfigBits_N[454+0]),
+	.S1 (ConfigBits[454+1]),
+	.S1N (ConfigBits_N[454+1]),
+	.X (J_l_GH_BEG3)
+	);
+
+// switch matrix multiplexer  J_SR_BEG0 		MUX-8
+	assign J_SR_BEG0_input = {JW2END1,JS2END1,JE2END1,JN2END1,J2MID_EFb_END0,J2MID_CDb_END0,J2MID_ABb_END0,J2MID_GHa_END0};
+	cus_mux81_buf inst_cus_mux81_buf_J_SR_BEG0 (
+	.A0 (J_SR_BEG0_input[0]),
+	.A1 (J_SR_BEG0_input[1]),
+	.A2 (J_SR_BEG0_input[2]),
+	.A3 (J_SR_BEG0_input[3]),
+	.A4 (J_SR_BEG0_input[4]),
+	.A5 (J_SR_BEG0_input[5]),
+	.A6 (J_SR_BEG0_input[6]),
+	.A7 (J_SR_BEG0_input[7]),
+	.S0 (ConfigBits[456+0]),
+	.S0N (ConfigBits_N[456+0]),
+	.S1 (ConfigBits[456+1]),
+	.S1N (ConfigBits_N[456+1]),
+	.S2 (ConfigBits[456+2]),
+	.S2N (ConfigBits_N[456+2]),
+	.X (J_SR_BEG0)
+	);
+
+// switch matrix multiplexer  J_EN_BEG0 		MUX-8
+	assign J_EN_BEG0_input = {JW2END2,JS2END2,JE2END2,JN2END2,J2MID_EFb_END3,J2MID_CDb_END3,J2MID_ABb_END3,J2MID_GHa_END3};
+	cus_mux81_buf inst_cus_mux81_buf_J_EN_BEG0 (
+	.A0 (J_EN_BEG0_input[0]),
+	.A1 (J_EN_BEG0_input[1]),
+	.A2 (J_EN_BEG0_input[2]),
+	.A3 (J_EN_BEG0_input[3]),
+	.A4 (J_EN_BEG0_input[4]),
+	.A5 (J_EN_BEG0_input[5]),
+	.A6 (J_EN_BEG0_input[6]),
+	.A7 (J_EN_BEG0_input[7]),
+	.S0 (ConfigBits[459+0]),
+	.S0N (ConfigBits_N[459+0]),
+	.S1 (ConfigBits[459+1]),
+	.S1N (ConfigBits_N[459+1]),
+	.S2 (ConfigBits[459+2]),
+	.S2N (ConfigBits_N[459+2]),
+	.X (J_EN_BEG0)
+	);
+
+	assign DEBUG_select_N1BEG0 = ConfigBits[1:0];
+	assign DEBUG_select_N1BEG1 = ConfigBits[3:2];
+	assign DEBUG_select_N1BEG2 = ConfigBits[5:4];
+	assign DEBUG_select_N1BEG3 = ConfigBits[7:6];
+	assign DEBUG_select_N4BEG0 = ConfigBits[9:8];
+	assign DEBUG_select_N4BEG1 = ConfigBits[11:10];
+	assign DEBUG_select_N4BEG2 = ConfigBits[13:12];
+	assign DEBUG_select_N4BEG3 = ConfigBits[15:14];
+	assign DEBUG_select_NN4BEG0 = ConfigBits[18:16];
+	assign DEBUG_select_NN4BEG1 = ConfigBits[21:19];
+	assign DEBUG_select_NN4BEG2 = ConfigBits[24:22];
+	assign DEBUG_select_NN4BEG3 = ConfigBits[27:25];
+	assign DEBUG_select_E1BEG0 = ConfigBits[29:28];
+	assign DEBUG_select_E1BEG1 = ConfigBits[31:30];
+	assign DEBUG_select_E1BEG2 = ConfigBits[33:32];
+	assign DEBUG_select_E1BEG3 = ConfigBits[35:34];
+	assign DEBUG_select_EE4BEG0 = ConfigBits[38:36];
+	assign DEBUG_select_EE4BEG1 = ConfigBits[41:39];
+	assign DEBUG_select_EE4BEG2 = ConfigBits[44:42];
+	assign DEBUG_select_EE4BEG3 = ConfigBits[47:45];
+	assign DEBUG_select_E6BEG0 = ConfigBits[51:48];
+	assign DEBUG_select_E6BEG1 = ConfigBits[55:52];
+	assign DEBUG_select_S1BEG0 = ConfigBits[57:56];
+	assign DEBUG_select_S1BEG1 = ConfigBits[59:58];
+	assign DEBUG_select_S1BEG2 = ConfigBits[61:60];
+	assign DEBUG_select_S1BEG3 = ConfigBits[63:62];
+	assign DEBUG_select_S4BEG0 = ConfigBits[65:64];
+	assign DEBUG_select_S4BEG1 = ConfigBits[67:66];
+	assign DEBUG_select_S4BEG2 = ConfigBits[69:68];
+	assign DEBUG_select_S4BEG3 = ConfigBits[71:70];
+	assign DEBUG_select_SS4BEG0 = ConfigBits[74:72];
+	assign DEBUG_select_SS4BEG1 = ConfigBits[77:75];
+	assign DEBUG_select_SS4BEG2 = ConfigBits[80:78];
+	assign DEBUG_select_SS4BEG3 = ConfigBits[83:81];
+	assign DEBUG_select_W1BEG0 = ConfigBits[85:84];
+	assign DEBUG_select_W1BEG1 = ConfigBits[87:86];
+	assign DEBUG_select_W1BEG2 = ConfigBits[89:88];
+	assign DEBUG_select_W1BEG3 = ConfigBits[91:90];
+	assign DEBUG_select_WW4BEG0 = ConfigBits[94:92];
+	assign DEBUG_select_WW4BEG1 = ConfigBits[97:95];
+	assign DEBUG_select_WW4BEG2 = ConfigBits[100:98];
+	assign DEBUG_select_WW4BEG3 = ConfigBits[103:101];
+	assign DEBUG_select_W6BEG0 = ConfigBits[107:104];
+	assign DEBUG_select_W6BEG1 = ConfigBits[111:108];
+	assign DEBUG_select_LA_I0 = ConfigBits[113:112];
+	assign DEBUG_select_LA_I1 = ConfigBits[115:114];
+	assign DEBUG_select_LA_I2 = ConfigBits[117:116];
+	assign DEBUG_select_LA_I3 = ConfigBits[119:118];
+	assign DEBUG_select_LA_SR = ConfigBits[120:120];
+	assign DEBUG_select_LA_EN = ConfigBits[121:121];
+	assign DEBUG_select_LB_I0 = ConfigBits[123:122];
+	assign DEBUG_select_LB_I1 = ConfigBits[125:124];
+	assign DEBUG_select_LB_I2 = ConfigBits[127:126];
+	assign DEBUG_select_LB_I3 = ConfigBits[129:128];
+	assign DEBUG_select_LB_SR = ConfigBits[130:130];
+	assign DEBUG_select_LB_EN = ConfigBits[131:131];
+	assign DEBUG_select_LC_I0 = ConfigBits[133:132];
+	assign DEBUG_select_LC_I1 = ConfigBits[135:134];
+	assign DEBUG_select_LC_I2 = ConfigBits[137:136];
+	assign DEBUG_select_LC_I3 = ConfigBits[139:138];
+	assign DEBUG_select_LC_SR = ConfigBits[140:140];
+	assign DEBUG_select_LC_EN = ConfigBits[141:141];
+	assign DEBUG_select_LD_I0 = ConfigBits[143:142];
+	assign DEBUG_select_LD_I1 = ConfigBits[145:144];
+	assign DEBUG_select_LD_I2 = ConfigBits[147:146];
+	assign DEBUG_select_LD_I3 = ConfigBits[149:148];
+	assign DEBUG_select_LD_SR = ConfigBits[150:150];
+	assign DEBUG_select_LD_EN = ConfigBits[151:151];
+	assign DEBUG_select_LE_I0 = ConfigBits[153:152];
+	assign DEBUG_select_LE_I1 = ConfigBits[155:154];
+	assign DEBUG_select_LE_I2 = ConfigBits[157:156];
+	assign DEBUG_select_LE_I3 = ConfigBits[159:158];
+	assign DEBUG_select_LE_SR = ConfigBits[160:160];
+	assign DEBUG_select_LE_EN = ConfigBits[161:161];
+	assign DEBUG_select_LF_I0 = ConfigBits[163:162];
+	assign DEBUG_select_LF_I1 = ConfigBits[165:164];
+	assign DEBUG_select_LF_I2 = ConfigBits[167:166];
+	assign DEBUG_select_LF_I3 = ConfigBits[169:168];
+	assign DEBUG_select_LF_SR = ConfigBits[170:170];
+	assign DEBUG_select_LF_EN = ConfigBits[171:171];
+	assign DEBUG_select_LG_I0 = ConfigBits[173:172];
+	assign DEBUG_select_LG_I1 = ConfigBits[175:174];
+	assign DEBUG_select_LG_I2 = ConfigBits[177:176];
+	assign DEBUG_select_LG_I3 = ConfigBits[179:178];
+	assign DEBUG_select_LG_SR = ConfigBits[180:180];
+	assign DEBUG_select_LG_EN = ConfigBits[181:181];
+	assign DEBUG_select_LH_I0 = ConfigBits[183:182];
+	assign DEBUG_select_LH_I1 = ConfigBits[185:184];
+	assign DEBUG_select_LH_I2 = ConfigBits[187:186];
+	assign DEBUG_select_LH_I3 = ConfigBits[189:188];
+	assign DEBUG_select_LH_SR = ConfigBits[190:190];
+	assign DEBUG_select_LH_EN = ConfigBits[191:191];
+	assign DEBUG_select_S0 = ConfigBits[193:192];
+	assign DEBUG_select_S1 = ConfigBits[195:194];
+	assign DEBUG_select_S2 = ConfigBits[197:196];
+	assign DEBUG_select_S3 = ConfigBits[199:198];
+	assign DEBUG_select_J2MID_ABa_BEG0 = ConfigBits[201:200];
+	assign DEBUG_select_J2MID_ABa_BEG1 = ConfigBits[203:202];
+	assign DEBUG_select_J2MID_ABa_BEG2 = ConfigBits[205:204];
+	assign DEBUG_select_J2MID_ABa_BEG3 = ConfigBits[207:206];
+	assign DEBUG_select_J2MID_CDa_BEG0 = ConfigBits[209:208];
+	assign DEBUG_select_J2MID_CDa_BEG1 = ConfigBits[211:210];
+	assign DEBUG_select_J2MID_CDa_BEG2 = ConfigBits[213:212];
+	assign DEBUG_select_J2MID_CDa_BEG3 = ConfigBits[215:214];
+	assign DEBUG_select_J2MID_EFa_BEG0 = ConfigBits[217:216];
+	assign DEBUG_select_J2MID_EFa_BEG1 = ConfigBits[219:218];
+	assign DEBUG_select_J2MID_EFa_BEG2 = ConfigBits[221:220];
+	assign DEBUG_select_J2MID_EFa_BEG3 = ConfigBits[223:222];
+	assign DEBUG_select_J2MID_GHa_BEG0 = ConfigBits[225:224];
+	assign DEBUG_select_J2MID_GHa_BEG1 = ConfigBits[227:226];
+	assign DEBUG_select_J2MID_GHa_BEG2 = ConfigBits[229:228];
+	assign DEBUG_select_J2MID_GHa_BEG3 = ConfigBits[231:230];
+	assign DEBUG_select_J2MID_ABb_BEG0 = ConfigBits[233:232];
+	assign DEBUG_select_J2MID_ABb_BEG1 = ConfigBits[235:234];
+	assign DEBUG_select_J2MID_ABb_BEG2 = ConfigBits[237:236];
+	assign DEBUG_select_J2MID_ABb_BEG3 = ConfigBits[239:238];
+	assign DEBUG_select_J2MID_CDb_BEG0 = ConfigBits[241:240];
+	assign DEBUG_select_J2MID_CDb_BEG1 = ConfigBits[243:242];
+	assign DEBUG_select_J2MID_CDb_BEG2 = ConfigBits[245:244];
+	assign DEBUG_select_J2MID_CDb_BEG3 = ConfigBits[247:246];
+	assign DEBUG_select_J2MID_EFb_BEG0 = ConfigBits[249:248];
+	assign DEBUG_select_J2MID_EFb_BEG1 = ConfigBits[251:250];
+	assign DEBUG_select_J2MID_EFb_BEG2 = ConfigBits[253:252];
+	assign DEBUG_select_J2MID_EFb_BEG3 = ConfigBits[255:254];
+	assign DEBUG_select_J2MID_GHb_BEG0 = ConfigBits[257:256];
+	assign DEBUG_select_J2MID_GHb_BEG1 = ConfigBits[259:258];
+	assign DEBUG_select_J2MID_GHb_BEG2 = ConfigBits[261:260];
+	assign DEBUG_select_J2MID_GHb_BEG3 = ConfigBits[263:262];
+	assign DEBUG_select_J2END_AB_BEG0 = ConfigBits[265:264];
+	assign DEBUG_select_J2END_AB_BEG1 = ConfigBits[267:266];
+	assign DEBUG_select_J2END_AB_BEG2 = ConfigBits[269:268];
+	assign DEBUG_select_J2END_AB_BEG3 = ConfigBits[271:270];
+	assign DEBUG_select_J2END_CD_BEG0 = ConfigBits[273:272];
+	assign DEBUG_select_J2END_CD_BEG1 = ConfigBits[275:274];
+	assign DEBUG_select_J2END_CD_BEG2 = ConfigBits[277:276];
+	assign DEBUG_select_J2END_CD_BEG3 = ConfigBits[279:278];
+	assign DEBUG_select_J2END_EF_BEG0 = ConfigBits[281:280];
+	assign DEBUG_select_J2END_EF_BEG1 = ConfigBits[283:282];
+	assign DEBUG_select_J2END_EF_BEG2 = ConfigBits[285:284];
+	assign DEBUG_select_J2END_EF_BEG3 = ConfigBits[287:286];
+	assign DEBUG_select_J2END_GH_BEG0 = ConfigBits[289:288];
+	assign DEBUG_select_J2END_GH_BEG1 = ConfigBits[291:290];
+	assign DEBUG_select_J2END_GH_BEG2 = ConfigBits[293:292];
+	assign DEBUG_select_J2END_GH_BEG3 = ConfigBits[295:294];
+	assign DEBUG_select_JN2BEG0 = ConfigBits[299:296];
+	assign DEBUG_select_JN2BEG1 = ConfigBits[303:300];
+	assign DEBUG_select_JN2BEG2 = ConfigBits[307:304];
+	assign DEBUG_select_JN2BEG3 = ConfigBits[311:308];
+	assign DEBUG_select_JN2BEG4 = ConfigBits[315:312];
+	assign DEBUG_select_JN2BEG5 = ConfigBits[319:316];
+	assign DEBUG_select_JN2BEG6 = ConfigBits[323:320];
+	assign DEBUG_select_JN2BEG7 = ConfigBits[327:324];
+	assign DEBUG_select_JE2BEG0 = ConfigBits[331:328];
+	assign DEBUG_select_JE2BEG1 = ConfigBits[335:332];
+	assign DEBUG_select_JE2BEG2 = ConfigBits[339:336];
+	assign DEBUG_select_JE2BEG3 = ConfigBits[343:340];
+	assign DEBUG_select_JE2BEG4 = ConfigBits[347:344];
+	assign DEBUG_select_JE2BEG5 = ConfigBits[351:348];
+	assign DEBUG_select_JE2BEG6 = ConfigBits[355:352];
+	assign DEBUG_select_JE2BEG7 = ConfigBits[359:356];
+	assign DEBUG_select_JS2BEG0 = ConfigBits[363:360];
+	assign DEBUG_select_JS2BEG1 = ConfigBits[367:364];
+	assign DEBUG_select_JS2BEG2 = ConfigBits[371:368];
+	assign DEBUG_select_JS2BEG3 = ConfigBits[375:372];
+	assign DEBUG_select_JS2BEG4 = ConfigBits[379:376];
+	assign DEBUG_select_JS2BEG5 = ConfigBits[383:380];
+	assign DEBUG_select_JS2BEG6 = ConfigBits[387:384];
+	assign DEBUG_select_JS2BEG7 = ConfigBits[391:388];
+	assign DEBUG_select_JW2BEG0 = ConfigBits[395:392];
+	assign DEBUG_select_JW2BEG1 = ConfigBits[399:396];
+	assign DEBUG_select_JW2BEG2 = ConfigBits[403:400];
+	assign DEBUG_select_JW2BEG3 = ConfigBits[407:404];
+	assign DEBUG_select_JW2BEG4 = ConfigBits[411:408];
+	assign DEBUG_select_JW2BEG5 = ConfigBits[415:412];
+	assign DEBUG_select_JW2BEG6 = ConfigBits[419:416];
+	assign DEBUG_select_JW2BEG7 = ConfigBits[423:420];
+	assign DEBUG_select_J_l_AB_BEG0 = ConfigBits[425:424];
+	assign DEBUG_select_J_l_AB_BEG1 = ConfigBits[427:426];
+	assign DEBUG_select_J_l_AB_BEG2 = ConfigBits[429:428];
+	assign DEBUG_select_J_l_AB_BEG3 = ConfigBits[431:430];
+	assign DEBUG_select_J_l_CD_BEG0 = ConfigBits[433:432];
+	assign DEBUG_select_J_l_CD_BEG1 = ConfigBits[435:434];
+	assign DEBUG_select_J_l_CD_BEG2 = ConfigBits[437:436];
+	assign DEBUG_select_J_l_CD_BEG3 = ConfigBits[439:438];
+	assign DEBUG_select_J_l_EF_BEG0 = ConfigBits[441:440];
+	assign DEBUG_select_J_l_EF_BEG1 = ConfigBits[443:442];
+	assign DEBUG_select_J_l_EF_BEG2 = ConfigBits[445:444];
+	assign DEBUG_select_J_l_EF_BEG3 = ConfigBits[447:446];
+	assign DEBUG_select_J_l_GH_BEG0 = ConfigBits[449:448];
+	assign DEBUG_select_J_l_GH_BEG1 = ConfigBits[451:450];
+	assign DEBUG_select_J_l_GH_BEG2 = ConfigBits[453:452];
+	assign DEBUG_select_J_l_GH_BEG3 = ConfigBits[455:454];
+	assign DEBUG_select_J_SR_BEG0 = ConfigBits[458:456];
+	assign DEBUG_select_J_EN_BEG0 = ConfigBits[461:459];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/LUT4AB_tile.v b/verilog/rtl/eFPGA_core/LUT4AB_tile.v
new file mode 100644
index 0000000..591d44d
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/LUT4AB_tile.v
@@ -0,0 +1,2335 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module LUT4AB (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, Co, N1END, N2MID, N2END, N4END, NN4END, Ci, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 616;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	output [0:0] Co; //wires:1 X_offset:0 Y_offset:1  source_name:Co destination_name:Ci  
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	input [0:0] Ci; //wires:1 X_offset:0 Y_offset:1  source_name:Co destination_name:Ci  
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	// Tile IO ports from BELs
+	input UserCLK;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire LA_I0;
+	wire LA_I1;
+	wire LA_I2;
+	wire LA_I3;
+	wire LA_Ci;
+	wire LA_SR;
+	wire LA_EN;
+	wire LB_I0;
+	wire LB_I1;
+	wire LB_I2;
+	wire LB_I3;
+	wire LB_Ci;
+	wire LB_SR;
+	wire LB_EN;
+	wire LC_I0;
+	wire LC_I1;
+	wire LC_I2;
+	wire LC_I3;
+	wire LC_Ci;
+	wire LC_SR;
+	wire LC_EN;
+	wire LD_I0;
+	wire LD_I1;
+	wire LD_I2;
+	wire LD_I3;
+	wire LD_Ci;
+	wire LD_SR;
+	wire LD_EN;
+	wire LE_I0;
+	wire LE_I1;
+	wire LE_I2;
+	wire LE_I3;
+	wire LE_Ci;
+	wire LE_SR;
+	wire LE_EN;
+	wire LF_I0;
+	wire LF_I1;
+	wire LF_I2;
+	wire LF_I3;
+	wire LF_Ci;
+	wire LF_SR;
+	wire LF_EN;
+	wire LG_I0;
+	wire LG_I1;
+	wire LG_I2;
+	wire LG_I3;
+	wire LG_Ci;
+	wire LG_SR;
+	wire LG_EN;
+	wire LH_I0;
+	wire LH_I1;
+	wire LH_I2;
+	wire LH_I3;
+	wire LH_Ci;
+	wire LH_SR;
+	wire LH_EN;
+	wire A;
+	wire B;
+	wire C;
+	wire D;
+	wire E;
+	wire F;
+	wire G;
+	wire H;
+	wire S0;
+	wire S1;
+	wire S2;
+	wire S3;
+	wire LA_O;
+	wire LA_Co;
+	wire LB_O;
+	wire LB_Co;
+	wire LC_O;
+	wire LC_Co;
+	wire LD_O;
+	wire LD_Co;
+	wire LE_O;
+	wire LE_Co;
+	wire LF_O;
+	wire LF_Co;
+	wire LG_O;
+	wire LG_Co;
+	wire LH_O;
+	wire LH_Co;
+	wire M_AB;
+	wire M_AD;
+	wire M_AH;
+	wire M_EF;
+//jump wires
+	wire [4-1:0] J2MID_ABa_BEG;
+	wire [4-1:0] J2MID_CDa_BEG;
+	wire [4-1:0] J2MID_EFa_BEG;
+	wire [4-1:0] J2MID_GHa_BEG;
+	wire [4-1:0] J2MID_ABb_BEG;
+	wire [4-1:0] J2MID_CDb_BEG;
+	wire [4-1:0] J2MID_EFb_BEG;
+	wire [4-1:0] J2MID_GHb_BEG;
+	wire [4-1:0] J2END_AB_BEG;
+	wire [4-1:0] J2END_CD_BEG;
+	wire [4-1:0] J2END_EF_BEG;
+	wire [4-1:0] J2END_GH_BEG;
+	wire [8-1:0] JN2BEG;
+	wire [8-1:0] JE2BEG;
+	wire [8-1:0] JS2BEG;
+	wire [8-1:0] JW2BEG;
+	wire [4-1:0] J_l_AB_BEG;
+	wire [4-1:0] J_l_CD_BEG;
+	wire [4-1:0] J_l_EF_BEG;
+	wire [4-1:0] J_l_GH_BEG;
+	wire [1-1:0] J_SR_BEG;
+	wire [1-1:0] J_EN_BEG;
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	wire [15:0] N4END_i;
+	wire [11:0] N4BEG_i;
+	assign N4BEG_i[15-4:0] = N4END_i[15:4];
+
+	my_buf N4END_inbuf_0 (
+	.A(N4END[4]),
+	.X(N4END_i[4])
+	);
+
+	my_buf N4END_inbuf_1 (
+	.A(N4END[5]),
+	.X(N4END_i[5])
+	);
+
+	my_buf N4END_inbuf_2 (
+	.A(N4END[6]),
+	.X(N4END_i[6])
+	);
+
+	my_buf N4END_inbuf_3 (
+	.A(N4END[7]),
+	.X(N4END_i[7])
+	);
+
+	my_buf N4END_inbuf_4 (
+	.A(N4END[8]),
+	.X(N4END_i[8])
+	);
+
+	my_buf N4END_inbuf_5 (
+	.A(N4END[9]),
+	.X(N4END_i[9])
+	);
+
+	my_buf N4END_inbuf_6 (
+	.A(N4END[10]),
+	.X(N4END_i[10])
+	);
+
+	my_buf N4END_inbuf_7 (
+	.A(N4END[11]),
+	.X(N4END_i[11])
+	);
+
+	my_buf N4END_inbuf_8 (
+	.A(N4END[12]),
+	.X(N4END_i[12])
+	);
+
+	my_buf N4END_inbuf_9 (
+	.A(N4END[13]),
+	.X(N4END_i[13])
+	);
+
+	my_buf N4END_inbuf_10 (
+	.A(N4END[14]),
+	.X(N4END_i[14])
+	);
+
+	my_buf N4END_inbuf_11 (
+	.A(N4END[15]),
+	.X(N4END_i[15])
+	);
+
+	my_buf N4BEG_outbuf_0 (
+	.A(N4BEG_i[0]),
+	.X(N4BEG[0])
+	);
+
+	my_buf N4BEG_outbuf_1 (
+	.A(N4BEG_i[1]),
+	.X(N4BEG[1])
+	);
+
+	my_buf N4BEG_outbuf_2 (
+	.A(N4BEG_i[2]),
+	.X(N4BEG[2])
+	);
+
+	my_buf N4BEG_outbuf_3 (
+	.A(N4BEG_i[3]),
+	.X(N4BEG[3])
+	);
+
+	my_buf N4BEG_outbuf_4 (
+	.A(N4BEG_i[4]),
+	.X(N4BEG[4])
+	);
+
+	my_buf N4BEG_outbuf_5 (
+	.A(N4BEG_i[5]),
+	.X(N4BEG[5])
+	);
+
+	my_buf N4BEG_outbuf_6 (
+	.A(N4BEG_i[6]),
+	.X(N4BEG[6])
+	);
+
+	my_buf N4BEG_outbuf_7 (
+	.A(N4BEG_i[7]),
+	.X(N4BEG[7])
+	);
+
+	my_buf N4BEG_outbuf_8 (
+	.A(N4BEG_i[8]),
+	.X(N4BEG[8])
+	);
+
+	my_buf N4BEG_outbuf_9 (
+	.A(N4BEG_i[9]),
+	.X(N4BEG[9])
+	);
+
+	my_buf N4BEG_outbuf_10 (
+	.A(N4BEG_i[10]),
+	.X(N4BEG[10])
+	);
+
+	my_buf N4BEG_outbuf_11 (
+	.A(N4BEG_i[11]),
+	.X(N4BEG[11])
+	);
+
+	wire [15:0] NN4END_i;
+	wire [11:0] NN4BEG_i;
+	assign NN4BEG_i[15-4:0] = NN4END_i[15:4];
+
+	my_buf NN4END_inbuf_0 (
+	.A(NN4END[4]),
+	.X(NN4END_i[4])
+	);
+
+	my_buf NN4END_inbuf_1 (
+	.A(NN4END[5]),
+	.X(NN4END_i[5])
+	);
+
+	my_buf NN4END_inbuf_2 (
+	.A(NN4END[6]),
+	.X(NN4END_i[6])
+	);
+
+	my_buf NN4END_inbuf_3 (
+	.A(NN4END[7]),
+	.X(NN4END_i[7])
+	);
+
+	my_buf NN4END_inbuf_4 (
+	.A(NN4END[8]),
+	.X(NN4END_i[8])
+	);
+
+	my_buf NN4END_inbuf_5 (
+	.A(NN4END[9]),
+	.X(NN4END_i[9])
+	);
+
+	my_buf NN4END_inbuf_6 (
+	.A(NN4END[10]),
+	.X(NN4END_i[10])
+	);
+
+	my_buf NN4END_inbuf_7 (
+	.A(NN4END[11]),
+	.X(NN4END_i[11])
+	);
+
+	my_buf NN4END_inbuf_8 (
+	.A(NN4END[12]),
+	.X(NN4END_i[12])
+	);
+
+	my_buf NN4END_inbuf_9 (
+	.A(NN4END[13]),
+	.X(NN4END_i[13])
+	);
+
+	my_buf NN4END_inbuf_10 (
+	.A(NN4END[14]),
+	.X(NN4END_i[14])
+	);
+
+	my_buf NN4END_inbuf_11 (
+	.A(NN4END[15]),
+	.X(NN4END_i[15])
+	);
+
+	my_buf NN4BEG_outbuf_0 (
+	.A(NN4BEG_i[0]),
+	.X(NN4BEG[0])
+	);
+
+	my_buf NN4BEG_outbuf_1 (
+	.A(NN4BEG_i[1]),
+	.X(NN4BEG[1])
+	);
+
+	my_buf NN4BEG_outbuf_2 (
+	.A(NN4BEG_i[2]),
+	.X(NN4BEG[2])
+	);
+
+	my_buf NN4BEG_outbuf_3 (
+	.A(NN4BEG_i[3]),
+	.X(NN4BEG[3])
+	);
+
+	my_buf NN4BEG_outbuf_4 (
+	.A(NN4BEG_i[4]),
+	.X(NN4BEG[4])
+	);
+
+	my_buf NN4BEG_outbuf_5 (
+	.A(NN4BEG_i[5]),
+	.X(NN4BEG[5])
+	);
+
+	my_buf NN4BEG_outbuf_6 (
+	.A(NN4BEG_i[6]),
+	.X(NN4BEG[6])
+	);
+
+	my_buf NN4BEG_outbuf_7 (
+	.A(NN4BEG_i[7]),
+	.X(NN4BEG[7])
+	);
+
+	my_buf NN4BEG_outbuf_8 (
+	.A(NN4BEG_i[8]),
+	.X(NN4BEG[8])
+	);
+
+	my_buf NN4BEG_outbuf_9 (
+	.A(NN4BEG_i[9]),
+	.X(NN4BEG[9])
+	);
+
+	my_buf NN4BEG_outbuf_10 (
+	.A(NN4BEG_i[10]),
+	.X(NN4BEG[10])
+	);
+
+	my_buf NN4BEG_outbuf_11 (
+	.A(NN4BEG_i[11]),
+	.X(NN4BEG[11])
+	);
+
+	wire [15:0] EE4END_i;
+	wire [11:0] EE4BEG_i;
+	assign EE4BEG_i[15-4:0] = EE4END_i[15:4];
+
+	my_buf EE4END_inbuf_0 (
+	.A(EE4END[4]),
+	.X(EE4END_i[4])
+	);
+
+	my_buf EE4END_inbuf_1 (
+	.A(EE4END[5]),
+	.X(EE4END_i[5])
+	);
+
+	my_buf EE4END_inbuf_2 (
+	.A(EE4END[6]),
+	.X(EE4END_i[6])
+	);
+
+	my_buf EE4END_inbuf_3 (
+	.A(EE4END[7]),
+	.X(EE4END_i[7])
+	);
+
+	my_buf EE4END_inbuf_4 (
+	.A(EE4END[8]),
+	.X(EE4END_i[8])
+	);
+
+	my_buf EE4END_inbuf_5 (
+	.A(EE4END[9]),
+	.X(EE4END_i[9])
+	);
+
+	my_buf EE4END_inbuf_6 (
+	.A(EE4END[10]),
+	.X(EE4END_i[10])
+	);
+
+	my_buf EE4END_inbuf_7 (
+	.A(EE4END[11]),
+	.X(EE4END_i[11])
+	);
+
+	my_buf EE4END_inbuf_8 (
+	.A(EE4END[12]),
+	.X(EE4END_i[12])
+	);
+
+	my_buf EE4END_inbuf_9 (
+	.A(EE4END[13]),
+	.X(EE4END_i[13])
+	);
+
+	my_buf EE4END_inbuf_10 (
+	.A(EE4END[14]),
+	.X(EE4END_i[14])
+	);
+
+	my_buf EE4END_inbuf_11 (
+	.A(EE4END[15]),
+	.X(EE4END_i[15])
+	);
+
+	my_buf EE4BEG_outbuf_0 (
+	.A(EE4BEG_i[0]),
+	.X(EE4BEG[0])
+	);
+
+	my_buf EE4BEG_outbuf_1 (
+	.A(EE4BEG_i[1]),
+	.X(EE4BEG[1])
+	);
+
+	my_buf EE4BEG_outbuf_2 (
+	.A(EE4BEG_i[2]),
+	.X(EE4BEG[2])
+	);
+
+	my_buf EE4BEG_outbuf_3 (
+	.A(EE4BEG_i[3]),
+	.X(EE4BEG[3])
+	);
+
+	my_buf EE4BEG_outbuf_4 (
+	.A(EE4BEG_i[4]),
+	.X(EE4BEG[4])
+	);
+
+	my_buf EE4BEG_outbuf_5 (
+	.A(EE4BEG_i[5]),
+	.X(EE4BEG[5])
+	);
+
+	my_buf EE4BEG_outbuf_6 (
+	.A(EE4BEG_i[6]),
+	.X(EE4BEG[6])
+	);
+
+	my_buf EE4BEG_outbuf_7 (
+	.A(EE4BEG_i[7]),
+	.X(EE4BEG[7])
+	);
+
+	my_buf EE4BEG_outbuf_8 (
+	.A(EE4BEG_i[8]),
+	.X(EE4BEG[8])
+	);
+
+	my_buf EE4BEG_outbuf_9 (
+	.A(EE4BEG_i[9]),
+	.X(EE4BEG[9])
+	);
+
+	my_buf EE4BEG_outbuf_10 (
+	.A(EE4BEG_i[10]),
+	.X(EE4BEG[10])
+	);
+
+	my_buf EE4BEG_outbuf_11 (
+	.A(EE4BEG_i[11]),
+	.X(EE4BEG[11])
+	);
+
+	wire [11:0] E6END_i;
+	wire [9:0] E6BEG_i;
+	assign E6BEG_i[11-2:0] = E6END_i[11:2];
+
+	my_buf E6END_inbuf_0 (
+	.A(E6END[2]),
+	.X(E6END_i[2])
+	);
+
+	my_buf E6END_inbuf_1 (
+	.A(E6END[3]),
+	.X(E6END_i[3])
+	);
+
+	my_buf E6END_inbuf_2 (
+	.A(E6END[4]),
+	.X(E6END_i[4])
+	);
+
+	my_buf E6END_inbuf_3 (
+	.A(E6END[5]),
+	.X(E6END_i[5])
+	);
+
+	my_buf E6END_inbuf_4 (
+	.A(E6END[6]),
+	.X(E6END_i[6])
+	);
+
+	my_buf E6END_inbuf_5 (
+	.A(E6END[7]),
+	.X(E6END_i[7])
+	);
+
+	my_buf E6END_inbuf_6 (
+	.A(E6END[8]),
+	.X(E6END_i[8])
+	);
+
+	my_buf E6END_inbuf_7 (
+	.A(E6END[9]),
+	.X(E6END_i[9])
+	);
+
+	my_buf E6END_inbuf_8 (
+	.A(E6END[10]),
+	.X(E6END_i[10])
+	);
+
+	my_buf E6END_inbuf_9 (
+	.A(E6END[11]),
+	.X(E6END_i[11])
+	);
+
+	my_buf E6BEG_outbuf_0 (
+	.A(E6BEG_i[0]),
+	.X(E6BEG[0])
+	);
+
+	my_buf E6BEG_outbuf_1 (
+	.A(E6BEG_i[1]),
+	.X(E6BEG[1])
+	);
+
+	my_buf E6BEG_outbuf_2 (
+	.A(E6BEG_i[2]),
+	.X(E6BEG[2])
+	);
+
+	my_buf E6BEG_outbuf_3 (
+	.A(E6BEG_i[3]),
+	.X(E6BEG[3])
+	);
+
+	my_buf E6BEG_outbuf_4 (
+	.A(E6BEG_i[4]),
+	.X(E6BEG[4])
+	);
+
+	my_buf E6BEG_outbuf_5 (
+	.A(E6BEG_i[5]),
+	.X(E6BEG[5])
+	);
+
+	my_buf E6BEG_outbuf_6 (
+	.A(E6BEG_i[6]),
+	.X(E6BEG[6])
+	);
+
+	my_buf E6BEG_outbuf_7 (
+	.A(E6BEG_i[7]),
+	.X(E6BEG[7])
+	);
+
+	my_buf E6BEG_outbuf_8 (
+	.A(E6BEG_i[8]),
+	.X(E6BEG[8])
+	);
+
+	my_buf E6BEG_outbuf_9 (
+	.A(E6BEG_i[9]),
+	.X(E6BEG[9])
+	);
+
+	wire [15:0] S4END_i;
+	wire [11:0] S4BEG_i;
+	assign S4BEG_i[15-4:0] = S4END_i[15:4];
+
+	my_buf S4END_inbuf_0 (
+	.A(S4END[4]),
+	.X(S4END_i[4])
+	);
+
+	my_buf S4END_inbuf_1 (
+	.A(S4END[5]),
+	.X(S4END_i[5])
+	);
+
+	my_buf S4END_inbuf_2 (
+	.A(S4END[6]),
+	.X(S4END_i[6])
+	);
+
+	my_buf S4END_inbuf_3 (
+	.A(S4END[7]),
+	.X(S4END_i[7])
+	);
+
+	my_buf S4END_inbuf_4 (
+	.A(S4END[8]),
+	.X(S4END_i[8])
+	);
+
+	my_buf S4END_inbuf_5 (
+	.A(S4END[9]),
+	.X(S4END_i[9])
+	);
+
+	my_buf S4END_inbuf_6 (
+	.A(S4END[10]),
+	.X(S4END_i[10])
+	);
+
+	my_buf S4END_inbuf_7 (
+	.A(S4END[11]),
+	.X(S4END_i[11])
+	);
+
+	my_buf S4END_inbuf_8 (
+	.A(S4END[12]),
+	.X(S4END_i[12])
+	);
+
+	my_buf S4END_inbuf_9 (
+	.A(S4END[13]),
+	.X(S4END_i[13])
+	);
+
+	my_buf S4END_inbuf_10 (
+	.A(S4END[14]),
+	.X(S4END_i[14])
+	);
+
+	my_buf S4END_inbuf_11 (
+	.A(S4END[15]),
+	.X(S4END_i[15])
+	);
+
+	my_buf S4BEG_outbuf_0 (
+	.A(S4BEG_i[0]),
+	.X(S4BEG[0])
+	);
+
+	my_buf S4BEG_outbuf_1 (
+	.A(S4BEG_i[1]),
+	.X(S4BEG[1])
+	);
+
+	my_buf S4BEG_outbuf_2 (
+	.A(S4BEG_i[2]),
+	.X(S4BEG[2])
+	);
+
+	my_buf S4BEG_outbuf_3 (
+	.A(S4BEG_i[3]),
+	.X(S4BEG[3])
+	);
+
+	my_buf S4BEG_outbuf_4 (
+	.A(S4BEG_i[4]),
+	.X(S4BEG[4])
+	);
+
+	my_buf S4BEG_outbuf_5 (
+	.A(S4BEG_i[5]),
+	.X(S4BEG[5])
+	);
+
+	my_buf S4BEG_outbuf_6 (
+	.A(S4BEG_i[6]),
+	.X(S4BEG[6])
+	);
+
+	my_buf S4BEG_outbuf_7 (
+	.A(S4BEG_i[7]),
+	.X(S4BEG[7])
+	);
+
+	my_buf S4BEG_outbuf_8 (
+	.A(S4BEG_i[8]),
+	.X(S4BEG[8])
+	);
+
+	my_buf S4BEG_outbuf_9 (
+	.A(S4BEG_i[9]),
+	.X(S4BEG[9])
+	);
+
+	my_buf S4BEG_outbuf_10 (
+	.A(S4BEG_i[10]),
+	.X(S4BEG[10])
+	);
+
+	my_buf S4BEG_outbuf_11 (
+	.A(S4BEG_i[11]),
+	.X(S4BEG[11])
+	);
+
+	wire [15:0] SS4END_i;
+	wire [11:0] SS4BEG_i;
+	assign SS4BEG_i[15-4:0] = SS4END_i[15:4];
+
+	my_buf SS4END_inbuf_0 (
+	.A(SS4END[4]),
+	.X(SS4END_i[4])
+	);
+
+	my_buf SS4END_inbuf_1 (
+	.A(SS4END[5]),
+	.X(SS4END_i[5])
+	);
+
+	my_buf SS4END_inbuf_2 (
+	.A(SS4END[6]),
+	.X(SS4END_i[6])
+	);
+
+	my_buf SS4END_inbuf_3 (
+	.A(SS4END[7]),
+	.X(SS4END_i[7])
+	);
+
+	my_buf SS4END_inbuf_4 (
+	.A(SS4END[8]),
+	.X(SS4END_i[8])
+	);
+
+	my_buf SS4END_inbuf_5 (
+	.A(SS4END[9]),
+	.X(SS4END_i[9])
+	);
+
+	my_buf SS4END_inbuf_6 (
+	.A(SS4END[10]),
+	.X(SS4END_i[10])
+	);
+
+	my_buf SS4END_inbuf_7 (
+	.A(SS4END[11]),
+	.X(SS4END_i[11])
+	);
+
+	my_buf SS4END_inbuf_8 (
+	.A(SS4END[12]),
+	.X(SS4END_i[12])
+	);
+
+	my_buf SS4END_inbuf_9 (
+	.A(SS4END[13]),
+	.X(SS4END_i[13])
+	);
+
+	my_buf SS4END_inbuf_10 (
+	.A(SS4END[14]),
+	.X(SS4END_i[14])
+	);
+
+	my_buf SS4END_inbuf_11 (
+	.A(SS4END[15]),
+	.X(SS4END_i[15])
+	);
+
+	my_buf SS4BEG_outbuf_0 (
+	.A(SS4BEG_i[0]),
+	.X(SS4BEG[0])
+	);
+
+	my_buf SS4BEG_outbuf_1 (
+	.A(SS4BEG_i[1]),
+	.X(SS4BEG[1])
+	);
+
+	my_buf SS4BEG_outbuf_2 (
+	.A(SS4BEG_i[2]),
+	.X(SS4BEG[2])
+	);
+
+	my_buf SS4BEG_outbuf_3 (
+	.A(SS4BEG_i[3]),
+	.X(SS4BEG[3])
+	);
+
+	my_buf SS4BEG_outbuf_4 (
+	.A(SS4BEG_i[4]),
+	.X(SS4BEG[4])
+	);
+
+	my_buf SS4BEG_outbuf_5 (
+	.A(SS4BEG_i[5]),
+	.X(SS4BEG[5])
+	);
+
+	my_buf SS4BEG_outbuf_6 (
+	.A(SS4BEG_i[6]),
+	.X(SS4BEG[6])
+	);
+
+	my_buf SS4BEG_outbuf_7 (
+	.A(SS4BEG_i[7]),
+	.X(SS4BEG[7])
+	);
+
+	my_buf SS4BEG_outbuf_8 (
+	.A(SS4BEG_i[8]),
+	.X(SS4BEG[8])
+	);
+
+	my_buf SS4BEG_outbuf_9 (
+	.A(SS4BEG_i[9]),
+	.X(SS4BEG[9])
+	);
+
+	my_buf SS4BEG_outbuf_10 (
+	.A(SS4BEG_i[10]),
+	.X(SS4BEG[10])
+	);
+
+	my_buf SS4BEG_outbuf_11 (
+	.A(SS4BEG_i[11]),
+	.X(SS4BEG[11])
+	);
+
+	wire [15:0] WW4END_i;
+	wire [11:0] WW4BEG_i;
+	assign WW4BEG_i[15-4:0] = WW4END_i[15:4];
+
+	my_buf WW4END_inbuf_0 (
+	.A(WW4END[4]),
+	.X(WW4END_i[4])
+	);
+
+	my_buf WW4END_inbuf_1 (
+	.A(WW4END[5]),
+	.X(WW4END_i[5])
+	);
+
+	my_buf WW4END_inbuf_2 (
+	.A(WW4END[6]),
+	.X(WW4END_i[6])
+	);
+
+	my_buf WW4END_inbuf_3 (
+	.A(WW4END[7]),
+	.X(WW4END_i[7])
+	);
+
+	my_buf WW4END_inbuf_4 (
+	.A(WW4END[8]),
+	.X(WW4END_i[8])
+	);
+
+	my_buf WW4END_inbuf_5 (
+	.A(WW4END[9]),
+	.X(WW4END_i[9])
+	);
+
+	my_buf WW4END_inbuf_6 (
+	.A(WW4END[10]),
+	.X(WW4END_i[10])
+	);
+
+	my_buf WW4END_inbuf_7 (
+	.A(WW4END[11]),
+	.X(WW4END_i[11])
+	);
+
+	my_buf WW4END_inbuf_8 (
+	.A(WW4END[12]),
+	.X(WW4END_i[12])
+	);
+
+	my_buf WW4END_inbuf_9 (
+	.A(WW4END[13]),
+	.X(WW4END_i[13])
+	);
+
+	my_buf WW4END_inbuf_10 (
+	.A(WW4END[14]),
+	.X(WW4END_i[14])
+	);
+
+	my_buf WW4END_inbuf_11 (
+	.A(WW4END[15]),
+	.X(WW4END_i[15])
+	);
+
+	my_buf WW4BEG_outbuf_0 (
+	.A(WW4BEG_i[0]),
+	.X(WW4BEG[0])
+	);
+
+	my_buf WW4BEG_outbuf_1 (
+	.A(WW4BEG_i[1]),
+	.X(WW4BEG[1])
+	);
+
+	my_buf WW4BEG_outbuf_2 (
+	.A(WW4BEG_i[2]),
+	.X(WW4BEG[2])
+	);
+
+	my_buf WW4BEG_outbuf_3 (
+	.A(WW4BEG_i[3]),
+	.X(WW4BEG[3])
+	);
+
+	my_buf WW4BEG_outbuf_4 (
+	.A(WW4BEG_i[4]),
+	.X(WW4BEG[4])
+	);
+
+	my_buf WW4BEG_outbuf_5 (
+	.A(WW4BEG_i[5]),
+	.X(WW4BEG[5])
+	);
+
+	my_buf WW4BEG_outbuf_6 (
+	.A(WW4BEG_i[6]),
+	.X(WW4BEG[6])
+	);
+
+	my_buf WW4BEG_outbuf_7 (
+	.A(WW4BEG_i[7]),
+	.X(WW4BEG[7])
+	);
+
+	my_buf WW4BEG_outbuf_8 (
+	.A(WW4BEG_i[8]),
+	.X(WW4BEG[8])
+	);
+
+	my_buf WW4BEG_outbuf_9 (
+	.A(WW4BEG_i[9]),
+	.X(WW4BEG[9])
+	);
+
+	my_buf WW4BEG_outbuf_10 (
+	.A(WW4BEG_i[10]),
+	.X(WW4BEG[10])
+	);
+
+	my_buf WW4BEG_outbuf_11 (
+	.A(WW4BEG_i[11]),
+	.X(WW4BEG[11])
+	);
+
+	wire [11:0] W6END_i;
+	wire [9:0] W6BEG_i;
+	assign W6BEG_i[11-2:0] = W6END_i[11:2];
+
+	my_buf W6END_inbuf_0 (
+	.A(W6END[2]),
+	.X(W6END_i[2])
+	);
+
+	my_buf W6END_inbuf_1 (
+	.A(W6END[3]),
+	.X(W6END_i[3])
+	);
+
+	my_buf W6END_inbuf_2 (
+	.A(W6END[4]),
+	.X(W6END_i[4])
+	);
+
+	my_buf W6END_inbuf_3 (
+	.A(W6END[5]),
+	.X(W6END_i[5])
+	);
+
+	my_buf W6END_inbuf_4 (
+	.A(W6END[6]),
+	.X(W6END_i[6])
+	);
+
+	my_buf W6END_inbuf_5 (
+	.A(W6END[7]),
+	.X(W6END_i[7])
+	);
+
+	my_buf W6END_inbuf_6 (
+	.A(W6END[8]),
+	.X(W6END_i[8])
+	);
+
+	my_buf W6END_inbuf_7 (
+	.A(W6END[9]),
+	.X(W6END_i[9])
+	);
+
+	my_buf W6END_inbuf_8 (
+	.A(W6END[10]),
+	.X(W6END_i[10])
+	);
+
+	my_buf W6END_inbuf_9 (
+	.A(W6END[11]),
+	.X(W6END_i[11])
+	);
+
+	my_buf W6BEG_outbuf_0 (
+	.A(W6BEG_i[0]),
+	.X(W6BEG[0])
+	);
+
+	my_buf W6BEG_outbuf_1 (
+	.A(W6BEG_i[1]),
+	.X(W6BEG[1])
+	);
+
+	my_buf W6BEG_outbuf_2 (
+	.A(W6BEG_i[2]),
+	.X(W6BEG[2])
+	);
+
+	my_buf W6BEG_outbuf_3 (
+	.A(W6BEG_i[3]),
+	.X(W6BEG[3])
+	);
+
+	my_buf W6BEG_outbuf_4 (
+	.A(W6BEG_i[4]),
+	.X(W6BEG[4])
+	);
+
+	my_buf W6BEG_outbuf_5 (
+	.A(W6BEG_i[5]),
+	.X(W6BEG[5])
+	);
+
+	my_buf W6BEG_outbuf_6 (
+	.A(W6BEG_i[6]),
+	.X(W6BEG[6])
+	);
+
+	my_buf W6BEG_outbuf_7 (
+	.A(W6BEG_i[7]),
+	.X(W6BEG[7])
+	);
+
+	my_buf W6BEG_outbuf_8 (
+	.A(W6BEG_i[8]),
+	.X(W6BEG[8])
+	);
+
+	my_buf W6BEG_outbuf_9 (
+	.A(W6BEG_i[9]),
+	.X(W6BEG[9])
+	);
+
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	LUT4AB_ConfigMem Inst_LUT4AB_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	LUT4c_frame_config Inst_LA_LUT4c_frame_config (
+	.I0(LA_I0),
+	.I1(LA_I1),
+	.I2(LA_I2),
+	.I3(LA_I3),
+	.Ci(LA_Ci),
+	.SR(LA_SR),
+	.EN(LA_EN),
+	.O(LA_O),
+	.Co(LA_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[19-1:0])
+	);
+
+	LUT4c_frame_config Inst_LB_LUT4c_frame_config (
+	.I0(LB_I0),
+	.I1(LB_I1),
+	.I2(LB_I2),
+	.I3(LB_I3),
+	.Ci(LB_Ci),
+	.SR(LB_SR),
+	.EN(LB_EN),
+	.O(LB_O),
+	.Co(LB_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[38-1:19])
+	);
+
+	LUT4c_frame_config Inst_LC_LUT4c_frame_config (
+	.I0(LC_I0),
+	.I1(LC_I1),
+	.I2(LC_I2),
+	.I3(LC_I3),
+	.Ci(LC_Ci),
+	.SR(LC_SR),
+	.EN(LC_EN),
+	.O(LC_O),
+	.Co(LC_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[57-1:38])
+	);
+
+	LUT4c_frame_config Inst_LD_LUT4c_frame_config (
+	.I0(LD_I0),
+	.I1(LD_I1),
+	.I2(LD_I2),
+	.I3(LD_I3),
+	.Ci(LD_Ci),
+	.SR(LD_SR),
+	.EN(LD_EN),
+	.O(LD_O),
+	.Co(LD_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[76-1:57])
+	);
+
+	LUT4c_frame_config Inst_LE_LUT4c_frame_config (
+	.I0(LE_I0),
+	.I1(LE_I1),
+	.I2(LE_I2),
+	.I3(LE_I3),
+	.Ci(LE_Ci),
+	.SR(LE_SR),
+	.EN(LE_EN),
+	.O(LE_O),
+	.Co(LE_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[95-1:76])
+	);
+
+	LUT4c_frame_config Inst_LF_LUT4c_frame_config (
+	.I0(LF_I0),
+	.I1(LF_I1),
+	.I2(LF_I2),
+	.I3(LF_I3),
+	.Ci(LF_Ci),
+	.SR(LF_SR),
+	.EN(LF_EN),
+	.O(LF_O),
+	.Co(LF_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[114-1:95])
+	);
+
+	LUT4c_frame_config Inst_LG_LUT4c_frame_config (
+	.I0(LG_I0),
+	.I1(LG_I1),
+	.I2(LG_I2),
+	.I3(LG_I3),
+	.Ci(LG_Ci),
+	.SR(LG_SR),
+	.EN(LG_EN),
+	.O(LG_O),
+	.Co(LG_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[133-1:114])
+	);
+
+	LUT4c_frame_config Inst_LH_LUT4c_frame_config (
+	.I0(LH_I0),
+	.I1(LH_I1),
+	.I2(LH_I2),
+	.I3(LH_I3),
+	.Ci(LH_Ci),
+	.SR(LH_SR),
+	.EN(LH_EN),
+	.O(LH_O),
+	.Co(LH_Co),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[152-1:133])
+	);
+
+	MUX8LUT_frame_config Inst_MUX8LUT_frame_config (
+	.A(A),
+	.B(B),
+	.C(C),
+	.D(D),
+	.E(E),
+	.F(F),
+	.G(G),
+	.H(H),
+	.S0(S0),
+	.S1(S1),
+	.S2(S2),
+	.S3(S3),
+	.M_AB(M_AB),
+	.M_AD(M_AD),
+	.M_AH(M_AH),
+	.M_EF(M_EF),
+	.ConfigBits(ConfigBits[154-1:152])
+	);
+
+
+//switch matrix component instantiation
+	LUT4AB_switch_matrix Inst_LUT4AB_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.Ci0(Ci[0]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.LA_O(LA_O),
+	.LA_Co(LA_Co),
+	.LB_O(LB_O),
+	.LB_Co(LB_Co),
+	.LC_O(LC_O),
+	.LC_Co(LC_Co),
+	.LD_O(LD_O),
+	.LD_Co(LD_Co),
+	.LE_O(LE_O),
+	.LE_Co(LE_Co),
+	.LF_O(LF_O),
+	.LF_Co(LF_Co),
+	.LG_O(LG_O),
+	.LG_Co(LG_Co),
+	.LH_O(LH_O),
+	.LH_Co(LH_Co),
+	.M_AB(M_AB),
+	.M_AD(M_AD),
+	.M_AH(M_AH),
+	.M_EF(M_EF),
+	.J2MID_ABa_END0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_END1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_END2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_END3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_END0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_END1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_END2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_END3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_END0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_END1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_END2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_END3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_END0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_END1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_END2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_END3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_END0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_END1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_END2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_END3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_END0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_END1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_END2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_END3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_END0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_END1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_END2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_END3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_END0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_END1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_END2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_END3(J2MID_GHb_BEG[3]),
+	.J2END_AB_END0(J2END_AB_BEG[0]),
+	.J2END_AB_END1(J2END_AB_BEG[1]),
+	.J2END_AB_END2(J2END_AB_BEG[2]),
+	.J2END_AB_END3(J2END_AB_BEG[3]),
+	.J2END_CD_END0(J2END_CD_BEG[0]),
+	.J2END_CD_END1(J2END_CD_BEG[1]),
+	.J2END_CD_END2(J2END_CD_BEG[2]),
+	.J2END_CD_END3(J2END_CD_BEG[3]),
+	.J2END_EF_END0(J2END_EF_BEG[0]),
+	.J2END_EF_END1(J2END_EF_BEG[1]),
+	.J2END_EF_END2(J2END_EF_BEG[2]),
+	.J2END_EF_END3(J2END_EF_BEG[3]),
+	.J2END_GH_END0(J2END_GH_BEG[0]),
+	.J2END_GH_END1(J2END_GH_BEG[1]),
+	.J2END_GH_END2(J2END_GH_BEG[2]),
+	.J2END_GH_END3(J2END_GH_BEG[3]),
+	.JN2END0(JN2BEG[0]),
+	.JN2END1(JN2BEG[1]),
+	.JN2END2(JN2BEG[2]),
+	.JN2END3(JN2BEG[3]),
+	.JN2END4(JN2BEG[4]),
+	.JN2END5(JN2BEG[5]),
+	.JN2END6(JN2BEG[6]),
+	.JN2END7(JN2BEG[7]),
+	.JE2END0(JE2BEG[0]),
+	.JE2END1(JE2BEG[1]),
+	.JE2END2(JE2BEG[2]),
+	.JE2END3(JE2BEG[3]),
+	.JE2END4(JE2BEG[4]),
+	.JE2END5(JE2BEG[5]),
+	.JE2END6(JE2BEG[6]),
+	.JE2END7(JE2BEG[7]),
+	.JS2END0(JS2BEG[0]),
+	.JS2END1(JS2BEG[1]),
+	.JS2END2(JS2BEG[2]),
+	.JS2END3(JS2BEG[3]),
+	.JS2END4(JS2BEG[4]),
+	.JS2END5(JS2BEG[5]),
+	.JS2END6(JS2BEG[6]),
+	.JS2END7(JS2BEG[7]),
+	.JW2END0(JW2BEG[0]),
+	.JW2END1(JW2BEG[1]),
+	.JW2END2(JW2BEG[2]),
+	.JW2END3(JW2BEG[3]),
+	.JW2END4(JW2BEG[4]),
+	.JW2END5(JW2BEG[5]),
+	.JW2END6(JW2BEG[6]),
+	.JW2END7(JW2BEG[7]),
+	.J_l_AB_END0(J_l_AB_BEG[0]),
+	.J_l_AB_END1(J_l_AB_BEG[1]),
+	.J_l_AB_END2(J_l_AB_BEG[2]),
+	.J_l_AB_END3(J_l_AB_BEG[3]),
+	.J_l_CD_END0(J_l_CD_BEG[0]),
+	.J_l_CD_END1(J_l_CD_BEG[1]),
+	.J_l_CD_END2(J_l_CD_BEG[2]),
+	.J_l_CD_END3(J_l_CD_BEG[3]),
+	.J_l_EF_END0(J_l_EF_BEG[0]),
+	.J_l_EF_END1(J_l_EF_BEG[1]),
+	.J_l_EF_END2(J_l_EF_BEG[2]),
+	.J_l_EF_END3(J_l_EF_BEG[3]),
+	.J_l_GH_END0(J_l_GH_BEG[0]),
+	.J_l_GH_END1(J_l_GH_BEG[1]),
+	.J_l_GH_END2(J_l_GH_BEG[2]),
+	.J_l_GH_END3(J_l_GH_BEG[3]),
+	.J_SR_END0(J_SR_BEG[0]),
+	.J_EN_END0(J_EN_BEG[0]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[12]),
+	.N4BEG1(N4BEG[13]),
+	.N4BEG2(N4BEG[14]),
+	.N4BEG3(N4BEG[15]),
+	.NN4BEG0(NN4BEG[12]),
+	.NN4BEG1(NN4BEG[13]),
+	.NN4BEG2(NN4BEG[14]),
+	.NN4BEG3(NN4BEG[15]),
+	.Co0(Co[0]),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[12]),
+	.EE4BEG1(EE4BEG[13]),
+	.EE4BEG2(EE4BEG[14]),
+	.EE4BEG3(EE4BEG[15]),
+	.E6BEG0(E6BEG[10]),
+	.E6BEG1(E6BEG[11]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[12]),
+	.S4BEG1(S4BEG[13]),
+	.S4BEG2(S4BEG[14]),
+	.S4BEG3(S4BEG[15]),
+	.SS4BEG0(SS4BEG[12]),
+	.SS4BEG1(SS4BEG[13]),
+	.SS4BEG2(SS4BEG[14]),
+	.SS4BEG3(SS4BEG[15]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[12]),
+	.WW4BEG1(WW4BEG[13]),
+	.WW4BEG2(WW4BEG[14]),
+	.WW4BEG3(WW4BEG[15]),
+	.W6BEG0(W6BEG[10]),
+	.W6BEG1(W6BEG[11]),
+	.LA_I0(LA_I0),
+	.LA_I1(LA_I1),
+	.LA_I2(LA_I2),
+	.LA_I3(LA_I3),
+	.LA_Ci(LA_Ci),
+	.LA_SR(LA_SR),
+	.LA_EN(LA_EN),
+	.LB_I0(LB_I0),
+	.LB_I1(LB_I1),
+	.LB_I2(LB_I2),
+	.LB_I3(LB_I3),
+	.LB_Ci(LB_Ci),
+	.LB_SR(LB_SR),
+	.LB_EN(LB_EN),
+	.LC_I0(LC_I0),
+	.LC_I1(LC_I1),
+	.LC_I2(LC_I2),
+	.LC_I3(LC_I3),
+	.LC_Ci(LC_Ci),
+	.LC_SR(LC_SR),
+	.LC_EN(LC_EN),
+	.LD_I0(LD_I0),
+	.LD_I1(LD_I1),
+	.LD_I2(LD_I2),
+	.LD_I3(LD_I3),
+	.LD_Ci(LD_Ci),
+	.LD_SR(LD_SR),
+	.LD_EN(LD_EN),
+	.LE_I0(LE_I0),
+	.LE_I1(LE_I1),
+	.LE_I2(LE_I2),
+	.LE_I3(LE_I3),
+	.LE_Ci(LE_Ci),
+	.LE_SR(LE_SR),
+	.LE_EN(LE_EN),
+	.LF_I0(LF_I0),
+	.LF_I1(LF_I1),
+	.LF_I2(LF_I2),
+	.LF_I3(LF_I3),
+	.LF_Ci(LF_Ci),
+	.LF_SR(LF_SR),
+	.LF_EN(LF_EN),
+	.LG_I0(LG_I0),
+	.LG_I1(LG_I1),
+	.LG_I2(LG_I2),
+	.LG_I3(LG_I3),
+	.LG_Ci(LG_Ci),
+	.LG_SR(LG_SR),
+	.LG_EN(LG_EN),
+	.LH_I0(LH_I0),
+	.LH_I1(LH_I1),
+	.LH_I2(LH_I2),
+	.LH_I3(LH_I3),
+	.LH_Ci(LH_Ci),
+	.LH_SR(LH_SR),
+	.LH_EN(LH_EN),
+	.A(A),
+	.B(B),
+	.C(C),
+	.D(D),
+	.E(E),
+	.F(F),
+	.G(G),
+	.H(H),
+	.S0(S0),
+	.S1(S1),
+	.S2(S2),
+	.S3(S3),
+	.J2MID_ABa_BEG0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_BEG1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_BEG2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_BEG3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_BEG0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_BEG1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_BEG2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_BEG3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_BEG0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_BEG1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_BEG2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_BEG3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_BEG0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_BEG1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_BEG2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_BEG3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_BEG0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_BEG1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_BEG2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_BEG3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_BEG0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_BEG1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_BEG2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_BEG3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_BEG0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_BEG1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_BEG2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_BEG3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_BEG0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_BEG1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_BEG2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_BEG3(J2MID_GHb_BEG[3]),
+	.J2END_AB_BEG0(J2END_AB_BEG[0]),
+	.J2END_AB_BEG1(J2END_AB_BEG[1]),
+	.J2END_AB_BEG2(J2END_AB_BEG[2]),
+	.J2END_AB_BEG3(J2END_AB_BEG[3]),
+	.J2END_CD_BEG0(J2END_CD_BEG[0]),
+	.J2END_CD_BEG1(J2END_CD_BEG[1]),
+	.J2END_CD_BEG2(J2END_CD_BEG[2]),
+	.J2END_CD_BEG3(J2END_CD_BEG[3]),
+	.J2END_EF_BEG0(J2END_EF_BEG[0]),
+	.J2END_EF_BEG1(J2END_EF_BEG[1]),
+	.J2END_EF_BEG2(J2END_EF_BEG[2]),
+	.J2END_EF_BEG3(J2END_EF_BEG[3]),
+	.J2END_GH_BEG0(J2END_GH_BEG[0]),
+	.J2END_GH_BEG1(J2END_GH_BEG[1]),
+	.J2END_GH_BEG2(J2END_GH_BEG[2]),
+	.J2END_GH_BEG3(J2END_GH_BEG[3]),
+	.JN2BEG0(JN2BEG[0]),
+	.JN2BEG1(JN2BEG[1]),
+	.JN2BEG2(JN2BEG[2]),
+	.JN2BEG3(JN2BEG[3]),
+	.JN2BEG4(JN2BEG[4]),
+	.JN2BEG5(JN2BEG[5]),
+	.JN2BEG6(JN2BEG[6]),
+	.JN2BEG7(JN2BEG[7]),
+	.JE2BEG0(JE2BEG[0]),
+	.JE2BEG1(JE2BEG[1]),
+	.JE2BEG2(JE2BEG[2]),
+	.JE2BEG3(JE2BEG[3]),
+	.JE2BEG4(JE2BEG[4]),
+	.JE2BEG5(JE2BEG[5]),
+	.JE2BEG6(JE2BEG[6]),
+	.JE2BEG7(JE2BEG[7]),
+	.JS2BEG0(JS2BEG[0]),
+	.JS2BEG1(JS2BEG[1]),
+	.JS2BEG2(JS2BEG[2]),
+	.JS2BEG3(JS2BEG[3]),
+	.JS2BEG4(JS2BEG[4]),
+	.JS2BEG5(JS2BEG[5]),
+	.JS2BEG6(JS2BEG[6]),
+	.JS2BEG7(JS2BEG[7]),
+	.JW2BEG0(JW2BEG[0]),
+	.JW2BEG1(JW2BEG[1]),
+	.JW2BEG2(JW2BEG[2]),
+	.JW2BEG3(JW2BEG[3]),
+	.JW2BEG4(JW2BEG[4]),
+	.JW2BEG5(JW2BEG[5]),
+	.JW2BEG6(JW2BEG[6]),
+	.JW2BEG7(JW2BEG[7]),
+	.J_l_AB_BEG0(J_l_AB_BEG[0]),
+	.J_l_AB_BEG1(J_l_AB_BEG[1]),
+	.J_l_AB_BEG2(J_l_AB_BEG[2]),
+	.J_l_AB_BEG3(J_l_AB_BEG[3]),
+	.J_l_CD_BEG0(J_l_CD_BEG[0]),
+	.J_l_CD_BEG1(J_l_CD_BEG[1]),
+	.J_l_CD_BEG2(J_l_CD_BEG[2]),
+	.J_l_CD_BEG3(J_l_CD_BEG[3]),
+	.J_l_EF_BEG0(J_l_EF_BEG[0]),
+	.J_l_EF_BEG1(J_l_EF_BEG[1]),
+	.J_l_EF_BEG2(J_l_EF_BEG[2]),
+	.J_l_EF_BEG3(J_l_EF_BEG[3]),
+	.J_l_GH_BEG0(J_l_GH_BEG[0]),
+	.J_l_GH_BEG1(J_l_GH_BEG[1]),
+	.J_l_GH_BEG2(J_l_GH_BEG[2]),
+	.J_l_GH_BEG3(J_l_GH_BEG[3]),
+	.J_SR_BEG0(J_SR_BEG[0]),
+	.J_EN_BEG0(J_EN_BEG[0]),
+	.ConfigBits(ConfigBits[616-1:154]),
+	.ConfigBits_N(ConfigBits_N[616-1:154])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/LUT4c_frame_config_dffesr.v b/verilog/rtl/eFPGA_core/LUT4c_frame_config_dffesr.v
new file mode 100644
index 0000000..85c0bda
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/LUT4c_frame_config_dffesr.v
@@ -0,0 +1,147 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2021 University of Manchester
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//	  http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module LUT4c_frame_config (I0, I1, I2, I3, O, Ci, Co, SR, EN, UserCLK, ConfigBits);
+	parameter NoConfigBits = 19 ; // has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// IMPORTANT: this has to be in a dedicated line
+	input I0; // LUT inputs
+	input I1;
+	input I2;
+	input I3;
+	output O; // LUT output (combinatorial or FF)
+	input Ci; // carry chain input
+	output Co; // carry chain output
+	input SR; // SHARED_RESET
+	input EN; // SHARED_ENABLE
+	input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1 : 0] ConfigBits;
+
+	localparam LUT_SIZE = 4; 
+	localparam N_LUT_flops = 2 ** LUT_SIZE; 
+
+	wire [N_LUT_flops-1 : 0] LUT_values;
+	wire [LUT_SIZE-1 : 0] LUT_index;
+	wire LUT_out;
+	reg LUT_flop;
+	wire I0mux; // normal input '0', or carry input '1'
+	wire c_out_mux, c_I0mux, c_reset_value;	// extra configuration bits
+
+	assign LUT_values = ConfigBits[15:0];
+	assign c_out_mux  = ConfigBits[16];
+	assign c_I0mux = ConfigBits[17];
+	assign c_reset_value = ConfigBits[18];
+
+//CONFout <= c_I0mux;
+
+	//assign I0mux = c_I0mux ? Ci : I0;
+	my_mux2 my_mux2_I0mux(
+	.A0(I0),
+	.A1(Ci),
+	.S(c_I0mux),
+	.X(I0mux)
+	);
+
+	assign LUT_index = {I3,I2,I1,I0mux};
+
+// The LUT is just a multiplexer 
+// for a first shot, I am using a 16:1
+// LUT_out <= LUT_values(TO_INTEGER(LUT_index));
+	/*MUX16PTv2 inst_MUX16PTv2_E6BEG1(
+	.IN1(LUT_values[0]),
+	.IN2(LUT_values[1]),
+	.IN3(LUT_values[2]),
+	.IN4(LUT_values[3]),
+	.IN5(LUT_values[4]),
+	.IN6(LUT_values[5]),
+	.IN7(LUT_values[6]),
+	.IN8(LUT_values[7]),
+	.IN9(LUT_values[8]),
+	.IN10(LUT_values[9]),
+	.IN11(LUT_values[10]),
+	.IN12(LUT_values[11]),
+	.IN13(LUT_values[12]),
+	.IN14(LUT_values[13]),
+	.IN15(LUT_values[14]),
+	.IN16(LUT_values[15]),
+	.S1(LUT_index[0]),
+	.S2(LUT_index[1]),
+	.S3(LUT_index[2]),
+	.S4(LUT_index[3]),
+	.O(LUT_out)
+	);*/
+	cus_mux161_buf inst_cus_mux161_buf(
+	.A0(LUT_values[0]),
+	.A1(LUT_values[1]),
+	.A2(LUT_values[2]),
+	.A3(LUT_values[3]),
+	.A4(LUT_values[4]),
+	.A5(LUT_values[5]),
+	.A6(LUT_values[6]),
+	.A7(LUT_values[7]),
+	.A8(LUT_values[8]),
+	.A9(LUT_values[9]),
+	.A10(LUT_values[10]),
+	.A11(LUT_values[11]),
+	.A12(LUT_values[12]),
+	.A13(LUT_values[13]),
+	.A14(LUT_values[14]),
+	.A15(LUT_values[15]),
+	.S0 (LUT_index[0]),
+	.S0N(~LUT_index[0]),
+	.S1 (LUT_index[1]),
+	.S1N(~LUT_index[1]),
+	.S2 (LUT_index[2]),
+	.S2N(~LUT_index[2]),
+	.S3 (LUT_index[3]),
+	.S3N(~LUT_index[3]),
+	.X  (LUT_out)
+	);
+
+	//assign O = c_out_mux ? LUT_flop : LUT_out;
+	my_mux2 my_mux2_O(
+	.A0(LUT_out),
+	.A1(LUT_flop),
+	.S(c_out_mux),
+	.X(O)
+	);
+	
+	assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);// iCE40 like carry chain (as this is supported in Yosys; would normally go for fractured LUT
+
+	always @ (posedge UserCLK) begin
+		if (EN) begin
+			if (SR)
+				LUT_flop <= c_reset_value;
+			else
+				LUT_flop <= LUT_out;
+		end
+	end
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/MULADD.v b/verilog/rtl/eFPGA_core/MULADD.v
new file mode 100644
index 0000000..d04ac17
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/MULADD.v
@@ -0,0 +1,147 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, UserCLK, ConfigBits);
+	parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// IMPORTANT: this has to be in a dedicated line
+	input A7;// operand A
+	input A6;
+	input A5;
+	input A4;
+	input A3;
+	input A2;
+	input A1;
+	input A0;
+	input B7;// operand B
+	input B6;
+	input B5;
+	input B4;
+	input B3;
+	input B2;
+	input B1;
+	input B0;
+	input C19;// operand C
+	input C18;
+	input C17;
+	input C16;
+	input C15;
+	input C14;
+	input C13;
+	input C12;
+	input C11;
+	input C10;
+	input C9;
+	input C8;
+	input C7;
+	input C6;
+	input C5;
+	input C4;
+	input C3;
+	input C2;
+	input C1;
+	input C0;
+	output Q19;// result
+	output Q18;
+	output Q17;
+	output Q16;
+	output Q15;
+	output Q14;
+	output Q13;
+	output Q12;
+	output Q11;
+	output Q10;
+	output Q9;
+	output Q8;
+	output Q7;
+	output Q6;
+	output Q5;
+	output Q4;
+	output Q3;
+	output Q2;
+	output Q1;
+	output Q0;
+
+	input clr;
+	input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1:0] ConfigBits;
+
+	wire [7:0] A;		// port A read data 
+	wire [7:0] B;		// port B read data 
+	wire [19:0] C;		// port B read data 
+	reg [7:0] A_reg;		// port A read data register
+	reg [7:0] B_reg;		// port B read data register
+	reg [19:0] C_reg;		// port B read data register
+	wire [7:0] OPA;		// port A 
+	wire [7:0] OPB;		// port B 
+	wire [19:0] OPC;		// port B  
+	reg [19:0] ACC ;		// accumulator register
+	wire [19:0] sum;// port B read data register
+	wire [19:0] sum_in;// port B read data register
+	wire [15:0] product;
+	wire [19:0] product_extended;
+
+	assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
+	assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
+	assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};
+
+	assign OPA = ConfigBits[0] ? A_reg : A;
+	assign OPB = ConfigBits[1] ? B_reg : B;
+	assign OPC = ConfigBits[2] ? C_reg : C;
+
+	assign sum_in = ConfigBits[3] ? ACC : OPC;// we can
+
+	assign product = OPA * OPB;
+
+// The sign extension was not tested
+	assign product_extended = ConfigBits[4] ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product};
+
+	assign sum = product_extended + sum_in;
+
+	assign Q19	= ConfigBits[5] ? ACC[19] : sum[19];
+	assign Q18	= ConfigBits[5] ? ACC[18] : sum[18];
+	assign Q17	= ConfigBits[5] ? ACC[17] : sum[17];
+	assign Q16	= ConfigBits[5] ? ACC[16] : sum[16];
+	assign Q15	= ConfigBits[5] ? ACC[15] : sum[15];
+	assign Q14	= ConfigBits[5] ? ACC[14] : sum[14];
+	assign Q13	= ConfigBits[5] ? ACC[13] : sum[13];
+	assign Q12	= ConfigBits[5] ? ACC[12] : sum[12];
+	assign Q11	= ConfigBits[5] ? ACC[11] : sum[11];
+	assign Q10	= ConfigBits[5] ? ACC[10] : sum[10];
+	assign Q9	= ConfigBits[5] ? ACC[9] : sum[9];
+	assign Q8	= ConfigBits[5] ? ACC[8] : sum[8];
+	assign Q7	= ConfigBits[5] ? ACC[7] : sum[7];
+	assign Q6	= ConfigBits[5] ? ACC[6] : sum[6];
+	assign Q5	= ConfigBits[5] ? ACC[5] : sum[5];
+	assign Q4	= ConfigBits[5] ? ACC[4] : sum[4];
+	assign Q3	= ConfigBits[5] ? ACC[3] : sum[3];
+	assign Q2	= ConfigBits[5] ? ACC[2] : sum[2];
+	assign Q1	= ConfigBits[5] ? ACC[1] : sum[1];
+	assign Q0	= ConfigBits[5] ? ACC[0] : sum[0];
+
+	always @ (posedge UserCLK)
+	begin
+		A_reg <= A;
+		B_reg <= B;
+		C_reg <= C;
+		if (clr == 1'b1) begin
+			ACC <= 20'b00000000000000000000;
+		end else begin
+			ACC <= sum;
+		end
+	end
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/MUX8LUT_frame_config_mux.v b/verilog/rtl/eFPGA_core/MUX8LUT_frame_config_mux.v
new file mode 100644
index 0000000..05310ed
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/MUX8LUT_frame_config_mux.v
@@ -0,0 +1,156 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module MUX8LUT_frame_config (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M_AD, M_AH, M_EF, ConfigBits);
+	parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// IMPORTANT: this has to be in a dedicated line
+	input A; // MUX inputs
+	input B;
+	input C;
+	input D;
+	input E; 
+	input F;
+	input G;
+	input H;
+	input S0;
+	input S1;
+	input S2;
+	input S3;
+	output M_AB;
+	output M_AD;
+	output M_AH;
+	output M_EF;
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1:0] ConfigBits;
+
+	wire AB, CD, EF, GH;
+	wire sCD, sEF, sGH, sEH;
+	wire AD, EH, AH;
+	wire EH_GH;
+
+	wire c0, c1;// configuration bits
+
+	assign c0 = ConfigBits[0];
+	assign c1 = ConfigBits[1];
+
+// see figure (column-wise left-to-right)
+	//assign AB = S0 ? B : A;
+    my_mux2 my_mux2_AB(
+    .A0(A),
+    .A1(B),
+    .S(S0),
+    .X(AB)
+    );
+	//assign CD = sCD ? D : C;
+    my_mux2 my_mux2_CD(
+    .A0(C),
+    .A1(D),
+    .S(sCD),
+    .X(CD)
+    );
+	//assign EF = sEF ? F : E;
+    my_mux2 my_mux2_EF(
+    .A0(E),
+    .A1(F),
+    .S(sEF),
+    .X(EF)
+    );
+	//assign GH = sGH ? H : G;
+    my_mux2 my_mux2_GH(
+    .A0(G),
+    .A1(H),
+    .S(sGH),
+    .X(GH)
+    );
+
+	//assign sCD = c0 ? S0 : S1;
+    my_mux2 my_mux2_sCD(
+    .A0(S1),
+    .A1(S0),
+    .S(c0),
+    .X(sCD)
+    );
+	//assign sEF = c1 ? S0 : S2;
+    my_mux2 my_mux2_sEF(
+    .A0(S2),
+    .A1(S0),
+    .S(c1),
+    .X(sEF)
+    );
+	//assign sGH = c0 ? sEF : sEH;
+    my_mux2 my_mux2_sGH(
+    .A0(sEH),
+    .A1(sEF),
+    .S(c0),
+    .X(sGH)
+    );
+	//assign sEH = c1 ? S1 : S3;
+    my_mux2 my_mux2_sEH(
+    .A0(S3),
+    .A1(S1),
+    .S(c1),
+    .X(sEH)
+    );
+
+	//assign AD = S1 ? CD : AB;
+    my_mux2 my_mux2_AD(
+    .A0(AB),
+    .A1(CD),
+    .S(S1),
+    .X(AD)
+    );
+	//assign EH = sEH ? GH : EF;
+    my_mux2 my_mux2_EH(
+    .A0(EF),
+    .A1(GH),
+    .S(sEH),
+    .X(EH)
+    );
+
+	//assign AH = S3 ? EH : AD;
+    my_mux2 my_mux2_AH(
+    .A0(AD),
+    .A1(EH),
+    .S(S3),
+    .X(AH)
+    );
+
+	//assign EH_GH = c0 ? EH : GH;
+    my_mux2 my_mux2_EH_GH(
+    .A0(GH),
+    .A1(EH),
+    .S(c0),
+    .X(EH_GH)
+    );
+
+	assign M_AB = AB;
+	//assign M_AD = c0 ? AD : CD;
+    my_mux2 my_mux2_M_AD(
+    .A0(CD),
+    .A1(AD),
+    .S(c0),
+    .X(M_AD)
+    );
+	//assign M_AH = c1 ? AH : EH_GH;
+    my_mux2 my_mux2_M_AH(
+    .A0(EH_GH),
+    .A1(AH),
+    .S(c1),
+    .X(M_AH)
+    );
+	assign M_EF = EF;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_DSP_switch_matrix.v b/verilog/rtl/eFPGA_core/N_term_DSP_switch_matrix.v
new file mode 100644
index 0000000..191c608
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_DSP_switch_matrix.v
@@ -0,0 +1,297 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module N_term_DSP_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, NN4END0, NN4END1, NN4END2, NN4END3, NN4END4, NN4END5, NN4END6, NN4END7, NN4END8, NN4END9, NN4END10, NN4END11, NN4END12, NN4END13, NN4END14, NN4END15, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, SS4BEG4, SS4BEG5, SS4BEG6, SS4BEG7, SS4BEG8, SS4BEG9, SS4BEG10, SS4BEG11, SS4BEG12, SS4BEG13, SS4BEG14, SS4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input NN4END4;
+	input NN4END5;
+	input NN4END6;
+	input NN4END7;
+	input NN4END8;
+	input NN4END9;
+	input NN4END10;
+	input NN4END11;
+	input NN4END12;
+	input NN4END13;
+	input NN4END14;
+	input NN4END15;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output SS4BEG4;
+	output SS4BEG5;
+	output SS4BEG6;
+	output SS4BEG7;
+	output SS4BEG8;
+	output SS4BEG9;
+	output SS4BEG10;
+	output SS4BEG11;
+	output SS4BEG12;
+	output SS4BEG13;
+	output SS4BEG14;
+	output SS4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+	wire [1-1:0] SS4BEG0_input;
+	wire [1-1:0] SS4BEG1_input;
+	wire [1-1:0] SS4BEG2_input;
+	wire [1-1:0] SS4BEG3_input;
+	wire [1-1:0] SS4BEG4_input;
+	wire [1-1:0] SS4BEG5_input;
+	wire [1-1:0] SS4BEG6_input;
+	wire [1-1:0] SS4BEG7_input;
+	wire [1-1:0] SS4BEG8_input;
+	wire [1-1:0] SS4BEG9_input;
+	wire [1-1:0] SS4BEG10_input;
+	wire [1-1:0] SS4BEG11_input;
+	wire [1-1:0] SS4BEG12_input;
+	wire [1-1:0] SS4BEG13_input;
+	wire [1-1:0] SS4BEG14_input;
+	wire [1-1:0] SS4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+// switch matrix multiplexer  SS4BEG0 		MUX-1
+	assign SS4BEG0 = NN4END15;
+// switch matrix multiplexer  SS4BEG1 		MUX-1
+	assign SS4BEG1 = NN4END14;
+// switch matrix multiplexer  SS4BEG2 		MUX-1
+	assign SS4BEG2 = NN4END13;
+// switch matrix multiplexer  SS4BEG3 		MUX-1
+	assign SS4BEG3 = NN4END12;
+// switch matrix multiplexer  SS4BEG4 		MUX-1
+	assign SS4BEG4 = NN4END11;
+// switch matrix multiplexer  SS4BEG5 		MUX-1
+	assign SS4BEG5 = NN4END10;
+// switch matrix multiplexer  SS4BEG6 		MUX-1
+	assign SS4BEG6 = NN4END9;
+// switch matrix multiplexer  SS4BEG7 		MUX-1
+	assign SS4BEG7 = NN4END8;
+// switch matrix multiplexer  SS4BEG8 		MUX-1
+	assign SS4BEG8 = NN4END7;
+// switch matrix multiplexer  SS4BEG9 		MUX-1
+	assign SS4BEG9 = NN4END6;
+// switch matrix multiplexer  SS4BEG10 		MUX-1
+	assign SS4BEG10 = NN4END5;
+// switch matrix multiplexer  SS4BEG11 		MUX-1
+	assign SS4BEG11 = NN4END4;
+// switch matrix multiplexer  SS4BEG12 		MUX-1
+	assign SS4BEG12 = NN4END3;
+// switch matrix multiplexer  SS4BEG13 		MUX-1
+	assign SS4BEG13 = NN4END2;
+// switch matrix multiplexer  SS4BEG14 		MUX-1
+	assign SS4BEG14 = NN4END1;
+// switch matrix multiplexer  SS4BEG15 		MUX-1
+	assign SS4BEG15 = NN4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_DSP_tile.v b/verilog/rtl/eFPGA_core/N_term_DSP_tile.v
new file mode 100644
index 0000000..99063cb
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_DSP_tile.v
@@ -0,0 +1,362 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module N_term_DSP (N1END, N2MID, N2END, N4END, NN4END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:NN4END  
+	//  EAST
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:NULL  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	N_term_DSP_switch_matrix Inst_N_term_DSP_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.NN4END4(NN4END[4]),
+	.NN4END5(NN4END[5]),
+	.NN4END6(NN4END[6]),
+	.NN4END7(NN4END[7]),
+	.NN4END8(NN4END[8]),
+	.NN4END9(NN4END[9]),
+	.NN4END10(NN4END[10]),
+	.NN4END11(NN4END[11]),
+	.NN4END12(NN4END[12]),
+	.NN4END13(NN4END[13]),
+	.NN4END14(NN4END[14]),
+	.NN4END15(NN4END[15]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15]),
+	.SS4BEG0(SS4BEG[0]),
+	.SS4BEG1(SS4BEG[1]),
+	.SS4BEG2(SS4BEG[2]),
+	.SS4BEG3(SS4BEG[3]),
+	.SS4BEG4(SS4BEG[4]),
+	.SS4BEG5(SS4BEG[5]),
+	.SS4BEG6(SS4BEG[6]),
+	.SS4BEG7(SS4BEG[7]),
+	.SS4BEG8(SS4BEG[8]),
+	.SS4BEG9(SS4BEG[9]),
+	.SS4BEG10(SS4BEG[10]),
+	.SS4BEG11(SS4BEG[11]),
+	.SS4BEG12(SS4BEG[12]),
+	.SS4BEG13(SS4BEG[13]),
+	.SS4BEG14(SS4BEG[14]),
+	.SS4BEG15(SS4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_RAM_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/N_term_RAM_IO_switch_matrix.v
new file mode 100644
index 0000000..e32ce13
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_RAM_IO_switch_matrix.v
@@ -0,0 +1,217 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module N_term_RAM_IO_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_RAM_IO_tile.v b/verilog/rtl/eFPGA_core/N_term_RAM_IO_tile.v
new file mode 100644
index 0000000..37ce9ae
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_RAM_IO_tile.v
@@ -0,0 +1,328 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module N_term_RAM_IO (N1END, N2MID, N2END, N4END, S1BEG, S2BEG, S2BEGb, S4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	//  EAST
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	N_term_RAM_IO_switch_matrix Inst_N_term_RAM_IO_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_single2_switch_matrix.v b/verilog/rtl/eFPGA_core/N_term_single2_switch_matrix.v
new file mode 100644
index 0000000..25270db
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_single2_switch_matrix.v
@@ -0,0 +1,297 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module N_term_single2_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, NN4END0, NN4END1, NN4END2, NN4END3, NN4END4, NN4END5, NN4END6, NN4END7, NN4END8, NN4END9, NN4END10, NN4END11, NN4END12, NN4END13, NN4END14, NN4END15, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, SS4BEG4, SS4BEG5, SS4BEG6, SS4BEG7, SS4BEG8, SS4BEG9, SS4BEG10, SS4BEG11, SS4BEG12, SS4BEG13, SS4BEG14, SS4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input NN4END4;
+	input NN4END5;
+	input NN4END6;
+	input NN4END7;
+	input NN4END8;
+	input NN4END9;
+	input NN4END10;
+	input NN4END11;
+	input NN4END12;
+	input NN4END13;
+	input NN4END14;
+	input NN4END15;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output SS4BEG4;
+	output SS4BEG5;
+	output SS4BEG6;
+	output SS4BEG7;
+	output SS4BEG8;
+	output SS4BEG9;
+	output SS4BEG10;
+	output SS4BEG11;
+	output SS4BEG12;
+	output SS4BEG13;
+	output SS4BEG14;
+	output SS4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+	wire [1-1:0] SS4BEG0_input;
+	wire [1-1:0] SS4BEG1_input;
+	wire [1-1:0] SS4BEG2_input;
+	wire [1-1:0] SS4BEG3_input;
+	wire [1-1:0] SS4BEG4_input;
+	wire [1-1:0] SS4BEG5_input;
+	wire [1-1:0] SS4BEG6_input;
+	wire [1-1:0] SS4BEG7_input;
+	wire [1-1:0] SS4BEG8_input;
+	wire [1-1:0] SS4BEG9_input;
+	wire [1-1:0] SS4BEG10_input;
+	wire [1-1:0] SS4BEG11_input;
+	wire [1-1:0] SS4BEG12_input;
+	wire [1-1:0] SS4BEG13_input;
+	wire [1-1:0] SS4BEG14_input;
+	wire [1-1:0] SS4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+// switch matrix multiplexer  SS4BEG0 		MUX-1
+	assign SS4BEG0 = NN4END15;
+// switch matrix multiplexer  SS4BEG1 		MUX-1
+	assign SS4BEG1 = NN4END14;
+// switch matrix multiplexer  SS4BEG2 		MUX-1
+	assign SS4BEG2 = NN4END13;
+// switch matrix multiplexer  SS4BEG3 		MUX-1
+	assign SS4BEG3 = NN4END12;
+// switch matrix multiplexer  SS4BEG4 		MUX-1
+	assign SS4BEG4 = NN4END11;
+// switch matrix multiplexer  SS4BEG5 		MUX-1
+	assign SS4BEG5 = NN4END10;
+// switch matrix multiplexer  SS4BEG6 		MUX-1
+	assign SS4BEG6 = NN4END9;
+// switch matrix multiplexer  SS4BEG7 		MUX-1
+	assign SS4BEG7 = NN4END8;
+// switch matrix multiplexer  SS4BEG8 		MUX-1
+	assign SS4BEG8 = NN4END7;
+// switch matrix multiplexer  SS4BEG9 		MUX-1
+	assign SS4BEG9 = NN4END6;
+// switch matrix multiplexer  SS4BEG10 		MUX-1
+	assign SS4BEG10 = NN4END5;
+// switch matrix multiplexer  SS4BEG11 		MUX-1
+	assign SS4BEG11 = NN4END4;
+// switch matrix multiplexer  SS4BEG12 		MUX-1
+	assign SS4BEG12 = NN4END3;
+// switch matrix multiplexer  SS4BEG13 		MUX-1
+	assign SS4BEG13 = NN4END2;
+// switch matrix multiplexer  SS4BEG14 		MUX-1
+	assign SS4BEG14 = NN4END1;
+// switch matrix multiplexer  SS4BEG15 		MUX-1
+	assign SS4BEG15 = NN4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_single2_tile.v b/verilog/rtl/eFPGA_core/N_term_single2_tile.v
new file mode 100644
index 0000000..0cc1a73
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_single2_tile.v
@@ -0,0 +1,362 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module N_term_single2 (N1END, N2MID, N2END, N4END, NN4END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:NN4END  
+	//  EAST
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:NULL  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	N_term_single2_switch_matrix Inst_N_term_single2_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.NN4END4(NN4END[4]),
+	.NN4END5(NN4END[5]),
+	.NN4END6(NN4END[6]),
+	.NN4END7(NN4END[7]),
+	.NN4END8(NN4END[8]),
+	.NN4END9(NN4END[9]),
+	.NN4END10(NN4END[10]),
+	.NN4END11(NN4END[11]),
+	.NN4END12(NN4END[12]),
+	.NN4END13(NN4END[13]),
+	.NN4END14(NN4END[14]),
+	.NN4END15(NN4END[15]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15]),
+	.SS4BEG0(SS4BEG[0]),
+	.SS4BEG1(SS4BEG[1]),
+	.SS4BEG2(SS4BEG[2]),
+	.SS4BEG3(SS4BEG[3]),
+	.SS4BEG4(SS4BEG[4]),
+	.SS4BEG5(SS4BEG[5]),
+	.SS4BEG6(SS4BEG[6]),
+	.SS4BEG7(SS4BEG[7]),
+	.SS4BEG8(SS4BEG[8]),
+	.SS4BEG9(SS4BEG[9]),
+	.SS4BEG10(SS4BEG[10]),
+	.SS4BEG11(SS4BEG[11]),
+	.SS4BEG12(SS4BEG[12]),
+	.SS4BEG13(SS4BEG[13]),
+	.SS4BEG14(SS4BEG[14]),
+	.SS4BEG15(SS4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_single_switch_matrix.v b/verilog/rtl/eFPGA_core/N_term_single_switch_matrix.v
new file mode 100644
index 0000000..c5ef424
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_single_switch_matrix.v
@@ -0,0 +1,298 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module N_term_single_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, NN4END0, NN4END1, NN4END2, NN4END3, NN4END4, NN4END5, NN4END6, NN4END7, NN4END8, NN4END9, NN4END10, NN4END11, NN4END12, NN4END13, NN4END14, NN4END15, Ci0, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, SS4BEG4, SS4BEG5, SS4BEG6, SS4BEG7, SS4BEG8, SS4BEG9, SS4BEG10, SS4BEG11, SS4BEG12, SS4BEG13, SS4BEG14, SS4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input NN4END4;
+	input NN4END5;
+	input NN4END6;
+	input NN4END7;
+	input NN4END8;
+	input NN4END9;
+	input NN4END10;
+	input NN4END11;
+	input NN4END12;
+	input NN4END13;
+	input NN4END14;
+	input NN4END15;
+	input Ci0;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output SS4BEG4;
+	output SS4BEG5;
+	output SS4BEG6;
+	output SS4BEG7;
+	output SS4BEG8;
+	output SS4BEG9;
+	output SS4BEG10;
+	output SS4BEG11;
+	output SS4BEG12;
+	output SS4BEG13;
+	output SS4BEG14;
+	output SS4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+	wire [1-1:0] SS4BEG0_input;
+	wire [1-1:0] SS4BEG1_input;
+	wire [1-1:0] SS4BEG2_input;
+	wire [1-1:0] SS4BEG3_input;
+	wire [1-1:0] SS4BEG4_input;
+	wire [1-1:0] SS4BEG5_input;
+	wire [1-1:0] SS4BEG6_input;
+	wire [1-1:0] SS4BEG7_input;
+	wire [1-1:0] SS4BEG8_input;
+	wire [1-1:0] SS4BEG9_input;
+	wire [1-1:0] SS4BEG10_input;
+	wire [1-1:0] SS4BEG11_input;
+	wire [1-1:0] SS4BEG12_input;
+	wire [1-1:0] SS4BEG13_input;
+	wire [1-1:0] SS4BEG14_input;
+	wire [1-1:0] SS4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+// switch matrix multiplexer  SS4BEG0 		MUX-1
+	assign SS4BEG0 = NN4END15;
+// switch matrix multiplexer  SS4BEG1 		MUX-1
+	assign SS4BEG1 = NN4END14;
+// switch matrix multiplexer  SS4BEG2 		MUX-1
+	assign SS4BEG2 = NN4END13;
+// switch matrix multiplexer  SS4BEG3 		MUX-1
+	assign SS4BEG3 = NN4END12;
+// switch matrix multiplexer  SS4BEG4 		MUX-1
+	assign SS4BEG4 = NN4END11;
+// switch matrix multiplexer  SS4BEG5 		MUX-1
+	assign SS4BEG5 = NN4END10;
+// switch matrix multiplexer  SS4BEG6 		MUX-1
+	assign SS4BEG6 = NN4END9;
+// switch matrix multiplexer  SS4BEG7 		MUX-1
+	assign SS4BEG7 = NN4END8;
+// switch matrix multiplexer  SS4BEG8 		MUX-1
+	assign SS4BEG8 = NN4END7;
+// switch matrix multiplexer  SS4BEG9 		MUX-1
+	assign SS4BEG9 = NN4END6;
+// switch matrix multiplexer  SS4BEG10 		MUX-1
+	assign SS4BEG10 = NN4END5;
+// switch matrix multiplexer  SS4BEG11 		MUX-1
+	assign SS4BEG11 = NN4END4;
+// switch matrix multiplexer  SS4BEG12 		MUX-1
+	assign SS4BEG12 = NN4END3;
+// switch matrix multiplexer  SS4BEG13 		MUX-1
+	assign SS4BEG13 = NN4END2;
+// switch matrix multiplexer  SS4BEG14 		MUX-1
+	assign SS4BEG14 = NN4END1;
+// switch matrix multiplexer  SS4BEG15 		MUX-1
+	assign SS4BEG15 = NN4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/N_term_single_tile.v b/verilog/rtl/eFPGA_core/N_term_single_tile.v
new file mode 100644
index 0000000..e5e5409
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/N_term_single_tile.v
@@ -0,0 +1,364 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module N_term_single (N1END, N2MID, N2END, N4END, NN4END, Ci, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:NN4END  
+	input [0:0] Ci; //wires:1 X_offset:0 Y_offset:1  source_name:NULL destination_name:Ci  
+	//  EAST
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:NULL  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	N_term_single_switch_matrix Inst_N_term_single_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.NN4END4(NN4END[4]),
+	.NN4END5(NN4END[5]),
+	.NN4END6(NN4END[6]),
+	.NN4END7(NN4END[7]),
+	.NN4END8(NN4END[8]),
+	.NN4END9(NN4END[9]),
+	.NN4END10(NN4END[10]),
+	.NN4END11(NN4END[11]),
+	.NN4END12(NN4END[12]),
+	.NN4END13(NN4END[13]),
+	.NN4END14(NN4END[14]),
+	.NN4END15(NN4END[15]),
+	.Ci0(Ci[0]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15]),
+	.SS4BEG0(SS4BEG[0]),
+	.SS4BEG1(SS4BEG[1]),
+	.SS4BEG2(SS4BEG[2]),
+	.SS4BEG3(SS4BEG[3]),
+	.SS4BEG4(SS4BEG[4]),
+	.SS4BEG5(SS4BEG[5]),
+	.SS4BEG6(SS4BEG[6]),
+	.SS4BEG7(SS4BEG[7]),
+	.SS4BEG8(SS4BEG[8]),
+	.SS4BEG9(SS4BEG[9]),
+	.SS4BEG10(SS4BEG[10]),
+	.SS4BEG11(SS4BEG[11]),
+	.SS4BEG12(SS4BEG[12]),
+	.SS4BEG13(SS4BEG[13]),
+	.SS4BEG14(SS4BEG[14]),
+	.SS4BEG15(SS4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/OutPass4_frame_config_mux.v b/verilog/rtl/eFPGA_core/OutPass4_frame_config_mux.v
new file mode 100644
index 0000000..4668174
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/OutPass4_frame_config_mux.v
@@ -0,0 +1,88 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+// InPassFlop2 and OutPassFlop2 are the same except for changing which side I0,I1 or O0,O1 gets connected to the top entity
+// InPassFlop2 and OutPassFlop2 are the same except for changing which side I0,I1 or O0,O1 gets connected to the top entity
+// InPassFlop2 and OutPassFlop2 are the same except for changing which side I0,I1 or O0,O1 gets connected to the top entity
+
+module OutPass4_frame_config (I0, I1, I2, I3, O0, O1, O2, O3, UserCLK, ConfigBits);
+	parameter NoConfigBits = 4;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// Pin0
+	input I0;
+	input I1;
+	input I2;
+	input I3;
+	output O0;// EXTERNAL
+	output O1;// EXTERNAL
+	output O2;// EXTERNAL
+	output O3;// EXTERNAL
+	// Tile IO ports from BELs
+	input UserCLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this signal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1:0] ConfigBits;
+
+//              ______   ______
+//    I////+//->|FLOP|-Q-|1 M |
+//         |             |  U |//////-> O
+//         +////////////-|0 X |               
+
+// I am instantiating an IOBUF primitive.
+// However, it is possible to connect corresponding pins all the way to top, just by adding an "// EXTERNAL" comment (see PAD in the entity)
+
+	reg Q0, Q1, Q2, Q3;   // FLOPs
+
+	always @ (posedge UserCLK)
+	begin
+		Q0 <= I0;
+		Q1 <= I1;
+		Q2 <= I2;
+		Q3 <= I3;
+	end
+
+	//assign O0 = ConfigBits[0] ? Q0 : I0;
+	//assign O1 = ConfigBits[1] ? Q1 : I1;
+	//assign O2 = ConfigBits[2] ? Q2 : I2;
+	//assign O3 = ConfigBits[3] ? Q3 : I3;
+
+    my_mux2 my_mux2_inst0(
+    .A0(I0),
+    .A1(Q0),
+    .S(ConfigBits[0]),
+    .X(O0)
+    );
+
+    my_mux2 my_mux2_inst1(
+    .A0(I1),
+    .A1(Q1),
+    .S(ConfigBits[1]),
+    .X(O1)
+    );
+
+    my_mux2 my_mux2_inst2(
+    .A0(I2),
+    .A1(Q2),
+    .S(ConfigBits[2]),
+    .X(O2)
+    );
+
+    my_mux2 my_mux2_inst3(
+    .A0(I3),
+    .A1(Q3),
+    .S(ConfigBits[3]),
+    .X(O3)
+    );
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RAM_IO_ConfigMem.v b/verilog/rtl/eFPGA_core/RAM_IO_ConfigMem.v
new file mode 100644
index 0000000..f444998
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RAM_IO_ConfigMem.v
@@ -0,0 +1,2334 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module RAM_IO_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 328;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [32-1:0] frame0;
+	wire [32-1:0] frame1;
+	wire [32-1:0] frame2;
+	wire [32-1:0] frame3;
+	wire [32-1:0] frame4;
+	wire [32-1:0] frame5;
+	wire [32-1:0] frame6;
+	wire [32-1:0] frame7;
+	wire [32-1:0] frame8;
+	wire [32-1:0] frame9;
+	wire [8-1:0] frame10;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[327]),
+	.QN(ConfigBits_N[327])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[326]),
+	.QN(ConfigBits_N[326])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[325]),
+	.QN(ConfigBits_N[325])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[324]),
+	.QN(ConfigBits_N[324])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[323]),
+	.QN(ConfigBits_N[323])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[322]),
+	.QN(ConfigBits_N[322])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[321]),
+	.QN(ConfigBits_N[321])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[320]),
+	.QN(ConfigBits_N[320])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[319]),
+	.QN(ConfigBits_N[319])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[318]),
+	.QN(ConfigBits_N[318])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[317]),
+	.QN(ConfigBits_N[317])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[316]),
+	.QN(ConfigBits_N[316])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[315]),
+	.QN(ConfigBits_N[315])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[314]),
+	.QN(ConfigBits_N[314])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[313]),
+	.QN(ConfigBits_N[313])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[312]),
+	.QN(ConfigBits_N[312])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[311]),
+	.QN(ConfigBits_N[311])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[310]),
+	.QN(ConfigBits_N[310])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[309]),
+	.QN(ConfigBits_N[309])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[308]),
+	.QN(ConfigBits_N[308])
+	);
+
+	LHQD1 Inst_frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[307]),
+	.QN(ConfigBits_N[307])
+	);
+
+	LHQD1 Inst_frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[306]),
+	.QN(ConfigBits_N[306])
+	);
+
+	LHQD1 Inst_frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[305]),
+	.QN(ConfigBits_N[305])
+	);
+
+	LHQD1 Inst_frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[304]),
+	.QN(ConfigBits_N[304])
+	);
+
+	LHQD1 Inst_frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[303]),
+	.QN(ConfigBits_N[303])
+	);
+
+	LHQD1 Inst_frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[302]),
+	.QN(ConfigBits_N[302])
+	);
+
+	LHQD1 Inst_frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[301]),
+	.QN(ConfigBits_N[301])
+	);
+
+	LHQD1 Inst_frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[300]),
+	.QN(ConfigBits_N[300])
+	);
+
+	LHQD1 Inst_frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[299]),
+	.QN(ConfigBits_N[299])
+	);
+
+	LHQD1 Inst_frame0_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[298]),
+	.QN(ConfigBits_N[298])
+	);
+
+	LHQD1 Inst_frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[297]),
+	.QN(ConfigBits_N[297])
+	);
+
+	LHQD1 Inst_frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[296]),
+	.QN(ConfigBits_N[296])
+	);
+
+	LHQD1 Inst_frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[295]),
+	.QN(ConfigBits_N[295])
+	);
+
+	LHQD1 Inst_frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[294]),
+	.QN(ConfigBits_N[294])
+	);
+
+	LHQD1 Inst_frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[293]),
+	.QN(ConfigBits_N[293])
+	);
+
+	LHQD1 Inst_frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[292]),
+	.QN(ConfigBits_N[292])
+	);
+
+	LHQD1 Inst_frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[291]),
+	.QN(ConfigBits_N[291])
+	);
+
+	LHQD1 Inst_frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[290]),
+	.QN(ConfigBits_N[290])
+	);
+
+	LHQD1 Inst_frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[289]),
+	.QN(ConfigBits_N[289])
+	);
+
+	LHQD1 Inst_frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[288]),
+	.QN(ConfigBits_N[288])
+	);
+
+	LHQD1 Inst_frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[287]),
+	.QN(ConfigBits_N[287])
+	);
+
+	LHQD1 Inst_frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[286]),
+	.QN(ConfigBits_N[286])
+	);
+
+	LHQD1 Inst_frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[285]),
+	.QN(ConfigBits_N[285])
+	);
+
+	LHQD1 Inst_frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[284]),
+	.QN(ConfigBits_N[284])
+	);
+
+	LHQD1 Inst_frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[283]),
+	.QN(ConfigBits_N[283])
+	);
+
+	LHQD1 Inst_frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[282]),
+	.QN(ConfigBits_N[282])
+	);
+
+	LHQD1 Inst_frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[281]),
+	.QN(ConfigBits_N[281])
+	);
+
+	LHQD1 Inst_frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[280]),
+	.QN(ConfigBits_N[280])
+	);
+
+	LHQD1 Inst_frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[279]),
+	.QN(ConfigBits_N[279])
+	);
+
+	LHQD1 Inst_frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[278]),
+	.QN(ConfigBits_N[278])
+	);
+
+	LHQD1 Inst_frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[277]),
+	.QN(ConfigBits_N[277])
+	);
+
+	LHQD1 Inst_frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[276]),
+	.QN(ConfigBits_N[276])
+	);
+
+	LHQD1 Inst_frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[275]),
+	.QN(ConfigBits_N[275])
+	);
+
+	LHQD1 Inst_frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[274]),
+	.QN(ConfigBits_N[274])
+	);
+
+	LHQD1 Inst_frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[273]),
+	.QN(ConfigBits_N[273])
+	);
+
+	LHQD1 Inst_frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[272]),
+	.QN(ConfigBits_N[272])
+	);
+
+	LHQD1 Inst_frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[271]),
+	.QN(ConfigBits_N[271])
+	);
+
+	LHQD1 Inst_frame1_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[270]),
+	.QN(ConfigBits_N[270])
+	);
+
+	LHQD1 Inst_frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[269]),
+	.QN(ConfigBits_N[269])
+	);
+
+	LHQD1 Inst_frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[268]),
+	.QN(ConfigBits_N[268])
+	);
+
+	LHQD1 Inst_frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[267]),
+	.QN(ConfigBits_N[267])
+	);
+
+	LHQD1 Inst_frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[266]),
+	.QN(ConfigBits_N[266])
+	);
+
+	LHQD1 Inst_frame1_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[265]),
+	.QN(ConfigBits_N[265])
+	);
+
+	LHQD1 Inst_frame1_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[264]),
+	.QN(ConfigBits_N[264])
+	);
+
+	LHQD1 Inst_frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[263]),
+	.QN(ConfigBits_N[263])
+	);
+
+	LHQD1 Inst_frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[262]),
+	.QN(ConfigBits_N[262])
+	);
+
+	LHQD1 Inst_frame2_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[261]),
+	.QN(ConfigBits_N[261])
+	);
+
+	LHQD1 Inst_frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[260]),
+	.QN(ConfigBits_N[260])
+	);
+
+	LHQD1 Inst_frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[259]),
+	.QN(ConfigBits_N[259])
+	);
+
+	LHQD1 Inst_frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[258]),
+	.QN(ConfigBits_N[258])
+	);
+
+	LHQD1 Inst_frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[257]),
+	.QN(ConfigBits_N[257])
+	);
+
+	LHQD1 Inst_frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[256]),
+	.QN(ConfigBits_N[256])
+	);
+
+	LHQD1 Inst_frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[255]),
+	.QN(ConfigBits_N[255])
+	);
+
+	LHQD1 Inst_frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[254]),
+	.QN(ConfigBits_N[254])
+	);
+
+	LHQD1 Inst_frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[253]),
+	.QN(ConfigBits_N[253])
+	);
+
+	LHQD1 Inst_frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[252]),
+	.QN(ConfigBits_N[252])
+	);
+
+	LHQD1 Inst_frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[251]),
+	.QN(ConfigBits_N[251])
+	);
+
+	LHQD1 Inst_frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[250]),
+	.QN(ConfigBits_N[250])
+	);
+
+	LHQD1 Inst_frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[249]),
+	.QN(ConfigBits_N[249])
+	);
+
+	LHQD1 Inst_frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[248]),
+	.QN(ConfigBits_N[248])
+	);
+
+	LHQD1 Inst_frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[247]),
+	.QN(ConfigBits_N[247])
+	);
+
+	LHQD1 Inst_frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[246]),
+	.QN(ConfigBits_N[246])
+	);
+
+	LHQD1 Inst_frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[245]),
+	.QN(ConfigBits_N[245])
+	);
+
+	LHQD1 Inst_frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[244]),
+	.QN(ConfigBits_N[244])
+	);
+
+	LHQD1 Inst_frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[243]),
+	.QN(ConfigBits_N[243])
+	);
+
+	LHQD1 Inst_frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[242]),
+	.QN(ConfigBits_N[242])
+	);
+
+	LHQD1 Inst_frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[241]),
+	.QN(ConfigBits_N[241])
+	);
+
+	LHQD1 Inst_frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[240]),
+	.QN(ConfigBits_N[240])
+	);
+
+	LHQD1 Inst_frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[239]),
+	.QN(ConfigBits_N[239])
+	);
+
+	LHQD1 Inst_frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[238]),
+	.QN(ConfigBits_N[238])
+	);
+
+	LHQD1 Inst_frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[237]),
+	.QN(ConfigBits_N[237])
+	);
+
+	LHQD1 Inst_frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[236]),
+	.QN(ConfigBits_N[236])
+	);
+
+	LHQD1 Inst_frame2_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[235]),
+	.QN(ConfigBits_N[235])
+	);
+
+	LHQD1 Inst_frame2_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[234]),
+	.QN(ConfigBits_N[234])
+	);
+
+	LHQD1 Inst_frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[233]),
+	.QN(ConfigBits_N[233])
+	);
+
+	LHQD1 Inst_frame2_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[232]),
+	.QN(ConfigBits_N[232])
+	);
+
+	LHQD1 Inst_frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[231]),
+	.QN(ConfigBits_N[231])
+	);
+
+	LHQD1 Inst_frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[230]),
+	.QN(ConfigBits_N[230])
+	);
+
+	LHQD1 Inst_frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[229]),
+	.QN(ConfigBits_N[229])
+	);
+
+	LHQD1 Inst_frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[228]),
+	.QN(ConfigBits_N[228])
+	);
+
+	LHQD1 Inst_frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[227]),
+	.QN(ConfigBits_N[227])
+	);
+
+	LHQD1 Inst_frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[226]),
+	.QN(ConfigBits_N[226])
+	);
+
+	LHQD1 Inst_frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[225]),
+	.QN(ConfigBits_N[225])
+	);
+
+	LHQD1 Inst_frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[224]),
+	.QN(ConfigBits_N[224])
+	);
+
+	LHQD1 Inst_frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[223]),
+	.QN(ConfigBits_N[223])
+	);
+
+	LHQD1 Inst_frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[222]),
+	.QN(ConfigBits_N[222])
+	);
+
+	LHQD1 Inst_frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[221]),
+	.QN(ConfigBits_N[221])
+	);
+
+	LHQD1 Inst_frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[220]),
+	.QN(ConfigBits_N[220])
+	);
+
+	LHQD1 Inst_frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[219]),
+	.QN(ConfigBits_N[219])
+	);
+
+	LHQD1 Inst_frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[218]),
+	.QN(ConfigBits_N[218])
+	);
+
+	LHQD1 Inst_frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[217]),
+	.QN(ConfigBits_N[217])
+	);
+
+	LHQD1 Inst_frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[216]),
+	.QN(ConfigBits_N[216])
+	);
+
+	LHQD1 Inst_frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[215]),
+	.QN(ConfigBits_N[215])
+	);
+
+	LHQD1 Inst_frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[214]),
+	.QN(ConfigBits_N[214])
+	);
+
+	LHQD1 Inst_frame3_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[213]),
+	.QN(ConfigBits_N[213])
+	);
+
+	LHQD1 Inst_frame3_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[212]),
+	.QN(ConfigBits_N[212])
+	);
+
+	LHQD1 Inst_frame3_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[211]),
+	.QN(ConfigBits_N[211])
+	);
+
+	LHQD1 Inst_frame3_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[210]),
+	.QN(ConfigBits_N[210])
+	);
+
+	LHQD1 Inst_frame3_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[209]),
+	.QN(ConfigBits_N[209])
+	);
+
+	LHQD1 Inst_frame3_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[208]),
+	.QN(ConfigBits_N[208])
+	);
+
+	LHQD1 Inst_frame3_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[207]),
+	.QN(ConfigBits_N[207])
+	);
+
+	LHQD1 Inst_frame3_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[206]),
+	.QN(ConfigBits_N[206])
+	);
+
+	LHQD1 Inst_frame3_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[205]),
+	.QN(ConfigBits_N[205])
+	);
+
+	LHQD1 Inst_frame3_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[204]),
+	.QN(ConfigBits_N[204])
+	);
+
+	LHQD1 Inst_frame3_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[203]),
+	.QN(ConfigBits_N[203])
+	);
+
+	LHQD1 Inst_frame3_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[202]),
+	.QN(ConfigBits_N[202])
+	);
+
+	LHQD1 Inst_frame3_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[201]),
+	.QN(ConfigBits_N[201])
+	);
+
+	LHQD1 Inst_frame3_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[200]),
+	.QN(ConfigBits_N[200])
+	);
+
+	LHQD1 Inst_frame4_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[199]),
+	.QN(ConfigBits_N[199])
+	);
+
+	LHQD1 Inst_frame4_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[198]),
+	.QN(ConfigBits_N[198])
+	);
+
+	LHQD1 Inst_frame4_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[197]),
+	.QN(ConfigBits_N[197])
+	);
+
+	LHQD1 Inst_frame4_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[196]),
+	.QN(ConfigBits_N[196])
+	);
+
+	LHQD1 Inst_frame4_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[195]),
+	.QN(ConfigBits_N[195])
+	);
+
+	LHQD1 Inst_frame4_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[194]),
+	.QN(ConfigBits_N[194])
+	);
+
+	LHQD1 Inst_frame4_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[193]),
+	.QN(ConfigBits_N[193])
+	);
+
+	LHQD1 Inst_frame4_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[192]),
+	.QN(ConfigBits_N[192])
+	);
+
+	LHQD1 Inst_frame4_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[191]),
+	.QN(ConfigBits_N[191])
+	);
+
+	LHQD1 Inst_frame4_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[190]),
+	.QN(ConfigBits_N[190])
+	);
+
+	LHQD1 Inst_frame4_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[189]),
+	.QN(ConfigBits_N[189])
+	);
+
+	LHQD1 Inst_frame4_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[188]),
+	.QN(ConfigBits_N[188])
+	);
+
+	LHQD1 Inst_frame4_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[187]),
+	.QN(ConfigBits_N[187])
+	);
+
+	LHQD1 Inst_frame4_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[186]),
+	.QN(ConfigBits_N[186])
+	);
+
+	LHQD1 Inst_frame4_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[185]),
+	.QN(ConfigBits_N[185])
+	);
+
+	LHQD1 Inst_frame4_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[184]),
+	.QN(ConfigBits_N[184])
+	);
+
+	LHQD1 Inst_frame4_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[183]),
+	.QN(ConfigBits_N[183])
+	);
+
+	LHQD1 Inst_frame4_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[182]),
+	.QN(ConfigBits_N[182])
+	);
+
+	LHQD1 Inst_frame4_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[181]),
+	.QN(ConfigBits_N[181])
+	);
+
+	LHQD1 Inst_frame4_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[180]),
+	.QN(ConfigBits_N[180])
+	);
+
+	LHQD1 Inst_frame4_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[179]),
+	.QN(ConfigBits_N[179])
+	);
+
+	LHQD1 Inst_frame4_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[178]),
+	.QN(ConfigBits_N[178])
+	);
+
+	LHQD1 Inst_frame4_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[177]),
+	.QN(ConfigBits_N[177])
+	);
+
+	LHQD1 Inst_frame4_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[176]),
+	.QN(ConfigBits_N[176])
+	);
+
+	LHQD1 Inst_frame4_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[175]),
+	.QN(ConfigBits_N[175])
+	);
+
+	LHQD1 Inst_frame4_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[174]),
+	.QN(ConfigBits_N[174])
+	);
+
+	LHQD1 Inst_frame4_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[173]),
+	.QN(ConfigBits_N[173])
+	);
+
+	LHQD1 Inst_frame4_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[172]),
+	.QN(ConfigBits_N[172])
+	);
+
+	LHQD1 Inst_frame4_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[171]),
+	.QN(ConfigBits_N[171])
+	);
+
+	LHQD1 Inst_frame4_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[170]),
+	.QN(ConfigBits_N[170])
+	);
+
+	LHQD1 Inst_frame4_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[169]),
+	.QN(ConfigBits_N[169])
+	);
+
+	LHQD1 Inst_frame4_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[168]),
+	.QN(ConfigBits_N[168])
+	);
+
+	LHQD1 Inst_frame5_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[167]),
+	.QN(ConfigBits_N[167])
+	);
+
+	LHQD1 Inst_frame5_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[166]),
+	.QN(ConfigBits_N[166])
+	);
+
+	LHQD1 Inst_frame5_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[165]),
+	.QN(ConfigBits_N[165])
+	);
+
+	LHQD1 Inst_frame5_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[164]),
+	.QN(ConfigBits_N[164])
+	);
+
+	LHQD1 Inst_frame5_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[163]),
+	.QN(ConfigBits_N[163])
+	);
+
+	LHQD1 Inst_frame5_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[162]),
+	.QN(ConfigBits_N[162])
+	);
+
+	LHQD1 Inst_frame5_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[161]),
+	.QN(ConfigBits_N[161])
+	);
+
+	LHQD1 Inst_frame5_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[160]),
+	.QN(ConfigBits_N[160])
+	);
+
+	LHQD1 Inst_frame5_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[159]),
+	.QN(ConfigBits_N[159])
+	);
+
+	LHQD1 Inst_frame5_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[158]),
+	.QN(ConfigBits_N[158])
+	);
+
+	LHQD1 Inst_frame5_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[157]),
+	.QN(ConfigBits_N[157])
+	);
+
+	LHQD1 Inst_frame5_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[156]),
+	.QN(ConfigBits_N[156])
+	);
+
+	LHQD1 Inst_frame5_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[155]),
+	.QN(ConfigBits_N[155])
+	);
+
+	LHQD1 Inst_frame5_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[154]),
+	.QN(ConfigBits_N[154])
+	);
+
+	LHQD1 Inst_frame5_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[153]),
+	.QN(ConfigBits_N[153])
+	);
+
+	LHQD1 Inst_frame5_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[152]),
+	.QN(ConfigBits_N[152])
+	);
+
+	LHQD1 Inst_frame5_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[151]),
+	.QN(ConfigBits_N[151])
+	);
+
+	LHQD1 Inst_frame5_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[150]),
+	.QN(ConfigBits_N[150])
+	);
+
+	LHQD1 Inst_frame5_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[149]),
+	.QN(ConfigBits_N[149])
+	);
+
+	LHQD1 Inst_frame5_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[148]),
+	.QN(ConfigBits_N[148])
+	);
+
+	LHQD1 Inst_frame5_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[147]),
+	.QN(ConfigBits_N[147])
+	);
+
+	LHQD1 Inst_frame5_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[146]),
+	.QN(ConfigBits_N[146])
+	);
+
+	LHQD1 Inst_frame5_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[145]),
+	.QN(ConfigBits_N[145])
+	);
+
+	LHQD1 Inst_frame5_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[144]),
+	.QN(ConfigBits_N[144])
+	);
+
+	LHQD1 Inst_frame5_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[143]),
+	.QN(ConfigBits_N[143])
+	);
+
+	LHQD1 Inst_frame5_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[142]),
+	.QN(ConfigBits_N[142])
+	);
+
+	LHQD1 Inst_frame5_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[141]),
+	.QN(ConfigBits_N[141])
+	);
+
+	LHQD1 Inst_frame5_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[140]),
+	.QN(ConfigBits_N[140])
+	);
+
+	LHQD1 Inst_frame5_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[139]),
+	.QN(ConfigBits_N[139])
+	);
+
+	LHQD1 Inst_frame5_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[138]),
+	.QN(ConfigBits_N[138])
+	);
+
+	LHQD1 Inst_frame5_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[137]),
+	.QN(ConfigBits_N[137])
+	);
+
+	LHQD1 Inst_frame5_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[136]),
+	.QN(ConfigBits_N[136])
+	);
+
+	LHQD1 Inst_frame6_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[135]),
+	.QN(ConfigBits_N[135])
+	);
+
+	LHQD1 Inst_frame6_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[134]),
+	.QN(ConfigBits_N[134])
+	);
+
+	LHQD1 Inst_frame6_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[133]),
+	.QN(ConfigBits_N[133])
+	);
+
+	LHQD1 Inst_frame6_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[132]),
+	.QN(ConfigBits_N[132])
+	);
+
+	LHQD1 Inst_frame6_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[131]),
+	.QN(ConfigBits_N[131])
+	);
+
+	LHQD1 Inst_frame6_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[130]),
+	.QN(ConfigBits_N[130])
+	);
+
+	LHQD1 Inst_frame6_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[129]),
+	.QN(ConfigBits_N[129])
+	);
+
+	LHQD1 Inst_frame6_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[128]),
+	.QN(ConfigBits_N[128])
+	);
+
+	LHQD1 Inst_frame6_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[127]),
+	.QN(ConfigBits_N[127])
+	);
+
+	LHQD1 Inst_frame6_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[126]),
+	.QN(ConfigBits_N[126])
+	);
+
+	LHQD1 Inst_frame6_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[125]),
+	.QN(ConfigBits_N[125])
+	);
+
+	LHQD1 Inst_frame6_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[124]),
+	.QN(ConfigBits_N[124])
+	);
+
+	LHQD1 Inst_frame6_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[123]),
+	.QN(ConfigBits_N[123])
+	);
+
+	LHQD1 Inst_frame6_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[122]),
+	.QN(ConfigBits_N[122])
+	);
+
+	LHQD1 Inst_frame6_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[121]),
+	.QN(ConfigBits_N[121])
+	);
+
+	LHQD1 Inst_frame6_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[120]),
+	.QN(ConfigBits_N[120])
+	);
+
+	LHQD1 Inst_frame6_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[119]),
+	.QN(ConfigBits_N[119])
+	);
+
+	LHQD1 Inst_frame6_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[118]),
+	.QN(ConfigBits_N[118])
+	);
+
+	LHQD1 Inst_frame6_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[117]),
+	.QN(ConfigBits_N[117])
+	);
+
+	LHQD1 Inst_frame6_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[116]),
+	.QN(ConfigBits_N[116])
+	);
+
+	LHQD1 Inst_frame6_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[115]),
+	.QN(ConfigBits_N[115])
+	);
+
+	LHQD1 Inst_frame6_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[114]),
+	.QN(ConfigBits_N[114])
+	);
+
+	LHQD1 Inst_frame6_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_frame6_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_frame6_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_frame6_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_frame6_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_frame6_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_frame6_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_frame6_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_frame6_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_frame6_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_frame7_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_frame7_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_frame7_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_frame7_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_frame7_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_frame7_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_frame7_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_frame7_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_frame7_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_frame7_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_frame7_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_frame7_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_frame7_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_frame7_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_frame7_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_frame7_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_frame7_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_frame7_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_frame7_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_frame7_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_frame7_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_frame7_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_frame7_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_frame7_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_frame7_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_frame7_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_frame7_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_frame7_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_frame7_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_frame7_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_frame7_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_frame7_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_frame8_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_frame8_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_frame8_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_frame8_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_frame8_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_frame8_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_frame8_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_frame8_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_frame8_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_frame8_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_frame8_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_frame8_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_frame8_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_frame8_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_frame8_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_frame8_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_frame8_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_frame8_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_frame8_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_frame8_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_frame8_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_frame8_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_frame8_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_frame8_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_frame8_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_frame8_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_frame8_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_frame8_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_frame8_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_frame8_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_frame8_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_frame8_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_frame9_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_frame9_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_frame9_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_frame9_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_frame9_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_frame9_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_frame9_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_frame9_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_frame9_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_frame9_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_frame9_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_frame9_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_frame9_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_frame9_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_frame9_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_frame9_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_frame9_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_frame9_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_frame9_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_frame9_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_frame9_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame9_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame9_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame9_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame9_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame9_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame9_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame9_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame9_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame9_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame9_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame9_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame10_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame10_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame10_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame10_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame10_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame10_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame10_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame10_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RAM_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/RAM_IO_switch_matrix.v
new file mode 100644
index 0000000..114335c
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RAM_IO_switch_matrix.v
@@ -0,0 +1,2738 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:280
+module RAM_IO_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, EE4END4, EE4END5, EE4END6, EE4END7, EE4END8, EE4END9, EE4END10, EE4END11, EE4END12, EE4END13, EE4END14, EE4END15, E6END0, E6END1, E6END2, E6END3, E6END4, E6END5, E6END6, E6END7, E6END8, E6END9, E6END10, E6END11, S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, RAM2FAB_D0_O0, RAM2FAB_D0_O1, RAM2FAB_D0_O2, RAM2FAB_D0_O3, RAM2FAB_D1_O0, RAM2FAB_D1_O1, RAM2FAB_D1_O2, RAM2FAB_D1_O3, RAM2FAB_D2_O0, RAM2FAB_D2_O1, RAM2FAB_D2_O2, RAM2FAB_D2_O3, RAM2FAB_D3_O0, RAM2FAB_D3_O1, RAM2FAB_D3_O2, RAM2FAB_D3_O3, J_NS4_END0, J_NS4_END1, J_NS4_END2, J_NS4_END3, J_NS4_END4, J_NS4_END5, J_NS4_END6, J_NS4_END7, J_NS4_END8, J_NS4_END9, J_NS4_END10, J_NS4_END11, J_NS4_END12, J_NS4_END13, J_NS4_END14, J_NS4_END15, J_NS2_END0, J_NS2_END1, J_NS2_END2, J_NS2_END3, J_NS2_END4, J_NS2_END5, J_NS2_END6, J_NS2_END7, J_NS1_END0, J_NS1_END1, J_NS1_END2, J_NS1_END3, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, WW4BEG4, WW4BEG5, WW4BEG6, WW4BEG7, WW4BEG8, WW4BEG9, WW4BEG10, WW4BEG11, WW4BEG12, WW4BEG13, WW4BEG14, WW4BEG15, W6BEG0, W6BEG1, W6BEG2, W6BEG3, W6BEG4, W6BEG5, W6BEG6, W6BEG7, W6BEG8, W6BEG9, W6BEG10, W6BEG11, FAB2RAM_D0_I0, FAB2RAM_D0_I1, FAB2RAM_D0_I2, FAB2RAM_D0_I3, FAB2RAM_D1_I0, FAB2RAM_D1_I1, FAB2RAM_D1_I2, FAB2RAM_D1_I3, FAB2RAM_D2_I0, FAB2RAM_D2_I1, FAB2RAM_D2_I2, FAB2RAM_D2_I3, FAB2RAM_D3_I0, FAB2RAM_D3_I1, FAB2RAM_D3_I2, FAB2RAM_D3_I3, FAB2RAM_A0_I0, FAB2RAM_A0_I1, FAB2RAM_A0_I2, FAB2RAM_A0_I3, FAB2RAM_A1_I0, FAB2RAM_A1_I1, FAB2RAM_A1_I2, FAB2RAM_A1_I3, FAB2RAM_C_I0, FAB2RAM_C_I1, FAB2RAM_C_I2, FAB2RAM_C_I3, J_NS4_BEG0, J_NS4_BEG1, J_NS4_BEG2, J_NS4_BEG3, J_NS4_BEG4, J_NS4_BEG5, J_NS4_BEG6, J_NS4_BEG7, J_NS4_BEG8, J_NS4_BEG9, J_NS4_BEG10, J_NS4_BEG11, J_NS4_BEG12, J_NS4_BEG13, J_NS4_BEG14, J_NS4_BEG15, J_NS2_BEG0, J_NS2_BEG1, J_NS2_BEG2, J_NS2_BEG3, J_NS2_BEG4, J_NS2_BEG5, J_NS2_BEG6, J_NS2_BEG7, J_NS1_BEG0, J_NS1_BEG1, J_NS1_BEG2, J_NS1_BEG3, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 280;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input EE4END4;
+	input EE4END5;
+	input EE4END6;
+	input EE4END7;
+	input EE4END8;
+	input EE4END9;
+	input EE4END10;
+	input EE4END11;
+	input EE4END12;
+	input EE4END13;
+	input EE4END14;
+	input EE4END15;
+	input E6END0;
+	input E6END1;
+	input E6END2;
+	input E6END3;
+	input E6END4;
+	input E6END5;
+	input E6END6;
+	input E6END7;
+	input E6END8;
+	input E6END9;
+	input E6END10;
+	input E6END11;
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input RAM2FAB_D0_O0;
+	input RAM2FAB_D0_O1;
+	input RAM2FAB_D0_O2;
+	input RAM2FAB_D0_O3;
+	input RAM2FAB_D1_O0;
+	input RAM2FAB_D1_O1;
+	input RAM2FAB_D1_O2;
+	input RAM2FAB_D1_O3;
+	input RAM2FAB_D2_O0;
+	input RAM2FAB_D2_O1;
+	input RAM2FAB_D2_O2;
+	input RAM2FAB_D2_O3;
+	input RAM2FAB_D3_O0;
+	input RAM2FAB_D3_O1;
+	input RAM2FAB_D3_O2;
+	input RAM2FAB_D3_O3;
+	input J_NS4_END0;
+	input J_NS4_END1;
+	input J_NS4_END2;
+	input J_NS4_END3;
+	input J_NS4_END4;
+	input J_NS4_END5;
+	input J_NS4_END6;
+	input J_NS4_END7;
+	input J_NS4_END8;
+	input J_NS4_END9;
+	input J_NS4_END10;
+	input J_NS4_END11;
+	input J_NS4_END12;
+	input J_NS4_END13;
+	input J_NS4_END14;
+	input J_NS4_END15;
+	input J_NS2_END0;
+	input J_NS2_END1;
+	input J_NS2_END2;
+	input J_NS2_END3;
+	input J_NS2_END4;
+	input J_NS2_END5;
+	input J_NS2_END6;
+	input J_NS2_END7;
+	input J_NS1_END0;
+	input J_NS1_END1;
+	input J_NS1_END2;
+	input J_NS1_END3;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output WW4BEG4;
+	output WW4BEG5;
+	output WW4BEG6;
+	output WW4BEG7;
+	output WW4BEG8;
+	output WW4BEG9;
+	output WW4BEG10;
+	output WW4BEG11;
+	output WW4BEG12;
+	output WW4BEG13;
+	output WW4BEG14;
+	output WW4BEG15;
+	output W6BEG0;
+	output W6BEG1;
+	output W6BEG2;
+	output W6BEG3;
+	output W6BEG4;
+	output W6BEG5;
+	output W6BEG6;
+	output W6BEG7;
+	output W6BEG8;
+	output W6BEG9;
+	output W6BEG10;
+	output W6BEG11;
+	output FAB2RAM_D0_I0;
+	output FAB2RAM_D0_I1;
+	output FAB2RAM_D0_I2;
+	output FAB2RAM_D0_I3;
+	output FAB2RAM_D1_I0;
+	output FAB2RAM_D1_I1;
+	output FAB2RAM_D1_I2;
+	output FAB2RAM_D1_I3;
+	output FAB2RAM_D2_I0;
+	output FAB2RAM_D2_I1;
+	output FAB2RAM_D2_I2;
+	output FAB2RAM_D2_I3;
+	output FAB2RAM_D3_I0;
+	output FAB2RAM_D3_I1;
+	output FAB2RAM_D3_I2;
+	output FAB2RAM_D3_I3;
+	output FAB2RAM_A0_I0;
+	output FAB2RAM_A0_I1;
+	output FAB2RAM_A0_I2;
+	output FAB2RAM_A0_I3;
+	output FAB2RAM_A1_I0;
+	output FAB2RAM_A1_I1;
+	output FAB2RAM_A1_I2;
+	output FAB2RAM_A1_I3;
+	output FAB2RAM_C_I0;
+	output FAB2RAM_C_I1;
+	output FAB2RAM_C_I2;
+	output FAB2RAM_C_I3;
+	output J_NS4_BEG0;
+	output J_NS4_BEG1;
+	output J_NS4_BEG2;
+	output J_NS4_BEG3;
+	output J_NS4_BEG4;
+	output J_NS4_BEG5;
+	output J_NS4_BEG6;
+	output J_NS4_BEG7;
+	output J_NS4_BEG8;
+	output J_NS4_BEG9;
+	output J_NS4_BEG10;
+	output J_NS4_BEG11;
+	output J_NS4_BEG12;
+	output J_NS4_BEG13;
+	output J_NS4_BEG14;
+	output J_NS4_BEG15;
+	output J_NS2_BEG0;
+	output J_NS2_BEG1;
+	output J_NS2_BEG2;
+	output J_NS2_BEG3;
+	output J_NS2_BEG4;
+	output J_NS2_BEG5;
+	output J_NS2_BEG6;
+	output J_NS2_BEG7;
+	output J_NS1_BEG0;
+	output J_NS1_BEG1;
+	output J_NS1_BEG2;
+	output J_NS1_BEG3;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [4-1:0] N1BEG0_input;
+	wire [4-1:0] N1BEG1_input;
+	wire [4-1:0] N1BEG2_input;
+	wire [4-1:0] N1BEG3_input;
+	wire [4-1:0] N2BEG0_input;
+	wire [4-1:0] N2BEG1_input;
+	wire [4-1:0] N2BEG2_input;
+	wire [4-1:0] N2BEG3_input;
+	wire [4-1:0] N2BEG4_input;
+	wire [4-1:0] N2BEG5_input;
+	wire [4-1:0] N2BEG6_input;
+	wire [4-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [8-1:0] N4BEG0_input;
+	wire [8-1:0] N4BEG1_input;
+	wire [8-1:0] N4BEG2_input;
+	wire [8-1:0] N4BEG3_input;
+	wire [4-1:0] S1BEG0_input;
+	wire [4-1:0] S1BEG1_input;
+	wire [4-1:0] S1BEG2_input;
+	wire [4-1:0] S1BEG3_input;
+	wire [4-1:0] S2BEG0_input;
+	wire [4-1:0] S2BEG1_input;
+	wire [4-1:0] S2BEG2_input;
+	wire [4-1:0] S2BEG3_input;
+	wire [4-1:0] S2BEG4_input;
+	wire [4-1:0] S2BEG5_input;
+	wire [4-1:0] S2BEG6_input;
+	wire [4-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [8-1:0] S4BEG0_input;
+	wire [8-1:0] S4BEG1_input;
+	wire [8-1:0] S4BEG2_input;
+	wire [8-1:0] S4BEG3_input;
+	wire [4-1:0] W1BEG0_input;
+	wire [4-1:0] W1BEG1_input;
+	wire [4-1:0] W1BEG2_input;
+	wire [4-1:0] W1BEG3_input;
+	wire [4-1:0] W2BEG0_input;
+	wire [4-1:0] W2BEG1_input;
+	wire [4-1:0] W2BEG2_input;
+	wire [4-1:0] W2BEG3_input;
+	wire [4-1:0] W2BEG4_input;
+	wire [4-1:0] W2BEG5_input;
+	wire [4-1:0] W2BEG6_input;
+	wire [4-1:0] W2BEG7_input;
+	wire [4-1:0] W2BEGb0_input;
+	wire [4-1:0] W2BEGb1_input;
+	wire [4-1:0] W2BEGb2_input;
+	wire [4-1:0] W2BEGb3_input;
+	wire [4-1:0] W2BEGb4_input;
+	wire [4-1:0] W2BEGb5_input;
+	wire [4-1:0] W2BEGb6_input;
+	wire [4-1:0] W2BEGb7_input;
+	wire [4-1:0] WW4BEG0_input;
+	wire [4-1:0] WW4BEG1_input;
+	wire [4-1:0] WW4BEG2_input;
+	wire [4-1:0] WW4BEG3_input;
+	wire [4-1:0] WW4BEG4_input;
+	wire [4-1:0] WW4BEG5_input;
+	wire [4-1:0] WW4BEG6_input;
+	wire [4-1:0] WW4BEG7_input;
+	wire [4-1:0] WW4BEG8_input;
+	wire [4-1:0] WW4BEG9_input;
+	wire [4-1:0] WW4BEG10_input;
+	wire [4-1:0] WW4BEG11_input;
+	wire [4-1:0] WW4BEG12_input;
+	wire [4-1:0] WW4BEG13_input;
+	wire [4-1:0] WW4BEG14_input;
+	wire [4-1:0] WW4BEG15_input;
+	wire [4-1:0] W6BEG0_input;
+	wire [4-1:0] W6BEG1_input;
+	wire [4-1:0] W6BEG2_input;
+	wire [4-1:0] W6BEG3_input;
+	wire [4-1:0] W6BEG4_input;
+	wire [4-1:0] W6BEG5_input;
+	wire [4-1:0] W6BEG6_input;
+	wire [4-1:0] W6BEG7_input;
+	wire [4-1:0] W6BEG8_input;
+	wire [4-1:0] W6BEG9_input;
+	wire [4-1:0] W6BEG10_input;
+	wire [4-1:0] W6BEG11_input;
+	wire [4-1:0] FAB2RAM_D0_I0_input;
+	wire [4-1:0] FAB2RAM_D0_I1_input;
+	wire [4-1:0] FAB2RAM_D0_I2_input;
+	wire [4-1:0] FAB2RAM_D0_I3_input;
+	wire [4-1:0] FAB2RAM_D1_I0_input;
+	wire [4-1:0] FAB2RAM_D1_I1_input;
+	wire [4-1:0] FAB2RAM_D1_I2_input;
+	wire [4-1:0] FAB2RAM_D1_I3_input;
+	wire [4-1:0] FAB2RAM_D2_I0_input;
+	wire [4-1:0] FAB2RAM_D2_I1_input;
+	wire [4-1:0] FAB2RAM_D2_I2_input;
+	wire [4-1:0] FAB2RAM_D2_I3_input;
+	wire [4-1:0] FAB2RAM_D3_I0_input;
+	wire [4-1:0] FAB2RAM_D3_I1_input;
+	wire [4-1:0] FAB2RAM_D3_I2_input;
+	wire [4-1:0] FAB2RAM_D3_I3_input;
+	wire [4-1:0] FAB2RAM_A0_I0_input;
+	wire [4-1:0] FAB2RAM_A0_I1_input;
+	wire [4-1:0] FAB2RAM_A0_I2_input;
+	wire [4-1:0] FAB2RAM_A0_I3_input;
+	wire [4-1:0] FAB2RAM_A1_I0_input;
+	wire [4-1:0] FAB2RAM_A1_I1_input;
+	wire [4-1:0] FAB2RAM_A1_I2_input;
+	wire [4-1:0] FAB2RAM_A1_I3_input;
+	wire [4-1:0] FAB2RAM_C_I0_input;
+	wire [4-1:0] FAB2RAM_C_I1_input;
+	wire [4-1:0] FAB2RAM_C_I2_input;
+	wire [4-1:0] FAB2RAM_C_I3_input;
+	wire [4-1:0] J_NS4_BEG0_input;
+	wire [4-1:0] J_NS4_BEG1_input;
+	wire [4-1:0] J_NS4_BEG2_input;
+	wire [4-1:0] J_NS4_BEG3_input;
+	wire [4-1:0] J_NS4_BEG4_input;
+	wire [4-1:0] J_NS4_BEG5_input;
+	wire [4-1:0] J_NS4_BEG6_input;
+	wire [4-1:0] J_NS4_BEG7_input;
+	wire [4-1:0] J_NS4_BEG8_input;
+	wire [4-1:0] J_NS4_BEG9_input;
+	wire [4-1:0] J_NS4_BEG10_input;
+	wire [4-1:0] J_NS4_BEG11_input;
+	wire [4-1:0] J_NS4_BEG12_input;
+	wire [4-1:0] J_NS4_BEG13_input;
+	wire [4-1:0] J_NS4_BEG14_input;
+	wire [4-1:0] J_NS4_BEG15_input;
+	wire [4-1:0] J_NS2_BEG0_input;
+	wire [4-1:0] J_NS2_BEG1_input;
+	wire [4-1:0] J_NS2_BEG2_input;
+	wire [4-1:0] J_NS2_BEG3_input;
+	wire [4-1:0] J_NS2_BEG4_input;
+	wire [4-1:0] J_NS2_BEG5_input;
+	wire [4-1:0] J_NS2_BEG6_input;
+	wire [4-1:0] J_NS2_BEG7_input;
+	wire [4-1:0] J_NS1_BEG0_input;
+	wire [4-1:0] J_NS1_BEG1_input;
+	wire [4-1:0] J_NS1_BEG2_input;
+	wire [4-1:0] J_NS1_BEG3_input;
+
+	wire [2-1:0] DEBUG_select_N1BEG0;
+	wire [2-1:0] DEBUG_select_N1BEG1;
+	wire [2-1:0] DEBUG_select_N1BEG2;
+	wire [2-1:0] DEBUG_select_N1BEG3;
+	wire [2-1:0] DEBUG_select_N2BEG0;
+	wire [2-1:0] DEBUG_select_N2BEG1;
+	wire [2-1:0] DEBUG_select_N2BEG2;
+	wire [2-1:0] DEBUG_select_N2BEG3;
+	wire [2-1:0] DEBUG_select_N2BEG4;
+	wire [2-1:0] DEBUG_select_N2BEG5;
+	wire [2-1:0] DEBUG_select_N2BEG6;
+	wire [2-1:0] DEBUG_select_N2BEG7;
+	wire [3-1:0] DEBUG_select_N4BEG0;
+	wire [3-1:0] DEBUG_select_N4BEG1;
+	wire [3-1:0] DEBUG_select_N4BEG2;
+	wire [3-1:0] DEBUG_select_N4BEG3;
+	wire [2-1:0] DEBUG_select_S1BEG0;
+	wire [2-1:0] DEBUG_select_S1BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG2;
+	wire [2-1:0] DEBUG_select_S1BEG3;
+	wire [2-1:0] DEBUG_select_S2BEG0;
+	wire [2-1:0] DEBUG_select_S2BEG1;
+	wire [2-1:0] DEBUG_select_S2BEG2;
+	wire [2-1:0] DEBUG_select_S2BEG3;
+	wire [2-1:0] DEBUG_select_S2BEG4;
+	wire [2-1:0] DEBUG_select_S2BEG5;
+	wire [2-1:0] DEBUG_select_S2BEG6;
+	wire [2-1:0] DEBUG_select_S2BEG7;
+	wire [3-1:0] DEBUG_select_S4BEG0;
+	wire [3-1:0] DEBUG_select_S4BEG1;
+	wire [3-1:0] DEBUG_select_S4BEG2;
+	wire [3-1:0] DEBUG_select_S4BEG3;
+	wire [2-1:0] DEBUG_select_W1BEG0;
+	wire [2-1:0] DEBUG_select_W1BEG1;
+	wire [2-1:0] DEBUG_select_W1BEG2;
+	wire [2-1:0] DEBUG_select_W1BEG3;
+	wire [2-1:0] DEBUG_select_W2BEG0;
+	wire [2-1:0] DEBUG_select_W2BEG1;
+	wire [2-1:0] DEBUG_select_W2BEG2;
+	wire [2-1:0] DEBUG_select_W2BEG3;
+	wire [2-1:0] DEBUG_select_W2BEG4;
+	wire [2-1:0] DEBUG_select_W2BEG5;
+	wire [2-1:0] DEBUG_select_W2BEG6;
+	wire [2-1:0] DEBUG_select_W2BEG7;
+	wire [2-1:0] DEBUG_select_W2BEGb0;
+	wire [2-1:0] DEBUG_select_W2BEGb1;
+	wire [2-1:0] DEBUG_select_W2BEGb2;
+	wire [2-1:0] DEBUG_select_W2BEGb3;
+	wire [2-1:0] DEBUG_select_W2BEGb4;
+	wire [2-1:0] DEBUG_select_W2BEGb5;
+	wire [2-1:0] DEBUG_select_W2BEGb6;
+	wire [2-1:0] DEBUG_select_W2BEGb7;
+	wire [2-1:0] DEBUG_select_WW4BEG0;
+	wire [2-1:0] DEBUG_select_WW4BEG1;
+	wire [2-1:0] DEBUG_select_WW4BEG2;
+	wire [2-1:0] DEBUG_select_WW4BEG3;
+	wire [2-1:0] DEBUG_select_WW4BEG4;
+	wire [2-1:0] DEBUG_select_WW4BEG5;
+	wire [2-1:0] DEBUG_select_WW4BEG6;
+	wire [2-1:0] DEBUG_select_WW4BEG7;
+	wire [2-1:0] DEBUG_select_WW4BEG8;
+	wire [2-1:0] DEBUG_select_WW4BEG9;
+	wire [2-1:0] DEBUG_select_WW4BEG10;
+	wire [2-1:0] DEBUG_select_WW4BEG11;
+	wire [2-1:0] DEBUG_select_WW4BEG12;
+	wire [2-1:0] DEBUG_select_WW4BEG13;
+	wire [2-1:0] DEBUG_select_WW4BEG14;
+	wire [2-1:0] DEBUG_select_WW4BEG15;
+	wire [2-1:0] DEBUG_select_W6BEG0;
+	wire [2-1:0] DEBUG_select_W6BEG1;
+	wire [2-1:0] DEBUG_select_W6BEG2;
+	wire [2-1:0] DEBUG_select_W6BEG3;
+	wire [2-1:0] DEBUG_select_W6BEG4;
+	wire [2-1:0] DEBUG_select_W6BEG5;
+	wire [2-1:0] DEBUG_select_W6BEG6;
+	wire [2-1:0] DEBUG_select_W6BEG7;
+	wire [2-1:0] DEBUG_select_W6BEG8;
+	wire [2-1:0] DEBUG_select_W6BEG9;
+	wire [2-1:0] DEBUG_select_W6BEG10;
+	wire [2-1:0] DEBUG_select_W6BEG11;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D0_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D0_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D0_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D0_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D1_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D1_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D1_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D1_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D2_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D2_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D2_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D2_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D3_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D3_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D3_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_D3_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A0_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A0_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A0_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A0_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A1_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A1_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A1_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_A1_I3;
+	wire [2-1:0] DEBUG_select_FAB2RAM_C_I0;
+	wire [2-1:0] DEBUG_select_FAB2RAM_C_I1;
+	wire [2-1:0] DEBUG_select_FAB2RAM_C_I2;
+	wire [2-1:0] DEBUG_select_FAB2RAM_C_I3;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG0;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG1;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG2;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG3;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG4;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG5;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG6;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG7;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG8;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG9;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG10;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG11;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG12;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG13;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG14;
+	wire [2-1:0] DEBUG_select_J_NS4_BEG15;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG0;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG1;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG2;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG3;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG4;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG5;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG6;
+	wire [2-1:0] DEBUG_select_J_NS2_BEG7;
+	wire [2-1:0] DEBUG_select_J_NS1_BEG0;
+	wire [2-1:0] DEBUG_select_J_NS1_BEG1;
+	wire [2-1:0] DEBUG_select_J_NS1_BEG2;
+	wire [2-1:0] DEBUG_select_J_NS1_BEG3;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-4
+	assign N1BEG0_input = {J_NS1_END0,J_NS4_END12,E6END4,E1END0};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG0 (
+	.A0 (N1BEG0_input[0]),
+	.A1 (N1BEG0_input[1]),
+	.A2 (N1BEG0_input[2]),
+	.A3 (N1BEG0_input[3]),
+	.S0 (ConfigBits[0+0]),
+	.S0N (ConfigBits_N[0+0]),
+	.S1 (ConfigBits[0+1]),
+	.S1N (ConfigBits_N[0+1]),
+	.X (N1BEG0)
+	);
+
+// switch matrix multiplexer  N1BEG1 		MUX-4
+	assign N1BEG1_input = {J_NS1_END1,J_NS4_END13,E6END5,E1END1};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG1 (
+	.A0 (N1BEG1_input[0]),
+	.A1 (N1BEG1_input[1]),
+	.A2 (N1BEG1_input[2]),
+	.A3 (N1BEG1_input[3]),
+	.S0 (ConfigBits[2+0]),
+	.S0N (ConfigBits_N[2+0]),
+	.S1 (ConfigBits[2+1]),
+	.S1N (ConfigBits_N[2+1]),
+	.X (N1BEG1)
+	);
+
+// switch matrix multiplexer  N1BEG2 		MUX-4
+	assign N1BEG2_input = {J_NS1_END2,J_NS4_END14,E6END6,E1END2};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG2 (
+	.A0 (N1BEG2_input[0]),
+	.A1 (N1BEG2_input[1]),
+	.A2 (N1BEG2_input[2]),
+	.A3 (N1BEG2_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (N1BEG2)
+	);
+
+// switch matrix multiplexer  N1BEG3 		MUX-4
+	assign N1BEG3_input = {J_NS1_END3,J_NS4_END15,E6END7,E1END3};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG3 (
+	.A0 (N1BEG3_input[0]),
+	.A1 (N1BEG3_input[1]),
+	.A2 (N1BEG3_input[2]),
+	.A3 (N1BEG3_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (N1BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG0 		MUX-4
+	assign N2BEG0_input = {J_NS2_END0,E6END7,E2END7,E2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG0 (
+	.A0 (N2BEG0_input[0]),
+	.A1 (N2BEG0_input[1]),
+	.A2 (N2BEG0_input[2]),
+	.A3 (N2BEG0_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (N2BEG0)
+	);
+
+// switch matrix multiplexer  N2BEG1 		MUX-4
+	assign N2BEG1_input = {J_NS2_END1,E6END6,E2END6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG1 (
+	.A0 (N2BEG1_input[0]),
+	.A1 (N2BEG1_input[1]),
+	.A2 (N2BEG1_input[2]),
+	.A3 (N2BEG1_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (N2BEG1)
+	);
+
+// switch matrix multiplexer  N2BEG2 		MUX-4
+	assign N2BEG2_input = {J_NS2_END2,E6END5,E2END5,E2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG2 (
+	.A0 (N2BEG2_input[0]),
+	.A1 (N2BEG2_input[1]),
+	.A2 (N2BEG2_input[2]),
+	.A3 (N2BEG2_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (N2BEG2)
+	);
+
+// switch matrix multiplexer  N2BEG3 		MUX-4
+	assign N2BEG3_input = {J_NS2_END3,E6END4,E2END4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG3 (
+	.A0 (N2BEG3_input[0]),
+	.A1 (N2BEG3_input[1]),
+	.A2 (N2BEG3_input[2]),
+	.A3 (N2BEG3_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (N2BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG4 		MUX-4
+	assign N2BEG4_input = {J_NS2_END4,E6END3,E2END3,E2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG4 (
+	.A0 (N2BEG4_input[0]),
+	.A1 (N2BEG4_input[1]),
+	.A2 (N2BEG4_input[2]),
+	.A3 (N2BEG4_input[3]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.X (N2BEG4)
+	);
+
+// switch matrix multiplexer  N2BEG5 		MUX-4
+	assign N2BEG5_input = {J_NS2_END5,E6END2,E2END2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG5 (
+	.A0 (N2BEG5_input[0]),
+	.A1 (N2BEG5_input[1]),
+	.A2 (N2BEG5_input[2]),
+	.A3 (N2BEG5_input[3]),
+	.S0 (ConfigBits[18+0]),
+	.S0N (ConfigBits_N[18+0]),
+	.S1 (ConfigBits[18+1]),
+	.S1N (ConfigBits_N[18+1]),
+	.X (N2BEG5)
+	);
+
+// switch matrix multiplexer  N2BEG6 		MUX-4
+	assign N2BEG6_input = {J_NS2_END6,E6END1,E2END1,E2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG6 (
+	.A0 (N2BEG6_input[0]),
+	.A1 (N2BEG6_input[1]),
+	.A2 (N2BEG6_input[2]),
+	.A3 (N2BEG6_input[3]),
+	.S0 (ConfigBits[20+0]),
+	.S0N (ConfigBits_N[20+0]),
+	.S1 (ConfigBits[20+1]),
+	.S1N (ConfigBits_N[20+1]),
+	.X (N2BEG6)
+	);
+
+// switch matrix multiplexer  N2BEG7 		MUX-4
+	assign N2BEG7_input = {J_NS2_END7,E6END0,E2END0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_N2BEG7 (
+	.A0 (N2BEG7_input[0]),
+	.A1 (N2BEG7_input[1]),
+	.A2 (N2BEG7_input[2]),
+	.A3 (N2BEG7_input[3]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.X (N2BEG7)
+	);
+
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = N2MID0;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = N2MID1;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = N2MID2;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = N2MID3;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = N2MID4;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = N2MID5;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = N2MID6;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = N2MID7;
+// switch matrix multiplexer  N4BEG0 		MUX-8
+	assign N4BEG0_input = {J_NS2_END0,J_NS4_END12,J_NS4_END8,J_NS4_END4,J_NS4_END0,E6END8,EE4END0,E1END0};
+	cus_mux81_buf inst_cus_mux81_buf_N4BEG0 (
+	.A0 (N4BEG0_input[0]),
+	.A1 (N4BEG0_input[1]),
+	.A2 (N4BEG0_input[2]),
+	.A3 (N4BEG0_input[3]),
+	.A4 (N4BEG0_input[4]),
+	.A5 (N4BEG0_input[5]),
+	.A6 (N4BEG0_input[6]),
+	.A7 (N4BEG0_input[7]),
+	.S0 (ConfigBits[24+0]),
+	.S0N (ConfigBits_N[24+0]),
+	.S1 (ConfigBits[24+1]),
+	.S1N (ConfigBits_N[24+1]),
+	.S2 (ConfigBits[24+2]),
+	.S2N (ConfigBits_N[24+2]),
+	.X (N4BEG0)
+	);
+
+// switch matrix multiplexer  N4BEG1 		MUX-8
+	assign N4BEG1_input = {J_NS2_END1,J_NS4_END13,J_NS4_END9,J_NS4_END5,J_NS4_END1,E6END9,EE4END1,E1END1};
+	cus_mux81_buf inst_cus_mux81_buf_N4BEG1 (
+	.A0 (N4BEG1_input[0]),
+	.A1 (N4BEG1_input[1]),
+	.A2 (N4BEG1_input[2]),
+	.A3 (N4BEG1_input[3]),
+	.A4 (N4BEG1_input[4]),
+	.A5 (N4BEG1_input[5]),
+	.A6 (N4BEG1_input[6]),
+	.A7 (N4BEG1_input[7]),
+	.S0 (ConfigBits[27+0]),
+	.S0N (ConfigBits_N[27+0]),
+	.S1 (ConfigBits[27+1]),
+	.S1N (ConfigBits_N[27+1]),
+	.S2 (ConfigBits[27+2]),
+	.S2N (ConfigBits_N[27+2]),
+	.X (N4BEG1)
+	);
+
+// switch matrix multiplexer  N4BEG2 		MUX-8
+	assign N4BEG2_input = {J_NS2_END2,J_NS4_END14,J_NS4_END10,J_NS4_END6,J_NS4_END2,E6END10,EE4END2,E1END2};
+	cus_mux81_buf inst_cus_mux81_buf_N4BEG2 (
+	.A0 (N4BEG2_input[0]),
+	.A1 (N4BEG2_input[1]),
+	.A2 (N4BEG2_input[2]),
+	.A3 (N4BEG2_input[3]),
+	.A4 (N4BEG2_input[4]),
+	.A5 (N4BEG2_input[5]),
+	.A6 (N4BEG2_input[6]),
+	.A7 (N4BEG2_input[7]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.S2 (ConfigBits[30+2]),
+	.S2N (ConfigBits_N[30+2]),
+	.X (N4BEG2)
+	);
+
+// switch matrix multiplexer  N4BEG3 		MUX-8
+	assign N4BEG3_input = {J_NS2_END3,J_NS4_END15,J_NS4_END11,J_NS4_END7,J_NS4_END3,E6END11,EE4END3,E1END3};
+	cus_mux81_buf inst_cus_mux81_buf_N4BEG3 (
+	.A0 (N4BEG3_input[0]),
+	.A1 (N4BEG3_input[1]),
+	.A2 (N4BEG3_input[2]),
+	.A3 (N4BEG3_input[3]),
+	.A4 (N4BEG3_input[4]),
+	.A5 (N4BEG3_input[5]),
+	.A6 (N4BEG3_input[6]),
+	.A7 (N4BEG3_input[7]),
+	.S0 (ConfigBits[33+0]),
+	.S0N (ConfigBits_N[33+0]),
+	.S1 (ConfigBits[33+1]),
+	.S1N (ConfigBits_N[33+1]),
+	.S2 (ConfigBits[33+2]),
+	.S2N (ConfigBits_N[33+2]),
+	.X (N4BEG3)
+	);
+
+// switch matrix multiplexer  S1BEG0 		MUX-4
+	assign S1BEG0_input = {J_NS1_END0,J_NS4_END12,E6END8,E1END0};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG0 (
+	.A0 (S1BEG0_input[0]),
+	.A1 (S1BEG0_input[1]),
+	.A2 (S1BEG0_input[2]),
+	.A3 (S1BEG0_input[3]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.X (S1BEG0)
+	);
+
+// switch matrix multiplexer  S1BEG1 		MUX-4
+	assign S1BEG1_input = {J_NS1_END1,J_NS4_END13,E6END9,E1END1};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG1 (
+	.A0 (S1BEG1_input[0]),
+	.A1 (S1BEG1_input[1]),
+	.A2 (S1BEG1_input[2]),
+	.A3 (S1BEG1_input[3]),
+	.S0 (ConfigBits[38+0]),
+	.S0N (ConfigBits_N[38+0]),
+	.S1 (ConfigBits[38+1]),
+	.S1N (ConfigBits_N[38+1]),
+	.X (S1BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG2 		MUX-4
+	assign S1BEG2_input = {J_NS1_END2,J_NS4_END14,E6END10,E1END2};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG2 (
+	.A0 (S1BEG2_input[0]),
+	.A1 (S1BEG2_input[1]),
+	.A2 (S1BEG2_input[2]),
+	.A3 (S1BEG2_input[3]),
+	.S0 (ConfigBits[40+0]),
+	.S0N (ConfigBits_N[40+0]),
+	.S1 (ConfigBits[40+1]),
+	.S1N (ConfigBits_N[40+1]),
+	.X (S1BEG2)
+	);
+
+// switch matrix multiplexer  S1BEG3 		MUX-4
+	assign S1BEG3_input = {J_NS1_END3,J_NS4_END15,E6END11,E1END3};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG3 (
+	.A0 (S1BEG3_input[0]),
+	.A1 (S1BEG3_input[1]),
+	.A2 (S1BEG3_input[2]),
+	.A3 (S1BEG3_input[3]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.X (S1BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG0 		MUX-4
+	assign S2BEG0_input = {J_NS2_END0,E6END8,E2END7,E2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG0 (
+	.A0 (S2BEG0_input[0]),
+	.A1 (S2BEG0_input[1]),
+	.A2 (S2BEG0_input[2]),
+	.A3 (S2BEG0_input[3]),
+	.S0 (ConfigBits[44+0]),
+	.S0N (ConfigBits_N[44+0]),
+	.S1 (ConfigBits[44+1]),
+	.S1N (ConfigBits_N[44+1]),
+	.X (S2BEG0)
+	);
+
+// switch matrix multiplexer  S2BEG1 		MUX-4
+	assign S2BEG1_input = {J_NS2_END1,E6END9,E2END6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG1 (
+	.A0 (S2BEG1_input[0]),
+	.A1 (S2BEG1_input[1]),
+	.A2 (S2BEG1_input[2]),
+	.A3 (S2BEG1_input[3]),
+	.S0 (ConfigBits[46+0]),
+	.S0N (ConfigBits_N[46+0]),
+	.S1 (ConfigBits[46+1]),
+	.S1N (ConfigBits_N[46+1]),
+	.X (S2BEG1)
+	);
+
+// switch matrix multiplexer  S2BEG2 		MUX-4
+	assign S2BEG2_input = {J_NS2_END2,E6END10,E2END5,E2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG2 (
+	.A0 (S2BEG2_input[0]),
+	.A1 (S2BEG2_input[1]),
+	.A2 (S2BEG2_input[2]),
+	.A3 (S2BEG2_input[3]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.X (S2BEG2)
+	);
+
+// switch matrix multiplexer  S2BEG3 		MUX-4
+	assign S2BEG3_input = {J_NS2_END3,E6END11,E2END4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG3 (
+	.A0 (S2BEG3_input[0]),
+	.A1 (S2BEG3_input[1]),
+	.A2 (S2BEG3_input[2]),
+	.A3 (S2BEG3_input[3]),
+	.S0 (ConfigBits[50+0]),
+	.S0N (ConfigBits_N[50+0]),
+	.S1 (ConfigBits[50+1]),
+	.S1N (ConfigBits_N[50+1]),
+	.X (S2BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG4 		MUX-4
+	assign S2BEG4_input = {J_NS2_END4,E2END3,E2MID3,E1END0};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG4 (
+	.A0 (S2BEG4_input[0]),
+	.A1 (S2BEG4_input[1]),
+	.A2 (S2BEG4_input[2]),
+	.A3 (S2BEG4_input[3]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.X (S2BEG4)
+	);
+
+// switch matrix multiplexer  S2BEG5 		MUX-4
+	assign S2BEG5_input = {J_NS2_END5,E2END2,E2MID2,E1END1};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG5 (
+	.A0 (S2BEG5_input[0]),
+	.A1 (S2BEG5_input[1]),
+	.A2 (S2BEG5_input[2]),
+	.A3 (S2BEG5_input[3]),
+	.S0 (ConfigBits[54+0]),
+	.S0N (ConfigBits_N[54+0]),
+	.S1 (ConfigBits[54+1]),
+	.S1N (ConfigBits_N[54+1]),
+	.X (S2BEG5)
+	);
+
+// switch matrix multiplexer  S2BEG6 		MUX-4
+	assign S2BEG6_input = {J_NS2_END6,E2END1,E2MID1,E1END2};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG6 (
+	.A0 (S2BEG6_input[0]),
+	.A1 (S2BEG6_input[1]),
+	.A2 (S2BEG6_input[2]),
+	.A3 (S2BEG6_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (S2BEG6)
+	);
+
+// switch matrix multiplexer  S2BEG7 		MUX-4
+	assign S2BEG7_input = {J_NS2_END7,E2END0,E2MID0,E1END3};
+	cus_mux41_buf inst_cus_mux41_buf_S2BEG7 (
+	.A0 (S2BEG7_input[0]),
+	.A1 (S2BEG7_input[1]),
+	.A2 (S2BEG7_input[2]),
+	.A3 (S2BEG7_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (S2BEG7)
+	);
+
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = S2MID0;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = S2MID1;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = S2MID2;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = S2MID3;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = S2MID4;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = S2MID5;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = S2MID6;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = S2MID7;
+// switch matrix multiplexer  S4BEG0 		MUX-8
+	assign S4BEG0_input = {J_NS2_END4,J_NS4_END12,J_NS4_END8,J_NS4_END4,J_NS4_END0,E6END4,EE4END12,E1END0};
+	cus_mux81_buf inst_cus_mux81_buf_S4BEG0 (
+	.A0 (S4BEG0_input[0]),
+	.A1 (S4BEG0_input[1]),
+	.A2 (S4BEG0_input[2]),
+	.A3 (S4BEG0_input[3]),
+	.A4 (S4BEG0_input[4]),
+	.A5 (S4BEG0_input[5]),
+	.A6 (S4BEG0_input[6]),
+	.A7 (S4BEG0_input[7]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.S2 (ConfigBits[60+2]),
+	.S2N (ConfigBits_N[60+2]),
+	.X (S4BEG0)
+	);
+
+// switch matrix multiplexer  S4BEG1 		MUX-8
+	assign S4BEG1_input = {J_NS2_END5,J_NS4_END13,J_NS4_END9,J_NS4_END5,J_NS4_END1,E6END5,EE4END13,E1END1};
+	cus_mux81_buf inst_cus_mux81_buf_S4BEG1 (
+	.A0 (S4BEG1_input[0]),
+	.A1 (S4BEG1_input[1]),
+	.A2 (S4BEG1_input[2]),
+	.A3 (S4BEG1_input[3]),
+	.A4 (S4BEG1_input[4]),
+	.A5 (S4BEG1_input[5]),
+	.A6 (S4BEG1_input[6]),
+	.A7 (S4BEG1_input[7]),
+	.S0 (ConfigBits[63+0]),
+	.S0N (ConfigBits_N[63+0]),
+	.S1 (ConfigBits[63+1]),
+	.S1N (ConfigBits_N[63+1]),
+	.S2 (ConfigBits[63+2]),
+	.S2N (ConfigBits_N[63+2]),
+	.X (S4BEG1)
+	);
+
+// switch matrix multiplexer  S4BEG2 		MUX-8
+	assign S4BEG2_input = {J_NS2_END6,J_NS4_END14,J_NS4_END10,J_NS4_END6,J_NS4_END2,E6END6,EE4END14,E1END2};
+	cus_mux81_buf inst_cus_mux81_buf_S4BEG2 (
+	.A0 (S4BEG2_input[0]),
+	.A1 (S4BEG2_input[1]),
+	.A2 (S4BEG2_input[2]),
+	.A3 (S4BEG2_input[3]),
+	.A4 (S4BEG2_input[4]),
+	.A5 (S4BEG2_input[5]),
+	.A6 (S4BEG2_input[6]),
+	.A7 (S4BEG2_input[7]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.S2 (ConfigBits[66+2]),
+	.S2N (ConfigBits_N[66+2]),
+	.X (S4BEG2)
+	);
+
+// switch matrix multiplexer  S4BEG3 		MUX-8
+	assign S4BEG3_input = {J_NS2_END7,J_NS4_END15,J_NS4_END11,J_NS4_END7,J_NS4_END3,E6END7,EE4END15,E1END3};
+	cus_mux81_buf inst_cus_mux81_buf_S4BEG3 (
+	.A0 (S4BEG3_input[0]),
+	.A1 (S4BEG3_input[1]),
+	.A2 (S4BEG3_input[2]),
+	.A3 (S4BEG3_input[3]),
+	.A4 (S4BEG3_input[4]),
+	.A5 (S4BEG3_input[5]),
+	.A6 (S4BEG3_input[6]),
+	.A7 (S4BEG3_input[7]),
+	.S0 (ConfigBits[69+0]),
+	.S0N (ConfigBits_N[69+0]),
+	.S1 (ConfigBits[69+1]),
+	.S1N (ConfigBits_N[69+1]),
+	.S2 (ConfigBits[69+2]),
+	.S2N (ConfigBits_N[69+2]),
+	.X (S4BEG3)
+	);
+
+// switch matrix multiplexer  W1BEG0 		MUX-4
+	assign W1BEG0_input = {RAM2FAB_D1_O3,RAM2FAB_D0_O2,S1END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG0 (
+	.A0 (W1BEG0_input[0]),
+	.A1 (W1BEG0_input[1]),
+	.A2 (W1BEG0_input[2]),
+	.A3 (W1BEG0_input[3]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.X (W1BEG0)
+	);
+
+// switch matrix multiplexer  W1BEG1 		MUX-4
+	assign W1BEG1_input = {RAM2FAB_D1_O2,RAM2FAB_D0_O3,S1END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG1 (
+	.A0 (W1BEG1_input[0]),
+	.A1 (W1BEG1_input[1]),
+	.A2 (W1BEG1_input[2]),
+	.A3 (W1BEG1_input[3]),
+	.S0 (ConfigBits[74+0]),
+	.S0N (ConfigBits_N[74+0]),
+	.S1 (ConfigBits[74+1]),
+	.S1N (ConfigBits_N[74+1]),
+	.X (W1BEG1)
+	);
+
+// switch matrix multiplexer  W1BEG2 		MUX-4
+	assign W1BEG2_input = {RAM2FAB_D1_O1,RAM2FAB_D0_O0,S1END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG2 (
+	.A0 (W1BEG2_input[0]),
+	.A1 (W1BEG2_input[1]),
+	.A2 (W1BEG2_input[2]),
+	.A3 (W1BEG2_input[3]),
+	.S0 (ConfigBits[76+0]),
+	.S0N (ConfigBits_N[76+0]),
+	.S1 (ConfigBits[76+1]),
+	.S1N (ConfigBits_N[76+1]),
+	.X (W1BEG2)
+	);
+
+// switch matrix multiplexer  W1BEG3 		MUX-4
+	assign W1BEG3_input = {RAM2FAB_D1_O0,RAM2FAB_D0_O1,S1END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG3 (
+	.A0 (W1BEG3_input[0]),
+	.A1 (W1BEG3_input[1]),
+	.A2 (W1BEG3_input[2]),
+	.A3 (W1BEG3_input[3]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.X (W1BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG0 		MUX-4
+	assign W2BEG0_input = {J_NS2_END7,J_NS2_END0,RAM2FAB_D2_O0,RAM2FAB_D0_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG0 (
+	.A0 (W2BEG0_input[0]),
+	.A1 (W2BEG0_input[1]),
+	.A2 (W2BEG0_input[2]),
+	.A3 (W2BEG0_input[3]),
+	.S0 (ConfigBits[80+0]),
+	.S0N (ConfigBits_N[80+0]),
+	.S1 (ConfigBits[80+1]),
+	.S1N (ConfigBits_N[80+1]),
+	.X (W2BEG0)
+	);
+
+// switch matrix multiplexer  W2BEG1 		MUX-4
+	assign W2BEG1_input = {J_NS2_END6,J_NS2_END1,RAM2FAB_D2_O1,RAM2FAB_D0_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG1 (
+	.A0 (W2BEG1_input[0]),
+	.A1 (W2BEG1_input[1]),
+	.A2 (W2BEG1_input[2]),
+	.A3 (W2BEG1_input[3]),
+	.S0 (ConfigBits[82+0]),
+	.S0N (ConfigBits_N[82+0]),
+	.S1 (ConfigBits[82+1]),
+	.S1N (ConfigBits_N[82+1]),
+	.X (W2BEG1)
+	);
+
+// switch matrix multiplexer  W2BEG2 		MUX-4
+	assign W2BEG2_input = {J_NS2_END5,J_NS2_END2,RAM2FAB_D2_O2,RAM2FAB_D0_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG2 (
+	.A0 (W2BEG2_input[0]),
+	.A1 (W2BEG2_input[1]),
+	.A2 (W2BEG2_input[2]),
+	.A3 (W2BEG2_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (W2BEG2)
+	);
+
+// switch matrix multiplexer  W2BEG3 		MUX-4
+	assign W2BEG3_input = {J_NS2_END4,J_NS2_END3,RAM2FAB_D2_O3,RAM2FAB_D0_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG3 (
+	.A0 (W2BEG3_input[0]),
+	.A1 (W2BEG3_input[1]),
+	.A2 (W2BEG3_input[2]),
+	.A3 (W2BEG3_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (W2BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG4 		MUX-4
+	assign W2BEG4_input = {J_NS2_END4,J_NS2_END3,RAM2FAB_D3_O0,RAM2FAB_D1_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG4 (
+	.A0 (W2BEG4_input[0]),
+	.A1 (W2BEG4_input[1]),
+	.A2 (W2BEG4_input[2]),
+	.A3 (W2BEG4_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (W2BEG4)
+	);
+
+// switch matrix multiplexer  W2BEG5 		MUX-4
+	assign W2BEG5_input = {J_NS2_END5,J_NS2_END2,RAM2FAB_D3_O1,RAM2FAB_D1_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG5 (
+	.A0 (W2BEG5_input[0]),
+	.A1 (W2BEG5_input[1]),
+	.A2 (W2BEG5_input[2]),
+	.A3 (W2BEG5_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (W2BEG5)
+	);
+
+// switch matrix multiplexer  W2BEG6 		MUX-4
+	assign W2BEG6_input = {J_NS2_END6,J_NS2_END1,RAM2FAB_D3_O2,RAM2FAB_D1_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG6 (
+	.A0 (W2BEG6_input[0]),
+	.A1 (W2BEG6_input[1]),
+	.A2 (W2BEG6_input[2]),
+	.A3 (W2BEG6_input[3]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.X (W2BEG6)
+	);
+
+// switch matrix multiplexer  W2BEG7 		MUX-4
+	assign W2BEG7_input = {J_NS2_END7,J_NS2_END0,RAM2FAB_D3_O3,RAM2FAB_D1_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEG7 (
+	.A0 (W2BEG7_input[0]),
+	.A1 (W2BEG7_input[1]),
+	.A2 (W2BEG7_input[2]),
+	.A3 (W2BEG7_input[3]),
+	.S0 (ConfigBits[94+0]),
+	.S0N (ConfigBits_N[94+0]),
+	.S1 (ConfigBits[94+1]),
+	.S1N (ConfigBits_N[94+1]),
+	.X (W2BEG7)
+	);
+
+// switch matrix multiplexer  W2BEGb0 		MUX-4
+	assign W2BEGb0_input = {J_NS2_END7,J_NS2_END0,RAM2FAB_D2_O0,RAM2FAB_D0_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb0 (
+	.A0 (W2BEGb0_input[0]),
+	.A1 (W2BEGb0_input[1]),
+	.A2 (W2BEGb0_input[2]),
+	.A3 (W2BEGb0_input[3]),
+	.S0 (ConfigBits[96+0]),
+	.S0N (ConfigBits_N[96+0]),
+	.S1 (ConfigBits[96+1]),
+	.S1N (ConfigBits_N[96+1]),
+	.X (W2BEGb0)
+	);
+
+// switch matrix multiplexer  W2BEGb1 		MUX-4
+	assign W2BEGb1_input = {J_NS2_END6,J_NS2_END1,RAM2FAB_D2_O1,RAM2FAB_D0_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb1 (
+	.A0 (W2BEGb1_input[0]),
+	.A1 (W2BEGb1_input[1]),
+	.A2 (W2BEGb1_input[2]),
+	.A3 (W2BEGb1_input[3]),
+	.S0 (ConfigBits[98+0]),
+	.S0N (ConfigBits_N[98+0]),
+	.S1 (ConfigBits[98+1]),
+	.S1N (ConfigBits_N[98+1]),
+	.X (W2BEGb1)
+	);
+
+// switch matrix multiplexer  W2BEGb2 		MUX-4
+	assign W2BEGb2_input = {J_NS2_END5,J_NS2_END2,RAM2FAB_D2_O2,RAM2FAB_D0_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb2 (
+	.A0 (W2BEGb2_input[0]),
+	.A1 (W2BEGb2_input[1]),
+	.A2 (W2BEGb2_input[2]),
+	.A3 (W2BEGb2_input[3]),
+	.S0 (ConfigBits[100+0]),
+	.S0N (ConfigBits_N[100+0]),
+	.S1 (ConfigBits[100+1]),
+	.S1N (ConfigBits_N[100+1]),
+	.X (W2BEGb2)
+	);
+
+// switch matrix multiplexer  W2BEGb3 		MUX-4
+	assign W2BEGb3_input = {J_NS2_END4,J_NS2_END3,RAM2FAB_D2_O3,RAM2FAB_D0_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb3 (
+	.A0 (W2BEGb3_input[0]),
+	.A1 (W2BEGb3_input[1]),
+	.A2 (W2BEGb3_input[2]),
+	.A3 (W2BEGb3_input[3]),
+	.S0 (ConfigBits[102+0]),
+	.S0N (ConfigBits_N[102+0]),
+	.S1 (ConfigBits[102+1]),
+	.S1N (ConfigBits_N[102+1]),
+	.X (W2BEGb3)
+	);
+
+// switch matrix multiplexer  W2BEGb4 		MUX-4
+	assign W2BEGb4_input = {J_NS2_END4,J_NS2_END3,RAM2FAB_D3_O0,RAM2FAB_D1_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb4 (
+	.A0 (W2BEGb4_input[0]),
+	.A1 (W2BEGb4_input[1]),
+	.A2 (W2BEGb4_input[2]),
+	.A3 (W2BEGb4_input[3]),
+	.S0 (ConfigBits[104+0]),
+	.S0N (ConfigBits_N[104+0]),
+	.S1 (ConfigBits[104+1]),
+	.S1N (ConfigBits_N[104+1]),
+	.X (W2BEGb4)
+	);
+
+// switch matrix multiplexer  W2BEGb5 		MUX-4
+	assign W2BEGb5_input = {J_NS2_END5,J_NS2_END2,RAM2FAB_D3_O1,RAM2FAB_D1_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb5 (
+	.A0 (W2BEGb5_input[0]),
+	.A1 (W2BEGb5_input[1]),
+	.A2 (W2BEGb5_input[2]),
+	.A3 (W2BEGb5_input[3]),
+	.S0 (ConfigBits[106+0]),
+	.S0N (ConfigBits_N[106+0]),
+	.S1 (ConfigBits[106+1]),
+	.S1N (ConfigBits_N[106+1]),
+	.X (W2BEGb5)
+	);
+
+// switch matrix multiplexer  W2BEGb6 		MUX-4
+	assign W2BEGb6_input = {J_NS2_END6,J_NS2_END1,RAM2FAB_D3_O2,RAM2FAB_D1_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb6 (
+	.A0 (W2BEGb6_input[0]),
+	.A1 (W2BEGb6_input[1]),
+	.A2 (W2BEGb6_input[2]),
+	.A3 (W2BEGb6_input[3]),
+	.S0 (ConfigBits[108+0]),
+	.S0N (ConfigBits_N[108+0]),
+	.S1 (ConfigBits[108+1]),
+	.S1N (ConfigBits_N[108+1]),
+	.X (W2BEGb6)
+	);
+
+// switch matrix multiplexer  W2BEGb7 		MUX-4
+	assign W2BEGb7_input = {J_NS2_END7,J_NS2_END0,RAM2FAB_D3_O3,RAM2FAB_D1_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W2BEGb7 (
+	.A0 (W2BEGb7_input[0]),
+	.A1 (W2BEGb7_input[1]),
+	.A2 (W2BEGb7_input[2]),
+	.A3 (W2BEGb7_input[3]),
+	.S0 (ConfigBits[110+0]),
+	.S0N (ConfigBits_N[110+0]),
+	.S1 (ConfigBits[110+1]),
+	.S1N (ConfigBits_N[110+1]),
+	.X (W2BEGb7)
+	);
+
+// switch matrix multiplexer  WW4BEG0 		MUX-4
+	assign WW4BEG0_input = {J_NS2_END7,J_NS4_END15,RAM2FAB_D3_O0,RAM2FAB_D0_O0};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG0 (
+	.A0 (WW4BEG0_input[0]),
+	.A1 (WW4BEG0_input[1]),
+	.A2 (WW4BEG0_input[2]),
+	.A3 (WW4BEG0_input[3]),
+	.S0 (ConfigBits[112+0]),
+	.S0N (ConfigBits_N[112+0]),
+	.S1 (ConfigBits[112+1]),
+	.S1N (ConfigBits_N[112+1]),
+	.X (WW4BEG0)
+	);
+
+// switch matrix multiplexer  WW4BEG1 		MUX-4
+	assign WW4BEG1_input = {J_NS2_END6,J_NS4_END14,RAM2FAB_D3_O1,RAM2FAB_D0_O1};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG1 (
+	.A0 (WW4BEG1_input[0]),
+	.A1 (WW4BEG1_input[1]),
+	.A2 (WW4BEG1_input[2]),
+	.A3 (WW4BEG1_input[3]),
+	.S0 (ConfigBits[114+0]),
+	.S0N (ConfigBits_N[114+0]),
+	.S1 (ConfigBits[114+1]),
+	.S1N (ConfigBits_N[114+1]),
+	.X (WW4BEG1)
+	);
+
+// switch matrix multiplexer  WW4BEG2 		MUX-4
+	assign WW4BEG2_input = {J_NS2_END5,J_NS4_END13,RAM2FAB_D3_O2,RAM2FAB_D0_O2};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG2 (
+	.A0 (WW4BEG2_input[0]),
+	.A1 (WW4BEG2_input[1]),
+	.A2 (WW4BEG2_input[2]),
+	.A3 (WW4BEG2_input[3]),
+	.S0 (ConfigBits[116+0]),
+	.S0N (ConfigBits_N[116+0]),
+	.S1 (ConfigBits[116+1]),
+	.S1N (ConfigBits_N[116+1]),
+	.X (WW4BEG2)
+	);
+
+// switch matrix multiplexer  WW4BEG3 		MUX-4
+	assign WW4BEG3_input = {J_NS2_END4,J_NS4_END12,RAM2FAB_D3_O3,RAM2FAB_D0_O3};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG3 (
+	.A0 (WW4BEG3_input[0]),
+	.A1 (WW4BEG3_input[1]),
+	.A2 (WW4BEG3_input[2]),
+	.A3 (WW4BEG3_input[3]),
+	.S0 (ConfigBits[118+0]),
+	.S0N (ConfigBits_N[118+0]),
+	.S1 (ConfigBits[118+1]),
+	.S1N (ConfigBits_N[118+1]),
+	.X (WW4BEG3)
+	);
+
+// switch matrix multiplexer  WW4BEG4 		MUX-4
+	assign WW4BEG4_input = {J_NS2_END3,J_NS4_END11,RAM2FAB_D2_O0,RAM2FAB_D1_O0};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG4 (
+	.A0 (WW4BEG4_input[0]),
+	.A1 (WW4BEG4_input[1]),
+	.A2 (WW4BEG4_input[2]),
+	.A3 (WW4BEG4_input[3]),
+	.S0 (ConfigBits[120+0]),
+	.S0N (ConfigBits_N[120+0]),
+	.S1 (ConfigBits[120+1]),
+	.S1N (ConfigBits_N[120+1]),
+	.X (WW4BEG4)
+	);
+
+// switch matrix multiplexer  WW4BEG5 		MUX-4
+	assign WW4BEG5_input = {J_NS2_END2,J_NS4_END10,RAM2FAB_D2_O1,RAM2FAB_D1_O1};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG5 (
+	.A0 (WW4BEG5_input[0]),
+	.A1 (WW4BEG5_input[1]),
+	.A2 (WW4BEG5_input[2]),
+	.A3 (WW4BEG5_input[3]),
+	.S0 (ConfigBits[122+0]),
+	.S0N (ConfigBits_N[122+0]),
+	.S1 (ConfigBits[122+1]),
+	.S1N (ConfigBits_N[122+1]),
+	.X (WW4BEG5)
+	);
+
+// switch matrix multiplexer  WW4BEG6 		MUX-4
+	assign WW4BEG6_input = {J_NS2_END1,J_NS4_END9,RAM2FAB_D2_O2,RAM2FAB_D1_O2};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG6 (
+	.A0 (WW4BEG6_input[0]),
+	.A1 (WW4BEG6_input[1]),
+	.A2 (WW4BEG6_input[2]),
+	.A3 (WW4BEG6_input[3]),
+	.S0 (ConfigBits[124+0]),
+	.S0N (ConfigBits_N[124+0]),
+	.S1 (ConfigBits[124+1]),
+	.S1N (ConfigBits_N[124+1]),
+	.X (WW4BEG6)
+	);
+
+// switch matrix multiplexer  WW4BEG7 		MUX-4
+	assign WW4BEG7_input = {J_NS2_END0,J_NS4_END8,RAM2FAB_D2_O3,RAM2FAB_D1_O3};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG7 (
+	.A0 (WW4BEG7_input[0]),
+	.A1 (WW4BEG7_input[1]),
+	.A2 (WW4BEG7_input[2]),
+	.A3 (WW4BEG7_input[3]),
+	.S0 (ConfigBits[126+0]),
+	.S0N (ConfigBits_N[126+0]),
+	.S1 (ConfigBits[126+1]),
+	.S1N (ConfigBits_N[126+1]),
+	.X (WW4BEG7)
+	);
+
+// switch matrix multiplexer  WW4BEG8 		MUX-4
+	assign WW4BEG8_input = {J_NS2_END7,J_NS4_END7,RAM2FAB_D2_O0,RAM2FAB_D1_O0};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG8 (
+	.A0 (WW4BEG8_input[0]),
+	.A1 (WW4BEG8_input[1]),
+	.A2 (WW4BEG8_input[2]),
+	.A3 (WW4BEG8_input[3]),
+	.S0 (ConfigBits[128+0]),
+	.S0N (ConfigBits_N[128+0]),
+	.S1 (ConfigBits[128+1]),
+	.S1N (ConfigBits_N[128+1]),
+	.X (WW4BEG8)
+	);
+
+// switch matrix multiplexer  WW4BEG9 		MUX-4
+	assign WW4BEG9_input = {J_NS2_END6,J_NS4_END6,RAM2FAB_D2_O1,RAM2FAB_D1_O1};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG9 (
+	.A0 (WW4BEG9_input[0]),
+	.A1 (WW4BEG9_input[1]),
+	.A2 (WW4BEG9_input[2]),
+	.A3 (WW4BEG9_input[3]),
+	.S0 (ConfigBits[130+0]),
+	.S0N (ConfigBits_N[130+0]),
+	.S1 (ConfigBits[130+1]),
+	.S1N (ConfigBits_N[130+1]),
+	.X (WW4BEG9)
+	);
+
+// switch matrix multiplexer  WW4BEG10 		MUX-4
+	assign WW4BEG10_input = {J_NS2_END5,J_NS4_END5,RAM2FAB_D2_O2,RAM2FAB_D1_O2};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG10 (
+	.A0 (WW4BEG10_input[0]),
+	.A1 (WW4BEG10_input[1]),
+	.A2 (WW4BEG10_input[2]),
+	.A3 (WW4BEG10_input[3]),
+	.S0 (ConfigBits[132+0]),
+	.S0N (ConfigBits_N[132+0]),
+	.S1 (ConfigBits[132+1]),
+	.S1N (ConfigBits_N[132+1]),
+	.X (WW4BEG10)
+	);
+
+// switch matrix multiplexer  WW4BEG11 		MUX-4
+	assign WW4BEG11_input = {J_NS2_END4,J_NS4_END4,RAM2FAB_D2_O3,RAM2FAB_D1_O3};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG11 (
+	.A0 (WW4BEG11_input[0]),
+	.A1 (WW4BEG11_input[1]),
+	.A2 (WW4BEG11_input[2]),
+	.A3 (WW4BEG11_input[3]),
+	.S0 (ConfigBits[134+0]),
+	.S0N (ConfigBits_N[134+0]),
+	.S1 (ConfigBits[134+1]),
+	.S1N (ConfigBits_N[134+1]),
+	.X (WW4BEG11)
+	);
+
+// switch matrix multiplexer  WW4BEG12 		MUX-4
+	assign WW4BEG12_input = {J_NS2_END3,J_NS4_END3,RAM2FAB_D3_O0,RAM2FAB_D0_O0};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG12 (
+	.A0 (WW4BEG12_input[0]),
+	.A1 (WW4BEG12_input[1]),
+	.A2 (WW4BEG12_input[2]),
+	.A3 (WW4BEG12_input[3]),
+	.S0 (ConfigBits[136+0]),
+	.S0N (ConfigBits_N[136+0]),
+	.S1 (ConfigBits[136+1]),
+	.S1N (ConfigBits_N[136+1]),
+	.X (WW4BEG12)
+	);
+
+// switch matrix multiplexer  WW4BEG13 		MUX-4
+	assign WW4BEG13_input = {J_NS2_END2,J_NS4_END2,RAM2FAB_D3_O1,RAM2FAB_D0_O1};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG13 (
+	.A0 (WW4BEG13_input[0]),
+	.A1 (WW4BEG13_input[1]),
+	.A2 (WW4BEG13_input[2]),
+	.A3 (WW4BEG13_input[3]),
+	.S0 (ConfigBits[138+0]),
+	.S0N (ConfigBits_N[138+0]),
+	.S1 (ConfigBits[138+1]),
+	.S1N (ConfigBits_N[138+1]),
+	.X (WW4BEG13)
+	);
+
+// switch matrix multiplexer  WW4BEG14 		MUX-4
+	assign WW4BEG14_input = {J_NS2_END1,J_NS4_END1,RAM2FAB_D3_O2,RAM2FAB_D0_O2};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG14 (
+	.A0 (WW4BEG14_input[0]),
+	.A1 (WW4BEG14_input[1]),
+	.A2 (WW4BEG14_input[2]),
+	.A3 (WW4BEG14_input[3]),
+	.S0 (ConfigBits[140+0]),
+	.S0N (ConfigBits_N[140+0]),
+	.S1 (ConfigBits[140+1]),
+	.S1N (ConfigBits_N[140+1]),
+	.X (WW4BEG14)
+	);
+
+// switch matrix multiplexer  WW4BEG15 		MUX-4
+	assign WW4BEG15_input = {J_NS2_END0,J_NS4_END0,RAM2FAB_D3_O3,RAM2FAB_D0_O3};
+	cus_mux41_buf inst_cus_mux41_buf_WW4BEG15 (
+	.A0 (WW4BEG15_input[0]),
+	.A1 (WW4BEG15_input[1]),
+	.A2 (WW4BEG15_input[2]),
+	.A3 (WW4BEG15_input[3]),
+	.S0 (ConfigBits[142+0]),
+	.S0N (ConfigBits_N[142+0]),
+	.S1 (ConfigBits[142+1]),
+	.S1N (ConfigBits_N[142+1]),
+	.X (WW4BEG15)
+	);
+
+// switch matrix multiplexer  W6BEG0 		MUX-4
+	assign W6BEG0_input = {J_NS4_END15,J_NS4_END11,S4END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG0 (
+	.A0 (W6BEG0_input[0]),
+	.A1 (W6BEG0_input[1]),
+	.A2 (W6BEG0_input[2]),
+	.A3 (W6BEG0_input[3]),
+	.S0 (ConfigBits[144+0]),
+	.S0N (ConfigBits_N[144+0]),
+	.S1 (ConfigBits[144+1]),
+	.S1N (ConfigBits_N[144+1]),
+	.X (W6BEG0)
+	);
+
+// switch matrix multiplexer  W6BEG1 		MUX-4
+	assign W6BEG1_input = {J_NS4_END14,J_NS4_END10,S4END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG1 (
+	.A0 (W6BEG1_input[0]),
+	.A1 (W6BEG1_input[1]),
+	.A2 (W6BEG1_input[2]),
+	.A3 (W6BEG1_input[3]),
+	.S0 (ConfigBits[146+0]),
+	.S0N (ConfigBits_N[146+0]),
+	.S1 (ConfigBits[146+1]),
+	.S1N (ConfigBits_N[146+1]),
+	.X (W6BEG1)
+	);
+
+// switch matrix multiplexer  W6BEG2 		MUX-4
+	assign W6BEG2_input = {J_NS4_END13,J_NS4_END9,S4END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG2 (
+	.A0 (W6BEG2_input[0]),
+	.A1 (W6BEG2_input[1]),
+	.A2 (W6BEG2_input[2]),
+	.A3 (W6BEG2_input[3]),
+	.S0 (ConfigBits[148+0]),
+	.S0N (ConfigBits_N[148+0]),
+	.S1 (ConfigBits[148+1]),
+	.S1N (ConfigBits_N[148+1]),
+	.X (W6BEG2)
+	);
+
+// switch matrix multiplexer  W6BEG3 		MUX-4
+	assign W6BEG3_input = {J_NS4_END12,J_NS4_END8,S4END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG3 (
+	.A0 (W6BEG3_input[0]),
+	.A1 (W6BEG3_input[1]),
+	.A2 (W6BEG3_input[2]),
+	.A3 (W6BEG3_input[3]),
+	.S0 (ConfigBits[150+0]),
+	.S0N (ConfigBits_N[150+0]),
+	.S1 (ConfigBits[150+1]),
+	.S1N (ConfigBits_N[150+1]),
+	.X (W6BEG3)
+	);
+
+// switch matrix multiplexer  W6BEG4 		MUX-4
+	assign W6BEG4_input = {J_NS2_END0,J_NS4_END11,J_NS4_END7,RAM2FAB_D1_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG4 (
+	.A0 (W6BEG4_input[0]),
+	.A1 (W6BEG4_input[1]),
+	.A2 (W6BEG4_input[2]),
+	.A3 (W6BEG4_input[3]),
+	.S0 (ConfigBits[152+0]),
+	.S0N (ConfigBits_N[152+0]),
+	.S1 (ConfigBits[152+1]),
+	.S1N (ConfigBits_N[152+1]),
+	.X (W6BEG4)
+	);
+
+// switch matrix multiplexer  W6BEG5 		MUX-4
+	assign W6BEG5_input = {J_NS2_END1,J_NS4_END10,J_NS4_END6,RAM2FAB_D1_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG5 (
+	.A0 (W6BEG5_input[0]),
+	.A1 (W6BEG5_input[1]),
+	.A2 (W6BEG5_input[2]),
+	.A3 (W6BEG5_input[3]),
+	.S0 (ConfigBits[154+0]),
+	.S0N (ConfigBits_N[154+0]),
+	.S1 (ConfigBits[154+1]),
+	.S1N (ConfigBits_N[154+1]),
+	.X (W6BEG5)
+	);
+
+// switch matrix multiplexer  W6BEG6 		MUX-4
+	assign W6BEG6_input = {J_NS2_END2,J_NS4_END9,J_NS4_END5,RAM2FAB_D1_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG6 (
+	.A0 (W6BEG6_input[0]),
+	.A1 (W6BEG6_input[1]),
+	.A2 (W6BEG6_input[2]),
+	.A3 (W6BEG6_input[3]),
+	.S0 (ConfigBits[156+0]),
+	.S0N (ConfigBits_N[156+0]),
+	.S1 (ConfigBits[156+1]),
+	.S1N (ConfigBits_N[156+1]),
+	.X (W6BEG6)
+	);
+
+// switch matrix multiplexer  W6BEG7 		MUX-4
+	assign W6BEG7_input = {J_NS2_END3,J_NS4_END8,J_NS4_END4,RAM2FAB_D1_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG7 (
+	.A0 (W6BEG7_input[0]),
+	.A1 (W6BEG7_input[1]),
+	.A2 (W6BEG7_input[2]),
+	.A3 (W6BEG7_input[3]),
+	.S0 (ConfigBits[158+0]),
+	.S0N (ConfigBits_N[158+0]),
+	.S1 (ConfigBits[158+1]),
+	.S1N (ConfigBits_N[158+1]),
+	.X (W6BEG7)
+	);
+
+// switch matrix multiplexer  W6BEG8 		MUX-4
+	assign W6BEG8_input = {J_NS2_END4,J_NS4_END7,J_NS4_END3,RAM2FAB_D0_O0};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG8 (
+	.A0 (W6BEG8_input[0]),
+	.A1 (W6BEG8_input[1]),
+	.A2 (W6BEG8_input[2]),
+	.A3 (W6BEG8_input[3]),
+	.S0 (ConfigBits[160+0]),
+	.S0N (ConfigBits_N[160+0]),
+	.S1 (ConfigBits[160+1]),
+	.S1N (ConfigBits_N[160+1]),
+	.X (W6BEG8)
+	);
+
+// switch matrix multiplexer  W6BEG9 		MUX-4
+	assign W6BEG9_input = {J_NS2_END5,J_NS4_END6,J_NS4_END2,RAM2FAB_D0_O1};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG9 (
+	.A0 (W6BEG9_input[0]),
+	.A1 (W6BEG9_input[1]),
+	.A2 (W6BEG9_input[2]),
+	.A3 (W6BEG9_input[3]),
+	.S0 (ConfigBits[162+0]),
+	.S0N (ConfigBits_N[162+0]),
+	.S1 (ConfigBits[162+1]),
+	.S1N (ConfigBits_N[162+1]),
+	.X (W6BEG9)
+	);
+
+// switch matrix multiplexer  W6BEG10 		MUX-4
+	assign W6BEG10_input = {J_NS2_END6,J_NS4_END5,J_NS4_END1,RAM2FAB_D0_O2};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG10 (
+	.A0 (W6BEG10_input[0]),
+	.A1 (W6BEG10_input[1]),
+	.A2 (W6BEG10_input[2]),
+	.A3 (W6BEG10_input[3]),
+	.S0 (ConfigBits[164+0]),
+	.S0N (ConfigBits_N[164+0]),
+	.S1 (ConfigBits[164+1]),
+	.S1N (ConfigBits_N[164+1]),
+	.X (W6BEG10)
+	);
+
+// switch matrix multiplexer  W6BEG11 		MUX-4
+	assign W6BEG11_input = {J_NS2_END7,J_NS4_END4,J_NS4_END0,RAM2FAB_D0_O3};
+	cus_mux41_buf inst_cus_mux41_buf_W6BEG11 (
+	.A0 (W6BEG11_input[0]),
+	.A1 (W6BEG11_input[1]),
+	.A2 (W6BEG11_input[2]),
+	.A3 (W6BEG11_input[3]),
+	.S0 (ConfigBits[166+0]),
+	.S0N (ConfigBits_N[166+0]),
+	.S1 (ConfigBits[166+1]),
+	.S1N (ConfigBits_N[166+1]),
+	.X (W6BEG11)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D0_I0 		MUX-4
+	assign FAB2RAM_D0_I0_input = {J_NS4_END0,E6END0,EE4END8,EE4END0};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D0_I0 (
+	.A0 (FAB2RAM_D0_I0_input[0]),
+	.A1 (FAB2RAM_D0_I0_input[1]),
+	.A2 (FAB2RAM_D0_I0_input[2]),
+	.A3 (FAB2RAM_D0_I0_input[3]),
+	.S0 (ConfigBits[168+0]),
+	.S0N (ConfigBits_N[168+0]),
+	.S1 (ConfigBits[168+1]),
+	.S1N (ConfigBits_N[168+1]),
+	.X (FAB2RAM_D0_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D0_I1 		MUX-4
+	assign FAB2RAM_D0_I1_input = {J_NS4_END1,E6END1,EE4END9,EE4END1};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D0_I1 (
+	.A0 (FAB2RAM_D0_I1_input[0]),
+	.A1 (FAB2RAM_D0_I1_input[1]),
+	.A2 (FAB2RAM_D0_I1_input[2]),
+	.A3 (FAB2RAM_D0_I1_input[3]),
+	.S0 (ConfigBits[170+0]),
+	.S0N (ConfigBits_N[170+0]),
+	.S1 (ConfigBits[170+1]),
+	.S1N (ConfigBits_N[170+1]),
+	.X (FAB2RAM_D0_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D0_I2 		MUX-4
+	assign FAB2RAM_D0_I2_input = {J_NS4_END2,E6END2,EE4END10,EE4END2};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D0_I2 (
+	.A0 (FAB2RAM_D0_I2_input[0]),
+	.A1 (FAB2RAM_D0_I2_input[1]),
+	.A2 (FAB2RAM_D0_I2_input[2]),
+	.A3 (FAB2RAM_D0_I2_input[3]),
+	.S0 (ConfigBits[172+0]),
+	.S0N (ConfigBits_N[172+0]),
+	.S1 (ConfigBits[172+1]),
+	.S1N (ConfigBits_N[172+1]),
+	.X (FAB2RAM_D0_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D0_I3 		MUX-4
+	assign FAB2RAM_D0_I3_input = {J_NS4_END3,E6END3,EE4END11,EE4END3};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D0_I3 (
+	.A0 (FAB2RAM_D0_I3_input[0]),
+	.A1 (FAB2RAM_D0_I3_input[1]),
+	.A2 (FAB2RAM_D0_I3_input[2]),
+	.A3 (FAB2RAM_D0_I3_input[3]),
+	.S0 (ConfigBits[174+0]),
+	.S0N (ConfigBits_N[174+0]),
+	.S1 (ConfigBits[174+1]),
+	.S1N (ConfigBits_N[174+1]),
+	.X (FAB2RAM_D0_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D1_I0 		MUX-4
+	assign FAB2RAM_D1_I0_input = {J_NS4_END4,E6END4,EE4END12,EE4END4};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D1_I0 (
+	.A0 (FAB2RAM_D1_I0_input[0]),
+	.A1 (FAB2RAM_D1_I0_input[1]),
+	.A2 (FAB2RAM_D1_I0_input[2]),
+	.A3 (FAB2RAM_D1_I0_input[3]),
+	.S0 (ConfigBits[176+0]),
+	.S0N (ConfigBits_N[176+0]),
+	.S1 (ConfigBits[176+1]),
+	.S1N (ConfigBits_N[176+1]),
+	.X (FAB2RAM_D1_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D1_I1 		MUX-4
+	assign FAB2RAM_D1_I1_input = {J_NS4_END5,E6END5,EE4END13,EE4END5};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D1_I1 (
+	.A0 (FAB2RAM_D1_I1_input[0]),
+	.A1 (FAB2RAM_D1_I1_input[1]),
+	.A2 (FAB2RAM_D1_I1_input[2]),
+	.A3 (FAB2RAM_D1_I1_input[3]),
+	.S0 (ConfigBits[178+0]),
+	.S0N (ConfigBits_N[178+0]),
+	.S1 (ConfigBits[178+1]),
+	.S1N (ConfigBits_N[178+1]),
+	.X (FAB2RAM_D1_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D1_I2 		MUX-4
+	assign FAB2RAM_D1_I2_input = {J_NS4_END6,E6END6,EE4END14,EE4END6};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D1_I2 (
+	.A0 (FAB2RAM_D1_I2_input[0]),
+	.A1 (FAB2RAM_D1_I2_input[1]),
+	.A2 (FAB2RAM_D1_I2_input[2]),
+	.A3 (FAB2RAM_D1_I2_input[3]),
+	.S0 (ConfigBits[180+0]),
+	.S0N (ConfigBits_N[180+0]),
+	.S1 (ConfigBits[180+1]),
+	.S1N (ConfigBits_N[180+1]),
+	.X (FAB2RAM_D1_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D1_I3 		MUX-4
+	assign FAB2RAM_D1_I3_input = {J_NS4_END7,E6END7,EE4END15,EE4END7};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D1_I3 (
+	.A0 (FAB2RAM_D1_I3_input[0]),
+	.A1 (FAB2RAM_D1_I3_input[1]),
+	.A2 (FAB2RAM_D1_I3_input[2]),
+	.A3 (FAB2RAM_D1_I3_input[3]),
+	.S0 (ConfigBits[182+0]),
+	.S0N (ConfigBits_N[182+0]),
+	.S1 (ConfigBits[182+1]),
+	.S1N (ConfigBits_N[182+1]),
+	.X (FAB2RAM_D1_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D2_I0 		MUX-4
+	assign FAB2RAM_D2_I0_input = {J_NS4_END8,E6END8,EE4END8,EE4END0};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D2_I0 (
+	.A0 (FAB2RAM_D2_I0_input[0]),
+	.A1 (FAB2RAM_D2_I0_input[1]),
+	.A2 (FAB2RAM_D2_I0_input[2]),
+	.A3 (FAB2RAM_D2_I0_input[3]),
+	.S0 (ConfigBits[184+0]),
+	.S0N (ConfigBits_N[184+0]),
+	.S1 (ConfigBits[184+1]),
+	.S1N (ConfigBits_N[184+1]),
+	.X (FAB2RAM_D2_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D2_I1 		MUX-4
+	assign FAB2RAM_D2_I1_input = {J_NS4_END9,E6END9,EE4END9,EE4END1};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D2_I1 (
+	.A0 (FAB2RAM_D2_I1_input[0]),
+	.A1 (FAB2RAM_D2_I1_input[1]),
+	.A2 (FAB2RAM_D2_I1_input[2]),
+	.A3 (FAB2RAM_D2_I1_input[3]),
+	.S0 (ConfigBits[186+0]),
+	.S0N (ConfigBits_N[186+0]),
+	.S1 (ConfigBits[186+1]),
+	.S1N (ConfigBits_N[186+1]),
+	.X (FAB2RAM_D2_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D2_I2 		MUX-4
+	assign FAB2RAM_D2_I2_input = {J_NS4_END10,E6END10,EE4END10,EE4END2};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D2_I2 (
+	.A0 (FAB2RAM_D2_I2_input[0]),
+	.A1 (FAB2RAM_D2_I2_input[1]),
+	.A2 (FAB2RAM_D2_I2_input[2]),
+	.A3 (FAB2RAM_D2_I2_input[3]),
+	.S0 (ConfigBits[188+0]),
+	.S0N (ConfigBits_N[188+0]),
+	.S1 (ConfigBits[188+1]),
+	.S1N (ConfigBits_N[188+1]),
+	.X (FAB2RAM_D2_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D2_I3 		MUX-4
+	assign FAB2RAM_D2_I3_input = {J_NS4_END11,E6END11,EE4END11,EE4END3};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D2_I3 (
+	.A0 (FAB2RAM_D2_I3_input[0]),
+	.A1 (FAB2RAM_D2_I3_input[1]),
+	.A2 (FAB2RAM_D2_I3_input[2]),
+	.A3 (FAB2RAM_D2_I3_input[3]),
+	.S0 (ConfigBits[190+0]),
+	.S0N (ConfigBits_N[190+0]),
+	.S1 (ConfigBits[190+1]),
+	.S1N (ConfigBits_N[190+1]),
+	.X (FAB2RAM_D2_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D3_I0 		MUX-4
+	assign FAB2RAM_D3_I0_input = {J_NS4_END12,EE4END12,EE4END4,E1END0};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D3_I0 (
+	.A0 (FAB2RAM_D3_I0_input[0]),
+	.A1 (FAB2RAM_D3_I0_input[1]),
+	.A2 (FAB2RAM_D3_I0_input[2]),
+	.A3 (FAB2RAM_D3_I0_input[3]),
+	.S0 (ConfigBits[192+0]),
+	.S0N (ConfigBits_N[192+0]),
+	.S1 (ConfigBits[192+1]),
+	.S1N (ConfigBits_N[192+1]),
+	.X (FAB2RAM_D3_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D3_I1 		MUX-4
+	assign FAB2RAM_D3_I1_input = {J_NS4_END13,EE4END13,EE4END5,E1END1};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D3_I1 (
+	.A0 (FAB2RAM_D3_I1_input[0]),
+	.A1 (FAB2RAM_D3_I1_input[1]),
+	.A2 (FAB2RAM_D3_I1_input[2]),
+	.A3 (FAB2RAM_D3_I1_input[3]),
+	.S0 (ConfigBits[194+0]),
+	.S0N (ConfigBits_N[194+0]),
+	.S1 (ConfigBits[194+1]),
+	.S1N (ConfigBits_N[194+1]),
+	.X (FAB2RAM_D3_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D3_I2 		MUX-4
+	assign FAB2RAM_D3_I2_input = {J_NS4_END14,EE4END14,EE4END6,E1END2};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D3_I2 (
+	.A0 (FAB2RAM_D3_I2_input[0]),
+	.A1 (FAB2RAM_D3_I2_input[1]),
+	.A2 (FAB2RAM_D3_I2_input[2]),
+	.A3 (FAB2RAM_D3_I2_input[3]),
+	.S0 (ConfigBits[196+0]),
+	.S0N (ConfigBits_N[196+0]),
+	.S1 (ConfigBits[196+1]),
+	.S1N (ConfigBits_N[196+1]),
+	.X (FAB2RAM_D3_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_D3_I3 		MUX-4
+	assign FAB2RAM_D3_I3_input = {J_NS4_END15,EE4END15,EE4END7,E1END3};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_D3_I3 (
+	.A0 (FAB2RAM_D3_I3_input[0]),
+	.A1 (FAB2RAM_D3_I3_input[1]),
+	.A2 (FAB2RAM_D3_I3_input[2]),
+	.A3 (FAB2RAM_D3_I3_input[3]),
+	.S0 (ConfigBits[198+0]),
+	.S0N (ConfigBits_N[198+0]),
+	.S1 (ConfigBits[198+1]),
+	.S1N (ConfigBits_N[198+1]),
+	.X (FAB2RAM_D3_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A0_I0 		MUX-4
+	assign FAB2RAM_A0_I0_input = {GND0,J_NS2_END0,E2END0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A0_I0 (
+	.A0 (FAB2RAM_A0_I0_input[0]),
+	.A1 (FAB2RAM_A0_I0_input[1]),
+	.A2 (FAB2RAM_A0_I0_input[2]),
+	.A3 (FAB2RAM_A0_I0_input[3]),
+	.S0 (ConfigBits[200+0]),
+	.S0N (ConfigBits_N[200+0]),
+	.S1 (ConfigBits[200+1]),
+	.S1N (ConfigBits_N[200+1]),
+	.X (FAB2RAM_A0_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A0_I1 		MUX-4
+	assign FAB2RAM_A0_I1_input = {GND0,J_NS2_END1,E2END1,E2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A0_I1 (
+	.A0 (FAB2RAM_A0_I1_input[0]),
+	.A1 (FAB2RAM_A0_I1_input[1]),
+	.A2 (FAB2RAM_A0_I1_input[2]),
+	.A3 (FAB2RAM_A0_I1_input[3]),
+	.S0 (ConfigBits[202+0]),
+	.S0N (ConfigBits_N[202+0]),
+	.S1 (ConfigBits[202+1]),
+	.S1N (ConfigBits_N[202+1]),
+	.X (FAB2RAM_A0_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A0_I2 		MUX-4
+	assign FAB2RAM_A0_I2_input = {GND0,J_NS2_END2,E2END2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A0_I2 (
+	.A0 (FAB2RAM_A0_I2_input[0]),
+	.A1 (FAB2RAM_A0_I2_input[1]),
+	.A2 (FAB2RAM_A0_I2_input[2]),
+	.A3 (FAB2RAM_A0_I2_input[3]),
+	.S0 (ConfigBits[204+0]),
+	.S0N (ConfigBits_N[204+0]),
+	.S1 (ConfigBits[204+1]),
+	.S1N (ConfigBits_N[204+1]),
+	.X (FAB2RAM_A0_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A0_I3 		MUX-4
+	assign FAB2RAM_A0_I3_input = {GND0,J_NS2_END3,E2END3,E2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A0_I3 (
+	.A0 (FAB2RAM_A0_I3_input[0]),
+	.A1 (FAB2RAM_A0_I3_input[1]),
+	.A2 (FAB2RAM_A0_I3_input[2]),
+	.A3 (FAB2RAM_A0_I3_input[3]),
+	.S0 (ConfigBits[206+0]),
+	.S0N (ConfigBits_N[206+0]),
+	.S1 (ConfigBits[206+1]),
+	.S1N (ConfigBits_N[206+1]),
+	.X (FAB2RAM_A0_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A1_I0 		MUX-4
+	assign FAB2RAM_A1_I0_input = {GND0,J_NS2_END4,E2END4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A1_I0 (
+	.A0 (FAB2RAM_A1_I0_input[0]),
+	.A1 (FAB2RAM_A1_I0_input[1]),
+	.A2 (FAB2RAM_A1_I0_input[2]),
+	.A3 (FAB2RAM_A1_I0_input[3]),
+	.S0 (ConfigBits[208+0]),
+	.S0N (ConfigBits_N[208+0]),
+	.S1 (ConfigBits[208+1]),
+	.S1N (ConfigBits_N[208+1]),
+	.X (FAB2RAM_A1_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A1_I1 		MUX-4
+	assign FAB2RAM_A1_I1_input = {GND0,J_NS2_END5,E2END5,E2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A1_I1 (
+	.A0 (FAB2RAM_A1_I1_input[0]),
+	.A1 (FAB2RAM_A1_I1_input[1]),
+	.A2 (FAB2RAM_A1_I1_input[2]),
+	.A3 (FAB2RAM_A1_I1_input[3]),
+	.S0 (ConfigBits[210+0]),
+	.S0N (ConfigBits_N[210+0]),
+	.S1 (ConfigBits[210+1]),
+	.S1N (ConfigBits_N[210+1]),
+	.X (FAB2RAM_A1_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A1_I2 		MUX-4
+	assign FAB2RAM_A1_I2_input = {GND0,J_NS2_END6,E2END6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A1_I2 (
+	.A0 (FAB2RAM_A1_I2_input[0]),
+	.A1 (FAB2RAM_A1_I2_input[1]),
+	.A2 (FAB2RAM_A1_I2_input[2]),
+	.A3 (FAB2RAM_A1_I2_input[3]),
+	.S0 (ConfigBits[212+0]),
+	.S0N (ConfigBits_N[212+0]),
+	.S1 (ConfigBits[212+1]),
+	.S1N (ConfigBits_N[212+1]),
+	.X (FAB2RAM_A1_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_A1_I3 		MUX-4
+	assign FAB2RAM_A1_I3_input = {GND0,J_NS2_END7,E2END7,E2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_A1_I3 (
+	.A0 (FAB2RAM_A1_I3_input[0]),
+	.A1 (FAB2RAM_A1_I3_input[1]),
+	.A2 (FAB2RAM_A1_I3_input[2]),
+	.A3 (FAB2RAM_A1_I3_input[3]),
+	.S0 (ConfigBits[214+0]),
+	.S0N (ConfigBits_N[214+0]),
+	.S1 (ConfigBits[214+1]),
+	.S1N (ConfigBits_N[214+1]),
+	.X (FAB2RAM_A1_I3)
+	);
+
+// switch matrix multiplexer  FAB2RAM_C_I0 		MUX-4
+	assign FAB2RAM_C_I0_input = {GND0,J_NS1_END0,E6END0,E1END0};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_C_I0 (
+	.A0 (FAB2RAM_C_I0_input[0]),
+	.A1 (FAB2RAM_C_I0_input[1]),
+	.A2 (FAB2RAM_C_I0_input[2]),
+	.A3 (FAB2RAM_C_I0_input[3]),
+	.S0 (ConfigBits[216+0]),
+	.S0N (ConfigBits_N[216+0]),
+	.S1 (ConfigBits[216+1]),
+	.S1N (ConfigBits_N[216+1]),
+	.X (FAB2RAM_C_I0)
+	);
+
+// switch matrix multiplexer  FAB2RAM_C_I1 		MUX-4
+	assign FAB2RAM_C_I1_input = {GND0,J_NS1_END1,E6END1,E1END1};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_C_I1 (
+	.A0 (FAB2RAM_C_I1_input[0]),
+	.A1 (FAB2RAM_C_I1_input[1]),
+	.A2 (FAB2RAM_C_I1_input[2]),
+	.A3 (FAB2RAM_C_I1_input[3]),
+	.S0 (ConfigBits[218+0]),
+	.S0N (ConfigBits_N[218+0]),
+	.S1 (ConfigBits[218+1]),
+	.S1N (ConfigBits_N[218+1]),
+	.X (FAB2RAM_C_I1)
+	);
+
+// switch matrix multiplexer  FAB2RAM_C_I2 		MUX-4
+	assign FAB2RAM_C_I2_input = {GND0,J_NS1_END2,E6END2,E1END2};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_C_I2 (
+	.A0 (FAB2RAM_C_I2_input[0]),
+	.A1 (FAB2RAM_C_I2_input[1]),
+	.A2 (FAB2RAM_C_I2_input[2]),
+	.A3 (FAB2RAM_C_I2_input[3]),
+	.S0 (ConfigBits[220+0]),
+	.S0N (ConfigBits_N[220+0]),
+	.S1 (ConfigBits[220+1]),
+	.S1N (ConfigBits_N[220+1]),
+	.X (FAB2RAM_C_I2)
+	);
+
+// switch matrix multiplexer  FAB2RAM_C_I3 		MUX-4
+	assign FAB2RAM_C_I3_input = {GND0,J_NS1_END3,E6END3,E1END3};
+	cus_mux41_buf inst_cus_mux41_buf_FAB2RAM_C_I3 (
+	.A0 (FAB2RAM_C_I3_input[0]),
+	.A1 (FAB2RAM_C_I3_input[1]),
+	.A2 (FAB2RAM_C_I3_input[2]),
+	.A3 (FAB2RAM_C_I3_input[3]),
+	.S0 (ConfigBits[222+0]),
+	.S0N (ConfigBits_N[222+0]),
+	.S1 (ConfigBits[222+1]),
+	.S1N (ConfigBits_N[222+1]),
+	.X (FAB2RAM_C_I3)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG0 		MUX-4
+	assign J_NS4_BEG0_input = {S4END0,S1END0,N4END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG0 (
+	.A0 (J_NS4_BEG0_input[0]),
+	.A1 (J_NS4_BEG0_input[1]),
+	.A2 (J_NS4_BEG0_input[2]),
+	.A3 (J_NS4_BEG0_input[3]),
+	.S0 (ConfigBits[224+0]),
+	.S0N (ConfigBits_N[224+0]),
+	.S1 (ConfigBits[224+1]),
+	.S1N (ConfigBits_N[224+1]),
+	.X (J_NS4_BEG0)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG1 		MUX-4
+	assign J_NS4_BEG1_input = {S4END1,S1END1,N4END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG1 (
+	.A0 (J_NS4_BEG1_input[0]),
+	.A1 (J_NS4_BEG1_input[1]),
+	.A2 (J_NS4_BEG1_input[2]),
+	.A3 (J_NS4_BEG1_input[3]),
+	.S0 (ConfigBits[226+0]),
+	.S0N (ConfigBits_N[226+0]),
+	.S1 (ConfigBits[226+1]),
+	.S1N (ConfigBits_N[226+1]),
+	.X (J_NS4_BEG1)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG2 		MUX-4
+	assign J_NS4_BEG2_input = {S4END2,S1END2,N4END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG2 (
+	.A0 (J_NS4_BEG2_input[0]),
+	.A1 (J_NS4_BEG2_input[1]),
+	.A2 (J_NS4_BEG2_input[2]),
+	.A3 (J_NS4_BEG2_input[3]),
+	.S0 (ConfigBits[228+0]),
+	.S0N (ConfigBits_N[228+0]),
+	.S1 (ConfigBits[228+1]),
+	.S1N (ConfigBits_N[228+1]),
+	.X (J_NS4_BEG2)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG3 		MUX-4
+	assign J_NS4_BEG3_input = {S4END3,S1END3,N4END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG3 (
+	.A0 (J_NS4_BEG3_input[0]),
+	.A1 (J_NS4_BEG3_input[1]),
+	.A2 (J_NS4_BEG3_input[2]),
+	.A3 (J_NS4_BEG3_input[3]),
+	.S0 (ConfigBits[230+0]),
+	.S0N (ConfigBits_N[230+0]),
+	.S1 (ConfigBits[230+1]),
+	.S1N (ConfigBits_N[230+1]),
+	.X (J_NS4_BEG3)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG4 		MUX-4
+	assign J_NS4_BEG4_input = {S4END0,S1END0,N4END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG4 (
+	.A0 (J_NS4_BEG4_input[0]),
+	.A1 (J_NS4_BEG4_input[1]),
+	.A2 (J_NS4_BEG4_input[2]),
+	.A3 (J_NS4_BEG4_input[3]),
+	.S0 (ConfigBits[232+0]),
+	.S0N (ConfigBits_N[232+0]),
+	.S1 (ConfigBits[232+1]),
+	.S1N (ConfigBits_N[232+1]),
+	.X (J_NS4_BEG4)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG5 		MUX-4
+	assign J_NS4_BEG5_input = {S4END1,S1END1,N4END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG5 (
+	.A0 (J_NS4_BEG5_input[0]),
+	.A1 (J_NS4_BEG5_input[1]),
+	.A2 (J_NS4_BEG5_input[2]),
+	.A3 (J_NS4_BEG5_input[3]),
+	.S0 (ConfigBits[234+0]),
+	.S0N (ConfigBits_N[234+0]),
+	.S1 (ConfigBits[234+1]),
+	.S1N (ConfigBits_N[234+1]),
+	.X (J_NS4_BEG5)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG6 		MUX-4
+	assign J_NS4_BEG6_input = {S4END2,S1END2,N4END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG6 (
+	.A0 (J_NS4_BEG6_input[0]),
+	.A1 (J_NS4_BEG6_input[1]),
+	.A2 (J_NS4_BEG6_input[2]),
+	.A3 (J_NS4_BEG6_input[3]),
+	.S0 (ConfigBits[236+0]),
+	.S0N (ConfigBits_N[236+0]),
+	.S1 (ConfigBits[236+1]),
+	.S1N (ConfigBits_N[236+1]),
+	.X (J_NS4_BEG6)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG7 		MUX-4
+	assign J_NS4_BEG7_input = {S4END3,S1END3,N4END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG7 (
+	.A0 (J_NS4_BEG7_input[0]),
+	.A1 (J_NS4_BEG7_input[1]),
+	.A2 (J_NS4_BEG7_input[2]),
+	.A3 (J_NS4_BEG7_input[3]),
+	.S0 (ConfigBits[238+0]),
+	.S0N (ConfigBits_N[238+0]),
+	.S1 (ConfigBits[238+1]),
+	.S1N (ConfigBits_N[238+1]),
+	.X (J_NS4_BEG7)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG8 		MUX-4
+	assign J_NS4_BEG8_input = {S4END0,S1END0,N4END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG8 (
+	.A0 (J_NS4_BEG8_input[0]),
+	.A1 (J_NS4_BEG8_input[1]),
+	.A2 (J_NS4_BEG8_input[2]),
+	.A3 (J_NS4_BEG8_input[3]),
+	.S0 (ConfigBits[240+0]),
+	.S0N (ConfigBits_N[240+0]),
+	.S1 (ConfigBits[240+1]),
+	.S1N (ConfigBits_N[240+1]),
+	.X (J_NS4_BEG8)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG9 		MUX-4
+	assign J_NS4_BEG9_input = {S4END1,S1END1,N4END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG9 (
+	.A0 (J_NS4_BEG9_input[0]),
+	.A1 (J_NS4_BEG9_input[1]),
+	.A2 (J_NS4_BEG9_input[2]),
+	.A3 (J_NS4_BEG9_input[3]),
+	.S0 (ConfigBits[242+0]),
+	.S0N (ConfigBits_N[242+0]),
+	.S1 (ConfigBits[242+1]),
+	.S1N (ConfigBits_N[242+1]),
+	.X (J_NS4_BEG9)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG10 		MUX-4
+	assign J_NS4_BEG10_input = {S4END2,S1END2,N4END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG10 (
+	.A0 (J_NS4_BEG10_input[0]),
+	.A1 (J_NS4_BEG10_input[1]),
+	.A2 (J_NS4_BEG10_input[2]),
+	.A3 (J_NS4_BEG10_input[3]),
+	.S0 (ConfigBits[244+0]),
+	.S0N (ConfigBits_N[244+0]),
+	.S1 (ConfigBits[244+1]),
+	.S1N (ConfigBits_N[244+1]),
+	.X (J_NS4_BEG10)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG11 		MUX-4
+	assign J_NS4_BEG11_input = {S4END3,S1END3,N4END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG11 (
+	.A0 (J_NS4_BEG11_input[0]),
+	.A1 (J_NS4_BEG11_input[1]),
+	.A2 (J_NS4_BEG11_input[2]),
+	.A3 (J_NS4_BEG11_input[3]),
+	.S0 (ConfigBits[246+0]),
+	.S0N (ConfigBits_N[246+0]),
+	.S1 (ConfigBits[246+1]),
+	.S1N (ConfigBits_N[246+1]),
+	.X (J_NS4_BEG11)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG12 		MUX-4
+	assign J_NS4_BEG12_input = {S4END0,S1END0,N4END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG12 (
+	.A0 (J_NS4_BEG12_input[0]),
+	.A1 (J_NS4_BEG12_input[1]),
+	.A2 (J_NS4_BEG12_input[2]),
+	.A3 (J_NS4_BEG12_input[3]),
+	.S0 (ConfigBits[248+0]),
+	.S0N (ConfigBits_N[248+0]),
+	.S1 (ConfigBits[248+1]),
+	.S1N (ConfigBits_N[248+1]),
+	.X (J_NS4_BEG12)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG13 		MUX-4
+	assign J_NS4_BEG13_input = {S4END1,S1END1,N4END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG13 (
+	.A0 (J_NS4_BEG13_input[0]),
+	.A1 (J_NS4_BEG13_input[1]),
+	.A2 (J_NS4_BEG13_input[2]),
+	.A3 (J_NS4_BEG13_input[3]),
+	.S0 (ConfigBits[250+0]),
+	.S0N (ConfigBits_N[250+0]),
+	.S1 (ConfigBits[250+1]),
+	.S1N (ConfigBits_N[250+1]),
+	.X (J_NS4_BEG13)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG14 		MUX-4
+	assign J_NS4_BEG14_input = {S4END2,S1END2,N4END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG14 (
+	.A0 (J_NS4_BEG14_input[0]),
+	.A1 (J_NS4_BEG14_input[1]),
+	.A2 (J_NS4_BEG14_input[2]),
+	.A3 (J_NS4_BEG14_input[3]),
+	.S0 (ConfigBits[252+0]),
+	.S0N (ConfigBits_N[252+0]),
+	.S1 (ConfigBits[252+1]),
+	.S1N (ConfigBits_N[252+1]),
+	.X (J_NS4_BEG14)
+	);
+
+// switch matrix multiplexer  J_NS4_BEG15 		MUX-4
+	assign J_NS4_BEG15_input = {S4END3,S1END3,N4END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS4_BEG15 (
+	.A0 (J_NS4_BEG15_input[0]),
+	.A1 (J_NS4_BEG15_input[1]),
+	.A2 (J_NS4_BEG15_input[2]),
+	.A3 (J_NS4_BEG15_input[3]),
+	.S0 (ConfigBits[254+0]),
+	.S0N (ConfigBits_N[254+0]),
+	.S1 (ConfigBits[254+1]),
+	.S1N (ConfigBits_N[254+1]),
+	.X (J_NS4_BEG15)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG0 		MUX-4
+	assign J_NS2_BEG0_input = {S2END0,S2MID0,N2END0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG0 (
+	.A0 (J_NS2_BEG0_input[0]),
+	.A1 (J_NS2_BEG0_input[1]),
+	.A2 (J_NS2_BEG0_input[2]),
+	.A3 (J_NS2_BEG0_input[3]),
+	.S0 (ConfigBits[256+0]),
+	.S0N (ConfigBits_N[256+0]),
+	.S1 (ConfigBits[256+1]),
+	.S1N (ConfigBits_N[256+1]),
+	.X (J_NS2_BEG0)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG1 		MUX-4
+	assign J_NS2_BEG1_input = {S2END1,S2MID1,N2END1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG1 (
+	.A0 (J_NS2_BEG1_input[0]),
+	.A1 (J_NS2_BEG1_input[1]),
+	.A2 (J_NS2_BEG1_input[2]),
+	.A3 (J_NS2_BEG1_input[3]),
+	.S0 (ConfigBits[258+0]),
+	.S0N (ConfigBits_N[258+0]),
+	.S1 (ConfigBits[258+1]),
+	.S1N (ConfigBits_N[258+1]),
+	.X (J_NS2_BEG1)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG2 		MUX-4
+	assign J_NS2_BEG2_input = {S2END2,S2MID2,N2END2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG2 (
+	.A0 (J_NS2_BEG2_input[0]),
+	.A1 (J_NS2_BEG2_input[1]),
+	.A2 (J_NS2_BEG2_input[2]),
+	.A3 (J_NS2_BEG2_input[3]),
+	.S0 (ConfigBits[260+0]),
+	.S0N (ConfigBits_N[260+0]),
+	.S1 (ConfigBits[260+1]),
+	.S1N (ConfigBits_N[260+1]),
+	.X (J_NS2_BEG2)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG3 		MUX-4
+	assign J_NS2_BEG3_input = {S2END3,S2MID3,N2END3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG3 (
+	.A0 (J_NS2_BEG3_input[0]),
+	.A1 (J_NS2_BEG3_input[1]),
+	.A2 (J_NS2_BEG3_input[2]),
+	.A3 (J_NS2_BEG3_input[3]),
+	.S0 (ConfigBits[262+0]),
+	.S0N (ConfigBits_N[262+0]),
+	.S1 (ConfigBits[262+1]),
+	.S1N (ConfigBits_N[262+1]),
+	.X (J_NS2_BEG3)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG4 		MUX-4
+	assign J_NS2_BEG4_input = {S2END4,S2MID4,N2END4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG4 (
+	.A0 (J_NS2_BEG4_input[0]),
+	.A1 (J_NS2_BEG4_input[1]),
+	.A2 (J_NS2_BEG4_input[2]),
+	.A3 (J_NS2_BEG4_input[3]),
+	.S0 (ConfigBits[264+0]),
+	.S0N (ConfigBits_N[264+0]),
+	.S1 (ConfigBits[264+1]),
+	.S1N (ConfigBits_N[264+1]),
+	.X (J_NS2_BEG4)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG5 		MUX-4
+	assign J_NS2_BEG5_input = {S2END5,S2MID5,N2END5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG5 (
+	.A0 (J_NS2_BEG5_input[0]),
+	.A1 (J_NS2_BEG5_input[1]),
+	.A2 (J_NS2_BEG5_input[2]),
+	.A3 (J_NS2_BEG5_input[3]),
+	.S0 (ConfigBits[266+0]),
+	.S0N (ConfigBits_N[266+0]),
+	.S1 (ConfigBits[266+1]),
+	.S1N (ConfigBits_N[266+1]),
+	.X (J_NS2_BEG5)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG6 		MUX-4
+	assign J_NS2_BEG6_input = {S2END6,S2MID6,N2END6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG6 (
+	.A0 (J_NS2_BEG6_input[0]),
+	.A1 (J_NS2_BEG6_input[1]),
+	.A2 (J_NS2_BEG6_input[2]),
+	.A3 (J_NS2_BEG6_input[3]),
+	.S0 (ConfigBits[268+0]),
+	.S0N (ConfigBits_N[268+0]),
+	.S1 (ConfigBits[268+1]),
+	.S1N (ConfigBits_N[268+1]),
+	.X (J_NS2_BEG6)
+	);
+
+// switch matrix multiplexer  J_NS2_BEG7 		MUX-4
+	assign J_NS2_BEG7_input = {S2END7,S2MID7,N2END7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS2_BEG7 (
+	.A0 (J_NS2_BEG7_input[0]),
+	.A1 (J_NS2_BEG7_input[1]),
+	.A2 (J_NS2_BEG7_input[2]),
+	.A3 (J_NS2_BEG7_input[3]),
+	.S0 (ConfigBits[270+0]),
+	.S0N (ConfigBits_N[270+0]),
+	.S1 (ConfigBits[270+1]),
+	.S1N (ConfigBits_N[270+1]),
+	.X (J_NS2_BEG7)
+	);
+
+// switch matrix multiplexer  J_NS1_BEG0 		MUX-4
+	assign J_NS1_BEG0_input = {GND0,S1END0,E6END0,N1END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS1_BEG0 (
+	.A0 (J_NS1_BEG0_input[0]),
+	.A1 (J_NS1_BEG0_input[1]),
+	.A2 (J_NS1_BEG0_input[2]),
+	.A3 (J_NS1_BEG0_input[3]),
+	.S0 (ConfigBits[272+0]),
+	.S0N (ConfigBits_N[272+0]),
+	.S1 (ConfigBits[272+1]),
+	.S1N (ConfigBits_N[272+1]),
+	.X (J_NS1_BEG0)
+	);
+
+// switch matrix multiplexer  J_NS1_BEG1 		MUX-4
+	assign J_NS1_BEG1_input = {GND0,S1END1,E6END1,N1END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS1_BEG1 (
+	.A0 (J_NS1_BEG1_input[0]),
+	.A1 (J_NS1_BEG1_input[1]),
+	.A2 (J_NS1_BEG1_input[2]),
+	.A3 (J_NS1_BEG1_input[3]),
+	.S0 (ConfigBits[274+0]),
+	.S0N (ConfigBits_N[274+0]),
+	.S1 (ConfigBits[274+1]),
+	.S1N (ConfigBits_N[274+1]),
+	.X (J_NS1_BEG1)
+	);
+
+// switch matrix multiplexer  J_NS1_BEG2 		MUX-4
+	assign J_NS1_BEG2_input = {GND0,S1END2,E6END2,N1END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS1_BEG2 (
+	.A0 (J_NS1_BEG2_input[0]),
+	.A1 (J_NS1_BEG2_input[1]),
+	.A2 (J_NS1_BEG2_input[2]),
+	.A3 (J_NS1_BEG2_input[3]),
+	.S0 (ConfigBits[276+0]),
+	.S0N (ConfigBits_N[276+0]),
+	.S1 (ConfigBits[276+1]),
+	.S1N (ConfigBits_N[276+1]),
+	.X (J_NS1_BEG2)
+	);
+
+// switch matrix multiplexer  J_NS1_BEG3 		MUX-4
+	assign J_NS1_BEG3_input = {GND0,S1END3,E6END3,N1END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_NS1_BEG3 (
+	.A0 (J_NS1_BEG3_input[0]),
+	.A1 (J_NS1_BEG3_input[1]),
+	.A2 (J_NS1_BEG3_input[2]),
+	.A3 (J_NS1_BEG3_input[3]),
+	.S0 (ConfigBits[278+0]),
+	.S0N (ConfigBits_N[278+0]),
+	.S1 (ConfigBits[278+1]),
+	.S1N (ConfigBits_N[278+1]),
+	.X (J_NS1_BEG3)
+	);
+
+	assign DEBUG_select_N1BEG0 = ConfigBits[1:0];
+	assign DEBUG_select_N1BEG1 = ConfigBits[3:2];
+	assign DEBUG_select_N1BEG2 = ConfigBits[5:4];
+	assign DEBUG_select_N1BEG3 = ConfigBits[7:6];
+	assign DEBUG_select_N2BEG0 = ConfigBits[9:8];
+	assign DEBUG_select_N2BEG1 = ConfigBits[11:10];
+	assign DEBUG_select_N2BEG2 = ConfigBits[13:12];
+	assign DEBUG_select_N2BEG3 = ConfigBits[15:14];
+	assign DEBUG_select_N2BEG4 = ConfigBits[17:16];
+	assign DEBUG_select_N2BEG5 = ConfigBits[19:18];
+	assign DEBUG_select_N2BEG6 = ConfigBits[21:20];
+	assign DEBUG_select_N2BEG7 = ConfigBits[23:22];
+	assign DEBUG_select_N4BEG0 = ConfigBits[26:24];
+	assign DEBUG_select_N4BEG1 = ConfigBits[29:27];
+	assign DEBUG_select_N4BEG2 = ConfigBits[32:30];
+	assign DEBUG_select_N4BEG3 = ConfigBits[35:33];
+	assign DEBUG_select_S1BEG0 = ConfigBits[37:36];
+	assign DEBUG_select_S1BEG1 = ConfigBits[39:38];
+	assign DEBUG_select_S1BEG2 = ConfigBits[41:40];
+	assign DEBUG_select_S1BEG3 = ConfigBits[43:42];
+	assign DEBUG_select_S2BEG0 = ConfigBits[45:44];
+	assign DEBUG_select_S2BEG1 = ConfigBits[47:46];
+	assign DEBUG_select_S2BEG2 = ConfigBits[49:48];
+	assign DEBUG_select_S2BEG3 = ConfigBits[51:50];
+	assign DEBUG_select_S2BEG4 = ConfigBits[53:52];
+	assign DEBUG_select_S2BEG5 = ConfigBits[55:54];
+	assign DEBUG_select_S2BEG6 = ConfigBits[57:56];
+	assign DEBUG_select_S2BEG7 = ConfigBits[59:58];
+	assign DEBUG_select_S4BEG0 = ConfigBits[62:60];
+	assign DEBUG_select_S4BEG1 = ConfigBits[65:63];
+	assign DEBUG_select_S4BEG2 = ConfigBits[68:66];
+	assign DEBUG_select_S4BEG3 = ConfigBits[71:69];
+	assign DEBUG_select_W1BEG0 = ConfigBits[73:72];
+	assign DEBUG_select_W1BEG1 = ConfigBits[75:74];
+	assign DEBUG_select_W1BEG2 = ConfigBits[77:76];
+	assign DEBUG_select_W1BEG3 = ConfigBits[79:78];
+	assign DEBUG_select_W2BEG0 = ConfigBits[81:80];
+	assign DEBUG_select_W2BEG1 = ConfigBits[83:82];
+	assign DEBUG_select_W2BEG2 = ConfigBits[85:84];
+	assign DEBUG_select_W2BEG3 = ConfigBits[87:86];
+	assign DEBUG_select_W2BEG4 = ConfigBits[89:88];
+	assign DEBUG_select_W2BEG5 = ConfigBits[91:90];
+	assign DEBUG_select_W2BEG6 = ConfigBits[93:92];
+	assign DEBUG_select_W2BEG7 = ConfigBits[95:94];
+	assign DEBUG_select_W2BEGb0 = ConfigBits[97:96];
+	assign DEBUG_select_W2BEGb1 = ConfigBits[99:98];
+	assign DEBUG_select_W2BEGb2 = ConfigBits[101:100];
+	assign DEBUG_select_W2BEGb3 = ConfigBits[103:102];
+	assign DEBUG_select_W2BEGb4 = ConfigBits[105:104];
+	assign DEBUG_select_W2BEGb5 = ConfigBits[107:106];
+	assign DEBUG_select_W2BEGb6 = ConfigBits[109:108];
+	assign DEBUG_select_W2BEGb7 = ConfigBits[111:110];
+	assign DEBUG_select_WW4BEG0 = ConfigBits[113:112];
+	assign DEBUG_select_WW4BEG1 = ConfigBits[115:114];
+	assign DEBUG_select_WW4BEG2 = ConfigBits[117:116];
+	assign DEBUG_select_WW4BEG3 = ConfigBits[119:118];
+	assign DEBUG_select_WW4BEG4 = ConfigBits[121:120];
+	assign DEBUG_select_WW4BEG5 = ConfigBits[123:122];
+	assign DEBUG_select_WW4BEG6 = ConfigBits[125:124];
+	assign DEBUG_select_WW4BEG7 = ConfigBits[127:126];
+	assign DEBUG_select_WW4BEG8 = ConfigBits[129:128];
+	assign DEBUG_select_WW4BEG9 = ConfigBits[131:130];
+	assign DEBUG_select_WW4BEG10 = ConfigBits[133:132];
+	assign DEBUG_select_WW4BEG11 = ConfigBits[135:134];
+	assign DEBUG_select_WW4BEG12 = ConfigBits[137:136];
+	assign DEBUG_select_WW4BEG13 = ConfigBits[139:138];
+	assign DEBUG_select_WW4BEG14 = ConfigBits[141:140];
+	assign DEBUG_select_WW4BEG15 = ConfigBits[143:142];
+	assign DEBUG_select_W6BEG0 = ConfigBits[145:144];
+	assign DEBUG_select_W6BEG1 = ConfigBits[147:146];
+	assign DEBUG_select_W6BEG2 = ConfigBits[149:148];
+	assign DEBUG_select_W6BEG3 = ConfigBits[151:150];
+	assign DEBUG_select_W6BEG4 = ConfigBits[153:152];
+	assign DEBUG_select_W6BEG5 = ConfigBits[155:154];
+	assign DEBUG_select_W6BEG6 = ConfigBits[157:156];
+	assign DEBUG_select_W6BEG7 = ConfigBits[159:158];
+	assign DEBUG_select_W6BEG8 = ConfigBits[161:160];
+	assign DEBUG_select_W6BEG9 = ConfigBits[163:162];
+	assign DEBUG_select_W6BEG10 = ConfigBits[165:164];
+	assign DEBUG_select_W6BEG11 = ConfigBits[167:166];
+	assign DEBUG_select_FAB2RAM_D0_I0 = ConfigBits[169:168];
+	assign DEBUG_select_FAB2RAM_D0_I1 = ConfigBits[171:170];
+	assign DEBUG_select_FAB2RAM_D0_I2 = ConfigBits[173:172];
+	assign DEBUG_select_FAB2RAM_D0_I3 = ConfigBits[175:174];
+	assign DEBUG_select_FAB2RAM_D1_I0 = ConfigBits[177:176];
+	assign DEBUG_select_FAB2RAM_D1_I1 = ConfigBits[179:178];
+	assign DEBUG_select_FAB2RAM_D1_I2 = ConfigBits[181:180];
+	assign DEBUG_select_FAB2RAM_D1_I3 = ConfigBits[183:182];
+	assign DEBUG_select_FAB2RAM_D2_I0 = ConfigBits[185:184];
+	assign DEBUG_select_FAB2RAM_D2_I1 = ConfigBits[187:186];
+	assign DEBUG_select_FAB2RAM_D2_I2 = ConfigBits[189:188];
+	assign DEBUG_select_FAB2RAM_D2_I3 = ConfigBits[191:190];
+	assign DEBUG_select_FAB2RAM_D3_I0 = ConfigBits[193:192];
+	assign DEBUG_select_FAB2RAM_D3_I1 = ConfigBits[195:194];
+	assign DEBUG_select_FAB2RAM_D3_I2 = ConfigBits[197:196];
+	assign DEBUG_select_FAB2RAM_D3_I3 = ConfigBits[199:198];
+	assign DEBUG_select_FAB2RAM_A0_I0 = ConfigBits[201:200];
+	assign DEBUG_select_FAB2RAM_A0_I1 = ConfigBits[203:202];
+	assign DEBUG_select_FAB2RAM_A0_I2 = ConfigBits[205:204];
+	assign DEBUG_select_FAB2RAM_A0_I3 = ConfigBits[207:206];
+	assign DEBUG_select_FAB2RAM_A1_I0 = ConfigBits[209:208];
+	assign DEBUG_select_FAB2RAM_A1_I1 = ConfigBits[211:210];
+	assign DEBUG_select_FAB2RAM_A1_I2 = ConfigBits[213:212];
+	assign DEBUG_select_FAB2RAM_A1_I3 = ConfigBits[215:214];
+	assign DEBUG_select_FAB2RAM_C_I0 = ConfigBits[217:216];
+	assign DEBUG_select_FAB2RAM_C_I1 = ConfigBits[219:218];
+	assign DEBUG_select_FAB2RAM_C_I2 = ConfigBits[221:220];
+	assign DEBUG_select_FAB2RAM_C_I3 = ConfigBits[223:222];
+	assign DEBUG_select_J_NS4_BEG0 = ConfigBits[225:224];
+	assign DEBUG_select_J_NS4_BEG1 = ConfigBits[227:226];
+	assign DEBUG_select_J_NS4_BEG2 = ConfigBits[229:228];
+	assign DEBUG_select_J_NS4_BEG3 = ConfigBits[231:230];
+	assign DEBUG_select_J_NS4_BEG4 = ConfigBits[233:232];
+	assign DEBUG_select_J_NS4_BEG5 = ConfigBits[235:234];
+	assign DEBUG_select_J_NS4_BEG6 = ConfigBits[237:236];
+	assign DEBUG_select_J_NS4_BEG7 = ConfigBits[239:238];
+	assign DEBUG_select_J_NS4_BEG8 = ConfigBits[241:240];
+	assign DEBUG_select_J_NS4_BEG9 = ConfigBits[243:242];
+	assign DEBUG_select_J_NS4_BEG10 = ConfigBits[245:244];
+	assign DEBUG_select_J_NS4_BEG11 = ConfigBits[247:246];
+	assign DEBUG_select_J_NS4_BEG12 = ConfigBits[249:248];
+	assign DEBUG_select_J_NS4_BEG13 = ConfigBits[251:250];
+	assign DEBUG_select_J_NS4_BEG14 = ConfigBits[253:252];
+	assign DEBUG_select_J_NS4_BEG15 = ConfigBits[255:254];
+	assign DEBUG_select_J_NS2_BEG0 = ConfigBits[257:256];
+	assign DEBUG_select_J_NS2_BEG1 = ConfigBits[259:258];
+	assign DEBUG_select_J_NS2_BEG2 = ConfigBits[261:260];
+	assign DEBUG_select_J_NS2_BEG3 = ConfigBits[263:262];
+	assign DEBUG_select_J_NS2_BEG4 = ConfigBits[265:264];
+	assign DEBUG_select_J_NS2_BEG5 = ConfigBits[267:266];
+	assign DEBUG_select_J_NS2_BEG6 = ConfigBits[269:268];
+	assign DEBUG_select_J_NS2_BEG7 = ConfigBits[271:270];
+	assign DEBUG_select_J_NS1_BEG0 = ConfigBits[273:272];
+	assign DEBUG_select_J_NS1_BEG1 = ConfigBits[275:274];
+	assign DEBUG_select_J_NS1_BEG2 = ConfigBits[277:276];
+	assign DEBUG_select_J_NS1_BEG3 = ConfigBits[279:278];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RAM_IO_tile.v b/verilog/rtl/eFPGA_core/RAM_IO_tile.v
new file mode 100644
index 0000000..5cbbe32
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RAM_IO_tile.v
@@ -0,0 +1,1413 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module RAM_IO (N1BEG, N2BEG, N2BEGb, N4BEG, N1END, N2MID, N2END, N4END, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, S1END, S2MID, S2END, S4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, RAM2FAB_D0_I0, RAM2FAB_D0_I1, RAM2FAB_D0_I2, RAM2FAB_D0_I3, UserCLK, RAM2FAB_D1_I0, RAM2FAB_D1_I1, RAM2FAB_D1_I2, RAM2FAB_D1_I3, RAM2FAB_D2_I0, RAM2FAB_D2_I1, RAM2FAB_D2_I2, RAM2FAB_D2_I3, RAM2FAB_D3_I0, RAM2FAB_D3_I1, RAM2FAB_D3_I2, RAM2FAB_D3_I3, FAB2RAM_D0_O0, FAB2RAM_D0_O1, FAB2RAM_D0_O2, FAB2RAM_D0_O3, FAB2RAM_D1_O0, FAB2RAM_D1_O1, FAB2RAM_D1_O2, FAB2RAM_D1_O3, FAB2RAM_D2_O0, FAB2RAM_D2_O1, FAB2RAM_D2_O2, FAB2RAM_D2_O3, FAB2RAM_D3_O0, FAB2RAM_D3_O1, FAB2RAM_D3_O2, FAB2RAM_D3_O3, FAB2RAM_A0_O0, FAB2RAM_A0_O1, FAB2RAM_A0_O2, FAB2RAM_A0_O3, FAB2RAM_A1_O0, FAB2RAM_A1_O1, FAB2RAM_A1_O2, FAB2RAM_A1_O3, FAB2RAM_C_O0, FAB2RAM_C_O1, FAB2RAM_C_O2, FAB2RAM_C_O3, Config_accessC_bit0, Config_accessC_bit1, Config_accessC_bit2, Config_accessC_bit3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 328;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	//  EAST
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:NULL destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:NULL destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:NULL destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:NULL destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:NULL  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:NULL  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:NULL  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:NULL  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:NULL  
+	// Tile IO ports from BELs
+	input RAM2FAB_D0_I0;
+	input RAM2FAB_D0_I1;
+	input RAM2FAB_D0_I2;
+	input RAM2FAB_D0_I3;
+	input UserCLK;
+	input RAM2FAB_D1_I0;
+	input RAM2FAB_D1_I1;
+	input RAM2FAB_D1_I2;
+	input RAM2FAB_D1_I3;
+	input RAM2FAB_D2_I0;
+	input RAM2FAB_D2_I1;
+	input RAM2FAB_D2_I2;
+	input RAM2FAB_D2_I3;
+	input RAM2FAB_D3_I0;
+	input RAM2FAB_D3_I1;
+	input RAM2FAB_D3_I2;
+	input RAM2FAB_D3_I3;
+	output FAB2RAM_D0_O0;
+	output FAB2RAM_D0_O1;
+	output FAB2RAM_D0_O2;
+	output FAB2RAM_D0_O3;
+	output FAB2RAM_D1_O0;
+	output FAB2RAM_D1_O1;
+	output FAB2RAM_D1_O2;
+	output FAB2RAM_D1_O3;
+	output FAB2RAM_D2_O0;
+	output FAB2RAM_D2_O1;
+	output FAB2RAM_D2_O2;
+	output FAB2RAM_D2_O3;
+	output FAB2RAM_D3_O0;
+	output FAB2RAM_D3_O1;
+	output FAB2RAM_D3_O2;
+	output FAB2RAM_D3_O3;
+	output FAB2RAM_A0_O0;
+	output FAB2RAM_A0_O1;
+	output FAB2RAM_A0_O2;
+	output FAB2RAM_A0_O3;
+	output FAB2RAM_A1_O0;
+	output FAB2RAM_A1_O1;
+	output FAB2RAM_A1_O2;
+	output FAB2RAM_A1_O3;
+	output FAB2RAM_C_O0;
+	output FAB2RAM_C_O1;
+	output FAB2RAM_C_O2;
+	output FAB2RAM_C_O3;
+	output Config_accessC_bit0;
+	output Config_accessC_bit1;
+	output Config_accessC_bit2;
+	output Config_accessC_bit3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire FAB2RAM_D0_I0;
+	wire FAB2RAM_D0_I1;
+	wire FAB2RAM_D0_I2;
+	wire FAB2RAM_D0_I3;
+	wire FAB2RAM_D1_I0;
+	wire FAB2RAM_D1_I1;
+	wire FAB2RAM_D1_I2;
+	wire FAB2RAM_D1_I3;
+	wire FAB2RAM_D2_I0;
+	wire FAB2RAM_D2_I1;
+	wire FAB2RAM_D2_I2;
+	wire FAB2RAM_D2_I3;
+	wire FAB2RAM_D3_I0;
+	wire FAB2RAM_D3_I1;
+	wire FAB2RAM_D3_I2;
+	wire FAB2RAM_D3_I3;
+	wire FAB2RAM_A0_I0;
+	wire FAB2RAM_A0_I1;
+	wire FAB2RAM_A0_I2;
+	wire FAB2RAM_A0_I3;
+	wire FAB2RAM_A1_I0;
+	wire FAB2RAM_A1_I1;
+	wire FAB2RAM_A1_I2;
+	wire FAB2RAM_A1_I3;
+	wire FAB2RAM_C_I0;
+	wire FAB2RAM_C_I1;
+	wire FAB2RAM_C_I2;
+	wire FAB2RAM_C_I3;
+	wire RAM2FAB_D0_O0;
+	wire RAM2FAB_D0_O1;
+	wire RAM2FAB_D0_O2;
+	wire RAM2FAB_D0_O3;
+	wire RAM2FAB_D1_O0;
+	wire RAM2FAB_D1_O1;
+	wire RAM2FAB_D1_O2;
+	wire RAM2FAB_D1_O3;
+	wire RAM2FAB_D2_O0;
+	wire RAM2FAB_D2_O1;
+	wire RAM2FAB_D2_O2;
+	wire RAM2FAB_D2_O3;
+	wire RAM2FAB_D3_O0;
+	wire RAM2FAB_D3_O1;
+	wire RAM2FAB_D3_O2;
+	wire RAM2FAB_D3_O3;
+//jump wires
+	wire [16-1:0] J_NS4_BEG;
+	wire [8-1:0] J_NS2_BEG;
+	wire [4-1:0] J_NS1_BEG;
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	wire [15:0] N4END_i;
+	wire [11:0] N4BEG_i;
+	assign N4BEG_i[15-4:0] = N4END_i[15:4];
+
+	my_buf N4END_inbuf_0 (
+	.A(N4END[4]),
+	.X(N4END_i[4])
+	);
+
+	my_buf N4END_inbuf_1 (
+	.A(N4END[5]),
+	.X(N4END_i[5])
+	);
+
+	my_buf N4END_inbuf_2 (
+	.A(N4END[6]),
+	.X(N4END_i[6])
+	);
+
+	my_buf N4END_inbuf_3 (
+	.A(N4END[7]),
+	.X(N4END_i[7])
+	);
+
+	my_buf N4END_inbuf_4 (
+	.A(N4END[8]),
+	.X(N4END_i[8])
+	);
+
+	my_buf N4END_inbuf_5 (
+	.A(N4END[9]),
+	.X(N4END_i[9])
+	);
+
+	my_buf N4END_inbuf_6 (
+	.A(N4END[10]),
+	.X(N4END_i[10])
+	);
+
+	my_buf N4END_inbuf_7 (
+	.A(N4END[11]),
+	.X(N4END_i[11])
+	);
+
+	my_buf N4END_inbuf_8 (
+	.A(N4END[12]),
+	.X(N4END_i[12])
+	);
+
+	my_buf N4END_inbuf_9 (
+	.A(N4END[13]),
+	.X(N4END_i[13])
+	);
+
+	my_buf N4END_inbuf_10 (
+	.A(N4END[14]),
+	.X(N4END_i[14])
+	);
+
+	my_buf N4END_inbuf_11 (
+	.A(N4END[15]),
+	.X(N4END_i[15])
+	);
+
+	my_buf N4BEG_outbuf_0 (
+	.A(N4BEG_i[0]),
+	.X(N4BEG[0])
+	);
+
+	my_buf N4BEG_outbuf_1 (
+	.A(N4BEG_i[1]),
+	.X(N4BEG[1])
+	);
+
+	my_buf N4BEG_outbuf_2 (
+	.A(N4BEG_i[2]),
+	.X(N4BEG[2])
+	);
+
+	my_buf N4BEG_outbuf_3 (
+	.A(N4BEG_i[3]),
+	.X(N4BEG[3])
+	);
+
+	my_buf N4BEG_outbuf_4 (
+	.A(N4BEG_i[4]),
+	.X(N4BEG[4])
+	);
+
+	my_buf N4BEG_outbuf_5 (
+	.A(N4BEG_i[5]),
+	.X(N4BEG[5])
+	);
+
+	my_buf N4BEG_outbuf_6 (
+	.A(N4BEG_i[6]),
+	.X(N4BEG[6])
+	);
+
+	my_buf N4BEG_outbuf_7 (
+	.A(N4BEG_i[7]),
+	.X(N4BEG[7])
+	);
+
+	my_buf N4BEG_outbuf_8 (
+	.A(N4BEG_i[8]),
+	.X(N4BEG[8])
+	);
+
+	my_buf N4BEG_outbuf_9 (
+	.A(N4BEG_i[9]),
+	.X(N4BEG[9])
+	);
+
+	my_buf N4BEG_outbuf_10 (
+	.A(N4BEG_i[10]),
+	.X(N4BEG[10])
+	);
+
+	my_buf N4BEG_outbuf_11 (
+	.A(N4BEG_i[11]),
+	.X(N4BEG[11])
+	);
+
+	wire [15:0] S4END_i;
+	wire [11:0] S4BEG_i;
+	assign S4BEG_i[15-4:0] = S4END_i[15:4];
+
+	my_buf S4END_inbuf_0 (
+	.A(S4END[4]),
+	.X(S4END_i[4])
+	);
+
+	my_buf S4END_inbuf_1 (
+	.A(S4END[5]),
+	.X(S4END_i[5])
+	);
+
+	my_buf S4END_inbuf_2 (
+	.A(S4END[6]),
+	.X(S4END_i[6])
+	);
+
+	my_buf S4END_inbuf_3 (
+	.A(S4END[7]),
+	.X(S4END_i[7])
+	);
+
+	my_buf S4END_inbuf_4 (
+	.A(S4END[8]),
+	.X(S4END_i[8])
+	);
+
+	my_buf S4END_inbuf_5 (
+	.A(S4END[9]),
+	.X(S4END_i[9])
+	);
+
+	my_buf S4END_inbuf_6 (
+	.A(S4END[10]),
+	.X(S4END_i[10])
+	);
+
+	my_buf S4END_inbuf_7 (
+	.A(S4END[11]),
+	.X(S4END_i[11])
+	);
+
+	my_buf S4END_inbuf_8 (
+	.A(S4END[12]),
+	.X(S4END_i[12])
+	);
+
+	my_buf S4END_inbuf_9 (
+	.A(S4END[13]),
+	.X(S4END_i[13])
+	);
+
+	my_buf S4END_inbuf_10 (
+	.A(S4END[14]),
+	.X(S4END_i[14])
+	);
+
+	my_buf S4END_inbuf_11 (
+	.A(S4END[15]),
+	.X(S4END_i[15])
+	);
+
+	my_buf S4BEG_outbuf_0 (
+	.A(S4BEG_i[0]),
+	.X(S4BEG[0])
+	);
+
+	my_buf S4BEG_outbuf_1 (
+	.A(S4BEG_i[1]),
+	.X(S4BEG[1])
+	);
+
+	my_buf S4BEG_outbuf_2 (
+	.A(S4BEG_i[2]),
+	.X(S4BEG[2])
+	);
+
+	my_buf S4BEG_outbuf_3 (
+	.A(S4BEG_i[3]),
+	.X(S4BEG[3])
+	);
+
+	my_buf S4BEG_outbuf_4 (
+	.A(S4BEG_i[4]),
+	.X(S4BEG[4])
+	);
+
+	my_buf S4BEG_outbuf_5 (
+	.A(S4BEG_i[5]),
+	.X(S4BEG[5])
+	);
+
+	my_buf S4BEG_outbuf_6 (
+	.A(S4BEG_i[6]),
+	.X(S4BEG[6])
+	);
+
+	my_buf S4BEG_outbuf_7 (
+	.A(S4BEG_i[7]),
+	.X(S4BEG[7])
+	);
+
+	my_buf S4BEG_outbuf_8 (
+	.A(S4BEG_i[8]),
+	.X(S4BEG[8])
+	);
+
+	my_buf S4BEG_outbuf_9 (
+	.A(S4BEG_i[9]),
+	.X(S4BEG[9])
+	);
+
+	my_buf S4BEG_outbuf_10 (
+	.A(S4BEG_i[10]),
+	.X(S4BEG[10])
+	);
+
+	my_buf S4BEG_outbuf_11 (
+	.A(S4BEG_i[11]),
+	.X(S4BEG[11])
+	);
+
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	RAM_IO_ConfigMem Inst_RAM_IO_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	InPass4_frame_config Inst_RAM2FAB_D0_InPass4_frame_config (
+	.O0(RAM2FAB_D0_O0),
+	.O1(RAM2FAB_D0_O1),
+	.O2(RAM2FAB_D0_O2),
+	.O3(RAM2FAB_D0_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(RAM2FAB_D0_I0),
+	.I1(RAM2FAB_D0_I1),
+	.I2(RAM2FAB_D0_I2),
+	.I3(RAM2FAB_D0_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	InPass4_frame_config Inst_RAM2FAB_D1_InPass4_frame_config (
+	.O0(RAM2FAB_D1_O0),
+	.O1(RAM2FAB_D1_O1),
+	.O2(RAM2FAB_D1_O2),
+	.O3(RAM2FAB_D1_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(RAM2FAB_D1_I0),
+	.I1(RAM2FAB_D1_I1),
+	.I2(RAM2FAB_D1_I2),
+	.I3(RAM2FAB_D1_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+	InPass4_frame_config Inst_RAM2FAB_D2_InPass4_frame_config (
+	.O0(RAM2FAB_D2_O0),
+	.O1(RAM2FAB_D2_O1),
+	.O2(RAM2FAB_D2_O2),
+	.O3(RAM2FAB_D2_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(RAM2FAB_D2_I0),
+	.I1(RAM2FAB_D2_I1),
+	.I2(RAM2FAB_D2_I2),
+	.I3(RAM2FAB_D2_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[12-1:8])
+	);
+
+	InPass4_frame_config Inst_RAM2FAB_D3_InPass4_frame_config (
+	.O0(RAM2FAB_D3_O0),
+	.O1(RAM2FAB_D3_O1),
+	.O2(RAM2FAB_D3_O2),
+	.O3(RAM2FAB_D3_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(RAM2FAB_D3_I0),
+	.I1(RAM2FAB_D3_I1),
+	.I2(RAM2FAB_D3_I2),
+	.I3(RAM2FAB_D3_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[16-1:12])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_D0_OutPass4_frame_config (
+	.I0(FAB2RAM_D0_I0),
+	.I1(FAB2RAM_D0_I1),
+	.I2(FAB2RAM_D0_I2),
+	.I3(FAB2RAM_D0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_D0_O0),
+	.O1(FAB2RAM_D0_O1),
+	.O2(FAB2RAM_D0_O2),
+	.O3(FAB2RAM_D0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[20-1:16])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_D1_OutPass4_frame_config (
+	.I0(FAB2RAM_D1_I0),
+	.I1(FAB2RAM_D1_I1),
+	.I2(FAB2RAM_D1_I2),
+	.I3(FAB2RAM_D1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_D1_O0),
+	.O1(FAB2RAM_D1_O1),
+	.O2(FAB2RAM_D1_O2),
+	.O3(FAB2RAM_D1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[24-1:20])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_D2_OutPass4_frame_config (
+	.I0(FAB2RAM_D2_I0),
+	.I1(FAB2RAM_D2_I1),
+	.I2(FAB2RAM_D2_I2),
+	.I3(FAB2RAM_D2_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_D2_O0),
+	.O1(FAB2RAM_D2_O1),
+	.O2(FAB2RAM_D2_O2),
+	.O3(FAB2RAM_D2_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[28-1:24])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_D3_OutPass4_frame_config (
+	.I0(FAB2RAM_D3_I0),
+	.I1(FAB2RAM_D3_I1),
+	.I2(FAB2RAM_D3_I2),
+	.I3(FAB2RAM_D3_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_D3_O0),
+	.O1(FAB2RAM_D3_O1),
+	.O2(FAB2RAM_D3_O2),
+	.O3(FAB2RAM_D3_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[32-1:28])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_A0_OutPass4_frame_config (
+	.I0(FAB2RAM_A0_I0),
+	.I1(FAB2RAM_A0_I1),
+	.I2(FAB2RAM_A0_I2),
+	.I3(FAB2RAM_A0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_A0_O0),
+	.O1(FAB2RAM_A0_O1),
+	.O2(FAB2RAM_A0_O2),
+	.O3(FAB2RAM_A0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[36-1:32])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_A1_OutPass4_frame_config (
+	.I0(FAB2RAM_A1_I0),
+	.I1(FAB2RAM_A1_I1),
+	.I2(FAB2RAM_A1_I2),
+	.I3(FAB2RAM_A1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_A1_O0),
+	.O1(FAB2RAM_A1_O1),
+	.O2(FAB2RAM_A1_O2),
+	.O3(FAB2RAM_A1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[40-1:36])
+	);
+
+	OutPass4_frame_config Inst_FAB2RAM_C_OutPass4_frame_config (
+	.I0(FAB2RAM_C_I0),
+	.I1(FAB2RAM_C_I1),
+	.I2(FAB2RAM_C_I2),
+	.I3(FAB2RAM_C_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(FAB2RAM_C_O0),
+	.O1(FAB2RAM_C_O1),
+	.O2(FAB2RAM_C_O2),
+	.O3(FAB2RAM_C_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[44-1:40])
+	);
+
+	Config_access Inst_Config_accessConfig_access (
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.C_bit0(Config_accessC_bit0),
+	.C_bit1(Config_accessC_bit1),
+	.C_bit2(Config_accessC_bit2),
+	.C_bit3(Config_accessC_bit3),
+	.ConfigBits(ConfigBits[48-1:44])
+	);
+
+
+//switch matrix component instantiation
+	RAM_IO_switch_matrix Inst_RAM_IO_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.EE4END4(EE4END[4]),
+	.EE4END5(EE4END[5]),
+	.EE4END6(EE4END[6]),
+	.EE4END7(EE4END[7]),
+	.EE4END8(EE4END[8]),
+	.EE4END9(EE4END[9]),
+	.EE4END10(EE4END[10]),
+	.EE4END11(EE4END[11]),
+	.EE4END12(EE4END[12]),
+	.EE4END13(EE4END[13]),
+	.EE4END14(EE4END[14]),
+	.EE4END15(EE4END[15]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.E6END2(E6END[2]),
+	.E6END3(E6END[3]),
+	.E6END4(E6END[4]),
+	.E6END5(E6END[5]),
+	.E6END6(E6END[6]),
+	.E6END7(E6END[7]),
+	.E6END8(E6END[8]),
+	.E6END9(E6END[9]),
+	.E6END10(E6END[10]),
+	.E6END11(E6END[11]),
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.RAM2FAB_D0_O0(RAM2FAB_D0_O0),
+	.RAM2FAB_D0_O1(RAM2FAB_D0_O1),
+	.RAM2FAB_D0_O2(RAM2FAB_D0_O2),
+	.RAM2FAB_D0_O3(RAM2FAB_D0_O3),
+	.RAM2FAB_D1_O0(RAM2FAB_D1_O0),
+	.RAM2FAB_D1_O1(RAM2FAB_D1_O1),
+	.RAM2FAB_D1_O2(RAM2FAB_D1_O2),
+	.RAM2FAB_D1_O3(RAM2FAB_D1_O3),
+	.RAM2FAB_D2_O0(RAM2FAB_D2_O0),
+	.RAM2FAB_D2_O1(RAM2FAB_D2_O1),
+	.RAM2FAB_D2_O2(RAM2FAB_D2_O2),
+	.RAM2FAB_D2_O3(RAM2FAB_D2_O3),
+	.RAM2FAB_D3_O0(RAM2FAB_D3_O0),
+	.RAM2FAB_D3_O1(RAM2FAB_D3_O1),
+	.RAM2FAB_D3_O2(RAM2FAB_D3_O2),
+	.RAM2FAB_D3_O3(RAM2FAB_D3_O3),
+	.J_NS4_END0(J_NS4_BEG[0]),
+	.J_NS4_END1(J_NS4_BEG[1]),
+	.J_NS4_END2(J_NS4_BEG[2]),
+	.J_NS4_END3(J_NS4_BEG[3]),
+	.J_NS4_END4(J_NS4_BEG[4]),
+	.J_NS4_END5(J_NS4_BEG[5]),
+	.J_NS4_END6(J_NS4_BEG[6]),
+	.J_NS4_END7(J_NS4_BEG[7]),
+	.J_NS4_END8(J_NS4_BEG[8]),
+	.J_NS4_END9(J_NS4_BEG[9]),
+	.J_NS4_END10(J_NS4_BEG[10]),
+	.J_NS4_END11(J_NS4_BEG[11]),
+	.J_NS4_END12(J_NS4_BEG[12]),
+	.J_NS4_END13(J_NS4_BEG[13]),
+	.J_NS4_END14(J_NS4_BEG[14]),
+	.J_NS4_END15(J_NS4_BEG[15]),
+	.J_NS2_END0(J_NS2_BEG[0]),
+	.J_NS2_END1(J_NS2_BEG[1]),
+	.J_NS2_END2(J_NS2_BEG[2]),
+	.J_NS2_END3(J_NS2_BEG[3]),
+	.J_NS2_END4(J_NS2_BEG[4]),
+	.J_NS2_END5(J_NS2_BEG[5]),
+	.J_NS2_END6(J_NS2_BEG[6]),
+	.J_NS2_END7(J_NS2_BEG[7]),
+	.J_NS1_END0(J_NS1_BEG[0]),
+	.J_NS1_END1(J_NS1_BEG[1]),
+	.J_NS1_END2(J_NS1_BEG[2]),
+	.J_NS1_END3(J_NS1_BEG[3]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[12]),
+	.N4BEG1(N4BEG[13]),
+	.N4BEG2(N4BEG[14]),
+	.N4BEG3(N4BEG[15]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[12]),
+	.S4BEG1(S4BEG[13]),
+	.S4BEG2(S4BEG[14]),
+	.S4BEG3(S4BEG[15]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[0]),
+	.WW4BEG1(WW4BEG[1]),
+	.WW4BEG2(WW4BEG[2]),
+	.WW4BEG3(WW4BEG[3]),
+	.WW4BEG4(WW4BEG[4]),
+	.WW4BEG5(WW4BEG[5]),
+	.WW4BEG6(WW4BEG[6]),
+	.WW4BEG7(WW4BEG[7]),
+	.WW4BEG8(WW4BEG[8]),
+	.WW4BEG9(WW4BEG[9]),
+	.WW4BEG10(WW4BEG[10]),
+	.WW4BEG11(WW4BEG[11]),
+	.WW4BEG12(WW4BEG[12]),
+	.WW4BEG13(WW4BEG[13]),
+	.WW4BEG14(WW4BEG[14]),
+	.WW4BEG15(WW4BEG[15]),
+	.W6BEG0(W6BEG[0]),
+	.W6BEG1(W6BEG[1]),
+	.W6BEG2(W6BEG[2]),
+	.W6BEG3(W6BEG[3]),
+	.W6BEG4(W6BEG[4]),
+	.W6BEG5(W6BEG[5]),
+	.W6BEG6(W6BEG[6]),
+	.W6BEG7(W6BEG[7]),
+	.W6BEG8(W6BEG[8]),
+	.W6BEG9(W6BEG[9]),
+	.W6BEG10(W6BEG[10]),
+	.W6BEG11(W6BEG[11]),
+	.FAB2RAM_D0_I0(FAB2RAM_D0_I0),
+	.FAB2RAM_D0_I1(FAB2RAM_D0_I1),
+	.FAB2RAM_D0_I2(FAB2RAM_D0_I2),
+	.FAB2RAM_D0_I3(FAB2RAM_D0_I3),
+	.FAB2RAM_D1_I0(FAB2RAM_D1_I0),
+	.FAB2RAM_D1_I1(FAB2RAM_D1_I1),
+	.FAB2RAM_D1_I2(FAB2RAM_D1_I2),
+	.FAB2RAM_D1_I3(FAB2RAM_D1_I3),
+	.FAB2RAM_D2_I0(FAB2RAM_D2_I0),
+	.FAB2RAM_D2_I1(FAB2RAM_D2_I1),
+	.FAB2RAM_D2_I2(FAB2RAM_D2_I2),
+	.FAB2RAM_D2_I3(FAB2RAM_D2_I3),
+	.FAB2RAM_D3_I0(FAB2RAM_D3_I0),
+	.FAB2RAM_D3_I1(FAB2RAM_D3_I1),
+	.FAB2RAM_D3_I2(FAB2RAM_D3_I2),
+	.FAB2RAM_D3_I3(FAB2RAM_D3_I3),
+	.FAB2RAM_A0_I0(FAB2RAM_A0_I0),
+	.FAB2RAM_A0_I1(FAB2RAM_A0_I1),
+	.FAB2RAM_A0_I2(FAB2RAM_A0_I2),
+	.FAB2RAM_A0_I3(FAB2RAM_A0_I3),
+	.FAB2RAM_A1_I0(FAB2RAM_A1_I0),
+	.FAB2RAM_A1_I1(FAB2RAM_A1_I1),
+	.FAB2RAM_A1_I2(FAB2RAM_A1_I2),
+	.FAB2RAM_A1_I3(FAB2RAM_A1_I3),
+	.FAB2RAM_C_I0(FAB2RAM_C_I0),
+	.FAB2RAM_C_I1(FAB2RAM_C_I1),
+	.FAB2RAM_C_I2(FAB2RAM_C_I2),
+	.FAB2RAM_C_I3(FAB2RAM_C_I3),
+	.J_NS4_BEG0(J_NS4_BEG[0]),
+	.J_NS4_BEG1(J_NS4_BEG[1]),
+	.J_NS4_BEG2(J_NS4_BEG[2]),
+	.J_NS4_BEG3(J_NS4_BEG[3]),
+	.J_NS4_BEG4(J_NS4_BEG[4]),
+	.J_NS4_BEG5(J_NS4_BEG[5]),
+	.J_NS4_BEG6(J_NS4_BEG[6]),
+	.J_NS4_BEG7(J_NS4_BEG[7]),
+	.J_NS4_BEG8(J_NS4_BEG[8]),
+	.J_NS4_BEG9(J_NS4_BEG[9]),
+	.J_NS4_BEG10(J_NS4_BEG[10]),
+	.J_NS4_BEG11(J_NS4_BEG[11]),
+	.J_NS4_BEG12(J_NS4_BEG[12]),
+	.J_NS4_BEG13(J_NS4_BEG[13]),
+	.J_NS4_BEG14(J_NS4_BEG[14]),
+	.J_NS4_BEG15(J_NS4_BEG[15]),
+	.J_NS2_BEG0(J_NS2_BEG[0]),
+	.J_NS2_BEG1(J_NS2_BEG[1]),
+	.J_NS2_BEG2(J_NS2_BEG[2]),
+	.J_NS2_BEG3(J_NS2_BEG[3]),
+	.J_NS2_BEG4(J_NS2_BEG[4]),
+	.J_NS2_BEG5(J_NS2_BEG[5]),
+	.J_NS2_BEG6(J_NS2_BEG[6]),
+	.J_NS2_BEG7(J_NS2_BEG[7]),
+	.J_NS1_BEG0(J_NS1_BEG[0]),
+	.J_NS1_BEG1(J_NS1_BEG[1]),
+	.J_NS1_BEG2(J_NS1_BEG[2]),
+	.J_NS1_BEG3(J_NS1_BEG[3]),
+	.ConfigBits(ConfigBits[328-1:48]),
+	.ConfigBits_N(ConfigBits_N[328-1:48])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RegFile_32x4.v b/verilog/rtl/eFPGA_core/RegFile_32x4.v
new file mode 100644
index 0000000..01032e1
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RegFile_32x4.v
@@ -0,0 +1,123 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2021 University of Manchester
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, UserCLK, ConfigBits);
+	parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+	// IMPORTANT: this has to be in a dedicated line
+	input D0; // Register File write port
+	input D1;
+	input D2;
+	input D3;
+	input W_ADR0;
+	input W_ADR1;
+	input W_ADR2;
+	input W_ADR3;
+	input W_ADR4;
+	input W_en;
+	
+	output AD0;// Register File read port A
+	output AD1;
+	output AD2;
+	output AD3;
+	input A_ADR0;
+	input A_ADR1;
+	input A_ADR2;
+	input A_ADR3;
+	input A_ADR4;
+
+	output BD0;//Register File read port B
+	output BD1;
+	output BD2;
+	output BD3;
+	input B_ADR0;
+	input B_ADR1;
+	input B_ADR2;
+	input B_ADR3;
+	input B_ADR4;
+
+	input UserCLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+	// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+	input [NoConfigBits-1:0] ConfigBits;
+
+	//type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
+	//signal mem : memtype := (others => (others => '0'));
+	reg [3:0] mem [31:0];
+
+	wire [4:0] W_ADR;// write address
+	wire [4:0] A_ADR;// port A read address
+	wire [4:0] B_ADR;// port B read address
+
+	wire [3:0] D;		// write data
+	wire [3:0] AD;		// port A read data
+	wire [3:0] BD;		// port B read data
+
+	reg [3:0] AD_reg;		// port A read data register
+	reg [3:0] BD_reg;		// port B read data register
+	
+	integer i;
+
+	assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
+	assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0};
+	assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
+
+	assign D = {D3,D2,D1,D0};
+	
+	initial begin
+		for (i=0; i<32; i=i+1) begin
+			mem[i] = 4'b0000;
+		end
+	end
+
+//P_write: process (UserCLK)
+	always @ (posedge UserCLK) begin : P_write
+		if (W_en == 1'b1) begin
+			mem[W_ADR] <= D ;
+		end
+	end
+
+	assign AD = mem[A_ADR];
+	assign BD = mem[B_ADR];
+
+    always @ (posedge UserCLK) begin
+        AD_reg <= AD;
+		BD_reg <= BD;
+    end
+
+	assign AD0 = ConfigBits[0] ? AD_reg[0] : AD[0];
+	assign AD1 = ConfigBits[0] ? AD_reg[1] : AD[1];
+	assign AD2 = ConfigBits[0] ? AD_reg[2] : AD[2];
+	assign AD3 = ConfigBits[0] ? AD_reg[3] : AD[3];
+
+	assign BD0 = ConfigBits[1] ? BD_reg[0] : BD[0];
+	assign BD1 = ConfigBits[1] ? BD_reg[1] : BD[1];
+	assign BD2 = ConfigBits[1] ? BD_reg[2] : BD[2];
+	assign BD3 = ConfigBits[1] ? BD_reg[3] : BD[3];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RegFile_ConfigMem.v b/verilog/rtl/eFPGA_core/RegFile_ConfigMem.v
new file mode 100644
index 0000000..b6fa03b
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RegFile_ConfigMem.v
@@ -0,0 +1,2938 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module RegFile_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 414;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [32-1:0] frame0;
+	wire [32-1:0] frame1;
+	wire [32-1:0] frame2;
+	wire [32-1:0] frame3;
+	wire [32-1:0] frame4;
+	wire [32-1:0] frame5;
+	wire [32-1:0] frame6;
+	wire [32-1:0] frame7;
+	wire [32-1:0] frame8;
+	wire [32-1:0] frame9;
+	wire [32-1:0] frame10;
+	wire [32-1:0] frame11;
+	wire [30-1:0] frame12;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[413]),
+	.QN(ConfigBits_N[413])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[412]),
+	.QN(ConfigBits_N[412])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[411]),
+	.QN(ConfigBits_N[411])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[410]),
+	.QN(ConfigBits_N[410])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[409]),
+	.QN(ConfigBits_N[409])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[408]),
+	.QN(ConfigBits_N[408])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[407]),
+	.QN(ConfigBits_N[407])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[406]),
+	.QN(ConfigBits_N[406])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[405]),
+	.QN(ConfigBits_N[405])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[404]),
+	.QN(ConfigBits_N[404])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[403]),
+	.QN(ConfigBits_N[403])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[402]),
+	.QN(ConfigBits_N[402])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[401]),
+	.QN(ConfigBits_N[401])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[400]),
+	.QN(ConfigBits_N[400])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[399]),
+	.QN(ConfigBits_N[399])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[398]),
+	.QN(ConfigBits_N[398])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[397]),
+	.QN(ConfigBits_N[397])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[396]),
+	.QN(ConfigBits_N[396])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[395]),
+	.QN(ConfigBits_N[395])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[394]),
+	.QN(ConfigBits_N[394])
+	);
+
+	LHQD1 Inst_frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[393]),
+	.QN(ConfigBits_N[393])
+	);
+
+	LHQD1 Inst_frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[392]),
+	.QN(ConfigBits_N[392])
+	);
+
+	LHQD1 Inst_frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[391]),
+	.QN(ConfigBits_N[391])
+	);
+
+	LHQD1 Inst_frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[390]),
+	.QN(ConfigBits_N[390])
+	);
+
+	LHQD1 Inst_frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[389]),
+	.QN(ConfigBits_N[389])
+	);
+
+	LHQD1 Inst_frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[388]),
+	.QN(ConfigBits_N[388])
+	);
+
+	LHQD1 Inst_frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[387]),
+	.QN(ConfigBits_N[387])
+	);
+
+	LHQD1 Inst_frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[386]),
+	.QN(ConfigBits_N[386])
+	);
+
+	LHQD1 Inst_frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[385]),
+	.QN(ConfigBits_N[385])
+	);
+
+	LHQD1 Inst_frame0_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[384]),
+	.QN(ConfigBits_N[384])
+	);
+
+	LHQD1 Inst_frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[383]),
+	.QN(ConfigBits_N[383])
+	);
+
+	LHQD1 Inst_frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[382]),
+	.QN(ConfigBits_N[382])
+	);
+
+	LHQD1 Inst_frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[381]),
+	.QN(ConfigBits_N[381])
+	);
+
+	LHQD1 Inst_frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[380]),
+	.QN(ConfigBits_N[380])
+	);
+
+	LHQD1 Inst_frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[379]),
+	.QN(ConfigBits_N[379])
+	);
+
+	LHQD1 Inst_frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[378]),
+	.QN(ConfigBits_N[378])
+	);
+
+	LHQD1 Inst_frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[377]),
+	.QN(ConfigBits_N[377])
+	);
+
+	LHQD1 Inst_frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[376]),
+	.QN(ConfigBits_N[376])
+	);
+
+	LHQD1 Inst_frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[375]),
+	.QN(ConfigBits_N[375])
+	);
+
+	LHQD1 Inst_frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[374]),
+	.QN(ConfigBits_N[374])
+	);
+
+	LHQD1 Inst_frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[373]),
+	.QN(ConfigBits_N[373])
+	);
+
+	LHQD1 Inst_frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[372]),
+	.QN(ConfigBits_N[372])
+	);
+
+	LHQD1 Inst_frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[371]),
+	.QN(ConfigBits_N[371])
+	);
+
+	LHQD1 Inst_frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[370]),
+	.QN(ConfigBits_N[370])
+	);
+
+	LHQD1 Inst_frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[369]),
+	.QN(ConfigBits_N[369])
+	);
+
+	LHQD1 Inst_frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[368]),
+	.QN(ConfigBits_N[368])
+	);
+
+	LHQD1 Inst_frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[367]),
+	.QN(ConfigBits_N[367])
+	);
+
+	LHQD1 Inst_frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[366]),
+	.QN(ConfigBits_N[366])
+	);
+
+	LHQD1 Inst_frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[365]),
+	.QN(ConfigBits_N[365])
+	);
+
+	LHQD1 Inst_frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[364]),
+	.QN(ConfigBits_N[364])
+	);
+
+	LHQD1 Inst_frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[363]),
+	.QN(ConfigBits_N[363])
+	);
+
+	LHQD1 Inst_frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[362]),
+	.QN(ConfigBits_N[362])
+	);
+
+	LHQD1 Inst_frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[361]),
+	.QN(ConfigBits_N[361])
+	);
+
+	LHQD1 Inst_frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[360]),
+	.QN(ConfigBits_N[360])
+	);
+
+	LHQD1 Inst_frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[359]),
+	.QN(ConfigBits_N[359])
+	);
+
+	LHQD1 Inst_frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[358]),
+	.QN(ConfigBits_N[358])
+	);
+
+	LHQD1 Inst_frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[357]),
+	.QN(ConfigBits_N[357])
+	);
+
+	LHQD1 Inst_frame1_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[356]),
+	.QN(ConfigBits_N[356])
+	);
+
+	LHQD1 Inst_frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[355]),
+	.QN(ConfigBits_N[355])
+	);
+
+	LHQD1 Inst_frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[354]),
+	.QN(ConfigBits_N[354])
+	);
+
+	LHQD1 Inst_frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[353]),
+	.QN(ConfigBits_N[353])
+	);
+
+	LHQD1 Inst_frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[352]),
+	.QN(ConfigBits_N[352])
+	);
+
+	LHQD1 Inst_frame1_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[351]),
+	.QN(ConfigBits_N[351])
+	);
+
+	LHQD1 Inst_frame1_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[350]),
+	.QN(ConfigBits_N[350])
+	);
+
+	LHQD1 Inst_frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[349]),
+	.QN(ConfigBits_N[349])
+	);
+
+	LHQD1 Inst_frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[348]),
+	.QN(ConfigBits_N[348])
+	);
+
+	LHQD1 Inst_frame2_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[347]),
+	.QN(ConfigBits_N[347])
+	);
+
+	LHQD1 Inst_frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[346]),
+	.QN(ConfigBits_N[346])
+	);
+
+	LHQD1 Inst_frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[345]),
+	.QN(ConfigBits_N[345])
+	);
+
+	LHQD1 Inst_frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[344]),
+	.QN(ConfigBits_N[344])
+	);
+
+	LHQD1 Inst_frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[343]),
+	.QN(ConfigBits_N[343])
+	);
+
+	LHQD1 Inst_frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[342]),
+	.QN(ConfigBits_N[342])
+	);
+
+	LHQD1 Inst_frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[341]),
+	.QN(ConfigBits_N[341])
+	);
+
+	LHQD1 Inst_frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[340]),
+	.QN(ConfigBits_N[340])
+	);
+
+	LHQD1 Inst_frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[339]),
+	.QN(ConfigBits_N[339])
+	);
+
+	LHQD1 Inst_frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[338]),
+	.QN(ConfigBits_N[338])
+	);
+
+	LHQD1 Inst_frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[337]),
+	.QN(ConfigBits_N[337])
+	);
+
+	LHQD1 Inst_frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[336]),
+	.QN(ConfigBits_N[336])
+	);
+
+	LHQD1 Inst_frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[335]),
+	.QN(ConfigBits_N[335])
+	);
+
+	LHQD1 Inst_frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[334]),
+	.QN(ConfigBits_N[334])
+	);
+
+	LHQD1 Inst_frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[333]),
+	.QN(ConfigBits_N[333])
+	);
+
+	LHQD1 Inst_frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[332]),
+	.QN(ConfigBits_N[332])
+	);
+
+	LHQD1 Inst_frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[331]),
+	.QN(ConfigBits_N[331])
+	);
+
+	LHQD1 Inst_frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[330]),
+	.QN(ConfigBits_N[330])
+	);
+
+	LHQD1 Inst_frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[329]),
+	.QN(ConfigBits_N[329])
+	);
+
+	LHQD1 Inst_frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[328]),
+	.QN(ConfigBits_N[328])
+	);
+
+	LHQD1 Inst_frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[327]),
+	.QN(ConfigBits_N[327])
+	);
+
+	LHQD1 Inst_frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[326]),
+	.QN(ConfigBits_N[326])
+	);
+
+	LHQD1 Inst_frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[325]),
+	.QN(ConfigBits_N[325])
+	);
+
+	LHQD1 Inst_frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[324]),
+	.QN(ConfigBits_N[324])
+	);
+
+	LHQD1 Inst_frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[323]),
+	.QN(ConfigBits_N[323])
+	);
+
+	LHQD1 Inst_frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[322]),
+	.QN(ConfigBits_N[322])
+	);
+
+	LHQD1 Inst_frame2_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[321]),
+	.QN(ConfigBits_N[321])
+	);
+
+	LHQD1 Inst_frame2_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[320]),
+	.QN(ConfigBits_N[320])
+	);
+
+	LHQD1 Inst_frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[319]),
+	.QN(ConfigBits_N[319])
+	);
+
+	LHQD1 Inst_frame2_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[318]),
+	.QN(ConfigBits_N[318])
+	);
+
+	LHQD1 Inst_frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[317]),
+	.QN(ConfigBits_N[317])
+	);
+
+	LHQD1 Inst_frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[316]),
+	.QN(ConfigBits_N[316])
+	);
+
+	LHQD1 Inst_frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[315]),
+	.QN(ConfigBits_N[315])
+	);
+
+	LHQD1 Inst_frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[314]),
+	.QN(ConfigBits_N[314])
+	);
+
+	LHQD1 Inst_frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[313]),
+	.QN(ConfigBits_N[313])
+	);
+
+	LHQD1 Inst_frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[312]),
+	.QN(ConfigBits_N[312])
+	);
+
+	LHQD1 Inst_frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[311]),
+	.QN(ConfigBits_N[311])
+	);
+
+	LHQD1 Inst_frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[310]),
+	.QN(ConfigBits_N[310])
+	);
+
+	LHQD1 Inst_frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[309]),
+	.QN(ConfigBits_N[309])
+	);
+
+	LHQD1 Inst_frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[308]),
+	.QN(ConfigBits_N[308])
+	);
+
+	LHQD1 Inst_frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[307]),
+	.QN(ConfigBits_N[307])
+	);
+
+	LHQD1 Inst_frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[306]),
+	.QN(ConfigBits_N[306])
+	);
+
+	LHQD1 Inst_frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[305]),
+	.QN(ConfigBits_N[305])
+	);
+
+	LHQD1 Inst_frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[304]),
+	.QN(ConfigBits_N[304])
+	);
+
+	LHQD1 Inst_frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[303]),
+	.QN(ConfigBits_N[303])
+	);
+
+	LHQD1 Inst_frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[302]),
+	.QN(ConfigBits_N[302])
+	);
+
+	LHQD1 Inst_frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[301]),
+	.QN(ConfigBits_N[301])
+	);
+
+	LHQD1 Inst_frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[300]),
+	.QN(ConfigBits_N[300])
+	);
+
+	LHQD1 Inst_frame3_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[299]),
+	.QN(ConfigBits_N[299])
+	);
+
+	LHQD1 Inst_frame3_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[298]),
+	.QN(ConfigBits_N[298])
+	);
+
+	LHQD1 Inst_frame3_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[297]),
+	.QN(ConfigBits_N[297])
+	);
+
+	LHQD1 Inst_frame3_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[296]),
+	.QN(ConfigBits_N[296])
+	);
+
+	LHQD1 Inst_frame3_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[295]),
+	.QN(ConfigBits_N[295])
+	);
+
+	LHQD1 Inst_frame3_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[294]),
+	.QN(ConfigBits_N[294])
+	);
+
+	LHQD1 Inst_frame3_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[293]),
+	.QN(ConfigBits_N[293])
+	);
+
+	LHQD1 Inst_frame3_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[292]),
+	.QN(ConfigBits_N[292])
+	);
+
+	LHQD1 Inst_frame3_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[291]),
+	.QN(ConfigBits_N[291])
+	);
+
+	LHQD1 Inst_frame3_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[290]),
+	.QN(ConfigBits_N[290])
+	);
+
+	LHQD1 Inst_frame3_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[289]),
+	.QN(ConfigBits_N[289])
+	);
+
+	LHQD1 Inst_frame3_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[288]),
+	.QN(ConfigBits_N[288])
+	);
+
+	LHQD1 Inst_frame3_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[287]),
+	.QN(ConfigBits_N[287])
+	);
+
+	LHQD1 Inst_frame3_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[286]),
+	.QN(ConfigBits_N[286])
+	);
+
+	LHQD1 Inst_frame4_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[285]),
+	.QN(ConfigBits_N[285])
+	);
+
+	LHQD1 Inst_frame4_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[284]),
+	.QN(ConfigBits_N[284])
+	);
+
+	LHQD1 Inst_frame4_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[283]),
+	.QN(ConfigBits_N[283])
+	);
+
+	LHQD1 Inst_frame4_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[282]),
+	.QN(ConfigBits_N[282])
+	);
+
+	LHQD1 Inst_frame4_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[281]),
+	.QN(ConfigBits_N[281])
+	);
+
+	LHQD1 Inst_frame4_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[280]),
+	.QN(ConfigBits_N[280])
+	);
+
+	LHQD1 Inst_frame4_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[279]),
+	.QN(ConfigBits_N[279])
+	);
+
+	LHQD1 Inst_frame4_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[278]),
+	.QN(ConfigBits_N[278])
+	);
+
+	LHQD1 Inst_frame4_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[277]),
+	.QN(ConfigBits_N[277])
+	);
+
+	LHQD1 Inst_frame4_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[276]),
+	.QN(ConfigBits_N[276])
+	);
+
+	LHQD1 Inst_frame4_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[275]),
+	.QN(ConfigBits_N[275])
+	);
+
+	LHQD1 Inst_frame4_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[274]),
+	.QN(ConfigBits_N[274])
+	);
+
+	LHQD1 Inst_frame4_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[273]),
+	.QN(ConfigBits_N[273])
+	);
+
+	LHQD1 Inst_frame4_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[272]),
+	.QN(ConfigBits_N[272])
+	);
+
+	LHQD1 Inst_frame4_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[271]),
+	.QN(ConfigBits_N[271])
+	);
+
+	LHQD1 Inst_frame4_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[270]),
+	.QN(ConfigBits_N[270])
+	);
+
+	LHQD1 Inst_frame4_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[269]),
+	.QN(ConfigBits_N[269])
+	);
+
+	LHQD1 Inst_frame4_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[268]),
+	.QN(ConfigBits_N[268])
+	);
+
+	LHQD1 Inst_frame4_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[267]),
+	.QN(ConfigBits_N[267])
+	);
+
+	LHQD1 Inst_frame4_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[266]),
+	.QN(ConfigBits_N[266])
+	);
+
+	LHQD1 Inst_frame4_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[265]),
+	.QN(ConfigBits_N[265])
+	);
+
+	LHQD1 Inst_frame4_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[264]),
+	.QN(ConfigBits_N[264])
+	);
+
+	LHQD1 Inst_frame4_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[263]),
+	.QN(ConfigBits_N[263])
+	);
+
+	LHQD1 Inst_frame4_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[262]),
+	.QN(ConfigBits_N[262])
+	);
+
+	LHQD1 Inst_frame4_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[261]),
+	.QN(ConfigBits_N[261])
+	);
+
+	LHQD1 Inst_frame4_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[260]),
+	.QN(ConfigBits_N[260])
+	);
+
+	LHQD1 Inst_frame4_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[259]),
+	.QN(ConfigBits_N[259])
+	);
+
+	LHQD1 Inst_frame4_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[258]),
+	.QN(ConfigBits_N[258])
+	);
+
+	LHQD1 Inst_frame4_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[257]),
+	.QN(ConfigBits_N[257])
+	);
+
+	LHQD1 Inst_frame4_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[256]),
+	.QN(ConfigBits_N[256])
+	);
+
+	LHQD1 Inst_frame4_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[255]),
+	.QN(ConfigBits_N[255])
+	);
+
+	LHQD1 Inst_frame4_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[4]),
+	.Q(ConfigBits[254]),
+	.QN(ConfigBits_N[254])
+	);
+
+	LHQD1 Inst_frame5_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[253]),
+	.QN(ConfigBits_N[253])
+	);
+
+	LHQD1 Inst_frame5_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[252]),
+	.QN(ConfigBits_N[252])
+	);
+
+	LHQD1 Inst_frame5_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[251]),
+	.QN(ConfigBits_N[251])
+	);
+
+	LHQD1 Inst_frame5_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[250]),
+	.QN(ConfigBits_N[250])
+	);
+
+	LHQD1 Inst_frame5_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[249]),
+	.QN(ConfigBits_N[249])
+	);
+
+	LHQD1 Inst_frame5_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[248]),
+	.QN(ConfigBits_N[248])
+	);
+
+	LHQD1 Inst_frame5_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[247]),
+	.QN(ConfigBits_N[247])
+	);
+
+	LHQD1 Inst_frame5_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[246]),
+	.QN(ConfigBits_N[246])
+	);
+
+	LHQD1 Inst_frame5_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[245]),
+	.QN(ConfigBits_N[245])
+	);
+
+	LHQD1 Inst_frame5_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[244]),
+	.QN(ConfigBits_N[244])
+	);
+
+	LHQD1 Inst_frame5_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[243]),
+	.QN(ConfigBits_N[243])
+	);
+
+	LHQD1 Inst_frame5_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[242]),
+	.QN(ConfigBits_N[242])
+	);
+
+	LHQD1 Inst_frame5_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[241]),
+	.QN(ConfigBits_N[241])
+	);
+
+	LHQD1 Inst_frame5_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[240]),
+	.QN(ConfigBits_N[240])
+	);
+
+	LHQD1 Inst_frame5_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[239]),
+	.QN(ConfigBits_N[239])
+	);
+
+	LHQD1 Inst_frame5_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[238]),
+	.QN(ConfigBits_N[238])
+	);
+
+	LHQD1 Inst_frame5_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[237]),
+	.QN(ConfigBits_N[237])
+	);
+
+	LHQD1 Inst_frame5_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[236]),
+	.QN(ConfigBits_N[236])
+	);
+
+	LHQD1 Inst_frame5_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[235]),
+	.QN(ConfigBits_N[235])
+	);
+
+	LHQD1 Inst_frame5_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[234]),
+	.QN(ConfigBits_N[234])
+	);
+
+	LHQD1 Inst_frame5_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[233]),
+	.QN(ConfigBits_N[233])
+	);
+
+	LHQD1 Inst_frame5_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[232]),
+	.QN(ConfigBits_N[232])
+	);
+
+	LHQD1 Inst_frame5_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[231]),
+	.QN(ConfigBits_N[231])
+	);
+
+	LHQD1 Inst_frame5_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[230]),
+	.QN(ConfigBits_N[230])
+	);
+
+	LHQD1 Inst_frame5_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[229]),
+	.QN(ConfigBits_N[229])
+	);
+
+	LHQD1 Inst_frame5_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[228]),
+	.QN(ConfigBits_N[228])
+	);
+
+	LHQD1 Inst_frame5_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[227]),
+	.QN(ConfigBits_N[227])
+	);
+
+	LHQD1 Inst_frame5_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[226]),
+	.QN(ConfigBits_N[226])
+	);
+
+	LHQD1 Inst_frame5_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[225]),
+	.QN(ConfigBits_N[225])
+	);
+
+	LHQD1 Inst_frame5_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[224]),
+	.QN(ConfigBits_N[224])
+	);
+
+	LHQD1 Inst_frame5_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[223]),
+	.QN(ConfigBits_N[223])
+	);
+
+	LHQD1 Inst_frame5_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[5]),
+	.Q(ConfigBits[222]),
+	.QN(ConfigBits_N[222])
+	);
+
+	LHQD1 Inst_frame6_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[221]),
+	.QN(ConfigBits_N[221])
+	);
+
+	LHQD1 Inst_frame6_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[220]),
+	.QN(ConfigBits_N[220])
+	);
+
+	LHQD1 Inst_frame6_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[219]),
+	.QN(ConfigBits_N[219])
+	);
+
+	LHQD1 Inst_frame6_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[218]),
+	.QN(ConfigBits_N[218])
+	);
+
+	LHQD1 Inst_frame6_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[217]),
+	.QN(ConfigBits_N[217])
+	);
+
+	LHQD1 Inst_frame6_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[216]),
+	.QN(ConfigBits_N[216])
+	);
+
+	LHQD1 Inst_frame6_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[215]),
+	.QN(ConfigBits_N[215])
+	);
+
+	LHQD1 Inst_frame6_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[214]),
+	.QN(ConfigBits_N[214])
+	);
+
+	LHQD1 Inst_frame6_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[213]),
+	.QN(ConfigBits_N[213])
+	);
+
+	LHQD1 Inst_frame6_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[212]),
+	.QN(ConfigBits_N[212])
+	);
+
+	LHQD1 Inst_frame6_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[211]),
+	.QN(ConfigBits_N[211])
+	);
+
+	LHQD1 Inst_frame6_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[210]),
+	.QN(ConfigBits_N[210])
+	);
+
+	LHQD1 Inst_frame6_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[209]),
+	.QN(ConfigBits_N[209])
+	);
+
+	LHQD1 Inst_frame6_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[208]),
+	.QN(ConfigBits_N[208])
+	);
+
+	LHQD1 Inst_frame6_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[207]),
+	.QN(ConfigBits_N[207])
+	);
+
+	LHQD1 Inst_frame6_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[206]),
+	.QN(ConfigBits_N[206])
+	);
+
+	LHQD1 Inst_frame6_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[205]),
+	.QN(ConfigBits_N[205])
+	);
+
+	LHQD1 Inst_frame6_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[204]),
+	.QN(ConfigBits_N[204])
+	);
+
+	LHQD1 Inst_frame6_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[203]),
+	.QN(ConfigBits_N[203])
+	);
+
+	LHQD1 Inst_frame6_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[202]),
+	.QN(ConfigBits_N[202])
+	);
+
+	LHQD1 Inst_frame6_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[201]),
+	.QN(ConfigBits_N[201])
+	);
+
+	LHQD1 Inst_frame6_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[200]),
+	.QN(ConfigBits_N[200])
+	);
+
+	LHQD1 Inst_frame6_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[199]),
+	.QN(ConfigBits_N[199])
+	);
+
+	LHQD1 Inst_frame6_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[198]),
+	.QN(ConfigBits_N[198])
+	);
+
+	LHQD1 Inst_frame6_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[197]),
+	.QN(ConfigBits_N[197])
+	);
+
+	LHQD1 Inst_frame6_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[196]),
+	.QN(ConfigBits_N[196])
+	);
+
+	LHQD1 Inst_frame6_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[195]),
+	.QN(ConfigBits_N[195])
+	);
+
+	LHQD1 Inst_frame6_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[194]),
+	.QN(ConfigBits_N[194])
+	);
+
+	LHQD1 Inst_frame6_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[193]),
+	.QN(ConfigBits_N[193])
+	);
+
+	LHQD1 Inst_frame6_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[192]),
+	.QN(ConfigBits_N[192])
+	);
+
+	LHQD1 Inst_frame6_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[191]),
+	.QN(ConfigBits_N[191])
+	);
+
+	LHQD1 Inst_frame6_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[6]),
+	.Q(ConfigBits[190]),
+	.QN(ConfigBits_N[190])
+	);
+
+	LHQD1 Inst_frame7_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[189]),
+	.QN(ConfigBits_N[189])
+	);
+
+	LHQD1 Inst_frame7_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[188]),
+	.QN(ConfigBits_N[188])
+	);
+
+	LHQD1 Inst_frame7_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[187]),
+	.QN(ConfigBits_N[187])
+	);
+
+	LHQD1 Inst_frame7_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[186]),
+	.QN(ConfigBits_N[186])
+	);
+
+	LHQD1 Inst_frame7_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[185]),
+	.QN(ConfigBits_N[185])
+	);
+
+	LHQD1 Inst_frame7_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[184]),
+	.QN(ConfigBits_N[184])
+	);
+
+	LHQD1 Inst_frame7_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[183]),
+	.QN(ConfigBits_N[183])
+	);
+
+	LHQD1 Inst_frame7_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[182]),
+	.QN(ConfigBits_N[182])
+	);
+
+	LHQD1 Inst_frame7_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[181]),
+	.QN(ConfigBits_N[181])
+	);
+
+	LHQD1 Inst_frame7_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[180]),
+	.QN(ConfigBits_N[180])
+	);
+
+	LHQD1 Inst_frame7_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[179]),
+	.QN(ConfigBits_N[179])
+	);
+
+	LHQD1 Inst_frame7_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[178]),
+	.QN(ConfigBits_N[178])
+	);
+
+	LHQD1 Inst_frame7_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[177]),
+	.QN(ConfigBits_N[177])
+	);
+
+	LHQD1 Inst_frame7_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[176]),
+	.QN(ConfigBits_N[176])
+	);
+
+	LHQD1 Inst_frame7_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[175]),
+	.QN(ConfigBits_N[175])
+	);
+
+	LHQD1 Inst_frame7_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[174]),
+	.QN(ConfigBits_N[174])
+	);
+
+	LHQD1 Inst_frame7_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[173]),
+	.QN(ConfigBits_N[173])
+	);
+
+	LHQD1 Inst_frame7_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[172]),
+	.QN(ConfigBits_N[172])
+	);
+
+	LHQD1 Inst_frame7_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[171]),
+	.QN(ConfigBits_N[171])
+	);
+
+	LHQD1 Inst_frame7_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[170]),
+	.QN(ConfigBits_N[170])
+	);
+
+	LHQD1 Inst_frame7_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[169]),
+	.QN(ConfigBits_N[169])
+	);
+
+	LHQD1 Inst_frame7_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[168]),
+	.QN(ConfigBits_N[168])
+	);
+
+	LHQD1 Inst_frame7_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[167]),
+	.QN(ConfigBits_N[167])
+	);
+
+	LHQD1 Inst_frame7_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[166]),
+	.QN(ConfigBits_N[166])
+	);
+
+	LHQD1 Inst_frame7_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[165]),
+	.QN(ConfigBits_N[165])
+	);
+
+	LHQD1 Inst_frame7_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[164]),
+	.QN(ConfigBits_N[164])
+	);
+
+	LHQD1 Inst_frame7_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[163]),
+	.QN(ConfigBits_N[163])
+	);
+
+	LHQD1 Inst_frame7_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[162]),
+	.QN(ConfigBits_N[162])
+	);
+
+	LHQD1 Inst_frame7_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[161]),
+	.QN(ConfigBits_N[161])
+	);
+
+	LHQD1 Inst_frame7_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[160]),
+	.QN(ConfigBits_N[160])
+	);
+
+	LHQD1 Inst_frame7_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[159]),
+	.QN(ConfigBits_N[159])
+	);
+
+	LHQD1 Inst_frame7_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[7]),
+	.Q(ConfigBits[158]),
+	.QN(ConfigBits_N[158])
+	);
+
+	LHQD1 Inst_frame8_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[157]),
+	.QN(ConfigBits_N[157])
+	);
+
+	LHQD1 Inst_frame8_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[156]),
+	.QN(ConfigBits_N[156])
+	);
+
+	LHQD1 Inst_frame8_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[155]),
+	.QN(ConfigBits_N[155])
+	);
+
+	LHQD1 Inst_frame8_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[154]),
+	.QN(ConfigBits_N[154])
+	);
+
+	LHQD1 Inst_frame8_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[153]),
+	.QN(ConfigBits_N[153])
+	);
+
+	LHQD1 Inst_frame8_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[152]),
+	.QN(ConfigBits_N[152])
+	);
+
+	LHQD1 Inst_frame8_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[151]),
+	.QN(ConfigBits_N[151])
+	);
+
+	LHQD1 Inst_frame8_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[150]),
+	.QN(ConfigBits_N[150])
+	);
+
+	LHQD1 Inst_frame8_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[149]),
+	.QN(ConfigBits_N[149])
+	);
+
+	LHQD1 Inst_frame8_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[148]),
+	.QN(ConfigBits_N[148])
+	);
+
+	LHQD1 Inst_frame8_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[147]),
+	.QN(ConfigBits_N[147])
+	);
+
+	LHQD1 Inst_frame8_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[146]),
+	.QN(ConfigBits_N[146])
+	);
+
+	LHQD1 Inst_frame8_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[145]),
+	.QN(ConfigBits_N[145])
+	);
+
+	LHQD1 Inst_frame8_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[144]),
+	.QN(ConfigBits_N[144])
+	);
+
+	LHQD1 Inst_frame8_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[143]),
+	.QN(ConfigBits_N[143])
+	);
+
+	LHQD1 Inst_frame8_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[142]),
+	.QN(ConfigBits_N[142])
+	);
+
+	LHQD1 Inst_frame8_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[141]),
+	.QN(ConfigBits_N[141])
+	);
+
+	LHQD1 Inst_frame8_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[140]),
+	.QN(ConfigBits_N[140])
+	);
+
+	LHQD1 Inst_frame8_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[139]),
+	.QN(ConfigBits_N[139])
+	);
+
+	LHQD1 Inst_frame8_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[138]),
+	.QN(ConfigBits_N[138])
+	);
+
+	LHQD1 Inst_frame8_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[137]),
+	.QN(ConfigBits_N[137])
+	);
+
+	LHQD1 Inst_frame8_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[136]),
+	.QN(ConfigBits_N[136])
+	);
+
+	LHQD1 Inst_frame8_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[135]),
+	.QN(ConfigBits_N[135])
+	);
+
+	LHQD1 Inst_frame8_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[134]),
+	.QN(ConfigBits_N[134])
+	);
+
+	LHQD1 Inst_frame8_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[133]),
+	.QN(ConfigBits_N[133])
+	);
+
+	LHQD1 Inst_frame8_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[132]),
+	.QN(ConfigBits_N[132])
+	);
+
+	LHQD1 Inst_frame8_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[131]),
+	.QN(ConfigBits_N[131])
+	);
+
+	LHQD1 Inst_frame8_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[130]),
+	.QN(ConfigBits_N[130])
+	);
+
+	LHQD1 Inst_frame8_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[129]),
+	.QN(ConfigBits_N[129])
+	);
+
+	LHQD1 Inst_frame8_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[128]),
+	.QN(ConfigBits_N[128])
+	);
+
+	LHQD1 Inst_frame8_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[127]),
+	.QN(ConfigBits_N[127])
+	);
+
+	LHQD1 Inst_frame8_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[8]),
+	.Q(ConfigBits[126]),
+	.QN(ConfigBits_N[126])
+	);
+
+	LHQD1 Inst_frame9_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[125]),
+	.QN(ConfigBits_N[125])
+	);
+
+	LHQD1 Inst_frame9_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[124]),
+	.QN(ConfigBits_N[124])
+	);
+
+	LHQD1 Inst_frame9_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[123]),
+	.QN(ConfigBits_N[123])
+	);
+
+	LHQD1 Inst_frame9_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[122]),
+	.QN(ConfigBits_N[122])
+	);
+
+	LHQD1 Inst_frame9_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[121]),
+	.QN(ConfigBits_N[121])
+	);
+
+	LHQD1 Inst_frame9_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[120]),
+	.QN(ConfigBits_N[120])
+	);
+
+	LHQD1 Inst_frame9_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[119]),
+	.QN(ConfigBits_N[119])
+	);
+
+	LHQD1 Inst_frame9_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[118]),
+	.QN(ConfigBits_N[118])
+	);
+
+	LHQD1 Inst_frame9_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[117]),
+	.QN(ConfigBits_N[117])
+	);
+
+	LHQD1 Inst_frame9_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[116]),
+	.QN(ConfigBits_N[116])
+	);
+
+	LHQD1 Inst_frame9_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[115]),
+	.QN(ConfigBits_N[115])
+	);
+
+	LHQD1 Inst_frame9_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[114]),
+	.QN(ConfigBits_N[114])
+	);
+
+	LHQD1 Inst_frame9_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_frame9_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_frame9_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_frame9_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_frame9_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_frame9_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_frame9_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_frame9_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_frame9_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_frame9_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_frame9_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_frame9_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_frame9_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_frame9_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_frame9_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_frame9_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_frame9_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_frame9_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_frame9_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_frame9_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[9]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_frame10_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_frame10_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_frame10_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_frame10_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_frame10_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_frame10_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_frame10_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_frame10_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_frame10_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_frame10_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_frame10_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_frame10_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_frame10_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_frame10_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_frame10_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_frame10_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_frame10_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_frame10_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_frame10_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_frame10_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_frame10_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_frame10_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_frame10_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_frame10_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_frame10_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_frame10_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_frame10_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_frame10_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_frame10_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_frame10_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_frame10_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_frame10_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[10]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_frame11_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_frame11_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_frame11_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_frame11_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_frame11_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_frame11_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_frame11_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_frame11_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_frame11_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_frame11_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_frame11_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_frame11_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_frame11_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_frame11_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_frame11_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_frame11_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_frame11_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_frame11_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_frame11_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_frame11_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_frame11_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_frame11_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_frame11_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_frame11_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_frame11_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_frame11_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_frame11_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_frame11_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_frame11_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_frame11_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_frame11_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_frame11_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[11]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_frame12_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_frame12_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_frame12_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_frame12_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_frame12_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_frame12_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_frame12_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_frame12_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_frame12_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_frame12_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_frame12_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame12_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame12_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame12_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame12_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame12_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame12_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame12_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame12_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame12_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame12_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame12_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame12_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame12_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame12_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame12_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame12_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame12_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame12_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame12_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[12]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RegFile_switch_matrix.v b/verilog/rtl/eFPGA_core/RegFile_switch_matrix.v
new file mode 100644
index 0000000..81345d1
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RegFile_switch_matrix.v
@@ -0,0 +1,4082 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:412
+module RegFile_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, NN4END0, NN4END1, NN4END2, NN4END3, E1END0, E1END1, E1END2, E1END3, E2MID0, E2MID1, E2MID2, E2MID3, E2MID4, E2MID5, E2MID6, E2MID7, E2END0, E2END1, E2END2, E2END3, E2END4, E2END5, E2END6, E2END7, EE4END0, EE4END1, EE4END2, EE4END3, E6END0, E6END1, S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, SS4END0, SS4END1, SS4END2, SS4END3, W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, W6END0, W6END1, AD0, AD1, AD2, AD3, BD0, BD1, BD2, BD3, J2MID_ABa_END0, J2MID_ABa_END1, J2MID_ABa_END2, J2MID_ABa_END3, J2MID_CDa_END0, J2MID_CDa_END1, J2MID_CDa_END2, J2MID_CDa_END3, J2MID_EFa_END0, J2MID_EFa_END1, J2MID_EFa_END2, J2MID_EFa_END3, J2MID_GHa_END0, J2MID_GHa_END1, J2MID_GHa_END2, J2MID_GHa_END3, J2MID_ABb_END0, J2MID_ABb_END1, J2MID_ABb_END2, J2MID_ABb_END3, J2MID_CDb_END0, J2MID_CDb_END1, J2MID_CDb_END2, J2MID_CDb_END3, J2MID_EFb_END0, J2MID_EFb_END1, J2MID_EFb_END2, J2MID_EFb_END3, J2MID_GHb_END0, J2MID_GHb_END1, J2MID_GHb_END2, J2MID_GHb_END3, J2END_AB_END0, J2END_AB_END1, J2END_AB_END2, J2END_AB_END3, J2END_CD_END0, J2END_CD_END1, J2END_CD_END2, J2END_CD_END3, J2END_EF_END0, J2END_EF_END1, J2END_EF_END2, J2END_EF_END3, J2END_GH_END0, J2END_GH_END1, J2END_GH_END2, J2END_GH_END3, JN2END0, JN2END1, JN2END2, JN2END3, JN2END4, JN2END5, JN2END6, JN2END7, JE2END0, JE2END1, JE2END2, JE2END3, JE2END4, JE2END5, JE2END6, JE2END7, JS2END0, JS2END1, JS2END2, JS2END3, JS2END4, JS2END5, JS2END6, JS2END7, JW2END0, JW2END1, JW2END2, JW2END3, JW2END4, JW2END5, JW2END6, JW2END7, J_l_AB_END0, J_l_AB_END1, J_l_AB_END2, J_l_AB_END3, J_l_CD_END0, J_l_CD_END1, J_l_CD_END2, J_l_CD_END3, J_l_EF_END0, J_l_EF_END1, J_l_EF_END2, J_l_EF_END3, J_l_GH_END0, J_l_GH_END1, J_l_GH_END2, J_l_GH_END3, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, E6BEG0, E6BEG1, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, W1BEG0, W1BEG1, W1BEG2, W1BEG3, W2BEG0, W2BEG1, W2BEG2, W2BEG3, W2BEG4, W2BEG5, W2BEG6, W2BEG7, W2BEGb0, W2BEGb1, W2BEGb2, W2BEGb3, W2BEGb4, W2BEGb5, W2BEGb6, W2BEGb7, WW4BEG0, WW4BEG1, WW4BEG2, WW4BEG3, W6BEG0, W6BEG1, D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, J2MID_ABa_BEG0, J2MID_ABa_BEG1, J2MID_ABa_BEG2, J2MID_ABa_BEG3, J2MID_CDa_BEG0, J2MID_CDa_BEG1, J2MID_CDa_BEG2, J2MID_CDa_BEG3, J2MID_EFa_BEG0, J2MID_EFa_BEG1, J2MID_EFa_BEG2, J2MID_EFa_BEG3, J2MID_GHa_BEG0, J2MID_GHa_BEG1, J2MID_GHa_BEG2, J2MID_GHa_BEG3, J2MID_ABb_BEG0, J2MID_ABb_BEG1, J2MID_ABb_BEG2, J2MID_ABb_BEG3, J2MID_CDb_BEG0, J2MID_CDb_BEG1, J2MID_CDb_BEG2, J2MID_CDb_BEG3, J2MID_EFb_BEG0, J2MID_EFb_BEG1, J2MID_EFb_BEG2, J2MID_EFb_BEG3, J2MID_GHb_BEG0, J2MID_GHb_BEG1, J2MID_GHb_BEG2, J2MID_GHb_BEG3, J2END_AB_BEG0, J2END_AB_BEG1, J2END_AB_BEG2, J2END_AB_BEG3, J2END_CD_BEG0, J2END_CD_BEG1, J2END_CD_BEG2, J2END_CD_BEG3, J2END_EF_BEG0, J2END_EF_BEG1, J2END_EF_BEG2, J2END_EF_BEG3, J2END_GH_BEG0, J2END_GH_BEG1, J2END_GH_BEG2, J2END_GH_BEG3, JN2BEG0, JN2BEG1, JN2BEG2, JN2BEG3, JN2BEG4, JN2BEG5, JN2BEG6, JN2BEG7, JE2BEG0, JE2BEG1, JE2BEG2, JE2BEG3, JE2BEG4, JE2BEG5, JE2BEG6, JE2BEG7, JS2BEG0, JS2BEG1, JS2BEG2, JS2BEG3, JS2BEG4, JS2BEG5, JS2BEG6, JS2BEG7, JW2BEG0, JW2BEG1, JW2BEG2, JW2BEG3, JW2BEG4, JW2BEG5, JW2BEG6, JW2BEG7, J_l_AB_BEG0, J_l_AB_BEG1, J_l_AB_BEG2, J_l_AB_BEG3, J_l_CD_BEG0, J_l_CD_BEG1, J_l_CD_BEG2, J_l_CD_BEG3, J_l_EF_BEG0, J_l_EF_BEG1, J_l_EF_BEG2, J_l_EF_BEG3, J_l_GH_BEG0, J_l_GH_BEG1, J_l_GH_BEG2, J_l_GH_BEG3, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 412;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input E1END0;
+	input E1END1;
+	input E1END2;
+	input E1END3;
+	input E2MID0;
+	input E2MID1;
+	input E2MID2;
+	input E2MID3;
+	input E2MID4;
+	input E2MID5;
+	input E2MID6;
+	input E2MID7;
+	input E2END0;
+	input E2END1;
+	input E2END2;
+	input E2END3;
+	input E2END4;
+	input E2END5;
+	input E2END6;
+	input E2END7;
+	input EE4END0;
+	input EE4END1;
+	input EE4END2;
+	input EE4END3;
+	input E6END0;
+	input E6END1;
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input W6END0;
+	input W6END1;
+	input AD0;
+	input AD1;
+	input AD2;
+	input AD3;
+	input BD0;
+	input BD1;
+	input BD2;
+	input BD3;
+	input J2MID_ABa_END0;
+	input J2MID_ABa_END1;
+	input J2MID_ABa_END2;
+	input J2MID_ABa_END3;
+	input J2MID_CDa_END0;
+	input J2MID_CDa_END1;
+	input J2MID_CDa_END2;
+	input J2MID_CDa_END3;
+	input J2MID_EFa_END0;
+	input J2MID_EFa_END1;
+	input J2MID_EFa_END2;
+	input J2MID_EFa_END3;
+	input J2MID_GHa_END0;
+	input J2MID_GHa_END1;
+	input J2MID_GHa_END2;
+	input J2MID_GHa_END3;
+	input J2MID_ABb_END0;
+	input J2MID_ABb_END1;
+	input J2MID_ABb_END2;
+	input J2MID_ABb_END3;
+	input J2MID_CDb_END0;
+	input J2MID_CDb_END1;
+	input J2MID_CDb_END2;
+	input J2MID_CDb_END3;
+	input J2MID_EFb_END0;
+	input J2MID_EFb_END1;
+	input J2MID_EFb_END2;
+	input J2MID_EFb_END3;
+	input J2MID_GHb_END0;
+	input J2MID_GHb_END1;
+	input J2MID_GHb_END2;
+	input J2MID_GHb_END3;
+	input J2END_AB_END0;
+	input J2END_AB_END1;
+	input J2END_AB_END2;
+	input J2END_AB_END3;
+	input J2END_CD_END0;
+	input J2END_CD_END1;
+	input J2END_CD_END2;
+	input J2END_CD_END3;
+	input J2END_EF_END0;
+	input J2END_EF_END1;
+	input J2END_EF_END2;
+	input J2END_EF_END3;
+	input J2END_GH_END0;
+	input J2END_GH_END1;
+	input J2END_GH_END2;
+	input J2END_GH_END3;
+	input JN2END0;
+	input JN2END1;
+	input JN2END2;
+	input JN2END3;
+	input JN2END4;
+	input JN2END5;
+	input JN2END6;
+	input JN2END7;
+	input JE2END0;
+	input JE2END1;
+	input JE2END2;
+	input JE2END3;
+	input JE2END4;
+	input JE2END5;
+	input JE2END6;
+	input JE2END7;
+	input JS2END0;
+	input JS2END1;
+	input JS2END2;
+	input JS2END3;
+	input JS2END4;
+	input JS2END5;
+	input JS2END6;
+	input JS2END7;
+	input JW2END0;
+	input JW2END1;
+	input JW2END2;
+	input JW2END3;
+	input JW2END4;
+	input JW2END5;
+	input JW2END6;
+	input JW2END7;
+	input J_l_AB_END0;
+	input J_l_AB_END1;
+	input J_l_AB_END2;
+	input J_l_AB_END3;
+	input J_l_CD_END0;
+	input J_l_CD_END1;
+	input J_l_CD_END2;
+	input J_l_CD_END3;
+	input J_l_EF_END0;
+	input J_l_EF_END1;
+	input J_l_EF_END2;
+	input J_l_EF_END3;
+	input J_l_GH_END0;
+	input J_l_GH_END1;
+	input J_l_GH_END2;
+	input J_l_GH_END3;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output E6BEG0;
+	output E6BEG1;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output W1BEG0;
+	output W1BEG1;
+	output W1BEG2;
+	output W1BEG3;
+	output W2BEG0;
+	output W2BEG1;
+	output W2BEG2;
+	output W2BEG3;
+	output W2BEG4;
+	output W2BEG5;
+	output W2BEG6;
+	output W2BEG7;
+	output W2BEGb0;
+	output W2BEGb1;
+	output W2BEGb2;
+	output W2BEGb3;
+	output W2BEGb4;
+	output W2BEGb5;
+	output W2BEGb6;
+	output W2BEGb7;
+	output WW4BEG0;
+	output WW4BEG1;
+	output WW4BEG2;
+	output WW4BEG3;
+	output W6BEG0;
+	output W6BEG1;
+	output D0;
+	output D1;
+	output D2;
+	output D3;
+	output W_ADR0;
+	output W_ADR1;
+	output W_ADR2;
+	output W_ADR3;
+	output W_ADR4;
+	output W_en;
+	output A_ADR0;
+	output A_ADR1;
+	output A_ADR2;
+	output A_ADR3;
+	output A_ADR4;
+	output B_ADR0;
+	output B_ADR1;
+	output B_ADR2;
+	output B_ADR3;
+	output B_ADR4;
+	output J2MID_ABa_BEG0;
+	output J2MID_ABa_BEG1;
+	output J2MID_ABa_BEG2;
+	output J2MID_ABa_BEG3;
+	output J2MID_CDa_BEG0;
+	output J2MID_CDa_BEG1;
+	output J2MID_CDa_BEG2;
+	output J2MID_CDa_BEG3;
+	output J2MID_EFa_BEG0;
+	output J2MID_EFa_BEG1;
+	output J2MID_EFa_BEG2;
+	output J2MID_EFa_BEG3;
+	output J2MID_GHa_BEG0;
+	output J2MID_GHa_BEG1;
+	output J2MID_GHa_BEG2;
+	output J2MID_GHa_BEG3;
+	output J2MID_ABb_BEG0;
+	output J2MID_ABb_BEG1;
+	output J2MID_ABb_BEG2;
+	output J2MID_ABb_BEG3;
+	output J2MID_CDb_BEG0;
+	output J2MID_CDb_BEG1;
+	output J2MID_CDb_BEG2;
+	output J2MID_CDb_BEG3;
+	output J2MID_EFb_BEG0;
+	output J2MID_EFb_BEG1;
+	output J2MID_EFb_BEG2;
+	output J2MID_EFb_BEG3;
+	output J2MID_GHb_BEG0;
+	output J2MID_GHb_BEG1;
+	output J2MID_GHb_BEG2;
+	output J2MID_GHb_BEG3;
+	output J2END_AB_BEG0;
+	output J2END_AB_BEG1;
+	output J2END_AB_BEG2;
+	output J2END_AB_BEG3;
+	output J2END_CD_BEG0;
+	output J2END_CD_BEG1;
+	output J2END_CD_BEG2;
+	output J2END_CD_BEG3;
+	output J2END_EF_BEG0;
+	output J2END_EF_BEG1;
+	output J2END_EF_BEG2;
+	output J2END_EF_BEG3;
+	output J2END_GH_BEG0;
+	output J2END_GH_BEG1;
+	output J2END_GH_BEG2;
+	output J2END_GH_BEG3;
+	output JN2BEG0;
+	output JN2BEG1;
+	output JN2BEG2;
+	output JN2BEG3;
+	output JN2BEG4;
+	output JN2BEG5;
+	output JN2BEG6;
+	output JN2BEG7;
+	output JE2BEG0;
+	output JE2BEG1;
+	output JE2BEG2;
+	output JE2BEG3;
+	output JE2BEG4;
+	output JE2BEG5;
+	output JE2BEG6;
+	output JE2BEG7;
+	output JS2BEG0;
+	output JS2BEG1;
+	output JS2BEG2;
+	output JS2BEG3;
+	output JS2BEG4;
+	output JS2BEG5;
+	output JS2BEG6;
+	output JS2BEG7;
+	output JW2BEG0;
+	output JW2BEG1;
+	output JW2BEG2;
+	output JW2BEG3;
+	output JW2BEG4;
+	output JW2BEG5;
+	output JW2BEG6;
+	output JW2BEG7;
+	output J_l_AB_BEG0;
+	output J_l_AB_BEG1;
+	output J_l_AB_BEG2;
+	output J_l_AB_BEG3;
+	output J_l_CD_BEG0;
+	output J_l_CD_BEG1;
+	output J_l_CD_BEG2;
+	output J_l_CD_BEG3;
+	output J_l_EF_BEG0;
+	output J_l_EF_BEG1;
+	output J_l_EF_BEG2;
+	output J_l_EF_BEG3;
+	output J_l_GH_BEG0;
+	output J_l_GH_BEG1;
+	output J_l_GH_BEG2;
+	output J_l_GH_BEG3;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [4-1:0] N1BEG0_input;
+	wire [4-1:0] N1BEG1_input;
+	wire [4-1:0] N1BEG2_input;
+	wire [4-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [4-1:0] N4BEG0_input;
+	wire [4-1:0] N4BEG1_input;
+	wire [4-1:0] N4BEG2_input;
+	wire [4-1:0] N4BEG3_input;
+	wire [8-1:0] NN4BEG0_input;
+	wire [8-1:0] NN4BEG1_input;
+	wire [8-1:0] NN4BEG2_input;
+	wire [8-1:0] NN4BEG3_input;
+	wire [4-1:0] E1BEG0_input;
+	wire [4-1:0] E1BEG1_input;
+	wire [4-1:0] E1BEG2_input;
+	wire [4-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [8-1:0] EE4BEG0_input;
+	wire [8-1:0] EE4BEG1_input;
+	wire [8-1:0] EE4BEG2_input;
+	wire [8-1:0] EE4BEG3_input;
+	wire [16-1:0] E6BEG0_input;
+	wire [16-1:0] E6BEG1_input;
+	wire [4-1:0] S1BEG0_input;
+	wire [4-1:0] S1BEG1_input;
+	wire [4-1:0] S1BEG2_input;
+	wire [4-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [4-1:0] S4BEG0_input;
+	wire [4-1:0] S4BEG1_input;
+	wire [4-1:0] S4BEG2_input;
+	wire [4-1:0] S4BEG3_input;
+	wire [8-1:0] SS4BEG0_input;
+	wire [8-1:0] SS4BEG1_input;
+	wire [8-1:0] SS4BEG2_input;
+	wire [8-1:0] SS4BEG3_input;
+	wire [4-1:0] W1BEG0_input;
+	wire [4-1:0] W1BEG1_input;
+	wire [4-1:0] W1BEG2_input;
+	wire [4-1:0] W1BEG3_input;
+	wire [1-1:0] W2BEG0_input;
+	wire [1-1:0] W2BEG1_input;
+	wire [1-1:0] W2BEG2_input;
+	wire [1-1:0] W2BEG3_input;
+	wire [1-1:0] W2BEG4_input;
+	wire [1-1:0] W2BEG5_input;
+	wire [1-1:0] W2BEG6_input;
+	wire [1-1:0] W2BEG7_input;
+	wire [1-1:0] W2BEGb0_input;
+	wire [1-1:0] W2BEGb1_input;
+	wire [1-1:0] W2BEGb2_input;
+	wire [1-1:0] W2BEGb3_input;
+	wire [1-1:0] W2BEGb4_input;
+	wire [1-1:0] W2BEGb5_input;
+	wire [1-1:0] W2BEGb6_input;
+	wire [1-1:0] W2BEGb7_input;
+	wire [8-1:0] WW4BEG0_input;
+	wire [8-1:0] WW4BEG1_input;
+	wire [8-1:0] WW4BEG2_input;
+	wire [8-1:0] WW4BEG3_input;
+	wire [16-1:0] W6BEG0_input;
+	wire [16-1:0] W6BEG1_input;
+	wire [4-1:0] D0_input;
+	wire [4-1:0] D1_input;
+	wire [4-1:0] D2_input;
+	wire [4-1:0] D3_input;
+	wire [4-1:0] W_ADR0_input;
+	wire [4-1:0] W_ADR1_input;
+	wire [4-1:0] W_ADR2_input;
+	wire [4-1:0] W_ADR3_input;
+	wire [8-1:0] W_ADR4_input;
+	wire [8-1:0] W_en_input;
+	wire [4-1:0] A_ADR0_input;
+	wire [4-1:0] A_ADR1_input;
+	wire [4-1:0] A_ADR2_input;
+	wire [4-1:0] A_ADR3_input;
+	wire [8-1:0] A_ADR4_input;
+	wire [4-1:0] B_ADR0_input;
+	wire [4-1:0] B_ADR1_input;
+	wire [4-1:0] B_ADR2_input;
+	wire [4-1:0] B_ADR3_input;
+	wire [8-1:0] B_ADR4_input;
+	wire [4-1:0] J2MID_ABa_BEG0_input;
+	wire [4-1:0] J2MID_ABa_BEG1_input;
+	wire [4-1:0] J2MID_ABa_BEG2_input;
+	wire [4-1:0] J2MID_ABa_BEG3_input;
+	wire [4-1:0] J2MID_CDa_BEG0_input;
+	wire [4-1:0] J2MID_CDa_BEG1_input;
+	wire [4-1:0] J2MID_CDa_BEG2_input;
+	wire [4-1:0] J2MID_CDa_BEG3_input;
+	wire [4-1:0] J2MID_EFa_BEG0_input;
+	wire [4-1:0] J2MID_EFa_BEG1_input;
+	wire [4-1:0] J2MID_EFa_BEG2_input;
+	wire [4-1:0] J2MID_EFa_BEG3_input;
+	wire [4-1:0] J2MID_GHa_BEG0_input;
+	wire [4-1:0] J2MID_GHa_BEG1_input;
+	wire [4-1:0] J2MID_GHa_BEG2_input;
+	wire [4-1:0] J2MID_GHa_BEG3_input;
+	wire [4-1:0] J2MID_ABb_BEG0_input;
+	wire [4-1:0] J2MID_ABb_BEG1_input;
+	wire [4-1:0] J2MID_ABb_BEG2_input;
+	wire [4-1:0] J2MID_ABb_BEG3_input;
+	wire [4-1:0] J2MID_CDb_BEG0_input;
+	wire [4-1:0] J2MID_CDb_BEG1_input;
+	wire [4-1:0] J2MID_CDb_BEG2_input;
+	wire [4-1:0] J2MID_CDb_BEG3_input;
+	wire [4-1:0] J2MID_EFb_BEG0_input;
+	wire [4-1:0] J2MID_EFb_BEG1_input;
+	wire [4-1:0] J2MID_EFb_BEG2_input;
+	wire [4-1:0] J2MID_EFb_BEG3_input;
+	wire [4-1:0] J2MID_GHb_BEG0_input;
+	wire [4-1:0] J2MID_GHb_BEG1_input;
+	wire [4-1:0] J2MID_GHb_BEG2_input;
+	wire [4-1:0] J2MID_GHb_BEG3_input;
+	wire [4-1:0] J2END_AB_BEG0_input;
+	wire [4-1:0] J2END_AB_BEG1_input;
+	wire [4-1:0] J2END_AB_BEG2_input;
+	wire [4-1:0] J2END_AB_BEG3_input;
+	wire [4-1:0] J2END_CD_BEG0_input;
+	wire [4-1:0] J2END_CD_BEG1_input;
+	wire [4-1:0] J2END_CD_BEG2_input;
+	wire [4-1:0] J2END_CD_BEG3_input;
+	wire [4-1:0] J2END_EF_BEG0_input;
+	wire [4-1:0] J2END_EF_BEG1_input;
+	wire [4-1:0] J2END_EF_BEG2_input;
+	wire [4-1:0] J2END_EF_BEG3_input;
+	wire [4-1:0] J2END_GH_BEG0_input;
+	wire [4-1:0] J2END_GH_BEG1_input;
+	wire [4-1:0] J2END_GH_BEG2_input;
+	wire [4-1:0] J2END_GH_BEG3_input;
+	wire [16-1:0] JN2BEG0_input;
+	wire [16-1:0] JN2BEG1_input;
+	wire [16-1:0] JN2BEG2_input;
+	wire [16-1:0] JN2BEG3_input;
+	wire [16-1:0] JN2BEG4_input;
+	wire [16-1:0] JN2BEG5_input;
+	wire [16-1:0] JN2BEG6_input;
+	wire [16-1:0] JN2BEG7_input;
+	wire [16-1:0] JE2BEG0_input;
+	wire [16-1:0] JE2BEG1_input;
+	wire [16-1:0] JE2BEG2_input;
+	wire [16-1:0] JE2BEG3_input;
+	wire [16-1:0] JE2BEG4_input;
+	wire [16-1:0] JE2BEG5_input;
+	wire [16-1:0] JE2BEG6_input;
+	wire [16-1:0] JE2BEG7_input;
+	wire [16-1:0] JS2BEG0_input;
+	wire [16-1:0] JS2BEG1_input;
+	wire [16-1:0] JS2BEG2_input;
+	wire [16-1:0] JS2BEG3_input;
+	wire [16-1:0] JS2BEG4_input;
+	wire [16-1:0] JS2BEG5_input;
+	wire [16-1:0] JS2BEG6_input;
+	wire [16-1:0] JS2BEG7_input;
+	wire [16-1:0] JW2BEG0_input;
+	wire [16-1:0] JW2BEG1_input;
+	wire [16-1:0] JW2BEG2_input;
+	wire [16-1:0] JW2BEG3_input;
+	wire [16-1:0] JW2BEG4_input;
+	wire [16-1:0] JW2BEG5_input;
+	wire [16-1:0] JW2BEG6_input;
+	wire [16-1:0] JW2BEG7_input;
+	wire [4-1:0] J_l_AB_BEG0_input;
+	wire [4-1:0] J_l_AB_BEG1_input;
+	wire [4-1:0] J_l_AB_BEG2_input;
+	wire [4-1:0] J_l_AB_BEG3_input;
+	wire [4-1:0] J_l_CD_BEG0_input;
+	wire [4-1:0] J_l_CD_BEG1_input;
+	wire [4-1:0] J_l_CD_BEG2_input;
+	wire [4-1:0] J_l_CD_BEG3_input;
+	wire [4-1:0] J_l_EF_BEG0_input;
+	wire [4-1:0] J_l_EF_BEG1_input;
+	wire [4-1:0] J_l_EF_BEG2_input;
+	wire [4-1:0] J_l_EF_BEG3_input;
+	wire [4-1:0] J_l_GH_BEG0_input;
+	wire [4-1:0] J_l_GH_BEG1_input;
+	wire [4-1:0] J_l_GH_BEG2_input;
+	wire [4-1:0] J_l_GH_BEG3_input;
+
+	wire [2-1:0] DEBUG_select_N1BEG0;
+	wire [2-1:0] DEBUG_select_N1BEG1;
+	wire [2-1:0] DEBUG_select_N1BEG2;
+	wire [2-1:0] DEBUG_select_N1BEG3;
+	wire [2-1:0] DEBUG_select_N4BEG0;
+	wire [2-1:0] DEBUG_select_N4BEG1;
+	wire [2-1:0] DEBUG_select_N4BEG2;
+	wire [2-1:0] DEBUG_select_N4BEG3;
+	wire [3-1:0] DEBUG_select_NN4BEG0;
+	wire [3-1:0] DEBUG_select_NN4BEG1;
+	wire [3-1:0] DEBUG_select_NN4BEG2;
+	wire [3-1:0] DEBUG_select_NN4BEG3;
+	wire [2-1:0] DEBUG_select_E1BEG0;
+	wire [2-1:0] DEBUG_select_E1BEG1;
+	wire [2-1:0] DEBUG_select_E1BEG2;
+	wire [2-1:0] DEBUG_select_E1BEG3;
+	wire [3-1:0] DEBUG_select_EE4BEG0;
+	wire [3-1:0] DEBUG_select_EE4BEG1;
+	wire [3-1:0] DEBUG_select_EE4BEG2;
+	wire [3-1:0] DEBUG_select_EE4BEG3;
+	wire [4-1:0] DEBUG_select_E6BEG0;
+	wire [4-1:0] DEBUG_select_E6BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG0;
+	wire [2-1:0] DEBUG_select_S1BEG1;
+	wire [2-1:0] DEBUG_select_S1BEG2;
+	wire [2-1:0] DEBUG_select_S1BEG3;
+	wire [2-1:0] DEBUG_select_S4BEG0;
+	wire [2-1:0] DEBUG_select_S4BEG1;
+	wire [2-1:0] DEBUG_select_S4BEG2;
+	wire [2-1:0] DEBUG_select_S4BEG3;
+	wire [3-1:0] DEBUG_select_SS4BEG0;
+	wire [3-1:0] DEBUG_select_SS4BEG1;
+	wire [3-1:0] DEBUG_select_SS4BEG2;
+	wire [3-1:0] DEBUG_select_SS4BEG3;
+	wire [2-1:0] DEBUG_select_W1BEG0;
+	wire [2-1:0] DEBUG_select_W1BEG1;
+	wire [2-1:0] DEBUG_select_W1BEG2;
+	wire [2-1:0] DEBUG_select_W1BEG3;
+	wire [3-1:0] DEBUG_select_WW4BEG0;
+	wire [3-1:0] DEBUG_select_WW4BEG1;
+	wire [3-1:0] DEBUG_select_WW4BEG2;
+	wire [3-1:0] DEBUG_select_WW4BEG3;
+	wire [4-1:0] DEBUG_select_W6BEG0;
+	wire [4-1:0] DEBUG_select_W6BEG1;
+	wire [2-1:0] DEBUG_select_D0;
+	wire [2-1:0] DEBUG_select_D1;
+	wire [2-1:0] DEBUG_select_D2;
+	wire [2-1:0] DEBUG_select_D3;
+	wire [2-1:0] DEBUG_select_W_ADR0;
+	wire [2-1:0] DEBUG_select_W_ADR1;
+	wire [2-1:0] DEBUG_select_W_ADR2;
+	wire [2-1:0] DEBUG_select_W_ADR3;
+	wire [3-1:0] DEBUG_select_W_ADR4;
+	wire [3-1:0] DEBUG_select_W_en;
+	wire [2-1:0] DEBUG_select_A_ADR0;
+	wire [2-1:0] DEBUG_select_A_ADR1;
+	wire [2-1:0] DEBUG_select_A_ADR2;
+	wire [2-1:0] DEBUG_select_A_ADR3;
+	wire [3-1:0] DEBUG_select_A_ADR4;
+	wire [2-1:0] DEBUG_select_B_ADR0;
+	wire [2-1:0] DEBUG_select_B_ADR1;
+	wire [2-1:0] DEBUG_select_B_ADR2;
+	wire [2-1:0] DEBUG_select_B_ADR3;
+	wire [3-1:0] DEBUG_select_B_ADR4;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHa_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_ABb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_CDb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_EFb_BEG3;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG0;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG1;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG2;
+	wire [2-1:0] DEBUG_select_J2MID_GHb_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J2END_GH_BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG0;
+	wire [4-1:0] DEBUG_select_JN2BEG1;
+	wire [4-1:0] DEBUG_select_JN2BEG2;
+	wire [4-1:0] DEBUG_select_JN2BEG3;
+	wire [4-1:0] DEBUG_select_JN2BEG4;
+	wire [4-1:0] DEBUG_select_JN2BEG5;
+	wire [4-1:0] DEBUG_select_JN2BEG6;
+	wire [4-1:0] DEBUG_select_JN2BEG7;
+	wire [4-1:0] DEBUG_select_JE2BEG0;
+	wire [4-1:0] DEBUG_select_JE2BEG1;
+	wire [4-1:0] DEBUG_select_JE2BEG2;
+	wire [4-1:0] DEBUG_select_JE2BEG3;
+	wire [4-1:0] DEBUG_select_JE2BEG4;
+	wire [4-1:0] DEBUG_select_JE2BEG5;
+	wire [4-1:0] DEBUG_select_JE2BEG6;
+	wire [4-1:0] DEBUG_select_JE2BEG7;
+	wire [4-1:0] DEBUG_select_JS2BEG0;
+	wire [4-1:0] DEBUG_select_JS2BEG1;
+	wire [4-1:0] DEBUG_select_JS2BEG2;
+	wire [4-1:0] DEBUG_select_JS2BEG3;
+	wire [4-1:0] DEBUG_select_JS2BEG4;
+	wire [4-1:0] DEBUG_select_JS2BEG5;
+	wire [4-1:0] DEBUG_select_JS2BEG6;
+	wire [4-1:0] DEBUG_select_JS2BEG7;
+	wire [4-1:0] DEBUG_select_JW2BEG0;
+	wire [4-1:0] DEBUG_select_JW2BEG1;
+	wire [4-1:0] DEBUG_select_JW2BEG2;
+	wire [4-1:0] DEBUG_select_JW2BEG3;
+	wire [4-1:0] DEBUG_select_JW2BEG4;
+	wire [4-1:0] DEBUG_select_JW2BEG5;
+	wire [4-1:0] DEBUG_select_JW2BEG6;
+	wire [4-1:0] DEBUG_select_JW2BEG7;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_AB_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_CD_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_EF_BEG3;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG0;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG1;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG2;
+	wire [2-1:0] DEBUG_select_J_l_GH_BEG3;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-4
+	assign N1BEG0_input = {J_l_CD_END1,JW2END3,J2MID_CDb_END3,AD2};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG0 (
+	.A0 (N1BEG0_input[0]),
+	.A1 (N1BEG0_input[1]),
+	.A2 (N1BEG0_input[2]),
+	.A3 (N1BEG0_input[3]),
+	.S0 (ConfigBits[0+0]),
+	.S0N (ConfigBits_N[0+0]),
+	.S1 (ConfigBits[0+1]),
+	.S1N (ConfigBits_N[0+1]),
+	.X (N1BEG0)
+	);
+
+// switch matrix multiplexer  N1BEG1 		MUX-4
+	assign N1BEG1_input = {J_l_EF_END2,JW2END0,J2MID_EFb_END0,AD3};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG1 (
+	.A0 (N1BEG1_input[0]),
+	.A1 (N1BEG1_input[1]),
+	.A2 (N1BEG1_input[2]),
+	.A3 (N1BEG1_input[3]),
+	.S0 (ConfigBits[2+0]),
+	.S0N (ConfigBits_N[2+0]),
+	.S1 (ConfigBits[2+1]),
+	.S1N (ConfigBits_N[2+1]),
+	.X (N1BEG1)
+	);
+
+// switch matrix multiplexer  N1BEG2 		MUX-4
+	assign N1BEG2_input = {J_l_GH_END3,JW2END1,J2MID_GHb_END1,BD0};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG2 (
+	.A0 (N1BEG2_input[0]),
+	.A1 (N1BEG2_input[1]),
+	.A2 (N1BEG2_input[2]),
+	.A3 (N1BEG2_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (N1BEG2)
+	);
+
+// switch matrix multiplexer  N1BEG3 		MUX-4
+	assign N1BEG3_input = {J_l_AB_END0,JW2END2,J2MID_ABb_END2,BD1};
+	cus_mux41_buf inst_cus_mux41_buf_N1BEG3 (
+	.A0 (N1BEG3_input[0]),
+	.A1 (N1BEG3_input[1]),
+	.A2 (N1BEG3_input[2]),
+	.A3 (N1BEG3_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (N1BEG3)
+	);
+
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = JN2END0;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = JN2END1;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = JN2END2;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = JN2END3;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = JN2END4;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = JN2END5;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = JN2END6;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = JN2END7;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = N2MID0;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = N2MID1;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = N2MID2;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = N2MID3;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = N2MID4;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = N2MID5;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = N2MID6;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = N2MID7;
+// switch matrix multiplexer  N4BEG0 		MUX-4
+	assign N4BEG0_input = {BD0,E6END1,N4END1,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG0 (
+	.A0 (N4BEG0_input[0]),
+	.A1 (N4BEG0_input[1]),
+	.A2 (N4BEG0_input[2]),
+	.A3 (N4BEG0_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (N4BEG0)
+	);
+
+// switch matrix multiplexer  N4BEG1 		MUX-4
+	assign N4BEG1_input = {BD1,E6END0,N4END2,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG1 (
+	.A0 (N4BEG1_input[0]),
+	.A1 (N4BEG1_input[1]),
+	.A2 (N4BEG1_input[2]),
+	.A3 (N4BEG1_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (N4BEG1)
+	);
+
+// switch matrix multiplexer  N4BEG2 		MUX-4
+	assign N4BEG2_input = {BD2,W6END1,N4END3,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG2 (
+	.A0 (N4BEG2_input[0]),
+	.A1 (N4BEG2_input[1]),
+	.A2 (N4BEG2_input[2]),
+	.A3 (N4BEG2_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (N4BEG2)
+	);
+
+// switch matrix multiplexer  N4BEG3 		MUX-4
+	assign N4BEG3_input = {BD3,W6END0,N4END0,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_N4BEG3 (
+	.A0 (N4BEG3_input[0]),
+	.A1 (N4BEG3_input[1]),
+	.A2 (N4BEG3_input[2]),
+	.A3 (N4BEG3_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (N4BEG3)
+	);
+
+// switch matrix multiplexer  NN4BEG0 		MUX-8
+	assign NN4BEG0_input = {J2END_GH_END1,J2MID_CDb_END1,J2MID_ABb_END1,BD1,AD1,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG0 (
+	.A0 (NN4BEG0_input[0]),
+	.A1 (NN4BEG0_input[1]),
+	.A2 (NN4BEG0_input[2]),
+	.A3 (NN4BEG0_input[3]),
+	.A4 (NN4BEG0_input[4]),
+	.A5 (NN4BEG0_input[5]),
+	.A6 (NN4BEG0_input[6]),
+	.A7 (NN4BEG0_input[7]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.S2 (ConfigBits[16+2]),
+	.S2N (ConfigBits_N[16+2]),
+	.X (NN4BEG0)
+	);
+
+// switch matrix multiplexer  NN4BEG1 		MUX-8
+	assign NN4BEG1_input = {J2END_EF_END1,J2MID_CDa_END2,J2MID_ABa_END2,BD2,AD2,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG1 (
+	.A0 (NN4BEG1_input[0]),
+	.A1 (NN4BEG1_input[1]),
+	.A2 (NN4BEG1_input[2]),
+	.A3 (NN4BEG1_input[3]),
+	.A4 (NN4BEG1_input[4]),
+	.A5 (NN4BEG1_input[5]),
+	.A6 (NN4BEG1_input[6]),
+	.A7 (NN4BEG1_input[7]),
+	.S0 (ConfigBits[19+0]),
+	.S0N (ConfigBits_N[19+0]),
+	.S1 (ConfigBits[19+1]),
+	.S1N (ConfigBits_N[19+1]),
+	.S2 (ConfigBits[19+2]),
+	.S2N (ConfigBits_N[19+2]),
+	.X (NN4BEG1)
+	);
+
+// switch matrix multiplexer  NN4BEG2 		MUX-8
+	assign NN4BEG2_input = {J2END_CD_END1,J2MID_GHb_END1,J2MID_EFb_END1,BD3,AD3,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG2 (
+	.A0 (NN4BEG2_input[0]),
+	.A1 (NN4BEG2_input[1]),
+	.A2 (NN4BEG2_input[2]),
+	.A3 (NN4BEG2_input[3]),
+	.A4 (NN4BEG2_input[4]),
+	.A5 (NN4BEG2_input[5]),
+	.A6 (NN4BEG2_input[6]),
+	.A7 (NN4BEG2_input[7]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.S2 (ConfigBits[22+2]),
+	.S2N (ConfigBits_N[22+2]),
+	.X (NN4BEG2)
+	);
+
+// switch matrix multiplexer  NN4BEG3 		MUX-8
+	assign NN4BEG3_input = {J2END_AB_END1,J2MID_GHa_END2,J2MID_EFa_END2,BD0,AD0,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_NN4BEG3 (
+	.A0 (NN4BEG3_input[0]),
+	.A1 (NN4BEG3_input[1]),
+	.A2 (NN4BEG3_input[2]),
+	.A3 (NN4BEG3_input[3]),
+	.A4 (NN4BEG3_input[4]),
+	.A5 (NN4BEG3_input[5]),
+	.A6 (NN4BEG3_input[6]),
+	.A7 (NN4BEG3_input[7]),
+	.S0 (ConfigBits[25+0]),
+	.S0N (ConfigBits_N[25+0]),
+	.S1 (ConfigBits[25+1]),
+	.S1N (ConfigBits_N[25+1]),
+	.S2 (ConfigBits[25+2]),
+	.S2N (ConfigBits_N[25+2]),
+	.X (NN4BEG3)
+	);
+
+// switch matrix multiplexer  E1BEG0 		MUX-4
+	assign E1BEG0_input = {J_l_CD_END1,JN2END3,J2MID_CDb_END3,AD3};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG0 (
+	.A0 (E1BEG0_input[0]),
+	.A1 (E1BEG0_input[1]),
+	.A2 (E1BEG0_input[2]),
+	.A3 (E1BEG0_input[3]),
+	.S0 (ConfigBits[28+0]),
+	.S0N (ConfigBits_N[28+0]),
+	.S1 (ConfigBits[28+1]),
+	.S1N (ConfigBits_N[28+1]),
+	.X (E1BEG0)
+	);
+
+// switch matrix multiplexer  E1BEG1 		MUX-4
+	assign E1BEG1_input = {J_l_EF_END2,JN2END0,J2MID_EFb_END0,BD0};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG1 (
+	.A0 (E1BEG1_input[0]),
+	.A1 (E1BEG1_input[1]),
+	.A2 (E1BEG1_input[2]),
+	.A3 (E1BEG1_input[3]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.X (E1BEG1)
+	);
+
+// switch matrix multiplexer  E1BEG2 		MUX-4
+	assign E1BEG2_input = {J_l_GH_END3,JN2END1,J2MID_GHb_END1,BD1};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG2 (
+	.A0 (E1BEG2_input[0]),
+	.A1 (E1BEG2_input[1]),
+	.A2 (E1BEG2_input[2]),
+	.A3 (E1BEG2_input[3]),
+	.S0 (ConfigBits[32+0]),
+	.S0N (ConfigBits_N[32+0]),
+	.S1 (ConfigBits[32+1]),
+	.S1N (ConfigBits_N[32+1]),
+	.X (E1BEG2)
+	);
+
+// switch matrix multiplexer  E1BEG3 		MUX-4
+	assign E1BEG3_input = {J_l_AB_END0,JN2END2,J2MID_ABb_END2,BD2};
+	cus_mux41_buf inst_cus_mux41_buf_E1BEG3 (
+	.A0 (E1BEG3_input[0]),
+	.A1 (E1BEG3_input[1]),
+	.A2 (E1BEG3_input[2]),
+	.A3 (E1BEG3_input[3]),
+	.S0 (ConfigBits[34+0]),
+	.S0N (ConfigBits_N[34+0]),
+	.S1 (ConfigBits[34+1]),
+	.S1N (ConfigBits_N[34+1]),
+	.X (E1BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = JE2END0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = JE2END1;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = JE2END2;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = JE2END3;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = JE2END4;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = JE2END5;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = JE2END6;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = JE2END7;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = E2MID0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = E2MID1;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = E2MID2;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = E2MID3;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = E2MID4;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = E2MID5;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = E2MID6;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = E2MID7;
+// switch matrix multiplexer  EE4BEG0 		MUX-8
+	assign EE4BEG0_input = {J2END_GH_END0,J2MID_CDb_END1,J2MID_ABb_END1,BD1,AD1,S1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG0 (
+	.A0 (EE4BEG0_input[0]),
+	.A1 (EE4BEG0_input[1]),
+	.A2 (EE4BEG0_input[2]),
+	.A3 (EE4BEG0_input[3]),
+	.A4 (EE4BEG0_input[4]),
+	.A5 (EE4BEG0_input[5]),
+	.A6 (EE4BEG0_input[6]),
+	.A7 (EE4BEG0_input[7]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.S2 (ConfigBits[36+2]),
+	.S2N (ConfigBits_N[36+2]),
+	.X (EE4BEG0)
+	);
+
+// switch matrix multiplexer  EE4BEG1 		MUX-8
+	assign EE4BEG1_input = {J2END_EF_END0,J2MID_CDa_END2,J2MID_ABa_END2,BD2,AD2,S1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG1 (
+	.A0 (EE4BEG1_input[0]),
+	.A1 (EE4BEG1_input[1]),
+	.A2 (EE4BEG1_input[2]),
+	.A3 (EE4BEG1_input[3]),
+	.A4 (EE4BEG1_input[4]),
+	.A5 (EE4BEG1_input[5]),
+	.A6 (EE4BEG1_input[6]),
+	.A7 (EE4BEG1_input[7]),
+	.S0 (ConfigBits[39+0]),
+	.S0N (ConfigBits_N[39+0]),
+	.S1 (ConfigBits[39+1]),
+	.S1N (ConfigBits_N[39+1]),
+	.S2 (ConfigBits[39+2]),
+	.S2N (ConfigBits_N[39+2]),
+	.X (EE4BEG1)
+	);
+
+// switch matrix multiplexer  EE4BEG2 		MUX-8
+	assign EE4BEG2_input = {J2END_CD_END0,J2MID_GHb_END1,J2MID_EFb_END1,BD3,AD3,S1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG2 (
+	.A0 (EE4BEG2_input[0]),
+	.A1 (EE4BEG2_input[1]),
+	.A2 (EE4BEG2_input[2]),
+	.A3 (EE4BEG2_input[3]),
+	.A4 (EE4BEG2_input[4]),
+	.A5 (EE4BEG2_input[5]),
+	.A6 (EE4BEG2_input[6]),
+	.A7 (EE4BEG2_input[7]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.S2 (ConfigBits[42+2]),
+	.S2N (ConfigBits_N[42+2]),
+	.X (EE4BEG2)
+	);
+
+// switch matrix multiplexer  EE4BEG3 		MUX-8
+	assign EE4BEG3_input = {J2END_AB_END0,J2MID_GHa_END2,J2MID_EFa_END2,BD0,AD0,S1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_EE4BEG3 (
+	.A0 (EE4BEG3_input[0]),
+	.A1 (EE4BEG3_input[1]),
+	.A2 (EE4BEG3_input[2]),
+	.A3 (EE4BEG3_input[3]),
+	.A4 (EE4BEG3_input[4]),
+	.A5 (EE4BEG3_input[5]),
+	.A6 (EE4BEG3_input[6]),
+	.A7 (EE4BEG3_input[7]),
+	.S0 (ConfigBits[45+0]),
+	.S0N (ConfigBits_N[45+0]),
+	.S1 (ConfigBits[45+1]),
+	.S1N (ConfigBits_N[45+1]),
+	.S2 (ConfigBits[45+2]),
+	.S2N (ConfigBits_N[45+2]),
+	.X (EE4BEG3)
+	);
+
+// switch matrix multiplexer  E6BEG0 		MUX-16
+	assign E6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,BD3,BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END3,SS4END0,E1END3,NN4END0};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG0 (
+	.A0 (E6BEG0_input[0]),
+	.A1 (E6BEG0_input[1]),
+	.A2 (E6BEG0_input[2]),
+	.A3 (E6BEG0_input[3]),
+	.A4 (E6BEG0_input[4]),
+	.A5 (E6BEG0_input[5]),
+	.A6 (E6BEG0_input[6]),
+	.A7 (E6BEG0_input[7]),
+	.A8 (E6BEG0_input[8]),
+	.A9 (E6BEG0_input[9]),
+	.A10 (E6BEG0_input[10]),
+	.A11 (E6BEG0_input[11]),
+	.A12 (E6BEG0_input[12]),
+	.A13 (E6BEG0_input[13]),
+	.A14 (E6BEG0_input[14]),
+	.A15 (E6BEG0_input[15]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.S2 (ConfigBits[48+2]),
+	.S2N (ConfigBits_N[48+2]),
+	.S3 (ConfigBits[48+3]),
+	.S3N (ConfigBits_N[48+3]),
+	.X (E6BEG0)
+	);
+
+// switch matrix multiplexer  E6BEG1 		MUX-16
+	assign E6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,BD3,BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END2,SS4END3,E1END2,NN4END3};
+	cus_mux161_buf inst_cus_mux161_buf_E6BEG1 (
+	.A0 (E6BEG1_input[0]),
+	.A1 (E6BEG1_input[1]),
+	.A2 (E6BEG1_input[2]),
+	.A3 (E6BEG1_input[3]),
+	.A4 (E6BEG1_input[4]),
+	.A5 (E6BEG1_input[5]),
+	.A6 (E6BEG1_input[6]),
+	.A7 (E6BEG1_input[7]),
+	.A8 (E6BEG1_input[8]),
+	.A9 (E6BEG1_input[9]),
+	.A10 (E6BEG1_input[10]),
+	.A11 (E6BEG1_input[11]),
+	.A12 (E6BEG1_input[12]),
+	.A13 (E6BEG1_input[13]),
+	.A14 (E6BEG1_input[14]),
+	.A15 (E6BEG1_input[15]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.S2 (ConfigBits[52+2]),
+	.S2N (ConfigBits_N[52+2]),
+	.S3 (ConfigBits[52+3]),
+	.S3N (ConfigBits_N[52+3]),
+	.X (E6BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG0 		MUX-4
+	assign S1BEG0_input = {J_l_CD_END1,JE2END3,J2MID_CDb_END3,BD0};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG0 (
+	.A0 (S1BEG0_input[0]),
+	.A1 (S1BEG0_input[1]),
+	.A2 (S1BEG0_input[2]),
+	.A3 (S1BEG0_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (S1BEG0)
+	);
+
+// switch matrix multiplexer  S1BEG1 		MUX-4
+	assign S1BEG1_input = {J_l_EF_END2,JE2END0,J2MID_EFb_END0,BD1};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG1 (
+	.A0 (S1BEG1_input[0]),
+	.A1 (S1BEG1_input[1]),
+	.A2 (S1BEG1_input[2]),
+	.A3 (S1BEG1_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (S1BEG1)
+	);
+
+// switch matrix multiplexer  S1BEG2 		MUX-4
+	assign S1BEG2_input = {J_l_GH_END3,JE2END1,J2MID_GHb_END1,BD2};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG2 (
+	.A0 (S1BEG2_input[0]),
+	.A1 (S1BEG2_input[1]),
+	.A2 (S1BEG2_input[2]),
+	.A3 (S1BEG2_input[3]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.X (S1BEG2)
+	);
+
+// switch matrix multiplexer  S1BEG3 		MUX-4
+	assign S1BEG3_input = {J_l_AB_END0,JE2END2,J2MID_ABb_END2,BD3};
+	cus_mux41_buf inst_cus_mux41_buf_S1BEG3 (
+	.A0 (S1BEG3_input[0]),
+	.A1 (S1BEG3_input[1]),
+	.A2 (S1BEG3_input[2]),
+	.A3 (S1BEG3_input[3]),
+	.S0 (ConfigBits[62+0]),
+	.S0N (ConfigBits_N[62+0]),
+	.S1 (ConfigBits[62+1]),
+	.S1N (ConfigBits_N[62+1]),
+	.X (S1BEG3)
+	);
+
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = JS2END0;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = JS2END1;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = JS2END2;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = JS2END3;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = JS2END4;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = JS2END5;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = JS2END6;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = JS2END7;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = S2MID0;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = S2MID1;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = S2MID2;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = S2MID3;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = S2MID4;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = S2MID5;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = S2MID6;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = S2MID7;
+// switch matrix multiplexer  S4BEG0 		MUX-4
+	assign S4BEG0_input = {AD0,S4END1,S2END2,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG0 (
+	.A0 (S4BEG0_input[0]),
+	.A1 (S4BEG0_input[1]),
+	.A2 (S4BEG0_input[2]),
+	.A3 (S4BEG0_input[3]),
+	.S0 (ConfigBits[64+0]),
+	.S0N (ConfigBits_N[64+0]),
+	.S1 (ConfigBits[64+1]),
+	.S1N (ConfigBits_N[64+1]),
+	.X (S4BEG0)
+	);
+
+// switch matrix multiplexer  S4BEG1 		MUX-4
+	assign S4BEG1_input = {AD1,S4END2,S2END3,E6END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG1 (
+	.A0 (S4BEG1_input[0]),
+	.A1 (S4BEG1_input[1]),
+	.A2 (S4BEG1_input[2]),
+	.A3 (S4BEG1_input[3]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.X (S4BEG1)
+	);
+
+// switch matrix multiplexer  S4BEG2 		MUX-4
+	assign S4BEG2_input = {AD2,W6END1,S4END3,S2END0};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG2 (
+	.A0 (S4BEG2_input[0]),
+	.A1 (S4BEG2_input[1]),
+	.A2 (S4BEG2_input[2]),
+	.A3 (S4BEG2_input[3]),
+	.S0 (ConfigBits[68+0]),
+	.S0N (ConfigBits_N[68+0]),
+	.S1 (ConfigBits[68+1]),
+	.S1N (ConfigBits_N[68+1]),
+	.X (S4BEG2)
+	);
+
+// switch matrix multiplexer  S4BEG3 		MUX-4
+	assign S4BEG3_input = {AD3,W6END0,S4END0,S2END1};
+	cus_mux41_buf inst_cus_mux41_buf_S4BEG3 (
+	.A0 (S4BEG3_input[0]),
+	.A1 (S4BEG3_input[1]),
+	.A2 (S4BEG3_input[2]),
+	.A3 (S4BEG3_input[3]),
+	.S0 (ConfigBits[70+0]),
+	.S0N (ConfigBits_N[70+0]),
+	.S1 (ConfigBits[70+1]),
+	.S1N (ConfigBits_N[70+1]),
+	.X (S4BEG3)
+	);
+
+// switch matrix multiplexer  SS4BEG0 		MUX-8
+	assign SS4BEG0_input = {J2END_GH_END3,J2MID_CDb_END1,J2MID_ABb_END1,BD1,AD1,W1END2,E1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG0 (
+	.A0 (SS4BEG0_input[0]),
+	.A1 (SS4BEG0_input[1]),
+	.A2 (SS4BEG0_input[2]),
+	.A3 (SS4BEG0_input[3]),
+	.A4 (SS4BEG0_input[4]),
+	.A5 (SS4BEG0_input[5]),
+	.A6 (SS4BEG0_input[6]),
+	.A7 (SS4BEG0_input[7]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.S2 (ConfigBits[72+2]),
+	.S2N (ConfigBits_N[72+2]),
+	.X (SS4BEG0)
+	);
+
+// switch matrix multiplexer  SS4BEG1 		MUX-8
+	assign SS4BEG1_input = {J2END_EF_END3,J2MID_CDa_END2,J2MID_ABa_END2,BD2,AD2,W1END3,E1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG1 (
+	.A0 (SS4BEG1_input[0]),
+	.A1 (SS4BEG1_input[1]),
+	.A2 (SS4BEG1_input[2]),
+	.A3 (SS4BEG1_input[3]),
+	.A4 (SS4BEG1_input[4]),
+	.A5 (SS4BEG1_input[5]),
+	.A6 (SS4BEG1_input[6]),
+	.A7 (SS4BEG1_input[7]),
+	.S0 (ConfigBits[75+0]),
+	.S0N (ConfigBits_N[75+0]),
+	.S1 (ConfigBits[75+1]),
+	.S1N (ConfigBits_N[75+1]),
+	.S2 (ConfigBits[75+2]),
+	.S2N (ConfigBits_N[75+2]),
+	.X (SS4BEG1)
+	);
+
+// switch matrix multiplexer  SS4BEG2 		MUX-8
+	assign SS4BEG2_input = {J2END_CD_END3,J2MID_GHb_END1,J2MID_EFb_END1,BD3,AD3,W1END0,E1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG2 (
+	.A0 (SS4BEG2_input[0]),
+	.A1 (SS4BEG2_input[1]),
+	.A2 (SS4BEG2_input[2]),
+	.A3 (SS4BEG2_input[3]),
+	.A4 (SS4BEG2_input[4]),
+	.A5 (SS4BEG2_input[5]),
+	.A6 (SS4BEG2_input[6]),
+	.A7 (SS4BEG2_input[7]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.S2 (ConfigBits[78+2]),
+	.S2N (ConfigBits_N[78+2]),
+	.X (SS4BEG2)
+	);
+
+// switch matrix multiplexer  SS4BEG3 		MUX-8
+	assign SS4BEG3_input = {J2END_AB_END3,J2MID_GHa_END2,J2MID_EFa_END2,BD0,AD0,W1END1,E1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_SS4BEG3 (
+	.A0 (SS4BEG3_input[0]),
+	.A1 (SS4BEG3_input[1]),
+	.A2 (SS4BEG3_input[2]),
+	.A3 (SS4BEG3_input[3]),
+	.A4 (SS4BEG3_input[4]),
+	.A5 (SS4BEG3_input[5]),
+	.A6 (SS4BEG3_input[6]),
+	.A7 (SS4BEG3_input[7]),
+	.S0 (ConfigBits[81+0]),
+	.S0N (ConfigBits_N[81+0]),
+	.S1 (ConfigBits[81+1]),
+	.S1N (ConfigBits_N[81+1]),
+	.S2 (ConfigBits[81+2]),
+	.S2N (ConfigBits_N[81+2]),
+	.X (SS4BEG3)
+	);
+
+// switch matrix multiplexer  W1BEG0 		MUX-4
+	assign W1BEG0_input = {J_l_CD_END1,JS2END3,J2MID_CDb_END3,BD1};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG0 (
+	.A0 (W1BEG0_input[0]),
+	.A1 (W1BEG0_input[1]),
+	.A2 (W1BEG0_input[2]),
+	.A3 (W1BEG0_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (W1BEG0)
+	);
+
+// switch matrix multiplexer  W1BEG1 		MUX-4
+	assign W1BEG1_input = {J_l_EF_END2,JS2END0,J2MID_EFb_END0,BD2};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG1 (
+	.A0 (W1BEG1_input[0]),
+	.A1 (W1BEG1_input[1]),
+	.A2 (W1BEG1_input[2]),
+	.A3 (W1BEG1_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (W1BEG1)
+	);
+
+// switch matrix multiplexer  W1BEG2 		MUX-4
+	assign W1BEG2_input = {J_l_GH_END3,JS2END1,J2MID_GHb_END1,BD3};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG2 (
+	.A0 (W1BEG2_input[0]),
+	.A1 (W1BEG2_input[1]),
+	.A2 (W1BEG2_input[2]),
+	.A3 (W1BEG2_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (W1BEG2)
+	);
+
+// switch matrix multiplexer  W1BEG3 		MUX-4
+	assign W1BEG3_input = {J_l_AB_END0,JS2END2,J2MID_ABb_END2,AD0};
+	cus_mux41_buf inst_cus_mux41_buf_W1BEG3 (
+	.A0 (W1BEG3_input[0]),
+	.A1 (W1BEG3_input[1]),
+	.A2 (W1BEG3_input[2]),
+	.A3 (W1BEG3_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (W1BEG3)
+	);
+
+// switch matrix multiplexer  W2BEG0 		MUX-1
+	assign W2BEG0 = JW2END0;
+// switch matrix multiplexer  W2BEG1 		MUX-1
+	assign W2BEG1 = JW2END1;
+// switch matrix multiplexer  W2BEG2 		MUX-1
+	assign W2BEG2 = JW2END2;
+// switch matrix multiplexer  W2BEG3 		MUX-1
+	assign W2BEG3 = JW2END3;
+// switch matrix multiplexer  W2BEG4 		MUX-1
+	assign W2BEG4 = JW2END4;
+// switch matrix multiplexer  W2BEG5 		MUX-1
+	assign W2BEG5 = JW2END5;
+// switch matrix multiplexer  W2BEG6 		MUX-1
+	assign W2BEG6 = JW2END6;
+// switch matrix multiplexer  W2BEG7 		MUX-1
+	assign W2BEG7 = JW2END7;
+// switch matrix multiplexer  W2BEGb0 		MUX-1
+	assign W2BEGb0 = W2MID0;
+// switch matrix multiplexer  W2BEGb1 		MUX-1
+	assign W2BEGb1 = W2MID1;
+// switch matrix multiplexer  W2BEGb2 		MUX-1
+	assign W2BEGb2 = W2MID2;
+// switch matrix multiplexer  W2BEGb3 		MUX-1
+	assign W2BEGb3 = W2MID3;
+// switch matrix multiplexer  W2BEGb4 		MUX-1
+	assign W2BEGb4 = W2MID4;
+// switch matrix multiplexer  W2BEGb5 		MUX-1
+	assign W2BEGb5 = W2MID5;
+// switch matrix multiplexer  W2BEGb6 		MUX-1
+	assign W2BEGb6 = W2MID6;
+// switch matrix multiplexer  W2BEGb7 		MUX-1
+	assign W2BEGb7 = W2MID7;
+// switch matrix multiplexer  WW4BEG0 		MUX-8
+	assign WW4BEG0_input = {J2END_GH_END2,J2MID_CDb_END1,J2MID_ABb_END1,BD1,AD1,W1END2,S1END2,N1END2};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG0 (
+	.A0 (WW4BEG0_input[0]),
+	.A1 (WW4BEG0_input[1]),
+	.A2 (WW4BEG0_input[2]),
+	.A3 (WW4BEG0_input[3]),
+	.A4 (WW4BEG0_input[4]),
+	.A5 (WW4BEG0_input[5]),
+	.A6 (WW4BEG0_input[6]),
+	.A7 (WW4BEG0_input[7]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.S2 (ConfigBits[92+2]),
+	.S2N (ConfigBits_N[92+2]),
+	.X (WW4BEG0)
+	);
+
+// switch matrix multiplexer  WW4BEG1 		MUX-8
+	assign WW4BEG1_input = {J2END_EF_END2,J2MID_CDa_END2,J2MID_ABa_END2,BD2,AD2,W1END3,S1END3,N1END3};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG1 (
+	.A0 (WW4BEG1_input[0]),
+	.A1 (WW4BEG1_input[1]),
+	.A2 (WW4BEG1_input[2]),
+	.A3 (WW4BEG1_input[3]),
+	.A4 (WW4BEG1_input[4]),
+	.A5 (WW4BEG1_input[5]),
+	.A6 (WW4BEG1_input[6]),
+	.A7 (WW4BEG1_input[7]),
+	.S0 (ConfigBits[95+0]),
+	.S0N (ConfigBits_N[95+0]),
+	.S1 (ConfigBits[95+1]),
+	.S1N (ConfigBits_N[95+1]),
+	.S2 (ConfigBits[95+2]),
+	.S2N (ConfigBits_N[95+2]),
+	.X (WW4BEG1)
+	);
+
+// switch matrix multiplexer  WW4BEG2 		MUX-8
+	assign WW4BEG2_input = {J2END_CD_END2,J2MID_GHb_END1,J2MID_EFb_END1,BD3,AD3,W1END0,S1END0,N1END0};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG2 (
+	.A0 (WW4BEG2_input[0]),
+	.A1 (WW4BEG2_input[1]),
+	.A2 (WW4BEG2_input[2]),
+	.A3 (WW4BEG2_input[3]),
+	.A4 (WW4BEG2_input[4]),
+	.A5 (WW4BEG2_input[5]),
+	.A6 (WW4BEG2_input[6]),
+	.A7 (WW4BEG2_input[7]),
+	.S0 (ConfigBits[98+0]),
+	.S0N (ConfigBits_N[98+0]),
+	.S1 (ConfigBits[98+1]),
+	.S1N (ConfigBits_N[98+1]),
+	.S2 (ConfigBits[98+2]),
+	.S2N (ConfigBits_N[98+2]),
+	.X (WW4BEG2)
+	);
+
+// switch matrix multiplexer  WW4BEG3 		MUX-8
+	assign WW4BEG3_input = {J2END_AB_END2,J2MID_GHa_END2,J2MID_EFa_END2,BD0,AD0,W1END1,S1END1,N1END1};
+	cus_mux81_buf inst_cus_mux81_buf_WW4BEG3 (
+	.A0 (WW4BEG3_input[0]),
+	.A1 (WW4BEG3_input[1]),
+	.A2 (WW4BEG3_input[2]),
+	.A3 (WW4BEG3_input[3]),
+	.A4 (WW4BEG3_input[4]),
+	.A5 (WW4BEG3_input[5]),
+	.A6 (WW4BEG3_input[6]),
+	.A7 (WW4BEG3_input[7]),
+	.S0 (ConfigBits[101+0]),
+	.S0N (ConfigBits_N[101+0]),
+	.S1 (ConfigBits[101+1]),
+	.S1N (ConfigBits_N[101+1]),
+	.S2 (ConfigBits[101+2]),
+	.S2N (ConfigBits_N[101+2]),
+	.X (WW4BEG3)
+	);
+
+// switch matrix multiplexer  W6BEG0 		MUX-16
+	assign W6BEG0_input = {J2MID_GHb_END1,J2MID_EFb_END1,J2MID_CDb_END1,J2MID_ABb_END1,BD3,BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END3,SS4END1,E1END3,NN4END1};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG0 (
+	.A0 (W6BEG0_input[0]),
+	.A1 (W6BEG0_input[1]),
+	.A2 (W6BEG0_input[2]),
+	.A3 (W6BEG0_input[3]),
+	.A4 (W6BEG0_input[4]),
+	.A5 (W6BEG0_input[5]),
+	.A6 (W6BEG0_input[6]),
+	.A7 (W6BEG0_input[7]),
+	.A8 (W6BEG0_input[8]),
+	.A9 (W6BEG0_input[9]),
+	.A10 (W6BEG0_input[10]),
+	.A11 (W6BEG0_input[11]),
+	.A12 (W6BEG0_input[12]),
+	.A13 (W6BEG0_input[13]),
+	.A14 (W6BEG0_input[14]),
+	.A15 (W6BEG0_input[15]),
+	.S0 (ConfigBits[104+0]),
+	.S0N (ConfigBits_N[104+0]),
+	.S1 (ConfigBits[104+1]),
+	.S1N (ConfigBits_N[104+1]),
+	.S2 (ConfigBits[104+2]),
+	.S2N (ConfigBits_N[104+2]),
+	.S3 (ConfigBits[104+3]),
+	.S3N (ConfigBits_N[104+3]),
+	.X (W6BEG0)
+	);
+
+// switch matrix multiplexer  W6BEG1 		MUX-16
+	assign W6BEG1_input = {J2MID_GHa_END2,J2MID_EFa_END2,J2MID_CDa_END2,J2MID_ABa_END2,BD3,BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END2,SS4END2,E1END2,NN4END2};
+	cus_mux161_buf inst_cus_mux161_buf_W6BEG1 (
+	.A0 (W6BEG1_input[0]),
+	.A1 (W6BEG1_input[1]),
+	.A2 (W6BEG1_input[2]),
+	.A3 (W6BEG1_input[3]),
+	.A4 (W6BEG1_input[4]),
+	.A5 (W6BEG1_input[5]),
+	.A6 (W6BEG1_input[6]),
+	.A7 (W6BEG1_input[7]),
+	.A8 (W6BEG1_input[8]),
+	.A9 (W6BEG1_input[9]),
+	.A10 (W6BEG1_input[10]),
+	.A11 (W6BEG1_input[11]),
+	.A12 (W6BEG1_input[12]),
+	.A13 (W6BEG1_input[13]),
+	.A14 (W6BEG1_input[14]),
+	.A15 (W6BEG1_input[15]),
+	.S0 (ConfigBits[108+0]),
+	.S0N (ConfigBits_N[108+0]),
+	.S1 (ConfigBits[108+1]),
+	.S1N (ConfigBits_N[108+1]),
+	.S2 (ConfigBits[108+2]),
+	.S2N (ConfigBits_N[108+2]),
+	.S3 (ConfigBits[108+3]),
+	.S3N (ConfigBits_N[108+3]),
+	.X (W6BEG1)
+	);
+
+// switch matrix multiplexer  D0 		MUX-4
+	assign D0_input = {J_l_AB_END0,J2END_AB_END0,J2MID_ABb_END0,J2MID_ABa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_D0 (
+	.A0 (D0_input[0]),
+	.A1 (D0_input[1]),
+	.A2 (D0_input[2]),
+	.A3 (D0_input[3]),
+	.S0 (ConfigBits[112+0]),
+	.S0N (ConfigBits_N[112+0]),
+	.S1 (ConfigBits[112+1]),
+	.S1N (ConfigBits_N[112+1]),
+	.X (D0)
+	);
+
+// switch matrix multiplexer  D1 		MUX-4
+	assign D1_input = {J_l_AB_END1,J2END_AB_END1,J2MID_ABb_END1,J2MID_ABa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_D1 (
+	.A0 (D1_input[0]),
+	.A1 (D1_input[1]),
+	.A2 (D1_input[2]),
+	.A3 (D1_input[3]),
+	.S0 (ConfigBits[114+0]),
+	.S0N (ConfigBits_N[114+0]),
+	.S1 (ConfigBits[114+1]),
+	.S1N (ConfigBits_N[114+1]),
+	.X (D1)
+	);
+
+// switch matrix multiplexer  D2 		MUX-4
+	assign D2_input = {J_l_AB_END2,J2END_AB_END2,J2MID_ABb_END2,J2MID_ABa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_D2 (
+	.A0 (D2_input[0]),
+	.A1 (D2_input[1]),
+	.A2 (D2_input[2]),
+	.A3 (D2_input[3]),
+	.S0 (ConfigBits[116+0]),
+	.S0N (ConfigBits_N[116+0]),
+	.S1 (ConfigBits[116+1]),
+	.S1N (ConfigBits_N[116+1]),
+	.X (D2)
+	);
+
+// switch matrix multiplexer  D3 		MUX-4
+	assign D3_input = {J_l_AB_END3,J2END_AB_END3,J2MID_ABb_END3,J2MID_ABa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_D3 (
+	.A0 (D3_input[0]),
+	.A1 (D3_input[1]),
+	.A2 (D3_input[2]),
+	.A3 (D3_input[3]),
+	.S0 (ConfigBits[118+0]),
+	.S0N (ConfigBits_N[118+0]),
+	.S1 (ConfigBits[118+1]),
+	.S1N (ConfigBits_N[118+1]),
+	.X (D3)
+	);
+
+// switch matrix multiplexer  W_ADR0 		MUX-4
+	assign W_ADR0_input = {J_l_CD_END0,J2END_CD_END0,J2MID_CDb_END0,J2MID_CDa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_W_ADR0 (
+	.A0 (W_ADR0_input[0]),
+	.A1 (W_ADR0_input[1]),
+	.A2 (W_ADR0_input[2]),
+	.A3 (W_ADR0_input[3]),
+	.S0 (ConfigBits[120+0]),
+	.S0N (ConfigBits_N[120+0]),
+	.S1 (ConfigBits[120+1]),
+	.S1N (ConfigBits_N[120+1]),
+	.X (W_ADR0)
+	);
+
+// switch matrix multiplexer  W_ADR1 		MUX-4
+	assign W_ADR1_input = {J_l_CD_END1,J2END_CD_END1,J2MID_CDb_END1,J2MID_CDa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_W_ADR1 (
+	.A0 (W_ADR1_input[0]),
+	.A1 (W_ADR1_input[1]),
+	.A2 (W_ADR1_input[2]),
+	.A3 (W_ADR1_input[3]),
+	.S0 (ConfigBits[122+0]),
+	.S0N (ConfigBits_N[122+0]),
+	.S1 (ConfigBits[122+1]),
+	.S1N (ConfigBits_N[122+1]),
+	.X (W_ADR1)
+	);
+
+// switch matrix multiplexer  W_ADR2 		MUX-4
+	assign W_ADR2_input = {J_l_CD_END2,J2END_CD_END2,J2MID_CDb_END2,J2MID_CDa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_W_ADR2 (
+	.A0 (W_ADR2_input[0]),
+	.A1 (W_ADR2_input[1]),
+	.A2 (W_ADR2_input[2]),
+	.A3 (W_ADR2_input[3]),
+	.S0 (ConfigBits[124+0]),
+	.S0N (ConfigBits_N[124+0]),
+	.S1 (ConfigBits[124+1]),
+	.S1N (ConfigBits_N[124+1]),
+	.X (W_ADR2)
+	);
+
+// switch matrix multiplexer  W_ADR3 		MUX-4
+	assign W_ADR3_input = {J_l_CD_END3,J2END_CD_END3,J2MID_CDb_END3,J2MID_CDa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_W_ADR3 (
+	.A0 (W_ADR3_input[0]),
+	.A1 (W_ADR3_input[1]),
+	.A2 (W_ADR3_input[2]),
+	.A3 (W_ADR3_input[3]),
+	.S0 (ConfigBits[126+0]),
+	.S0N (ConfigBits_N[126+0]),
+	.S1 (ConfigBits[126+1]),
+	.S1N (ConfigBits_N[126+1]),
+	.X (W_ADR3)
+	);
+
+// switch matrix multiplexer  W_ADR4 		MUX-8
+	assign W_ADR4_input = {JW2END7,JS2END7,JN2END7,J2END_AB_END3,J2MID_EFb_END2,J2MID_EFa_END1,S2END0,N2END0};
+	cus_mux81_buf inst_cus_mux81_buf_W_ADR4 (
+	.A0 (W_ADR4_input[0]),
+	.A1 (W_ADR4_input[1]),
+	.A2 (W_ADR4_input[2]),
+	.A3 (W_ADR4_input[3]),
+	.A4 (W_ADR4_input[4]),
+	.A5 (W_ADR4_input[5]),
+	.A6 (W_ADR4_input[6]),
+	.A7 (W_ADR4_input[7]),
+	.S0 (ConfigBits[128+0]),
+	.S0N (ConfigBits_N[128+0]),
+	.S1 (ConfigBits[128+1]),
+	.S1N (ConfigBits_N[128+1]),
+	.S2 (ConfigBits[128+2]),
+	.S2N (ConfigBits_N[128+2]),
+	.X (W_ADR4)
+	);
+
+// switch matrix multiplexer  W_en 		MUX-8
+	assign W_en_input = {JW2END0,JS2END0,JN2END0,J2END_GH_END3,J2MID_CDb_END2,J2MID_CDa_END1,S2END3,N2END3};
+	cus_mux81_buf inst_cus_mux81_buf_W_en (
+	.A0 (W_en_input[0]),
+	.A1 (W_en_input[1]),
+	.A2 (W_en_input[2]),
+	.A3 (W_en_input[3]),
+	.A4 (W_en_input[4]),
+	.A5 (W_en_input[5]),
+	.A6 (W_en_input[6]),
+	.A7 (W_en_input[7]),
+	.S0 (ConfigBits[131+0]),
+	.S0N (ConfigBits_N[131+0]),
+	.S1 (ConfigBits[131+1]),
+	.S1N (ConfigBits_N[131+1]),
+	.S2 (ConfigBits[131+2]),
+	.S2N (ConfigBits_N[131+2]),
+	.X (W_en)
+	);
+
+// switch matrix multiplexer  A_ADR0 		MUX-4
+	assign A_ADR0_input = {J_l_EF_END0,J2END_EF_END0,J2MID_EFb_END0,J2MID_EFa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_A_ADR0 (
+	.A0 (A_ADR0_input[0]),
+	.A1 (A_ADR0_input[1]),
+	.A2 (A_ADR0_input[2]),
+	.A3 (A_ADR0_input[3]),
+	.S0 (ConfigBits[134+0]),
+	.S0N (ConfigBits_N[134+0]),
+	.S1 (ConfigBits[134+1]),
+	.S1N (ConfigBits_N[134+1]),
+	.X (A_ADR0)
+	);
+
+// switch matrix multiplexer  A_ADR1 		MUX-4
+	assign A_ADR1_input = {J_l_EF_END1,J2END_EF_END1,J2MID_EFb_END1,J2MID_EFa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_A_ADR1 (
+	.A0 (A_ADR1_input[0]),
+	.A1 (A_ADR1_input[1]),
+	.A2 (A_ADR1_input[2]),
+	.A3 (A_ADR1_input[3]),
+	.S0 (ConfigBits[136+0]),
+	.S0N (ConfigBits_N[136+0]),
+	.S1 (ConfigBits[136+1]),
+	.S1N (ConfigBits_N[136+1]),
+	.X (A_ADR1)
+	);
+
+// switch matrix multiplexer  A_ADR2 		MUX-4
+	assign A_ADR2_input = {J_l_EF_END2,J2END_EF_END2,J2MID_EFb_END2,J2MID_EFa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_A_ADR2 (
+	.A0 (A_ADR2_input[0]),
+	.A1 (A_ADR2_input[1]),
+	.A2 (A_ADR2_input[2]),
+	.A3 (A_ADR2_input[3]),
+	.S0 (ConfigBits[138+0]),
+	.S0N (ConfigBits_N[138+0]),
+	.S1 (ConfigBits[138+1]),
+	.S1N (ConfigBits_N[138+1]),
+	.X (A_ADR2)
+	);
+
+// switch matrix multiplexer  A_ADR3 		MUX-4
+	assign A_ADR3_input = {J_l_EF_END3,J2END_EF_END3,J2MID_EFb_END3,J2MID_EFa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_A_ADR3 (
+	.A0 (A_ADR3_input[0]),
+	.A1 (A_ADR3_input[1]),
+	.A2 (A_ADR3_input[2]),
+	.A3 (A_ADR3_input[3]),
+	.S0 (ConfigBits[140+0]),
+	.S0N (ConfigBits_N[140+0]),
+	.S1 (ConfigBits[140+1]),
+	.S1N (ConfigBits_N[140+1]),
+	.X (A_ADR3)
+	);
+
+// switch matrix multiplexer  A_ADR4 		MUX-8
+	assign A_ADR4_input = {JW2END5,JS2END5,JN2END5,J2END_CD_END3,J2MID_GHb_END2,J2MID_GHa_END1,S2END1,N2END1};
+	cus_mux81_buf inst_cus_mux81_buf_A_ADR4 (
+	.A0 (A_ADR4_input[0]),
+	.A1 (A_ADR4_input[1]),
+	.A2 (A_ADR4_input[2]),
+	.A3 (A_ADR4_input[3]),
+	.A4 (A_ADR4_input[4]),
+	.A5 (A_ADR4_input[5]),
+	.A6 (A_ADR4_input[6]),
+	.A7 (A_ADR4_input[7]),
+	.S0 (ConfigBits[142+0]),
+	.S0N (ConfigBits_N[142+0]),
+	.S1 (ConfigBits[142+1]),
+	.S1N (ConfigBits_N[142+1]),
+	.S2 (ConfigBits[142+2]),
+	.S2N (ConfigBits_N[142+2]),
+	.X (A_ADR4)
+	);
+
+// switch matrix multiplexer  B_ADR0 		MUX-4
+	assign B_ADR0_input = {J_l_GH_END0,J2END_GH_END0,J2MID_GHb_END0,J2MID_GHa_END0};
+	cus_mux41_buf inst_cus_mux41_buf_B_ADR0 (
+	.A0 (B_ADR0_input[0]),
+	.A1 (B_ADR0_input[1]),
+	.A2 (B_ADR0_input[2]),
+	.A3 (B_ADR0_input[3]),
+	.S0 (ConfigBits[145+0]),
+	.S0N (ConfigBits_N[145+0]),
+	.S1 (ConfigBits[145+1]),
+	.S1N (ConfigBits_N[145+1]),
+	.X (B_ADR0)
+	);
+
+// switch matrix multiplexer  B_ADR1 		MUX-4
+	assign B_ADR1_input = {J_l_GH_END1,J2END_GH_END1,J2MID_GHb_END1,J2MID_GHa_END1};
+	cus_mux41_buf inst_cus_mux41_buf_B_ADR1 (
+	.A0 (B_ADR1_input[0]),
+	.A1 (B_ADR1_input[1]),
+	.A2 (B_ADR1_input[2]),
+	.A3 (B_ADR1_input[3]),
+	.S0 (ConfigBits[147+0]),
+	.S0N (ConfigBits_N[147+0]),
+	.S1 (ConfigBits[147+1]),
+	.S1N (ConfigBits_N[147+1]),
+	.X (B_ADR1)
+	);
+
+// switch matrix multiplexer  B_ADR2 		MUX-4
+	assign B_ADR2_input = {J_l_GH_END2,J2END_GH_END2,J2MID_GHb_END2,J2MID_GHa_END2};
+	cus_mux41_buf inst_cus_mux41_buf_B_ADR2 (
+	.A0 (B_ADR2_input[0]),
+	.A1 (B_ADR2_input[1]),
+	.A2 (B_ADR2_input[2]),
+	.A3 (B_ADR2_input[3]),
+	.S0 (ConfigBits[149+0]),
+	.S0N (ConfigBits_N[149+0]),
+	.S1 (ConfigBits[149+1]),
+	.S1N (ConfigBits_N[149+1]),
+	.X (B_ADR2)
+	);
+
+// switch matrix multiplexer  B_ADR3 		MUX-4
+	assign B_ADR3_input = {J_l_GH_END3,J2END_GH_END3,J2MID_GHb_END3,J2MID_GHa_END3};
+	cus_mux41_buf inst_cus_mux41_buf_B_ADR3 (
+	.A0 (B_ADR3_input[0]),
+	.A1 (B_ADR3_input[1]),
+	.A2 (B_ADR3_input[2]),
+	.A3 (B_ADR3_input[3]),
+	.S0 (ConfigBits[151+0]),
+	.S0N (ConfigBits_N[151+0]),
+	.S1 (ConfigBits[151+1]),
+	.S1N (ConfigBits_N[151+1]),
+	.X (B_ADR3)
+	);
+
+// switch matrix multiplexer  B_ADR4 		MUX-8
+	assign B_ADR4_input = {JW2END6,JS2END6,JN2END6,J2END_EF_END3,J2MID_ABb_END2,J2MID_ABa_END1,S2END2,N2END2};
+	cus_mux81_buf inst_cus_mux81_buf_B_ADR4 (
+	.A0 (B_ADR4_input[0]),
+	.A1 (B_ADR4_input[1]),
+	.A2 (B_ADR4_input[2]),
+	.A3 (B_ADR4_input[3]),
+	.A4 (B_ADR4_input[4]),
+	.A5 (B_ADR4_input[5]),
+	.A6 (B_ADR4_input[6]),
+	.A7 (B_ADR4_input[7]),
+	.S0 (ConfigBits[153+0]),
+	.S0N (ConfigBits_N[153+0]),
+	.S1 (ConfigBits[153+1]),
+	.S1N (ConfigBits_N[153+1]),
+	.S2 (ConfigBits[153+2]),
+	.S2N (ConfigBits_N[153+2]),
+	.X (B_ADR4)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG0 		MUX-4
+	assign J2MID_ABa_BEG0_input = {JN2END3,W2MID6,S2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG0 (
+	.A0 (J2MID_ABa_BEG0_input[0]),
+	.A1 (J2MID_ABa_BEG0_input[1]),
+	.A2 (J2MID_ABa_BEG0_input[2]),
+	.A3 (J2MID_ABa_BEG0_input[3]),
+	.S0 (ConfigBits[156+0]),
+	.S0N (ConfigBits_N[156+0]),
+	.S1 (ConfigBits[156+1]),
+	.S1N (ConfigBits_N[156+1]),
+	.X (J2MID_ABa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG1 		MUX-4
+	assign J2MID_ABa_BEG1_input = {JE2END3,W2MID2,S2MID2,E2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG1 (
+	.A0 (J2MID_ABa_BEG1_input[0]),
+	.A1 (J2MID_ABa_BEG1_input[1]),
+	.A2 (J2MID_ABa_BEG1_input[2]),
+	.A3 (J2MID_ABa_BEG1_input[3]),
+	.S0 (ConfigBits[158+0]),
+	.S0N (ConfigBits_N[158+0]),
+	.S1 (ConfigBits[158+1]),
+	.S1N (ConfigBits_N[158+1]),
+	.X (J2MID_ABa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG2 		MUX-4
+	assign J2MID_ABa_BEG2_input = {JS2END3,W2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG2 (
+	.A0 (J2MID_ABa_BEG2_input[0]),
+	.A1 (J2MID_ABa_BEG2_input[1]),
+	.A2 (J2MID_ABa_BEG2_input[2]),
+	.A3 (J2MID_ABa_BEG2_input[3]),
+	.S0 (ConfigBits[160+0]),
+	.S0N (ConfigBits_N[160+0]),
+	.S1 (ConfigBits[160+1]),
+	.S1N (ConfigBits_N[160+1]),
+	.X (J2MID_ABa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABa_BEG3 		MUX-4
+	assign J2MID_ABa_BEG3_input = {JW2END3,S2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABa_BEG3 (
+	.A0 (J2MID_ABa_BEG3_input[0]),
+	.A1 (J2MID_ABa_BEG3_input[1]),
+	.A2 (J2MID_ABa_BEG3_input[2]),
+	.A3 (J2MID_ABa_BEG3_input[3]),
+	.S0 (ConfigBits[162+0]),
+	.S0N (ConfigBits_N[162+0]),
+	.S1 (ConfigBits[162+1]),
+	.S1N (ConfigBits_N[162+1]),
+	.X (J2MID_ABa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG0 		MUX-4
+	assign J2MID_CDa_BEG0_input = {JN2END4,W2MID6,S2MID6,E2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG0 (
+	.A0 (J2MID_CDa_BEG0_input[0]),
+	.A1 (J2MID_CDa_BEG0_input[1]),
+	.A2 (J2MID_CDa_BEG0_input[2]),
+	.A3 (J2MID_CDa_BEG0_input[3]),
+	.S0 (ConfigBits[164+0]),
+	.S0N (ConfigBits_N[164+0]),
+	.S1 (ConfigBits[164+1]),
+	.S1N (ConfigBits_N[164+1]),
+	.X (J2MID_CDa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG1 		MUX-4
+	assign J2MID_CDa_BEG1_input = {JE2END4,W2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG1 (
+	.A0 (J2MID_CDa_BEG1_input[0]),
+	.A1 (J2MID_CDa_BEG1_input[1]),
+	.A2 (J2MID_CDa_BEG1_input[2]),
+	.A3 (J2MID_CDa_BEG1_input[3]),
+	.S0 (ConfigBits[166+0]),
+	.S0N (ConfigBits_N[166+0]),
+	.S1 (ConfigBits[166+1]),
+	.S1N (ConfigBits_N[166+1]),
+	.X (J2MID_CDa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG2 		MUX-4
+	assign J2MID_CDa_BEG2_input = {JS2END4,S2MID4,E2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG2 (
+	.A0 (J2MID_CDa_BEG2_input[0]),
+	.A1 (J2MID_CDa_BEG2_input[1]),
+	.A2 (J2MID_CDa_BEG2_input[2]),
+	.A3 (J2MID_CDa_BEG2_input[3]),
+	.S0 (ConfigBits[168+0]),
+	.S0N (ConfigBits_N[168+0]),
+	.S1 (ConfigBits[168+1]),
+	.S1N (ConfigBits_N[168+1]),
+	.X (J2MID_CDa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDa_BEG3 		MUX-4
+	assign J2MID_CDa_BEG3_input = {JW2END4,W2MID0,S2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDa_BEG3 (
+	.A0 (J2MID_CDa_BEG3_input[0]),
+	.A1 (J2MID_CDa_BEG3_input[1]),
+	.A2 (J2MID_CDa_BEG3_input[2]),
+	.A3 (J2MID_CDa_BEG3_input[3]),
+	.S0 (ConfigBits[170+0]),
+	.S0N (ConfigBits_N[170+0]),
+	.S1 (ConfigBits[170+1]),
+	.S1N (ConfigBits_N[170+1]),
+	.X (J2MID_CDa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG0 		MUX-4
+	assign J2MID_EFa_BEG0_input = {JN2END5,W2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG0 (
+	.A0 (J2MID_EFa_BEG0_input[0]),
+	.A1 (J2MID_EFa_BEG0_input[1]),
+	.A2 (J2MID_EFa_BEG0_input[2]),
+	.A3 (J2MID_EFa_BEG0_input[3]),
+	.S0 (ConfigBits[172+0]),
+	.S0N (ConfigBits_N[172+0]),
+	.S1 (ConfigBits[172+1]),
+	.S1N (ConfigBits_N[172+1]),
+	.X (J2MID_EFa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG1 		MUX-4
+	assign J2MID_EFa_BEG1_input = {JE2END5,S2MID2,E2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG1 (
+	.A0 (J2MID_EFa_BEG1_input[0]),
+	.A1 (J2MID_EFa_BEG1_input[1]),
+	.A2 (J2MID_EFa_BEG1_input[2]),
+	.A3 (J2MID_EFa_BEG1_input[3]),
+	.S0 (ConfigBits[174+0]),
+	.S0N (ConfigBits_N[174+0]),
+	.S1 (ConfigBits[174+1]),
+	.S1N (ConfigBits_N[174+1]),
+	.X (J2MID_EFa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG2 		MUX-4
+	assign J2MID_EFa_BEG2_input = {JS2END5,W2MID4,S2MID4,N2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG2 (
+	.A0 (J2MID_EFa_BEG2_input[0]),
+	.A1 (J2MID_EFa_BEG2_input[1]),
+	.A2 (J2MID_EFa_BEG2_input[2]),
+	.A3 (J2MID_EFa_BEG2_input[3]),
+	.S0 (ConfigBits[176+0]),
+	.S0N (ConfigBits_N[176+0]),
+	.S1 (ConfigBits[176+1]),
+	.S1N (ConfigBits_N[176+1]),
+	.X (J2MID_EFa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFa_BEG3 		MUX-4
+	assign J2MID_EFa_BEG3_input = {JW2END5,W2MID0,S2MID0,E2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFa_BEG3 (
+	.A0 (J2MID_EFa_BEG3_input[0]),
+	.A1 (J2MID_EFa_BEG3_input[1]),
+	.A2 (J2MID_EFa_BEG3_input[2]),
+	.A3 (J2MID_EFa_BEG3_input[3]),
+	.S0 (ConfigBits[178+0]),
+	.S0N (ConfigBits_N[178+0]),
+	.S1 (ConfigBits[178+1]),
+	.S1N (ConfigBits_N[178+1]),
+	.X (J2MID_EFa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG0 		MUX-4
+	assign J2MID_GHa_BEG0_input = {JN2END6,S2MID6,E2MID6,N2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG0 (
+	.A0 (J2MID_GHa_BEG0_input[0]),
+	.A1 (J2MID_GHa_BEG0_input[1]),
+	.A2 (J2MID_GHa_BEG0_input[2]),
+	.A3 (J2MID_GHa_BEG0_input[3]),
+	.S0 (ConfigBits[180+0]),
+	.S0N (ConfigBits_N[180+0]),
+	.S1 (ConfigBits[180+1]),
+	.S1N (ConfigBits_N[180+1]),
+	.X (J2MID_GHa_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG1 		MUX-4
+	assign J2MID_GHa_BEG1_input = {JE2END6,W2MID2,S2MID2,N2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG1 (
+	.A0 (J2MID_GHa_BEG1_input[0]),
+	.A1 (J2MID_GHa_BEG1_input[1]),
+	.A2 (J2MID_GHa_BEG1_input[2]),
+	.A3 (J2MID_GHa_BEG1_input[3]),
+	.S0 (ConfigBits[182+0]),
+	.S0N (ConfigBits_N[182+0]),
+	.S1 (ConfigBits[182+1]),
+	.S1N (ConfigBits_N[182+1]),
+	.X (J2MID_GHa_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG2 		MUX-4
+	assign J2MID_GHa_BEG2_input = {JS2END6,W2MID4,S2MID4,E2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG2 (
+	.A0 (J2MID_GHa_BEG2_input[0]),
+	.A1 (J2MID_GHa_BEG2_input[1]),
+	.A2 (J2MID_GHa_BEG2_input[2]),
+	.A3 (J2MID_GHa_BEG2_input[3]),
+	.S0 (ConfigBits[184+0]),
+	.S0N (ConfigBits_N[184+0]),
+	.S1 (ConfigBits[184+1]),
+	.S1N (ConfigBits_N[184+1]),
+	.X (J2MID_GHa_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHa_BEG3 		MUX-4
+	assign J2MID_GHa_BEG3_input = {JW2END6,W2MID0,E2MID0,N2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHa_BEG3 (
+	.A0 (J2MID_GHa_BEG3_input[0]),
+	.A1 (J2MID_GHa_BEG3_input[1]),
+	.A2 (J2MID_GHa_BEG3_input[2]),
+	.A3 (J2MID_GHa_BEG3_input[3]),
+	.S0 (ConfigBits[186+0]),
+	.S0N (ConfigBits_N[186+0]),
+	.S1 (ConfigBits[186+1]),
+	.S1N (ConfigBits_N[186+1]),
+	.X (J2MID_GHa_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG0 		MUX-4
+	assign J2MID_ABb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG0 (
+	.A0 (J2MID_ABb_BEG0_input[0]),
+	.A1 (J2MID_ABb_BEG0_input[1]),
+	.A2 (J2MID_ABb_BEG0_input[2]),
+	.A3 (J2MID_ABb_BEG0_input[3]),
+	.S0 (ConfigBits[188+0]),
+	.S0N (ConfigBits_N[188+0]),
+	.S1 (ConfigBits[188+1]),
+	.S1N (ConfigBits_N[188+1]),
+	.X (J2MID_ABb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG1 		MUX-4
+	assign J2MID_ABb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG1 (
+	.A0 (J2MID_ABb_BEG1_input[0]),
+	.A1 (J2MID_ABb_BEG1_input[1]),
+	.A2 (J2MID_ABb_BEG1_input[2]),
+	.A3 (J2MID_ABb_BEG1_input[3]),
+	.S0 (ConfigBits[190+0]),
+	.S0N (ConfigBits_N[190+0]),
+	.S1 (ConfigBits[190+1]),
+	.S1N (ConfigBits_N[190+1]),
+	.X (J2MID_ABb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG2 		MUX-4
+	assign J2MID_ABb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG2 (
+	.A0 (J2MID_ABb_BEG2_input[0]),
+	.A1 (J2MID_ABb_BEG2_input[1]),
+	.A2 (J2MID_ABb_BEG2_input[2]),
+	.A3 (J2MID_ABb_BEG2_input[3]),
+	.S0 (ConfigBits[192+0]),
+	.S0N (ConfigBits_N[192+0]),
+	.S1 (ConfigBits[192+1]),
+	.S1N (ConfigBits_N[192+1]),
+	.X (J2MID_ABb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_ABb_BEG3 		MUX-4
+	assign J2MID_ABb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_ABb_BEG3 (
+	.A0 (J2MID_ABb_BEG3_input[0]),
+	.A1 (J2MID_ABb_BEG3_input[1]),
+	.A2 (J2MID_ABb_BEG3_input[2]),
+	.A3 (J2MID_ABb_BEG3_input[3]),
+	.S0 (ConfigBits[194+0]),
+	.S0N (ConfigBits_N[194+0]),
+	.S1 (ConfigBits[194+1]),
+	.S1N (ConfigBits_N[194+1]),
+	.X (J2MID_ABb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG0 		MUX-4
+	assign J2MID_CDb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG0 (
+	.A0 (J2MID_CDb_BEG0_input[0]),
+	.A1 (J2MID_CDb_BEG0_input[1]),
+	.A2 (J2MID_CDb_BEG0_input[2]),
+	.A3 (J2MID_CDb_BEG0_input[3]),
+	.S0 (ConfigBits[196+0]),
+	.S0N (ConfigBits_N[196+0]),
+	.S1 (ConfigBits[196+1]),
+	.S1N (ConfigBits_N[196+1]),
+	.X (J2MID_CDb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG1 		MUX-4
+	assign J2MID_CDb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG1 (
+	.A0 (J2MID_CDb_BEG1_input[0]),
+	.A1 (J2MID_CDb_BEG1_input[1]),
+	.A2 (J2MID_CDb_BEG1_input[2]),
+	.A3 (J2MID_CDb_BEG1_input[3]),
+	.S0 (ConfigBits[198+0]),
+	.S0N (ConfigBits_N[198+0]),
+	.S1 (ConfigBits[198+1]),
+	.S1N (ConfigBits_N[198+1]),
+	.X (J2MID_CDb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG2 		MUX-4
+	assign J2MID_CDb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG2 (
+	.A0 (J2MID_CDb_BEG2_input[0]),
+	.A1 (J2MID_CDb_BEG2_input[1]),
+	.A2 (J2MID_CDb_BEG2_input[2]),
+	.A3 (J2MID_CDb_BEG2_input[3]),
+	.S0 (ConfigBits[200+0]),
+	.S0N (ConfigBits_N[200+0]),
+	.S1 (ConfigBits[200+1]),
+	.S1N (ConfigBits_N[200+1]),
+	.X (J2MID_CDb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_CDb_BEG3 		MUX-4
+	assign J2MID_CDb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_CDb_BEG3 (
+	.A0 (J2MID_CDb_BEG3_input[0]),
+	.A1 (J2MID_CDb_BEG3_input[1]),
+	.A2 (J2MID_CDb_BEG3_input[2]),
+	.A3 (J2MID_CDb_BEG3_input[3]),
+	.S0 (ConfigBits[202+0]),
+	.S0N (ConfigBits_N[202+0]),
+	.S1 (ConfigBits[202+1]),
+	.S1N (ConfigBits_N[202+1]),
+	.X (J2MID_CDb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG0 		MUX-4
+	assign J2MID_EFb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG0 (
+	.A0 (J2MID_EFb_BEG0_input[0]),
+	.A1 (J2MID_EFb_BEG0_input[1]),
+	.A2 (J2MID_EFb_BEG0_input[2]),
+	.A3 (J2MID_EFb_BEG0_input[3]),
+	.S0 (ConfigBits[204+0]),
+	.S0N (ConfigBits_N[204+0]),
+	.S1 (ConfigBits[204+1]),
+	.S1N (ConfigBits_N[204+1]),
+	.X (J2MID_EFb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG1 		MUX-4
+	assign J2MID_EFb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG1 (
+	.A0 (J2MID_EFb_BEG1_input[0]),
+	.A1 (J2MID_EFb_BEG1_input[1]),
+	.A2 (J2MID_EFb_BEG1_input[2]),
+	.A3 (J2MID_EFb_BEG1_input[3]),
+	.S0 (ConfigBits[206+0]),
+	.S0N (ConfigBits_N[206+0]),
+	.S1 (ConfigBits[206+1]),
+	.S1N (ConfigBits_N[206+1]),
+	.X (J2MID_EFb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG2 		MUX-4
+	assign J2MID_EFb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG2 (
+	.A0 (J2MID_EFb_BEG2_input[0]),
+	.A1 (J2MID_EFb_BEG2_input[1]),
+	.A2 (J2MID_EFb_BEG2_input[2]),
+	.A3 (J2MID_EFb_BEG2_input[3]),
+	.S0 (ConfigBits[208+0]),
+	.S0N (ConfigBits_N[208+0]),
+	.S1 (ConfigBits[208+1]),
+	.S1N (ConfigBits_N[208+1]),
+	.X (J2MID_EFb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_EFb_BEG3 		MUX-4
+	assign J2MID_EFb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_EFb_BEG3 (
+	.A0 (J2MID_EFb_BEG3_input[0]),
+	.A1 (J2MID_EFb_BEG3_input[1]),
+	.A2 (J2MID_EFb_BEG3_input[2]),
+	.A3 (J2MID_EFb_BEG3_input[3]),
+	.S0 (ConfigBits[210+0]),
+	.S0N (ConfigBits_N[210+0]),
+	.S1 (ConfigBits[210+1]),
+	.S1N (ConfigBits_N[210+1]),
+	.X (J2MID_EFb_BEG3)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG0 		MUX-4
+	assign J2MID_GHb_BEG0_input = {W2MID7,S2MID7,E2MID7,N2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG0 (
+	.A0 (J2MID_GHb_BEG0_input[0]),
+	.A1 (J2MID_GHb_BEG0_input[1]),
+	.A2 (J2MID_GHb_BEG0_input[2]),
+	.A3 (J2MID_GHb_BEG0_input[3]),
+	.S0 (ConfigBits[212+0]),
+	.S0N (ConfigBits_N[212+0]),
+	.S1 (ConfigBits[212+1]),
+	.S1N (ConfigBits_N[212+1]),
+	.X (J2MID_GHb_BEG0)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG1 		MUX-4
+	assign J2MID_GHb_BEG1_input = {W2MID3,S2MID3,E2MID3,N2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG1 (
+	.A0 (J2MID_GHb_BEG1_input[0]),
+	.A1 (J2MID_GHb_BEG1_input[1]),
+	.A2 (J2MID_GHb_BEG1_input[2]),
+	.A3 (J2MID_GHb_BEG1_input[3]),
+	.S0 (ConfigBits[214+0]),
+	.S0N (ConfigBits_N[214+0]),
+	.S1 (ConfigBits[214+1]),
+	.S1N (ConfigBits_N[214+1]),
+	.X (J2MID_GHb_BEG1)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG2 		MUX-4
+	assign J2MID_GHb_BEG2_input = {W2MID5,S2MID5,E2MID5,N2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG2 (
+	.A0 (J2MID_GHb_BEG2_input[0]),
+	.A1 (J2MID_GHb_BEG2_input[1]),
+	.A2 (J2MID_GHb_BEG2_input[2]),
+	.A3 (J2MID_GHb_BEG2_input[3]),
+	.S0 (ConfigBits[216+0]),
+	.S0N (ConfigBits_N[216+0]),
+	.S1 (ConfigBits[216+1]),
+	.S1N (ConfigBits_N[216+1]),
+	.X (J2MID_GHb_BEG2)
+	);
+
+// switch matrix multiplexer  J2MID_GHb_BEG3 		MUX-4
+	assign J2MID_GHb_BEG3_input = {W2MID1,S2MID1,E2MID1,N2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_J2MID_GHb_BEG3 (
+	.A0 (J2MID_GHb_BEG3_input[0]),
+	.A1 (J2MID_GHb_BEG3_input[1]),
+	.A2 (J2MID_GHb_BEG3_input[2]),
+	.A3 (J2MID_GHb_BEG3_input[3]),
+	.S0 (ConfigBits[218+0]),
+	.S0N (ConfigBits_N[218+0]),
+	.S1 (ConfigBits[218+1]),
+	.S1N (ConfigBits_N[218+1]),
+	.X (J2MID_GHb_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG0 		MUX-4
+	assign J2END_AB_BEG0_input = {W2END6,S2END6,E2END6,N2END6};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG0 (
+	.A0 (J2END_AB_BEG0_input[0]),
+	.A1 (J2END_AB_BEG0_input[1]),
+	.A2 (J2END_AB_BEG0_input[2]),
+	.A3 (J2END_AB_BEG0_input[3]),
+	.S0 (ConfigBits[220+0]),
+	.S0N (ConfigBits_N[220+0]),
+	.S1 (ConfigBits[220+1]),
+	.S1N (ConfigBits_N[220+1]),
+	.X (J2END_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG1 		MUX-4
+	assign J2END_AB_BEG1_input = {W2END2,S2END2,E2END2,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG1 (
+	.A0 (J2END_AB_BEG1_input[0]),
+	.A1 (J2END_AB_BEG1_input[1]),
+	.A2 (J2END_AB_BEG1_input[2]),
+	.A3 (J2END_AB_BEG1_input[3]),
+	.S0 (ConfigBits[222+0]),
+	.S0N (ConfigBits_N[222+0]),
+	.S1 (ConfigBits[222+1]),
+	.S1N (ConfigBits_N[222+1]),
+	.X (J2END_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG2 		MUX-4
+	assign J2END_AB_BEG2_input = {W2END4,S2END4,E2END4,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG2 (
+	.A0 (J2END_AB_BEG2_input[0]),
+	.A1 (J2END_AB_BEG2_input[1]),
+	.A2 (J2END_AB_BEG2_input[2]),
+	.A3 (J2END_AB_BEG2_input[3]),
+	.S0 (ConfigBits[224+0]),
+	.S0N (ConfigBits_N[224+0]),
+	.S1 (ConfigBits[224+1]),
+	.S1N (ConfigBits_N[224+1]),
+	.X (J2END_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_AB_BEG3 		MUX-4
+	assign J2END_AB_BEG3_input = {W2END0,S2END0,E2END0,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_AB_BEG3 (
+	.A0 (J2END_AB_BEG3_input[0]),
+	.A1 (J2END_AB_BEG3_input[1]),
+	.A2 (J2END_AB_BEG3_input[2]),
+	.A3 (J2END_AB_BEG3_input[3]),
+	.S0 (ConfigBits[226+0]),
+	.S0N (ConfigBits_N[226+0]),
+	.S1 (ConfigBits[226+1]),
+	.S1N (ConfigBits_N[226+1]),
+	.X (J2END_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG0 		MUX-4
+	assign J2END_CD_BEG0_input = {W2END6,S2END6,E2END6,N2END6};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG0 (
+	.A0 (J2END_CD_BEG0_input[0]),
+	.A1 (J2END_CD_BEG0_input[1]),
+	.A2 (J2END_CD_BEG0_input[2]),
+	.A3 (J2END_CD_BEG0_input[3]),
+	.S0 (ConfigBits[228+0]),
+	.S0N (ConfigBits_N[228+0]),
+	.S1 (ConfigBits[228+1]),
+	.S1N (ConfigBits_N[228+1]),
+	.X (J2END_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG1 		MUX-4
+	assign J2END_CD_BEG1_input = {W2END2,S2END2,E2END2,N2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG1 (
+	.A0 (J2END_CD_BEG1_input[0]),
+	.A1 (J2END_CD_BEG1_input[1]),
+	.A2 (J2END_CD_BEG1_input[2]),
+	.A3 (J2END_CD_BEG1_input[3]),
+	.S0 (ConfigBits[230+0]),
+	.S0N (ConfigBits_N[230+0]),
+	.S1 (ConfigBits[230+1]),
+	.S1N (ConfigBits_N[230+1]),
+	.X (J2END_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG2 		MUX-4
+	assign J2END_CD_BEG2_input = {W2END4,S2END4,E2END4,N2END4};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG2 (
+	.A0 (J2END_CD_BEG2_input[0]),
+	.A1 (J2END_CD_BEG2_input[1]),
+	.A2 (J2END_CD_BEG2_input[2]),
+	.A3 (J2END_CD_BEG2_input[3]),
+	.S0 (ConfigBits[232+0]),
+	.S0N (ConfigBits_N[232+0]),
+	.S1 (ConfigBits[232+1]),
+	.S1N (ConfigBits_N[232+1]),
+	.X (J2END_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_CD_BEG3 		MUX-4
+	assign J2END_CD_BEG3_input = {W2END0,S2END0,E2END0,N2END0};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_CD_BEG3 (
+	.A0 (J2END_CD_BEG3_input[0]),
+	.A1 (J2END_CD_BEG3_input[1]),
+	.A2 (J2END_CD_BEG3_input[2]),
+	.A3 (J2END_CD_BEG3_input[3]),
+	.S0 (ConfigBits[234+0]),
+	.S0N (ConfigBits_N[234+0]),
+	.S1 (ConfigBits[234+1]),
+	.S1N (ConfigBits_N[234+1]),
+	.X (J2END_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG0 		MUX-4
+	assign J2END_EF_BEG0_input = {W2END7,S2END7,E2END7,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG0 (
+	.A0 (J2END_EF_BEG0_input[0]),
+	.A1 (J2END_EF_BEG0_input[1]),
+	.A2 (J2END_EF_BEG0_input[2]),
+	.A3 (J2END_EF_BEG0_input[3]),
+	.S0 (ConfigBits[236+0]),
+	.S0N (ConfigBits_N[236+0]),
+	.S1 (ConfigBits[236+1]),
+	.S1N (ConfigBits_N[236+1]),
+	.X (J2END_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG1 		MUX-4
+	assign J2END_EF_BEG1_input = {W2END3,S2END3,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG1 (
+	.A0 (J2END_EF_BEG1_input[0]),
+	.A1 (J2END_EF_BEG1_input[1]),
+	.A2 (J2END_EF_BEG1_input[2]),
+	.A3 (J2END_EF_BEG1_input[3]),
+	.S0 (ConfigBits[238+0]),
+	.S0N (ConfigBits_N[238+0]),
+	.S1 (ConfigBits[238+1]),
+	.S1N (ConfigBits_N[238+1]),
+	.X (J2END_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG2 		MUX-4
+	assign J2END_EF_BEG2_input = {W2END5,S2END5,E2END5,N2END5};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG2 (
+	.A0 (J2END_EF_BEG2_input[0]),
+	.A1 (J2END_EF_BEG2_input[1]),
+	.A2 (J2END_EF_BEG2_input[2]),
+	.A3 (J2END_EF_BEG2_input[3]),
+	.S0 (ConfigBits[240+0]),
+	.S0N (ConfigBits_N[240+0]),
+	.S1 (ConfigBits[240+1]),
+	.S1N (ConfigBits_N[240+1]),
+	.X (J2END_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_EF_BEG3 		MUX-4
+	assign J2END_EF_BEG3_input = {W2END1,S2END1,E2END1,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_EF_BEG3 (
+	.A0 (J2END_EF_BEG3_input[0]),
+	.A1 (J2END_EF_BEG3_input[1]),
+	.A2 (J2END_EF_BEG3_input[2]),
+	.A3 (J2END_EF_BEG3_input[3]),
+	.S0 (ConfigBits[242+0]),
+	.S0N (ConfigBits_N[242+0]),
+	.S1 (ConfigBits[242+1]),
+	.S1N (ConfigBits_N[242+1]),
+	.X (J2END_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG0 		MUX-4
+	assign J2END_GH_BEG0_input = {W2END7,S2END7,E2END7,N2END7};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG0 (
+	.A0 (J2END_GH_BEG0_input[0]),
+	.A1 (J2END_GH_BEG0_input[1]),
+	.A2 (J2END_GH_BEG0_input[2]),
+	.A3 (J2END_GH_BEG0_input[3]),
+	.S0 (ConfigBits[244+0]),
+	.S0N (ConfigBits_N[244+0]),
+	.S1 (ConfigBits[244+1]),
+	.S1N (ConfigBits_N[244+1]),
+	.X (J2END_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG1 		MUX-4
+	assign J2END_GH_BEG1_input = {W2END3,S2END3,E2END3,N2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG1 (
+	.A0 (J2END_GH_BEG1_input[0]),
+	.A1 (J2END_GH_BEG1_input[1]),
+	.A2 (J2END_GH_BEG1_input[2]),
+	.A3 (J2END_GH_BEG1_input[3]),
+	.S0 (ConfigBits[246+0]),
+	.S0N (ConfigBits_N[246+0]),
+	.S1 (ConfigBits[246+1]),
+	.S1N (ConfigBits_N[246+1]),
+	.X (J2END_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG2 		MUX-4
+	assign J2END_GH_BEG2_input = {W2END5,S2END5,E2END5,N2END5};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG2 (
+	.A0 (J2END_GH_BEG2_input[0]),
+	.A1 (J2END_GH_BEG2_input[1]),
+	.A2 (J2END_GH_BEG2_input[2]),
+	.A3 (J2END_GH_BEG2_input[3]),
+	.S0 (ConfigBits[248+0]),
+	.S0N (ConfigBits_N[248+0]),
+	.S1 (ConfigBits[248+1]),
+	.S1N (ConfigBits_N[248+1]),
+	.X (J2END_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J2END_GH_BEG3 		MUX-4
+	assign J2END_GH_BEG3_input = {W2END1,S2END1,E2END1,N2END1};
+	cus_mux41_buf inst_cus_mux41_buf_J2END_GH_BEG3 (
+	.A0 (J2END_GH_BEG3_input[0]),
+	.A1 (J2END_GH_BEG3_input[1]),
+	.A2 (J2END_GH_BEG3_input[2]),
+	.A3 (J2END_GH_BEG3_input[3]),
+	.S0 (ConfigBits[250+0]),
+	.S0N (ConfigBits_N[250+0]),
+	.S1 (ConfigBits[250+1]),
+	.S1N (ConfigBits_N[250+1]),
+	.X (J2END_GH_BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG0 		MUX-16
+	assign JN2BEG0_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD1,W6END1,W2END1,S2END1,E6END1,EE4END0,E2END1,E1END3,N4END1,N2END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG0 (
+	.A0 (JN2BEG0_input[0]),
+	.A1 (JN2BEG0_input[1]),
+	.A2 (JN2BEG0_input[2]),
+	.A3 (JN2BEG0_input[3]),
+	.A4 (JN2BEG0_input[4]),
+	.A5 (JN2BEG0_input[5]),
+	.A6 (JN2BEG0_input[6]),
+	.A7 (JN2BEG0_input[7]),
+	.A8 (JN2BEG0_input[8]),
+	.A9 (JN2BEG0_input[9]),
+	.A10 (JN2BEG0_input[10]),
+	.A11 (JN2BEG0_input[11]),
+	.A12 (JN2BEG0_input[12]),
+	.A13 (JN2BEG0_input[13]),
+	.A14 (JN2BEG0_input[14]),
+	.A15 (JN2BEG0_input[15]),
+	.S0 (ConfigBits[252+0]),
+	.S0N (ConfigBits_N[252+0]),
+	.S1 (ConfigBits[252+1]),
+	.S1N (ConfigBits_N[252+1]),
+	.S2 (ConfigBits[252+2]),
+	.S2N (ConfigBits_N[252+2]),
+	.S3 (ConfigBits[252+3]),
+	.S3N (ConfigBits_N[252+3]),
+	.X (JN2BEG0)
+	);
+
+// switch matrix multiplexer  JN2BEG1 		MUX-16
+	assign JN2BEG1_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD0,W6END0,W2END2,S2END2,E6END0,EE4END1,E2END2,E1END0,N4END2,N2END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG1 (
+	.A0 (JN2BEG1_input[0]),
+	.A1 (JN2BEG1_input[1]),
+	.A2 (JN2BEG1_input[2]),
+	.A3 (JN2BEG1_input[3]),
+	.A4 (JN2BEG1_input[4]),
+	.A5 (JN2BEG1_input[5]),
+	.A6 (JN2BEG1_input[6]),
+	.A7 (JN2BEG1_input[7]),
+	.A8 (JN2BEG1_input[8]),
+	.A9 (JN2BEG1_input[9]),
+	.A10 (JN2BEG1_input[10]),
+	.A11 (JN2BEG1_input[11]),
+	.A12 (JN2BEG1_input[12]),
+	.A13 (JN2BEG1_input[13]),
+	.A14 (JN2BEG1_input[14]),
+	.A15 (JN2BEG1_input[15]),
+	.S0 (ConfigBits[256+0]),
+	.S0N (ConfigBits_N[256+0]),
+	.S1 (ConfigBits[256+1]),
+	.S1N (ConfigBits_N[256+1]),
+	.S2 (ConfigBits[256+2]),
+	.S2N (ConfigBits_N[256+2]),
+	.S3 (ConfigBits[256+3]),
+	.S3N (ConfigBits_N[256+3]),
+	.X (JN2BEG1)
+	);
+
+// switch matrix multiplexer  JN2BEG2 		MUX-16
+	assign JN2BEG2_input = {BD3,BD2,BD1,BD0,AD3,AD1,AD0,W6END1,WW4END2,W2END3,S2END3,E6END1,E2END3,E1END1,N4END3,N2END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG2 (
+	.A0 (JN2BEG2_input[0]),
+	.A1 (JN2BEG2_input[1]),
+	.A2 (JN2BEG2_input[2]),
+	.A3 (JN2BEG2_input[3]),
+	.A4 (JN2BEG2_input[4]),
+	.A5 (JN2BEG2_input[5]),
+	.A6 (JN2BEG2_input[6]),
+	.A7 (JN2BEG2_input[7]),
+	.A8 (JN2BEG2_input[8]),
+	.A9 (JN2BEG2_input[9]),
+	.A10 (JN2BEG2_input[10]),
+	.A11 (JN2BEG2_input[11]),
+	.A12 (JN2BEG2_input[12]),
+	.A13 (JN2BEG2_input[13]),
+	.A14 (JN2BEG2_input[14]),
+	.A15 (JN2BEG2_input[15]),
+	.S0 (ConfigBits[260+0]),
+	.S0N (ConfigBits_N[260+0]),
+	.S1 (ConfigBits[260+1]),
+	.S1N (ConfigBits_N[260+1]),
+	.S2 (ConfigBits[260+2]),
+	.S2N (ConfigBits_N[260+2]),
+	.S3 (ConfigBits[260+3]),
+	.S3N (ConfigBits_N[260+3]),
+	.X (JN2BEG2)
+	);
+
+// switch matrix multiplexer  JN2BEG3 		MUX-16
+	assign JN2BEG3_input = {BD3,BD2,BD1,BD0,AD2,AD1,AD0,W6END0,WW4END3,W2END4,S2END4,E6END0,E2END4,E1END2,N4END0,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG3 (
+	.A0 (JN2BEG3_input[0]),
+	.A1 (JN2BEG3_input[1]),
+	.A2 (JN2BEG3_input[2]),
+	.A3 (JN2BEG3_input[3]),
+	.A4 (JN2BEG3_input[4]),
+	.A5 (JN2BEG3_input[5]),
+	.A6 (JN2BEG3_input[6]),
+	.A7 (JN2BEG3_input[7]),
+	.A8 (JN2BEG3_input[8]),
+	.A9 (JN2BEG3_input[9]),
+	.A10 (JN2BEG3_input[10]),
+	.A11 (JN2BEG3_input[11]),
+	.A12 (JN2BEG3_input[12]),
+	.A13 (JN2BEG3_input[13]),
+	.A14 (JN2BEG3_input[14]),
+	.A15 (JN2BEG3_input[15]),
+	.S0 (ConfigBits[264+0]),
+	.S0N (ConfigBits_N[264+0]),
+	.S1 (ConfigBits[264+1]),
+	.S1N (ConfigBits_N[264+1]),
+	.S2 (ConfigBits[264+2]),
+	.S2N (ConfigBits_N[264+2]),
+	.S3 (ConfigBits[264+3]),
+	.S3N (ConfigBits_N[264+3]),
+	.X (JN2BEG3)
+	);
+
+// switch matrix multiplexer  JN2BEG4 		MUX-16
+	assign JN2BEG4_input = {BD3,BD2,BD1,AD3,AD2,AD1,AD0,W1END3,W1END1,S2END5,S1END1,E2END5,E1END1,NN4END3,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG4 (
+	.A0 (JN2BEG4_input[0]),
+	.A1 (JN2BEG4_input[1]),
+	.A2 (JN2BEG4_input[2]),
+	.A3 (JN2BEG4_input[3]),
+	.A4 (JN2BEG4_input[4]),
+	.A5 (JN2BEG4_input[5]),
+	.A6 (JN2BEG4_input[6]),
+	.A7 (JN2BEG4_input[7]),
+	.A8 (JN2BEG4_input[8]),
+	.A9 (JN2BEG4_input[9]),
+	.A10 (JN2BEG4_input[10]),
+	.A11 (JN2BEG4_input[11]),
+	.A12 (JN2BEG4_input[12]),
+	.A13 (JN2BEG4_input[13]),
+	.A14 (JN2BEG4_input[14]),
+	.A15 (JN2BEG4_input[15]),
+	.S0 (ConfigBits[268+0]),
+	.S0N (ConfigBits_N[268+0]),
+	.S1 (ConfigBits[268+1]),
+	.S1N (ConfigBits_N[268+1]),
+	.S2 (ConfigBits[268+2]),
+	.S2N (ConfigBits_N[268+2]),
+	.S3 (ConfigBits[268+3]),
+	.S3N (ConfigBits_N[268+3]),
+	.X (JN2BEG4)
+	);
+
+// switch matrix multiplexer  JN2BEG5 		MUX-16
+	assign JN2BEG5_input = {BD3,BD2,BD0,AD3,AD2,AD1,AD0,W1END2,W1END0,S2END6,S1END2,E2END6,E1END2,NN4END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG5 (
+	.A0 (JN2BEG5_input[0]),
+	.A1 (JN2BEG5_input[1]),
+	.A2 (JN2BEG5_input[2]),
+	.A3 (JN2BEG5_input[3]),
+	.A4 (JN2BEG5_input[4]),
+	.A5 (JN2BEG5_input[5]),
+	.A6 (JN2BEG5_input[6]),
+	.A7 (JN2BEG5_input[7]),
+	.A8 (JN2BEG5_input[8]),
+	.A9 (JN2BEG5_input[9]),
+	.A10 (JN2BEG5_input[10]),
+	.A11 (JN2BEG5_input[11]),
+	.A12 (JN2BEG5_input[12]),
+	.A13 (JN2BEG5_input[13]),
+	.A14 (JN2BEG5_input[14]),
+	.A15 (JN2BEG5_input[15]),
+	.S0 (ConfigBits[272+0]),
+	.S0N (ConfigBits_N[272+0]),
+	.S1 (ConfigBits[272+1]),
+	.S1N (ConfigBits_N[272+1]),
+	.S2 (ConfigBits[272+2]),
+	.S2N (ConfigBits_N[272+2]),
+	.S3 (ConfigBits[272+3]),
+	.S3N (ConfigBits_N[272+3]),
+	.X (JN2BEG5)
+	);
+
+// switch matrix multiplexer  JN2BEG6 		MUX-16
+	assign JN2BEG6_input = {BD3,BD1,BD0,AD3,AD2,AD1,AD0,W1END3,W1END1,S2END7,S1END3,E2END7,E1END3,NN4END1,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG6 (
+	.A0 (JN2BEG6_input[0]),
+	.A1 (JN2BEG6_input[1]),
+	.A2 (JN2BEG6_input[2]),
+	.A3 (JN2BEG6_input[3]),
+	.A4 (JN2BEG6_input[4]),
+	.A5 (JN2BEG6_input[5]),
+	.A6 (JN2BEG6_input[6]),
+	.A7 (JN2BEG6_input[7]),
+	.A8 (JN2BEG6_input[8]),
+	.A9 (JN2BEG6_input[9]),
+	.A10 (JN2BEG6_input[10]),
+	.A11 (JN2BEG6_input[11]),
+	.A12 (JN2BEG6_input[12]),
+	.A13 (JN2BEG6_input[13]),
+	.A14 (JN2BEG6_input[14]),
+	.A15 (JN2BEG6_input[15]),
+	.S0 (ConfigBits[276+0]),
+	.S0N (ConfigBits_N[276+0]),
+	.S1 (ConfigBits[276+1]),
+	.S1N (ConfigBits_N[276+1]),
+	.S2 (ConfigBits[276+2]),
+	.S2N (ConfigBits_N[276+2]),
+	.S3 (ConfigBits[276+3]),
+	.S3N (ConfigBits_N[276+3]),
+	.X (JN2BEG6)
+	);
+
+// switch matrix multiplexer  JN2BEG7 		MUX-16
+	assign JN2BEG7_input = {BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END2,W1END0,S2END0,S1END0,E2END0,E1END0,NN4END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JN2BEG7 (
+	.A0 (JN2BEG7_input[0]),
+	.A1 (JN2BEG7_input[1]),
+	.A2 (JN2BEG7_input[2]),
+	.A3 (JN2BEG7_input[3]),
+	.A4 (JN2BEG7_input[4]),
+	.A5 (JN2BEG7_input[5]),
+	.A6 (JN2BEG7_input[6]),
+	.A7 (JN2BEG7_input[7]),
+	.A8 (JN2BEG7_input[8]),
+	.A9 (JN2BEG7_input[9]),
+	.A10 (JN2BEG7_input[10]),
+	.A11 (JN2BEG7_input[11]),
+	.A12 (JN2BEG7_input[12]),
+	.A13 (JN2BEG7_input[13]),
+	.A14 (JN2BEG7_input[14]),
+	.A15 (JN2BEG7_input[15]),
+	.S0 (ConfigBits[280+0]),
+	.S0N (ConfigBits_N[280+0]),
+	.S1 (ConfigBits[280+1]),
+	.S1N (ConfigBits_N[280+1]),
+	.S2 (ConfigBits[280+2]),
+	.S2N (ConfigBits_N[280+2]),
+	.S3 (ConfigBits[280+3]),
+	.S3N (ConfigBits_N[280+3]),
+	.X (JN2BEG7)
+	);
+
+// switch matrix multiplexer  JE2BEG0 		MUX-16
+	assign JE2BEG0_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD1,W6END1,W2END1,S2END1,E6END1,E2END1,NN4END0,N4END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG0 (
+	.A0 (JE2BEG0_input[0]),
+	.A1 (JE2BEG0_input[1]),
+	.A2 (JE2BEG0_input[2]),
+	.A3 (JE2BEG0_input[3]),
+	.A4 (JE2BEG0_input[4]),
+	.A5 (JE2BEG0_input[5]),
+	.A6 (JE2BEG0_input[6]),
+	.A7 (JE2BEG0_input[7]),
+	.A8 (JE2BEG0_input[8]),
+	.A9 (JE2BEG0_input[9]),
+	.A10 (JE2BEG0_input[10]),
+	.A11 (JE2BEG0_input[11]),
+	.A12 (JE2BEG0_input[12]),
+	.A13 (JE2BEG0_input[13]),
+	.A14 (JE2BEG0_input[14]),
+	.A15 (JE2BEG0_input[15]),
+	.S0 (ConfigBits[284+0]),
+	.S0N (ConfigBits_N[284+0]),
+	.S1 (ConfigBits[284+1]),
+	.S1N (ConfigBits_N[284+1]),
+	.S2 (ConfigBits[284+2]),
+	.S2N (ConfigBits_N[284+2]),
+	.S3 (ConfigBits[284+3]),
+	.S3N (ConfigBits_N[284+3]),
+	.X (JE2BEG0)
+	);
+
+// switch matrix multiplexer  JE2BEG1 		MUX-16
+	assign JE2BEG1_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD0,W6END0,W2END2,S2END2,E6END0,E2END2,NN4END1,N4END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG1 (
+	.A0 (JE2BEG1_input[0]),
+	.A1 (JE2BEG1_input[1]),
+	.A2 (JE2BEG1_input[2]),
+	.A3 (JE2BEG1_input[3]),
+	.A4 (JE2BEG1_input[4]),
+	.A5 (JE2BEG1_input[5]),
+	.A6 (JE2BEG1_input[6]),
+	.A7 (JE2BEG1_input[7]),
+	.A8 (JE2BEG1_input[8]),
+	.A9 (JE2BEG1_input[9]),
+	.A10 (JE2BEG1_input[10]),
+	.A11 (JE2BEG1_input[11]),
+	.A12 (JE2BEG1_input[12]),
+	.A13 (JE2BEG1_input[13]),
+	.A14 (JE2BEG1_input[14]),
+	.A15 (JE2BEG1_input[15]),
+	.S0 (ConfigBits[288+0]),
+	.S0N (ConfigBits_N[288+0]),
+	.S1 (ConfigBits[288+1]),
+	.S1N (ConfigBits_N[288+1]),
+	.S2 (ConfigBits[288+2]),
+	.S2N (ConfigBits_N[288+2]),
+	.S3 (ConfigBits[288+3]),
+	.S3N (ConfigBits_N[288+3]),
+	.X (JE2BEG1)
+	);
+
+// switch matrix multiplexer  JE2BEG2 		MUX-16
+	assign JE2BEG2_input = {BD3,BD2,BD1,BD0,AD3,AD1,AD0,W6END1,W2END3,SS4END2,S2END3,E6END1,E2END3,N4END3,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG2 (
+	.A0 (JE2BEG2_input[0]),
+	.A1 (JE2BEG2_input[1]),
+	.A2 (JE2BEG2_input[2]),
+	.A3 (JE2BEG2_input[3]),
+	.A4 (JE2BEG2_input[4]),
+	.A5 (JE2BEG2_input[5]),
+	.A6 (JE2BEG2_input[6]),
+	.A7 (JE2BEG2_input[7]),
+	.A8 (JE2BEG2_input[8]),
+	.A9 (JE2BEG2_input[9]),
+	.A10 (JE2BEG2_input[10]),
+	.A11 (JE2BEG2_input[11]),
+	.A12 (JE2BEG2_input[12]),
+	.A13 (JE2BEG2_input[13]),
+	.A14 (JE2BEG2_input[14]),
+	.A15 (JE2BEG2_input[15]),
+	.S0 (ConfigBits[292+0]),
+	.S0N (ConfigBits_N[292+0]),
+	.S1 (ConfigBits[292+1]),
+	.S1N (ConfigBits_N[292+1]),
+	.S2 (ConfigBits[292+2]),
+	.S2N (ConfigBits_N[292+2]),
+	.S3 (ConfigBits[292+3]),
+	.S3N (ConfigBits_N[292+3]),
+	.X (JE2BEG2)
+	);
+
+// switch matrix multiplexer  JE2BEG3 		MUX-16
+	assign JE2BEG3_input = {BD3,BD2,BD1,BD0,AD2,AD1,AD0,W6END0,W2END4,SS4END3,S2END4,E6END0,E2END4,N4END0,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG3 (
+	.A0 (JE2BEG3_input[0]),
+	.A1 (JE2BEG3_input[1]),
+	.A2 (JE2BEG3_input[2]),
+	.A3 (JE2BEG3_input[3]),
+	.A4 (JE2BEG3_input[4]),
+	.A5 (JE2BEG3_input[5]),
+	.A6 (JE2BEG3_input[6]),
+	.A7 (JE2BEG3_input[7]),
+	.A8 (JE2BEG3_input[8]),
+	.A9 (JE2BEG3_input[9]),
+	.A10 (JE2BEG3_input[10]),
+	.A11 (JE2BEG3_input[11]),
+	.A12 (JE2BEG3_input[12]),
+	.A13 (JE2BEG3_input[13]),
+	.A14 (JE2BEG3_input[14]),
+	.A15 (JE2BEG3_input[15]),
+	.S0 (ConfigBits[296+0]),
+	.S0N (ConfigBits_N[296+0]),
+	.S1 (ConfigBits[296+1]),
+	.S1N (ConfigBits_N[296+1]),
+	.S2 (ConfigBits[296+2]),
+	.S2N (ConfigBits_N[296+2]),
+	.S3 (ConfigBits[296+3]),
+	.S3N (ConfigBits_N[296+3]),
+	.X (JE2BEG3)
+	);
+
+// switch matrix multiplexer  JE2BEG4 		MUX-16
+	assign JE2BEG4_input = {BD3,BD2,BD1,AD3,AD2,AD1,AD0,W1END1,S2END5,S1END3,S1END1,EE4END3,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG4 (
+	.A0 (JE2BEG4_input[0]),
+	.A1 (JE2BEG4_input[1]),
+	.A2 (JE2BEG4_input[2]),
+	.A3 (JE2BEG4_input[3]),
+	.A4 (JE2BEG4_input[4]),
+	.A5 (JE2BEG4_input[5]),
+	.A6 (JE2BEG4_input[6]),
+	.A7 (JE2BEG4_input[7]),
+	.A8 (JE2BEG4_input[8]),
+	.A9 (JE2BEG4_input[9]),
+	.A10 (JE2BEG4_input[10]),
+	.A11 (JE2BEG4_input[11]),
+	.A12 (JE2BEG4_input[12]),
+	.A13 (JE2BEG4_input[13]),
+	.A14 (JE2BEG4_input[14]),
+	.A15 (JE2BEG4_input[15]),
+	.S0 (ConfigBits[300+0]),
+	.S0N (ConfigBits_N[300+0]),
+	.S1 (ConfigBits[300+1]),
+	.S1N (ConfigBits_N[300+1]),
+	.S2 (ConfigBits[300+2]),
+	.S2N (ConfigBits_N[300+2]),
+	.S3 (ConfigBits[300+3]),
+	.S3N (ConfigBits_N[300+3]),
+	.X (JE2BEG4)
+	);
+
+// switch matrix multiplexer  JE2BEG5 		MUX-16
+	assign JE2BEG5_input = {BD3,BD2,BD0,AD3,AD2,AD1,AD0,W1END2,S2END6,S1END2,S1END0,EE4END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG5 (
+	.A0 (JE2BEG5_input[0]),
+	.A1 (JE2BEG5_input[1]),
+	.A2 (JE2BEG5_input[2]),
+	.A3 (JE2BEG5_input[3]),
+	.A4 (JE2BEG5_input[4]),
+	.A5 (JE2BEG5_input[5]),
+	.A6 (JE2BEG5_input[6]),
+	.A7 (JE2BEG5_input[7]),
+	.A8 (JE2BEG5_input[8]),
+	.A9 (JE2BEG5_input[9]),
+	.A10 (JE2BEG5_input[10]),
+	.A11 (JE2BEG5_input[11]),
+	.A12 (JE2BEG5_input[12]),
+	.A13 (JE2BEG5_input[13]),
+	.A14 (JE2BEG5_input[14]),
+	.A15 (JE2BEG5_input[15]),
+	.S0 (ConfigBits[304+0]),
+	.S0N (ConfigBits_N[304+0]),
+	.S1 (ConfigBits[304+1]),
+	.S1N (ConfigBits_N[304+1]),
+	.S2 (ConfigBits[304+2]),
+	.S2N (ConfigBits_N[304+2]),
+	.S3 (ConfigBits[304+3]),
+	.S3N (ConfigBits_N[304+3]),
+	.X (JE2BEG5)
+	);
+
+// switch matrix multiplexer  JE2BEG6 		MUX-16
+	assign JE2BEG6_input = {BD3,BD1,BD0,AD3,AD2,AD1,AD0,W1END3,S2END7,S1END3,S1END1,EE4END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG6 (
+	.A0 (JE2BEG6_input[0]),
+	.A1 (JE2BEG6_input[1]),
+	.A2 (JE2BEG6_input[2]),
+	.A3 (JE2BEG6_input[3]),
+	.A4 (JE2BEG6_input[4]),
+	.A5 (JE2BEG6_input[5]),
+	.A6 (JE2BEG6_input[6]),
+	.A7 (JE2BEG6_input[7]),
+	.A8 (JE2BEG6_input[8]),
+	.A9 (JE2BEG6_input[9]),
+	.A10 (JE2BEG6_input[10]),
+	.A11 (JE2BEG6_input[11]),
+	.A12 (JE2BEG6_input[12]),
+	.A13 (JE2BEG6_input[13]),
+	.A14 (JE2BEG6_input[14]),
+	.A15 (JE2BEG6_input[15]),
+	.S0 (ConfigBits[308+0]),
+	.S0N (ConfigBits_N[308+0]),
+	.S1 (ConfigBits[308+1]),
+	.S1N (ConfigBits_N[308+1]),
+	.S2 (ConfigBits[308+2]),
+	.S2N (ConfigBits_N[308+2]),
+	.S3 (ConfigBits[308+3]),
+	.S3N (ConfigBits_N[308+3]),
+	.X (JE2BEG6)
+	);
+
+// switch matrix multiplexer  JE2BEG7 		MUX-16
+	assign JE2BEG7_input = {BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END0,S2END0,S1END2,S1END0,EE4END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JE2BEG7 (
+	.A0 (JE2BEG7_input[0]),
+	.A1 (JE2BEG7_input[1]),
+	.A2 (JE2BEG7_input[2]),
+	.A3 (JE2BEG7_input[3]),
+	.A4 (JE2BEG7_input[4]),
+	.A5 (JE2BEG7_input[5]),
+	.A6 (JE2BEG7_input[6]),
+	.A7 (JE2BEG7_input[7]),
+	.A8 (JE2BEG7_input[8]),
+	.A9 (JE2BEG7_input[9]),
+	.A10 (JE2BEG7_input[10]),
+	.A11 (JE2BEG7_input[11]),
+	.A12 (JE2BEG7_input[12]),
+	.A13 (JE2BEG7_input[13]),
+	.A14 (JE2BEG7_input[14]),
+	.A15 (JE2BEG7_input[15]),
+	.S0 (ConfigBits[312+0]),
+	.S0N (ConfigBits_N[312+0]),
+	.S1 (ConfigBits[312+1]),
+	.S1N (ConfigBits_N[312+1]),
+	.S2 (ConfigBits[312+2]),
+	.S2N (ConfigBits_N[312+2]),
+	.S3 (ConfigBits[312+3]),
+	.S3N (ConfigBits_N[312+3]),
+	.X (JE2BEG7)
+	);
+
+// switch matrix multiplexer  JS2BEG0 		MUX-16
+	assign JS2BEG0_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD1,W6END1,WW4END0,W2END1,S4END1,S2END1,E6END1,E2END1,E1END3,N2END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG0 (
+	.A0 (JS2BEG0_input[0]),
+	.A1 (JS2BEG0_input[1]),
+	.A2 (JS2BEG0_input[2]),
+	.A3 (JS2BEG0_input[3]),
+	.A4 (JS2BEG0_input[4]),
+	.A5 (JS2BEG0_input[5]),
+	.A6 (JS2BEG0_input[6]),
+	.A7 (JS2BEG0_input[7]),
+	.A8 (JS2BEG0_input[8]),
+	.A9 (JS2BEG0_input[9]),
+	.A10 (JS2BEG0_input[10]),
+	.A11 (JS2BEG0_input[11]),
+	.A12 (JS2BEG0_input[12]),
+	.A13 (JS2BEG0_input[13]),
+	.A14 (JS2BEG0_input[14]),
+	.A15 (JS2BEG0_input[15]),
+	.S0 (ConfigBits[316+0]),
+	.S0N (ConfigBits_N[316+0]),
+	.S1 (ConfigBits[316+1]),
+	.S1N (ConfigBits_N[316+1]),
+	.S2 (ConfigBits[316+2]),
+	.S2N (ConfigBits_N[316+2]),
+	.S3 (ConfigBits[316+3]),
+	.S3N (ConfigBits_N[316+3]),
+	.X (JS2BEG0)
+	);
+
+// switch matrix multiplexer  JS2BEG1 		MUX-16
+	assign JS2BEG1_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD0,W6END0,WW4END1,W2END2,S4END2,S2END2,E6END0,E2END2,E1END0,N2END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG1 (
+	.A0 (JS2BEG1_input[0]),
+	.A1 (JS2BEG1_input[1]),
+	.A2 (JS2BEG1_input[2]),
+	.A3 (JS2BEG1_input[3]),
+	.A4 (JS2BEG1_input[4]),
+	.A5 (JS2BEG1_input[5]),
+	.A6 (JS2BEG1_input[6]),
+	.A7 (JS2BEG1_input[7]),
+	.A8 (JS2BEG1_input[8]),
+	.A9 (JS2BEG1_input[9]),
+	.A10 (JS2BEG1_input[10]),
+	.A11 (JS2BEG1_input[11]),
+	.A12 (JS2BEG1_input[12]),
+	.A13 (JS2BEG1_input[13]),
+	.A14 (JS2BEG1_input[14]),
+	.A15 (JS2BEG1_input[15]),
+	.S0 (ConfigBits[320+0]),
+	.S0N (ConfigBits_N[320+0]),
+	.S1 (ConfigBits[320+1]),
+	.S1N (ConfigBits_N[320+1]),
+	.S2 (ConfigBits[320+2]),
+	.S2N (ConfigBits_N[320+2]),
+	.S3 (ConfigBits[320+3]),
+	.S3N (ConfigBits_N[320+3]),
+	.X (JS2BEG1)
+	);
+
+// switch matrix multiplexer  JS2BEG2 		MUX-16
+	assign JS2BEG2_input = {BD3,BD2,BD1,BD0,AD3,AD1,AD0,W6END1,W2END3,S4END3,S2END3,E6END1,EE4END2,E2END3,E1END1,N2END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG2 (
+	.A0 (JS2BEG2_input[0]),
+	.A1 (JS2BEG2_input[1]),
+	.A2 (JS2BEG2_input[2]),
+	.A3 (JS2BEG2_input[3]),
+	.A4 (JS2BEG2_input[4]),
+	.A5 (JS2BEG2_input[5]),
+	.A6 (JS2BEG2_input[6]),
+	.A7 (JS2BEG2_input[7]),
+	.A8 (JS2BEG2_input[8]),
+	.A9 (JS2BEG2_input[9]),
+	.A10 (JS2BEG2_input[10]),
+	.A11 (JS2BEG2_input[11]),
+	.A12 (JS2BEG2_input[12]),
+	.A13 (JS2BEG2_input[13]),
+	.A14 (JS2BEG2_input[14]),
+	.A15 (JS2BEG2_input[15]),
+	.S0 (ConfigBits[324+0]),
+	.S0N (ConfigBits_N[324+0]),
+	.S1 (ConfigBits[324+1]),
+	.S1N (ConfigBits_N[324+1]),
+	.S2 (ConfigBits[324+2]),
+	.S2N (ConfigBits_N[324+2]),
+	.S3 (ConfigBits[324+3]),
+	.S3N (ConfigBits_N[324+3]),
+	.X (JS2BEG2)
+	);
+
+// switch matrix multiplexer  JS2BEG3 		MUX-16
+	assign JS2BEG3_input = {BD3,BD2,BD1,BD0,AD2,AD1,AD0,W6END0,W2END4,S4END0,S2END4,E6END0,EE4END3,E2END4,E1END2,N2END4};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG3 (
+	.A0 (JS2BEG3_input[0]),
+	.A1 (JS2BEG3_input[1]),
+	.A2 (JS2BEG3_input[2]),
+	.A3 (JS2BEG3_input[3]),
+	.A4 (JS2BEG3_input[4]),
+	.A5 (JS2BEG3_input[5]),
+	.A6 (JS2BEG3_input[6]),
+	.A7 (JS2BEG3_input[7]),
+	.A8 (JS2BEG3_input[8]),
+	.A9 (JS2BEG3_input[9]),
+	.A10 (JS2BEG3_input[10]),
+	.A11 (JS2BEG3_input[11]),
+	.A12 (JS2BEG3_input[12]),
+	.A13 (JS2BEG3_input[13]),
+	.A14 (JS2BEG3_input[14]),
+	.A15 (JS2BEG3_input[15]),
+	.S0 (ConfigBits[328+0]),
+	.S0N (ConfigBits_N[328+0]),
+	.S1 (ConfigBits[328+1]),
+	.S1N (ConfigBits_N[328+1]),
+	.S2 (ConfigBits[328+2]),
+	.S2N (ConfigBits_N[328+2]),
+	.S3 (ConfigBits[328+3]),
+	.S3N (ConfigBits_N[328+3]),
+	.X (JS2BEG3)
+	);
+
+// switch matrix multiplexer  JS2BEG4 		MUX-16
+	assign JS2BEG4_input = {BD3,BD2,BD1,AD3,AD2,AD1,AD0,W1END3,W1END1,SS4END3,S2END5,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG4 (
+	.A0 (JS2BEG4_input[0]),
+	.A1 (JS2BEG4_input[1]),
+	.A2 (JS2BEG4_input[2]),
+	.A3 (JS2BEG4_input[3]),
+	.A4 (JS2BEG4_input[4]),
+	.A5 (JS2BEG4_input[5]),
+	.A6 (JS2BEG4_input[6]),
+	.A7 (JS2BEG4_input[7]),
+	.A8 (JS2BEG4_input[8]),
+	.A9 (JS2BEG4_input[9]),
+	.A10 (JS2BEG4_input[10]),
+	.A11 (JS2BEG4_input[11]),
+	.A12 (JS2BEG4_input[12]),
+	.A13 (JS2BEG4_input[13]),
+	.A14 (JS2BEG4_input[14]),
+	.A15 (JS2BEG4_input[15]),
+	.S0 (ConfigBits[332+0]),
+	.S0N (ConfigBits_N[332+0]),
+	.S1 (ConfigBits[332+1]),
+	.S1N (ConfigBits_N[332+1]),
+	.S2 (ConfigBits[332+2]),
+	.S2N (ConfigBits_N[332+2]),
+	.S3 (ConfigBits[332+3]),
+	.S3N (ConfigBits_N[332+3]),
+	.X (JS2BEG4)
+	);
+
+// switch matrix multiplexer  JS2BEG5 		MUX-16
+	assign JS2BEG5_input = {BD3,BD2,BD0,AD3,AD2,AD1,AD0,W1END2,W1END0,SS4END2,S2END6,S1END2,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG5 (
+	.A0 (JS2BEG5_input[0]),
+	.A1 (JS2BEG5_input[1]),
+	.A2 (JS2BEG5_input[2]),
+	.A3 (JS2BEG5_input[3]),
+	.A4 (JS2BEG5_input[4]),
+	.A5 (JS2BEG5_input[5]),
+	.A6 (JS2BEG5_input[6]),
+	.A7 (JS2BEG5_input[7]),
+	.A8 (JS2BEG5_input[8]),
+	.A9 (JS2BEG5_input[9]),
+	.A10 (JS2BEG5_input[10]),
+	.A11 (JS2BEG5_input[11]),
+	.A12 (JS2BEG5_input[12]),
+	.A13 (JS2BEG5_input[13]),
+	.A14 (JS2BEG5_input[14]),
+	.A15 (JS2BEG5_input[15]),
+	.S0 (ConfigBits[336+0]),
+	.S0N (ConfigBits_N[336+0]),
+	.S1 (ConfigBits[336+1]),
+	.S1N (ConfigBits_N[336+1]),
+	.S2 (ConfigBits[336+2]),
+	.S2N (ConfigBits_N[336+2]),
+	.S3 (ConfigBits[336+3]),
+	.S3N (ConfigBits_N[336+3]),
+	.X (JS2BEG5)
+	);
+
+// switch matrix multiplexer  JS2BEG6 		MUX-16
+	assign JS2BEG6_input = {BD3,BD1,BD0,AD3,AD2,AD1,AD0,W1END3,W1END1,SS4END1,S2END7,S1END3,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG6 (
+	.A0 (JS2BEG6_input[0]),
+	.A1 (JS2BEG6_input[1]),
+	.A2 (JS2BEG6_input[2]),
+	.A3 (JS2BEG6_input[3]),
+	.A4 (JS2BEG6_input[4]),
+	.A5 (JS2BEG6_input[5]),
+	.A6 (JS2BEG6_input[6]),
+	.A7 (JS2BEG6_input[7]),
+	.A8 (JS2BEG6_input[8]),
+	.A9 (JS2BEG6_input[9]),
+	.A10 (JS2BEG6_input[10]),
+	.A11 (JS2BEG6_input[11]),
+	.A12 (JS2BEG6_input[12]),
+	.A13 (JS2BEG6_input[13]),
+	.A14 (JS2BEG6_input[14]),
+	.A15 (JS2BEG6_input[15]),
+	.S0 (ConfigBits[340+0]),
+	.S0N (ConfigBits_N[340+0]),
+	.S1 (ConfigBits[340+1]),
+	.S1N (ConfigBits_N[340+1]),
+	.S2 (ConfigBits[340+2]),
+	.S2N (ConfigBits_N[340+2]),
+	.S3 (ConfigBits[340+3]),
+	.S3N (ConfigBits_N[340+3]),
+	.X (JS2BEG6)
+	);
+
+// switch matrix multiplexer  JS2BEG7 		MUX-16
+	assign JS2BEG7_input = {BD2,BD1,BD0,AD3,AD2,AD1,AD0,W1END2,W1END0,SS4END0,S2END0,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JS2BEG7 (
+	.A0 (JS2BEG7_input[0]),
+	.A1 (JS2BEG7_input[1]),
+	.A2 (JS2BEG7_input[2]),
+	.A3 (JS2BEG7_input[3]),
+	.A4 (JS2BEG7_input[4]),
+	.A5 (JS2BEG7_input[5]),
+	.A6 (JS2BEG7_input[6]),
+	.A7 (JS2BEG7_input[7]),
+	.A8 (JS2BEG7_input[8]),
+	.A9 (JS2BEG7_input[9]),
+	.A10 (JS2BEG7_input[10]),
+	.A11 (JS2BEG7_input[11]),
+	.A12 (JS2BEG7_input[12]),
+	.A13 (JS2BEG7_input[13]),
+	.A14 (JS2BEG7_input[14]),
+	.A15 (JS2BEG7_input[15]),
+	.S0 (ConfigBits[344+0]),
+	.S0N (ConfigBits_N[344+0]),
+	.S1 (ConfigBits[344+1]),
+	.S1N (ConfigBits_N[344+1]),
+	.S2 (ConfigBits[344+2]),
+	.S2N (ConfigBits_N[344+2]),
+	.S3 (ConfigBits[344+3]),
+	.S3N (ConfigBits_N[344+3]),
+	.X (JS2BEG7)
+	);
+
+// switch matrix multiplexer  JW2BEG0 		MUX-16
+	assign JW2BEG0_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD1,W6END1,W2END1,SS4END0,S4END1,S2END1,E6END1,E2END1,N2END1,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG0 (
+	.A0 (JW2BEG0_input[0]),
+	.A1 (JW2BEG0_input[1]),
+	.A2 (JW2BEG0_input[2]),
+	.A3 (JW2BEG0_input[3]),
+	.A4 (JW2BEG0_input[4]),
+	.A5 (JW2BEG0_input[5]),
+	.A6 (JW2BEG0_input[6]),
+	.A7 (JW2BEG0_input[7]),
+	.A8 (JW2BEG0_input[8]),
+	.A9 (JW2BEG0_input[9]),
+	.A10 (JW2BEG0_input[10]),
+	.A11 (JW2BEG0_input[11]),
+	.A12 (JW2BEG0_input[12]),
+	.A13 (JW2BEG0_input[13]),
+	.A14 (JW2BEG0_input[14]),
+	.A15 (JW2BEG0_input[15]),
+	.S0 (ConfigBits[348+0]),
+	.S0N (ConfigBits_N[348+0]),
+	.S1 (ConfigBits[348+1]),
+	.S1N (ConfigBits_N[348+1]),
+	.S2 (ConfigBits[348+2]),
+	.S2N (ConfigBits_N[348+2]),
+	.S3 (ConfigBits[348+3]),
+	.S3N (ConfigBits_N[348+3]),
+	.X (JW2BEG0)
+	);
+
+// switch matrix multiplexer  JW2BEG1 		MUX-16
+	assign JW2BEG1_input = {BD3,BD2,BD1,BD0,AD3,AD2,AD0,W6END0,W2END2,SS4END1,S4END2,S2END2,E6END0,E2END2,N2END2,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG1 (
+	.A0 (JW2BEG1_input[0]),
+	.A1 (JW2BEG1_input[1]),
+	.A2 (JW2BEG1_input[2]),
+	.A3 (JW2BEG1_input[3]),
+	.A4 (JW2BEG1_input[4]),
+	.A5 (JW2BEG1_input[5]),
+	.A6 (JW2BEG1_input[6]),
+	.A7 (JW2BEG1_input[7]),
+	.A8 (JW2BEG1_input[8]),
+	.A9 (JW2BEG1_input[9]),
+	.A10 (JW2BEG1_input[10]),
+	.A11 (JW2BEG1_input[11]),
+	.A12 (JW2BEG1_input[12]),
+	.A13 (JW2BEG1_input[13]),
+	.A14 (JW2BEG1_input[14]),
+	.A15 (JW2BEG1_input[15]),
+	.S0 (ConfigBits[352+0]),
+	.S0N (ConfigBits_N[352+0]),
+	.S1 (ConfigBits[352+1]),
+	.S1N (ConfigBits_N[352+1]),
+	.S2 (ConfigBits[352+2]),
+	.S2N (ConfigBits_N[352+2]),
+	.S3 (ConfigBits[352+3]),
+	.S3N (ConfigBits_N[352+3]),
+	.X (JW2BEG1)
+	);
+
+// switch matrix multiplexer  JW2BEG2 		MUX-16
+	assign JW2BEG2_input = {BD3,BD2,BD1,BD0,AD3,AD1,AD0,W6END1,W2END3,S4END3,S2END3,E6END1,E2END3,NN4END2,N2END3,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG2 (
+	.A0 (JW2BEG2_input[0]),
+	.A1 (JW2BEG2_input[1]),
+	.A2 (JW2BEG2_input[2]),
+	.A3 (JW2BEG2_input[3]),
+	.A4 (JW2BEG2_input[4]),
+	.A5 (JW2BEG2_input[5]),
+	.A6 (JW2BEG2_input[6]),
+	.A7 (JW2BEG2_input[7]),
+	.A8 (JW2BEG2_input[8]),
+	.A9 (JW2BEG2_input[9]),
+	.A10 (JW2BEG2_input[10]),
+	.A11 (JW2BEG2_input[11]),
+	.A12 (JW2BEG2_input[12]),
+	.A13 (JW2BEG2_input[13]),
+	.A14 (JW2BEG2_input[14]),
+	.A15 (JW2BEG2_input[15]),
+	.S0 (ConfigBits[356+0]),
+	.S0N (ConfigBits_N[356+0]),
+	.S1 (ConfigBits[356+1]),
+	.S1N (ConfigBits_N[356+1]),
+	.S2 (ConfigBits[356+2]),
+	.S2N (ConfigBits_N[356+2]),
+	.S3 (ConfigBits[356+3]),
+	.S3N (ConfigBits_N[356+3]),
+	.X (JW2BEG2)
+	);
+
+// switch matrix multiplexer  JW2BEG3 		MUX-16
+	assign JW2BEG3_input = {BD3,BD2,BD1,BD0,AD2,AD1,AD0,W6END0,W2END4,S4END0,S2END4,E6END0,E2END4,NN4END3,N2END4,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG3 (
+	.A0 (JW2BEG3_input[0]),
+	.A1 (JW2BEG3_input[1]),
+	.A2 (JW2BEG3_input[2]),
+	.A3 (JW2BEG3_input[3]),
+	.A4 (JW2BEG3_input[4]),
+	.A5 (JW2BEG3_input[5]),
+	.A6 (JW2BEG3_input[6]),
+	.A7 (JW2BEG3_input[7]),
+	.A8 (JW2BEG3_input[8]),
+	.A9 (JW2BEG3_input[9]),
+	.A10 (JW2BEG3_input[10]),
+	.A11 (JW2BEG3_input[11]),
+	.A12 (JW2BEG3_input[12]),
+	.A13 (JW2BEG3_input[13]),
+	.A14 (JW2BEG3_input[14]),
+	.A15 (JW2BEG3_input[15]),
+	.S0 (ConfigBits[360+0]),
+	.S0N (ConfigBits_N[360+0]),
+	.S1 (ConfigBits[360+1]),
+	.S1N (ConfigBits_N[360+1]),
+	.S2 (ConfigBits[360+2]),
+	.S2N (ConfigBits_N[360+2]),
+	.S3 (ConfigBits[360+3]),
+	.S3N (ConfigBits_N[360+3]),
+	.X (JW2BEG3)
+	);
+
+// switch matrix multiplexer  JW2BEG4 		MUX-16
+	assign JW2BEG4_input = {BD3,BD2,BD1,AD3,AD2,AD1,AD0,WW4END3,W1END1,S2END5,S1END3,S1END1,E2END5,E1END1,N2END5,N1END1};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG4 (
+	.A0 (JW2BEG4_input[0]),
+	.A1 (JW2BEG4_input[1]),
+	.A2 (JW2BEG4_input[2]),
+	.A3 (JW2BEG4_input[3]),
+	.A4 (JW2BEG4_input[4]),
+	.A5 (JW2BEG4_input[5]),
+	.A6 (JW2BEG4_input[6]),
+	.A7 (JW2BEG4_input[7]),
+	.A8 (JW2BEG4_input[8]),
+	.A9 (JW2BEG4_input[9]),
+	.A10 (JW2BEG4_input[10]),
+	.A11 (JW2BEG4_input[11]),
+	.A12 (JW2BEG4_input[12]),
+	.A13 (JW2BEG4_input[13]),
+	.A14 (JW2BEG4_input[14]),
+	.A15 (JW2BEG4_input[15]),
+	.S0 (ConfigBits[364+0]),
+	.S0N (ConfigBits_N[364+0]),
+	.S1 (ConfigBits[364+1]),
+	.S1N (ConfigBits_N[364+1]),
+	.S2 (ConfigBits[364+2]),
+	.S2N (ConfigBits_N[364+2]),
+	.S3 (ConfigBits[364+3]),
+	.S3N (ConfigBits_N[364+3]),
+	.X (JW2BEG4)
+	);
+
+// switch matrix multiplexer  JW2BEG5 		MUX-16
+	assign JW2BEG5_input = {BD3,BD2,BD0,AD3,AD2,AD1,AD0,WW4END2,W1END2,S2END6,S1END2,S1END0,E2END6,E1END2,N2END6,N1END2};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG5 (
+	.A0 (JW2BEG5_input[0]),
+	.A1 (JW2BEG5_input[1]),
+	.A2 (JW2BEG5_input[2]),
+	.A3 (JW2BEG5_input[3]),
+	.A4 (JW2BEG5_input[4]),
+	.A5 (JW2BEG5_input[5]),
+	.A6 (JW2BEG5_input[6]),
+	.A7 (JW2BEG5_input[7]),
+	.A8 (JW2BEG5_input[8]),
+	.A9 (JW2BEG5_input[9]),
+	.A10 (JW2BEG5_input[10]),
+	.A11 (JW2BEG5_input[11]),
+	.A12 (JW2BEG5_input[12]),
+	.A13 (JW2BEG5_input[13]),
+	.A14 (JW2BEG5_input[14]),
+	.A15 (JW2BEG5_input[15]),
+	.S0 (ConfigBits[368+0]),
+	.S0N (ConfigBits_N[368+0]),
+	.S1 (ConfigBits[368+1]),
+	.S1N (ConfigBits_N[368+1]),
+	.S2 (ConfigBits[368+2]),
+	.S2N (ConfigBits_N[368+2]),
+	.S3 (ConfigBits[368+3]),
+	.S3N (ConfigBits_N[368+3]),
+	.X (JW2BEG5)
+	);
+
+// switch matrix multiplexer  JW2BEG6 		MUX-16
+	assign JW2BEG6_input = {BD3,BD1,BD0,AD3,AD2,AD1,AD0,WW4END1,W1END3,S2END7,S1END3,S1END1,E2END7,E1END3,N2END7,N1END3};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG6 (
+	.A0 (JW2BEG6_input[0]),
+	.A1 (JW2BEG6_input[1]),
+	.A2 (JW2BEG6_input[2]),
+	.A3 (JW2BEG6_input[3]),
+	.A4 (JW2BEG6_input[4]),
+	.A5 (JW2BEG6_input[5]),
+	.A6 (JW2BEG6_input[6]),
+	.A7 (JW2BEG6_input[7]),
+	.A8 (JW2BEG6_input[8]),
+	.A9 (JW2BEG6_input[9]),
+	.A10 (JW2BEG6_input[10]),
+	.A11 (JW2BEG6_input[11]),
+	.A12 (JW2BEG6_input[12]),
+	.A13 (JW2BEG6_input[13]),
+	.A14 (JW2BEG6_input[14]),
+	.A15 (JW2BEG6_input[15]),
+	.S0 (ConfigBits[372+0]),
+	.S0N (ConfigBits_N[372+0]),
+	.S1 (ConfigBits[372+1]),
+	.S1N (ConfigBits_N[372+1]),
+	.S2 (ConfigBits[372+2]),
+	.S2N (ConfigBits_N[372+2]),
+	.S3 (ConfigBits[372+3]),
+	.S3N (ConfigBits_N[372+3]),
+	.X (JW2BEG6)
+	);
+
+// switch matrix multiplexer  JW2BEG7 		MUX-16
+	assign JW2BEG7_input = {BD2,BD1,BD0,AD3,AD2,AD1,AD0,WW4END0,W1END0,S2END0,S1END2,S1END0,E2END0,E1END0,N2END0,N1END0};
+	cus_mux161_buf inst_cus_mux161_buf_JW2BEG7 (
+	.A0 (JW2BEG7_input[0]),
+	.A1 (JW2BEG7_input[1]),
+	.A2 (JW2BEG7_input[2]),
+	.A3 (JW2BEG7_input[3]),
+	.A4 (JW2BEG7_input[4]),
+	.A5 (JW2BEG7_input[5]),
+	.A6 (JW2BEG7_input[6]),
+	.A7 (JW2BEG7_input[7]),
+	.A8 (JW2BEG7_input[8]),
+	.A9 (JW2BEG7_input[9]),
+	.A10 (JW2BEG7_input[10]),
+	.A11 (JW2BEG7_input[11]),
+	.A12 (JW2BEG7_input[12]),
+	.A13 (JW2BEG7_input[13]),
+	.A14 (JW2BEG7_input[14]),
+	.A15 (JW2BEG7_input[15]),
+	.S0 (ConfigBits[376+0]),
+	.S0N (ConfigBits_N[376+0]),
+	.S1 (ConfigBits[376+1]),
+	.S1N (ConfigBits_N[376+1]),
+	.S2 (ConfigBits[376+2]),
+	.S2N (ConfigBits_N[376+2]),
+	.S3 (ConfigBits[376+3]),
+	.S3N (ConfigBits_N[376+3]),
+	.X (JW2BEG7)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG0 		MUX-4
+	assign J_l_AB_BEG0_input = {JN2END1,W2END3,S4END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG0 (
+	.A0 (J_l_AB_BEG0_input[0]),
+	.A1 (J_l_AB_BEG0_input[1]),
+	.A2 (J_l_AB_BEG0_input[2]),
+	.A3 (J_l_AB_BEG0_input[3]),
+	.S0 (ConfigBits[380+0]),
+	.S0N (ConfigBits_N[380+0]),
+	.S1 (ConfigBits[380+1]),
+	.S1N (ConfigBits_N[380+1]),
+	.X (J_l_AB_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG1 		MUX-4
+	assign J_l_AB_BEG1_input = {JE2END1,W2END7,S4END2,E2END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG1 (
+	.A0 (J_l_AB_BEG1_input[0]),
+	.A1 (J_l_AB_BEG1_input[1]),
+	.A2 (J_l_AB_BEG1_input[2]),
+	.A3 (J_l_AB_BEG1_input[3]),
+	.S0 (ConfigBits[382+0]),
+	.S0N (ConfigBits_N[382+0]),
+	.S1 (ConfigBits[382+1]),
+	.S1N (ConfigBits_N[382+1]),
+	.X (J_l_AB_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG2 		MUX-4
+	assign J_l_AB_BEG2_input = {JS2END1,W6END1,E6END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG2 (
+	.A0 (J_l_AB_BEG2_input[0]),
+	.A1 (J_l_AB_BEG2_input[1]),
+	.A2 (J_l_AB_BEG2_input[2]),
+	.A3 (J_l_AB_BEG2_input[3]),
+	.S0 (ConfigBits[384+0]),
+	.S0N (ConfigBits_N[384+0]),
+	.S1 (ConfigBits[384+1]),
+	.S1N (ConfigBits_N[384+1]),
+	.X (J_l_AB_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_AB_BEG3 		MUX-4
+	assign J_l_AB_BEG3_input = {JW2END1,S4END0,E6END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_AB_BEG3 (
+	.A0 (J_l_AB_BEG3_input[0]),
+	.A1 (J_l_AB_BEG3_input[1]),
+	.A2 (J_l_AB_BEG3_input[2]),
+	.A3 (J_l_AB_BEG3_input[3]),
+	.S0 (ConfigBits[386+0]),
+	.S0N (ConfigBits_N[386+0]),
+	.S1 (ConfigBits[386+1]),
+	.S1N (ConfigBits_N[386+1]),
+	.X (J_l_AB_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG0 		MUX-4
+	assign J_l_CD_BEG0_input = {JN2END2,W2END3,S4END3,E2END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG0 (
+	.A0 (J_l_CD_BEG0_input[0]),
+	.A1 (J_l_CD_BEG0_input[1]),
+	.A2 (J_l_CD_BEG0_input[2]),
+	.A3 (J_l_CD_BEG0_input[3]),
+	.S0 (ConfigBits[388+0]),
+	.S0N (ConfigBits_N[388+0]),
+	.S1 (ConfigBits[388+1]),
+	.S1N (ConfigBits_N[388+1]),
+	.X (J_l_CD_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG1 		MUX-4
+	assign J_l_CD_BEG1_input = {JE2END2,W2END7,E2END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG1 (
+	.A0 (J_l_CD_BEG1_input[0]),
+	.A1 (J_l_CD_BEG1_input[1]),
+	.A2 (J_l_CD_BEG1_input[2]),
+	.A3 (J_l_CD_BEG1_input[3]),
+	.S0 (ConfigBits[390+0]),
+	.S0N (ConfigBits_N[390+0]),
+	.S1 (ConfigBits[390+1]),
+	.S1N (ConfigBits_N[390+1]),
+	.X (J_l_CD_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG2 		MUX-4
+	assign J_l_CD_BEG2_input = {JS2END2,S4END1,E6END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG2 (
+	.A0 (J_l_CD_BEG2_input[0]),
+	.A1 (J_l_CD_BEG2_input[1]),
+	.A2 (J_l_CD_BEG2_input[2]),
+	.A3 (J_l_CD_BEG2_input[3]),
+	.S0 (ConfigBits[392+0]),
+	.S0N (ConfigBits_N[392+0]),
+	.S1 (ConfigBits[392+1]),
+	.S1N (ConfigBits_N[392+1]),
+	.X (J_l_CD_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_CD_BEG3 		MUX-4
+	assign J_l_CD_BEG3_input = {JW2END2,W6END0,S4END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_CD_BEG3 (
+	.A0 (J_l_CD_BEG3_input[0]),
+	.A1 (J_l_CD_BEG3_input[1]),
+	.A2 (J_l_CD_BEG3_input[2]),
+	.A3 (J_l_CD_BEG3_input[3]),
+	.S0 (ConfigBits[394+0]),
+	.S0N (ConfigBits_N[394+0]),
+	.S1 (ConfigBits[394+1]),
+	.S1N (ConfigBits_N[394+1]),
+	.X (J_l_CD_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG0 		MUX-4
+	assign J_l_EF_BEG0_input = {JN2END3,W2END3,E2END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG0 (
+	.A0 (J_l_EF_BEG0_input[0]),
+	.A1 (J_l_EF_BEG0_input[1]),
+	.A2 (J_l_EF_BEG0_input[2]),
+	.A3 (J_l_EF_BEG0_input[3]),
+	.S0 (ConfigBits[396+0]),
+	.S0N (ConfigBits_N[396+0]),
+	.S1 (ConfigBits[396+1]),
+	.S1N (ConfigBits_N[396+1]),
+	.X (J_l_EF_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG1 		MUX-4
+	assign J_l_EF_BEG1_input = {JE2END3,S4END2,E2END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG1 (
+	.A0 (J_l_EF_BEG1_input[0]),
+	.A1 (J_l_EF_BEG1_input[1]),
+	.A2 (J_l_EF_BEG1_input[2]),
+	.A3 (J_l_EF_BEG1_input[3]),
+	.S0 (ConfigBits[398+0]),
+	.S0N (ConfigBits_N[398+0]),
+	.S1 (ConfigBits[398+1]),
+	.S1N (ConfigBits_N[398+1]),
+	.X (J_l_EF_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG2 		MUX-4
+	assign J_l_EF_BEG2_input = {JS2END3,W2END4,S4END1,N4END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG2 (
+	.A0 (J_l_EF_BEG2_input[0]),
+	.A1 (J_l_EF_BEG2_input[1]),
+	.A2 (J_l_EF_BEG2_input[2]),
+	.A3 (J_l_EF_BEG2_input[3]),
+	.S0 (ConfigBits[400+0]),
+	.S0N (ConfigBits_N[400+0]),
+	.S1 (ConfigBits[400+1]),
+	.S1N (ConfigBits_N[400+1]),
+	.X (J_l_EF_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_EF_BEG3 		MUX-4
+	assign J_l_EF_BEG3_input = {JW2END3,W2END0,S4END0,E6END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_EF_BEG3 (
+	.A0 (J_l_EF_BEG3_input[0]),
+	.A1 (J_l_EF_BEG3_input[1]),
+	.A2 (J_l_EF_BEG3_input[2]),
+	.A3 (J_l_EF_BEG3_input[3]),
+	.S0 (ConfigBits[402+0]),
+	.S0N (ConfigBits_N[402+0]),
+	.S1 (ConfigBits[402+1]),
+	.S1N (ConfigBits_N[402+1]),
+	.X (J_l_EF_BEG3)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG0 		MUX-4
+	assign J_l_GH_BEG0_input = {JN2END4,S4END3,E2END3,N4END3};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG0 (
+	.A0 (J_l_GH_BEG0_input[0]),
+	.A1 (J_l_GH_BEG0_input[1]),
+	.A2 (J_l_GH_BEG0_input[2]),
+	.A3 (J_l_GH_BEG0_input[3]),
+	.S0 (ConfigBits[404+0]),
+	.S0N (ConfigBits_N[404+0]),
+	.S1 (ConfigBits[404+1]),
+	.S1N (ConfigBits_N[404+1]),
+	.X (J_l_GH_BEG0)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG1 		MUX-4
+	assign J_l_GH_BEG1_input = {JE2END4,W2END2,S4END2,N4END2};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG1 (
+	.A0 (J_l_GH_BEG1_input[0]),
+	.A1 (J_l_GH_BEG1_input[1]),
+	.A2 (J_l_GH_BEG1_input[2]),
+	.A3 (J_l_GH_BEG1_input[3]),
+	.S0 (ConfigBits[406+0]),
+	.S0N (ConfigBits_N[406+0]),
+	.S1 (ConfigBits[406+1]),
+	.S1N (ConfigBits_N[406+1]),
+	.X (J_l_GH_BEG1)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG2 		MUX-4
+	assign J_l_GH_BEG2_input = {JS2END4,W2END4,S4END1,E6END1};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG2 (
+	.A0 (J_l_GH_BEG2_input[0]),
+	.A1 (J_l_GH_BEG2_input[1]),
+	.A2 (J_l_GH_BEG2_input[2]),
+	.A3 (J_l_GH_BEG2_input[3]),
+	.S0 (ConfigBits[408+0]),
+	.S0N (ConfigBits_N[408+0]),
+	.S1 (ConfigBits[408+1]),
+	.S1N (ConfigBits_N[408+1]),
+	.X (J_l_GH_BEG2)
+	);
+
+// switch matrix multiplexer  J_l_GH_BEG3 		MUX-4
+	assign J_l_GH_BEG3_input = {JW2END4,W2END0,E6END0,N4END0};
+	cus_mux41_buf inst_cus_mux41_buf_J_l_GH_BEG3 (
+	.A0 (J_l_GH_BEG3_input[0]),
+	.A1 (J_l_GH_BEG3_input[1]),
+	.A2 (J_l_GH_BEG3_input[2]),
+	.A3 (J_l_GH_BEG3_input[3]),
+	.S0 (ConfigBits[410+0]),
+	.S0N (ConfigBits_N[410+0]),
+	.S1 (ConfigBits[410+1]),
+	.S1N (ConfigBits_N[410+1]),
+	.X (J_l_GH_BEG3)
+	);
+
+	assign DEBUG_select_N1BEG0 = ConfigBits[1:0];
+	assign DEBUG_select_N1BEG1 = ConfigBits[3:2];
+	assign DEBUG_select_N1BEG2 = ConfigBits[5:4];
+	assign DEBUG_select_N1BEG3 = ConfigBits[7:6];
+	assign DEBUG_select_N4BEG0 = ConfigBits[9:8];
+	assign DEBUG_select_N4BEG1 = ConfigBits[11:10];
+	assign DEBUG_select_N4BEG2 = ConfigBits[13:12];
+	assign DEBUG_select_N4BEG3 = ConfigBits[15:14];
+	assign DEBUG_select_NN4BEG0 = ConfigBits[18:16];
+	assign DEBUG_select_NN4BEG1 = ConfigBits[21:19];
+	assign DEBUG_select_NN4BEG2 = ConfigBits[24:22];
+	assign DEBUG_select_NN4BEG3 = ConfigBits[27:25];
+	assign DEBUG_select_E1BEG0 = ConfigBits[29:28];
+	assign DEBUG_select_E1BEG1 = ConfigBits[31:30];
+	assign DEBUG_select_E1BEG2 = ConfigBits[33:32];
+	assign DEBUG_select_E1BEG3 = ConfigBits[35:34];
+	assign DEBUG_select_EE4BEG0 = ConfigBits[38:36];
+	assign DEBUG_select_EE4BEG1 = ConfigBits[41:39];
+	assign DEBUG_select_EE4BEG2 = ConfigBits[44:42];
+	assign DEBUG_select_EE4BEG3 = ConfigBits[47:45];
+	assign DEBUG_select_E6BEG0 = ConfigBits[51:48];
+	assign DEBUG_select_E6BEG1 = ConfigBits[55:52];
+	assign DEBUG_select_S1BEG0 = ConfigBits[57:56];
+	assign DEBUG_select_S1BEG1 = ConfigBits[59:58];
+	assign DEBUG_select_S1BEG2 = ConfigBits[61:60];
+	assign DEBUG_select_S1BEG3 = ConfigBits[63:62];
+	assign DEBUG_select_S4BEG0 = ConfigBits[65:64];
+	assign DEBUG_select_S4BEG1 = ConfigBits[67:66];
+	assign DEBUG_select_S4BEG2 = ConfigBits[69:68];
+	assign DEBUG_select_S4BEG3 = ConfigBits[71:70];
+	assign DEBUG_select_SS4BEG0 = ConfigBits[74:72];
+	assign DEBUG_select_SS4BEG1 = ConfigBits[77:75];
+	assign DEBUG_select_SS4BEG2 = ConfigBits[80:78];
+	assign DEBUG_select_SS4BEG3 = ConfigBits[83:81];
+	assign DEBUG_select_W1BEG0 = ConfigBits[85:84];
+	assign DEBUG_select_W1BEG1 = ConfigBits[87:86];
+	assign DEBUG_select_W1BEG2 = ConfigBits[89:88];
+	assign DEBUG_select_W1BEG3 = ConfigBits[91:90];
+	assign DEBUG_select_WW4BEG0 = ConfigBits[94:92];
+	assign DEBUG_select_WW4BEG1 = ConfigBits[97:95];
+	assign DEBUG_select_WW4BEG2 = ConfigBits[100:98];
+	assign DEBUG_select_WW4BEG3 = ConfigBits[103:101];
+	assign DEBUG_select_W6BEG0 = ConfigBits[107:104];
+	assign DEBUG_select_W6BEG1 = ConfigBits[111:108];
+	assign DEBUG_select_D0 = ConfigBits[113:112];
+	assign DEBUG_select_D1 = ConfigBits[115:114];
+	assign DEBUG_select_D2 = ConfigBits[117:116];
+	assign DEBUG_select_D3 = ConfigBits[119:118];
+	assign DEBUG_select_W_ADR0 = ConfigBits[121:120];
+	assign DEBUG_select_W_ADR1 = ConfigBits[123:122];
+	assign DEBUG_select_W_ADR2 = ConfigBits[125:124];
+	assign DEBUG_select_W_ADR3 = ConfigBits[127:126];
+	assign DEBUG_select_W_ADR4 = ConfigBits[130:128];
+	assign DEBUG_select_W_en = ConfigBits[133:131];
+	assign DEBUG_select_A_ADR0 = ConfigBits[135:134];
+	assign DEBUG_select_A_ADR1 = ConfigBits[137:136];
+	assign DEBUG_select_A_ADR2 = ConfigBits[139:138];
+	assign DEBUG_select_A_ADR3 = ConfigBits[141:140];
+	assign DEBUG_select_A_ADR4 = ConfigBits[144:142];
+	assign DEBUG_select_B_ADR0 = ConfigBits[146:145];
+	assign DEBUG_select_B_ADR1 = ConfigBits[148:147];
+	assign DEBUG_select_B_ADR2 = ConfigBits[150:149];
+	assign DEBUG_select_B_ADR3 = ConfigBits[152:151];
+	assign DEBUG_select_B_ADR4 = ConfigBits[155:153];
+	assign DEBUG_select_J2MID_ABa_BEG0 = ConfigBits[157:156];
+	assign DEBUG_select_J2MID_ABa_BEG1 = ConfigBits[159:158];
+	assign DEBUG_select_J2MID_ABa_BEG2 = ConfigBits[161:160];
+	assign DEBUG_select_J2MID_ABa_BEG3 = ConfigBits[163:162];
+	assign DEBUG_select_J2MID_CDa_BEG0 = ConfigBits[165:164];
+	assign DEBUG_select_J2MID_CDa_BEG1 = ConfigBits[167:166];
+	assign DEBUG_select_J2MID_CDa_BEG2 = ConfigBits[169:168];
+	assign DEBUG_select_J2MID_CDa_BEG3 = ConfigBits[171:170];
+	assign DEBUG_select_J2MID_EFa_BEG0 = ConfigBits[173:172];
+	assign DEBUG_select_J2MID_EFa_BEG1 = ConfigBits[175:174];
+	assign DEBUG_select_J2MID_EFa_BEG2 = ConfigBits[177:176];
+	assign DEBUG_select_J2MID_EFa_BEG3 = ConfigBits[179:178];
+	assign DEBUG_select_J2MID_GHa_BEG0 = ConfigBits[181:180];
+	assign DEBUG_select_J2MID_GHa_BEG1 = ConfigBits[183:182];
+	assign DEBUG_select_J2MID_GHa_BEG2 = ConfigBits[185:184];
+	assign DEBUG_select_J2MID_GHa_BEG3 = ConfigBits[187:186];
+	assign DEBUG_select_J2MID_ABb_BEG0 = ConfigBits[189:188];
+	assign DEBUG_select_J2MID_ABb_BEG1 = ConfigBits[191:190];
+	assign DEBUG_select_J2MID_ABb_BEG2 = ConfigBits[193:192];
+	assign DEBUG_select_J2MID_ABb_BEG3 = ConfigBits[195:194];
+	assign DEBUG_select_J2MID_CDb_BEG0 = ConfigBits[197:196];
+	assign DEBUG_select_J2MID_CDb_BEG1 = ConfigBits[199:198];
+	assign DEBUG_select_J2MID_CDb_BEG2 = ConfigBits[201:200];
+	assign DEBUG_select_J2MID_CDb_BEG3 = ConfigBits[203:202];
+	assign DEBUG_select_J2MID_EFb_BEG0 = ConfigBits[205:204];
+	assign DEBUG_select_J2MID_EFb_BEG1 = ConfigBits[207:206];
+	assign DEBUG_select_J2MID_EFb_BEG2 = ConfigBits[209:208];
+	assign DEBUG_select_J2MID_EFb_BEG3 = ConfigBits[211:210];
+	assign DEBUG_select_J2MID_GHb_BEG0 = ConfigBits[213:212];
+	assign DEBUG_select_J2MID_GHb_BEG1 = ConfigBits[215:214];
+	assign DEBUG_select_J2MID_GHb_BEG2 = ConfigBits[217:216];
+	assign DEBUG_select_J2MID_GHb_BEG3 = ConfigBits[219:218];
+	assign DEBUG_select_J2END_AB_BEG0 = ConfigBits[221:220];
+	assign DEBUG_select_J2END_AB_BEG1 = ConfigBits[223:222];
+	assign DEBUG_select_J2END_AB_BEG2 = ConfigBits[225:224];
+	assign DEBUG_select_J2END_AB_BEG3 = ConfigBits[227:226];
+	assign DEBUG_select_J2END_CD_BEG0 = ConfigBits[229:228];
+	assign DEBUG_select_J2END_CD_BEG1 = ConfigBits[231:230];
+	assign DEBUG_select_J2END_CD_BEG2 = ConfigBits[233:232];
+	assign DEBUG_select_J2END_CD_BEG3 = ConfigBits[235:234];
+	assign DEBUG_select_J2END_EF_BEG0 = ConfigBits[237:236];
+	assign DEBUG_select_J2END_EF_BEG1 = ConfigBits[239:238];
+	assign DEBUG_select_J2END_EF_BEG2 = ConfigBits[241:240];
+	assign DEBUG_select_J2END_EF_BEG3 = ConfigBits[243:242];
+	assign DEBUG_select_J2END_GH_BEG0 = ConfigBits[245:244];
+	assign DEBUG_select_J2END_GH_BEG1 = ConfigBits[247:246];
+	assign DEBUG_select_J2END_GH_BEG2 = ConfigBits[249:248];
+	assign DEBUG_select_J2END_GH_BEG3 = ConfigBits[251:250];
+	assign DEBUG_select_JN2BEG0 = ConfigBits[255:252];
+	assign DEBUG_select_JN2BEG1 = ConfigBits[259:256];
+	assign DEBUG_select_JN2BEG2 = ConfigBits[263:260];
+	assign DEBUG_select_JN2BEG3 = ConfigBits[267:264];
+	assign DEBUG_select_JN2BEG4 = ConfigBits[271:268];
+	assign DEBUG_select_JN2BEG5 = ConfigBits[275:272];
+	assign DEBUG_select_JN2BEG6 = ConfigBits[279:276];
+	assign DEBUG_select_JN2BEG7 = ConfigBits[283:280];
+	assign DEBUG_select_JE2BEG0 = ConfigBits[287:284];
+	assign DEBUG_select_JE2BEG1 = ConfigBits[291:288];
+	assign DEBUG_select_JE2BEG2 = ConfigBits[295:292];
+	assign DEBUG_select_JE2BEG3 = ConfigBits[299:296];
+	assign DEBUG_select_JE2BEG4 = ConfigBits[303:300];
+	assign DEBUG_select_JE2BEG5 = ConfigBits[307:304];
+	assign DEBUG_select_JE2BEG6 = ConfigBits[311:308];
+	assign DEBUG_select_JE2BEG7 = ConfigBits[315:312];
+	assign DEBUG_select_JS2BEG0 = ConfigBits[319:316];
+	assign DEBUG_select_JS2BEG1 = ConfigBits[323:320];
+	assign DEBUG_select_JS2BEG2 = ConfigBits[327:324];
+	assign DEBUG_select_JS2BEG3 = ConfigBits[331:328];
+	assign DEBUG_select_JS2BEG4 = ConfigBits[335:332];
+	assign DEBUG_select_JS2BEG5 = ConfigBits[339:336];
+	assign DEBUG_select_JS2BEG6 = ConfigBits[343:340];
+	assign DEBUG_select_JS2BEG7 = ConfigBits[347:344];
+	assign DEBUG_select_JW2BEG0 = ConfigBits[351:348];
+	assign DEBUG_select_JW2BEG1 = ConfigBits[355:352];
+	assign DEBUG_select_JW2BEG2 = ConfigBits[359:356];
+	assign DEBUG_select_JW2BEG3 = ConfigBits[363:360];
+	assign DEBUG_select_JW2BEG4 = ConfigBits[367:364];
+	assign DEBUG_select_JW2BEG5 = ConfigBits[371:368];
+	assign DEBUG_select_JW2BEG6 = ConfigBits[375:372];
+	assign DEBUG_select_JW2BEG7 = ConfigBits[379:376];
+	assign DEBUG_select_J_l_AB_BEG0 = ConfigBits[381:380];
+	assign DEBUG_select_J_l_AB_BEG1 = ConfigBits[383:382];
+	assign DEBUG_select_J_l_AB_BEG2 = ConfigBits[385:384];
+	assign DEBUG_select_J_l_AB_BEG3 = ConfigBits[387:386];
+	assign DEBUG_select_J_l_CD_BEG0 = ConfigBits[389:388];
+	assign DEBUG_select_J_l_CD_BEG1 = ConfigBits[391:390];
+	assign DEBUG_select_J_l_CD_BEG2 = ConfigBits[393:392];
+	assign DEBUG_select_J_l_CD_BEG3 = ConfigBits[395:394];
+	assign DEBUG_select_J_l_EF_BEG0 = ConfigBits[397:396];
+	assign DEBUG_select_J_l_EF_BEG1 = ConfigBits[399:398];
+	assign DEBUG_select_J_l_EF_BEG2 = ConfigBits[401:400];
+	assign DEBUG_select_J_l_EF_BEG3 = ConfigBits[403:402];
+	assign DEBUG_select_J_l_GH_BEG0 = ConfigBits[405:404];
+	assign DEBUG_select_J_l_GH_BEG1 = ConfigBits[407:406];
+	assign DEBUG_select_J_l_GH_BEG2 = ConfigBits[409:408];
+	assign DEBUG_select_J_l_GH_BEG3 = ConfigBits[411:410];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/RegFile_tile.v b/verilog/rtl/eFPGA_core/RegFile_tile.v
new file mode 100644
index 0000000..c1faec3
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/RegFile_tile.v
@@ -0,0 +1,2099 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module RegFile (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, N1END, N2MID, N2END, N4END, NN4END, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 414;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NN4END  
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	input [3:0] E1END; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:E1END  
+	input [7:0] E2MID; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:E2MID  
+	input [7:0] E2END; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:E2END  
+	input [15:0] EE4END; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:EE4END  
+	input [11:0] E6END; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:E6END  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:SS4END  
+	//  WEST
+	output [3:0] W1BEG; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	output [7:0] W2BEG; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	output [7:0] W2BEGb; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	output [15:0] WW4BEG; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	output [11:0] W6BEG; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:W1BEG destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEG destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:W2BEGb destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:WW4BEG destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:W6BEG destination_name:W6END  
+	// Tile IO ports from BELs
+	input UserCLK;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire D0;
+	wire D1;
+	wire D2;
+	wire D3;
+	wire W_ADR0;
+	wire W_ADR1;
+	wire W_ADR2;
+	wire W_ADR3;
+	wire W_ADR4;
+	wire W_en;
+	wire A_ADR0;
+	wire A_ADR1;
+	wire A_ADR2;
+	wire A_ADR3;
+	wire A_ADR4;
+	wire B_ADR0;
+	wire B_ADR1;
+	wire B_ADR2;
+	wire B_ADR3;
+	wire B_ADR4;
+	wire AD0;
+	wire AD1;
+	wire AD2;
+	wire AD3;
+	wire BD0;
+	wire BD1;
+	wire BD2;
+	wire BD3;
+//jump wires
+	wire [4-1:0] J2MID_ABa_BEG;
+	wire [4-1:0] J2MID_CDa_BEG;
+	wire [4-1:0] J2MID_EFa_BEG;
+	wire [4-1:0] J2MID_GHa_BEG;
+	wire [4-1:0] J2MID_ABb_BEG;
+	wire [4-1:0] J2MID_CDb_BEG;
+	wire [4-1:0] J2MID_EFb_BEG;
+	wire [4-1:0] J2MID_GHb_BEG;
+	wire [4-1:0] J2END_AB_BEG;
+	wire [4-1:0] J2END_CD_BEG;
+	wire [4-1:0] J2END_EF_BEG;
+	wire [4-1:0] J2END_GH_BEG;
+	wire [8-1:0] JN2BEG;
+	wire [8-1:0] JE2BEG;
+	wire [8-1:0] JS2BEG;
+	wire [8-1:0] JW2BEG;
+	wire [4-1:0] J_l_AB_BEG;
+	wire [4-1:0] J_l_CD_BEG;
+	wire [4-1:0] J_l_EF_BEG;
+	wire [4-1:0] J_l_GH_BEG;
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	wire [15:0] N4END_i;
+	wire [11:0] N4BEG_i;
+	assign N4BEG_i[15-4:0] = N4END_i[15:4];
+
+	my_buf N4END_inbuf_0 (
+	.A(N4END[4]),
+	.X(N4END_i[4])
+	);
+
+	my_buf N4END_inbuf_1 (
+	.A(N4END[5]),
+	.X(N4END_i[5])
+	);
+
+	my_buf N4END_inbuf_2 (
+	.A(N4END[6]),
+	.X(N4END_i[6])
+	);
+
+	my_buf N4END_inbuf_3 (
+	.A(N4END[7]),
+	.X(N4END_i[7])
+	);
+
+	my_buf N4END_inbuf_4 (
+	.A(N4END[8]),
+	.X(N4END_i[8])
+	);
+
+	my_buf N4END_inbuf_5 (
+	.A(N4END[9]),
+	.X(N4END_i[9])
+	);
+
+	my_buf N4END_inbuf_6 (
+	.A(N4END[10]),
+	.X(N4END_i[10])
+	);
+
+	my_buf N4END_inbuf_7 (
+	.A(N4END[11]),
+	.X(N4END_i[11])
+	);
+
+	my_buf N4END_inbuf_8 (
+	.A(N4END[12]),
+	.X(N4END_i[12])
+	);
+
+	my_buf N4END_inbuf_9 (
+	.A(N4END[13]),
+	.X(N4END_i[13])
+	);
+
+	my_buf N4END_inbuf_10 (
+	.A(N4END[14]),
+	.X(N4END_i[14])
+	);
+
+	my_buf N4END_inbuf_11 (
+	.A(N4END[15]),
+	.X(N4END_i[15])
+	);
+
+	my_buf N4BEG_outbuf_0 (
+	.A(N4BEG_i[0]),
+	.X(N4BEG[0])
+	);
+
+	my_buf N4BEG_outbuf_1 (
+	.A(N4BEG_i[1]),
+	.X(N4BEG[1])
+	);
+
+	my_buf N4BEG_outbuf_2 (
+	.A(N4BEG_i[2]),
+	.X(N4BEG[2])
+	);
+
+	my_buf N4BEG_outbuf_3 (
+	.A(N4BEG_i[3]),
+	.X(N4BEG[3])
+	);
+
+	my_buf N4BEG_outbuf_4 (
+	.A(N4BEG_i[4]),
+	.X(N4BEG[4])
+	);
+
+	my_buf N4BEG_outbuf_5 (
+	.A(N4BEG_i[5]),
+	.X(N4BEG[5])
+	);
+
+	my_buf N4BEG_outbuf_6 (
+	.A(N4BEG_i[6]),
+	.X(N4BEG[6])
+	);
+
+	my_buf N4BEG_outbuf_7 (
+	.A(N4BEG_i[7]),
+	.X(N4BEG[7])
+	);
+
+	my_buf N4BEG_outbuf_8 (
+	.A(N4BEG_i[8]),
+	.X(N4BEG[8])
+	);
+
+	my_buf N4BEG_outbuf_9 (
+	.A(N4BEG_i[9]),
+	.X(N4BEG[9])
+	);
+
+	my_buf N4BEG_outbuf_10 (
+	.A(N4BEG_i[10]),
+	.X(N4BEG[10])
+	);
+
+	my_buf N4BEG_outbuf_11 (
+	.A(N4BEG_i[11]),
+	.X(N4BEG[11])
+	);
+
+	wire [15:0] NN4END_i;
+	wire [11:0] NN4BEG_i;
+	assign NN4BEG_i[15-4:0] = NN4END_i[15:4];
+
+	my_buf NN4END_inbuf_0 (
+	.A(NN4END[4]),
+	.X(NN4END_i[4])
+	);
+
+	my_buf NN4END_inbuf_1 (
+	.A(NN4END[5]),
+	.X(NN4END_i[5])
+	);
+
+	my_buf NN4END_inbuf_2 (
+	.A(NN4END[6]),
+	.X(NN4END_i[6])
+	);
+
+	my_buf NN4END_inbuf_3 (
+	.A(NN4END[7]),
+	.X(NN4END_i[7])
+	);
+
+	my_buf NN4END_inbuf_4 (
+	.A(NN4END[8]),
+	.X(NN4END_i[8])
+	);
+
+	my_buf NN4END_inbuf_5 (
+	.A(NN4END[9]),
+	.X(NN4END_i[9])
+	);
+
+	my_buf NN4END_inbuf_6 (
+	.A(NN4END[10]),
+	.X(NN4END_i[10])
+	);
+
+	my_buf NN4END_inbuf_7 (
+	.A(NN4END[11]),
+	.X(NN4END_i[11])
+	);
+
+	my_buf NN4END_inbuf_8 (
+	.A(NN4END[12]),
+	.X(NN4END_i[12])
+	);
+
+	my_buf NN4END_inbuf_9 (
+	.A(NN4END[13]),
+	.X(NN4END_i[13])
+	);
+
+	my_buf NN4END_inbuf_10 (
+	.A(NN4END[14]),
+	.X(NN4END_i[14])
+	);
+
+	my_buf NN4END_inbuf_11 (
+	.A(NN4END[15]),
+	.X(NN4END_i[15])
+	);
+
+	my_buf NN4BEG_outbuf_0 (
+	.A(NN4BEG_i[0]),
+	.X(NN4BEG[0])
+	);
+
+	my_buf NN4BEG_outbuf_1 (
+	.A(NN4BEG_i[1]),
+	.X(NN4BEG[1])
+	);
+
+	my_buf NN4BEG_outbuf_2 (
+	.A(NN4BEG_i[2]),
+	.X(NN4BEG[2])
+	);
+
+	my_buf NN4BEG_outbuf_3 (
+	.A(NN4BEG_i[3]),
+	.X(NN4BEG[3])
+	);
+
+	my_buf NN4BEG_outbuf_4 (
+	.A(NN4BEG_i[4]),
+	.X(NN4BEG[4])
+	);
+
+	my_buf NN4BEG_outbuf_5 (
+	.A(NN4BEG_i[5]),
+	.X(NN4BEG[5])
+	);
+
+	my_buf NN4BEG_outbuf_6 (
+	.A(NN4BEG_i[6]),
+	.X(NN4BEG[6])
+	);
+
+	my_buf NN4BEG_outbuf_7 (
+	.A(NN4BEG_i[7]),
+	.X(NN4BEG[7])
+	);
+
+	my_buf NN4BEG_outbuf_8 (
+	.A(NN4BEG_i[8]),
+	.X(NN4BEG[8])
+	);
+
+	my_buf NN4BEG_outbuf_9 (
+	.A(NN4BEG_i[9]),
+	.X(NN4BEG[9])
+	);
+
+	my_buf NN4BEG_outbuf_10 (
+	.A(NN4BEG_i[10]),
+	.X(NN4BEG[10])
+	);
+
+	my_buf NN4BEG_outbuf_11 (
+	.A(NN4BEG_i[11]),
+	.X(NN4BEG[11])
+	);
+
+	wire [15:0] EE4END_i;
+	wire [11:0] EE4BEG_i;
+	assign EE4BEG_i[15-4:0] = EE4END_i[15:4];
+
+	my_buf EE4END_inbuf_0 (
+	.A(EE4END[4]),
+	.X(EE4END_i[4])
+	);
+
+	my_buf EE4END_inbuf_1 (
+	.A(EE4END[5]),
+	.X(EE4END_i[5])
+	);
+
+	my_buf EE4END_inbuf_2 (
+	.A(EE4END[6]),
+	.X(EE4END_i[6])
+	);
+
+	my_buf EE4END_inbuf_3 (
+	.A(EE4END[7]),
+	.X(EE4END_i[7])
+	);
+
+	my_buf EE4END_inbuf_4 (
+	.A(EE4END[8]),
+	.X(EE4END_i[8])
+	);
+
+	my_buf EE4END_inbuf_5 (
+	.A(EE4END[9]),
+	.X(EE4END_i[9])
+	);
+
+	my_buf EE4END_inbuf_6 (
+	.A(EE4END[10]),
+	.X(EE4END_i[10])
+	);
+
+	my_buf EE4END_inbuf_7 (
+	.A(EE4END[11]),
+	.X(EE4END_i[11])
+	);
+
+	my_buf EE4END_inbuf_8 (
+	.A(EE4END[12]),
+	.X(EE4END_i[12])
+	);
+
+	my_buf EE4END_inbuf_9 (
+	.A(EE4END[13]),
+	.X(EE4END_i[13])
+	);
+
+	my_buf EE4END_inbuf_10 (
+	.A(EE4END[14]),
+	.X(EE4END_i[14])
+	);
+
+	my_buf EE4END_inbuf_11 (
+	.A(EE4END[15]),
+	.X(EE4END_i[15])
+	);
+
+	my_buf EE4BEG_outbuf_0 (
+	.A(EE4BEG_i[0]),
+	.X(EE4BEG[0])
+	);
+
+	my_buf EE4BEG_outbuf_1 (
+	.A(EE4BEG_i[1]),
+	.X(EE4BEG[1])
+	);
+
+	my_buf EE4BEG_outbuf_2 (
+	.A(EE4BEG_i[2]),
+	.X(EE4BEG[2])
+	);
+
+	my_buf EE4BEG_outbuf_3 (
+	.A(EE4BEG_i[3]),
+	.X(EE4BEG[3])
+	);
+
+	my_buf EE4BEG_outbuf_4 (
+	.A(EE4BEG_i[4]),
+	.X(EE4BEG[4])
+	);
+
+	my_buf EE4BEG_outbuf_5 (
+	.A(EE4BEG_i[5]),
+	.X(EE4BEG[5])
+	);
+
+	my_buf EE4BEG_outbuf_6 (
+	.A(EE4BEG_i[6]),
+	.X(EE4BEG[6])
+	);
+
+	my_buf EE4BEG_outbuf_7 (
+	.A(EE4BEG_i[7]),
+	.X(EE4BEG[7])
+	);
+
+	my_buf EE4BEG_outbuf_8 (
+	.A(EE4BEG_i[8]),
+	.X(EE4BEG[8])
+	);
+
+	my_buf EE4BEG_outbuf_9 (
+	.A(EE4BEG_i[9]),
+	.X(EE4BEG[9])
+	);
+
+	my_buf EE4BEG_outbuf_10 (
+	.A(EE4BEG_i[10]),
+	.X(EE4BEG[10])
+	);
+
+	my_buf EE4BEG_outbuf_11 (
+	.A(EE4BEG_i[11]),
+	.X(EE4BEG[11])
+	);
+
+	wire [11:0] E6END_i;
+	wire [9:0] E6BEG_i;
+	assign E6BEG_i[11-2:0] = E6END_i[11:2];
+
+	my_buf E6END_inbuf_0 (
+	.A(E6END[2]),
+	.X(E6END_i[2])
+	);
+
+	my_buf E6END_inbuf_1 (
+	.A(E6END[3]),
+	.X(E6END_i[3])
+	);
+
+	my_buf E6END_inbuf_2 (
+	.A(E6END[4]),
+	.X(E6END_i[4])
+	);
+
+	my_buf E6END_inbuf_3 (
+	.A(E6END[5]),
+	.X(E6END_i[5])
+	);
+
+	my_buf E6END_inbuf_4 (
+	.A(E6END[6]),
+	.X(E6END_i[6])
+	);
+
+	my_buf E6END_inbuf_5 (
+	.A(E6END[7]),
+	.X(E6END_i[7])
+	);
+
+	my_buf E6END_inbuf_6 (
+	.A(E6END[8]),
+	.X(E6END_i[8])
+	);
+
+	my_buf E6END_inbuf_7 (
+	.A(E6END[9]),
+	.X(E6END_i[9])
+	);
+
+	my_buf E6END_inbuf_8 (
+	.A(E6END[10]),
+	.X(E6END_i[10])
+	);
+
+	my_buf E6END_inbuf_9 (
+	.A(E6END[11]),
+	.X(E6END_i[11])
+	);
+
+	my_buf E6BEG_outbuf_0 (
+	.A(E6BEG_i[0]),
+	.X(E6BEG[0])
+	);
+
+	my_buf E6BEG_outbuf_1 (
+	.A(E6BEG_i[1]),
+	.X(E6BEG[1])
+	);
+
+	my_buf E6BEG_outbuf_2 (
+	.A(E6BEG_i[2]),
+	.X(E6BEG[2])
+	);
+
+	my_buf E6BEG_outbuf_3 (
+	.A(E6BEG_i[3]),
+	.X(E6BEG[3])
+	);
+
+	my_buf E6BEG_outbuf_4 (
+	.A(E6BEG_i[4]),
+	.X(E6BEG[4])
+	);
+
+	my_buf E6BEG_outbuf_5 (
+	.A(E6BEG_i[5]),
+	.X(E6BEG[5])
+	);
+
+	my_buf E6BEG_outbuf_6 (
+	.A(E6BEG_i[6]),
+	.X(E6BEG[6])
+	);
+
+	my_buf E6BEG_outbuf_7 (
+	.A(E6BEG_i[7]),
+	.X(E6BEG[7])
+	);
+
+	my_buf E6BEG_outbuf_8 (
+	.A(E6BEG_i[8]),
+	.X(E6BEG[8])
+	);
+
+	my_buf E6BEG_outbuf_9 (
+	.A(E6BEG_i[9]),
+	.X(E6BEG[9])
+	);
+
+	wire [15:0] S4END_i;
+	wire [11:0] S4BEG_i;
+	assign S4BEG_i[15-4:0] = S4END_i[15:4];
+
+	my_buf S4END_inbuf_0 (
+	.A(S4END[4]),
+	.X(S4END_i[4])
+	);
+
+	my_buf S4END_inbuf_1 (
+	.A(S4END[5]),
+	.X(S4END_i[5])
+	);
+
+	my_buf S4END_inbuf_2 (
+	.A(S4END[6]),
+	.X(S4END_i[6])
+	);
+
+	my_buf S4END_inbuf_3 (
+	.A(S4END[7]),
+	.X(S4END_i[7])
+	);
+
+	my_buf S4END_inbuf_4 (
+	.A(S4END[8]),
+	.X(S4END_i[8])
+	);
+
+	my_buf S4END_inbuf_5 (
+	.A(S4END[9]),
+	.X(S4END_i[9])
+	);
+
+	my_buf S4END_inbuf_6 (
+	.A(S4END[10]),
+	.X(S4END_i[10])
+	);
+
+	my_buf S4END_inbuf_7 (
+	.A(S4END[11]),
+	.X(S4END_i[11])
+	);
+
+	my_buf S4END_inbuf_8 (
+	.A(S4END[12]),
+	.X(S4END_i[12])
+	);
+
+	my_buf S4END_inbuf_9 (
+	.A(S4END[13]),
+	.X(S4END_i[13])
+	);
+
+	my_buf S4END_inbuf_10 (
+	.A(S4END[14]),
+	.X(S4END_i[14])
+	);
+
+	my_buf S4END_inbuf_11 (
+	.A(S4END[15]),
+	.X(S4END_i[15])
+	);
+
+	my_buf S4BEG_outbuf_0 (
+	.A(S4BEG_i[0]),
+	.X(S4BEG[0])
+	);
+
+	my_buf S4BEG_outbuf_1 (
+	.A(S4BEG_i[1]),
+	.X(S4BEG[1])
+	);
+
+	my_buf S4BEG_outbuf_2 (
+	.A(S4BEG_i[2]),
+	.X(S4BEG[2])
+	);
+
+	my_buf S4BEG_outbuf_3 (
+	.A(S4BEG_i[3]),
+	.X(S4BEG[3])
+	);
+
+	my_buf S4BEG_outbuf_4 (
+	.A(S4BEG_i[4]),
+	.X(S4BEG[4])
+	);
+
+	my_buf S4BEG_outbuf_5 (
+	.A(S4BEG_i[5]),
+	.X(S4BEG[5])
+	);
+
+	my_buf S4BEG_outbuf_6 (
+	.A(S4BEG_i[6]),
+	.X(S4BEG[6])
+	);
+
+	my_buf S4BEG_outbuf_7 (
+	.A(S4BEG_i[7]),
+	.X(S4BEG[7])
+	);
+
+	my_buf S4BEG_outbuf_8 (
+	.A(S4BEG_i[8]),
+	.X(S4BEG[8])
+	);
+
+	my_buf S4BEG_outbuf_9 (
+	.A(S4BEG_i[9]),
+	.X(S4BEG[9])
+	);
+
+	my_buf S4BEG_outbuf_10 (
+	.A(S4BEG_i[10]),
+	.X(S4BEG[10])
+	);
+
+	my_buf S4BEG_outbuf_11 (
+	.A(S4BEG_i[11]),
+	.X(S4BEG[11])
+	);
+
+	wire [15:0] SS4END_i;
+	wire [11:0] SS4BEG_i;
+	assign SS4BEG_i[15-4:0] = SS4END_i[15:4];
+
+	my_buf SS4END_inbuf_0 (
+	.A(SS4END[4]),
+	.X(SS4END_i[4])
+	);
+
+	my_buf SS4END_inbuf_1 (
+	.A(SS4END[5]),
+	.X(SS4END_i[5])
+	);
+
+	my_buf SS4END_inbuf_2 (
+	.A(SS4END[6]),
+	.X(SS4END_i[6])
+	);
+
+	my_buf SS4END_inbuf_3 (
+	.A(SS4END[7]),
+	.X(SS4END_i[7])
+	);
+
+	my_buf SS4END_inbuf_4 (
+	.A(SS4END[8]),
+	.X(SS4END_i[8])
+	);
+
+	my_buf SS4END_inbuf_5 (
+	.A(SS4END[9]),
+	.X(SS4END_i[9])
+	);
+
+	my_buf SS4END_inbuf_6 (
+	.A(SS4END[10]),
+	.X(SS4END_i[10])
+	);
+
+	my_buf SS4END_inbuf_7 (
+	.A(SS4END[11]),
+	.X(SS4END_i[11])
+	);
+
+	my_buf SS4END_inbuf_8 (
+	.A(SS4END[12]),
+	.X(SS4END_i[12])
+	);
+
+	my_buf SS4END_inbuf_9 (
+	.A(SS4END[13]),
+	.X(SS4END_i[13])
+	);
+
+	my_buf SS4END_inbuf_10 (
+	.A(SS4END[14]),
+	.X(SS4END_i[14])
+	);
+
+	my_buf SS4END_inbuf_11 (
+	.A(SS4END[15]),
+	.X(SS4END_i[15])
+	);
+
+	my_buf SS4BEG_outbuf_0 (
+	.A(SS4BEG_i[0]),
+	.X(SS4BEG[0])
+	);
+
+	my_buf SS4BEG_outbuf_1 (
+	.A(SS4BEG_i[1]),
+	.X(SS4BEG[1])
+	);
+
+	my_buf SS4BEG_outbuf_2 (
+	.A(SS4BEG_i[2]),
+	.X(SS4BEG[2])
+	);
+
+	my_buf SS4BEG_outbuf_3 (
+	.A(SS4BEG_i[3]),
+	.X(SS4BEG[3])
+	);
+
+	my_buf SS4BEG_outbuf_4 (
+	.A(SS4BEG_i[4]),
+	.X(SS4BEG[4])
+	);
+
+	my_buf SS4BEG_outbuf_5 (
+	.A(SS4BEG_i[5]),
+	.X(SS4BEG[5])
+	);
+
+	my_buf SS4BEG_outbuf_6 (
+	.A(SS4BEG_i[6]),
+	.X(SS4BEG[6])
+	);
+
+	my_buf SS4BEG_outbuf_7 (
+	.A(SS4BEG_i[7]),
+	.X(SS4BEG[7])
+	);
+
+	my_buf SS4BEG_outbuf_8 (
+	.A(SS4BEG_i[8]),
+	.X(SS4BEG[8])
+	);
+
+	my_buf SS4BEG_outbuf_9 (
+	.A(SS4BEG_i[9]),
+	.X(SS4BEG[9])
+	);
+
+	my_buf SS4BEG_outbuf_10 (
+	.A(SS4BEG_i[10]),
+	.X(SS4BEG[10])
+	);
+
+	my_buf SS4BEG_outbuf_11 (
+	.A(SS4BEG_i[11]),
+	.X(SS4BEG[11])
+	);
+
+	wire [15:0] WW4END_i;
+	wire [11:0] WW4BEG_i;
+	assign WW4BEG_i[15-4:0] = WW4END_i[15:4];
+
+	my_buf WW4END_inbuf_0 (
+	.A(WW4END[4]),
+	.X(WW4END_i[4])
+	);
+
+	my_buf WW4END_inbuf_1 (
+	.A(WW4END[5]),
+	.X(WW4END_i[5])
+	);
+
+	my_buf WW4END_inbuf_2 (
+	.A(WW4END[6]),
+	.X(WW4END_i[6])
+	);
+
+	my_buf WW4END_inbuf_3 (
+	.A(WW4END[7]),
+	.X(WW4END_i[7])
+	);
+
+	my_buf WW4END_inbuf_4 (
+	.A(WW4END[8]),
+	.X(WW4END_i[8])
+	);
+
+	my_buf WW4END_inbuf_5 (
+	.A(WW4END[9]),
+	.X(WW4END_i[9])
+	);
+
+	my_buf WW4END_inbuf_6 (
+	.A(WW4END[10]),
+	.X(WW4END_i[10])
+	);
+
+	my_buf WW4END_inbuf_7 (
+	.A(WW4END[11]),
+	.X(WW4END_i[11])
+	);
+
+	my_buf WW4END_inbuf_8 (
+	.A(WW4END[12]),
+	.X(WW4END_i[12])
+	);
+
+	my_buf WW4END_inbuf_9 (
+	.A(WW4END[13]),
+	.X(WW4END_i[13])
+	);
+
+	my_buf WW4END_inbuf_10 (
+	.A(WW4END[14]),
+	.X(WW4END_i[14])
+	);
+
+	my_buf WW4END_inbuf_11 (
+	.A(WW4END[15]),
+	.X(WW4END_i[15])
+	);
+
+	my_buf WW4BEG_outbuf_0 (
+	.A(WW4BEG_i[0]),
+	.X(WW4BEG[0])
+	);
+
+	my_buf WW4BEG_outbuf_1 (
+	.A(WW4BEG_i[1]),
+	.X(WW4BEG[1])
+	);
+
+	my_buf WW4BEG_outbuf_2 (
+	.A(WW4BEG_i[2]),
+	.X(WW4BEG[2])
+	);
+
+	my_buf WW4BEG_outbuf_3 (
+	.A(WW4BEG_i[3]),
+	.X(WW4BEG[3])
+	);
+
+	my_buf WW4BEG_outbuf_4 (
+	.A(WW4BEG_i[4]),
+	.X(WW4BEG[4])
+	);
+
+	my_buf WW4BEG_outbuf_5 (
+	.A(WW4BEG_i[5]),
+	.X(WW4BEG[5])
+	);
+
+	my_buf WW4BEG_outbuf_6 (
+	.A(WW4BEG_i[6]),
+	.X(WW4BEG[6])
+	);
+
+	my_buf WW4BEG_outbuf_7 (
+	.A(WW4BEG_i[7]),
+	.X(WW4BEG[7])
+	);
+
+	my_buf WW4BEG_outbuf_8 (
+	.A(WW4BEG_i[8]),
+	.X(WW4BEG[8])
+	);
+
+	my_buf WW4BEG_outbuf_9 (
+	.A(WW4BEG_i[9]),
+	.X(WW4BEG[9])
+	);
+
+	my_buf WW4BEG_outbuf_10 (
+	.A(WW4BEG_i[10]),
+	.X(WW4BEG[10])
+	);
+
+	my_buf WW4BEG_outbuf_11 (
+	.A(WW4BEG_i[11]),
+	.X(WW4BEG[11])
+	);
+
+	wire [11:0] W6END_i;
+	wire [9:0] W6BEG_i;
+	assign W6BEG_i[11-2:0] = W6END_i[11:2];
+
+	my_buf W6END_inbuf_0 (
+	.A(W6END[2]),
+	.X(W6END_i[2])
+	);
+
+	my_buf W6END_inbuf_1 (
+	.A(W6END[3]),
+	.X(W6END_i[3])
+	);
+
+	my_buf W6END_inbuf_2 (
+	.A(W6END[4]),
+	.X(W6END_i[4])
+	);
+
+	my_buf W6END_inbuf_3 (
+	.A(W6END[5]),
+	.X(W6END_i[5])
+	);
+
+	my_buf W6END_inbuf_4 (
+	.A(W6END[6]),
+	.X(W6END_i[6])
+	);
+
+	my_buf W6END_inbuf_5 (
+	.A(W6END[7]),
+	.X(W6END_i[7])
+	);
+
+	my_buf W6END_inbuf_6 (
+	.A(W6END[8]),
+	.X(W6END_i[8])
+	);
+
+	my_buf W6END_inbuf_7 (
+	.A(W6END[9]),
+	.X(W6END_i[9])
+	);
+
+	my_buf W6END_inbuf_8 (
+	.A(W6END[10]),
+	.X(W6END_i[10])
+	);
+
+	my_buf W6END_inbuf_9 (
+	.A(W6END[11]),
+	.X(W6END_i[11])
+	);
+
+	my_buf W6BEG_outbuf_0 (
+	.A(W6BEG_i[0]),
+	.X(W6BEG[0])
+	);
+
+	my_buf W6BEG_outbuf_1 (
+	.A(W6BEG_i[1]),
+	.X(W6BEG[1])
+	);
+
+	my_buf W6BEG_outbuf_2 (
+	.A(W6BEG_i[2]),
+	.X(W6BEG[2])
+	);
+
+	my_buf W6BEG_outbuf_3 (
+	.A(W6BEG_i[3]),
+	.X(W6BEG[3])
+	);
+
+	my_buf W6BEG_outbuf_4 (
+	.A(W6BEG_i[4]),
+	.X(W6BEG[4])
+	);
+
+	my_buf W6BEG_outbuf_5 (
+	.A(W6BEG_i[5]),
+	.X(W6BEG[5])
+	);
+
+	my_buf W6BEG_outbuf_6 (
+	.A(W6BEG_i[6]),
+	.X(W6BEG[6])
+	);
+
+	my_buf W6BEG_outbuf_7 (
+	.A(W6BEG_i[7]),
+	.X(W6BEG[7])
+	);
+
+	my_buf W6BEG_outbuf_8 (
+	.A(W6BEG_i[8]),
+	.X(W6BEG[8])
+	);
+
+	my_buf W6BEG_outbuf_9 (
+	.A(W6BEG_i[9]),
+	.X(W6BEG[9])
+	);
+
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	RegFile_ConfigMem Inst_RegFile_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	RegFile_32x4 Inst_RegFile_32x4 (
+	.D0(D0),
+	.D1(D1),
+	.D2(D2),
+	.D3(D3),
+	.W_ADR0(W_ADR0),
+	.W_ADR1(W_ADR1),
+	.W_ADR2(W_ADR2),
+	.W_ADR3(W_ADR3),
+	.W_ADR4(W_ADR4),
+	.W_en(W_en),
+	.A_ADR0(A_ADR0),
+	.A_ADR1(A_ADR1),
+	.A_ADR2(A_ADR2),
+	.A_ADR3(A_ADR3),
+	.A_ADR4(A_ADR4),
+	.B_ADR0(B_ADR0),
+	.B_ADR1(B_ADR1),
+	.B_ADR2(B_ADR2),
+	.B_ADR3(B_ADR3),
+	.B_ADR4(B_ADR4),
+	.AD0(AD0),
+	.AD1(AD1),
+	.AD2(AD2),
+	.AD3(AD3),
+	.BD0(BD0),
+	.BD1(BD1),
+	.BD2(BD2),
+	.BD3(BD3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[2-1:0])
+	);
+
+
+//switch matrix component instantiation
+	RegFile_switch_matrix Inst_RegFile_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.E1END0(E1END[0]),
+	.E1END1(E1END[1]),
+	.E1END2(E1END[2]),
+	.E1END3(E1END[3]),
+	.E2MID0(E2MID[0]),
+	.E2MID1(E2MID[1]),
+	.E2MID2(E2MID[2]),
+	.E2MID3(E2MID[3]),
+	.E2MID4(E2MID[4]),
+	.E2MID5(E2MID[5]),
+	.E2MID6(E2MID[6]),
+	.E2MID7(E2MID[7]),
+	.E2END0(E2END[0]),
+	.E2END1(E2END[1]),
+	.E2END2(E2END[2]),
+	.E2END3(E2END[3]),
+	.E2END4(E2END[4]),
+	.E2END5(E2END[5]),
+	.E2END6(E2END[6]),
+	.E2END7(E2END[7]),
+	.EE4END0(EE4END[0]),
+	.EE4END1(EE4END[1]),
+	.EE4END2(EE4END[2]),
+	.EE4END3(EE4END[3]),
+	.E6END0(E6END[0]),
+	.E6END1(E6END[1]),
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.AD0(AD0),
+	.AD1(AD1),
+	.AD2(AD2),
+	.AD3(AD3),
+	.BD0(BD0),
+	.BD1(BD1),
+	.BD2(BD2),
+	.BD3(BD3),
+	.J2MID_ABa_END0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_END1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_END2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_END3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_END0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_END1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_END2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_END3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_END0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_END1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_END2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_END3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_END0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_END1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_END2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_END3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_END0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_END1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_END2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_END3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_END0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_END1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_END2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_END3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_END0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_END1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_END2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_END3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_END0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_END1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_END2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_END3(J2MID_GHb_BEG[3]),
+	.J2END_AB_END0(J2END_AB_BEG[0]),
+	.J2END_AB_END1(J2END_AB_BEG[1]),
+	.J2END_AB_END2(J2END_AB_BEG[2]),
+	.J2END_AB_END3(J2END_AB_BEG[3]),
+	.J2END_CD_END0(J2END_CD_BEG[0]),
+	.J2END_CD_END1(J2END_CD_BEG[1]),
+	.J2END_CD_END2(J2END_CD_BEG[2]),
+	.J2END_CD_END3(J2END_CD_BEG[3]),
+	.J2END_EF_END0(J2END_EF_BEG[0]),
+	.J2END_EF_END1(J2END_EF_BEG[1]),
+	.J2END_EF_END2(J2END_EF_BEG[2]),
+	.J2END_EF_END3(J2END_EF_BEG[3]),
+	.J2END_GH_END0(J2END_GH_BEG[0]),
+	.J2END_GH_END1(J2END_GH_BEG[1]),
+	.J2END_GH_END2(J2END_GH_BEG[2]),
+	.J2END_GH_END3(J2END_GH_BEG[3]),
+	.JN2END0(JN2BEG[0]),
+	.JN2END1(JN2BEG[1]),
+	.JN2END2(JN2BEG[2]),
+	.JN2END3(JN2BEG[3]),
+	.JN2END4(JN2BEG[4]),
+	.JN2END5(JN2BEG[5]),
+	.JN2END6(JN2BEG[6]),
+	.JN2END7(JN2BEG[7]),
+	.JE2END0(JE2BEG[0]),
+	.JE2END1(JE2BEG[1]),
+	.JE2END2(JE2BEG[2]),
+	.JE2END3(JE2BEG[3]),
+	.JE2END4(JE2BEG[4]),
+	.JE2END5(JE2BEG[5]),
+	.JE2END6(JE2BEG[6]),
+	.JE2END7(JE2BEG[7]),
+	.JS2END0(JS2BEG[0]),
+	.JS2END1(JS2BEG[1]),
+	.JS2END2(JS2BEG[2]),
+	.JS2END3(JS2BEG[3]),
+	.JS2END4(JS2BEG[4]),
+	.JS2END5(JS2BEG[5]),
+	.JS2END6(JS2BEG[6]),
+	.JS2END7(JS2BEG[7]),
+	.JW2END0(JW2BEG[0]),
+	.JW2END1(JW2BEG[1]),
+	.JW2END2(JW2BEG[2]),
+	.JW2END3(JW2BEG[3]),
+	.JW2END4(JW2BEG[4]),
+	.JW2END5(JW2BEG[5]),
+	.JW2END6(JW2BEG[6]),
+	.JW2END7(JW2BEG[7]),
+	.J_l_AB_END0(J_l_AB_BEG[0]),
+	.J_l_AB_END1(J_l_AB_BEG[1]),
+	.J_l_AB_END2(J_l_AB_BEG[2]),
+	.J_l_AB_END3(J_l_AB_BEG[3]),
+	.J_l_CD_END0(J_l_CD_BEG[0]),
+	.J_l_CD_END1(J_l_CD_BEG[1]),
+	.J_l_CD_END2(J_l_CD_BEG[2]),
+	.J_l_CD_END3(J_l_CD_BEG[3]),
+	.J_l_EF_END0(J_l_EF_BEG[0]),
+	.J_l_EF_END1(J_l_EF_BEG[1]),
+	.J_l_EF_END2(J_l_EF_BEG[2]),
+	.J_l_EF_END3(J_l_EF_BEG[3]),
+	.J_l_GH_END0(J_l_GH_BEG[0]),
+	.J_l_GH_END1(J_l_GH_BEG[1]),
+	.J_l_GH_END2(J_l_GH_BEG[2]),
+	.J_l_GH_END3(J_l_GH_BEG[3]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[12]),
+	.N4BEG1(N4BEG[13]),
+	.N4BEG2(N4BEG[14]),
+	.N4BEG3(N4BEG[15]),
+	.NN4BEG0(NN4BEG[12]),
+	.NN4BEG1(NN4BEG[13]),
+	.NN4BEG2(NN4BEG[14]),
+	.NN4BEG3(NN4BEG[15]),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[12]),
+	.EE4BEG1(EE4BEG[13]),
+	.EE4BEG2(EE4BEG[14]),
+	.EE4BEG3(EE4BEG[15]),
+	.E6BEG0(E6BEG[10]),
+	.E6BEG1(E6BEG[11]),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[12]),
+	.S4BEG1(S4BEG[13]),
+	.S4BEG2(S4BEG[14]),
+	.S4BEG3(S4BEG[15]),
+	.SS4BEG0(SS4BEG[12]),
+	.SS4BEG1(SS4BEG[13]),
+	.SS4BEG2(SS4BEG[14]),
+	.SS4BEG3(SS4BEG[15]),
+	.W1BEG0(W1BEG[0]),
+	.W1BEG1(W1BEG[1]),
+	.W1BEG2(W1BEG[2]),
+	.W1BEG3(W1BEG[3]),
+	.W2BEG0(W2BEG[0]),
+	.W2BEG1(W2BEG[1]),
+	.W2BEG2(W2BEG[2]),
+	.W2BEG3(W2BEG[3]),
+	.W2BEG4(W2BEG[4]),
+	.W2BEG5(W2BEG[5]),
+	.W2BEG6(W2BEG[6]),
+	.W2BEG7(W2BEG[7]),
+	.W2BEGb0(W2BEGb[0]),
+	.W2BEGb1(W2BEGb[1]),
+	.W2BEGb2(W2BEGb[2]),
+	.W2BEGb3(W2BEGb[3]),
+	.W2BEGb4(W2BEGb[4]),
+	.W2BEGb5(W2BEGb[5]),
+	.W2BEGb6(W2BEGb[6]),
+	.W2BEGb7(W2BEGb[7]),
+	.WW4BEG0(WW4BEG[12]),
+	.WW4BEG1(WW4BEG[13]),
+	.WW4BEG2(WW4BEG[14]),
+	.WW4BEG3(WW4BEG[15]),
+	.W6BEG0(W6BEG[10]),
+	.W6BEG1(W6BEG[11]),
+	.D0(D0),
+	.D1(D1),
+	.D2(D2),
+	.D3(D3),
+	.W_ADR0(W_ADR0),
+	.W_ADR1(W_ADR1),
+	.W_ADR2(W_ADR2),
+	.W_ADR3(W_ADR3),
+	.W_ADR4(W_ADR4),
+	.W_en(W_en),
+	.A_ADR0(A_ADR0),
+	.A_ADR1(A_ADR1),
+	.A_ADR2(A_ADR2),
+	.A_ADR3(A_ADR3),
+	.A_ADR4(A_ADR4),
+	.B_ADR0(B_ADR0),
+	.B_ADR1(B_ADR1),
+	.B_ADR2(B_ADR2),
+	.B_ADR3(B_ADR3),
+	.B_ADR4(B_ADR4),
+	.J2MID_ABa_BEG0(J2MID_ABa_BEG[0]),
+	.J2MID_ABa_BEG1(J2MID_ABa_BEG[1]),
+	.J2MID_ABa_BEG2(J2MID_ABa_BEG[2]),
+	.J2MID_ABa_BEG3(J2MID_ABa_BEG[3]),
+	.J2MID_CDa_BEG0(J2MID_CDa_BEG[0]),
+	.J2MID_CDa_BEG1(J2MID_CDa_BEG[1]),
+	.J2MID_CDa_BEG2(J2MID_CDa_BEG[2]),
+	.J2MID_CDa_BEG3(J2MID_CDa_BEG[3]),
+	.J2MID_EFa_BEG0(J2MID_EFa_BEG[0]),
+	.J2MID_EFa_BEG1(J2MID_EFa_BEG[1]),
+	.J2MID_EFa_BEG2(J2MID_EFa_BEG[2]),
+	.J2MID_EFa_BEG3(J2MID_EFa_BEG[3]),
+	.J2MID_GHa_BEG0(J2MID_GHa_BEG[0]),
+	.J2MID_GHa_BEG1(J2MID_GHa_BEG[1]),
+	.J2MID_GHa_BEG2(J2MID_GHa_BEG[2]),
+	.J2MID_GHa_BEG3(J2MID_GHa_BEG[3]),
+	.J2MID_ABb_BEG0(J2MID_ABb_BEG[0]),
+	.J2MID_ABb_BEG1(J2MID_ABb_BEG[1]),
+	.J2MID_ABb_BEG2(J2MID_ABb_BEG[2]),
+	.J2MID_ABb_BEG3(J2MID_ABb_BEG[3]),
+	.J2MID_CDb_BEG0(J2MID_CDb_BEG[0]),
+	.J2MID_CDb_BEG1(J2MID_CDb_BEG[1]),
+	.J2MID_CDb_BEG2(J2MID_CDb_BEG[2]),
+	.J2MID_CDb_BEG3(J2MID_CDb_BEG[3]),
+	.J2MID_EFb_BEG0(J2MID_EFb_BEG[0]),
+	.J2MID_EFb_BEG1(J2MID_EFb_BEG[1]),
+	.J2MID_EFb_BEG2(J2MID_EFb_BEG[2]),
+	.J2MID_EFb_BEG3(J2MID_EFb_BEG[3]),
+	.J2MID_GHb_BEG0(J2MID_GHb_BEG[0]),
+	.J2MID_GHb_BEG1(J2MID_GHb_BEG[1]),
+	.J2MID_GHb_BEG2(J2MID_GHb_BEG[2]),
+	.J2MID_GHb_BEG3(J2MID_GHb_BEG[3]),
+	.J2END_AB_BEG0(J2END_AB_BEG[0]),
+	.J2END_AB_BEG1(J2END_AB_BEG[1]),
+	.J2END_AB_BEG2(J2END_AB_BEG[2]),
+	.J2END_AB_BEG3(J2END_AB_BEG[3]),
+	.J2END_CD_BEG0(J2END_CD_BEG[0]),
+	.J2END_CD_BEG1(J2END_CD_BEG[1]),
+	.J2END_CD_BEG2(J2END_CD_BEG[2]),
+	.J2END_CD_BEG3(J2END_CD_BEG[3]),
+	.J2END_EF_BEG0(J2END_EF_BEG[0]),
+	.J2END_EF_BEG1(J2END_EF_BEG[1]),
+	.J2END_EF_BEG2(J2END_EF_BEG[2]),
+	.J2END_EF_BEG3(J2END_EF_BEG[3]),
+	.J2END_GH_BEG0(J2END_GH_BEG[0]),
+	.J2END_GH_BEG1(J2END_GH_BEG[1]),
+	.J2END_GH_BEG2(J2END_GH_BEG[2]),
+	.J2END_GH_BEG3(J2END_GH_BEG[3]),
+	.JN2BEG0(JN2BEG[0]),
+	.JN2BEG1(JN2BEG[1]),
+	.JN2BEG2(JN2BEG[2]),
+	.JN2BEG3(JN2BEG[3]),
+	.JN2BEG4(JN2BEG[4]),
+	.JN2BEG5(JN2BEG[5]),
+	.JN2BEG6(JN2BEG[6]),
+	.JN2BEG7(JN2BEG[7]),
+	.JE2BEG0(JE2BEG[0]),
+	.JE2BEG1(JE2BEG[1]),
+	.JE2BEG2(JE2BEG[2]),
+	.JE2BEG3(JE2BEG[3]),
+	.JE2BEG4(JE2BEG[4]),
+	.JE2BEG5(JE2BEG[5]),
+	.JE2BEG6(JE2BEG[6]),
+	.JE2BEG7(JE2BEG[7]),
+	.JS2BEG0(JS2BEG[0]),
+	.JS2BEG1(JS2BEG[1]),
+	.JS2BEG2(JS2BEG[2]),
+	.JS2BEG3(JS2BEG[3]),
+	.JS2BEG4(JS2BEG[4]),
+	.JS2BEG5(JS2BEG[5]),
+	.JS2BEG6(JS2BEG[6]),
+	.JS2BEG7(JS2BEG[7]),
+	.JW2BEG0(JW2BEG[0]),
+	.JW2BEG1(JW2BEG[1]),
+	.JW2BEG2(JW2BEG[2]),
+	.JW2BEG3(JW2BEG[3]),
+	.JW2BEG4(JW2BEG[4]),
+	.JW2BEG5(JW2BEG[5]),
+	.JW2BEG6(JW2BEG[6]),
+	.JW2BEG7(JW2BEG[7]),
+	.J_l_AB_BEG0(J_l_AB_BEG[0]),
+	.J_l_AB_BEG1(J_l_AB_BEG[1]),
+	.J_l_AB_BEG2(J_l_AB_BEG[2]),
+	.J_l_AB_BEG3(J_l_AB_BEG[3]),
+	.J_l_CD_BEG0(J_l_CD_BEG[0]),
+	.J_l_CD_BEG1(J_l_CD_BEG[1]),
+	.J_l_CD_BEG2(J_l_CD_BEG[2]),
+	.J_l_CD_BEG3(J_l_CD_BEG[3]),
+	.J_l_EF_BEG0(J_l_EF_BEG[0]),
+	.J_l_EF_BEG1(J_l_EF_BEG[1]),
+	.J_l_EF_BEG2(J_l_EF_BEG[2]),
+	.J_l_EF_BEG3(J_l_EF_BEG[3]),
+	.J_l_GH_BEG0(J_l_GH_BEG[0]),
+	.J_l_GH_BEG1(J_l_GH_BEG[1]),
+	.J_l_GH_BEG2(J_l_GH_BEG[2]),
+	.J_l_GH_BEG3(J_l_GH_BEG[3]),
+	.ConfigBits(ConfigBits[414-1:2]),
+	.ConfigBits_N(ConfigBits_N[414-1:2])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_DSP_switch_matrix.v b/verilog/rtl/eFPGA_core/S_term_DSP_switch_matrix.v
new file mode 100644
index 0000000..312527e
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_DSP_switch_matrix.v
@@ -0,0 +1,297 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module S_term_DSP_switch_matrix (S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, S4END4, S4END5, S4END6, S4END7, S4END8, S4END9, S4END10, S4END11, S4END12, S4END13, S4END14, S4END15, SS4END0, SS4END1, SS4END2, SS4END3, SS4END4, SS4END5, SS4END6, SS4END7, SS4END8, SS4END9, SS4END10, SS4END11, SS4END12, SS4END13, SS4END14, SS4END15, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, N4BEG4, N4BEG5, N4BEG6, N4BEG7, N4BEG8, N4BEG9, N4BEG10, N4BEG11, N4BEG12, N4BEG13, N4BEG14, N4BEG15, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, NN4BEG4, NN4BEG5, NN4BEG6, NN4BEG7, NN4BEG8, NN4BEG9, NN4BEG10, NN4BEG11, NN4BEG12, NN4BEG13, NN4BEG14, NN4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input S4END4;
+	input S4END5;
+	input S4END6;
+	input S4END7;
+	input S4END8;
+	input S4END9;
+	input S4END10;
+	input S4END11;
+	input S4END12;
+	input S4END13;
+	input S4END14;
+	input S4END15;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input SS4END4;
+	input SS4END5;
+	input SS4END6;
+	input SS4END7;
+	input SS4END8;
+	input SS4END9;
+	input SS4END10;
+	input SS4END11;
+	input SS4END12;
+	input SS4END13;
+	input SS4END14;
+	input SS4END15;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output N4BEG4;
+	output N4BEG5;
+	output N4BEG6;
+	output N4BEG7;
+	output N4BEG8;
+	output N4BEG9;
+	output N4BEG10;
+	output N4BEG11;
+	output N4BEG12;
+	output N4BEG13;
+	output N4BEG14;
+	output N4BEG15;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output NN4BEG4;
+	output NN4BEG5;
+	output NN4BEG6;
+	output NN4BEG7;
+	output NN4BEG8;
+	output NN4BEG9;
+	output NN4BEG10;
+	output NN4BEG11;
+	output NN4BEG12;
+	output NN4BEG13;
+	output NN4BEG14;
+	output NN4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] N1BEG0_input;
+	wire [1-1:0] N1BEG1_input;
+	wire [1-1:0] N1BEG2_input;
+	wire [1-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [1-1:0] N4BEG0_input;
+	wire [1-1:0] N4BEG1_input;
+	wire [1-1:0] N4BEG2_input;
+	wire [1-1:0] N4BEG3_input;
+	wire [1-1:0] N4BEG4_input;
+	wire [1-1:0] N4BEG5_input;
+	wire [1-1:0] N4BEG6_input;
+	wire [1-1:0] N4BEG7_input;
+	wire [1-1:0] N4BEG8_input;
+	wire [1-1:0] N4BEG9_input;
+	wire [1-1:0] N4BEG10_input;
+	wire [1-1:0] N4BEG11_input;
+	wire [1-1:0] N4BEG12_input;
+	wire [1-1:0] N4BEG13_input;
+	wire [1-1:0] N4BEG14_input;
+	wire [1-1:0] N4BEG15_input;
+	wire [1-1:0] NN4BEG0_input;
+	wire [1-1:0] NN4BEG1_input;
+	wire [1-1:0] NN4BEG2_input;
+	wire [1-1:0] NN4BEG3_input;
+	wire [1-1:0] NN4BEG4_input;
+	wire [1-1:0] NN4BEG5_input;
+	wire [1-1:0] NN4BEG6_input;
+	wire [1-1:0] NN4BEG7_input;
+	wire [1-1:0] NN4BEG8_input;
+	wire [1-1:0] NN4BEG9_input;
+	wire [1-1:0] NN4BEG10_input;
+	wire [1-1:0] NN4BEG11_input;
+	wire [1-1:0] NN4BEG12_input;
+	wire [1-1:0] NN4BEG13_input;
+	wire [1-1:0] NN4BEG14_input;
+	wire [1-1:0] NN4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-1
+	assign N1BEG0 = S1END3;
+// switch matrix multiplexer  N1BEG1 		MUX-1
+	assign N1BEG1 = S1END2;
+// switch matrix multiplexer  N1BEG2 		MUX-1
+	assign N1BEG2 = S1END1;
+// switch matrix multiplexer  N1BEG3 		MUX-1
+	assign N1BEG3 = S1END0;
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = S2MID7;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = S2MID6;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = S2MID5;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = S2MID4;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = S2MID3;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = S2MID2;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = S2MID1;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = S2MID0;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = S2END7;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = S2END6;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = S2END5;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = S2END4;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = S2END3;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = S2END2;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = S2END1;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = S2END0;
+// switch matrix multiplexer  N4BEG0 		MUX-1
+	assign N4BEG0 = S4END15;
+// switch matrix multiplexer  N4BEG1 		MUX-1
+	assign N4BEG1 = S4END14;
+// switch matrix multiplexer  N4BEG2 		MUX-1
+	assign N4BEG2 = S4END13;
+// switch matrix multiplexer  N4BEG3 		MUX-1
+	assign N4BEG3 = S4END12;
+// switch matrix multiplexer  N4BEG4 		MUX-1
+	assign N4BEG4 = S4END11;
+// switch matrix multiplexer  N4BEG5 		MUX-1
+	assign N4BEG5 = S4END10;
+// switch matrix multiplexer  N4BEG6 		MUX-1
+	assign N4BEG6 = S4END9;
+// switch matrix multiplexer  N4BEG7 		MUX-1
+	assign N4BEG7 = S4END8;
+// switch matrix multiplexer  N4BEG8 		MUX-1
+	assign N4BEG8 = S4END7;
+// switch matrix multiplexer  N4BEG9 		MUX-1
+	assign N4BEG9 = S4END6;
+// switch matrix multiplexer  N4BEG10 		MUX-1
+	assign N4BEG10 = S4END5;
+// switch matrix multiplexer  N4BEG11 		MUX-1
+	assign N4BEG11 = S4END4;
+// switch matrix multiplexer  N4BEG12 		MUX-1
+	assign N4BEG12 = S4END3;
+// switch matrix multiplexer  N4BEG13 		MUX-1
+	assign N4BEG13 = S4END2;
+// switch matrix multiplexer  N4BEG14 		MUX-1
+	assign N4BEG14 = S4END1;
+// switch matrix multiplexer  N4BEG15 		MUX-1
+	assign N4BEG15 = S4END0;
+// switch matrix multiplexer  NN4BEG0 		MUX-1
+	assign NN4BEG0 = SS4END15;
+// switch matrix multiplexer  NN4BEG1 		MUX-1
+	assign NN4BEG1 = SS4END14;
+// switch matrix multiplexer  NN4BEG2 		MUX-1
+	assign NN4BEG2 = SS4END13;
+// switch matrix multiplexer  NN4BEG3 		MUX-1
+	assign NN4BEG3 = SS4END12;
+// switch matrix multiplexer  NN4BEG4 		MUX-1
+	assign NN4BEG4 = SS4END11;
+// switch matrix multiplexer  NN4BEG5 		MUX-1
+	assign NN4BEG5 = SS4END10;
+// switch matrix multiplexer  NN4BEG6 		MUX-1
+	assign NN4BEG6 = SS4END9;
+// switch matrix multiplexer  NN4BEG7 		MUX-1
+	assign NN4BEG7 = SS4END8;
+// switch matrix multiplexer  NN4BEG8 		MUX-1
+	assign NN4BEG8 = SS4END7;
+// switch matrix multiplexer  NN4BEG9 		MUX-1
+	assign NN4BEG9 = SS4END6;
+// switch matrix multiplexer  NN4BEG10 		MUX-1
+	assign NN4BEG10 = SS4END5;
+// switch matrix multiplexer  NN4BEG11 		MUX-1
+	assign NN4BEG11 = SS4END4;
+// switch matrix multiplexer  NN4BEG12 		MUX-1
+	assign NN4BEG12 = SS4END3;
+// switch matrix multiplexer  NN4BEG13 		MUX-1
+	assign NN4BEG13 = SS4END2;
+// switch matrix multiplexer  NN4BEG14 		MUX-1
+	assign NN4BEG14 = SS4END1;
+// switch matrix multiplexer  NN4BEG15 		MUX-1
+	assign NN4BEG15 = SS4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_DSP_tile.v b/verilog/rtl/eFPGA_core/S_term_DSP_tile.v
new file mode 100644
index 0000000..19324e2
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_DSP_tile.v
@@ -0,0 +1,362 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module S_term_DSP (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:NULL  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:NULL  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:NULL  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:NULL  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NULL  
+	//  EAST
+	//  SOUTH
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:SS4END  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	S_term_DSP_switch_matrix Inst_S_term_DSP_switch_matrix (
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.S4END4(S4END[4]),
+	.S4END5(S4END[5]),
+	.S4END6(S4END[6]),
+	.S4END7(S4END[7]),
+	.S4END8(S4END[8]),
+	.S4END9(S4END[9]),
+	.S4END10(S4END[10]),
+	.S4END11(S4END[11]),
+	.S4END12(S4END[12]),
+	.S4END13(S4END[13]),
+	.S4END14(S4END[14]),
+	.S4END15(S4END[15]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.SS4END4(SS4END[4]),
+	.SS4END5(SS4END[5]),
+	.SS4END6(SS4END[6]),
+	.SS4END7(SS4END[7]),
+	.SS4END8(SS4END[8]),
+	.SS4END9(SS4END[9]),
+	.SS4END10(SS4END[10]),
+	.SS4END11(SS4END[11]),
+	.SS4END12(SS4END[12]),
+	.SS4END13(SS4END[13]),
+	.SS4END14(SS4END[14]),
+	.SS4END15(SS4END[15]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[0]),
+	.N4BEG1(N4BEG[1]),
+	.N4BEG2(N4BEG[2]),
+	.N4BEG3(N4BEG[3]),
+	.N4BEG4(N4BEG[4]),
+	.N4BEG5(N4BEG[5]),
+	.N4BEG6(N4BEG[6]),
+	.N4BEG7(N4BEG[7]),
+	.N4BEG8(N4BEG[8]),
+	.N4BEG9(N4BEG[9]),
+	.N4BEG10(N4BEG[10]),
+	.N4BEG11(N4BEG[11]),
+	.N4BEG12(N4BEG[12]),
+	.N4BEG13(N4BEG[13]),
+	.N4BEG14(N4BEG[14]),
+	.N4BEG15(N4BEG[15]),
+	.NN4BEG0(NN4BEG[0]),
+	.NN4BEG1(NN4BEG[1]),
+	.NN4BEG2(NN4BEG[2]),
+	.NN4BEG3(NN4BEG[3]),
+	.NN4BEG4(NN4BEG[4]),
+	.NN4BEG5(NN4BEG[5]),
+	.NN4BEG6(NN4BEG[6]),
+	.NN4BEG7(NN4BEG[7]),
+	.NN4BEG8(NN4BEG[8]),
+	.NN4BEG9(NN4BEG[9]),
+	.NN4BEG10(NN4BEG[10]),
+	.NN4BEG11(NN4BEG[11]),
+	.NN4BEG12(NN4BEG[12]),
+	.NN4BEG13(NN4BEG[13]),
+	.NN4BEG14(NN4BEG[14]),
+	.NN4BEG15(NN4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_RAM_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/S_term_RAM_IO_switch_matrix.v
new file mode 100644
index 0000000..8af861b
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_RAM_IO_switch_matrix.v
@@ -0,0 +1,217 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module S_term_RAM_IO_switch_matrix (S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, S4END4, S4END5, S4END6, S4END7, S4END8, S4END9, S4END10, S4END11, S4END12, S4END13, S4END14, S4END15, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, N4BEG4, N4BEG5, N4BEG6, N4BEG7, N4BEG8, N4BEG9, N4BEG10, N4BEG11, N4BEG12, N4BEG13, N4BEG14, N4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input S4END4;
+	input S4END5;
+	input S4END6;
+	input S4END7;
+	input S4END8;
+	input S4END9;
+	input S4END10;
+	input S4END11;
+	input S4END12;
+	input S4END13;
+	input S4END14;
+	input S4END15;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output N4BEG4;
+	output N4BEG5;
+	output N4BEG6;
+	output N4BEG7;
+	output N4BEG8;
+	output N4BEG9;
+	output N4BEG10;
+	output N4BEG11;
+	output N4BEG12;
+	output N4BEG13;
+	output N4BEG14;
+	output N4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] N1BEG0_input;
+	wire [1-1:0] N1BEG1_input;
+	wire [1-1:0] N1BEG2_input;
+	wire [1-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [1-1:0] N4BEG0_input;
+	wire [1-1:0] N4BEG1_input;
+	wire [1-1:0] N4BEG2_input;
+	wire [1-1:0] N4BEG3_input;
+	wire [1-1:0] N4BEG4_input;
+	wire [1-1:0] N4BEG5_input;
+	wire [1-1:0] N4BEG6_input;
+	wire [1-1:0] N4BEG7_input;
+	wire [1-1:0] N4BEG8_input;
+	wire [1-1:0] N4BEG9_input;
+	wire [1-1:0] N4BEG10_input;
+	wire [1-1:0] N4BEG11_input;
+	wire [1-1:0] N4BEG12_input;
+	wire [1-1:0] N4BEG13_input;
+	wire [1-1:0] N4BEG14_input;
+	wire [1-1:0] N4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-1
+	assign N1BEG0 = S1END3;
+// switch matrix multiplexer  N1BEG1 		MUX-1
+	assign N1BEG1 = S1END2;
+// switch matrix multiplexer  N1BEG2 		MUX-1
+	assign N1BEG2 = S1END1;
+// switch matrix multiplexer  N1BEG3 		MUX-1
+	assign N1BEG3 = S1END0;
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = S2MID7;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = S2MID6;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = S2MID5;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = S2MID4;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = S2MID3;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = S2MID2;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = S2MID1;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = S2MID0;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = S2END7;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = S2END6;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = S2END5;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = S2END4;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = S2END3;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = S2END2;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = S2END1;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = S2END0;
+// switch matrix multiplexer  N4BEG0 		MUX-1
+	assign N4BEG0 = S4END15;
+// switch matrix multiplexer  N4BEG1 		MUX-1
+	assign N4BEG1 = S4END14;
+// switch matrix multiplexer  N4BEG2 		MUX-1
+	assign N4BEG2 = S4END13;
+// switch matrix multiplexer  N4BEG3 		MUX-1
+	assign N4BEG3 = S4END12;
+// switch matrix multiplexer  N4BEG4 		MUX-1
+	assign N4BEG4 = S4END11;
+// switch matrix multiplexer  N4BEG5 		MUX-1
+	assign N4BEG5 = S4END10;
+// switch matrix multiplexer  N4BEG6 		MUX-1
+	assign N4BEG6 = S4END9;
+// switch matrix multiplexer  N4BEG7 		MUX-1
+	assign N4BEG7 = S4END8;
+// switch matrix multiplexer  N4BEG8 		MUX-1
+	assign N4BEG8 = S4END7;
+// switch matrix multiplexer  N4BEG9 		MUX-1
+	assign N4BEG9 = S4END6;
+// switch matrix multiplexer  N4BEG10 		MUX-1
+	assign N4BEG10 = S4END5;
+// switch matrix multiplexer  N4BEG11 		MUX-1
+	assign N4BEG11 = S4END4;
+// switch matrix multiplexer  N4BEG12 		MUX-1
+	assign N4BEG12 = S4END3;
+// switch matrix multiplexer  N4BEG13 		MUX-1
+	assign N4BEG13 = S4END2;
+// switch matrix multiplexer  N4BEG14 		MUX-1
+	assign N4BEG14 = S4END1;
+// switch matrix multiplexer  N4BEG15 		MUX-1
+	assign N4BEG15 = S4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_RAM_IO_tile.v b/verilog/rtl/eFPGA_core/S_term_RAM_IO_tile.v
new file mode 100644
index 0000000..3660cce
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_RAM_IO_tile.v
@@ -0,0 +1,328 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module S_term_RAM_IO (N1BEG, N2BEG, N2BEGb, N4BEG, S1END, S2MID, S2END, S4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:NULL  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:NULL  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:NULL  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:NULL  
+	//  EAST
+	//  SOUTH
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:S4END  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	S_term_RAM_IO_switch_matrix Inst_S_term_RAM_IO_switch_matrix (
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.S4END4(S4END[4]),
+	.S4END5(S4END[5]),
+	.S4END6(S4END[6]),
+	.S4END7(S4END[7]),
+	.S4END8(S4END[8]),
+	.S4END9(S4END[9]),
+	.S4END10(S4END[10]),
+	.S4END11(S4END[11]),
+	.S4END12(S4END[12]),
+	.S4END13(S4END[13]),
+	.S4END14(S4END[14]),
+	.S4END15(S4END[15]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[0]),
+	.N4BEG1(N4BEG[1]),
+	.N4BEG2(N4BEG[2]),
+	.N4BEG3(N4BEG[3]),
+	.N4BEG4(N4BEG[4]),
+	.N4BEG5(N4BEG[5]),
+	.N4BEG6(N4BEG[6]),
+	.N4BEG7(N4BEG[7]),
+	.N4BEG8(N4BEG[8]),
+	.N4BEG9(N4BEG[9]),
+	.N4BEG10(N4BEG[10]),
+	.N4BEG11(N4BEG[11]),
+	.N4BEG12(N4BEG[12]),
+	.N4BEG13(N4BEG[13]),
+	.N4BEG14(N4BEG[14]),
+	.N4BEG15(N4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_single2_switch_matrix.v b/verilog/rtl/eFPGA_core/S_term_single2_switch_matrix.v
new file mode 100644
index 0000000..47eded7
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_single2_switch_matrix.v
@@ -0,0 +1,297 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module S_term_single2_switch_matrix (S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, S4END4, S4END5, S4END6, S4END7, S4END8, S4END9, S4END10, S4END11, S4END12, S4END13, S4END14, S4END15, SS4END0, SS4END1, SS4END2, SS4END3, SS4END4, SS4END5, SS4END6, SS4END7, SS4END8, SS4END9, SS4END10, SS4END11, SS4END12, SS4END13, SS4END14, SS4END15, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, N4BEG4, N4BEG5, N4BEG6, N4BEG7, N4BEG8, N4BEG9, N4BEG10, N4BEG11, N4BEG12, N4BEG13, N4BEG14, N4BEG15, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, NN4BEG4, NN4BEG5, NN4BEG6, NN4BEG7, NN4BEG8, NN4BEG9, NN4BEG10, NN4BEG11, NN4BEG12, NN4BEG13, NN4BEG14, NN4BEG15);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input S4END4;
+	input S4END5;
+	input S4END6;
+	input S4END7;
+	input S4END8;
+	input S4END9;
+	input S4END10;
+	input S4END11;
+	input S4END12;
+	input S4END13;
+	input S4END14;
+	input S4END15;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input SS4END4;
+	input SS4END5;
+	input SS4END6;
+	input SS4END7;
+	input SS4END8;
+	input SS4END9;
+	input SS4END10;
+	input SS4END11;
+	input SS4END12;
+	input SS4END13;
+	input SS4END14;
+	input SS4END15;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output N4BEG4;
+	output N4BEG5;
+	output N4BEG6;
+	output N4BEG7;
+	output N4BEG8;
+	output N4BEG9;
+	output N4BEG10;
+	output N4BEG11;
+	output N4BEG12;
+	output N4BEG13;
+	output N4BEG14;
+	output N4BEG15;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output NN4BEG4;
+	output NN4BEG5;
+	output NN4BEG6;
+	output NN4BEG7;
+	output NN4BEG8;
+	output NN4BEG9;
+	output NN4BEG10;
+	output NN4BEG11;
+	output NN4BEG12;
+	output NN4BEG13;
+	output NN4BEG14;
+	output NN4BEG15;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] N1BEG0_input;
+	wire [1-1:0] N1BEG1_input;
+	wire [1-1:0] N1BEG2_input;
+	wire [1-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [1-1:0] N4BEG0_input;
+	wire [1-1:0] N4BEG1_input;
+	wire [1-1:0] N4BEG2_input;
+	wire [1-1:0] N4BEG3_input;
+	wire [1-1:0] N4BEG4_input;
+	wire [1-1:0] N4BEG5_input;
+	wire [1-1:0] N4BEG6_input;
+	wire [1-1:0] N4BEG7_input;
+	wire [1-1:0] N4BEG8_input;
+	wire [1-1:0] N4BEG9_input;
+	wire [1-1:0] N4BEG10_input;
+	wire [1-1:0] N4BEG11_input;
+	wire [1-1:0] N4BEG12_input;
+	wire [1-1:0] N4BEG13_input;
+	wire [1-1:0] N4BEG14_input;
+	wire [1-1:0] N4BEG15_input;
+	wire [1-1:0] NN4BEG0_input;
+	wire [1-1:0] NN4BEG1_input;
+	wire [1-1:0] NN4BEG2_input;
+	wire [1-1:0] NN4BEG3_input;
+	wire [1-1:0] NN4BEG4_input;
+	wire [1-1:0] NN4BEG5_input;
+	wire [1-1:0] NN4BEG6_input;
+	wire [1-1:0] NN4BEG7_input;
+	wire [1-1:0] NN4BEG8_input;
+	wire [1-1:0] NN4BEG9_input;
+	wire [1-1:0] NN4BEG10_input;
+	wire [1-1:0] NN4BEG11_input;
+	wire [1-1:0] NN4BEG12_input;
+	wire [1-1:0] NN4BEG13_input;
+	wire [1-1:0] NN4BEG14_input;
+	wire [1-1:0] NN4BEG15_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-1
+	assign N1BEG0 = S1END3;
+// switch matrix multiplexer  N1BEG1 		MUX-1
+	assign N1BEG1 = S1END2;
+// switch matrix multiplexer  N1BEG2 		MUX-1
+	assign N1BEG2 = S1END1;
+// switch matrix multiplexer  N1BEG3 		MUX-1
+	assign N1BEG3 = S1END0;
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = S2MID7;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = S2MID6;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = S2MID5;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = S2MID4;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = S2MID3;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = S2MID2;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = S2MID1;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = S2MID0;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = S2END7;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = S2END6;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = S2END5;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = S2END4;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = S2END3;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = S2END2;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = S2END1;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = S2END0;
+// switch matrix multiplexer  N4BEG0 		MUX-1
+	assign N4BEG0 = S4END15;
+// switch matrix multiplexer  N4BEG1 		MUX-1
+	assign N4BEG1 = S4END14;
+// switch matrix multiplexer  N4BEG2 		MUX-1
+	assign N4BEG2 = S4END13;
+// switch matrix multiplexer  N4BEG3 		MUX-1
+	assign N4BEG3 = S4END12;
+// switch matrix multiplexer  N4BEG4 		MUX-1
+	assign N4BEG4 = S4END11;
+// switch matrix multiplexer  N4BEG5 		MUX-1
+	assign N4BEG5 = S4END10;
+// switch matrix multiplexer  N4BEG6 		MUX-1
+	assign N4BEG6 = S4END9;
+// switch matrix multiplexer  N4BEG7 		MUX-1
+	assign N4BEG7 = S4END8;
+// switch matrix multiplexer  N4BEG8 		MUX-1
+	assign N4BEG8 = S4END7;
+// switch matrix multiplexer  N4BEG9 		MUX-1
+	assign N4BEG9 = S4END6;
+// switch matrix multiplexer  N4BEG10 		MUX-1
+	assign N4BEG10 = S4END5;
+// switch matrix multiplexer  N4BEG11 		MUX-1
+	assign N4BEG11 = S4END4;
+// switch matrix multiplexer  N4BEG12 		MUX-1
+	assign N4BEG12 = S4END3;
+// switch matrix multiplexer  N4BEG13 		MUX-1
+	assign N4BEG13 = S4END2;
+// switch matrix multiplexer  N4BEG14 		MUX-1
+	assign N4BEG14 = S4END1;
+// switch matrix multiplexer  N4BEG15 		MUX-1
+	assign N4BEG15 = S4END0;
+// switch matrix multiplexer  NN4BEG0 		MUX-1
+	assign NN4BEG0 = SS4END15;
+// switch matrix multiplexer  NN4BEG1 		MUX-1
+	assign NN4BEG1 = SS4END14;
+// switch matrix multiplexer  NN4BEG2 		MUX-1
+	assign NN4BEG2 = SS4END13;
+// switch matrix multiplexer  NN4BEG3 		MUX-1
+	assign NN4BEG3 = SS4END12;
+// switch matrix multiplexer  NN4BEG4 		MUX-1
+	assign NN4BEG4 = SS4END11;
+// switch matrix multiplexer  NN4BEG5 		MUX-1
+	assign NN4BEG5 = SS4END10;
+// switch matrix multiplexer  NN4BEG6 		MUX-1
+	assign NN4BEG6 = SS4END9;
+// switch matrix multiplexer  NN4BEG7 		MUX-1
+	assign NN4BEG7 = SS4END8;
+// switch matrix multiplexer  NN4BEG8 		MUX-1
+	assign NN4BEG8 = SS4END7;
+// switch matrix multiplexer  NN4BEG9 		MUX-1
+	assign NN4BEG9 = SS4END6;
+// switch matrix multiplexer  NN4BEG10 		MUX-1
+	assign NN4BEG10 = SS4END5;
+// switch matrix multiplexer  NN4BEG11 		MUX-1
+	assign NN4BEG11 = SS4END4;
+// switch matrix multiplexer  NN4BEG12 		MUX-1
+	assign NN4BEG12 = SS4END3;
+// switch matrix multiplexer  NN4BEG13 		MUX-1
+	assign NN4BEG13 = SS4END2;
+// switch matrix multiplexer  NN4BEG14 		MUX-1
+	assign NN4BEG14 = SS4END1;
+// switch matrix multiplexer  NN4BEG15 		MUX-1
+	assign NN4BEG15 = SS4END0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_single2_tile.v b/verilog/rtl/eFPGA_core/S_term_single2_tile.v
new file mode 100644
index 0000000..ae84ade
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_single2_tile.v
@@ -0,0 +1,362 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module S_term_single2 (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:NULL  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:NULL  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:NULL  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:NULL  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NULL  
+	//  EAST
+	//  SOUTH
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:SS4END  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	S_term_single2_switch_matrix Inst_S_term_single2_switch_matrix (
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.S4END4(S4END[4]),
+	.S4END5(S4END[5]),
+	.S4END6(S4END[6]),
+	.S4END7(S4END[7]),
+	.S4END8(S4END[8]),
+	.S4END9(S4END[9]),
+	.S4END10(S4END[10]),
+	.S4END11(S4END[11]),
+	.S4END12(S4END[12]),
+	.S4END13(S4END[13]),
+	.S4END14(S4END[14]),
+	.S4END15(S4END[15]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.SS4END4(SS4END[4]),
+	.SS4END5(SS4END[5]),
+	.SS4END6(SS4END[6]),
+	.SS4END7(SS4END[7]),
+	.SS4END8(SS4END[8]),
+	.SS4END9(SS4END[9]),
+	.SS4END10(SS4END[10]),
+	.SS4END11(SS4END[11]),
+	.SS4END12(SS4END[12]),
+	.SS4END13(SS4END[13]),
+	.SS4END14(SS4END[14]),
+	.SS4END15(SS4END[15]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[0]),
+	.N4BEG1(N4BEG[1]),
+	.N4BEG2(N4BEG[2]),
+	.N4BEG3(N4BEG[3]),
+	.N4BEG4(N4BEG[4]),
+	.N4BEG5(N4BEG[5]),
+	.N4BEG6(N4BEG[6]),
+	.N4BEG7(N4BEG[7]),
+	.N4BEG8(N4BEG[8]),
+	.N4BEG9(N4BEG[9]),
+	.N4BEG10(N4BEG[10]),
+	.N4BEG11(N4BEG[11]),
+	.N4BEG12(N4BEG[12]),
+	.N4BEG13(N4BEG[13]),
+	.N4BEG14(N4BEG[14]),
+	.N4BEG15(N4BEG[15]),
+	.NN4BEG0(NN4BEG[0]),
+	.NN4BEG1(NN4BEG[1]),
+	.NN4BEG2(NN4BEG[2]),
+	.NN4BEG3(NN4BEG[3]),
+	.NN4BEG4(NN4BEG[4]),
+	.NN4BEG5(NN4BEG[5]),
+	.NN4BEG6(NN4BEG[6]),
+	.NN4BEG7(NN4BEG[7]),
+	.NN4BEG8(NN4BEG[8]),
+	.NN4BEG9(NN4BEG[9]),
+	.NN4BEG10(NN4BEG[10]),
+	.NN4BEG11(NN4BEG[11]),
+	.NN4BEG12(NN4BEG[12]),
+	.NN4BEG13(NN4BEG[13]),
+	.NN4BEG14(NN4BEG[14]),
+	.NN4BEG15(NN4BEG[15])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_single_switch_matrix.v b/verilog/rtl/eFPGA_core/S_term_single_switch_matrix.v
new file mode 100644
index 0000000..baf7be3
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_single_switch_matrix.v
@@ -0,0 +1,301 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module S_term_single_switch_matrix (S1END0, S1END1, S1END2, S1END3, S2MID0, S2MID1, S2MID2, S2MID3, S2MID4, S2MID5, S2MID6, S2MID7, S2END0, S2END1, S2END2, S2END3, S2END4, S2END5, S2END6, S2END7, S4END0, S4END1, S4END2, S4END3, S4END4, S4END5, S4END6, S4END7, S4END8, S4END9, S4END10, S4END11, S4END12, S4END13, S4END14, S4END15, SS4END0, SS4END1, SS4END2, SS4END3, SS4END4, SS4END5, SS4END6, SS4END7, SS4END8, SS4END9, SS4END10, SS4END11, SS4END12, SS4END13, SS4END14, SS4END15, N1BEG0, N1BEG1, N1BEG2, N1BEG3, N2BEG0, N2BEG1, N2BEG2, N2BEG3, N2BEG4, N2BEG5, N2BEG6, N2BEG7, N2BEGb0, N2BEGb1, N2BEGb2, N2BEGb3, N2BEGb4, N2BEGb5, N2BEGb6, N2BEGb7, N4BEG0, N4BEG1, N4BEG2, N4BEG3, N4BEG4, N4BEG5, N4BEG6, N4BEG7, N4BEG8, N4BEG9, N4BEG10, N4BEG11, N4BEG12, N4BEG13, N4BEG14, N4BEG15, NN4BEG0, NN4BEG1, NN4BEG2, NN4BEG3, NN4BEG4, NN4BEG5, NN4BEG6, NN4BEG7, NN4BEG8, NN4BEG9, NN4BEG10, NN4BEG11, NN4BEG12, NN4BEG13, NN4BEG14, NN4BEG15, Co0);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input S1END0;
+	input S1END1;
+	input S1END2;
+	input S1END3;
+	input S2MID0;
+	input S2MID1;
+	input S2MID2;
+	input S2MID3;
+	input S2MID4;
+	input S2MID5;
+	input S2MID6;
+	input S2MID7;
+	input S2END0;
+	input S2END1;
+	input S2END2;
+	input S2END3;
+	input S2END4;
+	input S2END5;
+	input S2END6;
+	input S2END7;
+	input S4END0;
+	input S4END1;
+	input S4END2;
+	input S4END3;
+	input S4END4;
+	input S4END5;
+	input S4END6;
+	input S4END7;
+	input S4END8;
+	input S4END9;
+	input S4END10;
+	input S4END11;
+	input S4END12;
+	input S4END13;
+	input S4END14;
+	input S4END15;
+	input SS4END0;
+	input SS4END1;
+	input SS4END2;
+	input SS4END3;
+	input SS4END4;
+	input SS4END5;
+	input SS4END6;
+	input SS4END7;
+	input SS4END8;
+	input SS4END9;
+	input SS4END10;
+	input SS4END11;
+	input SS4END12;
+	input SS4END13;
+	input SS4END14;
+	input SS4END15;
+	output N1BEG0;
+	output N1BEG1;
+	output N1BEG2;
+	output N1BEG3;
+	output N2BEG0;
+	output N2BEG1;
+	output N2BEG2;
+	output N2BEG3;
+	output N2BEG4;
+	output N2BEG5;
+	output N2BEG6;
+	output N2BEG7;
+	output N2BEGb0;
+	output N2BEGb1;
+	output N2BEGb2;
+	output N2BEGb3;
+	output N2BEGb4;
+	output N2BEGb5;
+	output N2BEGb6;
+	output N2BEGb7;
+	output N4BEG0;
+	output N4BEG1;
+	output N4BEG2;
+	output N4BEG3;
+	output N4BEG4;
+	output N4BEG5;
+	output N4BEG6;
+	output N4BEG7;
+	output N4BEG8;
+	output N4BEG9;
+	output N4BEG10;
+	output N4BEG11;
+	output N4BEG12;
+	output N4BEG13;
+	output N4BEG14;
+	output N4BEG15;
+	output NN4BEG0;
+	output NN4BEG1;
+	output NN4BEG2;
+	output NN4BEG3;
+	output NN4BEG4;
+	output NN4BEG5;
+	output NN4BEG6;
+	output NN4BEG7;
+	output NN4BEG8;
+	output NN4BEG9;
+	output NN4BEG10;
+	output NN4BEG11;
+	output NN4BEG12;
+	output NN4BEG13;
+	output NN4BEG14;
+	output NN4BEG15;
+	output Co0;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] N1BEG0_input;
+	wire [1-1:0] N1BEG1_input;
+	wire [1-1:0] N1BEG2_input;
+	wire [1-1:0] N1BEG3_input;
+	wire [1-1:0] N2BEG0_input;
+	wire [1-1:0] N2BEG1_input;
+	wire [1-1:0] N2BEG2_input;
+	wire [1-1:0] N2BEG3_input;
+	wire [1-1:0] N2BEG4_input;
+	wire [1-1:0] N2BEG5_input;
+	wire [1-1:0] N2BEG6_input;
+	wire [1-1:0] N2BEG7_input;
+	wire [1-1:0] N2BEGb0_input;
+	wire [1-1:0] N2BEGb1_input;
+	wire [1-1:0] N2BEGb2_input;
+	wire [1-1:0] N2BEGb3_input;
+	wire [1-1:0] N2BEGb4_input;
+	wire [1-1:0] N2BEGb5_input;
+	wire [1-1:0] N2BEGb6_input;
+	wire [1-1:0] N2BEGb7_input;
+	wire [1-1:0] N4BEG0_input;
+	wire [1-1:0] N4BEG1_input;
+	wire [1-1:0] N4BEG2_input;
+	wire [1-1:0] N4BEG3_input;
+	wire [1-1:0] N4BEG4_input;
+	wire [1-1:0] N4BEG5_input;
+	wire [1-1:0] N4BEG6_input;
+	wire [1-1:0] N4BEG7_input;
+	wire [1-1:0] N4BEG8_input;
+	wire [1-1:0] N4BEG9_input;
+	wire [1-1:0] N4BEG10_input;
+	wire [1-1:0] N4BEG11_input;
+	wire [1-1:0] N4BEG12_input;
+	wire [1-1:0] N4BEG13_input;
+	wire [1-1:0] N4BEG14_input;
+	wire [1-1:0] N4BEG15_input;
+	wire [1-1:0] NN4BEG0_input;
+	wire [1-1:0] NN4BEG1_input;
+	wire [1-1:0] NN4BEG2_input;
+	wire [1-1:0] NN4BEG3_input;
+	wire [1-1:0] NN4BEG4_input;
+	wire [1-1:0] NN4BEG5_input;
+	wire [1-1:0] NN4BEG6_input;
+	wire [1-1:0] NN4BEG7_input;
+	wire [1-1:0] NN4BEG8_input;
+	wire [1-1:0] NN4BEG9_input;
+	wire [1-1:0] NN4BEG10_input;
+	wire [1-1:0] NN4BEG11_input;
+	wire [1-1:0] NN4BEG12_input;
+	wire [1-1:0] NN4BEG13_input;
+	wire [1-1:0] NN4BEG14_input;
+	wire [1-1:0] NN4BEG15_input;
+	wire [1-1:0] Co0_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  N1BEG0 		MUX-1
+	assign N1BEG0 = S1END3;
+// switch matrix multiplexer  N1BEG1 		MUX-1
+	assign N1BEG1 = S1END2;
+// switch matrix multiplexer  N1BEG2 		MUX-1
+	assign N1BEG2 = S1END1;
+// switch matrix multiplexer  N1BEG3 		MUX-1
+	assign N1BEG3 = S1END0;
+// switch matrix multiplexer  N2BEG0 		MUX-1
+	assign N2BEG0 = S2MID7;
+// switch matrix multiplexer  N2BEG1 		MUX-1
+	assign N2BEG1 = S2MID6;
+// switch matrix multiplexer  N2BEG2 		MUX-1
+	assign N2BEG2 = S2MID5;
+// switch matrix multiplexer  N2BEG3 		MUX-1
+	assign N2BEG3 = S2MID4;
+// switch matrix multiplexer  N2BEG4 		MUX-1
+	assign N2BEG4 = S2MID3;
+// switch matrix multiplexer  N2BEG5 		MUX-1
+	assign N2BEG5 = S2MID2;
+// switch matrix multiplexer  N2BEG6 		MUX-1
+	assign N2BEG6 = S2MID1;
+// switch matrix multiplexer  N2BEG7 		MUX-1
+	assign N2BEG7 = S2MID0;
+// switch matrix multiplexer  N2BEGb0 		MUX-1
+	assign N2BEGb0 = S2END7;
+// switch matrix multiplexer  N2BEGb1 		MUX-1
+	assign N2BEGb1 = S2END6;
+// switch matrix multiplexer  N2BEGb2 		MUX-1
+	assign N2BEGb2 = S2END5;
+// switch matrix multiplexer  N2BEGb3 		MUX-1
+	assign N2BEGb3 = S2END4;
+// switch matrix multiplexer  N2BEGb4 		MUX-1
+	assign N2BEGb4 = S2END3;
+// switch matrix multiplexer  N2BEGb5 		MUX-1
+	assign N2BEGb5 = S2END2;
+// switch matrix multiplexer  N2BEGb6 		MUX-1
+	assign N2BEGb6 = S2END1;
+// switch matrix multiplexer  N2BEGb7 		MUX-1
+	assign N2BEGb7 = S2END0;
+// switch matrix multiplexer  N4BEG0 		MUX-1
+	assign N4BEG0 = S4END15;
+// switch matrix multiplexer  N4BEG1 		MUX-1
+	assign N4BEG1 = S4END14;
+// switch matrix multiplexer  N4BEG2 		MUX-1
+	assign N4BEG2 = S4END13;
+// switch matrix multiplexer  N4BEG3 		MUX-1
+	assign N4BEG3 = S4END12;
+// switch matrix multiplexer  N4BEG4 		MUX-1
+	assign N4BEG4 = S4END11;
+// switch matrix multiplexer  N4BEG5 		MUX-1
+	assign N4BEG5 = S4END10;
+// switch matrix multiplexer  N4BEG6 		MUX-1
+	assign N4BEG6 = S4END9;
+// switch matrix multiplexer  N4BEG7 		MUX-1
+	assign N4BEG7 = S4END8;
+// switch matrix multiplexer  N4BEG8 		MUX-1
+	assign N4BEG8 = S4END7;
+// switch matrix multiplexer  N4BEG9 		MUX-1
+	assign N4BEG9 = S4END6;
+// switch matrix multiplexer  N4BEG10 		MUX-1
+	assign N4BEG10 = S4END5;
+// switch matrix multiplexer  N4BEG11 		MUX-1
+	assign N4BEG11 = S4END4;
+// switch matrix multiplexer  N4BEG12 		MUX-1
+	assign N4BEG12 = S4END3;
+// switch matrix multiplexer  N4BEG13 		MUX-1
+	assign N4BEG13 = S4END2;
+// switch matrix multiplexer  N4BEG14 		MUX-1
+	assign N4BEG14 = S4END1;
+// switch matrix multiplexer  N4BEG15 		MUX-1
+	assign N4BEG15 = S4END0;
+// switch matrix multiplexer  NN4BEG0 		MUX-1
+	assign NN4BEG0 = SS4END15;
+// switch matrix multiplexer  NN4BEG1 		MUX-1
+	assign NN4BEG1 = SS4END14;
+// switch matrix multiplexer  NN4BEG2 		MUX-1
+	assign NN4BEG2 = SS4END13;
+// switch matrix multiplexer  NN4BEG3 		MUX-1
+	assign NN4BEG3 = SS4END12;
+// switch matrix multiplexer  NN4BEG4 		MUX-1
+	assign NN4BEG4 = SS4END11;
+// switch matrix multiplexer  NN4BEG5 		MUX-1
+	assign NN4BEG5 = SS4END10;
+// switch matrix multiplexer  NN4BEG6 		MUX-1
+	assign NN4BEG6 = SS4END9;
+// switch matrix multiplexer  NN4BEG7 		MUX-1
+	assign NN4BEG7 = SS4END8;
+// switch matrix multiplexer  NN4BEG8 		MUX-1
+	assign NN4BEG8 = SS4END7;
+// switch matrix multiplexer  NN4BEG9 		MUX-1
+	assign NN4BEG9 = SS4END6;
+// switch matrix multiplexer  NN4BEG10 		MUX-1
+	assign NN4BEG10 = SS4END5;
+// switch matrix multiplexer  NN4BEG11 		MUX-1
+	assign NN4BEG11 = SS4END4;
+// switch matrix multiplexer  NN4BEG12 		MUX-1
+	assign NN4BEG12 = SS4END3;
+// switch matrix multiplexer  NN4BEG13 		MUX-1
+	assign NN4BEG13 = SS4END2;
+// switch matrix multiplexer  NN4BEG14 		MUX-1
+	assign NN4BEG14 = SS4END1;
+// switch matrix multiplexer  NN4BEG15 		MUX-1
+	assign NN4BEG15 = SS4END0;
+// switch matrix multiplexer  Co0 		MUX-1
+	assign Co0 = GND0;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/S_term_single_tile.v b/verilog/rtl/eFPGA_core/S_term_single_tile.v
new file mode 100644
index 0000000..ef1a1f4
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/S_term_single_tile.v
@@ -0,0 +1,364 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module S_term_single (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, Co, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 0;
+	//  NORTH
+	output [3:0] N1BEG; //wires:4 X_offset:0 Y_offset:1  source_name:N1BEG destination_name:NULL  
+	output [7:0] N2BEG; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEG destination_name:NULL  
+	output [7:0] N2BEGb; //wires:8 X_offset:0 Y_offset:1  source_name:N2BEGb destination_name:NULL  
+	output [15:0] N4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:N4BEG destination_name:NULL  
+	output [15:0] NN4BEG; //wires:4 X_offset:0 Y_offset:4  source_name:NN4BEG destination_name:NULL  
+	output [0:0] Co; //wires:1 X_offset:0 Y_offset:1  source_name:Co destination_name:NULL  
+	//  EAST
+	//  SOUTH
+	input [3:0] S1END; //wires:4 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S1END  
+	input [7:0] S2MID; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2MID  
+	input [7:0] S2END; //wires:8 X_offset:0 Y_offset:-1  source_name:NULL destination_name:S2END  
+	input [15:0] S4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:S4END  
+	input [15:0] SS4END; //wires:4 X_offset:0 Y_offset:-4  source_name:NULL destination_name:SS4END  
+	//  WEST
+	input UserCLK;
+	output UserCLKo;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+//BEL component instantiations
+
+//switch matrix component instantiation
+	S_term_single_switch_matrix Inst_S_term_single_switch_matrix (
+	.S1END0(S1END[0]),
+	.S1END1(S1END[1]),
+	.S1END2(S1END[2]),
+	.S1END3(S1END[3]),
+	.S2MID0(S2MID[0]),
+	.S2MID1(S2MID[1]),
+	.S2MID2(S2MID[2]),
+	.S2MID3(S2MID[3]),
+	.S2MID4(S2MID[4]),
+	.S2MID5(S2MID[5]),
+	.S2MID6(S2MID[6]),
+	.S2MID7(S2MID[7]),
+	.S2END0(S2END[0]),
+	.S2END1(S2END[1]),
+	.S2END2(S2END[2]),
+	.S2END3(S2END[3]),
+	.S2END4(S2END[4]),
+	.S2END5(S2END[5]),
+	.S2END6(S2END[6]),
+	.S2END7(S2END[7]),
+	.S4END0(S4END[0]),
+	.S4END1(S4END[1]),
+	.S4END2(S4END[2]),
+	.S4END3(S4END[3]),
+	.S4END4(S4END[4]),
+	.S4END5(S4END[5]),
+	.S4END6(S4END[6]),
+	.S4END7(S4END[7]),
+	.S4END8(S4END[8]),
+	.S4END9(S4END[9]),
+	.S4END10(S4END[10]),
+	.S4END11(S4END[11]),
+	.S4END12(S4END[12]),
+	.S4END13(S4END[13]),
+	.S4END14(S4END[14]),
+	.S4END15(S4END[15]),
+	.SS4END0(SS4END[0]),
+	.SS4END1(SS4END[1]),
+	.SS4END2(SS4END[2]),
+	.SS4END3(SS4END[3]),
+	.SS4END4(SS4END[4]),
+	.SS4END5(SS4END[5]),
+	.SS4END6(SS4END[6]),
+	.SS4END7(SS4END[7]),
+	.SS4END8(SS4END[8]),
+	.SS4END9(SS4END[9]),
+	.SS4END10(SS4END[10]),
+	.SS4END11(SS4END[11]),
+	.SS4END12(SS4END[12]),
+	.SS4END13(SS4END[13]),
+	.SS4END14(SS4END[14]),
+	.SS4END15(SS4END[15]),
+	.N1BEG0(N1BEG[0]),
+	.N1BEG1(N1BEG[1]),
+	.N1BEG2(N1BEG[2]),
+	.N1BEG3(N1BEG[3]),
+	.N2BEG0(N2BEG[0]),
+	.N2BEG1(N2BEG[1]),
+	.N2BEG2(N2BEG[2]),
+	.N2BEG3(N2BEG[3]),
+	.N2BEG4(N2BEG[4]),
+	.N2BEG5(N2BEG[5]),
+	.N2BEG6(N2BEG[6]),
+	.N2BEG7(N2BEG[7]),
+	.N2BEGb0(N2BEGb[0]),
+	.N2BEGb1(N2BEGb[1]),
+	.N2BEGb2(N2BEGb[2]),
+	.N2BEGb3(N2BEGb[3]),
+	.N2BEGb4(N2BEGb[4]),
+	.N2BEGb5(N2BEGb[5]),
+	.N2BEGb6(N2BEGb[6]),
+	.N2BEGb7(N2BEGb[7]),
+	.N4BEG0(N4BEG[0]),
+	.N4BEG1(N4BEG[1]),
+	.N4BEG2(N4BEG[2]),
+	.N4BEG3(N4BEG[3]),
+	.N4BEG4(N4BEG[4]),
+	.N4BEG5(N4BEG[5]),
+	.N4BEG6(N4BEG[6]),
+	.N4BEG7(N4BEG[7]),
+	.N4BEG8(N4BEG[8]),
+	.N4BEG9(N4BEG[9]),
+	.N4BEG10(N4BEG[10]),
+	.N4BEG11(N4BEG[11]),
+	.N4BEG12(N4BEG[12]),
+	.N4BEG13(N4BEG[13]),
+	.N4BEG14(N4BEG[14]),
+	.N4BEG15(N4BEG[15]),
+	.NN4BEG0(NN4BEG[0]),
+	.NN4BEG1(NN4BEG[1]),
+	.NN4BEG2(NN4BEG[2]),
+	.NN4BEG3(NN4BEG[3]),
+	.NN4BEG4(NN4BEG[4]),
+	.NN4BEG5(NN4BEG[5]),
+	.NN4BEG6(NN4BEG[6]),
+	.NN4BEG7(NN4BEG[7]),
+	.NN4BEG8(NN4BEG[8]),
+	.NN4BEG9(NN4BEG[9]),
+	.NN4BEG10(NN4BEG[10]),
+	.NN4BEG11(NN4BEG[11]),
+	.NN4BEG12(NN4BEG[12]),
+	.NN4BEG13(NN4BEG[13]),
+	.NN4BEG14(NN4BEG[14]),
+	.NN4BEG15(NN4BEG[15]),
+	.Co0(Co[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_ConfigMem.v b/verilog/rtl/eFPGA_core/W_CPU_IO_ConfigMem.v
new file mode 100644
index 0000000..9f44f1d
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_ConfigMem.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_CPU_IO_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [20-1:0] frame0;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_bot_ConfigMem.v b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_ConfigMem.v
new file mode 100644
index 0000000..b35531d
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_ConfigMem.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_CPU_IO_bot_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [20-1:0] frame0;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_bot_switch_matrix.v b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_switch_matrix.v
new file mode 100644
index 0000000..7e9dc29
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_switch_matrix.v
@@ -0,0 +1,594 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module W_CPU_IO_bot_switch_matrix (N1END0, N1END1, N1END2, N1END3, N2MID0, N2MID1, N2MID2, N2MID3, N2MID4, N2MID5, N2MID6, N2MID7, N2END0, N2END1, N2END2, N2END3, N2END4, N2END5, N2END6, N2END7, N4END0, N4END1, N4END2, N4END3, N4END4, N4END5, N4END6, N4END7, N4END8, N4END9, N4END10, N4END11, N4END12, N4END13, N4END14, N4END15, NN4END0, NN4END1, NN4END2, NN4END3, NN4END4, NN4END5, NN4END6, NN4END7, NN4END8, NN4END9, NN4END10, NN4END11, NN4END12, NN4END13, NN4END14, NN4END15, Ci0, W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, WW4END4, WW4END5, WW4END6, WW4END7, WW4END8, WW4END9, WW4END10, WW4END11, WW4END12, WW4END13, WW4END14, WW4END15, W6END0, W6END1, W6END2, W6END3, W6END4, W6END5, W6END6, W6END7, W6END8, W6END9, W6END10, W6END11, OPA_O0, OPA_O1, OPA_O2, OPA_O3, OPB_O0, OPB_O1, OPB_O2, OPB_O3, S1BEG0, S1BEG1, S1BEG2, S1BEG3, S2BEG0, S2BEG1, S2BEG2, S2BEG3, S2BEG4, S2BEG5, S2BEG6, S2BEG7, S2BEGb0, S2BEGb1, S2BEGb2, S2BEGb3, S2BEGb4, S2BEGb5, S2BEGb6, S2BEGb7, S4BEG0, S4BEG1, S4BEG2, S4BEG3, S4BEG4, S4BEG5, S4BEG6, S4BEG7, S4BEG8, S4BEG9, S4BEG10, S4BEG11, S4BEG12, S4BEG13, S4BEG14, S4BEG15, SS4BEG0, SS4BEG1, SS4BEG2, SS4BEG3, SS4BEG4, SS4BEG5, SS4BEG6, SS4BEG7, SS4BEG8, SS4BEG9, SS4BEG10, SS4BEG11, SS4BEG12, SS4BEG13, SS4BEG14, SS4BEG15, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, EE4BEG4, EE4BEG5, EE4BEG6, EE4BEG7, EE4BEG8, EE4BEG9, EE4BEG10, EE4BEG11, EE4BEG12, EE4BEG13, EE4BEG14, EE4BEG15, E6BEG0, E6BEG1, E6BEG2, E6BEG3, E6BEG4, E6BEG5, E6BEG6, E6BEG7, E6BEG8, E6BEG9, E6BEG10, E6BEG11, RES0_I0, RES0_I1, RES0_I2, RES0_I3, RES1_I0, RES1_I1, RES1_I2, RES1_I3, RES2_I0, RES2_I1, RES2_I2, RES2_I3);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input N1END0;
+	input N1END1;
+	input N1END2;
+	input N1END3;
+	input N2MID0;
+	input N2MID1;
+	input N2MID2;
+	input N2MID3;
+	input N2MID4;
+	input N2MID5;
+	input N2MID6;
+	input N2MID7;
+	input N2END0;
+	input N2END1;
+	input N2END2;
+	input N2END3;
+	input N2END4;
+	input N2END5;
+	input N2END6;
+	input N2END7;
+	input N4END0;
+	input N4END1;
+	input N4END2;
+	input N4END3;
+	input N4END4;
+	input N4END5;
+	input N4END6;
+	input N4END7;
+	input N4END8;
+	input N4END9;
+	input N4END10;
+	input N4END11;
+	input N4END12;
+	input N4END13;
+	input N4END14;
+	input N4END15;
+	input NN4END0;
+	input NN4END1;
+	input NN4END2;
+	input NN4END3;
+	input NN4END4;
+	input NN4END5;
+	input NN4END6;
+	input NN4END7;
+	input NN4END8;
+	input NN4END9;
+	input NN4END10;
+	input NN4END11;
+	input NN4END12;
+	input NN4END13;
+	input NN4END14;
+	input NN4END15;
+	input Ci0;
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input WW4END4;
+	input WW4END5;
+	input WW4END6;
+	input WW4END7;
+	input WW4END8;
+	input WW4END9;
+	input WW4END10;
+	input WW4END11;
+	input WW4END12;
+	input WW4END13;
+	input WW4END14;
+	input WW4END15;
+	input W6END0;
+	input W6END1;
+	input W6END2;
+	input W6END3;
+	input W6END4;
+	input W6END5;
+	input W6END6;
+	input W6END7;
+	input W6END8;
+	input W6END9;
+	input W6END10;
+	input W6END11;
+	input OPA_O0;
+	input OPA_O1;
+	input OPA_O2;
+	input OPA_O3;
+	input OPB_O0;
+	input OPB_O1;
+	input OPB_O2;
+	input OPB_O3;
+	output S1BEG0;
+	output S1BEG1;
+	output S1BEG2;
+	output S1BEG3;
+	output S2BEG0;
+	output S2BEG1;
+	output S2BEG2;
+	output S2BEG3;
+	output S2BEG4;
+	output S2BEG5;
+	output S2BEG6;
+	output S2BEG7;
+	output S2BEGb0;
+	output S2BEGb1;
+	output S2BEGb2;
+	output S2BEGb3;
+	output S2BEGb4;
+	output S2BEGb5;
+	output S2BEGb6;
+	output S2BEGb7;
+	output S4BEG0;
+	output S4BEG1;
+	output S4BEG2;
+	output S4BEG3;
+	output S4BEG4;
+	output S4BEG5;
+	output S4BEG6;
+	output S4BEG7;
+	output S4BEG8;
+	output S4BEG9;
+	output S4BEG10;
+	output S4BEG11;
+	output S4BEG12;
+	output S4BEG13;
+	output S4BEG14;
+	output S4BEG15;
+	output SS4BEG0;
+	output SS4BEG1;
+	output SS4BEG2;
+	output SS4BEG3;
+	output SS4BEG4;
+	output SS4BEG5;
+	output SS4BEG6;
+	output SS4BEG7;
+	output SS4BEG8;
+	output SS4BEG9;
+	output SS4BEG10;
+	output SS4BEG11;
+	output SS4BEG12;
+	output SS4BEG13;
+	output SS4BEG14;
+	output SS4BEG15;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output EE4BEG4;
+	output EE4BEG5;
+	output EE4BEG6;
+	output EE4BEG7;
+	output EE4BEG8;
+	output EE4BEG9;
+	output EE4BEG10;
+	output EE4BEG11;
+	output EE4BEG12;
+	output EE4BEG13;
+	output EE4BEG14;
+	output EE4BEG15;
+	output E6BEG0;
+	output E6BEG1;
+	output E6BEG2;
+	output E6BEG3;
+	output E6BEG4;
+	output E6BEG5;
+	output E6BEG6;
+	output E6BEG7;
+	output E6BEG8;
+	output E6BEG9;
+	output E6BEG10;
+	output E6BEG11;
+	output RES0_I0;
+	output RES0_I1;
+	output RES0_I2;
+	output RES0_I3;
+	output RES1_I0;
+	output RES1_I1;
+	output RES1_I2;
+	output RES1_I3;
+	output RES2_I0;
+	output RES2_I1;
+	output RES2_I2;
+	output RES2_I3;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] S1BEG0_input;
+	wire [1-1:0] S1BEG1_input;
+	wire [1-1:0] S1BEG2_input;
+	wire [1-1:0] S1BEG3_input;
+	wire [1-1:0] S2BEG0_input;
+	wire [1-1:0] S2BEG1_input;
+	wire [1-1:0] S2BEG2_input;
+	wire [1-1:0] S2BEG3_input;
+	wire [1-1:0] S2BEG4_input;
+	wire [1-1:0] S2BEG5_input;
+	wire [1-1:0] S2BEG6_input;
+	wire [1-1:0] S2BEG7_input;
+	wire [1-1:0] S2BEGb0_input;
+	wire [1-1:0] S2BEGb1_input;
+	wire [1-1:0] S2BEGb2_input;
+	wire [1-1:0] S2BEGb3_input;
+	wire [1-1:0] S2BEGb4_input;
+	wire [1-1:0] S2BEGb5_input;
+	wire [1-1:0] S2BEGb6_input;
+	wire [1-1:0] S2BEGb7_input;
+	wire [1-1:0] S4BEG0_input;
+	wire [1-1:0] S4BEG1_input;
+	wire [1-1:0] S4BEG2_input;
+	wire [1-1:0] S4BEG3_input;
+	wire [1-1:0] S4BEG4_input;
+	wire [1-1:0] S4BEG5_input;
+	wire [1-1:0] S4BEG6_input;
+	wire [1-1:0] S4BEG7_input;
+	wire [1-1:0] S4BEG8_input;
+	wire [1-1:0] S4BEG9_input;
+	wire [1-1:0] S4BEG10_input;
+	wire [1-1:0] S4BEG11_input;
+	wire [1-1:0] S4BEG12_input;
+	wire [1-1:0] S4BEG13_input;
+	wire [1-1:0] S4BEG14_input;
+	wire [1-1:0] S4BEG15_input;
+	wire [1-1:0] SS4BEG0_input;
+	wire [1-1:0] SS4BEG1_input;
+	wire [1-1:0] SS4BEG2_input;
+	wire [1-1:0] SS4BEG3_input;
+	wire [1-1:0] SS4BEG4_input;
+	wire [1-1:0] SS4BEG5_input;
+	wire [1-1:0] SS4BEG6_input;
+	wire [1-1:0] SS4BEG7_input;
+	wire [1-1:0] SS4BEG8_input;
+	wire [1-1:0] SS4BEG9_input;
+	wire [1-1:0] SS4BEG10_input;
+	wire [1-1:0] SS4BEG11_input;
+	wire [1-1:0] SS4BEG12_input;
+	wire [1-1:0] SS4BEG13_input;
+	wire [1-1:0] SS4BEG14_input;
+	wire [1-1:0] SS4BEG15_input;
+	wire [1-1:0] E1BEG0_input;
+	wire [1-1:0] E1BEG1_input;
+	wire [1-1:0] E1BEG2_input;
+	wire [1-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [0-1:0] EE4BEG0_input;
+	wire [0-1:0] EE4BEG1_input;
+	wire [0-1:0] EE4BEG2_input;
+	wire [0-1:0] EE4BEG3_input;
+	wire [0-1:0] EE4BEG4_input;
+	wire [0-1:0] EE4BEG5_input;
+	wire [0-1:0] EE4BEG6_input;
+	wire [0-1:0] EE4BEG7_input;
+	wire [0-1:0] EE4BEG8_input;
+	wire [0-1:0] EE4BEG9_input;
+	wire [0-1:0] EE4BEG10_input;
+	wire [0-1:0] EE4BEG11_input;
+	wire [0-1:0] EE4BEG12_input;
+	wire [0-1:0] EE4BEG13_input;
+	wire [0-1:0] EE4BEG14_input;
+	wire [0-1:0] EE4BEG15_input;
+	wire [1-1:0] E6BEG0_input;
+	wire [1-1:0] E6BEG1_input;
+	wire [1-1:0] E6BEG2_input;
+	wire [1-1:0] E6BEG3_input;
+	wire [1-1:0] E6BEG4_input;
+	wire [1-1:0] E6BEG5_input;
+	wire [1-1:0] E6BEG6_input;
+	wire [1-1:0] E6BEG7_input;
+	wire [1-1:0] E6BEG8_input;
+	wire [1-1:0] E6BEG9_input;
+	wire [1-1:0] E6BEG10_input;
+	wire [1-1:0] E6BEG11_input;
+	wire [1-1:0] RES0_I0_input;
+	wire [1-1:0] RES0_I1_input;
+	wire [1-1:0] RES0_I2_input;
+	wire [1-1:0] RES0_I3_input;
+	wire [1-1:0] RES1_I0_input;
+	wire [1-1:0] RES1_I1_input;
+	wire [1-1:0] RES1_I2_input;
+	wire [1-1:0] RES1_I3_input;
+	wire [1-1:0] RES2_I0_input;
+	wire [1-1:0] RES2_I1_input;
+	wire [1-1:0] RES2_I2_input;
+	wire [1-1:0] RES2_I3_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  S1BEG0 		MUX-1
+	assign S1BEG0 = N1END3;
+// switch matrix multiplexer  S1BEG1 		MUX-1
+	assign S1BEG1 = N1END2;
+// switch matrix multiplexer  S1BEG2 		MUX-1
+	assign S1BEG2 = N1END1;
+// switch matrix multiplexer  S1BEG3 		MUX-1
+	assign S1BEG3 = N1END0;
+// switch matrix multiplexer  S2BEG0 		MUX-1
+	assign S2BEG0 = N2MID7;
+// switch matrix multiplexer  S2BEG1 		MUX-1
+	assign S2BEG1 = N2MID6;
+// switch matrix multiplexer  S2BEG2 		MUX-1
+	assign S2BEG2 = N2MID5;
+// switch matrix multiplexer  S2BEG3 		MUX-1
+	assign S2BEG3 = N2MID4;
+// switch matrix multiplexer  S2BEG4 		MUX-1
+	assign S2BEG4 = N2MID3;
+// switch matrix multiplexer  S2BEG5 		MUX-1
+	assign S2BEG5 = N2MID2;
+// switch matrix multiplexer  S2BEG6 		MUX-1
+	assign S2BEG6 = N2MID1;
+// switch matrix multiplexer  S2BEG7 		MUX-1
+	assign S2BEG7 = N2MID0;
+// switch matrix multiplexer  S2BEGb0 		MUX-1
+	assign S2BEGb0 = N2END7;
+// switch matrix multiplexer  S2BEGb1 		MUX-1
+	assign S2BEGb1 = N2END6;
+// switch matrix multiplexer  S2BEGb2 		MUX-1
+	assign S2BEGb2 = N2END5;
+// switch matrix multiplexer  S2BEGb3 		MUX-1
+	assign S2BEGb3 = N2END4;
+// switch matrix multiplexer  S2BEGb4 		MUX-1
+	assign S2BEGb4 = N2END3;
+// switch matrix multiplexer  S2BEGb5 		MUX-1
+	assign S2BEGb5 = N2END2;
+// switch matrix multiplexer  S2BEGb6 		MUX-1
+	assign S2BEGb6 = N2END1;
+// switch matrix multiplexer  S2BEGb7 		MUX-1
+	assign S2BEGb7 = N2END0;
+// switch matrix multiplexer  S4BEG0 		MUX-1
+	assign S4BEG0 = N4END15;
+// switch matrix multiplexer  S4BEG1 		MUX-1
+	assign S4BEG1 = N4END14;
+// switch matrix multiplexer  S4BEG2 		MUX-1
+	assign S4BEG2 = N4END13;
+// switch matrix multiplexer  S4BEG3 		MUX-1
+	assign S4BEG3 = N4END12;
+// switch matrix multiplexer  S4BEG4 		MUX-1
+	assign S4BEG4 = N4END11;
+// switch matrix multiplexer  S4BEG5 		MUX-1
+	assign S4BEG5 = N4END10;
+// switch matrix multiplexer  S4BEG6 		MUX-1
+	assign S4BEG6 = N4END9;
+// switch matrix multiplexer  S4BEG7 		MUX-1
+	assign S4BEG7 = N4END8;
+// switch matrix multiplexer  S4BEG8 		MUX-1
+	assign S4BEG8 = N4END7;
+// switch matrix multiplexer  S4BEG9 		MUX-1
+	assign S4BEG9 = N4END6;
+// switch matrix multiplexer  S4BEG10 		MUX-1
+	assign S4BEG10 = N4END5;
+// switch matrix multiplexer  S4BEG11 		MUX-1
+	assign S4BEG11 = N4END4;
+// switch matrix multiplexer  S4BEG12 		MUX-1
+	assign S4BEG12 = N4END3;
+// switch matrix multiplexer  S4BEG13 		MUX-1
+	assign S4BEG13 = N4END2;
+// switch matrix multiplexer  S4BEG14 		MUX-1
+	assign S4BEG14 = N4END1;
+// switch matrix multiplexer  S4BEG15 		MUX-1
+	assign S4BEG15 = N4END0;
+// switch matrix multiplexer  SS4BEG0 		MUX-1
+	assign SS4BEG0 = NN4END15;
+// switch matrix multiplexer  SS4BEG1 		MUX-1
+	assign SS4BEG1 = NN4END14;
+// switch matrix multiplexer  SS4BEG2 		MUX-1
+	assign SS4BEG2 = NN4END13;
+// switch matrix multiplexer  SS4BEG3 		MUX-1
+	assign SS4BEG3 = NN4END12;
+// switch matrix multiplexer  SS4BEG4 		MUX-1
+	assign SS4BEG4 = NN4END11;
+// switch matrix multiplexer  SS4BEG5 		MUX-1
+	assign SS4BEG5 = NN4END10;
+// switch matrix multiplexer  SS4BEG6 		MUX-1
+	assign SS4BEG6 = NN4END9;
+// switch matrix multiplexer  SS4BEG7 		MUX-1
+	assign SS4BEG7 = NN4END8;
+// switch matrix multiplexer  SS4BEG8 		MUX-1
+	assign SS4BEG8 = NN4END7;
+// switch matrix multiplexer  SS4BEG9 		MUX-1
+	assign SS4BEG9 = NN4END6;
+// switch matrix multiplexer  SS4BEG10 		MUX-1
+	assign SS4BEG10 = NN4END5;
+// switch matrix multiplexer  SS4BEG11 		MUX-1
+	assign SS4BEG11 = NN4END4;
+// switch matrix multiplexer  SS4BEG12 		MUX-1
+	assign SS4BEG12 = NN4END3;
+// switch matrix multiplexer  SS4BEG13 		MUX-1
+	assign SS4BEG13 = NN4END2;
+// switch matrix multiplexer  SS4BEG14 		MUX-1
+	assign SS4BEG14 = NN4END1;
+// switch matrix multiplexer  SS4BEG15 		MUX-1
+	assign SS4BEG15 = NN4END0;
+// switch matrix multiplexer  E1BEG0 		MUX-1
+	assign E1BEG0 = W1END3;
+// switch matrix multiplexer  E1BEG1 		MUX-1
+	assign E1BEG1 = W1END2;
+// switch matrix multiplexer  E1BEG2 		MUX-1
+	assign E1BEG2 = W1END1;
+// switch matrix multiplexer  E1BEG3 		MUX-1
+	assign E1BEG3 = W1END0;
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = OPB_O0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = W2MID6;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = W2MID5;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = OPB_O1;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = OPB_O2;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = W2MID2;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = W2MID1;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = OPB_O3;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = OPA_O0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = W2END6;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = W2END5;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = OPA_O1;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = OPA_O2;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = W2END2;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = W2END1;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = OPA_O3;
+// switch matrix multiplexer  EE4BEG0 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG0
+// switch matrix multiplexer  EE4BEG1 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG1
+// switch matrix multiplexer  EE4BEG2 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG2
+// switch matrix multiplexer  EE4BEG3 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG3
+// switch matrix multiplexer  EE4BEG4 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG4
+// switch matrix multiplexer  EE4BEG5 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG5
+// switch matrix multiplexer  EE4BEG6 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG6
+// switch matrix multiplexer  EE4BEG7 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG7
+// switch matrix multiplexer  EE4BEG8 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG8
+// switch matrix multiplexer  EE4BEG9 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG9
+// switch matrix multiplexer  EE4BEG10 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG10
+// switch matrix multiplexer  EE4BEG11 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG11
+// switch matrix multiplexer  EE4BEG12 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG12
+// switch matrix multiplexer  EE4BEG13 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG13
+// switch matrix multiplexer  EE4BEG14 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG14
+// switch matrix multiplexer  EE4BEG15 		MUX-0
+// WARNING unused multiplexer MUX-EE4BEG15
+// switch matrix multiplexer  E6BEG0 		MUX-1
+	assign E6BEG0 = OPA_O0;
+// switch matrix multiplexer  E6BEG1 		MUX-1
+	assign E6BEG1 = OPA_O1;
+// switch matrix multiplexer  E6BEG2 		MUX-1
+	assign E6BEG2 = OPB_O0;
+// switch matrix multiplexer  E6BEG3 		MUX-1
+	assign E6BEG3 = OPB_O1;
+// switch matrix multiplexer  E6BEG4 		MUX-1
+	assign E6BEG4 = GND0;
+// switch matrix multiplexer  E6BEG5 		MUX-1
+	assign E6BEG5 = GND0;
+// switch matrix multiplexer  E6BEG6 		MUX-1
+	assign E6BEG6 = OPA_O2;
+// switch matrix multiplexer  E6BEG7 		MUX-1
+	assign E6BEG7 = OPA_O3;
+// switch matrix multiplexer  E6BEG8 		MUX-1
+	assign E6BEG8 = OPB_O2;
+// switch matrix multiplexer  E6BEG9 		MUX-1
+	assign E6BEG9 = OPB_O3;
+// switch matrix multiplexer  E6BEG10 		MUX-1
+	assign E6BEG10 = GND0;
+// switch matrix multiplexer  E6BEG11 		MUX-1
+	assign E6BEG11 = GND0;
+// switch matrix multiplexer  RES0_I0 		MUX-1
+	assign RES0_I0 = W6END0;
+// switch matrix multiplexer  RES0_I1 		MUX-1
+	assign RES0_I1 = W6END1;
+// switch matrix multiplexer  RES0_I2 		MUX-1
+	assign RES0_I2 = W6END2;
+// switch matrix multiplexer  RES0_I3 		MUX-1
+	assign RES0_I3 = W6END3;
+// switch matrix multiplexer  RES1_I0 		MUX-1
+	assign RES1_I0 = W6END4;
+// switch matrix multiplexer  RES1_I1 		MUX-1
+	assign RES1_I1 = W6END5;
+// switch matrix multiplexer  RES1_I2 		MUX-1
+	assign RES1_I2 = W6END6;
+// switch matrix multiplexer  RES1_I3 		MUX-1
+	assign RES1_I3 = W6END7;
+// switch matrix multiplexer  RES2_I0 		MUX-1
+	assign RES2_I0 = W6END8;
+// switch matrix multiplexer  RES2_I1 		MUX-1
+	assign RES2_I1 = W6END9;
+// switch matrix multiplexer  RES2_I2 		MUX-1
+	assign RES2_I2 = W6END10;
+// switch matrix multiplexer  RES2_I3 		MUX-1
+	assign RES2_I3 = W6END11;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_bot_tile.v b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_tile.v
new file mode 100644
index 0000000..9469d67
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_bot_tile.v
@@ -0,0 +1,939 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_CPU_IO_bot (N1END, N2MID, N2END, N4END, NN4END, Ci, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, W1END, W2MID, W2END, WW4END, W6END, OPA_I0, OPA_I1, OPA_I2, OPA_I3, UserCLK, OPB_I0, OPB_I1, OPB_I2, OPB_I3, RES0_O0, RES0_O1, RES0_O2, RES0_O3, RES1_O0, RES1_O1, RES1_O2, RES1_O3, RES2_O0, RES2_O1, RES2_O2, RES2_O3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	//  NORTH
+	input [3:0] N1END; //wires:4 X_offset:0 Y_offset:1  source_name:NULL destination_name:N1END  
+	input [7:0] N2MID; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2MID  
+	input [7:0] N2END; //wires:8 X_offset:0 Y_offset:1  source_name:NULL destination_name:N2END  
+	input [15:0] N4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:N4END  
+	input [15:0] NN4END; //wires:4 X_offset:0 Y_offset:4  source_name:NULL destination_name:NN4END  
+	input [0:0] Ci; //wires:1 X_offset:0 Y_offset:1  source_name:NULL destination_name:Ci  
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:NULL  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:NULL  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:NULL  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:NULL  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:NULL  
+	//  SOUTH
+	output [3:0] S1BEG; //wires:4 X_offset:0 Y_offset:-1  source_name:S1BEG destination_name:NULL  
+	output [7:0] S2BEG; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEG destination_name:NULL  
+	output [7:0] S2BEGb; //wires:8 X_offset:0 Y_offset:-1  source_name:S2BEGb destination_name:NULL  
+	output [15:0] S4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:S4BEG destination_name:NULL  
+	output [15:0] SS4BEG; //wires:4 X_offset:0 Y_offset:-4  source_name:SS4BEG destination_name:NULL  
+	//  WEST
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:NULL destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:NULL destination_name:W6END  
+	// Tile IO ports from BELs
+	input OPA_I0;
+	input OPA_I1;
+	input OPA_I2;
+	input OPA_I3;
+	input UserCLK;
+	input OPB_I0;
+	input OPB_I1;
+	input OPB_I2;
+	input OPB_I3;
+	output RES0_O0;
+	output RES0_O1;
+	output RES0_O2;
+	output RES0_O3;
+	output RES1_O0;
+	output RES1_O1;
+	output RES1_O2;
+	output RES1_O3;
+	output RES2_O0;
+	output RES2_O1;
+	output RES2_O2;
+	output RES2_O3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire RES0_I0;
+	wire RES0_I1;
+	wire RES0_I2;
+	wire RES0_I3;
+	wire RES1_I0;
+	wire RES1_I1;
+	wire RES1_I2;
+	wire RES1_I3;
+	wire RES2_I0;
+	wire RES2_I1;
+	wire RES2_I2;
+	wire RES2_I3;
+	wire OPA_O0;
+	wire OPA_O1;
+	wire OPA_O2;
+	wire OPA_O3;
+	wire OPB_O0;
+	wire OPB_O1;
+	wire OPB_O2;
+	wire OPB_O3;
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	W_CPU_IO_bot_ConfigMem Inst_W_CPU_IO_bot_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	InPass4_frame_config Inst_OPA_InPass4_frame_config (
+	.O0(OPA_O0),
+	.O1(OPA_O1),
+	.O2(OPA_O2),
+	.O3(OPA_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPA_I0),
+	.I1(OPA_I1),
+	.I2(OPA_I2),
+	.I3(OPA_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	InPass4_frame_config Inst_OPB_InPass4_frame_config (
+	.O0(OPB_O0),
+	.O1(OPB_O1),
+	.O2(OPB_O2),
+	.O3(OPB_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPB_I0),
+	.I1(OPB_I1),
+	.I2(OPB_I2),
+	.I3(OPB_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+	OutPass4_frame_config Inst_RES0_OutPass4_frame_config (
+	.I0(RES0_I0),
+	.I1(RES0_I1),
+	.I2(RES0_I2),
+	.I3(RES0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES0_O0),
+	.O1(RES0_O1),
+	.O2(RES0_O2),
+	.O3(RES0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[12-1:8])
+	);
+
+	OutPass4_frame_config Inst_RES1_OutPass4_frame_config (
+	.I0(RES1_I0),
+	.I1(RES1_I1),
+	.I2(RES1_I2),
+	.I3(RES1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES1_O0),
+	.O1(RES1_O1),
+	.O2(RES1_O2),
+	.O3(RES1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[16-1:12])
+	);
+
+	OutPass4_frame_config Inst_RES2_OutPass4_frame_config (
+	.I0(RES2_I0),
+	.I1(RES2_I1),
+	.I2(RES2_I2),
+	.I3(RES2_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES2_O0),
+	.O1(RES2_O1),
+	.O2(RES2_O2),
+	.O3(RES2_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[20-1:16])
+	);
+
+
+//switch matrix component instantiation
+	W_CPU_IO_bot_switch_matrix Inst_W_CPU_IO_bot_switch_matrix (
+	.N1END0(N1END[0]),
+	.N1END1(N1END[1]),
+	.N1END2(N1END[2]),
+	.N1END3(N1END[3]),
+	.N2MID0(N2MID[0]),
+	.N2MID1(N2MID[1]),
+	.N2MID2(N2MID[2]),
+	.N2MID3(N2MID[3]),
+	.N2MID4(N2MID[4]),
+	.N2MID5(N2MID[5]),
+	.N2MID6(N2MID[6]),
+	.N2MID7(N2MID[7]),
+	.N2END0(N2END[0]),
+	.N2END1(N2END[1]),
+	.N2END2(N2END[2]),
+	.N2END3(N2END[3]),
+	.N2END4(N2END[4]),
+	.N2END5(N2END[5]),
+	.N2END6(N2END[6]),
+	.N2END7(N2END[7]),
+	.N4END0(N4END[0]),
+	.N4END1(N4END[1]),
+	.N4END2(N4END[2]),
+	.N4END3(N4END[3]),
+	.N4END4(N4END[4]),
+	.N4END5(N4END[5]),
+	.N4END6(N4END[6]),
+	.N4END7(N4END[7]),
+	.N4END8(N4END[8]),
+	.N4END9(N4END[9]),
+	.N4END10(N4END[10]),
+	.N4END11(N4END[11]),
+	.N4END12(N4END[12]),
+	.N4END13(N4END[13]),
+	.N4END14(N4END[14]),
+	.N4END15(N4END[15]),
+	.NN4END0(NN4END[0]),
+	.NN4END1(NN4END[1]),
+	.NN4END2(NN4END[2]),
+	.NN4END3(NN4END[3]),
+	.NN4END4(NN4END[4]),
+	.NN4END5(NN4END[5]),
+	.NN4END6(NN4END[6]),
+	.NN4END7(NN4END[7]),
+	.NN4END8(NN4END[8]),
+	.NN4END9(NN4END[9]),
+	.NN4END10(NN4END[10]),
+	.NN4END11(NN4END[11]),
+	.NN4END12(NN4END[12]),
+	.NN4END13(NN4END[13]),
+	.NN4END14(NN4END[14]),
+	.NN4END15(NN4END[15]),
+	.Ci0(Ci[0]),
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.WW4END4(WW4END[4]),
+	.WW4END5(WW4END[5]),
+	.WW4END6(WW4END[6]),
+	.WW4END7(WW4END[7]),
+	.WW4END8(WW4END[8]),
+	.WW4END9(WW4END[9]),
+	.WW4END10(WW4END[10]),
+	.WW4END11(WW4END[11]),
+	.WW4END12(WW4END[12]),
+	.WW4END13(WW4END[13]),
+	.WW4END14(WW4END[14]),
+	.WW4END15(WW4END[15]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.W6END2(W6END[2]),
+	.W6END3(W6END[3]),
+	.W6END4(W6END[4]),
+	.W6END5(W6END[5]),
+	.W6END6(W6END[6]),
+	.W6END7(W6END[7]),
+	.W6END8(W6END[8]),
+	.W6END9(W6END[9]),
+	.W6END10(W6END[10]),
+	.W6END11(W6END[11]),
+	.OPA_O0(OPA_O0),
+	.OPA_O1(OPA_O1),
+	.OPA_O2(OPA_O2),
+	.OPA_O3(OPA_O3),
+	.OPB_O0(OPB_O0),
+	.OPB_O1(OPB_O1),
+	.OPB_O2(OPB_O2),
+	.OPB_O3(OPB_O3),
+	.S1BEG0(S1BEG[0]),
+	.S1BEG1(S1BEG[1]),
+	.S1BEG2(S1BEG[2]),
+	.S1BEG3(S1BEG[3]),
+	.S2BEG0(S2BEG[0]),
+	.S2BEG1(S2BEG[1]),
+	.S2BEG2(S2BEG[2]),
+	.S2BEG3(S2BEG[3]),
+	.S2BEG4(S2BEG[4]),
+	.S2BEG5(S2BEG[5]),
+	.S2BEG6(S2BEG[6]),
+	.S2BEG7(S2BEG[7]),
+	.S2BEGb0(S2BEGb[0]),
+	.S2BEGb1(S2BEGb[1]),
+	.S2BEGb2(S2BEGb[2]),
+	.S2BEGb3(S2BEGb[3]),
+	.S2BEGb4(S2BEGb[4]),
+	.S2BEGb5(S2BEGb[5]),
+	.S2BEGb6(S2BEGb[6]),
+	.S2BEGb7(S2BEGb[7]),
+	.S4BEG0(S4BEG[0]),
+	.S4BEG1(S4BEG[1]),
+	.S4BEG2(S4BEG[2]),
+	.S4BEG3(S4BEG[3]),
+	.S4BEG4(S4BEG[4]),
+	.S4BEG5(S4BEG[5]),
+	.S4BEG6(S4BEG[6]),
+	.S4BEG7(S4BEG[7]),
+	.S4BEG8(S4BEG[8]),
+	.S4BEG9(S4BEG[9]),
+	.S4BEG10(S4BEG[10]),
+	.S4BEG11(S4BEG[11]),
+	.S4BEG12(S4BEG[12]),
+	.S4BEG13(S4BEG[13]),
+	.S4BEG14(S4BEG[14]),
+	.S4BEG15(S4BEG[15]),
+	.SS4BEG0(SS4BEG[0]),
+	.SS4BEG1(SS4BEG[1]),
+	.SS4BEG2(SS4BEG[2]),
+	.SS4BEG3(SS4BEG[3]),
+	.SS4BEG4(SS4BEG[4]),
+	.SS4BEG5(SS4BEG[5]),
+	.SS4BEG6(SS4BEG[6]),
+	.SS4BEG7(SS4BEG[7]),
+	.SS4BEG8(SS4BEG[8]),
+	.SS4BEG9(SS4BEG[9]),
+	.SS4BEG10(SS4BEG[10]),
+	.SS4BEG11(SS4BEG[11]),
+	.SS4BEG12(SS4BEG[12]),
+	.SS4BEG13(SS4BEG[13]),
+	.SS4BEG14(SS4BEG[14]),
+	.SS4BEG15(SS4BEG[15]),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[0]),
+	.EE4BEG1(EE4BEG[1]),
+	.EE4BEG2(EE4BEG[2]),
+	.EE4BEG3(EE4BEG[3]),
+	.EE4BEG4(EE4BEG[4]),
+	.EE4BEG5(EE4BEG[5]),
+	.EE4BEG6(EE4BEG[6]),
+	.EE4BEG7(EE4BEG[7]),
+	.EE4BEG8(EE4BEG[8]),
+	.EE4BEG9(EE4BEG[9]),
+	.EE4BEG10(EE4BEG[10]),
+	.EE4BEG11(EE4BEG[11]),
+	.EE4BEG12(EE4BEG[12]),
+	.EE4BEG13(EE4BEG[13]),
+	.EE4BEG14(EE4BEG[14]),
+	.EE4BEG15(EE4BEG[15]),
+	.E6BEG0(E6BEG[0]),
+	.E6BEG1(E6BEG[1]),
+	.E6BEG2(E6BEG[2]),
+	.E6BEG3(E6BEG[3]),
+	.E6BEG4(E6BEG[4]),
+	.E6BEG5(E6BEG[5]),
+	.E6BEG6(E6BEG[6]),
+	.E6BEG7(E6BEG[7]),
+	.E6BEG8(E6BEG[8]),
+	.E6BEG9(E6BEG[9]),
+	.E6BEG10(E6BEG[10]),
+	.E6BEG11(E6BEG[11]),
+	.RES0_I0(RES0_I0),
+	.RES0_I1(RES0_I1),
+	.RES0_I2(RES0_I2),
+	.RES0_I3(RES0_I3),
+	.RES1_I0(RES1_I0),
+	.RES1_I1(RES1_I1),
+	.RES1_I2(RES1_I2),
+	.RES1_I3(RES1_I3),
+	.RES2_I0(RES2_I0),
+	.RES2_I1(RES2_I1),
+	.RES2_I2(RES2_I2),
+	.RES2_I3(RES2_I3)
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/W_CPU_IO_switch_matrix.v
new file mode 100644
index 0000000..851f85c
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_switch_matrix.v
@@ -0,0 +1,333 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:0
+module W_CPU_IO_switch_matrix (W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, WW4END4, WW4END5, WW4END6, WW4END7, WW4END8, WW4END9, WW4END10, WW4END11, WW4END12, WW4END13, WW4END14, WW4END15, W6END0, W6END1, W6END2, W6END3, W6END4, W6END5, W6END6, W6END7, W6END8, W6END9, W6END10, W6END11, OPA_O0, OPA_O1, OPA_O2, OPA_O3, OPB_O0, OPB_O1, OPB_O2, OPB_O3, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, EE4BEG4, EE4BEG5, EE4BEG6, EE4BEG7, EE4BEG8, EE4BEG9, EE4BEG10, EE4BEG11, EE4BEG12, EE4BEG13, EE4BEG14, EE4BEG15, E6BEG0, E6BEG1, E6BEG2, E6BEG3, E6BEG4, E6BEG5, E6BEG6, E6BEG7, E6BEG8, E6BEG9, E6BEG10, E6BEG11, RES0_I0, RES0_I1, RES0_I2, RES0_I3, RES1_I0, RES1_I1, RES1_I2, RES1_I3, RES2_I0, RES2_I1, RES2_I2, RES2_I3);
+	parameter NoConfigBits = 0;
+	 // switch matrix inputs
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input WW4END4;
+	input WW4END5;
+	input WW4END6;
+	input WW4END7;
+	input WW4END8;
+	input WW4END9;
+	input WW4END10;
+	input WW4END11;
+	input WW4END12;
+	input WW4END13;
+	input WW4END14;
+	input WW4END15;
+	input W6END0;
+	input W6END1;
+	input W6END2;
+	input W6END3;
+	input W6END4;
+	input W6END5;
+	input W6END6;
+	input W6END7;
+	input W6END8;
+	input W6END9;
+	input W6END10;
+	input W6END11;
+	input OPA_O0;
+	input OPA_O1;
+	input OPA_O2;
+	input OPA_O3;
+	input OPB_O0;
+	input OPB_O1;
+	input OPB_O2;
+	input OPB_O3;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output EE4BEG4;
+	output EE4BEG5;
+	output EE4BEG6;
+	output EE4BEG7;
+	output EE4BEG8;
+	output EE4BEG9;
+	output EE4BEG10;
+	output EE4BEG11;
+	output EE4BEG12;
+	output EE4BEG13;
+	output EE4BEG14;
+	output EE4BEG15;
+	output E6BEG0;
+	output E6BEG1;
+	output E6BEG2;
+	output E6BEG3;
+	output E6BEG4;
+	output E6BEG5;
+	output E6BEG6;
+	output E6BEG7;
+	output E6BEG8;
+	output E6BEG9;
+	output E6BEG10;
+	output E6BEG11;
+	output RES0_I0;
+	output RES0_I1;
+	output RES0_I2;
+	output RES0_I3;
+	output RES1_I0;
+	output RES1_I1;
+	output RES1_I2;
+	output RES1_I3;
+	output RES2_I0;
+	output RES2_I1;
+	output RES2_I2;
+	output RES2_I3;
+	//global
+
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [1-1:0] E1BEG0_input;
+	wire [1-1:0] E1BEG1_input;
+	wire [1-1:0] E1BEG2_input;
+	wire [1-1:0] E1BEG3_input;
+	wire [1-1:0] E2BEG0_input;
+	wire [1-1:0] E2BEG1_input;
+	wire [1-1:0] E2BEG2_input;
+	wire [1-1:0] E2BEG3_input;
+	wire [1-1:0] E2BEG4_input;
+	wire [1-1:0] E2BEG5_input;
+	wire [1-1:0] E2BEG6_input;
+	wire [1-1:0] E2BEG7_input;
+	wire [1-1:0] E2BEGb0_input;
+	wire [1-1:0] E2BEGb1_input;
+	wire [1-1:0] E2BEGb2_input;
+	wire [1-1:0] E2BEGb3_input;
+	wire [1-1:0] E2BEGb4_input;
+	wire [1-1:0] E2BEGb5_input;
+	wire [1-1:0] E2BEGb6_input;
+	wire [1-1:0] E2BEGb7_input;
+	wire [1-1:0] EE4BEG0_input;
+	wire [1-1:0] EE4BEG1_input;
+	wire [1-1:0] EE4BEG2_input;
+	wire [1-1:0] EE4BEG3_input;
+	wire [1-1:0] EE4BEG4_input;
+	wire [1-1:0] EE4BEG5_input;
+	wire [1-1:0] EE4BEG6_input;
+	wire [1-1:0] EE4BEG7_input;
+	wire [1-1:0] EE4BEG8_input;
+	wire [1-1:0] EE4BEG9_input;
+	wire [1-1:0] EE4BEG10_input;
+	wire [1-1:0] EE4BEG11_input;
+	wire [1-1:0] EE4BEG12_input;
+	wire [1-1:0] EE4BEG13_input;
+	wire [1-1:0] EE4BEG14_input;
+	wire [1-1:0] EE4BEG15_input;
+	wire [1-1:0] E6BEG0_input;
+	wire [1-1:0] E6BEG1_input;
+	wire [1-1:0] E6BEG2_input;
+	wire [1-1:0] E6BEG3_input;
+	wire [1-1:0] E6BEG4_input;
+	wire [1-1:0] E6BEG5_input;
+	wire [1-1:0] E6BEG6_input;
+	wire [1-1:0] E6BEG7_input;
+	wire [1-1:0] E6BEG8_input;
+	wire [1-1:0] E6BEG9_input;
+	wire [1-1:0] E6BEG10_input;
+	wire [1-1:0] E6BEG11_input;
+	wire [1-1:0] RES0_I0_input;
+	wire [1-1:0] RES0_I1_input;
+	wire [1-1:0] RES0_I2_input;
+	wire [1-1:0] RES0_I3_input;
+	wire [1-1:0] RES1_I0_input;
+	wire [1-1:0] RES1_I1_input;
+	wire [1-1:0] RES1_I2_input;
+	wire [1-1:0] RES1_I3_input;
+	wire [1-1:0] RES2_I0_input;
+	wire [1-1:0] RES2_I1_input;
+	wire [1-1:0] RES2_I2_input;
+	wire [1-1:0] RES2_I3_input;
+
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  E1BEG0 		MUX-1
+	assign E1BEG0 = W1END3;
+// switch matrix multiplexer  E1BEG1 		MUX-1
+	assign E1BEG1 = W1END2;
+// switch matrix multiplexer  E1BEG2 		MUX-1
+	assign E1BEG2 = W1END1;
+// switch matrix multiplexer  E1BEG3 		MUX-1
+	assign E1BEG3 = W1END0;
+// switch matrix multiplexer  E2BEG0 		MUX-1
+	assign E2BEG0 = OPB_O0;
+// switch matrix multiplexer  E2BEG1 		MUX-1
+	assign E2BEG1 = W2MID6;
+// switch matrix multiplexer  E2BEG2 		MUX-1
+	assign E2BEG2 = W2MID5;
+// switch matrix multiplexer  E2BEG3 		MUX-1
+	assign E2BEG3 = OPB_O1;
+// switch matrix multiplexer  E2BEG4 		MUX-1
+	assign E2BEG4 = OPB_O2;
+// switch matrix multiplexer  E2BEG5 		MUX-1
+	assign E2BEG5 = W2MID2;
+// switch matrix multiplexer  E2BEG6 		MUX-1
+	assign E2BEG6 = W2MID1;
+// switch matrix multiplexer  E2BEG7 		MUX-1
+	assign E2BEG7 = OPB_O3;
+// switch matrix multiplexer  E2BEGb0 		MUX-1
+	assign E2BEGb0 = OPA_O0;
+// switch matrix multiplexer  E2BEGb1 		MUX-1
+	assign E2BEGb1 = W2END6;
+// switch matrix multiplexer  E2BEGb2 		MUX-1
+	assign E2BEGb2 = W2END5;
+// switch matrix multiplexer  E2BEGb3 		MUX-1
+	assign E2BEGb3 = OPA_O1;
+// switch matrix multiplexer  E2BEGb4 		MUX-1
+	assign E2BEGb4 = OPA_O2;
+// switch matrix multiplexer  E2BEGb5 		MUX-1
+	assign E2BEGb5 = W2END2;
+// switch matrix multiplexer  E2BEGb6 		MUX-1
+	assign E2BEGb6 = W2END1;
+// switch matrix multiplexer  E2BEGb7 		MUX-1
+	assign E2BEGb7 = OPA_O3;
+// switch matrix multiplexer  EE4BEG0 		MUX-1
+	assign EE4BEG0 = WW4END15;
+// switch matrix multiplexer  EE4BEG1 		MUX-1
+	assign EE4BEG1 = WW4END14;
+// switch matrix multiplexer  EE4BEG2 		MUX-1
+	assign EE4BEG2 = WW4END13;
+// switch matrix multiplexer  EE4BEG3 		MUX-1
+	assign EE4BEG3 = WW4END12;
+// switch matrix multiplexer  EE4BEG4 		MUX-1
+	assign EE4BEG4 = WW4END11;
+// switch matrix multiplexer  EE4BEG5 		MUX-1
+	assign EE4BEG5 = WW4END10;
+// switch matrix multiplexer  EE4BEG6 		MUX-1
+	assign EE4BEG6 = WW4END9;
+// switch matrix multiplexer  EE4BEG7 		MUX-1
+	assign EE4BEG7 = WW4END8;
+// switch matrix multiplexer  EE4BEG8 		MUX-1
+	assign EE4BEG8 = WW4END7;
+// switch matrix multiplexer  EE4BEG9 		MUX-1
+	assign EE4BEG9 = WW4END6;
+// switch matrix multiplexer  EE4BEG10 		MUX-1
+	assign EE4BEG10 = WW4END5;
+// switch matrix multiplexer  EE4BEG11 		MUX-1
+	assign EE4BEG11 = WW4END4;
+// switch matrix multiplexer  EE4BEG12 		MUX-1
+	assign EE4BEG12 = WW4END3;
+// switch matrix multiplexer  EE4BEG13 		MUX-1
+	assign EE4BEG13 = WW4END2;
+// switch matrix multiplexer  EE4BEG14 		MUX-1
+	assign EE4BEG14 = WW4END1;
+// switch matrix multiplexer  EE4BEG15 		MUX-1
+	assign EE4BEG15 = WW4END0;
+// switch matrix multiplexer  E6BEG0 		MUX-1
+	assign E6BEG0 = OPA_O0;
+// switch matrix multiplexer  E6BEG1 		MUX-1
+	assign E6BEG1 = OPA_O1;
+// switch matrix multiplexer  E6BEG2 		MUX-1
+	assign E6BEG2 = OPB_O0;
+// switch matrix multiplexer  E6BEG3 		MUX-1
+	assign E6BEG3 = OPB_O1;
+// switch matrix multiplexer  E6BEG4 		MUX-1
+	assign E6BEG4 = GND0;
+// switch matrix multiplexer  E6BEG5 		MUX-1
+	assign E6BEG5 = GND0;
+// switch matrix multiplexer  E6BEG6 		MUX-1
+	assign E6BEG6 = OPA_O2;
+// switch matrix multiplexer  E6BEG7 		MUX-1
+	assign E6BEG7 = OPA_O3;
+// switch matrix multiplexer  E6BEG8 		MUX-1
+	assign E6BEG8 = OPB_O2;
+// switch matrix multiplexer  E6BEG9 		MUX-1
+	assign E6BEG9 = OPB_O3;
+// switch matrix multiplexer  E6BEG10 		MUX-1
+	assign E6BEG10 = GND0;
+// switch matrix multiplexer  E6BEG11 		MUX-1
+	assign E6BEG11 = GND0;
+// switch matrix multiplexer  RES0_I0 		MUX-1
+	assign RES0_I0 = W6END0;
+// switch matrix multiplexer  RES0_I1 		MUX-1
+	assign RES0_I1 = W6END1;
+// switch matrix multiplexer  RES0_I2 		MUX-1
+	assign RES0_I2 = W6END2;
+// switch matrix multiplexer  RES0_I3 		MUX-1
+	assign RES0_I3 = W6END3;
+// switch matrix multiplexer  RES1_I0 		MUX-1
+	assign RES1_I0 = W6END4;
+// switch matrix multiplexer  RES1_I1 		MUX-1
+	assign RES1_I1 = W6END5;
+// switch matrix multiplexer  RES1_I2 		MUX-1
+	assign RES1_I2 = W6END6;
+// switch matrix multiplexer  RES1_I3 		MUX-1
+	assign RES1_I3 = W6END7;
+// switch matrix multiplexer  RES2_I0 		MUX-1
+	assign RES2_I0 = W6END8;
+// switch matrix multiplexer  RES2_I1 		MUX-1
+	assign RES2_I1 = W6END9;
+// switch matrix multiplexer  RES2_I2 		MUX-1
+	assign RES2_I2 = W6END10;
+// switch matrix multiplexer  RES2_I3 		MUX-1
+	assign RES2_I3 = W6END11;
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_CPU_IO_tile.v b/verilog/rtl/eFPGA_core/W_CPU_IO_tile.v
new file mode 100644
index 0000000..8355546
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_CPU_IO_tile.v
@@ -0,0 +1,823 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_CPU_IO (E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, W1END, W2MID, W2END, WW4END, W6END, OPA_I0, OPA_I1, OPA_I2, OPA_I3, UserCLK, OPB_I0, OPB_I1, OPB_I2, OPB_I3, RES0_O0, RES0_O1, RES0_O2, RES0_O3, RES1_O0, RES1_O1, RES1_O2, RES1_O3, RES2_O0, RES2_O1, RES2_O2, RES2_O3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 20;
+	//  NORTH
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:NULL  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:NULL  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:NULL  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:NULL  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:NULL  
+	//  SOUTH
+	//  WEST
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:NULL destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:NULL destination_name:W6END  
+	// Tile IO ports from BELs
+	input OPA_I0;
+	input OPA_I1;
+	input OPA_I2;
+	input OPA_I3;
+	input UserCLK;
+	input OPB_I0;
+	input OPB_I1;
+	input OPB_I2;
+	input OPB_I3;
+	output RES0_O0;
+	output RES0_O1;
+	output RES0_O2;
+	output RES0_O3;
+	output RES1_O0;
+	output RES1_O1;
+	output RES1_O2;
+	output RES1_O3;
+	output RES2_O0;
+	output RES2_O1;
+	output RES2_O2;
+	output RES2_O3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire RES0_I0;
+	wire RES0_I1;
+	wire RES0_I2;
+	wire RES0_I3;
+	wire RES1_I0;
+	wire RES1_I1;
+	wire RES1_I2;
+	wire RES1_I3;
+	wire RES2_I0;
+	wire RES2_I1;
+	wire RES2_I2;
+	wire RES2_I3;
+	wire OPA_O0;
+	wire OPA_O1;
+	wire OPA_O2;
+	wire OPA_O3;
+	wire OPB_O0;
+	wire OPB_O1;
+	wire OPB_O2;
+	wire OPB_O3;
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	W_CPU_IO_ConfigMem Inst_W_CPU_IO_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	InPass4_frame_config Inst_OPA_InPass4_frame_config (
+	.O0(OPA_O0),
+	.O1(OPA_O1),
+	.O2(OPA_O2),
+	.O3(OPA_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPA_I0),
+	.I1(OPA_I1),
+	.I2(OPA_I2),
+	.I3(OPA_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	InPass4_frame_config Inst_OPB_InPass4_frame_config (
+	.O0(OPB_O0),
+	.O1(OPB_O1),
+	.O2(OPB_O2),
+	.O3(OPB_O3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I0(OPB_I0),
+	.I1(OPB_I1),
+	.I2(OPB_I2),
+	.I3(OPB_I3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+	OutPass4_frame_config Inst_RES0_OutPass4_frame_config (
+	.I0(RES0_I0),
+	.I1(RES0_I1),
+	.I2(RES0_I2),
+	.I3(RES0_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES0_O0),
+	.O1(RES0_O1),
+	.O2(RES0_O2),
+	.O3(RES0_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[12-1:8])
+	);
+
+	OutPass4_frame_config Inst_RES1_OutPass4_frame_config (
+	.I0(RES1_I0),
+	.I1(RES1_I1),
+	.I2(RES1_I2),
+	.I3(RES1_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES1_O0),
+	.O1(RES1_O1),
+	.O2(RES1_O2),
+	.O3(RES1_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[16-1:12])
+	);
+
+	OutPass4_frame_config Inst_RES2_OutPass4_frame_config (
+	.I0(RES2_I0),
+	.I1(RES2_I1),
+	.I2(RES2_I2),
+	.I3(RES2_I3),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.O0(RES2_O0),
+	.O1(RES2_O1),
+	.O2(RES2_O2),
+	.O3(RES2_O3),
+	.UserCLK(UserCLK),
+	.ConfigBits(ConfigBits[20-1:16])
+	);
+
+
+//switch matrix component instantiation
+	W_CPU_IO_switch_matrix Inst_W_CPU_IO_switch_matrix (
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.WW4END4(WW4END[4]),
+	.WW4END5(WW4END[5]),
+	.WW4END6(WW4END[6]),
+	.WW4END7(WW4END[7]),
+	.WW4END8(WW4END[8]),
+	.WW4END9(WW4END[9]),
+	.WW4END10(WW4END[10]),
+	.WW4END11(WW4END[11]),
+	.WW4END12(WW4END[12]),
+	.WW4END13(WW4END[13]),
+	.WW4END14(WW4END[14]),
+	.WW4END15(WW4END[15]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.W6END2(W6END[2]),
+	.W6END3(W6END[3]),
+	.W6END4(W6END[4]),
+	.W6END5(W6END[5]),
+	.W6END6(W6END[6]),
+	.W6END7(W6END[7]),
+	.W6END8(W6END[8]),
+	.W6END9(W6END[9]),
+	.W6END10(W6END[10]),
+	.W6END11(W6END[11]),
+	.OPA_O0(OPA_O0),
+	.OPA_O1(OPA_O1),
+	.OPA_O2(OPA_O2),
+	.OPA_O3(OPA_O3),
+	.OPB_O0(OPB_O0),
+	.OPB_O1(OPB_O1),
+	.OPB_O2(OPB_O2),
+	.OPB_O3(OPB_O3),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[0]),
+	.EE4BEG1(EE4BEG[1]),
+	.EE4BEG2(EE4BEG[2]),
+	.EE4BEG3(EE4BEG[3]),
+	.EE4BEG4(EE4BEG[4]),
+	.EE4BEG5(EE4BEG[5]),
+	.EE4BEG6(EE4BEG[6]),
+	.EE4BEG7(EE4BEG[7]),
+	.EE4BEG8(EE4BEG[8]),
+	.EE4BEG9(EE4BEG[9]),
+	.EE4BEG10(EE4BEG[10]),
+	.EE4BEG11(EE4BEG[11]),
+	.EE4BEG12(EE4BEG[12]),
+	.EE4BEG13(EE4BEG[13]),
+	.EE4BEG14(EE4BEG[14]),
+	.EE4BEG15(EE4BEG[15]),
+	.E6BEG0(E6BEG[0]),
+	.E6BEG1(E6BEG[1]),
+	.E6BEG2(E6BEG[2]),
+	.E6BEG3(E6BEG[3]),
+	.E6BEG4(E6BEG[4]),
+	.E6BEG5(E6BEG[5]),
+	.E6BEG6(E6BEG[6]),
+	.E6BEG7(E6BEG[7]),
+	.E6BEG8(E6BEG[8]),
+	.E6BEG9(E6BEG[9]),
+	.E6BEG10(E6BEG[10]),
+	.E6BEG11(E6BEG[11]),
+	.RES0_I0(RES0_I0),
+	.RES0_I1(RES0_I1),
+	.RES0_I2(RES0_I2),
+	.RES0_I3(RES0_I3),
+	.RES1_I0(RES1_I0),
+	.RES1_I1(RES1_I1),
+	.RES1_I2(RES1_I2),
+	.RES1_I3(RES1_I3),
+	.RES2_I0(RES2_I0),
+	.RES2_I1(RES2_I1),
+	.RES2_I2(RES2_I2),
+	.RES2_I3(RES2_I3)
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_IO_ConfigMem.v b/verilog/rtl/eFPGA_core/W_IO_ConfigMem.v
new file mode 100644
index 0000000..e49fadc
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_IO_ConfigMem.v
@@ -0,0 +1,829 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_IO_ConfigMem (FrameData, FrameStrobe, ConfigBits, ConfigBits_N);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 114;
+	input [FrameBitsPerRow-1:0] FrameData;
+	input [MaxFramesPerCol-1:0] FrameStrobe;
+	output [NoConfigBits-1:0] ConfigBits;
+	output [NoConfigBits-1:0] ConfigBits_N;
+	wire [32-1:0] frame0;
+	wire [32-1:0] frame1;
+	wire [32-1:0] frame2;
+	wire [18-1:0] frame3;
+
+//instantiate frame latches
+	LHQD1 Inst_frame0_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[113]),
+	.QN(ConfigBits_N[113])
+	);
+
+	LHQD1 Inst_frame0_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[112]),
+	.QN(ConfigBits_N[112])
+	);
+
+	LHQD1 Inst_frame0_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[111]),
+	.QN(ConfigBits_N[111])
+	);
+
+	LHQD1 Inst_frame0_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[110]),
+	.QN(ConfigBits_N[110])
+	);
+
+	LHQD1 Inst_frame0_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[109]),
+	.QN(ConfigBits_N[109])
+	);
+
+	LHQD1 Inst_frame0_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[108]),
+	.QN(ConfigBits_N[108])
+	);
+
+	LHQD1 Inst_frame0_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[107]),
+	.QN(ConfigBits_N[107])
+	);
+
+	LHQD1 Inst_frame0_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[106]),
+	.QN(ConfigBits_N[106])
+	);
+
+	LHQD1 Inst_frame0_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[105]),
+	.QN(ConfigBits_N[105])
+	);
+
+	LHQD1 Inst_frame0_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[104]),
+	.QN(ConfigBits_N[104])
+	);
+
+	LHQD1 Inst_frame0_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[103]),
+	.QN(ConfigBits_N[103])
+	);
+
+	LHQD1 Inst_frame0_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[102]),
+	.QN(ConfigBits_N[102])
+	);
+
+	LHQD1 Inst_frame0_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[101]),
+	.QN(ConfigBits_N[101])
+	);
+
+	LHQD1 Inst_frame0_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[100]),
+	.QN(ConfigBits_N[100])
+	);
+
+	LHQD1 Inst_frame0_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[99]),
+	.QN(ConfigBits_N[99])
+	);
+
+	LHQD1 Inst_frame0_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[98]),
+	.QN(ConfigBits_N[98])
+	);
+
+	LHQD1 Inst_frame0_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[97]),
+	.QN(ConfigBits_N[97])
+	);
+
+	LHQD1 Inst_frame0_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[96]),
+	.QN(ConfigBits_N[96])
+	);
+
+	LHQD1 Inst_frame0_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[95]),
+	.QN(ConfigBits_N[95])
+	);
+
+	LHQD1 Inst_frame0_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[94]),
+	.QN(ConfigBits_N[94])
+	);
+
+	LHQD1 Inst_frame0_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[93]),
+	.QN(ConfigBits_N[93])
+	);
+
+	LHQD1 Inst_frame0_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[92]),
+	.QN(ConfigBits_N[92])
+	);
+
+	LHQD1 Inst_frame0_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[91]),
+	.QN(ConfigBits_N[91])
+	);
+
+	LHQD1 Inst_frame0_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[90]),
+	.QN(ConfigBits_N[90])
+	);
+
+	LHQD1 Inst_frame0_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[89]),
+	.QN(ConfigBits_N[89])
+	);
+
+	LHQD1 Inst_frame0_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[88]),
+	.QN(ConfigBits_N[88])
+	);
+
+	LHQD1 Inst_frame0_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[87]),
+	.QN(ConfigBits_N[87])
+	);
+
+	LHQD1 Inst_frame0_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[86]),
+	.QN(ConfigBits_N[86])
+	);
+
+	LHQD1 Inst_frame0_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[85]),
+	.QN(ConfigBits_N[85])
+	);
+
+	LHQD1 Inst_frame0_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[84]),
+	.QN(ConfigBits_N[84])
+	);
+
+	LHQD1 Inst_frame0_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[83]),
+	.QN(ConfigBits_N[83])
+	);
+
+	LHQD1 Inst_frame0_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[0]),
+	.Q(ConfigBits[82]),
+	.QN(ConfigBits_N[82])
+	);
+
+	LHQD1 Inst_frame1_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[81]),
+	.QN(ConfigBits_N[81])
+	);
+
+	LHQD1 Inst_frame1_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[80]),
+	.QN(ConfigBits_N[80])
+	);
+
+	LHQD1 Inst_frame1_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[79]),
+	.QN(ConfigBits_N[79])
+	);
+
+	LHQD1 Inst_frame1_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[78]),
+	.QN(ConfigBits_N[78])
+	);
+
+	LHQD1 Inst_frame1_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[77]),
+	.QN(ConfigBits_N[77])
+	);
+
+	LHQD1 Inst_frame1_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[76]),
+	.QN(ConfigBits_N[76])
+	);
+
+	LHQD1 Inst_frame1_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[75]),
+	.QN(ConfigBits_N[75])
+	);
+
+	LHQD1 Inst_frame1_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[74]),
+	.QN(ConfigBits_N[74])
+	);
+
+	LHQD1 Inst_frame1_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[73]),
+	.QN(ConfigBits_N[73])
+	);
+
+	LHQD1 Inst_frame1_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[72]),
+	.QN(ConfigBits_N[72])
+	);
+
+	LHQD1 Inst_frame1_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[71]),
+	.QN(ConfigBits_N[71])
+	);
+
+	LHQD1 Inst_frame1_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[70]),
+	.QN(ConfigBits_N[70])
+	);
+
+	LHQD1 Inst_frame1_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[69]),
+	.QN(ConfigBits_N[69])
+	);
+
+	LHQD1 Inst_frame1_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[68]),
+	.QN(ConfigBits_N[68])
+	);
+
+	LHQD1 Inst_frame1_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[67]),
+	.QN(ConfigBits_N[67])
+	);
+
+	LHQD1 Inst_frame1_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[66]),
+	.QN(ConfigBits_N[66])
+	);
+
+	LHQD1 Inst_frame1_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[65]),
+	.QN(ConfigBits_N[65])
+	);
+
+	LHQD1 Inst_frame1_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[64]),
+	.QN(ConfigBits_N[64])
+	);
+
+	LHQD1 Inst_frame1_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[63]),
+	.QN(ConfigBits_N[63])
+	);
+
+	LHQD1 Inst_frame1_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[62]),
+	.QN(ConfigBits_N[62])
+	);
+
+	LHQD1 Inst_frame1_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[61]),
+	.QN(ConfigBits_N[61])
+	);
+
+	LHQD1 Inst_frame1_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[60]),
+	.QN(ConfigBits_N[60])
+	);
+
+	LHQD1 Inst_frame1_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[59]),
+	.QN(ConfigBits_N[59])
+	);
+
+	LHQD1 Inst_frame1_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[58]),
+	.QN(ConfigBits_N[58])
+	);
+
+	LHQD1 Inst_frame1_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[57]),
+	.QN(ConfigBits_N[57])
+	);
+
+	LHQD1 Inst_frame1_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[56]),
+	.QN(ConfigBits_N[56])
+	);
+
+	LHQD1 Inst_frame1_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[55]),
+	.QN(ConfigBits_N[55])
+	);
+
+	LHQD1 Inst_frame1_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[54]),
+	.QN(ConfigBits_N[54])
+	);
+
+	LHQD1 Inst_frame1_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[53]),
+	.QN(ConfigBits_N[53])
+	);
+
+	LHQD1 Inst_frame1_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[52]),
+	.QN(ConfigBits_N[52])
+	);
+
+	LHQD1 Inst_frame1_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[51]),
+	.QN(ConfigBits_N[51])
+	);
+
+	LHQD1 Inst_frame1_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[1]),
+	.Q(ConfigBits[50]),
+	.QN(ConfigBits_N[50])
+	);
+
+	LHQD1 Inst_frame2_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[49]),
+	.QN(ConfigBits_N[49])
+	);
+
+	LHQD1 Inst_frame2_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[48]),
+	.QN(ConfigBits_N[48])
+	);
+
+	LHQD1 Inst_frame2_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[47]),
+	.QN(ConfigBits_N[47])
+	);
+
+	LHQD1 Inst_frame2_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[46]),
+	.QN(ConfigBits_N[46])
+	);
+
+	LHQD1 Inst_frame2_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[45]),
+	.QN(ConfigBits_N[45])
+	);
+
+	LHQD1 Inst_frame2_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[44]),
+	.QN(ConfigBits_N[44])
+	);
+
+	LHQD1 Inst_frame2_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[43]),
+	.QN(ConfigBits_N[43])
+	);
+
+	LHQD1 Inst_frame2_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[42]),
+	.QN(ConfigBits_N[42])
+	);
+
+	LHQD1 Inst_frame2_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[41]),
+	.QN(ConfigBits_N[41])
+	);
+
+	LHQD1 Inst_frame2_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[40]),
+	.QN(ConfigBits_N[40])
+	);
+
+	LHQD1 Inst_frame2_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[39]),
+	.QN(ConfigBits_N[39])
+	);
+
+	LHQD1 Inst_frame2_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[38]),
+	.QN(ConfigBits_N[38])
+	);
+
+	LHQD1 Inst_frame2_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[37]),
+	.QN(ConfigBits_N[37])
+	);
+
+	LHQD1 Inst_frame2_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[36]),
+	.QN(ConfigBits_N[36])
+	);
+
+	LHQD1 Inst_frame2_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[35]),
+	.QN(ConfigBits_N[35])
+	);
+
+	LHQD1 Inst_frame2_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[34]),
+	.QN(ConfigBits_N[34])
+	);
+
+	LHQD1 Inst_frame2_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[33]),
+	.QN(ConfigBits_N[33])
+	);
+
+	LHQD1 Inst_frame2_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[32]),
+	.QN(ConfigBits_N[32])
+	);
+
+	LHQD1 Inst_frame2_bit13(
+	.D(FrameData[13]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[31]),
+	.QN(ConfigBits_N[31])
+	);
+
+	LHQD1 Inst_frame2_bit12(
+	.D(FrameData[12]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[30]),
+	.QN(ConfigBits_N[30])
+	);
+
+	LHQD1 Inst_frame2_bit11(
+	.D(FrameData[11]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[29]),
+	.QN(ConfigBits_N[29])
+	);
+
+	LHQD1 Inst_frame2_bit10(
+	.D(FrameData[10]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[28]),
+	.QN(ConfigBits_N[28])
+	);
+
+	LHQD1 Inst_frame2_bit9(
+	.D(FrameData[9]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[27]),
+	.QN(ConfigBits_N[27])
+	);
+
+	LHQD1 Inst_frame2_bit8(
+	.D(FrameData[8]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[26]),
+	.QN(ConfigBits_N[26])
+	);
+
+	LHQD1 Inst_frame2_bit7(
+	.D(FrameData[7]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[25]),
+	.QN(ConfigBits_N[25])
+	);
+
+	LHQD1 Inst_frame2_bit6(
+	.D(FrameData[6]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[24]),
+	.QN(ConfigBits_N[24])
+	);
+
+	LHQD1 Inst_frame2_bit5(
+	.D(FrameData[5]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[23]),
+	.QN(ConfigBits_N[23])
+	);
+
+	LHQD1 Inst_frame2_bit4(
+	.D(FrameData[4]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[22]),
+	.QN(ConfigBits_N[22])
+	);
+
+	LHQD1 Inst_frame2_bit3(
+	.D(FrameData[3]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[21]),
+	.QN(ConfigBits_N[21])
+	);
+
+	LHQD1 Inst_frame2_bit2(
+	.D(FrameData[2]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[20]),
+	.QN(ConfigBits_N[20])
+	);
+
+	LHQD1 Inst_frame2_bit1(
+	.D(FrameData[1]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[19]),
+	.QN(ConfigBits_N[19])
+	);
+
+	LHQD1 Inst_frame2_bit0(
+	.D(FrameData[0]),
+	.E(FrameStrobe[2]),
+	.Q(ConfigBits[18]),
+	.QN(ConfigBits_N[18])
+	);
+
+	LHQD1 Inst_frame3_bit31(
+	.D(FrameData[31]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[17]),
+	.QN(ConfigBits_N[17])
+	);
+
+	LHQD1 Inst_frame3_bit30(
+	.D(FrameData[30]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[16]),
+	.QN(ConfigBits_N[16])
+	);
+
+	LHQD1 Inst_frame3_bit29(
+	.D(FrameData[29]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[15]),
+	.QN(ConfigBits_N[15])
+	);
+
+	LHQD1 Inst_frame3_bit28(
+	.D(FrameData[28]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[14]),
+	.QN(ConfigBits_N[14])
+	);
+
+	LHQD1 Inst_frame3_bit27(
+	.D(FrameData[27]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[13]),
+	.QN(ConfigBits_N[13])
+	);
+
+	LHQD1 Inst_frame3_bit26(
+	.D(FrameData[26]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[12]),
+	.QN(ConfigBits_N[12])
+	);
+
+	LHQD1 Inst_frame3_bit25(
+	.D(FrameData[25]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[11]),
+	.QN(ConfigBits_N[11])
+	);
+
+	LHQD1 Inst_frame3_bit24(
+	.D(FrameData[24]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[10]),
+	.QN(ConfigBits_N[10])
+	);
+
+	LHQD1 Inst_frame3_bit23(
+	.D(FrameData[23]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[9]),
+	.QN(ConfigBits_N[9])
+	);
+
+	LHQD1 Inst_frame3_bit22(
+	.D(FrameData[22]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[8]),
+	.QN(ConfigBits_N[8])
+	);
+
+	LHQD1 Inst_frame3_bit21(
+	.D(FrameData[21]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[7]),
+	.QN(ConfigBits_N[7])
+	);
+
+	LHQD1 Inst_frame3_bit20(
+	.D(FrameData[20]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[6]),
+	.QN(ConfigBits_N[6])
+	);
+
+	LHQD1 Inst_frame3_bit19(
+	.D(FrameData[19]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[5]),
+	.QN(ConfigBits_N[5])
+	);
+
+	LHQD1 Inst_frame3_bit18(
+	.D(FrameData[18]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[4]),
+	.QN(ConfigBits_N[4])
+	);
+
+	LHQD1 Inst_frame3_bit17(
+	.D(FrameData[17]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[3]),
+	.QN(ConfigBits_N[3])
+	);
+
+	LHQD1 Inst_frame3_bit16(
+	.D(FrameData[16]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[2]),
+	.QN(ConfigBits_N[2])
+	);
+
+	LHQD1 Inst_frame3_bit15(
+	.D(FrameData[15]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[1]),
+	.QN(ConfigBits_N[1])
+	);
+
+	LHQD1 Inst_frame3_bit14(
+	.D(FrameData[14]),
+	.E(FrameStrobe[3]),
+	.Q(ConfigBits[0]),
+	.QN(ConfigBits_N[0])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_IO_switch_matrix.v b/verilog/rtl/eFPGA_core/W_IO_switch_matrix.v
new file mode 100644
index 0000000..fac4c0a
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_IO_switch_matrix.v
@@ -0,0 +1,1050 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+//NumberOfConfigBits:106
+module W_IO_switch_matrix (W1END0, W1END1, W1END2, W1END3, W2MID0, W2MID1, W2MID2, W2MID3, W2MID4, W2MID5, W2MID6, W2MID7, W2END0, W2END1, W2END2, W2END3, W2END4, W2END5, W2END6, W2END7, WW4END0, WW4END1, WW4END2, WW4END3, WW4END4, WW4END5, WW4END6, WW4END7, WW4END8, WW4END9, WW4END10, WW4END11, WW4END12, WW4END13, WW4END14, WW4END15, W6END0, W6END1, W6END2, W6END3, W6END4, W6END5, W6END6, W6END7, W6END8, W6END9, W6END10, W6END11, A_O, A_Q, B_O, B_Q, E1BEG0, E1BEG1, E1BEG2, E1BEG3, E2BEG0, E2BEG1, E2BEG2, E2BEG3, E2BEG4, E2BEG5, E2BEG6, E2BEG7, E2BEGb0, E2BEGb1, E2BEGb2, E2BEGb3, E2BEGb4, E2BEGb5, E2BEGb6, E2BEGb7, EE4BEG0, EE4BEG1, EE4BEG2, EE4BEG3, EE4BEG4, EE4BEG5, EE4BEG6, EE4BEG7, EE4BEG8, EE4BEG9, EE4BEG10, EE4BEG11, EE4BEG12, EE4BEG13, EE4BEG14, EE4BEG15, E6BEG0, E6BEG1, E6BEG2, E6BEG3, E6BEG4, E6BEG5, E6BEG6, E6BEG7, E6BEG8, E6BEG9, E6BEG10, E6BEG11, A_I, A_T, B_I, B_T, ConfigBits, ConfigBits_N);
+	parameter NoConfigBits = 106;
+	 // switch matrix inputs
+	input W1END0;
+	input W1END1;
+	input W1END2;
+	input W1END3;
+	input W2MID0;
+	input W2MID1;
+	input W2MID2;
+	input W2MID3;
+	input W2MID4;
+	input W2MID5;
+	input W2MID6;
+	input W2MID7;
+	input W2END0;
+	input W2END1;
+	input W2END2;
+	input W2END3;
+	input W2END4;
+	input W2END5;
+	input W2END6;
+	input W2END7;
+	input WW4END0;
+	input WW4END1;
+	input WW4END2;
+	input WW4END3;
+	input WW4END4;
+	input WW4END5;
+	input WW4END6;
+	input WW4END7;
+	input WW4END8;
+	input WW4END9;
+	input WW4END10;
+	input WW4END11;
+	input WW4END12;
+	input WW4END13;
+	input WW4END14;
+	input WW4END15;
+	input W6END0;
+	input W6END1;
+	input W6END2;
+	input W6END3;
+	input W6END4;
+	input W6END5;
+	input W6END6;
+	input W6END7;
+	input W6END8;
+	input W6END9;
+	input W6END10;
+	input W6END11;
+	input A_O;
+	input A_Q;
+	input B_O;
+	input B_Q;
+	output E1BEG0;
+	output E1BEG1;
+	output E1BEG2;
+	output E1BEG3;
+	output E2BEG0;
+	output E2BEG1;
+	output E2BEG2;
+	output E2BEG3;
+	output E2BEG4;
+	output E2BEG5;
+	output E2BEG6;
+	output E2BEG7;
+	output E2BEGb0;
+	output E2BEGb1;
+	output E2BEGb2;
+	output E2BEGb3;
+	output E2BEGb4;
+	output E2BEGb5;
+	output E2BEGb6;
+	output E2BEGb7;
+	output EE4BEG0;
+	output EE4BEG1;
+	output EE4BEG2;
+	output EE4BEG3;
+	output EE4BEG4;
+	output EE4BEG5;
+	output EE4BEG6;
+	output EE4BEG7;
+	output EE4BEG8;
+	output EE4BEG9;
+	output EE4BEG10;
+	output EE4BEG11;
+	output EE4BEG12;
+	output EE4BEG13;
+	output EE4BEG14;
+	output EE4BEG15;
+	output E6BEG0;
+	output E6BEG1;
+	output E6BEG2;
+	output E6BEG3;
+	output E6BEG4;
+	output E6BEG5;
+	output E6BEG6;
+	output E6BEG7;
+	output E6BEG8;
+	output E6BEG9;
+	output E6BEG10;
+	output E6BEG11;
+	output A_I;
+	output A_T;
+	output B_I;
+	output B_T;
+	//global
+	input [NoConfigBits-1:0] ConfigBits;
+	input [NoConfigBits-1:0] ConfigBits_N;
+
+	parameter GND0 = 1'b0;
+	parameter GND = 1'b0;
+	parameter VCC0 = 1'b1;
+	parameter VCC = 1'b1;
+	parameter VDD0 = 1'b1;
+	parameter VDD = 1'b1;
+	
+	wire [2-1:0] E1BEG0_input;
+	wire [2-1:0] E1BEG1_input;
+	wire [2-1:0] E1BEG2_input;
+	wire [2-1:0] E1BEG3_input;
+	wire [4-1:0] E2BEG0_input;
+	wire [4-1:0] E2BEG1_input;
+	wire [4-1:0] E2BEG2_input;
+	wire [4-1:0] E2BEG3_input;
+	wire [4-1:0] E2BEG4_input;
+	wire [4-1:0] E2BEG5_input;
+	wire [4-1:0] E2BEG6_input;
+	wire [4-1:0] E2BEG7_input;
+	wire [4-1:0] E2BEGb0_input;
+	wire [4-1:0] E2BEGb1_input;
+	wire [4-1:0] E2BEGb2_input;
+	wire [4-1:0] E2BEGb3_input;
+	wire [4-1:0] E2BEGb4_input;
+	wire [4-1:0] E2BEGb5_input;
+	wire [4-1:0] E2BEGb6_input;
+	wire [4-1:0] E2BEGb7_input;
+	wire [4-1:0] EE4BEG0_input;
+	wire [4-1:0] EE4BEG1_input;
+	wire [4-1:0] EE4BEG2_input;
+	wire [4-1:0] EE4BEG3_input;
+	wire [4-1:0] EE4BEG4_input;
+	wire [4-1:0] EE4BEG5_input;
+	wire [4-1:0] EE4BEG6_input;
+	wire [4-1:0] EE4BEG7_input;
+	wire [4-1:0] EE4BEG8_input;
+	wire [4-1:0] EE4BEG9_input;
+	wire [4-1:0] EE4BEG10_input;
+	wire [4-1:0] EE4BEG11_input;
+	wire [4-1:0] EE4BEG12_input;
+	wire [4-1:0] EE4BEG13_input;
+	wire [4-1:0] EE4BEG14_input;
+	wire [4-1:0] EE4BEG15_input;
+	wire [4-1:0] E6BEG0_input;
+	wire [4-1:0] E6BEG1_input;
+	wire [4-1:0] E6BEG2_input;
+	wire [4-1:0] E6BEG3_input;
+	wire [4-1:0] E6BEG4_input;
+	wire [4-1:0] E6BEG5_input;
+	wire [4-1:0] E6BEG6_input;
+	wire [4-1:0] E6BEG7_input;
+	wire [4-1:0] E6BEG8_input;
+	wire [4-1:0] E6BEG9_input;
+	wire [4-1:0] E6BEG10_input;
+	wire [4-1:0] E6BEG11_input;
+	wire [16-1:0] A_I_input;
+	wire [8-1:0] A_T_input;
+	wire [16-1:0] B_I_input;
+	wire [8-1:0] B_T_input;
+
+	wire [1-1:0] DEBUG_select_E1BEG0;
+	wire [1-1:0] DEBUG_select_E1BEG1;
+	wire [1-1:0] DEBUG_select_E1BEG2;
+	wire [1-1:0] DEBUG_select_E1BEG3;
+	wire [2-1:0] DEBUG_select_E2BEG0;
+	wire [2-1:0] DEBUG_select_E2BEG1;
+	wire [2-1:0] DEBUG_select_E2BEG2;
+	wire [2-1:0] DEBUG_select_E2BEG3;
+	wire [2-1:0] DEBUG_select_E2BEG4;
+	wire [2-1:0] DEBUG_select_E2BEG5;
+	wire [2-1:0] DEBUG_select_E2BEG6;
+	wire [2-1:0] DEBUG_select_E2BEG7;
+	wire [2-1:0] DEBUG_select_E2BEGb0;
+	wire [2-1:0] DEBUG_select_E2BEGb1;
+	wire [2-1:0] DEBUG_select_E2BEGb2;
+	wire [2-1:0] DEBUG_select_E2BEGb3;
+	wire [2-1:0] DEBUG_select_E2BEGb4;
+	wire [2-1:0] DEBUG_select_E2BEGb5;
+	wire [2-1:0] DEBUG_select_E2BEGb6;
+	wire [2-1:0] DEBUG_select_E2BEGb7;
+	wire [2-1:0] DEBUG_select_EE4BEG0;
+	wire [2-1:0] DEBUG_select_EE4BEG1;
+	wire [2-1:0] DEBUG_select_EE4BEG2;
+	wire [2-1:0] DEBUG_select_EE4BEG3;
+	wire [2-1:0] DEBUG_select_EE4BEG4;
+	wire [2-1:0] DEBUG_select_EE4BEG5;
+	wire [2-1:0] DEBUG_select_EE4BEG6;
+	wire [2-1:0] DEBUG_select_EE4BEG7;
+	wire [2-1:0] DEBUG_select_EE4BEG8;
+	wire [2-1:0] DEBUG_select_EE4BEG9;
+	wire [2-1:0] DEBUG_select_EE4BEG10;
+	wire [2-1:0] DEBUG_select_EE4BEG11;
+	wire [2-1:0] DEBUG_select_EE4BEG12;
+	wire [2-1:0] DEBUG_select_EE4BEG13;
+	wire [2-1:0] DEBUG_select_EE4BEG14;
+	wire [2-1:0] DEBUG_select_EE4BEG15;
+	wire [2-1:0] DEBUG_select_E6BEG0;
+	wire [2-1:0] DEBUG_select_E6BEG1;
+	wire [2-1:0] DEBUG_select_E6BEG2;
+	wire [2-1:0] DEBUG_select_E6BEG3;
+	wire [2-1:0] DEBUG_select_E6BEG4;
+	wire [2-1:0] DEBUG_select_E6BEG5;
+	wire [2-1:0] DEBUG_select_E6BEG6;
+	wire [2-1:0] DEBUG_select_E6BEG7;
+	wire [2-1:0] DEBUG_select_E6BEG8;
+	wire [2-1:0] DEBUG_select_E6BEG9;
+	wire [2-1:0] DEBUG_select_E6BEG10;
+	wire [2-1:0] DEBUG_select_E6BEG11;
+	wire [4-1:0] DEBUG_select_A_I;
+	wire [3-1:0] DEBUG_select_A_T;
+	wire [4-1:0] DEBUG_select_B_I;
+	wire [3-1:0] DEBUG_select_B_T;
+
+// The configuration bits (if any) are just a long shift register
+
+// This shift register is padded to an even number of flops/latches
+// switch matrix multiplexer  E1BEG0 		MUX-2
+	assign E1BEG0_input = {A_O,W1END3};
+	my_mux2 inst_my_mux2_E1BEG0 (
+	.A0 (E1BEG0_input[0]),
+	.A1 (E1BEG0_input[1]),
+	.S (ConfigBits[0+0]),
+	.X (E1BEG0)
+	);
+
+// switch matrix multiplexer  E1BEG1 		MUX-2
+	assign E1BEG1_input = {A_Q,W1END2};
+	my_mux2 inst_my_mux2_E1BEG1 (
+	.A0 (E1BEG1_input[0]),
+	.A1 (E1BEG1_input[1]),
+	.S (ConfigBits[1+0]),
+	.X (E1BEG1)
+	);
+
+// switch matrix multiplexer  E1BEG2 		MUX-2
+	assign E1BEG2_input = {B_O,W1END1};
+	my_mux2 inst_my_mux2_E1BEG2 (
+	.A0 (E1BEG2_input[0]),
+	.A1 (E1BEG2_input[1]),
+	.S (ConfigBits[2+0]),
+	.X (E1BEG2)
+	);
+
+// switch matrix multiplexer  E1BEG3 		MUX-2
+	assign E1BEG3_input = {B_Q,W1END0};
+	my_mux2 inst_my_mux2_E1BEG3 (
+	.A0 (E1BEG3_input[0]),
+	.A1 (E1BEG3_input[1]),
+	.S (ConfigBits[3+0]),
+	.X (E1BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG0 		MUX-4
+	assign E2BEG0_input = {W6END7,WW4END15,WW4END7,W2MID7};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG0 (
+	.A0 (E2BEG0_input[0]),
+	.A1 (E2BEG0_input[1]),
+	.A2 (E2BEG0_input[2]),
+	.A3 (E2BEG0_input[3]),
+	.S0 (ConfigBits[4+0]),
+	.S0N (ConfigBits_N[4+0]),
+	.S1 (ConfigBits[4+1]),
+	.S1N (ConfigBits_N[4+1]),
+	.X (E2BEG0)
+	);
+
+// switch matrix multiplexer  E2BEG1 		MUX-4
+	assign E2BEG1_input = {W6END6,WW4END14,WW4END6,W2MID6};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG1 (
+	.A0 (E2BEG1_input[0]),
+	.A1 (E2BEG1_input[1]),
+	.A2 (E2BEG1_input[2]),
+	.A3 (E2BEG1_input[3]),
+	.S0 (ConfigBits[6+0]),
+	.S0N (ConfigBits_N[6+0]),
+	.S1 (ConfigBits[6+1]),
+	.S1N (ConfigBits_N[6+1]),
+	.X (E2BEG1)
+	);
+
+// switch matrix multiplexer  E2BEG2 		MUX-4
+	assign E2BEG2_input = {W6END5,WW4END13,WW4END5,W2MID5};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG2 (
+	.A0 (E2BEG2_input[0]),
+	.A1 (E2BEG2_input[1]),
+	.A2 (E2BEG2_input[2]),
+	.A3 (E2BEG2_input[3]),
+	.S0 (ConfigBits[8+0]),
+	.S0N (ConfigBits_N[8+0]),
+	.S1 (ConfigBits[8+1]),
+	.S1N (ConfigBits_N[8+1]),
+	.X (E2BEG2)
+	);
+
+// switch matrix multiplexer  E2BEG3 		MUX-4
+	assign E2BEG3_input = {W6END4,WW4END12,WW4END4,W2MID4};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG3 (
+	.A0 (E2BEG3_input[0]),
+	.A1 (E2BEG3_input[1]),
+	.A2 (E2BEG3_input[2]),
+	.A3 (E2BEG3_input[3]),
+	.S0 (ConfigBits[10+0]),
+	.S0N (ConfigBits_N[10+0]),
+	.S1 (ConfigBits[10+1]),
+	.S1N (ConfigBits_N[10+1]),
+	.X (E2BEG3)
+	);
+
+// switch matrix multiplexer  E2BEG4 		MUX-4
+	assign E2BEG4_input = {W6END3,WW4END11,WW4END3,W2MID3};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG4 (
+	.A0 (E2BEG4_input[0]),
+	.A1 (E2BEG4_input[1]),
+	.A2 (E2BEG4_input[2]),
+	.A3 (E2BEG4_input[3]),
+	.S0 (ConfigBits[12+0]),
+	.S0N (ConfigBits_N[12+0]),
+	.S1 (ConfigBits[12+1]),
+	.S1N (ConfigBits_N[12+1]),
+	.X (E2BEG4)
+	);
+
+// switch matrix multiplexer  E2BEG5 		MUX-4
+	assign E2BEG5_input = {W6END2,WW4END10,WW4END2,W2MID2};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG5 (
+	.A0 (E2BEG5_input[0]),
+	.A1 (E2BEG5_input[1]),
+	.A2 (E2BEG5_input[2]),
+	.A3 (E2BEG5_input[3]),
+	.S0 (ConfigBits[14+0]),
+	.S0N (ConfigBits_N[14+0]),
+	.S1 (ConfigBits[14+1]),
+	.S1N (ConfigBits_N[14+1]),
+	.X (E2BEG5)
+	);
+
+// switch matrix multiplexer  E2BEG6 		MUX-4
+	assign E2BEG6_input = {W6END1,WW4END9,WW4END1,W2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG6 (
+	.A0 (E2BEG6_input[0]),
+	.A1 (E2BEG6_input[1]),
+	.A2 (E2BEG6_input[2]),
+	.A3 (E2BEG6_input[3]),
+	.S0 (ConfigBits[16+0]),
+	.S0N (ConfigBits_N[16+0]),
+	.S1 (ConfigBits[16+1]),
+	.S1N (ConfigBits_N[16+1]),
+	.X (E2BEG6)
+	);
+
+// switch matrix multiplexer  E2BEG7 		MUX-4
+	assign E2BEG7_input = {W6END0,WW4END8,WW4END0,W2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEG7 (
+	.A0 (E2BEG7_input[0]),
+	.A1 (E2BEG7_input[1]),
+	.A2 (E2BEG7_input[2]),
+	.A3 (E2BEG7_input[3]),
+	.S0 (ConfigBits[18+0]),
+	.S0N (ConfigBits_N[18+0]),
+	.S1 (ConfigBits[18+1]),
+	.S1N (ConfigBits_N[18+1]),
+	.X (E2BEG7)
+	);
+
+// switch matrix multiplexer  E2BEGb0 		MUX-4
+	assign E2BEGb0_input = {W6END7,WW4END15,WW4END7,W2END7};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb0 (
+	.A0 (E2BEGb0_input[0]),
+	.A1 (E2BEGb0_input[1]),
+	.A2 (E2BEGb0_input[2]),
+	.A3 (E2BEGb0_input[3]),
+	.S0 (ConfigBits[20+0]),
+	.S0N (ConfigBits_N[20+0]),
+	.S1 (ConfigBits[20+1]),
+	.S1N (ConfigBits_N[20+1]),
+	.X (E2BEGb0)
+	);
+
+// switch matrix multiplexer  E2BEGb1 		MUX-4
+	assign E2BEGb1_input = {W6END6,WW4END14,WW4END6,W2END6};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb1 (
+	.A0 (E2BEGb1_input[0]),
+	.A1 (E2BEGb1_input[1]),
+	.A2 (E2BEGb1_input[2]),
+	.A3 (E2BEGb1_input[3]),
+	.S0 (ConfigBits[22+0]),
+	.S0N (ConfigBits_N[22+0]),
+	.S1 (ConfigBits[22+1]),
+	.S1N (ConfigBits_N[22+1]),
+	.X (E2BEGb1)
+	);
+
+// switch matrix multiplexer  E2BEGb2 		MUX-4
+	assign E2BEGb2_input = {W6END5,WW4END13,WW4END5,W2END5};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb2 (
+	.A0 (E2BEGb2_input[0]),
+	.A1 (E2BEGb2_input[1]),
+	.A2 (E2BEGb2_input[2]),
+	.A3 (E2BEGb2_input[3]),
+	.S0 (ConfigBits[24+0]),
+	.S0N (ConfigBits_N[24+0]),
+	.S1 (ConfigBits[24+1]),
+	.S1N (ConfigBits_N[24+1]),
+	.X (E2BEGb2)
+	);
+
+// switch matrix multiplexer  E2BEGb3 		MUX-4
+	assign E2BEGb3_input = {W6END4,WW4END12,WW4END4,W2END4};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb3 (
+	.A0 (E2BEGb3_input[0]),
+	.A1 (E2BEGb3_input[1]),
+	.A2 (E2BEGb3_input[2]),
+	.A3 (E2BEGb3_input[3]),
+	.S0 (ConfigBits[26+0]),
+	.S0N (ConfigBits_N[26+0]),
+	.S1 (ConfigBits[26+1]),
+	.S1N (ConfigBits_N[26+1]),
+	.X (E2BEGb3)
+	);
+
+// switch matrix multiplexer  E2BEGb4 		MUX-4
+	assign E2BEGb4_input = {W6END3,WW4END11,WW4END3,W2END3};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb4 (
+	.A0 (E2BEGb4_input[0]),
+	.A1 (E2BEGb4_input[1]),
+	.A2 (E2BEGb4_input[2]),
+	.A3 (E2BEGb4_input[3]),
+	.S0 (ConfigBits[28+0]),
+	.S0N (ConfigBits_N[28+0]),
+	.S1 (ConfigBits[28+1]),
+	.S1N (ConfigBits_N[28+1]),
+	.X (E2BEGb4)
+	);
+
+// switch matrix multiplexer  E2BEGb5 		MUX-4
+	assign E2BEGb5_input = {W6END2,WW4END10,WW4END2,W2END2};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb5 (
+	.A0 (E2BEGb5_input[0]),
+	.A1 (E2BEGb5_input[1]),
+	.A2 (E2BEGb5_input[2]),
+	.A3 (E2BEGb5_input[3]),
+	.S0 (ConfigBits[30+0]),
+	.S0N (ConfigBits_N[30+0]),
+	.S1 (ConfigBits[30+1]),
+	.S1N (ConfigBits_N[30+1]),
+	.X (E2BEGb5)
+	);
+
+// switch matrix multiplexer  E2BEGb6 		MUX-4
+	assign E2BEGb6_input = {W6END1,WW4END9,WW4END1,W2END1};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb6 (
+	.A0 (E2BEGb6_input[0]),
+	.A1 (E2BEGb6_input[1]),
+	.A2 (E2BEGb6_input[2]),
+	.A3 (E2BEGb6_input[3]),
+	.S0 (ConfigBits[32+0]),
+	.S0N (ConfigBits_N[32+0]),
+	.S1 (ConfigBits[32+1]),
+	.S1N (ConfigBits_N[32+1]),
+	.X (E2BEGb6)
+	);
+
+// switch matrix multiplexer  E2BEGb7 		MUX-4
+	assign E2BEGb7_input = {W6END0,WW4END8,WW4END0,W2END0};
+	cus_mux41_buf inst_cus_mux41_buf_E2BEGb7 (
+	.A0 (E2BEGb7_input[0]),
+	.A1 (E2BEGb7_input[1]),
+	.A2 (E2BEGb7_input[2]),
+	.A3 (E2BEGb7_input[3]),
+	.S0 (ConfigBits[34+0]),
+	.S0N (ConfigBits_N[34+0]),
+	.S1 (ConfigBits[34+1]),
+	.S1N (ConfigBits_N[34+1]),
+	.X (E2BEGb7)
+	);
+
+// switch matrix multiplexer  EE4BEG0 		MUX-4
+	assign EE4BEG0_input = {A_O,W6END4,W6END2,W6END0};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG0 (
+	.A0 (EE4BEG0_input[0]),
+	.A1 (EE4BEG0_input[1]),
+	.A2 (EE4BEG0_input[2]),
+	.A3 (EE4BEG0_input[3]),
+	.S0 (ConfigBits[36+0]),
+	.S0N (ConfigBits_N[36+0]),
+	.S1 (ConfigBits[36+1]),
+	.S1N (ConfigBits_N[36+1]),
+	.X (EE4BEG0)
+	);
+
+// switch matrix multiplexer  EE4BEG1 		MUX-4
+	assign EE4BEG1_input = {B_O,W6END10,W6END8,W6END6};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG1 (
+	.A0 (EE4BEG1_input[0]),
+	.A1 (EE4BEG1_input[1]),
+	.A2 (EE4BEG1_input[2]),
+	.A3 (EE4BEG1_input[3]),
+	.S0 (ConfigBits[38+0]),
+	.S0N (ConfigBits_N[38+0]),
+	.S1 (ConfigBits[38+1]),
+	.S1N (ConfigBits_N[38+1]),
+	.X (EE4BEG1)
+	);
+
+// switch matrix multiplexer  EE4BEG2 		MUX-4
+	assign EE4BEG2_input = {A_Q,W6END5,W6END3,W6END1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG2 (
+	.A0 (EE4BEG2_input[0]),
+	.A1 (EE4BEG2_input[1]),
+	.A2 (EE4BEG2_input[2]),
+	.A3 (EE4BEG2_input[3]),
+	.S0 (ConfigBits[40+0]),
+	.S0N (ConfigBits_N[40+0]),
+	.S1 (ConfigBits[40+1]),
+	.S1N (ConfigBits_N[40+1]),
+	.X (EE4BEG2)
+	);
+
+// switch matrix multiplexer  EE4BEG3 		MUX-4
+	assign EE4BEG3_input = {B_Q,W6END11,W6END9,W6END7};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG3 (
+	.A0 (EE4BEG3_input[0]),
+	.A1 (EE4BEG3_input[1]),
+	.A2 (EE4BEG3_input[2]),
+	.A3 (EE4BEG3_input[3]),
+	.S0 (ConfigBits[42+0]),
+	.S0N (ConfigBits_N[42+0]),
+	.S1 (ConfigBits[42+1]),
+	.S1N (ConfigBits_N[42+1]),
+	.X (EE4BEG3)
+	);
+
+// switch matrix multiplexer  EE4BEG4 		MUX-4
+	assign EE4BEG4_input = {W2END6,W2END4,W2END2,W2END0};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG4 (
+	.A0 (EE4BEG4_input[0]),
+	.A1 (EE4BEG4_input[1]),
+	.A2 (EE4BEG4_input[2]),
+	.A3 (EE4BEG4_input[3]),
+	.S0 (ConfigBits[44+0]),
+	.S0N (ConfigBits_N[44+0]),
+	.S1 (ConfigBits[44+1]),
+	.S1N (ConfigBits_N[44+1]),
+	.X (EE4BEG4)
+	);
+
+// switch matrix multiplexer  EE4BEG5 		MUX-4
+	assign EE4BEG5_input = {W2END7,W2END5,W2END3,W2END1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG5 (
+	.A0 (EE4BEG5_input[0]),
+	.A1 (EE4BEG5_input[1]),
+	.A2 (EE4BEG5_input[2]),
+	.A3 (EE4BEG5_input[3]),
+	.S0 (ConfigBits[46+0]),
+	.S0N (ConfigBits_N[46+0]),
+	.S1 (ConfigBits[46+1]),
+	.S1N (ConfigBits_N[46+1]),
+	.X (EE4BEG5)
+	);
+
+// switch matrix multiplexer  EE4BEG6 		MUX-4
+	assign EE4BEG6_input = {W2MID6,W2MID4,W2MID2,W2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG6 (
+	.A0 (EE4BEG6_input[0]),
+	.A1 (EE4BEG6_input[1]),
+	.A2 (EE4BEG6_input[2]),
+	.A3 (EE4BEG6_input[3]),
+	.S0 (ConfigBits[48+0]),
+	.S0N (ConfigBits_N[48+0]),
+	.S1 (ConfigBits[48+1]),
+	.S1N (ConfigBits_N[48+1]),
+	.X (EE4BEG6)
+	);
+
+// switch matrix multiplexer  EE4BEG7 		MUX-4
+	assign EE4BEG7_input = {W2MID7,W2MID5,W2MID3,W2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG7 (
+	.A0 (EE4BEG7_input[0]),
+	.A1 (EE4BEG7_input[1]),
+	.A2 (EE4BEG7_input[2]),
+	.A3 (EE4BEG7_input[3]),
+	.S0 (ConfigBits[50+0]),
+	.S0N (ConfigBits_N[50+0]),
+	.S1 (ConfigBits[50+1]),
+	.S1N (ConfigBits_N[50+1]),
+	.X (EE4BEG7)
+	);
+
+// switch matrix multiplexer  EE4BEG8 		MUX-4
+	assign EE4BEG8_input = {W6END10,W6END8,W6END6,W6END4};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG8 (
+	.A0 (EE4BEG8_input[0]),
+	.A1 (EE4BEG8_input[1]),
+	.A2 (EE4BEG8_input[2]),
+	.A3 (EE4BEG8_input[3]),
+	.S0 (ConfigBits[52+0]),
+	.S0N (ConfigBits_N[52+0]),
+	.S1 (ConfigBits[52+1]),
+	.S1N (ConfigBits_N[52+1]),
+	.X (EE4BEG8)
+	);
+
+// switch matrix multiplexer  EE4BEG9 		MUX-4
+	assign EE4BEG9_input = {W6END7,W6END5,W6END3,W6END1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG9 (
+	.A0 (EE4BEG9_input[0]),
+	.A1 (EE4BEG9_input[1]),
+	.A2 (EE4BEG9_input[2]),
+	.A3 (EE4BEG9_input[3]),
+	.S0 (ConfigBits[54+0]),
+	.S0N (ConfigBits_N[54+0]),
+	.S1 (ConfigBits[54+1]),
+	.S1N (ConfigBits_N[54+1]),
+	.X (EE4BEG9)
+	);
+
+// switch matrix multiplexer  EE4BEG10 		MUX-4
+	assign EE4BEG10_input = {A_O,W6END4,W6END2,W6END0};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG10 (
+	.A0 (EE4BEG10_input[0]),
+	.A1 (EE4BEG10_input[1]),
+	.A2 (EE4BEG10_input[2]),
+	.A3 (EE4BEG10_input[3]),
+	.S0 (ConfigBits[56+0]),
+	.S0N (ConfigBits_N[56+0]),
+	.S1 (ConfigBits[56+1]),
+	.S1N (ConfigBits_N[56+1]),
+	.X (EE4BEG10)
+	);
+
+// switch matrix multiplexer  EE4BEG11 		MUX-4
+	assign EE4BEG11_input = {B_O,W6END10,W6END8,W6END6};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG11 (
+	.A0 (EE4BEG11_input[0]),
+	.A1 (EE4BEG11_input[1]),
+	.A2 (EE4BEG11_input[2]),
+	.A3 (EE4BEG11_input[3]),
+	.S0 (ConfigBits[58+0]),
+	.S0N (ConfigBits_N[58+0]),
+	.S1 (ConfigBits[58+1]),
+	.S1N (ConfigBits_N[58+1]),
+	.X (EE4BEG11)
+	);
+
+// switch matrix multiplexer  EE4BEG12 		MUX-4
+	assign EE4BEG12_input = {A_Q,W6END5,W6END3,W6END1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG12 (
+	.A0 (EE4BEG12_input[0]),
+	.A1 (EE4BEG12_input[1]),
+	.A2 (EE4BEG12_input[2]),
+	.A3 (EE4BEG12_input[3]),
+	.S0 (ConfigBits[60+0]),
+	.S0N (ConfigBits_N[60+0]),
+	.S1 (ConfigBits[60+1]),
+	.S1N (ConfigBits_N[60+1]),
+	.X (EE4BEG12)
+	);
+
+// switch matrix multiplexer  EE4BEG13 		MUX-4
+	assign EE4BEG13_input = {B_Q,W6END11,W6END9,W6END7};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG13 (
+	.A0 (EE4BEG13_input[0]),
+	.A1 (EE4BEG13_input[1]),
+	.A2 (EE4BEG13_input[2]),
+	.A3 (EE4BEG13_input[3]),
+	.S0 (ConfigBits[62+0]),
+	.S0N (ConfigBits_N[62+0]),
+	.S1 (ConfigBits[62+1]),
+	.S1N (ConfigBits_N[62+1]),
+	.X (EE4BEG13)
+	);
+
+// switch matrix multiplexer  EE4BEG14 		MUX-4
+	assign EE4BEG14_input = {W2MID6,W2MID4,W2MID2,W2MID0};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG14 (
+	.A0 (EE4BEG14_input[0]),
+	.A1 (EE4BEG14_input[1]),
+	.A2 (EE4BEG14_input[2]),
+	.A3 (EE4BEG14_input[3]),
+	.S0 (ConfigBits[64+0]),
+	.S0N (ConfigBits_N[64+0]),
+	.S1 (ConfigBits[64+1]),
+	.S1N (ConfigBits_N[64+1]),
+	.X (EE4BEG14)
+	);
+
+// switch matrix multiplexer  EE4BEG15 		MUX-4
+	assign EE4BEG15_input = {W2MID7,W2MID5,W2MID3,W2MID1};
+	cus_mux41_buf inst_cus_mux41_buf_EE4BEG15 (
+	.A0 (EE4BEG15_input[0]),
+	.A1 (EE4BEG15_input[1]),
+	.A2 (EE4BEG15_input[2]),
+	.A3 (EE4BEG15_input[3]),
+	.S0 (ConfigBits[66+0]),
+	.S0N (ConfigBits_N[66+0]),
+	.S1 (ConfigBits[66+1]),
+	.S1N (ConfigBits_N[66+1]),
+	.X (EE4BEG15)
+	);
+
+// switch matrix multiplexer  E6BEG0 		MUX-4
+	assign E6BEG0_input = {A_O,W6END11,WW4END11,W1END2};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG0 (
+	.A0 (E6BEG0_input[0]),
+	.A1 (E6BEG0_input[1]),
+	.A2 (E6BEG0_input[2]),
+	.A3 (E6BEG0_input[3]),
+	.S0 (ConfigBits[68+0]),
+	.S0N (ConfigBits_N[68+0]),
+	.S1 (ConfigBits[68+1]),
+	.S1N (ConfigBits_N[68+1]),
+	.X (E6BEG0)
+	);
+
+// switch matrix multiplexer  E6BEG1 		MUX-4
+	assign E6BEG1_input = {B_O,W6END10,WW4END10,W1END3};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG1 (
+	.A0 (E6BEG1_input[0]),
+	.A1 (E6BEG1_input[1]),
+	.A2 (E6BEG1_input[2]),
+	.A3 (E6BEG1_input[3]),
+	.S0 (ConfigBits[70+0]),
+	.S0N (ConfigBits_N[70+0]),
+	.S1 (ConfigBits[70+1]),
+	.S1N (ConfigBits_N[70+1]),
+	.X (E6BEG1)
+	);
+
+// switch matrix multiplexer  E6BEG2 		MUX-4
+	assign E6BEG2_input = {A_O,W6END7,WW4END15,WW4END7};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG2 (
+	.A0 (E6BEG2_input[0]),
+	.A1 (E6BEG2_input[1]),
+	.A2 (E6BEG2_input[2]),
+	.A3 (E6BEG2_input[3]),
+	.S0 (ConfigBits[72+0]),
+	.S0N (ConfigBits_N[72+0]),
+	.S1 (ConfigBits[72+1]),
+	.S1N (ConfigBits_N[72+1]),
+	.X (E6BEG2)
+	);
+
+// switch matrix multiplexer  E6BEG3 		MUX-4
+	assign E6BEG3_input = {B_O,W6END6,WW4END14,WW4END6};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG3 (
+	.A0 (E6BEG3_input[0]),
+	.A1 (E6BEG3_input[1]),
+	.A2 (E6BEG3_input[2]),
+	.A3 (E6BEG3_input[3]),
+	.S0 (ConfigBits[74+0]),
+	.S0N (ConfigBits_N[74+0]),
+	.S1 (ConfigBits[74+1]),
+	.S1N (ConfigBits_N[74+1]),
+	.X (E6BEG3)
+	);
+
+// switch matrix multiplexer  E6BEG4 		MUX-4
+	assign E6BEG4_input = {A_O,W6END3,WW4END3,W1END2};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG4 (
+	.A0 (E6BEG4_input[0]),
+	.A1 (E6BEG4_input[1]),
+	.A2 (E6BEG4_input[2]),
+	.A3 (E6BEG4_input[3]),
+	.S0 (ConfigBits[76+0]),
+	.S0N (ConfigBits_N[76+0]),
+	.S1 (ConfigBits[76+1]),
+	.S1N (ConfigBits_N[76+1]),
+	.X (E6BEG4)
+	);
+
+// switch matrix multiplexer  E6BEG5 		MUX-4
+	assign E6BEG5_input = {B_O,W6END2,WW4END2,W1END3};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG5 (
+	.A0 (E6BEG5_input[0]),
+	.A1 (E6BEG5_input[1]),
+	.A2 (E6BEG5_input[2]),
+	.A3 (E6BEG5_input[3]),
+	.S0 (ConfigBits[78+0]),
+	.S0N (ConfigBits_N[78+0]),
+	.S1 (ConfigBits[78+1]),
+	.S1N (ConfigBits_N[78+1]),
+	.X (E6BEG5)
+	);
+
+// switch matrix multiplexer  E6BEG6 		MUX-4
+	assign E6BEG6_input = {A_Q,W6END9,WW4END9,W1END1};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG6 (
+	.A0 (E6BEG6_input[0]),
+	.A1 (E6BEG6_input[1]),
+	.A2 (E6BEG6_input[2]),
+	.A3 (E6BEG6_input[3]),
+	.S0 (ConfigBits[80+0]),
+	.S0N (ConfigBits_N[80+0]),
+	.S1 (ConfigBits[80+1]),
+	.S1N (ConfigBits_N[80+1]),
+	.X (E6BEG6)
+	);
+
+// switch matrix multiplexer  E6BEG7 		MUX-4
+	assign E6BEG7_input = {B_Q,W6END8,WW4END8,W1END0};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG7 (
+	.A0 (E6BEG7_input[0]),
+	.A1 (E6BEG7_input[1]),
+	.A2 (E6BEG7_input[2]),
+	.A3 (E6BEG7_input[3]),
+	.S0 (ConfigBits[82+0]),
+	.S0N (ConfigBits_N[82+0]),
+	.S1 (ConfigBits[82+1]),
+	.S1N (ConfigBits_N[82+1]),
+	.X (E6BEG7)
+	);
+
+// switch matrix multiplexer  E6BEG8 		MUX-4
+	assign E6BEG8_input = {A_Q,W6END5,WW4END13,WW4END5};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG8 (
+	.A0 (E6BEG8_input[0]),
+	.A1 (E6BEG8_input[1]),
+	.A2 (E6BEG8_input[2]),
+	.A3 (E6BEG8_input[3]),
+	.S0 (ConfigBits[84+0]),
+	.S0N (ConfigBits_N[84+0]),
+	.S1 (ConfigBits[84+1]),
+	.S1N (ConfigBits_N[84+1]),
+	.X (E6BEG8)
+	);
+
+// switch matrix multiplexer  E6BEG9 		MUX-4
+	assign E6BEG9_input = {B_Q,W6END4,WW4END12,WW4END4};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG9 (
+	.A0 (E6BEG9_input[0]),
+	.A1 (E6BEG9_input[1]),
+	.A2 (E6BEG9_input[2]),
+	.A3 (E6BEG9_input[3]),
+	.S0 (ConfigBits[86+0]),
+	.S0N (ConfigBits_N[86+0]),
+	.S1 (ConfigBits[86+1]),
+	.S1N (ConfigBits_N[86+1]),
+	.X (E6BEG9)
+	);
+
+// switch matrix multiplexer  E6BEG10 		MUX-4
+	assign E6BEG10_input = {A_Q,W6END1,WW4END1,W1END1};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG10 (
+	.A0 (E6BEG10_input[0]),
+	.A1 (E6BEG10_input[1]),
+	.A2 (E6BEG10_input[2]),
+	.A3 (E6BEG10_input[3]),
+	.S0 (ConfigBits[88+0]),
+	.S0N (ConfigBits_N[88+0]),
+	.S1 (ConfigBits[88+1]),
+	.S1N (ConfigBits_N[88+1]),
+	.X (E6BEG10)
+	);
+
+// switch matrix multiplexer  E6BEG11 		MUX-4
+	assign E6BEG11_input = {B_Q,W6END0,WW4END0,W1END0};
+	cus_mux41_buf inst_cus_mux41_buf_E6BEG11 (
+	.A0 (E6BEG11_input[0]),
+	.A1 (E6BEG11_input[1]),
+	.A2 (E6BEG11_input[2]),
+	.A3 (E6BEG11_input[3]),
+	.S0 (ConfigBits[90+0]),
+	.S0N (ConfigBits_N[90+0]),
+	.S1 (ConfigBits[90+1]),
+	.S1N (ConfigBits_N[90+1]),
+	.X (E6BEG11)
+	);
+
+// switch matrix multiplexer  A_I 		MUX-16
+	assign A_I_input = {W2END7,W2END6,W2END5,W2END4,W2END3,W2END2,W2END1,W2END0,W2MID7,W2MID6,W2MID5,W2MID4,W2MID3,W2MID2,W2MID1,W2MID0};
+	cus_mux161_buf inst_cus_mux161_buf_A_I (
+	.A0 (A_I_input[0]),
+	.A1 (A_I_input[1]),
+	.A2 (A_I_input[2]),
+	.A3 (A_I_input[3]),
+	.A4 (A_I_input[4]),
+	.A5 (A_I_input[5]),
+	.A6 (A_I_input[6]),
+	.A7 (A_I_input[7]),
+	.A8 (A_I_input[8]),
+	.A9 (A_I_input[9]),
+	.A10 (A_I_input[10]),
+	.A11 (A_I_input[11]),
+	.A12 (A_I_input[12]),
+	.A13 (A_I_input[13]),
+	.A14 (A_I_input[14]),
+	.A15 (A_I_input[15]),
+	.S0 (ConfigBits[92+0]),
+	.S0N (ConfigBits_N[92+0]),
+	.S1 (ConfigBits[92+1]),
+	.S1N (ConfigBits_N[92+1]),
+	.S2 (ConfigBits[92+2]),
+	.S2N (ConfigBits_N[92+2]),
+	.S3 (ConfigBits[92+3]),
+	.S3N (ConfigBits_N[92+3]),
+	.X (A_I)
+	);
+
+// switch matrix multiplexer  A_T 		MUX-8
+	assign A_T_input = {VCC0,GND0,W2END4,W2END3,W2END2,W2END1,W2END0,W2MID7};
+	cus_mux81_buf inst_cus_mux81_buf_A_T (
+	.A0 (A_T_input[0]),
+	.A1 (A_T_input[1]),
+	.A2 (A_T_input[2]),
+	.A3 (A_T_input[3]),
+	.A4 (A_T_input[4]),
+	.A5 (A_T_input[5]),
+	.A6 (A_T_input[6]),
+	.A7 (A_T_input[7]),
+	.S0 (ConfigBits[96+0]),
+	.S0N (ConfigBits_N[96+0]),
+	.S1 (ConfigBits[96+1]),
+	.S1N (ConfigBits_N[96+1]),
+	.S2 (ConfigBits[96+2]),
+	.S2N (ConfigBits_N[96+2]),
+	.X (A_T)
+	);
+
+// switch matrix multiplexer  B_I 		MUX-16
+	assign B_I_input = {W2END7,W2END6,W2END5,W2END4,W2END3,W2END2,W2END1,W2END0,W2MID7,W2MID6,W2MID5,W2MID4,W2MID3,W2MID2,W2MID1,W2MID0};
+	cus_mux161_buf inst_cus_mux161_buf_B_I (
+	.A0 (B_I_input[0]),
+	.A1 (B_I_input[1]),
+	.A2 (B_I_input[2]),
+	.A3 (B_I_input[3]),
+	.A4 (B_I_input[4]),
+	.A5 (B_I_input[5]),
+	.A6 (B_I_input[6]),
+	.A7 (B_I_input[7]),
+	.A8 (B_I_input[8]),
+	.A9 (B_I_input[9]),
+	.A10 (B_I_input[10]),
+	.A11 (B_I_input[11]),
+	.A12 (B_I_input[12]),
+	.A13 (B_I_input[13]),
+	.A14 (B_I_input[14]),
+	.A15 (B_I_input[15]),
+	.S0 (ConfigBits[99+0]),
+	.S0N (ConfigBits_N[99+0]),
+	.S1 (ConfigBits[99+1]),
+	.S1N (ConfigBits_N[99+1]),
+	.S2 (ConfigBits[99+2]),
+	.S2N (ConfigBits_N[99+2]),
+	.S3 (ConfigBits[99+3]),
+	.S3N (ConfigBits_N[99+3]),
+	.X (B_I)
+	);
+
+// switch matrix multiplexer  B_T 		MUX-8
+	assign B_T_input = {VCC0,GND0,W2END6,W2END5,W2END4,W2END0,W2MID7,W2MID6};
+	cus_mux81_buf inst_cus_mux81_buf_B_T (
+	.A0 (B_T_input[0]),
+	.A1 (B_T_input[1]),
+	.A2 (B_T_input[2]),
+	.A3 (B_T_input[3]),
+	.A4 (B_T_input[4]),
+	.A5 (B_T_input[5]),
+	.A6 (B_T_input[6]),
+	.A7 (B_T_input[7]),
+	.S0 (ConfigBits[103+0]),
+	.S0N (ConfigBits_N[103+0]),
+	.S1 (ConfigBits[103+1]),
+	.S1N (ConfigBits_N[103+1]),
+	.S2 (ConfigBits[103+2]),
+	.S2N (ConfigBits_N[103+2]),
+	.X (B_T)
+	);
+
+	assign DEBUG_select_E1BEG0 = ConfigBits[0:0];
+	assign DEBUG_select_E1BEG1 = ConfigBits[1:1];
+	assign DEBUG_select_E1BEG2 = ConfigBits[2:2];
+	assign DEBUG_select_E1BEG3 = ConfigBits[3:3];
+	assign DEBUG_select_E2BEG0 = ConfigBits[5:4];
+	assign DEBUG_select_E2BEG1 = ConfigBits[7:6];
+	assign DEBUG_select_E2BEG2 = ConfigBits[9:8];
+	assign DEBUG_select_E2BEG3 = ConfigBits[11:10];
+	assign DEBUG_select_E2BEG4 = ConfigBits[13:12];
+	assign DEBUG_select_E2BEG5 = ConfigBits[15:14];
+	assign DEBUG_select_E2BEG6 = ConfigBits[17:16];
+	assign DEBUG_select_E2BEG7 = ConfigBits[19:18];
+	assign DEBUG_select_E2BEGb0 = ConfigBits[21:20];
+	assign DEBUG_select_E2BEGb1 = ConfigBits[23:22];
+	assign DEBUG_select_E2BEGb2 = ConfigBits[25:24];
+	assign DEBUG_select_E2BEGb3 = ConfigBits[27:26];
+	assign DEBUG_select_E2BEGb4 = ConfigBits[29:28];
+	assign DEBUG_select_E2BEGb5 = ConfigBits[31:30];
+	assign DEBUG_select_E2BEGb6 = ConfigBits[33:32];
+	assign DEBUG_select_E2BEGb7 = ConfigBits[35:34];
+	assign DEBUG_select_EE4BEG0 = ConfigBits[37:36];
+	assign DEBUG_select_EE4BEG1 = ConfigBits[39:38];
+	assign DEBUG_select_EE4BEG2 = ConfigBits[41:40];
+	assign DEBUG_select_EE4BEG3 = ConfigBits[43:42];
+	assign DEBUG_select_EE4BEG4 = ConfigBits[45:44];
+	assign DEBUG_select_EE4BEG5 = ConfigBits[47:46];
+	assign DEBUG_select_EE4BEG6 = ConfigBits[49:48];
+	assign DEBUG_select_EE4BEG7 = ConfigBits[51:50];
+	assign DEBUG_select_EE4BEG8 = ConfigBits[53:52];
+	assign DEBUG_select_EE4BEG9 = ConfigBits[55:54];
+	assign DEBUG_select_EE4BEG10 = ConfigBits[57:56];
+	assign DEBUG_select_EE4BEG11 = ConfigBits[59:58];
+	assign DEBUG_select_EE4BEG12 = ConfigBits[61:60];
+	assign DEBUG_select_EE4BEG13 = ConfigBits[63:62];
+	assign DEBUG_select_EE4BEG14 = ConfigBits[65:64];
+	assign DEBUG_select_EE4BEG15 = ConfigBits[67:66];
+	assign DEBUG_select_E6BEG0 = ConfigBits[69:68];
+	assign DEBUG_select_E6BEG1 = ConfigBits[71:70];
+	assign DEBUG_select_E6BEG2 = ConfigBits[73:72];
+	assign DEBUG_select_E6BEG3 = ConfigBits[75:74];
+	assign DEBUG_select_E6BEG4 = ConfigBits[77:76];
+	assign DEBUG_select_E6BEG5 = ConfigBits[79:78];
+	assign DEBUG_select_E6BEG6 = ConfigBits[81:80];
+	assign DEBUG_select_E6BEG7 = ConfigBits[83:82];
+	assign DEBUG_select_E6BEG8 = ConfigBits[85:84];
+	assign DEBUG_select_E6BEG9 = ConfigBits[87:86];
+	assign DEBUG_select_E6BEG10 = ConfigBits[89:88];
+	assign DEBUG_select_E6BEG11 = ConfigBits[91:90];
+	assign DEBUG_select_A_I = ConfigBits[95:92];
+	assign DEBUG_select_A_T = ConfigBits[98:96];
+	assign DEBUG_select_B_I = ConfigBits[102:99];
+	assign DEBUG_select_B_T = ConfigBits[105:103];
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/W_IO_tile.v b/verilog/rtl/eFPGA_core/W_IO_tile.v
new file mode 100644
index 0000000..ab4f260
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/W_IO_tile.v
@@ -0,0 +1,767 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module W_IO (E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, W1END, W2MID, W2END, WW4END, W6END, A_I_top, A_T_top, A_O_top, UserCLK, B_I_top, B_T_top, B_O_top, A_config_C_bit0, A_config_C_bit1, A_config_C_bit2, A_config_C_bit3, B_config_C_bit0, B_config_C_bit1, B_config_C_bit2, B_config_C_bit3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
+	parameter MaxFramesPerCol = 20;
+	parameter FrameBitsPerRow = 32;
+	parameter NoConfigBits = 114;
+	//  NORTH
+	//  EAST
+	output [3:0] E1BEG; //wires:4 X_offset:1 Y_offset:0  source_name:E1BEG destination_name:NULL  
+	output [7:0] E2BEG; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEG destination_name:NULL  
+	output [7:0] E2BEGb; //wires:8 X_offset:1 Y_offset:0  source_name:E2BEGb destination_name:NULL  
+	output [15:0] EE4BEG; //wires:4 X_offset:4 Y_offset:0  source_name:EE4BEG destination_name:NULL  
+	output [11:0] E6BEG; //wires:2 X_offset:6 Y_offset:0  source_name:E6BEG destination_name:NULL  
+	//  SOUTH
+	//  WEST
+	input [3:0] W1END; //wires:4 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W1END  
+	input [7:0] W2MID; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2MID  
+	input [7:0] W2END; //wires:8 X_offset:-1 Y_offset:0  source_name:NULL destination_name:W2END  
+	input [15:0] WW4END; //wires:4 X_offset:-4 Y_offset:0  source_name:NULL destination_name:WW4END  
+	input [11:0] W6END; //wires:2 X_offset:-6 Y_offset:0  source_name:NULL destination_name:W6END  
+	// Tile IO ports from BELs
+	output A_I_top;
+	output A_T_top;
+	input A_O_top;
+	input UserCLK;
+	output B_I_top;
+	output B_T_top;
+	input B_O_top;
+	output A_config_C_bit0;
+	output A_config_C_bit1;
+	output A_config_C_bit2;
+	output A_config_C_bit3;
+	output B_config_C_bit0;
+	output B_config_C_bit1;
+	output B_config_C_bit2;
+	output B_config_C_bit3;
+	output UserCLKo;
+	input [FrameBitsPerRow-1:0] FrameData; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [FrameBitsPerRow-1:0] FrameData_O;
+	input [MaxFramesPerCol-1:0] FrameStrobe; //CONFIG_PORT this is a keyword needed to connect the tile to the bitstream frame register
+	output [MaxFramesPerCol-1:0] FrameStrobe_O;
+	//global
+
+
+//signal declarations
+//BEL ports (e.g., slices)
+	wire A_I;
+	wire A_T;
+	wire B_I;
+	wire B_T;
+	wire A_O;
+	wire A_Q;
+	wire B_O;
+	wire B_Q;
+//jump wires
+//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
+	wire [NoConfigBits-1:0] ConfigBits;
+	wire [NoConfigBits-1:0] ConfigBits_N;
+
+// Cascading of routing for wires spanning more than one tile
+	wire [FrameBitsPerRow-1:0] FrameData_i;
+	wire [FrameBitsPerRow-1:0] FrameData_O_i;
+	assign FrameData_O_i = FrameData_i;
+
+	my_buf data_inbuf_0 (
+	.A(FrameData[0]),
+	.X(FrameData_i[0])
+	);
+
+	my_buf data_inbuf_1 (
+	.A(FrameData[1]),
+	.X(FrameData_i[1])
+	);
+
+	my_buf data_inbuf_2 (
+	.A(FrameData[2]),
+	.X(FrameData_i[2])
+	);
+
+	my_buf data_inbuf_3 (
+	.A(FrameData[3]),
+	.X(FrameData_i[3])
+	);
+
+	my_buf data_inbuf_4 (
+	.A(FrameData[4]),
+	.X(FrameData_i[4])
+	);
+
+	my_buf data_inbuf_5 (
+	.A(FrameData[5]),
+	.X(FrameData_i[5])
+	);
+
+	my_buf data_inbuf_6 (
+	.A(FrameData[6]),
+	.X(FrameData_i[6])
+	);
+
+	my_buf data_inbuf_7 (
+	.A(FrameData[7]),
+	.X(FrameData_i[7])
+	);
+
+	my_buf data_inbuf_8 (
+	.A(FrameData[8]),
+	.X(FrameData_i[8])
+	);
+
+	my_buf data_inbuf_9 (
+	.A(FrameData[9]),
+	.X(FrameData_i[9])
+	);
+
+	my_buf data_inbuf_10 (
+	.A(FrameData[10]),
+	.X(FrameData_i[10])
+	);
+
+	my_buf data_inbuf_11 (
+	.A(FrameData[11]),
+	.X(FrameData_i[11])
+	);
+
+	my_buf data_inbuf_12 (
+	.A(FrameData[12]),
+	.X(FrameData_i[12])
+	);
+
+	my_buf data_inbuf_13 (
+	.A(FrameData[13]),
+	.X(FrameData_i[13])
+	);
+
+	my_buf data_inbuf_14 (
+	.A(FrameData[14]),
+	.X(FrameData_i[14])
+	);
+
+	my_buf data_inbuf_15 (
+	.A(FrameData[15]),
+	.X(FrameData_i[15])
+	);
+
+	my_buf data_inbuf_16 (
+	.A(FrameData[16]),
+	.X(FrameData_i[16])
+	);
+
+	my_buf data_inbuf_17 (
+	.A(FrameData[17]),
+	.X(FrameData_i[17])
+	);
+
+	my_buf data_inbuf_18 (
+	.A(FrameData[18]),
+	.X(FrameData_i[18])
+	);
+
+	my_buf data_inbuf_19 (
+	.A(FrameData[19]),
+	.X(FrameData_i[19])
+	);
+
+	my_buf data_inbuf_20 (
+	.A(FrameData[20]),
+	.X(FrameData_i[20])
+	);
+
+	my_buf data_inbuf_21 (
+	.A(FrameData[21]),
+	.X(FrameData_i[21])
+	);
+
+	my_buf data_inbuf_22 (
+	.A(FrameData[22]),
+	.X(FrameData_i[22])
+	);
+
+	my_buf data_inbuf_23 (
+	.A(FrameData[23]),
+	.X(FrameData_i[23])
+	);
+
+	my_buf data_inbuf_24 (
+	.A(FrameData[24]),
+	.X(FrameData_i[24])
+	);
+
+	my_buf data_inbuf_25 (
+	.A(FrameData[25]),
+	.X(FrameData_i[25])
+	);
+
+	my_buf data_inbuf_26 (
+	.A(FrameData[26]),
+	.X(FrameData_i[26])
+	);
+
+	my_buf data_inbuf_27 (
+	.A(FrameData[27]),
+	.X(FrameData_i[27])
+	);
+
+	my_buf data_inbuf_28 (
+	.A(FrameData[28]),
+	.X(FrameData_i[28])
+	);
+
+	my_buf data_inbuf_29 (
+	.A(FrameData[29]),
+	.X(FrameData_i[29])
+	);
+
+	my_buf data_inbuf_30 (
+	.A(FrameData[30]),
+	.X(FrameData_i[30])
+	);
+
+	my_buf data_inbuf_31 (
+	.A(FrameData[31]),
+	.X(FrameData_i[31])
+	);
+
+	my_buf data_outbuf_0 (
+	.A(FrameData_O_i[0]),
+	.X(FrameData_O[0])
+	);
+
+	my_buf data_outbuf_1 (
+	.A(FrameData_O_i[1]),
+	.X(FrameData_O[1])
+	);
+
+	my_buf data_outbuf_2 (
+	.A(FrameData_O_i[2]),
+	.X(FrameData_O[2])
+	);
+
+	my_buf data_outbuf_3 (
+	.A(FrameData_O_i[3]),
+	.X(FrameData_O[3])
+	);
+
+	my_buf data_outbuf_4 (
+	.A(FrameData_O_i[4]),
+	.X(FrameData_O[4])
+	);
+
+	my_buf data_outbuf_5 (
+	.A(FrameData_O_i[5]),
+	.X(FrameData_O[5])
+	);
+
+	my_buf data_outbuf_6 (
+	.A(FrameData_O_i[6]),
+	.X(FrameData_O[6])
+	);
+
+	my_buf data_outbuf_7 (
+	.A(FrameData_O_i[7]),
+	.X(FrameData_O[7])
+	);
+
+	my_buf data_outbuf_8 (
+	.A(FrameData_O_i[8]),
+	.X(FrameData_O[8])
+	);
+
+	my_buf data_outbuf_9 (
+	.A(FrameData_O_i[9]),
+	.X(FrameData_O[9])
+	);
+
+	my_buf data_outbuf_10 (
+	.A(FrameData_O_i[10]),
+	.X(FrameData_O[10])
+	);
+
+	my_buf data_outbuf_11 (
+	.A(FrameData_O_i[11]),
+	.X(FrameData_O[11])
+	);
+
+	my_buf data_outbuf_12 (
+	.A(FrameData_O_i[12]),
+	.X(FrameData_O[12])
+	);
+
+	my_buf data_outbuf_13 (
+	.A(FrameData_O_i[13]),
+	.X(FrameData_O[13])
+	);
+
+	my_buf data_outbuf_14 (
+	.A(FrameData_O_i[14]),
+	.X(FrameData_O[14])
+	);
+
+	my_buf data_outbuf_15 (
+	.A(FrameData_O_i[15]),
+	.X(FrameData_O[15])
+	);
+
+	my_buf data_outbuf_16 (
+	.A(FrameData_O_i[16]),
+	.X(FrameData_O[16])
+	);
+
+	my_buf data_outbuf_17 (
+	.A(FrameData_O_i[17]),
+	.X(FrameData_O[17])
+	);
+
+	my_buf data_outbuf_18 (
+	.A(FrameData_O_i[18]),
+	.X(FrameData_O[18])
+	);
+
+	my_buf data_outbuf_19 (
+	.A(FrameData_O_i[19]),
+	.X(FrameData_O[19])
+	);
+
+	my_buf data_outbuf_20 (
+	.A(FrameData_O_i[20]),
+	.X(FrameData_O[20])
+	);
+
+	my_buf data_outbuf_21 (
+	.A(FrameData_O_i[21]),
+	.X(FrameData_O[21])
+	);
+
+	my_buf data_outbuf_22 (
+	.A(FrameData_O_i[22]),
+	.X(FrameData_O[22])
+	);
+
+	my_buf data_outbuf_23 (
+	.A(FrameData_O_i[23]),
+	.X(FrameData_O[23])
+	);
+
+	my_buf data_outbuf_24 (
+	.A(FrameData_O_i[24]),
+	.X(FrameData_O[24])
+	);
+
+	my_buf data_outbuf_25 (
+	.A(FrameData_O_i[25]),
+	.X(FrameData_O[25])
+	);
+
+	my_buf data_outbuf_26 (
+	.A(FrameData_O_i[26]),
+	.X(FrameData_O[26])
+	);
+
+	my_buf data_outbuf_27 (
+	.A(FrameData_O_i[27]),
+	.X(FrameData_O[27])
+	);
+
+	my_buf data_outbuf_28 (
+	.A(FrameData_O_i[28]),
+	.X(FrameData_O[28])
+	);
+
+	my_buf data_outbuf_29 (
+	.A(FrameData_O_i[29]),
+	.X(FrameData_O[29])
+	);
+
+	my_buf data_outbuf_30 (
+	.A(FrameData_O_i[30]),
+	.X(FrameData_O[30])
+	);
+
+	my_buf data_outbuf_31 (
+	.A(FrameData_O_i[31]),
+	.X(FrameData_O[31])
+	);
+
+	wire [MaxFramesPerCol-1:0] FrameStrobe_i;
+	wire [MaxFramesPerCol-1:0] FrameStrobe_O_i;
+	assign FrameStrobe_O_i = FrameStrobe_i;
+
+	my_buf strobe_inbuf_0 (
+	.A(FrameStrobe[0]),
+	.X(FrameStrobe_i[0])
+	)
+;
+	my_buf strobe_inbuf_1 (
+	.A(FrameStrobe[1]),
+	.X(FrameStrobe_i[1])
+	)
+;
+	my_buf strobe_inbuf_2 (
+	.A(FrameStrobe[2]),
+	.X(FrameStrobe_i[2])
+	)
+;
+	my_buf strobe_inbuf_3 (
+	.A(FrameStrobe[3]),
+	.X(FrameStrobe_i[3])
+	)
+;
+	my_buf strobe_inbuf_4 (
+	.A(FrameStrobe[4]),
+	.X(FrameStrobe_i[4])
+	)
+;
+	my_buf strobe_inbuf_5 (
+	.A(FrameStrobe[5]),
+	.X(FrameStrobe_i[5])
+	)
+;
+	my_buf strobe_inbuf_6 (
+	.A(FrameStrobe[6]),
+	.X(FrameStrobe_i[6])
+	)
+;
+	my_buf strobe_inbuf_7 (
+	.A(FrameStrobe[7]),
+	.X(FrameStrobe_i[7])
+	)
+;
+	my_buf strobe_inbuf_8 (
+	.A(FrameStrobe[8]),
+	.X(FrameStrobe_i[8])
+	)
+;
+	my_buf strobe_inbuf_9 (
+	.A(FrameStrobe[9]),
+	.X(FrameStrobe_i[9])
+	)
+;
+	my_buf strobe_inbuf_10 (
+	.A(FrameStrobe[10]),
+	.X(FrameStrobe_i[10])
+	)
+;
+	my_buf strobe_inbuf_11 (
+	.A(FrameStrobe[11]),
+	.X(FrameStrobe_i[11])
+	)
+;
+	my_buf strobe_inbuf_12 (
+	.A(FrameStrobe[12]),
+	.X(FrameStrobe_i[12])
+	)
+;
+	my_buf strobe_inbuf_13 (
+	.A(FrameStrobe[13]),
+	.X(FrameStrobe_i[13])
+	)
+;
+	my_buf strobe_inbuf_14 (
+	.A(FrameStrobe[14]),
+	.X(FrameStrobe_i[14])
+	)
+;
+	my_buf strobe_inbuf_15 (
+	.A(FrameStrobe[15]),
+	.X(FrameStrobe_i[15])
+	)
+;
+	my_buf strobe_inbuf_16 (
+	.A(FrameStrobe[16]),
+	.X(FrameStrobe_i[16])
+	)
+;
+	my_buf strobe_inbuf_17 (
+	.A(FrameStrobe[17]),
+	.X(FrameStrobe_i[17])
+	)
+;
+	my_buf strobe_inbuf_18 (
+	.A(FrameStrobe[18]),
+	.X(FrameStrobe_i[18])
+	)
+;
+	my_buf strobe_inbuf_19 (
+	.A(FrameStrobe[19]),
+	.X(FrameStrobe_i[19])
+	)
+;
+	my_buf strobe_outbuf_0 (
+	.A(FrameStrobe_O_i[0]),
+	.X(FrameStrobe_O[0])
+	)
+;
+	my_buf strobe_outbuf_1 (
+	.A(FrameStrobe_O_i[1]),
+	.X(FrameStrobe_O[1])
+	)
+;
+	my_buf strobe_outbuf_2 (
+	.A(FrameStrobe_O_i[2]),
+	.X(FrameStrobe_O[2])
+	)
+;
+	my_buf strobe_outbuf_3 (
+	.A(FrameStrobe_O_i[3]),
+	.X(FrameStrobe_O[3])
+	)
+;
+	my_buf strobe_outbuf_4 (
+	.A(FrameStrobe_O_i[4]),
+	.X(FrameStrobe_O[4])
+	)
+;
+	my_buf strobe_outbuf_5 (
+	.A(FrameStrobe_O_i[5]),
+	.X(FrameStrobe_O[5])
+	)
+;
+	my_buf strobe_outbuf_6 (
+	.A(FrameStrobe_O_i[6]),
+	.X(FrameStrobe_O[6])
+	)
+;
+	my_buf strobe_outbuf_7 (
+	.A(FrameStrobe_O_i[7]),
+	.X(FrameStrobe_O[7])
+	)
+;
+	my_buf strobe_outbuf_8 (
+	.A(FrameStrobe_O_i[8]),
+	.X(FrameStrobe_O[8])
+	)
+;
+	my_buf strobe_outbuf_9 (
+	.A(FrameStrobe_O_i[9]),
+	.X(FrameStrobe_O[9])
+	)
+;
+	my_buf strobe_outbuf_10 (
+	.A(FrameStrobe_O_i[10]),
+	.X(FrameStrobe_O[10])
+	)
+;
+	my_buf strobe_outbuf_11 (
+	.A(FrameStrobe_O_i[11]),
+	.X(FrameStrobe_O[11])
+	)
+;
+	my_buf strobe_outbuf_12 (
+	.A(FrameStrobe_O_i[12]),
+	.X(FrameStrobe_O[12])
+	)
+;
+	my_buf strobe_outbuf_13 (
+	.A(FrameStrobe_O_i[13]),
+	.X(FrameStrobe_O[13])
+	)
+;
+	my_buf strobe_outbuf_14 (
+	.A(FrameStrobe_O_i[14]),
+	.X(FrameStrobe_O[14])
+	)
+;
+	my_buf strobe_outbuf_15 (
+	.A(FrameStrobe_O_i[15]),
+	.X(FrameStrobe_O[15])
+	)
+;
+	my_buf strobe_outbuf_16 (
+	.A(FrameStrobe_O_i[16]),
+	.X(FrameStrobe_O[16])
+	)
+;
+	my_buf strobe_outbuf_17 (
+	.A(FrameStrobe_O_i[17]),
+	.X(FrameStrobe_O[17])
+	)
+;
+	my_buf strobe_outbuf_18 (
+	.A(FrameStrobe_O_i[18]),
+	.X(FrameStrobe_O[18])
+	)
+;
+	my_buf strobe_outbuf_19 (
+	.A(FrameStrobe_O_i[19]),
+	.X(FrameStrobe_O[19])
+	)
+;
+	clk_buf inst_clk_buf(.A(UserCLK), .X(UserCLKo));
+
+// configuration storage latches
+	W_IO_ConfigMem Inst_W_IO_ConfigMem (
+	.FrameData(FrameData),
+	.FrameStrobe(FrameStrobe),
+	.ConfigBits(ConfigBits),
+	.ConfigBits_N(ConfigBits_N)
+	);
+
+//BEL component instantiations
+	IO_1_bidirectional_frame_config_pass Inst_A_IO_1_bidirectional_frame_config_pass (
+	.I(A_I),
+	.T(A_T),
+	.O(A_O),
+	.Q(A_Q),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I_top(A_I_top),
+	.T_top(A_T_top),
+	.O_top(A_O_top),
+	.UserCLK(UserCLK) 
+	);
+
+	IO_1_bidirectional_frame_config_pass Inst_B_IO_1_bidirectional_frame_config_pass (
+	.I(B_I),
+	.T(B_T),
+	.O(B_O),
+	.Q(B_Q),
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.I_top(B_I_top),
+	.T_top(B_T_top),
+	.O_top(B_O_top),
+	.UserCLK(UserCLK) 
+	);
+
+	Config_access Inst_A_config_Config_access (
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.C_bit0(A_config_C_bit0),
+	.C_bit1(A_config_C_bit1),
+	.C_bit2(A_config_C_bit2),
+	.C_bit3(A_config_C_bit3),
+	.ConfigBits(ConfigBits[4-1:0])
+	);
+
+	Config_access Inst_B_config_Config_access (
+	//I/O primitive pins go to tile top level module (not further parsed)  
+	.C_bit0(B_config_C_bit0),
+	.C_bit1(B_config_C_bit1),
+	.C_bit2(B_config_C_bit2),
+	.C_bit3(B_config_C_bit3),
+	.ConfigBits(ConfigBits[8-1:4])
+	);
+
+
+//switch matrix component instantiation
+	W_IO_switch_matrix Inst_W_IO_switch_matrix (
+	.W1END0(W1END[0]),
+	.W1END1(W1END[1]),
+	.W1END2(W1END[2]),
+	.W1END3(W1END[3]),
+	.W2MID0(W2MID[0]),
+	.W2MID1(W2MID[1]),
+	.W2MID2(W2MID[2]),
+	.W2MID3(W2MID[3]),
+	.W2MID4(W2MID[4]),
+	.W2MID5(W2MID[5]),
+	.W2MID6(W2MID[6]),
+	.W2MID7(W2MID[7]),
+	.W2END0(W2END[0]),
+	.W2END1(W2END[1]),
+	.W2END2(W2END[2]),
+	.W2END3(W2END[3]),
+	.W2END4(W2END[4]),
+	.W2END5(W2END[5]),
+	.W2END6(W2END[6]),
+	.W2END7(W2END[7]),
+	.WW4END0(WW4END[0]),
+	.WW4END1(WW4END[1]),
+	.WW4END2(WW4END[2]),
+	.WW4END3(WW4END[3]),
+	.WW4END4(WW4END[4]),
+	.WW4END5(WW4END[5]),
+	.WW4END6(WW4END[6]),
+	.WW4END7(WW4END[7]),
+	.WW4END8(WW4END[8]),
+	.WW4END9(WW4END[9]),
+	.WW4END10(WW4END[10]),
+	.WW4END11(WW4END[11]),
+	.WW4END12(WW4END[12]),
+	.WW4END13(WW4END[13]),
+	.WW4END14(WW4END[14]),
+	.WW4END15(WW4END[15]),
+	.W6END0(W6END[0]),
+	.W6END1(W6END[1]),
+	.W6END2(W6END[2]),
+	.W6END3(W6END[3]),
+	.W6END4(W6END[4]),
+	.W6END5(W6END[5]),
+	.W6END6(W6END[6]),
+	.W6END7(W6END[7]),
+	.W6END8(W6END[8]),
+	.W6END9(W6END[9]),
+	.W6END10(W6END[10]),
+	.W6END11(W6END[11]),
+	.A_O(A_O),
+	.A_Q(A_Q),
+	.B_O(B_O),
+	.B_Q(B_Q),
+	.E1BEG0(E1BEG[0]),
+	.E1BEG1(E1BEG[1]),
+	.E1BEG2(E1BEG[2]),
+	.E1BEG3(E1BEG[3]),
+	.E2BEG0(E2BEG[0]),
+	.E2BEG1(E2BEG[1]),
+	.E2BEG2(E2BEG[2]),
+	.E2BEG3(E2BEG[3]),
+	.E2BEG4(E2BEG[4]),
+	.E2BEG5(E2BEG[5]),
+	.E2BEG6(E2BEG[6]),
+	.E2BEG7(E2BEG[7]),
+	.E2BEGb0(E2BEGb[0]),
+	.E2BEGb1(E2BEGb[1]),
+	.E2BEGb2(E2BEGb[2]),
+	.E2BEGb3(E2BEGb[3]),
+	.E2BEGb4(E2BEGb[4]),
+	.E2BEGb5(E2BEGb[5]),
+	.E2BEGb6(E2BEGb[6]),
+	.E2BEGb7(E2BEGb[7]),
+	.EE4BEG0(EE4BEG[0]),
+	.EE4BEG1(EE4BEG[1]),
+	.EE4BEG2(EE4BEG[2]),
+	.EE4BEG3(EE4BEG[3]),
+	.EE4BEG4(EE4BEG[4]),
+	.EE4BEG5(EE4BEG[5]),
+	.EE4BEG6(EE4BEG[6]),
+	.EE4BEG7(EE4BEG[7]),
+	.EE4BEG8(EE4BEG[8]),
+	.EE4BEG9(EE4BEG[9]),
+	.EE4BEG10(EE4BEG[10]),
+	.EE4BEG11(EE4BEG[11]),
+	.EE4BEG12(EE4BEG[12]),
+	.EE4BEG13(EE4BEG[13]),
+	.EE4BEG14(EE4BEG[14]),
+	.EE4BEG15(EE4BEG[15]),
+	.E6BEG0(E6BEG[0]),
+	.E6BEG1(E6BEG[1]),
+	.E6BEG2(E6BEG[2]),
+	.E6BEG3(E6BEG[3]),
+	.E6BEG4(E6BEG[4]),
+	.E6BEG5(E6BEG[5]),
+	.E6BEG6(E6BEG[6]),
+	.E6BEG7(E6BEG[7]),
+	.E6BEG8(E6BEG[8]),
+	.E6BEG9(E6BEG[9]),
+	.E6BEG10(E6BEG[10]),
+	.E6BEG11(E6BEG[11]),
+	.A_I(A_I),
+	.A_T(A_T),
+	.B_I(B_I),
+	.B_T(B_T),
+	.ConfigBits(ConfigBits[114-1:8]),
+	.ConfigBits_N(ConfigBits_N[114-1:8])
+	);
+
+endmodule
diff --git a/verilog/rtl/eFPGA_core/eFPGAcore_netlists.vh b/verilog/rtl/eFPGA_core/eFPGAcore_netlists.vh
new file mode 100644
index 0000000..8d0affd
--- /dev/null
+++ b/verilog/rtl/eFPGA_core/eFPGAcore_netlists.vh
@@ -0,0 +1,59 @@
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+`else
+    `include "DSP_bot_ConfigMem.v"
+    `include "DSP_bot_switch_matrix.v"
+    `include "DSP_bot_tile.v"
+    `include "DSP_tile.v"
+    `include "DSP_top_ConfigMem.v"
+    `include "DSP_top_switch_matrix.v"
+    `include "DSP_top_tile.v"
+    `include "E_CPU_IO_bot_ConfigMem.v"
+    `include "E_CPU_IO_bot_switch_matrix.v"
+    `include "E_CPU_IO_bot_tile.v"
+    `include "E_CPU_IO_ConfigMem.v"
+    `include "E_CPU_IO_switch_matrix.v"
+    `include "E_CPU_IO_tile.v"
+    `include "InPass4_frame_config_mux.v"
+    `include "IO_1_bidirectional_frame_config_pass.v"
+    `include "LUT4AB_ConfigMem.v"
+    `include "LUT4AB_switch_matrix.v"
+    `include "LUT4AB_tile.v"
+    `include "LUT4c_frame_config_dffesr.v"
+    `include "MULADD.v"
+    `include "MUX8LUT_frame_config_mux.v"
+    `include "N_term_DSP_switch_matrix.v"
+    `include "N_term_DSP_tile.v"
+    `include "N_term_RAM_IO_switch_matrix.v"
+    `include "N_term_RAM_IO_tile.v"
+    `include "N_term_single2_switch_matrix.v"
+    `include "N_term_single2_tile.v"
+    `include "N_term_single_switch_matrix.v"
+    `include "N_term_single_tile.v"
+    `include "OutPass4_frame_config_mux.v"
+    `include "RAM_IO_ConfigMem.v"
+    `include "RAM_IO_switch_matrix.v"
+    `include "RAM_IO_tile.v"
+    `include "RegFile_32x4.v"
+    `include "RegFile_ConfigMem.v"
+    `include "RegFile_switch_matrix.v"
+    `include "RegFile_tile.v"
+    `include "S_term_DSP_switch_matrix.v"
+    `include "S_term_DSP_tile.v"
+    `include "S_term_RAM_IO_switch_matrix.v"
+    `include "S_term_RAM_IO_tile.v"
+    `include "S_term_single2_switch_matrix.v"
+    `include "S_term_single2_tile.v"
+    `include "S_term_single_switch_matrix.v"
+    `include "S_term_single_tile.v"
+    `include "W_CPU_IO_bot_ConfigMem.v"
+    `include "W_CPU_IO_bot_switch_matrix.v"
+    `include "W_CPU_IO_bot_tile.v"
+    `include "W_CPU_IO_ConfigMem.v"
+    `include "W_CPU_IO_switch_matrix.v"
+    `include "W_CPU_IO_tile.v"
+    `include "W_IO_ConfigMem.v"
+    `include "W_IO_switch_matrix.v"
+    `include "W_IO_tile.v"
+`endif
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_alu.v b/verilog/rtl/ibex_core/flexbex_ibex_alu.v
new file mode 100644
index 0000000..1a126d1
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_alu.v
@@ -0,0 +1,120 @@
+module flexbex_ibex_alu (
+	operator_i,
+	operand_a_i,
+	operand_b_i,
+	multdiv_operand_a_i,
+	multdiv_operand_b_i,
+	multdiv_en_i,
+	adder_result_o,
+	adder_result_ext_o,
+	result_o,
+	comparison_result_o,
+	is_equal_result_o
+);
+	input wire [4:0] operator_i;
+	input wire [31:0] operand_a_i;
+	input wire [31:0] operand_b_i;
+	input wire [32:0] multdiv_operand_a_i;
+	input wire [32:0] multdiv_operand_b_i;
+	input wire multdiv_en_i;
+	output wire [31:0] adder_result_o;
+	output wire [33:0] adder_result_ext_o;
+	output reg [31:0] result_o;
+	output wire comparison_result_o;
+	output wire is_equal_result_o;
+	wire [31:0] operand_a_rev;
+	wire [32:0] operand_b_neg;
+	genvar k;
+	generate
+		for (k = 0; k < 32; k = k + 1) begin : gen_revloop
+			assign operand_a_rev[k] = operand_a_i[31 - k];
+		end
+	endgenerate
+	reg adder_op_b_negate;
+	wire [32:0] adder_in_a;
+	wire [32:0] adder_in_b;
+	wire [31:0] adder_result;
+	always @(*) begin
+		adder_op_b_negate = 1'b0;
+		case (operator_i)
+			5'd1, 5'd16, 5'd17, 5'd13, 5'd15, 5'd9, 5'd11, 5'd12, 5'd14, 5'd8, 5'd10, 5'd18, 5'd19, 5'd20, 5'd21: adder_op_b_negate = 1'b1;
+			default:
+				;
+		endcase
+	end
+	assign adder_in_a = (multdiv_en_i ? multdiv_operand_a_i : {operand_a_i, 1'b1});
+	assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {adder_op_b_negate}};
+	assign adder_in_b = (multdiv_en_i ? multdiv_operand_b_i : operand_b_neg);
+	assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
+	assign adder_result = adder_result_ext_o[32:1];
+	assign adder_result_o = adder_result;
+	wire shift_left;
+	wire shift_arithmetic;
+	wire [4:0] shift_amt;
+	wire [31:0] shift_op_a;
+	wire [31:0] shift_result;
+	wire [31:0] shift_right_result;
+	wire [31:0] shift_left_result;
+	assign shift_amt = operand_b_i[4:0];
+	assign shift_left = operator_i == 5'd7;
+	assign shift_arithmetic = operator_i == 5'd5;
+	assign shift_op_a = (shift_left ? operand_a_rev : operand_a_i);
+	wire [32:0] shift_op_a_32;
+	assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a};
+	wire signed [32:0] shift_right_result_signed;
+	assign shift_right_result_signed = $signed(shift_op_a_32) >>> shift_amt[4:0];
+	assign shift_right_result = shift_right_result_signed[31:0];
+	genvar j;
+	generate
+		for (j = 0; j < 32; j = j + 1) begin : gen_resrevloop
+			assign shift_left_result[j] = shift_right_result[31 - j];
+		end
+	endgenerate
+	assign shift_result = (shift_left ? shift_left_result : shift_right_result);
+	wire is_equal;
+	reg is_greater_equal;
+	reg cmp_signed;
+	always @(*) begin
+		cmp_signed = 1'b0;
+		case (operator_i)
+			5'd12, 5'd14, 5'd8, 5'd10, 5'd18, 5'd20: cmp_signed = 1'b1;
+			default:
+				;
+		endcase
+	end
+	assign is_equal = adder_result == 32'b00000000000000000000000000000000;
+	assign is_equal_result_o = is_equal;
+	always @(*)
+		if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0)
+			is_greater_equal = adder_result[31] == 1'b0;
+		else
+			is_greater_equal = operand_a_i[31] ^ cmp_signed;
+	reg cmp_result;
+	always @(*) begin
+		cmp_result = is_equal;
+		case (operator_i)
+			5'd16: cmp_result = is_equal;
+			5'd17: cmp_result = ~is_equal;
+			5'd12, 5'd13: cmp_result = is_greater_equal & ~is_equal;
+			5'd14, 5'd15: cmp_result = is_greater_equal;
+			5'd8, 5'd18, 5'd9, 5'd19: cmp_result = ~is_greater_equal;
+			5'd20, 5'd21, 5'd10, 5'd11: cmp_result = ~is_greater_equal | is_equal;
+			default:
+				;
+		endcase
+	end
+	assign comparison_result_o = cmp_result;
+	always @(*) begin
+		result_o = 1'sb0;
+		case (operator_i)
+			5'd4: result_o = operand_a_i & operand_b_i;
+			5'd3: result_o = operand_a_i | operand_b_i;
+			5'd2: result_o = operand_a_i ^ operand_b_i;
+			5'd0, 5'd1: result_o = adder_result;
+			5'd7, 5'd6, 5'd5: result_o = shift_result;
+			5'd16, 5'd17, 5'd13, 5'd15, 5'd9, 5'd11, 5'd12, 5'd14, 5'd8, 5'd10, 5'd18, 5'd19, 5'd20, 5'd21: result_o = {31'h00000000, cmp_result};
+			default:
+				;
+		endcase
+	end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_compressed_decoder.v b/verilog/rtl/ibex_core/flexbex_ibex_compressed_decoder.v
new file mode 100644
index 0000000..95ee5fa
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_compressed_decoder.v
@@ -0,0 +1,104 @@
+module flexbex_ibex_compressed_decoder (
+	instr_i,
+	instr_o,
+	is_compressed_o,
+	illegal_instr_o
+);
+	input wire [31:0] instr_i;
+	output reg [31:0] instr_o;
+	output wire is_compressed_o;
+	output reg illegal_instr_o;
+	always @(*) begin
+		illegal_instr_o = 1'b0;
+		instr_o = 1'sb0;
+		case (instr_i[1:0])
+			2'b00:
+				case (instr_i[15:13])
+					3'b000: begin
+						instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], 7'h13};
+						if (instr_i[12:5] == 8'b00000000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], 7'h03};
+					3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, 7'h23};
+					default: illegal_instr_o = 1'b1;
+				endcase
+			2'b01:
+				case (instr_i[15:13])
+					3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], 7'h13};
+					3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], 7'h6f};
+					3'b010: begin
+						instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], 7'h13};
+						if (instr_i[11:7] == 5'b00000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b011: begin
+						instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], 7'h37};
+						if (instr_i[11:7] == 5'h02)
+							instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, 7'h13};
+						else if (instr_i[11:7] == 5'b00000)
+							illegal_instr_o = 1'b1;
+						if ({instr_i[12], instr_i[6:2]} == 6'b000000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b100:
+						case (instr_i[11:10])
+							2'b00, 2'b01: begin
+								instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], 7'h13};
+								if (instr_i[12] == 1'b1)
+									illegal_instr_o = 1'b1;
+								if (instr_i[6:2] == 5'b00000)
+									illegal_instr_o = 1'b1;
+							end
+							2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], 7'h13};
+							2'b11:
+								case ({instr_i[12], instr_i[6:5]})
+									3'b000: instr_o = {9'b010000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], 7'h33};
+									3'b001: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], 7'h33};
+									3'b010: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], 7'h33};
+									3'b011: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], 7'h33};
+									3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1;
+								endcase
+						endcase
+					3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], 7'h63};
+					default:
+						;
+				endcase
+			2'b10:
+				case (instr_i[15:13])
+					3'b000: begin
+						instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], 7'h13};
+						if (instr_i[11:7] == 5'b00000)
+							illegal_instr_o = 1'b1;
+						if ((instr_i[12] == 1'b1) || (instr_i[6:2] == 5'b00000))
+							illegal_instr_o = 1'b1;
+					end
+					3'b010: begin
+						instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], 7'h03};
+						if (instr_i[11:7] == 5'b00000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b100:
+						if (instr_i[12] == 1'b0) begin
+							instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], 7'h33};
+							if (instr_i[6:2] == 5'b00000)
+								instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, 7'h67};
+						end
+						else begin
+							instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], 7'h33};
+							if (instr_i[11:7] == 5'b00000) begin
+								instr_o = 32'h00100073;
+								if (instr_i[6:2] != 5'b00000)
+									illegal_instr_o = 1'b1;
+							end
+							else if (instr_i[6:2] == 5'b00000)
+								instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, 7'h67};
+						end
+					3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, 7'h23};
+					default: illegal_instr_o = 1'b1;
+				endcase
+			default: instr_o = instr_i;
+		endcase
+	end
+	assign is_compressed_o = instr_i[1:0] != 2'b11;
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_controller.v b/verilog/rtl/ibex_core/flexbex_ibex_controller.v
new file mode 100644
index 0000000..ade64aa
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_controller.v
@@ -0,0 +1,340 @@
+module flexbex_ibex_controller (
+	clk,
+	rst_n,
+	fetch_enable_i,
+	ctrl_busy_o,
+	first_fetch_o,
+	is_decoding_o,
+	deassert_we_o,
+	illegal_insn_i,
+	ecall_insn_i,
+	mret_insn_i,
+	dret_insn_i,
+	pipe_flush_i,
+	ebrk_insn_i,
+	csr_status_i,
+	instr_valid_i,
+	instr_req_o,
+	pc_set_o,
+	pc_mux_o,
+	exc_pc_mux_o,
+	data_misaligned_i,
+	branch_in_id_i,
+	branch_set_i,
+	jump_set_i,
+	instr_multicyle_i,
+	irq_i,
+	irq_req_ctrl_i,
+	irq_id_ctrl_i,
+	m_IE_i,
+	irq_ack_o,
+	irq_id_o,
+	exc_cause_o,
+	exc_ack_o,
+	exc_kill_o,
+	debug_req_i,
+	debug_cause_o,
+	debug_csr_save_o,
+	debug_single_step_i,
+	debug_ebreakm_i,
+	csr_save_if_o,
+	csr_save_id_o,
+	csr_cause_o,
+	csr_restore_mret_id_o,
+	csr_restore_dret_id_o,
+	csr_save_cause_o,
+	operand_a_fw_mux_sel_o,
+	halt_if_o,
+	halt_id_o,
+	id_ready_i,
+	perf_jump_o,
+	perf_tbranch_o
+);
+	input wire clk;
+	input wire rst_n;
+	input wire fetch_enable_i;
+	output reg ctrl_busy_o;
+	output reg first_fetch_o;
+	output reg is_decoding_o;
+	output wire deassert_we_o;
+	input wire illegal_insn_i;
+	input wire ecall_insn_i;
+	input wire mret_insn_i;
+	input wire dret_insn_i;
+	input wire pipe_flush_i;
+	input wire ebrk_insn_i;
+	input wire csr_status_i;
+	input wire instr_valid_i;
+	output reg instr_req_o;
+	output reg pc_set_o;
+	output reg [2:0] pc_mux_o;
+	output reg [2:0] exc_pc_mux_o;
+	input wire data_misaligned_i;
+	input wire branch_in_id_i;
+	input wire branch_set_i;
+	input wire jump_set_i;
+	input wire instr_multicyle_i;
+	input wire irq_i;
+	input wire irq_req_ctrl_i;
+	input wire [4:0] irq_id_ctrl_i;
+	input wire m_IE_i;
+	output reg irq_ack_o;
+	output reg [4:0] irq_id_o;
+	output reg [5:0] exc_cause_o;
+	output reg exc_ack_o;
+	output reg exc_kill_o;
+	input wire debug_req_i;
+	output reg [2:0] debug_cause_o;
+	output reg debug_csr_save_o;
+	input wire debug_single_step_i;
+	input wire debug_ebreakm_i;
+	output reg csr_save_if_o;
+	output reg csr_save_id_o;
+	output reg [5:0] csr_cause_o;
+	output reg csr_restore_mret_id_o;
+	output reg csr_restore_dret_id_o;
+	output reg csr_save_cause_o;
+	output wire operand_a_fw_mux_sel_o;
+	output reg halt_if_o;
+	output reg halt_id_o;
+	input wire id_ready_i;
+	output reg perf_jump_o;
+	output reg perf_tbranch_o;
+	reg [3:0] ctrl_fsm_cs;
+	reg [3:0] ctrl_fsm_ns;
+	reg irq_enable_int;
+	reg debug_mode_q;
+	reg debug_mode_n;
+	function automatic [5:0] sv2v_cast_6;
+		input reg [5:0] inp;
+		sv2v_cast_6 = inp;
+	endfunction
+	always @(*) begin
+		instr_req_o = 1'b1;
+		exc_ack_o = 1'b0;
+		exc_kill_o = 1'b0;
+		csr_save_if_o = 1'b0;
+		csr_save_id_o = 1'b0;
+		csr_restore_mret_id_o = 1'b0;
+		csr_restore_dret_id_o = 1'b0;
+		csr_save_cause_o = 1'b0;
+		exc_cause_o = 6'h00;
+		exc_pc_mux_o = 3'd4;
+		csr_cause_o = 6'h00;
+		pc_mux_o = 3'd0;
+		pc_set_o = 1'b0;
+		ctrl_fsm_ns = ctrl_fsm_cs;
+		ctrl_busy_o = 1'b1;
+		is_decoding_o = 1'b0;
+		first_fetch_o = 1'b0;
+		halt_if_o = 1'b0;
+		halt_id_o = 1'b0;
+		irq_ack_o = 1'b0;
+		irq_id_o = irq_id_ctrl_i;
+		irq_enable_int = m_IE_i;
+		debug_csr_save_o = 1'b0;
+		debug_cause_o = 3'h1;
+		debug_mode_n = debug_mode_q;
+		perf_tbranch_o = 1'b0;
+		perf_jump_o = 1'b0;
+		case (ctrl_fsm_cs)
+			4'd0: begin
+				instr_req_o = 1'b0;
+				pc_mux_o = 3'd0;
+				pc_set_o = 1'b1;
+				if (fetch_enable_i)
+					ctrl_fsm_ns = 4'd1;
+			end
+			4'd1: begin
+				instr_req_o = 1'b1;
+				pc_mux_o = 3'd0;
+				pc_set_o = 1'b1;
+				ctrl_fsm_ns = 4'd4;
+			end
+			4'd2: begin
+				ctrl_busy_o = 1'b0;
+				instr_req_o = 1'b0;
+				halt_if_o = 1'b1;
+				halt_id_o = 1'b1;
+				ctrl_fsm_ns = 4'd3;
+			end
+			4'd3: begin
+				ctrl_busy_o = 1'b0;
+				instr_req_o = 1'b0;
+				halt_if_o = 1'b1;
+				halt_id_o = 1'b1;
+				if (((irq_i || debug_req_i) || debug_mode_q) || debug_single_step_i)
+					ctrl_fsm_ns = 4'd4;
+			end
+			4'd4: begin
+				first_fetch_o = 1'b1;
+				if (id_ready_i)
+					ctrl_fsm_ns = 4'd5;
+				if (irq_req_ctrl_i && irq_enable_int) begin
+					ctrl_fsm_ns = 4'd7;
+					halt_if_o = 1'b1;
+					halt_id_o = 1'b1;
+				end
+				if (debug_req_i && !debug_mode_q) begin
+					ctrl_fsm_ns = 4'd8;
+					halt_if_o = 1'b1;
+					halt_id_o = 1'b1;
+				end
+			end
+			4'd5: begin
+				is_decoding_o = 1'b0;
+				case (1'b1)
+					debug_req_i && !debug_mode_q: begin
+						ctrl_fsm_ns = 4'd9;
+						halt_if_o = 1'b1;
+						halt_id_o = 1'b1;
+					end
+					((irq_req_ctrl_i && irq_enable_int) && !debug_req_i) && !debug_mode_q: begin
+						ctrl_fsm_ns = 4'd7;
+						halt_if_o = 1'b1;
+						halt_id_o = 1'b1;
+					end
+					default: begin
+						exc_kill_o = (irq_req_ctrl_i & ~instr_multicyle_i) & ~branch_in_id_i;
+						if (instr_valid_i) begin
+							is_decoding_o = 1'b1;
+							if (branch_set_i || jump_set_i) begin
+								pc_mux_o = 3'd1;
+								pc_set_o = 1'b1;
+								perf_tbranch_o = branch_set_i;
+								perf_jump_o = jump_set_i;
+							end
+							else if ((((((mret_insn_i || dret_insn_i) || ecall_insn_i) || pipe_flush_i) || ebrk_insn_i) || illegal_insn_i) || csr_status_i) begin
+								ctrl_fsm_ns = 4'd6;
+								halt_if_o = 1'b1;
+								halt_id_o = 1'b1;
+							end
+						end
+					end
+				endcase
+				if (debug_single_step_i && !debug_mode_q) begin
+					halt_if_o = 1'b1;
+					ctrl_fsm_ns = 4'd8;
+				end
+			end
+			4'd7: begin
+				pc_mux_o = 3'd2;
+				pc_set_o = 1'b1;
+				exc_pc_mux_o = 3'd4;
+				exc_cause_o = sv2v_cast_6({1'b0, irq_id_ctrl_i});
+				csr_save_cause_o = 1'b1;
+				csr_cause_o = sv2v_cast_6({1'b1, irq_id_ctrl_i});
+				csr_save_if_o = 1'b1;
+				irq_ack_o = 1'b1;
+				exc_ack_o = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd8: begin
+				pc_mux_o = 3'd2;
+				pc_set_o = 1'b1;
+				exc_pc_mux_o = 3'd5;
+				csr_save_if_o = 1'b1;
+				debug_csr_save_o = 1'b1;
+				csr_save_cause_o = 1'b1;
+				if (debug_single_step_i)
+					debug_cause_o = 3'h4;
+				else if (debug_req_i)
+					debug_cause_o = 3'h3;
+				else if (ebrk_insn_i)
+					debug_cause_o = 3'h1;
+				debug_mode_n = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd9: begin
+				pc_mux_o = 3'd2;
+				pc_set_o = 1'b1;
+				exc_pc_mux_o = 3'd5;
+				if (((ebrk_insn_i && debug_ebreakm_i) && !debug_mode_q) || (debug_req_i && !debug_mode_q)) begin
+					csr_save_cause_o = 1'b1;
+					csr_save_id_o = 1'b1;
+					debug_csr_save_o = 1'b1;
+					if (debug_req_i)
+						debug_cause_o = 3'h3;
+					else if (ebrk_insn_i)
+						debug_cause_o = 3'h1;
+				end
+				debug_mode_n = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd6: begin
+				halt_if_o = 1'b1;
+				halt_id_o = 1'b1;
+				if (!pipe_flush_i)
+					ctrl_fsm_ns = 4'd5;
+				else
+					ctrl_fsm_ns = 4'd2;
+				case (1'b1)
+					ecall_insn_i: begin
+						pc_mux_o = 3'd2;
+						pc_set_o = 1'b1;
+						csr_save_id_o = 1'b1;
+						csr_save_cause_o = 1'b1;
+						exc_pc_mux_o = 3'd1;
+						exc_cause_o = 6'h0b;
+						csr_cause_o = 6'h0b;
+					end
+					illegal_insn_i: begin
+						pc_mux_o = 3'd2;
+						pc_set_o = 1'b1;
+						csr_save_id_o = 1'b1;
+						csr_save_cause_o = 1'b1;
+						if (debug_mode_q)
+							exc_pc_mux_o = 3'd6;
+						else
+							exc_pc_mux_o = 3'd0;
+						exc_cause_o = 6'h02;
+						csr_cause_o = 6'h02;
+					end
+					mret_insn_i: begin
+						pc_mux_o = 3'd3;
+						pc_set_o = 1'b1;
+						csr_restore_mret_id_o = 1'b1;
+					end
+					dret_insn_i: begin
+						pc_mux_o = 3'd4;
+						pc_set_o = 1'b1;
+						debug_mode_n = 1'b0;
+						csr_restore_dret_id_o = 1'b1;
+					end
+					ebrk_insn_i:
+						if (debug_mode_q)
+							ctrl_fsm_ns = 4'd9;
+						else if (debug_ebreakm_i)
+							ctrl_fsm_ns = 4'd9;
+						else begin
+							pc_mux_o = 3'd2;
+							pc_set_o = 1'b1;
+							csr_save_id_o = 1'b1;
+							csr_save_cause_o = 1'b1;
+							exc_pc_mux_o = 3'd7;
+							exc_cause_o = 6'h03;
+							csr_cause_o = 6'h03;
+						end
+					default:
+						;
+				endcase
+			end
+			default: begin
+				instr_req_o = 1'b0;
+				ctrl_fsm_ns = 4'd0;
+			end
+		endcase
+	end
+	assign deassert_we_o = ~is_decoding_o | illegal_insn_i;
+	assign operand_a_fw_mux_sel_o = (data_misaligned_i ? 1'd1 : 1'd0);
+	always @(posedge clk or negedge rst_n) begin : UPDATE_REGS
+		if (!rst_n) begin
+			ctrl_fsm_cs <= 4'd0;
+			debug_mode_q <= 1'b0;
+		end
+		else begin
+			ctrl_fsm_cs <= ctrl_fsm_ns;
+			debug_mode_q <= debug_mode_n;
+		end
+	end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_core.v b/verilog/rtl/ibex_core/flexbex_ibex_core.v
new file mode 100644
index 0000000..8fa2125
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_core.v
@@ -0,0 +1,394 @@
+module flexbex_ibex_core (
+	clk_i,
+	rst_ni,
+	test_en_i,
+	core_id_i,
+	cluster_id_i,
+	boot_addr_i,
+	instr_req_o,
+	instr_gnt_i,
+	instr_rvalid_i,
+	instr_addr_o,
+	instr_rdata_i,
+	data_req_o,
+	data_gnt_i,
+	data_rvalid_i,
+	data_we_o,
+	data_be_o,
+	data_addr_o,
+	data_wdata_o,
+	data_rdata_i,
+	data_err_i,
+	irq_i,
+	irq_id_i,
+	irq_ack_o,
+	irq_id_o,
+	debug_req_i,
+	fetch_enable_i,
+	ext_perf_counters_i,
+	eFPGA_operand_a_o,
+	eFPGA_operand_b_o,
+	eFPGA_result_a_i,
+	eFPGA_result_b_i,
+	eFPGA_result_c_i,
+	eFPGA_write_strobe_o,
+	eFPGA_fpga_done_i,
+	eFPGA_en_o,
+	eFPGA_operator_o,
+	eFPGA_delay_o
+);
+	parameter N_EXT_PERF_COUNTERS = 1;
+	parameter [0:0] RV32E = 0;
+	parameter [0:0] RV32M = 1;
+	parameter DM_HALT_ADDRESS = 32'h000000d8;
+	parameter DM_EXCEPTION_ADDRESS = 32'h000000f4;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire test_en_i;
+	input wire [3:0] core_id_i;
+	input wire [5:0] cluster_id_i;
+	input wire [31:0] boot_addr_i;
+	output wire instr_req_o;
+	input wire instr_gnt_i;
+	input wire instr_rvalid_i;
+	output wire [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	output wire data_req_o;
+	input wire data_gnt_i;
+	input wire data_rvalid_i;
+	output wire data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_addr_o;
+	output wire [31:0] data_wdata_o;
+	input wire [31:0] data_rdata_i;
+	input wire data_err_i;
+	input wire irq_i;
+	input wire [4:0] irq_id_i;
+	output wire irq_ack_o;
+	output wire [4:0] irq_id_o;
+	input wire debug_req_i;
+	input wire fetch_enable_i;
+	input wire [N_EXT_PERF_COUNTERS - 1:0] ext_perf_counters_i;
+	output wire [31:0] eFPGA_operand_a_o;
+	output wire [31:0] eFPGA_operand_b_o;
+	input wire [31:0] eFPGA_result_a_i;
+	input wire [31:0] eFPGA_result_b_i;
+	input wire [31:0] eFPGA_result_c_i;
+	output wire eFPGA_write_strobe_o;
+	input eFPGA_fpga_done_i;
+	output wire eFPGA_en_o;
+	output wire [1:0] eFPGA_operator_o;
+	output wire [3:0] eFPGA_delay_o;
+	wire eFPGA_en;
+	assign eFPGA_en_o = eFPGA_en;
+	wire [1:0] eFPGA_operator;
+	assign eFPGA_operator_o = eFPGA_operator;
+	wire [3:0] eFPGA_delay;
+	assign eFPGA_delay_o = eFPGA_delay;
+	wire instr_valid_id;
+	wire [31:0] instr_rdata_id;
+	wire is_compressed_id;
+	wire illegal_c_insn_id;
+	wire [31:0] pc_if;
+	wire [31:0] pc_id;
+	wire clear_instr_valid;
+	wire pc_set;
+	wire [2:0] pc_mux_id;
+	wire [2:0] exc_pc_mux_id;
+	wire [5:0] exc_cause;
+	wire lsu_load_err;
+	wire lsu_store_err;
+	wire is_decoding;
+	wire data_misaligned;
+	wire [31:0] misaligned_addr;
+	wire [31:0] jump_target_ex;
+	wire branch_decision;
+	wire ctrl_busy;
+	wire if_busy;
+	wire lsu_busy;
+	wire core_busy;
+	wire core_ctrl_firstfetch;
+	wire core_busy_int;
+	reg core_busy_q;
+	wire [4:0] alu_operator_ex;
+	wire [31:0] alu_operand_a_ex;
+	wire [31:0] alu_operand_b_ex;
+	wire [31:0] alu_adder_result_ex;
+	wire [31:0] regfile_wdata_ex;
+	wire mult_en_ex;
+	wire div_en_ex;
+	wire [1:0] multdiv_operator_ex;
+	wire [1:0] multdiv_signed_mode_ex;
+	wire [31:0] multdiv_operand_a_ex;
+	wire [31:0] multdiv_operand_b_ex;
+	wire csr_access_ex;
+	wire [1:0] csr_op_ex;
+	wire csr_access;
+	wire [1:0] csr_op;
+	wire [11:0] csr_addr;
+	wire [31:0] csr_rdata;
+	wire [31:0] csr_wdata;
+	wire data_we_ex;
+	wire [1:0] data_type_ex;
+	wire data_sign_ext_ex;
+	wire [1:0] data_reg_offset_ex;
+	wire data_req_ex;
+	wire [31:0] data_wdata_ex;
+	wire [31:0] regfile_wdata_lsu;
+	wire halt_if;
+	wire id_ready;
+	wire ex_ready;
+	wire if_valid;
+	wire id_valid;
+	wire data_valid_lsu;
+	wire instr_req_int;
+	wire m_irq_enable;
+	wire [31:0] mepc;
+	wire [31:0] depc;
+	wire csr_save_cause;
+	wire csr_save_if;
+	wire csr_save_id;
+	wire [5:0] csr_cause;
+	wire csr_restore_mret_id;
+	wire csr_restore_dret_id;
+	wire [2:0] debug_cause;
+	wire debug_csr_save;
+	wire debug_single_step;
+	wire debug_ebreakm;
+	wire perf_imiss;
+	wire perf_jump;
+	wire perf_branch;
+	wire perf_tbranch;
+	wire clk;
+	wire clock_en;
+	assign core_busy_int = (if_busy | ctrl_busy) | lsu_busy;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			core_busy_q <= 1'b0;
+		else
+			core_busy_q <= core_busy_int;
+	assign core_busy = (core_ctrl_firstfetch ? 1'b1 : core_busy_q);
+	assign clock_en = (core_busy | irq_i) | debug_req_i;
+	flexbex_prim_clock_gating core_clock_gate_i(
+		.clk_i(clk_i),
+		.en_i(clock_en),
+		.test_en_i(test_en_i),
+		.clk_o(clk)
+	);
+	flexbex_ibex_if_stage #(
+		.DM_HALT_ADDRESS(DM_HALT_ADDRESS),
+		.DM_EXCEPTION_ADDRESS(DM_EXCEPTION_ADDRESS)
+	) if_stage_i(
+		.clk(clk),
+		.rst_n(rst_ni),
+		.boot_addr_i(boot_addr_i),
+		.req_i(instr_req_int),
+		.instr_req_o(instr_req_o),
+		.instr_addr_o(instr_addr_o),
+		.instr_gnt_i(instr_gnt_i),
+		.instr_rvalid_i(instr_rvalid_i),
+		.instr_rdata_i(instr_rdata_i),
+		.instr_valid_id_o(instr_valid_id),
+		.instr_rdata_id_o(instr_rdata_id),
+		.is_compressed_id_o(is_compressed_id),
+		.illegal_c_insn_id_o(illegal_c_insn_id),
+		.pc_if_o(pc_if),
+		.pc_id_o(pc_id),
+		.clear_instr_valid_i(clear_instr_valid),
+		.pc_set_i(pc_set),
+		.exception_pc_reg_i(mepc),
+		.depc_i(depc),
+		.pc_mux_i(pc_mux_id),
+		.exc_pc_mux_i(exc_pc_mux_id),
+		.exc_vec_pc_mux_i(exc_cause),
+		.jump_target_ex_i(jump_target_ex),
+		.halt_if_i(halt_if),
+		.id_ready_i(id_ready),
+		.if_valid_o(if_valid),
+		.if_busy_o(if_busy),
+		.perf_imiss_o(perf_imiss)
+	);
+	flexbex_ibex_id_stage #(
+		.RV32E(RV32E),
+		.RV32M(RV32M)
+	) id_stage_i(
+		.clk(clk),
+		.rst_n(rst_ni),
+		.test_en_i(test_en_i),
+		.fetch_enable_i(fetch_enable_i),
+		.ctrl_busy_o(ctrl_busy),
+		.core_ctrl_firstfetch_o(core_ctrl_firstfetch),
+		.is_decoding_o(is_decoding),
+		.instr_valid_i(instr_valid_id),
+		.instr_rdata_i(instr_rdata_id),
+		.instr_req_o(instr_req_int),
+		.branch_decision_i(branch_decision),
+		.clear_instr_valid_o(clear_instr_valid),
+		.pc_set_o(pc_set),
+		.pc_mux_o(pc_mux_id),
+		.exc_pc_mux_o(exc_pc_mux_id),
+		.exc_cause_o(exc_cause),
+		.illegal_c_insn_i(illegal_c_insn_id),
+		.is_compressed_i(is_compressed_id),
+		.pc_id_i(pc_id),
+		.halt_if_o(halt_if),
+		.id_ready_o(id_ready),
+		.ex_ready_i(ex_ready),
+		.id_valid_o(id_valid),
+		.alu_operator_ex_o(alu_operator_ex),
+		.alu_operand_a_ex_o(alu_operand_a_ex),
+		.alu_operand_b_ex_o(alu_operand_b_ex),
+		.mult_en_ex_o(mult_en_ex),
+		.div_en_ex_o(div_en_ex),
+		.multdiv_operator_ex_o(multdiv_operator_ex),
+		.multdiv_signed_mode_ex_o(multdiv_signed_mode_ex),
+		.multdiv_operand_a_ex_o(multdiv_operand_a_ex),
+		.multdiv_operand_b_ex_o(multdiv_operand_b_ex),
+		.eFPGA_en_o(eFPGA_en),
+		.eFPGA_operator_o(eFPGA_operator),
+		.eFPGA_operand_a_o(eFPGA_operand_a_o),
+		.eFPGA_operand_b_o(eFPGA_operand_b_o),
+		.eFPGA_delay_o(eFPGA_delay),
+		.csr_access_ex_o(csr_access_ex),
+		.csr_op_ex_o(csr_op_ex),
+		.csr_cause_o(csr_cause),
+		.csr_save_if_o(csr_save_if),
+		.csr_save_id_o(csr_save_id),
+		.csr_restore_mret_id_o(csr_restore_mret_id),
+		.csr_restore_dret_id_o(csr_restore_dret_id),
+		.csr_save_cause_o(csr_save_cause),
+		.data_req_ex_o(data_req_ex),
+		.data_we_ex_o(data_we_ex),
+		.data_type_ex_o(data_type_ex),
+		.data_sign_ext_ex_o(data_sign_ext_ex),
+		.data_reg_offset_ex_o(data_reg_offset_ex),
+		.data_wdata_ex_o(data_wdata_ex),
+		.data_misaligned_i(data_misaligned),
+		.misaligned_addr_i(misaligned_addr),
+		.irq_i(irq_i),
+		.irq_id_i(irq_id_i),
+		.m_irq_enable_i(m_irq_enable),
+		.irq_ack_o(irq_ack_o),
+		.irq_id_o(irq_id_o),
+		.lsu_load_err_i(lsu_load_err),
+		.lsu_store_err_i(lsu_store_err),
+		.debug_cause_o(debug_cause),
+		.debug_csr_save_o(debug_csr_save),
+		.debug_req_i(debug_req_i),
+		.debug_single_step_i(debug_single_step),
+		.debug_ebreakm_i(debug_ebreakm),
+		.regfile_wdata_lsu_i(regfile_wdata_lsu),
+		.regfile_wdata_ex_i(regfile_wdata_ex),
+		.csr_rdata_i(csr_rdata),
+		.perf_jump_o(perf_jump),
+		.perf_branch_o(perf_branch),
+		.perf_tbranch_o(perf_tbranch)
+	);
+	flexbex_ibex_ex_block #(.RV32M(RV32M)) ex_block_i(
+		.clk(clk),
+		.rst_n(rst_ni),
+		.alu_operator_i(alu_operator_ex),
+		.multdiv_operator_i(multdiv_operator_ex),
+		.alu_operand_a_i(alu_operand_a_ex),
+		.alu_operand_b_i(alu_operand_b_ex),
+		.mult_en_i(mult_en_ex),
+		.div_en_i(div_en_ex),
+		.multdiv_signed_mode_i(multdiv_signed_mode_ex),
+		.multdiv_operand_a_i(multdiv_operand_a_ex),
+		.multdiv_operand_b_i(multdiv_operand_b_ex),
+		.alu_adder_result_ex_o(alu_adder_result_ex),
+		.regfile_wdata_ex_o(regfile_wdata_ex),
+		.eFPGA_en_i(eFPGA_en),
+		.eFPGA_operator_i(eFPGA_operator),
+		.eFPGA_fpga_done_i(eFPGA_fpga_done_i),
+		.eFPGA_result_a_i(eFPGA_result_a_i),
+		.eFPGA_result_b_i(eFPGA_result_b_i),
+		.eFPGA_result_c_i(eFPGA_result_c_i),
+		.eFPGA_delay_i(eFPGA_delay),
+		.eFPGA_write_strobe_o(eFPGA_write_strobe_o),
+		.jump_target_o(jump_target_ex),
+		.branch_decision_o(branch_decision),
+		.lsu_en_i(data_req_ex),
+		.lsu_ready_ex_i(data_valid_lsu),
+		.ex_ready_o(ex_ready)
+	);
+	flexbex_ibex_load_store_unit load_store_unit_i(
+		.clk(clk),
+		.rst_n(rst_ni),
+		.data_req_o(data_req_o),
+		.data_gnt_i(data_gnt_i),
+		.data_rvalid_i(data_rvalid_i),
+		.data_err_i(data_err_i),
+		.data_addr_o(data_addr_o),
+		.data_we_o(data_we_o),
+		.data_be_o(data_be_o),
+		.data_wdata_o(data_wdata_o),
+		.data_rdata_i(data_rdata_i),
+		.data_we_ex_i(data_we_ex),
+		.data_type_ex_i(data_type_ex),
+		.data_wdata_ex_i(data_wdata_ex),
+		.data_reg_offset_ex_i(data_reg_offset_ex),
+		.data_sign_ext_ex_i(data_sign_ext_ex),
+		.data_rdata_ex_o(regfile_wdata_lsu),
+		.data_req_ex_i(data_req_ex),
+		.adder_result_ex_i(alu_adder_result_ex),
+		.data_misaligned_o(data_misaligned),
+		.misaligned_addr_o(misaligned_addr),
+		.load_err_o(lsu_load_err),
+		.store_err_o(lsu_store_err),
+		.data_valid_o(data_valid_lsu),
+		.lsu_update_addr_o(),
+		.busy_o(lsu_busy)
+	);
+	flexbex_ibex_cs_registers #(
+		.N_EXT_CNT(N_EXT_PERF_COUNTERS),
+		.RV32E(RV32E),
+		.RV32M(RV32M)
+	) cs_registers_i(
+		.clk(clk),
+		.rst_n(rst_ni),
+		.core_id_i(core_id_i),
+		.cluster_id_i(cluster_id_i),
+		.boot_addr_i(boot_addr_i),
+		.csr_access_i(csr_access),
+		.csr_addr_i(csr_addr),
+		.csr_wdata_i(csr_wdata),
+		.csr_op_i(csr_op),
+		.csr_rdata_o(csr_rdata),
+		.m_irq_enable_o(m_irq_enable),
+		.mepc_o(mepc),
+		.debug_cause_i(debug_cause),
+		.debug_csr_save_i(debug_csr_save),
+		.depc_o(depc),
+		.debug_single_step_o(debug_single_step),
+		.debug_ebreakm_o(debug_ebreakm),
+		.pc_if_i(pc_if),
+		.pc_id_i(pc_id),
+		.csr_save_if_i(csr_save_if),
+		.csr_save_id_i(csr_save_id),
+		.csr_restore_mret_i(csr_restore_mret_id),
+		.csr_restore_dret_i(csr_restore_dret_id),
+		.csr_cause_i(csr_cause),
+		.csr_save_cause_i(csr_save_cause),
+		.if_valid_i(if_valid),
+		.id_valid_i(id_valid),
+		.is_compressed_i(is_compressed_id),
+		.is_decoding_i(is_decoding),
+		.imiss_i(perf_imiss),
+		.pc_set_i(pc_set),
+		.jump_i(perf_jump),
+		.branch_i(perf_branch),
+		.branch_taken_i(perf_tbranch),
+		.mem_load_i((data_req_o & data_gnt_i) & ~data_we_o),
+		.mem_store_i((data_req_o & data_gnt_i) & data_we_o),
+		.ext_counters_i(ext_perf_counters_i)
+	);
+	assign csr_access = csr_access_ex;
+	assign csr_wdata = alu_operand_a_ex;
+	assign csr_op = csr_op_ex;
+	function automatic [11:0] sv2v_cast_12;
+		input reg [11:0] inp;
+		sv2v_cast_12 = inp;
+	endfunction
+	assign csr_addr = sv2v_cast_12((csr_access_ex ? alu_operand_b_ex[11:0] : 12'b000000000000));
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_cs_registers.v b/verilog/rtl/ibex_core/flexbex_ibex_cs_registers.v
new file mode 100644
index 0000000..0230adc
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_cs_registers.v
@@ -0,0 +1,364 @@
+module flexbex_ibex_cs_registers (
+	clk,
+	rst_n,
+	core_id_i,
+	cluster_id_i,
+	boot_addr_i,
+	csr_access_i,
+	csr_addr_i,
+	csr_wdata_i,
+	csr_op_i,
+	csr_rdata_o,
+	m_irq_enable_o,
+	mepc_o,
+	debug_cause_i,
+	debug_csr_save_i,
+	depc_o,
+	debug_single_step_o,
+	debug_ebreakm_o,
+	pc_if_i,
+	pc_id_i,
+	csr_save_if_i,
+	csr_save_id_i,
+	csr_restore_mret_i,
+	csr_restore_dret_i,
+	csr_cause_i,
+	csr_save_cause_i,
+	if_valid_i,
+	id_valid_i,
+	is_compressed_i,
+	is_decoding_i,
+	imiss_i,
+	pc_set_i,
+	jump_i,
+	branch_i,
+	branch_taken_i,
+	mem_load_i,
+	mem_store_i,
+	ext_counters_i
+);
+	parameter N_EXT_CNT = 0;
+	parameter [0:0] RV32E = 0;
+	parameter [0:0] RV32M = 0;
+	input wire clk;
+	input wire rst_n;
+	input wire [3:0] core_id_i;
+	input wire [5:0] cluster_id_i;
+	input wire [31:0] boot_addr_i;
+	input wire csr_access_i;
+	input wire [11:0] csr_addr_i;
+	input wire [31:0] csr_wdata_i;
+	input wire [1:0] csr_op_i;
+	output wire [31:0] csr_rdata_o;
+	output wire m_irq_enable_o;
+	output wire [31:0] mepc_o;
+	input wire [2:0] debug_cause_i;
+	input wire debug_csr_save_i;
+	output wire [31:0] depc_o;
+	output wire debug_single_step_o;
+	output wire debug_ebreakm_o;
+	input wire [31:0] pc_if_i;
+	input wire [31:0] pc_id_i;
+	input wire csr_save_if_i;
+	input wire csr_save_id_i;
+	input wire csr_restore_mret_i;
+	input wire csr_restore_dret_i;
+	input wire [5:0] csr_cause_i;
+	input wire csr_save_cause_i;
+	input wire if_valid_i;
+	input wire id_valid_i;
+	input wire is_compressed_i;
+	input wire is_decoding_i;
+	input wire imiss_i;
+	input wire pc_set_i;
+	input wire jump_i;
+	input wire branch_i;
+	input wire branch_taken_i;
+	input wire mem_load_i;
+	input wire mem_store_i;
+	input wire [N_EXT_CNT - 1:0] ext_counters_i;
+	localparam [1:0] MXL = 2'd1;
+	localparam [31:0] MISA_VALUE = ((((((((((0 | 4) | 0) | (RV32E << 4)) | 0) | 256) | (RV32M << 12)) | 0) | 0) | 0) | 0) | (MXL << 30);
+	localparam N_PERF_COUNTERS = 11 + N_EXT_CNT;
+	localparam N_PERF_REGS = N_PERF_COUNTERS;
+	wire [N_PERF_COUNTERS - 1:0] PCCR_in;
+	reg [N_PERF_COUNTERS - 1:0] PCCR_inc;
+	reg [N_PERF_COUNTERS - 1:0] PCCR_inc_q;
+	reg [(N_PERF_REGS * 32) - 1:0] PCCR_q;
+	reg [(N_PERF_REGS * 32) - 1:0] PCCR_n;
+	reg [1:0] PCMR_n;
+	reg [1:0] PCMR_q;
+	reg [N_PERF_COUNTERS - 1:0] PCER_n;
+	reg [N_PERF_COUNTERS - 1:0] PCER_q;
+	reg [31:0] perf_rdata;
+	reg [4:0] pccr_index;
+	reg pccr_all_sel;
+	reg is_pccr;
+	reg is_pcer;
+	reg is_pcmr;
+	reg [31:0] csr_wdata_int;
+	reg [31:0] csr_rdata_int;
+	reg csr_we_int;
+	reg [31:0] mepc_q;
+	reg [31:0] mepc_n;
+	reg [31:0] dcsr_q;
+	reg [31:0] dcsr_n;
+	reg [31:0] depc_q;
+	reg [31:0] depc_n;
+	reg [31:0] dscratch0_q;
+	reg [31:0] dscratch0_n;
+	reg [31:0] dscratch1_q;
+	reg [31:0] dscratch1_n;
+	reg [5:0] mcause_q;
+	reg [5:0] mcause_n;
+	reg [3:0] mstatus_q;
+	reg [3:0] mstatus_n;
+	reg [31:0] exception_pc;
+	always @(*) begin
+		csr_rdata_int = 1'sb0;
+		case (csr_addr_i)
+			12'h300: csr_rdata_int = {19'b0000000000000000000, mstatus_q[1-:2], 3'b000, mstatus_q[2], 3'h0, mstatus_q[3], 3'h0};
+			12'h305: csr_rdata_int = boot_addr_i;
+			12'h341: csr_rdata_int = mepc_q;
+			12'h342: csr_rdata_int = {mcause_q[5], 26'b00000000000000000000000000, mcause_q[4:0]};
+			12'hf14: csr_rdata_int = {21'b000000000000000000000, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
+			12'h301: csr_rdata_int = MISA_VALUE;
+			12'h7b0: csr_rdata_int = dcsr_q;
+			12'h7b1: csr_rdata_int = depc_q;
+			12'h7b2: csr_rdata_int = dscratch0_q;
+			12'h7b3: csr_rdata_int = dscratch1_q;
+			default:
+				;
+		endcase
+	end
+	always @(*) begin
+		mepc_n = mepc_q;
+		depc_n = depc_q;
+		dcsr_n = dcsr_q;
+		dscratch0_n = dscratch0_q;
+		dscratch1_n = dscratch1_q;
+		mstatus_n = mstatus_q;
+		mcause_n = mcause_q;
+		exception_pc = pc_id_i;
+		case (csr_addr_i)
+			12'h300:
+				if (csr_we_int)
+					mstatus_n = {csr_wdata_int[3], csr_wdata_int[7], 2'b11};
+			12'h341:
+				if (csr_we_int)
+					mepc_n = csr_wdata_int;
+			12'h342:
+				if (csr_we_int)
+					mcause_n = {csr_wdata_int[31], csr_wdata_int[4:0]};
+			12'h7b0:
+				if (csr_we_int) begin
+					dcsr_n = csr_wdata_int;
+					dcsr_n[31-:4] = 4'd4;
+					dcsr_n[1-:2] = 2'b11;
+					dcsr_n[3] = 1'b0;
+					dcsr_n[4] = 1'b0;
+					dcsr_n[10] = 1'b0;
+					dcsr_n[9] = 1'b0;
+					dcsr_n[5] = 1'b0;
+					dcsr_n[14] = 1'b0;
+					dcsr_n[27-:12] = 12'h000;
+				end
+			12'h7b1:
+				if (csr_we_int && (csr_wdata_int[0] == 1'b0))
+					depc_n = csr_wdata_int;
+			12'h7b2:
+				if (csr_we_int)
+					dscratch0_n = csr_wdata_int;
+			12'h7b3:
+				if (csr_we_int)
+					dscratch1_n = csr_wdata_int;
+			default:
+				;
+		endcase
+		case (1'b1)
+			csr_save_cause_i: begin
+				case (1'b1)
+					csr_save_if_i: exception_pc = pc_if_i;
+					csr_save_id_i: exception_pc = pc_id_i;
+					default:
+						;
+				endcase
+				if (debug_csr_save_i) begin
+					dcsr_n[1-:2] = 2'b11;
+					dcsr_n[8-:3] = debug_cause_i;
+					depc_n = exception_pc;
+				end
+				else begin
+					mstatus_n[2] = mstatus_q[3];
+					mstatus_n[3] = 1'b0;
+					mstatus_n[1-:2] = 2'b11;
+					mepc_n = exception_pc;
+					mcause_n = csr_cause_i;
+				end
+			end
+			csr_restore_mret_i: begin
+				mstatus_n[3] = mstatus_q[2];
+				mstatus_n[2] = 1'b1;
+			end
+			csr_restore_dret_i: begin
+				mstatus_n[3] = mstatus_q[2];
+				mstatus_n[2] = 1'b1;
+			end
+			default:
+				;
+		endcase
+	end
+	always @(*) begin
+		csr_wdata_int = csr_wdata_i;
+		csr_we_int = 1'b1;
+		case (csr_op_i)
+			2'd1: csr_wdata_int = csr_wdata_i;
+			2'd2: csr_wdata_int = csr_wdata_i | csr_rdata_o;
+			2'd3: csr_wdata_int = ~csr_wdata_i & csr_rdata_o;
+			2'd0: begin
+				csr_wdata_int = csr_wdata_i;
+				csr_we_int = 1'b0;
+			end
+			default:
+				;
+		endcase
+	end
+	assign csr_rdata_o = ((is_pccr || is_pcer) || is_pcmr ? perf_rdata : csr_rdata_int);
+	assign m_irq_enable_o = mstatus_q[3];
+	assign mepc_o = mepc_q;
+	assign depc_o = depc_q;
+	assign debug_single_step_o = dcsr_q[2];
+	assign debug_ebreakm_o = dcsr_q[15];
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			mstatus_q <= 4'b0011;
+			mepc_q <= 1'sb0;
+			mcause_q <= 1'sb0;
+			depc_q <= 1'sb0;
+			dcsr_q <= 32'b00000000000000000000000000000011;
+			dscratch0_q <= 1'sb0;
+			dscratch1_q <= 1'sb0;
+		end
+		else begin
+			mstatus_q <= {mstatus_n[3], mstatus_n[2], 2'b11};
+			mepc_q <= mepc_n;
+			mcause_q <= mcause_n;
+			depc_q <= depc_n;
+			dcsr_q <= dcsr_n;
+			dscratch0_q <= dscratch0_n;
+			dscratch1_q <= dscratch1_n;
+		end
+	wire [11:0] csr_addr;
+	assign csr_addr = {csr_addr_i};
+	assign PCCR_in[0] = 1'b1;
+	assign PCCR_in[1] = if_valid_i;
+	assign PCCR_in[2] = 1'b0;
+	assign PCCR_in[3] = 1'b0;
+	assign PCCR_in[4] = imiss_i & ~pc_set_i;
+	assign PCCR_in[5] = mem_load_i;
+	assign PCCR_in[6] = mem_store_i;
+	assign PCCR_in[7] = jump_i;
+	assign PCCR_in[8] = branch_i;
+	assign PCCR_in[9] = branch_taken_i;
+	assign PCCR_in[10] = (id_valid_i & is_decoding_i) & is_compressed_i;
+	genvar i;
+	generate
+		for (i = 0; i < N_EXT_CNT; i = i + 1) begin : gen_extcounters
+			assign PCCR_in[(N_PERF_COUNTERS - N_EXT_CNT) + i] = ext_counters_i[i];
+		end
+	endgenerate
+	always @(*) begin
+		is_pccr = 1'b0;
+		is_pcmr = 1'b0;
+		is_pcer = 1'b0;
+		pccr_all_sel = 1'b0;
+		pccr_index = 1'sb0;
+		perf_rdata = 1'sb0;
+		if (csr_access_i) begin
+			case (csr_addr_i)
+				12'h7a0: begin
+					is_pcer = 1'b1;
+					perf_rdata[N_PERF_COUNTERS - 1:0] = PCER_q;
+				end
+				12'h7a1: begin
+					is_pcmr = 1'b1;
+					perf_rdata[1:0] = PCMR_q;
+				end
+				12'h79f: begin
+					is_pccr = 1'b1;
+					pccr_all_sel = 1'b1;
+				end
+				default:
+					;
+			endcase
+			if (csr_addr[11:5] == 7'b0111100) begin
+				is_pccr = 1'b1;
+				pccr_index = csr_addr[4:0];
+				perf_rdata = (csr_addr[4:0] < N_PERF_COUNTERS ? PCCR_q[csr_addr[4:0] * 32+:32] : {32 {1'sb0}});
+			end
+		end
+	end
+	always @(*) begin : sv2v_autoblock_1
+		reg signed [31:0] c;
+		for (c = 0; c < N_PERF_COUNTERS; c = c + 1)
+			begin : PERF_CNT_INC
+				PCCR_inc[c] = (PCCR_in[c] & PCER_q[c]) & PCMR_q[0];
+				PCCR_n[c * 32+:32] = PCCR_q[c * 32+:32];
+				if ((PCCR_inc_q[c] == 1'b1) && ((PCCR_q[c * 32+:32] != 32'hffffffff) || (PCMR_q[1] == 1'b0)))
+					PCCR_n[c * 32+:32] = PCCR_q[c * 32+:32] + 32'h00000001;
+				if (is_pccr && (pccr_all_sel || (pccr_index == c)))
+					case (csr_op_i)
+						2'd0:
+							;
+						2'd1: PCCR_n[c * 32+:32] = csr_wdata_i;
+						2'd2: PCCR_n[c * 32+:32] = csr_wdata_i | PCCR_q[c * 32+:32];
+						2'd3: PCCR_n[c * 32+:32] = csr_wdata_i & ~PCCR_q[c * 32+:32];
+					endcase
+			end
+	end
+	always @(*) begin
+		PCMR_n = PCMR_q;
+		PCER_n = PCER_q;
+		if (is_pcmr)
+			case (csr_op_i)
+				2'd0:
+					;
+				2'd1: PCMR_n = csr_wdata_i[1:0];
+				2'd2: PCMR_n = csr_wdata_i[1:0] | PCMR_q;
+				2'd3: PCMR_n = csr_wdata_i[1:0] & ~PCMR_q;
+			endcase
+		if (is_pcer)
+			case (csr_op_i)
+				2'd0:
+					;
+				2'd1: PCER_n = csr_wdata_i[N_PERF_COUNTERS - 1:0];
+				2'd2: PCER_n = csr_wdata_i[N_PERF_COUNTERS - 1:0] | PCER_q;
+				2'd3: PCER_n = csr_wdata_i[N_PERF_COUNTERS - 1:0] & ~PCER_q;
+			endcase
+	end
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			PCER_q <= 1'sb0;
+			PCMR_q <= 2'h3;
+			begin : sv2v_autoblock_2
+				reg signed [31:0] r;
+				for (r = 0; r < N_PERF_REGS; r = r + 1)
+					begin
+						PCCR_q[r * 32+:32] <= 1'sb0;
+						PCCR_inc_q[r] <= 1'sb0;
+					end
+			end
+		end
+		else begin
+			PCER_q <= PCER_n;
+			PCMR_q <= PCMR_n;
+			begin : sv2v_autoblock_3
+				reg signed [31:0] r;
+				for (r = 0; r < N_PERF_REGS; r = r + 1)
+					begin
+						PCCR_q[r * 32+:32] <= PCCR_n[r * 32+:32];
+						PCCR_inc_q[r] <= PCCR_inc[r];
+					end
+			end
+		end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_decoder.v b/verilog/rtl/ibex_core/flexbex_ibex_decoder.v
new file mode 100644
index 0000000..d763cff
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_decoder.v
@@ -0,0 +1,406 @@
+module flexbex_ibex_decoder (
+	deassert_we_i,
+	data_misaligned_i,
+	branch_mux_i,
+	jump_mux_i,
+	illegal_insn_o,
+	ebrk_insn_o,
+	mret_insn_o,
+	dret_insn_o,
+	ecall_insn_o,
+	pipe_flush_o,
+	instr_rdata_i,
+	illegal_c_insn_i,
+	alu_operator_o,
+	alu_op_a_mux_sel_o,
+	alu_op_b_mux_sel_o,
+	imm_a_mux_sel_o,
+	imm_b_mux_sel_o,
+	mult_int_en_o,
+	div_int_en_o,
+	multdiv_operator_o,
+	multdiv_signed_mode_o,
+	regfile_we_o,
+	csr_access_o,
+	csr_op_o,
+	csr_status_o,
+	data_req_o,
+	data_we_o,
+	data_type_o,
+	data_sign_extension_o,
+	data_reg_offset_o,
+	jump_in_id_o,
+	branch_in_id_o,
+	eFPGA_operator_o,
+	eFPGA_int_en_o,
+	eFPGA_delay_o
+);
+	parameter [0:0] RV32M = 1;
+	input wire deassert_we_i;
+	input wire data_misaligned_i;
+	input wire branch_mux_i;
+	input wire jump_mux_i;
+	output reg illegal_insn_o;
+	output reg ebrk_insn_o;
+	output reg mret_insn_o;
+	output reg dret_insn_o;
+	output reg ecall_insn_o;
+	output reg pipe_flush_o;
+	input wire [31:0] instr_rdata_i;
+	input wire illegal_c_insn_i;
+	output reg [4:0] alu_operator_o;
+	output reg [1:0] alu_op_a_mux_sel_o;
+	output reg alu_op_b_mux_sel_o;
+	output reg imm_a_mux_sel_o;
+	output reg [2:0] imm_b_mux_sel_o;
+	output wire mult_int_en_o;
+	output wire div_int_en_o;
+	output reg [1:0] multdiv_operator_o;
+	output reg [1:0] multdiv_signed_mode_o;
+	output wire regfile_we_o;
+	output reg csr_access_o;
+	output wire [1:0] csr_op_o;
+	output reg csr_status_o;
+	output wire data_req_o;
+	output reg data_we_o;
+	output reg [1:0] data_type_o;
+	output reg data_sign_extension_o;
+	output reg [1:0] data_reg_offset_o;
+	output wire jump_in_id_o;
+	output wire branch_in_id_o;
+	output reg [1:0] eFPGA_operator_o;
+	output wire eFPGA_int_en_o;
+	output reg [3:0] eFPGA_delay_o;
+	reg regfile_we;
+	reg data_req;
+	reg mult_int_en;
+	reg div_int_en;
+	reg branch_in_id;
+	reg jump_in_id;
+	reg eFPGA_int_en;
+	reg [1:0] csr_op;
+	reg csr_illegal;
+	reg [6:0] opcode;
+	always @(*) begin
+		jump_in_id = 1'b0;
+		branch_in_id = 1'b0;
+		alu_operator_o = 5'd19;
+		alu_op_a_mux_sel_o = 2'd0;
+		alu_op_b_mux_sel_o = 1'd0;
+		imm_a_mux_sel_o = 1'd1;
+		imm_b_mux_sel_o = 3'd0;
+		mult_int_en = 1'b0;
+		div_int_en = 1'b0;
+		multdiv_operator_o = 2'd0;
+		multdiv_signed_mode_o = 2'b00;
+		eFPGA_int_en = 1'b0;
+		eFPGA_operator_o = 2'b00;
+		regfile_we = 1'b0;
+		csr_access_o = 1'b0;
+		csr_status_o = 1'b0;
+		csr_illegal = 1'b0;
+		csr_op = 2'd0;
+		data_we_o = 1'b0;
+		data_type_o = 2'b00;
+		data_sign_extension_o = 1'b0;
+		data_reg_offset_o = 2'b00;
+		data_req = 1'b0;
+		illegal_insn_o = 1'b0;
+		ebrk_insn_o = 1'b0;
+		mret_insn_o = 1'b0;
+		dret_insn_o = 1'b0;
+		ecall_insn_o = 1'b0;
+		pipe_flush_o = 1'b0;
+		opcode = instr_rdata_i[6:0];
+		case (opcode)
+			7'h6f: begin
+				jump_in_id = 1'b1;
+				if (jump_mux_i) begin
+					alu_op_a_mux_sel_o = 2'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd4;
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b0;
+				end
+				else begin
+					alu_op_a_mux_sel_o = 2'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd5;
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b1;
+				end
+			end
+			7'h67: begin
+				jump_in_id = 1'b1;
+				if (jump_mux_i) begin
+					alu_op_a_mux_sel_o = 2'd0;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd0;
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b0;
+				end
+				else begin
+					alu_op_a_mux_sel_o = 2'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd5;
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b1;
+				end
+				if (instr_rdata_i[14:12] != 3'b000) begin
+					jump_in_id = 1'b0;
+					regfile_we = 1'b0;
+					illegal_insn_o = 1'b1;
+				end
+			end
+			7'h63: begin
+				branch_in_id = 1'b1;
+				if (branch_mux_i)
+					case (instr_rdata_i[14:12])
+						3'b000: alu_operator_o = 5'd16;
+						3'b001: alu_operator_o = 5'd17;
+						3'b100: alu_operator_o = 5'd8;
+						3'b101: alu_operator_o = 5'd14;
+						3'b110: alu_operator_o = 5'd9;
+						3'b111: alu_operator_o = 5'd15;
+						default: illegal_insn_o = 1'b1;
+					endcase
+				else begin
+					alu_op_a_mux_sel_o = 2'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd2;
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b0;
+				end
+			end
+			7'h23: begin
+				data_req = 1'b1;
+				data_we_o = 1'b1;
+				alu_operator_o = 5'd0;
+				if (!instr_rdata_i[14]) begin
+					imm_b_mux_sel_o = 3'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+				end
+				else begin
+					data_req = 1'b0;
+					data_we_o = 1'b0;
+					illegal_insn_o = 1'b1;
+				end
+				case (instr_rdata_i[13:12])
+					2'b00: data_type_o = 2'b10;
+					2'b01: data_type_o = 2'b01;
+					2'b10: data_type_o = 2'b00;
+					default: begin
+						data_req = 1'b0;
+						data_we_o = 1'b0;
+						illegal_insn_o = 1'b1;
+					end
+				endcase
+			end
+			7'h03: begin
+				data_req = 1'b1;
+				regfile_we = 1'b1;
+				data_type_o = 2'b00;
+				alu_operator_o = 5'd0;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd0;
+				data_sign_extension_o = ~instr_rdata_i[14];
+				case (instr_rdata_i[13:12])
+					2'b00: data_type_o = 2'b10;
+					2'b01: data_type_o = 2'b01;
+					2'b10: data_type_o = 2'b00;
+					default: data_type_o = 2'b00;
+				endcase
+				if (instr_rdata_i[14:12] == 3'b111) begin
+					alu_op_b_mux_sel_o = 1'd0;
+					data_sign_extension_o = ~instr_rdata_i[30];
+					case (instr_rdata_i[31:25])
+						7'b0000000, 7'b0100000: data_type_o = 2'b10;
+						7'b0001000, 7'b0101000: data_type_o = 2'b01;
+						7'b0010000: data_type_o = 2'b00;
+						default: illegal_insn_o = 1'b1;
+					endcase
+				end
+				if (instr_rdata_i[14:12] == 3'b011)
+					illegal_insn_o = 1'b1;
+			end
+			7'h37: begin
+				alu_op_a_mux_sel_o = 2'd2;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_a_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd3;
+				alu_operator_o = 5'd0;
+				regfile_we = 1'b1;
+			end
+			7'h17: begin
+				alu_op_a_mux_sel_o = 2'd1;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd3;
+				alu_operator_o = 5'd0;
+				regfile_we = 1'b1;
+			end
+			7'h13: begin
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd0;
+				regfile_we = 1'b1;
+				case (instr_rdata_i[14:12])
+					3'b000: alu_operator_o = 5'd0;
+					3'b010: alu_operator_o = 5'd18;
+					3'b011: alu_operator_o = 5'd19;
+					3'b100: alu_operator_o = 5'd2;
+					3'b110: alu_operator_o = 5'd3;
+					3'b111: alu_operator_o = 5'd4;
+					3'b001: begin
+						alu_operator_o = 5'd7;
+						if (instr_rdata_i[31:25] != 7'b0000000)
+							illegal_insn_o = 1'b1;
+					end
+					3'b101:
+						if (instr_rdata_i[31:25] == 7'b0000000)
+							alu_operator_o = 5'd6;
+						else if (instr_rdata_i[31:25] == 7'b0100000)
+							alu_operator_o = 5'd5;
+						else
+							illegal_insn_o = 1'b1;
+					default:
+						;
+				endcase
+			end
+			7'h33: begin
+				regfile_we = 1'b1;
+				if (instr_rdata_i[31])
+					illegal_insn_o = 1'b1;
+				else if (!instr_rdata_i[28])
+					case ({instr_rdata_i[30:25], instr_rdata_i[14:12]})
+						9'b000000000: alu_operator_o = 5'd0;
+						9'b100000000: alu_operator_o = 5'd1;
+						9'b000000010: alu_operator_o = 5'd18;
+						9'b000000011: alu_operator_o = 5'd19;
+						9'b000000100: alu_operator_o = 5'd2;
+						9'b000000110: alu_operator_o = 5'd3;
+						9'b000000111: alu_operator_o = 5'd4;
+						9'b000000001: alu_operator_o = 5'd7;
+						9'b000000101: alu_operator_o = 5'd6;
+						9'b100000101: alu_operator_o = 5'd5;
+						9'b000001000: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd0;
+							mult_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001001: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd1;
+							mult_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001010: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd1;
+							mult_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b01;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001011: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd1;
+							mult_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001100: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd2;
+							div_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001101: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd2;
+							div_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001110: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd3;
+							div_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						9'b000001111: begin
+							alu_operator_o = 5'd0;
+							multdiv_operator_o = 2'd3;
+							div_int_en = 1'b1;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn_o = (RV32M ? 1'b0 : 1'b1);
+						end
+						default: illegal_insn_o = 1'b1;
+					endcase
+			end
+			7'h0b: begin
+				regfile_we = 1'b1;
+				eFPGA_operator_o = instr_rdata_i[13:12];
+				eFPGA_delay_o = instr_rdata_i[28:25];
+				eFPGA_int_en = 1'b1;
+			end
+			7'h0f:
+				if (instr_rdata_i[14:12] == 3'b000) begin
+					alu_operator_o = 5'd0;
+					regfile_we = 1'b0;
+				end
+				else
+					illegal_insn_o = 1'b1;
+			7'h73:
+				if (instr_rdata_i[14:12] == 3'b000)
+					case (instr_rdata_i[31:20])
+						12'h000: ecall_insn_o = 1'b1;
+						12'h001: ebrk_insn_o = 1'b1;
+						12'h302: mret_insn_o = 1'b1;
+						12'h7b2: dret_insn_o = 1'b1;
+						12'h105: pipe_flush_o = 1'b1;
+						default: illegal_insn_o = 1'b1;
+					endcase
+				else begin
+					csr_access_o = 1'b1;
+					regfile_we = 1'b1;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_a_mux_sel_o = 1'd0;
+					imm_b_mux_sel_o = 3'd0;
+					if (instr_rdata_i[14])
+						alu_op_a_mux_sel_o = 2'd2;
+					else
+						alu_op_a_mux_sel_o = 2'd0;
+					case (instr_rdata_i[13:12])
+						2'b01: csr_op = 2'd1;
+						2'b10: csr_op = 2'd2;
+						2'b11: csr_op = 2'd3;
+						default: csr_illegal = 1'b1;
+					endcase
+					if (!csr_illegal)
+						if (((((instr_rdata_i[31:20] == 12'h300) || (instr_rdata_i[31:20] == 12'h7b0)) || (instr_rdata_i[31:20] == 12'h7b1)) || (instr_rdata_i[31:20] == 12'h7b2)) || (instr_rdata_i[31:20] == 12'h7b3))
+							csr_status_o = 1'b1;
+					illegal_insn_o = csr_illegal;
+				end
+			default: illegal_insn_o = 1'b1;
+		endcase
+		if (illegal_c_insn_i)
+			illegal_insn_o = 1'b1;
+		if (data_misaligned_i) begin
+			alu_op_a_mux_sel_o = 2'd0;
+			alu_op_b_mux_sel_o = 1'd1;
+			imm_b_mux_sel_o = 3'd5;
+			regfile_we = 1'b0;
+		end
+	end
+	assign regfile_we_o = (deassert_we_i ? 1'b0 : regfile_we);
+	assign mult_int_en_o = (RV32M ? (deassert_we_i ? 1'b0 : mult_int_en) : 1'b0);
+	assign div_int_en_o = (RV32M ? (deassert_we_i ? 1'b0 : div_int_en) : 1'b0);
+	assign data_req_o = (deassert_we_i ? 1'b0 : data_req);
+	assign csr_op_o = (deassert_we_i ? 2'd0 : csr_op);
+	assign jump_in_id_o = (deassert_we_i ? 1'b0 : jump_in_id);
+	assign branch_in_id_o = (deassert_we_i ? 1'b0 : branch_in_id);
+	assign eFPGA_int_en_o = (deassert_we_i ? 1'b0 : eFPGA_int_en);
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_defines.v b/verilog/rtl/ibex_core/flexbex_ibex_defines.v
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_defines.v
@@ -0,0 +1 @@
+
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_eFPGA.v b/verilog/rtl/ibex_core/flexbex_ibex_eFPGA.v
new file mode 100644
index 0000000..78389c5
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_eFPGA.v
@@ -0,0 +1,66 @@
+module flexbex_ibex_eFPGA (
+	clk,
+	rst_n,
+	en_i,
+	operator_i,
+	ready_o,
+	endresult_o,
+	result_a_i,
+	result_b_i,
+	result_c_i,
+	delay_i,
+	write_strobe,
+	efpga_done_i
+);
+	input wire clk;
+	input wire rst_n;
+	input wire en_i;
+	input wire [1:0] operator_i;
+	output wire ready_o;
+	output reg [31:0] endresult_o;
+	input wire [31:0] result_a_i;
+	input wire [31:0] result_b_i;
+	input wire [31:0] result_c_i;
+	input wire [3:0] delay_i;
+	output reg write_strobe;
+	input wire efpga_done_i;
+	reg [1:0] eFPGA_fsm_r;
+	reg [3:0] count;
+	always @(posedge clk)
+		if (!rst_n) begin
+			eFPGA_fsm_r <= 2'd0;
+			count <= 0;
+			write_strobe <= 1'b0;
+		end
+		else
+			case (eFPGA_fsm_r)
+				2'd0: begin
+					count <= 0;
+					if (en_i == 1) begin
+						eFPGA_fsm_r <= 2'd1;
+						if (operator_i == 2'b11)
+							write_strobe <= 1'b1;
+					end
+				end
+				2'd1: begin
+					count <= count + 1;
+					if (((count == delay_i) & (delay_i != 4'b1111)) | ((delay_i == 4'b1111) & efpga_done_i)) begin
+						eFPGA_fsm_r <= 2'd2;
+						case (operator_i)
+							2'b00: endresult_o <= result_a_i;
+							2'b01: endresult_o <= result_b_i;
+							2'b10: endresult_o <= result_c_i;
+							2'b11: begin
+								endresult_o <= result_a_i;
+								write_strobe <= 1'b0;
+							end
+							default: endresult_o <= result_a_i;
+						endcase
+					end
+				end
+				2'd2: eFPGA_fsm_r <= 2'd0;
+				default:
+					;
+			endcase
+	assign ready_o = eFPGA_fsm_r == 2'd2;
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_ex_block.v b/verilog/rtl/ibex_core/flexbex_ibex_ex_block.v
new file mode 100644
index 0000000..f4d2e47
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_ex_block.v
@@ -0,0 +1,133 @@
+module flexbex_ibex_ex_block (
+	clk,
+	rst_n,
+	alu_operator_i,
+	multdiv_operator_i,
+	mult_en_i,
+	div_en_i,
+	eFPGA_en_i,
+	eFPGA_operator_i,
+	eFPGA_result_a_i,
+	eFPGA_result_b_i,
+	eFPGA_result_c_i,
+	eFPGA_delay_i,
+	eFPGA_fpga_done_i,
+	eFPGA_write_strobe_o,
+	alu_operand_a_i,
+	alu_operand_b_i,
+	multdiv_signed_mode_i,
+	multdiv_operand_a_i,
+	multdiv_operand_b_i,
+	alu_adder_result_ex_o,
+	regfile_wdata_ex_o,
+	jump_target_o,
+	branch_decision_o,
+	lsu_en_i,
+	lsu_ready_ex_i,
+	ex_ready_o
+);
+	parameter [0:0] RV32M = 1;
+	input wire clk;
+	input wire rst_n;
+	input wire [4:0] alu_operator_i;
+	input wire [1:0] multdiv_operator_i;
+	input wire mult_en_i;
+	input wire div_en_i;
+	input wire eFPGA_en_i;
+	input wire [1:0] eFPGA_operator_i;
+	input wire [31:0] eFPGA_result_a_i;
+	input wire [31:0] eFPGA_result_b_i;
+	input wire [31:0] eFPGA_result_c_i;
+	input wire [3:0] eFPGA_delay_i;
+	input wire eFPGA_fpga_done_i;
+	output wire eFPGA_write_strobe_o;
+	input wire [31:0] alu_operand_a_i;
+	input wire [31:0] alu_operand_b_i;
+	input wire [1:0] multdiv_signed_mode_i;
+	input wire [31:0] multdiv_operand_a_i;
+	input wire [31:0] multdiv_operand_b_i;
+	output wire [31:0] alu_adder_result_ex_o;
+	output wire [31:0] regfile_wdata_ex_o;
+	output wire [31:0] jump_target_o;
+	output wire branch_decision_o;
+	input wire lsu_en_i;
+	input wire lsu_ready_ex_i;
+	output reg ex_ready_o;
+	localparam MULT_TYPE = 1;
+	wire [31:0] alu_result;
+	wire [31:0] multdiv_result;
+	wire [31:0] eFPGA_result;
+	wire [32:0] multdiv_alu_operand_b;
+	wire [32:0] multdiv_alu_operand_a;
+	wire [33:0] alu_adder_result_ext;
+	wire alu_cmp_result;
+	wire alu_is_equal_result;
+	wire multdiv_ready;
+	wire multdiv_en_sel;
+	wire multdiv_en;
+	generate
+		if (RV32M) begin : gen_multdiv_m
+			assign multdiv_en_sel = (MULT_TYPE ? div_en_i : mult_en_i | div_en_i);
+			assign multdiv_en = mult_en_i | div_en_i;
+		end
+		else begin : gen_multdiv_nom
+			assign multdiv_en_sel = 1'b0;
+			assign multdiv_en = 1'b0;
+		end
+	endgenerate
+	assign regfile_wdata_ex_o = (multdiv_en ? multdiv_result : (eFPGA_en_i ? eFPGA_result : alu_result));
+	assign branch_decision_o = alu_cmp_result;
+	assign jump_target_o = alu_adder_result_ex_o;
+	flexbex_ibex_alu alu_i(
+		.operator_i(alu_operator_i),
+		.operand_a_i(alu_operand_a_i),
+		.operand_b_i(alu_operand_b_i),
+		.multdiv_operand_a_i(multdiv_alu_operand_a),
+		.multdiv_operand_b_i(multdiv_alu_operand_b),
+		.multdiv_en_i(multdiv_en_sel),
+		.adder_result_o(alu_adder_result_ex_o),
+		.adder_result_ext_o(alu_adder_result_ext),
+		.result_o(alu_result),
+		.comparison_result_o(alu_cmp_result),
+		.is_equal_result_o(alu_is_equal_result)
+	);
+	flexbex_ibex_multdiv_fast multdiv_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.mult_en_i(mult_en_i),
+		.div_en_i(div_en_i),
+		.operator_i(multdiv_operator_i),
+		.signed_mode_i(multdiv_signed_mode_i),
+		.op_a_i(multdiv_operand_a_i),
+		.op_b_i(multdiv_operand_b_i),
+		.alu_operand_a_o(multdiv_alu_operand_a),
+		.alu_operand_b_o(multdiv_alu_operand_b),
+		.alu_adder_ext_i(alu_adder_result_ext),
+		.alu_adder_i(alu_adder_result_ex_o),
+		.equal_to_zero(alu_is_equal_result),
+		.ready_o(multdiv_ready),
+		.multdiv_result_o(multdiv_result)
+	);
+	wire eFPGA_ready;
+	flexbex_ibex_eFPGA eFPGA_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.en_i(eFPGA_en_i),
+		.operator_i(eFPGA_operator_i),
+		.ready_o(eFPGA_ready),
+		.endresult_o(eFPGA_result),
+		.result_a_i(eFPGA_result_a_i),
+		.result_b_i(eFPGA_result_b_i),
+		.result_c_i(eFPGA_result_c_i),
+		.delay_i(eFPGA_delay_i),
+		.write_strobe(eFPGA_write_strobe_o),
+		.efpga_done_i(eFPGA_fpga_done_i)
+	);
+	always @(*)
+		case (1'b1)
+			multdiv_en: ex_ready_o = multdiv_ready;
+			lsu_en_i: ex_ready_o = lsu_ready_ex_i;
+			eFPGA_en_i: ex_ready_o = eFPGA_ready;
+			default: ex_ready_o = 1'b1;
+		endcase
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_fetch_fifo.v b/verilog/rtl/ibex_core/flexbex_ibex_fetch_fifo.v
new file mode 100644
index 0000000..9117da7
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_fetch_fifo.v
@@ -0,0 +1,134 @@
+module flexbex_ibex_fetch_fifo (
+	clk,
+	rst_n,
+	clear_i,
+	in_addr_i,
+	in_rdata_i,
+	in_valid_i,
+	in_ready_o,
+	out_valid_o,
+	out_ready_i,
+	out_rdata_o,
+	out_addr_o,
+	out_valid_stored_o
+);
+	input wire clk;
+	input wire rst_n;
+	input wire clear_i;
+	input wire [31:0] in_addr_i;
+	input wire [31:0] in_rdata_i;
+	input wire in_valid_i;
+	output wire in_ready_o;
+	output reg out_valid_o;
+	input wire out_ready_i;
+	output reg [31:0] out_rdata_o;
+	output wire [31:0] out_addr_o;
+	output reg out_valid_stored_o;
+	localparam DEPTH = 3;
+	reg [95:0] addr_n;
+	reg [95:0] addr_int;
+	reg [95:0] addr_Q;
+	reg [95:0] rdata_n;
+	reg [95:0] rdata_int;
+	reg [95:0] rdata_Q;
+	reg [2:0] valid_n;
+	reg [2:0] valid_int;
+	reg [2:0] valid_Q;
+	wire [31:2] addr_next;
+	wire [31:0] rdata;
+	wire [31:0] rdata_unaligned;
+	wire valid;
+	wire valid_unaligned;
+	wire aligned_is_compressed;
+	wire unaligned_is_compressed;
+	wire unaligned_is_compressed_st;
+	assign rdata = (valid_Q[0] ? rdata_Q[0+:32] : in_rdata_i);
+	assign valid = valid_Q[0] | in_valid_i;
+	assign rdata_unaligned = (valid_Q[1] ? {rdata_Q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]});
+	assign valid_unaligned = valid_Q[1] | (valid_Q[0] & in_valid_i);
+	assign unaligned_is_compressed = rdata[17:16] != 2'b11;
+	assign aligned_is_compressed = rdata[1:0] != 2'b11;
+	assign unaligned_is_compressed_st = rdata_Q[17-:2] != 2'b11;
+	always @(*)
+		if (out_addr_o[1]) begin
+			out_rdata_o = rdata_unaligned;
+			if (unaligned_is_compressed)
+				out_valid_o = valid;
+			else
+				out_valid_o = valid_unaligned;
+		end
+		else begin
+			out_rdata_o = rdata;
+			out_valid_o = valid;
+		end
+	assign out_addr_o = (valid_Q[0] ? addr_Q[0+:32] : in_addr_i);
+	always @(*) begin
+		out_valid_stored_o = 1'b1;
+		if (out_addr_o[1]) begin
+			if (unaligned_is_compressed_st)
+				out_valid_stored_o = 1'b1;
+			else
+				out_valid_stored_o = valid_Q[1];
+		end
+		else
+			out_valid_stored_o = valid_Q[0];
+	end
+	assign in_ready_o = ~valid_Q[1];
+	always @(*) begin : sv2v_autoblock_1
+		reg [0:1] _sv2v_jump;
+		_sv2v_jump = 2'b00;
+		addr_int = addr_Q;
+		rdata_int = rdata_Q;
+		valid_int = valid_Q;
+		if (in_valid_i) begin : sv2v_autoblock_2
+			reg signed [31:0] j;
+			for (j = 0; j < DEPTH; j = j + 1)
+				if (_sv2v_jump < 2'b10) begin
+					_sv2v_jump = 2'b00;
+					if (!valid_Q[j]) begin
+						addr_int[j * 32+:32] = in_addr_i;
+						rdata_int[j * 32+:32] = in_rdata_i;
+						valid_int[j] = 1'b1;
+						_sv2v_jump = 2'b10;
+					end
+				end
+			if (_sv2v_jump != 2'b11)
+				_sv2v_jump = 2'b00;
+		end
+	end
+	assign addr_next[31:2] = addr_int[31-:30] + 30'h00000001;
+	always @(*) begin
+		addr_n = addr_int;
+		rdata_n = rdata_int;
+		valid_n = valid_int;
+		if (out_ready_i && out_valid_o)
+			if (addr_int[1]) begin
+				if (unaligned_is_compressed)
+					addr_n[0+:32] = {addr_next[31:2], 2'b00};
+				else
+					addr_n[0+:32] = {addr_next[31:2], 2'b10};
+				rdata_n = {32'b00000000000000000000000000000000, rdata_int[32+:64]};
+				valid_n = {1'b0, valid_int[2:1]};
+			end
+			else if (aligned_is_compressed)
+				addr_n[0+:32] = {addr_int[31-:30], 2'b10};
+			else begin
+				addr_n[0+:32] = {addr_next[31:2], 2'b00};
+				rdata_n = {32'b00000000000000000000000000000000, rdata_int[32+:64]};
+				valid_n = {1'b0, valid_int[2:1]};
+			end
+	end
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			addr_Q <= {DEPTH {32'b00000000000000000000000000000000}};
+			rdata_Q <= {DEPTH {32'b00000000000000000000000000000000}};
+			valid_Q <= 1'sb0;
+		end
+		else if (clear_i)
+			valid_Q <= 1'sb0;
+		else begin
+			addr_Q <= addr_n;
+			rdata_Q <= rdata_n;
+			valid_Q <= valid_n;
+		end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_id_stage.v b/verilog/rtl/ibex_core/flexbex_ibex_id_stage.v
new file mode 100644
index 0000000..dfc16cb
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_id_stage.v
@@ -0,0 +1,492 @@
+module flexbex_ibex_id_stage (
+	clk,
+	rst_n,
+	test_en_i,
+	fetch_enable_i,
+	ctrl_busy_o,
+	core_ctrl_firstfetch_o,
+	is_decoding_o,
+	instr_valid_i,
+	instr_rdata_i,
+	instr_req_o,
+	branch_decision_i,
+	clear_instr_valid_o,
+	pc_set_o,
+	pc_mux_o,
+	exc_pc_mux_o,
+	illegal_c_insn_i,
+	is_compressed_i,
+	pc_id_i,
+	halt_if_o,
+	id_ready_o,
+	ex_ready_i,
+	id_valid_o,
+	alu_operator_ex_o,
+	alu_operand_a_ex_o,
+	alu_operand_b_ex_o,
+	mult_en_ex_o,
+	div_en_ex_o,
+	multdiv_operator_ex_o,
+	multdiv_signed_mode_ex_o,
+	multdiv_operand_a_ex_o,
+	multdiv_operand_b_ex_o,
+	eFPGA_en_o,
+	eFPGA_operator_o,
+	eFPGA_operand_a_o,
+	eFPGA_operand_b_o,
+	eFPGA_delay_o,
+	csr_access_ex_o,
+	csr_op_ex_o,
+	csr_cause_o,
+	csr_save_if_o,
+	csr_save_id_o,
+	csr_restore_mret_id_o,
+	csr_restore_dret_id_o,
+	csr_save_cause_o,
+	data_req_ex_o,
+	data_we_ex_o,
+	data_type_ex_o,
+	data_sign_ext_ex_o,
+	data_reg_offset_ex_o,
+	data_wdata_ex_o,
+	data_misaligned_i,
+	misaligned_addr_i,
+	irq_i,
+	irq_id_i,
+	m_irq_enable_i,
+	irq_ack_o,
+	irq_id_o,
+	exc_cause_o,
+	lsu_load_err_i,
+	lsu_store_err_i,
+	debug_cause_o,
+	debug_csr_save_o,
+	debug_req_i,
+	debug_single_step_i,
+	debug_ebreakm_i,
+	regfile_wdata_lsu_i,
+	regfile_wdata_ex_i,
+	csr_rdata_i,
+	perf_jump_o,
+	perf_branch_o,
+	perf_tbranch_o
+);
+	parameter [0:0] RV32M = 1;
+	parameter [0:0] RV32E = 0;
+	input wire clk;
+	input wire rst_n;
+	input wire test_en_i;
+	input wire fetch_enable_i;
+	output wire ctrl_busy_o;
+	output wire core_ctrl_firstfetch_o;
+	output wire is_decoding_o;
+	input wire instr_valid_i;
+	input wire [31:0] instr_rdata_i;
+	output wire instr_req_o;
+	input wire branch_decision_i;
+	output wire clear_instr_valid_o;
+	output wire pc_set_o;
+	output wire [2:0] pc_mux_o;
+	output wire [2:0] exc_pc_mux_o;
+	input wire illegal_c_insn_i;
+	input wire is_compressed_i;
+	input wire [31:0] pc_id_i;
+	output wire halt_if_o;
+	output wire id_ready_o;
+	input wire ex_ready_i;
+	output wire id_valid_o;
+	output wire [4:0] alu_operator_ex_o;
+	output wire [31:0] alu_operand_a_ex_o;
+	output wire [31:0] alu_operand_b_ex_o;
+	output wire mult_en_ex_o;
+	output wire div_en_ex_o;
+	output wire [1:0] multdiv_operator_ex_o;
+	output wire [1:0] multdiv_signed_mode_ex_o;
+	output wire [31:0] multdiv_operand_a_ex_o;
+	output wire [31:0] multdiv_operand_b_ex_o;
+	output wire eFPGA_en_o;
+	output wire [1:0] eFPGA_operator_o;
+	output wire [31:0] eFPGA_operand_a_o;
+	output wire [31:0] eFPGA_operand_b_o;
+	output wire [3:0] eFPGA_delay_o;
+	output wire csr_access_ex_o;
+	output wire [1:0] csr_op_ex_o;
+	output wire [5:0] csr_cause_o;
+	output wire csr_save_if_o;
+	output wire csr_save_id_o;
+	output wire csr_restore_mret_id_o;
+	output wire csr_restore_dret_id_o;
+	output wire csr_save_cause_o;
+	output wire data_req_ex_o;
+	output wire data_we_ex_o;
+	output wire [1:0] data_type_ex_o;
+	output wire data_sign_ext_ex_o;
+	output wire [1:0] data_reg_offset_ex_o;
+	output wire [31:0] data_wdata_ex_o;
+	input wire data_misaligned_i;
+	input wire [31:0] misaligned_addr_i;
+	input wire irq_i;
+	input wire [4:0] irq_id_i;
+	input wire m_irq_enable_i;
+	output wire irq_ack_o;
+	output wire [4:0] irq_id_o;
+	output wire [5:0] exc_cause_o;
+	input wire lsu_load_err_i;
+	input wire lsu_store_err_i;
+	output wire [2:0] debug_cause_o;
+	output wire debug_csr_save_o;
+	input wire debug_req_i;
+	input wire debug_single_step_i;
+	input wire debug_ebreakm_i;
+	input wire [31:0] regfile_wdata_lsu_i;
+	input wire [31:0] regfile_wdata_ex_i;
+	input wire [31:0] csr_rdata_i;
+	output wire perf_jump_o;
+	output reg perf_branch_o;
+	output wire perf_tbranch_o;
+	wire [31:0] instr;
+	wire deassert_we;
+	wire illegal_insn_dec;
+	wire illegal_reg_rv32e;
+	wire ebrk_insn;
+	wire mret_insn_dec;
+	wire dret_insn_dec;
+	wire ecall_insn_dec;
+	wire pipe_flush_dec;
+	wire branch_in_id;
+	reg branch_set_n;
+	reg branch_set_q;
+	reg branch_mux_dec;
+	reg jump_set;
+	reg jump_mux_dec;
+	wire jump_in_id;
+	reg instr_multicyle;
+	reg load_stall;
+	reg multdiv_stall;
+	reg branch_stall;
+	reg jump_stall;
+	reg eFPGA_stall;
+	wire halt_id;
+	reg regfile_we;
+	reg select_data_rf;
+	wire [31:0] imm_i_type;
+	wire [31:0] imm_s_type;
+	wire [31:0] imm_b_type;
+	wire [31:0] imm_u_type;
+	wire [31:0] imm_j_type;
+	wire [31:0] zimm_rs1_type;
+	wire [31:0] imm_a;
+	reg [31:0] imm_b;
+	wire irq_req_ctrl;
+	wire [4:0] irq_id_ctrl;
+	wire exc_ack;
+	wire exc_kill;
+	wire [4:0] regfile_addr_ra_id;
+	wire [4:0] regfile_addr_rb_id;
+	wire [4:0] regfile_alu_waddr_id;
+	wire regfile_we_id;
+	wire [31:0] regfile_data_ra_id;
+	wire [31:0] regfile_data_rb_id;
+	wire [4:0] alu_operator;
+	wire [1:0] alu_op_a_mux_sel;
+	wire alu_op_b_mux_sel;
+	wire imm_a_mux_sel;
+	wire [2:0] imm_b_mux_sel;
+	wire mult_int_en;
+	wire div_int_en;
+	wire multdiv_int_en;
+	wire [1:0] multdiv_operator;
+	wire [1:0] multdiv_signed_mode;
+	wire eFPGA_en;
+	wire eFPGA_int_en;
+	wire [1:0] eFPGA_operator;
+	wire [3:0] eFPGA_delay;
+	assign eFPGA_en_o = eFPGA_int_en;
+	wire data_we_id;
+	wire [1:0] data_type_id;
+	wire data_sign_ext_id;
+	wire [1:0] data_reg_offset_id;
+	wire data_req_id;
+	wire csr_access;
+	wire [1:0] csr_op;
+	wire csr_status;
+	wire operand_a_fw_mux_sel;
+	wire [31:0] operand_a_fw_id;
+	reg [31:0] alu_operand_a;
+	wire [31:0] alu_operand_b;
+	assign instr = instr_rdata_i;
+	assign imm_i_type = {{20 {instr[31]}}, instr[31:20]};
+	assign imm_s_type = {{20 {instr[31]}}, instr[31:25], instr[11:7]};
+	assign imm_b_type = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+	assign imm_u_type = {instr[31:12], 12'b000000000000};
+	assign imm_j_type = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+	assign zimm_rs1_type = {27'b000000000000000000000000000, instr[19:15]};
+	assign regfile_addr_ra_id = instr[19:15];
+	assign regfile_addr_rb_id = instr[24:20];
+	assign regfile_alu_waddr_id = instr[11:7];
+	assign illegal_reg_rv32e = 1'b0;
+	assign clear_instr_valid_o = id_ready_o | halt_id;
+	always @(*) begin : alu_operand_a_mux
+		case (alu_op_a_mux_sel)
+			2'd0: alu_operand_a = operand_a_fw_id;
+			2'd1: alu_operand_a = pc_id_i;
+			2'd2: alu_operand_a = imm_a;
+			default: alu_operand_a = operand_a_fw_id;
+		endcase
+	end
+	assign imm_a = (imm_a_mux_sel == 1'd0 ? zimm_rs1_type : {32 {1'sb0}});
+	assign operand_a_fw_id = (operand_a_fw_mux_sel == 1'd1 ? misaligned_addr_i : regfile_data_ra_id);
+	always @(*) begin : immediate_b_mux
+		case (imm_b_mux_sel)
+			3'd0: imm_b = imm_i_type;
+			3'd1: imm_b = imm_s_type;
+			3'd2: imm_b = imm_b_type;
+			3'd3: imm_b = imm_u_type;
+			3'd4: imm_b = imm_j_type;
+			3'd5: imm_b = (is_compressed_i && !data_misaligned_i ? 32'h00000002 : 32'h00000004);
+			default: imm_b = imm_i_type;
+		endcase
+	end
+	assign alu_operand_b = (alu_op_b_mux_sel == 1'd1 ? imm_b : regfile_data_rb_id);
+	reg [31:0] regfile_wdata_mux;
+	reg regfile_we_mux;
+	reg [4:0] regfile_waddr_mux;
+	always @(*) begin
+		regfile_we_mux = regfile_we;
+		regfile_waddr_mux = regfile_alu_waddr_id;
+		if (select_data_rf == 1'd0)
+			regfile_wdata_mux = regfile_wdata_lsu_i;
+		else if (csr_access)
+			regfile_wdata_mux = csr_rdata_i;
+		else
+			regfile_wdata_mux = regfile_wdata_ex_i;
+	end
+	flexbex_ibex_register_file #(.RV32E(RV32E)) registers_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.test_en_i(test_en_i),
+		.raddr_a_i(regfile_addr_ra_id),
+		.rdata_a_o(regfile_data_ra_id),
+		.raddr_b_i(regfile_addr_rb_id),
+		.rdata_b_o(regfile_data_rb_id),
+		.waddr_a_i(regfile_waddr_mux),
+		.wdata_a_i(regfile_wdata_mux),
+		.we_a_i(regfile_we_mux)
+	);
+	assign multdiv_int_en = mult_int_en | div_int_en;
+	flexbex_ibex_decoder #(.RV32M(RV32M)) decoder_i(
+		.deassert_we_i(deassert_we),
+		.data_misaligned_i(data_misaligned_i),
+		.branch_mux_i(branch_mux_dec),
+		.jump_mux_i(jump_mux_dec),
+		.illegal_insn_o(illegal_insn_dec),
+		.ebrk_insn_o(ebrk_insn),
+		.mret_insn_o(mret_insn_dec),
+		.dret_insn_o(dret_insn_dec),
+		.ecall_insn_o(ecall_insn_dec),
+		.pipe_flush_o(pipe_flush_dec),
+		.instr_rdata_i(instr),
+		.illegal_c_insn_i(illegal_c_insn_i),
+		.alu_operator_o(alu_operator),
+		.alu_op_a_mux_sel_o(alu_op_a_mux_sel),
+		.alu_op_b_mux_sel_o(alu_op_b_mux_sel),
+		.imm_a_mux_sel_o(imm_a_mux_sel),
+		.imm_b_mux_sel_o(imm_b_mux_sel),
+		.mult_int_en_o(mult_int_en),
+		.div_int_en_o(div_int_en),
+		.multdiv_operator_o(multdiv_operator),
+		.multdiv_signed_mode_o(multdiv_signed_mode),
+		.regfile_we_o(regfile_we_id),
+		.csr_access_o(csr_access),
+		.csr_op_o(csr_op),
+		.csr_status_o(csr_status),
+		.data_req_o(data_req_id),
+		.data_we_o(data_we_id),
+		.data_type_o(data_type_id),
+		.data_sign_extension_o(data_sign_ext_id),
+		.data_reg_offset_o(data_reg_offset_id),
+		.jump_in_id_o(jump_in_id),
+		.branch_in_id_o(branch_in_id),
+		.eFPGA_operator_o(eFPGA_operator),
+		.eFPGA_int_en_o(eFPGA_int_en),
+		.eFPGA_delay_o(eFPGA_delay)
+	);
+	assign eFPGA_operator_o = eFPGA_operator;
+	assign eFPGA_delay_o = eFPGA_delay;
+	flexbex_ibex_controller controller_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.fetch_enable_i(fetch_enable_i),
+		.ctrl_busy_o(ctrl_busy_o),
+		.first_fetch_o(core_ctrl_firstfetch_o),
+		.is_decoding_o(is_decoding_o),
+		.deassert_we_o(deassert_we),
+		.illegal_insn_i(illegal_insn_dec | illegal_reg_rv32e),
+		.ecall_insn_i(ecall_insn_dec),
+		.mret_insn_i(mret_insn_dec),
+		.dret_insn_i(dret_insn_dec),
+		.pipe_flush_i(pipe_flush_dec),
+		.ebrk_insn_i(ebrk_insn),
+		.csr_status_i(csr_status),
+		.instr_valid_i(instr_valid_i),
+		.instr_req_o(instr_req_o),
+		.pc_set_o(pc_set_o),
+		.pc_mux_o(pc_mux_o),
+		.exc_pc_mux_o(exc_pc_mux_o),
+		.exc_cause_o(exc_cause_o),
+		.data_misaligned_i(data_misaligned_i),
+		.branch_in_id_i(branch_in_id),
+		.branch_set_i(branch_set_q),
+		.jump_set_i(jump_set),
+		.instr_multicyle_i(instr_multicyle),
+		.irq_i(irq_i),
+		.irq_req_ctrl_i(irq_req_ctrl),
+		.irq_id_ctrl_i(irq_id_ctrl),
+		.m_IE_i(m_irq_enable_i),
+		.irq_ack_o(irq_ack_o),
+		.irq_id_o(irq_id_o),
+		.exc_ack_o(exc_ack),
+		.exc_kill_o(exc_kill),
+		.csr_save_cause_o(csr_save_cause_o),
+		.csr_cause_o(csr_cause_o),
+		.csr_save_if_o(csr_save_if_o),
+		.csr_save_id_o(csr_save_id_o),
+		.csr_restore_mret_id_o(csr_restore_mret_id_o),
+		.csr_restore_dret_id_o(csr_restore_dret_id_o),
+		.debug_cause_o(debug_cause_o),
+		.debug_csr_save_o(debug_csr_save_o),
+		.debug_req_i(debug_req_i),
+		.debug_single_step_i(debug_single_step_i),
+		.debug_ebreakm_i(debug_ebreakm_i),
+		.operand_a_fw_mux_sel_o(operand_a_fw_mux_sel),
+		.halt_if_o(halt_if_o),
+		.halt_id_o(halt_id),
+		.id_ready_i(id_ready_o),
+		.perf_jump_o(perf_jump_o),
+		.perf_tbranch_o(perf_tbranch_o)
+	);
+	flexbex_ibex_int_controller int_controller_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.irq_req_ctrl_o(irq_req_ctrl),
+		.irq_id_ctrl_o(irq_id_ctrl),
+		.ctrl_ack_i(exc_ack),
+		.ctrl_kill_i(exc_kill),
+		.irq_i(irq_i),
+		.irq_id_i(irq_id_i),
+		.m_IE_i(m_irq_enable_i)
+	);
+	assign data_we_ex_o = data_we_id;
+	assign data_type_ex_o = data_type_id;
+	assign data_sign_ext_ex_o = data_sign_ext_id;
+	assign data_wdata_ex_o = regfile_data_rb_id;
+	assign data_req_ex_o = data_req_id;
+	assign data_reg_offset_ex_o = data_reg_offset_id;
+	assign alu_operator_ex_o = alu_operator;
+	assign alu_operand_a_ex_o = alu_operand_a;
+	assign alu_operand_b_ex_o = alu_operand_b;
+	assign csr_access_ex_o = csr_access;
+	assign csr_op_ex_o = csr_op;
+	assign mult_en_ex_o = mult_int_en;
+	assign div_en_ex_o = div_int_en;
+	assign multdiv_operator_ex_o = multdiv_operator;
+	assign multdiv_signed_mode_ex_o = multdiv_signed_mode;
+	assign multdiv_operand_a_ex_o = regfile_data_ra_id;
+	assign multdiv_operand_b_ex_o = regfile_data_rb_id;
+	assign eFPGA_operand_a_o = regfile_data_ra_id;
+	assign eFPGA_operand_b_o = regfile_data_rb_id;
+	reg id_wb_fsm_cs;
+	reg id_wb_fsm_ns;
+	always @(posedge clk or negedge rst_n) begin : EX_WB_Pipeline_Register
+		if (!rst_n) begin
+			id_wb_fsm_cs <= 1'd0;
+			branch_set_q <= 1'b0;
+		end
+		else begin
+			id_wb_fsm_cs <= id_wb_fsm_ns;
+			branch_set_q <= branch_set_n;
+		end
+	end
+	always @(*) begin
+		id_wb_fsm_ns = id_wb_fsm_cs;
+		regfile_we = regfile_we_id;
+		load_stall = 1'b0;
+		multdiv_stall = 1'b0;
+		eFPGA_stall = 1'b0;
+		jump_stall = 1'b0;
+		branch_stall = 1'b0;
+		select_data_rf = 1'd1;
+		instr_multicyle = 1'b0;
+		branch_set_n = 1'b0;
+		branch_mux_dec = 1'b0;
+		jump_set = 1'b0;
+		jump_mux_dec = 1'b0;
+		perf_branch_o = 1'b0;
+		case (id_wb_fsm_cs)
+			1'd0: begin
+				jump_mux_dec = 1'b1;
+				branch_mux_dec = 1'b1;
+				case (1'b1)
+					data_req_id: begin
+						regfile_we = 1'b0;
+						id_wb_fsm_ns = 1'd1;
+						load_stall = 1'b1;
+						instr_multicyle = 1'b1;
+					end
+					branch_in_id: begin
+						id_wb_fsm_ns = (branch_decision_i ? 1'd1 : 1'd0);
+						branch_stall = branch_decision_i;
+						instr_multicyle = branch_decision_i;
+						branch_set_n = branch_decision_i;
+						perf_branch_o = 1'b1;
+					end
+					multdiv_int_en: begin
+						regfile_we = 1'b0;
+						id_wb_fsm_ns = 1'd1;
+						multdiv_stall = 1'b1;
+						instr_multicyle = 1'b1;
+					end
+					eFPGA_int_en: begin
+						regfile_we = 1'b0;
+						id_wb_fsm_ns = 1'd1;
+						eFPGA_stall = 1'b1;
+						instr_multicyle = 1'b1;
+					end
+					jump_in_id: begin
+						regfile_we = 1'b0;
+						id_wb_fsm_ns = 1'd1;
+						jump_stall = 1'b1;
+						instr_multicyle = 1'b1;
+						jump_set = 1'b1;
+					end
+					default:
+						;
+				endcase
+			end
+			1'd1:
+				if (ex_ready_i) begin
+					regfile_we = regfile_we_id;
+					id_wb_fsm_ns = 1'd0;
+					load_stall = 1'b0;
+					multdiv_stall = 1'b0;
+					eFPGA_stall = 1'b0;
+					select_data_rf = (data_req_id ? 1'd0 : 1'd1);
+				end
+				else begin
+					regfile_we = 1'b0;
+					instr_multicyle = 1'b1;
+					case (1'b1)
+						data_req_id: load_stall = 1'b1;
+						multdiv_int_en: multdiv_stall = 1'b1;
+						eFPGA_int_en: eFPGA_stall = 1'b1;
+						default:
+							;
+					endcase
+				end
+			default:
+				;
+		endcase
+	end
+	assign id_ready_o = (((~load_stall & ~branch_stall) & ~jump_stall) & ~multdiv_stall) & ~eFPGA_stall;
+	assign id_valid_o = ~halt_id & id_ready_o;
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_if_stage.v b/verilog/rtl/ibex_core/flexbex_ibex_if_stage.v
new file mode 100644
index 0000000..329709c
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_if_stage.v
@@ -0,0 +1,176 @@
+module flexbex_ibex_if_stage (
+	clk,
+	rst_n,
+	boot_addr_i,
+	req_i,
+	instr_req_o,
+	instr_addr_o,
+	instr_gnt_i,
+	instr_rvalid_i,
+	instr_rdata_i,
+	instr_valid_id_o,
+	instr_rdata_id_o,
+	is_compressed_id_o,
+	illegal_c_insn_id_o,
+	pc_if_o,
+	pc_id_o,
+	clear_instr_valid_i,
+	pc_set_i,
+	exception_pc_reg_i,
+	depc_i,
+	pc_mux_i,
+	exc_pc_mux_i,
+	exc_vec_pc_mux_i,
+	jump_target_ex_i,
+	halt_if_i,
+	id_ready_i,
+	if_valid_o,
+	if_busy_o,
+	perf_imiss_o
+);
+	parameter DM_HALT_ADDRESS = 32'h1a110800;
+	parameter DM_EXCEPTION_ADDRESS = 32'h1a110808;
+	input wire clk;
+	input wire rst_n;
+	input wire [31:0] boot_addr_i;
+	input wire req_i;
+	output wire instr_req_o;
+	output wire [31:0] instr_addr_o;
+	input wire instr_gnt_i;
+	input wire instr_rvalid_i;
+	input wire [31:0] instr_rdata_i;
+	output reg instr_valid_id_o;
+	output reg [31:0] instr_rdata_id_o;
+	output reg is_compressed_id_o;
+	output reg illegal_c_insn_id_o;
+	output wire [31:0] pc_if_o;
+	output reg [31:0] pc_id_o;
+	input wire clear_instr_valid_i;
+	input wire pc_set_i;
+	input wire [31:0] exception_pc_reg_i;
+	input wire [31:0] depc_i;
+	input wire [2:0] pc_mux_i;
+	input wire [2:0] exc_pc_mux_i;
+	input wire [5:0] exc_vec_pc_mux_i;
+	input wire [31:0] jump_target_ex_i;
+	input wire halt_if_i;
+	input wire id_ready_i;
+	output wire if_valid_o;
+	output wire if_busy_o;
+	output wire perf_imiss_o;
+	reg offset_in_init_d;
+	reg offset_in_init_q;
+	reg valid;
+	wire if_ready;
+	wire prefetch_busy;
+	reg branch_req;
+	reg [31:0] fetch_addr_n;
+	wire fetch_valid;
+	reg fetch_ready;
+	wire [31:0] fetch_rdata;
+	wire [31:0] fetch_addr;
+	reg [31:0] exc_pc;
+	always @(*) begin : EXC_PC_MUX
+		exc_pc = 1'sb0;
+		case (exc_pc_mux_i)
+			3'd0: exc_pc = {boot_addr_i[31:8], 8'h84};
+			3'd1: exc_pc = {boot_addr_i[31:8], 8'h88};
+			3'd7: exc_pc = {boot_addr_i[31:8], 8'h90};
+			3'd4: exc_pc = {boot_addr_i[31:8], {exc_vec_pc_mux_i}, 2'b00};
+			3'd5: exc_pc = {DM_HALT_ADDRESS};
+			3'd6: exc_pc = {DM_EXCEPTION_ADDRESS};
+			default:
+				;
+		endcase
+	end
+	always @(*) begin
+		fetch_addr_n = 1'sb0;
+		case (pc_mux_i)
+			3'd0: fetch_addr_n = {boot_addr_i[31:8], 8'h80};
+			3'd1: fetch_addr_n = jump_target_ex_i;
+			3'd2: fetch_addr_n = exc_pc;
+			3'd3: fetch_addr_n = exception_pc_reg_i;
+			3'd4: fetch_addr_n = depc_i;
+			default:
+				;
+		endcase
+	end
+	flexbex_ibex_prefetch_buffer prefetch_buffer_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.req_i(req_i),
+		.branch_i(branch_req),
+		.addr_i({fetch_addr_n[31:1], 1'b0}),
+		.ready_i(fetch_ready),
+		.valid_o(fetch_valid),
+		.rdata_o(fetch_rdata),
+		.addr_o(fetch_addr),
+		.instr_req_o(instr_req_o),
+		.instr_addr_o(instr_addr_o),
+		.instr_gnt_i(instr_gnt_i),
+		.instr_rvalid_i(instr_rvalid_i),
+		.instr_rdata_i(instr_rdata_i),
+		.busy_o(prefetch_busy)
+	);
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n)
+			offset_in_init_q <= 1'b1;
+		else
+			offset_in_init_q <= offset_in_init_d;
+	always @(*) begin
+		offset_in_init_d = offset_in_init_q;
+		fetch_ready = 1'b0;
+		branch_req = 1'b0;
+		valid = 1'b0;
+		if (offset_in_init_q) begin
+			if (req_i) begin
+				branch_req = 1'b1;
+				offset_in_init_d = 1'b0;
+			end
+		end
+		else if (fetch_valid) begin
+			valid = 1'b1;
+			if (req_i && if_valid_o) begin
+				fetch_ready = 1'b1;
+				offset_in_init_d = 1'b0;
+			end
+		end
+		if (pc_set_i) begin
+			valid = 1'b0;
+			branch_req = 1'b1;
+			offset_in_init_d = 1'b0;
+		end
+	end
+	assign pc_if_o = fetch_addr;
+	assign if_busy_o = prefetch_busy;
+	assign perf_imiss_o = ~fetch_valid | branch_req;
+	wire [31:0] instr_decompressed;
+	wire illegal_c_insn;
+	wire instr_compressed_int;
+	flexbex_ibex_compressed_decoder compressed_decoder_i(
+		.instr_i(fetch_rdata),
+		.instr_o(instr_decompressed),
+		.is_compressed_o(instr_compressed_int),
+		.illegal_instr_o(illegal_c_insn)
+	);
+	always @(posedge clk or negedge rst_n) begin : IF_ID_PIPE_REGISTERS
+		if (!rst_n) begin
+			instr_valid_id_o <= 1'b0;
+			instr_rdata_id_o <= 1'sb0;
+			illegal_c_insn_id_o <= 1'b0;
+			is_compressed_id_o <= 1'b0;
+			pc_id_o <= 1'sb0;
+		end
+		else if (if_valid_o) begin
+			instr_valid_id_o <= 1'b1;
+			instr_rdata_id_o <= instr_decompressed;
+			illegal_c_insn_id_o <= illegal_c_insn;
+			is_compressed_id_o <= instr_compressed_int;
+			pc_id_o <= pc_if_o;
+		end
+		else if (clear_instr_valid_i)
+			instr_valid_id_o <= 1'b0;
+	end
+	assign if_ready = valid & id_ready_i;
+	assign if_valid_o = ~halt_if_i & if_ready;
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_int_controller.v b/verilog/rtl/ibex_core/flexbex_ibex_int_controller.v
new file mode 100644
index 0000000..6ed4e7f
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_int_controller.v
@@ -0,0 +1,56 @@
+module flexbex_ibex_int_controller (
+	clk,
+	rst_n,
+	irq_req_ctrl_o,
+	irq_id_ctrl_o,
+	ctrl_ack_i,
+	ctrl_kill_i,
+	irq_i,
+	irq_id_i,
+	m_IE_i
+);
+	input wire clk;
+	input wire rst_n;
+	output wire irq_req_ctrl_o;
+	output wire [4:0] irq_id_ctrl_o;
+	input wire ctrl_ack_i;
+	input wire ctrl_kill_i;
+	input wire irq_i;
+	input wire [4:0] irq_id_i;
+	input wire m_IE_i;
+	reg [1:0] exc_ctrl_ns;
+	reg [1:0] exc_ctrl_cs;
+	wire irq_enable_ext;
+	reg [4:0] irq_id_d;
+	reg [4:0] irq_id_q;
+	assign irq_enable_ext = m_IE_i;
+	assign irq_req_ctrl_o = exc_ctrl_cs == 2'd1;
+	assign irq_id_ctrl_o = irq_id_q;
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			irq_id_q <= 1'sb0;
+			exc_ctrl_cs <= 2'd0;
+		end
+		else begin
+			irq_id_q <= irq_id_d;
+			exc_ctrl_cs <= exc_ctrl_ns;
+		end
+	always @(*) begin
+		irq_id_d = irq_id_q;
+		exc_ctrl_ns = exc_ctrl_cs;
+		case (exc_ctrl_cs)
+			2'd0:
+				if (irq_enable_ext && irq_i) begin
+					exc_ctrl_ns = 2'd1;
+					irq_id_d = irq_id_i;
+				end
+			2'd1:
+				case (1'b1)
+					ctrl_ack_i: exc_ctrl_ns = 2'd2;
+					ctrl_kill_i: exc_ctrl_ns = 2'd0;
+					default: exc_ctrl_ns = 2'd1;
+				endcase
+			2'd2: exc_ctrl_ns = 2'd0;
+		endcase
+	end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_load_store_unit.v b/verilog/rtl/ibex_core/flexbex_ibex_load_store_unit.v
new file mode 100644
index 0000000..8d35751
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_load_store_unit.v
@@ -0,0 +1,295 @@
+module flexbex_ibex_load_store_unit (
+	clk,
+	rst_n,
+	data_req_o,
+	data_gnt_i,
+	data_rvalid_i,
+	data_err_i,
+	data_addr_o,
+	data_we_o,
+	data_be_o,
+	data_wdata_o,
+	data_rdata_i,
+	data_we_ex_i,
+	data_type_ex_i,
+	data_wdata_ex_i,
+	data_reg_offset_ex_i,
+	data_sign_ext_ex_i,
+	data_rdata_ex_o,
+	data_req_ex_i,
+	adder_result_ex_i,
+	data_misaligned_o,
+	misaligned_addr_o,
+	load_err_o,
+	store_err_o,
+	lsu_update_addr_o,
+	data_valid_o,
+	busy_o
+);
+	input wire clk;
+	input wire rst_n;
+	output reg data_req_o;
+	input wire data_gnt_i;
+	input wire data_rvalid_i;
+	input wire data_err_i;
+	output wire [31:0] data_addr_o;
+	output wire data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_wdata_o;
+	input wire [31:0] data_rdata_i;
+	input wire data_we_ex_i;
+	input wire [1:0] data_type_ex_i;
+	input wire [31:0] data_wdata_ex_i;
+	input wire [1:0] data_reg_offset_ex_i;
+	input wire data_sign_ext_ex_i;
+	output wire [31:0] data_rdata_ex_o;
+	input wire data_req_ex_i;
+	input wire [31:0] adder_result_ex_i;
+	output reg data_misaligned_o;
+	output reg [31:0] misaligned_addr_o;
+	output wire load_err_o;
+	output wire store_err_o;
+	output reg lsu_update_addr_o;
+	output reg data_valid_o;
+	output wire busy_o;
+	wire [31:0] data_addr_int;
+	reg [1:0] data_type_q;
+	reg [1:0] rdata_offset_q;
+	reg data_sign_ext_q;
+	reg data_we_q;
+	wire [1:0] wdata_offset;
+	reg [3:0] data_be;
+	reg [31:0] data_wdata;
+	wire misaligned_st;
+	reg data_misaligned;
+	reg data_misaligned_q;
+	reg increase_address;
+	reg [2:0] CS;
+	reg [2:0] NS;
+	reg [31:0] rdata_q;
+	always @(*)
+		case (data_type_ex_i)
+			2'b00:
+				if (!misaligned_st)
+					case (data_addr_int[1:0])
+						2'b00: data_be = 4'b1111;
+						2'b01: data_be = 4'b1110;
+						2'b10: data_be = 4'b1100;
+						2'b11: data_be = 4'b1000;
+					endcase
+				else
+					case (data_addr_int[1:0])
+						2'b00: data_be = 4'b0000;
+						2'b01: data_be = 4'b0001;
+						2'b10: data_be = 4'b0011;
+						2'b11: data_be = 4'b0111;
+					endcase
+			2'b01:
+				if (!misaligned_st)
+					case (data_addr_int[1:0])
+						2'b00: data_be = 4'b0011;
+						2'b01: data_be = 4'b0110;
+						2'b10: data_be = 4'b1100;
+						2'b11: data_be = 4'b1000;
+					endcase
+				else
+					data_be = 4'b0001;
+			2'b10, 2'b11:
+				case (data_addr_int[1:0])
+					2'b00: data_be = 4'b0001;
+					2'b01: data_be = 4'b0010;
+					2'b10: data_be = 4'b0100;
+					2'b11: data_be = 4'b1000;
+				endcase
+		endcase
+	assign wdata_offset = data_addr_int[1:0] - data_reg_offset_ex_i[1:0];
+	always @(*)
+		case (wdata_offset)
+			2'b00: data_wdata = data_wdata_ex_i[31:0];
+			2'b01: data_wdata = {data_wdata_ex_i[23:0], data_wdata_ex_i[31:24]};
+			2'b10: data_wdata = {data_wdata_ex_i[15:0], data_wdata_ex_i[31:16]};
+			2'b11: data_wdata = {data_wdata_ex_i[7:0], data_wdata_ex_i[31:8]};
+		endcase
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			data_type_q <= 2'h0;
+			rdata_offset_q <= 2'h0;
+			data_sign_ext_q <= 1'b0;
+			data_we_q <= 1'b0;
+		end
+		else if (data_gnt_i) begin
+			data_type_q <= data_type_ex_i;
+			rdata_offset_q <= data_addr_int[1:0];
+			data_sign_ext_q <= data_sign_ext_ex_i;
+			data_we_q <= data_we_ex_i;
+		end
+	reg [31:0] data_rdata_ext;
+	reg [31:0] rdata_w_ext;
+	reg [31:0] rdata_h_ext;
+	reg [31:0] rdata_b_ext;
+	always @(*)
+		case (rdata_offset_q)
+			2'b00: rdata_w_ext = data_rdata_i[31:0];
+			2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]};
+			2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
+			2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
+		endcase
+	always @(*)
+		case (rdata_offset_q)
+			2'b00:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]};
+			2'b01:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]};
+			2'b10:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]};
+			2'b11:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
+		endcase
+	always @(*)
+		case (rdata_offset_q)
+			2'b00:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[7:0]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]};
+			2'b01:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[15:8]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]};
+			2'b10:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[23:16]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]};
+			2'b11:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[31:24]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]};
+		endcase
+	always @(*)
+		case (data_type_q)
+			2'b00: data_rdata_ext = rdata_w_ext;
+			2'b01: data_rdata_ext = rdata_h_ext;
+			2'b10, 2'b11: data_rdata_ext = rdata_b_ext;
+		endcase
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			CS <= 3'd0;
+			rdata_q <= 1'sb0;
+			data_misaligned_q <= 1'sb0;
+			misaligned_addr_o <= 32'b00000000000000000000000000000000;
+		end
+		else begin
+			CS <= NS;
+			if (lsu_update_addr_o) begin
+				data_misaligned_q <= data_misaligned;
+				if (increase_address)
+					misaligned_addr_o <= data_addr_int;
+			end
+			if (data_rvalid_i && !data_we_q)
+				if (data_misaligned_q || data_misaligned)
+					rdata_q <= data_rdata_i;
+				else
+					rdata_q <= data_rdata_ext;
+		end
+	assign data_rdata_ex_o = (data_rvalid_i ? data_rdata_ext : rdata_q);
+	assign data_addr_o = data_addr_int;
+	assign data_wdata_o = data_wdata;
+	assign data_we_o = data_we_ex_i;
+	assign data_be_o = data_be;
+	assign misaligned_st = data_misaligned_q;
+	assign load_err_o = 1'b0;
+	assign store_err_o = 1'b0;
+	always @(*) begin
+		NS = CS;
+		data_req_o = 1'b0;
+		lsu_update_addr_o = 1'b0;
+		data_valid_o = 1'b0;
+		increase_address = 1'b0;
+		data_misaligned_o = 1'b0;
+		case (CS)
+			3'd0:
+				if (data_req_ex_i) begin
+					data_req_o = data_req_ex_i;
+					if (data_gnt_i) begin
+						lsu_update_addr_o = 1'b1;
+						increase_address = data_misaligned;
+						NS = (data_misaligned ? 3'd2 : 3'd4);
+					end
+					else
+						NS = (data_misaligned ? 3'd1 : 3'd3);
+				end
+			3'd1: begin
+				data_req_o = 1'b1;
+				if (data_gnt_i) begin
+					lsu_update_addr_o = 1'b1;
+					increase_address = data_misaligned;
+					NS = 3'd2;
+				end
+			end
+			3'd2: begin
+				increase_address = 1'b0;
+				data_misaligned_o = 1'b1;
+				data_req_o = 1'b0;
+				lsu_update_addr_o = data_gnt_i;
+				if (data_rvalid_i) begin
+					data_req_o = 1'b1;
+					if (data_gnt_i)
+						NS = 3'd4;
+					else
+						NS = 3'd3;
+				end
+				else
+					NS = 3'd2;
+			end
+			3'd3: begin
+				data_misaligned_o = data_misaligned_q;
+				data_req_o = 1'b1;
+				if (data_gnt_i) begin
+					lsu_update_addr_o = 1'b1;
+					NS = 3'd4;
+				end
+			end
+			3'd4: begin
+				data_req_o = 1'b0;
+				if (data_rvalid_i) begin
+					data_valid_o = 1'b1;
+					NS = 3'd0;
+				end
+				else
+					NS = 3'd4;
+			end
+			default: NS = 3'd0;
+		endcase
+	end
+	always @(*) begin
+		data_misaligned = 1'b0;
+		if (data_req_ex_i && !data_misaligned_q)
+			case (data_type_ex_i)
+				2'b00:
+					if (data_addr_int[1:0] != 2'b00)
+						data_misaligned = 1'b1;
+				2'b01:
+					if (data_addr_int[1:0] == 2'b11)
+						data_misaligned = 1'b1;
+				default:
+					;
+			endcase
+	end
+	assign data_addr_int = adder_result_ex_i;
+	assign busy_o = (CS == 3'd4) | (data_req_o == 1'b1);
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_multdiv_fast.v b/verilog/rtl/ibex_core/flexbex_ibex_multdiv_fast.v
new file mode 100644
index 0000000..0c2e0dd
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_multdiv_fast.v
@@ -0,0 +1,243 @@
+module flexbex_ibex_multdiv_fast (
+	clk,
+	rst_n,
+	mult_en_i,
+	div_en_i,
+	operator_i,
+	signed_mode_i,
+	op_a_i,
+	op_b_i,
+	alu_adder_ext_i,
+	alu_adder_i,
+	equal_to_zero,
+	alu_operand_a_o,
+	alu_operand_b_o,
+	multdiv_result_o,
+	ready_o
+);
+	input wire clk;
+	input wire rst_n;
+	input wire mult_en_i;
+	input wire div_en_i;
+	input wire [1:0] operator_i;
+	input wire [1:0] signed_mode_i;
+	input wire [31:0] op_a_i;
+	input wire [31:0] op_b_i;
+	input wire [33:0] alu_adder_ext_i;
+	input wire [31:0] alu_adder_i;
+	input wire equal_to_zero;
+	output reg [32:0] alu_operand_a_o;
+	output reg [32:0] alu_operand_b_o;
+	output wire [31:0] multdiv_result_o;
+	output wire ready_o;
+	reg [4:0] div_counter_q;
+	reg [4:0] div_counter_n;
+	reg [1:0] mult_state_q;
+	reg [1:0] mult_state_n;
+	reg [2:0] divcurr_state_q;
+	reg [2:0] divcurr_state_n;
+	wire signed [34:0] mac_res_ext;
+	reg [33:0] mac_res_q;
+	reg [33:0] mac_res_n;
+	wire [33:0] mac_res;
+	reg [33:0] op_reminder_n;
+	reg [15:0] mult_op_a;
+	reg [15:0] mult_op_b;
+	reg [33:0] accum;
+	reg sign_a;
+	reg sign_b;
+	wire div_sign_a;
+	wire div_sign_b;
+	wire signed_mult;
+	reg is_greater_equal;
+	wire div_change_sign;
+	wire rem_change_sign;
+	wire [31:0] one_shift;
+	reg [31:0] op_denominator_q;
+	reg [31:0] op_numerator_q;
+	reg [31:0] op_quotient_q;
+	reg [31:0] op_denominator_n;
+	reg [31:0] op_numerator_n;
+	reg [31:0] op_quotient_n;
+	wire [31:0] next_reminder;
+	wire [32:0] next_quotient;
+	wire [32:0] res_adder_h;
+	reg mult_is_ready;
+	always @(posedge clk or negedge rst_n) begin : proc_mult_state_q
+		if (!rst_n) begin
+			mult_state_q <= 2'd0;
+			mac_res_q <= 1'sb0;
+			div_counter_q <= 1'sb0;
+			divcurr_state_q <= 3'd0;
+			op_denominator_q <= 1'sb0;
+			op_numerator_q <= 1'sb0;
+			op_quotient_q <= 1'sb0;
+		end
+		else begin
+			if (mult_en_i)
+				mult_state_q <= mult_state_n;
+			if (div_en_i) begin
+				div_counter_q <= div_counter_n;
+				op_denominator_q <= op_denominator_n;
+				op_numerator_q <= op_numerator_n;
+				op_quotient_q <= op_quotient_n;
+				divcurr_state_q <= divcurr_state_n;
+			end
+			case (1'b1)
+				mult_en_i: mac_res_q <= mac_res_n;
+				div_en_i: mac_res_q <= op_reminder_n;
+				default: mac_res_q <= mac_res_q;
+			endcase
+		end
+	end
+	assign signed_mult = signed_mode_i != 2'b00;
+	assign multdiv_result_o = (div_en_i ? mac_res_q[31:0] : mac_res_n[31:0]);
+	assign mac_res_ext = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum);
+	assign mac_res = mac_res_ext[33:0];
+	assign res_adder_h = alu_adder_ext_i[33:1];
+	assign next_reminder = (is_greater_equal ? res_adder_h[31:0] : mac_res_q[31:0]);
+	assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q});
+	assign one_shift = 32'b00000000000000000000000000000001 << div_counter_q;
+	always @(*)
+		if ((mac_res_q[31] ^ op_denominator_q[31]) == 1'b0)
+			is_greater_equal = res_adder_h[31] == 1'b0;
+		else
+			is_greater_equal = mac_res_q[31];
+	assign div_sign_a = op_a_i[31] & signed_mode_i[0];
+	assign div_sign_b = op_b_i[31] & signed_mode_i[1];
+	assign div_change_sign = div_sign_a ^ div_sign_b;
+	assign rem_change_sign = div_sign_a;
+	always @(*) begin : div_fsm
+		div_counter_n = div_counter_q - 5'h01;
+		op_reminder_n = mac_res_q;
+		op_quotient_n = op_quotient_q;
+		divcurr_state_n = divcurr_state_q;
+		op_numerator_n = op_numerator_q;
+		op_denominator_n = op_denominator_q;
+		alu_operand_a_o = 33'b000000000000000000000000000000001;
+		alu_operand_b_o = {~op_b_i, 1'b1};
+		case (divcurr_state_q)
+			3'd0: begin
+				if (operator_i == 2'd2) begin
+					op_reminder_n = 1'sb1;
+					divcurr_state_n = (equal_to_zero ? 3'd6 : 3'd1);
+				end
+				else begin
+					op_reminder_n = {2'b00, op_a_i};
+					divcurr_state_n = (equal_to_zero ? 3'd6 : 3'd1);
+				end
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_b_i, 1'b1};
+				div_counter_n = 5'd31;
+			end
+			3'd1: begin
+				op_quotient_n = 1'sb0;
+				op_numerator_n = (div_sign_a ? alu_adder_i : op_a_i);
+				divcurr_state_n = 3'd2;
+				div_counter_n = 5'd31;
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_a_i, 1'b1};
+			end
+			3'd2: begin
+				op_reminder_n = {33'h000000000, op_numerator_q[31]};
+				op_denominator_n = (div_sign_b ? alu_adder_i : op_b_i);
+				divcurr_state_n = 3'd3;
+				div_counter_n = 5'd31;
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_b_i, 1'b1};
+			end
+			3'd3: begin
+				op_reminder_n = {1'b0, next_reminder[31:0], op_numerator_q[div_counter_n]};
+				op_quotient_n = next_quotient[31:0];
+				divcurr_state_n = (div_counter_q == 5'd1 ? 3'd4 : 3'd3);
+				alu_operand_a_o = {mac_res_q[31:0], 1'b1};
+				alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
+			end
+			3'd4: begin
+				if (operator_i == 2'd2)
+					op_reminder_n = {1'b0, next_quotient};
+				else
+					op_reminder_n = {2'b00, next_reminder[31:0]};
+				alu_operand_a_o = {mac_res_q[31:0], 1'b1};
+				alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
+				divcurr_state_n = 3'd5;
+			end
+			3'd5: begin
+				divcurr_state_n = 3'd6;
+				if (operator_i == 2'd2)
+					op_reminder_n = (div_change_sign ? {2'h0, alu_adder_i} : mac_res_q);
+				else
+					op_reminder_n = (rem_change_sign ? {2'h0, alu_adder_i} : mac_res_q);
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~mac_res_q[31:0], 1'b1};
+			end
+			3'd6: divcurr_state_n = 3'd0;
+			default:
+				;
+		endcase
+	end
+	assign ready_o = mult_is_ready | (divcurr_state_q == 3'd6);
+	always @(*) begin : mult_fsm
+		mult_op_a = op_a_i[15:0];
+		mult_op_b = op_b_i[15:0];
+		sign_a = 1'b0;
+		sign_b = 1'b0;
+		accum = mac_res_q;
+		mac_res_n = mac_res;
+		mult_state_n = mult_state_q;
+		mult_is_ready = 1'b0;
+		case (mult_state_q)
+			2'd0: begin
+				mult_op_a = op_a_i[15:0];
+				mult_op_b = op_b_i[15:0];
+				sign_a = 1'b0;
+				sign_b = 1'b0;
+				accum = 1'sb0;
+				mac_res_n = mac_res;
+				mult_state_n = 2'd1;
+			end
+			2'd1: begin
+				mult_op_a = op_a_i[15:0];
+				mult_op_b = op_b_i[31:16];
+				sign_a = 1'b0;
+				sign_b = signed_mode_i[1] & op_b_i[31];
+				accum = {18'b000000000000000000, mac_res_q[31:16]};
+				if (operator_i == 2'd0)
+					mac_res_n = {2'b00, mac_res[15:0], mac_res_q[15:0]};
+				else
+					mac_res_n = mac_res;
+				mult_state_n = 2'd2;
+			end
+			2'd2: begin
+				mult_op_a = op_a_i[31:16];
+				mult_op_b = op_b_i[15:0];
+				sign_a = signed_mode_i[0] & op_a_i[31];
+				sign_b = 1'b0;
+				if (operator_i == 2'd0) begin
+					accum = {18'b000000000000000000, mac_res_q[31:16]};
+					mac_res_n = {2'b00, mac_res[15:0], mac_res_q[15:0]};
+					mult_is_ready = 1'b1;
+					mult_state_n = 2'd0;
+				end
+				else begin
+					accum = mac_res_q;
+					mac_res_n = mac_res;
+					mult_state_n = 2'd3;
+				end
+			end
+			2'd3: begin
+				mult_op_a = op_a_i[31:16];
+				mult_op_b = op_b_i[31:16];
+				sign_a = signed_mode_i[0] & op_a_i[31];
+				sign_b = signed_mode_i[1] & op_b_i[31];
+				accum[17:0] = mac_res_q[33:16];
+				accum[33:18] = {16 {signed_mult & mac_res_q[33]}};
+				mac_res_n = mac_res;
+				mult_state_n = 2'd0;
+				mult_is_ready = 1'b1;
+			end
+			default:
+				;
+		endcase
+	end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_prefetch_buffer.v b/verilog/rtl/ibex_core/flexbex_ibex_prefetch_buffer.v
new file mode 100644
index 0000000..8919dec
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_prefetch_buffer.v
@@ -0,0 +1,131 @@
+module flexbex_ibex_prefetch_buffer (
+	clk,
+	rst_n,
+	req_i,
+	branch_i,
+	addr_i,
+	ready_i,
+	valid_o,
+	rdata_o,
+	addr_o,
+	instr_req_o,
+	instr_gnt_i,
+	instr_addr_o,
+	instr_rdata_i,
+	instr_rvalid_i,
+	busy_o
+);
+	input wire clk;
+	input wire rst_n;
+	input wire req_i;
+	input wire branch_i;
+	input wire [31:0] addr_i;
+	input wire ready_i;
+	output wire valid_o;
+	output wire [31:0] rdata_o;
+	output wire [31:0] addr_o;
+	output reg instr_req_o;
+	input wire instr_gnt_i;
+	output reg [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	input wire instr_rvalid_i;
+	output wire busy_o;
+	reg [1:0] CS;
+	reg [1:0] NS;
+	reg [31:0] instr_addr_q;
+	wire [31:0] fetch_addr;
+	reg addr_valid;
+	reg fifo_valid;
+	wire fifo_ready;
+	wire fifo_clear;
+	assign busy_o = (CS != 2'd0) | instr_req_o;
+	flexbex_ibex_fetch_fifo fifo_i(
+		.clk(clk),
+		.rst_n(rst_n),
+		.clear_i(fifo_clear),
+		.in_addr_i(instr_addr_q),
+		.in_rdata_i(instr_rdata_i),
+		.in_valid_i(fifo_valid),
+		.in_ready_o(fifo_ready),
+		.out_valid_o(valid_o),
+		.out_ready_i(ready_i),
+		.out_rdata_o(rdata_o),
+		.out_addr_o(addr_o),
+		.out_valid_stored_o()
+	);
+	assign fetch_addr = {instr_addr_q[31:2], 2'b00} + 32'd4;
+	assign fifo_clear = branch_i;
+	always @(*) begin
+		instr_req_o = 1'b0;
+		instr_addr_o = fetch_addr;
+		fifo_valid = 1'b0;
+		addr_valid = 1'b0;
+		NS = CS;
+		case (CS)
+			2'd0: begin
+				instr_addr_o = fetch_addr;
+				instr_req_o = 1'b0;
+				if (branch_i)
+					instr_addr_o = addr_i;
+				if (req_i && (fifo_ready || branch_i)) begin
+					instr_req_o = 1'b1;
+					addr_valid = 1'b1;
+					NS = (instr_gnt_i ? 2'd2 : 2'd1);
+				end
+			end
+			2'd1: begin
+				instr_addr_o = instr_addr_q;
+				instr_req_o = 1'b1;
+				if (branch_i) begin
+					instr_addr_o = addr_i;
+					addr_valid = 1'b1;
+				end
+				NS = (instr_gnt_i ? 2'd2 : 2'd1);
+			end
+			2'd2: begin
+				instr_addr_o = fetch_addr;
+				if (branch_i)
+					instr_addr_o = addr_i;
+				if (req_i && (fifo_ready || branch_i)) begin
+					if (instr_rvalid_i) begin
+						instr_req_o = 1'b1;
+						fifo_valid = 1'b1;
+						addr_valid = 1'b1;
+						NS = (instr_gnt_i ? 2'd2 : 2'd1);
+					end
+					else if (branch_i) begin
+						addr_valid = 1'b1;
+						NS = 2'd3;
+					end
+				end
+				else if (instr_rvalid_i) begin
+					fifo_valid = 1'b1;
+					NS = 2'd0;
+				end
+			end
+			2'd3: begin
+				instr_addr_o = instr_addr_q;
+				if (branch_i) begin
+					instr_addr_o = addr_i;
+					addr_valid = 1'b1;
+				end
+				if (instr_rvalid_i) begin
+					instr_req_o = 1'b1;
+					NS = (instr_gnt_i ? 2'd2 : 2'd1);
+				end
+			end
+			default:
+				;
+		endcase
+	end
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			CS <= 2'd0;
+			instr_addr_q <= 1'sb0;
+		end
+		else begin
+			CS <= NS;
+			if (addr_valid)
+				instr_addr_q <= instr_addr_o;
+		end
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_ibex_register_file.v b/verilog/rtl/ibex_core/flexbex_ibex_register_file.v
new file mode 100644
index 0000000..c7ebfac
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_ibex_register_file.v
@@ -0,0 +1,54 @@
+module flexbex_ibex_register_file (
+	clk,
+	rst_n,
+	test_en_i,
+	raddr_a_i,
+	rdata_a_o,
+	raddr_b_i,
+	rdata_b_o,
+	waddr_a_i,
+	wdata_a_i,
+	we_a_i
+);
+	parameter [0:0] RV32E = 0;
+	parameter DATA_WIDTH = 32;
+	input wire clk;
+	input wire rst_n;
+	input wire test_en_i;
+	input wire [4:0] raddr_a_i;
+	output wire [DATA_WIDTH - 1:0] rdata_a_o;
+	input wire [4:0] raddr_b_i;
+	output wire [DATA_WIDTH - 1:0] rdata_b_o;
+	input wire [4:0] waddr_a_i;
+	input wire [DATA_WIDTH - 1:0] wdata_a_i;
+	input wire we_a_i;
+	localparam ADDR_WIDTH = (RV32E ? 4 : 5);
+	localparam NUM_WORDS = 2 ** ADDR_WIDTH;
+	wire [(NUM_WORDS * DATA_WIDTH) - 1:0] rf_reg;
+	reg [((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) * DATA_WIDTH) + (DATA_WIDTH - 1) : ((3 - NUM_WORDS) * DATA_WIDTH) + (((NUM_WORDS - 1) * DATA_WIDTH) - 1)):((NUM_WORDS - 1) >= 1 ? DATA_WIDTH : (NUM_WORDS - 1) * DATA_WIDTH)] rf_reg_tmp;
+	reg [NUM_WORDS - 1:1] we_a_dec;
+	always @(*) begin : we_a_decoder
+		begin : sv2v_autoblock_1
+			reg signed [31:0] i;
+			for (i = 1; i < NUM_WORDS; i = i + 1)
+				we_a_dec[i] = (waddr_a_i == i ? we_a_i : 1'b0);
+		end
+	end
+	function automatic [DATA_WIDTH - 1:0] sv2v_cast_16D66;
+		input reg [DATA_WIDTH - 1:0] inp;
+		sv2v_cast_16D66 = inp;
+	endfunction
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n)
+			rf_reg_tmp <= {((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) {sv2v_cast_16D66(1'sb0)}};
+		else begin : sv2v_autoblock_2
+			reg signed [31:0] r;
+			for (r = 1; r < NUM_WORDS; r = r + 1)
+				if (we_a_dec[r])
+					rf_reg_tmp[((NUM_WORDS - 1) >= 1 ? r : 1 - (r - (NUM_WORDS - 1))) * DATA_WIDTH+:DATA_WIDTH] <= wdata_a_i;
+		end
+	assign rf_reg[0+:DATA_WIDTH] = 1'sb0;
+	assign rf_reg[DATA_WIDTH * (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1))+:DATA_WIDTH * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)] = rf_reg_tmp[DATA_WIDTH * ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) : 1 - (((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) - (NUM_WORDS - 1)))+:DATA_WIDTH * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)];
+	assign rdata_a_o = rf_reg[raddr_a_i * DATA_WIDTH+:DATA_WIDTH];
+	assign rdata_b_o = rf_reg[raddr_b_i * DATA_WIDTH+:DATA_WIDTH];
+endmodule
diff --git a/verilog/rtl/ibex_core/flexbex_prim_clock_gating.v b/verilog/rtl/ibex_core/flexbex_prim_clock_gating.v
new file mode 100644
index 0000000..0d11945
--- /dev/null
+++ b/verilog/rtl/ibex_core/flexbex_prim_clock_gating.v
@@ -0,0 +1,16 @@
+module flexbex_prim_clock_gating (
+	clk_i,
+	en_i,
+	test_en_i,
+	clk_o
+);
+	input wire clk_i;
+	input wire en_i;
+	input wire test_en_i;
+	output wire clk_o;
+	reg clk_en;
+	always @(*)
+		if (clk_i == 1'b0)
+			clk_en <= en_i | test_en_i;
+	assign clk_o = clk_i & clk_en;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_aes_sbox.v b/verilog/rtl/ibex_core/ibex_aes_sbox.v
new file mode 100644
index 0000000..abe658d
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_aes_sbox.v
@@ -0,0 +1,405 @@
+module ibex_aes_sbox (
+	fw,
+	in,
+	fx
+);
+	input wire fw;
+	input wire [7:0] in;
+	output wire [7:0] fx;
+	function automatic [20:0] aes_sbox_top;
+		input reg [7:0] x;
+		reg y20;
+		reg y19;
+		reg y18;
+		reg y17;
+		reg y16;
+		reg y15;
+		reg y14;
+		reg y13;
+		reg y12;
+		reg y11;
+		reg y10;
+		reg y9;
+		reg y8;
+		reg y7;
+		reg y6;
+		reg y5;
+		reg y4;
+		reg y3;
+		reg y2;
+		reg y1;
+		reg y0;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			y0 = x[0];
+			y1 = x[7] ^ x[4];
+			y2 = x[7] ^ x[2];
+			y3 = x[7] ^ x[1];
+			y4 = x[4] ^ x[2];
+			t0 = x[3] ^ x[1];
+			y5 = y1 ^ t0;
+			t1 = x[6] ^ x[5];
+			y6 = x[0] ^ y5;
+			y7 = x[0] ^ t1;
+			y8 = y5 ^ t1;
+			t2 = x[6] ^ x[2];
+			t3 = x[5] ^ x[2];
+			y9 = y3 ^ y4;
+			y10 = y5 ^ t2;
+			y11 = t0 ^ t2;
+			y12 = t0 ^ t3;
+			y13 = y7 ^ y12;
+			t4 = x[4] ^ x[0];
+			y14 = t1 ^ t4;
+			y15 = y1 ^ y14;
+			t5 = x[1] ^ x[0];
+			y16 = t1 ^ t5;
+			y17 = y2 ^ y16;
+			y18 = y2 ^ y8;
+			y19 = y15 ^ y13;
+			y20 = y1 ^ t3;
+			aes_sbox_top = {y20, y19, y18, y17, y16, y15, y14, y13, y12, y11, y10, y9, y8, y7, y6, y5, y4, y3, y2, y1, y0};
+		end
+	endfunction
+	function automatic [7:0] aes_sbox_out;
+		input reg [17:0] x;
+		reg [7:0] y;
+		reg t29;
+		reg t28;
+		reg t27;
+		reg t26;
+		reg t25;
+		reg t24;
+		reg t23;
+		reg t22;
+		reg t21;
+		reg t20;
+		reg t19;
+		reg t18;
+		reg t17;
+		reg t16;
+		reg t15;
+		reg t14;
+		reg t13;
+		reg t12;
+		reg t11;
+		reg t10;
+		reg t9;
+		reg t8;
+		reg t7;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			t0 = x[11] ^ x[12];
+			t1 = x[0] ^ x[6];
+			t2 = x[14] ^ x[16];
+			t3 = x[15] ^ x[5];
+			t4 = x[4] ^ x[8];
+			t5 = x[17] ^ x[11];
+			t6 = x[12] ^ t5;
+			t7 = x[14] ^ t3;
+			t8 = x[1] ^ x[9];
+			t9 = x[2] ^ x[3];
+			t10 = x[3] ^ t4;
+			t11 = x[10] ^ t2;
+			t12 = x[16] ^ x[1];
+			t13 = x[0] ^ t0;
+			t14 = x[2] ^ x[11];
+			t15 = x[5] ^ t1;
+			t16 = x[6] ^ t0;
+			t17 = x[7] ^ t1;
+			t18 = x[8] ^ t8;
+			t19 = x[13] ^ t4;
+			t20 = t0 ^ t1;
+			t21 = t1 ^ t7;
+			t22 = t3 ^ t12;
+			t23 = t18 ^ t2;
+			t24 = t15 ^ t9;
+			t25 = t6 ^ t10;
+			t26 = t7 ^ t9;
+			t27 = t8 ^ t10;
+			t28 = t11 ^ t14;
+			t29 = t11 ^ t17;
+			y[0] = t6 ~^ t23;
+			y[1] = t13 ~^ t27;
+			y[2] = t25 ^ t29;
+			y[3] = t20 ^ t22;
+			y[4] = t6 ^ t21;
+			y[5] = t19 ~^ t28;
+			y[6] = t16 ~^ t26;
+			y[7] = t6 ^ t24;
+			aes_sbox_out = y;
+		end
+	endfunction
+	function automatic [17:0] aes_sbox_inv_mid;
+		input reg [20:0] x;
+		reg [17:0] y;
+		reg t45;
+		reg t44;
+		reg t43;
+		reg t42;
+		reg t41;
+		reg t40;
+		reg t39;
+		reg t38;
+		reg t37;
+		reg t36;
+		reg t35;
+		reg t34;
+		reg t33;
+		reg t32;
+		reg t31;
+		reg t30;
+		reg t29;
+		reg t28;
+		reg t27;
+		reg t26;
+		reg t25;
+		reg t24;
+		reg t23;
+		reg t22;
+		reg t21;
+		reg t20;
+		reg t19;
+		reg t18;
+		reg t17;
+		reg t16;
+		reg t15;
+		reg t14;
+		reg t13;
+		reg t12;
+		reg t11;
+		reg t10;
+		reg t9;
+		reg t8;
+		reg t7;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			t0 = x[3] ^ x[12];
+			t1 = x[9] & x[5];
+			t2 = x[17] & x[6];
+			t3 = x[10] ^ t1;
+			t4 = x[14] & x[0];
+			t5 = t4 ^ t1;
+			t6 = x[3] & x[12];
+			t7 = x[16] & x[7];
+			t8 = t0 ^ t6;
+			t9 = x[15] & x[13];
+			t10 = t9 ^ t6;
+			t11 = x[1] & x[11];
+			t12 = x[4] & x[20];
+			t13 = t12 ^ t11;
+			t14 = x[2] & x[8];
+			t15 = t14 ^ t11;
+			t16 = t3 ^ t2;
+			t17 = t5 ^ x[18];
+			t18 = t8 ^ t7;
+			t19 = t10 ^ t15;
+			t20 = t16 ^ t13;
+			t21 = t17 ^ t15;
+			t22 = t18 ^ t13;
+			t23 = t19 ^ x[19];
+			t24 = t22 ^ t23;
+			t25 = t22 & t20;
+			t26 = t21 ^ t25;
+			t27 = t20 ^ t21;
+			t28 = t23 ^ t25;
+			t29 = t28 & t27;
+			t30 = t26 & t24;
+			t31 = t20 & t23;
+			t32 = t27 & t31;
+			t33 = t27 ^ t25;
+			t34 = t21 & t22;
+			t35 = t24 & t34;
+			t36 = t24 ^ t25;
+			t37 = t21 ^ t29;
+			t38 = t32 ^ t33;
+			t39 = t23 ^ t30;
+			t40 = t35 ^ t36;
+			t41 = t38 ^ t40;
+			t42 = t37 ^ t39;
+			t43 = t37 ^ t38;
+			t44 = t39 ^ t40;
+			t45 = t42 ^ t41;
+			y[0] = t38 & x[7];
+			y[1] = t37 & x[13];
+			y[2] = t42 & x[11];
+			y[3] = t45 & x[20];
+			y[4] = t41 & x[8];
+			y[5] = t44 & x[9];
+			y[6] = t40 & x[17];
+			y[7] = t39 & x[14];
+			y[8] = t43 & x[3];
+			y[9] = t38 & x[16];
+			y[10] = t37 & x[15];
+			y[11] = t42 & x[1];
+			y[12] = t45 & x[4];
+			y[13] = t41 & x[2];
+			y[14] = t44 & x[5];
+			y[15] = t40 & x[6];
+			y[16] = t39 & x[0];
+			y[17] = t43 & x[12];
+			aes_sbox_inv_mid = y;
+		end
+	endfunction
+	function automatic [20:0] aes_inv_sbox_top;
+		input reg [7:0] x;
+		reg y20;
+		reg y19;
+		reg y18;
+		reg y17;
+		reg y16;
+		reg y15;
+		reg y14;
+		reg y13;
+		reg y12;
+		reg y11;
+		reg y10;
+		reg y9;
+		reg y8;
+		reg y7;
+		reg y6;
+		reg y5;
+		reg y4;
+		reg y3;
+		reg y2;
+		reg y1;
+		reg y0;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			y17 = x[7] ^ x[4];
+			y16 = x[6] ~^ x[4];
+			y2 = x[7] ~^ x[6];
+			y1 = x[4] ^ x[3];
+			y18 = x[3] ~^ x[0];
+			t0 = x[1] ^ x[0];
+			y6 = x[6] ~^ y17;
+			y14 = y16 ^ t0;
+			y7 = x[0] ~^ y1;
+			y8 = y2 ^ y18;
+			y9 = y2 ^ t0;
+			y3 = y1 ^ t0;
+			y19 = x[5] ~^ y1;
+			t1 = x[6] ^ x[1];
+			y13 = x[5] ~^ y14;
+			y15 = y18 ^ t1;
+			y4 = x[3] ^ y6;
+			t2 = x[5] ~^ x[2];
+			t3 = x[2] ~^ x[1];
+			t4 = x[5] ~^ x[3];
+			y5 = y16 ^ t2;
+			y12 = t1 ^ t4;
+			y20 = y1 ^ t3;
+			y11 = y8 ^ y20;
+			y10 = y8 ^ t3;
+			y0 = x[7] ^ t2;
+			aes_inv_sbox_top = {y20, y19, y18, y17, y16, y15, y14, y13, y12, y11, y10, y9, y8, y7, y6, y5, y4, y3, y2, y1, y0};
+		end
+	endfunction
+	function automatic [7:0] aes_inv_sbox_out;
+		input reg [17:0] x;
+		reg [7:0] y;
+		reg t29;
+		reg t28;
+		reg t27;
+		reg t26;
+		reg t25;
+		reg t24;
+		reg t23;
+		reg t22;
+		reg t20;
+		reg t19;
+		reg t18;
+		reg t17;
+		reg t16;
+		reg t15;
+		reg t14;
+		reg t13;
+		reg t12;
+		reg t11;
+		reg t10;
+		reg t9;
+		reg t8;
+		reg t7;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			t0 = x[2] ^ x[11];
+			t1 = x[8] ^ x[9];
+			t2 = x[4] ^ x[12];
+			t3 = x[15] ^ x[0];
+			t4 = x[16] ^ x[6];
+			t5 = x[14] ^ x[1];
+			t6 = x[17] ^ x[10];
+			t7 = t0 ^ t1;
+			t8 = x[0] ^ x[3];
+			t9 = x[5] ^ x[13];
+			t10 = x[7] ^ t4;
+			t11 = t0 ^ t3;
+			t12 = x[14] ^ x[16];
+			t13 = x[17] ^ x[1];
+			t14 = x[17] ^ x[12];
+			t15 = x[4] ^ x[9];
+			t16 = x[7] ^ x[11];
+			t17 = x[8] ^ t2;
+			t18 = x[13] ^ t5;
+			t19 = t2 ^ t3;
+			t20 = t4 ^ t6;
+			t22 = t2 ^ t7;
+			t23 = t7 ^ t8;
+			t24 = t5 ^ t7;
+			t25 = t6 ^ t10;
+			t26 = t9 ^ t11;
+			t27 = t10 ^ t18;
+			t28 = t11 ^ t25;
+			t29 = t15 ^ t20;
+			y[0] = t9 ^ t16;
+			y[1] = t14 ^ t23;
+			y[2] = t19 ^ t24;
+			y[3] = t23 ^ t27;
+			y[4] = t12 ^ t22;
+			y[5] = t17 ^ t28;
+			y[6] = t26 ^ t29;
+			y[7] = t13 ^ t22;
+			aes_inv_sbox_out = y;
+		end
+	endfunction
+	wire [20:0] fwd_top;
+	wire [20:0] inv_top;
+	wire [20:0] top_box;
+	assign fwd_top = aes_sbox_top(in);
+	assign inv_top = aes_inv_sbox_top(in);
+	assign top_box = (fw ? fwd_top : inv_top);
+	wire [17:0] mid;
+	assign mid = aes_sbox_inv_mid(top_box);
+	wire [7:0] fwd_out;
+	wire [7:0] inv_out;
+	assign fwd_out = aes_sbox_out(mid);
+	assign inv_out = aes_inv_sbox_out(mid);
+	assign fx = (fw ? fwd_out : inv_out);
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_alu.v b/verilog/rtl/ibex_core/ibex_alu.v
new file mode 100644
index 0000000..b5ec3ef
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_alu.v
@@ -0,0 +1,693 @@
+module ibex_alu (
+	operator_i,
+	operand_a_i,
+	operand_b_i,
+	instr_first_cycle_i,
+	multdiv_operand_a_i,
+	multdiv_operand_b_i,
+	multdiv_sel_i,
+	imd_val_q_i,
+	imd_val_d_o,
+	imd_val_we_o,
+	adder_result_o,
+	adder_result_ext_o,
+	result_o,
+	comparison_result_o,
+	is_equal_result_o
+);
+	parameter integer RV32B = 32'sd0;
+	input wire [6:0] operator_i;
+	input wire [31:0] operand_a_i;
+	input wire [31:0] operand_b_i;
+	input wire instr_first_cycle_i;
+	input wire [32:0] multdiv_operand_a_i;
+	input wire [32:0] multdiv_operand_b_i;
+	input wire multdiv_sel_i;
+	input wire [63:0] imd_val_q_i;
+	output reg [63:0] imd_val_d_o;
+	output reg [1:0] imd_val_we_o;
+	output wire [31:0] adder_result_o;
+	output wire [33:0] adder_result_ext_o;
+	output reg [31:0] result_o;
+	output wire comparison_result_o;
+	output wire is_equal_result_o;
+	wire [31:0] operand_a_rev;
+	wire [32:0] operand_b_neg;
+	genvar k;
+	generate
+		for (k = 0; k < 32; k = k + 1) begin : gen_rev_operand_a
+			assign operand_a_rev[k] = operand_a_i[31 - k];
+		end
+	endgenerate
+	reg adder_op_a_shift1;
+	reg adder_op_a_shift2;
+	reg adder_op_a_shift3;
+	reg adder_op_b_negate;
+	reg [32:0] adder_in_a;
+	reg [32:0] adder_in_b;
+	wire [31:0] adder_result;
+	always @(*) begin
+		adder_op_a_shift1 = 1'b0;
+		adder_op_a_shift2 = 1'b0;
+		adder_op_a_shift3 = 1'b0;
+		adder_op_b_negate = 1'b0;
+		case (operator_i)
+			7'd1, 7'd26, 7'd27, 7'd24, 7'd25, 7'd22, 7'd23, 7'd40, 7'd41, 7'd28, 7'd29, 7'd30, 7'd31: adder_op_b_negate = 1'b1;
+			7'd19:
+				if (RV32B != 32'sd0)
+					adder_op_a_shift1 = 1'b1;
+			7'd20:
+				if (RV32B != 32'sd0)
+					adder_op_a_shift2 = 1'b1;
+			7'd21:
+				if (RV32B != 32'sd0)
+					adder_op_a_shift3 = 1'b1;
+			default:
+				;
+		endcase
+	end
+	always @(*)
+		case (1'b1)
+			multdiv_sel_i: adder_in_a = multdiv_operand_a_i;
+			adder_op_a_shift1: adder_in_a = {operand_a_i[30:0], 2'b01};
+			adder_op_a_shift2: adder_in_a = {operand_a_i[29:0], 3'b001};
+			adder_op_a_shift3: adder_in_a = {operand_a_i[28:0], 4'b0001};
+			default: adder_in_a = {operand_a_i, 1'b1};
+		endcase
+	assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {1'b1}};
+	always @(*)
+		case (1'b1)
+			multdiv_sel_i: adder_in_b = multdiv_operand_b_i;
+			adder_op_b_negate: adder_in_b = operand_b_neg;
+			default: adder_in_b = {operand_b_i, 1'b0};
+		endcase
+	assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
+	assign adder_result = adder_result_ext_o[32:1];
+	assign adder_result_o = adder_result;
+	wire is_equal;
+	reg is_greater_equal;
+	reg cmp_signed;
+	always @(*)
+		case (operator_i)
+			7'd24, 7'd22, 7'd40, 7'd28, 7'd30: cmp_signed = 1'b1;
+			default: cmp_signed = 1'b0;
+		endcase
+	assign is_equal = adder_result == 32'b00000000000000000000000000000000;
+	assign is_equal_result_o = is_equal;
+	always @(*)
+		if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0)
+			is_greater_equal = adder_result[31] == 1'b0;
+		else
+			is_greater_equal = operand_a_i[31] ^ cmp_signed;
+	reg cmp_result;
+	always @(*)
+		case (operator_i)
+			7'd26: cmp_result = is_equal;
+			7'd27: cmp_result = ~is_equal;
+			7'd24, 7'd25, 7'd30, 7'd31: cmp_result = is_greater_equal;
+			7'd22, 7'd23, 7'd28, 7'd29, 7'd40, 7'd41: cmp_result = ~is_greater_equal;
+			default: cmp_result = is_equal;
+		endcase
+	assign comparison_result_o = cmp_result;
+	reg shift_left;
+	wire shift_ones;
+	wire shift_arith;
+	wire shift_funnel;
+	wire shift_sbmode;
+	reg [5:0] shift_amt;
+	wire [5:0] shift_amt_compl;
+	reg [31:0] shift_operand;
+	reg signed [32:0] shift_result_ext_signed;
+	reg [32:0] shift_result_ext;
+	reg unused_shift_result_ext;
+	reg [31:0] shift_result;
+	reg [31:0] shift_result_rev;
+	wire bfp_op;
+	wire [4:0] bfp_len;
+	wire [4:0] bfp_off;
+	wire [31:0] bfp_mask;
+	wire [31:0] bfp_mask_rev;
+	wire [31:0] bfp_result;
+	assign bfp_op = (RV32B != 32'sd0 ? operator_i == 7'd52 : 1'b0);
+	assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]};
+	assign bfp_off = operand_b_i[20:16];
+	assign bfp_mask = (RV32B != 32'sd0 ? ~(32'hffffffff << bfp_len) : {32 {1'sb0}});
+	genvar i;
+	generate
+		for (i = 0; i < 32; i = i + 1) begin : gen_rev_bfp_mask
+			assign bfp_mask_rev[i] = bfp_mask[31 - i];
+		end
+	endgenerate
+	assign bfp_result = (RV32B != 32'sd0 ? (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : {32 {1'sb0}});
+	wire [1:1] sv2v_tmp_3EBA5;
+	assign sv2v_tmp_3EBA5 = operand_b_i[5] & shift_funnel;
+	always @(*) shift_amt[5] = sv2v_tmp_3EBA5;
+	assign shift_amt_compl = 32 - operand_b_i[4:0];
+	always @(*)
+		if (bfp_op)
+			shift_amt[4:0] = bfp_off;
+		else
+			shift_amt[4:0] = (instr_first_cycle_i ? (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0]));
+	assign shift_sbmode = (RV32B != 32'sd0 ? ((operator_i == 7'd46) | (operator_i == 7'd47)) | (operator_i == 7'd48) : 1'b0);
+	always @(*) begin
+		case (operator_i)
+			7'd10: shift_left = 1'b1;
+			7'd12, 7'd52: shift_left = (RV32B != 32'sd0 ? 1'b1 : 1'b0);
+			7'd14: shift_left = (RV32B != 32'sd0 ? instr_first_cycle_i : 0);
+			7'd13: shift_left = (RV32B != 32'sd0 ? ~instr_first_cycle_i : 0);
+			7'd44: shift_left = (RV32B != 32'sd0 ? (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0);
+			7'd45: shift_left = (RV32B != 32'sd0 ? (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0);
+			default: shift_left = 1'b0;
+		endcase
+		if (shift_sbmode)
+			shift_left = 1'b1;
+	end
+	assign shift_arith = operator_i == 7'd8;
+	assign shift_ones = (RV32B != 32'sd0 ? (operator_i == 7'd12) | (operator_i == 7'd11) : 1'b0);
+	assign shift_funnel = (RV32B != 32'sd0 ? (operator_i == 7'd44) | (operator_i == 7'd45) : 1'b0);
+	always @(*) begin
+		if (RV32B == 32'sd0)
+			shift_operand = (shift_left ? operand_a_rev : operand_a_i);
+		else
+			case (1'b1)
+				bfp_op: shift_operand = bfp_mask_rev;
+				shift_sbmode: shift_operand = 32'h80000000;
+				default: shift_operand = (shift_left ? operand_a_rev : operand_a_i);
+			endcase
+		shift_result_ext_signed = $signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0];
+		shift_result_ext = $unsigned(shift_result_ext_signed);
+		shift_result = shift_result_ext[31:0];
+		unused_shift_result_ext = shift_result_ext[32];
+		begin : sv2v_autoblock_1
+			reg [31:0] i;
+			for (i = 0; i < 32; i = i + 1)
+				shift_result_rev[i] = shift_result[31 - i];
+		end
+		shift_result = (shift_left ? shift_result_rev : shift_result);
+	end
+	wire bwlogic_or;
+	wire bwlogic_and;
+	wire [31:0] bwlogic_operand_b;
+	wire [31:0] bwlogic_or_result;
+	wire [31:0] bwlogic_and_result;
+	wire [31:0] bwlogic_xor_result;
+	reg [31:0] bwlogic_result;
+	reg bwlogic_op_b_negate;
+	always @(*)
+		case (operator_i)
+			7'd5, 7'd6, 7'd7: bwlogic_op_b_negate = (RV32B != 32'sd0 ? 1'b1 : 1'b0);
+			7'd43: bwlogic_op_b_negate = (RV32B != 32'sd0 ? ~instr_first_cycle_i : 1'b0);
+			default: bwlogic_op_b_negate = 1'b0;
+		endcase
+	assign bwlogic_operand_b = (bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i);
+	assign bwlogic_or_result = operand_a_i | bwlogic_operand_b;
+	assign bwlogic_and_result = operand_a_i & bwlogic_operand_b;
+	assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b;
+	assign bwlogic_or = (operator_i == 7'd3) | (operator_i == 7'd6);
+	assign bwlogic_and = (operator_i == 7'd4) | (operator_i == 7'd7);
+	always @(*)
+		case (1'b1)
+			bwlogic_or: bwlogic_result = bwlogic_or_result;
+			bwlogic_and: bwlogic_result = bwlogic_and_result;
+			default: bwlogic_result = bwlogic_xor_result;
+		endcase
+	wire [5:0] bitcnt_result;
+	wire [31:0] minmax_result;
+	reg [31:0] pack_result;
+	wire [31:0] sext_result;
+	reg [31:0] singlebit_result;
+	reg [31:0] rev_result;
+	reg [31:0] shuffle_result;
+	reg [31:0] butterfly_result;
+	reg [31:0] invbutterfly_result;
+	reg [31:0] clmul_result;
+	reg [31:0] multicycle_result;
+	generate
+		if (RV32B != 32'sd0) begin : g_alu_rvb
+			wire zbe_op;
+			wire bitcnt_ctz;
+			wire bitcnt_clz;
+			wire bitcnt_cz;
+			reg [31:0] bitcnt_bits;
+			wire [31:0] bitcnt_mask_op;
+			reg [31:0] bitcnt_bit_mask;
+			reg [191:0] bitcnt_partial;
+			wire [31:0] bitcnt_partial_lsb_d;
+			wire [31:0] bitcnt_partial_msb_d;
+			assign bitcnt_ctz = operator_i == 7'd38;
+			assign bitcnt_clz = operator_i == 7'd37;
+			assign bitcnt_cz = bitcnt_ctz | bitcnt_clz;
+			assign bitcnt_result = bitcnt_partial[0+:6];
+			assign bitcnt_mask_op = (bitcnt_clz ? operand_a_rev : operand_a_i);
+			always @(*) begin
+				bitcnt_bit_mask = bitcnt_mask_op;
+				bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 1);
+				bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 2);
+				bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 4);
+				bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 8);
+				bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 16);
+				bitcnt_bit_mask = ~bitcnt_bit_mask;
+			end
+			assign zbe_op = (operator_i == 7'd50) | (operator_i == 7'd51);
+			always @(*)
+				case (1'b1)
+					zbe_op: bitcnt_bits = operand_b_i;
+					bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op;
+					default: bitcnt_bits = operand_a_i;
+				endcase
+			always @(*) begin
+				bitcnt_partial = {32 {6'b000000}};
+				begin : sv2v_autoblock_2
+					reg [31:0] i;
+					for (i = 1; i < 32; i = i + 2)
+						bitcnt_partial[(31 - i) * 6+:6] = {5'h00, bitcnt_bits[i]} + {5'h00, bitcnt_bits[i - 1]};
+				end
+				begin : sv2v_autoblock_3
+					reg [31:0] i;
+					for (i = 3; i < 32; i = i + 4)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
+				end
+				begin : sv2v_autoblock_4
+					reg [31:0] i;
+					for (i = 7; i < 32; i = i + 8)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
+				end
+				begin : sv2v_autoblock_5
+					reg [31:0] i;
+					for (i = 15; i < 32; i = i + 16)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(39 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
+				end
+				bitcnt_partial[0+:6] = bitcnt_partial[96+:6] + bitcnt_partial[0+:6];
+				bitcnt_partial[48+:6] = bitcnt_partial[96+:6] + bitcnt_partial[48+:6];
+				begin : sv2v_autoblock_6
+					reg [31:0] i;
+					for (i = 11; i < 32; i = i + 8)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
+				end
+				begin : sv2v_autoblock_7
+					reg [31:0] i;
+					for (i = 5; i < 32; i = i + 4)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
+				end
+				bitcnt_partial[186+:6] = {5'h00, bitcnt_bits[0]};
+				begin : sv2v_autoblock_8
+					reg [31:0] i;
+					for (i = 2; i < 32; i = i + 2)
+						bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(32 - i) * 6+:6] + {5'h00, bitcnt_bits[i]};
+				end
+			end
+			assign minmax_result = (cmp_result ? operand_a_i : operand_b_i);
+			wire packu;
+			wire packh;
+			assign packu = operator_i == 7'd33;
+			assign packh = operator_i == 7'd34;
+			always @(*)
+				case (1'b1)
+					packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]};
+					packh: pack_result = {16'h0000, operand_b_i[7:0], operand_a_i[7:0]};
+					default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]};
+				endcase
+			assign sext_result = (operator_i == 7'd35 ? {{24 {operand_a_i[7]}}, operand_a_i[7:0]} : {{16 {operand_a_i[15]}}, operand_a_i[15:0]});
+			always @(*)
+				case (operator_i)
+					7'd46: singlebit_result = operand_a_i | shift_result;
+					7'd47: singlebit_result = operand_a_i & ~shift_result;
+					7'd48: singlebit_result = operand_a_i ^ shift_result;
+					default: singlebit_result = {31'h00000000, shift_result[0]};
+				endcase
+			wire [4:0] zbp_shift_amt;
+			wire gorc_op;
+			assign gorc_op = operator_i == 7'd16;
+			assign zbp_shift_amt[2:0] = (RV32B == 32'sd2 ? shift_amt[2:0] : {3 {&shift_amt[2:0]}});
+			assign zbp_shift_amt[4:3] = (RV32B == 32'sd2 ? shift_amt[4:3] : {2 {&shift_amt[4:3]}});
+			always @(*) begin
+				rev_result = operand_a_i;
+				if (zbp_shift_amt[0])
+					rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h55555555) << 1)) | ((rev_result & 32'haaaaaaaa) >> 1);
+				if (zbp_shift_amt[1])
+					rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h33333333) << 2)) | ((rev_result & 32'hcccccccc) >> 2);
+				if (zbp_shift_amt[2])
+					rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h0f0f0f0f) << 4)) | ((rev_result & 32'hf0f0f0f0) >> 4);
+				if (zbp_shift_amt[3])
+					rev_result = ((gorc_op & (RV32B == 32'sd2) ? rev_result : 32'h00000000) | ((rev_result & 32'h00ff00ff) << 8)) | ((rev_result & 32'hff00ff00) >> 8);
+				if (zbp_shift_amt[4])
+					rev_result = ((gorc_op & (RV32B == 32'sd2) ? rev_result : 32'h00000000) | ((rev_result & 32'h0000ffff) << 16)) | ((rev_result & 32'hffff0000) >> 16);
+			end
+			wire crc_hmode;
+			wire crc_bmode;
+			wire [31:0] clmul_result_rev;
+			if (RV32B == 32'sd2) begin : gen_alu_rvb_full
+				localparam [127:0] SHUFFLE_MASK_L = 128'h00ff00000f000f003030303044444444;
+				localparam [127:0] SHUFFLE_MASK_R = 128'h0000ff0000f000f00c0c0c0c22222222;
+				localparam [127:0] FLIP_MASK_L = 128'h22001100004400004411000011000000;
+				localparam [127:0] FLIP_MASK_R = 128'h00880044000022000000882200000088;
+				wire [31:0] SHUFFLE_MASK_NOT [0:3];
+				genvar i;
+				for (i = 0; i < 4; i = i + 1) begin : gen_shuffle_mask_not
+					assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[(3 - i) * 32+:32] | SHUFFLE_MASK_R[(3 - i) * 32+:32]);
+				end
+				wire shuffle_flip;
+				assign shuffle_flip = operator_i == 7'd18;
+				reg [3:0] shuffle_mode;
+				always @(*) begin
+					shuffle_result = operand_a_i;
+					if (shuffle_flip) begin
+						shuffle_mode[3] = shift_amt[0];
+						shuffle_mode[2] = shift_amt[1];
+						shuffle_mode[1] = shift_amt[2];
+						shuffle_mode[0] = shift_amt[3];
+					end
+					else
+						shuffle_mode = shift_amt[3:0];
+					if (shuffle_flip)
+						shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]);
+					if (shuffle_mode[3])
+						shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | (((shuffle_result << 8) & SHUFFLE_MASK_L[96+:32]) | ((shuffle_result >> 8) & SHUFFLE_MASK_R[96+:32]));
+					if (shuffle_mode[2])
+						shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | (((shuffle_result << 4) & SHUFFLE_MASK_L[64+:32]) | ((shuffle_result >> 4) & SHUFFLE_MASK_R[64+:32]));
+					if (shuffle_mode[1])
+						shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | (((shuffle_result << 2) & SHUFFLE_MASK_L[32+:32]) | ((shuffle_result >> 2) & SHUFFLE_MASK_R[32+:32]));
+					if (shuffle_mode[0])
+						shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | (((shuffle_result << 1) & SHUFFLE_MASK_L[0+:32]) | ((shuffle_result >> 1) & SHUFFLE_MASK_R[0+:32]));
+					if (shuffle_flip)
+						shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]);
+				end
+				reg [191:0] bitcnt_partial_q;
+				for (i = 0; i < 32; i = i + 1) begin : gen_bitcnt_reg_in_lsb
+					assign bitcnt_partial_lsb_d[i] = bitcnt_partial[(31 - i) * 6];
+				end
+				for (i = 0; i < 16; i = i + 1) begin : gen_bitcnt_reg_in_b1
+					assign bitcnt_partial_msb_d[i] = bitcnt_partial[((31 - ((2 * i) + 1)) * 6) + 1];
+				end
+				for (i = 0; i < 8; i = i + 1) begin : gen_bitcnt_reg_in_b2
+					assign bitcnt_partial_msb_d[16 + i] = bitcnt_partial[((31 - ((4 * i) + 3)) * 6) + 2];
+				end
+				for (i = 0; i < 4; i = i + 1) begin : gen_bitcnt_reg_in_b3
+					assign bitcnt_partial_msb_d[24 + i] = bitcnt_partial[((31 - ((8 * i) + 7)) * 6) + 3];
+				end
+				for (i = 0; i < 2; i = i + 1) begin : gen_bitcnt_reg_in_b4
+					assign bitcnt_partial_msb_d[28 + i] = bitcnt_partial[((31 - ((16 * i) + 15)) * 6) + 4];
+				end
+				assign bitcnt_partial_msb_d[30] = bitcnt_partial[5];
+				assign bitcnt_partial_msb_d[31] = 1'b0;
+				always @(*) begin
+					bitcnt_partial_q = {32 {6'b000000}};
+					begin : sv2v_autoblock_9
+						reg [31:0] i;
+						for (i = 0; i < 32; i = i + 1)
+							begin : gen_bitcnt_reg_out_lsb
+								bitcnt_partial_q[(31 - i) * 6] = imd_val_q_i[32 + i];
+							end
+					end
+					begin : sv2v_autoblock_10
+						reg [31:0] i;
+						for (i = 0; i < 16; i = i + 1)
+							begin : gen_bitcnt_reg_out_b1
+								bitcnt_partial_q[((31 - ((2 * i) + 1)) * 6) + 1] = imd_val_q_i[i];
+							end
+					end
+					begin : sv2v_autoblock_11
+						reg [31:0] i;
+						for (i = 0; i < 8; i = i + 1)
+							begin : gen_bitcnt_reg_out_b2
+								bitcnt_partial_q[((31 - ((4 * i) + 3)) * 6) + 2] = imd_val_q_i[16 + i];
+							end
+					end
+					begin : sv2v_autoblock_12
+						reg [31:0] i;
+						for (i = 0; i < 4; i = i + 1)
+							begin : gen_bitcnt_reg_out_b3
+								bitcnt_partial_q[((31 - ((8 * i) + 7)) * 6) + 3] = imd_val_q_i[24 + i];
+							end
+					end
+					begin : sv2v_autoblock_13
+						reg [31:0] i;
+						for (i = 0; i < 2; i = i + 1)
+							begin : gen_bitcnt_reg_out_b4
+								bitcnt_partial_q[((31 - ((16 * i) + 15)) * 6) + 4] = imd_val_q_i[28 + i];
+							end
+					end
+					bitcnt_partial_q[5] = imd_val_q_i[30];
+				end
+				wire [31:0] butterfly_mask_l [0:4];
+				wire [31:0] butterfly_mask_r [0:4];
+				wire [31:0] butterfly_mask_not [0:4];
+				wire [31:0] lrotc_stage [0:4];
+				genvar stg;
+				for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_ctrl_stage
+					genvar seg;
+					for (seg = 0; seg < (2 ** stg); seg = seg + 1) begin : gen_butterfly_ctrl
+						assign lrotc_stage[stg][((2 * (16 >> stg)) * (seg + 1)) - 1:(2 * (16 >> stg)) * seg] = {{16 >> stg {1'b0}}, {16 >> stg {1'b1}}} << bitcnt_partial_q[((32 - ((16 >> stg) * ((2 * seg) + 1))) * 6) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) : ($clog2(16 >> stg) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))) - 1)-:($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))];
+						assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)];
+						assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)];
+						assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = 1'sb0;
+						assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = 1'sb0;
+					end
+				end
+				for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_not
+					assign butterfly_mask_not[stg] = ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]);
+				end
+				always @(*) begin
+					butterfly_result = operand_a_i;
+					butterfly_result = ((butterfly_result & butterfly_mask_not[0]) | ((butterfly_result & butterfly_mask_l[0]) >> 16)) | ((butterfly_result & butterfly_mask_r[0]) << 16);
+					butterfly_result = ((butterfly_result & butterfly_mask_not[1]) | ((butterfly_result & butterfly_mask_l[1]) >> 8)) | ((butterfly_result & butterfly_mask_r[1]) << 8);
+					butterfly_result = ((butterfly_result & butterfly_mask_not[2]) | ((butterfly_result & butterfly_mask_l[2]) >> 4)) | ((butterfly_result & butterfly_mask_r[2]) << 4);
+					butterfly_result = ((butterfly_result & butterfly_mask_not[3]) | ((butterfly_result & butterfly_mask_l[3]) >> 2)) | ((butterfly_result & butterfly_mask_r[3]) << 2);
+					butterfly_result = ((butterfly_result & butterfly_mask_not[4]) | ((butterfly_result & butterfly_mask_l[4]) >> 1)) | ((butterfly_result & butterfly_mask_r[4]) << 1);
+					butterfly_result = butterfly_result & operand_b_i;
+				end
+				always @(*) begin
+					invbutterfly_result = operand_a_i & operand_b_i;
+					invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[4]) | ((invbutterfly_result & butterfly_mask_l[4]) >> 1)) | ((invbutterfly_result & butterfly_mask_r[4]) << 1);
+					invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[3]) | ((invbutterfly_result & butterfly_mask_l[3]) >> 2)) | ((invbutterfly_result & butterfly_mask_r[3]) << 2);
+					invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[2]) | ((invbutterfly_result & butterfly_mask_l[2]) >> 4)) | ((invbutterfly_result & butterfly_mask_r[2]) << 4);
+					invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[1]) | ((invbutterfly_result & butterfly_mask_l[1]) >> 8)) | ((invbutterfly_result & butterfly_mask_r[1]) << 8);
+					invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[0]) | ((invbutterfly_result & butterfly_mask_l[0]) >> 16)) | ((invbutterfly_result & butterfly_mask_r[0]) << 16);
+				end
+				wire clmul_rmode;
+				wire clmul_hmode;
+				reg [31:0] clmul_op_a;
+				reg [31:0] clmul_op_b;
+				wire [31:0] operand_b_rev;
+				wire [31:0] clmul_and_stage [0:31];
+				wire [31:0] clmul_xor_stage1 [0:15];
+				wire [31:0] clmul_xor_stage2 [0:7];
+				wire [31:0] clmul_xor_stage3 [0:3];
+				wire [31:0] clmul_xor_stage4 [0:1];
+				wire [31:0] clmul_result_raw;
+				for (i = 0; i < 32; i = i + 1) begin : gen_rev_operand_b
+					assign operand_b_rev[i] = operand_b_i[31 - i];
+				end
+				assign clmul_rmode = operator_i == 7'd54;
+				assign clmul_hmode = operator_i == 7'd55;
+				localparam [31:0] CRC32_POLYNOMIAL = 32'h04c11db7;
+				localparam [31:0] CRC32_MU_REV = 32'hf7011641;
+				localparam [31:0] CRC32C_POLYNOMIAL = 32'h1edc6f41;
+				localparam [31:0] CRC32C_MU_REV = 32'hdea713f1;
+				wire crc_op;
+				wire crc_cpoly;
+				reg [31:0] crc_operand;
+				wire [31:0] crc_poly;
+				wire [31:0] crc_mu_rev;
+				assign crc_op = (((((operator_i == 7'd61) | (operator_i == 7'd60)) | (operator_i == 7'd59)) | (operator_i == 7'd58)) | (operator_i == 7'd57)) | (operator_i == 7'd56);
+				assign crc_cpoly = ((operator_i == 7'd61) | (operator_i == 7'd59)) | (operator_i == 7'd57);
+				assign crc_hmode = (operator_i == 7'd58) | (operator_i == 7'd59);
+				assign crc_bmode = (operator_i == 7'd56) | (operator_i == 7'd57);
+				assign crc_poly = (crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL);
+				assign crc_mu_rev = (crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV);
+				always @(*)
+					case (1'b1)
+						crc_bmode: crc_operand = {operand_a_i[7:0], 24'h000000};
+						crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0000};
+						default: crc_operand = operand_a_i;
+					endcase
+				always @(*)
+					if (crc_op) begin
+						clmul_op_a = (instr_first_cycle_i ? crc_operand : imd_val_q_i[32+:32]);
+						clmul_op_b = (instr_first_cycle_i ? crc_mu_rev : crc_poly);
+					end
+					else begin
+						clmul_op_a = (clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i);
+						clmul_op_b = (clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i);
+					end
+				for (i = 0; i < 32; i = i + 1) begin : gen_clmul_and_op
+					assign clmul_and_stage[i] = (clmul_op_b[i] ? clmul_op_a << i : {32 {1'sb0}});
+				end
+				for (i = 0; i < 16; i = i + 1) begin : gen_clmul_xor_op_l1
+					assign clmul_xor_stage1[i] = clmul_and_stage[2 * i] ^ clmul_and_stage[(2 * i) + 1];
+				end
+				for (i = 0; i < 8; i = i + 1) begin : gen_clmul_xor_op_l2
+					assign clmul_xor_stage2[i] = clmul_xor_stage1[2 * i] ^ clmul_xor_stage1[(2 * i) + 1];
+				end
+				for (i = 0; i < 4; i = i + 1) begin : gen_clmul_xor_op_l3
+					assign clmul_xor_stage3[i] = clmul_xor_stage2[2 * i] ^ clmul_xor_stage2[(2 * i) + 1];
+				end
+				for (i = 0; i < 2; i = i + 1) begin : gen_clmul_xor_op_l4
+					assign clmul_xor_stage4[i] = clmul_xor_stage3[2 * i] ^ clmul_xor_stage3[(2 * i) + 1];
+				end
+				assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1];
+				for (i = 0; i < 32; i = i + 1) begin : gen_rev_clmul_result
+					assign clmul_result_rev[i] = clmul_result_raw[31 - i];
+				end
+				always @(*)
+					case (1'b1)
+						clmul_rmode: clmul_result = clmul_result_rev;
+						clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]};
+						default: clmul_result = clmul_result_raw;
+					endcase
+			end
+			else begin : gen_alu_rvb_notfull
+				wire [31:0] unused_imd_val_q_1;
+				assign unused_imd_val_q_1 = imd_val_q_i[0+:32];
+				wire [32:1] sv2v_tmp_F189D;
+				assign sv2v_tmp_F189D = 1'sb0;
+				always @(*) shuffle_result = sv2v_tmp_F189D;
+				wire [32:1] sv2v_tmp_F770D;
+				assign sv2v_tmp_F770D = 1'sb0;
+				always @(*) butterfly_result = sv2v_tmp_F770D;
+				wire [32:1] sv2v_tmp_02B8B;
+				assign sv2v_tmp_02B8B = 1'sb0;
+				always @(*) invbutterfly_result = sv2v_tmp_02B8B;
+				wire [32:1] sv2v_tmp_B9A55;
+				assign sv2v_tmp_B9A55 = 1'sb0;
+				always @(*) clmul_result = sv2v_tmp_B9A55;
+				assign bitcnt_partial_lsb_d = 1'sb0;
+				assign bitcnt_partial_msb_d = 1'sb0;
+				assign clmul_result_rev = 1'sb0;
+				assign crc_bmode = 1'sb0;
+				assign crc_hmode = 1'sb0;
+			end
+			always @(*)
+				case (operator_i)
+					7'd42: begin
+						multicycle_result = (operand_b_i == 32'h00000000 ? operand_a_i : imd_val_q_i[32+:32]);
+						imd_val_d_o = {operand_a_i, 32'h00000000};
+						if (instr_first_cycle_i)
+							imd_val_we_o = 2'b01;
+						else
+							imd_val_we_o = 2'b00;
+					end
+					7'd43: begin
+						multicycle_result = imd_val_q_i[32+:32] | bwlogic_and_result;
+						imd_val_d_o = {bwlogic_and_result, 32'h00000000};
+						if (instr_first_cycle_i)
+							imd_val_we_o = 2'b01;
+						else
+							imd_val_we_o = 2'b00;
+					end
+					7'd45, 7'd44, 7'd14, 7'd13: begin
+						if (shift_amt[4:0] == 5'h00)
+							multicycle_result = (shift_amt[5] ? operand_a_i : imd_val_q_i[32+:32]);
+						else
+							multicycle_result = imd_val_q_i[32+:32] | shift_result;
+						imd_val_d_o = {shift_result, 32'h00000000};
+						if (instr_first_cycle_i)
+							imd_val_we_o = 2'b01;
+						else
+							imd_val_we_o = 2'b00;
+					end
+					7'd60, 7'd61, 7'd58, 7'd59, 7'd56, 7'd57:
+						if (RV32B == 32'sd2) begin
+							case (1'b1)
+								crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8);
+								crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16);
+								default: multicycle_result = clmul_result_rev;
+							endcase
+							imd_val_d_o = {clmul_result_rev, 32'h00000000};
+							if (instr_first_cycle_i)
+								imd_val_we_o = 2'b01;
+							else
+								imd_val_we_o = 2'b00;
+						end
+						else begin
+							imd_val_d_o = {operand_a_i, 32'h00000000};
+							imd_val_we_o = 2'b00;
+							multicycle_result = 1'sb0;
+						end
+					7'd50, 7'd51:
+						if (RV32B == 32'sd2) begin
+							multicycle_result = (operator_i == 7'd51 ? butterfly_result : invbutterfly_result);
+							imd_val_d_o = {bitcnt_partial_lsb_d, bitcnt_partial_msb_d};
+							if (instr_first_cycle_i)
+								imd_val_we_o = 2'b11;
+							else
+								imd_val_we_o = 2'b00;
+						end
+						else begin
+							imd_val_d_o = {operand_a_i, 32'h00000000};
+							imd_val_we_o = 2'b00;
+							multicycle_result = 1'sb0;
+						end
+					default: begin
+						imd_val_d_o = {operand_a_i, 32'h00000000};
+						imd_val_we_o = 2'b00;
+						multicycle_result = 1'sb0;
+					end
+				endcase
+		end
+		else begin : g_no_alu_rvb
+			wire [63:0] unused_imd_val_q;
+			assign unused_imd_val_q = imd_val_q_i;
+			wire [31:0] unused_butterfly_result;
+			assign unused_butterfly_result = butterfly_result;
+			wire [31:0] unused_invbutterfly_result;
+			assign unused_invbutterfly_result = invbutterfly_result;
+			assign bitcnt_result = 1'sb0;
+			assign minmax_result = 1'sb0;
+			wire [32:1] sv2v_tmp_B3EA0;
+			assign sv2v_tmp_B3EA0 = 1'sb0;
+			always @(*) pack_result = sv2v_tmp_B3EA0;
+			assign sext_result = 1'sb0;
+			wire [32:1] sv2v_tmp_C8829;
+			assign sv2v_tmp_C8829 = 1'sb0;
+			always @(*) singlebit_result = sv2v_tmp_C8829;
+			wire [32:1] sv2v_tmp_F744D;
+			assign sv2v_tmp_F744D = 1'sb0;
+			always @(*) rev_result = sv2v_tmp_F744D;
+			wire [32:1] sv2v_tmp_F189D;
+			assign sv2v_tmp_F189D = 1'sb0;
+			always @(*) shuffle_result = sv2v_tmp_F189D;
+			wire [32:1] sv2v_tmp_F770D;
+			assign sv2v_tmp_F770D = 1'sb0;
+			always @(*) butterfly_result = sv2v_tmp_F770D;
+			wire [32:1] sv2v_tmp_02B8B;
+			assign sv2v_tmp_02B8B = 1'sb0;
+			always @(*) invbutterfly_result = sv2v_tmp_02B8B;
+			wire [32:1] sv2v_tmp_B9A55;
+			assign sv2v_tmp_B9A55 = 1'sb0;
+			always @(*) clmul_result = sv2v_tmp_B9A55;
+			wire [32:1] sv2v_tmp_8750A;
+			assign sv2v_tmp_8750A = 1'sb0;
+			always @(*) multicycle_result = sv2v_tmp_8750A;
+			wire [64:1] sv2v_tmp_78BC2;
+			assign sv2v_tmp_78BC2 = {2 {32'b00000000000000000000000000000000}};
+			always @(*) imd_val_d_o = sv2v_tmp_78BC2;
+			wire [2:1] sv2v_tmp_02FDF;
+			assign sv2v_tmp_02FDF = {2 {1'b0}};
+			always @(*) imd_val_we_o = sv2v_tmp_02FDF;
+		end
+	endgenerate
+	always @(*) begin
+		result_o = 1'sb0;
+		case (operator_i)
+			7'd2, 7'd5, 7'd3, 7'd6, 7'd4, 7'd7: result_o = bwlogic_result;
+			7'd0, 7'd1, 7'd19, 7'd20, 7'd21: result_o = adder_result;
+			7'd10, 7'd9, 7'd8, 7'd12, 7'd11: result_o = shift_result;
+			7'd17, 7'd18: result_o = shuffle_result;
+			7'd26, 7'd27, 7'd24, 7'd25, 7'd22, 7'd23, 7'd40, 7'd41: result_o = {31'h00000000, cmp_result};
+			7'd28, 7'd30, 7'd29, 7'd31: result_o = minmax_result;
+			7'd37, 7'd38, 7'd39: result_o = {26'h0000000, bitcnt_result};
+			7'd32, 7'd34, 7'd33: result_o = pack_result;
+			7'd35, 7'd36: result_o = sext_result;
+			7'd43, 7'd42, 7'd44, 7'd45, 7'd14, 7'd13, 7'd60, 7'd61, 7'd58, 7'd59, 7'd56, 7'd57, 7'd50, 7'd51: result_o = multicycle_result;
+			7'd46, 7'd47, 7'd48, 7'd49: result_o = singlebit_result;
+			7'd15, 7'd16: result_o = rev_result;
+			7'd52: result_o = bfp_result;
+			7'd53, 7'd54, 7'd55: result_o = clmul_result;
+			default:
+				;
+		endcase
+	end
+	wire unused_shift_amt_compl;
+	assign unused_shift_amt_compl = shift_amt_compl[5];
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_branch_predict.v b/verilog/rtl/ibex_core/ibex_branch_predict.v
new file mode 100644
index 0000000..0fe8126
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_branch_predict.v
@@ -0,0 +1,51 @@
+module ibex_branch_predict (
+	clk_i,
+	rst_ni,
+	fetch_rdata_i,
+	fetch_pc_i,
+	fetch_valid_i,
+	predict_branch_taken_o,
+	predict_branch_pc_o
+);
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [31:0] fetch_rdata_i;
+	input wire [31:0] fetch_pc_i;
+	input wire fetch_valid_i;
+	output wire predict_branch_taken_o;
+	output wire [31:0] predict_branch_pc_o;
+	wire [31:0] imm_j_type;
+	wire [31:0] imm_b_type;
+	wire [31:0] imm_cj_type;
+	wire [31:0] imm_cb_type;
+	reg [31:0] branch_imm;
+	wire [31:0] instr;
+	wire instr_j;
+	wire instr_b;
+	wire instr_cj;
+	wire instr_cb;
+	wire instr_b_taken;
+	assign instr = fetch_rdata_i;
+	assign imm_j_type = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+	assign imm_b_type = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+	assign imm_cj_type = {{20 {instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
+	assign imm_cb_type = {{23 {instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
+	assign instr_b = instr[6:0] == 7'h63;
+	assign instr_j = instr[6:0] == 7'h6f;
+	assign instr_cb = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b110) | (instr[15:13] == 3'b111));
+	assign instr_cj = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b101) | (instr[15:13] == 3'b001));
+	always @(*) begin
+		branch_imm = imm_b_type;
+		case (1'b1)
+			instr_j: branch_imm = imm_j_type;
+			instr_b: branch_imm = imm_b_type;
+			instr_cj: branch_imm = imm_cj_type;
+			instr_cb: branch_imm = imm_cb_type;
+			default:
+				;
+		endcase
+	end
+	assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]);
+	assign predict_branch_taken_o = fetch_valid_i & ((instr_j | instr_cj) | instr_b_taken);
+	assign predict_branch_pc_o = fetch_pc_i + branch_imm;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_compressed_decoder.v b/verilog/rtl/ibex_core/ibex_compressed_decoder.v
new file mode 100644
index 0000000..131abd1
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_compressed_decoder.v
@@ -0,0 +1,111 @@
+module ibex_compressed_decoder (
+	clk_i,
+	rst_ni,
+	valid_i,
+	instr_i,
+	instr_o,
+	is_compressed_o,
+	illegal_instr_o
+);
+	input wire clk_i;
+	input wire rst_ni;
+	input wire valid_i;
+	input wire [31:0] instr_i;
+	output reg [31:0] instr_o;
+	output wire is_compressed_o;
+	output reg illegal_instr_o;
+	wire unused_valid;
+	assign unused_valid = valid_i;
+	wire unused_clk_i;
+	wire unused_rst_ni;
+	assign unused_clk_i = clk_i;
+	assign unused_rst_ni = rst_ni;
+	always @(*) begin
+		instr_o = instr_i;
+		illegal_instr_o = 1'b0;
+		case (instr_i[1:0])
+			2'b00:
+				case (instr_i[15:13])
+					3'b000: begin
+						instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], 7'h13};
+						if (instr_i[12:5] == 8'b00000000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], 7'h03};
+					3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, 7'h23};
+					3'b001, 3'b011, 3'b100, 3'b101, 3'b111: illegal_instr_o = 1'b1;
+					default: illegal_instr_o = 1'b1;
+				endcase
+			2'b01:
+				case (instr_i[15:13])
+					3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], 7'h13};
+					3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], 7'h6f};
+					3'b010: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], 7'h13};
+					3'b011: begin
+						instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], 7'h37};
+						if (instr_i[11:7] == 5'h02)
+							instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, 7'h13};
+						if ({instr_i[12], instr_i[6:2]} == 6'b000000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b100:
+						case (instr_i[11:10])
+							2'b00, 2'b01: begin
+								instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], 7'h13};
+								if (instr_i[12] == 1'b1)
+									illegal_instr_o = 1'b1;
+							end
+							2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], 7'h13};
+							2'b11:
+								case ({instr_i[12], instr_i[6:5]})
+									3'b000: instr_o = {9'b010000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], 7'h33};
+									3'b001: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], 7'h33};
+									3'b010: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], 7'h33};
+									3'b011: instr_o = {9'b000000001, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], 7'h33};
+									3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1;
+									default: illegal_instr_o = 1'b1;
+								endcase
+							default: illegal_instr_o = 1'b1;
+						endcase
+					3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], 7'h63};
+					default: illegal_instr_o = 1'b1;
+				endcase
+			2'b10:
+				case (instr_i[15:13])
+					3'b000: begin
+						instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], 7'h13};
+						if (instr_i[12] == 1'b1)
+							illegal_instr_o = 1'b1;
+					end
+					3'b010: begin
+						instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], 7'h03};
+						if (instr_i[11:7] == 5'b00000)
+							illegal_instr_o = 1'b1;
+					end
+					3'b100:
+						if (instr_i[12] == 1'b0) begin
+							if (instr_i[6:2] != 5'b00000)
+								instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], 7'h33};
+							else begin
+								instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, 7'h67};
+								if (instr_i[11:7] == 5'b00000)
+									illegal_instr_o = 1'b1;
+							end
+						end
+						else if (instr_i[6:2] != 5'b00000)
+							instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], 7'h33};
+						else if (instr_i[11:7] == 5'b00000)
+							instr_o = 32'h00100073;
+						else
+							instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, 7'h67};
+					3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, 7'h23};
+					3'b001, 3'b011, 3'b101, 3'b111: illegal_instr_o = 1'b1;
+					default: illegal_instr_o = 1'b1;
+				endcase
+			2'b11:
+				;
+			default: illegal_instr_o = 1'b1;
+		endcase
+	end
+	assign is_compressed_o = instr_i[1:0] != 2'b11;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_controller.v b/verilog/rtl/ibex_core/ibex_controller.v
new file mode 100644
index 0000000..fec6b6b
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_controller.v
@@ -0,0 +1,532 @@
+module ibex_controller (
+	clk_i,
+	rst_ni,
+	ctrl_busy_o,
+	illegal_insn_i,
+	ecall_insn_i,
+	mret_insn_i,
+	dret_insn_i,
+	wfi_insn_i,
+	ebrk_insn_i,
+	csr_pipe_flush_i,
+	instr_valid_i,
+	instr_i,
+	instr_compressed_i,
+	instr_is_compressed_i,
+	instr_bp_taken_i,
+	instr_fetch_err_i,
+	instr_fetch_err_plus2_i,
+	pc_id_i,
+	instr_valid_clear_o,
+	id_in_ready_o,
+	controller_run_o,
+	instr_req_o,
+	pc_set_o,
+	pc_set_spec_o,
+	pc_mux_o,
+	nt_branch_mispredict_o,
+	exc_pc_mux_o,
+	exc_cause_o,
+	lsu_addr_last_i,
+	load_err_i,
+	store_err_i,
+	wb_exception_o,
+	id_exception_o,
+	branch_set_i,
+	branch_set_spec_i,
+	branch_not_set_i,
+	jump_set_i,
+	csr_mstatus_mie_i,
+	irq_pending_i,
+	irqs_i,
+	irq_nm_i,
+	nmi_mode_o,
+	debug_req_i,
+	debug_cause_o,
+	debug_csr_save_o,
+	debug_mode_o,
+	debug_single_step_i,
+	debug_ebreakm_i,
+	debug_ebreaku_i,
+	trigger_match_i,
+	csr_save_if_o,
+	csr_save_id_o,
+	csr_save_wb_o,
+	csr_restore_mret_id_o,
+	csr_restore_dret_id_o,
+	csr_save_cause_o,
+	csr_mtval_o,
+	priv_mode_i,
+	csr_mstatus_tw_i,
+	stall_id_i,
+	stall_wb_i,
+	flush_id_o,
+	ready_wb_i,
+	perf_jump_o,
+	perf_tbranch_o
+);
+	parameter [0:0] WritebackStage = 0;
+	parameter [0:0] BranchPredictor = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	output reg ctrl_busy_o;
+	input wire illegal_insn_i;
+	input wire ecall_insn_i;
+	input wire mret_insn_i;
+	input wire dret_insn_i;
+	input wire wfi_insn_i;
+	input wire ebrk_insn_i;
+	input wire csr_pipe_flush_i;
+	input wire instr_valid_i;
+	input wire [31:0] instr_i;
+	input wire [15:0] instr_compressed_i;
+	input wire instr_is_compressed_i;
+	input wire instr_bp_taken_i;
+	input wire instr_fetch_err_i;
+	input wire instr_fetch_err_plus2_i;
+	input wire [31:0] pc_id_i;
+	output wire instr_valid_clear_o;
+	output wire id_in_ready_o;
+	output reg controller_run_o;
+	output reg instr_req_o;
+	output reg pc_set_o;
+	output reg pc_set_spec_o;
+	output reg [2:0] pc_mux_o;
+	output reg nt_branch_mispredict_o;
+	output reg [1:0] exc_pc_mux_o;
+	output reg [5:0] exc_cause_o;
+	input wire [31:0] lsu_addr_last_i;
+	input wire load_err_i;
+	input wire store_err_i;
+	output wire wb_exception_o;
+	output wire id_exception_o;
+	input wire branch_set_i;
+	input wire branch_set_spec_i;
+	input wire branch_not_set_i;
+	input wire jump_set_i;
+	input wire csr_mstatus_mie_i;
+	input wire irq_pending_i;
+	input wire [17:0] irqs_i;
+	input wire irq_nm_i;
+	output wire nmi_mode_o;
+	input wire debug_req_i;
+	output reg [2:0] debug_cause_o;
+	output reg debug_csr_save_o;
+	output wire debug_mode_o;
+	input wire debug_single_step_i;
+	input wire debug_ebreakm_i;
+	input wire debug_ebreaku_i;
+	input wire trigger_match_i;
+	output reg csr_save_if_o;
+	output reg csr_save_id_o;
+	output reg csr_save_wb_o;
+	output reg csr_restore_mret_id_o;
+	output reg csr_restore_dret_id_o;
+	output reg csr_save_cause_o;
+	output reg [31:0] csr_mtval_o;
+	input wire [1:0] priv_mode_i;
+	input wire csr_mstatus_tw_i;
+	input wire stall_id_i;
+	input wire stall_wb_i;
+	output wire flush_id_o;
+	input wire ready_wb_i;
+	output reg perf_jump_o;
+	output reg perf_tbranch_o;
+	reg [3:0] ctrl_fsm_cs;
+	reg [3:0] ctrl_fsm_ns;
+	reg nmi_mode_q;
+	reg nmi_mode_d;
+	reg debug_mode_q;
+	reg debug_mode_d;
+	reg load_err_q;
+	wire load_err_d;
+	reg store_err_q;
+	wire store_err_d;
+	reg exc_req_q;
+	wire exc_req_d;
+	reg illegal_insn_q;
+	wire illegal_insn_d;
+	reg instr_fetch_err_prio;
+	reg illegal_insn_prio;
+	reg ecall_insn_prio;
+	reg ebrk_insn_prio;
+	reg store_err_prio;
+	reg load_err_prio;
+	wire stall;
+	reg halt_if;
+	reg retain_id;
+	reg flush_id;
+	wire illegal_dret;
+	wire illegal_umode;
+	wire exc_req_lsu;
+	wire special_req;
+	wire special_req_pc_change;
+	wire special_req_flush_only;
+	wire do_single_step_d;
+	reg do_single_step_q;
+	wire enter_debug_mode_prio_d;
+	reg enter_debug_mode_prio_q;
+	wire enter_debug_mode;
+	wire ebreak_into_debug;
+	wire handle_irq;
+	wire id_wb_pending;
+	reg [3:0] mfip_id;
+	wire unused_irq_timer;
+	wire ecall_insn;
+	wire mret_insn;
+	wire dret_insn;
+	wire wfi_insn;
+	wire ebrk_insn;
+	wire csr_pipe_flush;
+	wire instr_fetch_err;
+	assign load_err_d = load_err_i;
+	assign store_err_d = store_err_i;
+	assign ecall_insn = ecall_insn_i & instr_valid_i;
+	assign mret_insn = mret_insn_i & instr_valid_i;
+	assign dret_insn = dret_insn_i & instr_valid_i;
+	assign wfi_insn = wfi_insn_i & instr_valid_i;
+	assign ebrk_insn = ebrk_insn_i & instr_valid_i;
+	assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i;
+	assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;
+	assign illegal_dret = dret_insn & ~debug_mode_q;
+	assign illegal_umode = (priv_mode_i != 2'b11) & (mret_insn | (csr_mstatus_tw_i & wfi_insn));
+	assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != 4'd6);
+	assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != 4'd6);
+	assign exc_req_lsu = store_err_i | load_err_i;
+	assign id_exception_o = exc_req_d;
+	assign special_req_flush_only = wfi_insn | csr_pipe_flush;
+	assign special_req_pc_change = ((mret_insn | dret_insn) | exc_req_d) | exc_req_lsu;
+	assign special_req = special_req_pc_change | special_req_flush_only;
+	assign id_wb_pending = instr_valid_i | ~ready_wb_i;
+	generate
+		if (WritebackStage) begin : g_wb_exceptions
+			always @(*) begin
+				instr_fetch_err_prio = 0;
+				illegal_insn_prio = 0;
+				ecall_insn_prio = 0;
+				ebrk_insn_prio = 0;
+				store_err_prio = 0;
+				load_err_prio = 0;
+				if (store_err_q)
+					store_err_prio = 1'b1;
+				else if (load_err_q)
+					load_err_prio = 1'b1;
+				else if (instr_fetch_err)
+					instr_fetch_err_prio = 1'b1;
+				else if (illegal_insn_q)
+					illegal_insn_prio = 1'b1;
+				else if (ecall_insn)
+					ecall_insn_prio = 1'b1;
+				else if (ebrk_insn)
+					ebrk_insn_prio = 1'b1;
+			end
+			assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i;
+		end
+		else begin : g_no_wb_exceptions
+			always @(*) begin
+				instr_fetch_err_prio = 0;
+				illegal_insn_prio = 0;
+				ecall_insn_prio = 0;
+				ebrk_insn_prio = 0;
+				store_err_prio = 0;
+				load_err_prio = 0;
+				if (instr_fetch_err)
+					instr_fetch_err_prio = 1'b1;
+				else if (illegal_insn_q)
+					illegal_insn_prio = 1'b1;
+				else if (ecall_insn)
+					ecall_insn_prio = 1'b1;
+				else if (ebrk_insn)
+					ebrk_insn_prio = 1'b1;
+				else if (store_err_q)
+					store_err_prio = 1'b1;
+				else if (load_err_q)
+					load_err_prio = 1'b1;
+			end
+			assign wb_exception_o = 1'b0;
+		end
+	endgenerate
+	assign do_single_step_d = (instr_valid_i ? ~debug_mode_q & debug_single_step_i : do_single_step_q);
+	assign enter_debug_mode_prio_d = (debug_req_i | do_single_step_d) & ~debug_mode_q;
+	assign enter_debug_mode = enter_debug_mode_prio_d | (trigger_match_i & ~debug_mode_q);
+	assign ebreak_into_debug = (priv_mode_i == 2'b11 ? debug_ebreakm_i : (priv_mode_i == 2'b00 ? debug_ebreaku_i : 1'b0));
+	assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));
+	always @(*) begin : gen_mfip_id
+		mfip_id = 4'd0;
+		begin : sv2v_autoblock_1
+			reg signed [31:0] i;
+			for (i = 14; i >= 0; i = i - 1)
+				if (irqs_i[i])
+					mfip_id = i[3:0];
+		end
+	end
+	assign unused_irq_timer = irqs_i[16];
+	function automatic [5:0] sv2v_cast_6;
+		input reg [5:0] inp;
+		sv2v_cast_6 = inp;
+	endfunction
+	always @(*) begin
+		instr_req_o = 1'b1;
+		csr_save_if_o = 1'b0;
+		csr_save_id_o = 1'b0;
+		csr_save_wb_o = 1'b0;
+		csr_restore_mret_id_o = 1'b0;
+		csr_restore_dret_id_o = 1'b0;
+		csr_save_cause_o = 1'b0;
+		csr_mtval_o = 1'sb0;
+		pc_mux_o = 3'd0;
+		pc_set_o = 1'b0;
+		pc_set_spec_o = 1'b0;
+		nt_branch_mispredict_o = 1'b0;
+		exc_pc_mux_o = 2'd1;
+		exc_cause_o = 6'b000000;
+		ctrl_fsm_ns = ctrl_fsm_cs;
+		ctrl_busy_o = 1'b1;
+		halt_if = 1'b0;
+		retain_id = 1'b0;
+		flush_id = 1'b0;
+		debug_csr_save_o = 1'b0;
+		debug_cause_o = 3'h1;
+		debug_mode_d = debug_mode_q;
+		nmi_mode_d = nmi_mode_q;
+		perf_tbranch_o = 1'b0;
+		perf_jump_o = 1'b0;
+		controller_run_o = 1'b0;
+		case (ctrl_fsm_cs)
+			4'd0: begin
+				instr_req_o = 1'b0;
+				pc_mux_o = 3'd0;
+				pc_set_o = 1'b1;
+				pc_set_spec_o = 1'b1;
+				ctrl_fsm_ns = 4'd1;
+			end
+			4'd1: begin
+				instr_req_o = 1'b1;
+				pc_mux_o = 3'd0;
+				pc_set_o = 1'b1;
+				pc_set_spec_o = 1'b1;
+				ctrl_fsm_ns = 4'd4;
+			end
+			4'd2: begin
+				ctrl_busy_o = 1'b0;
+				instr_req_o = 1'b0;
+				halt_if = 1'b1;
+				flush_id = 1'b1;
+				ctrl_fsm_ns = 4'd3;
+			end
+			4'd3: begin
+				instr_req_o = 1'b0;
+				halt_if = 1'b1;
+				flush_id = 1'b1;
+				if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i)
+					ctrl_fsm_ns = 4'd4;
+				else
+					ctrl_busy_o = 1'b0;
+			end
+			4'd4: begin
+				if (id_in_ready_o)
+					ctrl_fsm_ns = 4'd5;
+				if (handle_irq) begin
+					ctrl_fsm_ns = 4'd7;
+					halt_if = 1'b1;
+				end
+				if (enter_debug_mode) begin
+					ctrl_fsm_ns = 4'd8;
+					halt_if = 1'b1;
+				end
+			end
+			4'd5: begin
+				controller_run_o = 1'b1;
+				pc_mux_o = 3'd1;
+				if (special_req) begin
+					retain_id = 1'b1;
+					if (ready_wb_i | wb_exception_o)
+						ctrl_fsm_ns = 4'd6;
+				end
+				if (branch_set_i || jump_set_i) begin
+					pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1);
+					perf_tbranch_o = branch_set_i;
+					perf_jump_o = jump_set_i;
+				end
+				if (BranchPredictor)
+					if (instr_bp_taken_i & branch_not_set_i)
+						nt_branch_mispredict_o = 1'b1;
+				if (branch_set_spec_i || jump_set_i)
+					pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1);
+				if ((enter_debug_mode || handle_irq) && (stall || id_wb_pending))
+					halt_if = 1'b1;
+				if ((!stall && !special_req) && !id_wb_pending)
+					if (enter_debug_mode) begin
+						ctrl_fsm_ns = 4'd8;
+						halt_if = 1'b1;
+					end
+					else if (handle_irq) begin
+						ctrl_fsm_ns = 4'd7;
+						halt_if = 1'b1;
+					end
+			end
+			4'd7: begin
+				pc_mux_o = 3'd2;
+				exc_pc_mux_o = 2'd1;
+				if (handle_irq) begin
+					pc_set_o = 1'b1;
+					pc_set_spec_o = 1'b1;
+					csr_save_if_o = 1'b1;
+					csr_save_cause_o = 1'b1;
+					if (irq_nm_i && !nmi_mode_q) begin
+						exc_cause_o = 6'b111111;
+						nmi_mode_d = 1'b1;
+					end
+					else if (irqs_i[14-:15] != 15'b000000000000000)
+						exc_cause_o = sv2v_cast_6({2'b11, mfip_id});
+					else if (irqs_i[15])
+						exc_cause_o = 6'b101011;
+					else if (irqs_i[17])
+						exc_cause_o = 6'b100011;
+					else
+						exc_cause_o = 6'b100111;
+				end
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd8: begin
+				pc_mux_o = 3'd2;
+				exc_pc_mux_o = 2'd2;
+				flush_id = 1'b1;
+				pc_set_o = 1'b1;
+				pc_set_spec_o = 1'b1;
+				csr_save_if_o = 1'b1;
+				debug_csr_save_o = 1'b1;
+				csr_save_cause_o = 1'b1;
+				if (trigger_match_i)
+					debug_cause_o = 3'h2;
+				else if (debug_single_step_i)
+					debug_cause_o = 3'h4;
+				else
+					debug_cause_o = 3'h3;
+				debug_mode_d = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd9: begin
+				flush_id = 1'b1;
+				pc_mux_o = 3'd2;
+				pc_set_o = 1'b1;
+				pc_set_spec_o = 1'b1;
+				exc_pc_mux_o = 2'd2;
+				if (ebreak_into_debug && !debug_mode_q) begin
+					csr_save_cause_o = 1'b1;
+					csr_save_id_o = 1'b1;
+					debug_csr_save_o = 1'b1;
+					debug_cause_o = 3'h1;
+				end
+				debug_mode_d = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+			end
+			4'd6: begin
+				halt_if = 1'b1;
+				flush_id = 1'b1;
+				ctrl_fsm_ns = 4'd5;
+				if ((exc_req_q || store_err_q) || load_err_q) begin
+					pc_set_o = 1'b1;
+					pc_set_spec_o = 1'b1;
+					pc_mux_o = 3'd2;
+					exc_pc_mux_o = (debug_mode_q ? 2'd3 : 2'd0);
+					if (WritebackStage) begin : g_writeback_mepc_save
+						csr_save_id_o = ~(store_err_q | load_err_q);
+						csr_save_wb_o = store_err_q | load_err_q;
+					end
+					else begin : g_no_writeback_mepc_save
+						csr_save_id_o = 1'b0;
+					end
+					csr_save_cause_o = 1'b1;
+					case (1'b1)
+						instr_fetch_err_prio: begin
+							exc_cause_o = 6'b000001;
+							csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i);
+						end
+						illegal_insn_prio: begin
+							exc_cause_o = 6'b000010;
+							csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i);
+						end
+						ecall_insn_prio: exc_cause_o = (priv_mode_i == 2'b11 ? 6'b001011 : 6'b001000);
+						ebrk_insn_prio:
+							if (debug_mode_q | ebreak_into_debug) begin
+								pc_set_o = 1'b0;
+								pc_set_spec_o = 1'b0;
+								csr_save_id_o = 1'b0;
+								csr_save_cause_o = 1'b0;
+								ctrl_fsm_ns = 4'd9;
+								flush_id = 1'b0;
+							end
+							else
+								exc_cause_o = 6'b000011;
+						store_err_prio: begin
+							exc_cause_o = 6'b000111;
+							csr_mtval_o = lsu_addr_last_i;
+						end
+						load_err_prio: begin
+							exc_cause_o = 6'b000101;
+							csr_mtval_o = lsu_addr_last_i;
+						end
+						default:
+							;
+					endcase
+				end
+				else if (mret_insn) begin
+					pc_mux_o = 3'd3;
+					pc_set_o = 1'b1;
+					pc_set_spec_o = 1'b1;
+					csr_restore_mret_id_o = 1'b1;
+					if (nmi_mode_q)
+						nmi_mode_d = 1'b0;
+				end
+				else if (dret_insn) begin
+					pc_mux_o = 3'd4;
+					pc_set_o = 1'b1;
+					pc_set_spec_o = 1'b1;
+					debug_mode_d = 1'b0;
+					csr_restore_dret_id_o = 1'b1;
+				end
+				else if (wfi_insn)
+					ctrl_fsm_ns = 4'd2;
+				else if (csr_pipe_flush && handle_irq)
+					ctrl_fsm_ns = 4'd7;
+				if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug))
+					ctrl_fsm_ns = 4'd8;
+			end
+			default: begin
+				instr_req_o = 1'b0;
+				ctrl_fsm_ns = 4'd0;
+			end
+		endcase
+	end
+	assign flush_id_o = flush_id;
+	assign debug_mode_o = debug_mode_q;
+	assign nmi_mode_o = nmi_mode_q;
+	assign stall = stall_id_i | stall_wb_i;
+	assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id;
+	assign instr_valid_clear_o = ~(stall | retain_id) | flush_id;
+	always @(posedge clk_i or negedge rst_ni) begin : update_regs
+		if (!rst_ni) begin
+			ctrl_fsm_cs <= 4'd0;
+			nmi_mode_q <= 1'b0;
+			do_single_step_q <= 1'b0;
+			debug_mode_q <= 1'b0;
+			enter_debug_mode_prio_q <= 1'b0;
+			load_err_q <= 1'b0;
+			store_err_q <= 1'b0;
+			exc_req_q <= 1'b0;
+			illegal_insn_q <= 1'b0;
+		end
+		else begin
+			ctrl_fsm_cs <= ctrl_fsm_ns;
+			nmi_mode_q <= nmi_mode_d;
+			do_single_step_q <= do_single_step_d;
+			debug_mode_q <= debug_mode_d;
+			enter_debug_mode_prio_q <= enter_debug_mode_prio_d;
+			load_err_q <= load_err_d;
+			store_err_q <= store_err_d;
+			exc_req_q <= exc_req_d;
+			illegal_insn_q <= illegal_insn_d;
+		end
+	end
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_core.v b/verilog/rtl/ibex_core/ibex_core.v
new file mode 100644
index 0000000..209a9ce
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_core.v
@@ -0,0 +1,804 @@
+module ibex_core (
+	clk_i,
+	rst_ni,
+	hart_id_i,
+	boot_addr_i,
+	instr_req_o,
+	instr_gnt_i,
+	instr_rvalid_i,
+	instr_addr_o,
+	instr_rdata_i,
+	instr_err_i,
+	data_req_o,
+	data_gnt_i,
+	data_rvalid_i,
+	data_we_o,
+	data_be_o,
+	data_addr_o,
+	data_wdata_o,
+	data_rdata_i,
+	data_err_i,
+	dummy_instr_id_o,
+	rf_raddr_a_o,
+	rf_raddr_b_o,
+	rf_waddr_wb_o,
+	rf_we_wb_o,
+	rf_wdata_wb_ecc_o,
+	rf_rdata_a_ecc_i,
+	rf_rdata_b_ecc_i,
+	ic_tag_req_o,
+	ic_tag_write_o,
+	ic_tag_addr_o,
+	ic_tag_wdata_o,
+	ic_tag_rdata_i,
+	ic_data_req_o,
+	ic_data_write_o,
+	ic_data_addr_o,
+	ic_data_wdata_o,
+	ic_data_rdata_i,
+	eFPGA_operand_a_o,
+	eFPGA_operand_b_o,
+	eFPGA_result_a_i,
+	eFPGA_result_b_i,
+	eFPGA_result_c_i,
+	eFPGA_write_strobe_o,
+	eFPGA_fpga_done_i,
+	eFPGA_en_o,
+	eFPGA_operator_o,
+	eFPGA_delay_o,
+	irq_software_i,
+	irq_timer_i,
+	irq_external_i,
+	irq_fast_i,
+	irq_nm_i,
+	irq_pending_o,
+	debug_req_i,
+	crash_dump_o,
+	fetch_enable_i,
+	alert_minor_o,
+	alert_major_o,
+	core_busy_o
+);
+	parameter [0:0] PMPEnable = 1'b0;
+	parameter [31:0] PMPGranularity = 0;
+	parameter [31:0] PMPNumRegions = 4;
+	parameter [31:0] MHPMCounterNum = 0;
+	parameter [31:0] MHPMCounterWidth = 40;
+	parameter [0:0] RV32E = 1'b0;
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd0;
+	parameter [0:0] BranchTargetALU = 1'b0;
+	parameter [0:0] WritebackStage = 1'b0;
+	parameter [0:0] ICache = 1'b0;
+	parameter [0:0] ICacheECC = 1'b0;
+	localparam [31:0] ibex_pkg_BUS_SIZE = 32;
+	parameter [31:0] BusSizeECC = ibex_pkg_BUS_SIZE;
+	localparam [31:0] ibex_pkg_ADDR_W = 32;
+	localparam [31:0] ibex_pkg_IC_LINE_SIZE = 64;
+	localparam [31:0] ibex_pkg_IC_LINE_BYTES = 8;
+	localparam [31:0] ibex_pkg_IC_NUM_WAYS = 2;
+	localparam [31:0] ibex_pkg_IC_SIZE_BYTES = 4096;
+	localparam [31:0] ibex_pkg_IC_NUM_LINES = (ibex_pkg_IC_SIZE_BYTES / ibex_pkg_IC_NUM_WAYS) / ibex_pkg_IC_LINE_BYTES;
+	localparam [31:0] ibex_pkg_IC_INDEX_W = $clog2(ibex_pkg_IC_NUM_LINES);
+	localparam [31:0] ibex_pkg_IC_LINE_W = 3;
+	localparam [31:0] ibex_pkg_IC_TAG_SIZE = ((ibex_pkg_ADDR_W - ibex_pkg_IC_INDEX_W) - ibex_pkg_IC_LINE_W) + 1;
+	parameter [31:0] TagSizeECC = ibex_pkg_IC_TAG_SIZE;
+	parameter [31:0] LineSizeECC = ibex_pkg_IC_LINE_SIZE;
+	parameter [0:0] BranchPredictor = 1'b0;
+	parameter [0:0] DbgTriggerEn = 1'b0;
+	parameter [31:0] DbgHwBreakNum = 1;
+	parameter [0:0] ResetAll = 1'b0;
+	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
+	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
+	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
+	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
+	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
+	parameter [0:0] SecureIbex = 1'b0;
+	parameter [0:0] DummyInstructions = 1'b0;
+	parameter [0:0] RegFileECC = 1'b0;
+	parameter [31:0] RegFileDataWidth = 32;
+	parameter [31:0] DmHaltAddr = 32'h1a110800;
+	parameter [31:0] DmExceptionAddr = 32'h1a110808;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [31:0] hart_id_i;
+	input wire [31:0] boot_addr_i;
+	output wire instr_req_o;
+	input wire instr_gnt_i;
+	input wire instr_rvalid_i;
+	output wire [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	input wire instr_err_i;
+	output wire data_req_o;
+	input wire data_gnt_i;
+	input wire data_rvalid_i;
+	output wire data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_addr_o;
+	output wire [31:0] data_wdata_o;
+	input wire [31:0] data_rdata_i;
+	input wire data_err_i;
+	output wire dummy_instr_id_o;
+	output wire [4:0] rf_raddr_a_o;
+	output wire [4:0] rf_raddr_b_o;
+	output wire [4:0] rf_waddr_wb_o;
+	output wire rf_we_wb_o;
+	output wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc_o;
+	input wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc_i;
+	input wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc_i;
+	output wire [1:0] ic_tag_req_o;
+	output wire ic_tag_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_tag_addr_o;
+	output wire [TagSizeECC - 1:0] ic_tag_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] ic_tag_rdata_i;
+	output wire [1:0] ic_data_req_o;
+	output wire ic_data_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_data_addr_o;
+	output wire [LineSizeECC - 1:0] ic_data_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] ic_data_rdata_i;
+	output wire [31:0] eFPGA_operand_a_o;
+	output wire [31:0] eFPGA_operand_b_o;
+	input wire [31:0] eFPGA_result_a_i;
+	input wire [31:0] eFPGA_result_b_i;
+	input wire [31:0] eFPGA_result_c_i;
+	output wire eFPGA_write_strobe_o;
+	input wire eFPGA_fpga_done_i;
+	output wire eFPGA_en_o;
+	output wire [1:0] eFPGA_operator_o;
+	output wire [3:0] eFPGA_delay_o;
+	input wire irq_software_i;
+	input wire irq_timer_i;
+	input wire irq_external_i;
+	input wire [14:0] irq_fast_i;
+	input wire irq_nm_i;
+	output wire irq_pending_o;
+	input wire debug_req_i;
+	output wire [127:0] crash_dump_o;
+	input wire fetch_enable_i;
+	output wire alert_minor_o;
+	output wire alert_major_o;
+	output wire core_busy_o;
+	localparam [31:0] PMP_NUM_CHAN = 2;
+	localparam [0:0] DataIndTiming = SecureIbex;
+	localparam [0:0] PCIncrCheck = SecureIbex;
+	localparam [0:0] ShadowCSR = 1'b0;
+	localparam [0:0] SpecBranch = PMPEnable & (PMPNumRegions == 16);
+	wire dummy_instr_id;
+	wire instr_valid_id;
+	wire instr_new_id;
+	wire [31:0] instr_rdata_id;
+	wire [31:0] instr_rdata_alu_id;
+	wire [15:0] instr_rdata_c_id;
+	wire instr_is_compressed_id;
+	wire instr_perf_count_id;
+	wire instr_bp_taken_id;
+	wire instr_fetch_err;
+	wire instr_fetch_err_plus2;
+	wire illegal_c_insn_id;
+	wire [31:0] pc_if;
+	wire [31:0] pc_id;
+	wire [31:0] pc_wb;
+	wire [67:0] imd_val_d_ex;
+	wire [67:0] imd_val_q_ex;
+	wire [1:0] imd_val_we_ex;
+	wire data_ind_timing;
+	wire dummy_instr_en;
+	wire [2:0] dummy_instr_mask;
+	wire dummy_instr_seed_en;
+	wire [31:0] dummy_instr_seed;
+	wire icache_enable;
+	wire icache_inval;
+	wire pc_mismatch_alert;
+	wire csr_shadow_err;
+	wire instr_first_cycle_id;
+	wire instr_valid_clear;
+	wire pc_set;
+	wire pc_set_spec;
+	wire nt_branch_mispredict;
+	wire [31:0] nt_branch_addr;
+	wire [2:0] pc_mux_id;
+	wire [1:0] exc_pc_mux_id;
+	wire [5:0] exc_cause;
+	wire lsu_load_err;
+	wire lsu_store_err;
+	wire lsu_addr_incr_req;
+	wire [31:0] lsu_addr_last;
+	wire [31:0] branch_target_ex;
+	wire branch_decision;
+	wire ctrl_busy;
+	wire if_busy;
+	wire lsu_busy;
+	wire [4:0] rf_raddr_a;
+	wire [31:0] rf_rdata_a;
+	wire [4:0] rf_raddr_b;
+	wire [31:0] rf_rdata_b;
+	wire rf_ren_a;
+	wire rf_ren_b;
+	wire [4:0] rf_waddr_wb;
+	wire [31:0] rf_wdata_wb;
+	wire [31:0] rf_wdata_fwd_wb;
+	wire [31:0] rf_wdata_lsu;
+	wire rf_we_wb;
+	wire rf_we_lsu;
+	wire rf_ecc_err_comb;
+	wire [4:0] rf_waddr_id;
+	wire [31:0] rf_wdata_id;
+	wire rf_we_id;
+	wire rf_rd_a_wb_match;
+	wire rf_rd_b_wb_match;
+	wire [6:0] alu_operator_ex;
+	wire [31:0] alu_operand_a_ex;
+	wire [31:0] alu_operand_b_ex;
+	wire [31:0] bt_a_operand;
+	wire [31:0] bt_b_operand;
+	wire [31:0] alu_adder_result_ex;
+	wire [31:0] result_ex;
+	wire mult_en_ex;
+	wire div_en_ex;
+	wire mult_sel_ex;
+	wire div_sel_ex;
+	wire [1:0] multdiv_operator_ex;
+	wire [1:0] multdiv_signed_mode_ex;
+	wire [31:0] multdiv_operand_a_ex;
+	wire [31:0] multdiv_operand_b_ex;
+	wire multdiv_ready_id;
+	wire csr_access;
+	wire [1:0] csr_op;
+	wire csr_op_en;
+	wire [11:0] csr_addr;
+	wire [31:0] csr_rdata;
+	wire [31:0] csr_wdata;
+	wire illegal_csr_insn_id;
+	wire lsu_we;
+	wire [1:0] lsu_type;
+	wire lsu_sign_ext;
+	wire lsu_req;
+	wire [31:0] lsu_wdata;
+	wire lsu_req_done;
+	wire id_in_ready;
+	wire ex_valid;
+	wire lsu_resp_valid;
+	wire lsu_resp_err;
+	wire instr_req_int;
+	wire instr_req_gated;
+	wire en_wb;
+	wire [1:0] instr_type_wb;
+	wire ready_wb;
+	wire rf_write_wb;
+	wire outstanding_load_wb;
+	wire outstanding_store_wb;
+	wire nmi_mode;
+	wire [17:0] irqs;
+	wire csr_mstatus_mie;
+	wire [31:0] csr_mepc;
+	wire [31:0] csr_depc;
+	wire [(PMPNumRegions * 34) - 1:0] csr_pmp_addr;
+	wire [(PMPNumRegions * 6) - 1:0] csr_pmp_cfg;
+	wire [2:0] csr_pmp_mseccfg;
+	wire pmp_req_err [0:1];
+	wire instr_req_out;
+	wire data_req_out;
+	wire csr_save_if;
+	wire csr_save_id;
+	wire csr_save_wb;
+	wire csr_restore_mret_id;
+	wire csr_restore_dret_id;
+	wire csr_save_cause;
+	wire csr_mtvec_init;
+	wire [31:0] csr_mtvec;
+	wire [31:0] csr_mtval;
+	wire csr_mstatus_tw;
+	wire [1:0] priv_mode_id;
+	wire [1:0] priv_mode_if;
+	wire [1:0] priv_mode_lsu;
+	wire debug_mode;
+	wire [2:0] debug_cause;
+	wire debug_csr_save;
+	wire debug_single_step;
+	wire debug_ebreakm;
+	wire debug_ebreaku;
+	wire trigger_match;
+	wire instr_id_done;
+	wire instr_done_wb;
+	wire perf_instr_ret_wb;
+	wire perf_instr_ret_compressed_wb;
+	wire perf_instr_ret_wb_spec;
+	wire perf_instr_ret_compressed_wb_spec;
+	wire perf_iside_wait;
+	wire perf_dside_wait;
+	wire perf_mul_wait;
+	wire perf_div_wait;
+	wire perf_jump;
+	wire perf_branch;
+	wire perf_tbranch;
+	wire perf_load;
+	wire perf_store;
+	wire illegal_insn_id;
+	wire unused_illegal_insn_id;
+	assign core_busy_o = (ctrl_busy | if_busy) | lsu_busy;
+	localparam [31:0] ibex_pkg_PMP_I = 0;
+	ibex_if_stage #(
+		.DmHaltAddr(DmHaltAddr),
+		.DmExceptionAddr(DmExceptionAddr),
+		.DummyInstructions(DummyInstructions),
+		.ICache(ICache),
+		.ICacheECC(ICacheECC),
+		.BusSizeECC(BusSizeECC),
+		.TagSizeECC(TagSizeECC),
+		.LineSizeECC(LineSizeECC),
+		.PCIncrCheck(PCIncrCheck),
+		.ResetAll(ResetAll),
+		.RndCnstLfsrSeed(RndCnstLfsrSeed),
+		.RndCnstLfsrPerm(RndCnstLfsrPerm),
+		.BranchPredictor(BranchPredictor)
+	) if_stage_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.boot_addr_i(boot_addr_i),
+		.req_i(instr_req_gated),
+		.instr_req_o(instr_req_out),
+		.instr_addr_o(instr_addr_o),
+		.instr_gnt_i(instr_gnt_i),
+		.instr_rvalid_i(instr_rvalid_i),
+		.instr_rdata_i(instr_rdata_i),
+		.instr_err_i(instr_err_i),
+		.instr_pmp_err_i(pmp_req_err[ibex_pkg_PMP_I]),
+		.ic_tag_req_o(ic_tag_req_o),
+		.ic_tag_write_o(ic_tag_write_o),
+		.ic_tag_addr_o(ic_tag_addr_o),
+		.ic_tag_wdata_o(ic_tag_wdata_o),
+		.ic_tag_rdata_i(ic_tag_rdata_i),
+		.ic_data_req_o(ic_data_req_o),
+		.ic_data_write_o(ic_data_write_o),
+		.ic_data_addr_o(ic_data_addr_o),
+		.ic_data_wdata_o(ic_data_wdata_o),
+		.ic_data_rdata_i(ic_data_rdata_i),
+		.instr_valid_id_o(instr_valid_id),
+		.instr_new_id_o(instr_new_id),
+		.instr_rdata_id_o(instr_rdata_id),
+		.instr_rdata_alu_id_o(instr_rdata_alu_id),
+		.instr_rdata_c_id_o(instr_rdata_c_id),
+		.instr_is_compressed_id_o(instr_is_compressed_id),
+		.instr_bp_taken_o(instr_bp_taken_id),
+		.instr_fetch_err_o(instr_fetch_err),
+		.instr_fetch_err_plus2_o(instr_fetch_err_plus2),
+		.illegal_c_insn_id_o(illegal_c_insn_id),
+		.dummy_instr_id_o(dummy_instr_id),
+		.pc_if_o(pc_if),
+		.pc_id_o(pc_id),
+		.instr_valid_clear_i(instr_valid_clear),
+		.pc_set_i(pc_set),
+		.pc_set_spec_i(pc_set_spec),
+		.pc_mux_i(pc_mux_id),
+		.nt_branch_mispredict_i(nt_branch_mispredict),
+		.exc_pc_mux_i(exc_pc_mux_id),
+		.exc_cause(exc_cause),
+		.dummy_instr_en_i(dummy_instr_en),
+		.dummy_instr_mask_i(dummy_instr_mask),
+		.dummy_instr_seed_en_i(dummy_instr_seed_en),
+		.dummy_instr_seed_i(dummy_instr_seed),
+		.icache_enable_i(icache_enable),
+		.icache_inval_i(icache_inval),
+		.branch_target_ex_i(branch_target_ex),
+		.nt_branch_addr_i(nt_branch_addr),
+		.csr_mepc_i(csr_mepc),
+		.csr_depc_i(csr_depc),
+		.csr_mtvec_i(csr_mtvec),
+		.csr_mtvec_init_o(csr_mtvec_init),
+		.id_in_ready_i(id_in_ready),
+		.pc_mismatch_alert_o(pc_mismatch_alert),
+		.if_busy_o(if_busy)
+	);
+	assign perf_iside_wait = id_in_ready & ~instr_valid_id;
+	assign instr_req_o = instr_req_out & ~pmp_req_err[ibex_pkg_PMP_I];
+	assign instr_req_gated = instr_req_int & fetch_enable_i;
+	wire eFPGA_en;
+	wire [1:0] eFPGA_operator;
+	wire [3:0] eFPGA_delay;
+	assign eFPGA_en_o = eFPGA_en;
+	assign eFPGA_operator_o = eFPGA_operator;
+	assign eFPGA_delay_o = eFPGA_delay;
+	ibex_id_stage #(
+		.RV32E(RV32E),
+		.RV32M(RV32M),
+		.RV32B(RV32B),
+		.RV32Zk(RV32Zk),
+		.BranchTargetALU(BranchTargetALU),
+		.DataIndTiming(DataIndTiming),
+		.SpecBranch(SpecBranch),
+		.WritebackStage(WritebackStage),
+		.BranchPredictor(BranchPredictor)
+	) id_stage_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.ctrl_busy_o(ctrl_busy),
+		.illegal_insn_o(illegal_insn_id),
+		.instr_valid_i(instr_valid_id),
+		.instr_rdata_i(instr_rdata_id),
+		.instr_rdata_alu_i(instr_rdata_alu_id),
+		.instr_rdata_c_i(instr_rdata_c_id),
+		.instr_is_compressed_i(instr_is_compressed_id),
+		.instr_bp_taken_i(instr_bp_taken_id),
+		.branch_decision_i(branch_decision),
+		.instr_first_cycle_id_o(instr_first_cycle_id),
+		.instr_valid_clear_o(instr_valid_clear),
+		.id_in_ready_o(id_in_ready),
+		.instr_req_o(instr_req_int),
+		.pc_set_o(pc_set),
+		.pc_set_spec_o(pc_set_spec),
+		.pc_mux_o(pc_mux_id),
+		.nt_branch_mispredict_o(nt_branch_mispredict),
+		.nt_branch_addr_o(nt_branch_addr),
+		.exc_pc_mux_o(exc_pc_mux_id),
+		.exc_cause_o(exc_cause),
+		.icache_inval_o(icache_inval),
+		.instr_fetch_err_i(instr_fetch_err),
+		.instr_fetch_err_plus2_i(instr_fetch_err_plus2),
+		.illegal_c_insn_i(illegal_c_insn_id),
+		.pc_id_i(pc_id),
+		.ex_valid_i(ex_valid),
+		.lsu_resp_valid_i(lsu_resp_valid),
+		.alu_operator_ex_o(alu_operator_ex),
+		.alu_operand_a_ex_o(alu_operand_a_ex),
+		.alu_operand_b_ex_o(alu_operand_b_ex),
+		.imd_val_q_ex_o(imd_val_q_ex),
+		.imd_val_d_ex_i(imd_val_d_ex),
+		.imd_val_we_ex_i(imd_val_we_ex),
+		.bt_a_operand_o(bt_a_operand),
+		.bt_b_operand_o(bt_b_operand),
+		.mult_en_ex_o(mult_en_ex),
+		.div_en_ex_o(div_en_ex),
+		.mult_sel_ex_o(mult_sel_ex),
+		.div_sel_ex_o(div_sel_ex),
+		.multdiv_operator_ex_o(multdiv_operator_ex),
+		.multdiv_signed_mode_ex_o(multdiv_signed_mode_ex),
+		.multdiv_operand_a_ex_o(multdiv_operand_a_ex),
+		.multdiv_operand_b_ex_o(multdiv_operand_b_ex),
+		.multdiv_ready_id_o(multdiv_ready_id),
+		.csr_access_o(csr_access),
+		.csr_op_o(csr_op),
+		.csr_op_en_o(csr_op_en),
+		.csr_save_if_o(csr_save_if),
+		.csr_save_id_o(csr_save_id),
+		.csr_save_wb_o(csr_save_wb),
+		.csr_restore_mret_id_o(csr_restore_mret_id),
+		.csr_restore_dret_id_o(csr_restore_dret_id),
+		.csr_save_cause_o(csr_save_cause),
+		.csr_mtval_o(csr_mtval),
+		.priv_mode_i(priv_mode_id),
+		.csr_mstatus_tw_i(csr_mstatus_tw),
+		.illegal_csr_insn_i(illegal_csr_insn_id),
+		.data_ind_timing_i(data_ind_timing),
+		.eFPGA_en_o(eFPGA_en),
+		.eFPGA_operator_o(eFPGA_operator),
+		.eFPGA_operand_a_o(eFPGA_operand_a_o),
+		.eFPGA_operand_b_o(eFPGA_operand_b_o),
+		.eFPGA_delay_o(eFPGA_delay),
+		.lsu_req_o(lsu_req),
+		.lsu_we_o(lsu_we),
+		.lsu_type_o(lsu_type),
+		.lsu_sign_ext_o(lsu_sign_ext),
+		.lsu_wdata_o(lsu_wdata),
+		.lsu_req_done_i(lsu_req_done),
+		.lsu_addr_incr_req_i(lsu_addr_incr_req),
+		.lsu_addr_last_i(lsu_addr_last),
+		.lsu_load_err_i(lsu_load_err),
+		.lsu_store_err_i(lsu_store_err),
+		.csr_mstatus_mie_i(csr_mstatus_mie),
+		.irq_pending_i(irq_pending_o),
+		.irqs_i(irqs),
+		.irq_nm_i(irq_nm_i),
+		.nmi_mode_o(nmi_mode),
+		.debug_mode_o(debug_mode),
+		.debug_cause_o(debug_cause),
+		.debug_csr_save_o(debug_csr_save),
+		.debug_req_i(debug_req_i),
+		.debug_single_step_i(debug_single_step),
+		.debug_ebreakm_i(debug_ebreakm),
+		.debug_ebreaku_i(debug_ebreaku),
+		.trigger_match_i(trigger_match),
+		.result_ex_i(result_ex),
+		.csr_rdata_i(csr_rdata),
+		.rf_raddr_a_o(rf_raddr_a),
+		.rf_rdata_a_i(rf_rdata_a),
+		.rf_raddr_b_o(rf_raddr_b),
+		.rf_rdata_b_i(rf_rdata_b),
+		.rf_ren_a_o(rf_ren_a),
+		.rf_ren_b_o(rf_ren_b),
+		.rf_waddr_id_o(rf_waddr_id),
+		.rf_wdata_id_o(rf_wdata_id),
+		.rf_we_id_o(rf_we_id),
+		.rf_rd_a_wb_match_o(rf_rd_a_wb_match),
+		.rf_rd_b_wb_match_o(rf_rd_b_wb_match),
+		.rf_waddr_wb_i(rf_waddr_wb),
+		.rf_wdata_fwd_wb_i(rf_wdata_fwd_wb),
+		.rf_write_wb_i(rf_write_wb),
+		.en_wb_o(en_wb),
+		.instr_type_wb_o(instr_type_wb),
+		.instr_perf_count_id_o(instr_perf_count_id),
+		.ready_wb_i(ready_wb),
+		.outstanding_load_wb_i(outstanding_load_wb),
+		.outstanding_store_wb_i(outstanding_store_wb),
+		.perf_jump_o(perf_jump),
+		.perf_branch_o(perf_branch),
+		.perf_tbranch_o(perf_tbranch),
+		.perf_dside_wait_o(perf_dside_wait),
+		.perf_mul_wait_o(perf_mul_wait),
+		.perf_div_wait_o(perf_div_wait),
+		.instr_id_done_o(instr_id_done)
+	);
+	assign unused_illegal_insn_id = illegal_insn_id;
+	ibex_ex_block #(
+		.RV32M(RV32M),
+		.RV32B(RV32B),
+		.RV32Zk(RV32Zk),
+		.BranchTargetALU(BranchTargetALU)
+	) ex_block_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.alu_operator_i(alu_operator_ex),
+		.alu_operand_a_i(alu_operand_a_ex),
+		.alu_operand_b_i(alu_operand_b_ex),
+		.alu_instr_first_cycle_i(instr_first_cycle_id),
+		.bt_a_operand_i(bt_a_operand),
+		.bt_b_operand_i(bt_b_operand),
+		.multdiv_operator_i(multdiv_operator_ex),
+		.mult_en_i(mult_en_ex),
+		.div_en_i(div_en_ex),
+		.mult_sel_i(mult_sel_ex),
+		.div_sel_i(div_sel_ex),
+		.multdiv_signed_mode_i(multdiv_signed_mode_ex),
+		.multdiv_operand_a_i(multdiv_operand_a_ex),
+		.multdiv_operand_b_i(multdiv_operand_b_ex),
+		.multdiv_ready_id_i(multdiv_ready_id),
+		.data_ind_timing_i(data_ind_timing),
+		.imd_val_we_o(imd_val_we_ex),
+		.imd_val_d_o(imd_val_d_ex),
+		.imd_val_q_i(imd_val_q_ex),
+		.eFPGA_en_i(eFPGA_en),
+		.eFPGA_operator_i(eFPGA_operator),
+		.eFPGA_fpga_done_i(eFPGA_fpga_done_i),
+		.eFPGA_result_a_i(eFPGA_result_a_i),
+		.eFPGA_result_b_i(eFPGA_result_b_i),
+		.eFPGA_result_c_i(eFPGA_result_c_i),
+		.eFPGA_delay_i(eFPGA_delay),
+		.eFPGA_write_strobe_o(eFPGA_write_strobe_o),
+		.alu_adder_result_ex_o(alu_adder_result_ex),
+		.result_ex_o(result_ex),
+		.branch_target_o(branch_target_ex),
+		.branch_decision_o(branch_decision),
+		.ex_valid_o(ex_valid)
+	);
+	localparam [31:0] ibex_pkg_PMP_D = 1;
+	assign data_req_o = data_req_out & ~pmp_req_err[ibex_pkg_PMP_D];
+	assign lsu_resp_err = lsu_load_err | lsu_store_err;
+	ibex_load_store_unit load_store_unit_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.data_req_o(data_req_out),
+		.data_gnt_i(data_gnt_i),
+		.data_rvalid_i(data_rvalid_i),
+		.data_err_i(data_err_i),
+		.data_pmp_err_i(pmp_req_err[ibex_pkg_PMP_D]),
+		.data_addr_o(data_addr_o),
+		.data_we_o(data_we_o),
+		.data_be_o(data_be_o),
+		.data_wdata_o(data_wdata_o),
+		.data_rdata_i(data_rdata_i),
+		.lsu_we_i(lsu_we),
+		.lsu_type_i(lsu_type),
+		.lsu_wdata_i(lsu_wdata),
+		.lsu_sign_ext_i(lsu_sign_ext),
+		.lsu_rdata_o(rf_wdata_lsu),
+		.lsu_rdata_valid_o(rf_we_lsu),
+		.lsu_req_i(lsu_req),
+		.lsu_req_done_o(lsu_req_done),
+		.adder_result_ex_i(alu_adder_result_ex),
+		.addr_incr_req_o(lsu_addr_incr_req),
+		.addr_last_o(lsu_addr_last),
+		.lsu_resp_valid_o(lsu_resp_valid),
+		.load_err_o(lsu_load_err),
+		.store_err_o(lsu_store_err),
+		.busy_o(lsu_busy),
+		.perf_load_o(perf_load),
+		.perf_store_o(perf_store)
+	);
+	ibex_wb_stage #(
+		.ResetAll(ResetAll),
+		.WritebackStage(WritebackStage)
+	) wb_stage_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.en_wb_i(en_wb),
+		.instr_type_wb_i(instr_type_wb),
+		.pc_id_i(pc_id),
+		.instr_is_compressed_id_i(instr_is_compressed_id),
+		.instr_perf_count_id_i(instr_perf_count_id),
+		.ready_wb_o(ready_wb),
+		.rf_write_wb_o(rf_write_wb),
+		.outstanding_load_wb_o(outstanding_load_wb),
+		.outstanding_store_wb_o(outstanding_store_wb),
+		.pc_wb_o(pc_wb),
+		.perf_instr_ret_wb_o(perf_instr_ret_wb),
+		.perf_instr_ret_compressed_wb_o(perf_instr_ret_compressed_wb),
+		.perf_instr_ret_wb_spec_o(perf_instr_ret_wb_spec),
+		.perf_instr_ret_compressed_wb_spec_o(perf_instr_ret_compressed_wb_spec),
+		.rf_waddr_id_i(rf_waddr_id),
+		.rf_wdata_id_i(rf_wdata_id),
+		.rf_we_id_i(rf_we_id),
+		.rf_wdata_lsu_i(rf_wdata_lsu),
+		.rf_we_lsu_i(rf_we_lsu),
+		.rf_wdata_fwd_wb_o(rf_wdata_fwd_wb),
+		.rf_waddr_wb_o(rf_waddr_wb),
+		.rf_wdata_wb_o(rf_wdata_wb),
+		.rf_we_wb_o(rf_we_wb),
+		.lsu_resp_valid_i(lsu_resp_valid),
+		.lsu_resp_err_i(lsu_resp_err),
+		.instr_done_wb_o(instr_done_wb)
+	);
+	assign dummy_instr_id_o = dummy_instr_id;
+	assign rf_raddr_a_o = rf_raddr_a;
+	assign rf_waddr_wb_o = rf_waddr_wb;
+	assign rf_we_wb_o = rf_we_wb;
+	assign rf_raddr_b_o = rf_raddr_b;
+	generate
+		if (RegFileECC) begin : gen_regfile_ecc
+			wire [1:0] rf_ecc_err_a;
+			wire [1:0] rf_ecc_err_b;
+			wire rf_ecc_err_a_id;
+			wire rf_ecc_err_b_id;
+			prim_secded_39_32_enc regfile_ecc_enc(
+				.data_i(rf_wdata_wb),
+				.data_o(rf_wdata_wb_ecc_o)
+			);
+			prim_secded_39_32_dec regfile_ecc_dec_a(
+				.data_i(rf_rdata_a_ecc_i),
+				.data_o(),
+				.syndrome_o(),
+				.err_o(rf_ecc_err_a)
+			);
+			prim_secded_39_32_dec regfile_ecc_dec_b(
+				.data_i(rf_rdata_b_ecc_i),
+				.data_o(),
+				.syndrome_o(),
+				.err_o(rf_ecc_err_b)
+			);
+			assign rf_rdata_a = rf_rdata_a_ecc_i[31:0];
+			assign rf_rdata_b = rf_rdata_b_ecc_i[31:0];
+			assign rf_ecc_err_a_id = (|rf_ecc_err_a & rf_ren_a) & ~rf_rd_a_wb_match;
+			assign rf_ecc_err_b_id = (|rf_ecc_err_b & rf_ren_b) & ~rf_rd_b_wb_match;
+			assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id);
+		end
+		else begin : gen_no_regfile_ecc
+			wire unused_rf_ren_a;
+			wire unused_rf_ren_b;
+			wire unused_rf_rd_a_wb_match;
+			wire unused_rf_rd_b_wb_match;
+			assign unused_rf_ren_a = rf_ren_a;
+			assign unused_rf_ren_b = rf_ren_b;
+			assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match;
+			assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match;
+			assign rf_wdata_wb_ecc_o = rf_wdata_wb;
+			assign rf_rdata_a = rf_rdata_a_ecc_i;
+			assign rf_rdata_b = rf_rdata_b_ecc_i;
+			assign rf_ecc_err_comb = 1'b0;
+		end
+	endgenerate
+	assign crash_dump_o[127-:32] = pc_id;
+	assign crash_dump_o[95-:32] = pc_if;
+	assign crash_dump_o[63-:32] = lsu_addr_last;
+	assign crash_dump_o[31-:32] = csr_mepc;
+	assign alert_minor_o = 1'b0;
+	assign alert_major_o = (rf_ecc_err_comb | pc_mismatch_alert) | csr_shadow_err;
+	assign csr_wdata = alu_operand_a_ex;
+	function automatic [11:0] sv2v_cast_12;
+		input reg [11:0] inp;
+		sv2v_cast_12 = inp;
+	endfunction
+	assign csr_addr = sv2v_cast_12((csr_access ? alu_operand_b_ex[11:0] : 12'b000000000000));
+	ibex_cs_registers #(
+		.DbgTriggerEn(DbgTriggerEn),
+		.DbgHwBreakNum(DbgHwBreakNum),
+		.DataIndTiming(DataIndTiming),
+		.DummyInstructions(DummyInstructions),
+		.ShadowCSR(ShadowCSR),
+		.ICache(ICache),
+		.MHPMCounterNum(MHPMCounterNum),
+		.MHPMCounterWidth(MHPMCounterWidth),
+		.PMPEnable(PMPEnable),
+		.PMPGranularity(PMPGranularity),
+		.PMPNumRegions(PMPNumRegions),
+		.RV32E(RV32E),
+		.RV32M(RV32M),
+		.RV32B(RV32B),
+		.RV32Zk(RV32Zk)
+	) cs_registers_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.hart_id_i(hart_id_i),
+		.priv_mode_id_o(priv_mode_id),
+		.priv_mode_if_o(priv_mode_if),
+		.priv_mode_lsu_o(priv_mode_lsu),
+		.csr_mtvec_o(csr_mtvec),
+		.csr_mtvec_init_i(csr_mtvec_init),
+		.boot_addr_i(boot_addr_i),
+		.csr_access_i(csr_access),
+		.csr_addr_i(csr_addr),
+		.csr_wdata_i(csr_wdata),
+		.csr_op_i(csr_op),
+		.csr_op_en_i(csr_op_en),
+		.csr_rdata_o(csr_rdata),
+		.irq_software_i(irq_software_i),
+		.irq_timer_i(irq_timer_i),
+		.irq_external_i(irq_external_i),
+		.irq_fast_i(irq_fast_i),
+		.nmi_mode_i(nmi_mode),
+		.irq_pending_o(irq_pending_o),
+		.irqs_o(irqs),
+		.csr_mstatus_mie_o(csr_mstatus_mie),
+		.csr_mstatus_tw_o(csr_mstatus_tw),
+		.csr_mepc_o(csr_mepc),
+		.csr_pmp_cfg_o(csr_pmp_cfg),
+		.csr_pmp_addr_o(csr_pmp_addr),
+		.csr_pmp_mseccfg_o(csr_pmp_mseccfg),
+		.csr_depc_o(csr_depc),
+		.debug_mode_i(debug_mode),
+		.debug_cause_i(debug_cause),
+		.debug_csr_save_i(debug_csr_save),
+		.debug_single_step_o(debug_single_step),
+		.debug_ebreakm_o(debug_ebreakm),
+		.debug_ebreaku_o(debug_ebreaku),
+		.trigger_match_o(trigger_match),
+		.pc_if_i(pc_if),
+		.pc_id_i(pc_id),
+		.pc_wb_i(pc_wb),
+		.data_ind_timing_o(data_ind_timing),
+		.dummy_instr_en_o(dummy_instr_en),
+		.dummy_instr_mask_o(dummy_instr_mask),
+		.dummy_instr_seed_en_o(dummy_instr_seed_en),
+		.dummy_instr_seed_o(dummy_instr_seed),
+		.icache_enable_o(icache_enable),
+		.csr_shadow_err_o(csr_shadow_err),
+		.csr_save_if_i(csr_save_if),
+		.csr_save_id_i(csr_save_id),
+		.csr_save_wb_i(csr_save_wb),
+		.csr_restore_mret_i(csr_restore_mret_id),
+		.csr_restore_dret_i(csr_restore_dret_id),
+		.csr_save_cause_i(csr_save_cause),
+		.csr_mcause_i(exc_cause),
+		.csr_mtval_i(csr_mtval),
+		.illegal_csr_insn_o(illegal_csr_insn_id),
+		.instr_ret_i(perf_instr_ret_wb),
+		.instr_ret_compressed_i(perf_instr_ret_compressed_wb),
+		.instr_ret_spec_i(perf_instr_ret_wb_spec),
+		.instr_ret_compressed_spec_i(perf_instr_ret_compressed_wb_spec),
+		.iside_wait_i(perf_iside_wait),
+		.jump_i(perf_jump),
+		.branch_i(perf_branch),
+		.branch_taken_i(perf_tbranch),
+		.mem_load_i(perf_load),
+		.mem_store_i(perf_store),
+		.dside_wait_i(perf_dside_wait),
+		.mul_wait_i(perf_mul_wait),
+		.div_wait_i(perf_div_wait)
+	);
+	wire [1:0] unused_priv_lvl_if;
+	wire [1:0] unused_priv_lvl_ls;
+	wire [(PMPNumRegions * 34) - 1:0] unused_csr_pmp_addr;
+	wire [(PMPNumRegions * 6) - 1:0] unused_csr_pmp_cfg;
+	wire [2:0] unused_csr_pmp_mseccfg;
+	assign unused_priv_lvl_if = priv_mode_if;
+	assign unused_priv_lvl_ls = priv_mode_lsu;
+	assign unused_csr_pmp_addr = csr_pmp_addr;
+	assign unused_csr_pmp_cfg = csr_pmp_cfg;
+	assign unused_csr_pmp_mseccfg = csr_pmp_mseccfg;
+	assign pmp_req_err[ibex_pkg_PMP_I] = 1'b0;
+	assign pmp_req_err[ibex_pkg_PMP_D] = 1'b0;
+	wire unused_instr_new_id;
+	wire unused_instr_id_done;
+	wire unused_instr_done_wb;
+	assign unused_instr_id_done = instr_id_done;
+	assign unused_instr_new_id = instr_new_id;
+	assign unused_instr_done_wb = instr_done_wb;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_counter.v b/verilog/rtl/ibex_core/ibex_counter.v
new file mode 100644
index 0000000..159d735
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_counter.v
@@ -0,0 +1,73 @@
+module ibex_counter (
+	clk_i,
+	rst_ni,
+	counter_inc_i,
+	counterh_we_i,
+	counter_we_i,
+	counter_val_i,
+	counter_val_o,
+	counter_val_upd_o
+);
+	parameter signed [31:0] CounterWidth = 32;
+	parameter [0:0] ProvideValUpd = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire counter_inc_i;
+	input wire counterh_we_i;
+	input wire counter_we_i;
+	input wire [31:0] counter_val_i;
+	output wire [63:0] counter_val_o;
+	output wire [63:0] counter_val_upd_o;
+	wire [63:0] counter;
+	wire [CounterWidth - 1:0] counter_upd;
+	reg [63:0] counter_load;
+	reg we;
+	reg [CounterWidth - 1:0] counter_d;
+	assign counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1};
+	always @(*) begin
+		we = counter_we_i | counterh_we_i;
+		counter_load[63:32] = counter[63:32];
+		counter_load[31:0] = counter_val_i;
+		if (counterh_we_i) begin
+			counter_load[63:32] = counter_val_i;
+			counter_load[31:0] = counter[31:0];
+		end
+		if (we)
+			counter_d = counter_load[CounterWidth - 1:0];
+		else if (counter_inc_i)
+			counter_d = counter_upd[CounterWidth - 1:0];
+		else
+			counter_d = counter[CounterWidth - 1:0];
+	end
+	reg [CounterWidth - 1:0] counter_q;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			counter_q <= 1'sb0;
+		else
+			counter_q <= counter_d;
+	generate
+		if (CounterWidth < 64) begin : g_counter_narrow
+			wire [63:CounterWidth] unused_counter_load;
+			assign counter[CounterWidth - 1:0] = counter_q;
+			assign counter[63:CounterWidth] = 1'sb0;
+			if (ProvideValUpd) begin : g_counter_val_upd_o
+				assign counter_val_upd_o[CounterWidth - 1:0] = counter_upd;
+			end
+			else begin : g_no_counter_val_upd_o
+				assign counter_val_upd_o[CounterWidth - 1:0] = 1'sb0;
+			end
+			assign counter_val_upd_o[63:CounterWidth] = 1'sb0;
+			assign unused_counter_load = counter_load[63:CounterWidth];
+		end
+		else begin : g_counter_full
+			assign counter = counter_q;
+			if (ProvideValUpd) begin : g_counter_val_upd_o
+				assign counter_val_upd_o = counter_upd;
+			end
+			else begin : g_no_counter_val_upd_o
+				assign counter_val_upd_o = 1'sb0;
+			end
+		end
+	endgenerate
+	assign counter_val_o = counter;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_cs_registers.v b/verilog/rtl/ibex_core/ibex_cs_registers.v
new file mode 100644
index 0000000..3135d7a
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_cs_registers.v
@@ -0,0 +1,1146 @@
+module ibex_cs_registers (
+	clk_i,
+	rst_ni,
+	hart_id_i,
+	priv_mode_id_o,
+	priv_mode_if_o,
+	priv_mode_lsu_o,
+	csr_mstatus_tw_o,
+	csr_mtvec_o,
+	csr_mtvec_init_i,
+	boot_addr_i,
+	csr_access_i,
+	csr_addr_i,
+	csr_wdata_i,
+	csr_op_i,
+	csr_op_en_i,
+	csr_rdata_o,
+	irq_software_i,
+	irq_timer_i,
+	irq_external_i,
+	irq_fast_i,
+	nmi_mode_i,
+	irq_pending_o,
+	irqs_o,
+	csr_mstatus_mie_o,
+	csr_mepc_o,
+	csr_pmp_cfg_o,
+	csr_pmp_addr_o,
+	csr_pmp_mseccfg_o,
+	debug_mode_i,
+	debug_cause_i,
+	debug_csr_save_i,
+	csr_depc_o,
+	debug_single_step_o,
+	debug_ebreakm_o,
+	debug_ebreaku_o,
+	trigger_match_o,
+	pc_if_i,
+	pc_id_i,
+	pc_wb_i,
+	data_ind_timing_o,
+	dummy_instr_en_o,
+	dummy_instr_mask_o,
+	dummy_instr_seed_en_o,
+	dummy_instr_seed_o,
+	icache_enable_o,
+	csr_shadow_err_o,
+	csr_save_if_i,
+	csr_save_id_i,
+	csr_save_wb_i,
+	csr_restore_mret_i,
+	csr_restore_dret_i,
+	csr_save_cause_i,
+	csr_mcause_i,
+	csr_mtval_i,
+	illegal_csr_insn_o,
+	instr_ret_i,
+	instr_ret_compressed_i,
+	instr_ret_spec_i,
+	instr_ret_compressed_spec_i,
+	iside_wait_i,
+	jump_i,
+	branch_i,
+	branch_taken_i,
+	mem_load_i,
+	mem_store_i,
+	dside_wait_i,
+	mul_wait_i,
+	div_wait_i
+);
+	parameter [0:0] DbgTriggerEn = 0;
+	parameter [31:0] DbgHwBreakNum = 1;
+	parameter [0:0] DataIndTiming = 1'b0;
+	parameter [0:0] DummyInstructions = 1'b0;
+	parameter [0:0] ShadowCSR = 1'b0;
+	parameter [0:0] ICache = 1'b0;
+	parameter [31:0] MHPMCounterNum = 10;
+	parameter [31:0] MHPMCounterWidth = 40;
+	parameter [0:0] PMPEnable = 0;
+	parameter [31:0] PMPGranularity = 0;
+	parameter [31:0] PMPNumRegions = 4;
+	parameter [0:0] RV32E = 0;
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [31:0] hart_id_i;
+	output wire [1:0] priv_mode_id_o;
+	output wire [1:0] priv_mode_if_o;
+	output wire [1:0] priv_mode_lsu_o;
+	output wire csr_mstatus_tw_o;
+	output wire [31:0] csr_mtvec_o;
+	input wire csr_mtvec_init_i;
+	input wire [31:0] boot_addr_i;
+	input wire csr_access_i;
+	input wire [11:0] csr_addr_i;
+	input wire [31:0] csr_wdata_i;
+	input wire [1:0] csr_op_i;
+	input csr_op_en_i;
+	output wire [31:0] csr_rdata_o;
+	input wire irq_software_i;
+	input wire irq_timer_i;
+	input wire irq_external_i;
+	input wire [14:0] irq_fast_i;
+	input wire nmi_mode_i;
+	output wire irq_pending_o;
+	output wire [17:0] irqs_o;
+	output wire csr_mstatus_mie_o;
+	output wire [31:0] csr_mepc_o;
+	output wire [(PMPNumRegions * 6) - 1:0] csr_pmp_cfg_o;
+	output wire [(PMPNumRegions * 34) - 1:0] csr_pmp_addr_o;
+	output wire [2:0] csr_pmp_mseccfg_o;
+	input wire debug_mode_i;
+	input wire [2:0] debug_cause_i;
+	input wire debug_csr_save_i;
+	output wire [31:0] csr_depc_o;
+	output wire debug_single_step_o;
+	output wire debug_ebreakm_o;
+	output wire debug_ebreaku_o;
+	output wire trigger_match_o;
+	input wire [31:0] pc_if_i;
+	input wire [31:0] pc_id_i;
+	input wire [31:0] pc_wb_i;
+	output wire data_ind_timing_o;
+	output wire dummy_instr_en_o;
+	output wire [2:0] dummy_instr_mask_o;
+	output wire dummy_instr_seed_en_o;
+	output wire [31:0] dummy_instr_seed_o;
+	output wire icache_enable_o;
+	output wire csr_shadow_err_o;
+	input wire csr_save_if_i;
+	input wire csr_save_id_i;
+	input wire csr_save_wb_i;
+	input wire csr_restore_mret_i;
+	input wire csr_restore_dret_i;
+	input wire csr_save_cause_i;
+	input wire [5:0] csr_mcause_i;
+	input wire [31:0] csr_mtval_i;
+	output wire illegal_csr_insn_o;
+	input wire instr_ret_i;
+	input wire instr_ret_compressed_i;
+	input wire instr_ret_spec_i;
+	input wire instr_ret_compressed_spec_i;
+	input wire iside_wait_i;
+	input wire jump_i;
+	input wire branch_i;
+	input wire branch_taken_i;
+	input wire mem_load_i;
+	input wire mem_store_i;
+	input wire dside_wait_i;
+	input wire mul_wait_i;
+	input wire div_wait_i;
+	localparam [31:0] RV32BEnabled = (RV32B == 32'sd0 ? 0 : 1);
+	localparam [31:0] RV32MEnabled = (RV32M == 32'sd0 ? 0 : 1);
+	localparam [31:0] PMPAddrWidth = (PMPGranularity > 0 ? 33 - PMPGranularity : 32);
+	localparam [1:0] ibex_pkg_CSR_MISA_MXL = 2'd1;
+	function automatic [31:0] sv2v_cast_32;
+		input reg [31:0] inp;
+		sv2v_cast_32 = inp;
+	endfunction
+	localparam [31:0] MISA_VALUE = (((((((((((0 | (RV32BEnabled << 1)) | 4) | 0) | (sv2v_cast_32(RV32E) << 4)) | 0) | (sv2v_cast_32(!RV32E) << 8)) | (RV32MEnabled << 12)) | 0) | 0) | 1048576) | 0) | (sv2v_cast_32(ibex_pkg_CSR_MISA_MXL) << 30);
+	reg [31:0] exception_pc;
+	reg [1:0] priv_lvl_q;
+	reg [1:0] priv_lvl_d;
+	wire [5:0] mstatus_q;
+	reg [5:0] mstatus_d;
+	wire mstatus_err;
+	reg mstatus_en;
+	wire [17:0] mie_q;
+	wire [17:0] mie_d;
+	reg mie_en;
+	wire [31:0] mscratch_q;
+	reg mscratch_en;
+	wire [31:0] mepc_q;
+	reg [31:0] mepc_d;
+	reg mepc_en;
+	wire [5:0] mcause_q;
+	reg [5:0] mcause_d;
+	reg mcause_en;
+	wire [31:0] mtval_q;
+	reg [31:0] mtval_d;
+	reg mtval_en;
+	wire [31:0] mtvec_q;
+	reg [31:0] mtvec_d;
+	wire mtvec_err;
+	reg mtvec_en;
+	wire [17:0] mip;
+	wire [31:0] dcsr_q;
+	reg [31:0] dcsr_d;
+	reg dcsr_en;
+	wire [31:0] depc_q;
+	reg [31:0] depc_d;
+	reg depc_en;
+	wire [31:0] dscratch0_q;
+	wire [31:0] dscratch1_q;
+	reg dscratch0_en;
+	reg dscratch1_en;
+	wire [2:0] mstack_q;
+	reg [2:0] mstack_d;
+	reg mstack_en;
+	wire [31:0] mstack_epc_q;
+	reg [31:0] mstack_epc_d;
+	wire [5:0] mstack_cause_q;
+	reg [5:0] mstack_cause_d;
+	localparam [31:0] ibex_pkg_PMP_MAX_REGIONS = 16;
+	reg [31:0] pmp_addr_rdata [0:15];
+	localparam [31:0] ibex_pkg_PMP_CFG_W = 8;
+	wire [7:0] pmp_cfg_rdata [0:15];
+	wire pmp_csr_err;
+	wire [2:0] pmp_mseccfg;
+	wire [31:0] mcountinhibit;
+	reg [MHPMCounterNum + 2:0] mcountinhibit_d;
+	reg [MHPMCounterNum + 2:0] mcountinhibit_q;
+	reg mcountinhibit_we;
+	wire [63:0] mhpmcounter [0:31];
+	reg [31:0] mhpmcounter_we;
+	reg [31:0] mhpmcounterh_we;
+	reg [31:0] mhpmcounter_incr;
+	reg [31:0] mhpmevent [0:31];
+	wire [4:0] mhpmcounter_idx;
+	wire unused_mhpmcounter_we_1;
+	wire unused_mhpmcounterh_we_1;
+	wire unused_mhpmcounter_incr_1;
+	wire [63:0] minstret_next;
+	wire [63:0] minstret_raw;
+	wire [31:0] tselect_rdata;
+	wire [31:0] tmatch_control_rdata;
+	wire [31:0] tmatch_value_rdata;
+	wire [5:0] cpuctrl_q;
+	wire [5:0] cpuctrl_d;
+	wire [5:0] cpuctrl_wdata;
+	reg cpuctrl_we;
+	wire cpuctrl_err;
+	reg [31:0] csr_wdata_int;
+	reg [31:0] csr_rdata_int;
+	wire csr_we_int;
+	wire csr_wr;
+	reg illegal_csr;
+	wire illegal_csr_priv;
+	wire illegal_csr_write;
+	wire [7:0] unused_boot_addr;
+	wire [2:0] unused_csr_addr;
+	assign unused_boot_addr = boot_addr_i[7:0];
+	wire [11:0] csr_addr;
+	assign csr_addr = {csr_addr_i};
+	assign unused_csr_addr = csr_addr[7:5];
+	assign mhpmcounter_idx = csr_addr[4:0];
+	assign illegal_csr_priv = csr_addr[9:8] > {priv_lvl_q};
+	assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wr;
+	assign illegal_csr_insn_o = csr_access_i & ((illegal_csr | illegal_csr_write) | illegal_csr_priv);
+	assign mip[17] = irq_software_i;
+	assign mip[16] = irq_timer_i;
+	assign mip[15] = irq_external_i;
+	assign mip[14-:15] = irq_fast_i;
+	localparam [31:0] ibex_pkg_CSR_MARCHID_VALUE = 32'b00000000000000000000000000010110;
+	localparam [31:0] ibex_pkg_CSR_MEIX_BIT = 11;
+	localparam [31:0] ibex_pkg_CSR_MFIX_BIT_HIGH = 30;
+	localparam [31:0] ibex_pkg_CSR_MFIX_BIT_LOW = 16;
+	localparam [31:0] ibex_pkg_CSR_MIMPID_VALUE = 32'b00000000000000000000000000000000;
+	localparam [31:0] ibex_pkg_CSR_MSECCFG_MML_BIT = 0;
+	localparam [31:0] ibex_pkg_CSR_MSECCFG_MMWP_BIT = 1;
+	localparam [31:0] ibex_pkg_CSR_MSECCFG_RLB_BIT = 2;
+	localparam [31:0] ibex_pkg_CSR_MSIX_BIT = 3;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_MIE_BIT = 3;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_MPIE_BIT = 7;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH = 12;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW = 11;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_MPRV_BIT = 17;
+	localparam [31:0] ibex_pkg_CSR_MSTATUS_TW_BIT = 21;
+	localparam [31:0] ibex_pkg_CSR_MTIX_BIT = 7;
+	localparam [31:0] ibex_pkg_CSR_MVENDORID_VALUE = 32'b00000000000000000000000000000000;
+	always @(*) begin
+		csr_rdata_int = 1'sb0;
+		illegal_csr = 1'b0;
+		case (csr_addr_i)
+			12'hf11: csr_rdata_int = ibex_pkg_CSR_MVENDORID_VALUE;
+			12'hf12: csr_rdata_int = ibex_pkg_CSR_MARCHID_VALUE;
+			12'hf13: csr_rdata_int = ibex_pkg_CSR_MIMPID_VALUE;
+			12'hf14: csr_rdata_int = hart_id_i;
+			12'h015:
+				if (RV32Zk == 32'sd2) begin
+					if (csr_op_i == 2'd1)
+						csr_rdata_int = 32'hffffdead;
+					else
+						illegal_csr = 1'b1;
+				end
+				else
+					illegal_csr = 1'b1;
+			12'h300: begin
+				csr_rdata_int = 1'sb0;
+				csr_rdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT] = mstatus_q[5];
+				csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT] = mstatus_q[4];
+				csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q[3-:2];
+				csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT] = mstatus_q[1];
+				csr_rdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT] = mstatus_q[0];
+			end
+			12'h301: csr_rdata_int = MISA_VALUE;
+			12'h304: begin
+				csr_rdata_int = 1'sb0;
+				csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mie_q[17];
+				csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mie_q[16];
+				csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mie_q[15];
+				csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mie_q[14-:15];
+			end
+			12'h306: csr_rdata_int = 1'sb0;
+			12'h340: csr_rdata_int = mscratch_q;
+			12'h305: csr_rdata_int = mtvec_q;
+			12'h341: csr_rdata_int = mepc_q;
+			12'h342: csr_rdata_int = {mcause_q[5], 26'b00000000000000000000000000, mcause_q[4:0]};
+			12'h343: csr_rdata_int = mtval_q;
+			12'h344: begin
+				csr_rdata_int = 1'sb0;
+				csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mip[17];
+				csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mip[16];
+				csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mip[15];
+				csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mip[14-:15];
+			end
+			12'h747:
+				if (PMPEnable) begin
+					csr_rdata_int = 1'sb0;
+					csr_rdata_int[ibex_pkg_CSR_MSECCFG_MML_BIT] = pmp_mseccfg[0];
+					csr_rdata_int[ibex_pkg_CSR_MSECCFG_MMWP_BIT] = pmp_mseccfg[1];
+					csr_rdata_int[ibex_pkg_CSR_MSECCFG_RLB_BIT] = pmp_mseccfg[2];
+				end
+				else
+					illegal_csr = 1'b1;
+			12'h757:
+				if (PMPEnable)
+					csr_rdata_int = 1'sb0;
+				else
+					illegal_csr = 1'b1;
+			12'h3a0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], pmp_cfg_rdata[1], pmp_cfg_rdata[0]};
+			12'h3a1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], pmp_cfg_rdata[5], pmp_cfg_rdata[4]};
+			12'h3a2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], pmp_cfg_rdata[9], pmp_cfg_rdata[8]};
+			12'h3a3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], pmp_cfg_rdata[13], pmp_cfg_rdata[12]};
+			12'h3b0: csr_rdata_int = pmp_addr_rdata[0];
+			12'h3b1: csr_rdata_int = pmp_addr_rdata[1];
+			12'h3b2: csr_rdata_int = pmp_addr_rdata[2];
+			12'h3b3: csr_rdata_int = pmp_addr_rdata[3];
+			12'h3b4: csr_rdata_int = pmp_addr_rdata[4];
+			12'h3b5: csr_rdata_int = pmp_addr_rdata[5];
+			12'h3b6: csr_rdata_int = pmp_addr_rdata[6];
+			12'h3b7: csr_rdata_int = pmp_addr_rdata[7];
+			12'h3b8: csr_rdata_int = pmp_addr_rdata[8];
+			12'h3b9: csr_rdata_int = pmp_addr_rdata[9];
+			12'h3ba: csr_rdata_int = pmp_addr_rdata[10];
+			12'h3bb: csr_rdata_int = pmp_addr_rdata[11];
+			12'h3bc: csr_rdata_int = pmp_addr_rdata[12];
+			12'h3bd: csr_rdata_int = pmp_addr_rdata[13];
+			12'h3be: csr_rdata_int = pmp_addr_rdata[14];
+			12'h3bf: csr_rdata_int = pmp_addr_rdata[15];
+			12'h7b0: begin
+				csr_rdata_int = dcsr_q;
+				illegal_csr = ~debug_mode_i;
+			end
+			12'h7b1: begin
+				csr_rdata_int = depc_q;
+				illegal_csr = ~debug_mode_i;
+			end
+			12'h7b2: begin
+				csr_rdata_int = dscratch0_q;
+				illegal_csr = ~debug_mode_i;
+			end
+			12'h7b3: begin
+				csr_rdata_int = dscratch1_q;
+				illegal_csr = ~debug_mode_i;
+			end
+			12'h320: csr_rdata_int = mcountinhibit;
+			12'h323, 12'h324, 12'h325, 12'h326, 12'h327, 12'h328, 12'h329, 12'h32a, 12'h32b, 12'h32c, 12'h32d, 12'h32e, 12'h32f, 12'h330, 12'h331, 12'h332, 12'h333, 12'h334, 12'h335, 12'h336, 12'h337, 12'h338, 12'h339, 12'h33a, 12'h33b, 12'h33c, 12'h33d, 12'h33e, 12'h33f: csr_rdata_int = mhpmevent[mhpmcounter_idx];
+			12'hb00, 12'hb02, 12'hb03, 12'hb04, 12'hb05, 12'hb06, 12'hb07, 12'hb08, 12'hb09, 12'hb0a, 12'hb0b, 12'hb0c, 12'hb0d, 12'hb0e, 12'hb0f, 12'hb10, 12'hb11, 12'hb12, 12'hb13, 12'hb14, 12'hb15, 12'hb16, 12'hb17, 12'hb18, 12'hb19, 12'hb1a, 12'hb1b, 12'hb1c, 12'hb1d, 12'hb1e, 12'hb1f: csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0];
+			12'hb80, 12'hb82, 12'hb83, 12'hb84, 12'hb85, 12'hb86, 12'hb87, 12'hb88, 12'hb89, 12'hb8a, 12'hb8b, 12'hb8c, 12'hb8d, 12'hb8e, 12'hb8f, 12'hb90, 12'hb91, 12'hb92, 12'hb93, 12'hb94, 12'hb95, 12'hb96, 12'hb97, 12'hb98, 12'hb99, 12'hb9a, 12'hb9b, 12'hb9c, 12'hb9d, 12'hb9e, 12'hb9f: csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32];
+			12'h7a0: begin
+				csr_rdata_int = tselect_rdata;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7a1: begin
+				csr_rdata_int = tmatch_control_rdata;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7a2: begin
+				csr_rdata_int = tmatch_value_rdata;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7a3: begin
+				csr_rdata_int = 1'sb0;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7a8: begin
+				csr_rdata_int = 1'sb0;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7aa: begin
+				csr_rdata_int = 1'sb0;
+				illegal_csr = ~DbgTriggerEn;
+			end
+			12'h7c0: csr_rdata_int = {{26 {1'b0}}, cpuctrl_q};
+			12'h7c1: csr_rdata_int = 1'sb0;
+			default: illegal_csr = 1'b1;
+		endcase
+	end
+	function automatic [1:0] sv2v_cast_2;
+		input reg [1:0] inp;
+		sv2v_cast_2 = inp;
+	endfunction
+	always @(*) begin
+		exception_pc = pc_id_i;
+		priv_lvl_d = priv_lvl_q;
+		mstatus_en = 1'b0;
+		mstatus_d = mstatus_q;
+		mie_en = 1'b0;
+		mscratch_en = 1'b0;
+		mepc_en = 1'b0;
+		mepc_d = {csr_wdata_int[31:1], 1'b0};
+		mcause_en = 1'b0;
+		mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
+		mtval_en = 1'b0;
+		mtval_d = csr_wdata_int;
+		mtvec_en = csr_mtvec_init_i;
+		mtvec_d = (csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b000000, 2'b01} : {csr_wdata_int[31:8], 6'b000000, 2'b01});
+		dcsr_en = 1'b0;
+		dcsr_d = dcsr_q;
+		depc_d = {csr_wdata_int[31:1], 1'b0};
+		depc_en = 1'b0;
+		dscratch0_en = 1'b0;
+		dscratch1_en = 1'b0;
+		mstack_en = 1'b0;
+		mstack_d[2] = mstatus_q[4];
+		mstack_d[1-:2] = mstatus_q[3-:2];
+		mstack_epc_d = mepc_q;
+		mstack_cause_d = mcause_q;
+		mcountinhibit_we = 1'b0;
+		mhpmcounter_we = 1'sb0;
+		mhpmcounterh_we = 1'sb0;
+		cpuctrl_we = 1'b0;
+		if (csr_we_int)
+			case (csr_addr_i)
+				12'h300: begin
+					mstatus_en = 1'b1;
+					mstatus_d = {csr_wdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT], sv2v_cast_2(csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW]), csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT]};
+					if ((mstatus_d[3-:2] != 2'b11) && (mstatus_d[3-:2] != 2'b00))
+						mstatus_d[3-:2] = 2'b11;
+				end
+				12'h304: mie_en = 1'b1;
+				12'h340: mscratch_en = 1'b1;
+				12'h341: mepc_en = 1'b1;
+				12'h342: mcause_en = 1'b1;
+				12'h343: mtval_en = 1'b1;
+				12'h305: mtvec_en = 1'b1;
+				12'h7b0: begin
+					dcsr_d = csr_wdata_int;
+					dcsr_d[31-:4] = 4'd4;
+					if ((dcsr_d[1-:2] != 2'b11) && (dcsr_d[1-:2] != 2'b00))
+						dcsr_d[1-:2] = 2'b11;
+					dcsr_d[8-:3] = dcsr_q[8-:3];
+					dcsr_d[11] = 1'b0;
+					dcsr_d[3] = 1'b0;
+					dcsr_d[4] = 1'b0;
+					dcsr_d[10] = 1'b0;
+					dcsr_d[9] = 1'b0;
+					dcsr_d[5] = 1'b0;
+					dcsr_d[14] = 1'b0;
+					dcsr_d[27-:12] = 12'h000;
+					dcsr_en = 1'b1;
+				end
+				12'h7b1: depc_en = 1'b1;
+				12'h7b2: dscratch0_en = 1'b1;
+				12'h7b3: dscratch1_en = 1'b1;
+				12'h320: mcountinhibit_we = 1'b1;
+				12'hb00, 12'hb02, 12'hb03, 12'hb04, 12'hb05, 12'hb06, 12'hb07, 12'hb08, 12'hb09, 12'hb0a, 12'hb0b, 12'hb0c, 12'hb0d, 12'hb0e, 12'hb0f, 12'hb10, 12'hb11, 12'hb12, 12'hb13, 12'hb14, 12'hb15, 12'hb16, 12'hb17, 12'hb18, 12'hb19, 12'hb1a, 12'hb1b, 12'hb1c, 12'hb1d, 12'hb1e, 12'hb1f: mhpmcounter_we[mhpmcounter_idx] = 1'b1;
+				12'hb80, 12'hb82, 12'hb83, 12'hb84, 12'hb85, 12'hb86, 12'hb87, 12'hb88, 12'hb89, 12'hb8a, 12'hb8b, 12'hb8c, 12'hb8d, 12'hb8e, 12'hb8f, 12'hb90, 12'hb91, 12'hb92, 12'hb93, 12'hb94, 12'hb95, 12'hb96, 12'hb97, 12'hb98, 12'hb99, 12'hb9a, 12'hb9b, 12'hb9c, 12'hb9d, 12'hb9e, 12'hb9f: mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
+				12'h7c0: cpuctrl_we = 1'b1;
+				default:
+					;
+			endcase
+		case (1'b1)
+			csr_save_cause_i: begin
+				case (1'b1)
+					csr_save_if_i: exception_pc = pc_if_i;
+					csr_save_id_i: exception_pc = pc_id_i;
+					csr_save_wb_i: exception_pc = pc_wb_i;
+					default:
+						;
+				endcase
+				priv_lvl_d = 2'b11;
+				if (debug_csr_save_i) begin
+					dcsr_d[1-:2] = priv_lvl_q;
+					dcsr_d[8-:3] = debug_cause_i;
+					dcsr_en = 1'b1;
+					depc_d = exception_pc;
+					depc_en = 1'b1;
+				end
+				else if (!debug_mode_i) begin
+					mtval_en = 1'b1;
+					mtval_d = csr_mtval_i;
+					mstatus_en = 1'b1;
+					mstatus_d[5] = 1'b0;
+					mstatus_d[4] = mstatus_q[5];
+					mstatus_d[3-:2] = priv_lvl_q;
+					mepc_en = 1'b1;
+					mepc_d = exception_pc;
+					mcause_en = 1'b1;
+					mcause_d = {csr_mcause_i};
+					mstack_en = 1'b1;
+				end
+			end
+			csr_restore_dret_i: priv_lvl_d = dcsr_q[1-:2];
+			csr_restore_mret_i: begin
+				priv_lvl_d = mstatus_q[3-:2];
+				mstatus_en = 1'b1;
+				mstatus_d[5] = mstatus_q[4];
+				if (nmi_mode_i) begin
+					mstatus_d[4] = mstack_q[2];
+					mstatus_d[3-:2] = mstack_q[1-:2];
+					mepc_en = 1'b1;
+					mepc_d = mstack_epc_q;
+					mcause_en = 1'b1;
+					mcause_d = mstack_cause_q;
+				end
+				else begin
+					mstatus_d[4] = 1'b1;
+					mstatus_d[3-:2] = 2'b00;
+				end
+			end
+			default:
+				;
+		endcase
+	end
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			priv_lvl_q <= 2'b11;
+		else
+			priv_lvl_q <= priv_lvl_d;
+	assign priv_mode_id_o = priv_lvl_q;
+	assign priv_mode_if_o = priv_lvl_d;
+	assign priv_mode_lsu_o = (mstatus_q[1] ? mstatus_q[3-:2] : priv_lvl_q);
+	always @(*)
+		case (csr_op_i)
+			2'd1: csr_wdata_int = csr_wdata_i;
+			2'd2: csr_wdata_int = csr_wdata_i | csr_rdata_o;
+			2'd3: csr_wdata_int = ~csr_wdata_i & csr_rdata_o;
+			2'd0: csr_wdata_int = csr_wdata_i;
+			default: csr_wdata_int = csr_wdata_i;
+		endcase
+	assign csr_wr = |{csr_op_i == 2'd1, csr_op_i == 2'd2, csr_op_i == 2'd3};
+	assign csr_we_int = (csr_wr & csr_op_en_i) & ~illegal_csr_insn_o;
+	assign csr_rdata_o = csr_rdata_int;
+	assign csr_mepc_o = mepc_q;
+	assign csr_depc_o = depc_q;
+	assign csr_mtvec_o = mtvec_q;
+	assign csr_mstatus_mie_o = mstatus_q[5];
+	assign csr_mstatus_tw_o = mstatus_q[0];
+	assign debug_single_step_o = dcsr_q[2];
+	assign debug_ebreakm_o = dcsr_q[15];
+	assign debug_ebreaku_o = dcsr_q[12];
+	assign irqs_o = mip & mie_q;
+	assign irq_pending_o = |irqs_o;
+	localparam [5:0] MSTATUS_RST_VAL = 6'b010000;
+	ibex_csr #(
+		.Width(6),
+		.ShadowCopy(ShadowCSR),
+		.ResetValue({MSTATUS_RST_VAL})
+	) u_mstatus_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i({mstatus_d}),
+		.wr_en_i(mstatus_en),
+		.rd_data_o(mstatus_q),
+		.rd_error_o(mstatus_err)
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mepc_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mepc_d),
+		.wr_en_i(mepc_en),
+		.rd_data_o(mepc_q),
+		.rd_error_o()
+	);
+	assign mie_d[17] = csr_wdata_int[ibex_pkg_CSR_MSIX_BIT];
+	assign mie_d[16] = csr_wdata_int[ibex_pkg_CSR_MTIX_BIT];
+	assign mie_d[15] = csr_wdata_int[ibex_pkg_CSR_MEIX_BIT];
+	assign mie_d[14-:15] = csr_wdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW];
+	ibex_csr #(
+		.Width(18),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mie_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i({mie_d}),
+		.wr_en_i(mie_en),
+		.rd_data_o(mie_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mscratch_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(csr_wdata_int),
+		.wr_en_i(mscratch_en),
+		.rd_data_o(mscratch_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(6),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mcause_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mcause_d),
+		.wr_en_i(mcause_en),
+		.rd_data_o(mcause_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mtval_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mtval_d),
+		.wr_en_i(mtval_en),
+		.rd_data_o(mtval_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(ShadowCSR),
+		.ResetValue(32'd1)
+	) u_mtvec_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mtvec_d),
+		.wr_en_i(mtvec_en),
+		.rd_data_o(mtvec_q),
+		.rd_error_o(mtvec_err)
+	);
+	localparam [31:0] DCSR_RESET_VAL = 32'b01000000000000000000000000000011;
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue({DCSR_RESET_VAL})
+	) u_dcsr_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i({dcsr_d}),
+		.wr_en_i(dcsr_en),
+		.rd_data_o(dcsr_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_depc_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(depc_d),
+		.wr_en_i(depc_en),
+		.rd_data_o(depc_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_dscratch0_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(csr_wdata_int),
+		.wr_en_i(dscratch0_en),
+		.rd_data_o(dscratch0_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_dscratch1_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(csr_wdata_int),
+		.wr_en_i(dscratch1_en),
+		.rd_data_o(dscratch1_q),
+		.rd_error_o()
+	);
+	localparam [2:0] MSTACK_RESET_VAL = 3'b100;
+	ibex_csr #(
+		.Width(3),
+		.ShadowCopy(1'b0),
+		.ResetValue({MSTACK_RESET_VAL})
+	) u_mstack_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i({mstack_d}),
+		.wr_en_i(mstack_en),
+		.rd_data_o(mstack_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(32),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mstack_epc_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mstack_epc_d),
+		.wr_en_i(mstack_en),
+		.rd_data_o(mstack_epc_q),
+		.rd_error_o()
+	);
+	ibex_csr #(
+		.Width(6),
+		.ShadowCopy(1'b0),
+		.ResetValue(1'sb0)
+	) u_mstack_cause_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i(mstack_cause_d),
+		.wr_en_i(mstack_en),
+		.rd_data_o(mstack_cause_q),
+		.rd_error_o()
+	);
+	localparam [11:0] ibex_pkg_CSR_OFF_PMP_ADDR = 12'h3b0;
+	localparam [11:0] ibex_pkg_CSR_OFF_PMP_CFG = 12'h3a0;
+	generate
+		if (PMPEnable) begin : g_pmp_registers
+			wire [2:0] pmp_mseccfg_q;
+			wire [2:0] pmp_mseccfg_d;
+			wire pmp_mseccfg_we;
+			wire pmp_mseccfg_err;
+			wire [5:0] pmp_cfg [0:PMPNumRegions - 1];
+			wire [PMPNumRegions - 1:0] pmp_cfg_locked;
+			reg [5:0] pmp_cfg_wdata [0:PMPNumRegions - 1];
+			wire [PMPAddrWidth - 1:0] pmp_addr [0:PMPNumRegions - 1];
+			wire [PMPNumRegions - 1:0] pmp_cfg_we;
+			wire [PMPNumRegions - 1:0] pmp_cfg_err;
+			wire [PMPNumRegions - 1:0] pmp_addr_we;
+			wire [PMPNumRegions - 1:0] pmp_addr_err;
+			wire any_pmp_entry_locked;
+			genvar i;
+			for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_exp_rd_data
+				if (i < PMPNumRegions) begin : g_implemented_regions
+					assign pmp_cfg_rdata[i] = {pmp_cfg[i][5], 2'b00, pmp_cfg[i][4-:2], pmp_cfg[i][2], pmp_cfg[i][1], pmp_cfg[i][0]};
+					if (PMPGranularity == 0) begin : g_pmp_g0
+						wire [32:1] sv2v_tmp_646D9;
+						assign sv2v_tmp_646D9 = pmp_addr[i];
+						always @(*) pmp_addr_rdata[i] = sv2v_tmp_646D9;
+					end
+					else if (PMPGranularity == 1) begin : g_pmp_g1
+						always @(*) begin
+							pmp_addr_rdata[i] = pmp_addr[i];
+							if ((pmp_cfg[i][4-:2] == 2'b00) || (pmp_cfg[i][4-:2] == 2'b01))
+								pmp_addr_rdata[i][PMPGranularity - 1:0] = 1'sb0;
+						end
+					end
+					else begin : g_pmp_g2
+						always @(*) begin
+							pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity - 1 {1'b1}}};
+							if ((pmp_cfg[i][4-:2] == 2'b00) || (pmp_cfg[i][4-:2] == 2'b01))
+								pmp_addr_rdata[i][PMPGranularity - 1:0] = 1'sb0;
+						end
+					end
+				end
+				else begin : g_other_regions
+					assign pmp_cfg_rdata[i] = 1'sb0;
+					wire [32:1] sv2v_tmp_96282;
+					assign sv2v_tmp_96282 = 1'sb0;
+					always @(*) pmp_addr_rdata[i] = sv2v_tmp_96282;
+				end
+			end
+			for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_pmp_csrs
+				assign pmp_cfg_we[i] = (csr_we_int & ~pmp_cfg_locked[i]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_CFG + (i[11:0] >> 2)));
+				wire [1:1] sv2v_tmp_43D04;
+				assign sv2v_tmp_43D04 = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 7];
+				always @(*) pmp_cfg_wdata[i][5] = sv2v_tmp_43D04;
+				always @(*)
+					case (csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 3+:2])
+						2'b00: pmp_cfg_wdata[i][4-:2] = 2'b00;
+						2'b01: pmp_cfg_wdata[i][4-:2] = 2'b01;
+						2'b10: pmp_cfg_wdata[i][4-:2] = (PMPGranularity == 0 ? 2'b10 : 2'b00);
+						2'b11: pmp_cfg_wdata[i][4-:2] = 2'b11;
+						default: pmp_cfg_wdata[i][4-:2] = 2'b00;
+					endcase
+				wire [1:1] sv2v_tmp_B5F8A;
+				assign sv2v_tmp_B5F8A = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 2];
+				always @(*) pmp_cfg_wdata[i][2] = sv2v_tmp_B5F8A;
+				wire [1:1] sv2v_tmp_DA81D;
+				assign sv2v_tmp_DA81D = (pmp_mseccfg_q[0] ? csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 1] : &csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W+:2]);
+				always @(*) pmp_cfg_wdata[i][1] = sv2v_tmp_DA81D;
+				wire [1:1] sv2v_tmp_92290;
+				assign sv2v_tmp_92290 = csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W];
+				always @(*) pmp_cfg_wdata[i][0] = sv2v_tmp_92290;
+				ibex_csr #(
+					.Width(6),
+					.ShadowCopy(ShadowCSR),
+					.ResetValue(1'sb0)
+				) u_pmp_cfg_csr(
+					.clk_i(clk_i),
+					.rst_ni(rst_ni),
+					.wr_data_i({pmp_cfg_wdata[i]}),
+					.wr_en_i(pmp_cfg_we[i]),
+					.rd_data_o(pmp_cfg[i]),
+					.rd_error_o(pmp_cfg_err[i])
+				);
+				assign pmp_cfg_locked[i] = pmp_cfg[i][5] & ~pmp_mseccfg_q[2];
+				if (i < (PMPNumRegions - 1)) begin : g_lower
+					assign pmp_addr_we[i] = ((csr_we_int & ~pmp_cfg_locked[i]) & (~pmp_cfg_locked[i + 1] | (pmp_cfg[i + 1][4-:2] != 2'b01))) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0]));
+				end
+				else begin : g_upper
+					assign pmp_addr_we[i] = (csr_we_int & ~pmp_cfg_locked[i]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0]));
+				end
+				ibex_csr #(
+					.Width(PMPAddrWidth),
+					.ShadowCopy(ShadowCSR),
+					.ResetValue(1'sb0)
+				) u_pmp_addr_csr(
+					.clk_i(clk_i),
+					.rst_ni(rst_ni),
+					.wr_data_i(csr_wdata_int[31-:PMPAddrWidth]),
+					.wr_en_i(pmp_addr_we[i]),
+					.rd_data_o(pmp_addr[i]),
+					.rd_error_o(pmp_addr_err[i])
+				);
+				assign csr_pmp_cfg_o[((PMPNumRegions - 1) - i) * 6+:6] = pmp_cfg[i];
+				assign csr_pmp_addr_o[((PMPNumRegions - 1) - i) * 34+:34] = {pmp_addr_rdata[i], 2'b00};
+			end
+			assign pmp_mseccfg_we = csr_we_int & (csr_addr == 12'h747);
+			assign pmp_mseccfg_d[0] = (pmp_mseccfg_q[0] ? 1'b1 : csr_wdata_int[ibex_pkg_CSR_MSECCFG_MML_BIT]);
+			assign pmp_mseccfg_d[1] = (pmp_mseccfg_q[1] ? 1'b1 : csr_wdata_int[ibex_pkg_CSR_MSECCFG_MMWP_BIT]);
+			assign any_pmp_entry_locked = |pmp_cfg_locked;
+			assign pmp_mseccfg_d[2] = (any_pmp_entry_locked ? 1'b0 : csr_wdata_int[ibex_pkg_CSR_MSECCFG_RLB_BIT]);
+			ibex_csr #(
+				.Width(3),
+				.ShadowCopy(ShadowCSR),
+				.ResetValue(1'sb0)
+			) u_pmp_mseccfg(
+				.clk_i(clk_i),
+				.rst_ni(rst_ni),
+				.wr_data_i(pmp_mseccfg_d),
+				.wr_en_i(pmp_mseccfg_we),
+				.rd_data_o(pmp_mseccfg_q),
+				.rd_error_o(pmp_mseccfg_err)
+			);
+			assign pmp_csr_err = (|pmp_cfg_err | |pmp_addr_err) | pmp_mseccfg_err;
+			assign pmp_mseccfg = pmp_mseccfg_q;
+		end
+		else begin : g_no_pmp_tieoffs
+			genvar i;
+			for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_rdata
+				wire [32:1] sv2v_tmp_96282;
+				assign sv2v_tmp_96282 = 1'sb0;
+				always @(*) pmp_addr_rdata[i] = sv2v_tmp_96282;
+				assign pmp_cfg_rdata[i] = 1'sb0;
+			end
+			for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_outputs
+				assign csr_pmp_cfg_o[((PMPNumRegions - 1) - i) * 6+:6] = 6'b000000;
+				assign csr_pmp_addr_o[((PMPNumRegions - 1) - i) * 34+:34] = 1'sb0;
+			end
+			assign pmp_csr_err = 1'b0;
+			assign pmp_mseccfg = 1'sb0;
+		end
+	endgenerate
+	assign csr_pmp_mseccfg_o = pmp_mseccfg;
+	always @(*) begin : mcountinhibit_update
+		if (mcountinhibit_we == 1'b1)
+			mcountinhibit_d = {csr_wdata_int[MHPMCounterNum + 2:2], 1'b0, csr_wdata_int[0]};
+		else
+			mcountinhibit_d = mcountinhibit_q;
+	end
+	always @(*) begin : gen_mhpmcounter_incr
+		begin : sv2v_autoblock_1
+			reg [31:0] i;
+			for (i = 0; i < 32; i = i + 1)
+				begin : gen_mhpmcounter_incr_inactive
+					mhpmcounter_incr[i] = 1'b0;
+				end
+		end
+		mhpmcounter_incr[0] = 1'b1;
+		mhpmcounter_incr[1] = 1'b0;
+		mhpmcounter_incr[2] = instr_ret_i;
+		mhpmcounter_incr[3] = dside_wait_i;
+		mhpmcounter_incr[4] = iside_wait_i;
+		mhpmcounter_incr[5] = mem_load_i;
+		mhpmcounter_incr[6] = mem_store_i;
+		mhpmcounter_incr[7] = jump_i;
+		mhpmcounter_incr[8] = branch_i;
+		mhpmcounter_incr[9] = branch_taken_i;
+		mhpmcounter_incr[10] = instr_ret_compressed_i;
+		mhpmcounter_incr[11] = mul_wait_i;
+		mhpmcounter_incr[12] = div_wait_i;
+	end
+	always @(*) begin : gen_mhpmevent
+		begin : sv2v_autoblock_2
+			reg signed [31:0] i;
+			for (i = 0; i < 32; i = i + 1)
+				begin : gen_mhpmevent_active
+					mhpmevent[i] = 1'sb0;
+					mhpmevent[i][i] = 1'b1;
+				end
+		end
+		mhpmevent[1] = 1'sb0;
+		begin : sv2v_autoblock_3
+			reg [31:0] i;
+			for (i = 3 + MHPMCounterNum; i < 32; i = i + 1)
+				begin : gen_mhpmevent_inactive
+					mhpmevent[i] = 1'sb0;
+				end
+		end
+	end
+	ibex_counter #(.CounterWidth(64)) mcycle_counter_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]),
+		.counterh_we_i(mhpmcounterh_we[0]),
+		.counter_we_i(mhpmcounter_we[0]),
+		.counter_val_i(csr_wdata_int),
+		.counter_val_o(mhpmcounter[0]),
+		.counter_val_upd_o()
+	);
+	ibex_counter #(
+		.CounterWidth(64),
+		.ProvideValUpd(1)
+	) minstret_counter_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]),
+		.counterh_we_i(mhpmcounterh_we[2]),
+		.counter_we_i(mhpmcounter_we[2]),
+		.counter_val_i(csr_wdata_int),
+		.counter_val_o(minstret_raw),
+		.counter_val_upd_o(minstret_next)
+	);
+	assign mhpmcounter[2] = (instr_ret_spec_i & ~mcountinhibit[2] ? minstret_next : minstret_raw);
+	assign mhpmcounter[1] = 1'sb0;
+	assign unused_mhpmcounter_we_1 = mhpmcounter_we[1];
+	assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1];
+	assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1];
+	genvar i;
+	generate
+		for (i = 0; i < 29; i = i + 1) begin : gen_cntrs
+			localparam signed [31:0] Cnt = i + 3;
+			if (i < MHPMCounterNum) begin : gen_imp
+				wire [63:0] mhpmcounter_raw;
+				wire [63:0] mhpmcounter_next;
+				ibex_counter #(
+					.CounterWidth(MHPMCounterWidth),
+					.ProvideValUpd(Cnt == 10)
+				) mcounters_variable_i(
+					.clk_i(clk_i),
+					.rst_ni(rst_ni),
+					.counter_inc_i(mhpmcounter_incr[Cnt] & ~mcountinhibit[Cnt]),
+					.counterh_we_i(mhpmcounterh_we[Cnt]),
+					.counter_we_i(mhpmcounter_we[Cnt]),
+					.counter_val_i(csr_wdata_int),
+					.counter_val_o(mhpmcounter_raw),
+					.counter_val_upd_o(mhpmcounter_next)
+				);
+				if (Cnt == 10) begin : gen_compressed_instr_cnt
+					assign mhpmcounter[Cnt] = (instr_ret_compressed_spec_i & ~mcountinhibit[Cnt] ? mhpmcounter_next : mhpmcounter_raw);
+				end
+				else begin : gen_other_cnts
+					wire [63:0] unused_mhpmcounter_next;
+					assign mhpmcounter[Cnt] = mhpmcounter_raw;
+					assign unused_mhpmcounter_next = mhpmcounter_next;
+				end
+			end
+			else begin : gen_unimp
+				assign mhpmcounter[Cnt] = 1'sb0;
+				if (Cnt == 10) begin : gen_no_compressed_instr_cnt
+					wire unused_instr_ret_compressed_spec_i;
+					assign unused_instr_ret_compressed_spec_i = instr_ret_compressed_spec_i;
+				end
+			end
+		end
+		if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced
+			wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_we;
+			wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounterh_we;
+			wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_incr;
+			assign mcountinhibit = {{29 - MHPMCounterNum {1'b1}}, mcountinhibit_q};
+			assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum + 3];
+			assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum + 3];
+			assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum + 3];
+		end
+		else begin : g_mcountinhibit_full
+			assign mcountinhibit = mcountinhibit_q;
+		end
+	endgenerate
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			mcountinhibit_q <= 1'sb0;
+		else
+			mcountinhibit_q <= mcountinhibit_d;
+	generate
+		if (DbgTriggerEn) begin : gen_trigger_regs
+			localparam [31:0] DbgHwNumLen = (DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1);
+			localparam [31:0] MaxTselect = DbgHwBreakNum - 1;
+			wire [DbgHwNumLen - 1:0] tselect_d;
+			wire [DbgHwNumLen - 1:0] tselect_q;
+			wire tmatch_control_d;
+			wire [DbgHwBreakNum - 1:0] tmatch_control_q;
+			wire [31:0] tmatch_value_d;
+			wire [31:0] tmatch_value_q [0:DbgHwBreakNum - 1];
+			wire selected_tmatch_control;
+			wire [31:0] selected_tmatch_value;
+			wire tselect_we;
+			wire [DbgHwBreakNum - 1:0] tmatch_control_we;
+			wire [DbgHwBreakNum - 1:0] tmatch_value_we;
+			wire [DbgHwBreakNum - 1:0] trigger_match;
+			assign tselect_we = (csr_we_int & debug_mode_i) & (csr_addr_i == 12'h7a0);
+			genvar i;
+			for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_we
+				assign tmatch_control_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == 12'h7a1);
+				assign tmatch_value_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == 12'h7a2);
+			end
+			assign tselect_d = (csr_wdata_int < DbgHwBreakNum ? csr_wdata_int[DbgHwNumLen - 1:0] : MaxTselect[DbgHwNumLen - 1:0]);
+			assign tmatch_control_d = csr_wdata_int[2];
+			assign tmatch_value_d = csr_wdata_int[31:0];
+			ibex_csr #(
+				.Width(DbgHwNumLen),
+				.ShadowCopy(1'b0),
+				.ResetValue(1'sb0)
+			) u_tselect_csr(
+				.clk_i(clk_i),
+				.rst_ni(rst_ni),
+				.wr_data_i(tselect_d),
+				.wr_en_i(tselect_we),
+				.rd_data_o(tselect_q),
+				.rd_error_o()
+			);
+			for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_reg
+				ibex_csr #(
+					.Width(1),
+					.ShadowCopy(1'b0),
+					.ResetValue(1'sb0)
+				) u_tmatch_control_csr(
+					.clk_i(clk_i),
+					.rst_ni(rst_ni),
+					.wr_data_i(tmatch_control_d),
+					.wr_en_i(tmatch_control_we[i]),
+					.rd_data_o(tmatch_control_q[i]),
+					.rd_error_o()
+				);
+				ibex_csr #(
+					.Width(32),
+					.ShadowCopy(1'b0),
+					.ResetValue(1'sb0)
+				) u_tmatch_value_csr(
+					.clk_i(clk_i),
+					.rst_ni(rst_ni),
+					.wr_data_i(tmatch_value_d),
+					.wr_en_i(tmatch_value_we[i]),
+					.rd_data_o(tmatch_value_q[i]),
+					.rd_error_o()
+				);
+			end
+			localparam [31:0] TSelectRdataPadlen = (DbgHwNumLen >= 32 ? 0 : 32 - DbgHwNumLen);
+			assign tselect_rdata = {{TSelectRdataPadlen {1'b0}}, tselect_q};
+			if (DbgHwBreakNum > 1) begin : g_dbg_tmatch_multiple_select
+				assign selected_tmatch_control = tmatch_control_q[tselect_q];
+				assign selected_tmatch_value = tmatch_value_q[tselect_q];
+			end
+			else begin : g_dbg_tmatch_single_select
+				assign selected_tmatch_control = tmatch_control_q[0];
+				assign selected_tmatch_value = tmatch_value_q[0];
+			end
+			assign tmatch_control_rdata = {29'b00101000000000000001000001001, selected_tmatch_control, 1'b0, 1'b0};
+			assign tmatch_value_rdata = selected_tmatch_value;
+			for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_trigger_match
+				assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]);
+			end
+			assign trigger_match_o = |trigger_match;
+		end
+		else begin : gen_no_trigger_regs
+			assign tselect_rdata = 'b0;
+			assign tmatch_control_rdata = 'b0;
+			assign tmatch_value_rdata = 'b0;
+			assign trigger_match_o = 'b0;
+		end
+	endgenerate
+	assign cpuctrl_wdata = csr_wdata_int[5:0];
+	generate
+		if (DataIndTiming) begin : gen_dit
+			assign cpuctrl_d[1] = cpuctrl_wdata[1];
+		end
+		else begin : gen_no_dit
+			wire unused_dit;
+			assign unused_dit = cpuctrl_wdata[1];
+			assign cpuctrl_d[1] = 1'b0;
+		end
+	endgenerate
+	assign data_ind_timing_o = cpuctrl_q[1];
+	generate
+		if (DummyInstructions) begin : gen_dummy
+			assign cpuctrl_d[2] = cpuctrl_wdata[2];
+			assign cpuctrl_d[5-:3] = cpuctrl_wdata[5-:3];
+			assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == 12'h7c1);
+			assign dummy_instr_seed_o = csr_wdata_int;
+		end
+		else begin : gen_no_dummy
+			wire unused_dummy_en;
+			wire [2:0] unused_dummy_mask;
+			assign unused_dummy_en = cpuctrl_wdata[2];
+			assign unused_dummy_mask = cpuctrl_wdata[5-:3];
+			assign cpuctrl_d[2] = 1'b0;
+			assign cpuctrl_d[5-:3] = 3'b000;
+			assign dummy_instr_seed_en_o = 1'b0;
+			assign dummy_instr_seed_o = 1'sb0;
+		end
+	endgenerate
+	assign dummy_instr_en_o = cpuctrl_q[2];
+	assign dummy_instr_mask_o = cpuctrl_q[5-:3];
+	generate
+		if (ICache) begin : gen_icache_enable
+			assign cpuctrl_d[0] = cpuctrl_wdata[0];
+		end
+		else begin : gen_no_icache
+			wire unused_icen;
+			assign unused_icen = cpuctrl_wdata[0];
+			assign cpuctrl_d[0] = 1'b0;
+		end
+	endgenerate
+	assign icache_enable_o = cpuctrl_q[0];
+	ibex_csr #(
+		.Width(6),
+		.ShadowCopy(ShadowCSR),
+		.ResetValue(1'sb0)
+	) u_cpuctrl_csr(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.wr_data_i({cpuctrl_d}),
+		.wr_en_i(cpuctrl_we),
+		.rd_data_o(cpuctrl_q),
+		.rd_error_o(cpuctrl_err)
+	);
+	assign csr_shadow_err_o = ((mstatus_err | mtvec_err) | pmp_csr_err) | cpuctrl_err;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_csr.v b/verilog/rtl/ibex_core/ibex_csr.v
new file mode 100644
index 0000000..edae878
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_csr.v
@@ -0,0 +1,39 @@
+module ibex_csr (
+	clk_i,
+	rst_ni,
+	wr_data_i,
+	wr_en_i,
+	rd_data_o,
+	rd_error_o
+);
+	parameter [31:0] Width = 32;
+	parameter [0:0] ShadowCopy = 1'b0;
+	parameter [Width - 1:0] ResetValue = 1'sb0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [Width - 1:0] wr_data_i;
+	input wire wr_en_i;
+	output wire [Width - 1:0] rd_data_o;
+	output wire rd_error_o;
+	reg [Width - 1:0] rdata_q;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			rdata_q <= ResetValue;
+		else if (wr_en_i)
+			rdata_q <= wr_data_i;
+	assign rd_data_o = rdata_q;
+	generate
+		if (ShadowCopy) begin : gen_shadow
+			reg [Width - 1:0] shadow_q;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					shadow_q <= ~ResetValue;
+				else if (wr_en_i)
+					shadow_q <= ~wr_data_i;
+			assign rd_error_o = rdata_q != ~shadow_q;
+		end
+		else begin : gen_no_shadow
+			assign rd_error_o = 1'b0;
+		end
+	endgenerate
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_decoder.v b/verilog/rtl/ibex_core/ibex_decoder.v
new file mode 100644
index 0000000..ae09c5d
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_decoder.v
@@ -0,0 +1,1092 @@
+module ibex_decoder (
+	clk_i,
+	rst_ni,
+	illegal_insn_o,
+	ebrk_insn_o,
+	mret_insn_o,
+	dret_insn_o,
+	ecall_insn_o,
+	wfi_insn_o,
+	jump_set_o,
+	branch_taken_i,
+	icache_inval_o,
+	instr_first_cycle_i,
+	instr_rdata_i,
+	instr_rdata_alu_i,
+	illegal_c_insn_i,
+	imm_a_mux_sel_o,
+	imm_b_mux_sel_o,
+	bt_a_mux_sel_o,
+	bt_b_mux_sel_o,
+	imm_i_type_o,
+	imm_s_type_o,
+	imm_b_type_o,
+	imm_u_type_o,
+	imm_j_type_o,
+	zimm_rs1_type_o,
+	rf_wdata_sel_o,
+	rf_we_o,
+	rf_raddr_a_o,
+	rf_raddr_b_o,
+	rf_waddr_o,
+	rf_ren_a_o,
+	rf_ren_b_o,
+	alu_operator_o,
+	alu_op_a_mux_sel_o,
+	alu_op_b_mux_sel_o,
+	alu_multicycle_o,
+	eFPGA_operator_o,
+	eFPGA_int_en_o,
+	eFPGA_delay_o,
+	mult_en_o,
+	div_en_o,
+	mult_sel_o,
+	div_sel_o,
+	multdiv_operator_o,
+	multdiv_signed_mode_o,
+	csr_access_o,
+	csr_op_o,
+	data_req_o,
+	data_we_o,
+	data_type_o,
+	data_sign_extension_o,
+	jump_in_dec_o,
+	branch_in_dec_o
+);
+	parameter [0:0] RV32E = 0;
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd0;
+	parameter [0:0] BranchTargetALU = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	output wire illegal_insn_o;
+	output reg ebrk_insn_o;
+	output reg mret_insn_o;
+	output reg dret_insn_o;
+	output reg ecall_insn_o;
+	output reg wfi_insn_o;
+	output reg jump_set_o;
+	input wire branch_taken_i;
+	output reg icache_inval_o;
+	input wire instr_first_cycle_i;
+	input wire [31:0] instr_rdata_i;
+	input wire [31:0] instr_rdata_alu_i;
+	input wire illegal_c_insn_i;
+	output reg imm_a_mux_sel_o;
+	output reg [2:0] imm_b_mux_sel_o;
+	output reg [1:0] bt_a_mux_sel_o;
+	output reg [2:0] bt_b_mux_sel_o;
+	output wire [31:0] imm_i_type_o;
+	output wire [31:0] imm_s_type_o;
+	output wire [31:0] imm_b_type_o;
+	output wire [31:0] imm_u_type_o;
+	output wire [31:0] imm_j_type_o;
+	output wire [31:0] zimm_rs1_type_o;
+	output reg rf_wdata_sel_o;
+	output wire rf_we_o;
+	output wire [4:0] rf_raddr_a_o;
+	output wire [4:0] rf_raddr_b_o;
+	output wire [4:0] rf_waddr_o;
+	output reg rf_ren_a_o;
+	output reg rf_ren_b_o;
+	output reg [6:0] alu_operator_o;
+	output reg [1:0] alu_op_a_mux_sel_o;
+	output reg alu_op_b_mux_sel_o;
+	output reg alu_multicycle_o;
+	output reg [1:0] eFPGA_operator_o;
+	output wire eFPGA_int_en_o;
+	output reg [3:0] eFPGA_delay_o;
+	output wire mult_en_o;
+	output wire div_en_o;
+	output reg mult_sel_o;
+	output reg div_sel_o;
+	output reg [1:0] multdiv_operator_o;
+	output reg [1:0] multdiv_signed_mode_o;
+	output reg csr_access_o;
+	output reg [1:0] csr_op_o;
+	output reg data_req_o;
+	output reg data_we_o;
+	output reg [1:0] data_type_o;
+	output reg data_sign_extension_o;
+	output reg jump_in_dec_o;
+	output reg branch_in_dec_o;
+	reg illegal_insn;
+	wire illegal_reg_rv32e;
+	reg csr_illegal;
+	reg rf_we;
+	wire [31:0] instr;
+	wire [31:0] instr_alu;
+	wire [9:0] unused_instr_alu;
+	wire [4:0] instr_rs1;
+	wire [4:0] instr_rs2;
+	wire [4:0] instr_rs3;
+	wire [4:0] instr_rd;
+	reg use_rs3_d;
+	reg use_rs3_q;
+	reg [1:0] csr_op;
+	reg [6:0] opcode;
+	reg [6:0] opcode_alu;
+	assign instr = instr_rdata_i;
+	assign instr_alu = instr_rdata_alu_i;
+	assign imm_i_type_o = {{20 {instr[31]}}, instr[31:20]};
+	assign imm_s_type_o = {{20 {instr[31]}}, instr[31:25], instr[11:7]};
+	assign imm_b_type_o = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+	assign imm_u_type_o = {instr[31:12], 12'b000000000000};
+	assign imm_j_type_o = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+	assign zimm_rs1_type_o = {27'b000000000000000000000000000, instr_rs1};
+	generate
+		if (RV32B != 32'sd0) begin : gen_rs3_flop
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					use_rs3_q <= 1'b0;
+				else
+					use_rs3_q <= use_rs3_d;
+		end
+		else begin : gen_no_rs3_flop
+			wire unused_clk;
+			wire unused_rst_n;
+			assign unused_clk = clk_i;
+			assign unused_rst_n = rst_ni;
+			wire [1:1] sv2v_tmp_44B6F;
+			assign sv2v_tmp_44B6F = use_rs3_d;
+			always @(*) use_rs3_q = sv2v_tmp_44B6F;
+		end
+	endgenerate
+	assign instr_rs1 = instr[19:15];
+	assign instr_rs2 = instr[24:20];
+	assign instr_rs3 = instr[31:27];
+	assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i ? instr_rs3 : instr_rs1);
+	assign rf_raddr_b_o = instr_rs2;
+	assign instr_rd = instr[11:7];
+	assign rf_waddr_o = instr_rd;
+	generate
+		if (RV32E) begin : gen_rv32e_reg_check_active
+			assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == 2'd0)) | (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == 1'd0))) | (rf_waddr_o[4] & rf_we);
+		end
+		else begin : gen_rv32e_reg_check_inactive
+			assign illegal_reg_rv32e = 1'b0;
+		end
+	endgenerate
+	always @(*) begin : csr_operand_check
+		csr_op_o = csr_op;
+		if (((csr_op == 2'd2) || (csr_op == 2'd3)) && (instr_rs1 == {5 {1'sb0}}))
+			csr_op_o = 2'd0;
+	end
+	reg eFPGA_int_en;
+	always @(*) begin
+		jump_in_dec_o = 1'b0;
+		jump_set_o = 1'b0;
+		branch_in_dec_o = 1'b0;
+		icache_inval_o = 1'b0;
+		eFPGA_int_en = 1'b0;
+		eFPGA_operator_o = 2'b00;
+		eFPGA_delay_o = 4'b0000;
+		multdiv_operator_o = 2'd0;
+		multdiv_signed_mode_o = 2'b00;
+		rf_wdata_sel_o = 1'd0;
+		rf_we = 1'b0;
+		rf_ren_a_o = 1'b0;
+		rf_ren_b_o = 1'b0;
+		csr_access_o = 1'b0;
+		csr_illegal = 1'b0;
+		csr_op = 2'd0;
+		data_we_o = 1'b0;
+		data_type_o = 2'b00;
+		data_sign_extension_o = 1'b0;
+		data_req_o = 1'b0;
+		illegal_insn = 1'b0;
+		ebrk_insn_o = 1'b0;
+		mret_insn_o = 1'b0;
+		dret_insn_o = 1'b0;
+		ecall_insn_o = 1'b0;
+		wfi_insn_o = 1'b0;
+		opcode = instr[6:0];
+		case (opcode)
+			7'h6f: begin
+				jump_in_dec_o = 1'b1;
+				if (instr_first_cycle_i) begin
+					rf_we = BranchTargetALU;
+					jump_set_o = 1'b1;
+				end
+				else
+					rf_we = 1'b1;
+			end
+			7'h67: begin
+				jump_in_dec_o = 1'b1;
+				if (instr_first_cycle_i) begin
+					rf_we = BranchTargetALU;
+					jump_set_o = 1'b1;
+				end
+				else
+					rf_we = 1'b1;
+				if (instr[14:12] != 3'b000)
+					illegal_insn = 1'b1;
+				rf_ren_a_o = 1'b1;
+			end
+			7'h63: begin
+				branch_in_dec_o = 1'b1;
+				case (instr[14:12])
+					3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: illegal_insn = 1'b0;
+					default: illegal_insn = 1'b1;
+				endcase
+				rf_ren_a_o = 1'b1;
+				rf_ren_b_o = 1'b1;
+			end
+			7'h23: begin
+				rf_ren_a_o = 1'b1;
+				rf_ren_b_o = 1'b1;
+				data_req_o = 1'b1;
+				data_we_o = 1'b1;
+				if (instr[14])
+					illegal_insn = 1'b1;
+				case (instr[13:12])
+					2'b00: data_type_o = 2'b10;
+					2'b01: data_type_o = 2'b01;
+					2'b10: data_type_o = 2'b00;
+					default: illegal_insn = 1'b1;
+				endcase
+			end
+			7'h03: begin
+				rf_ren_a_o = 1'b1;
+				data_req_o = 1'b1;
+				data_type_o = 2'b00;
+				data_sign_extension_o = ~instr[14];
+				case (instr[13:12])
+					2'b00: data_type_o = 2'b10;
+					2'b01: data_type_o = 2'b01;
+					2'b10: begin
+						data_type_o = 2'b00;
+						if (instr[14])
+							illegal_insn = 1'b1;
+					end
+					default: illegal_insn = 1'b1;
+				endcase
+			end
+			7'h37: rf_we = 1'b1;
+			7'h17: rf_we = 1'b1;
+			7'h13: begin
+				rf_ren_a_o = 1'b1;
+				rf_we = 1'b1;
+				case (instr[14:12])
+					3'b000, 3'b010, 3'b011, 3'b100, 3'b110, 3'b111: illegal_insn = 1'b0;
+					3'b001:
+						case (instr[31:27])
+							5'b00000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1);
+							5'b00100, 5'b01001, 5'b00101, 5'b01101: illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+							5'b00001:
+								if (instr[26] == 1'b0) begin
+									if (RV32B == 32'sd2)
+										illegal_insn = 1'b0;
+									else if (RV32Zk != 32'sd0)
+										illegal_insn = (instr[25:20] == 6'b001111 ? 1'b0 : 1'b1);
+									else
+										illegal_insn = 1'b1;
+								end
+								else
+									illegal_insn = 1'b1;
+							5'b01100:
+								case (instr[26:20])
+									7'b0000000, 7'b0000001, 7'b0000010, 7'b0000100, 7'b0000101: illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+									7'b0010000, 7'b0010001, 7'b0010010, 7'b0011000, 7'b0011001, 7'b0011010: illegal_insn = (RV32B == 32'sd2 ? 1'b0 : 1'b1);
+									default: illegal_insn = 1'b1;
+								endcase
+							5'b00010:
+								case (instr[26:20])
+									7'b0000000, 7'b0000001, 7'b0000010, 7'b0000011: illegal_insn = (RV32Zk == 32'sd2 ? 1'b0 : 1'b1);
+									7'b0001000, 7'b0001001: illegal_insn = (RV32Zk == 32'sd3 ? 1'b0 : 1'b1);
+									default: illegal_insn = 1'b1;
+								endcase
+							default: illegal_insn = 1'b1;
+						endcase
+					3'b101:
+						if (instr[26])
+							illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+						else
+							case (instr[31:27])
+								5'b00000, 5'b01000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1);
+								5'b00100, 5'b01001: illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+								5'b01100: illegal_insn = ((RV32B != 32'sd0) || (RV32Zk != 32'sd0) ? 1'b0 : 1'b1);
+								5'b01101:
+									if (RV32B == 32'sd2)
+										illegal_insn = 1'b0;
+									else
+										case (instr[24:20])
+											5'b11111: illegal_insn = (RV32B == 32'sd1 ? 1'b0 : 1'b1);
+											5'b11000: illegal_insn = ((RV32B == 32'sd1) || (RV32Zk != 32'sd0) ? 1'b0 : 1'b1);
+											5'b00111: illegal_insn = (RV32Zk != 32'sd0 ? 1'b0 : 1'b1);
+											default: illegal_insn = 1'b1;
+										endcase
+								5'b00101:
+									if (RV32B == 32'sd2)
+										illegal_insn = 1'b0;
+									else if (instr[24:20] == 5'b00111)
+										illegal_insn = (RV32B == 32'sd1 ? 1'b0 : 1'b1);
+									else
+										illegal_insn = 1'b1;
+								5'b00001:
+									if (instr[26] == 1'b0) begin
+										if (RV32B == 32'sd2)
+											illegal_insn = 1'b0;
+										else if (RV32Zk != 32'sd0)
+											illegal_insn = (instr[25:20] == 6'b001111 ? 1'b0 : 1'b1);
+										else
+											illegal_insn = 1'b1;
+									end
+									else
+										illegal_insn = 1'b1;
+								default: illegal_insn = 1'b1;
+							endcase
+					default: illegal_insn = 1'b1;
+				endcase
+			end
+			7'h33: begin
+				rf_ren_a_o = 1'b1;
+				rf_ren_b_o = 1'b1;
+				rf_we = 1'b1;
+				if ({instr[26], instr[13:12]} == 3'b101)
+					illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+				else if ({instr[29:28], instr[25], instr[14:12]} == 6'b101000)
+					illegal_insn = (RV32Zk == 32'sd2 ? 1'b0 : 1'b1);
+				else if ({instr[29:27], instr[25], instr[14:12]} == 7'b1100000)
+					illegal_insn = (RV32Zk == 32'sd3 ? 1'b0 : 1'b1);
+				else
+					case ({instr[31:25], instr[14:12]})
+						10'b0000000000, 10'b0100000000, 10'b0000000010, 10'b0000000011, 10'b0000000100, 10'b0000000110, 10'b0000000111, 10'b0000000001, 10'b0000000101, 10'b0100000101: illegal_insn = 1'b0;
+						10'b0010000010, 10'b0010000100, 10'b0010000110: illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+						10'b0100000111, 10'b0100000110, 10'b0100000100, 10'b0110000001, 10'b0110000101, 10'b0000100100, 10'b0000100111: illegal_insn = ((RV32B != 32'sd0) || (RV32Zk != 32'sd0) ? 1'b0 : 1'b1);
+						10'b0100100100, 10'b0010000001, 10'b0010000101, 10'b0000101100, 10'b0000101101, 10'b0000101110, 10'b0000101111, 10'b0100100001, 10'b0010100001, 10'b0110100001, 10'b0100100101, 10'b0100100111: illegal_insn = (RV32B != 32'sd0 ? 1'b0 : 1'b1);
+						10'b0100100110, 10'b0000100110, 10'b0110100101, 10'b0010100101, 10'b0000100001, 10'b0000100101: illegal_insn = (RV32B == 32'sd2 ? 1'b0 : 1'b1);
+						10'b0000101001, 10'b0000101011: illegal_insn = ((RV32B == 32'sd2) || (RV32Zk != 32'sd0) ? 1'b0 : 1'b1);
+						10'b0000101010: illegal_insn = (RV32B == 32'sd2 ? 1'b0 : 1'b1);
+						10'b0010100100, 10'b0010100010: illegal_insn = (RV32Zk != 32'sd0 ? 1'b0 : 1'b1);
+						10'b0101000000, 10'b0101001000, 10'b0101010000, 10'b0101011000, 10'b0101110000, 10'b0101111000: illegal_insn = (RV32Zk == 32'sd2 ? 1'b0 : 1'b1);
+						10'b0000001000: begin
+							multdiv_operator_o = 2'd0;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001001: begin
+							multdiv_operator_o = 2'd1;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001010: begin
+							multdiv_operator_o = 2'd1;
+							multdiv_signed_mode_o = 2'b01;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001011: begin
+							multdiv_operator_o = 2'd1;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001100: begin
+							multdiv_operator_o = 2'd2;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001101: begin
+							multdiv_operator_o = 2'd2;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001110: begin
+							multdiv_operator_o = 2'd3;
+							multdiv_signed_mode_o = 2'b11;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						10'b0000001111: begin
+							multdiv_operator_o = 2'd3;
+							multdiv_signed_mode_o = 2'b00;
+							illegal_insn = (RV32M == 32'sd0 ? 1'b1 : 1'b0);
+						end
+						default: illegal_insn = 1'b1;
+					endcase
+			end
+			7'h0b: begin
+				rf_ren_a_o = 1'b1;
+				rf_ren_b_o = 1'b1;
+				rf_we = 1'b1;
+				eFPGA_operator_o = instr_rdata_i[13:12];
+				eFPGA_delay_o = instr_rdata_i[28:25];
+				eFPGA_int_en = 1'b1;
+				illegal_insn = 1'b0;
+			end
+			7'h0f:
+				case (instr[14:12])
+					3'b000: rf_we = 1'b0;
+					3'b001: begin
+						jump_in_dec_o = 1'b1;
+						rf_we = 1'b0;
+						if (instr_first_cycle_i) begin
+							jump_set_o = 1'b1;
+							icache_inval_o = 1'b1;
+						end
+					end
+					default: illegal_insn = 1'b1;
+				endcase
+			7'h73:
+				if (instr[14:12] == 3'b000) begin
+					case (instr[31:20])
+						12'h000: ecall_insn_o = 1'b1;
+						12'h001: ebrk_insn_o = 1'b1;
+						12'h302: mret_insn_o = 1'b1;
+						12'h7b2: dret_insn_o = 1'b1;
+						12'h105: wfi_insn_o = 1'b1;
+						default: illegal_insn = 1'b1;
+					endcase
+					if ((instr_rs1 != 5'b00000) || (instr_rd != 5'b00000))
+						illegal_insn = 1'b1;
+				end
+				else begin
+					csr_access_o = 1'b1;
+					rf_wdata_sel_o = 1'd1;
+					rf_we = 1'b1;
+					if (~instr[14])
+						rf_ren_a_o = 1'b1;
+					case (instr[13:12])
+						2'b01: csr_op = 2'd1;
+						2'b10: csr_op = 2'd2;
+						2'b11: csr_op = 2'd3;
+						default: csr_illegal = 1'b1;
+					endcase
+					illegal_insn = csr_illegal;
+				end
+			default: illegal_insn = 1'b1;
+		endcase
+		if (illegal_c_insn_i)
+			illegal_insn = 1'b1;
+		if (illegal_insn) begin
+			rf_we = 1'b0;
+			data_req_o = 1'b0;
+			data_we_o = 1'b0;
+			jump_in_dec_o = 1'b0;
+			jump_set_o = 1'b0;
+			branch_in_dec_o = 1'b0;
+			csr_access_o = 1'b0;
+		end
+	end
+	always @(*) begin
+		alu_operator_o = 7'd41;
+		alu_op_a_mux_sel_o = 2'd3;
+		alu_op_b_mux_sel_o = 1'd1;
+		imm_a_mux_sel_o = 1'd1;
+		imm_b_mux_sel_o = 3'd0;
+		bt_a_mux_sel_o = 2'd2;
+		bt_b_mux_sel_o = 3'd0;
+		opcode_alu = instr_alu[6:0];
+		use_rs3_d = 1'b0;
+		alu_multicycle_o = 1'b0;
+		mult_sel_o = 1'b0;
+		div_sel_o = 1'b0;
+		case (opcode_alu)
+			7'h6f: begin
+				if (BranchTargetALU) begin
+					bt_a_mux_sel_o = 2'd2;
+					bt_b_mux_sel_o = 3'd4;
+				end
+				if (instr_first_cycle_i && !BranchTargetALU) begin
+					alu_op_a_mux_sel_o = 2'd2;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd4;
+					alu_operator_o = 7'd0;
+				end
+				else begin
+					alu_op_a_mux_sel_o = 2'd2;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd5;
+					alu_operator_o = 7'd0;
+				end
+			end
+			7'h67: begin
+				if (BranchTargetALU) begin
+					bt_a_mux_sel_o = 2'd0;
+					bt_b_mux_sel_o = 3'd0;
+				end
+				if (instr_first_cycle_i && !BranchTargetALU) begin
+					alu_op_a_mux_sel_o = 2'd0;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd0;
+					alu_operator_o = 7'd0;
+				end
+				else begin
+					alu_op_a_mux_sel_o = 2'd2;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = 3'd5;
+					alu_operator_o = 7'd0;
+				end
+			end
+			7'h63: begin
+				case (instr_alu[14:12])
+					3'b000: alu_operator_o = 7'd26;
+					3'b001: alu_operator_o = 7'd27;
+					3'b100: alu_operator_o = 7'd22;
+					3'b101: alu_operator_o = 7'd24;
+					3'b110: alu_operator_o = 7'd23;
+					3'b111: alu_operator_o = 7'd25;
+					default:
+						;
+				endcase
+				if (BranchTargetALU) begin
+					bt_a_mux_sel_o = 2'd2;
+					bt_b_mux_sel_o = (branch_taken_i ? 3'd2 : 3'd5);
+				end
+				if (instr_first_cycle_i) begin
+					alu_op_a_mux_sel_o = 2'd0;
+					alu_op_b_mux_sel_o = 1'd0;
+				end
+				else if (!BranchTargetALU) begin
+					alu_op_a_mux_sel_o = 2'd2;
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_b_mux_sel_o = (branch_taken_i ? 3'd2 : 3'd5);
+					alu_operator_o = 7'd0;
+				end
+			end
+			7'h23: begin
+				alu_op_a_mux_sel_o = 2'd0;
+				alu_op_b_mux_sel_o = 1'd0;
+				alu_operator_o = 7'd0;
+				if (!instr_alu[14]) begin
+					imm_b_mux_sel_o = 3'd1;
+					alu_op_b_mux_sel_o = 1'd1;
+				end
+			end
+			7'h03: begin
+				alu_op_a_mux_sel_o = 2'd0;
+				alu_operator_o = 7'd0;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd0;
+			end
+			7'h37: begin
+				alu_op_a_mux_sel_o = 2'd3;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_a_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd3;
+				alu_operator_o = 7'd0;
+			end
+			7'h17: begin
+				alu_op_a_mux_sel_o = 2'd2;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd3;
+				alu_operator_o = 7'd0;
+			end
+			7'h13: begin
+				alu_op_a_mux_sel_o = 2'd0;
+				alu_op_b_mux_sel_o = 1'd1;
+				imm_b_mux_sel_o = 3'd0;
+				case (instr_alu[14:12])
+					3'b000: alu_operator_o = 7'd0;
+					3'b010: alu_operator_o = 7'd40;
+					3'b011: alu_operator_o = 7'd41;
+					3'b100: alu_operator_o = 7'd2;
+					3'b110: alu_operator_o = 7'd3;
+					3'b111: alu_operator_o = 7'd4;
+					3'b001:
+						case (instr_alu[31:27])
+							5'b00000: alu_operator_o = 7'd10;
+							5'b00100:
+								if (RV32B != 32'sd0)
+									alu_operator_o = 7'd12;
+							5'b01001:
+								if (RV32B != 32'sd0)
+									alu_operator_o = 7'd47;
+							5'b00101:
+								if (RV32B != 32'sd0)
+									alu_operator_o = 7'd46;
+							5'b01101:
+								if (RV32B != 32'sd0)
+									alu_operator_o = 7'd48;
+							5'b00001:
+								if (instr_alu[26] == 0)
+									if (RV32B == 32'sd2)
+										alu_operator_o = 7'd17;
+									else if (RV32Zk != 32'sd0)
+										alu_operator_o = (instr[25:20] == 6'b001111 ? 7'd65 : 7'd10);
+									else
+										alu_operator_o = 7'd10;
+							5'b01100:
+								case (instr_alu[26:20])
+									7'b0000000:
+										if (RV32B != 32'sd0)
+											alu_operator_o = 7'd37;
+									7'b0000001:
+										if (RV32B != 32'sd0)
+											alu_operator_o = 7'd38;
+									7'b0000010:
+										if (RV32B != 32'sd0)
+											alu_operator_o = 7'd39;
+									7'b0000100:
+										if (RV32B != 32'sd0)
+											alu_operator_o = 7'd35;
+									7'b0000101:
+										if (RV32B != 32'sd0)
+											alu_operator_o = 7'd36;
+									7'b0010000:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd56;
+											alu_multicycle_o = 1'b1;
+										end
+									7'b0010001:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd58;
+											alu_multicycle_o = 1'b1;
+										end
+									7'b0010010:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd60;
+											alu_multicycle_o = 1'b1;
+										end
+									7'b0011000:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd57;
+											alu_multicycle_o = 1'b1;
+										end
+									7'b0011001:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd59;
+											alu_multicycle_o = 1'b1;
+										end
+									7'b0011010:
+										if (RV32B == 32'sd2) begin
+											alu_operator_o = 7'd61;
+											alu_multicycle_o = 1'b1;
+										end
+									default:
+										;
+								endcase
+							5'b00010:
+								case (instr_alu[26:20])
+									7'b0000000:
+										if (RV32Zk == 32'sd2)
+											alu_operator_o = 7'd78;
+									7'b0000001:
+										if (RV32Zk == 32'sd2)
+											alu_operator_o = 7'd79;
+									7'b0000010:
+										if (RV32Zk == 32'sd2)
+											alu_operator_o = 7'd80;
+									7'b0000011:
+										if (RV32Zk == 32'sd2)
+											alu_operator_o = 7'd81;
+									7'b0001000:
+										if (RV32Zk == 32'sd3)
+											alu_operator_o = 7'd112;
+									7'b0001001:
+										if (RV32Zk == 32'sd3)
+											alu_operator_o = 7'd113;
+									default: alu_operator_o = 7'd10;
+								endcase
+							default: alu_operator_o = 7'd10;
+						endcase
+					3'b101:
+						if (RV32B != 32'sd0) begin
+							if (instr_alu[26] == 1'b1) begin
+								alu_operator_o = 7'd45;
+								alu_multicycle_o = 1'b1;
+								if (instr_first_cycle_i)
+									use_rs3_d = 1'b1;
+								else
+									use_rs3_d = 1'b0;
+							end
+							else
+								case (instr_alu[31:27])
+									5'b00000: alu_operator_o = 7'd9;
+									5'b01000: alu_operator_o = 7'd8;
+									5'b00100: alu_operator_o = 7'd11;
+									5'b01001: alu_operator_o = 7'd49;
+									5'b01100: begin
+										alu_operator_o = 7'd13;
+										alu_multicycle_o = 1'b1;
+									end
+									5'b01101: alu_operator_o = 7'd15;
+									5'b00101: alu_operator_o = 7'd16;
+									5'b00001:
+										if (RV32B == 32'sd2)
+											if (instr_alu[26] == 1'b0)
+												alu_operator_o = 7'd18;
+									default:
+										;
+								endcase
+						end
+						else
+							case (instr_alu[31:27])
+								5'b00000: alu_operator_o = 7'd9;
+								5'b01000: alu_operator_o = 7'd8;
+								5'b01100:
+									if (RV32Zk != 32'sd0)
+										if (instr_alu[26] == 1'b0)
+											alu_operator_o = 7'd62;
+								5'b01101:
+									if (RV32Zk != 32'sd0) begin
+										if (instr_alu[26:20] == 7'b0000111)
+											alu_operator_o = 7'd63;
+										if (instr_alu[26:20] == 7'b0011000)
+											alu_operator_o = 7'd64;
+									end
+								5'b00001:
+									if (RV32Zk != 32'sd0)
+										if (instr_alu[26:20] == 7'b0001111)
+											alu_operator_o = 7'd66;
+								default:
+									;
+							endcase
+					default:
+						;
+				endcase
+			end
+			7'h33: begin
+				alu_op_a_mux_sel_o = 2'd0;
+				alu_op_b_mux_sel_o = 1'd0;
+				if ({instr[26], instr[13:12]} == 3'b101) begin
+					if (RV32B != 32'sd0)
+						case ({instr_alu[26:25], instr_alu[14:12]})
+							5'b11001: begin
+								alu_operator_o = 7'd43;
+								alu_multicycle_o = 1'b1;
+								if (instr_first_cycle_i)
+									use_rs3_d = 1'b1;
+								else
+									use_rs3_d = 1'b0;
+							end
+							5'b11101: begin
+								alu_operator_o = 7'd42;
+								alu_multicycle_o = 1'b1;
+								if (instr_first_cycle_i)
+									use_rs3_d = 1'b1;
+								else
+									use_rs3_d = 1'b0;
+							end
+							5'b10001: begin
+								alu_operator_o = 7'd44;
+								alu_multicycle_o = 1'b1;
+								if (instr_first_cycle_i)
+									use_rs3_d = 1'b1;
+								else
+									use_rs3_d = 1'b0;
+							end
+							5'b10101: begin
+								alu_operator_o = 7'd45;
+								alu_multicycle_o = 1'b1;
+								if (instr_first_cycle_i)
+									use_rs3_d = 1'b1;
+								else
+									use_rs3_d = 1'b0;
+							end
+							default:
+								;
+						endcase
+				end
+				else
+					case ({instr_alu[31:25], instr_alu[14:12]})
+						10'b0000000000: alu_operator_o = 7'd0;
+						10'b0100000000: alu_operator_o = 7'd1;
+						10'b0000000010: alu_operator_o = 7'd40;
+						10'b0000000011: alu_operator_o = 7'd41;
+						10'b0000000100: alu_operator_o = 7'd2;
+						10'b0000000110: alu_operator_o = 7'd3;
+						10'b0000000111: alu_operator_o = 7'd4;
+						10'b0000000001: alu_operator_o = 7'd10;
+						10'b0000000101: alu_operator_o = 7'd9;
+						10'b0100000101: alu_operator_o = 7'd8;
+						10'b0010000001:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd12;
+						10'b0010000101:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd11;
+						10'b0110000001:
+							if (RV32B != 32'sd0) begin
+								alu_operator_o = 7'd14;
+								alu_multicycle_o = 1'b1;
+							end
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd68;
+						10'b0110000101:
+							if (RV32B != 32'sd0) begin
+								alu_operator_o = 7'd13;
+								alu_multicycle_o = 1'b1;
+							end
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd67;
+						10'b0000101100:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd28;
+						10'b0000101101:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd30;
+						10'b0000101110:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd29;
+						10'b0000101111:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd31;
+						10'b0000100100:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd32;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd72;
+						10'b0100100100:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd33;
+						10'b0000100111:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd34;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd73;
+						10'b0100000100:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd5;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd71;
+						10'b0100000110:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd6;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd70;
+						10'b0100000111:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd7;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd69;
+						10'b0010000010:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd19;
+						10'b0010000100:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd20;
+						10'b0010000110:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd21;
+						10'b0100100001:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd47;
+						10'b0010100001:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd46;
+						10'b0110100001:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd48;
+						10'b0100100101:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd49;
+						10'b0100100111:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd52;
+						10'b0110100101:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd15;
+						10'b0010100101:
+							if (RV32B != 32'sd0)
+								alu_operator_o = 7'd16;
+						10'b0000100001:
+							if (RV32B == 32'sd2)
+								alu_operator_o = 7'd17;
+						10'b0000100101:
+							if (RV32B == 32'sd2)
+								alu_operator_o = 7'd18;
+						10'b0000101001:
+							if (RV32B == 32'sd2)
+								alu_operator_o = 7'd53;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd74;
+						10'b0000101010:
+							if (RV32B == 32'sd2)
+								alu_operator_o = 7'd54;
+						10'b0000101011:
+							if (RV32B == 32'sd2)
+								alu_operator_o = 7'd55;
+							else if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd75;
+						10'b0100100110:
+							if (RV32B == 32'sd2) begin
+								alu_operator_o = 7'd51;
+								alu_multicycle_o = 1'b1;
+							end
+						10'b0000100110:
+							if (RV32B == 32'sd2) begin
+								alu_operator_o = 7'd50;
+								alu_multicycle_o = 1'b1;
+							end
+						10'b0010100100:
+							if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd76;
+						10'b0010100010:
+							if (RV32Zk != 32'sd0)
+								alu_operator_o = 7'd77;
+						10'b0101000000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd82;
+						10'b0101001000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd83;
+						10'b0101010000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd84;
+						10'b0101011000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd85;
+						10'b0101110000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd86;
+						10'b0101111000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd87;
+						10'b0010001000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd96;
+						10'b0110001000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd97;
+						10'b1010001000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd98;
+						10'b1110001000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd99;
+						10'b0010011000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd100;
+						10'b0110011000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd101;
+						10'b1010011000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd102;
+						10'b1110011000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd103;
+						10'b0010101000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd88;
+						10'b0110101000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd89;
+						10'b1010101000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd90;
+						10'b1110101000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd91;
+						10'b0010111000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd92;
+						10'b0110111000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd93;
+						10'b1010111000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd94;
+						10'b1110111000:
+							if (RV32Zk == 32'sd2)
+								alu_operator_o = 7'd95;
+						10'b0011000000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd104;
+						10'b0111000000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd105;
+						10'b1011000000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd106;
+						10'b1111000000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd107;
+						10'b0011010000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd108;
+						10'b0111010000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd109;
+						10'b1011010000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd110;
+						10'b1111010000:
+							if (RV32Zk == 32'sd3)
+								alu_operator_o = 7'd111;
+						10'b0000001000: begin
+							alu_operator_o = 7'd0;
+							mult_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001001: begin
+							alu_operator_o = 7'd0;
+							mult_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001010: begin
+							alu_operator_o = 7'd0;
+							mult_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001011: begin
+							alu_operator_o = 7'd0;
+							mult_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001100: begin
+							alu_operator_o = 7'd0;
+							div_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001101: begin
+							alu_operator_o = 7'd0;
+							div_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001110: begin
+							alu_operator_o = 7'd0;
+							div_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						10'b0000001111: begin
+							alu_operator_o = 7'd0;
+							div_sel_o = (RV32M == 32'sd0 ? 1'b0 : 1'b1);
+						end
+						default:
+							;
+					endcase
+			end
+			7'h0b: begin
+				alu_op_a_mux_sel_o = 2'd0;
+				alu_op_b_mux_sel_o = 1'd0;
+			end
+			7'h0f:
+				case (instr_alu[14:12])
+					3'b000: begin
+						alu_operator_o = 7'd0;
+						alu_op_a_mux_sel_o = 2'd0;
+						alu_op_b_mux_sel_o = 1'd1;
+					end
+					3'b001:
+						if (BranchTargetALU) begin
+							bt_a_mux_sel_o = 2'd2;
+							bt_b_mux_sel_o = 3'd5;
+						end
+						else begin
+							alu_op_a_mux_sel_o = 2'd2;
+							alu_op_b_mux_sel_o = 1'd1;
+							imm_b_mux_sel_o = 3'd5;
+							alu_operator_o = 7'd0;
+						end
+					default:
+						;
+				endcase
+			7'h73:
+				if (instr_alu[14:12] == 3'b000) begin
+					alu_op_a_mux_sel_o = 2'd0;
+					alu_op_b_mux_sel_o = 1'd1;
+				end
+				else begin
+					alu_op_b_mux_sel_o = 1'd1;
+					imm_a_mux_sel_o = 1'd0;
+					imm_b_mux_sel_o = 3'd0;
+					if (instr_alu[14])
+						alu_op_a_mux_sel_o = 2'd3;
+					else
+						alu_op_a_mux_sel_o = 2'd0;
+				end
+			default:
+				;
+		endcase
+	end
+	assign eFPGA_int_en_o = (illegal_insn ? 1'b0 : eFPGA_int_en);
+	assign mult_en_o = (illegal_insn ? 1'b0 : mult_sel_o);
+	assign div_en_o = (illegal_insn ? 1'b0 : div_sel_o);
+	assign illegal_insn_o = illegal_insn | illegal_reg_rv32e;
+	assign rf_we_o = rf_we & ~illegal_reg_rv32e;
+	assign unused_instr_alu = {instr_alu[19:15], instr_alu[11:7]};
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_eFPGA.v b/verilog/rtl/ibex_core/ibex_eFPGA.v
new file mode 100644
index 0000000..c201808
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_eFPGA.v
@@ -0,0 +1,66 @@
+module ibex_eFPGA (
+	clk_i,
+	rst_ni,
+	en_i,
+	operator_i,
+	ready_o,
+	endresult_o,
+	result_a_i,
+	result_b_i,
+	result_c_i,
+	delay_i,
+	write_strobe,
+	efpga_done_i
+);
+	input wire clk_i;
+	input wire rst_ni;
+	input wire en_i;
+	input wire [1:0] operator_i;
+	output wire ready_o;
+	output reg [31:0] endresult_o;
+	input wire [31:0] result_a_i;
+	input wire [31:0] result_b_i;
+	input wire [31:0] result_c_i;
+	input wire [3:0] delay_i;
+	output reg write_strobe;
+	input wire efpga_done_i;
+	reg [1:0] eFPGA_fsm_r;
+	reg [3:0] count;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			eFPGA_fsm_r <= 2'd0;
+			count <= 0;
+			write_strobe <= 1'b0;
+		end
+		else
+			case (eFPGA_fsm_r)
+				2'd0: begin
+					count <= 0;
+					if (en_i == 1) begin
+						eFPGA_fsm_r <= 2'd1;
+						if (operator_i == 2'b11)
+							write_strobe <= 1'b1;
+					end
+				end
+				2'd1: begin
+					count <= count + 1;
+					if (((count == delay_i) & (delay_i != 4'b1111)) | ((delay_i == 4'b1111) & efpga_done_i)) begin
+						eFPGA_fsm_r <= 2'd2;
+						case (operator_i)
+							2'b00: endresult_o <= result_a_i;
+							2'b01: endresult_o <= result_b_i;
+							2'b10: endresult_o <= result_c_i;
+							2'b11: begin
+								endresult_o <= result_a_i;
+								write_strobe <= 1'b0;
+							end
+							default: endresult_o <= result_a_i;
+						endcase
+					end
+				end
+				2'd2: eFPGA_fsm_r <= 2'd0;
+				default:
+					;
+			endcase
+	assign ready_o = eFPGA_fsm_r == 2'd2;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_ex_block.v b/verilog/rtl/ibex_core/ibex_ex_block.v
new file mode 100644
index 0000000..ed51409
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_ex_block.v
@@ -0,0 +1,220 @@
+module ibex_ex_block (
+	clk_i,
+	rst_ni,
+	alu_operator_i,
+	alu_operand_a_i,
+	alu_operand_b_i,
+	alu_instr_first_cycle_i,
+	bt_a_operand_i,
+	bt_b_operand_i,
+	eFPGA_en_i,
+	eFPGA_operator_i,
+	eFPGA_result_a_i,
+	eFPGA_result_b_i,
+	eFPGA_result_c_i,
+	eFPGA_delay_i,
+	eFPGA_fpga_done_i,
+	eFPGA_write_strobe_o,
+	multdiv_operator_i,
+	mult_en_i,
+	div_en_i,
+	mult_sel_i,
+	div_sel_i,
+	multdiv_signed_mode_i,
+	multdiv_operand_a_i,
+	multdiv_operand_b_i,
+	multdiv_ready_id_i,
+	data_ind_timing_i,
+	imd_val_we_o,
+	imd_val_d_o,
+	imd_val_q_i,
+	alu_adder_result_ex_o,
+	result_ex_o,
+	branch_target_o,
+	branch_decision_o,
+	ex_valid_o
+);
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd0;
+	parameter [0:0] BranchTargetALU = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [6:0] alu_operator_i;
+	input wire [31:0] alu_operand_a_i;
+	input wire [31:0] alu_operand_b_i;
+	input wire alu_instr_first_cycle_i;
+	input wire [31:0] bt_a_operand_i;
+	input wire [31:0] bt_b_operand_i;
+	input wire eFPGA_en_i;
+	input wire [1:0] eFPGA_operator_i;
+	input wire [31:0] eFPGA_result_a_i;
+	input wire [31:0] eFPGA_result_b_i;
+	input wire [31:0] eFPGA_result_c_i;
+	input wire [3:0] eFPGA_delay_i;
+	input wire eFPGA_fpga_done_i;
+	output wire eFPGA_write_strobe_o;
+	input wire [1:0] multdiv_operator_i;
+	input wire mult_en_i;
+	input wire div_en_i;
+	input wire mult_sel_i;
+	input wire div_sel_i;
+	input wire [1:0] multdiv_signed_mode_i;
+	input wire [31:0] multdiv_operand_a_i;
+	input wire [31:0] multdiv_operand_b_i;
+	input wire multdiv_ready_id_i;
+	input wire data_ind_timing_i;
+	output wire [1:0] imd_val_we_o;
+	output wire [67:0] imd_val_d_o;
+	input wire [67:0] imd_val_q_i;
+	output wire [31:0] alu_adder_result_ex_o;
+	output wire [31:0] result_ex_o;
+	output wire [31:0] branch_target_o;
+	output wire branch_decision_o;
+	output wire ex_valid_o;
+	wire [31:0] alu_result;
+	wire [31:0] zke_result;
+	wire [31:0] multdiv_result;
+	wire [31:0] eFPGA_result;
+	wire [32:0] multdiv_alu_operand_b;
+	wire [32:0] multdiv_alu_operand_a;
+	wire [33:0] alu_adder_result_ext;
+	wire alu_cmp_result;
+	wire alu_is_equal_result;
+	wire zke_val;
+	wire eFPGA_val;
+	wire multdiv_valid;
+	wire multdiv_sel;
+	wire [63:0] alu_imd_val_q;
+	wire [63:0] alu_imd_val_d;
+	wire [1:0] alu_imd_val_we;
+	wire [67:0] multdiv_imd_val_d;
+	wire [1:0] multdiv_imd_val_we;
+	generate
+		if (RV32M != 32'sd0) begin : gen_multdiv_m
+			assign multdiv_sel = mult_sel_i | div_sel_i;
+		end
+		else begin : gen_multdiv_no_m
+			assign multdiv_sel = 1'b0;
+		end
+	endgenerate
+	assign imd_val_d_o[34+:34] = (multdiv_sel ? multdiv_imd_val_d[34+:34] : {2'b00, alu_imd_val_d[32+:32]});
+	assign imd_val_d_o[0+:34] = (multdiv_sel ? multdiv_imd_val_d[0+:34] : {2'b00, alu_imd_val_d[0+:32]});
+	assign imd_val_we_o = (multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we);
+	assign alu_imd_val_q = {imd_val_q_i[65-:32], imd_val_q_i[31-:32]};
+	assign result_ex_o = (multdiv_sel ? multdiv_result : (zke_val ? zke_result : (eFPGA_val ? eFPGA_result : alu_result)));
+	assign branch_decision_o = alu_cmp_result;
+	generate
+		if (BranchTargetALU) begin : g_branch_target_alu
+			wire [32:0] bt_alu_result;
+			wire unused_bt_carry;
+			assign bt_alu_result = bt_a_operand_i + bt_b_operand_i;
+			assign unused_bt_carry = bt_alu_result[32];
+			assign branch_target_o = bt_alu_result[31:0];
+		end
+		else begin : g_no_branch_target_alu
+			wire [31:0] unused_bt_a_operand;
+			wire [31:0] unused_bt_b_operand;
+			assign unused_bt_a_operand = bt_a_operand_i;
+			assign unused_bt_b_operand = bt_b_operand_i;
+			assign branch_target_o = alu_adder_result_ex_o;
+		end
+	endgenerate
+	ibex_alu #(.RV32B(RV32B)) alu_i(
+		.operator_i(alu_operator_i),
+		.operand_a_i(alu_operand_a_i),
+		.operand_b_i(alu_operand_b_i),
+		.instr_first_cycle_i(alu_instr_first_cycle_i),
+		.imd_val_q_i(alu_imd_val_q),
+		.imd_val_we_o(alu_imd_val_we),
+		.imd_val_d_o(alu_imd_val_d),
+		.multdiv_operand_a_i(multdiv_alu_operand_a),
+		.multdiv_operand_b_i(multdiv_alu_operand_b),
+		.multdiv_sel_i(multdiv_sel),
+		.adder_result_o(alu_adder_result_ex_o),
+		.adder_result_ext_o(alu_adder_result_ext),
+		.result_o(alu_result),
+		.comparison_result_o(alu_cmp_result),
+		.is_equal_result_o(alu_is_equal_result)
+	);
+	generate
+		if (RV32Zk != 32'sd0) begin : gen_Zkn
+			ibex_zk #(.RV32Zk(RV32Zk)) zkn_i(
+				.operator_i(alu_operator_i),
+				.operand_a_i(alu_operand_a_i),
+				.operand_b_i(alu_operand_b_i),
+				.result_o(zke_result),
+				.zk_val_o(zke_val)
+			);
+		end
+	endgenerate
+	ibex_eFPGA eFPGA_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.en_i(eFPGA_en_i),
+		.operator_i(eFPGA_operator_i),
+		.ready_o(eFPGA_val),
+		.endresult_o(eFPGA_result),
+		.result_a_i(eFPGA_result_a_i),
+		.result_b_i(eFPGA_result_b_i),
+		.result_c_i(eFPGA_result_c_i),
+		.delay_i(eFPGA_delay_i),
+		.write_strobe(eFPGA_write_strobe_o),
+		.efpga_done_i(eFPGA_fpga_done_i)
+	);
+	generate
+		if (RV32M == 32'sd1) begin : gen_multdiv_slow
+			ibex_multdiv_slow multdiv_i(
+				.clk_i(clk_i),
+				.rst_ni(rst_ni),
+				.mult_en_i(mult_en_i),
+				.div_en_i(div_en_i),
+				.mult_sel_i(mult_sel_i),
+				.div_sel_i(div_sel_i),
+				.operator_i(multdiv_operator_i),
+				.signed_mode_i(multdiv_signed_mode_i),
+				.op_a_i(multdiv_operand_a_i),
+				.op_b_i(multdiv_operand_b_i),
+				.alu_adder_ext_i(alu_adder_result_ext),
+				.alu_adder_i(alu_adder_result_ex_o),
+				.equal_to_zero_i(alu_is_equal_result),
+				.data_ind_timing_i(data_ind_timing_i),
+				.valid_o(multdiv_valid),
+				.alu_operand_a_o(multdiv_alu_operand_a),
+				.alu_operand_b_o(multdiv_alu_operand_b),
+				.imd_val_q_i(imd_val_q_i),
+				.imd_val_d_o(multdiv_imd_val_d),
+				.imd_val_we_o(multdiv_imd_val_we),
+				.multdiv_ready_id_i(multdiv_ready_id_i),
+				.multdiv_result_o(multdiv_result)
+			);
+		end
+		else if ((RV32M == 32'sd2) || (RV32M == 32'sd3)) begin : gen_multdiv_fast
+			ibex_multdiv_fast #(.RV32M(RV32M)) multdiv_i(
+				.clk_i(clk_i),
+				.rst_ni(rst_ni),
+				.mult_en_i(mult_en_i),
+				.div_en_i(div_en_i),
+				.mult_sel_i(mult_sel_i),
+				.div_sel_i(div_sel_i),
+				.operator_i(multdiv_operator_i),
+				.signed_mode_i(multdiv_signed_mode_i),
+				.op_a_i(multdiv_operand_a_i),
+				.op_b_i(multdiv_operand_b_i),
+				.alu_operand_a_o(multdiv_alu_operand_a),
+				.alu_operand_b_o(multdiv_alu_operand_b),
+				.alu_adder_ext_i(alu_adder_result_ext),
+				.alu_adder_i(alu_adder_result_ex_o),
+				.equal_to_zero_i(alu_is_equal_result),
+				.data_ind_timing_i(data_ind_timing_i),
+				.imd_val_q_i(imd_val_q_i),
+				.imd_val_d_o(multdiv_imd_val_d),
+				.imd_val_we_o(multdiv_imd_val_we),
+				.multdiv_ready_id_i(multdiv_ready_id_i),
+				.valid_o(multdiv_valid),
+				.multdiv_result_o(multdiv_result)
+			);
+		end
+	endgenerate
+	assign ex_valid_o = (multdiv_sel ? multdiv_valid : (eFPGA_en_i ? eFPGA_val : ~(|alu_imd_val_we)));
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_fetch_fifo.v b/verilog/rtl/ibex_core/ibex_fetch_fifo.v
new file mode 100644
index 0000000..9ecc882
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_fetch_fifo.v
@@ -0,0 +1,158 @@
+module ibex_fetch_fifo (
+	clk_i,
+	rst_ni,
+	clear_i,
+	busy_o,
+	in_valid_i,
+	in_addr_i,
+	in_rdata_i,
+	in_err_i,
+	out_valid_o,
+	out_ready_i,
+	out_addr_o,
+	out_rdata_o,
+	out_err_o,
+	out_err_plus2_o
+);
+	parameter [31:0] NUM_REQS = 2;
+	parameter [0:0] ResetAll = 1'b0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire clear_i;
+	output wire [NUM_REQS - 1:0] busy_o;
+	input wire in_valid_i;
+	input wire [31:0] in_addr_i;
+	input wire [31:0] in_rdata_i;
+	input wire in_err_i;
+	output reg out_valid_o;
+	input wire out_ready_i;
+	output wire [31:0] out_addr_o;
+	output reg [31:0] out_rdata_o;
+	output reg out_err_o;
+	output reg out_err_plus2_o;
+	localparam [31:0] DEPTH = NUM_REQS + 1;
+	wire [(DEPTH * 32) - 1:0] rdata_d;
+	reg [(DEPTH * 32) - 1:0] rdata_q;
+	wire [DEPTH - 1:0] err_d;
+	reg [DEPTH - 1:0] err_q;
+	wire [DEPTH - 1:0] valid_d;
+	reg [DEPTH - 1:0] valid_q;
+	wire [DEPTH - 1:0] lowest_free_entry;
+	wire [DEPTH - 1:0] valid_pushed;
+	wire [DEPTH - 1:0] valid_popped;
+	wire [DEPTH - 1:0] entry_en;
+	wire pop_fifo;
+	wire [31:0] rdata;
+	wire [31:0] rdata_unaligned;
+	wire err;
+	wire err_unaligned;
+	wire err_plus2;
+	wire valid;
+	wire valid_unaligned;
+	wire aligned_is_compressed;
+	wire unaligned_is_compressed;
+	wire addr_incr_two;
+	wire [31:1] instr_addr_next;
+	wire [31:1] instr_addr_d;
+	reg [31:1] instr_addr_q;
+	wire instr_addr_en;
+	wire unused_addr_in;
+	assign rdata = (valid_q[0] ? rdata_q[0+:32] : in_rdata_i);
+	assign err = (valid_q[0] ? err_q[0] : in_err_i);
+	assign valid = valid_q[0] | in_valid_i;
+	assign rdata_unaligned = (valid_q[1] ? {rdata_q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]});
+	assign err_unaligned = (valid_q[1] ? (err_q[1] & ~unaligned_is_compressed) | err_q[0] : (valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));
+	assign err_plus2 = (valid_q[1] ? err_q[1] & ~err_q[0] : (in_err_i & valid_q[0]) & ~err_q[0]);
+	assign valid_unaligned = (valid_q[1] ? 1'b1 : valid_q[0] & in_valid_i);
+	assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err;
+	assign aligned_is_compressed = (rdata[1:0] != 2'b11) & ~err;
+	always @(*)
+		if (out_addr_o[1]) begin
+			out_rdata_o = rdata_unaligned;
+			out_err_o = err_unaligned;
+			out_err_plus2_o = err_plus2;
+			if (unaligned_is_compressed)
+				out_valid_o = valid;
+			else
+				out_valid_o = valid_unaligned;
+		end
+		else begin
+			out_rdata_o = rdata;
+			out_err_o = err;
+			out_err_plus2_o = 1'b0;
+			out_valid_o = valid;
+		end
+	assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);
+	assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed);
+	assign instr_addr_next = instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two};
+	assign instr_addr_d = (clear_i ? in_addr_i[31:1] : instr_addr_next);
+	generate
+		if (ResetAll) begin : g_instr_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					instr_addr_q <= 1'sb0;
+				else if (instr_addr_en)
+					instr_addr_q <= instr_addr_d;
+		end
+		else begin : g_instr_addr_nr
+			always @(posedge clk_i)
+				if (instr_addr_en)
+					instr_addr_q <= instr_addr_d;
+		end
+	endgenerate
+	assign out_addr_o = {instr_addr_q, 1'b0};
+	assign unused_addr_in = in_addr_i[0];
+	assign busy_o = valid_q[DEPTH - 1:DEPTH - NUM_REQS];
+	assign pop_fifo = (out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]);
+	genvar i;
+	generate
+		for (i = 0; i < (DEPTH - 1); i = i + 1) begin : g_fifo_next
+			if (i == 0) begin : g_ent0
+				assign lowest_free_entry[i] = ~valid_q[i];
+			end
+			else begin : g_ent_others
+				assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i - 1];
+			end
+			assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | valid_q[i];
+			assign valid_popped[i] = (pop_fifo ? valid_pushed[i + 1] : valid_pushed[i]);
+			assign valid_d[i] = valid_popped[i] & ~clear_i;
+			assign entry_en[i] = (valid_pushed[i + 1] & pop_fifo) | ((in_valid_i & lowest_free_entry[i]) & ~pop_fifo);
+			assign rdata_d[i * 32+:32] = (valid_q[i + 1] ? rdata_q[(i + 1) * 32+:32] : in_rdata_i);
+			assign err_d[i] = (valid_q[i + 1] ? err_q[i + 1] : in_err_i);
+		end
+	endgenerate
+	assign lowest_free_entry[DEPTH - 1] = ~valid_q[DEPTH - 1] & valid_q[DEPTH - 2];
+	assign valid_pushed[DEPTH - 1] = valid_q[DEPTH - 1] | (in_valid_i & lowest_free_entry[DEPTH - 1]);
+	assign valid_popped[DEPTH - 1] = (pop_fifo ? 1'b0 : valid_pushed[DEPTH - 1]);
+	assign valid_d[DEPTH - 1] = valid_popped[DEPTH - 1] & ~clear_i;
+	assign entry_en[DEPTH - 1] = in_valid_i & lowest_free_entry[DEPTH - 1];
+	assign rdata_d[(DEPTH - 1) * 32+:32] = in_rdata_i;
+	assign err_d[DEPTH - 1] = in_err_i;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			valid_q <= 1'sb0;
+		else
+			valid_q <= valid_d;
+	generate
+		for (i = 0; i < DEPTH; i = i + 1) begin : g_fifo_regs
+			if (ResetAll) begin : g_rdata_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni) begin
+						rdata_q[i * 32+:32] <= 1'sb0;
+						err_q[i] <= 1'sb0;
+					end
+					else if (entry_en[i]) begin
+						rdata_q[i * 32+:32] <= rdata_d[i * 32+:32];
+						err_q[i] <= err_d[i];
+					end
+			end
+			else begin : g_rdata_nr
+				always @(posedge clk_i)
+					if (entry_en[i]) begin
+						rdata_q[i * 32+:32] <= rdata_d[i * 32+:32];
+						err_q[i] <= err_d[i];
+					end
+			end
+		end
+	endgenerate
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_icache.v b/verilog/rtl/ibex_core/ibex_icache.v
new file mode 100644
index 0000000..fc2ad5c
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_icache.v
@@ -0,0 +1,769 @@
+module ibex_icache (
+	clk_i,
+	rst_ni,
+	req_i,
+	branch_i,
+	branch_spec_i,
+	branch_mispredict_i,
+	mispredict_addr_i,
+	addr_i,
+	ready_i,
+	valid_o,
+	rdata_o,
+	addr_o,
+	err_o,
+	err_plus2_o,
+	instr_req_o,
+	instr_gnt_i,
+	instr_addr_o,
+	instr_rdata_i,
+	instr_err_i,
+	instr_pmp_err_i,
+	instr_rvalid_i,
+	ic_tag_req_o,
+	ic_tag_write_o,
+	ic_tag_addr_o,
+	ic_tag_wdata_o,
+	ic_tag_rdata_i,
+	ic_data_req_o,
+	ic_data_write_o,
+	ic_data_addr_o,
+	ic_data_wdata_o,
+	ic_data_rdata_i,
+	icache_enable_i,
+	icache_inval_i,
+	busy_o
+);
+	parameter [0:0] ICacheECC = 1'b0;
+	parameter [0:0] ResetAll = 1'b0;
+	localparam [31:0] ibex_pkg_BUS_SIZE = 32;
+	parameter [31:0] BusSizeECC = ibex_pkg_BUS_SIZE;
+	localparam [31:0] ibex_pkg_ADDR_W = 32;
+	localparam [31:0] ibex_pkg_IC_LINE_SIZE = 64;
+	localparam [31:0] ibex_pkg_IC_LINE_BYTES = 8;
+	localparam [31:0] ibex_pkg_IC_NUM_WAYS = 2;
+	localparam [31:0] ibex_pkg_IC_SIZE_BYTES = 4096;
+	localparam [31:0] ibex_pkg_IC_NUM_LINES = (ibex_pkg_IC_SIZE_BYTES / ibex_pkg_IC_NUM_WAYS) / ibex_pkg_IC_LINE_BYTES;
+	localparam [31:0] ibex_pkg_IC_INDEX_W = $clog2(ibex_pkg_IC_NUM_LINES);
+	localparam [31:0] ibex_pkg_IC_LINE_W = 3;
+	localparam [31:0] ibex_pkg_IC_TAG_SIZE = ((ibex_pkg_ADDR_W - ibex_pkg_IC_INDEX_W) - ibex_pkg_IC_LINE_W) + 1;
+	parameter [31:0] TagSizeECC = ibex_pkg_IC_TAG_SIZE;
+	parameter [31:0] LineSizeECC = ibex_pkg_IC_LINE_SIZE;
+	parameter [0:0] BranchCache = 1'b0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire req_i;
+	input wire branch_i;
+	input wire branch_spec_i;
+	input wire branch_mispredict_i;
+	input wire [31:0] mispredict_addr_i;
+	input wire [31:0] addr_i;
+	input wire ready_i;
+	output wire valid_o;
+	output wire [31:0] rdata_o;
+	output wire [31:0] addr_o;
+	output wire err_o;
+	output wire err_plus2_o;
+	output wire instr_req_o;
+	input wire instr_gnt_i;
+	output wire [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	input wire instr_err_i;
+	input wire instr_pmp_err_i;
+	input wire instr_rvalid_i;
+	output wire [1:0] ic_tag_req_o;
+	output wire ic_tag_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_tag_addr_o;
+	output wire [TagSizeECC - 1:0] ic_tag_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] ic_tag_rdata_i;
+	output wire [1:0] ic_data_req_o;
+	output wire ic_data_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_data_addr_o;
+	output wire [LineSizeECC - 1:0] ic_data_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] ic_data_rdata_i;
+	input wire icache_enable_i;
+	input wire icache_inval_i;
+	output wire busy_o;
+	localparam [31:0] NUM_FB = 4;
+	localparam [31:0] FB_THRESHOLD = 2;
+	wire [31:0] lookup_addr_aligned;
+	wire [31:0] prefetch_addr_d;
+	reg [31:0] prefetch_addr_q;
+	wire prefetch_addr_en;
+	wire branch_or_mispredict;
+	wire branch_suppress;
+	wire lookup_throttle;
+	wire lookup_req_ic0;
+	wire [31:0] lookup_addr_ic0;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] lookup_index_ic0;
+	wire fill_req_ic0;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] fill_index_ic0;
+	wire [ibex_pkg_IC_TAG_SIZE - 1:0] fill_tag_ic0;
+	wire [63:0] fill_wdata_ic0;
+	wire lookup_grant_ic0;
+	wire lookup_actual_ic0;
+	wire fill_grant_ic0;
+	wire tag_req_ic0;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] tag_index_ic0;
+	wire [1:0] tag_banks_ic0;
+	wire tag_write_ic0;
+	wire [TagSizeECC - 1:0] tag_wdata_ic0;
+	wire data_req_ic0;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] data_index_ic0;
+	wire [1:0] data_banks_ic0;
+	wire data_write_ic0;
+	wire [LineSizeECC - 1:0] data_wdata_ic0;
+	wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] tag_rdata_ic1;
+	wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] data_rdata_ic1;
+	reg [LineSizeECC - 1:0] hit_data_ecc_ic1;
+	wire [63:0] hit_data_ic1;
+	reg lookup_valid_ic1;
+	localparam [31:0] ibex_pkg_IC_INDEX_HI = (ibex_pkg_IC_INDEX_W + ibex_pkg_IC_LINE_W) - 1;
+	reg [31:ibex_pkg_IC_INDEX_HI + 1] lookup_addr_ic1;
+	wire [1:0] tag_match_ic1;
+	wire tag_hit_ic1;
+	wire [1:0] tag_invalid_ic1;
+	wire [1:0] lowest_invalid_way_ic1;
+	wire [1:0] round_robin_way_ic1;
+	reg [1:0] round_robin_way_q;
+	wire [1:0] sel_way_ic1;
+	wire ecc_err_ic1;
+	wire ecc_write_req;
+	wire [1:0] ecc_write_ways;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] ecc_write_index;
+	wire gnt_or_pmp_err;
+	wire gnt_not_pmp_err;
+	reg [1:0] fb_fill_level;
+	wire fill_cache_new;
+	wire fill_new_alloc;
+	wire fill_spec_req;
+	wire fill_spec_done;
+	wire fill_spec_hold;
+	wire [(NUM_FB * NUM_FB) - 1:0] fill_older_d;
+	reg [(NUM_FB * NUM_FB) - 1:0] fill_older_q;
+	wire [3:0] fill_alloc_sel;
+	wire [3:0] fill_alloc;
+	wire [3:0] fill_busy_d;
+	reg [3:0] fill_busy_q;
+	wire [3:0] fill_done;
+	reg [3:0] fill_in_ic1;
+	wire [3:0] fill_stale_d;
+	reg [3:0] fill_stale_q;
+	wire [3:0] fill_cache_d;
+	reg [3:0] fill_cache_q;
+	wire [3:0] fill_hit_ic1;
+	wire [3:0] fill_hit_d;
+	reg [3:0] fill_hit_q;
+	localparam [31:0] ibex_pkg_BUS_BYTES = 4;
+	localparam [31:0] ibex_pkg_IC_LINE_BEATS = ibex_pkg_IC_LINE_BYTES / ibex_pkg_BUS_BYTES;
+	localparam [31:0] ibex_pkg_IC_LINE_BEATS_W = $clog2(ibex_pkg_IC_LINE_BEATS);
+	wire [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_ext_cnt_d;
+	reg [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_ext_cnt_q;
+	wire [3:0] fill_ext_hold_d;
+	reg [3:0] fill_ext_hold_q;
+	wire [3:0] fill_ext_done_d;
+	reg [3:0] fill_ext_done_q;
+	wire [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_rvd_cnt_d;
+	reg [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_rvd_cnt_q;
+	wire [3:0] fill_rvd_done;
+	wire [3:0] fill_ram_done_d;
+	reg [3:0] fill_ram_done_q;
+	wire [3:0] fill_out_grant;
+	wire [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_out_cnt_d;
+	reg [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_out_cnt_q;
+	wire [3:0] fill_out_done;
+	wire [3:0] fill_ext_req;
+	wire [3:0] fill_rvd_exp;
+	wire [3:0] fill_ram_req;
+	wire [3:0] fill_out_req;
+	wire [3:0] fill_data_sel;
+	wire [3:0] fill_data_reg;
+	wire [3:0] fill_data_hit;
+	wire [3:0] fill_data_rvd;
+	wire [(NUM_FB * ibex_pkg_IC_LINE_BEATS_W) - 1:0] fill_ext_off;
+	wire [(NUM_FB * ibex_pkg_IC_LINE_BEATS_W) - 1:0] fill_rvd_off;
+	wire [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_ext_beat;
+	wire [(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (NUM_FB * (ibex_pkg_IC_LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W - 1)):(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W)] fill_rvd_beat;
+	wire [3:0] fill_ext_arb;
+	wire [3:0] fill_ram_arb;
+	wire [3:0] fill_out_arb;
+	wire [3:0] fill_rvd_arb;
+	wire [3:0] fill_entry_en;
+	wire [3:0] fill_addr_en;
+	wire [3:0] fill_way_en;
+	wire [(NUM_FB * ibex_pkg_IC_LINE_BEATS) - 1:0] fill_data_en;
+	wire [(NUM_FB * ibex_pkg_IC_LINE_BEATS) - 1:0] fill_err_d;
+	reg [(NUM_FB * ibex_pkg_IC_LINE_BEATS) - 1:0] fill_err_q;
+	reg [31:0] fill_addr_q [0:3];
+	reg [1:0] fill_way_q [0:3];
+	wire [63:0] fill_data_d [0:3];
+	reg [63:0] fill_data_q [0:3];
+	localparam [31:0] ibex_pkg_BUS_W = 2;
+	reg [31:ibex_pkg_BUS_W] fill_ext_req_addr;
+	reg [31:0] fill_ram_req_addr;
+	reg [1:0] fill_ram_req_way;
+	reg [63:0] fill_ram_req_data;
+	reg [63:0] fill_out_data;
+	reg [ibex_pkg_IC_LINE_BEATS - 1:0] fill_out_err;
+	wire instr_req;
+	wire [31:ibex_pkg_BUS_W] instr_addr;
+	wire skid_complete_instr;
+	wire skid_ready;
+	wire output_compressed;
+	wire skid_valid_d;
+	reg skid_valid_q;
+	wire skid_en;
+	wire [15:0] skid_data_d;
+	reg [15:0] skid_data_q;
+	reg skid_err_q;
+	wire output_valid;
+	wire addr_incr_two;
+	wire output_addr_en;
+	wire [31:1] output_addr_incr;
+	wire [31:1] output_addr_d;
+	reg [31:1] output_addr_q;
+	reg [15:0] output_data_lo;
+	reg [15:0] output_data_hi;
+	wire data_valid;
+	wire output_ready;
+	wire [63:0] line_data;
+	wire [ibex_pkg_IC_LINE_BEATS - 1:0] line_err;
+	reg [31:0] line_data_muxed;
+	reg line_err_muxed;
+	wire [31:0] output_data;
+	wire output_err;
+	wire start_inval;
+	wire inval_done;
+	reg reset_inval_q;
+	wire inval_prog_d;
+	reg inval_prog_q;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] inval_index_d;
+	reg [ibex_pkg_IC_INDEX_W - 1:0] inval_index_q;
+	assign branch_or_mispredict = branch_i | branch_mispredict_i;
+	assign lookup_addr_aligned = {lookup_addr_ic0[31:ibex_pkg_IC_LINE_W], {ibex_pkg_IC_LINE_W {1'b0}}};
+	assign prefetch_addr_d = (lookup_grant_ic0 ? lookup_addr_aligned + {{(ibex_pkg_ADDR_W - ibex_pkg_IC_LINE_W) - 1 {1'b0}}, 1'b1, {ibex_pkg_IC_LINE_W {1'b0}}} : (branch_i ? addr_i : mispredict_addr_i));
+	assign prefetch_addr_en = branch_or_mispredict | lookup_grant_ic0;
+	generate
+		if (ResetAll) begin : g_prefetch_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					prefetch_addr_q <= 1'sb0;
+				else if (prefetch_addr_en)
+					prefetch_addr_q <= prefetch_addr_d;
+		end
+		else begin : g_prefetch_addr_nr
+			always @(posedge clk_i)
+				if (prefetch_addr_en)
+					prefetch_addr_q <= prefetch_addr_d;
+		end
+	endgenerate
+	assign lookup_throttle = fb_fill_level > FB_THRESHOLD[1:0];
+	assign lookup_req_ic0 = ((req_i & ~&fill_busy_q) & (branch_or_mispredict | ~lookup_throttle)) & ~ecc_write_req;
+	assign lookup_addr_ic0 = (branch_spec_i ? addr_i : (branch_mispredict_i ? mispredict_addr_i : prefetch_addr_q));
+	assign lookup_index_ic0 = lookup_addr_ic0[ibex_pkg_IC_INDEX_HI:ibex_pkg_IC_LINE_W];
+	assign fill_req_ic0 = |fill_ram_req;
+	assign fill_index_ic0 = fill_ram_req_addr[ibex_pkg_IC_INDEX_HI:ibex_pkg_IC_LINE_W];
+	assign fill_tag_ic0 = {~inval_prog_q & ~ecc_write_req, fill_ram_req_addr[31:ibex_pkg_IC_INDEX_HI + 1]};
+	assign fill_wdata_ic0 = fill_ram_req_data;
+	assign branch_suppress = branch_spec_i & ~branch_i;
+	assign lookup_grant_ic0 = lookup_req_ic0 & ~branch_suppress;
+	assign fill_grant_ic0 = ((fill_req_ic0 & (~lookup_req_ic0 | branch_suppress)) & ~inval_prog_q) & ~ecc_write_req;
+	assign lookup_actual_ic0 = ((lookup_grant_ic0 & icache_enable_i) & ~inval_prog_q) & ~start_inval;
+	assign tag_req_ic0 = ((lookup_req_ic0 | fill_req_ic0) | inval_prog_q) | ecc_write_req;
+	assign tag_index_ic0 = (inval_prog_q ? inval_index_q : (ecc_write_req ? ecc_write_index : (fill_grant_ic0 ? fill_index_ic0 : lookup_index_ic0)));
+	assign tag_banks_ic0 = (ecc_write_req ? ecc_write_ways : (fill_grant_ic0 ? fill_ram_req_way : {ibex_pkg_IC_NUM_WAYS {1'b1}}));
+	assign tag_write_ic0 = (fill_grant_ic0 | inval_prog_q) | ecc_write_req;
+	assign data_req_ic0 = lookup_req_ic0 | fill_req_ic0;
+	assign data_index_ic0 = tag_index_ic0;
+	assign data_banks_ic0 = tag_banks_ic0;
+	assign data_write_ic0 = tag_write_ic0;
+	generate
+		if (ICacheECC) begin : gen_ecc_wdata
+			wire [21:0] tag_ecc_input_padded;
+			wire [27:0] tag_ecc_output_padded;
+			wire [22 - ibex_pkg_IC_TAG_SIZE:0] tag_ecc_output_unused;
+			assign tag_ecc_input_padded = {{22 - ibex_pkg_IC_TAG_SIZE {1'b0}}, fill_tag_ic0};
+			assign tag_ecc_output_unused = tag_ecc_output_padded[21:ibex_pkg_IC_TAG_SIZE - 1];
+			prim_secded_28_22_enc tag_ecc_enc(
+				.data_i(tag_ecc_input_padded),
+				.data_o(tag_ecc_output_padded)
+			);
+			assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22], tag_ecc_output_padded[ibex_pkg_IC_TAG_SIZE - 1:0]};
+			genvar bank;
+			for (bank = 0; bank < ibex_pkg_IC_LINE_BEATS; bank = bank + 1) begin : gen_ecc_banks
+				prim_secded_39_32_enc data_ecc_enc(
+					.data_i(fill_wdata_ic0[bank * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE]),
+					.data_o(data_wdata_ic0[bank * BusSizeECC+:BusSizeECC])
+				);
+			end
+		end
+		else begin : gen_noecc_wdata
+			assign tag_wdata_ic0 = fill_tag_ic0;
+			assign data_wdata_ic0 = fill_wdata_ic0;
+		end
+	endgenerate
+	assign ic_tag_req_o = {ibex_pkg_IC_NUM_WAYS {tag_req_ic0}} & tag_banks_ic0;
+	assign ic_tag_write_o = tag_write_ic0;
+	assign ic_tag_addr_o = tag_index_ic0;
+	assign ic_tag_wdata_o = tag_wdata_ic0;
+	assign tag_rdata_ic1 = ic_tag_rdata_i;
+	assign ic_data_req_o = {ibex_pkg_IC_NUM_WAYS {data_req_ic0}} & data_banks_ic0;
+	assign ic_data_write_o = data_write_ic0;
+	assign ic_data_addr_o = data_index_ic0;
+	assign ic_data_wdata_o = data_wdata_ic0;
+	assign data_rdata_ic1 = ic_data_rdata_i;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			lookup_valid_ic1 <= 1'b0;
+		else
+			lookup_valid_ic1 <= lookup_actual_ic0;
+	generate
+		if (ResetAll) begin : g_lookup_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni) begin
+					lookup_addr_ic1 <= 1'sb0;
+					fill_in_ic1 <= 1'sb0;
+				end
+				else if (lookup_grant_ic0) begin
+					lookup_addr_ic1 <= lookup_addr_ic0[31:ibex_pkg_IC_INDEX_HI + 1];
+					fill_in_ic1 <= fill_alloc_sel;
+				end
+		end
+		else begin : g_lookup_addr_nr
+			always @(posedge clk_i)
+				if (lookup_grant_ic0) begin
+					lookup_addr_ic1 <= lookup_addr_ic0[31:ibex_pkg_IC_INDEX_HI + 1];
+					fill_in_ic1 <= fill_alloc_sel;
+				end
+		end
+	endgenerate
+	genvar way;
+	generate
+		for (way = 0; way < ibex_pkg_IC_NUM_WAYS; way = way + 1) begin : gen_tag_match
+			assign tag_match_ic1[way] = tag_rdata_ic1[((1 - way) * TagSizeECC) + (ibex_pkg_IC_TAG_SIZE - 1)-:ibex_pkg_IC_TAG_SIZE] == {1'b1, lookup_addr_ic1[31:ibex_pkg_IC_INDEX_HI + 1]};
+			assign tag_invalid_ic1[way] = ~tag_rdata_ic1[((1 - way) * TagSizeECC) + (ibex_pkg_IC_TAG_SIZE - 1)];
+		end
+	endgenerate
+	assign tag_hit_ic1 = |tag_match_ic1;
+	always @(*) begin
+		hit_data_ecc_ic1 = 'b0;
+		begin : sv2v_autoblock_1
+			reg signed [31:0] way;
+			for (way = 0; way < ibex_pkg_IC_NUM_WAYS; way = way + 1)
+				if (tag_match_ic1[way])
+					hit_data_ecc_ic1 = hit_data_ecc_ic1 | data_rdata_ic1[(1 - way) * LineSizeECC+:LineSizeECC];
+		end
+	end
+	assign lowest_invalid_way_ic1[0] = tag_invalid_ic1[0];
+	assign round_robin_way_ic1[0] = round_robin_way_q[1];
+	generate
+		for (way = 1; way < ibex_pkg_IC_NUM_WAYS; way = way + 1) begin : gen_lowest_way
+			assign lowest_invalid_way_ic1[way] = tag_invalid_ic1[way] & ~|tag_invalid_ic1[way - 1:0];
+			assign round_robin_way_ic1[way] = round_robin_way_q[way - 1];
+		end
+	endgenerate
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			round_robin_way_q <= 2'b01;
+		else if (lookup_valid_ic1)
+			round_robin_way_q <= round_robin_way_ic1;
+	assign sel_way_ic1 = (|tag_invalid_ic1 ? lowest_invalid_way_ic1 : round_robin_way_q);
+	generate
+		if (ICacheECC) begin : gen_data_ecc_checking
+			wire [1:0] tag_err_ic1;
+			wire [(ibex_pkg_IC_LINE_BEATS * 2) - 1:0] data_err_ic1;
+			wire ecc_correction_write_d;
+			reg ecc_correction_write_q;
+			wire [1:0] ecc_correction_ways_d;
+			reg [1:0] ecc_correction_ways_q;
+			reg [ibex_pkg_IC_INDEX_W - 1:0] lookup_index_ic1;
+			reg [ibex_pkg_IC_INDEX_W - 1:0] ecc_correction_index_q;
+			genvar way;
+			for (way = 0; way < ibex_pkg_IC_NUM_WAYS; way = way + 1) begin : gen_tag_ecc
+				wire [1:0] tag_err_bank_ic1;
+				wire [27:0] tag_rdata_padded_ic1;
+				assign tag_rdata_padded_ic1 = {tag_rdata_ic1[((1 - way) * TagSizeECC) + (TagSizeECC - 1)-:6], {22 - ibex_pkg_IC_TAG_SIZE {1'b0}}, tag_rdata_ic1[((1 - way) * TagSizeECC) + (ibex_pkg_IC_TAG_SIZE - 1)-:ibex_pkg_IC_TAG_SIZE]};
+				prim_secded_28_22_dec data_ecc_dec(
+					.data_i(tag_rdata_padded_ic1),
+					.data_o(),
+					.syndrome_o(),
+					.err_o(tag_err_bank_ic1)
+				);
+				assign tag_err_ic1[way] = |tag_err_bank_ic1;
+			end
+			genvar bank;
+			for (bank = 0; bank < ibex_pkg_IC_LINE_BEATS; bank = bank + 1) begin : gen_ecc_banks
+				prim_secded_39_32_dec data_ecc_dec(
+					.data_i(hit_data_ecc_ic1[bank * BusSizeECC+:BusSizeECC]),
+					.data_o(),
+					.syndrome_o(),
+					.err_o(data_err_ic1[bank * 2+:2])
+				);
+				assign hit_data_ic1[bank * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE] = hit_data_ecc_ic1[bank * BusSizeECC+:ibex_pkg_BUS_SIZE];
+			end
+			assign ecc_err_ic1 = lookup_valid_ic1 & (|data_err_ic1 | |tag_err_ic1);
+			assign ecc_correction_ways_d = {ibex_pkg_IC_NUM_WAYS {|tag_err_ic1}} | (tag_match_ic1 & {ibex_pkg_IC_NUM_WAYS {|data_err_ic1}});
+			assign ecc_correction_write_d = ecc_err_ic1;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					ecc_correction_write_q <= 1'b0;
+				else
+					ecc_correction_write_q <= ecc_correction_write_d;
+			if (ResetAll) begin : g_lookup_ind_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni)
+						lookup_index_ic1 <= 1'sb0;
+					else if (lookup_grant_ic0)
+						lookup_index_ic1 <= lookup_addr_ic0[ibex_pkg_IC_INDEX_HI-:ibex_pkg_IC_INDEX_W];
+			end
+			else begin : g_lookup_ind_nr
+				always @(posedge clk_i)
+					if (lookup_grant_ic0)
+						lookup_index_ic1 <= lookup_addr_ic0[ibex_pkg_IC_INDEX_HI-:ibex_pkg_IC_INDEX_W];
+			end
+			if (ResetAll) begin : g_ecc_correction_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni) begin
+						ecc_correction_ways_q <= 1'sb0;
+						ecc_correction_index_q <= 1'sb0;
+					end
+					else if (ecc_err_ic1) begin
+						ecc_correction_ways_q <= ecc_correction_ways_d;
+						ecc_correction_index_q <= lookup_index_ic1;
+					end
+			end
+			else begin : g_ecc_correction_nr
+				always @(posedge clk_i)
+					if (ecc_err_ic1) begin
+						ecc_correction_ways_q <= ecc_correction_ways_d;
+						ecc_correction_index_q <= lookup_index_ic1;
+					end
+			end
+			assign ecc_write_req = ecc_correction_write_q;
+			assign ecc_write_ways = ecc_correction_ways_q;
+			assign ecc_write_index = ecc_correction_index_q;
+		end
+		else begin : gen_no_data_ecc
+			assign ecc_err_ic1 = 1'b0;
+			assign ecc_write_req = 1'b0;
+			assign ecc_write_ways = 1'sb0;
+			assign ecc_write_index = 1'sb0;
+			assign hit_data_ic1 = hit_data_ecc_ic1;
+		end
+		if (BranchCache) begin : gen_caching_logic
+			localparam [31:0] CACHE_AHEAD = 2;
+			localparam [31:0] CACHE_CNT_W = 2;
+			wire cache_cnt_dec;
+			wire [1:0] cache_cnt_d;
+			reg [1:0] cache_cnt_q;
+			assign cache_cnt_dec = lookup_grant_ic0 & |cache_cnt_q;
+			assign cache_cnt_d = (branch_i ? CACHE_AHEAD[1:0] : cache_cnt_q - {1'b0, cache_cnt_dec});
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					cache_cnt_q <= 1'sb0;
+				else
+					cache_cnt_q <= cache_cnt_d;
+			assign fill_cache_new = (((branch_i | |cache_cnt_q) & icache_enable_i) & ~icache_inval_i) & ~inval_prog_q;
+		end
+		else begin : gen_cache_all
+			assign fill_cache_new = (icache_enable_i & ~start_inval) & ~inval_prog_q;
+		end
+	endgenerate
+	always @(*) begin
+		fb_fill_level = 1'sb0;
+		begin : sv2v_autoblock_2
+			reg signed [31:0] i;
+			for (i = 0; i < NUM_FB; i = i + 1)
+				if (fill_busy_q[i] & ~fill_stale_q[i])
+					fb_fill_level = fb_fill_level + 2'b01;
+		end
+	end
+	assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i;
+	assign gnt_not_pmp_err = instr_gnt_i & ~instr_pmp_err_i;
+	assign fill_new_alloc = lookup_grant_ic0;
+	assign fill_spec_req = (~icache_enable_i | branch_or_mispredict) & ~|fill_ext_req;
+	assign fill_spec_done = fill_spec_req & gnt_not_pmp_err;
+	assign fill_spec_hold = fill_spec_req & ~gnt_or_pmp_err;
+	genvar fb;
+	generate
+		for (fb = 0; fb < NUM_FB; fb = fb + 1) begin : gen_fbs
+			if (fb == 0) begin : gen_fb_zero
+				assign fill_alloc_sel[fb] = ~fill_busy_q[fb];
+			end
+			else begin : gen_fb_rest
+				assign fill_alloc_sel[fb] = ~fill_busy_q[fb] & &fill_busy_q[fb - 1:0];
+			end
+			assign fill_alloc[fb] = fill_alloc_sel[fb] & fill_new_alloc;
+			assign fill_busy_d[fb] = fill_alloc[fb] | (fill_busy_q[fb] & ~fill_done[fb]);
+			assign fill_older_d[fb * NUM_FB+:NUM_FB] = (fill_alloc[fb] ? fill_busy_q : fill_older_q[fb * NUM_FB+:NUM_FB]) & ~fill_done;
+			assign fill_done[fb] = ((((fill_ram_done_q[fb] | fill_hit_q[fb]) | ~fill_cache_q[fb]) | |fill_err_q[fb * ibex_pkg_IC_LINE_BEATS+:ibex_pkg_IC_LINE_BEATS]) & ((fill_out_done[fb] | fill_stale_q[fb]) | branch_or_mispredict)) & fill_rvd_done[fb];
+			assign fill_stale_d[fb] = fill_busy_q[fb] & (branch_or_mispredict | fill_stale_q[fb]);
+			assign fill_cache_d[fb] = (fill_alloc[fb] & fill_cache_new) | (((fill_cache_q[fb] & fill_busy_q[fb]) & icache_enable_i) & ~icache_inval_i);
+			assign fill_hit_ic1[fb] = ((lookup_valid_ic1 & fill_in_ic1[fb]) & tag_hit_ic1) & ~ecc_err_ic1;
+			assign fill_hit_d[fb] = fill_hit_ic1[fb] | (fill_hit_q[fb] & fill_busy_q[fb]);
+			assign fill_ext_req[fb] = fill_busy_q[fb] & ~fill_ext_done_d[fb];
+			assign fill_ext_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] = (fill_alloc[fb] ? {{ibex_pkg_IC_LINE_BEATS_W {1'b0}}, fill_spec_done} : fill_ext_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] + {{ibex_pkg_IC_LINE_BEATS_W {1'b0}}, fill_ext_arb[fb] & gnt_not_pmp_err});
+			assign fill_ext_hold_d[fb] = (fill_alloc[fb] & fill_spec_hold) | (fill_ext_arb[fb] & ~gnt_or_pmp_err);
+			assign fill_ext_done_d[fb] = (((((fill_ext_cnt_q[(fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : ibex_pkg_IC_LINE_BEATS_W - ibex_pkg_IC_LINE_BEATS_W)] | fill_hit_ic1[fb]) | fill_hit_q[fb]) | fill_err_q[(fb * ibex_pkg_IC_LINE_BEATS) + fill_ext_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W]]) | (~fill_cache_q[fb] & ((branch_or_mispredict | fill_stale_q[fb]) | fill_ext_beat[(fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : ibex_pkg_IC_LINE_BEATS_W - ibex_pkg_IC_LINE_BEATS_W)]))) & ~fill_ext_hold_q[fb]) & fill_busy_q[fb];
+			assign fill_rvd_exp[fb] = fill_busy_q[fb] & ~fill_rvd_done[fb];
+			assign fill_rvd_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] = (fill_alloc[fb] ? {(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W) {1'sb0}} : fill_rvd_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] + {{ibex_pkg_IC_LINE_BEATS_W {1'b0}}, fill_rvd_arb[fb]});
+			assign fill_rvd_done[fb] = (fill_ext_done_q[fb] & ~fill_ext_hold_q[fb]) & (fill_rvd_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] == fill_ext_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)]);
+			assign fill_out_req[fb] = ((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & ((((fill_hit_ic1[fb] | fill_hit_q[fb]) | fill_err_q[(fb * ibex_pkg_IC_LINE_BEATS) + fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1)) : (((fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1))) + ibex_pkg_IC_LINE_BEATS_W) - 1)-:ibex_pkg_IC_LINE_BEATS_W]]) | (fill_rvd_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] > fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)])) | fill_rvd_arb[fb]);
+			assign fill_out_grant[fb] = fill_out_arb[fb] & output_ready;
+			assign fill_out_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] = (fill_alloc[fb] ? {1'b0, lookup_addr_ic0[2:ibex_pkg_BUS_W]} : fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] + {{ibex_pkg_IC_LINE_BEATS_W {1'b0}}, fill_out_grant[fb]});
+			assign fill_out_done[fb] = fill_out_cnt_q[(fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : ibex_pkg_IC_LINE_BEATS_W - ibex_pkg_IC_LINE_BEATS_W)];
+			assign fill_ram_req[fb] = ((((fill_busy_q[fb] & fill_rvd_cnt_q[(fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : ibex_pkg_IC_LINE_BEATS_W - ibex_pkg_IC_LINE_BEATS_W)]) & ~fill_hit_q[fb]) & fill_cache_q[fb]) & ~|fill_err_q[fb * ibex_pkg_IC_LINE_BEATS+:ibex_pkg_IC_LINE_BEATS]) & ~fill_ram_done_q[fb];
+			assign fill_ram_done_d[fb] = fill_ram_arb[fb] | (fill_ram_done_q[fb] & fill_busy_q[fb]);
+			assign fill_ext_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] = {1'b0, fill_addr_q[fb][2:ibex_pkg_BUS_W]} + fill_ext_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1) : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1)) : (((fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1) : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1))) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1)-:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)];
+			assign fill_ext_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W] = fill_ext_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1)) : (((fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1))) + ibex_pkg_IC_LINE_BEATS_W) - 1)-:ibex_pkg_IC_LINE_BEATS_W];
+			assign fill_rvd_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] = {1'b0, fill_addr_q[fb][2:ibex_pkg_BUS_W]} + fill_rvd_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1) : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1)) : (((fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1) : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W : (ibex_pkg_IC_LINE_BEATS_W + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1))) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) - 1)-:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)];
+			assign fill_rvd_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W] = fill_rvd_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1)) : (((fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)) + (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W - 1 : ibex_pkg_IC_LINE_BEATS_W - (ibex_pkg_IC_LINE_BEATS_W - 1))) + ibex_pkg_IC_LINE_BEATS_W) - 1)-:ibex_pkg_IC_LINE_BEATS_W];
+			assign fill_ext_arb[fb] = fill_ext_req[fb] & ~|(fill_ext_req & fill_older_q[fb * NUM_FB+:NUM_FB]);
+			assign fill_ram_arb[fb] = (fill_ram_req[fb] & fill_grant_ic0) & ~|(fill_ram_req & fill_older_q[fb * NUM_FB+:NUM_FB]);
+			assign fill_data_sel[fb] = ~|(((fill_busy_q & ~fill_out_done) & ~fill_stale_q) & fill_older_q[fb * NUM_FB+:NUM_FB]);
+			assign fill_out_arb[fb] = fill_out_req[fb] & fill_data_sel[fb];
+			assign fill_rvd_arb[fb] = (instr_rvalid_i & fill_rvd_exp[fb]) & ~|(fill_rvd_exp & fill_older_q[fb * NUM_FB+:NUM_FB]);
+			assign fill_data_reg[fb] = (((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & fill_data_sel[fb]) & (((fill_rvd_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] > fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)]) | fill_hit_q[fb]) | |fill_err_q[fb * ibex_pkg_IC_LINE_BEATS+:ibex_pkg_IC_LINE_BEATS]);
+			assign fill_data_hit[fb] = (fill_busy_q[fb] & fill_hit_ic1[fb]) & fill_data_sel[fb];
+			assign fill_data_rvd[fb] = ((((((fill_busy_q[fb] & fill_rvd_arb[fb]) & ~fill_hit_q[fb]) & ~fill_hit_ic1[fb]) & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & (fill_rvd_beat[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] == fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)])) & fill_data_sel[fb];
+			assign fill_entry_en[fb] = fill_alloc[fb] | fill_busy_q[fb];
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni) begin
+					fill_busy_q[fb] <= 1'b0;
+					fill_older_q[fb * NUM_FB+:NUM_FB] <= 1'sb0;
+					fill_stale_q[fb] <= 1'b0;
+					fill_cache_q[fb] <= 1'b0;
+					fill_hit_q[fb] <= 1'b0;
+					fill_ext_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= 1'sb0;
+					fill_ext_hold_q[fb] <= 1'b0;
+					fill_ext_done_q[fb] <= 1'b0;
+					fill_rvd_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= 1'sb0;
+					fill_ram_done_q[fb] <= 1'b0;
+					fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= 1'sb0;
+				end
+				else if (fill_entry_en[fb]) begin
+					fill_busy_q[fb] <= fill_busy_d[fb];
+					fill_older_q[fb * NUM_FB+:NUM_FB] <= fill_older_d[fb * NUM_FB+:NUM_FB];
+					fill_stale_q[fb] <= fill_stale_d[fb];
+					fill_cache_q[fb] <= fill_cache_d[fb];
+					fill_hit_q[fb] <= fill_hit_d[fb];
+					fill_ext_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= fill_ext_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)];
+					fill_ext_hold_q[fb] <= fill_ext_hold_d[fb];
+					fill_ext_done_q[fb] <= fill_ext_done_d[fb];
+					fill_rvd_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= fill_rvd_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)];
+					fill_ram_done_q[fb] <= fill_ram_done_d[fb];
+					fill_out_cnt_q[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)] <= fill_out_cnt_d[(ibex_pkg_IC_LINE_BEATS_W >= 0 ? 0 : ibex_pkg_IC_LINE_BEATS_W) + (fb * (ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W))+:(ibex_pkg_IC_LINE_BEATS_W >= 0 ? ibex_pkg_IC_LINE_BEATS_W + 1 : 1 - ibex_pkg_IC_LINE_BEATS_W)];
+				end
+			assign fill_addr_en[fb] = fill_alloc[fb];
+			assign fill_way_en[fb] = lookup_valid_ic1 & fill_in_ic1[fb];
+			if (ResetAll) begin : g_fill_addr_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni)
+						fill_addr_q[fb] <= 1'sb0;
+					else if (fill_addr_en[fb])
+						fill_addr_q[fb] <= lookup_addr_ic0;
+			end
+			else begin : g_fill_addr_nr
+				always @(posedge clk_i)
+					if (fill_addr_en[fb])
+						fill_addr_q[fb] <= lookup_addr_ic0;
+			end
+			if (ResetAll) begin : g_fill_way_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni)
+						fill_way_q[fb] <= 1'sb0;
+					else if (fill_way_en[fb])
+						fill_way_q[fb] <= sel_way_ic1;
+			end
+			else begin : g_fill_way_nr
+				always @(posedge clk_i)
+					if (fill_way_en[fb])
+						fill_way_q[fb] <= sel_way_ic1;
+			end
+			assign fill_data_d[fb] = (fill_hit_ic1[fb] ? hit_data_ic1 : {ibex_pkg_IC_LINE_BEATS {instr_rdata_i}});
+			genvar b;
+			for (b = 0; b < ibex_pkg_IC_LINE_BEATS; b = b + 1) begin : gen_data_buf
+				assign fill_err_d[(fb * ibex_pkg_IC_LINE_BEATS) + b] = (((((instr_pmp_err_i & fill_alloc[fb]) & fill_spec_req) & (lookup_addr_ic0[2:ibex_pkg_BUS_W] == b[ibex_pkg_IC_LINE_BEATS_W - 1:0])) | ((instr_pmp_err_i & fill_ext_arb[fb]) & (fill_ext_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W] == b[ibex_pkg_IC_LINE_BEATS_W - 1:0]))) | ((fill_rvd_arb[fb] & instr_err_i) & (fill_rvd_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W] == b[ibex_pkg_IC_LINE_BEATS_W - 1:0]))) | (fill_busy_q[fb] & fill_err_q[(fb * ibex_pkg_IC_LINE_BEATS) + b]);
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni)
+						fill_err_q[(fb * ibex_pkg_IC_LINE_BEATS) + b] <= 1'sb0;
+					else if (fill_entry_en[fb])
+						fill_err_q[(fb * ibex_pkg_IC_LINE_BEATS) + b] <= fill_err_d[(fb * ibex_pkg_IC_LINE_BEATS) + b];
+				assign fill_data_en[(fb * ibex_pkg_IC_LINE_BEATS) + b] = fill_hit_ic1[fb] | ((fill_rvd_arb[fb] & ~fill_hit_q[fb]) & (fill_rvd_off[fb * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W] == b[ibex_pkg_IC_LINE_BEATS_W - 1:0]));
+				if (ResetAll) begin : g_fill_data_ra
+					always @(posedge clk_i or negedge rst_ni)
+						if (!rst_ni)
+							fill_data_q[fb][b * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE] <= 1'sb0;
+						else if (fill_data_en[(fb * ibex_pkg_IC_LINE_BEATS) + b])
+							fill_data_q[fb][b * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE] <= fill_data_d[fb][b * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE];
+				end
+				else begin : g_fill_data_nr
+					always @(posedge clk_i)
+						if (fill_data_en[(fb * ibex_pkg_IC_LINE_BEATS) + b])
+							fill_data_q[fb][b * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE] <= fill_data_d[fb][b * ibex_pkg_BUS_SIZE+:ibex_pkg_BUS_SIZE];
+				end
+			end
+		end
+	endgenerate
+	always @(*) begin
+		fill_ext_req_addr = 1'sb0;
+		begin : sv2v_autoblock_3
+			reg signed [31:0] i;
+			for (i = 0; i < NUM_FB; i = i + 1)
+				if (fill_ext_arb[i])
+					fill_ext_req_addr = fill_ext_req_addr | {fill_addr_q[i][31:ibex_pkg_IC_LINE_W], fill_ext_off[i * ibex_pkg_IC_LINE_BEATS_W+:ibex_pkg_IC_LINE_BEATS_W]};
+		end
+	end
+	always @(*) begin
+		fill_ram_req_addr = 1'sb0;
+		fill_ram_req_way = 1'sb0;
+		fill_ram_req_data = 1'sb0;
+		begin : sv2v_autoblock_4
+			reg signed [31:0] i;
+			for (i = 0; i < NUM_FB; i = i + 1)
+				if (fill_ram_arb[i]) begin
+					fill_ram_req_addr = fill_ram_req_addr | fill_addr_q[i];
+					fill_ram_req_way = fill_ram_req_way | fill_way_q[i];
+					fill_ram_req_data = fill_ram_req_data | fill_data_q[i];
+				end
+		end
+	end
+	always @(*) begin
+		fill_out_data = 1'sb0;
+		fill_out_err = 1'sb0;
+		begin : sv2v_autoblock_5
+			reg signed [31:0] i;
+			for (i = 0; i < NUM_FB; i = i + 1)
+				if (fill_data_reg[i]) begin
+					fill_out_data = fill_out_data | fill_data_q[i];
+					fill_out_err = fill_out_err | (fill_err_q[i * ibex_pkg_IC_LINE_BEATS+:ibex_pkg_IC_LINE_BEATS] & ~{ibex_pkg_IC_LINE_BEATS {fill_hit_q[i]}});
+				end
+		end
+	end
+	assign instr_req = ((~icache_enable_i | branch_or_mispredict) & lookup_grant_ic0) | |fill_ext_req;
+	assign instr_addr = (|fill_ext_req ? fill_ext_req_addr : lookup_addr_ic0[31:ibex_pkg_BUS_W]);
+	assign instr_req_o = instr_req;
+	assign instr_addr_o = {instr_addr[31:ibex_pkg_BUS_W], {ibex_pkg_BUS_W {1'b0}}};
+	assign line_data = (|fill_data_hit ? hit_data_ic1 : fill_out_data);
+	assign line_err = (|fill_data_hit ? {ibex_pkg_IC_LINE_BEATS {1'b0}} : fill_out_err);
+	always @(*) begin
+		line_data_muxed = 1'sb0;
+		line_err_muxed = 1'b0;
+		begin : sv2v_autoblock_6
+			reg signed [31:0] i;
+			for (i = 0; i < ibex_pkg_IC_LINE_BEATS; i = i + 1)
+				if ((output_addr_q[2:ibex_pkg_BUS_W] + {{ibex_pkg_IC_LINE_BEATS_W - 1 {1'b0}}, skid_valid_q}) == i[ibex_pkg_IC_LINE_BEATS_W - 1:0]) begin
+					line_data_muxed = line_data_muxed | line_data[i * 32+:32];
+					line_err_muxed = line_err_muxed | line_err[i];
+				end
+		end
+	end
+	assign output_data = (|fill_data_rvd ? instr_rdata_i : line_data_muxed);
+	assign output_err = (|fill_data_rvd ? instr_err_i : line_err_muxed);
+	assign data_valid = |fill_out_arb;
+	assign skid_data_d = output_data[31:16];
+	assign skid_en = data_valid & (ready_i | skid_ready);
+	generate
+		if (ResetAll) begin : g_skid_data_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni) begin
+					skid_data_q <= 1'sb0;
+					skid_err_q <= 1'sb0;
+				end
+				else if (skid_en) begin
+					skid_data_q <= skid_data_d;
+					skid_err_q <= output_err;
+				end
+		end
+		else begin : g_skid_data_nr
+			always @(posedge clk_i)
+				if (skid_en) begin
+					skid_data_q <= skid_data_d;
+					skid_err_q <= output_err;
+				end
+		end
+	endgenerate
+	assign skid_complete_instr = skid_valid_q & ((skid_data_q[1:0] != 2'b11) | skid_err_q);
+	assign skid_ready = (output_addr_q[1] & ~skid_valid_q) & (~output_compressed | output_err);
+	assign output_ready = (ready_i | skid_ready) & ~skid_complete_instr;
+	assign output_compressed = rdata_o[1:0] != 2'b11;
+	assign skid_valid_d = (branch_or_mispredict ? 1'b0 : (skid_valid_q ? ~(ready_i & ((skid_data_q[1:0] != 2'b11) | skid_err_q)) : data_valid & ((output_addr_q[1] & (~output_compressed | output_err)) | (((~output_addr_q[1] & output_compressed) & ~output_err) & ready_i))));
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			skid_valid_q <= 1'b0;
+		else
+			skid_valid_q <= skid_valid_d;
+	assign output_valid = skid_complete_instr | (data_valid & (((~output_addr_q[1] | skid_valid_q) | output_err) | (output_data[17:16] != 2'b11)));
+	assign output_addr_en = branch_or_mispredict | (ready_i & valid_o);
+	assign addr_incr_two = output_compressed & ~err_o;
+	assign output_addr_incr = output_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two};
+	assign output_addr_d = (branch_i ? addr_i[31:1] : (branch_mispredict_i ? mispredict_addr_i[31:1] : output_addr_incr));
+	generate
+		if (ResetAll) begin : g_output_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					output_addr_q <= 1'sb0;
+				else if (output_addr_en)
+					output_addr_q <= output_addr_d;
+		end
+		else begin : g_output_addr_nr
+			always @(posedge clk_i)
+				if (output_addr_en)
+					output_addr_q <= output_addr_d;
+		end
+	endgenerate
+	localparam [31:0] ibex_pkg_IC_OUTPUT_BEATS = 2;
+	always @(*) begin
+		output_data_lo = 1'sb0;
+		begin : sv2v_autoblock_7
+			reg signed [31:0] i;
+			for (i = 0; i < ibex_pkg_IC_OUTPUT_BEATS; i = i + 1)
+				if (output_addr_q[1:1] == i[0:0])
+					output_data_lo = output_data_lo | output_data[i * 16+:16];
+		end
+	end
+	always @(*) begin
+		output_data_hi = 1'sb0;
+		begin : sv2v_autoblock_8
+			reg signed [31:0] i;
+			for (i = 0; i < 1; i = i + 1)
+				if (output_addr_q[1:1] == i[0:0])
+					output_data_hi = output_data_hi | output_data[(i + 1) * 16+:16];
+		end
+		if (&output_addr_q[1:1])
+			output_data_hi = output_data_hi | output_data[15:0];
+	end
+	assign valid_o = output_valid & ~branch_mispredict_i;
+	assign rdata_o = {output_data_hi, (skid_valid_q ? skid_data_q : output_data_lo)};
+	assign addr_o = {output_addr_q, 1'b0};
+	assign err_o = (skid_valid_q & skid_err_q) | (~skid_complete_instr & output_err);
+	assign err_plus2_o = skid_valid_q & ~skid_err_q;
+	assign start_inval = (~reset_inval_q | icache_inval_i) & ~inval_prog_q;
+	assign inval_prog_d = start_inval | (inval_prog_q & ~inval_done);
+	assign inval_done = &inval_index_q;
+	assign inval_index_d = (start_inval ? {ibex_pkg_IC_INDEX_W {1'sb0}} : inval_index_q + {{ibex_pkg_IC_INDEX_W - 1 {1'b0}}, 1'b1});
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			inval_prog_q <= 1'b0;
+			reset_inval_q <= 1'b0;
+		end
+		else begin
+			inval_prog_q <= inval_prog_d;
+			reset_inval_q <= 1'b1;
+		end
+	generate
+		if (ResetAll) begin : g_inval_index_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					inval_index_q <= 1'sb0;
+				else if (inval_prog_d)
+					inval_index_q <= inval_index_d;
+		end
+		else begin : g_inval_index_nr
+			always @(posedge clk_i)
+				if (inval_prog_d)
+					inval_index_q <= inval_index_d;
+		end
+	endgenerate
+	assign busy_o = inval_prog_q | |(fill_busy_q & ~fill_rvd_done);
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_id_stage.v b/verilog/rtl/ibex_core/ibex_id_stage.v
new file mode 100644
index 0000000..3eec58d
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_id_stage.v
@@ -0,0 +1,785 @@
+module ibex_id_stage (
+	clk_i,
+	rst_ni,
+	ctrl_busy_o,
+	illegal_insn_o,
+	instr_valid_i,
+	instr_rdata_i,
+	instr_rdata_alu_i,
+	instr_rdata_c_i,
+	instr_is_compressed_i,
+	instr_bp_taken_i,
+	instr_req_o,
+	instr_first_cycle_id_o,
+	instr_valid_clear_o,
+	id_in_ready_o,
+	icache_inval_o,
+	branch_decision_i,
+	pc_set_o,
+	pc_set_spec_o,
+	pc_mux_o,
+	nt_branch_mispredict_o,
+	nt_branch_addr_o,
+	exc_pc_mux_o,
+	exc_cause_o,
+	illegal_c_insn_i,
+	instr_fetch_err_i,
+	instr_fetch_err_plus2_i,
+	pc_id_i,
+	ex_valid_i,
+	lsu_resp_valid_i,
+	alu_operator_ex_o,
+	alu_operand_a_ex_o,
+	alu_operand_b_ex_o,
+	imd_val_we_ex_i,
+	imd_val_d_ex_i,
+	imd_val_q_ex_o,
+	bt_a_operand_o,
+	bt_b_operand_o,
+	mult_en_ex_o,
+	div_en_ex_o,
+	mult_sel_ex_o,
+	div_sel_ex_o,
+	multdiv_operator_ex_o,
+	multdiv_signed_mode_ex_o,
+	multdiv_operand_a_ex_o,
+	multdiv_operand_b_ex_o,
+	multdiv_ready_id_o,
+	eFPGA_en_o,
+	eFPGA_operator_o,
+	eFPGA_operand_a_o,
+	eFPGA_operand_b_o,
+	eFPGA_delay_o,
+	csr_access_o,
+	csr_op_o,
+	csr_op_en_o,
+	csr_save_if_o,
+	csr_save_id_o,
+	csr_save_wb_o,
+	csr_restore_mret_id_o,
+	csr_restore_dret_id_o,
+	csr_save_cause_o,
+	csr_mtval_o,
+	priv_mode_i,
+	csr_mstatus_tw_i,
+	illegal_csr_insn_i,
+	data_ind_timing_i,
+	lsu_req_o,
+	lsu_we_o,
+	lsu_type_o,
+	lsu_sign_ext_o,
+	lsu_wdata_o,
+	lsu_req_done_i,
+	lsu_addr_incr_req_i,
+	lsu_addr_last_i,
+	csr_mstatus_mie_i,
+	irq_pending_i,
+	irqs_i,
+	irq_nm_i,
+	nmi_mode_o,
+	lsu_load_err_i,
+	lsu_store_err_i,
+	debug_mode_o,
+	debug_cause_o,
+	debug_csr_save_o,
+	debug_req_i,
+	debug_single_step_i,
+	debug_ebreakm_i,
+	debug_ebreaku_i,
+	trigger_match_i,
+	result_ex_i,
+	csr_rdata_i,
+	rf_raddr_a_o,
+	rf_rdata_a_i,
+	rf_raddr_b_o,
+	rf_rdata_b_i,
+	rf_ren_a_o,
+	rf_ren_b_o,
+	rf_waddr_id_o,
+	rf_wdata_id_o,
+	rf_we_id_o,
+	rf_rd_a_wb_match_o,
+	rf_rd_b_wb_match_o,
+	rf_waddr_wb_i,
+	rf_wdata_fwd_wb_i,
+	rf_write_wb_i,
+	en_wb_o,
+	instr_type_wb_o,
+	instr_perf_count_id_o,
+	ready_wb_i,
+	outstanding_load_wb_i,
+	outstanding_store_wb_i,
+	perf_jump_o,
+	perf_branch_o,
+	perf_tbranch_o,
+	perf_dside_wait_o,
+	perf_mul_wait_o,
+	perf_div_wait_o,
+	instr_id_done_o
+);
+	parameter [0:0] RV32E = 0;
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd0;
+	parameter [0:0] DataIndTiming = 1'b0;
+	parameter [0:0] BranchTargetALU = 0;
+	parameter [0:0] SpecBranch = 0;
+	parameter [0:0] WritebackStage = 0;
+	parameter [0:0] BranchPredictor = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	output wire ctrl_busy_o;
+	output wire illegal_insn_o;
+	input wire instr_valid_i;
+	input wire [31:0] instr_rdata_i;
+	input wire [31:0] instr_rdata_alu_i;
+	input wire [15:0] instr_rdata_c_i;
+	input wire instr_is_compressed_i;
+	input wire instr_bp_taken_i;
+	output wire instr_req_o;
+	output wire instr_first_cycle_id_o;
+	output wire instr_valid_clear_o;
+	output wire id_in_ready_o;
+	output wire icache_inval_o;
+	input wire branch_decision_i;
+	output wire pc_set_o;
+	output wire pc_set_spec_o;
+	output wire [2:0] pc_mux_o;
+	output wire nt_branch_mispredict_o;
+	output wire [31:0] nt_branch_addr_o;
+	output wire [1:0] exc_pc_mux_o;
+	output wire [5:0] exc_cause_o;
+	input wire illegal_c_insn_i;
+	input wire instr_fetch_err_i;
+	input wire instr_fetch_err_plus2_i;
+	input wire [31:0] pc_id_i;
+	input wire ex_valid_i;
+	input wire lsu_resp_valid_i;
+	output wire [6:0] alu_operator_ex_o;
+	output wire [31:0] alu_operand_a_ex_o;
+	output wire [31:0] alu_operand_b_ex_o;
+	input wire [1:0] imd_val_we_ex_i;
+	input wire [67:0] imd_val_d_ex_i;
+	output wire [67:0] imd_val_q_ex_o;
+	output reg [31:0] bt_a_operand_o;
+	output reg [31:0] bt_b_operand_o;
+	output wire mult_en_ex_o;
+	output wire div_en_ex_o;
+	output wire mult_sel_ex_o;
+	output wire div_sel_ex_o;
+	output wire [1:0] multdiv_operator_ex_o;
+	output wire [1:0] multdiv_signed_mode_ex_o;
+	output wire [31:0] multdiv_operand_a_ex_o;
+	output wire [31:0] multdiv_operand_b_ex_o;
+	output wire multdiv_ready_id_o;
+	output wire eFPGA_en_o;
+	output wire [1:0] eFPGA_operator_o;
+	output wire [31:0] eFPGA_operand_a_o;
+	output wire [31:0] eFPGA_operand_b_o;
+	output wire [3:0] eFPGA_delay_o;
+	output wire csr_access_o;
+	output wire [1:0] csr_op_o;
+	output wire csr_op_en_o;
+	output wire csr_save_if_o;
+	output wire csr_save_id_o;
+	output wire csr_save_wb_o;
+	output wire csr_restore_mret_id_o;
+	output wire csr_restore_dret_id_o;
+	output wire csr_save_cause_o;
+	output wire [31:0] csr_mtval_o;
+	input wire [1:0] priv_mode_i;
+	input wire csr_mstatus_tw_i;
+	input wire illegal_csr_insn_i;
+	input wire data_ind_timing_i;
+	output wire lsu_req_o;
+	output wire lsu_we_o;
+	output wire [1:0] lsu_type_o;
+	output wire lsu_sign_ext_o;
+	output wire [31:0] lsu_wdata_o;
+	input wire lsu_req_done_i;
+	input wire lsu_addr_incr_req_i;
+	input wire [31:0] lsu_addr_last_i;
+	input wire csr_mstatus_mie_i;
+	input wire irq_pending_i;
+	input wire [17:0] irqs_i;
+	input wire irq_nm_i;
+	output wire nmi_mode_o;
+	input wire lsu_load_err_i;
+	input wire lsu_store_err_i;
+	output wire debug_mode_o;
+	output wire [2:0] debug_cause_o;
+	output wire debug_csr_save_o;
+	input wire debug_req_i;
+	input wire debug_single_step_i;
+	input wire debug_ebreakm_i;
+	input wire debug_ebreaku_i;
+	input wire trigger_match_i;
+	input wire [31:0] result_ex_i;
+	input wire [31:0] csr_rdata_i;
+	output wire [4:0] rf_raddr_a_o;
+	input wire [31:0] rf_rdata_a_i;
+	output wire [4:0] rf_raddr_b_o;
+	input wire [31:0] rf_rdata_b_i;
+	output wire rf_ren_a_o;
+	output wire rf_ren_b_o;
+	output wire [4:0] rf_waddr_id_o;
+	output reg [31:0] rf_wdata_id_o;
+	output wire rf_we_id_o;
+	output wire rf_rd_a_wb_match_o;
+	output wire rf_rd_b_wb_match_o;
+	input wire [4:0] rf_waddr_wb_i;
+	input wire [31:0] rf_wdata_fwd_wb_i;
+	input wire rf_write_wb_i;
+	output wire en_wb_o;
+	output wire [1:0] instr_type_wb_o;
+	output wire instr_perf_count_id_o;
+	input wire ready_wb_i;
+	input wire outstanding_load_wb_i;
+	input wire outstanding_store_wb_i;
+	output wire perf_jump_o;
+	output reg perf_branch_o;
+	output wire perf_tbranch_o;
+	output wire perf_dside_wait_o;
+	output wire perf_mul_wait_o;
+	output wire perf_div_wait_o;
+	output wire instr_id_done_o;
+	wire illegal_insn_dec;
+	wire ebrk_insn;
+	wire mret_insn_dec;
+	wire dret_insn_dec;
+	wire ecall_insn_dec;
+	wire wfi_insn_dec;
+	wire wb_exception;
+	wire id_exception;
+	wire branch_in_dec;
+	reg branch_spec;
+	wire branch_set_spec;
+	wire branch_set_raw_spec;
+	wire branch_set;
+	wire branch_set_raw;
+	reg branch_set_raw_d;
+	reg branch_jump_set_done_q;
+	wire branch_jump_set_done_d;
+	reg branch_not_set;
+	wire branch_taken;
+	wire jump_in_dec;
+	wire jump_set_dec;
+	wire jump_set;
+	reg jump_set_raw;
+	wire instr_first_cycle;
+	wire instr_executing_spec;
+	wire instr_executing;
+	wire instr_done;
+	wire controller_run;
+	wire stall_ld_hz;
+	wire stall_mem;
+	reg stall_multdiv;
+	reg stall_branch;
+	reg stall_jump;
+	wire stall_id;
+	wire stall_wb;
+	wire flush_id;
+	wire multicycle_done;
+	reg eFPGA_stall;
+	wire [31:0] imm_i_type;
+	wire [31:0] imm_s_type;
+	wire [31:0] imm_b_type;
+	wire [31:0] imm_u_type;
+	wire [31:0] imm_j_type;
+	wire [31:0] zimm_rs1_type;
+	wire [31:0] imm_a;
+	reg [31:0] imm_b;
+	wire rf_wdata_sel;
+	wire rf_we_dec;
+	reg rf_we_raw;
+	wire rf_ren_a;
+	wire rf_ren_b;
+	wire rf_ren_a_dec;
+	wire rf_ren_b_dec;
+	assign rf_ren_a = ((instr_valid_i & ~instr_fetch_err_i) & ~illegal_insn_o) & rf_ren_a_dec;
+	assign rf_ren_b = ((instr_valid_i & ~instr_fetch_err_i) & ~illegal_insn_o) & rf_ren_b_dec;
+	assign rf_ren_a_o = rf_ren_a;
+	assign rf_ren_b_o = rf_ren_b;
+	wire [31:0] rf_rdata_a_fwd;
+	wire [31:0] rf_rdata_b_fwd;
+	wire [6:0] alu_operator;
+	wire [1:0] alu_op_a_mux_sel;
+	wire [1:0] alu_op_a_mux_sel_dec;
+	wire alu_op_b_mux_sel;
+	wire alu_op_b_mux_sel_dec;
+	wire alu_multicycle_dec;
+	reg stall_alu;
+	reg [67:0] imd_val_q;
+	wire [1:0] bt_a_mux_sel;
+	wire [2:0] bt_b_mux_sel;
+	wire imm_a_mux_sel;
+	wire [2:0] imm_b_mux_sel;
+	wire [2:0] imm_b_mux_sel_dec;
+	wire mult_en_id;
+	wire mult_en_dec;
+	wire div_en_id;
+	wire div_en_dec;
+	wire multdiv_en_dec;
+	wire [1:0] multdiv_operator;
+	wire [1:0] multdiv_signed_mode;
+	wire lsu_we;
+	wire [1:0] lsu_type;
+	wire lsu_sign_ext;
+	wire lsu_req;
+	wire lsu_req_dec;
+	wire data_req_allowed;
+	reg csr_pipe_flush;
+	reg [31:0] alu_operand_a;
+	wire [31:0] alu_operand_b;
+	assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? 2'd1 : alu_op_a_mux_sel_dec);
+	assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? 1'd1 : alu_op_b_mux_sel_dec);
+	assign imm_b_mux_sel = (lsu_addr_incr_req_i ? 3'd6 : imm_b_mux_sel_dec);
+	assign imm_a = (imm_a_mux_sel == 1'd0 ? zimm_rs1_type : {32 {1'sb0}});
+	always @(*) begin : alu_operand_a_mux
+		case (alu_op_a_mux_sel)
+			2'd0: alu_operand_a = rf_rdata_a_fwd;
+			2'd1: alu_operand_a = lsu_addr_last_i;
+			2'd2: alu_operand_a = pc_id_i;
+			2'd3: alu_operand_a = imm_a;
+			default: alu_operand_a = pc_id_i;
+		endcase
+	end
+	generate
+		if (BranchTargetALU) begin : g_btalu_muxes
+			always @(*) begin : bt_operand_a_mux
+				case (bt_a_mux_sel)
+					2'd0: bt_a_operand_o = rf_rdata_a_fwd;
+					2'd2: bt_a_operand_o = pc_id_i;
+					default: bt_a_operand_o = pc_id_i;
+				endcase
+			end
+			always @(*) begin : bt_immediate_b_mux
+				case (bt_b_mux_sel)
+					3'd0: bt_b_operand_o = imm_i_type;
+					3'd2: bt_b_operand_o = imm_b_type;
+					3'd4: bt_b_operand_o = imm_j_type;
+					3'd5: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004);
+					default: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004);
+				endcase
+			end
+			always @(*) begin : immediate_b_mux
+				case (imm_b_mux_sel)
+					3'd0: imm_b = imm_i_type;
+					3'd1: imm_b = imm_s_type;
+					3'd3: imm_b = imm_u_type;
+					3'd5: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004);
+					3'd6: imm_b = 32'h00000004;
+					default: imm_b = 32'h00000004;
+				endcase
+			end
+		end
+		else begin : g_nobtalu
+			wire [1:0] unused_a_mux_sel;
+			wire [2:0] unused_b_mux_sel;
+			assign unused_a_mux_sel = bt_a_mux_sel;
+			assign unused_b_mux_sel = bt_b_mux_sel;
+			wire [32:1] sv2v_tmp_FACAA;
+			assign sv2v_tmp_FACAA = 1'sb0;
+			always @(*) bt_a_operand_o = sv2v_tmp_FACAA;
+			wire [32:1] sv2v_tmp_A4AF9;
+			assign sv2v_tmp_A4AF9 = 1'sb0;
+			always @(*) bt_b_operand_o = sv2v_tmp_A4AF9;
+			always @(*) begin : immediate_b_mux
+				case (imm_b_mux_sel)
+					3'd0: imm_b = imm_i_type;
+					3'd1: imm_b = imm_s_type;
+					3'd2: imm_b = imm_b_type;
+					3'd3: imm_b = imm_u_type;
+					3'd4: imm_b = imm_j_type;
+					3'd5: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004);
+					3'd6: imm_b = 32'h00000004;
+					default: imm_b = 32'h00000004;
+				endcase
+			end
+		end
+	endgenerate
+	assign alu_operand_b = (alu_op_b_mux_sel == 1'd1 ? imm_b : rf_rdata_b_fwd);
+	genvar i;
+	generate
+		for (i = 0; i < 2; i = i + 1) begin : gen_intermediate_val_reg
+			always @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg
+				if (!rst_ni)
+					imd_val_q[(1 - i) * 34+:34] <= 1'sb0;
+				else if (imd_val_we_ex_i[i])
+					imd_val_q[(1 - i) * 34+:34] <= imd_val_d_ex_i[(1 - i) * 34+:34];
+			end
+		end
+	endgenerate
+	assign imd_val_q_ex_o = imd_val_q;
+	assign rf_we_id_o = (rf_we_raw & instr_executing) & ~illegal_csr_insn_i;
+	always @(*) begin : rf_wdata_id_mux
+		case (rf_wdata_sel)
+			1'd0: rf_wdata_id_o = result_ex_i;
+			1'd1: rf_wdata_id_o = csr_rdata_i;
+			default: rf_wdata_id_o = result_ex_i;
+		endcase
+	end
+	wire eFPGA_int_en;
+	wire [1:0] eFPGA_operator;
+	wire [3:0] eFPGA_delay;
+	assign eFPGA_en_o = eFPGA_int_en;
+	assign eFPGA_operator_o = eFPGA_operator;
+	assign eFPGA_delay_o = eFPGA_delay;
+	ibex_decoder #(
+		.RV32E(RV32E),
+		.RV32M(RV32M),
+		.RV32B(RV32B),
+		.RV32Zk(RV32Zk),
+		.BranchTargetALU(BranchTargetALU)
+	) decoder_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.illegal_insn_o(illegal_insn_dec),
+		.ebrk_insn_o(ebrk_insn),
+		.mret_insn_o(mret_insn_dec),
+		.dret_insn_o(dret_insn_dec),
+		.ecall_insn_o(ecall_insn_dec),
+		.wfi_insn_o(wfi_insn_dec),
+		.jump_set_o(jump_set_dec),
+		.branch_taken_i(branch_taken),
+		.icache_inval_o(icache_inval_o),
+		.instr_first_cycle_i(instr_first_cycle),
+		.instr_rdata_i(instr_rdata_i),
+		.instr_rdata_alu_i(instr_rdata_alu_i),
+		.illegal_c_insn_i(illegal_c_insn_i),
+		.imm_a_mux_sel_o(imm_a_mux_sel),
+		.imm_b_mux_sel_o(imm_b_mux_sel_dec),
+		.bt_a_mux_sel_o(bt_a_mux_sel),
+		.bt_b_mux_sel_o(bt_b_mux_sel),
+		.imm_i_type_o(imm_i_type),
+		.imm_s_type_o(imm_s_type),
+		.imm_b_type_o(imm_b_type),
+		.imm_u_type_o(imm_u_type),
+		.imm_j_type_o(imm_j_type),
+		.zimm_rs1_type_o(zimm_rs1_type),
+		.rf_wdata_sel_o(rf_wdata_sel),
+		.rf_we_o(rf_we_dec),
+		.rf_raddr_a_o(rf_raddr_a_o),
+		.rf_raddr_b_o(rf_raddr_b_o),
+		.rf_waddr_o(rf_waddr_id_o),
+		.rf_ren_a_o(rf_ren_a_dec),
+		.rf_ren_b_o(rf_ren_b_dec),
+		.alu_operator_o(alu_operator),
+		.alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec),
+		.alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec),
+		.alu_multicycle_o(alu_multicycle_dec),
+		.eFPGA_operator_o(eFPGA_operator),
+		.eFPGA_int_en_o(eFPGA_int_en),
+		.eFPGA_delay_o(eFPGA_delay),
+		.mult_en_o(mult_en_dec),
+		.div_en_o(div_en_dec),
+		.mult_sel_o(mult_sel_ex_o),
+		.div_sel_o(div_sel_ex_o),
+		.multdiv_operator_o(multdiv_operator),
+		.multdiv_signed_mode_o(multdiv_signed_mode),
+		.csr_access_o(csr_access_o),
+		.csr_op_o(csr_op_o),
+		.data_req_o(lsu_req_dec),
+		.data_we_o(lsu_we),
+		.data_type_o(lsu_type),
+		.data_sign_extension_o(lsu_sign_ext),
+		.jump_in_dec_o(jump_in_dec),
+		.branch_in_dec_o(branch_in_dec)
+	);
+	always @(*) begin : csr_pipeline_flushes
+		csr_pipe_flush = 1'b0;
+		if ((csr_op_en_o == 1'b1) && ((csr_op_o == 2'd1) || (csr_op_o == 2'd2))) begin
+			if ((instr_rdata_i[31:20] == 12'h300) || (instr_rdata_i[31:20] == 12'h304))
+				csr_pipe_flush = 1'b1;
+		end
+		else if ((csr_op_en_o == 1'b1) && (csr_op_o != 2'd0))
+			if ((((instr_rdata_i[31:20] == 12'h7b0) || (instr_rdata_i[31:20] == 12'h7b1)) || (instr_rdata_i[31:20] == 12'h7b2)) || (instr_rdata_i[31:20] == 12'h7b3))
+				csr_pipe_flush = 1'b1;
+	end
+	assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
+	ibex_controller #(
+		.WritebackStage(WritebackStage),
+		.BranchPredictor(BranchPredictor)
+	) controller_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.ctrl_busy_o(ctrl_busy_o),
+		.illegal_insn_i(illegal_insn_o),
+		.ecall_insn_i(ecall_insn_dec),
+		.mret_insn_i(mret_insn_dec),
+		.dret_insn_i(dret_insn_dec),
+		.wfi_insn_i(wfi_insn_dec),
+		.ebrk_insn_i(ebrk_insn),
+		.csr_pipe_flush_i(csr_pipe_flush),
+		.instr_valid_i(instr_valid_i),
+		.instr_i(instr_rdata_i),
+		.instr_compressed_i(instr_rdata_c_i),
+		.instr_is_compressed_i(instr_is_compressed_i),
+		.instr_bp_taken_i(instr_bp_taken_i),
+		.instr_fetch_err_i(instr_fetch_err_i),
+		.instr_fetch_err_plus2_i(instr_fetch_err_plus2_i),
+		.pc_id_i(pc_id_i),
+		.instr_valid_clear_o(instr_valid_clear_o),
+		.id_in_ready_o(id_in_ready_o),
+		.controller_run_o(controller_run),
+		.instr_req_o(instr_req_o),
+		.pc_set_o(pc_set_o),
+		.pc_set_spec_o(pc_set_spec_o),
+		.pc_mux_o(pc_mux_o),
+		.nt_branch_mispredict_o(nt_branch_mispredict_o),
+		.exc_pc_mux_o(exc_pc_mux_o),
+		.exc_cause_o(exc_cause_o),
+		.lsu_addr_last_i(lsu_addr_last_i),
+		.load_err_i(lsu_load_err_i),
+		.store_err_i(lsu_store_err_i),
+		.wb_exception_o(wb_exception),
+		.id_exception_o(id_exception),
+		.branch_set_i(branch_set),
+		.branch_set_spec_i(branch_set_spec),
+		.branch_not_set_i(branch_not_set),
+		.jump_set_i(jump_set),
+		.csr_mstatus_mie_i(csr_mstatus_mie_i),
+		.irq_pending_i(irq_pending_i),
+		.irqs_i(irqs_i),
+		.irq_nm_i(irq_nm_i),
+		.nmi_mode_o(nmi_mode_o),
+		.csr_save_if_o(csr_save_if_o),
+		.csr_save_id_o(csr_save_id_o),
+		.csr_save_wb_o(csr_save_wb_o),
+		.csr_restore_mret_id_o(csr_restore_mret_id_o),
+		.csr_restore_dret_id_o(csr_restore_dret_id_o),
+		.csr_save_cause_o(csr_save_cause_o),
+		.csr_mtval_o(csr_mtval_o),
+		.priv_mode_i(priv_mode_i),
+		.csr_mstatus_tw_i(csr_mstatus_tw_i),
+		.debug_mode_o(debug_mode_o),
+		.debug_cause_o(debug_cause_o),
+		.debug_csr_save_o(debug_csr_save_o),
+		.debug_req_i(debug_req_i),
+		.debug_single_step_i(debug_single_step_i),
+		.debug_ebreakm_i(debug_ebreakm_i),
+		.debug_ebreaku_i(debug_ebreaku_i),
+		.trigger_match_i(trigger_match_i),
+		.stall_id_i(stall_id),
+		.stall_wb_i(stall_wb),
+		.flush_id_o(flush_id),
+		.ready_wb_i(ready_wb_i),
+		.perf_jump_o(perf_jump_o),
+		.perf_tbranch_o(perf_tbranch_o)
+	);
+	assign multdiv_en_dec = mult_en_dec | div_en_dec;
+	assign lsu_req = (instr_executing ? data_req_allowed & lsu_req_dec : 1'b0);
+	assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0);
+	assign div_en_id = (instr_executing ? div_en_dec : 1'b0);
+	assign lsu_req_o = lsu_req;
+	assign lsu_we_o = lsu_we;
+	assign lsu_type_o = lsu_type;
+	assign lsu_sign_ext_o = lsu_sign_ext;
+	assign lsu_wdata_o = rf_rdata_b_fwd;
+	assign csr_op_en_o = (csr_access_o & instr_executing) & instr_id_done_o;
+	assign alu_operator_ex_o = alu_operator;
+	assign alu_operand_a_ex_o = alu_operand_a;
+	assign alu_operand_b_ex_o = alu_operand_b;
+	assign mult_en_ex_o = mult_en_id;
+	assign div_en_ex_o = div_en_id;
+	assign multdiv_operator_ex_o = multdiv_operator;
+	assign multdiv_signed_mode_ex_o = multdiv_signed_mode;
+	assign multdiv_operand_a_ex_o = rf_rdata_a_fwd;
+	assign multdiv_operand_b_ex_o = rf_rdata_b_fwd;
+	generate
+		if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct
+			assign branch_set_raw = branch_set_raw_d;
+			assign branch_set_raw_spec = branch_spec;
+		end
+		else begin : g_branch_set_flop
+			reg branch_set_raw_q;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					branch_set_raw_q <= 1'b0;
+				else
+					branch_set_raw_q <= branch_set_raw_d;
+			assign branch_set_raw = (BranchTargetALU && !data_ind_timing_i ? branch_set_raw_d : branch_set_raw_q);
+			assign branch_set_raw_spec = (BranchTargetALU && !data_ind_timing_i ? branch_spec : branch_set_raw_q);
+		end
+	endgenerate
+	assign branch_jump_set_done_d = ((branch_set_raw | jump_set_raw) | branch_jump_set_done_q) & ~instr_valid_clear_o;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			branch_jump_set_done_q <= 1'b0;
+		else
+			branch_jump_set_done_q <= branch_jump_set_done_d;
+	assign jump_set = jump_set_raw & ~branch_jump_set_done_q;
+	assign branch_set = branch_set_raw & ~branch_jump_set_done_q;
+	assign branch_set_spec = branch_set_raw_spec & ~branch_jump_set_done_q;
+	generate
+		if (DataIndTiming) begin : g_sec_branch_taken
+			reg branch_taken_q;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					branch_taken_q <= 1'b0;
+				else
+					branch_taken_q <= branch_decision_i;
+			assign branch_taken = ~data_ind_timing_i | branch_taken_q;
+		end
+		else begin : g_nosec_branch_taken
+			assign branch_taken = 1'b1;
+		end
+		if (BranchPredictor) begin : g_calc_nt_addr
+			assign nt_branch_addr_o = pc_id_i + (instr_is_compressed_i ? 32'd2 : 32'd4);
+		end
+		else begin : g_n_calc_nt_addr
+			assign nt_branch_addr_o = 32'd0;
+		end
+	endgenerate
+	assign eFPGA_operand_a_o = rf_rdata_a_fwd;
+	assign eFPGA_operand_b_o = rf_rdata_b_fwd;
+	reg id_fsm_q;
+	reg id_fsm_d;
+	always @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg
+		if (!rst_ni)
+			id_fsm_q <= 1'd0;
+		else if (instr_executing)
+			id_fsm_q <= id_fsm_d;
+	end
+	always @(*) begin
+		id_fsm_d = id_fsm_q;
+		rf_we_raw = rf_we_dec;
+		stall_multdiv = 1'b0;
+		eFPGA_stall = 1'b0;
+		stall_jump = 1'b0;
+		stall_branch = 1'b0;
+		stall_alu = 1'b0;
+		branch_set_raw_d = 1'b0;
+		branch_spec = 1'b0;
+		branch_not_set = 1'b0;
+		jump_set_raw = 1'b0;
+		perf_branch_o = 1'b0;
+		if (instr_executing_spec)
+			case (id_fsm_q)
+				1'd0:
+					case (1'b1)
+						lsu_req_dec:
+							if (!WritebackStage)
+								id_fsm_d = 1'd1;
+							else if (~lsu_req_done_i)
+								id_fsm_d = 1'd1;
+						multdiv_en_dec:
+							if (~ex_valid_i) begin
+								id_fsm_d = 1'd1;
+								rf_we_raw = 1'b0;
+								stall_multdiv = 1'b1;
+							end
+						eFPGA_int_en:
+							if (~ex_valid_i) begin
+								id_fsm_d = 1'd1;
+								rf_we_raw = 1'b0;
+								eFPGA_stall = 1'b1;
+							end
+						branch_in_dec: begin
+							id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i) ? 1'd1 : 1'd0);
+							stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i;
+							branch_set_raw_d = branch_decision_i | data_ind_timing_i;
+							if (BranchPredictor)
+								branch_not_set = ~branch_decision_i;
+							branch_spec = (SpecBranch ? 1'b1 : branch_decision_i);
+							perf_branch_o = 1'b1;
+						end
+						jump_in_dec: begin
+							id_fsm_d = (BranchTargetALU ? 1'd0 : 1'd1);
+							stall_jump = ~BranchTargetALU;
+							jump_set_raw = jump_set_dec;
+						end
+						alu_multicycle_dec: begin
+							stall_alu = 1'b1;
+							id_fsm_d = 1'd1;
+							rf_we_raw = 1'b0;
+						end
+						default: id_fsm_d = 1'd0;
+					endcase
+				1'd1: begin
+					if (multdiv_en_dec)
+						rf_we_raw = rf_we_dec & ex_valid_i;
+					if (multicycle_done & ready_wb_i)
+						id_fsm_d = 1'd0;
+					else begin
+						stall_multdiv = multdiv_en_dec;
+						stall_branch = branch_in_dec;
+						stall_jump = jump_in_dec;
+						eFPGA_stall = eFPGA_int_en;
+					end
+				end
+				default: id_fsm_d = 1'd0;
+			endcase
+	end
+	assign multdiv_ready_id_o = ready_wb_i;
+	assign stall_id = (((((stall_ld_hz | stall_mem) | stall_multdiv) | stall_jump) | stall_branch) | stall_alu) | eFPGA_stall;
+	assign instr_done = (~stall_id & ~flush_id) & instr_executing;
+	assign instr_first_cycle = instr_valid_i & (id_fsm_q == 1'd0);
+	assign instr_first_cycle_id_o = instr_first_cycle;
+	generate
+		if (WritebackStage) begin : gen_stall_mem
+			wire rf_rd_a_wb_match;
+			wire rf_rd_b_wb_match;
+			wire rf_rd_a_hz;
+			wire rf_rd_b_hz;
+			wire outstanding_memory_access;
+			wire instr_kill;
+			assign multicycle_done = (lsu_req_dec ? ~stall_mem : ex_valid_i);
+			assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & ~lsu_resp_valid_i;
+			assign data_req_allowed = ~outstanding_memory_access;
+			assign instr_kill = ((instr_fetch_err_i | wb_exception) | id_exception) | ~controller_run;
+			assign instr_executing_spec = ((instr_valid_i & ~instr_fetch_err_i) & controller_run) & ~stall_ld_hz;
+			assign instr_executing = ((instr_valid_i & ~instr_kill) & ~stall_ld_hz) & ~outstanding_memory_access;
+			assign stall_mem = instr_valid_i & (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i));
+			assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o;
+			assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o;
+			assign rf_rd_a_wb_match_o = rf_rd_a_wb_match;
+			assign rf_rd_b_wb_match_o = rf_rd_b_wb_match;
+			assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a;
+			assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b;
+			assign rf_rdata_a_fwd = (rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i);
+			assign rf_rdata_b_fwd = (rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i);
+			assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz);
+			assign instr_type_wb_o = (~lsu_req_dec ? 2'd2 : (lsu_we ? 2'd1 : 2'd0));
+			assign instr_id_done_o = en_wb_o & ready_wb_i;
+			assign stall_wb = en_wb_o & ~ready_wb_i;
+			assign perf_dside_wait_o = (instr_valid_i & ~instr_kill) & (outstanding_memory_access | stall_ld_hz);
+		end
+		else begin : gen_no_stall_mem
+			assign multicycle_done = (lsu_req_dec ? lsu_resp_valid_i : ex_valid_i);
+			assign data_req_allowed = instr_first_cycle;
+			assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle));
+			assign stall_ld_hz = 1'b0;
+			assign instr_executing_spec = (instr_valid_i & ~instr_fetch_err_i) & controller_run;
+			assign instr_executing = instr_executing_spec;
+			assign rf_rdata_a_fwd = rf_rdata_a_i;
+			assign rf_rdata_b_fwd = rf_rdata_b_i;
+			assign rf_rd_a_wb_match_o = 1'b0;
+			assign rf_rd_b_wb_match_o = 1'b0;
+			wire unused_data_req_done_ex;
+			wire [4:0] unused_rf_waddr_wb;
+			wire unused_rf_write_wb;
+			wire unused_outstanding_load_wb;
+			wire unused_outstanding_store_wb;
+			wire unused_wb_exception;
+			wire [31:0] unused_rf_wdata_fwd_wb;
+			wire unused_id_exception;
+			assign unused_data_req_done_ex = lsu_req_done_i;
+			assign unused_rf_waddr_wb = rf_waddr_wb_i;
+			assign unused_rf_write_wb = rf_write_wb_i;
+			assign unused_outstanding_load_wb = outstanding_load_wb_i;
+			assign unused_outstanding_store_wb = outstanding_store_wb_i;
+			assign unused_wb_exception = wb_exception;
+			assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i;
+			assign unused_id_exception = id_exception;
+			assign instr_type_wb_o = 2'd2;
+			assign stall_wb = 1'b0;
+			assign perf_dside_wait_o = (instr_executing & lsu_req_dec) & ~lsu_resp_valid_i;
+			assign instr_id_done_o = instr_done;
+		end
+	endgenerate
+	assign instr_perf_count_id_o = (((~ebrk_insn & ~ecall_insn_dec) & ~illegal_insn_dec) & ~illegal_csr_insn_i) & ~instr_fetch_err_i;
+	assign en_wb_o = instr_done;
+	assign perf_mul_wait_o = stall_multdiv & mult_en_dec;
+	assign perf_div_wait_o = stall_multdiv & div_en_dec;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_if_stage.v b/verilog/rtl/ibex_core/ibex_if_stage.v
new file mode 100644
index 0000000..eda4468
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_if_stage.v
@@ -0,0 +1,427 @@
+module ibex_if_stage (
+	clk_i,
+	rst_ni,
+	boot_addr_i,
+	req_i,
+	instr_req_o,
+	instr_addr_o,
+	instr_gnt_i,
+	instr_rvalid_i,
+	instr_rdata_i,
+	instr_err_i,
+	instr_pmp_err_i,
+	ic_tag_req_o,
+	ic_tag_write_o,
+	ic_tag_addr_o,
+	ic_tag_wdata_o,
+	ic_tag_rdata_i,
+	ic_data_req_o,
+	ic_data_write_o,
+	ic_data_addr_o,
+	ic_data_wdata_o,
+	ic_data_rdata_i,
+	instr_valid_id_o,
+	instr_new_id_o,
+	instr_rdata_id_o,
+	instr_rdata_alu_id_o,
+	instr_rdata_c_id_o,
+	instr_is_compressed_id_o,
+	instr_bp_taken_o,
+	instr_fetch_err_o,
+	instr_fetch_err_plus2_o,
+	illegal_c_insn_id_o,
+	dummy_instr_id_o,
+	pc_if_o,
+	pc_id_o,
+	instr_valid_clear_i,
+	pc_set_i,
+	pc_set_spec_i,
+	pc_mux_i,
+	nt_branch_mispredict_i,
+	nt_branch_addr_i,
+	exc_pc_mux_i,
+	exc_cause,
+	dummy_instr_en_i,
+	dummy_instr_mask_i,
+	dummy_instr_seed_en_i,
+	dummy_instr_seed_i,
+	icache_enable_i,
+	icache_inval_i,
+	branch_target_ex_i,
+	csr_mepc_i,
+	csr_depc_i,
+	csr_mtvec_i,
+	csr_mtvec_init_o,
+	id_in_ready_i,
+	pc_mismatch_alert_o,
+	if_busy_o
+);
+	parameter [31:0] DmHaltAddr = 32'h1a110800;
+	parameter [31:0] DmExceptionAddr = 32'h1a110808;
+	parameter [0:0] DummyInstructions = 1'b0;
+	parameter [0:0] ICache = 1'b0;
+	parameter [0:0] ICacheECC = 1'b0;
+	localparam [31:0] ibex_pkg_BUS_SIZE = 32;
+	parameter [31:0] BusSizeECC = ibex_pkg_BUS_SIZE;
+	localparam [31:0] ibex_pkg_ADDR_W = 32;
+	localparam [31:0] ibex_pkg_IC_LINE_SIZE = 64;
+	localparam [31:0] ibex_pkg_IC_LINE_BYTES = 8;
+	localparam [31:0] ibex_pkg_IC_NUM_WAYS = 2;
+	localparam [31:0] ibex_pkg_IC_SIZE_BYTES = 4096;
+	localparam [31:0] ibex_pkg_IC_NUM_LINES = (ibex_pkg_IC_SIZE_BYTES / ibex_pkg_IC_NUM_WAYS) / ibex_pkg_IC_LINE_BYTES;
+	localparam [31:0] ibex_pkg_IC_INDEX_W = $clog2(ibex_pkg_IC_NUM_LINES);
+	localparam [31:0] ibex_pkg_IC_LINE_W = 3;
+	localparam [31:0] ibex_pkg_IC_TAG_SIZE = ((ibex_pkg_ADDR_W - ibex_pkg_IC_INDEX_W) - ibex_pkg_IC_LINE_W) + 1;
+	parameter [31:0] TagSizeECC = ibex_pkg_IC_TAG_SIZE;
+	parameter [31:0] LineSizeECC = ibex_pkg_IC_LINE_SIZE;
+	parameter [0:0] PCIncrCheck = 1'b0;
+	parameter [0:0] ResetAll = 1'b0;
+	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
+	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
+	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
+	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
+	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
+	parameter [0:0] BranchPredictor = 1'b0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire [31:0] boot_addr_i;
+	input wire req_i;
+	output wire instr_req_o;
+	output wire [31:0] instr_addr_o;
+	input wire instr_gnt_i;
+	input wire instr_rvalid_i;
+	input wire [31:0] instr_rdata_i;
+	input wire instr_err_i;
+	input wire instr_pmp_err_i;
+	output wire [1:0] ic_tag_req_o;
+	output wire ic_tag_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_tag_addr_o;
+	output wire [TagSizeECC - 1:0] ic_tag_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] ic_tag_rdata_i;
+	output wire [1:0] ic_data_req_o;
+	output wire ic_data_write_o;
+	output wire [ibex_pkg_IC_INDEX_W - 1:0] ic_data_addr_o;
+	output wire [LineSizeECC - 1:0] ic_data_wdata_o;
+	input wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] ic_data_rdata_i;
+	output wire instr_valid_id_o;
+	output wire instr_new_id_o;
+	output reg [31:0] instr_rdata_id_o;
+	output reg [31:0] instr_rdata_alu_id_o;
+	output reg [15:0] instr_rdata_c_id_o;
+	output reg instr_is_compressed_id_o;
+	output wire instr_bp_taken_o;
+	output reg instr_fetch_err_o;
+	output reg instr_fetch_err_plus2_o;
+	output reg illegal_c_insn_id_o;
+	output wire dummy_instr_id_o;
+	output wire [31:0] pc_if_o;
+	output reg [31:0] pc_id_o;
+	input wire instr_valid_clear_i;
+	input wire pc_set_i;
+	input wire pc_set_spec_i;
+	input wire [2:0] pc_mux_i;
+	input wire nt_branch_mispredict_i;
+	input wire [31:0] nt_branch_addr_i;
+	input wire [1:0] exc_pc_mux_i;
+	input wire [5:0] exc_cause;
+	input wire dummy_instr_en_i;
+	input wire [2:0] dummy_instr_mask_i;
+	input wire dummy_instr_seed_en_i;
+	input wire [31:0] dummy_instr_seed_i;
+	input wire icache_enable_i;
+	input wire icache_inval_i;
+	input wire [31:0] branch_target_ex_i;
+	input wire [31:0] csr_mepc_i;
+	input wire [31:0] csr_depc_i;
+	input wire [31:0] csr_mtvec_i;
+	output wire csr_mtvec_init_o;
+	input wire id_in_ready_i;
+	output wire pc_mismatch_alert_o;
+	output wire if_busy_o;
+	wire instr_valid_id_d;
+	reg instr_valid_id_q;
+	wire instr_new_id_d;
+	reg instr_new_id_q;
+	wire prefetch_busy;
+	wire branch_req;
+	wire branch_spec;
+	reg [31:0] fetch_addr_n;
+	wire unused_fetch_addr_n0;
+	wire fetch_valid;
+	wire fetch_ready;
+	wire [31:0] fetch_rdata;
+	wire [31:0] fetch_addr;
+	wire fetch_err;
+	wire fetch_err_plus2;
+	wire if_instr_valid;
+	wire [31:0] if_instr_rdata;
+	wire [31:0] if_instr_addr;
+	wire if_instr_err;
+	reg [31:0] exc_pc;
+	wire [5:0] irq_id;
+	wire unused_irq_bit;
+	wire if_id_pipe_reg_we;
+	wire stall_dummy_instr;
+	wire [31:0] instr_out;
+	wire instr_is_compressed_out;
+	wire illegal_c_instr_out;
+	wire instr_err_out;
+	wire predict_branch_taken;
+	wire [31:0] predict_branch_pc;
+	wire [2:0] pc_mux_internal;
+	wire [7:0] unused_boot_addr;
+	wire [7:0] unused_csr_mtvec;
+	assign unused_boot_addr = boot_addr_i[7:0];
+	assign unused_csr_mtvec = csr_mtvec_i[7:0];
+	assign irq_id = {exc_cause};
+	assign unused_irq_bit = irq_id[5];
+	always @(*) begin : exc_pc_mux
+		case (exc_pc_mux_i)
+			2'd0: exc_pc = {csr_mtvec_i[31:8], 8'h00};
+			2'd1: exc_pc = {csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00};
+			2'd2: exc_pc = DmHaltAddr;
+			2'd3: exc_pc = DmExceptionAddr;
+			default: exc_pc = {csr_mtvec_i[31:8], 8'h00};
+		endcase
+	end
+	assign pc_mux_internal = ((BranchPredictor && predict_branch_taken) && !pc_set_i ? 3'd5 : pc_mux_i);
+	always @(*) begin : fetch_addr_mux
+		case (pc_mux_internal)
+			3'd0: fetch_addr_n = {boot_addr_i[31:8], 8'h80};
+			3'd1: fetch_addr_n = branch_target_ex_i;
+			3'd2: fetch_addr_n = exc_pc;
+			3'd3: fetch_addr_n = csr_mepc_i;
+			3'd4: fetch_addr_n = csr_depc_i;
+			3'd5: fetch_addr_n = (BranchPredictor ? predict_branch_pc : {boot_addr_i[31:8], 8'h80});
+			default: fetch_addr_n = {boot_addr_i[31:8], 8'h80};
+		endcase
+	end
+	assign csr_mtvec_init_o = (pc_mux_i == 3'd0) & pc_set_i;
+	ibex_prefetch_buffer #(.ResetAll(ResetAll)) prefetch_buffer_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.req_i(req_i),
+		.branch_i(branch_req),
+		.branch_spec_i(branch_spec),
+		.branch_mispredict_i(nt_branch_mispredict_i),
+		.mispredict_addr_i(nt_branch_addr_i),
+		.addr_i({fetch_addr_n[31:1], 1'b0}),
+		.ready_i(fetch_ready),
+		.valid_o(fetch_valid),
+		.rdata_o(fetch_rdata),
+		.addr_o(fetch_addr),
+		.err_o(fetch_err),
+		.err_plus2_o(fetch_err_plus2),
+		.instr_req_o(instr_req_o),
+		.instr_addr_o(instr_addr_o),
+		.instr_gnt_i(instr_gnt_i),
+		.instr_rvalid_i(instr_rvalid_i),
+		.instr_rdata_i(instr_rdata_i),
+		.instr_err_i(instr_err_i),
+		.instr_pmp_err_i(instr_pmp_err_i),
+		.busy_o(prefetch_busy)
+	);
+	wire unused_icen;
+	wire unused_icinv;
+	wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] unused_tag_ram_input;
+	wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] unused_data_ram_input;
+	assign unused_icen = icache_enable_i;
+	assign unused_icinv = icache_inval_i;
+	assign unused_tag_ram_input = ic_tag_rdata_i;
+	assign unused_data_ram_input = ic_data_rdata_i;
+	assign ic_tag_req_o = 'b0;
+	assign ic_tag_write_o = 'b0;
+	assign ic_tag_addr_o = 'b0;
+	assign ic_tag_wdata_o = 'b0;
+	assign ic_data_req_o = 'b0;
+	assign ic_data_write_o = 'b0;
+	assign ic_data_addr_o = 'b0;
+	assign ic_data_wdata_o = 'b0;
+	wire unused_icache;
+	wire unused_icacheECC;
+	wire signed [31:0] unused_bussizeECC;
+	assign unused_icache = ICache;
+	assign unused_icacheECC = ICacheECC;
+	assign unused_bussizeECC = BusSizeECC;
+	assign unused_fetch_addr_n0 = fetch_addr_n[0];
+	assign branch_req = pc_set_i | predict_branch_taken;
+	assign branch_spec = pc_set_spec_i | predict_branch_taken;
+	assign pc_if_o = if_instr_addr;
+	assign if_busy_o = prefetch_busy;
+	wire [31:0] instr_decompressed;
+	wire illegal_c_insn;
+	wire instr_is_compressed;
+	ibex_compressed_decoder compressed_decoder_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.valid_i(fetch_valid & ~fetch_err),
+		.instr_i(if_instr_rdata),
+		.instr_o(instr_decompressed),
+		.is_compressed_o(instr_is_compressed),
+		.illegal_instr_o(illegal_c_insn)
+	);
+	wire unused_dummy_en;
+	wire [2:0] unused_dummy_mask;
+	wire unused_dummy_seed_en;
+	wire [31:0] unused_dummy_seed;
+	assign unused_dummy_en = dummy_instr_en_i && DummyInstructions;
+	assign unused_dummy_mask = dummy_instr_mask_i;
+	assign unused_dummy_seed_en = dummy_instr_seed_en_i;
+	assign unused_dummy_seed = dummy_instr_seed_i;
+	assign instr_out = instr_decompressed;
+	assign instr_is_compressed_out = instr_is_compressed;
+	assign illegal_c_instr_out = illegal_c_insn;
+	assign instr_err_out = if_instr_err;
+	assign stall_dummy_instr = 1'b0;
+	assign dummy_instr_id_o = 1'b0;
+	wire [31:0] unused_RndCnstLfsrSeed;
+	assign unused_RndCnstLfsrSeed = RndCnstLfsrSeed;
+	wire [159:0] unused_RndCnstLfsrPerm;
+	assign unused_RndCnstLfsrPerm = RndCnstLfsrPerm;
+	assign instr_valid_id_d = ((if_instr_valid & id_in_ready_i) & ~pc_set_i) | (instr_valid_id_q & ~instr_valid_clear_i);
+	assign instr_new_id_d = if_instr_valid & id_in_ready_i;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			instr_valid_id_q <= 1'b0;
+			instr_new_id_q <= 1'b0;
+		end
+		else begin
+			instr_valid_id_q <= instr_valid_id_d;
+			instr_new_id_q <= instr_new_id_d;
+		end
+	assign instr_valid_id_o = instr_valid_id_q;
+	assign instr_new_id_o = instr_new_id_q;
+	assign if_id_pipe_reg_we = instr_new_id_d;
+	generate
+		if (ResetAll) begin : g_instr_rdata_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni) begin
+					instr_rdata_id_o <= 1'sb0;
+					instr_rdata_alu_id_o <= 1'sb0;
+					instr_fetch_err_o <= 1'sb0;
+					instr_fetch_err_plus2_o <= 1'sb0;
+					instr_rdata_c_id_o <= 1'sb0;
+					instr_is_compressed_id_o <= 1'sb0;
+					illegal_c_insn_id_o <= 1'sb0;
+					pc_id_o <= 1'sb0;
+				end
+				else if (if_id_pipe_reg_we) begin
+					instr_rdata_id_o <= instr_out;
+					instr_rdata_alu_id_o <= instr_out;
+					instr_fetch_err_o <= instr_err_out;
+					instr_fetch_err_plus2_o <= fetch_err_plus2;
+					instr_rdata_c_id_o <= if_instr_rdata[15:0];
+					instr_is_compressed_id_o <= instr_is_compressed_out;
+					illegal_c_insn_id_o <= illegal_c_instr_out;
+					pc_id_o <= pc_if_o;
+				end
+		end
+		else begin : g_instr_rdata_nr
+			always @(posedge clk_i)
+				if (if_id_pipe_reg_we) begin
+					instr_rdata_id_o <= instr_out;
+					instr_rdata_alu_id_o <= instr_out;
+					instr_fetch_err_o <= instr_err_out;
+					instr_fetch_err_plus2_o <= fetch_err_plus2;
+					instr_rdata_c_id_o <= if_instr_rdata[15:0];
+					instr_is_compressed_id_o <= instr_is_compressed_out;
+					illegal_c_insn_id_o <= illegal_c_instr_out;
+					pc_id_o <= pc_if_o;
+				end
+		end
+		if (PCIncrCheck) begin : g_secure_pc
+			wire [31:0] prev_instr_addr_incr;
+			reg prev_instr_seq_q;
+			wire prev_instr_seq_d;
+			assign prev_instr_seq_d = ((prev_instr_seq_q | instr_new_id_d) & ~branch_req) & ~stall_dummy_instr;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					prev_instr_seq_q <= 1'b0;
+				else
+					prev_instr_seq_q <= prev_instr_seq_d;
+			assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o && !instr_fetch_err_o ? 32'd2 : 32'd4);
+			assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr);
+		end
+		else begin : g_no_secure_pc
+			assign pc_mismatch_alert_o = 1'b0;
+		end
+		if (BranchPredictor) begin : g_branch_predictor
+			reg [31:0] instr_skid_data_q;
+			reg [31:0] instr_skid_addr_q;
+			reg instr_skid_bp_taken_q;
+			reg instr_skid_valid_q;
+			wire instr_skid_valid_d;
+			wire instr_skid_en;
+			reg instr_bp_taken_q;
+			wire instr_bp_taken_d;
+			wire predict_branch_taken_raw;
+			if (ResetAll) begin : g_bp_taken_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni)
+						instr_bp_taken_q <= 1'sb0;
+					else if (if_id_pipe_reg_we)
+						instr_bp_taken_q <= instr_bp_taken_d;
+			end
+			else begin : g_bp_taken_nr
+				always @(posedge clk_i)
+					if (if_id_pipe_reg_we)
+						instr_bp_taken_q <= instr_bp_taken_d;
+			end
+			assign instr_skid_en = ((predict_branch_taken & ~pc_set_i) & ~id_in_ready_i) & ~instr_skid_valid_q;
+			assign instr_skid_valid_d = ((instr_skid_valid_q & ~id_in_ready_i) & ~stall_dummy_instr) | instr_skid_en;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					instr_skid_valid_q <= 1'b0;
+				else
+					instr_skid_valid_q <= instr_skid_valid_d;
+			if (ResetAll) begin : g_instr_skid_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni) begin
+						instr_skid_bp_taken_q <= 1'sb0;
+						instr_skid_data_q <= 1'sb0;
+						instr_skid_addr_q <= 1'sb0;
+					end
+					else if (instr_skid_en) begin
+						instr_skid_bp_taken_q <= predict_branch_taken;
+						instr_skid_data_q <= fetch_rdata;
+						instr_skid_addr_q <= fetch_addr;
+					end
+			end
+			else begin : g_instr_skid_nr
+				always @(posedge clk_i)
+					if (instr_skid_en) begin
+						instr_skid_bp_taken_q <= predict_branch_taken;
+						instr_skid_data_q <= fetch_rdata;
+						instr_skid_addr_q <= fetch_addr;
+					end
+			end
+			ibex_branch_predict branch_predict_i(
+				.clk_i(clk_i),
+				.rst_ni(rst_ni),
+				.fetch_rdata_i(fetch_rdata),
+				.fetch_pc_i(fetch_addr),
+				.fetch_valid_i(fetch_valid),
+				.predict_branch_taken_o(predict_branch_taken_raw),
+				.predict_branch_pc_o(predict_branch_pc)
+			);
+			assign predict_branch_taken = (predict_branch_taken_raw & ~instr_skid_valid_q) & ~fetch_err;
+			assign if_instr_valid = fetch_valid | (instr_skid_valid_q & ~nt_branch_mispredict_i);
+			assign if_instr_rdata = (instr_skid_valid_q ? instr_skid_data_q : fetch_rdata);
+			assign if_instr_addr = (instr_skid_valid_q ? instr_skid_addr_q : fetch_addr);
+			assign if_instr_err = ~instr_skid_valid_q & fetch_err;
+			assign instr_bp_taken_d = (instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken);
+			assign fetch_ready = (id_in_ready_i & ~stall_dummy_instr) & ~instr_skid_valid_q;
+			assign instr_bp_taken_o = instr_bp_taken_q;
+		end
+		else begin : g_no_branch_predictor
+			assign instr_bp_taken_o = 1'b0;
+			assign predict_branch_taken = 1'b0;
+			assign predict_branch_pc = 32'b00000000000000000000000000000000;
+			assign if_instr_valid = fetch_valid;
+			assign if_instr_rdata = fetch_rdata;
+			assign if_instr_addr = fetch_addr;
+			assign if_instr_err = fetch_err;
+			assign fetch_ready = id_in_ready_i & ~stall_dummy_instr;
+		end
+	endgenerate
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_load_store_unit.v b/verilog/rtl/ibex_core/ibex_load_store_unit.v
new file mode 100644
index 0000000..c9abb0b
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_load_store_unit.v
@@ -0,0 +1,334 @@
+module ibex_load_store_unit (
+	clk_i,
+	rst_ni,
+	data_req_o,
+	data_gnt_i,
+	data_rvalid_i,
+	data_err_i,
+	data_pmp_err_i,
+	data_addr_o,
+	data_we_o,
+	data_be_o,
+	data_wdata_o,
+	data_rdata_i,
+	lsu_we_i,
+	lsu_type_i,
+	lsu_wdata_i,
+	lsu_sign_ext_i,
+	lsu_rdata_o,
+	lsu_rdata_valid_o,
+	lsu_req_i,
+	adder_result_ex_i,
+	addr_incr_req_o,
+	addr_last_o,
+	lsu_req_done_o,
+	lsu_resp_valid_o,
+	load_err_o,
+	store_err_o,
+	busy_o,
+	perf_load_o,
+	perf_store_o
+);
+	input wire clk_i;
+	input wire rst_ni;
+	output reg data_req_o;
+	input wire data_gnt_i;
+	input wire data_rvalid_i;
+	input wire data_err_i;
+	input wire data_pmp_err_i;
+	output wire [31:0] data_addr_o;
+	output wire data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_wdata_o;
+	input wire [31:0] data_rdata_i;
+	input wire lsu_we_i;
+	input wire [1:0] lsu_type_i;
+	input wire [31:0] lsu_wdata_i;
+	input wire lsu_sign_ext_i;
+	output wire [31:0] lsu_rdata_o;
+	output wire lsu_rdata_valid_o;
+	input wire lsu_req_i;
+	input wire [31:0] adder_result_ex_i;
+	output reg addr_incr_req_o;
+	output wire [31:0] addr_last_o;
+	output wire lsu_req_done_o;
+	output wire lsu_resp_valid_o;
+	output wire load_err_o;
+	output wire store_err_o;
+	output wire busy_o;
+	output reg perf_load_o;
+	output reg perf_store_o;
+	wire [31:0] data_addr;
+	wire [31:0] data_addr_w_aligned;
+	reg [31:0] addr_last_q;
+	wire [31:0] addr_last_d;
+	reg addr_update;
+	reg ctrl_update;
+	reg rdata_update;
+	reg [31:8] rdata_q;
+	reg [1:0] rdata_offset_q;
+	reg [1:0] data_type_q;
+	reg data_sign_ext_q;
+	reg data_we_q;
+	wire [1:0] data_offset;
+	reg [3:0] data_be;
+	reg [31:0] data_wdata;
+	reg [31:0] data_rdata_ext;
+	reg [31:0] rdata_w_ext;
+	reg [31:0] rdata_h_ext;
+	reg [31:0] rdata_b_ext;
+	wire split_misaligned_access;
+	reg handle_misaligned_q;
+	reg handle_misaligned_d;
+	reg pmp_err_q;
+	reg pmp_err_d;
+	reg lsu_err_q;
+	reg lsu_err_d;
+	wire data_or_pmp_err;
+	reg [2:0] ls_fsm_cs;
+	reg [2:0] ls_fsm_ns;
+	assign data_addr = adder_result_ex_i;
+	assign data_offset = data_addr[1:0];
+	always @(*)
+		case (lsu_type_i)
+			2'b00:
+				if (!handle_misaligned_q)
+					case (data_offset)
+						2'b00: data_be = 4'b1111;
+						2'b01: data_be = 4'b1110;
+						2'b10: data_be = 4'b1100;
+						2'b11: data_be = 4'b1000;
+						default: data_be = 4'b1111;
+					endcase
+				else
+					case (data_offset)
+						2'b00: data_be = 4'b0000;
+						2'b01: data_be = 4'b0001;
+						2'b10: data_be = 4'b0011;
+						2'b11: data_be = 4'b0111;
+						default: data_be = 4'b1111;
+					endcase
+			2'b01:
+				if (!handle_misaligned_q)
+					case (data_offset)
+						2'b00: data_be = 4'b0011;
+						2'b01: data_be = 4'b0110;
+						2'b10: data_be = 4'b1100;
+						2'b11: data_be = 4'b1000;
+						default: data_be = 4'b1111;
+					endcase
+				else
+					data_be = 4'b0001;
+			2'b10, 2'b11:
+				case (data_offset)
+					2'b00: data_be = 4'b0001;
+					2'b01: data_be = 4'b0010;
+					2'b10: data_be = 4'b0100;
+					2'b11: data_be = 4'b1000;
+					default: data_be = 4'b1111;
+				endcase
+			default: data_be = 4'b1111;
+		endcase
+	always @(*)
+		case (data_offset)
+			2'b00: data_wdata = lsu_wdata_i[31:0];
+			2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};
+			2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};
+			2'b11: data_wdata = {lsu_wdata_i[7:0], lsu_wdata_i[31:8]};
+			default: data_wdata = lsu_wdata_i[31:0];
+		endcase
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			rdata_q <= 1'sb0;
+		else if (rdata_update)
+			rdata_q <= data_rdata_i[31:8];
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			rdata_offset_q <= 2'h0;
+			data_type_q <= 2'h0;
+			data_sign_ext_q <= 1'b0;
+			data_we_q <= 1'b0;
+		end
+		else if (ctrl_update) begin
+			rdata_offset_q <= data_offset;
+			data_type_q <= lsu_type_i;
+			data_sign_ext_q <= lsu_sign_ext_i;
+			data_we_q <= lsu_we_i;
+		end
+	assign addr_last_d = (addr_incr_req_o ? data_addr_w_aligned : data_addr);
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			addr_last_q <= 1'sb0;
+		else if (addr_update)
+			addr_last_q <= addr_last_d;
+	always @(*)
+		case (rdata_offset_q)
+			2'b00: rdata_w_ext = data_rdata_i[31:0];
+			2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]};
+			2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
+			2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
+			default: rdata_w_ext = data_rdata_i[31:0];
+		endcase
+	always @(*)
+		case (rdata_offset_q)
+			2'b00:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]};
+			2'b01:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]};
+			2'b10:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]};
+			2'b11:
+				if (!data_sign_ext_q)
+					rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
+				else
+					rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
+			default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
+		endcase
+	always @(*)
+		case (rdata_offset_q)
+			2'b00:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[7:0]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]};
+			2'b01:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[15:8]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]};
+			2'b10:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[23:16]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]};
+			2'b11:
+				if (!data_sign_ext_q)
+					rdata_b_ext = {24'h000000, data_rdata_i[31:24]};
+				else
+					rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]};
+			default: rdata_b_ext = {24'h000000, data_rdata_i[7:0]};
+		endcase
+	always @(*)
+		case (data_type_q)
+			2'b00: data_rdata_ext = rdata_w_ext;
+			2'b01: data_rdata_ext = rdata_h_ext;
+			2'b10, 2'b11: data_rdata_ext = rdata_b_ext;
+			default: data_rdata_ext = rdata_w_ext;
+		endcase
+	assign split_misaligned_access = ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || ((lsu_type_i == 2'b01) && (data_offset == 2'b11));
+	always @(*) begin
+		ls_fsm_ns = ls_fsm_cs;
+		data_req_o = 1'b0;
+		addr_incr_req_o = 1'b0;
+		handle_misaligned_d = handle_misaligned_q;
+		pmp_err_d = pmp_err_q;
+		lsu_err_d = lsu_err_q;
+		addr_update = 1'b0;
+		ctrl_update = 1'b0;
+		rdata_update = 1'b0;
+		perf_load_o = 1'b0;
+		perf_store_o = 1'b0;
+		case (ls_fsm_cs)
+			3'd0: begin
+				pmp_err_d = 1'b0;
+				if (lsu_req_i) begin
+					data_req_o = 1'b1;
+					pmp_err_d = data_pmp_err_i;
+					lsu_err_d = 1'b0;
+					perf_load_o = ~lsu_we_i;
+					perf_store_o = lsu_we_i;
+					if (data_gnt_i) begin
+						ctrl_update = 1'b1;
+						addr_update = 1'b1;
+						handle_misaligned_d = split_misaligned_access;
+						ls_fsm_ns = (split_misaligned_access ? 3'd2 : 3'd0);
+					end
+					else
+						ls_fsm_ns = (split_misaligned_access ? 3'd1 : 3'd3);
+				end
+			end
+			3'd1: begin
+				data_req_o = 1'b1;
+				if (data_gnt_i || pmp_err_q) begin
+					addr_update = 1'b1;
+					ctrl_update = 1'b1;
+					handle_misaligned_d = 1'b1;
+					ls_fsm_ns = 3'd2;
+				end
+			end
+			3'd2: begin
+				data_req_o = 1'b1;
+				addr_incr_req_o = 1'b1;
+				if (data_rvalid_i || pmp_err_q) begin
+					pmp_err_d = data_pmp_err_i;
+					lsu_err_d = data_err_i | pmp_err_q;
+					rdata_update = ~data_we_q;
+					ls_fsm_ns = (data_gnt_i ? 3'd0 : 3'd3);
+					addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);
+					handle_misaligned_d = ~data_gnt_i;
+				end
+				else if (data_gnt_i) begin
+					ls_fsm_ns = 3'd4;
+					handle_misaligned_d = 1'b0;
+				end
+			end
+			3'd3: begin
+				addr_incr_req_o = handle_misaligned_q;
+				data_req_o = 1'b1;
+				if (data_gnt_i || pmp_err_q) begin
+					ctrl_update = 1'b1;
+					addr_update = ~lsu_err_q;
+					ls_fsm_ns = 3'd0;
+					handle_misaligned_d = 1'b0;
+				end
+			end
+			3'd4: begin
+				addr_incr_req_o = 1'b1;
+				if (data_rvalid_i) begin
+					pmp_err_d = data_pmp_err_i;
+					lsu_err_d = data_err_i;
+					addr_update = ~data_err_i;
+					rdata_update = ~data_we_q;
+					ls_fsm_ns = 3'd0;
+				end
+			end
+			default: ls_fsm_ns = 3'd0;
+		endcase
+	end
+	assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != 3'd0)) & (ls_fsm_ns == 3'd0);
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			ls_fsm_cs <= 3'd0;
+			handle_misaligned_q <= 1'sb0;
+			pmp_err_q <= 1'sb0;
+			lsu_err_q <= 1'sb0;
+		end
+		else begin
+			ls_fsm_cs <= ls_fsm_ns;
+			handle_misaligned_q <= handle_misaligned_d;
+			pmp_err_q <= pmp_err_d;
+			lsu_err_q <= lsu_err_d;
+		end
+	assign data_or_pmp_err = (lsu_err_q | data_err_i) | pmp_err_q;
+	assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == 3'd0);
+	assign lsu_rdata_valid_o = (((ls_fsm_cs == 3'd0) & data_rvalid_i) & ~data_or_pmp_err) & ~data_we_q;
+	assign lsu_rdata_o = data_rdata_ext;
+	assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
+	assign data_addr_o = data_addr_w_aligned;
+	assign data_wdata_o = data_wdata;
+	assign data_we_o = lsu_we_i;
+	assign data_be_o = data_be;
+	assign addr_last_o = addr_last_q;
+	assign load_err_o = (data_or_pmp_err & ~data_we_q) & lsu_resp_valid_o;
+	assign store_err_o = (data_or_pmp_err & data_we_q) & lsu_resp_valid_o;
+	assign busy_o = ls_fsm_cs != 3'd0;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_multdiv_fast.v b/verilog/rtl/ibex_core/ibex_multdiv_fast.v
new file mode 100644
index 0000000..8922093
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_multdiv_fast.v
@@ -0,0 +1,383 @@
+module ibex_multdiv_fast (
+	clk_i,
+	rst_ni,
+	mult_en_i,
+	div_en_i,
+	mult_sel_i,
+	div_sel_i,
+	operator_i,
+	signed_mode_i,
+	op_a_i,
+	op_b_i,
+	alu_adder_ext_i,
+	alu_adder_i,
+	equal_to_zero_i,
+	data_ind_timing_i,
+	alu_operand_a_o,
+	alu_operand_b_o,
+	imd_val_q_i,
+	imd_val_d_o,
+	imd_val_we_o,
+	multdiv_ready_id_i,
+	multdiv_result_o,
+	valid_o
+);
+	parameter integer RV32M = 32'sd2;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire mult_en_i;
+	input wire div_en_i;
+	input wire mult_sel_i;
+	input wire div_sel_i;
+	input wire [1:0] operator_i;
+	input wire [1:0] signed_mode_i;
+	input wire [31:0] op_a_i;
+	input wire [31:0] op_b_i;
+	input wire [33:0] alu_adder_ext_i;
+	input wire [31:0] alu_adder_i;
+	input wire equal_to_zero_i;
+	input wire data_ind_timing_i;
+	output reg [32:0] alu_operand_a_o;
+	output reg [32:0] alu_operand_b_o;
+	input wire [67:0] imd_val_q_i;
+	output wire [67:0] imd_val_d_o;
+	output wire [1:0] imd_val_we_o;
+	input wire multdiv_ready_id_i;
+	output wire [31:0] multdiv_result_o;
+	output wire valid_o;
+	wire signed [34:0] mac_res_signed;
+	wire [34:0] mac_res_ext;
+	reg [33:0] accum;
+	reg sign_a;
+	reg sign_b;
+	reg mult_valid;
+	wire signed_mult;
+	reg [33:0] mac_res_d;
+	reg [33:0] op_remainder_d;
+	wire [33:0] mac_res;
+	wire div_sign_a;
+	wire div_sign_b;
+	reg is_greater_equal;
+	wire div_change_sign;
+	wire rem_change_sign;
+	wire [31:0] one_shift;
+	wire [31:0] op_denominator_q;
+	reg [31:0] op_numerator_q;
+	reg [31:0] op_quotient_q;
+	reg [31:0] op_denominator_d;
+	reg [31:0] op_numerator_d;
+	reg [31:0] op_quotient_d;
+	wire [31:0] next_remainder;
+	wire [32:0] next_quotient;
+	wire [31:0] res_adder_h;
+	reg div_valid;
+	reg [4:0] div_counter_q;
+	reg [4:0] div_counter_d;
+	wire multdiv_en;
+	reg mult_hold;
+	reg div_hold;
+	reg div_by_zero_d;
+	reg div_by_zero_q;
+	wire mult_en_internal;
+	wire div_en_internal;
+	reg [2:0] md_state_q;
+	reg [2:0] md_state_d;
+	wire unused_mult_sel_i;
+	assign unused_mult_sel_i = mult_sel_i;
+	assign mult_en_internal = mult_en_i & ~mult_hold;
+	assign div_en_internal = div_en_i & ~div_hold;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			div_counter_q <= 1'sb0;
+			md_state_q <= 3'd0;
+			op_numerator_q <= 1'sb0;
+			op_quotient_q <= 1'sb0;
+			div_by_zero_q <= 1'sb0;
+		end
+		else if (div_en_internal) begin
+			div_counter_q <= div_counter_d;
+			op_numerator_q <= op_numerator_d;
+			op_quotient_q <= op_quotient_d;
+			md_state_q <= md_state_d;
+			div_by_zero_q <= div_by_zero_d;
+		end
+	assign multdiv_en = mult_en_internal | div_en_internal;
+	assign imd_val_d_o[34+:34] = (div_sel_i ? op_remainder_d : mac_res_d);
+	assign imd_val_we_o[0] = multdiv_en;
+	assign imd_val_d_o[0+:34] = {2'b00, op_denominator_d};
+	assign imd_val_we_o[1] = div_en_internal;
+	assign op_denominator_q = imd_val_q_i[31-:32];
+	wire [1:0] unused_imd_val;
+	assign unused_imd_val = imd_val_q_i[33-:2];
+	wire unused_mac_res_ext;
+	assign unused_mac_res_ext = mac_res_ext[34];
+	assign signed_mult = signed_mode_i != 2'b00;
+	assign multdiv_result_o = (div_sel_i ? imd_val_q_i[65-:32] : mac_res_d[31:0]);
+	generate
+		if (RV32M == 32'sd3) begin : gen_mult_single_cycle
+			reg mult_state_q;
+			reg mult_state_d;
+			wire signed [33:0] mult1_res;
+			wire signed [33:0] mult2_res;
+			wire signed [33:0] mult3_res;
+			wire [33:0] mult1_res_uns;
+			wire [33:32] unused_mult1_res_uns;
+			wire [15:0] mult1_op_a;
+			wire [15:0] mult1_op_b;
+			wire [15:0] mult2_op_a;
+			wire [15:0] mult2_op_b;
+			reg [15:0] mult3_op_a;
+			reg [15:0] mult3_op_b;
+			wire mult1_sign_a;
+			wire mult1_sign_b;
+			wire mult2_sign_a;
+			wire mult2_sign_b;
+			reg mult3_sign_a;
+			reg mult3_sign_b;
+			reg [33:0] summand1;
+			reg [33:0] summand2;
+			reg [33:0] summand3;
+			assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b});
+			assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b});
+			assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b});
+			assign mac_res_signed = ($signed(summand1) + $signed(summand2)) + $signed(summand3);
+			assign mult1_res_uns = $unsigned(mult1_res);
+			assign mac_res_ext = $unsigned(mac_res_signed);
+			assign mac_res = mac_res_ext[33:0];
+			wire [1:1] sv2v_tmp_822BD;
+			assign sv2v_tmp_822BD = signed_mode_i[0] & op_a_i[31];
+			always @(*) sign_a = sv2v_tmp_822BD;
+			wire [1:1] sv2v_tmp_4DE54;
+			assign sv2v_tmp_4DE54 = signed_mode_i[1] & op_b_i[31];
+			always @(*) sign_b = sv2v_tmp_4DE54;
+			assign mult1_sign_a = 1'b0;
+			assign mult1_sign_b = 1'b0;
+			assign mult1_op_a = op_a_i[15:0];
+			assign mult1_op_b = op_b_i[15:0];
+			assign mult2_sign_a = 1'b0;
+			assign mult2_sign_b = sign_b;
+			assign mult2_op_a = op_a_i[15:0];
+			assign mult2_op_b = op_b_i[31:16];
+			wire [18:1] sv2v_tmp_915C6;
+			assign sv2v_tmp_915C6 = imd_val_q_i[67-:18];
+			always @(*) accum[17:0] = sv2v_tmp_915C6;
+			wire [16:1] sv2v_tmp_2094F;
+			assign sv2v_tmp_2094F = {16 {signed_mult & imd_val_q_i[67]}};
+			always @(*) accum[33:18] = sv2v_tmp_2094F;
+			always @(*) begin
+				mult3_sign_a = sign_a;
+				mult3_sign_b = 1'b0;
+				mult3_op_a = op_a_i[31:16];
+				mult3_op_b = op_b_i[15:0];
+				summand1 = {18'h00000, mult1_res_uns[31:16]};
+				summand2 = $unsigned(mult2_res);
+				summand3 = $unsigned(mult3_res);
+				mac_res_d = {2'b00, mac_res[15:0], mult1_res_uns[15:0]};
+				mult_valid = mult_en_i;
+				mult_state_d = 1'd0;
+				mult_hold = 1'b0;
+				case (mult_state_q)
+					1'd0:
+						if (operator_i != 2'd0) begin
+							mac_res_d = mac_res;
+							mult_valid = 1'b0;
+							mult_state_d = 1'd1;
+						end
+						else
+							mult_hold = ~multdiv_ready_id_i;
+					1'd1: begin
+						mult3_sign_a = sign_a;
+						mult3_sign_b = sign_b;
+						mult3_op_a = op_a_i[31:16];
+						mult3_op_b = op_b_i[31:16];
+						mac_res_d = mac_res;
+						summand1 = 1'sb0;
+						summand2 = accum;
+						summand3 = $unsigned(mult3_res);
+						mult_state_d = 1'd0;
+						mult_valid = 1'b1;
+						mult_hold = ~multdiv_ready_id_i;
+					end
+					default: mult_state_d = 1'd0;
+				endcase
+			end
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					mult_state_q <= 1'd0;
+				else if (mult_en_internal)
+					mult_state_q <= mult_state_d;
+			assign unused_mult1_res_uns = mult1_res_uns[33:32];
+		end
+		else begin : gen_mult_fast
+			reg [15:0] mult_op_a;
+			reg [15:0] mult_op_b;
+			reg [1:0] mult_state_q;
+			reg [1:0] mult_state_d;
+			assign mac_res_signed = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum);
+			assign mac_res_ext = $unsigned(mac_res_signed);
+			assign mac_res = mac_res_ext[33:0];
+			always @(*) begin
+				mult_op_a = op_a_i[15:0];
+				mult_op_b = op_b_i[15:0];
+				sign_a = 1'b0;
+				sign_b = 1'b0;
+				accum = imd_val_q_i[34+:34];
+				mac_res_d = mac_res;
+				mult_state_d = mult_state_q;
+				mult_valid = 1'b0;
+				mult_hold = 1'b0;
+				case (mult_state_q)
+					2'd0: begin
+						mult_op_a = op_a_i[15:0];
+						mult_op_b = op_b_i[15:0];
+						sign_a = 1'b0;
+						sign_b = 1'b0;
+						accum = 1'sb0;
+						mac_res_d = mac_res;
+						mult_state_d = 2'd1;
+					end
+					2'd1: begin
+						mult_op_a = op_a_i[15:0];
+						mult_op_b = op_b_i[31:16];
+						sign_a = 1'b0;
+						sign_b = signed_mode_i[1] & op_b_i[31];
+						accum = {18'b000000000000000000, imd_val_q_i[65-:16]};
+						if (operator_i == 2'd0)
+							mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]};
+						else
+							mac_res_d = mac_res;
+						mult_state_d = 2'd2;
+					end
+					2'd2: begin
+						mult_op_a = op_a_i[31:16];
+						mult_op_b = op_b_i[15:0];
+						sign_a = signed_mode_i[0] & op_a_i[31];
+						sign_b = 1'b0;
+						if (operator_i == 2'd0) begin
+							accum = {18'b000000000000000000, imd_val_q_i[65-:16]};
+							mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]};
+							mult_valid = 1'b1;
+							mult_state_d = 2'd0;
+							mult_hold = ~multdiv_ready_id_i;
+						end
+						else begin
+							accum = imd_val_q_i[34+:34];
+							mac_res_d = mac_res;
+							mult_state_d = 2'd3;
+						end
+					end
+					2'd3: begin
+						mult_op_a = op_a_i[31:16];
+						mult_op_b = op_b_i[31:16];
+						sign_a = signed_mode_i[0] & op_a_i[31];
+						sign_b = signed_mode_i[1] & op_b_i[31];
+						accum[17:0] = imd_val_q_i[67-:18];
+						accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}};
+						mac_res_d = mac_res;
+						mult_valid = 1'b1;
+						mult_state_d = 2'd0;
+						mult_hold = ~multdiv_ready_id_i;
+					end
+					default: mult_state_d = 2'd0;
+				endcase
+			end
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					mult_state_q <= 2'd0;
+				else if (mult_en_internal)
+					mult_state_q <= mult_state_d;
+		end
+	endgenerate
+	assign res_adder_h = alu_adder_ext_i[32:1];
+	wire [1:0] unused_alu_adder_ext;
+	assign unused_alu_adder_ext = {alu_adder_ext_i[33], alu_adder_ext_i[0]};
+	assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[65-:32]);
+	assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q});
+	assign one_shift = 32'b00000000000000000000000000000001 << div_counter_q;
+	always @(*)
+		if ((imd_val_q_i[65] ^ op_denominator_q[31]) == 1'b0)
+			is_greater_equal = res_adder_h[31] == 1'b0;
+		else
+			is_greater_equal = imd_val_q_i[65];
+	assign div_sign_a = op_a_i[31] & signed_mode_i[0];
+	assign div_sign_b = op_b_i[31] & signed_mode_i[1];
+	assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q;
+	assign rem_change_sign = div_sign_a;
+	always @(*) begin
+		div_counter_d = div_counter_q - 5'h01;
+		op_remainder_d = imd_val_q_i[34+:34];
+		op_quotient_d = op_quotient_q;
+		md_state_d = md_state_q;
+		op_numerator_d = op_numerator_q;
+		op_denominator_d = op_denominator_q;
+		alu_operand_a_o = 33'b000000000000000000000000000000001;
+		alu_operand_b_o = {~op_b_i, 1'b1};
+		div_valid = 1'b0;
+		div_hold = 1'b0;
+		div_by_zero_d = div_by_zero_q;
+		case (md_state_q)
+			3'd0: begin
+				if (operator_i == 2'd2) begin
+					op_remainder_d = 1'sb1;
+					md_state_d = (!data_ind_timing_i && equal_to_zero_i ? 3'd6 : 3'd1);
+					div_by_zero_d = equal_to_zero_i;
+				end
+				else begin
+					op_remainder_d = {2'b00, op_a_i};
+					md_state_d = (!data_ind_timing_i && equal_to_zero_i ? 3'd6 : 3'd1);
+				end
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_b_i, 1'b1};
+				div_counter_d = 5'd31;
+			end
+			3'd1: begin
+				op_quotient_d = 1'sb0;
+				op_numerator_d = (div_sign_a ? alu_adder_i : op_a_i);
+				md_state_d = 3'd2;
+				div_counter_d = 5'd31;
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_a_i, 1'b1};
+			end
+			3'd2: begin
+				op_remainder_d = {33'h000000000, op_numerator_q[31]};
+				op_denominator_d = (div_sign_b ? alu_adder_i : op_b_i);
+				md_state_d = 3'd3;
+				div_counter_d = 5'd31;
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~op_b_i, 1'b1};
+			end
+			3'd3: begin
+				op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]};
+				op_quotient_d = next_quotient[31:0];
+				md_state_d = (div_counter_q == 5'd1 ? 3'd4 : 3'd3);
+				alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1};
+				alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
+			end
+			3'd4: begin
+				if (operator_i == 2'd2)
+					op_remainder_d = {1'b0, next_quotient};
+				else
+					op_remainder_d = {2'b00, next_remainder[31:0]};
+				alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1};
+				alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
+				md_state_d = 3'd5;
+			end
+			3'd5: begin
+				md_state_d = 3'd6;
+				if (operator_i == 2'd2)
+					op_remainder_d = (div_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]);
+				else
+					op_remainder_d = (rem_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]);
+				alu_operand_a_o = 33'b000000000000000000000000000000001;
+				alu_operand_b_o = {~imd_val_q_i[65-:32], 1'b1};
+			end
+			3'd6: begin
+				md_state_d = 3'd0;
+				div_hold = ~multdiv_ready_id_i;
+				div_valid = 1'b1;
+			end
+			default: md_state_d = 3'd0;
+		endcase
+	end
+	assign valid_o = mult_valid | div_valid;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_multdiv_slow.v b/verilog/rtl/ibex_core/ibex_multdiv_slow.v
new file mode 100644
index 0000000..43ca1bf
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_multdiv_slow.v
@@ -0,0 +1,268 @@
+module ibex_multdiv_slow (
+	clk_i,
+	rst_ni,
+	mult_en_i,
+	div_en_i,
+	mult_sel_i,
+	div_sel_i,
+	operator_i,
+	signed_mode_i,
+	op_a_i,
+	op_b_i,
+	alu_adder_ext_i,
+	alu_adder_i,
+	equal_to_zero_i,
+	data_ind_timing_i,
+	alu_operand_a_o,
+	alu_operand_b_o,
+	imd_val_q_i,
+	imd_val_d_o,
+	imd_val_we_o,
+	multdiv_ready_id_i,
+	multdiv_result_o,
+	valid_o
+);
+	input wire clk_i;
+	input wire rst_ni;
+	input wire mult_en_i;
+	input wire div_en_i;
+	input wire mult_sel_i;
+	input wire div_sel_i;
+	input wire [1:0] operator_i;
+	input wire [1:0] signed_mode_i;
+	input wire [31:0] op_a_i;
+	input wire [31:0] op_b_i;
+	input wire [33:0] alu_adder_ext_i;
+	input wire [31:0] alu_adder_i;
+	input wire equal_to_zero_i;
+	input wire data_ind_timing_i;
+	output reg [32:0] alu_operand_a_o;
+	output reg [32:0] alu_operand_b_o;
+	input wire [67:0] imd_val_q_i;
+	output wire [67:0] imd_val_d_o;
+	output wire [1:0] imd_val_we_o;
+	input wire multdiv_ready_id_i;
+	output wire [31:0] multdiv_result_o;
+	output wire valid_o;
+	reg [2:0] md_state_q;
+	reg [2:0] md_state_d;
+	wire [32:0] accum_window_q;
+	reg [32:0] accum_window_d;
+	wire unused_imd_val0;
+	wire [1:0] unused_imd_val1;
+	wire [32:0] res_adder_l;
+	wire [32:0] res_adder_h;
+	reg [4:0] multdiv_count_q;
+	reg [4:0] multdiv_count_d;
+	reg [32:0] op_b_shift_q;
+	reg [32:0] op_b_shift_d;
+	reg [32:0] op_a_shift_q;
+	reg [32:0] op_a_shift_d;
+	wire [32:0] op_a_ext;
+	wire [32:0] op_b_ext;
+	wire [32:0] one_shift;
+	wire [32:0] op_a_bw_pp;
+	wire [32:0] op_a_bw_last_pp;
+	wire [31:0] b_0;
+	wire sign_a;
+	wire sign_b;
+	wire [32:0] next_quotient;
+	wire [31:0] next_remainder;
+	wire [31:0] op_numerator_q;
+	reg [31:0] op_numerator_d;
+	wire is_greater_equal;
+	wire div_change_sign;
+	wire rem_change_sign;
+	reg div_by_zero_d;
+	reg div_by_zero_q;
+	reg multdiv_hold;
+	wire multdiv_en;
+	assign res_adder_l = alu_adder_ext_i[32:0];
+	assign res_adder_h = alu_adder_ext_i[33:1];
+	assign imd_val_d_o[34+:34] = {1'b0, accum_window_d};
+	assign imd_val_we_o[0] = ~multdiv_hold;
+	assign accum_window_q = imd_val_q_i[66-:33];
+	assign unused_imd_val0 = imd_val_q_i[67];
+	assign imd_val_d_o[0+:34] = {2'b00, op_numerator_d};
+	assign imd_val_we_o[1] = multdiv_en;
+	assign op_numerator_q = imd_val_q_i[31-:32];
+	assign unused_imd_val1 = imd_val_q_i[33-:2];
+	always @(*) begin
+		alu_operand_a_o = accum_window_q;
+		case (operator_i)
+			2'd0: alu_operand_b_o = op_a_bw_pp;
+			2'd1: alu_operand_b_o = (md_state_q == 3'd4 ? op_a_bw_last_pp : op_a_bw_pp);
+			2'd2, 2'd3:
+				case (md_state_q)
+					3'd0: begin
+						alu_operand_a_o = 33'b000000000000000000000000000000001;
+						alu_operand_b_o = {~op_b_i, 1'b1};
+					end
+					3'd1: begin
+						alu_operand_a_o = 33'b000000000000000000000000000000001;
+						alu_operand_b_o = {~op_a_i, 1'b1};
+					end
+					3'd2: begin
+						alu_operand_a_o = 33'b000000000000000000000000000000001;
+						alu_operand_b_o = {~op_b_i, 1'b1};
+					end
+					3'd5: begin
+						alu_operand_a_o = 33'b000000000000000000000000000000001;
+						alu_operand_b_o = {~accum_window_q[31:0], 1'b1};
+					end
+					default: begin
+						alu_operand_a_o = {accum_window_q[31:0], 1'b1};
+						alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};
+					end
+				endcase
+			default: begin
+				alu_operand_a_o = accum_window_q;
+				alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};
+			end
+		endcase
+	end
+	assign b_0 = {32 {op_b_shift_q[0]}};
+	assign op_a_bw_pp = {~(op_a_shift_q[32] & op_b_shift_q[0]), op_a_shift_q[31:0] & b_0};
+	assign op_a_bw_last_pp = {op_a_shift_q[32] & op_b_shift_q[0], ~(op_a_shift_q[31:0] & b_0)};
+	assign sign_a = op_a_i[31] & signed_mode_i[0];
+	assign sign_b = op_b_i[31] & signed_mode_i[1];
+	assign op_a_ext = {sign_a, op_a_i};
+	assign op_b_ext = {sign_b, op_b_i};
+	assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31] ? ~res_adder_h[31] : accum_window_q[31]);
+	assign one_shift = 33'b000000000000000000000000000000001 << multdiv_count_q;
+	assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]);
+	assign next_quotient = (is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q);
+	assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q;
+	assign rem_change_sign = sign_a;
+	always @(*) begin
+		multdiv_count_d = multdiv_count_q;
+		accum_window_d = accum_window_q;
+		op_b_shift_d = op_b_shift_q;
+		op_a_shift_d = op_a_shift_q;
+		op_numerator_d = op_numerator_q;
+		md_state_d = md_state_q;
+		multdiv_hold = 1'b0;
+		div_by_zero_d = div_by_zero_q;
+		if (mult_sel_i || div_sel_i)
+			case (md_state_q)
+				3'd0: begin
+					case (operator_i)
+						2'd0: begin
+							op_a_shift_d = op_a_ext << 1;
+							accum_window_d = {~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:0] & {32 {op_b_i[0]}}};
+							op_b_shift_d = op_b_ext >> 1;
+							md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0) ? 3'd4 : 3'd3);
+						end
+						2'd1: begin
+							op_a_shift_d = op_a_ext;
+							accum_window_d = {1'b1, ~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:1] & {31 {op_b_i[0]}}};
+							op_b_shift_d = op_b_ext >> 1;
+							md_state_d = 3'd3;
+						end
+						2'd2: begin
+							accum_window_d = {33 {1'b1}};
+							md_state_d = (!data_ind_timing_i && equal_to_zero_i ? 3'd6 : 3'd1);
+							div_by_zero_d = equal_to_zero_i;
+						end
+						2'd3: begin
+							accum_window_d = op_a_ext;
+							md_state_d = (!data_ind_timing_i && equal_to_zero_i ? 3'd6 : 3'd1);
+						end
+						default:
+							;
+					endcase
+					multdiv_count_d = 5'd31;
+				end
+				3'd1: begin
+					op_a_shift_d = 1'sb0;
+					op_numerator_d = (sign_a ? alu_adder_i : op_a_i);
+					md_state_d = 3'd2;
+				end
+				3'd2: begin
+					accum_window_d = {32'h00000000, op_numerator_q[31]};
+					op_b_shift_d = (sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i});
+					md_state_d = 3'd3;
+				end
+				3'd3: begin
+					multdiv_count_d = multdiv_count_q - 5'h01;
+					case (operator_i)
+						2'd0: begin
+							accum_window_d = res_adder_l;
+							op_a_shift_d = op_a_shift_q << 1;
+							op_b_shift_d = op_b_shift_q >> 1;
+							md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || (multdiv_count_q == 5'd1) ? 3'd4 : 3'd3);
+						end
+						2'd1: begin
+							accum_window_d = res_adder_h;
+							op_a_shift_d = op_a_shift_q;
+							op_b_shift_d = op_b_shift_q >> 1;
+							md_state_d = (multdiv_count_q == 5'd1 ? 3'd4 : 3'd3);
+						end
+						2'd2, 2'd3: begin
+							accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]};
+							op_a_shift_d = next_quotient;
+							md_state_d = (multdiv_count_q == 5'd1 ? 3'd4 : 3'd3);
+						end
+						default:
+							;
+					endcase
+				end
+				3'd4:
+					case (operator_i)
+						2'd0: begin
+							accum_window_d = res_adder_l;
+							md_state_d = 3'd0;
+							multdiv_hold = ~multdiv_ready_id_i;
+						end
+						2'd1: begin
+							accum_window_d = res_adder_l;
+							md_state_d = 3'd0;
+							md_state_d = 3'd0;
+							multdiv_hold = ~multdiv_ready_id_i;
+						end
+						2'd2: begin
+							accum_window_d = next_quotient;
+							md_state_d = 3'd5;
+						end
+						2'd3: begin
+							accum_window_d = {1'b0, next_remainder[31:0]};
+							md_state_d = 3'd5;
+						end
+						default:
+							;
+					endcase
+				3'd5: begin
+					md_state_d = 3'd6;
+					case (operator_i)
+						2'd2: accum_window_d = (div_change_sign ? {1'b0, alu_adder_i} : accum_window_q);
+						2'd3: accum_window_d = (rem_change_sign ? {1'b0, alu_adder_i} : accum_window_q);
+						default:
+							;
+					endcase
+				end
+				3'd6: begin
+					md_state_d = 3'd0;
+					multdiv_hold = ~multdiv_ready_id_i;
+				end
+				default: md_state_d = 3'd0;
+			endcase
+	end
+	assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			multdiv_count_q <= 5'h00;
+			op_b_shift_q <= 33'h000000000;
+			op_a_shift_q <= 33'h000000000;
+			md_state_q <= 3'd0;
+			div_by_zero_q <= 1'b0;
+		end
+		else if (multdiv_en) begin
+			multdiv_count_q <= multdiv_count_d;
+			op_b_shift_q <= op_b_shift_d;
+			op_a_shift_q <= op_a_shift_d;
+			md_state_q <= md_state_d;
+			div_by_zero_q <= div_by_zero_d;
+		end
+	assign valid_o = (md_state_q == 3'd6) | ((md_state_q == 3'd4) & ((operator_i == 2'd0) | (operator_i == 2'd1)));
+	assign multdiv_result_o = (div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]);
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_poly16_mul.v b/verilog/rtl/ibex_core/ibex_poly16_mul.v
new file mode 100644
index 0000000..e7e7ea0
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_poly16_mul.v
@@ -0,0 +1,708 @@
+module ibex_poly16_mul (
+	a,
+	b,
+	r
+);
+	input wire [15:0] a;
+	input wire [15:0] b;
+	output wire [31:0] r;
+	wire t1;
+	wire t2;
+	wire t3;
+	wire t4;
+	wire t5;
+	wire t6;
+	wire t7;
+	wire t8;
+	wire t9;
+	wire t10;
+	wire t11;
+	wire t12;
+	wire t13;
+	wire t14;
+	wire t15;
+	wire t16;
+	wire t17;
+	wire t18;
+	wire t19;
+	wire t20;
+	wire t21;
+	wire t22;
+	wire t23;
+	wire t24;
+	wire t25;
+	wire t26;
+	wire t27;
+	wire t28;
+	wire t29;
+	wire t30;
+	wire t31;
+	wire t32;
+	wire t33;
+	wire t34;
+	wire t35;
+	wire t36;
+	wire t37;
+	wire t38;
+	wire t39;
+	wire t40;
+	wire t41;
+	wire t42;
+	wire t43;
+	wire t44;
+	wire t45;
+	wire t46;
+	wire t47;
+	wire t48;
+	wire t49;
+	wire t50;
+	wire t51;
+	wire t52;
+	wire t53;
+	wire t54;
+	wire t55;
+	wire t56;
+	wire t57;
+	wire t58;
+	wire t59;
+	wire t60;
+	wire t61;
+	wire t62;
+	wire t63;
+	wire t64;
+	wire t65;
+	wire t66;
+	wire t67;
+	wire t68;
+	wire t69;
+	wire t70;
+	wire t71;
+	wire t72;
+	wire t73;
+	wire t74;
+	wire t75;
+	wire t76;
+	wire t77;
+	wire t78;
+	wire t79;
+	wire t80;
+	wire t81;
+	wire t82;
+	wire t83;
+	wire t84;
+	wire t85;
+	wire t86;
+	wire t87;
+	wire t88;
+	wire t89;
+	wire t90;
+	wire t91;
+	wire t92;
+	wire t93;
+	wire t94;
+	wire t95;
+	wire t96;
+	wire t97;
+	wire t98;
+	wire t99;
+	wire t100;
+	wire t101;
+	wire t102;
+	wire t103;
+	wire t104;
+	wire t105;
+	wire t106;
+	wire t107;
+	wire t108;
+	wire t109;
+	wire t110;
+	wire t111;
+	wire t112;
+	wire t113;
+	wire t114;
+	wire t115;
+	wire t116;
+	wire t117;
+	wire t118;
+	wire t119;
+	wire t120;
+	wire t121;
+	wire t122;
+	wire t123;
+	wire t124;
+	wire t125;
+	wire t126;
+	wire t127;
+	wire t128;
+	wire t129;
+	wire t130;
+	wire t131;
+	wire t132;
+	wire t133;
+	wire t134;
+	wire t135;
+	wire t136;
+	wire t137;
+	wire t138;
+	wire t139;
+	wire t140;
+	wire t141;
+	wire t142;
+	wire t143;
+	wire t144;
+	wire t145;
+	wire t146;
+	wire t147;
+	wire t148;
+	wire t149;
+	wire t150;
+	wire t151;
+	wire t152;
+	wire t153;
+	wire t154;
+	wire t155;
+	wire t156;
+	wire t157;
+	wire t158;
+	wire t159;
+	wire t160;
+	wire t161;
+	wire t162;
+	wire t163;
+	wire t164;
+	wire t165;
+	wire t166;
+	wire t167;
+	wire t168;
+	wire t169;
+	wire t170;
+	wire t171;
+	wire t172;
+	wire t173;
+	wire t174;
+	wire t175;
+	wire t176;
+	wire t177;
+	wire t178;
+	wire t179;
+	wire t180;
+	wire t181;
+	wire t182;
+	wire t183;
+	wire t184;
+	wire t185;
+	wire t186;
+	wire t187;
+	wire t188;
+	wire t189;
+	wire t190;
+	wire t191;
+	wire t192;
+	wire t193;
+	wire t194;
+	wire t195;
+	wire t196;
+	wire t197;
+	wire t198;
+	wire t199;
+	wire t200;
+	wire t201;
+	wire t202;
+	wire t203;
+	wire t204;
+	wire t205;
+	wire t206;
+	wire t207;
+	wire t208;
+	wire t209;
+	wire t210;
+	wire t211;
+	wire t212;
+	wire t213;
+	wire t214;
+	wire t215;
+	wire t216;
+	wire t217;
+	wire t218;
+	wire t219;
+	wire t220;
+	wire t221;
+	wire t222;
+	wire t223;
+	wire t224;
+	wire t225;
+	wire t226;
+	wire t227;
+	wire t228;
+	wire t229;
+	wire t230;
+	wire t231;
+	wire t232;
+	wire t233;
+	wire t234;
+	wire t235;
+	wire t236;
+	wire t237;
+	wire t238;
+	wire t239;
+	wire t240;
+	wire t241;
+	wire t242;
+	wire t243;
+	wire t244;
+	wire t245;
+	wire t246;
+	wire t247;
+	wire t248;
+	wire t249;
+	wire t250;
+	wire t251;
+	wire t252;
+	wire t253;
+	wire t254;
+	wire t255;
+	wire t256;
+	wire t257;
+	wire t258;
+	wire t259;
+	wire t260;
+	wire t261;
+	wire t262;
+	wire t263;
+	wire t264;
+	wire t265;
+	wire t266;
+	wire t267;
+	wire t268;
+	wire t269;
+	wire t270;
+	wire t271;
+	wire t272;
+	wire t273;
+	wire t274;
+	wire t275;
+	wire t276;
+	wire t277;
+	wire t278;
+	wire t279;
+	wire t280;
+	wire t281;
+	wire t282;
+	wire t283;
+	wire t284;
+	wire t285;
+	wire t286;
+	wire t287;
+	wire t288;
+	wire t289;
+	wire t290;
+	wire t291;
+	wire t292;
+	wire t293;
+	wire t294;
+	wire t295;
+	wire t296;
+	wire t297;
+	wire t298;
+	wire t299;
+	wire t300;
+	wire t301;
+	wire t302;
+	wire t303;
+	wire t304;
+	wire t305;
+	wire t306;
+	wire t307;
+	wire t308;
+	wire t309;
+	wire t310;
+	wire t311;
+	wire t312;
+	wire t313;
+	wire t314;
+	wire t315;
+	wire t316;
+	wire t317;
+	wire t318;
+	wire z0;
+	wire z1;
+	wire z2;
+	wire z3;
+	wire z4;
+	wire z5;
+	wire z6;
+	wire z7;
+	wire z8;
+	wire z9;
+	wire z10;
+	wire z11;
+	wire z12;
+	wire z13;
+	wire z14;
+	wire z15;
+	wire z16;
+	wire z17;
+	wire z18;
+	wire z19;
+	wire z20;
+	wire z21;
+	wire z22;
+	wire z23;
+	wire z24;
+	wire z25;
+	wire z26;
+	wire z27;
+	wire z28;
+	wire z29;
+	wire z30;
+	assign z30 = a[15] & b[15];
+	assign t1 = a[15] & b[12];
+	assign t2 = a[15] & b[13];
+	assign t3 = a[15] & b[14];
+	assign t4 = a[12] & b[15];
+	assign t5 = a[13] & b[15];
+	assign t6 = a[14] & b[15];
+	assign t7 = a[14] & b[14];
+	assign t8 = a[14] & b[12];
+	assign t9 = a[14] & b[13];
+	assign t10 = a[12] & b[14];
+	assign t11 = a[13] & b[14];
+	assign t12 = a[13] & b[13];
+	assign t13 = a[13] & b[12];
+	assign t14 = a[12] & b[13];
+	assign t15 = a[12] & b[12];
+	assign t16 = a[11] & b[11];
+	assign t17 = a[11] & b[8];
+	assign t18 = a[11] & b[9];
+	assign t19 = a[11] & b[10];
+	assign t20 = a[8] & b[11];
+	assign t21 = a[9] & b[11];
+	assign t22 = a[10] & b[11];
+	assign t23 = a[10] & b[10];
+	assign t24 = a[10] & b[8];
+	assign t25 = a[10] & b[9];
+	assign t26 = a[8] & b[10];
+	assign t27 = a[9] & b[10];
+	assign t28 = a[9] & b[9];
+	assign t29 = a[9] & b[8];
+	assign t30 = a[8] & b[9];
+	assign t31 = a[8] & b[8];
+	assign t32 = a[7] & b[7];
+	assign t33 = a[7] & b[4];
+	assign t34 = a[7] & b[5];
+	assign t35 = a[7] & b[6];
+	assign t36 = a[4] & b[7];
+	assign t37 = a[5] & b[7];
+	assign t38 = a[6] & b[7];
+	assign t39 = a[6] & b[6];
+	assign t40 = a[6] & b[4];
+	assign t41 = a[6] & b[5];
+	assign t42 = a[4] & b[6];
+	assign t43 = a[5] & b[6];
+	assign t44 = a[5] & b[5];
+	assign t45 = a[5] & b[4];
+	assign t46 = a[4] & b[5];
+	assign t47 = a[4] & b[4];
+	assign t48 = a[3] & b[3];
+	assign t49 = a[3] & b[0];
+	assign t50 = a[3] & b[1];
+	assign t51 = a[3] & b[2];
+	assign t52 = a[0] & b[3];
+	assign t53 = a[1] & b[3];
+	assign t54 = a[2] & b[3];
+	assign t55 = a[2] & b[2];
+	assign t56 = a[2] & b[0];
+	assign t57 = a[2] & b[1];
+	assign t58 = a[0] & b[2];
+	assign t59 = a[1] & b[2];
+	assign t60 = a[1] & b[1];
+	assign t61 = a[1] & b[0];
+	assign t62 = a[0] & b[1];
+	assign z0 = a[0] & b[0];
+	assign t63 = b[8] ^ b[12];
+	assign t64 = b[9] ^ b[13];
+	assign t65 = b[10] ^ b[14];
+	assign t66 = b[11] ^ b[15];
+	assign t67 = a[8] ^ a[12];
+	assign t68 = a[9] ^ a[13];
+	assign t69 = a[10] ^ a[14];
+	assign t70 = a[11] ^ a[15];
+	assign t71 = t70 & t66;
+	assign t72 = t70 & t63;
+	assign t73 = t70 & t64;
+	assign t74 = t70 & t65;
+	assign t75 = t67 & t66;
+	assign t76 = t68 & t66;
+	assign t77 = t69 & t66;
+	assign t78 = t69 & t65;
+	assign t79 = t69 & t63;
+	assign t80 = t69 & t64;
+	assign t81 = t67 & t65;
+	assign t82 = t68 & t65;
+	assign t83 = t68 & t64;
+	assign t84 = t68 & t63;
+	assign t85 = t67 & t64;
+	assign t86 = t67 & t63;
+	assign t87 = b[0] ^ b[4];
+	assign t88 = b[1] ^ b[5];
+	assign t89 = b[2] ^ b[6];
+	assign t90 = b[3] ^ b[7];
+	assign t91 = a[0] ^ a[4];
+	assign t92 = a[1] ^ a[5];
+	assign t93 = a[2] ^ a[6];
+	assign t94 = a[3] ^ a[7];
+	assign t95 = t94 & t90;
+	assign t96 = t94 & t87;
+	assign t97 = t94 & t88;
+	assign t98 = t94 & t89;
+	assign t99 = t91 & t90;
+	assign t100 = t92 & t90;
+	assign t101 = t93 & t90;
+	assign t102 = t93 & t89;
+	assign t103 = t93 & t87;
+	assign t104 = t93 & t88;
+	assign t105 = t91 & t89;
+	assign t106 = t92 & t89;
+	assign t107 = t92 & t88;
+	assign t108 = t92 & t87;
+	assign t109 = t91 & t88;
+	assign t110 = t91 & t87;
+	assign t111 = b[4] ^ b[12];
+	assign t112 = b[5] ^ b[13];
+	assign t113 = b[6] ^ b[14];
+	assign t114 = b[7] ^ b[15];
+	assign t115 = b[0] ^ b[8];
+	assign t116 = b[1] ^ b[9];
+	assign t117 = b[2] ^ b[10];
+	assign t118 = b[3] ^ b[11];
+	assign t119 = a[4] ^ a[12];
+	assign t120 = a[5] ^ a[13];
+	assign t121 = a[6] ^ a[14];
+	assign t122 = a[7] ^ a[15];
+	assign t123 = a[0] ^ a[8];
+	assign t124 = a[1] ^ a[9];
+	assign t125 = a[2] ^ a[10];
+	assign t126 = a[3] ^ a[11];
+	assign t127 = t126 & t118;
+	assign t128 = t126 & t115;
+	assign t129 = t126 & t116;
+	assign t130 = t126 & t117;
+	assign t131 = t123 & t118;
+	assign t132 = t124 & t118;
+	assign t133 = t125 & t118;
+	assign t134 = t125 & t117;
+	assign t135 = t125 & t115;
+	assign t136 = t125 & t116;
+	assign t137 = t123 & t117;
+	assign t138 = t124 & t117;
+	assign t139 = t124 & t116;
+	assign t140 = t124 & t115;
+	assign t141 = t123 & t116;
+	assign t142 = t123 & t115;
+	assign t143 = t122 & t114;
+	assign t144 = t122 & t111;
+	assign t145 = t122 & t112;
+	assign t146 = t122 & t113;
+	assign t147 = t119 & t114;
+	assign t148 = t120 & t114;
+	assign t149 = t121 & t114;
+	assign t150 = t121 & t113;
+	assign t151 = t121 & t111;
+	assign t152 = t121 & t112;
+	assign t153 = t119 & t113;
+	assign t154 = t120 & t113;
+	assign t155 = t120 & t112;
+	assign t156 = t120 & t111;
+	assign t157 = t119 & t112;
+	assign t158 = t119 & t111;
+	assign t159 = t115 ^ t111;
+	assign t160 = t116 ^ t112;
+	assign t161 = t117 ^ t113;
+	assign t162 = t118 ^ t114;
+	assign t163 = t123 ^ t119;
+	assign t164 = t124 ^ t120;
+	assign t165 = t125 ^ t121;
+	assign t166 = t126 ^ t122;
+	assign t167 = t166 & t162;
+	assign t168 = t166 & t159;
+	assign t169 = t166 & t160;
+	assign t170 = t166 & t161;
+	assign t171 = t163 & t162;
+	assign t172 = t164 & t162;
+	assign t173 = t165 & t162;
+	assign t174 = t165 & t161;
+	assign t175 = t165 & t159;
+	assign t176 = t165 & t160;
+	assign t177 = t163 & t161;
+	assign t178 = t164 & t161;
+	assign t179 = t164 & t160;
+	assign t180 = t164 & t159;
+	assign t181 = t163 & t160;
+	assign t182 = t163 & t159;
+	assign t183 = t73 ^ t76;
+	assign t184 = t97 ^ t100;
+	assign t185 = t15 ^ t18;
+	assign t186 = t129 ^ t132;
+	assign t187 = t134 ^ t158;
+	assign t188 = t145 ^ t148;
+	assign t189 = t169 ^ t172;
+	assign t190 = t2 ^ t5;
+	assign t191 = t21 ^ t23;
+	assign t192 = t31 ^ t34;
+	assign t193 = t37 ^ t39;
+	assign t194 = t47 ^ t50;
+	assign t195 = t53 ^ t55;
+	assign t196 = t183 ^ t78;
+	assign t197 = t192 ^ t193;
+	assign t198 = t194 ^ t195;
+	assign t199 = t184 ^ t102;
+	assign t200 = t185 ^ t191;
+	assign t201 = t186 ^ t187;
+	assign t202 = t188 ^ t150;
+	assign t203 = t189 ^ t174;
+	assign z28 = t190 ^ t7;
+	assign t204 = t198 ^ z0;
+	assign z4 = t110 ^ t204;
+	assign t205 = t200 ^ z28;
+	assign z24 = t196 ^ t205;
+	assign t206 = t197 ^ t199;
+	assign t207 = t197 ^ t86;
+	assign t208 = t202 ^ t205;
+	assign z20 = t207 ^ t208;
+	assign t209 = t142 ^ t204;
+	assign z8 = t206 ^ t209;
+	assign t210 = t196 ^ t198;
+	assign t211 = t201 ^ t206;
+	assign t212 = t208 ^ t210;
+	assign t213 = t211 ^ t212;
+	assign t214 = t200 ^ t201;
+	assign t215 = t110 ^ t182;
+	assign t216 = t209 ^ t214;
+	assign t217 = t215 ^ t207;
+	assign z12 = t217 ^ t216;
+	assign z16 = t213 ^ t203;
+	assign t218 = t74 ^ t77;
+	assign t219 = t84 ^ t85;
+	assign t220 = t13 ^ t14;
+	assign t221 = t98 ^ t101;
+	assign t222 = t108 ^ t109;
+	assign t223 = t130 ^ t133;
+	assign t224 = t140 ^ t141;
+	assign t225 = t146 ^ t149;
+	assign t226 = t156 ^ t157;
+	assign t227 = t170 ^ t173;
+	assign t228 = t19 ^ t22;
+	assign t229 = t180 ^ t181;
+	assign t230 = t29 ^ t30;
+	assign z29 = t3 ^ t6;
+	assign t231 = t35 ^ t38;
+	assign t232 = t45 ^ t46;
+	assign t233 = t51 ^ t54;
+	assign z1 = t61 ^ t62;
+	assign t234 = t228 ^ t220;
+	assign t235 = t230 ^ t231;
+	assign t236 = t232 ^ t233;
+	assign t237 = t223 ^ t226;
+	assign t238 = z29 ^ t234;
+	assign z25 = t218 ^ t238;
+	assign t239 = z1 ^ t236;
+	assign z5 = t222 ^ t239;
+	assign t240 = t219 ^ t235;
+	assign t241 = t235 ^ t221;
+	assign t242 = t224 ^ t239;
+	assign z9 = t241 ^ t242;
+	assign t243 = t225 ^ t238;
+	assign z21 = t240 ^ t243;
+	assign t244 = t218 ^ t236;
+	assign t245 = t237 ^ t241;
+	assign t246 = t243 ^ t244;
+	assign t247 = t245 ^ t227;
+	assign t248 = t234 ^ t237;
+	assign t249 = t222 ^ t240;
+	assign t250 = t242 ^ t248;
+	assign t251 = t249 ^ t229;
+	assign z17 = t247 ^ t246;
+	assign z13 = t251 ^ t250;
+	assign t252 = t10 ^ t12;
+	assign t253 = t79 ^ t81;
+	assign t254 = t103 ^ t105;
+	assign t255 = t127 ^ t151;
+	assign t256 = t135 ^ t137;
+	assign t257 = t153 ^ t155;
+	assign t258 = t16 ^ t8;
+	assign t259 = t175 ^ t177;
+	assign t260 = t24 ^ t26;
+	assign t261 = t28 ^ t32;
+	assign t262 = t40 ^ t42;
+	assign t263 = t44 ^ t48;
+	assign t264 = t56 ^ t58;
+	assign t265 = t252 ^ t258;
+	assign t266 = t261 ^ t260;
+	assign t267 = t262 ^ t263;
+	assign z2 = t264 ^ t60;
+	assign t268 = t253 ^ t83;
+	assign t269 = t254 ^ t107;
+	assign t270 = t255 ^ t257;
+	assign t271 = t256 ^ t139;
+	assign t272 = t259 ^ t179;
+	assign t273 = t265 ^ z30;
+	assign z26 = t71 ^ t273;
+	assign t274 = t267 ^ z2;
+	assign z6 = t269 ^ t274;
+	assign t275 = t266 ^ t268;
+	assign t276 = t266 ^ t95;
+	assign t277 = t271 ^ t274;
+	assign z10 = t276 ^ t277;
+	assign t278 = t143 ^ t273;
+	assign z22 = t275 ^ t278;
+	assign t279 = t265 ^ t269;
+	assign t280 = t270 ^ t275;
+	assign t281 = t277 ^ t279;
+	assign t282 = t280 ^ t281;
+	assign t283 = t267 ^ t270;
+	assign t284 = t71 ^ t167;
+	assign t285 = t278 ^ t283;
+	assign t286 = t284 ^ t276;
+	assign z14 = t282 ^ t272;
+	assign z18 = t286 ^ t285;
+	assign t287 = t9 ^ t11;
+	assign t288 = t72 ^ t75;
+	assign t289 = t80 ^ t82;
+	assign t290 = t96 ^ t99;
+	assign t291 = t104 ^ t106;
+	assign t292 = t1 ^ t4;
+	assign t293 = t128 ^ t131;
+	assign t294 = t136 ^ t138;
+	assign t295 = t144 ^ t147;
+	assign t296 = t152 ^ t154;
+	assign t297 = t17 ^ t20;
+	assign t298 = t168 ^ t171;
+	assign t299 = t176 ^ t178;
+	assign t300 = t25 ^ t27;
+	assign t301 = t33 ^ t36;
+	assign t302 = t41 ^ t43;
+	assign t303 = t49 ^ t52;
+	assign t304 = t57 ^ t59;
+	assign z27 = t287 ^ t292;
+	assign t305 = t296 ^ t295;
+	assign t306 = t297 ^ t300;
+	assign t307 = t298 ^ t299;
+	assign t308 = t301 ^ t302;
+	assign z3 = t303 ^ t304;
+	assign t309 = t288 ^ t289;
+	assign t310 = t290 ^ t291;
+	assign t311 = t293 ^ t294;
+	assign t312 = z27 ^ t306;
+	assign z23 = t309 ^ t312;
+	assign t313 = t308 ^ z3;
+	assign z7 = t310 ^ t313;
+	assign t314 = t305 ^ t308;
+	assign z19 = t312 ^ t314;
+	assign t315 = t306 ^ t311;
+	assign z11 = t313 ^ t315;
+	assign t316 = t305 ^ t311;
+	assign t317 = z23 ^ z7;
+	assign t318 = t316 ^ t307;
+	assign z15 = t318 ^ t317;
+	assign r = {1'b0, z30, z29, z28, z27, z26, z25, z24, z23, z22, z21, z20, z19, z18, z17, z16, z15, z14, z13, z12, z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z0};
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_prefetch_buffer.v b/verilog/rtl/ibex_core/ibex_prefetch_buffer.v
new file mode 100644
index 0000000..e734516
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_prefetch_buffer.v
@@ -0,0 +1,192 @@
+module ibex_prefetch_buffer (
+	clk_i,
+	rst_ni,
+	req_i,
+	branch_i,
+	branch_spec_i,
+	branch_mispredict_i,
+	mispredict_addr_i,
+	addr_i,
+	ready_i,
+	valid_o,
+	rdata_o,
+	addr_o,
+	err_o,
+	err_plus2_o,
+	instr_req_o,
+	instr_gnt_i,
+	instr_addr_o,
+	instr_rdata_i,
+	instr_err_i,
+	instr_pmp_err_i,
+	instr_rvalid_i,
+	busy_o
+);
+	parameter [0:0] ResetAll = 1'b0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire req_i;
+	input wire branch_i;
+	input wire branch_spec_i;
+	input wire branch_mispredict_i;
+	input wire [31:0] mispredict_addr_i;
+	input wire [31:0] addr_i;
+	input wire ready_i;
+	output wire valid_o;
+	output wire [31:0] rdata_o;
+	output wire [31:0] addr_o;
+	output wire err_o;
+	output wire err_plus2_o;
+	output wire instr_req_o;
+	input wire instr_gnt_i;
+	output wire [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	input wire instr_err_i;
+	input wire instr_pmp_err_i;
+	input wire instr_rvalid_i;
+	output wire busy_o;
+	localparam [31:0] NUM_REQS = 2;
+	wire branch_suppress;
+	wire valid_new_req;
+	wire valid_req;
+	wire valid_req_d;
+	reg valid_req_q;
+	wire discard_req_d;
+	reg discard_req_q;
+	wire gnt_or_pmp_err;
+	wire rvalid_or_pmp_err;
+	wire [1:0] rdata_outstanding_n;
+	wire [1:0] rdata_outstanding_s;
+	reg [1:0] rdata_outstanding_q;
+	wire [1:0] branch_discard_n;
+	wire [1:0] branch_discard_s;
+	reg [1:0] branch_discard_q;
+	wire [1:0] rdata_pmp_err_n;
+	wire [1:0] rdata_pmp_err_s;
+	reg [1:0] rdata_pmp_err_q;
+	wire [1:0] rdata_outstanding_rev;
+	wire [31:0] stored_addr_d;
+	reg [31:0] stored_addr_q;
+	wire stored_addr_en;
+	wire [31:0] fetch_addr_d;
+	reg [31:0] fetch_addr_q;
+	wire fetch_addr_en;
+	wire [31:0] instr_addr;
+	wire [31:0] instr_addr_w_aligned;
+	wire instr_or_pmp_err;
+	wire fifo_valid;
+	wire [31:0] fifo_addr;
+	wire fifo_ready;
+	wire fifo_clear;
+	wire [1:0] fifo_busy;
+	wire valid_raw;
+	wire branch_or_mispredict;
+	assign busy_o = |rdata_outstanding_q | instr_req_o;
+	assign branch_or_mispredict = branch_i | branch_mispredict_i;
+	assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0];
+	assign fifo_clear = branch_or_mispredict;
+	genvar i;
+	generate
+		for (i = 0; i < NUM_REQS; i = i + 1) begin : gen_rd_rev
+			assign rdata_outstanding_rev[i] = rdata_outstanding_q[1 - i];
+		end
+	endgenerate
+	assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev);
+	ibex_fetch_fifo #(
+		.NUM_REQS(NUM_REQS),
+		.ResetAll(ResetAll)
+	) fifo_i(
+		.clk_i(clk_i),
+		.rst_ni(rst_ni),
+		.clear_i(fifo_clear),
+		.busy_o(fifo_busy),
+		.in_valid_i(fifo_valid),
+		.in_addr_i(fifo_addr),
+		.in_rdata_i(instr_rdata_i),
+		.in_err_i(instr_or_pmp_err),
+		.out_valid_o(valid_raw),
+		.out_ready_i(ready_i),
+		.out_rdata_o(rdata_o),
+		.out_addr_o(addr_o),
+		.out_err_o(err_o),
+		.out_err_plus2_o(err_plus2_o)
+	);
+	assign branch_suppress = branch_spec_i & ~branch_i;
+	assign valid_new_req = ((~branch_suppress & req_i) & (fifo_ready | branch_or_mispredict)) & ~rdata_outstanding_q[1];
+	assign valid_req = valid_req_q | valid_new_req;
+	assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i;
+	assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]);
+	assign valid_req_d = valid_req & ~gnt_or_pmp_err;
+	assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q);
+	assign stored_addr_en = (valid_new_req & ~valid_req_q) & ~gnt_or_pmp_err;
+	assign stored_addr_d = instr_addr;
+	generate
+		if (ResetAll) begin : g_stored_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					stored_addr_q <= 1'sb0;
+				else if (stored_addr_en)
+					stored_addr_q <= stored_addr_d;
+		end
+		else begin : g_stored_addr_nr
+			always @(posedge clk_i)
+				if (stored_addr_en)
+					stored_addr_q <= stored_addr_d;
+		end
+	endgenerate
+	assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q);
+	assign fetch_addr_d = (branch_i ? addr_i : (branch_mispredict_i ? {mispredict_addr_i[31:2], 2'b00} : {fetch_addr_q[31:2], 2'b00})) + {{29 {1'b0}}, valid_new_req & ~valid_req_q, 2'b00};
+	generate
+		if (ResetAll) begin : g_fetch_addr_ra
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					fetch_addr_q <= 1'sb0;
+				else if (fetch_addr_en)
+					fetch_addr_q <= fetch_addr_d;
+		end
+		else begin : g_fetch_addr_nr
+			always @(posedge clk_i)
+				if (fetch_addr_en)
+					fetch_addr_q <= fetch_addr_d;
+		end
+	endgenerate
+	assign instr_addr = (valid_req_q ? stored_addr_q : (branch_spec_i ? addr_i : (branch_mispredict_i ? mispredict_addr_i : fetch_addr_q)));
+	assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
+	generate
+		for (i = 0; i < NUM_REQS; i = i + 1) begin : g_outstanding_reqs
+			if (i == 0) begin : g_req0
+				assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | rdata_outstanding_q[i];
+				assign branch_discard_n[i] = (((valid_req & gnt_or_pmp_err) & discard_req_d) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i];
+				assign rdata_pmp_err_n[i] = ((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) | rdata_pmp_err_q[i];
+			end
+			else begin : g_reqtop
+				assign rdata_outstanding_n[i] = ((valid_req & gnt_or_pmp_err) & rdata_outstanding_q[i - 1]) | rdata_outstanding_q[i];
+				assign branch_discard_n[i] = ((((valid_req & gnt_or_pmp_err) & discard_req_d) & rdata_outstanding_q[i - 1]) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i];
+				assign rdata_pmp_err_n[i] = (((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) & rdata_outstanding_q[i - 1]) | rdata_pmp_err_q[i];
+			end
+		end
+	endgenerate
+	assign rdata_outstanding_s = (rvalid_or_pmp_err ? {1'b0, rdata_outstanding_n[1:1]} : rdata_outstanding_n);
+	assign branch_discard_s = (rvalid_or_pmp_err ? {1'b0, branch_discard_n[1:1]} : branch_discard_n);
+	assign rdata_pmp_err_s = (rvalid_or_pmp_err ? {1'b0, rdata_pmp_err_n[1:1]} : rdata_pmp_err_n);
+	assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0];
+	assign fifo_addr = (branch_i ? addr_i : mispredict_addr_i);
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			valid_req_q <= 1'b0;
+			discard_req_q <= 1'b0;
+			rdata_outstanding_q <= 'b0;
+			branch_discard_q <= 'b0;
+			rdata_pmp_err_q <= 'b0;
+		end
+		else begin
+			valid_req_q <= valid_req_d;
+			discard_req_q <= discard_req_d;
+			rdata_outstanding_q <= rdata_outstanding_s;
+			branch_discard_q <= branch_discard_s;
+			rdata_pmp_err_q <= rdata_pmp_err_s;
+		end
+	assign instr_req_o = valid_req;
+	assign instr_addr_o = instr_addr_w_aligned;
+	assign valid_o = valid_raw & ~branch_mispredict_i;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_register_file_ff.v b/verilog/rtl/ibex_core/ibex_register_file_ff.v
new file mode 100644
index 0000000..b11bc48
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_register_file_ff.v
@@ -0,0 +1,75 @@
+module ibex_register_file_ff (
+	clk_i,
+	rst_ni,
+	test_en_i,
+	dummy_instr_id_i,
+	raddr_a_i,
+	rdata_a_o,
+	raddr_b_i,
+	rdata_b_o,
+	waddr_a_i,
+	wdata_a_i,
+	we_a_i
+);
+	parameter [0:0] RV32E = 0;
+	parameter [31:0] DataWidth = 32;
+	parameter [0:0] DummyInstructions = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire test_en_i;
+	input wire dummy_instr_id_i;
+	input wire [4:0] raddr_a_i;
+	output wire [DataWidth - 1:0] rdata_a_o;
+	input wire [4:0] raddr_b_i;
+	output wire [DataWidth - 1:0] rdata_b_o;
+	input wire [4:0] waddr_a_i;
+	input wire [DataWidth - 1:0] wdata_a_i;
+	input wire we_a_i;
+	localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
+	localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH;
+	wire [(NUM_WORDS * DataWidth) - 1:0] rf_reg;
+	reg [((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) * DataWidth) + (DataWidth - 1) : ((3 - NUM_WORDS) * DataWidth) + (((NUM_WORDS - 1) * DataWidth) - 1)):((NUM_WORDS - 1) >= 1 ? DataWidth : (NUM_WORDS - 1) * DataWidth)] rf_reg_q;
+	reg [NUM_WORDS - 1:1] we_a_dec;
+	function automatic [4:0] sv2v_cast_5;
+		input reg [4:0] inp;
+		sv2v_cast_5 = inp;
+	endfunction
+	always @(*) begin : we_a_decoder
+		begin : sv2v_autoblock_1
+			reg [31:0] i;
+			for (i = 1; i < NUM_WORDS; i = i + 1)
+				we_a_dec[i] = (waddr_a_i == sv2v_cast_5(i) ? we_a_i : 1'b0);
+		end
+	end
+	genvar i;
+	generate
+		for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_flops
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= 1'sb0;
+				else if (we_a_dec[i])
+					rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= wdata_a_i;
+		end
+		if (DummyInstructions) begin : g_dummy_r0
+			wire we_r0_dummy;
+			reg [DataWidth - 1:0] rf_r0_q;
+			assign we_r0_dummy = we_a_i & dummy_instr_id_i;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					rf_r0_q <= 1'sb0;
+				else if (we_r0_dummy)
+					rf_r0_q <= wdata_a_i;
+			assign rf_reg[0+:DataWidth] = (dummy_instr_id_i ? rf_r0_q : {DataWidth {1'sb0}});
+		end
+		else begin : g_normal_r0
+			wire unused_dummy_instr_id;
+			assign unused_dummy_instr_id = dummy_instr_id_i;
+			assign rf_reg[0+:DataWidth] = 1'sb0;
+		end
+	endgenerate
+	assign rf_reg[DataWidth * (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)] = rf_reg_q[DataWidth * ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) : 1 - (((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) - (NUM_WORDS - 1)))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)];
+	assign rdata_a_o = rf_reg[raddr_a_i * DataWidth+:DataWidth];
+	assign rdata_b_o = rf_reg[raddr_b_i * DataWidth+:DataWidth];
+	wire unused_test_en;
+	assign unused_test_en = test_en_i;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_register_file_fpga.v b/verilog/rtl/ibex_core/ibex_register_file_fpga.v
new file mode 100644
index 0000000..a249fcf
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_register_file_fpga.v
@@ -0,0 +1,45 @@
+module ibex_register_file_fpga (
+	clk_i,
+	rst_ni,
+	test_en_i,
+	dummy_instr_id_i,
+	raddr_a_i,
+	rdata_a_o,
+	raddr_b_i,
+	rdata_b_o,
+	waddr_a_i,
+	wdata_a_i,
+	we_a_i
+);
+	parameter [0:0] RV32E = 0;
+	parameter [31:0] DataWidth = 32;
+	parameter [0:0] DummyInstructions = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire test_en_i;
+	input wire dummy_instr_id_i;
+	input wire [4:0] raddr_a_i;
+	output wire [DataWidth - 1:0] rdata_a_o;
+	input wire [4:0] raddr_b_i;
+	output wire [DataWidth - 1:0] rdata_b_o;
+	input wire [4:0] waddr_a_i;
+	input wire [DataWidth - 1:0] wdata_a_i;
+	input wire we_a_i;
+	localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
+	localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH;
+	reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1];
+	wire we;
+	assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]);
+	assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]);
+	assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i);
+	always @(posedge clk_i) begin : sync_write
+		if (we == 1'b1)
+			mem[waddr_a_i] <= wdata_a_i;
+	end
+	wire unused_rst_ni;
+	assign unused_rst_ni = rst_ni;
+	wire unused_dummy_instr;
+	assign unused_dummy_instr = dummy_instr_id_i;
+	wire unused_test_en;
+	assign unused_test_en = test_en_i;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_register_file_latch.v b/verilog/rtl/ibex_core/ibex_register_file_latch.v
new file mode 100644
index 0000000..4bbdacd
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_register_file_latch.v
@@ -0,0 +1,116 @@
+module ibex_register_file_latch (
+	clk_i,
+	rst_ni,
+	test_en_i,
+	dummy_instr_id_i,
+	raddr_a_i,
+	rdata_a_o,
+	raddr_b_i,
+	rdata_b_o,
+	waddr_a_i,
+	wdata_a_i,
+	we_a_i
+);
+	parameter [0:0] RV32E = 0;
+	parameter [31:0] DataWidth = 32;
+	parameter [0:0] DummyInstructions = 0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire test_en_i;
+	input wire dummy_instr_id_i;
+	input wire [4:0] raddr_a_i;
+	output wire [DataWidth - 1:0] rdata_a_o;
+	input wire [4:0] raddr_b_i;
+	output wire [DataWidth - 1:0] rdata_b_o;
+	input wire [4:0] waddr_a_i;
+	input wire [DataWidth - 1:0] wdata_a_i;
+	input wire we_a_i;
+	localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
+	localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH;
+	reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1];
+	reg [NUM_WORDS - 1:1] waddr_onehot_a;
+	wire [NUM_WORDS - 1:1] mem_clocks;
+	reg [DataWidth - 1:0] wdata_a_q;
+	wire [ADDR_WIDTH - 1:0] raddr_a_int;
+	wire [ADDR_WIDTH - 1:0] raddr_b_int;
+	wire [ADDR_WIDTH - 1:0] waddr_a_int;
+	assign raddr_a_int = raddr_a_i[ADDR_WIDTH - 1:0];
+	assign raddr_b_int = raddr_b_i[ADDR_WIDTH - 1:0];
+	assign waddr_a_int = waddr_a_i[ADDR_WIDTH - 1:0];
+	wire clk_int;
+	assign rdata_a_o = mem[raddr_a_int];
+	assign rdata_b_o = mem[raddr_b_int];
+	prim_clock_gating cg_we_global(
+		.clk_i(clk_i),
+		.en_i(we_a_i),
+		.test_en_i(test_en_i),
+		.clk_o(clk_int)
+	);
+	always @(posedge clk_int or negedge rst_ni) begin : sample_wdata
+		if (!rst_ni)
+			wdata_a_q <= 1'sb0;
+		else if (we_a_i)
+			wdata_a_q <= wdata_a_i;
+	end
+	function automatic signed [4:0] sv2v_cast_5_signed;
+		input reg signed [4:0] inp;
+		sv2v_cast_5_signed = inp;
+	endfunction
+	always @(*) begin : wad
+		begin : sv2v_autoblock_1
+			reg signed [31:0] i;
+			for (i = 1; i < NUM_WORDS; i = i + 1)
+				begin : wad_word_iter
+					if (we_a_i && (waddr_a_int == sv2v_cast_5_signed(i)))
+						waddr_onehot_a[i] = 1'b1;
+					else
+						waddr_onehot_a[i] = 1'b0;
+				end
+		end
+	end
+	genvar x;
+	generate
+		for (x = 1; x < NUM_WORDS; x = x + 1) begin : gen_cg_word_iter
+			prim_clock_gating cg_i(
+				.clk_i(clk_int),
+				.en_i(waddr_onehot_a[x]),
+				.test_en_i(test_en_i),
+				.clk_o(mem_clocks[x])
+			);
+		end
+	endgenerate
+	genvar i;
+	generate
+		for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_latches
+			always @(*)
+				if (mem_clocks[i])
+					mem[i] = wdata_a_q;
+		end
+		if (DummyInstructions) begin : g_dummy_r0
+			wire we_r0_dummy;
+			wire r0_clock;
+			reg [DataWidth - 1:0] mem_r0;
+			assign we_r0_dummy = we_a_i & dummy_instr_id_i;
+			prim_clock_gating cg_i(
+				.clk_i(clk_int),
+				.en_i(we_r0_dummy),
+				.test_en_i(test_en_i),
+				.clk_o(r0_clock)
+			);
+			always @(*) begin : latch_wdata
+				if (r0_clock)
+					mem_r0 = wdata_a_q;
+			end
+			wire [DataWidth:1] sv2v_tmp_35384;
+			assign sv2v_tmp_35384 = (dummy_instr_id_i ? mem_r0 : {DataWidth {1'sb0}});
+			always @(*) mem[0] = sv2v_tmp_35384;
+		end
+		else begin : g_normal_r0
+			wire unused_dummy_instr_id;
+			assign unused_dummy_instr_id = dummy_instr_id_i;
+			wire [DataWidth:1] sv2v_tmp_450E3;
+			assign sv2v_tmp_450E3 = 1'sb0;
+			always @(*) mem[0] = sv2v_tmp_450E3;
+		end
+	endgenerate
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_sm4_sbox.v b/verilog/rtl/ibex_core/ibex_sm4_sbox.v
new file mode 100644
index 0000000..9abf01d
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_sm4_sbox.v
@@ -0,0 +1,266 @@
+module ibex_sm4_sbox (
+	in,
+	fx
+);
+	input wire [7:0] in;
+	output wire [7:0] fx;
+	function automatic [20:0] sm4_sbox_top;
+		input reg [7:0] x;
+		reg y20;
+		reg y19;
+		reg y18;
+		reg y17;
+		reg y16;
+		reg y15;
+		reg y14;
+		reg y13;
+		reg y12;
+		reg y11;
+		reg y10;
+		reg y9;
+		reg y8;
+		reg y7;
+		reg y6;
+		reg y5;
+		reg y4;
+		reg y3;
+		reg y2;
+		reg y1;
+		reg y0;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			y18 = x[2] ^ x[6];
+			t0 = x[3] ^ x[4];
+			t1 = x[2] ^ x[7];
+			t2 = x[7] ^ y18;
+			t3 = x[1] ^ t1;
+			t4 = x[6] ^ x[7];
+			t5 = x[0] ^ y18;
+			t6 = x[3] ^ x[6];
+			y10 = x[1] ^ y18;
+			y0 = x[5] ~^ y10;
+			y1 = t0 ^ t3;
+			y2 = x[0] ^ t0;
+			y4 = x[0] ^ t3;
+			y3 = x[3] ^ y4;
+			y5 = x[5] ^ t5;
+			y6 = x[0] ~^ x[1];
+			y7 = t0 ~^ y10;
+			y8 = t0 ^ t5;
+			y9 = x[3];
+			y11 = t0 ^ t4;
+			y12 = x[5] ^ t4;
+			y13 = x[5] ~^ y1;
+			y14 = x[4] ~^ t2;
+			y15 = x[1] ~^ t6;
+			y16 = x[0] ~^ t2;
+			y17 = t0 ~^ t2;
+			y19 = x[5] ~^ y14;
+			y20 = x[0] ^ t1;
+			sm4_sbox_top = {y20, y19, y18, y17, y16, y15, y14, y13, y12, y11, y10, y9, y8, y7, y6, y5, y4, y3, y2, y1, y0};
+		end
+	endfunction
+	function automatic [7:0] sm4_sbox_out;
+		input reg [17:0] x;
+		reg [7:0] y;
+		reg t29;
+		reg t28;
+		reg t27;
+		reg t26;
+		reg t25;
+		reg t24;
+		reg t23;
+		reg t22;
+		reg t21;
+		reg t20;
+		reg t19;
+		reg t18;
+		reg t17;
+		reg t16;
+		reg t15;
+		reg t14;
+		reg t13;
+		reg t12;
+		reg t11;
+		reg t10;
+		reg t9;
+		reg t8;
+		reg t7;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			t0 = x[4] ^ x[7];
+			t1 = x[13] ^ x[15];
+			t2 = x[2] ^ x[16];
+			t3 = x[6] ^ t0;
+			t4 = x[12] ^ t1;
+			t5 = x[9] ^ x[10];
+			t6 = x[11] ^ t2;
+			t7 = x[1] ^ t4;
+			t8 = x[0] ^ x[17];
+			t9 = x[3] ^ x[17];
+			t10 = x[8] ^ t3;
+			t11 = t2 ^ t5;
+			t12 = x[14] ^ t6;
+			t13 = t7 ^ t9;
+			t14 = x[0] ^ x[6];
+			t15 = x[7] ^ x[16];
+			t16 = x[5] ^ x[13];
+			t17 = x[3] ^ x[15];
+			t18 = x[10] ^ x[12];
+			t19 = x[9] ^ t1;
+			t20 = x[4] ^ t4;
+			t21 = x[14] ^ t3;
+			t22 = x[16] ^ t5;
+			t23 = t7 ^ t14;
+			t24 = t8 ^ t11;
+			t25 = t0 ^ t12;
+			t26 = t17 ^ t3;
+			t27 = t18 ^ t10;
+			t28 = t19 ^ t6;
+			t29 = t8 ^ t10;
+			y[0] = t11 ~^ t13;
+			y[1] = t15 ~^ t23;
+			y[2] = t20 ^ t24;
+			y[3] = t16 ^ t25;
+			y[4] = t26 ~^ t22;
+			y[5] = t21 ^ t13;
+			y[6] = t27 ~^ t12;
+			y[7] = t28 ~^ t29;
+			sm4_sbox_out = y;
+		end
+	endfunction
+	function automatic [17:0] sm4_sbox_inv_mid;
+		input reg [20:0] x;
+		reg [17:0] y;
+		reg t45;
+		reg t44;
+		reg t43;
+		reg t42;
+		reg t41;
+		reg t40;
+		reg t39;
+		reg t38;
+		reg t37;
+		reg t36;
+		reg t35;
+		reg t34;
+		reg t33;
+		reg t32;
+		reg t31;
+		reg t30;
+		reg t29;
+		reg t28;
+		reg t27;
+		reg t26;
+		reg t25;
+		reg t24;
+		reg t23;
+		reg t22;
+		reg t21;
+		reg t20;
+		reg t19;
+		reg t18;
+		reg t17;
+		reg t16;
+		reg t15;
+		reg t14;
+		reg t13;
+		reg t12;
+		reg t11;
+		reg t10;
+		reg t9;
+		reg t8;
+		reg t7;
+		reg t6;
+		reg t5;
+		reg t4;
+		reg t3;
+		reg t2;
+		reg t1;
+		reg t0;
+		begin
+			t0 = x[3] ^ x[12];
+			t1 = x[9] & x[5];
+			t2 = x[17] & x[6];
+			t3 = x[10] ^ t1;
+			t4 = x[14] & x[0];
+			t5 = t4 ^ t1;
+			t6 = x[3] & x[12];
+			t7 = x[16] & x[7];
+			t8 = t0 ^ t6;
+			t9 = x[15] & x[13];
+			t10 = t9 ^ t6;
+			t11 = x[1] & x[11];
+			t12 = x[4] & x[20];
+			t13 = t12 ^ t11;
+			t14 = x[2] & x[8];
+			t15 = t14 ^ t11;
+			t16 = t3 ^ t2;
+			t17 = t5 ^ x[18];
+			t18 = t8 ^ t7;
+			t19 = t10 ^ t15;
+			t20 = t16 ^ t13;
+			t21 = t17 ^ t15;
+			t22 = t18 ^ t13;
+			t23 = t19 ^ x[19];
+			t24 = t22 ^ t23;
+			t25 = t22 & t20;
+			t26 = t21 ^ t25;
+			t27 = t20 ^ t21;
+			t28 = t23 ^ t25;
+			t29 = t28 & t27;
+			t30 = t26 & t24;
+			t31 = t20 & t23;
+			t32 = t27 & t31;
+			t33 = t27 ^ t25;
+			t34 = t21 & t22;
+			t35 = t24 & t34;
+			t36 = t24 ^ t25;
+			t37 = t21 ^ t29;
+			t38 = t32 ^ t33;
+			t39 = t23 ^ t30;
+			t40 = t35 ^ t36;
+			t41 = t38 ^ t40;
+			t42 = t37 ^ t39;
+			t43 = t37 ^ t38;
+			t44 = t39 ^ t40;
+			t45 = t42 ^ t41;
+			y[0] = t38 & x[7];
+			y[1] = t37 & x[13];
+			y[2] = t42 & x[11];
+			y[3] = t45 & x[20];
+			y[4] = t41 & x[8];
+			y[5] = t44 & x[9];
+			y[6] = t40 & x[17];
+			y[7] = t39 & x[14];
+			y[8] = t43 & x[3];
+			y[9] = t38 & x[16];
+			y[10] = t37 & x[15];
+			y[11] = t42 & x[1];
+			y[12] = t45 & x[4];
+			y[13] = t41 & x[2];
+			y[14] = t44 & x[5];
+			y[15] = t40 & x[6];
+			y[16] = t39 & x[0];
+			y[17] = t43 & x[12];
+			sm4_sbox_inv_mid = y;
+		end
+	endfunction
+	wire [20:0] t1;
+	wire [17:0] t2;
+	assign t1 = sm4_sbox_top(in);
+	assign t2 = sm4_sbox_inv_mid(t1);
+	assign fx = sm4_sbox_out(t2);
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_top.v b/verilog/rtl/ibex_core/ibex_top.v
new file mode 100644
index 0000000..4aeb609
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_top.v
@@ -0,0 +1,352 @@
+module ibex_top (
+	clk_i,
+	rst_ni,
+	test_en_i,
+	ram_cfg_i,
+	hart_id_i,
+	boot_addr_i,
+	instr_req_o,
+	instr_gnt_i,
+	instr_rvalid_i,
+	instr_addr_o,
+	instr_rdata_i,
+	instr_rdata_intg_i,
+	instr_err_i,
+	data_req_o,
+	data_gnt_i,
+	data_rvalid_i,
+	data_we_o,
+	data_be_o,
+	data_addr_o,
+	data_wdata_o,
+	data_wdata_intg_o,
+	data_rdata_i,
+	data_rdata_intg_i,
+	data_err_i,
+	eFPGA_operand_a_o,
+	eFPGA_operand_b_o,
+	eFPGA_result_a_i,
+	eFPGA_result_b_i,
+	eFPGA_result_c_i,
+	eFPGA_write_strobe_o,
+	eFPGA_fpga_done_i,
+	eFPGA_en_o,
+	eFPGA_operator_o,
+	eFPGA_delay_o,
+	irq_software_i,
+	irq_timer_i,
+	irq_external_i,
+	irq_fast_i,
+	irq_nm_i,
+	debug_req_i,
+	crash_dump_o,
+	fetch_enable_i,
+	alert_minor_o,
+	alert_major_o,
+	core_sleep_o,
+	scan_rst_ni
+);
+	parameter [0:0] PMPEnable = 1'b0;
+	parameter [31:0] PMPGranularity = 0;
+	parameter [31:0] PMPNumRegions = 4;
+	parameter [31:0] MHPMCounterNum = 0;
+	parameter [31:0] MHPMCounterWidth = 40;
+	parameter [0:0] RV32E = 1'b0;
+	parameter integer RV32M = 32'sd2;
+	parameter integer RV32B = 32'sd0;
+	parameter integer RV32Zk = 32'sd2;
+	parameter integer RegFile = 32'sd0;
+	parameter [0:0] BranchTargetALU = 1'b0;
+	parameter [0:0] WritebackStage = 1'b0;
+	parameter [0:0] ICache = 1'b0;
+	parameter [0:0] ICacheECC = 1'b0;
+	parameter [0:0] BranchPredictor = 1'b0;
+	parameter [0:0] DbgTriggerEn = 1'b0;
+	parameter [31:0] DbgHwBreakNum = 1;
+	parameter [0:0] SecureIbex = 1'b0;
+	localparam signed [31:0] ibex_pkg_LfsrWidth = 32;
+	localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4;
+	parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault;
+	localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed;
+	parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault;
+	parameter [31:0] DmHaltAddr = 32'h1a110800;
+	parameter [31:0] DmExceptionAddr = 32'h1a110808;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire test_en_i;
+	input wire ram_cfg_i;
+	input wire [31:0] hart_id_i;
+	input wire [31:0] boot_addr_i;
+	output wire instr_req_o;
+	input wire instr_gnt_i;
+	input wire instr_rvalid_i;
+	output wire [31:0] instr_addr_o;
+	input wire [31:0] instr_rdata_i;
+	input wire [6:0] instr_rdata_intg_i;
+	input wire instr_err_i;
+	output wire data_req_o;
+	input wire data_gnt_i;
+	input wire data_rvalid_i;
+	output wire data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_addr_o;
+	output wire [31:0] data_wdata_o;
+	output wire [6:0] data_wdata_intg_o;
+	input wire [31:0] data_rdata_i;
+	input wire [6:0] data_rdata_intg_i;
+	input wire data_err_i;
+	output wire [31:0] eFPGA_operand_a_o;
+	output wire [31:0] eFPGA_operand_b_o;
+	input wire [31:0] eFPGA_result_a_i;
+	input wire [31:0] eFPGA_result_b_i;
+	input wire [31:0] eFPGA_result_c_i;
+	output wire eFPGA_write_strobe_o;
+	input wire eFPGA_fpga_done_i;
+	output wire eFPGA_en_o;
+	output wire [1:0] eFPGA_operator_o;
+	output wire [3:0] eFPGA_delay_o;
+	input wire irq_software_i;
+	input wire irq_timer_i;
+	input wire irq_external_i;
+	input wire [14:0] irq_fast_i;
+	input wire irq_nm_i;
+	input wire debug_req_i;
+	output wire [127:0] crash_dump_o;
+	input wire fetch_enable_i;
+	output wire alert_minor_o;
+	output wire alert_major_o;
+	output wire core_sleep_o;
+	input wire scan_rst_ni;
+	localparam [0:0] Lockstep = SecureIbex;
+	localparam [0:0] ResetAll = Lockstep;
+	localparam [0:0] DummyInstructions = SecureIbex;
+	localparam [0:0] RegFileECC = SecureIbex;
+	localparam [31:0] RegFileDataWidth = (RegFileECC ? 39 : 32);
+	localparam [31:0] ibex_pkg_BUS_SIZE = 32;
+	localparam [31:0] BusSizeECC = (ICacheECC ? 39 : ibex_pkg_BUS_SIZE);
+	localparam [31:0] ibex_pkg_BUS_BYTES = 4;
+	localparam [31:0] ibex_pkg_IC_LINE_SIZE = 64;
+	localparam [31:0] ibex_pkg_IC_LINE_BYTES = 8;
+	localparam [31:0] ibex_pkg_IC_LINE_BEATS = ibex_pkg_IC_LINE_BYTES / ibex_pkg_BUS_BYTES;
+	localparam [31:0] LineSizeECC = BusSizeECC * ibex_pkg_IC_LINE_BEATS;
+	localparam [31:0] ibex_pkg_ADDR_W = 32;
+	localparam [31:0] ibex_pkg_IC_NUM_WAYS = 2;
+	localparam [31:0] ibex_pkg_IC_SIZE_BYTES = 4096;
+	localparam [31:0] ibex_pkg_IC_NUM_LINES = (ibex_pkg_IC_SIZE_BYTES / ibex_pkg_IC_NUM_WAYS) / ibex_pkg_IC_LINE_BYTES;
+	localparam [31:0] ibex_pkg_IC_INDEX_W = $clog2(ibex_pkg_IC_NUM_LINES);
+	localparam [31:0] ibex_pkg_IC_LINE_W = 3;
+	localparam [31:0] ibex_pkg_IC_TAG_SIZE = ((ibex_pkg_ADDR_W - ibex_pkg_IC_INDEX_W) - ibex_pkg_IC_LINE_W) + 1;
+	localparam [31:0] TagSizeECC = (ICacheECC ? ibex_pkg_IC_TAG_SIZE + 6 : ibex_pkg_IC_TAG_SIZE);
+	wire clk;
+	wire core_busy_d;
+	reg core_busy_q;
+	wire clock_en;
+	wire irq_pending;
+	wire dummy_instr_id;
+	wire [4:0] rf_raddr_a;
+	wire [4:0] rf_raddr_b;
+	wire [4:0] rf_waddr_wb;
+	wire rf_we_wb;
+	wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc;
+	wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc;
+	wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc;
+	wire [1:0] ic_tag_req;
+	wire ic_tag_write;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] ic_tag_addr;
+	wire [TagSizeECC - 1:0] ic_tag_wdata;
+	wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] ic_tag_rdata;
+	wire [1:0] ic_data_req;
+	wire ic_data_write;
+	wire [ibex_pkg_IC_INDEX_W - 1:0] ic_data_addr;
+	wire [LineSizeECC - 1:0] ic_data_wdata;
+	wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] ic_data_rdata;
+	wire core_alert_major;
+	wire core_alert_minor;
+	wire lockstep_alert_major;
+	wire lockstep_alert_minor;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni)
+			core_busy_q <= 1'b0;
+		else
+			core_busy_q <= core_busy_d;
+	assign clock_en = ((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i;
+	assign core_sleep_o = ~clock_en;
+	prim_clock_gating core_clock_gate_i(
+		.clk_i(clk_i),
+		.en_i(clock_en),
+		.test_en_i(test_en_i),
+		.clk_o(clk)
+	);
+	ibex_core #(
+		.PMPEnable(PMPEnable),
+		.PMPGranularity(PMPGranularity),
+		.PMPNumRegions(PMPNumRegions),
+		.MHPMCounterNum(MHPMCounterNum),
+		.MHPMCounterWidth(MHPMCounterWidth),
+		.RV32E(RV32E),
+		.RV32M(RV32M),
+		.RV32B(RV32B),
+		.RV32Zk(RV32Zk),
+		.BranchTargetALU(BranchTargetALU),
+		.ICache(ICache),
+		.ICacheECC(ICacheECC),
+		.BusSizeECC(BusSizeECC),
+		.TagSizeECC(TagSizeECC),
+		.LineSizeECC(LineSizeECC),
+		.BranchPredictor(BranchPredictor),
+		.DbgTriggerEn(DbgTriggerEn),
+		.DbgHwBreakNum(DbgHwBreakNum),
+		.WritebackStage(WritebackStage),
+		.ResetAll(ResetAll),
+		.RndCnstLfsrSeed(RndCnstLfsrSeed),
+		.RndCnstLfsrPerm(RndCnstLfsrPerm),
+		.SecureIbex(SecureIbex),
+		.DummyInstructions(DummyInstructions),
+		.RegFileECC(RegFileECC),
+		.RegFileDataWidth(RegFileDataWidth),
+		.DmHaltAddr(DmHaltAddr),
+		.DmExceptionAddr(DmExceptionAddr)
+	) u_ibex_core(
+		.clk_i(clk),
+		.rst_ni(rst_ni),
+		.hart_id_i(hart_id_i),
+		.boot_addr_i(boot_addr_i),
+		.instr_req_o(instr_req_o),
+		.instr_gnt_i(instr_gnt_i),
+		.instr_rvalid_i(instr_rvalid_i),
+		.instr_addr_o(instr_addr_o),
+		.instr_rdata_i(instr_rdata_i),
+		.instr_err_i(instr_err_i),
+		.data_req_o(data_req_o),
+		.data_gnt_i(data_gnt_i),
+		.data_rvalid_i(data_rvalid_i),
+		.data_we_o(data_we_o),
+		.data_be_o(data_be_o),
+		.data_addr_o(data_addr_o),
+		.data_wdata_o(data_wdata_o),
+		.data_rdata_i(data_rdata_i),
+		.data_err_i(data_err_i),
+		.eFPGA_operand_a_o(eFPGA_operand_a_o),
+		.eFPGA_operand_b_o(eFPGA_operand_b_o),
+		.eFPGA_result_a_i(eFPGA_result_a_i),
+		.eFPGA_result_b_i(eFPGA_result_b_i),
+		.eFPGA_result_c_i(eFPGA_result_c_i),
+		.eFPGA_write_strobe_o(eFPGA_write_strobe_o),
+		.eFPGA_fpga_done_i(eFPGA_fpga_done_i),
+		.eFPGA_en_o(eFPGA_en_o),
+		.eFPGA_operator_o(eFPGA_operator_o),
+		.eFPGA_delay_o(eFPGA_delay_o),
+		.dummy_instr_id_o(dummy_instr_id),
+		.rf_raddr_a_o(rf_raddr_a),
+		.rf_raddr_b_o(rf_raddr_b),
+		.rf_waddr_wb_o(rf_waddr_wb),
+		.rf_we_wb_o(rf_we_wb),
+		.rf_wdata_wb_ecc_o(rf_wdata_wb_ecc),
+		.rf_rdata_a_ecc_i(rf_rdata_a_ecc),
+		.rf_rdata_b_ecc_i(rf_rdata_b_ecc),
+		.ic_tag_req_o(ic_tag_req),
+		.ic_tag_write_o(ic_tag_write),
+		.ic_tag_addr_o(ic_tag_addr),
+		.ic_tag_wdata_o(ic_tag_wdata),
+		.ic_tag_rdata_i(ic_tag_rdata),
+		.ic_data_req_o(ic_data_req),
+		.ic_data_write_o(ic_data_write),
+		.ic_data_addr_o(ic_data_addr),
+		.ic_data_wdata_o(ic_data_wdata),
+		.ic_data_rdata_i(ic_data_rdata),
+		.irq_software_i(irq_software_i),
+		.irq_timer_i(irq_timer_i),
+		.irq_external_i(irq_external_i),
+		.irq_fast_i(irq_fast_i),
+		.irq_nm_i(irq_nm_i),
+		.irq_pending_o(irq_pending),
+		.debug_req_i(debug_req_i),
+		.crash_dump_o(crash_dump_o),
+		.fetch_enable_i(fetch_enable_i),
+		.alert_minor_o(core_alert_minor),
+		.alert_major_o(core_alert_major),
+		.core_busy_o(core_busy_d)
+	);
+	generate
+		if (RegFile == 32'sd0) begin : gen_regfile_ff
+			ibex_register_file_ff #(
+				.RV32E(RV32E),
+				.DataWidth(RegFileDataWidth),
+				.DummyInstructions(DummyInstructions)
+			) register_file_i(
+				.clk_i(clk),
+				.rst_ni(rst_ni),
+				.test_en_i(test_en_i),
+				.dummy_instr_id_i(dummy_instr_id),
+				.raddr_a_i(rf_raddr_a),
+				.rdata_a_o(rf_rdata_a_ecc),
+				.raddr_b_i(rf_raddr_b),
+				.rdata_b_o(rf_rdata_b_ecc),
+				.waddr_a_i(rf_waddr_wb),
+				.wdata_a_i(rf_wdata_wb_ecc),
+				.we_a_i(rf_we_wb)
+			);
+		end
+		else if (RegFile == 32'sd1) begin : gen_regfile_fpga
+			ibex_register_file_fpga #(
+				.RV32E(RV32E),
+				.DataWidth(RegFileDataWidth),
+				.DummyInstructions(DummyInstructions)
+			) register_file_i(
+				.clk_i(clk),
+				.rst_ni(rst_ni),
+				.test_en_i(test_en_i),
+				.dummy_instr_id_i(dummy_instr_id),
+				.raddr_a_i(rf_raddr_a),
+				.rdata_a_o(rf_rdata_a_ecc),
+				.raddr_b_i(rf_raddr_b),
+				.rdata_b_o(rf_rdata_b_ecc),
+				.waddr_a_i(rf_waddr_wb),
+				.wdata_a_i(rf_wdata_wb_ecc),
+				.we_a_i(rf_we_wb)
+			);
+		end
+		else if (RegFile == 32'sd2) begin : gen_regfile_latch
+			ibex_register_file_latch #(
+				.RV32E(RV32E),
+				.DataWidth(RegFileDataWidth),
+				.DummyInstructions(DummyInstructions)
+			) register_file_i(
+				.clk_i(clk),
+				.rst_ni(rst_ni),
+				.test_en_i(test_en_i),
+				.dummy_instr_id_i(dummy_instr_id),
+				.raddr_a_i(rf_raddr_a),
+				.rdata_a_o(rf_rdata_a_ecc),
+				.raddr_b_i(rf_raddr_b),
+				.rdata_b_o(rf_rdata_b_ecc),
+				.waddr_a_i(rf_waddr_wb),
+				.wdata_a_i(rf_wdata_wb_ecc),
+				.we_a_i(rf_we_wb)
+			);
+		end
+	endgenerate
+	wire unused_ram_cfg;
+	wire unused_ram_inputs;
+	assign unused_ram_cfg = ram_cfg_i;
+	assign unused_ram_inputs = ((((((|ic_tag_req & ic_tag_write) & |ic_tag_addr) & |ic_tag_wdata) & |ic_data_req) & ic_data_write) & |ic_data_addr) & |ic_data_wdata;
+	function automatic [TagSizeECC - 1:0] sv2v_cast_CFEC9;
+		input reg [TagSizeECC - 1:0] inp;
+		sv2v_cast_CFEC9 = inp;
+	endfunction
+	assign ic_tag_rdata = {ibex_pkg_IC_NUM_WAYS {sv2v_cast_CFEC9('b0)}};
+	function automatic [LineSizeECC - 1:0] sv2v_cast_80844;
+		input reg [LineSizeECC - 1:0] inp;
+		sv2v_cast_80844 = inp;
+	endfunction
+	assign ic_data_rdata = {ibex_pkg_IC_NUM_WAYS {sv2v_cast_80844('b0)}};
+	assign lockstep_alert_major = 1'b0;
+	assign lockstep_alert_minor = 1'b0;
+	assign data_wdata_intg_o = 'b0;
+	wire unused_scan;
+	wire unused_intg;
+	assign unused_scan = scan_rst_ni;
+	assign unused_intg = |{instr_rdata_intg_i, data_rdata_intg_i};
+	assign alert_major_o = core_alert_major | lockstep_alert_major;
+	assign alert_minor_o = core_alert_minor | lockstep_alert_minor;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_wb_stage.v b/verilog/rtl/ibex_core/ibex_wb_stage.v
new file mode 100644
index 0000000..3460e52
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_wb_stage.v
@@ -0,0 +1,159 @@
+module ibex_wb_stage (
+	clk_i,
+	rst_ni,
+	en_wb_i,
+	instr_type_wb_i,
+	pc_id_i,
+	instr_is_compressed_id_i,
+	instr_perf_count_id_i,
+	ready_wb_o,
+	rf_write_wb_o,
+	outstanding_load_wb_o,
+	outstanding_store_wb_o,
+	pc_wb_o,
+	perf_instr_ret_wb_o,
+	perf_instr_ret_compressed_wb_o,
+	perf_instr_ret_wb_spec_o,
+	perf_instr_ret_compressed_wb_spec_o,
+	rf_waddr_id_i,
+	rf_wdata_id_i,
+	rf_we_id_i,
+	rf_wdata_lsu_i,
+	rf_we_lsu_i,
+	rf_wdata_fwd_wb_o,
+	rf_waddr_wb_o,
+	rf_wdata_wb_o,
+	rf_we_wb_o,
+	lsu_resp_valid_i,
+	lsu_resp_err_i,
+	instr_done_wb_o
+);
+	parameter [0:0] ResetAll = 1'b0;
+	parameter [0:0] WritebackStage = 1'b0;
+	input wire clk_i;
+	input wire rst_ni;
+	input wire en_wb_i;
+	input wire [1:0] instr_type_wb_i;
+	input wire [31:0] pc_id_i;
+	input wire instr_is_compressed_id_i;
+	input wire instr_perf_count_id_i;
+	output wire ready_wb_o;
+	output wire rf_write_wb_o;
+	output wire outstanding_load_wb_o;
+	output wire outstanding_store_wb_o;
+	output wire [31:0] pc_wb_o;
+	output wire perf_instr_ret_wb_o;
+	output wire perf_instr_ret_compressed_wb_o;
+	output wire perf_instr_ret_wb_spec_o;
+	output wire perf_instr_ret_compressed_wb_spec_o;
+	input wire [4:0] rf_waddr_id_i;
+	input wire [31:0] rf_wdata_id_i;
+	input wire rf_we_id_i;
+	input wire [31:0] rf_wdata_lsu_i;
+	input wire rf_we_lsu_i;
+	output wire [31:0] rf_wdata_fwd_wb_o;
+	output wire [4:0] rf_waddr_wb_o;
+	output wire [31:0] rf_wdata_wb_o;
+	output wire rf_we_wb_o;
+	input wire lsu_resp_valid_i;
+	input wire lsu_resp_err_i;
+	output wire instr_done_wb_o;
+	wire [31:0] rf_wdata_wb_mux [0:1];
+	wire [1:0] rf_wdata_wb_mux_we;
+	generate
+		if (WritebackStage) begin : g_writeback_stage
+			reg [31:0] rf_wdata_wb_q;
+			reg rf_we_wb_q;
+			reg [4:0] rf_waddr_wb_q;
+			wire wb_done;
+			reg wb_valid_q;
+			reg [31:0] wb_pc_q;
+			reg wb_compressed_q;
+			reg wb_count_q;
+			reg [1:0] wb_instr_type_q;
+			wire wb_valid_d;
+			assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);
+			assign wb_done = (wb_instr_type_q == 2'd2) | lsu_resp_valid_i;
+			always @(posedge clk_i or negedge rst_ni)
+				if (!rst_ni)
+					wb_valid_q <= 1'b0;
+				else
+					wb_valid_q <= wb_valid_d;
+			if (ResetAll) begin : g_wb_regs_ra
+				always @(posedge clk_i or negedge rst_ni)
+					if (!rst_ni) begin
+						rf_we_wb_q <= 1'sb0;
+						rf_waddr_wb_q <= 1'sb0;
+						rf_wdata_wb_q <= 1'sb0;
+						wb_instr_type_q <= 2'd0;
+						wb_pc_q <= 1'sb0;
+						wb_compressed_q <= 1'sb0;
+						wb_count_q <= 1'sb0;
+					end
+					else if (en_wb_i) begin
+						rf_we_wb_q <= rf_we_id_i;
+						rf_waddr_wb_q <= rf_waddr_id_i;
+						rf_wdata_wb_q <= rf_wdata_id_i;
+						wb_instr_type_q <= instr_type_wb_i;
+						wb_pc_q <= pc_id_i;
+						wb_compressed_q <= instr_is_compressed_id_i;
+						wb_count_q <= instr_perf_count_id_i;
+					end
+			end
+			else begin : g_wb_regs_nr
+				always @(posedge clk_i)
+					if (en_wb_i) begin
+						rf_we_wb_q <= rf_we_id_i;
+						rf_waddr_wb_q <= rf_waddr_id_i;
+						rf_wdata_wb_q <= rf_wdata_id_i;
+						wb_instr_type_q <= instr_type_wb_i;
+						wb_pc_q <= pc_id_i;
+						wb_compressed_q <= instr_is_compressed_id_i;
+						wb_count_q <= instr_perf_count_id_i;
+					end
+			end
+			assign rf_waddr_wb_o = rf_waddr_wb_q;
+			assign rf_wdata_wb_mux[0] = rf_wdata_wb_q;
+			assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;
+			assign ready_wb_o = ~wb_valid_q | wb_done;
+			assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == 2'd0));
+			assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == 2'd0);
+			assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == 2'd1);
+			assign pc_wb_o = wb_pc_q;
+			assign instr_done_wb_o = wb_valid_q & wb_done;
+			assign perf_instr_ret_wb_spec_o = wb_count_q;
+			assign perf_instr_ret_compressed_wb_spec_o = perf_instr_ret_wb_spec_o & wb_compressed_q;
+			assign perf_instr_ret_wb_o = (instr_done_wb_o & wb_count_q) & ~(lsu_resp_valid_i & lsu_resp_err_i);
+			assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q;
+			assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
+		end
+		else begin : g_bypass_wb
+			assign rf_waddr_wb_o = rf_waddr_id_i;
+			assign rf_wdata_wb_mux[0] = rf_wdata_id_i;
+			assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
+			assign perf_instr_ret_wb_spec_o = 1'b0;
+			assign perf_instr_ret_compressed_wb_spec_o = 1'b0;
+			assign perf_instr_ret_wb_o = (instr_perf_count_id_i & en_wb_i) & ~(lsu_resp_valid_i & lsu_resp_err_i);
+			assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i;
+			assign ready_wb_o = 1'b1;
+			wire unused_clk;
+			wire unused_rst;
+			wire [1:0] unused_instr_type_wb;
+			wire [31:0] unused_pc_id;
+			assign unused_clk = clk_i;
+			assign unused_rst = rst_ni;
+			assign unused_instr_type_wb = instr_type_wb_i;
+			assign unused_pc_id = pc_id_i;
+			assign outstanding_load_wb_o = 1'b0;
+			assign outstanding_store_wb_o = 1'b0;
+			assign pc_wb_o = 1'sb0;
+			assign rf_write_wb_o = 1'b0;
+			assign rf_wdata_fwd_wb_o = 32'b00000000000000000000000000000000;
+			assign instr_done_wb_o = 1'b0;
+		end
+	endgenerate
+	assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i;
+	assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
+	assign rf_wdata_wb_o = ({32 {rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) | ({32 {rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
+	assign rf_we_wb_o = |rf_wdata_wb_mux_we;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibex_zk.v b/verilog/rtl/ibex_core/ibex_zk.v
new file mode 100644
index 0000000..1e80e35
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibex_zk.v
@@ -0,0 +1,406 @@
+module ibex_zk (
+	operator_i,
+	operand_a_i,
+	operand_b_i,
+	result_o,
+	zk_val_o
+);
+	parameter integer RV32Zk = 32'sd0;
+	input wire [6:0] operator_i;
+	input wire [31:0] operand_a_i;
+	input wire [31:0] operand_b_i;
+	output wire [31:0] result_o;
+	output wire zk_val_o;
+	function automatic [31:0] ror32;
+		input reg [31:0] x;
+		input reg [4:0] amt;
+		reg [31:0] ro;
+		reg [31:0] l8;
+		reg [31:0] l4;
+		reg [31:0] l2;
+		reg [31:0] l1;
+		reg [31:0] l0;
+		begin
+			l0 = x;
+			l1 = ({32 {amt[0]}} & {l0[0], l0[31:1]}) | ({32 {!amt[0]}} & l0[31:0]);
+			l2 = ({32 {amt[1]}} & {l1[1:0], l1[31:2]}) | ({32 {!amt[1]}} & l1[31:0]);
+			l4 = ({32 {amt[2]}} & {l2[3:0], l2[31:4]}) | ({32 {!amt[2]}} & l2[31:0]);
+			l8 = ({32 {amt[3]}} & {l4[7:0], l4[31:8]}) | ({32 {!amt[3]}} & l4[31:0]);
+			ro = ({32 {amt[4]}} & {l8[15:0], l8[31:16]}) | ({32 {!amt[4]}} & l8[31:0]);
+			ror32 = ro;
+		end
+	endfunction
+	function automatic [31:0] rol32;
+		input reg [31:0] x;
+		input reg [4:0] amt;
+		reg [31:0] ro;
+		reg [31:0] l8;
+		reg [31:0] l4;
+		reg [31:0] l2;
+		reg [31:0] l1;
+		reg [31:0] l0;
+		begin
+			l0 = x;
+			l1 = ({32 {amt[0]}} & {l0[30:0], l0[31]}) | ({32 {!amt[0]}} & l0[31:0]);
+			l2 = ({32 {amt[1]}} & {l1[29:0], l1[31:30]}) | ({32 {!amt[1]}} & l1[31:0]);
+			l4 = ({32 {amt[2]}} & {l2[27:0], l2[31:28]}) | ({32 {!amt[2]}} & l2[31:0]);
+			l8 = ({32 {amt[3]}} & {l4[23:0], l4[31:24]}) | ({32 {!amt[3]}} & l4[31:0]);
+			ro = ({32 {amt[4]}} & {l8[15:0], l8[31:16]}) | ({32 {!amt[4]}} & l8[31:0]);
+			rol32 = ro;
+		end
+	endfunction
+	function automatic [7:0] rev8;
+		input reg [7:0] x;
+		reg [7:0] rb;
+		begin
+			begin : sv2v_autoblock_1
+				reg signed [31:0] i;
+				for (i = 0; i < 8; i = i + 1)
+					rb[i] = x[(8 - i) - 1];
+			end
+			rev8 = rb;
+		end
+	endfunction
+	function automatic [31:0] zip32;
+		input reg [31:0] x;
+		reg [31:0] uz;
+		begin
+			begin : sv2v_autoblock_2
+				reg signed [31:0] i;
+				for (i = 0; i < 16; i = i + 1)
+					begin
+						uz[2 * i] = x[i];
+						uz[(2 * i) + 1] = x[i + 16];
+					end
+			end
+			zip32 = uz;
+		end
+	endfunction
+	function automatic [31:0] unzip32;
+		input reg [31:0] x;
+		reg [15:0] zh;
+		reg [15:0] zl;
+		begin
+			begin : sv2v_autoblock_3
+				reg signed [31:0] i;
+				for (i = 0; i < 16; i = i + 1)
+					begin
+						zh[i] = x[(2 * i) + 1];
+						zl[i] = x[2 * i];
+					end
+			end
+			unzip32 = {zh, zl};
+		end
+	endfunction
+	function automatic [7:0] xtime2;
+		input reg [7:0] a;
+		reg [7:0] x2;
+		begin
+			x2 = {a[6:0], 1'b0} ^ (a[7] ? 8'h1b : 8'b00000000);
+			xtime2 = x2;
+		end
+	endfunction
+	function automatic [7:0] xtimeN;
+		input reg [7:0] a;
+		input reg [3:0] b;
+		reg [7:0] xn;
+		begin
+			xn = (((b[0] ? a : 0) ^ (b[1] ? xtime2(a) : 0)) ^ (b[2] ? xtime2(xtime2(a)) : 0)) ^ (b[3] ? xtime2(xtime2(xtime2(a))) : 0);
+			xtimeN = xn;
+		end
+	endfunction
+	wire zkb_val;
+	wire [31:0] zkb_result;
+	generate
+		if (RV32Zk != 32'sd0) begin : gen_zkb
+			wire ror_sel;
+			wire rol_sel;
+			wire rori_sel;
+			wire andn_sel;
+			wire orn_sel;
+			wire xnor_sel;
+			wire pack_sel;
+			wire packh_sel;
+			wire brev8_sel;
+			wire rev8_sel;
+			wire zip_sel;
+			wire unzip_sel;
+			wire clmull_sel;
+			wire clmulh_sel;
+			wire xperm8_sel;
+			wire xperm4_sel;
+			assign ror_sel = operator_i == 7'd67;
+			assign rol_sel = operator_i == 7'd68;
+			assign rori_sel = operator_i == 7'd62;
+			assign andn_sel = operator_i == 7'd69;
+			assign orn_sel = operator_i == 7'd70;
+			assign xnor_sel = operator_i == 7'd71;
+			assign pack_sel = operator_i == 7'd72;
+			assign packh_sel = operator_i == 7'd73;
+			assign brev8_sel = operator_i == 7'd63;
+			assign rev8_sel = operator_i == 7'd64;
+			assign zip_sel = operator_i == 7'd65;
+			assign unzip_sel = operator_i == 7'd66;
+			assign clmull_sel = operator_i == 7'd74;
+			assign clmulh_sel = operator_i == 7'd75;
+			assign xperm8_sel = operator_i == 7'd76;
+			assign xperm4_sel = operator_i == 7'd77;
+			wire [4:0] shamt;
+			assign shamt = operand_b_i[4:0];
+			wire [31:0] wror;
+			wire [31:0] wrol;
+			wire [31:0] wandn;
+			wire [31:0] worn;
+			wire [31:0] wxnor;
+			wire [31:0] wpack;
+			wire [31:0] wpackh;
+			assign wror = ror32(operand_a_i, shamt);
+			assign wrol = rol32(operand_a_i, shamt);
+			assign wandn = operand_a_i & ~operand_b_i;
+			assign worn = operand_a_i | ~operand_b_i;
+			assign wxnor = operand_a_i ^ ~operand_b_i;
+			assign wpack = {operand_b_i[15:0], operand_a_i[15:0]};
+			assign wpackh = {16'd0, operand_b_i[7:0], operand_a_i[7:0]};
+			wire [7:0] rs1_b0;
+			wire [7:0] rs1_b1;
+			wire [7:0] rs1_b2;
+			wire [7:0] rs1_b3;
+			assign rs1_b0 = operand_a_i[7:0];
+			assign rs1_b1 = operand_a_i[15:8];
+			assign rs1_b2 = operand_a_i[23:16];
+			assign rs1_b3 = operand_a_i[31:24];
+			wire [7:0] brev8_0;
+			wire [7:0] brev8_1;
+			wire [7:0] brev8_2;
+			wire [7:0] brev8_3;
+			assign brev8_0 = rev8(rs1_b0);
+			assign brev8_1 = rev8(rs1_b1);
+			assign brev8_2 = rev8(rs1_b2);
+			assign brev8_3 = rev8(rs1_b3);
+			wire [31:0] wbrev8;
+			wire [31:0] wrev8;
+			assign wbrev8 = {brev8_3, brev8_2, brev8_1, brev8_0};
+			assign wrev8 = {rs1_b0, rs1_b1, rs1_b2, rs1_b3};
+			wire [31:0] wzip;
+			wire [31:0] wunzip;
+			assign wzip = zip32(operand_a_i);
+			assign wunzip = unzip32(operand_a_i);
+			wire [3:0] lut_4b [7:0];
+			wire [31:0] wxperm4;
+			genvar i;
+			for (i = 0; i < 8; i = i + 1) begin : gen_lut_xperm4
+				assign lut_4b[i] = operand_a_i[4 * i+:4];
+				wire [2:0] lut_8idx;
+				assign lut_8idx = operand_b_i[4 * i+:3];
+				wire [3:0] lut4_out;
+				assign lut4_out = lut_4b[lut_8idx];
+				assign wxperm4[i * 4+:4] = (operand_b_i[(4 * i) + 3] ? 4'b0000 : lut4_out);
+			end
+			wire [7:0] lut_8b [3:0];
+			wire [31:0] wxperm8;
+			for (i = 0; i < 4; i = i + 1) begin : gen_lut_xperm8
+				assign lut_8b[i] = operand_a_i[8 * i+:8];
+				wire [1:0] lut_4idx;
+				assign lut_4idx = operand_b_i[8 * i+:2];
+				wire [7:0] lut8_out;
+				assign lut8_out = lut_8b[lut_4idx];
+				assign wxperm8[i * 8+:8] = (|{operand_b_i[(8 * i) + 7:(8 * i) + 2]} ? 8'd0 : lut8_out);
+			end
+			wire [15:0] lhs0;
+			wire [15:0] rhs0;
+			wire [15:0] lhs1;
+			wire [15:0] rhs1;
+			wire [15:0] lhs2;
+			wire [15:0] rhs2;
+			assign lhs0 = (clmulh_sel ? operand_a_i[31:16] : operand_a_i[15:0]);
+			assign rhs0 = (clmulh_sel ? operand_b_i[31:16] : operand_b_i[15:0]);
+			assign lhs1 = operand_a_i[15:0];
+			assign rhs1 = operand_b_i[31:16];
+			assign lhs2 = operand_a_i[31:16];
+			assign rhs2 = operand_b_i[15:0];
+			wire [31:0] polymul0;
+			wire [31:0] polymul1;
+			wire [31:0] polymul2;
+			ibex_poly16_mul mul16_ins0(
+				lhs0,
+				rhs0,
+				polymul0
+			);
+			ibex_poly16_mul mul16_ins1(
+				lhs1,
+				rhs1,
+				polymul1
+			);
+			ibex_poly16_mul mul16_ins2(
+				lhs2,
+				rhs2,
+				polymul2
+			);
+			wire [31:0] wclmull;
+			wire [31:0] wclmulh;
+			wire [31:0] clmulm;
+			assign clmulm = polymul1 ^ polymul2;
+			assign wclmulh = {polymul0[31:16], polymul0[15:0] ^ clmulm[31:16]};
+			assign wclmull = {polymul0[31:16] ^ clmulm[15:0], polymul0[15:0]};
+			assign zkb_val = |{ror_sel, rol_sel, rori_sel, andn_sel, orn_sel, xnor_sel, pack_sel, packh_sel, brev8_sel, rev8_sel, zip_sel, unzip_sel, clmull_sel, clmulh_sel, xperm8_sel, xperm4_sel};
+			assign zkb_result = ((((((((((((((({32 {ror_sel}} & wror) | ({32 {rol_sel}} & wrol)) | ({32 {rori_sel}} & wror)) | ({32 {andn_sel}} & wandn)) | ({32 {orn_sel}} & worn)) | ({32 {xnor_sel}} & wxnor)) | ({32 {pack_sel}} & wpack)) | ({32 {packh_sel}} & wpackh)) | ({32 {brev8_sel}} & wbrev8)) | ({32 {rev8_sel}} & wrev8)) | ({32 {zip_sel}} & wzip)) | ({32 {unzip_sel}} & wunzip)) | ({32 {clmull_sel}} & wclmull)) | ({32 {clmulh_sel}} & wclmulh)) | ({32 {xperm8_sel}} & wxperm8)) | ({32 {xperm4_sel}} & wxperm4);
+		end
+		else begin : no_gen_zkb
+			assign zkb_val = 1'b0;
+			assign zkb_result = 32'd0;
+		end
+	endgenerate
+	wire zkn_val;
+	wire [31:0] zkn_result;
+	generate
+		if (RV32Zk == 32'sd2) begin : gen_zkn
+			wire bs0;
+			wire bs1;
+			wire bs2;
+			wire bs3;
+			assign bs0 = (((operator_i == 7'd88) || (operator_i == 7'd92)) || (operator_i == 7'd96)) || (operator_i == 7'd100);
+			assign bs1 = (((operator_i == 7'd89) || (operator_i == 7'd93)) || (operator_i == 7'd97)) || (operator_i == 7'd101);
+			assign bs2 = (((operator_i == 7'd90) || (operator_i == 7'd94)) || (operator_i == 7'd98)) || (operator_i == 7'd102);
+			assign bs3 = (((operator_i == 7'd91) || (operator_i == 7'd95)) || (operator_i == 7'd99)) || (operator_i == 7'd103);
+			wire decs_sel;
+			wire encs_sel;
+			wire decsm_sel;
+			wire encsm_sel;
+			assign decs_sel = (((operator_i == 7'd88) || (operator_i == 7'd89)) || (operator_i == 7'd90)) || (operator_i == 7'd91);
+			assign encs_sel = (((operator_i == 7'd96) || (operator_i == 7'd97)) || (operator_i == 7'd98)) || (operator_i == 7'd99);
+			assign decsm_sel = (((operator_i == 7'd92) || (operator_i == 7'd93)) || (operator_i == 7'd94)) || (operator_i == 7'd95);
+			assign encsm_sel = (((operator_i == 7'd100) || (operator_i == 7'd101)) || (operator_i == 7'd102)) || (operator_i == 7'd103);
+			wire aes32_sel;
+			assign aes32_sel = ((decs_sel || encs_sel) || encsm_sel) || decsm_sel;
+			wire [7:0] sel_byte;
+			assign sel_byte = ((({8 {bs0}} & operand_b_i[7:0]) | ({8 {bs1}} & operand_b_i[15:8])) | ({8 {bs2}} & operand_b_i[23:16])) | ({8 {bs3}} & operand_b_i[31:24]);
+			wire dec;
+			wire mix;
+			assign dec = decs_sel || decsm_sel;
+			assign mix = encsm_sel || decsm_sel;
+			wire [7:0] sbox_out;
+			ibex_aes_sbox i_aes_sbox(
+				.fw(~dec),
+				.in(sel_byte),
+				.fx(sbox_out)
+			);
+			wire [7:0] mix_b0;
+			wire [7:0] mix_b1;
+			wire [7:0] mix_b2;
+			wire [7:0] mix_b3;
+			assign mix_b3 = xtimeN(sbox_out, (dec ? 11 : 3));
+			assign mix_b2 = (dec ? xtimeN(sbox_out, 13) : sbox_out);
+			assign mix_b1 = (dec ? xtimeN(sbox_out, 9) : sbox_out);
+			assign mix_b0 = xtimeN(sbox_out, (dec ? 14 : 2));
+			wire [31:0] mixed;
+			wire [31:0] sbox_mix;
+			wire [31:0] rotated;
+			assign mixed = {mix_b3, mix_b2, mix_b1, mix_b0};
+			assign sbox_mix = (mix ? mixed : {24'b000000000000000000000000, sbox_out});
+			assign rotated = ((({32 {bs0}} & {sbox_mix}) | ({32 {bs1}} & {sbox_mix[23:0], sbox_mix[31:24]})) | ({32 {bs2}} & {sbox_mix[15:0], sbox_mix[31:16]})) | ({32 {bs3}} & {sbox_mix[7:0], sbox_mix[31:8]});
+			wire sha256_sum0_sel;
+			wire sha256_sum1_sel;
+			wire sha256_sig0_sel;
+			wire sha256_sig1_sel;
+			assign sha256_sum0_sel = operator_i == 7'd78;
+			assign sha256_sum1_sel = operator_i == 7'd79;
+			assign sha256_sig0_sel = operator_i == 7'd80;
+			assign sha256_sig1_sel = operator_i == 7'd81;
+			wire sha512_sum0r_sel;
+			wire sha512_sum1r_sel;
+			wire sha512_sig0l_sel;
+			wire sha512_sig1l_sel;
+			wire sha512_sig0h_sel;
+			wire sha512_sig1h_sel;
+			assign sha512_sum0r_sel = operator_i == 7'd82;
+			assign sha512_sum1r_sel = operator_i == 7'd83;
+			assign sha512_sig0l_sel = operator_i == 7'd84;
+			assign sha512_sig0h_sel = operator_i == 7'd86;
+			assign sha512_sig1l_sel = operator_i == 7'd85;
+			assign sha512_sig1h_sel = operator_i == 7'd87;
+			wire [31:0] sha256_sum0;
+			wire [31:0] sha256_sum1;
+			wire [31:0] sha256_sig0;
+			wire [31:0] sha256_sig1;
+			assign sha256_sig0 = (((operand_a_i >> 7) | (operand_a_i << 25)) ^ ((operand_a_i >> 18) | (operand_a_i << 14))) ^ (operand_a_i >> 3);
+			assign sha256_sig1 = (((operand_a_i >> 17) | (operand_a_i << 15)) ^ ((operand_a_i >> 19) | (operand_a_i << 13))) ^ (operand_a_i >> 10);
+			assign sha256_sum0 = (((operand_a_i >> 2) | (operand_a_i << 30)) ^ ((operand_a_i >> 13) | (operand_a_i << 19))) ^ ((operand_a_i >> 22) | (operand_a_i << 10));
+			assign sha256_sum1 = (((operand_a_i >> 6) | (operand_a_i << 26)) ^ ((operand_a_i >> 11) | (operand_a_i << 21))) ^ ((operand_a_i >> 25) | (operand_a_i << 7));
+			wire [31:0] sha512_sum0r;
+			wire [31:0] sha512_sum1r;
+			wire [31:0] sha512_sig0l;
+			wire [31:0] sha512_sig1l;
+			wire [31:0] sha512_sig0h;
+			wire [31:0] sha512_sig1h;
+			assign sha512_sum0r = (((((operand_a_i << 25) ^ (operand_a_i << 30)) ^ (operand_a_i >> 28)) ^ (operand_b_i >> 7)) ^ (operand_b_i >> 2)) ^ (operand_b_i << 4);
+			assign sha512_sum1r = (((((operand_a_i << 23) ^ (operand_a_i >> 14)) ^ (operand_a_i >> 18)) ^ (operand_b_i >> 9)) ^ (operand_b_i << 18)) ^ (operand_b_i << 14);
+			assign sha512_sig0l = (((((operand_a_i >> 1) ^ (operand_a_i >> 7)) ^ (operand_a_i >> 8)) ^ (operand_b_i << 31)) ^ (operand_b_i << 25)) ^ (operand_b_i << 24);
+			assign sha512_sig0h = ((((operand_a_i >> 1) ^ (operand_a_i >> 7)) ^ (operand_a_i >> 8)) ^ (operand_b_i << 31)) ^ (operand_b_i << 24);
+			assign sha512_sig1l = (((((operand_a_i << 3) ^ (operand_a_i >> 6)) ^ (operand_a_i >> 19)) ^ (operand_b_i >> 29)) ^ (operand_b_i << 26)) ^ (operand_b_i << 13);
+			assign sha512_sig1h = ((((operand_a_i << 3) ^ (operand_a_i >> 6)) ^ (operand_a_i >> 19)) ^ (operand_b_i >> 29)) ^ (operand_b_i << 13);
+			assign zkn_val = |{sha256_sum0_sel, sha256_sum1_sel, sha256_sig0_sel, sha256_sig1_sel, sha512_sum0r_sel, sha512_sum1r_sel, sha512_sig0l_sel, sha512_sig1l_sel, sha512_sig0h_sel, sha512_sig1h_sel, aes32_sel};
+			assign zkn_result = (((((((((({32 {aes32_sel}} & (rotated ^ operand_a_i)) | ({32 {sha256_sig0_sel}} & sha256_sig0)) | ({32 {sha256_sig1_sel}} & sha256_sig1)) | ({32 {sha256_sum0_sel}} & sha256_sum0)) | ({32 {sha256_sum1_sel}} & sha256_sum1)) | ({32 {sha512_sum0r_sel}} & sha512_sum0r)) | ({32 {sha512_sum1r_sel}} & sha512_sum1r)) | ({32 {sha512_sig0l_sel}} & sha512_sig0l)) | ({32 {sha512_sig0h_sel}} & sha512_sig0h)) | ({32 {sha512_sig1l_sel}} & sha512_sig1l)) | ({32 {sha512_sig1h_sel}} & sha512_sig1h);
+		end
+		else begin : no_gen_zkn
+			assign zkn_val = 1'b0;
+			assign zkn_result = 32'd0;
+		end
+	endgenerate
+	wire zks_val;
+	wire [31:0] zks_result;
+	generate
+		if (RV32Zk == 32'sd3) begin : gen_zks
+			wire sm4ed_sel;
+			wire sm4ks_sel;
+			wire sm3p0_sel;
+			wire sm3p1_sel;
+			assign sm4ed_sel = (((operator_i == 7'd104) || (operator_i == 7'd106)) || (operator_i == 7'd105)) || (operator_i == 7'd107);
+			assign sm4ks_sel = (((operator_i == 7'd108) || (operator_i == 7'd110)) || (operator_i == 7'd109)) || (operator_i == 7'd111);
+			assign sm3p0_sel = operator_i == 7'd112;
+			assign sm3p1_sel = operator_i == 7'd113;
+			wire zks_bs0;
+			wire zks_bs1;
+			wire zks_bs2;
+			wire zks_bs3;
+			assign zks_bs0 = (operator_i == 7'd104) || (operator_i == 7'd108);
+			assign zks_bs1 = (operator_i == 7'd105) || (operator_i == 7'd109);
+			assign zks_bs2 = (operator_i == 7'd106) || (operator_i == 7'd110);
+			assign zks_bs3 = (operator_i == 7'd107) || (operator_i == 7'd111);
+			wire [7:0] sbox_in;
+			assign sbox_in = ((({8 {zks_bs0}} & operand_b_i[7:0]) | ({8 {zks_bs1}} & operand_b_i[15:8])) | ({8 {zks_bs2}} & operand_b_i[23:16])) | ({8 {zks_bs3}} & operand_b_i[31:24]);
+			wire [7:0] sm4_sbox_out;
+			ibex_sm4_sbox ism4_sbox(
+				.in(sbox_in),
+				.fx(sm4_sbox_out)
+			);
+			wire [31:0] s;
+			assign s = {24'b000000000000000000000000, sm4_sbox_out};
+			wire [31:0] ed1;
+			wire [31:0] ed2;
+			assign ed1 = ((s ^ (s << 8)) ^ (s << 2)) ^ (s << 18);
+			assign ed2 = (ed1 ^ ((s & 32'h0000003f) << 26)) ^ ((s & 32'h000000c0) << 10);
+			wire [31:0] ks1;
+			wire [31:0] ks2;
+			assign ks1 = (s ^ ((s & 32'h00000007) << 29)) ^ ((s & 32'h000000fe) << 7);
+			assign ks2 = (ks1 ^ ((s & 32'h00000001) << 23)) ^ ((s & 32'h000000f8) << 13);
+			wire [31:0] rot_in;
+			wire [31:0] rot_out;
+			wire [31:0] sm4;
+			assign rot_in = (sm4ks_sel ? ks2 : ed2);
+			assign rot_out = ((({32 {zks_bs0}} & {rot_in}) | ({32 {zks_bs1}} & {rot_in[23:0], rot_in[31:24]})) | ({32 {zks_bs2}} & {rot_in[15:0], rot_in[31:16]})) | ({32 {zks_bs3}} & {rot_in[7:0], rot_in[31:8]});
+			assign sm4 = rot_out ^ operand_a_i;
+			wire [31:0] sm3_p0;
+			wire [31:0] sm3_p1;
+			assign sm3_p0 = (operand_a_i ^ ((operand_a_i << 9) | (operand_a_i >> 23))) ^ ((operand_a_i << 17) | (operand_a_i >> 15));
+			assign sm3_p1 = (operand_a_i ^ ((operand_a_i << 15) | (operand_a_i >> 17))) ^ ((operand_a_i << 23) | (operand_a_i >> 9));
+			assign zks_val = |{sm4ed_sel, sm4ks_sel, sm3p0_sel, sm3p1_sel};
+			assign zks_result = ((({32 {sm4ed_sel}} & sm4) | ({32 {sm4ks_sel}} & sm4)) | ({32 {sm3p0_sel}} & sm3_p0)) | ({32 {sm3p1_sel}} & sm3_p1);
+		end
+		else begin : no_gen_zks
+			assign zks_val = 1'b0;
+			assign zks_result = 32'd0;
+		end
+	endgenerate
+	assign zk_val_o = (zkb_val || zkn_val) || zks_val;
+	assign result_o = (zkb_result | zkn_result) | zks_result;
+endmodule
diff --git a/verilog/rtl/ibex_core/ibexcore_netlists.vh b/verilog/rtl/ibex_core/ibexcore_netlists.vh
new file mode 100644
index 0000000..5009177
--- /dev/null
+++ b/verilog/rtl/ibex_core/ibexcore_netlists.vh
@@ -0,0 +1,52 @@
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+`else
+    `include "flexbex_ibex_alu.v"
+    `include "flexbex_ibex_compressed_decoder.v"
+    `include "flexbex_ibex_controller.v"
+    `include "flexbex_ibex_core.v"
+    `include "flexbex_ibex_cs_registers.v"
+    `include "flexbex_ibex_decoder.v"
+    `include "flexbex_ibex_defines.v"
+    `include "flexbex_ibex_eFPGA.v"
+    `include "flexbex_ibex_ex_block.v"
+    `include "flexbex_ibex_fetch_fifo.v"
+    `include "flexbex_ibex_id_stage.v"
+    `include "flexbex_ibex_if_stage.v"
+    `include "flexbex_ibex_int_controller.v"
+    `include "flexbex_ibex_load_store_unit.v"
+    `include "flexbex_ibex_multdiv_fast.v"
+    `include "flexbex_ibex_prefetch_buffer.v"
+    `include "flexbex_ibex_register_file.v"
+    `include "flexbex_prim_clock_gating.v"
+    `include "ibex_aes_sbox.v"
+    `include "ibex_alu.v"
+    `include "ibex_branch_predict.v"
+    `include "ibex_compressed_decoder.v"
+    `include "ibex_controller.v"
+    `include "ibex_core.v"
+    `include "ibex_counter.v"
+    `include "ibex_cs_registers.v"
+    `include "ibex_csr.v"
+    `include "ibex_decoder.v"
+    `include "ibex_eFPGA.v"
+    `include "ibex_ex_block.v"
+    `include "ibex_fetch_fifo.v"
+    `include "ibex_icache.v"
+    `include "ibex_id_stage.v"
+    `include "ibex_if_stage.v"
+    `include "ibex_load_store_unit.v"
+    `include "ibex_multdiv_fast.v"
+    `include "ibex_multdiv_slow.v"
+    `include "ibex_poly16_mul.v"
+    `include "ibex_prefetch_buffer.v"
+    `include "ibex_register_file_ff.v"
+    `include "ibex_register_file_fpga.v"
+    `include "ibex_register_file_latch.v"
+    `include "ibex_sm4_sbox.v"
+    `include "ibex_top.v"
+    `include "ibex_wb_stage.v"
+    `include "ibex_zk.v"
+    `include "prim_clock_gating.v"
+`endif
diff --git a/verilog/rtl/ibex_core/prim_clock_gating.v b/verilog/rtl/ibex_core/prim_clock_gating.v
new file mode 100644
index 0000000..4c79019
--- /dev/null
+++ b/verilog/rtl/ibex_core/prim_clock_gating.v
@@ -0,0 +1,16 @@
+module prim_clock_gating (
+	clk_i,
+	en_i,
+	test_en_i,
+	clk_o
+);
+	input wire clk_i;
+	input wire en_i;
+	input wire test_en_i;
+	output wire clk_o;
+	reg clk_en;
+	always @(*)
+		if (clk_i == 1'b0)
+			clk_en <= en_i | test_en_i;
+	assign clk_o = clk_i & clk_en;
+endmodule
diff --git a/verilog/rtl/icesoc/axi_uart.v b/verilog/rtl/icesoc/axi_uart.v
new file mode 100644
index 0000000..a876406
--- /dev/null
+++ b/verilog/rtl/icesoc/axi_uart.v
@@ -0,0 +1,114 @@
+/*
+
+Copyright (c) 2014-2017 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+prescale = Fclk / (baud * 8)
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream UART
+ */
+module axi_uart #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
+    input  wire                   s_axis_tvalid,
+    output wire                   s_axis_tready,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
+    output wire                   m_axis_tvalid,
+    input  wire                   m_axis_tready,
+
+    /*
+     * UART interface
+     */
+    input  wire                   rxd,
+    output wire                   txd,
+
+    /*
+     * Status
+     */
+    output wire                   tx_busy,
+    output wire                   rx_busy,
+    output wire                   rx_overrun_error,
+    output wire                   rx_frame_error,
+
+    /*
+     * Configuration
+     */
+    input  wire [15:0]            prescale
+
+);
+
+uart_tx #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+uart_tx_inst (
+    .clk(clk),
+    .rst(rst),
+    // axi input
+    .s_axis_tdata(s_axis_tdata),
+    .s_axis_tvalid(s_axis_tvalid),
+    .s_axis_tready(s_axis_tready),
+    // output
+    .txd(txd),
+    // status
+    .busy(tx_busy),
+    // configuration
+    .prescale(prescale)
+);
+
+uart_rx #(
+    .DATA_WIDTH(DATA_WIDTH)
+)
+uart_rx_inst (
+    .clk(clk),
+    .rst(rst),
+    // axi output
+    .m_axis_tdata(m_axis_tdata),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tready(m_axis_tready),
+    // input
+    .rxd(rxd),
+    // status
+    .busy(rx_busy),
+    .overrun_error(rx_overrun_error),
+    .frame_error(rx_frame_error),
+    // configuration
+    .prescale(prescale)
+);
+
+endmodule
diff --git a/verilog/rtl/icesoc/icesoc_netlists.vh b/verilog/rtl/icesoc/icesoc_netlists.vh
new file mode 100644
index 0000000..c0e7c13
--- /dev/null
+++ b/verilog/rtl/icesoc/icesoc_netlists.vh
@@ -0,0 +1,15 @@
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+`else
+    `include "axi_uart.v"
+    `include "icesoc_top.v"
+    `include "inter_read.v"
+    `include "inter.v"
+    `include "peripheral.v"
+    `include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+    `include "uart_rx.v"
+    `include "uart_to_mem.v"
+    `include "uart_tx.v"
+    `include "uart.v"
+`endif
diff --git a/verilog/rtl/icesoc/icesoc_top.v b/verilog/rtl/icesoc/icesoc_top.v
new file mode 100644
index 0000000..5b0a066
--- /dev/null
+++ b/verilog/rtl/icesoc/icesoc_top.v
@@ -0,0 +1,385 @@
+`timescale 1 ps / 1 ps
+
+//need to check the address width through the application.
+
+module icesoc_top #(
+   parameter SLAVE_ADDR_WIDTH = 10,
+   parameter ADDR_WIDTH       = 12,
+   parameter MASTERS          =  4,
+   parameter SLAVES           =  3,
+   parameter ROMASTERS        =  2,
+   parameter ROSLAVES         =  2,
+   parameter ROMASTER_ADDR_WIDTH=11
+) (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+   //core 1
+   input  wire        debug_req_1_i,
+   input  wire        fetch_enable_1_i,         // enable cpu 1
+   output             irq_ack_1_o,
+   input  wire        irq_1_i,
+   input  wire [ 4:0] irq_id_1_i,
+   output wire [ 4:0] irq_id_1_o,
+   output wire [31:0] eFPGA_operand_a_1_o,
+   output wire [31:0] eFPGA_operand_b_1_o,
+   input  wire [31:0] eFPGA_result_a_1_i,
+   input  wire [31:0] eFPGA_result_b_1_i,
+   input  wire [31:0] eFPGA_result_c_1_i,       // total 160 pins to fpga
+   output wire        eFPGA_write_strobe_1_o,
+   input  wire        eFPGA_fpga_done_1_i,
+   output wire        eFPGA_en_1_o,
+   output wire [ 1:0] eFPGA_operator_1_o,
+   output wire [ 3:0] eFPGA_delay_1_o,
+
+   input  wire        debug_req_2_i,
+   input  wire        fetch_enable_2_i,          // enable cpu 2
+   output wire        irq_ack_2_o,
+   input  wire        irq_2_i,
+   input  wire [ 4:0] irq_id_2_i,
+   output wire [ 4:0] irq_id_2_o,
+   output wire [31:0] eFPGA_operand_a_2_o,
+   output wire [31:0] eFPGA_operand_b_2_o,
+   input  wire [31:0] eFPGA_result_a_2_i,
+   input  wire [31:0] eFPGA_result_b_2_i,
+   input  wire [31:0] eFPGA_result_c_2_i,        // total 160 pins to fpga
+   output wire        eFPGA_write_strobe_2_o,
+   input  wire        eFPGA_fpga_done_2_i,
+   output wire        eFPGA_en_2_o,
+   output wire [ 1:0] eFPGA_operator_2_o,
+   output wire [ 3:0] eFPGA_delay_2_o,
+
+   input  wire        rxd_uart,
+   output wire        txd_uart,
+   input  wire        rxd_uart_to_mem,
+   output wire        txd_uart_to_mem,
+   output wire        error_uart_to_mem,
+
+   input  wire        wb_clk_i,
+   input  wire        wb_rst_i,
+   input  wire        wbs_stb_i,
+   input  wire        wbs_cyc_i,
+   input  wire        wbs_we_i,
+   input  wire [ 3:0] wbs_sel_i,
+   input  wire [31:0] wbs_dat_i,
+   input  wire [31:0] wbs_adr_i,
+   output wire        wbs_ack_o,
+   output wire [31:0] wbs_dat_o
+);
+
+    wire clk_i = wb_clk_i;      //main clock 20mhz
+    wire reset = wb_rst_i;
+    wire reset_ni = ~reset;
+
+    wire [ MASTERS                     - 1:0]  master_data_req_to_inter;
+    wire [(MASTERS *  ADDR_WIDTH)      - 1:0]  master_data_addr_to_inter;
+    wire [ MASTERS                     - 1:0]  master_data_we_to_inter;
+    wire [(MASTERS * (32 / 8))         - 1:0]  master_data_be_to_inter;
+    wire [(MASTERS *  32)              - 1:0]  master_data_wdata_to_inter;
+    wire [(MASTERS *  32)              - 1:0]  master_data_rdata_to_inter;
+    wire [ MASTERS                     - 1:0]  master_data_rvalid_to_inter;
+    wire [ MASTERS                     - 1:0]  master_data_gnt_to_inter;
+
+    wire [ SLAVES                      - 1:0]  slave_data_req_to_inter;
+    wire [(SLAVES *  SLAVE_ADDR_WIDTH) - 1:0]  slave_data_addr_to_inter;
+    wire [ SLAVES                      - 1:0]  slave_data_we_to_inter;
+    wire [(SLAVES * (32 / 8) )         - 1:0]  slave_data_be_to_inter;
+    wire [(SLAVES *  32)               - 1:0]  slave_data_wdata_to_inter;
+    wire [(SLAVES *  32)               - 1:0]  slave_data_rdata_to_inter;
+
+    wire                                       slave_data_rvalid_to_inter;
+    wire                                       slave_data_gnt_to_inter;
+
+ibex_top #(
+    .PMPEnable        (1'b0),
+    .RV32E            (1'b0),    //None
+    .RV32M            (2),       //RV32MFast
+    .RV32B            (0),       //RV32BNone
+    .RV32Zk           (2),       //RV32Zkn
+    .DmHaltAddr       (32'h00000000),
+    .DmExceptionAddr  (32'h00000000)
+) ibex_core_1 (
+    .clk_i (clk_i),
+    .rst_ni(reset_ni),
+
+    .test_en_i(1'b1),
+    .ram_cfg_i(1'b0),  // not in use
+
+    .hart_id_i  (32'd0),
+    .boot_addr_i(32'h00000000),
+
+    .instr_req_o(       master_data_req_to_inter_ro[0]),
+    .instr_gnt_i(       master_data_gnt_to_inter_ro[0]),
+    .instr_rvalid_i(    master_data_rvalid_to_inter_ro[0]),
+    .instr_addr_o(      master_data_addr_to_inter_ro[  ROMASTER_ADDR_WIDTH - 1 : 0]),
+    .instr_rdata_i(     master_data_rdata_to_inter_ro[ 31: 0 ]),
+    .instr_rdata_intg_i(7'd0),
+    .instr_err_i(       1'b0),
+
+    .data_req_o(        master_data_req_to_inter[0]),
+    .data_gnt_i(        master_data_gnt_to_inter[0]),
+    .data_rvalid_i(     master_data_rvalid_to_inter[0]),
+    .data_we_o(         master_data_we_to_inter[0]),
+    .data_be_o(         master_data_be_to_inter[   (32 / 8)   - 1 : 0]),
+    .data_addr_o(       master_data_addr_to_inter[ ADDR_WIDTH - 1 : 0]),
+    .data_wdata_o(      master_data_wdata_to_inter[31: 0]),
+    .data_wdata_intg_o(),
+    .data_rdata_i(      master_data_rdata_to_inter[31: 0]),
+    .data_rdata_intg_i(7'd0),
+    .data_err_i(       1'b0),
+
+    .eFPGA_operand_a_o(    eFPGA_operand_a_1_o   ),
+    .eFPGA_operand_b_o(    eFPGA_operand_b_1_o   ),
+    .eFPGA_result_a_i(     eFPGA_result_a_1_i    ),
+    .eFPGA_result_b_i(     eFPGA_result_b_1_i    ),
+    .eFPGA_result_c_i(     eFPGA_result_c_1_i    ),
+    .eFPGA_write_strobe_o( eFPGA_write_strobe_1_o),
+    .eFPGA_fpga_done_i(    eFPGA_fpga_done_1_i   ),
+    .eFPGA_en_o(           eFPGA_en_1_o          ),
+    .eFPGA_operator_o(     eFPGA_operator_1_o    ),
+    .eFPGA_delay_o(        eFPGA_delay_1_o       ),
+
+    .debug_req_i(debug_req_1_i),
+    .crash_dump_o(),
+
+    .fetch_enable_i(fetch_enable_1_i),
+    .alert_minor_o         (),
+    .alert_major_o         (),
+    .core_sleep_o          (),
+
+    // Interrupt inputs
+    .irq_software_i( 1'b0  ),
+    .irq_timer_i(    1'b0  ),
+    .irq_external_i(irq_1_i),
+    .irq_fast_i(    15'd0  ),
+    .irq_nm_i(       1'b0  ),      // non-maskeable interrupt
+
+    .scan_rst_ni(    1'b1  )    //unactivated
+);
+
+wire [ADDR_WIDTH-1:0] flexbex_addr_o;
+//need to set the debug vector
+flexbex_ibex_core ibex_core_2 (
+    .boot_addr_i(32'h0),
+    .clk_i(clk_i),
+    .cluster_id_i(6'd0),
+    .core_id_i(4'd1),
+
+    .data_addr_o(   flexbex_addr_o),
+    .data_be_o(     master_data_be_to_inter[ (  (2 * (32 / 8)))  - 1 : 1 * (32 / 8)]),
+    .data_err_i(    1'b0),
+    .data_gnt_i(    master_data_gnt_to_inter[1]),
+    .data_rdata_i(  master_data_rdata_to_inter[ (2 *  32)        - 1 : 1 *  32]),
+    .data_req_o(    master_data_req_to_inter[1]),
+    .data_rvalid_i( master_data_rvalid_to_inter[1]),
+    .data_wdata_o(  master_data_wdata_to_inter[ (2 *  32)        - 1 : 1 *  32]),
+    .data_we_o(     master_data_we_to_inter[1]),
+
+    .debug_req_i(         debug_req_2_i),
+    .ext_perf_counters_i( 1'b0 ),
+    .fetch_enable_i(      fetch_enable_2_i),
+
+    .instr_addr_o(  master_data_addr_to_inter_ro[ (2 * ROMASTER_ADDR_WIDTH) - 1 : ROMASTER_ADDR_WIDTH]),
+    .instr_gnt_i(   master_data_gnt_to_inter_ro[1]),
+    .instr_rdata_i( master_data_rdata_to_inter_ro[(2 * 32)       - 1 : 1 * 32 ]),
+    .instr_req_o(   master_data_req_to_inter_ro[1]),
+    .instr_rvalid_i(master_data_rvalid_to_inter_ro[1]),
+
+    .irq_ack_o(     irq_ack_2_o),
+    .irq_i(         irq_2_i),
+    .irq_id_i(      irq_id_2_i),
+    .irq_id_o(      irq_id_2_o),
+    .rst_ni(        reset_ni),
+    .test_en_i(     1'b1    ),
+    .eFPGA_operand_a_o(     eFPGA_operand_a_2_o),
+    .eFPGA_operand_b_o(     eFPGA_operand_b_2_o),
+    .eFPGA_result_a_i(      eFPGA_result_a_2_i),
+    .eFPGA_result_b_i(      eFPGA_result_b_2_i),
+    .eFPGA_result_c_i(      eFPGA_result_c_2_i),
+    .eFPGA_write_strobe_o(  eFPGA_write_strobe_2_o),
+    .eFPGA_fpga_done_i(     eFPGA_fpga_done_2_i),
+    .eFPGA_en_o(            eFPGA_en_2_o),
+    .eFPGA_operator_o(      eFPGA_operator_2_o),
+    .eFPGA_delay_o(         eFPGA_delay_2_o)
+);
+
+assign master_data_addr_to_inter[  (2 * ADDR_WIDTH) - 1 : 1 * ADDR_WIDTH]= {flexbex_addr_o[ADDR_WIDTH-1:2], 2'b00};
+// Intructions read only interconnection
+
+    wire [ ROMASTERS - 1:0] master_data_req_to_inter_ro;
+    wire [(ROMASTERS * ROMASTER_ADDR_WIDTH) - 1:0] master_data_addr_to_inter_ro;
+    wire [(ROMASTERS * 32) - 1:0] master_data_rdata_to_inter_ro;
+    wire [ ROMASTERS - 1:0] master_data_rvalid_to_inter_ro;
+    wire [ ROMASTERS - 1:0] master_data_gnt_to_inter_ro;
+
+    wire [ ROSLAVES - 1:0] slave_data_req_to_inter_ro;
+    wire [(ROSLAVES * SLAVE_ADDR_WIDTH) - 1:0] slave_data_addr_to_inter_ro;
+    wire [(ROSLAVES * 32) - 1:0] slave_data_rdata_to_inter_ro;
+
+inter_read inter_read_i
+(
+    .clk(clk_i),
+    .reset(reset),
+    .master_data_req_i(master_data_req_to_inter_ro),
+    .master_data_addr_i(master_data_addr_to_inter_ro),
+    .master_data_rdata_o(master_data_rdata_to_inter_ro),
+    .master_data_rvalid_o(master_data_rvalid_to_inter_ro),
+    .master_data_gnt_o(master_data_gnt_to_inter_ro),
+    .slave_data_req_o(slave_data_req_to_inter_ro), //active low
+    .slave_data_addr_o(slave_data_addr_to_inter_ro),
+    .slave_data_rdata_i(slave_data_rdata_to_inter_ro),
+    .slave_data_gnt_i(2'd3)
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 sram_1_i(
+//sram sram_1_i(
+// Port 0: RW
+    .clk0(clk_i),
+    .csb0(!slave_data_req_to_inter[0]),
+    .web0(!slave_data_we_to_inter[0]),
+    .wmask0(slave_data_be_to_inter[( ((32 / 8))) - 1 :0]),
+    .addr0(slave_data_addr_to_inter[ (SLAVE_ADDR_WIDTH) - 1 : 0]),
+    .din0(slave_data_wdata_to_inter[  31 : 0 ]),
+    .dout0(slave_data_rdata_to_inter[ 31 : 0 ]),
+// Port 1: R
+    .clk1(clk_i),
+    .csb1(!slave_data_req_to_inter_ro[0]),
+    .addr1(slave_data_addr_to_inter_ro[(SLAVE_ADDR_WIDTH) - 1 : 0]),
+    .dout1(slave_data_rdata_to_inter_ro[31 : 0])
+  );
+
+//use sram module name
+sky130_sram_1kbyte_1rw1r_32x256_8 sram_2_i(
+//sram sram_2_i(
+// Port 0: RW
+    .clk0(clk_i),
+    .csb0(!slave_data_req_to_inter[1]),
+    .web0(!slave_data_we_to_inter[1]),
+    .wmask0(slave_data_be_to_inter[( (2 * (32 / 8))) - 1 : ((32 / 8))]),
+    .addr0(slave_data_addr_to_inter[ (2 * SLAVE_ADDR_WIDTH) - 1 : SLAVE_ADDR_WIDTH]),
+    .din0(slave_data_wdata_to_inter[ (2 * 32) - 1 : 32 ]),
+    .dout0(slave_data_rdata_to_inter[ (2 * 32) - 1 : 32 ]),
+// Port 1: R
+    .clk1(clk_i),
+    .csb1(!slave_data_req_to_inter_ro[1]),
+    .addr1(slave_data_addr_to_inter_ro[(2 * SLAVE_ADDR_WIDTH) - 1 : SLAVE_ADDR_WIDTH]),
+    .dout1(slave_data_rdata_to_inter_ro[ (2 * 32) - 1 : 32 ])
+  );
+
+
+// Read/Write interconnection (Memory and Peripherals)
+    assign master_data_addr_to_inter[  (3 * ADDR_WIDTH) - 1: 2 * ADDR_WIDTH ] = wbs_adr_i[ADDR_WIDTH - 1:0];
+    assign master_data_wdata_to_inter[ (3 * 32) - 1        : 2 * 32]          = wbs_dat_i;
+    assign master_data_be_to_inter[  ( (3 * (32 / 8))) - 1 : 2 * (32 / 8)]    = wbs_sel_i;
+    assign master_data_req_to_inter[2]                                        = wbs_stb_i & wbs_cyc_i;
+    assign master_data_we_to_inter[2]                                         = wbs_we_i;
+    assign wbs_dat_o = master_data_rdata_to_inter[ (3 * 32) - 1 : 2 * 32];
+    assign wbs_ack_o = master_data_gnt_to_inter[2] & master_data_rvalid_to_inter[2];     //todo check ack
+
+
+uart_to_mem #(
+     .ADDR_WIDTH(ADDR_WIDTH)
+) uart_to_mem_i (
+    .clk_i(clk_i), // The master clock for this module
+    .rst_i(reset), // Synchronous reset.
+    .rx_i(rxd_uart_to_mem), // Incoming serial line
+    .tx_o(txd_uart_to_mem),  // Outgoing serial line
+    .data_req_o(master_data_req_to_inter[3]),//Request ready, must stay high until data_gnt_i is high for one cycle
+    .data_addr_o(master_data_addr_to_inter[   (4 * ADDR_WIDTH) - 1: 3 * ADDR_WIDTH ]),//Address
+    .data_we_o(master_data_we_to_inter[3] ),                                          //Write Enable, high for writes, low for reads. Sent together with data_req_o
+    .data_be_o(master_data_be_to_inter[     ( (4 * (32 / 8)))  - 1: 3 * (32 / 8)]),   //Byte Enable. Is set for the bytes to write/read, sent together with data_req_o
+    .data_wdata_o(master_data_wdata_to_inter[ (4 *  32)        - 1: 3 *  32 ]),       //Data to be written to memory, sent together with data_req_o
+    .data_rdata_i(master_data_rdata_to_inter[ (4 *  32)        - 1: 3 *  32 ]),       //Data read from memory
+    .data_rvalid_i(master_data_rvalid_to_inter[3]),//data_rdata_is holds valid data when data_rvalid_i is high. This signal will be high for exactly one cycle per request.
+    .data_gnt_i(master_data_gnt_to_inter[3]),//The other side accepted the request. data_addr_o may change in the next cycle
+    .uart_error(error_uart_to_mem)
+);
+
+    wire                 slave_data_gnt_peri1_i;
+    wire [SLAVES - 1:0]  slave_data_rvalid;
+    reg  [SLAVES - 1:0]  slave_data_rvalid_write;
+    reg  [SLAVES - 1:0]  slave_data_rvalid_read;
+
+inter #(
+    .DATA_WIDTH(32),
+    .MASTERS(4),
+    .SLAVES(3)
+) inter_i (
+    .clk(clk_i),
+    .reset(reset),
+    .master_data_req_i(master_data_req_to_inter),
+    .master_data_addr_i(master_data_addr_to_inter),
+    .master_data_we_i(master_data_we_to_inter),
+    .master_data_be_i(master_data_be_to_inter),
+    .master_data_wdata_i(master_data_wdata_to_inter),
+    .master_data_rdata_o(master_data_rdata_to_inter),
+    .master_data_rvalid_o(master_data_rvalid_to_inter),
+    .master_data_gnt_o(master_data_gnt_to_inter),
+    .slave_data_req_o(slave_data_req_to_inter),
+    .slave_data_addr_o(slave_data_addr_to_inter),
+    .slave_data_we_o(slave_data_we_to_inter),
+    .slave_data_be_o(slave_data_be_to_inter),
+    .slave_data_wdata_o(slave_data_wdata_to_inter),
+    .slave_data_rdata_i(slave_data_rdata_to_inter),
+    .slave_data_rvalid_i(slave_data_rvalid),
+    .slave_data_gnt_i({ slave_data_gnt_peri1_i,2'd3})
+);
+
+assign slave_data_rvalid[0] = slave_data_rvalid_write[0] | slave_data_rvalid_read[0];
+assign slave_data_rvalid[1] = slave_data_rvalid_write[1] | slave_data_rvalid_read[1];
+assign slave_data_rvalid[2] = slave_data_rvalid_write[2] | slave_data_rvalid_read[2];
+
+wire slave_data_rvalid_peri1_i;
+wire [SLAVES - 1:0]slave_data_rvalid_source = {slave_data_rvalid_peri1_i, 2'd3};
+
+//for sram interfaces rvalid should be high following gnt(1) + we_o(0)
+genvar i;
+
+generate
+    for (i = 0; i < SLAVES; i = i + 1) begin
+        always @(posedge clk_i)
+        begin
+            if(reset == 1)
+                slave_data_rvalid_read[i] = 0;
+            else if(slave_data_req_to_inter[i] == 1'b1 && slave_data_we_to_inter[i] == 1'b0)
+                slave_data_rvalid_read[i] = slave_data_rvalid_source[i];
+            else
+                slave_data_rvalid_read[i] = 0;
+        end
+    end
+endgenerate
+genvar j;
+generate
+    for (j = 0; j < SLAVES; j = j + 1) begin
+        always @(posedge clk_i)
+        begin
+            if(reset == 1)
+                slave_data_rvalid_write[j] = 0;
+            else if(slave_data_req_to_inter[j] == 1'b1 && slave_data_we_to_inter[j] == 1'b1)
+                slave_data_rvalid_write[j] = slave_data_rvalid_source[j];
+            else
+                slave_data_rvalid_write[j] = 0;
+        end
+    end
+endgenerate
+
+peripheral #(
+    .DATA_WIDTH(32),
+    .ADDR_WIDTH(SLAVE_ADDR_WIDTH)
+) peripheral1 (
+    .clk(clk_i),
+    .reset(reset),
+    .slave_data_addr_i(slave_data_addr_to_inter[ (  3 * SLAVE_ADDR_WIDTH) - 1 : 2 * SLAVE_ADDR_WIDTH]),
+    .slave_data_we_i(slave_data_we_to_inter[2]),
+    .slave_data_be_i(slave_data_be_to_inter[(      (3 * (32 / 8))) - 1 : 2 * ((32 / 8))]),
+    .slave_data_wdata_i(slave_data_wdata_to_inter[ (3 *  32) - 1 : 2 * 32 ]),
+    .slave_data_rdata_o(slave_data_rdata_to_inter[ (3 *  32) - 1 : 2 * 32 ]),
+    .slave_data_rvalid_o(slave_data_rvalid_peri1_i),
+    .slave_data_gnt_o(slave_data_gnt_peri1_i),
+    .data_req_i(slave_data_req_to_inter[2]),
+    .rxd_uart(rxd_uart),
+    .txd_uart(txd_uart)
+);
+
+endmodule
diff --git a/verilog/rtl/icesoc/inter.v b/verilog/rtl/icesoc/inter.v
new file mode 100644
index 0000000..3aa2b09
--- /dev/null
+++ b/verilog/rtl/icesoc/inter.v
@@ -0,0 +1,204 @@
+`timescale 1 ps / 1 ps
+
+module inter #(
+        parameter DATA_WIDTH = 32,
+        parameter MASTER_ADDR_WIDTH = 12,
+        parameter SLAVE_ADDR_WIDTH = 10,
+        parameter MASTERS = 4,
+        parameter SLAVES = 3,
+        parameter [SLAVES * MASTER_ADDR_WIDTH - 1 :0] MASTER_ADDR_MATCH   = {12'h800, 12'h400, 12'h0},
+        parameter [SLAVES * MASTER_ADDR_WIDTH - 1 :0] MASTER_ADDR_MASK = { 12'hC00, 12'hC00, 12'hC00}
+)(
+        clk,
+        reset,
+        master_data_req_i,
+        master_data_addr_i,
+        master_data_we_i,
+        master_data_be_i,
+        master_data_wdata_i,
+        master_data_rdata_o,
+        master_data_rvalid_o,
+        master_data_gnt_o,
+        slave_data_req_o,
+        slave_data_addr_o,
+        slave_data_we_o,
+        slave_data_be_o,
+        slave_data_wdata_o,
+        slave_data_rdata_i,
+        slave_data_rvalid_i,
+        slave_data_gnt_i
+);
+
+        input clk;
+        input reset;
+        input wire [MASTERS - 1:0] master_data_req_i;
+        input wire [(MASTERS * MASTER_ADDR_WIDTH) - 1:0] master_data_addr_i;
+        input wire [MASTERS - 1:0] master_data_we_i;
+        input wire [(MASTERS * (DATA_WIDTH / 8)) - 1:0] master_data_be_i;
+        input wire [(MASTERS * DATA_WIDTH) - 1:0] master_data_wdata_i;
+        output reg [(MASTERS * DATA_WIDTH) - 1:0] master_data_rdata_o;
+        output reg [MASTERS - 1:0] master_data_rvalid_o;
+        output reg [MASTERS - 1:0] master_data_gnt_o;
+        output reg [SLAVES - 1:0] slave_data_req_o;
+        output reg [(SLAVES * SLAVE_ADDR_WIDTH) - 1:0] slave_data_addr_o;
+        output reg [SLAVES - 1:0] slave_data_we_o;
+        output reg [(SLAVES * (DATA_WIDTH / 8)) - 1:0] slave_data_be_o;
+        output reg [(SLAVES * DATA_WIDTH) - 1:0] slave_data_wdata_o;
+        input wire [(SLAVES * DATA_WIDTH) - 1:0] slave_data_rdata_i;
+        input wire [SLAVES - 1:0] slave_data_rvalid_i;
+        input wire [SLAVES - 1:0] slave_data_gnt_i;
+        reg arb_to_master_grant [MASTERS - 1:0];
+     //   wire arb_active;
+        genvar i;
+        //genvar j;
+        logic [(SLAVES * MASTERS) - 1:0] arbiter_request;
+        wire [(SLAVES * MASTERS) - 1:0] arbiter_grant;
+       //parameter [$clog2(SLAVES):0] PARAM_SLAVE_ADDR = 2'b10;
+      
+                for (i = 0; i < SLAVES; i = i + 1)  
+                always @(*)
+                begin
+                        for (int j = 0; j < MASTERS; j = j + 1)
+                               arbiter_request[(i * MASTERS) + j] = (( master_data_addr_i[ j * MASTER_ADDR_WIDTH +: MASTER_ADDR_WIDTH ] & MASTER_ADDR_MASK[ i * MASTER_ADDR_WIDTH +: MASTER_ADDR_WIDTH ]) ==  MASTER_ADDR_MATCH[ i * MASTER_ADDR_WIDTH +: MASTER_ADDR_WIDTH ] )? master_data_req_i[j] : 0;
+                end
+                for (i = 0; i < MASTERS; i = i + 1)
+                        begin : sv2v_autoblock_1
+                           always @(*)begin
+                                reg local_arb_grant;
+                                local_arb_grant = 1'b0;
+                                begin : sv2v_autoblock_2
+                                        reg signed [31:0] j;
+                                        for (int j = 0; j < SLAVES; j = j + 1)
+                                                local_arb_grant = local_arb_grant | arbiter_grant[(j * MASTERS) + i];
+                                end
+                                arb_to_master_grant[i] = local_arb_grant;
+                           end
+                        end
+
+                        
+        generate
+                for (i = 0; i < SLAVES; i = i + 1) begin : generate_arbiters
+                        arbiter #(.NUM_PORTS(MASTERS)) i_arb(
+                                .clk(clk),
+                                .rst(reset),
+                                .request(arbiter_request[(i * MASTERS) + (MASTERS - 1)-:MASTERS]),
+                                .grant(arbiter_grant[(i * MASTERS) + (MASTERS - 1)-:MASTERS])
+                     
+                        );
+                end
+        endgenerate
+        genvar a,t;
+         
+         generate
+                 for ( a = 0; a < SLAVES; a = a + 1)
+                        begin : slave_out1
+                          
+                                always @(*)
+                                begin 
+                                        
+                                        slave_data_addr_o[a * SLAVE_ADDR_WIDTH+:SLAVE_ADDR_WIDTH] = 0;
+                                        slave_data_we_o[a] = 0;
+                                        slave_data_be_o[a * (DATA_WIDTH / 8)+:DATA_WIDTH / 8] = 0;
+                                        slave_data_wdata_o[a * DATA_WIDTH+:DATA_WIDTH] = 0;
+                                        slave_data_req_o[a] = 0;
+                                        for (int  t = 0; t < MASTERS; t = t + 1)
+                                        begin : slave_out2
+                                                
+                                
+                                                if (arbiter_grant[(a*MASTERS) + t] == 1'b1) begin : slave_out
+                                                        slave_data_addr_o[a * SLAVE_ADDR_WIDTH+:SLAVE_ADDR_WIDTH] = master_data_addr_i[t * MASTER_ADDR_WIDTH+:SLAVE_ADDR_WIDTH];
+                                                        slave_data_we_o[a] = master_data_we_i[t];
+                                                        slave_data_be_o[a * (DATA_WIDTH / 8)+:DATA_WIDTH / 8] = master_data_be_i[t * (DATA_WIDTH / 8)+:DATA_WIDTH / 8];
+                                                        slave_data_wdata_o[a * DATA_WIDTH+:DATA_WIDTH] = master_data_wdata_i[t * DATA_WIDTH+:DATA_WIDTH];
+                                                        //need to fix
+                                                        slave_data_req_o[a] = master_data_req_i[t];
+                                                end
+                                        end
+                                end
+                             
+
+                        end
+         endgenerate
+        
+        generate
+        for (i = 0; i < MASTERS; i = i + 1)
+                begin :m_data1
+                        always @(*)                       
+                        begin :m_data2
+                                master_data_rdata_o[i * DATA_WIDTH+:DATA_WIDTH] = 0;
+                                master_data_rvalid_o[i] = 0;
+                                master_data_gnt_o[i] = 0;
+                                for (int k = 0; k < SLAVES; k = k + 1)
+                                begin
+                                        if (arbiter_grant[(k * MASTERS) + i] == 1'b1) 
+                                        begin 
+                                                master_data_rdata_o[i * DATA_WIDTH+:DATA_WIDTH] = slave_data_rdata_i[k * DATA_WIDTH+:DATA_WIDTH];
+                                                master_data_rvalid_o[i] = slave_data_rvalid_i[k];
+                                                master_data_gnt_o[i] = slave_data_gnt_i[k] & master_data_req_i[i] ;
+                                        end
+                                end
+                        end
+                end
+        endgenerate
+endmodule
+
+
+module arbiter     #(
+    parameter NUM_PORTS=5
+    )(
+	clk,
+	rst,
+	request,
+	grant
+	//active
+);
+	parameter SEL_WIDTH = (NUM_PORTS > 1 ? $clog2(NUM_PORTS) : 1);
+	input clk;
+	input rst;
+	input [NUM_PORTS - 1:0] request;
+	output reg [NUM_PORTS - 1:0] grant;
+	
+	//output reg active;
+	localparam WRAP_LENGTH = 2 * NUM_PORTS;
+	function [SEL_WIDTH - 1:0] ff1;
+		input [NUM_PORTS - 1:0] in;
+		reg set;
+		integer i;
+		begin
+			set = 1'b0;
+			ff1 = 'b0;
+			for (i = 0; i < NUM_PORTS; i = i + 1)
+				if (in[i] & ~set) begin
+					set = 1'b1;
+					ff1 = i[0+:SEL_WIDTH];
+				end
+		end
+	endfunction
+	integer yy;
+	wire next;
+	wire [NUM_PORTS - 1:0] order;
+	reg [NUM_PORTS - 1:0] token;
+	wire [NUM_PORTS - 1:0] token_lookahead [NUM_PORTS - 1:0];
+	wire [WRAP_LENGTH - 1:0] token_wrap;
+	assign token_wrap = {token, token};
+	assign next = ~|(token & request);
+	always @(posedge clk) grant <= token & request;
+
+	//always @(posedge clk) active <= |(token & request);
+	always @(posedge clk)
+		if (rst)
+			token <= 'b1;
+		else if (next)
+			for (yy = 0; yy < NUM_PORTS; yy = yy + 1)
+				begin : TOKEN_
+					if (order[yy])
+						token <= token_lookahead[yy];
+				end
+	genvar xx;
+	generate
+		for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
+			assign token_lookahead[xx] = token_wrap[xx+:NUM_PORTS];
+			assign order[xx] = |(token_lookahead[xx] & request);
+		end
+	endgenerate
+endmodule
diff --git a/verilog/rtl/icesoc/inter_read.v b/verilog/rtl/icesoc/inter_read.v
new file mode 100644
index 0000000..3fedbf8
--- /dev/null
+++ b/verilog/rtl/icesoc/inter_read.v
@@ -0,0 +1,89 @@
+module inter_read (
+	clk,
+	reset,
+	master_data_req_i,
+	master_data_addr_i,
+	master_data_rdata_o,
+	master_data_rvalid_o,
+	master_data_gnt_o,
+	slave_data_req_o,
+	slave_data_addr_o,
+	slave_data_rdata_i,
+	slave_data_gnt_i
+);
+	parameter DATA_WIDTH = 32;
+	parameter M_ADDR_WIDTH = 11;
+	parameter S_ADDR_WIDTH = 10;
+	parameter ROMASTERS = 2;
+	parameter ROSLAVES = 2;
+	parameter [(ROSLAVES * M_ADDR_WIDTH) - 1:0] M_ADDR_MATCH = 22'h200000;
+	parameter [(ROSLAVES * M_ADDR_WIDTH) - 1:0] M_ADDR_MASK = 22'h200400;
+	input clk;
+	input reset;
+	input wire [ROMASTERS - 1:0] master_data_req_i;
+	input wire [(ROMASTERS * M_ADDR_WIDTH) - 1:0] master_data_addr_i;
+	output reg [(ROMASTERS * DATA_WIDTH) - 1:0] master_data_rdata_o;
+	output reg [ROMASTERS - 1:0] master_data_rvalid_o;
+	output reg [ROMASTERS - 1:0] master_data_gnt_o;
+	output reg [ROSLAVES - 1:0] slave_data_req_o;
+	output reg [(ROSLAVES * S_ADDR_WIDTH) - 1:0] slave_data_addr_o;
+	input wire [(ROSLAVES * DATA_WIDTH) - 1:0] slave_data_rdata_i;
+	input wire [ROSLAVES - 1:0] slave_data_gnt_i;
+	genvar i;
+	reg [(ROSLAVES * ROMASTERS) - 1:0] arbiter_request;
+	wire [(ROSLAVES * ROMASTERS) - 1:0] arbiter_grant;
+	generate
+		for (i = 0; i < ROSLAVES; i = i + 1) begin : gen_slave_arbiter
+			always @(*) begin : sv2v_autoblock_1
+				reg signed [31:0] j;
+				for (j = 0; j < ROMASTERS; j = j + 1)
+					arbiter_request[(i * ROMASTERS) + j] = ((master_data_addr_i[j * M_ADDR_WIDTH+:M_ADDR_WIDTH] & M_ADDR_MASK[i * M_ADDR_WIDTH+:M_ADDR_WIDTH]) == M_ADDR_MATCH[i * M_ADDR_WIDTH+:M_ADDR_WIDTH] ? master_data_req_i[j] : 0);
+			end
+		end
+		for (i = 0; i < ROSLAVES; i = i + 1) begin : generate_arbiters
+			arbiter #(.NUM_PORTS(ROMASTERS)) i_arb(
+				.clk(clk),
+				.rst(reset),
+				.request(arbiter_request[(i * ROMASTERS) + (ROMASTERS - 1)-:ROMASTERS]),
+				.grant(arbiter_grant[(i * ROMASTERS) + (ROMASTERS - 1)-:ROMASTERS])
+			);
+		end
+	endgenerate
+	genvar a;
+	generate
+		for (a = 0; a < ROSLAVES; a = a + 1) begin : slave_out1
+			always @(*) begin
+				slave_data_addr_o[a * S_ADDR_WIDTH+:S_ADDR_WIDTH] = 0;
+				slave_data_req_o[a] = 0;
+				begin : sv2v_autoblock_2
+					reg signed [31:0] t;
+					for (t = 0; t < ROMASTERS; t = t + 1)
+						if (arbiter_grant[(a * ROMASTERS) + t] == 1'b1) begin
+							slave_data_addr_o[a * S_ADDR_WIDTH+:S_ADDR_WIDTH] = master_data_addr_i[t * M_ADDR_WIDTH+:S_ADDR_WIDTH];
+							slave_data_req_o[a] = master_data_req_i[t];
+						end
+				end
+			end
+		end
+	endgenerate
+	reg [ROMASTERS - 1:0] master_data_rvalid;
+	generate
+		for (i = 0; i < ROMASTERS; i = i + 1) begin : m_data1
+			always @(*) begin
+				master_data_rdata_o[i * DATA_WIDTH+:DATA_WIDTH] = 0;
+				master_data_gnt_o[i] = 0;
+                                master_data_rvalid[i] = 0;
+				begin : sv2v_autoblock_3
+					reg signed [31:0] j;
+					for (j = 0; j < ROSLAVES; j = j + 1)
+						if (arbiter_grant[(j * ROMASTERS) + i] == 1'b1) begin
+							master_data_rdata_o[i * DATA_WIDTH+:DATA_WIDTH] = slave_data_rdata_i[j * DATA_WIDTH+:DATA_WIDTH];
+							master_data_gnt_o[i] = ((slave_data_gnt_i[j] & master_data_req_i[i]) & arbiter_grant[(j * ROMASTERS) + i+:1]) & arbiter_request[(j * ROMASTERS) + i+:1];
+							master_data_rvalid[i] = master_data_gnt_o[i];
+						end
+				end
+			end
+		end
+	endgenerate
+	always @(posedge clk) master_data_rvalid_o = master_data_rvalid;
+endmodule
diff --git a/verilog/rtl/icesoc/peripheral.v b/verilog/rtl/icesoc/peripheral.v
new file mode 100644
index 0000000..ee1a51d
--- /dev/null
+++ b/verilog/rtl/icesoc/peripheral.v
@@ -0,0 +1,110 @@
+module peripheral (
+	clk,
+	reset,
+	slave_data_addr_i,
+	slave_data_we_i,
+	slave_data_be_i,
+	slave_data_wdata_i,
+	slave_data_rdata_o,
+	slave_data_rvalid_o,
+	slave_data_gnt_o,
+	data_req_i,
+	rxd_uart,
+	txd_uart
+);
+	parameter DATA_WIDTH = 32;
+	parameter ADDR_WIDTH = 10;
+	input clk;
+	input reset;
+	input wire [ADDR_WIDTH - 1:0] slave_data_addr_i;
+	input wire slave_data_we_i;
+	input wire [(DATA_WIDTH / 8) - 1:0] slave_data_be_i;
+	input wire [DATA_WIDTH - 1:0] slave_data_wdata_i;
+	output reg [DATA_WIDTH - 1:0] slave_data_rdata_o;
+	output reg slave_data_rvalid_o;
+	output reg slave_data_gnt_o;
+	input wire data_req_i;
+	input wire rxd_uart;
+	output wire txd_uart;
+	localparam tdataaddress = 2'b00;
+	reg [7:0] s_axis_tdata_uart;
+	reg s_axis_tvalid_uart;
+	wire s_axis_tready_uart;
+	reg [7:0] m_axis_tdata_uart;
+	wire m_axis_tvalid_uart;
+	reg m_axis_tready_uart;
+	wire tx_busy_uart;
+	wire rx_busy_uart;
+	wire rx_overrun_error_uart;
+	wire rx_frame_error_uart;
+	reg [22:0] configuration;
+	always @(posedge clk) begin : setregister
+		if (reset) begin
+			slave_data_rvalid_o <= 0;
+			slave_data_gnt_o <= 0;
+			slave_data_rdata_o <= 0;
+			s_axis_tdata_uart <= 0;
+			s_axis_tvalid_uart <= 0;
+			configuration[22:0] <= 0;
+		end
+		else if (data_req_i == 1) begin
+			slave_data_gnt_o <= 1;
+			slave_data_rvalid_o <= 1;
+			if (slave_data_addr_i[2:0] == 3'h0) begin
+				if (slave_data_we_i == 1'b1) begin
+					if (s_axis_tready_uart == 1'b1) begin
+						s_axis_tdata_uart <= slave_data_wdata_i[7:0];
+						s_axis_tvalid_uart <= 1;
+					end
+				end
+				else begin
+					slave_data_rdata_o[7:0] <= m_axis_tdata_uart;
+					configuration[22] <= 0;
+				end
+			end
+			else if (slave_data_addr_i[2:0] == 3'h4)
+				if (slave_data_we_i == 1'b1) begin
+					configuration[15:0] <= slave_data_wdata_i[15:0];
+					configuration[22] <= slave_data_wdata_i[22];
+				end
+				else
+					slave_data_rdata_o[21:0] <= configuration[21:0];
+		end
+		else begin
+			slave_data_rvalid_o <= 0;
+			slave_data_gnt_o <= 0;
+			s_axis_tvalid_uart <= 0;
+			configuration[16] <= rx_frame_error_uart;
+			configuration[17] <= rx_overrun_error_uart;
+			configuration[18] <= rx_busy_uart;
+			configuration[19] <= tx_busy_uart;
+			configuration[20] <= s_axis_tready_uart;
+			if (configuration[21] == 1'b0)
+				configuration[21] <= m_axis_tvalid_uart;
+			else if ((configuration[22] == 1) && (configuration[21] == 1'b1))
+				configuration[21] <= 1'b0;
+		end
+	end
+	reg [7:0] uart_data_recv;
+	always @(posedge clk) begin : uart_data
+		if (m_axis_tvalid_uart)
+			uart_data_recv <= m_axis_tdata_uart;
+	end
+	axi_uart axi_uart_i(
+		.clk(clk),
+		.rst(reset),
+		.s_axis_tdata(s_axis_tdata_uart),
+		.s_axis_tvalid(s_axis_tvalid_uart),
+		.s_axis_tready(s_axis_tready_uart),
+		.m_axis_tdata(m_axis_tdata_uart),
+		.m_axis_tvalid(m_axis_tvalid_uart),
+		.m_axis_tready(1'b1),
+		.rxd(rxd_uart),
+		.txd(txd_uart),
+		.tx_busy(tx_busy_uart),
+		.rx_busy(rx_busy_uart),
+		.rx_overrun_error(rx_overrun_error_uart),
+		.rx_frame_error(rx_frame_error_uart),
+		.prescale(configuration[15:0])
+	);
+endmodule
diff --git a/verilog/rtl/icesoc/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/icesoc/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100644
index 0000000..0be018f
--- /dev/null
+++ b/verilog/rtl/icesoc/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,143 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1 ps / 1 ps
+
+`default_nettype none
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+/*verilator no_inline_module*/
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 10 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+`ifdef USE_POWER_PINS
+  inout vdd;
+  inout gnd;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output  [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //dout0 = 32'bx;
+`ifdef DBG
+    if ( !csb0_reg && web0_reg )
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+`endif
+   end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+`ifdef DBG
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+         $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    dout1 = 32'bx;
+    if ( !csb1_reg )
+      $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+`endif
+   end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always_ff @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <=  mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always_ff @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <=  mem[addr1_reg];
+  end
+
+  function [31:0] readWord;
+    /* verilator public */
+    input integer word_addr;
+    readWord = mem[word_addr];
+  endfunction
+
+  task writeWord;
+    /* verilator public */
+    input integer word_addr;
+    input [31:0] val;
+   mem[word_addr] = val;
+  endtask
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/icesoc/uart.v b/verilog/rtl/icesoc/uart.v
new file mode 100644
index 0000000..f1095c2
--- /dev/null
+++ b/verilog/rtl/icesoc/uart.v
@@ -0,0 +1,128 @@
+module uart (
+	clk,
+	rst,
+	rx,
+	tx,
+	transmit,
+	tx_byte,
+	received,
+	rx_byte,
+	is_receiving,
+	is_transmitting,
+	recv_error
+);
+	input clk;
+	input rst;
+	input rx;
+	output wire tx;
+	input transmit;
+	input [7:0] tx_byte;
+	output wire received;
+	output wire [7:0] rx_byte;
+	output wire is_receiving;
+	output wire is_transmitting;
+	output wire recv_error;
+	parameter CLOCK_DIVIDE = 2;
+	parameter RX_IDLE = 0;
+	parameter RX_CHECK_START = 1;
+	parameter RX_READ_BITS = 2;
+	parameter RX_CHECK_STOP = 3;
+	parameter RX_DELAY_RESTART = 4;
+	parameter RX_ERROR = 5;
+	parameter RX_RECEIVED = 6;
+	parameter TX_IDLE = 0;
+	parameter TX_SENDING = 1;
+	parameter TX_DELAY_RESTART = 2;
+	reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
+	reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
+	reg [2:0] recv_state = RX_IDLE;
+	reg [5:0] rx_countdown;
+	reg [3:0] rx_bits_remaining;
+	reg [7:0] rx_data;
+	reg tx_out = 1'b1;
+	reg [1:0] tx_state = TX_IDLE;
+	reg [5:0] tx_countdown;
+	reg [3:0] tx_bits_remaining;
+	reg [7:0] tx_data;
+	assign received = recv_state == RX_RECEIVED;
+	assign recv_error = recv_state == RX_ERROR;
+	assign is_receiving = recv_state != RX_IDLE;
+	assign rx_byte = rx_data;
+	assign tx = tx_out;
+	assign is_transmitting = tx_state != TX_IDLE;
+	always @(posedge clk) begin
+		if (rst) begin
+			recv_state = RX_IDLE;
+			tx_state = TX_IDLE;
+		end
+		rx_clk_divider = rx_clk_divider - 1;
+		if (!rx_clk_divider) begin
+			rx_clk_divider = CLOCK_DIVIDE;
+			rx_countdown = rx_countdown - 1;
+		end
+		tx_clk_divider = tx_clk_divider - 1;
+		if (!tx_clk_divider) begin
+			tx_clk_divider = CLOCK_DIVIDE;
+			tx_countdown = tx_countdown - 1;
+		end
+		case (recv_state)
+			RX_IDLE:
+				if (!rx) begin
+					rx_clk_divider = CLOCK_DIVIDE;
+					rx_countdown = 2;
+					recv_state = RX_CHECK_START;
+				end
+			RX_CHECK_START:
+				if (!rx_countdown)
+					if (!rx) begin
+						rx_countdown = 4;
+						rx_bits_remaining = 8;
+						recv_state = RX_READ_BITS;
+					end
+					else
+						recv_state = RX_ERROR;
+			RX_READ_BITS:
+				if (!rx_countdown) begin
+					rx_data = {rx, rx_data[7:1]};
+					rx_countdown = 4;
+					rx_bits_remaining = rx_bits_remaining - 1;
+					recv_state = (rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP);
+				end
+			RX_CHECK_STOP:
+				if (!rx_countdown)
+					recv_state = (rx ? RX_RECEIVED : RX_ERROR);
+			RX_DELAY_RESTART: recv_state = (rx_countdown ? RX_DELAY_RESTART : RX_IDLE);
+			RX_ERROR: begin
+				rx_countdown = 8;
+				recv_state = RX_DELAY_RESTART;
+			end
+			RX_RECEIVED: recv_state = RX_IDLE;
+		endcase
+		case (tx_state)
+			TX_IDLE:
+				if (transmit) begin
+					tx_data = tx_byte;
+					tx_clk_divider = CLOCK_DIVIDE;
+					tx_countdown = 4;
+					tx_out = 0;
+					tx_bits_remaining = 8;
+					tx_state = TX_SENDING;
+				end
+			TX_SENDING:
+				if (!tx_countdown)
+					if (tx_bits_remaining) begin
+						tx_bits_remaining = tx_bits_remaining - 1;
+						tx_out = tx_data[0];
+						tx_data = {1'b0, tx_data[7:1]};
+						tx_countdown = 4;
+						tx_state = TX_SENDING;
+					end
+					else begin
+						tx_out = 1;
+						tx_countdown = 8;
+						tx_state = TX_DELAY_RESTART;
+					end
+			TX_DELAY_RESTART: tx_state = (tx_countdown ? TX_DELAY_RESTART : TX_IDLE);
+		endcase
+	end
+endmodule
diff --git a/verilog/rtl/icesoc/uart_rx.v b/verilog/rtl/icesoc/uart_rx.v
new file mode 100644
index 0000000..9c7985d
--- /dev/null
+++ b/verilog/rtl/icesoc/uart_rx.v
@@ -0,0 +1,142 @@
+/*
+
+Copyright (c) 2014-2017 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream UART
+ */
+module uart_rx #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
+    output wire                   m_axis_tvalid,
+    input  wire                   m_axis_tready,
+
+    /*
+     * UART interface
+     */
+    input  wire                   rxd,
+
+    /*
+     * Status
+     */
+    output wire                   busy,
+    output wire                   overrun_error,
+    output wire                   frame_error,
+
+    /*
+     * Configuration
+     */
+    input  wire [15:0]            prescale
+
+);
+
+reg [DATA_WIDTH-1:0] m_axis_tdata_reg = 0;
+reg m_axis_tvalid_reg = 0;
+
+reg rxd_reg = 1;
+
+reg busy_reg = 0;
+reg overrun_error_reg = 0;
+reg frame_error_reg = 0;
+
+reg [DATA_WIDTH-1:0] data_reg = 0;
+reg [18:0] prescale_reg = 0;
+reg [3:0] bit_cnt = 0;
+
+assign m_axis_tdata = m_axis_tdata_reg;
+assign m_axis_tvalid = m_axis_tvalid_reg;
+
+assign busy = busy_reg;
+assign overrun_error = overrun_error_reg;
+assign frame_error = frame_error_reg;
+
+always @(posedge clk) begin
+    if (rst) begin
+        m_axis_tdata_reg <= 0;
+        m_axis_tvalid_reg <= 0;
+        rxd_reg <= 1;
+        prescale_reg <= 0;
+        bit_cnt <= 0;
+        busy_reg <= 0;
+        overrun_error_reg <= 0;
+        frame_error_reg <= 0;
+    end else begin
+        rxd_reg <= rxd;
+        overrun_error_reg <= 0;
+        frame_error_reg <= 0;
+
+        if (m_axis_tvalid && m_axis_tready) begin
+            m_axis_tvalid_reg <= 0;
+        end
+
+        if (prescale_reg > 0) begin
+            prescale_reg <= prescale_reg - 1;
+        end else if (bit_cnt > 0) begin
+            if (bit_cnt > DATA_WIDTH+1) begin
+                if (!rxd_reg) begin
+                    bit_cnt <= bit_cnt - 1;
+                    prescale_reg <= (prescale << 3)-1;
+                end else begin
+                    bit_cnt <= 0;
+                    prescale_reg <= 0;
+                end
+            end else if (bit_cnt > 1) begin
+                bit_cnt <= bit_cnt - 1;
+                prescale_reg <= (prescale << 3)-1;
+                data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
+            end else if (bit_cnt == 1) begin
+                bit_cnt <= bit_cnt - 1;
+                if (rxd_reg) begin
+                    m_axis_tdata_reg <= data_reg;
+                    m_axis_tvalid_reg <= 1;
+                    overrun_error_reg <= m_axis_tvalid_reg;
+                end else begin
+                    frame_error_reg <= 1;
+                end
+            end
+        end else begin
+            busy_reg <= 0;
+            if (!rxd_reg) begin
+                prescale_reg <= (prescale << 2)-2;
+                bit_cnt <= DATA_WIDTH+2;
+                data_reg <= 0;
+                busy_reg <= 1;
+            end
+        end
+    end
+end
+
+endmodule
diff --git a/verilog/rtl/icesoc/uart_to_mem.v b/verilog/rtl/icesoc/uart_to_mem.v
new file mode 100644
index 0000000..dace924
--- /dev/null
+++ b/verilog/rtl/icesoc/uart_to_mem.v
@@ -0,0 +1,264 @@
+module uart_to_mem (
+	clk_i,
+	rst_i,
+	rx_i,
+	tx_o,
+	data_req_o,
+	data_addr_o,
+	data_we_o,
+	data_be_o,
+	data_wdata_o,
+	data_rdata_i,
+	data_rvalid_i,
+	data_gnt_i,
+	uart_error
+);
+	parameter ADDR_WIDTH = 12;
+	input clk_i;
+	input rst_i;
+	input rx_i;
+	output wire tx_o;
+	output reg data_req_o;
+	output wire [ADDR_WIDTH - 1:0] data_addr_o;
+	output reg data_we_o;
+	output wire [3:0] data_be_o;
+	output wire [31:0] data_wdata_o;
+	input [31:0] data_rdata_i;
+	input data_rvalid_i;
+	input data_gnt_i;
+	output wire uart_error;
+	assign data_be_o = 4'b1111;
+	wire transmit_i;
+	reg [7:0] tx_byte_i;
+	wire received_o;
+	wire [7:0] rx_byte_o;
+	wire is_receiving_o;
+	wire is_transmitting_o;
+	wire recv_error_o;
+	assign uart_error = recv_error_o;
+	parameter IDLE = 0;
+	parameter WAIT_ADDR_HEAD = 1;
+	parameter WAIT_ADDR_TAIL = 2;
+	parameter RECEIVE_WRITE_DATA = 3;
+	parameter SEND_READ_DATA = 4;
+	parameter PKT_ALIVE = 8'b00100000;
+	parameter PKT_WRITE_CMD = 8'b01000001;
+	parameter PKT_ADR = 8'b01100000;
+	parameter PKT_READ_CMD = 8'b01000010;
+	reg [2:0] UART_STATE;
+	reg [31:0] DATA;
+	reg [31:0] DATA_READ;
+	reg [ADDR_WIDTH - 1:0] MEMORY_ADDRESS;
+	assign data_wdata_o = DATA[31:0];
+	assign data_addr_o[ADDR_WIDTH - 1:0] = {MEMORY_ADDRESS[ADDR_WIDTH - 1:0]};
+	reg transmit;
+	reg trans_txn_ff2;
+	reg trans_txn_ff;
+	reg transmit_on_nontras;
+	assign transmit_i = transmit_on_nontras;
+	always @(posedge clk_i)
+		if (rst_i) begin
+			trans_txn_ff <= 1'b0;
+			trans_txn_ff2 <= 1'b0;
+			transmit_on_nontras <= 1'b0;
+		end
+		else begin
+			trans_txn_ff <= is_transmitting_o;
+			trans_txn_ff2 <= trans_txn_ff;
+			if ((transmit == 1'b1) && (transmit_on_nontras != 1'b1))
+				transmit_on_nontras <= 1'b1;
+			else if ((trans_txn_ff == 1'b1) && (trans_txn_ff2 == 2'b00))
+				transmit_on_nontras <= 1'b0;
+		end
+	reg [2:0] data_count;
+	reg we;
+	reg start_read;
+	reg read_issued;
+	reg read_registered;
+	reg read_complete;
+	reg write_issued;
+	reg pending_res;
+	always @(posedge clk_i or posedge rst_i)
+		if (rst_i) begin
+			pending_res <= 0;
+			UART_STATE <= IDLE;
+			MEMORY_ADDRESS <= 0;
+			transmit <= 0;
+			data_count <= 4;
+			we <= 0;
+			start_read <= 0;
+			DATA <= 0;
+			tx_byte_i <= 0;
+		end
+		else
+			case (UART_STATE)
+				IDLE: begin
+					data_count <= 4;
+					start_read <= 0;
+					if (received_o || (pending_res == 1'b1)) begin
+						if (recv_error_o == 1'b0)
+							if (is_transmitting_o)
+								pending_res <= 1'b1;
+							else if (rx_byte_o[7:0] == PKT_WRITE_CMD[7:0]) begin
+								tx_byte_i <= PKT_WRITE_CMD;
+								we <= 1;
+								transmit <= 1;
+								pending_res <= 1'b0;
+								UART_STATE <= WAIT_ADDR_HEAD;
+							end
+							else if (rx_byte_o[7:0] == PKT_READ_CMD[7:0]) begin
+								tx_byte_i <= PKT_READ_CMD;
+								we <= 0;
+								transmit <= 1;
+								pending_res <= 1'b0;
+								UART_STATE <= WAIT_ADDR_HEAD;
+							end
+					end
+					else if (((((((!is_transmitting_o & !received_o) & !is_receiving_o) & !transmit_i) & !data_req_o) & !data_rvalid_i) & !data_gnt_i) & !transmit) begin
+						tx_byte_i <= PKT_ALIVE;
+						transmit <= 1;
+					end
+					else
+						transmit <= 0;
+				end
+				WAIT_ADDR_HEAD:
+					if (received_o) begin
+						if (recv_error_o == 1'b1)
+							UART_STATE <= IDLE;
+						else if (rx_byte_o[7:5] == PKT_ADR[7:5]) begin
+							tx_byte_i <= rx_byte_o;
+							MEMORY_ADDRESS[11:8] <= rx_byte_o[3:0];
+							transmit <= 1;
+							UART_STATE <= WAIT_ADDR_TAIL;
+						end
+					end
+					else
+						transmit <= 0;
+				WAIT_ADDR_TAIL:
+					if (received_o) begin
+						MEMORY_ADDRESS[7:0] <= rx_byte_o[7:0];
+						data_count <= 4;
+						if (recv_error_o == 1'b1)
+							UART_STATE <= IDLE;
+						else if (we == 1) begin
+							tx_byte_i <= rx_byte_o;
+							transmit <= 1;
+							UART_STATE <= RECEIVE_WRITE_DATA;
+						end
+						else
+							start_read <= 1;
+					end
+					else if (read_issued)
+						start_read <= 0;
+					else if (read_complete)
+						UART_STATE <= SEND_READ_DATA;
+					else
+						transmit <= 0;
+				RECEIVE_WRITE_DATA:
+					if (received_o) begin
+						tx_byte_i <= rx_byte_o;
+						if (data_count == 4) begin
+							DATA[31:24] <= rx_byte_o;
+							data_count <= 3;
+						end
+						else if (data_count == 3) begin
+							DATA[23:16] <= rx_byte_o;
+							data_count <= 2;
+						end
+						else if (data_count == 2) begin
+							DATA[15:8] <= rx_byte_o;
+							data_count <= 1;
+						end
+						else if (data_count == 1) begin
+							DATA[7:0] <= rx_byte_o;
+							data_count <= 0;
+							UART_STATE <= IDLE;
+						end
+						transmit <= 1;
+					end
+					else
+						transmit <= 0;
+				SEND_READ_DATA:
+					if (data_count == 4) begin
+						tx_byte_i <= DATA_READ[31:24];
+						transmit <= 1;
+						data_count <= 3;
+					end
+					else if (((((!is_transmitting_o & !transmit_i) & !data_req_o) & !data_rvalid_i) & !data_gnt_i) & !transmit) begin
+						if (data_count == 3) begin
+							tx_byte_i <= DATA_READ[23:16];
+							data_count <= 2;
+							transmit <= 1;
+						end
+						else if (data_count == 2) begin
+							tx_byte_i <= DATA_READ[15:8];
+							data_count <= 1;
+							transmit <= 1;
+						end
+						else if (data_count == 1) begin
+							tx_byte_i <= DATA_READ[7:0];
+							data_count <= 0;
+							transmit <= 1;
+						end
+						else if (data_count == 0)
+							UART_STATE <= IDLE;
+					end
+					else
+						transmit <= 0;
+			endcase
+	always @(posedge clk_i)
+		if (rst_i) begin
+			write_issued <= 0;
+			read_issued <= 0;
+			read_registered <= 0;
+			DATA_READ <= 0;
+			data_we_o <= 0;
+			data_req_o <= 0;
+			read_complete <= 0;
+		end
+		else if (((data_count == 0) | (write_issued == 1)) & (we == 1)) begin
+			if (write_issued == 0) begin
+				data_we_o <= 1;
+				data_req_o <= 1;
+				write_issued <= 1;
+			end
+			else if (write_issued == 1)
+				if (data_gnt_i == 1) begin
+					data_req_o <= 0;
+					write_issued <= 0;
+				end
+		end
+		else if (~read_issued & (start_read == 1)) begin
+			read_complete <= 0;
+			data_we_o <= 0;
+			data_req_o <= 1;
+			read_issued <= 1;
+		end
+		else if ((read_issued == 1) & (data_gnt_i == 1)) begin
+			data_req_o <= 0;
+			read_issued <= 0;
+			read_registered <= 1;
+		end
+		else if (read_registered == 1) begin
+			if (data_rvalid_i) begin
+				read_registered <= 0;
+				DATA_READ <= data_rdata_i;
+				read_complete <= 1;
+			end
+		end
+		else if (read_complete == 1)
+			read_complete <= 0;
+	uart uart_i(
+		clk_i,
+		rst_i,
+		rx_i,
+		tx_o,
+		transmit_i,
+		tx_byte_i,
+		received_o,
+		rx_byte_o,
+		is_receiving_o,
+		is_transmitting_o,
+		recv_error_o
+	);
+endmodule
diff --git a/verilog/rtl/icesoc/uart_tx.v b/verilog/rtl/icesoc/uart_tx.v
new file mode 100644
index 0000000..518b6d3
--- /dev/null
+++ b/verilog/rtl/icesoc/uart_tx.v
@@ -0,0 +1,115 @@
+/*
+
+Copyright (c) 2014-2017 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream UART
+ */
+module uart_tx #
+(
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
+    input  wire                   s_axis_tvalid,
+    output wire                   s_axis_tready,
+
+    /*
+     * UART interface
+     */
+    output wire                   txd,
+
+    /*
+     * Status
+     */
+    output wire                   busy,
+
+    /*
+     * Configuration
+     */
+    input  wire [15:0]            prescale
+);
+
+reg s_axis_tready_reg = 0;
+
+reg txd_reg = 1;
+
+reg busy_reg = 0;
+
+reg [DATA_WIDTH:0] data_reg = 0;
+reg [18:0] prescale_reg = 0;
+reg [3:0] bit_cnt = 0;
+
+assign s_axis_tready = s_axis_tready_reg;
+assign txd = txd_reg;
+
+assign busy = busy_reg;
+
+always @(posedge clk) begin
+    if (rst) begin
+        s_axis_tready_reg <= 0;
+        txd_reg <= 1;
+        prescale_reg <= 0;
+        bit_cnt <= 0;
+        busy_reg <= 0;
+    end else begin
+        if (prescale_reg > 0) begin
+            s_axis_tready_reg <= 0;
+            prescale_reg <= prescale_reg - 1;
+        end else if (bit_cnt == 0) begin
+            s_axis_tready_reg <= 1;
+            busy_reg <= 0;
+
+            if (s_axis_tvalid) begin
+                s_axis_tready_reg <= !s_axis_tready_reg;
+                prescale_reg <= (prescale << 3)-1;
+                bit_cnt <= DATA_WIDTH+1;
+                data_reg <= {1'b1, s_axis_tdata};
+                txd_reg <= 0;
+                busy_reg <= 1;
+            end
+        end else begin
+            if (bit_cnt > 1) begin
+                bit_cnt <= bit_cnt - 1;
+                prescale_reg <= (prescale << 3)-1;
+                {data_reg, txd_reg} <= {1'b0, data_reg};
+            end else if (bit_cnt == 1) begin
+                bit_cnt <= bit_cnt - 1;
+                prescale_reg <= (prescale << 3);
+                txd_reg <= 1;
+            end
+        end
+    end
+end
+
+endmodule
diff --git a/verilog/rtl/models_pack.v b/verilog/rtl/models_pack.v
new file mode 100644
index 0000000..b30bd69
--- /dev/null
+++ b/verilog/rtl/models_pack.v
@@ -0,0 +1,532 @@
+// SPDX-FileCopyrightText: 
+// 2021 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+// Models for the embedded FPGA fabric
+// LHD1 Latch area 11.76
+//`timescale 1ns/1ns
+/* module LHD1_old (D, E, Q, QN);
+	input D;     // global signal 1: configuration, 0: operation
+	input E;
+	output Q;
+	output QN; 
+
+	wire M_set_gate, M_reset_gate;
+	wire S_set_gate, S_reset_gate;
+	wire M_q, M_qn;
+	wire S_q, S_qn;
+
+	// master
+	assign M_set_gate = ~(D & E);
+	assign M_reset_gate = ~((~D) & E);
+	assign M_q = ~(M_qn & M_set_gate);
+	assign M_qn = ~(M_q & M_reset_gate);
+
+	assign Q = M_q;
+	assign QN = M_qn;
+
+endmodule
+
+module LHQD1 (input D, E, output reg Q);
+    always @(*) begin
+        if (E == 1'b1) begin
+            Q = D;
+        end
+    end
+endmodule
+
+module LHQD1_old (D, E, Q);
+	input D;// global signal 1: configuration, 0: operation
+	input E;
+	output Q;
+
+	wire M_set_gate;
+	wire M_reset_gate;
+	wire M_q;
+	wire M_qn;
+
+// master
+	assign M_set_gate = ~(D & E);
+	assign M_reset_gate = ~((~D) & E);
+	assign M_q = ~(M_qn & M_set_gate);
+	assign M_qn = (M_q & M_reset_gate);
+
+	assign Q = M_q;
+
+endmodule */
+
+module LHQD1 (input D, E, output reg Q, QN);
+    always @(*)
+    begin
+        if (E == 1'b1) begin
+            Q = D;
+            QN = ~D;
+        end
+    end
+endmodule
+
+// (MUX4PTv4) and 1.2ns (MUX16PTv2) in worse case when all select bits=0, so I think they work fine with f=50MHz. 
+// The area are HxW = 7um x 9.86um (MUX4PTv4) and 7um x 44.72um (MUX16PTv2). 
+// Please note, the pins are named as IN1, IN2, ..., IN16 for inputs, S1, .., S4 for selects and OUT for output.
+
+module MUX4PTv4 (IN1, IN2, IN3, IN4, S1, S2, O);
+	input IN1;
+	input IN2;
+	input IN3;
+	input IN4;
+	input S1;
+	input S2;
+	output O; 
+	reg O;
+	wire [1:0] SEL;
+
+	assign SEL = {S2,S1};
+	always @(*) 
+	begin
+		case(SEL)
+			2'b00:O = IN1;
+			2'b01:O = IN2;
+			2'b10:O = IN3;
+			2'b11:O = IN4;
+			default:O = 1'b0;
+		endcase
+	end
+
+endmodule 
+
+module MUX16PTv2 (IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, IN10, IN11, IN12, IN13, IN14, IN15, IN16, S1, S2, S3, S4, O);
+	input IN1;
+	input IN2;
+	input IN3;
+	input IN4;
+	input IN5;
+	input IN6;
+	input IN7;
+	input IN8;
+	input IN9;
+	input IN10;
+	input IN11;
+	input IN12;
+	input IN13;
+	input IN14;
+	input IN15;
+	input IN16;
+	input S1;
+	input S2;
+	input S3;
+	input S4;
+	output O;
+	reg O;
+	wire [3:0] SEL;
+
+	assign SEL = {S4,S3,S2,S1};
+	always @(*)
+	begin
+		case(SEL)
+			4'b0000: O = IN1;
+			4'b0001: O = IN2;
+			4'b0010: O = IN3;
+			4'b0011: O = IN4;
+			4'b0100: O = IN5;
+			4'b0101: O = IN6;
+			4'b0110: O = IN7;
+			4'b0111: O = IN8;
+			4'b1000: O = IN9;
+			4'b1001: O = IN10;
+			4'b1010: O = IN11;
+			4'b1011: O = IN12;
+			4'b1100: O = IN13;
+			4'b1101: O = IN14;
+			4'b1110: O = IN15;
+			4'b1111: O = IN16;
+			default: O = 1'b0;
+		endcase
+	end
+
+endmodule
+
+module my_buf (A, X);
+    input A;
+    output X;
+    assign X = A;
+endmodule
+
+module clk_buf (A, X); //this will later be mapped to clk buffer
+    input A;
+    output X;
+    assign X = A;
+endmodule
+
+module cus_mux41 (A0, A1, A2, A3, S0, S0N, S1, S1N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	output X; 
+	reg X;
+	wire [1:0] SEL;
+
+	assign SEL = {S1,S0};
+	always @(*) 
+	begin
+		case(SEL)
+			2'b00:X = A0;
+			2'b01:X = A1;
+			2'b10:X = A2;
+			2'b11:X = A3;
+			default:X = 1'b0;
+		endcase
+	end
+endmodule
+
+module cus_mux41_buf (A0, A1, A2, A3, S0, S0N, S1, S1N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	output X; 
+	reg X;
+	wire [1:0] SEL;
+
+	assign SEL = {S1,S0};
+	always @(*) 
+	begin
+		case(SEL)
+			2'b00:X = A0;
+			2'b01:X = A1;
+			2'b10:X = A2;
+			2'b11:X = A3;
+			default:X = 1'b0;
+		endcase
+	end
+endmodule
+
+module my_mux2 (A0, A1, S, X);
+	input A0;
+	input A1;
+	input S;
+	output X; 
+	reg X;
+	wire SEL;
+
+	assign SEL = S;
+	always @(*) 
+	begin
+		case(SEL)
+			1'b0:X = A0;
+			1'b1:X = A1;
+			default:X = 1'b0;
+		endcase
+	end
+endmodule 
+
+module cus_mux81 (A0, A1, A2, A3, A4, A5, A6, A7, S0, S0N, S1, S1N, S2, S2N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input A4;
+	input A5;
+	input A6;
+	input A7;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	input S2;
+	input S2N;
+	output X;
+
+	wire cus_mux41_out0;
+	wire cus_mux41_out1;
+
+	cus_mux41 cus_mux41_inst0(
+	.A0 (A0),
+	.A1 (A1),
+	.A2 (A2),
+	.A3 (A3),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out0)
+	);
+	
+	cus_mux41 cus_mux41_inst1(
+	.A0 (A4),
+	.A1 (A5),
+	.A2 (A6),
+	.A3 (A7),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out1)
+	);
+
+	my_mux2 my_mux2_inst(
+	.A0(cus_mux41_out0),
+	.A1(cus_mux41_out1),
+	.S (S2),
+	.X (X)
+	);
+endmodule
+
+module cus_mux81_buf (A0, A1, A2, A3, A4, A5, A6, A7, S0, S0N, S1, S1N, S2, S2N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input A4;
+	input A5;
+	input A6;
+	input A7;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	input S2;
+	input S2N;
+	output X;
+
+	wire cus_mux41_buf_out0;
+	wire cus_mux41_buf_out1;
+
+	cus_mux41_buf cus_mux41_buf_inst0(
+	.A0 (A0),
+	.A1 (A1),
+	.A2 (A2),
+	.A3 (A3),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out0)
+	);
+	
+	cus_mux41_buf cus_mux41_buf_inst1(
+	.A0 (A4),
+	.A1 (A5),
+	.A2 (A6),
+	.A3 (A7),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out1)
+	);
+
+	my_mux2 my_mux2_inst(
+	.A0(cus_mux41_buf_out0),
+	.A1(cus_mux41_buf_out1),
+	.S (S2),
+	.X (X)
+	);
+endmodule
+
+module cus_mux161 (A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, S0, S0N, S1, S1N, S2, S2N, S3, S3N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input A4;
+	input A5;
+	input A6;
+	input A7;
+	input A8;
+	input A9;
+	input A10;
+	input A11;
+	input A12;
+	input A13;
+	input A14;
+	input A15;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	input S2;
+	input S2N;
+	input S3;
+	input S3N;
+	output X;
+
+	wire cus_mux41_out0;
+	wire cus_mux41_out1;
+	wire cus_mux41_out2;
+	wire cus_mux41_out3;
+
+	cus_mux41 cus_mux41_inst0(
+	.A0 (A0),
+	.A1 (A1),
+	.A2 (A2),
+	.A3 (A3),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out0)
+	);
+	
+	cus_mux41 cus_mux41_inst1(
+	.A0 (A4),
+	.A1 (A5),
+	.A2 (A6),
+	.A3 (A7),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out1)
+	);
+
+	cus_mux41 cus_mux41_inst2(
+	.A0 (A8),
+	.A1 (A9),
+	.A2 (A10),
+	.A3 (A11),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out2)
+	);
+
+	cus_mux41 cus_mux41_inst3(
+	.A0 (A12),
+	.A1 (A13),
+	.A2 (A14),
+	.A3 (A15),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_out3)
+	);
+	
+	cus_mux41 cus_mux41_inst4(
+	.A0 (cus_mux41_out0),
+	.A1 (cus_mux41_out1),
+	.A2 (cus_mux41_out2),
+	.A3 (cus_mux41_out3),
+	.S0 (S2),
+	.S0N(S2N),
+	.S1 (S3),
+	.S1N(S3N),
+	.X  (X)
+	);
+endmodule
+
+module cus_mux161_buf (A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, S0, S0N, S1, S1N, S2, S2N, S3, S3N, X);
+	input A0;
+	input A1;
+	input A2;
+	input A3;
+	input A4;
+	input A5;
+	input A6;
+	input A7;
+	input A8;
+	input A9;
+	input A10;
+	input A11;
+	input A12;
+	input A13;
+	input A14;
+	input A15;
+	input S0;
+	input S0N;
+	input S1;
+	input S1N;
+	input S2;
+	input S2N;
+	input S3;
+	input S3N;
+	output X;
+
+	wire cus_mux41_buf_out0;
+	wire cus_mux41_buf_out1;
+	wire cus_mux41_buf_out2;
+	wire cus_mux41_buf_out3;
+
+	cus_mux41_buf cus_mux41_buf_inst0(
+	.A0 (A0),
+	.A1 (A1),
+	.A2 (A2),
+	.A3 (A3),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out0)
+	);
+	
+	cus_mux41_buf cus_mux41_buf_inst1(
+	.A0 (A4),
+	.A1 (A5),
+	.A2 (A6),
+	.A3 (A7),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out1)
+	);
+
+	cus_mux41_buf cus_mux41_buf_inst2(
+	.A0 (A8),
+	.A1 (A9),
+	.A2 (A10),
+	.A3 (A11),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out2)
+	);
+
+	cus_mux41_buf cus_mux41_buf_inst3(
+	.A0 (A12),
+	.A1 (A13),
+	.A2 (A14),
+	.A3 (A15),
+	.S0 (S0),
+	.S0N(S0N),
+	.S1 (S1),
+	.S1N(S1N),
+	.X  (cus_mux41_buf_out3)
+	);
+	
+	cus_mux41_buf cus_mux41_buf_inst4(
+	.A0 (cus_mux41_buf_out0),
+	.A1 (cus_mux41_buf_out1),
+	.A2 (cus_mux41_buf_out2),
+	.A3 (cus_mux41_buf_out3),
+	.S0 (S2),
+	.S0N(S2N),
+	.S1 (S3),
+	.S1N(S3N),
+	.X  (X)
+	);
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..a1590a6 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,123 +1,147 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper.  The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-module user_project_wrapper #(
-    parameter BITS = 32
-) (
-`ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
-`endif
-
-    // Wishbone Slave ports (WB MI A)
-    input wb_clk_i,
-    input wb_rst_i,
-    input wbs_stb_i,
-    input wbs_cyc_i,
-    input wbs_we_i,
-    input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
-    output wbs_ack_o,
-    output [31:0] wbs_dat_o,
-
-    // Logic Analyzer Signals
-    input  [127:0] la_data_in,
-    output [127:0] la_data_out,
-    input  [127:0] la_oenb,
-
-    // IOs
-    input  [`MPRJ_IO_PADS-1:0] io_in,
-    output [`MPRJ_IO_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-1:0] io_oeb,
-
-    // Analog (direct connection to GPIO pad---use with caution)
-    // Note that analog I/O is not available on the 7 lowest-numbered
-    // GPIO pads, and so the analog_io indexing is offset from the
-    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
-    inout [`MPRJ_IO_PADS-10:0] analog_io,
-
-    // Independent clock (on independent integer divider)
-    input   user_clock2,
-
-    // User maskable interrupt signals
-    output [2:0] user_irq
-);
-
-/*--------------------------------------*/
-/* User project is instantiated  here   */
-/*--------------------------------------*/
-
-user_proj_example mprj (
-`ifdef USE_POWER_PINS
-	.vccd1(vccd1),	// User area 1 1.8V power
-	.vssd1(vssd1),	// User area 1 digital ground
-`endif
-
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
-
-    // MGMT SoC Wishbone Slave
-
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
-
-    // Logic Analyzer
-
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
-
-    // IO Pads
-
-    .io_in (io_in),
-    .io_out(io_out),
-    .io_oeb(io_oeb),
-
-    // IRQ
-    .irq(user_irq)
-);
-
-endmodule	// user_project_wrapper
-
-`default_nettype wire
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper.  The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+    parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated  here   */
+/*--------------------------------------*/
+
+eFPGA_CPU_top inst_eFPGA_CPU_top (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+	.wb_clk_i(wb_clk_i),
+	.wb_rst_i(wb_rst_i),
+	.wbs_stb_i(wbs_stb_i),
+	.wbs_cyc_i(wbs_cyc_i),
+	.wbs_we_i(wbs_we_i),
+	.wbs_sel_i(wbs_sel_i),
+	.wbs_dat_i(wbs_dat_i),
+	.wbs_adr_i(wbs_adr_i),
+	.wbs_ack_o(wbs_ack_o),
+	.wbs_dat_o(wbs_dat_o),
+	.la_data_out(la_data_out[6:4]),
+	.la_data_in(la_data_in[3:0]),
+	.io_in(io_in),
+	.io_out(io_out),
+	.io_oeb(io_oeb),
+	.user_clock2(user_clock2)
+);
+
+assign user_irq = 3'b000;
+/*
+user_proj_example mprj (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in (io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+
+    // IRQ
+    .irq(user_irq)
+);
+*/
+endmodule	// user_project_wrapper
+`default_nettype wire