# YONGA-Turbo Encoder

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Table of contents
=================

- [Overview](#overview)
- [Setup](#setup)
- [Running Simulation](#running-simulation)
- [Hardening the User Project Macro using OpenLANE](#hardening-the-user-project-macro-using-openlane)
- [List of Contributors](#list-of-contributors)

Overview
========
#### DVB-RCS2 Turbo Encoder

Turbo Encoder is used for FEC encoding for linear modulation.

Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)

First couple of parity bits (Y1W1) are generated from linearly ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.

The design involves two paths: 
1) Linear order path
2) Interleaved path

#### Top-Level Diagram
![alt text](docs/images/encoder_schematic.png)

-Input Data is stored at dual channel rams. 

-AGU's (Address Generator Unit) generate data indices for linearly ordered and interleaved data inputs.

-Pre Encoder unit identifies initial state of the encoder.

-Encoder Core produces outputs according to the state and the inputs.

#### Synthesis Report
![alt text](docs/images/synt_encoder.png)

#### Implementation Report
![alt text](docs/images/imp_encoder.png)

-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1


#### Throughput
![equation](http://www.sciweavers.org/tex2img.php?eq=%5Cfrac%7B2%2AN%7D%7B3%2AN%2B10%7D%20%2A%20f&bc=White&fc=Black&im=jpg&fs=12&ff=arev&edit=0)

'N' = input data block size in couple number ranging from 56 to 2396.

'f' = frequency in Mhz.

For 50 Mhz clock speed and N = 56, throughput equals to 31.5 Mbps.

For 50 Mhz clock speed and N = 2396, throughput equals to 33.3 Mbps.

Setup
========

TBA

Running Simulation
========

TBA

Hardening the User Project Macro using OpenLANE
========

TBA

List of Contributors
=================================

*In alphabetical order:*

- Baris Bilgili
- Burak Yakup Cakar
- Muhammed Celik