| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/digitalcore_macro,digitalcore_macro,digitalcore_macro,flow_completed,0h8m29s,-1,26768.0,0.5,13384.0,14.13,1256.05,6692,0,0,0,0,0,0,0,8,0,0,-1,372888,57349,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,263757490.0,14.05,14.13,21.61,0.09,0.86,-1,2996,11068,516,8220,0,0,0,3925,0,0,0,0,0,0,0,4,1351,2092,27,718,6678,0,7396,38.46153846153846,26,25,AREA 0,5,50,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hd,4,4 |
