)]}'
{
  "commit": "6643b61db2b43499291241e03ac8dbf29d8db2fa",
  "tree": "ab104c5a6ef2fc33be1d8c8d74a447df60a5a86d",
  "parents": [
    "7f024646f327b8cfc0e80fef52505b4bfa8bc87a"
  ],
  "author": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Fri Dec 31 18:16:12 2021 -0800"
  },
  "committer": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Fri Dec 31 18:16:12 2021 -0800"
  },
  "message": "Move addresses for compatibility with litex soc.\n\nThe new litex design appears to restrict the wishbone address space\nsignificantly so we need to use the bottom part of the address region\notherwise we won\u0027t be able to access our registers.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "188e9973612e460ee2d567820de4c66c9042284e",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "ad4875ca7785107f40b7b1b06f9f9704640e8dcc",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "0f16ba8eaae841a6f122fc0d5837005d3312fd2b",
      "old_mode": 57344,
      "old_path": "caravel",
      "new_id": "c2943440e278814787f761585b99b9ea3c1f4121",
      "new_mode": 57344,
      "new_path": "caravel"
    },
    {
      "type": "modify",
      "old_id": "024480d0405a069b30649e1efb1e814257d85c73",
      "old_mode": 33188,
      "old_path": "envsetup",
      "new_id": "c4a6a3277806041dece22821314b4556e2435516",
      "new_mode": 33188,
      "new_path": "envsetup"
    },
    {
      "type": "modify",
      "old_id": "467fbc5d9cd312aa8fb52f9ac5c76528f2f0fe54",
      "old_mode": 33188,
      "old_path": "ip/randsack/rtl/digitalcore_macro.v",
      "new_id": "864850a0b0ab86a541b53d019f0c35c85ee7d43a",
      "new_mode": 33188,
      "new_path": "ip/randsack/rtl/digitalcore_macro.v"
    },
    {
      "type": "modify",
      "old_id": "8797dcdee01982869d8ce5675cdc7171aa9a1275",
      "old_mode": 40960,
      "old_path": "openlane/user_project_wrapper/pin_order.cfg",
      "new_id": "267d91c68441a18d6035c9f882b1c6f3ac8447a1",
      "new_mode": 40960,
      "new_path": "openlane/user_project_wrapper/pin_order.cfg"
    },
    {
      "type": "modify",
      "old_id": "a820b17265867c59d62a1458117ee18366715d99",
      "old_mode": 33188,
      "old_path": "verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c",
      "new_id": "90dba8525bbafc98adf90972a53ee6285611448e",
      "new_mode": 33188,
      "new_path": "verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c"
    }
  ]
}