diff --git a/Makefile b/Makefile
index 188e997..ad4875c 100644
--- a/Makefile
+++ b/Makefile
@@ -24,11 +24,11 @@
 ifeq ($(CARAVEL_LITE),1) 
 	CARAVEL_NAME := caravel-lite
 	CARAVEL_REPO := https://github.com/efabless/caravel-lite 
-	CARAVEL_BRANCH := main
+	CARAVEL_BRANCH ?= main
 else
 	CARAVEL_NAME := caravel
 	CARAVEL_REPO := https://github.com/efabless/caravel 
-	CARAVEL_BRANCH := master
+	CARAVEL_BRANCH ?= master
 endif
 
 # Install caravel as submodule, (1): submodule, (0): clone
diff --git a/caravel b/caravel
index 0f16ba8..c294344 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
+Subproject commit c2943440e278814787f761585b99b9ea3c1f4121
diff --git a/envsetup b/envsetup
index 024480d..c4a6a32 100644
--- a/envsetup
+++ b/envsetup
@@ -9,8 +9,10 @@
 export PDK_PATH=/home/harrison/workspace/sky130/sky130A/
 
 # Precheck
-export PRECHECK_ROOT=/home/harrison/workspace/precheck/
+export PRECHECK_ROOT=/home/harrison/workspace/mpw4/precheck/
 
-# Hack for mpw-3
-export OPENLANE_TAG=master
+export OPENLANE_TAG=mpw-3a
+
+export CARAVEL_LITE=1
+export CARAVEL_BRANCH=mpw-3a
 
diff --git a/ip/randsack/rtl/digitalcore_macro.v b/ip/randsack/rtl/digitalcore_macro.v
index 467fbc5..864850a 100644
--- a/ip/randsack/rtl/digitalcore_macro.v
+++ b/ip/randsack/rtl/digitalcore_macro.v
@@ -65,22 +65,22 @@
   parameter DTOP_ADDR    = 32'h3000_0000;
 
   // Peripherals.
-  parameter GPIO0_ADDR_MASK   = 32'hffff_0000;
-  parameter GPIO0_BASE_ADDR   = 32'h3080_0000;
+  parameter GPIO0_ADDR_MASK   = 32'hffff_ff00;
+  parameter GPIO0_BASE_ADDR   = 32'h3000_0000;
   parameter PWM0_ADDR_MASK    = 32'hffff_ff00;
-  parameter PWM0_BASE_ADDR    = 32'h3081_0000;
+  parameter PWM0_BASE_ADDR    = 32'h3000_1000;
   parameter PWM1_ADDR_MASK    = 32'hffff_ff00;
-  parameter PWM1_BASE_ADDR    = 32'h3081_0100;
+  parameter PWM1_BASE_ADDR    = 32'h3000_1100;
   parameter PWM2_ADDR_MASK    = 32'hffff_ff00;
-  parameter PWM2_BASE_ADDR    = 32'h3081_0200;
+  parameter PWM2_BASE_ADDR    = 32'h3000_1200;
   parameter PWM3_ADDR_MASK    = 32'hffff_ff00;
-  parameter PWM3_BASE_ADDR    = 32'h3081_0300;
-  parameter UART0_ADDR_MASK   = 32'hffff_0000;
-  parameter UART0_BASE_ADDR   = 32'h3082_0000;
+  parameter PWM3_BASE_ADDR    = 32'h3000_1300;
+  parameter UART0_ADDR_MASK   = 32'hffff_ff00;
+  parameter UART0_BASE_ADDR   = 32'h3000_2000;
   parameter RING0_ADDR_MASK   = 32'hffff_ff00;
-  parameter RING0_BASE_ADDR   = 32'h3083_0000;
+  parameter RING0_BASE_ADDR   = 32'h3000_3000;
   parameter RING1_ADDR_MASK   = 32'hffff_ff00;
-  parameter RING1_BASE_ADDR   = 32'h3083_0100;
+  parameter RING1_BASE_ADDR   = 32'h3000_3100;
 
   // Filter addresses from Caravel since we want to be absolutely sure it is
   // selecting us before letting it access the arbiter.  This is mostly needed
@@ -248,7 +248,7 @@
   wire pwm_stb_i[4];
   wire pwm_ack_o[4];
   wire [31:0] pwm_dat_o[4];
-  
+
   wire pwm_out[4];
 
   genvar i;
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 8797dcd..267d91c 120000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1 @@
-../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
diff --git a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
index a820b17..90dba85 100644
--- a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
+++ b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
@@ -21,14 +21,14 @@
 
 #define REG(addr) (*(volatile uint32_t*)(addr))
 
-#define RANDSACK_GPIO0_BASE 0x30800000
-#define RANDSACK_PWM0_BASE  0x30810000
-#define RANDSACK_PWM1_BASE  0x30810100
-#define RANDSACK_PWM2_BASE  0x30810200
-#define RANDSACK_PWM3_BASE  0x30810300
-#define RANDSACK_UART0_BASE 0x30820000
-#define RANDSACK_RING0_BASE 0x30830000
-#define RANDSACK_RING1_BASE 0x30830100
+#define RANDSACK_GPIO0_BASE 0x30000000
+#define RANDSACK_PWM0_BASE  0x30001000
+#define RANDSACK_PWM1_BASE  0x30001100
+#define RANDSACK_PWM2_BASE  0x30001200
+#define RANDSACK_PWM3_BASE  0x30001300
+#define RANDSACK_UART0_BASE 0x30002000
+#define RANDSACK_RING0_BASE 0x30003000
+#define RANDSACK_RING1_BASE 0x30003100
 
 #define RANDSACK_GPIO_DATA  0x00
 #define RANDSACK_GPIO_ENA   0x04