)]}'
{
  "commit": "43158e89965ed57ae62000dd7bab523194484e19",
  "tree": "ba6900f876347f395eb6430203c378d05218c93f",
  "parents": [
    "c170f923f97375ee6c3814b6722fdf33b665a32a"
  ],
  "author": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Sat Oct 23 17:22:57 2021 -0700"
  },
  "committer": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Sat Oct 23 17:22:57 2021 -0700"
  },
  "message": "Wrapper now hardens and DRC/LVS clean.\n\nStill need to double check timing and add remaining IP blocks.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c94b7a0d8a8b92a2cd637b9a887858b5d16aa125",
      "old_mode": 33261,
      "old_path": "openlane/user_project_wrapper/config.tcl",
      "new_id": "80814acde64faaeb2245a5c4e40d5eaba1005bcb",
      "new_mode": 33261,
      "new_path": "openlane/user_project_wrapper/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "a7365ab26ff25197ed46ceb62342f48e1473ea19",
      "old_mode": 33188,
      "old_path": "openlane/user_project_wrapper/macro.cfg",
      "new_id": "732f5abe612d65d5aee5724b6cce760471d3498a",
      "new_mode": 33188,
      "new_path": "openlane/user_project_wrapper/macro.cfg"
    },
    {
      "type": "modify",
      "old_id": "646c96de48050c7fdf098aa3fb747a5d68a8933d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "bde06b68da1fba8429527e23c2ed3fde627fc968",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}