diff --git a/verilog/rtl/control_module.v b/verilog/rtl/control_module.v
index 5a6cf35..ed8723a 100644
--- a/verilog/rtl/control_module.v
+++ b/verilog/rtl/control_module.v
@@ -24,8 +24,10 @@
 (
     parameter WORD_SIZE = 32,
     parameter SIZE_WORD = 3,
-    parameter INPUT_DATA_SIZE = 40,
-    parameter STATUS_SIGNALS = 4,
+    parameter AUXILIAR_SIZE = 44,
+    parameter IO_OUTPUT_SIZE = 8,
+    parameter INPUT_DATA_SIZE = 52,
+    parameter STATUS_SIGNALS = 6,
     parameter DATA_WIDTH = 8,
     parameter OUTPUTS = 32,
     parameter INPUTS = 32,
@@ -38,9 +40,8 @@
     input rtx,
     input rst,
     input [15:0] preescalar_data_rate,
-    input [2:0] id,
     input [INPUTS-1:0] input_io,
-    output [3:0]staus_control_module, // TODO possible expansion of that
+    output [STATUS_SIGNALS-1:0]staus_control_module, // TODO possible expansion of that
     output trx,
     output valid_io, 
     output [OUTPUTS-1:0] output_io 
@@ -48,13 +49,13 @@
 );
 
     
-
+   
     // connection wires
     (* mark_debug = "true" *) wire busy_io_module;
     (* mark_debug = "true" *) wire busy_sender_data;
     (* mark_debug = "true" *) wire [INSTRUCTION_SIZE-1:0] instrucction;
     (* mark_debug = "true" *) wire [SIZE_WORD_REGISTER-1:0] register;
-    (* mark_debug = "true" *) wire [WORD_SIZE-1:0] clock_time;
+    (* mark_debug = "true" *) wire [AUXILIAR_SIZE-1:0] auxiliar_register;
     (* mark_debug = "true" *) wire valid_instrucction;
     (* mark_debug = "true" *) wire valid_control_value;
     // control value
@@ -62,9 +63,12 @@
     (* mark_debug = "true" *) wire [WORD_SIZE-1:0] send_data_register;
     (* mark_debug = "true" *) wire valid_data;
     (* mark_debug = "true" *) wire [SIZE_WORD-1:0] size_line;
-    (* mark_debug = "true" *) wire result_input_io;
+    (* mark_debug = "true" *) wire [IO_OUTPUT_SIZE-1:0] result_input_io;
  
-    
+    // assigments 
+    assign staus_control_module[4] = busy_io_module;
+    assign staus_control_module[5] = busy_sender_data;
+
     // status sender module
     status_sender_data #(
         .WORD_SIZE(WORD_SIZE),
@@ -84,7 +88,7 @@
         .valid_control_value(valid_control_value),
         .control_value(control_value),
         .busy(busy_sender_data),
-        .control_uart(staus_control_module),
+        .control_uart(staus_control_module[3:0]),
         .txd(trx)
     );
 
@@ -93,7 +97,8 @@
         .WORD_SIZE(WORD_SIZE),
         .INSTRUCTION_SIZE(INSTRUCTION_SIZE),
         .OUTPUTS(OUTPUTS),
-        .INPUTS(INPUTS)
+        .INPUTS(INPUTS),
+        .IO_OUTPUT_SIZE(IO_OUTPUT_SIZE)
     )
     io_module_inst (
         .clk(clk),
@@ -101,7 +106,7 @@
         .busy(busy_io_module),
         .instrucction(instrucction),
         .register(register),
-        .clock_time(clock_time),
+        .auxiliar_register(auxiliar_register),
         .valid_instrucction(valid_instrucction),
         .input_io(input_io),
         .valid_io(valid_io),
@@ -129,7 +134,7 @@
         .send_data_register(send_data_register),
         .instrucction(instrucction),
         .register(register),
-        .clock_time(clock_time),
+        .auxiliar_register(auxiliar_register),
         .valid_instrucction(valid_instrucction)
     );
  
diff --git a/verilog/rtl/io_module.v b/verilog/rtl/io_module.v
index 5f17992..c6d9875 100644
--- a/verilog/rtl/io_module.v
+++ b/verilog/rtl/io_module.v
@@ -25,28 +25,30 @@
     parameter SIZE_WORD = 5,
     parameter WORD_SIZE = 32,
     parameter INSTRUCTION_SIZE = 3,
+    parameter IO_OUTPUT_SIZE = 8,
+    parameter AUXILIAR_SIZE = 44,
     parameter OUTPUTS = 32,
     parameter INPUTS = 32,
-    parameter ONE_SECOND_CLOCK = 32'h07735940
+    parameter ONE_SECOND_CLOCK = 44'h00007735940
 )
 (
     input clk,
     input rst,
     (* mark_debug = "true" *)input [INSTRUCTION_SIZE-1:0] instrucction,
     (* mark_debug = "true" *)input [SIZE_WORD-1:0] register,
-    (* mark_debug = "true" *)input [WORD_SIZE-1:0] clock_time,
+    (* mark_debug = "true" *)input [AUXILIAR_SIZE-1:0] auxiliar_register,
     input valid_instrucction,
     input [INPUTS-1:0] input_io,
     output busy,
     output valid_io,
-    output result_input_io, 
+    output [IO_OUTPUT_SIZE-1:0] result_input_io, 
     output [OUTPUTS-1:0] output_io
-    );
+);
         reg busy;
-        (* mark_debug = "true" *) reg result_input_io;
+        (* mark_debug = "true" *) reg [IO_OUTPUT_SIZE-1:0] result_input_io;
         (* mark_debug = "true" *) reg [OUTPUTS-1:0]output_io;
         (* mark_debug = "true" *) reg valid_io;
-        (* mark_debug = "true" *) reg [WORD_SIZE-1:0] curent_clock;
+        (* mark_debug = "true" *) reg [AUXILIAR_SIZE-1:0] curent_clock;
         (* mark_debug = "true" *) reg delay_maintained;
 
 
@@ -62,50 +64,115 @@
         else begin
             if (busy == 1) begin
                 if (curent_clock == 0) begin
-                    if (instrucction[2:1] == 2'b00) begin
+                    // MANTENINED 
+                    if (instrucction == 3'b000) begin
                         output_io[register] <= 1'b0;
                         busy <= 0;
                     end
-                    else if (instrucction == 3'b010) begin
-                        //output_io[register] <= 1'b0;
-                        //busy <= 0;
-                        // TODO
-                    end
-                    else if (instrucction == 3'b011) begin
+                    // DELAYDED TWO TIMES READ AND DELAED 1 SEC AND MANTEINED 
+                    else if (instrucction == 3'b010 || instrucction == 3'b001) begin
                         if (delay_maintained == 1'b0) begin
                             busy <= 0;
                             output_io[register] <= 1'b0;
                         end
                         else begin
                             output_io[register] <= 1'b1;
-                            curent_clock <= clock_time;
+                            curent_clock <= auxiliar_register;
                             busy <= 1;
                             delay_maintained <= 1'b0;
-                        end
-                        
+                        end 
                     end
+                    else if (instrucction == 3'b011) begin
+                        busy <= 0;
+                        valid_io <= 0;
+                        // stop the writes
+                        output_io[register]                 <= 1'b0;
+                        // register 6
+                        output_io[auxiliar_register[43:39]] <= 1'b0;
+                        // register 5
+                        output_io[auxiliar_register[38:34]] <= 1'b0;
+                        // register 4
+                        output_io[auxiliar_register[33:29]] <= 1'b0;
+                        // register 3
+                        output_io[auxiliar_register[28:24]] <= 1'b0;
+                        // register 2
+                        output_io[auxiliar_register[23:19]] <= 1'b0;
+                        // register 1
+                        output_io[auxiliar_register[18:14]] <= 1'b0;
+                        // register 0
+                        output_io[auxiliar_register[13:9]]  <= 1'b0;
+                    end
+                    // END WRITES
                     else if (instrucction[2:1] == 2'b10) begin
                         valid_io <= 1;
                         busy <= 0;
-                        result_input_io <= input_io[register];
-                    end
+                        result_input_io[0] <= input_io[register];
                     end
                     else if (instrucction == 3'b110) begin
-                        //output_io[register] <= 1'b0;
-                        //busy <= 0;
-                        // TODO
+                        valid_io <= 1;
+                        busy <= 0;
+                        // register 7
+                        result_input_io[7] <= input_io[register];
+                        // register 6
+                        result_input_io[6] <= input_io[auxiliar_register[43:39]];
+                        // register 5
+                        result_input_io[5] <= input_io[auxiliar_register[38:34]];
+                        // register 4
+                        result_input_io[4] <= input_io[auxiliar_register[33:29]];
+                        // register 3
+                        result_input_io[3] <= input_io[auxiliar_register[28:24]];
+                        // register 2
+                        result_input_io[2] <= input_io[auxiliar_register[23:19]];
+                        // register 1
+                        result_input_io[1] <= input_io[auxiliar_register[18:14]];
+                        // register 0
+                        result_input_io[0] <= input_io[auxiliar_register[13:9]];
                     end
                     else if (instrucction == 3'b111) begin
                         if (delay_maintained == 1'b0) begin
                             busy <= 0;
-                            result_input_io <= input_io[register];
+                            valid_io <= 0;
+                            // stop the writes
+                            output_io[register]                 <= 1'b0;
+                            // register 6
+                            output_io[auxiliar_register[43:39]] <= 1'b0;
+                            // register 5
+                            output_io[auxiliar_register[38:34]] <= 1'b0;
+                            // register 4
+                            output_io[auxiliar_register[33:29]] <= 1'b0;
+                            // register 3
+                            output_io[auxiliar_register[28:24]] <= 1'b0;
+                            // register 2
+                            output_io[auxiliar_register[23:19]] <= 1'b0;
+                            // register 1
+                            output_io[auxiliar_register[18:14]] <= 1'b0;
+                            // register 0
+                            output_io[auxiliar_register[13:9]]  <= 1'b0;
                         end
                         else begin
-                            result_input_io <= input_io[register];
-                            curent_clock <= clock_time;
+                            curent_clock <= ONE_SECOND_CLOCK;
                             busy <= 1;
                             delay_maintained <= 1'b0;
-                        end
+                            // start the writes
+                            // register 7
+                            output_io[register]                 <= auxiliar_register[7];
+                            // register 6
+                            output_io[auxiliar_register[43:39]] <= auxiliar_register[6];
+                            // register 5
+                            output_io[auxiliar_register[38:34]] <= auxiliar_register[5];
+                            // register 4
+                            output_io[auxiliar_register[33:29]] <= auxiliar_register[4];
+                            // register 3
+                            output_io[auxiliar_register[28:24]] <= auxiliar_register[3];
+                            // register 2
+                            output_io[auxiliar_register[23:19]] <= auxiliar_register[2];
+                            // register 1
+                            output_io[auxiliar_register[18:14]] <= auxiliar_register[1];
+                            // register 0
+                            output_io[auxiliar_register[13:9]] <= auxiliar_register[0];
+                        end 
+                        
+                    end
                 end
                 else begin
                    curent_clock <= curent_clock - 1'b1;
@@ -115,47 +182,66 @@
                 valid_io <= 1'b0;
                 if (valid_instrucction == 1'b1)begin
                     if (instrucction == 3'b000) begin
-                        curent_clock <= ONE_SECOND_CLOCK;
+                        curent_clock <= auxiliar_register;
                         output_io[register] <= 1'b1;
                         valid_io <= 1'b1;
                         busy <= 1;
                     end
                     else if (instrucction == 3'b001) begin
-                        curent_clock <= clock_time;
+                        curent_clock <= ONE_SECOND_CLOCK;
                         output_io[register] <= 1'b1;
+                        delay_maintained <= 1'b1;
                         valid_io <= 1'b1;
                         busy <= 1;
                     end
                     else if (instrucction == 3'b010) begin
-                        // TODO
-                        output_io[register] <= 1'b0;
-                        valid_io <= 1'b1;
-                        busy <= 1;
-                    end
-                    else if (instrucction == 3'b011) begin
-                        curent_clock <= clock_time;
+                        curent_clock <= auxiliar_register;
                         delay_maintained <= 1'b1;
                         valid_io <= 1'b0;
                         busy <= 1;        
                     end
-                    else if (instrucction == 3'b100) begin
+                    else if (instrucction == 3'b011) begin
                         curent_clock <= 0;
+                        valid_io <= 1'b1;
+                        busy <= 1;
+                        // start the writes
+                        // register 7
+                        output_io[register]                 <= auxiliar_register[7];
+                        // register 6
+                        output_io[auxiliar_register[43:39]] <= auxiliar_register[6];
+                        // register 5
+                        output_io[auxiliar_register[38:34]] <= auxiliar_register[5];
+                        // register 4
+                        output_io[auxiliar_register[33:29]] <= auxiliar_register[4];
+                        // register 3
+                        output_io[auxiliar_register[28:24]] <= auxiliar_register[3];
+                        // register 2
+                        output_io[auxiliar_register[23:19]] <= auxiliar_register[2];
+                        // register 1
+                        output_io[auxiliar_register[18:14]] <= auxiliar_register[1];
+                        // register 0
+                        output_io[auxiliar_register[13:9]] <= auxiliar_register[0];
+                    end
+                    else if (instrucction == 3'b100) begin
+                        curent_clock <= auxiliar_register;
                         busy <= 1;
                         valid_io <= 1'b0;      
                     end
                     else if (instrucction == 3'b101) begin
-                        curent_clock <= clock_time;
+                        curent_clock <= auxiliar_register;
                         busy <= 1;
                         valid_io <= 1'b0;       
                     end
                     else if (instrucction == 3'b110) begin
-                        // TODO       
+                        curent_clock <= 0;
+                        busy <= 1;
+                        valid_io <= 1'b0;       
                     end
                     else if (instrucction == 3'b111) begin
-                        delay_maintained <= 1'b1; 
-                        curent_clock <= clock_time;
+                        curent_clock <= ONE_SECOND_CLOCK;
+                        delay_maintained <= 1'b1;
                         busy <= 1;
-                        valid_io <= 1'b0;         
+                        valid_io <= 1'b0;       
                     end
                 end
             end
diff --git a/verilog/rtl/logic_control.v b/verilog/rtl/logic_control.v
index cda53b2..ea820a0 100644
--- a/verilog/rtl/logic_control.v
+++ b/verilog/rtl/logic_control.v
@@ -23,12 +23,21 @@
 module logic_control#
 (
     parameter WORD_SIZE = 32,
+    parameter AUXILIAR_SIZE = 44,
     parameter SIZE_WORD = 3,
-    parameter INPUT_DATA_SIZE = 40,
-    parameter STATUS_SIGNALS = 4,
+    parameter IO_OUTPUT_SIZE = 8,
+    parameter INPUT_DATA_SIZE = 52,
+    parameter STATUS_SIGNALS = 6,
     parameter DATA_WIDTH = 8,
     parameter INSTRUCTION_SIZE = 3,
-    parameter SIZE_WORD_REGISTER = 5
+    parameter SIZE_WORD_REGISTER = 5,
+    parameter INSTRUCCION_INPUT_START = INPUT_DATA_SIZE - 1 , //51 
+    parameter INSTRUCCION_INPUT_END = INSTRUCCION_INPUT_START - (INSTRUCTION_SIZE - 1), // 49
+    parameter REGISTER_INPUT_START = INSTRUCCION_INPUT_END -1, // 48 
+    parameter REGISTER_INPUT_END = REGISTER_INPUT_START - (SIZE_WORD_REGISTER - 1), // 44
+    parameter AUXILIAR_INPUT_START = REGISTER_INPUT_END - 1,
+    parameter AUXILIAR_INPUT_END = 0
+
 )
 (
     input clk,
@@ -37,17 +46,16 @@
     input valid_control_value,
     input busy_sender_data,
     input busy_io_module,
-    input result_input_io,
+    input [IO_OUTPUT_SIZE-1:0] result_input_io,
     output [SIZE_WORD-1:0] size_line,
     output [WORD_SIZE-1:0] send_data_register,
     output valid_data,
     output [INSTRUCTION_SIZE-1:0] instrucction,
     output [SIZE_WORD_REGISTER-1:0] register,
-    output [WORD_SIZE-1:0] clock_time,
+    output [AUXILIAR_SIZE-1:0] auxiliar_register,
     output valid_instrucction
 );
 
-
     // fix register with the multiple words
     reg [WORD_SIZE-1:0] data_1 = {8'h0D, 8'h59, 8'h53, 8'h42};
     reg [WORD_SIZE-1:0] data_2 = {8'h0D, 8'h0A, 8'h4B, 8'h4F};
@@ -67,7 +75,7 @@
     reg valid_instrucction;
     reg [INSTRUCTION_SIZE-1:0] instrucction;
     reg [SIZE_WORD_REGISTER-1:0] register;
-    reg [WORD_SIZE-1:0] clock_time;
+    reg [AUXILIAR_SIZE-1:0] auxiliar_register;
     
     
     always @(posedge clk or posedge rst) begin
@@ -80,9 +88,9 @@
         else begin
             if (busy_io_module == 1'b0 & valid_control_value == 1'b1) begin
                 valid_instrucction <= 1'b1;
-                instrucction <= control_value[INPUT_DATA_SIZE-1: 37];
-                register <= control_value[36: 32];
-                clock_time <= control_value[WORD_SIZE -1: 0];
+                instrucction <= control_value[INSTRUCCION_INPUT_START: INSTRUCCION_INPUT_END];
+                register <= control_value[REGISTER_INPUT_START : REGISTER_INPUT_END];
+                auxiliar_register <= control_value[AUXILIAR_INPUT_START: AUXILIAR_INPUT_END];
                 send_petition_to_io <= 2'b11;
             end
             else if (busy_io_module == 1'b1 & valid_control_value == 1'b1 & busy_sender_data == 1'b0) begin
@@ -92,15 +100,60 @@
                 // a petition have been send so clean the valid instrucction
                 valid_instrucction = 1'b0;
                 if (busy_io_module == 1'b0 & send_petition_to_io[1] == 1'b0) begin
-                    if (instrucction[INSTRUCTION_SIZE-1] == 1'b0) begin
+                    if (instrucction[INSTRUCTION_SIZE-1] == 1'b0 || instrucction == 3'b111) begin
                         send_petition_to_io<= 2'b00;
                         send_data_register <= data_2; 
                         valid_data <= 1'b1; 
                         size_line <= 3'h4;
                     end
+                    else if (instrucction == 3'b110) begin
+                        send_petition_to_io<= 2'b00;
+                        valid_data <= 1'b1; 
+                        size_line <= 3'h4;
+                        send_data_register[31:16] <= 16'h0D0A;
+                        // conversion from binary to hex
+                        case (result_input_io[7:4])
+                            4'h0 : send_data_register[7:0] <= 8'h30;
+                            4'h1 : send_data_register[7:0] <= 8'h31;
+                            4'h2 : send_data_register[7:0] <= 8'h32;
+                            4'h3 : send_data_register[7:0] <= 8'h33;
+                            4'h4 : send_data_register[7:0] <= 8'h34;
+                            4'h5 : send_data_register[7:0] <= 8'h35;
+                            4'h6 : send_data_register[7:0] <= 8'h36;
+                            4'h7 : send_data_register[7:0] <= 8'h37;
+                            4'h8 : send_data_register[7:0] <= 8'h38;
+                            4'h9 : send_data_register[7:0] <= 8'h39;
+                            4'hA : send_data_register[7:0] <= 8'h41;
+                            4'hB : send_data_register[7:0] <= 8'h42;
+                            4'hC : send_data_register[7:0] <= 8'h43;
+                            4'hD : send_data_register[7:0] <= 8'h44;
+                            4'hE : send_data_register[7:0] <= 8'h45;
+                            4'hF : send_data_register[7:0] <= 8'h46;
+                            default: send_data_register[7:0] <= 8'h00;
+                        endcase
+                        case (result_input_io[3:0])
+                            4'h0 : send_data_register[15:8] <= 8'h30;
+                            4'h1 : send_data_register[15:8] <= 8'h31;
+                            4'h2 : send_data_register[15:8] <= 8'h32;
+                            4'h3 : send_data_register[15:8] <= 8'h33;
+                            4'h4 : send_data_register[15:8] <= 8'h34;
+                            4'h5 : send_data_register[15:8] <= 8'h35;
+                            4'h6 : send_data_register[15:8] <= 8'h36;
+                            4'h7 : send_data_register[15:8] <= 8'h37;
+                            4'h8 : send_data_register[15:8] <= 8'h38;
+                            4'h9 : send_data_register[15:8] <= 8'h39;
+                            4'hA : send_data_register[15:8] <= 8'h41;
+                            4'hB : send_data_register[15:8] <= 8'h42;
+                            4'hC : send_data_register[15:8] <= 8'h43;
+                            4'hD : send_data_register[15:8] <= 8'h44;
+                            4'hE : send_data_register[15:8] <= 8'h45;
+                            4'hF : send_data_register[15:8] <= 8'h46;
+                            default: send_data_register[15:8] <= 8'h00;
+                        endcase
+                    end
                     else begin
                         send_petition_to_io<= 2'b00;
-                        if (result_input_io == 1'b0 ) begin
+                        if (result_input_io[0] == 1'b0 ) begin
                             send_data_register <= data_3; 
                             valid_data <= 1'b1; 
                             size_line <= 3'h4;
@@ -124,27 +177,5 @@
             end
         end
     end
-    /*always @(posedge clk or posedge rst) begin
-        if (rst) begin
-            size_line <= 3'h4;
-            send_data_register <= 0;
-            valid_data <= 0;
-        end
-        else begin
-            // main code
-            if (busy_sender_data == 1'b0 & valid_control_value == 1'b1) begin
-                // new valid data available
-                 case(control_value)
-                        40'h1000000000: begin send_data_register <= data_1; valid_data <= 1'b1; size_line <= 3'h4; end
-                        40'h2000000000: begin send_data_register <= data_2; valid_data <= 1'b1; size_line <= 3'h4; end
-                        40'h3000000000: begin send_data_register <= data_3; valid_data <= 1'b1; size_line <= 3'h4; end
-                        default: valid_data <= 0;
-                endcase
-            end
-            else begin
-                valid_data <= 1'b0;
-            end
-        end
-    end*/
 
 endmodule
diff --git a/verilog/rtl/status_sender_data.v b/verilog/rtl/status_sender_data.v
index cb0b1c0..adaed8a 100644
--- a/verilog/rtl/status_sender_data.v
+++ b/verilog/rtl/status_sender_data.v
@@ -23,9 +23,10 @@
 module status_sender_data #
 (
     parameter WORD_SIZE = 32,
-    parameter INPUT_DATA_SIZE = 40,
+    parameter INPUT_DATA_SIZE = 52,
     parameter SIZE_WORD = 3,
-    parameter STATUS_SIGNALS = 4,
+    parameter STATUS_SIGNALS = 6,
+    parameter STATUS_SIGNALS_UART = 4,
     parameter DATA_WIDTH = 8,
     parameter SYMBOL_WITH = 4,
     parameter [8:0]ESCAPE_CHARCTER = 8'h0D,
@@ -43,7 +44,7 @@
     output reg [INPUT_DATA_SIZE-1:0] control_value,
     output reg valid_control_value,
     output busy,
-    output [STATUS_SIGNALS-1:0]control_uart,
+    output [STATUS_SIGNALS_UART-1:0]control_uart,
     output txd
     );
 
diff --git a/verilog/rtl/top_module.v b/verilog/rtl/top_module.v
index e7ec595..0b3dbac 100644
--- a/verilog/rtl/top_module.v
+++ b/verilog/rtl/top_module.v
@@ -24,8 +24,8 @@
 (
     parameter WORD_SIZE = 32,
     parameter SIZE_WORD = 3,
-    parameter INPUT_DATA_SIZE = 40,
-    parameter STATUS_SIGNALS = 4,
+    parameter INPUT_DATA_SIZE = 52,
+    parameter STATUS_SIGNALS = 6,
     parameter DATA_WIDTH = 8,
     parameter BAUD_RATE = 115200,
     parameter CLOCK_SPEED = 125000000,
@@ -42,8 +42,82 @@
     );
     // prescalar reister fix for now
     reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);
-    // id of the control module
-    reg [2:0] id = 2'b00;
+
+    // input IO
+    wire [OUTPUTS - 1 : 0]input_io;
+    // TMP assigment TODO change
+    assign sw = input_io[3:0];
+
+    // TRX triple redundancy
+    // uart transtransmision wires
+    wire uart_output_signal;
+    wire uart_output_signal_inst_1;
+    wire uart_output_signal_inst_2;
+    wire uart_output_signal_inst_3;
+    // asignations
+    assign jc_2 = uart_output_signal;
+    // auxiliar wires
+    wire nand_1_trx;
+    wire nand_2_trx;
+    wire nand_3_trx;
+    wire xor_1_trx;
+    wire xor_2_trx;
+    wire xor_3_trx;
+    wire xor_reduce_1_trx;
+    wire xor_reduce_2_trx;
+    wire xor_reduce_3_trx;
+    // uart transtransmision wires triple redundant
+    (* mark_debug = "true" *) assign nand_1_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_2);
+    (* mark_debug = "true" *) assign nand_2_trx  = ~(uart_output_signal_inst_2 & uart_output_signal_inst_3);
+    (* mark_debug = "true" *) assign nand_3_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_3);
+    (* mark_debug = "true" *) assign uart_output_signal = ~(nand_1_trx & nand_2_trx & nand_3_trx);
+    // uart transtransmision wires triple redundant detection
+    assign xor_1_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_2;
+    assign xor_2_trx  = uart_output_signal_inst_2 ^ uart_output_signal_inst_3;
+    assign xor_3_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_3;
+    assign xor_reduce_1_trx = |xor_1_trx;
+    assign xor_reduce_2_trx = |xor_2_trx;
+    assign xor_reduce_3_trx = |xor_3_trx;
+    //end TRX
+    
+    // output_io triple redundancy
+    wire [OUTPUTS - 1 : 0] output_io_signal;
+    wire [OUTPUTS - 1 : 0] output_io_signal_inst_1;
+    wire [OUTPUTS - 1 : 0] output_io_signal_inst_2;
+    wire [OUTPUTS - 1 : 0] output_io_signal_inst_3;
+    // asignations
+    // TMP assigment TODO change
+    assign led = output_io_signal[3:0];
+    // auxiliar wires
+    wire [OUTPUTS - 1 : 0] nand_1_out_io;
+    wire [OUTPUTS - 1 : 0] nand_2_out_io;
+    wire [OUTPUTS - 1 : 0] nand_3_out_io;
+    wire [OUTPUTS - 1 : 0] xor_1_out_io;
+    wire [OUTPUTS - 1 : 0] xor_2_out_io;
+    wire [OUTPUTS - 1 : 0] xor_3_out_io;
+    wire xor_reduce_1_out_io;
+    wire xor_reduce_2_out_io;
+    wire xor_reduce_3_out_io;
+
+    // Output IO  wires triple redundant
+    (* mark_debug = "true" *) assign nand_1_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_2);
+    (* mark_debug = "true" *) assign nand_2_out_io  = ~(output_io_signal_inst_2 & output_io_signal_inst_3);
+    (* mark_debug = "true" *) assign nand_3_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_3);
+    (* mark_debug = "true" *) assign output_io_signal = ~(nand_1_out_io & nand_2_out_io & nand_3_out_io);
+    // Output IO wires triple redundant detection
+    assign xor_1_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_2;
+    assign xor_2_out_io  = output_io_signal_inst_2 ^ output_io_signal_inst_3;
+    assign xor_3_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_3;
+    assign xor_reduce_1_out_io = |xor_1_out_io;
+    assign xor_reduce_2_out_io = |xor_2_out_io;
+    assign xor_reduce_3_out_io = |xor_3_out_io;
+    // end output_io
+    
+
+
+    //redundat_validation_o[0] <= (xor_reduce_1 ^ xor_reduce_2) | (xor_reduce_2 ^ xor_reduce_3);
+    //redundat_validation_o[1] <= xor_reduce_1 & xor_reduce_2 & xor_reduce_3 ;
+    //store_data_o <= ~(nand_1 & nand_2 & nand_3)};
 
     control_module #(
         .WORD_SIZE(WORD_SIZE),
@@ -54,17 +128,58 @@
         .OUTPUTS(OUTPUTS),
         .INPUTS(INPUTS)
     )
-    control_module_inst(
+    control_module_inst_1(
         .clk(clk),
         .rtx(jc_1),
         .rst(btn),
         .preescalar_data_rate(preescalar_data_rate),
-        .id(id),
-        .input_io({28'b00000000000000000000000000,sw}),
+        .input_io(input_io),
         .staus_control_module(),
-        .trx(jc_2),
+        .trx(uart_output_signal_inst_1),
         .valid_io(),
-        .output_io({28'b00000000000000000000000000,led})
+        .output_io(output_io_signal_inst_1)
+    );
+
+    control_module #(
+        .WORD_SIZE(WORD_SIZE),
+        .SIZE_WORD(SIZE_WORD),
+        .STATUS_SIGNALS(STATUS_SIGNALS),
+        .DATA_WIDTH(DATA_WIDTH),
+        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
+        .OUTPUTS(OUTPUTS),
+        .INPUTS(INPUTS)
+    )
+    control_module_inst_2(
+        .clk(clk),
+        .rtx(jc_1),
+        .rst(btn),
+        .preescalar_data_rate(preescalar_data_rate),
+        .input_io(input_io),
+        .staus_control_module(),
+        .trx(uart_output_signal_inst_2),
+        .valid_io(),
+        .output_io(output_io_signal_inst_2)
+    );
+
+    control_module #(
+        .WORD_SIZE(WORD_SIZE),
+        .SIZE_WORD(SIZE_WORD),
+        .STATUS_SIGNALS(STATUS_SIGNALS),
+        .DATA_WIDTH(DATA_WIDTH),
+        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
+        .OUTPUTS(OUTPUTS),
+        .INPUTS(INPUTS)
+    )
+    control_module_inst_3(
+        .clk(clk),
+        .rtx(jc_1),
+        .rst(btn),
+        .preescalar_data_rate(preescalar_data_rate),
+        .input_io(input_io),
+        .staus_control_module(),
+        .trx(uart_output_signal_inst_3),
+        .valid_io(),
+        .output_io(output_io_signal_inst_3)
     );
 
 endmodule