)]}'
{
  "commit": "e2f32569d0a1b4946cd94c5b8610a8204bf3d852",
  "tree": "9a03ddf4110f421689048ed054ef741f2b19acdf",
  "parents": [
    "d978d63cca4d7905c57d43a572d0ea5dab3d338d"
  ],
  "author": {
    "name": "wajehulhasan",
    "email": "wuhassan@uit.edu",
    "time": "Thu Dec 30 17:07:35 2021 +0500"
  },
  "committer": {
    "name": "wajehulhasan",
    "email": "wuhassan@uit.edu",
    "time": "Thu Dec 30 17:07:35 2021 +0500"
  },
  "message": "compressed\n",
  "tree_diff": [
    {
      "type": "delete",
      "old_id": "fb166ee305ac4e67b4b1385fd27d12d0e79571c1",
      "old_mode": 33188,
      "old_path": "verilog/gl/ram_power.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "54dbfad3c9ec412401f30e9c3d3ce08e1624c696",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_proj_example_power.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b78719345d90632f5fdfb612eacb227bea739536",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_proj_example_power.v.gz"
    }
  ]
}