blob: 66c0ead7086932cd7b12936d66a70ba011a12f23 [file] [log] [blame]
---
project:
description: "Testing."
foundry: "SkyWater"
git_url: "https://github.com/HamzaShabbir517/caravel_BrqRV_EB1.git"
organization: "Micro Electronics Research Lab (MERL)"
organization_url: "https://merledupk.org/"
owner: "Micro Electronics Research Lab (MERL)"
process: "SKY130"
project_name: "Ram Generator"
project_id: "00000001"
tags:
- "Open MPW"
- "RAM Generator"
category: "Memory"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/ram.png"