diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index e973ddd..5830735 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -83,15 +83,15 @@
             wait(mprj_io_0 == 28'd13);
             */
             // Observe Output pins [35:8] for multliplication_table
-            /*wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd15);
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
-            */
+            
             // Observe Output pins [35:8] for mean & Determinant
-            wait(mprj_io_0 == 28'd5);
+           // wait(mprj_io_0 == 28'd5);
             
             // Observe Output pins [35:8] for power
             //wait(mprj_io_0 == 28'd64);
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index a1a7a1a..5509980 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,8 +1,6 @@
 @00000000
-B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
-7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37
-D0 58 09 B7 00 23 42 91 42 95 00 54 00 54 00 A3
-01 23 42 99 02 83 00 54 03 03 00 04 83 B3 00 14
-02 83 00 62 83 33 00 24 42 8D 00 53 02 53 43 B3
-00 74 01 A3 00 79 80 23 D0 58 01 B7 0F F0 02 93
-00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF 
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+44 99 44 15 03 B7 43 01 0E 37 F0 04 03 05 D0 58
+02 64 02 B3 00 53 A0 23 00 5E 20 23 0E 11 03 91
+FE 93 17 E3 D0 58 01 B7 0F F0 02 93 00 51 80 23
+FE 00 0A E3 00 01 00 01 00 00 0F FF 
diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
index b451470..d6a3b33 100644
--- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
@@ -897,9 +897,9 @@
 		.reset_o(core_rst)
 	);
 	
-	//always @(iccm_instr_wdata) begin
-	//$display("Instruction = %h", iccm_instr_wdata);
-	//end
+	always @(iccm_instr_we) begin
+	$display("Instruction = %h", iccm_instr_wdata);
+	end
 	
 	eb1_uart_rx_prog uart_rx_m(
 		.i_Clock(clk),
@@ -15334,7 +15334,7 @@
 					.addr1(8'h00),
 					.dout1()
 				);*/
-				/*DFFRAM iccm
+				DFFRAM iccm
 					(
 					`ifdef USE_POWER_PINS
     					 .VPWR(vccd1),
@@ -15346,8 +15346,8 @@
     					 .Di(iccm_bank_wr_data[(i * 39) + 31-:32]),
     					 .Do(iccm_bank_dout[(i * 39) + 31-:32]),
     					 .A(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)])
-					);*/
-					SRAM64x32 iccm(
+					);
+					/*SRAM64x32 iccm(
 						`ifdef USE_POWER_PINS
     						.VPWR(vccd1),
     						.VGND(vssd1),
@@ -15359,7 +15359,7 @@
     						.Do(iccm_bank_dout[(i * 39) + 31-:32]),
     						.A(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)])
 );
-					
+			*/		
 			end
 			else if (pt[917-:8] == 9) begin : iccm
 				ram_512x39 iccm_bank(
@@ -20920,7 +20920,7 @@
 					.addr1(8'h00),
 					.dout1()
 				);*/
-				SRAM64x32 dccm(
+				/*SRAM64x32 dccm(
 						`ifdef USE_POWER_PINS
     						.VPWR(vccd1),
     						.VGND(vssd1),
@@ -20931,9 +20931,9 @@
     						.Di(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
     						.Do(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
     						.A(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)])
-);
+);*/
 					
-				/*DFFRAM dccm
+				DFFRAM dccm
 					(
 					`ifdef USE_POWER_PINS
     					 .VPWR(vccd1),
@@ -20945,7 +20945,7 @@
     					 .Di(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
     					 .Do(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
     					 .A(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)])
-					);*/
+					);
 			end
 			else if (DCCM_INDEX_DEPTH == 128) begin : dccm
 				ram_128x39 dccm_bank(