diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
index 99b9a94..bc4267d 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
@@ -18,35 +18,45 @@
 
 void main()
 {
+
+        /* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+
    //reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    //reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    //reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
-   //reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    //reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
   // reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
   // reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
-  //reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
-  //reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
   reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
   reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
   reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
@@ -55,24 +65,57 @@
   reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
   reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
   reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
-  reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
-  //reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;
   
   reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
 
   reg_mprj_xfer = 1;
   while(reg_mprj_xfer == 1);
-
-  reg_la2_oenb = reg_la2_iena =  0x00000002;
-  reg_la2_data = 0x00000000; // reset
-  reg_la2_data = 0x00000001;
-  reg_la2_oenb = reg_la2_iena =  0x00000003;
-  	
-  reg_la1_oenb = reg_la1_iena =  0x00000000;
-  reg_la1_data = 0x00000015C; // Clk_per_bit
+   
+  // For CPU input keep bit 1 for output from CPU keep bit 0 
+  reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+  reg_la1_oenb = reg_la1_iena = 0xFFFF0000;    // [63:32]
+  reg_la2_oenb = reg_la2_iena = 0xFFFFFFFE;    // [95:64]
+  reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
   
-  reg_la0_oenb = reg_la0_iena = 0x00000002;
-  reg_la0_data = 0x00000000;
+  // Set clk & reset to one
+  reg_la2_data = 0x00000001;
+  reg_la2_data = 0x00000000;
+  
+  // writing data into memory 1
+  reg_la0_data = 0x00000002; // 0
+  reg_la0_data = 0x0008000a; // 1 
+  reg_la0_data = 0x00100012; // 2
+  reg_la0_data = 0x0018001a; // 3 
+  reg_la0_data = 0x00200022; // 4
+  reg_la0_data = 0x0028002a; // 5 
+  reg_la0_data = 0x00300032; // 6
+  reg_la0_data = 0x0038003a; // 7
+  reg_la0_data = 0x00400042; // 8
+  reg_la0_data = 0x0048004a; // 9     
+  
+  // Turning off memory 1
+  reg_la0_data = 0x00000007;  
+  
+  // writing data into memory 2
+  reg_la0_data = 0x00000001; // 0
+  reg_la0_data = 0x00080009; // 1 
+  reg_la0_data = 0x00100011; // 2
+  reg_la0_data = 0x00180019; // 3 
+  reg_la0_data = 0x00200021; // 4
+  reg_la0_data = 0x00280029; // 5 
+  reg_la0_data = 0x00300031; // 6
+  reg_la0_data = 0x00380039; // 7
+  reg_la0_data = 0x00400041; // 8
+  reg_la0_data = 0x00480049; // 9     
+  
+  // Turning off memory 2
+  reg_la0_data = 0x00000007;  
+  reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0] 
+  reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+  reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+  reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
   reg_mprj_datah = 0x20;
 
 }
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 5830735..11394a7 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -20,7 +20,7 @@
 `include "uprj_netlists.v"
 `include "caravel_netlists.v"
 `include "spiflash.v"
-`include "tb_prog.v"
+//`include "tb_prog.v"
 
 module BrqRV_EB1_tb();
     reg clock;
@@ -32,20 +32,33 @@
     wire gpio;
     wire [37:0] mprj_io;
 
-    wire [27:0] mprj_io_0;
+    wire [7:0] mprj_io_0;
     wire mprj_ready;
+    reg [31:0] count;
     
-    assign mprj_io_0 = mprj_io[35:8];
+    assign mprj_io_0 = mprj_io[34:27];
     assign mprj_ready = mprj_io[37];
     
     assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+    assign mprj_io[8] = (mprj_ready) ? 1'b0 : 1'b1;
+    assign mprj_io[9] = (mprj_ready) ? 1'b1 : 1'b1;
+    assign mprj_io[10] = (mprj_ready) ? 1'b1 : 1'b1;
+    assign mprj_io[35] = 1'b1;
+    assign mprj_io[26:11] = (mprj_ready) ? count : 16'h0000;
     
     always #12.5 clock <= (clock === 1'b0);
     
     initial begin
         clock = 0;
+        count = 0;
     end
  
+    always @(posedge clock) begin
+    	if(mprj_ready) begin
+    		count = count + 32'd1;
+    	end
+    end
+    		
     initial begin
         $dumpfile("BrqRV_EB1.vcd");
         $dumpvars(0, BrqRV_EB1_tb);
@@ -61,7 +74,20 @@
     end
 
 	initial begin
+	    $display("I am not ready");
 	    wait(mprj_ready == 1'b1)
+	    $display("I am ready");
+	    // Memory output
+	    //wait(mprj_io_0 == 8'h00);
+	    //wait(mprj_io_0 == 8'h01);
+	    //wait(mprj_io_0 == 8'h02);
+	    //wait(mprj_io_0 == 8'h03);
+	    //wait(mprj_io_0 == 8'h04);
+	    //wait(mprj_io_0 == 8'h05);
+	    //wait(mprj_io_0 == 8'h06);
+	    //wait(mprj_io_0 == 8'h07);
+	    //wait(mprj_io_0 == 8'h08);
+	    wait(mprj_io_0 == 8'h99);
 	    // Observe Output pins [35:8] for factorial
 	    /*wait(mprj_io_0 == 28'h0000001);
 	    wait(mprj_io_0 == 28'h0000002);
@@ -83,13 +109,13 @@
             wait(mprj_io_0 == 28'd13);
             */
             // Observe Output pins [35:8] for multliplication_table
-            wait(mprj_io_0 == 28'd5);
+            /*wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd15);
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
-            
+            */
             // Observe Output pins [35:8] for mean & Determinant
            // wait(mprj_io_0 == 28'd5);
             
@@ -100,14 +126,14 @@
             //wait(mprj_io_0 == 28'd4889874);
             
             // Observe Output pins [35:8] for Queue 
-            //wait(mprj_io_0 == 28'd5);
-            //wait(mprj_io_0 == 28'd6);
-            //wait(mprj_io_0 == 28'd7);
-            
+            /*wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd7);
+            */
             // Observe Output pins [35:8] for perfect square
             //wait(mprj_io_0 == 28'd5);
             
-            // Observe Output pins [35:8] for counter / ascending / reverse
+            // Observe Output pins [35:8] for counter / ascending
             /*wait(mprj_io_0 == 28'd0);
             wait(mprj_io_0 == 28'd1);
             wait(mprj_io_0 == 28'd2);
@@ -121,11 +147,25 @@
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd11);
             */
-            //wait(mprj_io_0 == 28'd3);
-            //wait(mprj_io_0 == 28'd2);
-            //wait(mprj_io_0 == 28'd1);
-            //wait(mprj_io_0 == 28'd0);
-            $display("MPRJ-IO state = %d", mprj_io[35:8]);  
+            // Observe Output pin [35:8] for reverse
+            /*wait(mprj_io_0 == 28'd15);
+            wait(mprj_io_0 == 28'd14);
+            wait(mprj_io_0 == 28'd13);
+            wait(mprj_io_0 == 28'd12);
+            wait(mprj_io_0 == 28'd11);
+            wait(mprj_io_0 == 28'd10);
+            wait(mprj_io_0 == 28'd9);
+            wait(mprj_io_0 == 28'd8);
+            wait(mprj_io_0 == 28'd7);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd4); 
+            wait(mprj_io_0 == 28'd3);
+            wait(mprj_io_0 == 28'd2);
+            wait(mprj_io_0 == 28'd1);
+            wait(mprj_io_0 == 28'd0);
+            */
+            //$display("MPRJ-IO state = %d", mprj_io[35:8]);  
 		
 		`ifdef GL
 	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -161,16 +201,14 @@
 	end
 	
 	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %d, at time = %0t  ", mprj_io[35:8], $time);
+		$display("MPRJ-IO state = %h, at time = %0t  ", mprj_io[34:27], $time);
 	end
 	
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire r_Rx_Serial;
-	assign mprj_io[5] = r_Rx_Serial;
-	assign mprj_io[3:0] = 4'h0;
+	//assign mprj_io[3:0] = 4'h0;
 
 	wire VDD3V3 = power1;
 	wire VDD1V8 = power2;
@@ -185,12 +223,12 @@
 		.vssa	  (VSS),
 		.vccd	  (VDD1V8),
 		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
 		.vssa1	  (VSS),
 		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
 		.vssd1	  (VSS),
 		.vssd2	  (VSS),
 		.clock	  (clock),
@@ -215,13 +253,14 @@
 	);
 	
 	
-	uartprog #(
+	/*uartprog #(
 		.FILENAME("../hex/uart.hex")
 	) prog_uut (
 		//.clk(clock),
 		.mprj_ready (mprj_ready),
 		.r_Rx_Serial (r_Rx_Serial)
-	);
+	);*/
 
 endmodule
 `default_nettype wire
+    
diff --git a/verilog/dv/BrqRV_EB1/Makefile b/verilog/dv/BrqRV_EB1/Makefile
index 1cfd1c1..ba427e6 100644
--- a/verilog/dv/BrqRV_EB1/Makefile
+++ b/verilog/dv/BrqRV_EB1/Makefile
@@ -25,7 +25,7 @@
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/BrqRV_EB1/
+UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/rams/ram_256x32_2r1w/
 UPRJ_BEHAVIOURAL_MODELS = ../
 
 ## RISCV GCC 
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/Makefile b/verilog/rtl/rams/ram_256x32_2r1w/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v
new file mode 100644
index 0000000..90b67bb
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v
@@ -0,0 +1,184 @@
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+                   
+//`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 256,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 8,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @(Addr_sel or addr or web or csb) begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @(Addr_sel_1 or addr1 or csb1) begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v
new file mode 100644
index 0000000..d7b2f26
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v
@@ -0,0 +1,81 @@
+
+//`include "utils.vh"
+module ram_generic_nr1w
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 256,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 2 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 8,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  vccd1,
+  vssd1,
+`endif
+  addr, clk, csb, web, wmask, din, dout, addr1, csb1, clk1, dout1);
+  `ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+  `endif
+  input  clk; // clock
+  input  csb; // active low chip select
+  input  web; // active low write control
+  input [NUM_WMASKS-1:0]  wmask; // write mask
+  input [ADDR_WIDTH * nRPORTS-1:0] addr;
+  input [DATA_WIDTH-1:0]  din;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout;
+  input clk1;
+  input csb1;
+  input [ADDR_WIDTH * nRPORTS-1:0] addr1;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout1;
+    // unpacked read addresses/data
+  reg  [ADDR_WIDTH-1:0] RAddr_upk [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk [nRPORTS-1:0]; // read data      - unpacked 2D array 
+  reg  [ADDR_WIDTH-1:0] RAddr_upk_1 [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk_1 [nRPORTS-1:0]; // read data      - unpacked 2D array 
+
+  // unpack read addresses; pack read data
+  `ARRINIT;
+  always @* begin
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr,RAddr_upk);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk,dout);
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr1,RAddr_upk_1);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk_1,dout1);
+  end
+genvar rpi;
+  generate
+    for (rpi=0 ; rpi<nRPORTS; rpi=rpi+1) begin
+    ram_generic_1rw #( .NUM_WMASKS (NUM_WMASKS),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATA_WIDTH), // data width
+                    .nRPORTS(1), // number of reading ports
+      		    .nWPORTS(1), // number of write ports
+     		    .IZERO  (IZERO), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (IFILE),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDR_WIDTH),
+     		    .DELAY (DELAY),
+     		    .BYPASS(BYPASS))
+    ram_1rw      ( `ifdef USE_POWER_PINS
+    		    .vccd1(vccd1),
+    		    .vssd1(vssd1),
+    		    `endif
+    		    .clk(clk), // clock
+  		    .csb(csb), // active low chip select
+  		    .web(web), // active low write control
+  		    .wmask(wmask), // write mask
+  		    .addr(RAddr_upk[rpi]/*(web == 0) ? RAddr_upk[0] : RAddr_upk[rpi]*/),
+  		    .din(din),
+   		    .dout(RData_upk[rpi]),
+                    .clk1(clk1),
+                    .csb1(csb1), 
+                    .addr1(RAddr_upk_1[rpi]),
+                    .dout1(RData_upk_1[rpi]));
+    end
+  endgenerate
+endmodule
+
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v
new file mode 100644
index 0000000..3cc323c
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v
@@ -0,0 +1,289 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   256
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 2
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 8
+`endif
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+module ram_generic_nr1w_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+  reg                      clk = 1'b0                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+   
+  initial begin
+  	$dumpfile("srimulation.vcd");
+  	$dumpvars(0,ram_generic_nr1w_tb);
+  end
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"===============================Simulation Results======================================\n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fwrite(rep_fd,"Golden   Golden     Golden          Actual       Actual     Actual          Result   \n");
+      $fwrite(rep_fd,"Read     Model      Model           Read         Model      Model                    \n");
+      $fwrite(rep_fd,"Port     RAddr      RData           Port         RAddr      RData                    \n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fclose(rep_fd);
+    end
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n",ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end
+
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        );
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR2D1D(nRPORTS,DATAW,RData_upk_golden ,RData_pck_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+    // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+integer p;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        
+        //if (cycc==CYCC) begin
+        for(p=0; p<nRPORTS; p=p+1) begin
+            pass = (RData_upk_golden[p]===RData_upk_sram[p]);
+    	    rep_fd = $fopen("sim.txt","a+");
+            $fwrite(rep_fd,"%-10d %-10d %-15h %-10d %-10d %-15h %-10s \n",p,RAddr_upk[p],RData_upk_golden[p],p,RAddr_upk[p],RData_upk_sram[p],pass?"pass":"fail");
+            $fclose(rep_fd);
+        end
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r,s;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+//      $readmemh("init_ram.hex", mem);
+        for(r=0; r<MEMD; r=r+1) mem[r] = {DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(s=0; s<`WMASK; s=s+1) begin
+    		if(wmask_pck[s])
+        		mem[WAddr_pck][8*s +: 8] = WData_pck[8*s +: 8];
+    	end
+    end
+   else begin
+      for(q=0; q<nRPORTS; q=q+1) begin
+        RData_upk_golden[q] <= #(10) mem[RAddr_upk[q]];
+      end
+   end
+  end
+
+
+ram_generic_nr1w #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDRW),
+     		    .DELAY (3))
+ram_nr1w          ( `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)? {nRPORTS{WAddr_pck}}:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW*nRPORTS{1'b0}}),
+                    .dout1());
+endmodule
+
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/sim.txt b/verilog/rtl/rams/ram_256x32_2r1w/sim.txt
new file mode 100644
index 0000000..eb7b9fa
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/sim.txt
@@ -0,0 +1,2006 @@
+===============================Simulation Results======================================
+=======================================================================================
+Golden   Golden     Golden          Actual       Actual     Actual          Result   
+Read     Model      Model           Read         Model      Model                    
+Port     RAddr      RData           Port         RAddr      RData                    
+=======================================================================================
+0          100        00000000        0          100        00000000        pass       
+1          135        00000000        1          135        00000000        pass       
+0          172        00000000        0          172        00000000        pass       
+1          217        00000000        1          217        00000000        pass       
+0          1          00000000        0          1          00000000        pass       
+1          2          00000000        1          2          00000000        pass       
+0          70         00000000        0          70         00000000        pass       
+1          116        00000000        1          116        00000000        pass       
+0          160        00000000        0          160        00000000        pass       
+1          134        00000000        1          134        00000000        pass       
+0          152        00000000        0          152        00000000        pass       
+1          40         00000000        1          40         00000000        pass       
+0          174        00000000        0          174        00000000        pass       
+1          181        00000000        1          181        00000000        pass       
+0          35         00000000        0          35         00000000        pass       
+1          201        00000000        1          201        00000000        pass       
+0          172        00000000        0          172        00000000        pass       
+1          180        00000000        1          180        00000000        pass       
+0          92         00000000        0          92         00000000        pass       
+1          104        00000000        1          104        00000000        pass       
+0          69         00000000        0          69         00000000        pass       
+1          110        00000000        1          110        00000000        pass       
+0          249        00000000        0          249        00000000        pass       
+1          98         00000000        1          98         00000000        pass       
+0          226        00000000        0          226        00000000        pass       
+1          13         00000000        1          13         00000000        pass       
+0          97         00000000        0          97         00000000        pass       
+1          124        00000000        1          124        00000000        pass       
+0          214        00000000        0          214        00000000        pass       
+1          146        00000000        1          146        00000000        pass       
+0          46         00000000        0          46         00000000        pass       
+1          130        00000000        1          130        00000000        pass       
+0          242        00000000        0          242        00000000        pass       
+1          213        00000000        1          213        00000000        pass       
+0          125        00000000        0          125        00000000        pass       
+1          238        00000000        1          238        00000000        pass       
+0          196        00000000        0          196        00000000        pass       
+1          223        00000000        1          223        00000000        pass       
+0          13         00000000        0          13         00000000        pass       
+1          235        00000000        1          235        00000000        pass       
+0          14         00008dab        0          14         00008dab        pass       
+1          246        00000000        1          246        00000000        pass       
+0          255        006a00d8        0          255        006a00d8        pass       
+1          159        00000000        1          159        00000000        pass       
+0          9          00000000        0          9          00000000        pass       
+1          226        03004500        1          226        03004500        pass       
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diff --git a/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..428a5a7
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,122 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 0 ;
+  parameter VERBOSE = 0 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 0 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+   // $display("hey");
+    //#(T_HOLD) dout0 = 32'bx;
+    //if ( !csb0_reg && web0_reg && VERBOSE ) 
+    //  $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    //if ( !csb0_reg && !web0_reg && VERBOSE )
+    //  $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    //if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+    //    $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    //if ( !csb1_reg && VERBOSE ) 
+    // $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+//integer i;
+//initial
+    //if (IZERO)
+  //    for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule
diff --git a/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd b/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd
new file mode 100644
index 0000000..55bd769
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd
@@ -0,0 +1,53164 @@
+$date
+	Wed Nov 24 03:18:12 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_nr1w_tb $end
+$var wire 64 ! RData_pck_sram [63:0] $end
+$var reg 16 " RAddr_pck [15:0] $end
+$var reg 64 # RData_pck_golden [63:0] $end
+$var reg 8 $ WAddr_pck [7:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 p [31:0] $end
+$var integer 32 3 pass [31:0] $end
+$var integer 32 4 q [31:0] $end
+$var integer 32 5 r [31:0] $end
+$var integer 32 6 rep_fd [31:0] $end
+$var integer 32 7 s [31:0] $end
+$scope module ram_nr1w $end
+$var wire 16 8 addr [15:0] $end
+$var wire 16 9 addr1 [15:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 < din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 > wmask [3:0] $end
+$var reg 64 ? dout [63:0] $end
+$var reg 64 @ dout1 [63:0] $end
+$var integer 32 A _i_ [31:0] $end
+$scope begin genblk1[0] $end
+$scope module ram_1rw $end
+$var wire 8 B addr [7:0] $end
+$var wire 8 C addr1 [7:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 D din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 E wmask [3:0] $end
+$var wire 1 F Addr_sel_1 $end
+$var wire 1 G Addr_sel $end
+$var reg 32 H RData_out [31:0] $end
+$var reg 32 I RData_out_1 [31:0] $end
+$var reg 1 J Raddr_sel $end
+$var reg 1 K Raddr_sel_1 $end
+$var reg 32 L dout [31:0] $end
+$var reg 32 M dout1 [31:0] $end
+$var reg 1 N web_reg $end
+$var integer 32 O i [31:0] $end
+$var integer 32 P j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Q addr0 [7:0] $end
+$var wire 8 R addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 S csb0 $end
+$var wire 1 T csb1 $end
+$var wire 32 U din0 [31:0] $end
+$var wire 1 V web0 $end
+$var wire 4 W wmask0 [3:0] $end
+$var reg 8 X addr0_reg [7:0] $end
+$var reg 8 Y addr1_reg [7:0] $end
+$var reg 1 Z csb0_reg $end
+$var reg 1 [ csb1_reg $end
+$var reg 32 \ din0_reg [31:0] $end
+$var reg 32 ] dout0 [31:0] $end
+$var reg 32 ^ dout1 [31:0] $end
+$var reg 1 _ web0_reg $end
+$var reg 4 ` wmask0_reg [3:0] $end
+$var integer 32 a i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope module ram_1rw $end
+$var wire 8 b addr [7:0] $end
+$var wire 8 c addr1 [7:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 d din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 e wmask [3:0] $end
+$var wire 1 f Addr_sel_1 $end
+$var wire 1 g Addr_sel $end
+$var reg 32 h RData_out [31:0] $end
+$var reg 32 i RData_out_1 [31:0] $end
+$var reg 1 j Raddr_sel $end
+$var reg 1 k Raddr_sel_1 $end
+$var reg 32 l dout [31:0] $end
+$var reg 32 m dout1 [31:0] $end
+$var reg 1 n web_reg $end
+$var integer 32 o i [31:0] $end
+$var integer 32 p j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 q addr0 [7:0] $end
+$var wire 8 r addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 s csb0 $end
+$var wire 1 t csb1 $end
+$var wire 32 u din0 [31:0] $end
+$var wire 1 v web0 $end
+$var wire 4 w wmask0 [3:0] $end
+$var reg 8 x addr0_reg [7:0] $end
+$var reg 8 y addr1_reg [7:0] $end
+$var reg 1 z csb0_reg $end
+$var reg 1 { csb1_reg $end
+$var reg 32 | din0_reg [31:0] $end
+$var reg 32 } dout0 [31:0] $end
+$var reg 32 ~ dout1 [31:0] $end
+$var reg 1 !" web0_reg $end
+$var reg 4 "" wmask0_reg [3:0] $end
+$var integer 32 #" i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope task genInitFiles $end
+$var reg 32 $" DEPTH [31:0] $end
+$var reg 160 %" FILEN [1:160] $end
+$var reg 256 &" INITVAL [255:0] $end
+$var reg 1 '" RAND $end
+$var reg 32 (" WIDTH [31:0] $end
+$var reg 256 )" ramdata [255:0] $end
+$var integer 32 *" addr [31:0] $end
+$var integer 32 +" hex_fd [31:0] $end
+$var integer 32 ," mif_fd [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000000000000000000000100 ,"
+b10000000000000000000000000000011 +"
+b100000000 *"
+b10101101111001111101000001011011 )"
+b100000 ("
+1'"
+b0 &"
+b110100101101110011010010111010001011111011100100110000101101101 %"
+b100000000 $"
+b100000000 #"
+bx ""
+x!"
+bx ~
+bx }
+bx |
+x{
+xz
+bx y
+bx x
+bx w
+xv
+bx u
+1t
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+bx q
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+bx i
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+0f
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+bx b
+b100000000 a
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+x[
+xZ
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+xV
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+xS
+b0 R
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+xG
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+b0 C
+bx B
+b11 A
+bx @
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+x=
+bx <
+1;
+0:
+b0 9
+bx 8
+bx 7
+b10000000000000000000000000000011 6
+b100000000 5
+bx 4
+bx 3
+bx 2
+bx 1
+bx 0
+b1 /
+bx .
+bx -
+x,
+x+
+1*
+x)
+x(
+0'
+x&
+bx %
+bx $
+bx #
+bx "
+bx !
+$end
+#5
+0K
+0k
+b0 Y
+1[
+b1 P
+b0 y
+1{
+b1 p
+b10 4
+1'
+#10
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+0S
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+b100101011100 "
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+b101000110001100010011101010001 %
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+b101000110001100010011101010001 d
+b101000110001100010011101010001 u
+0(
+0)
+b0 1
+0+
+0,
+b1 0
+0'
+#15
+1n
+0j
+1N
+0J
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+b101000110001100010011101010001 |
+b1001 x
+b0 ""
+1!"
+0z
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+b101000110001100010011101010001 \
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+1_
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+1'
+#20
+b110001 q
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+b11000110011101 8
+b11001100 $
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+b11000110011101 "
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+b10101000100111101110100101010 d
+b10101000100111101110100101010 u
+0(
+0)
+0+
+0,
+b10 0
+0'
+#23
+b0 }
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+#25
+b0 #
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+b0 l
+b10101000100111101110100101010 \
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+b1110010001110010 8
+b101100 $
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+b1110010001110010 "
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+b1010111110000011101000110101111 %
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+b1010111110000011101000110101111 U
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+b1010111110000011101000110101111 u
+0(
+0)
+0+
+0,
+b1 0
+0'
+#35
+b10 4
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+b1010111110000011101000110101111 |
+b11100100 x
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+b1010111110000011101000110101111 \
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+1'
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+b11010001 q
+b1 o
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+b1101000100111000 8
+b11100110 $
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+0(
+0)
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+0'
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+b10110101010101011101111001101010 \
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+b11010001 x
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+0!"
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+1'
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+b1101100110101100 8
+1=
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+b10111010111101001110001001110101 u
+0(
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+0'
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+b1111010111101101010101111110101 u
+0(
+0)
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+#95
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+0!"
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+0_
+1'
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+b111101 q
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+b11110100111101 8
+b111101 $
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+b1 w
+b1000011010100000 "
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+b10110110010111111100100101101 %
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+b10110110010111111100100101101 d
+b10110110010111111100100101101 u
+0(
+0)
+0+
+0,
+b10 0
+0'
+#105
+b10110110010111111100100101101 \
+b111101 X
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+b10110110010111111100100101101 |
+b111101 x
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+1'
+#106
+b110 /
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+#110
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+b1011110 b
+b1011110 B
+b11 A
+b101111001011110 8
+b1011110 $
+b110 -
+b110 >
+b110 E
+b110 W
+b110 e
+b110 w
+b10100010011000 "
+b11 .
+1&
+b100110101111110011111101001101 %
+b100110101111110011111101001101 <
+b100110101111110011111101001101 D
+b100110101111110011111101001101 U
+b100110101111110011111101001101 d
+b100110101111110011111101001101 u
+0(
+0)
+0+
+0,
+b1 0
+0'
+#115
+b100 7
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+b100110101111110011111101001101 |
+b1011110 x
+b110 ""
+b1 P
+b100110101111110011111101001101 \
+b1011110 X
+b110 `
+1'
+#116
+b111 /
+b10 2
+#120
+b1111010 q
+b1 o
+b1111010 Q
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diff --git a/verilog/rtl/rams/ram_256x32_2r1w/utils.vh b/verilog/rtl/rams/ram_256x32_2r1w/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__
diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean
diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v
new file mode 100644
index 0000000..35c2bd5
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v
@@ -0,0 +1,159 @@
+`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+
diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v
new file mode 100644
index 0000000..8009039
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v
@@ -0,0 +1,287 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   512
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 1
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 9
+`endif
+
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+
+
+module ram_generic_1rw_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+
+  reg                      clk = 1'b1                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+  
+  initial begin
+  $dumpfile("simulation.vcd");
+  $dumpvars(0,ram_generic_1rw_tb);
+  end
+
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"=======================Simulation Results======================\n");
+      $fwrite(rep_fd,"===============================================================\n");
+      $fwrite(rep_fd,"Golden   Golden           Actual      Actual          Result   \n");
+      $fwrite(rep_fd,"Model    Model            Model       Model                    \n");
+      $fwrite(rep_fd,"RAddr    RData            RAddr       RData                    \n");
+      $fwrite(rep_fd,"===============================================================\n");
+      $fclose(rep_fd);
+    end
+   // rep_fd = $fopen("sim.txt","a+");
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n"  ,ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    //$fclose(rep_fd);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end   
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        ); 
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_golden ,RData_upk_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+   // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+    
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        pass = (RData_pck_golden===RData_pck_sram);
+        //if (cycc==CYCC) begin
+    	rep_fd = $fopen("sim.txt","a+");
+        $fwrite(rep_fd,"%-10d %-15h %-10d %-15h %-10s \n",RAddr_pck,RData_pck_golden,RAddr_pck,RData_pck_sram,pass?"pass":"fail");
+        $fclose(rep_fd);
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+      //$readmemh("init_ram.hex", mem);
+      for(q=0; q<MEMD; q=q+1) mem[q] ={DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(r=0; r<`WMASK; r=r+1) begin
+    		if(wmask_pck[r])
+        		mem[WAddr_pck][8*r +: 8] = WData_pck[8*r +: 8];
+    	end
+    end
+   else
+        RData_pck_golden <= #(10) mem[RAddr_pck];
+  end
+
+// Actual Model
+ram_generic_1rw #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE(""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(`log2(MEMD)),
+     		    .DELAY (3))
+ram_1rw          (  `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)?WAddr_pck:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW{1'b0}}),
+                    .dout1());
+endmodule
+
diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt
new file mode 100644
index 0000000..e55150a
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt
@@ -0,0 +1,1006 @@
+=======================Simulation Results======================
+===============================================================
+Golden   Golden           Actual      Actual          Result   
+Model    Model            Model       Model                    
+RAddr    RData            RAddr       RData                    
+===============================================================
+185        00000000        185        00000000        pass       
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diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd
new file mode 100644
index 0000000..5018e38
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd
@@ -0,0 +1,40667 @@
+$date
+	Wed Nov 24 03:19:06 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_1rw_tb $end
+$var wire 32 ! RData_pck_sram [31:0] $end
+$var reg 9 " RAddr_pck [8:0] $end
+$var reg 32 # RData_pck_golden [31:0] $end
+$var reg 9 $ WAddr_pck [8:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 pass [31:0] $end
+$var integer 32 3 q [31:0] $end
+$var integer 32 4 r [31:0] $end
+$var integer 32 5 rep_fd [31:0] $end
+$scope module ram_1rw $end
+$var wire 9 6 addr [8:0] $end
+$var wire 9 7 addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 8 csb $end
+$var wire 1 9 csb1 $end
+$var wire 32 : din [31:0] $end
+$var wire 1 ; web $end
+$var wire 4 < wmask [3:0] $end
+$var wire 2 = Addr_sel_1 [1:0] $end
+$var wire 2 > Addr_sel [1:0] $end
+$var reg 32 ? RData_out [31:0] $end
+$var reg 32 @ RData_out_1 [31:0] $end
+$var reg 2 A Raddr_sel [1:0] $end
+$var reg 2 B Raddr_sel_1 [1:0] $end
+$var reg 32 C dout [31:0] $end
+$var reg 32 D dout1 [31:0] $end
+$var reg 1 E web_reg $end
+$var integer 32 F i [31:0] $end
+$var integer 32 G j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 H addr0 [7:0] $end
+$var wire 8 I addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 J csb0 $end
+$var wire 1 K csb1 $end
+$var wire 32 L din0 [31:0] $end
+$var wire 1 M web0 $end
+$var wire 4 N wmask0 [3:0] $end
+$var reg 8 O addr0_reg [7:0] $end
+$var reg 8 P addr1_reg [7:0] $end
+$var reg 1 Q csb0_reg $end
+$var reg 1 R csb1_reg $end
+$var reg 32 S din0_reg [31:0] $end
+$var reg 32 T dout0 [31:0] $end
+$var reg 32 U dout1 [31:0] $end
+$var reg 1 V web0_reg $end
+$var reg 4 W wmask0_reg [3:0] $end
+$var integer 32 X i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Y addr0 [7:0] $end
+$var wire 8 Z addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 [ csb0 $end
+$var wire 1 \ csb1 $end
+$var wire 32 ] din0 [31:0] $end
+$var wire 1 ^ web0 $end
+$var wire 4 _ wmask0 [3:0] $end
+$var reg 8 ` addr0_reg [7:0] $end
+$var reg 8 a addr1_reg [7:0] $end
+$var reg 1 b csb0_reg $end
+$var reg 1 c csb1_reg $end
+$var reg 32 d din0_reg [31:0] $end
+$var reg 32 e dout0 [31:0] $end
+$var reg 32 f dout1 [31:0] $end
+$var reg 1 g web0_reg $end
+$var reg 4 h wmask0_reg [3:0] $end
+$var integer 32 i i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope task genInitFiles $end
+$var reg 32 j DEPTH [31:0] $end
+$var reg 160 k FILEN [1:160] $end
+$var reg 256 l INITVAL [255:0] $end
+$var reg 1 m RAND $end
+$var reg 32 n WIDTH [31:0] $end
+$var reg 256 o ramdata [255:0] $end
+$var integer 32 p addr [31:0] $end
+$var integer 32 q hex_fd [31:0] $end
+$var integer 32 r mif_fd [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..1a195b3
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,121 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+        $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+     $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+integer i;
+initial
+    //if (IZERO)
+      for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule
diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v
new file mode 100644
index 0000000..35c2bd5
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v
@@ -0,0 +1,159 @@
+`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v
new file mode 100644
index 0000000..95edafa
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v
@@ -0,0 +1,80 @@
+`include "utils.vh"
+module ram_generic_nr1w
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 2 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  vccd1,
+  vssd1,
+`endif
+  addr, clk, csb, web, wmask, din, dout, addr1, csb1, clk1, dout1);
+  `ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+  `endif
+  input  clk; // clock
+  input  csb; // active low chip select
+  input  web; // active low write control
+  input [NUM_WMASKS-1:0]  wmask; // write mask
+  input [ADDR_WIDTH * nRPORTS-1:0] addr;
+  input [DATA_WIDTH-1:0]  din;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout;
+  input clk1;
+  input csb1;
+  input [ADDR_WIDTH * nRPORTS-1:0] addr1;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout1;
+    // unpacked read addresses/data
+  reg  [ADDR_WIDTH-1:0] RAddr_upk [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk [nRPORTS-1:0]; // read data      - unpacked 2D array 
+  reg  [ADDR_WIDTH-1:0] RAddr_upk_1 [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk_1 [nRPORTS-1:0]; // read data      - unpacked 2D array 
+
+  // unpack read addresses; pack read data
+  `ARRINIT;
+  always @* begin
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr,RAddr_upk);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk,dout);
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr1,RAddr_upk_1);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk_1,dout1);
+  end
+genvar rpi;
+  generate
+    for (rpi=0 ; rpi<nRPORTS; rpi=rpi+1) begin
+    ram_generic_1rw #( .NUM_WMASKS (NUM_WMASKS),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATA_WIDTH), // data width
+                    .nRPORTS(1), // number of reading ports
+      		    .nWPORTS(1), // number of write ports
+     		    .IZERO  (IZERO), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (IFILE),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDR_WIDTH),
+     		    .DELAY (DELAY),
+     		    .BYPASS(BYPASS))
+    ram_1rw      ( `ifdef USE_POWER_PINS
+    		    .vccd1(vccd1),
+    		    .vssd1(vssd1),
+    		    `endif
+    		    .clk(clk), // clock
+  		    .csb(csb), // active low chip select
+  		    .web(web), // active low write control
+  		    .wmask(wmask), // write mask
+  		    .addr(RAddr_upk[rpi]/*(web == 0) ? RAddr_upk[0] : RAddr_upk[rpi]*/),
+  		    .din(din),
+   		    .dout(RData_upk[rpi]),
+                    .clk1(clk1),
+                    .csb1(csb1), 
+                    .addr1(RAddr_upk_1[rpi]),
+                    .dout1(RData_upk_1[rpi]));
+    end
+  endgenerate
+endmodule
+
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v
new file mode 100644
index 0000000..49cb7a9
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v
@@ -0,0 +1,289 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   512
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 2
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 9
+`endif
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+module ram_generic_nr1w_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+  reg                      clk = 1'b0                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+   
+  initial begin
+  	$dumpfile("srimulation.vcd");
+  	$dumpvars(0,ram_generic_nr1w_tb);
+  end
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"===============================Simulation Results======================================\n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fwrite(rep_fd,"Golden   Golden     Golden          Actual       Actual     Actual          Result   \n");
+      $fwrite(rep_fd,"Read     Model      Model           Read         Model      Model                    \n");
+      $fwrite(rep_fd,"Port     RAddr      RData           Port         RAddr      RData                    \n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fclose(rep_fd);
+    end
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n",ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end
+
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        );
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR2D1D(nRPORTS,DATAW,RData_upk_golden ,RData_pck_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+    // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+integer p;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        
+        //if (cycc==CYCC) begin
+        for(p=0; p<nRPORTS; p=p+1) begin
+            pass = (RData_upk_golden[p]===RData_upk_sram[p]);
+    	    rep_fd = $fopen("sim.txt","a+");
+            $fwrite(rep_fd,"%-10d %-10d %-15h %-10d %-10d %-15h %-10s \n",p,RAddr_upk[p],RData_upk_golden[p],p,RAddr_upk[p],RData_upk_sram[p],pass?"pass":"fail");
+            $fclose(rep_fd);
+        end
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r,s;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+//      $readmemh("init_ram.hex", mem);
+        for(r=0; r<MEMD; r=r+1) mem[r] = {DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(s=0; s<`WMASK; s=s+1) begin
+    		if(wmask_pck[s])
+        		mem[WAddr_pck][8*s +: 8] = WData_pck[8*s +: 8];
+    	end
+    end
+   else begin
+      for(q=0; q<nRPORTS; q=q+1) begin
+        RData_upk_golden[q] <= #(10) mem[RAddr_upk[q]];
+      end
+   end
+  end
+
+
+ram_generic_nr1w #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDRW),
+     		    .DELAY (3))
+ram_nr1w          ( `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)? {nRPORTS{WAddr_pck}}:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW*nRPORTS{1'b0}}),
+                    .dout1());
+endmodule
+
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt
new file mode 100644
index 0000000..405adfa
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt
@@ -0,0 +1,2006 @@
+===============================Simulation Results======================================
+=======================================================================================
+Golden   Golden     Golden          Actual       Actual     Actual          Result   
+Read     Model      Model           Read         Model      Model                    
+Port     RAddr      RData           Port         RAddr      RData                    
+=======================================================================================
+0          51         00000000        0          51         00000000        pass       
+1          86         00000000        1          86         00000000        pass       
+0          314        00000000        0          314        00000000        pass       
+1          376        00000000        1          376        00000000        pass       
+0          300        00000000        0          300        00000000        pass       
+1          26         00000000        1          26         00000000        pass       
+0          416        00000000        0          416        00000000        pass       
+1          209        00000000        1          209        00000000        pass       
+0          332        00000000        0          332        00000000        pass       
+1          337        00000000        1          337        00000000        pass       
+0          384        00000000        0          384        00000000        pass       
+1          72         00000000        1          72         00000000        pass       
+0          319        00000000        0          319        00000000        pass       
+1          356        00000000        1          356        00000000        pass       
+0          232        00000000        0          232        00000000        pass       
+1          266        00000000        1          266        00000000        pass       
+0          364        00000000        0          364        00000000        pass       
+1          350        00000000        1          350        00000000        pass       
+0          404        00000000        0          404        00000000        pass       
+1          60         00000000        1          60         00000000        pass       
+0          278        00000000        0          278        00000000        pass       
+1          162        00000000        1          162        00000000        pass       
+0          305        00000000        0          305        00000000        pass       
+1          341        00000000        1          341        00000000        pass       
+0          8          00000000        0          8          00000000        pass       
+1          319        00000000        1          319        00000000        pass       
+0          94         00000000        0          94         00000000        pass       
+1          125        00000000        1          125        00000000        pass       
+0          436        00000000        0          436        00000000        pass       
+1          52         00000000        1          52         00000000        pass       
+0          180        00000000        0          180        00000000        pass       
+1          100        00000000        1          100        00000000        pass       
+0          461        00000000        0          461        00000000        pass       
+1          171        00000000        1          171        00000000        pass       
+0          480        00000000        0          480        00000000        pass       
+1          285        00000000        1          285        00000000        pass       
+0          364        00000000        0          364        00000000        pass       
+1          176        00000000        1          176        00000000        pass       
+0          79         00000000        0          79         00000000        pass       
+1          285        00000000        1          285        00000000        pass       
+0          63         00000000        0          63         00000000        pass       
+1          84         00000000        1          84         00000000        pass       
+0          390        00000000        0          390        00000000        pass       
+1          184        00000000        1          184        00000000        pass       
+0          424        00000000        0          424        00000000        pass       
+1          286        00000000        1          286        00000000        pass       
+0          425        00000000        0          425        00000000        pass       
+1          53         00000000        1          53         00000000        pass       
+0          225        00000000        0          225        00000000        pass       
+1          295        00000000        1          295        00000000        pass       
+0          201        00000000        0          201        00000000        pass       
+1          133        00000000        1          133        00000000        pass       
+0          61         00000000        0          61         00000000        pass       
+1          283        00000000        1          283        00000000        pass       
+0          47         00000000        0          47         00000000        pass       
+1          492        00000000        1          492        00000000        pass       
+0          356        00000000        0          356        00000000        pass       
+1          145        00000000        1          145        00000000        pass       
+0          28         00000000        0          28         00000000        pass       
+1          42         00000000        1          42         00000000        pass       
+0          376        00000000        0          376        00000000        pass       
+1          93         00000000        1          93         00000000        pass       
+0          436        00000000        0          436        00000000        pass       
+1          4          00000000        1          4          00000000        pass       
+0          425        00000000        0          425        00000000        pass       
+1          221        00000000        1          221        00000000        pass       
+0          434        00000000        0          434        00000000        pass       
+1          11         00000000        1          11         00000000        pass       
+0          416        00000000        0          416        00000000        pass       
+1          117        00000000        1          117        00000000        pass       
+0          252        00000000        0          252        00000000        pass       
+1          351        00000000        1          351        00000000        pass       
+0          25         00000000        0          25         00000000        pass       
+1          83         00000000        1          83         00000000        pass       
+0          289        00000000        0          289        00000000        pass       
+1          104        00000000        1          104        00000000        pass       
+0          503        00000000        0          503        00000000        pass       
+1          317        00000000        1          317        00000000        pass       
+0          0          00000000        0          0          00000000        pass       
+1          112        00000000        1          112        00000000        pass       
+0          35         00000000        0          35         00000000        pass       
+1          330        00000000        1          330        00000000        pass       
+0          113        00000000        0          113        00000000        pass       
+1          275        00000000        1          275        00000000        pass       
+0          244        00000000        0          244        00000000        pass       
+1          467        00000000        1          467        00000000        pass       
+0          293        00000000        0          293        00000000        pass       
+1          227        00000000        1          227        00000000        pass       
+0          96         00000000        0          96         00000000        pass       
+1          207        00000000        1          207        00000000        pass       
+0          152        00000000        0          152        00000000        pass       
+1          248        00000000        1          248        00000000        pass       
+0          224        00000000        0          224        00000000        pass       
+1          404        00000000        1          404        00000000        pass       
+0          59         00000000        0          59         00000000        pass       
+1          156        00000000        1          156        00000000        pass       
+0          301        00000000        0          301        00000000        pass       
+1          263        00000000        1          263        00000000        pass       
+0          235        00000000        0          235        00000000        pass       
+1          82         00000000        1          82         00000000        pass       
+0          372        00000000        0          372        00000000        pass       
+1          498        00000000        1          498        00000000        pass       
+0          396        00000000        0          396        00000000        pass       
+1          399        00000000        1          399        00000000        pass       
+0          54         00000000        0          54         00000000        pass       
+1          501        00000000        1          501        00000000        pass       
+0          147        00000000        0          147        00000000        pass       
+1          452        00000000        1          452        00000000        pass       
+0          163        00000000        0          163        00000000        pass       
+1          407        00000000        1          407        00000000        pass       
+0          180        00000000        0          180        00000000        pass       
+1          371        00000000        1          371        00000000        pass       
+0          205        00000000        0          205        00000000        pass       
+1          215        00000000        1          215        00000000        pass       
+0          135        00000000        0          135        00000000        pass       
+1          44         00000000        1          44         00000000        pass       
+0          61         00000000        0          61         00000000        pass       
+1          185        00000000        1          185        00000000        pass       
+0          157        00000000        0          157        00000000        pass       
+1          479        00000000        1          479        00000000        pass       
+0          129        00000000        0          129        00000000        pass       
+1          424        00000000        1          424        00000000        pass       
+0          24         00000000        0          24         00000000        pass       
+1          107        00000000        1          107        00000000        pass       
+0          399        00000000        0          399        00000000        pass       
+1          10         00000000        1          10         00000000        pass       
+0          349        00000000        0          349        00000000        pass       
+1          215        00000000        1          215        00000000        pass       
+0          210        00000000        0          210        00000000        pass       
+1          19         00000000        1          19         00000000        pass       
+0          398        00000000        0          398        00000000        pass       
+1          503        00000000        1          503        00000000        pass       
+0          423        00000000        0          423        00000000        pass       
+1          290        00000000        1          290        00000000        pass       
+0          59         00000000        0          59         00000000        pass       
+1          332        00000000        1          332        00000000        pass       
+0          108        00000000        0          108        00000000        pass       
+1          91         00000000        1          91         00000000        pass       
+0          494        00000000        0          494        00000000        pass       
+1          114        00000000        1          114        00000000        pass       
+0          99         00000000        0          99         00000000        pass       
+1          220        00000000        1          220        00000000        pass       
+0          430        00000000        0          430        00000000        pass       
+1          164        00000000        1          164        00000000        pass       
+0          476        00000000        0          476        00000000        pass       
+1          122        00000000        1          122        00000000        pass       
+0          94         00000000        0          94         00000000        pass       
+1          27         00000000        1          27         00000000        pass       
+0          0          00000000        0          0          00000000        pass       
+1          380        00000000        1          380        00000000        pass       
+0          145        00000000        0          145        00000000        pass       
+1          450        00000000        1          450        00000000        pass       
+0          279        00000000        0          279        00000000        pass       
+1          273        00000000        1          273        00000000        pass       
+0          322        00000000        0          322        00000000        pass       
+1          84         00000000        1          84         00000000        pass       
+0          55         00000000        0          55         00000000        pass       
+1          23         00000000        1          23         00000000        pass       
+0          354        00000000        0          354        00000000        pass       
+1          415        00000000        1          415        00000000        pass       
+0          193        00000000        0          193        00000000        pass       
+1          345        00000000        1          345        00000000        pass       
+0          134        00000000        0          134        00000000        pass       
+1          275        00000000        1          275        00000000        pass       
+0          430        00000000        0          430        00000000        pass       
+1          18         00000000        1          18         00000000        pass       
+0          452        00000000        0          452        00000000        pass       
+1          253        00000000        1          253        00000000        pass       
+0          428        00000000        0          428        00000000        pass       
+1          183        00000000        1          183        00000000        pass       
+0          51         00000000        0          51         00000000        pass       
+1          373        00000000        1          373        00000000        pass       
+0          459        00000000        0          459        00000000        pass       
+1          311        00000000        1          311        00000000        pass       
+0          28         00000000        0          28         00000000        pass       
+1          57         00000000        1          57         00000000        pass       
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+0          499        0000002e        0          499        0000002e        pass       
+1          362        00000000        1          362        00000000        pass       
+0          386        0000002e        0          386        0000002e        pass       
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+1          436        00000000        1          436        00000000        pass       
+0          287        0e082d00        0          287        0e082d00        pass       
+1          329        e0c500c1        1          329        e0c500c1        pass       
+0          499        0e082d00        0          499        0e082d00        pass       
+1          286        e0c500c1        1          286        e0c500c1        pass       
+0          282        00bce391        0          282        00bce391        pass       
+1          399        00000000        1          399        00000000        pass       
+0          229        00000000        0          229        00000000        pass       
+1          32         00000000        1          32         00000000        pass       
+0          334        00000000        0          334        00000000        pass       
+1          498        00000000        1          498        00000000        pass       
+0          390        00000000        0          390        00000000        pass       
+1          420        00000000        1          420        00000000        pass       
+0          129        000017f7        0          129        000017f7        pass       
+1          175        4900fb93        1          175        4900fb93        pass       
+0          51         000017f7        0          51         000017f7        pass       
+1          165        4900fb93        1          165        4900fb93        pass       
+0          194        43e00087        0          194        43e00087        pass       
+1          306        00c30093        1          306        00c30093        pass       
+0          264        00ecbab5        0          264        00ecbab5        pass       
+1          31         fa158300        1          31         fa158300        pass       
+0          391        00ecbab5        0          391        00ecbab5        pass       
+1          172        fa158300        1          172        fa158300        pass       
+0          501        00ecbab5        0          501        00ecbab5        pass       
+1          345        fa158300        1          345        fa158300        pass       
+0          222        00ecbab5        0          222        00ecbab5        pass       
+1          122        fa158300        1          122        fa158300        pass       
+0          214        00000000        0          214        00000000        pass       
+1          146        0000aca4        1          146        0000aca4        pass       
+0          364        0000bd00        0          364        0000bd00        pass       
+1          85         00000000        1          85         00000000        pass       
+0          236        005e29b6        0          236        005e29b6        pass       
+1          393        00617b9e        1          393        00617b9e        pass       
+0          377        c4aa2700        0          377        c4aa2700        pass       
+1          247        0000b300        1          247        0000b300        pass       
+0          28         00000000        0          28         00000000        pass       
+1          254        00000292        1          254        00000292        pass       
+0          61         37440096        0          61         37440096        pass       
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+1          340        879d1c00        1          340        879d1c00        pass       
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+1          116        dd0000ba        1          116        dd0000ba        pass       
+0          173        8b135a16        0          173        8b135a16        pass       
+1          116        b4280068        1          116        b4280068        pass       
+0          12         8b135a16        0          12         8b135a16        pass       
+1          296        b4280068        1          296        b4280068        pass       
+0          444        009f5b00        0          444        009f5b00        pass       
+1          450        fa004e00        1          450        fa004e00        pass       
+0          60         00a70065        0          60         00a70065        pass       
+1          412        74005b00        1          412        74005b00        pass       
+0          481        00000000        0          481        00000000        pass       
+1          448        00000000        1          448        00000000        pass       
+0          249        0b000000        0          249        0b000000        pass       
+1          287        00000000        1          287        00000000        pass       
+0          466        00000000        0          466        00000000        pass       
+1          282        00000000        1          282        00000000        pass       
+0          446        00000000        0          446        00000000        pass       
+1          62         00000000        1          62         00000000        pass       
+0          183        00000000        0          183        00000000        pass       
+1          204        41009700        1          204        41009700        pass       
+0          121        00000000        0          121        00000000        pass       
+1          479        00000000        1          479        00000000        pass       
+0          30         00000000        0          30         00000000        pass       
+1          335        00000000        1          335        00000000        pass       
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..1a195b3
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,121 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+        $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+     $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+integer i;
+initial
+    //if (IZERO)
+      for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule
diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd
new file mode 100644
index 0000000..a0d44da
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd
@@ -0,0 +1,69464 @@
+$date
+	Wed Nov 24 03:18:48 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_nr1w_tb $end
+$var wire 64 ! RData_pck_sram [63:0] $end
+$var reg 18 " RAddr_pck [17:0] $end
+$var reg 64 # RData_pck_golden [63:0] $end
+$var reg 9 $ WAddr_pck [8:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 p [31:0] $end
+$var integer 32 3 pass [31:0] $end
+$var integer 32 4 q [31:0] $end
+$var integer 32 5 r [31:0] $end
+$var integer 32 6 rep_fd [31:0] $end
+$var integer 32 7 s [31:0] $end
+$scope module ram_nr1w $end
+$var wire 18 8 addr [17:0] $end
+$var wire 18 9 addr1 [17:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 < din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 > wmask [3:0] $end
+$var reg 64 ? dout [63:0] $end
+$var reg 64 @ dout1 [63:0] $end
+$var integer 32 A _i_ [31:0] $end
+$scope begin genblk1[0] $end
+$scope module ram_1rw $end
+$var wire 9 B addr [8:0] $end
+$var wire 9 C addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 D din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 E wmask [3:0] $end
+$var wire 2 F Addr_sel_1 [1:0] $end
+$var wire 2 G Addr_sel [1:0] $end
+$var reg 32 H RData_out [31:0] $end
+$var reg 32 I RData_out_1 [31:0] $end
+$var reg 2 J Raddr_sel [1:0] $end
+$var reg 2 K Raddr_sel_1 [1:0] $end
+$var reg 32 L dout [31:0] $end
+$var reg 32 M dout1 [31:0] $end
+$var reg 1 N web_reg $end
+$var integer 32 O i [31:0] $end
+$var integer 32 P j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Q addr0 [7:0] $end
+$var wire 8 R addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 S csb0 $end
+$var wire 1 T csb1 $end
+$var wire 32 U din0 [31:0] $end
+$var wire 1 V web0 $end
+$var wire 4 W wmask0 [3:0] $end
+$var reg 8 X addr0_reg [7:0] $end
+$var reg 8 Y addr1_reg [7:0] $end
+$var reg 1 Z csb0_reg $end
+$var reg 1 [ csb1_reg $end
+$var reg 32 \ din0_reg [31:0] $end
+$var reg 32 ] dout0 [31:0] $end
+$var reg 32 ^ dout1 [31:0] $end
+$var reg 1 _ web0_reg $end
+$var reg 4 ` wmask0_reg [3:0] $end
+$var integer 32 a i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 b addr0 [7:0] $end
+$var wire 8 c addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 d csb0 $end
+$var wire 1 e csb1 $end
+$var wire 32 f din0 [31:0] $end
+$var wire 1 g web0 $end
+$var wire 4 h wmask0 [3:0] $end
+$var reg 8 i addr0_reg [7:0] $end
+$var reg 8 j addr1_reg [7:0] $end
+$var reg 1 k csb0_reg $end
+$var reg 1 l csb1_reg $end
+$var reg 32 m din0_reg [31:0] $end
+$var reg 32 n dout0 [31:0] $end
+$var reg 32 o dout1 [31:0] $end
+$var reg 1 p web0_reg $end
+$var reg 4 q wmask0_reg [3:0] $end
+$var integer 32 r i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope module ram_1rw $end
+$var wire 9 s addr [8:0] $end
+$var wire 9 t addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 u din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 v wmask [3:0] $end
+$var wire 2 w Addr_sel_1 [1:0] $end
+$var wire 2 x Addr_sel [1:0] $end
+$var reg 32 y RData_out [31:0] $end
+$var reg 32 z RData_out_1 [31:0] $end
+$var reg 2 { Raddr_sel [1:0] $end
+$var reg 2 | Raddr_sel_1 [1:0] $end
+$var reg 32 } dout [31:0] $end
+$var reg 32 ~ dout1 [31:0] $end
+$var reg 1 !" web_reg $end
+$var integer 32 "" i [31:0] $end
+$var integer 32 #" j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 $" addr0 [7:0] $end
+$var wire 8 %" addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 &" csb0 $end
+$var wire 1 '" csb1 $end
+$var wire 32 (" din0 [31:0] $end
+$var wire 1 )" web0 $end
+$var wire 4 *" wmask0 [3:0] $end
+$var reg 8 +" addr0_reg [7:0] $end
+$var reg 8 ," addr1_reg [7:0] $end
+$var reg 1 -" csb0_reg $end
+$var reg 1 ." csb1_reg $end
+$var reg 32 /" din0_reg [31:0] $end
+$var reg 32 0" dout0 [31:0] $end
+$var reg 32 1" dout1 [31:0] $end
+$var reg 1 2" web0_reg $end
+$var reg 4 3" wmask0_reg [3:0] $end
+$var integer 32 4" i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 5" addr0 [7:0] $end
+$var wire 8 6" addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 7" csb0 $end
+$var wire 1 8" csb1 $end
+$var wire 32 9" din0 [31:0] $end
+$var wire 1 :" web0 $end
+$var wire 4 ;" wmask0 [3:0] $end
+$var reg 8 <" addr0_reg [7:0] $end
+$var reg 8 =" addr1_reg [7:0] $end
+$var reg 1 >" csb0_reg $end
+$var reg 1 ?" csb1_reg $end
+$var reg 32 @" din0_reg [31:0] $end
+$var reg 32 A" dout0 [31:0] $end
+$var reg 32 B" dout1 [31:0] $end
+$var reg 1 C" web0_reg $end
+$var reg 4 D" wmask0_reg [3:0] $end
+$var integer 32 E" i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope task genInitFiles $end
+$var reg 32 F" DEPTH [31:0] $end
+$var reg 160 G" FILEN [1:160] $end
+$var reg 256 H" INITVAL [255:0] $end
+$var reg 1 I" RAND $end
+$var reg 32 J" WIDTH [31:0] $end
+$var reg 256 K" ramdata [255:0] $end
+$var integer 32 L" addr [31:0] $end
+$var integer 32 M" hex_fd [31:0] $end
+$var integer 32 N" mif_fd [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000000000000000000000100 N"
+b10000000000000000000000000000011 M"
+b1000000000 L"
+b10100010001010101100011001000100 K"
+b100000 J"
+1I"
+b0 H"
+b110100101101110011010010111010001011111011100100110000101101101 G"
+b1000000000 F"
+b100000000 E"
+bx D"
+xC"
+bx B"
+bx A"
+bx @"
+x?"
+x>"
+bx ="
+bx <"
+bx ;"
+x:"
+bx 9"
+18"
+x7"
+b0 6"
+bx 5"
+b100000000 4"
+bx 3"
+x2"
+bx 1"
+bx 0"
+bx /"
+x."
+x-"
+bx ,"
+bx +"
+bx *"
+x)"
+bx ("
+1'"
+x&"
+b0 %"
+bx $"
+bx #"
+b10 ""
+x!"
+bx ~
+bx }
+bx |
+bx {
+bx z
+bx y
+bx x
+b0 w
+bx v
+bx u
+b0 t
+bx s
+b100000000 r
+bx q
+xp
+bx o
+bx n
+bx m
+xl
+xk
+bx j
+bx i
+bx h
+xg
+bx f
+1e
+xd
+b0 c
+bx b
+b100000000 a
+bx `
+x_
+bx ^
+bx ]
+bx \
+x[
+xZ
+bx Y
+bx X
+bx W
+xV
+bx U
+1T
+xS
+b0 R
+bx Q
+bx P
+b10 O
+xN
+bx M
+bx L
+bx K
+bx J
+bx I
+bx H
+bx G
+b0 F
+bx E
+bx D
+b0 C
+bx B
+b11 A
+bx @
+bx ?
+bx >
+x=
+bx <
+1;
+0:
+b0 9
+bx 8
+bx 7
+b10000000000000000000000000000011 6
+b1000000000 5
+bx 4
+bx 3
+bx 2
+bx 1
+bx 0
+b1 /
+bx .
+bx -
+x,
+x+
+1*
+x)
+x(
+0'
+x&
+bx %
+bx $
+bx #
+bx "
+bx !
+$end
+#5
+b0 K
+b0 |
+b0 Y
+1[
+b0 j
+1l
+b10 P
+b0 ,"
+1."
+b0 ="
+1?"
+b10 #"
+b10 4
+1'
+#10
+07"
+b10001101 5"
+1&"
+b0 $"
+b1 x
+1d
+b0 b
+0S
+b11101001 Q
+b0 G
+b110001101 s
+b11101001 B
+b11 A
+1g
+1V
+b10 O
+1:"
+1)"
+b10 ""
+b110001101011101001 8
+1=
+b101100010 $
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diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100644
index 0000000..4048ea8
--- /dev/null
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+         $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+      $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 1232147..969d635 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -32,6 +32,10 @@
   // for rtl verification
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
-    `include "BrqRV_EB1/BrqRV_EB1.v"
+    `include "rams/ram_256x32_2r1w/utils.vh"
+    `include "rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v"
+    `include "rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v"
+    `include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+    
     
 `endif
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b03a01f..97bef5e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -86,21 +86,13 @@
 );
     wire clk;
     wire rst;
-    wire rx_i;
-    wire [31:0] reset_vector;
-    wire [31:0] jtag_id;
-    wire [31:0] nmi_vector;
-    wire nmi_int;
-    
-    wire [`MPRJ_IO_PADS-1:0] io_in;
-    wire [`MPRJ_IO_PADS-1:0] io_out;
-    wire [`MPRJ_IO_PADS-1:0] io_oeb;
-    
-    wire		lsu_axi_wvalid;
-    wire [63:0]	lsu_axi_wdata;
-    wire [7:0]         lsu_axi_wstrb;
-    reg		lsu_axi_bvalid;
-    //reg  [2:0]	        lsu_axi_bid;
+    reg csb0;
+    reg csb1;
+    reg web; 
+    wire [15:0] addr;
+    wire [31:0] din;
+    wire [63:0] dout0;
+    wire [31:0] dout1;
 
 
     // WB MI A
@@ -109,410 +101,101 @@
 
 
     // IO
-    assign io_out[35:8] = (| lsu_axi_wstrb[3:0]) ? lsu_axi_wdata[27:0] : (| lsu_axi_wstrb[7:4]) ? lsu_axi_wdata[59:32] : {28{1'b0}};
+    //assign io_out[35:8] = (| lsu_axi_wstrb[3:0]) ? lsu_axi_wdata[27:0] : (| lsu_axi_wstrb[7:4]) ? lsu_axi_wdata[59:32] : {28{1'b0}};
     
-    assign io_oeb[35:8] = {28{~lsu_axi_wvalid}};
+    // io_oeb 0 for output 1 for input
+    
     assign io_oeb[3:0]  = 4'hf;
     assign io_oeb[4]    = 1'b0;
     assign io_oeb[6:5]  = 2'b01;
     assign io_oeb[7]    = 1'b0;
-    
-    always @(posedge wb_clk_i) begin
-    	lsu_axi_bvalid = (lsu_axi_wvalid) ? 1'b1 : 1'b0;
-    	//lsu_axi_bid    = (| lsu_axi_wstrb[3:0]) ? 3'b000 : (| lsu_axi_wstrb[7:4]) ? 3'b001 : 3'b000;
-    end
+    assign io_oeb[8]    = 1'b1; // csb0 for M0
+    assign io_oeb[9]    = 1'b1; // csb1 for M1
+    assign io_oeb[10]    = 1'b1; // web
+    assign io_oeb[26:11]    = 16'hFFFF; // addr
+    assign io_oeb[34:27]    = 8'h00; // data out
+    assign io_oeb[35]    = 1'b1; // output selector // if 0 so output will map on la_data if 1 so will map on io ports
     // IRQ
     assign user_irq = 3'b000;	// Unused
 
-    // LA
-    assign la_data_out = (| lsu_axi_wstrb[3:0]) ? {{(127-BITS){1'b0}}, lsu_axi_wdata[31:0]} : (| lsu_axi_wstrb[7:4]) ? {{(127-BITS){1'b0}}, lsu_axi_wdata[63:32]} : {128{1'b0}};
 
-    // Assuming LA probes [65:64] are for controlling the count clk & reset  
+    // Assuming LA probes [65:64] are for controlling the clk & reset  
     assign clk = (~la_oenb[65]) ? la_data_in[65] :  wb_clk_i;
-    assign rst = (~la_oenb[64]) ? la_data_in[64] : ~wb_rst_i;
-    assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];
-    assign reset_vector = 32'haffff000;
-    assign jtag_id[31:28] = 4'b1;
-    assign jtag_id[27:12] = {16{1'b0}};
-    assign jtag_id[11:1]  = 11'h45;
-    assign nmi_vector   = 32'hee000000;
-    assign nmi_int   = 0;
+    assign rst = (~la_oenb[64]) ? la_data_in[64] :  wb_rst_i;
+    always @(negedge clk) begin
+    	csb0 <= (~la_oenb[0]) ? la_data_in[0] : io_in[8];
+    	csb1 <= (~la_oenb[1]) ? la_data_in[1] : io_in[9];
+    	web <= (~la_oenb[2]) ? la_data_in[2] : io_in[10];
+    end
+    assign addr = (~la_oenb[18:3]) ? la_data_in[18:3] : io_in[26:11];
+    assign din = la_data_in[50:19];    
+    assign la_data_out[97:66] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[31:0] : (csb1 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout1 : 32'h00000000;
+    assign la_data_out[61:52] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[41:32] : 10'h000;
+    assign la_data_out[119:98] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[63:42] : 22'h000000;
+    assign io_out[34:27] = (csb0 == 1'b0 & web == 1'b1 & io_in[35]) ? {dout0[35:32],dout0[3:0]} : (csb1 == 1'b0 & web == 1'b1 & io_in[35]) ? dout1[7:0] : 8'h00;
     
+
     
+    /*always @posedge(clk) begin
+    if(rst) begin
+    state <= 2'b00; // IDLE
+    end
+    else begin
+    state <= next_state;
+    end
+    */
+    /*// IDLE = 3'b000, READ_M1 = 3'b001, WRITE_M1 = 3'b010, READ_M2 = 3'b011, WRITE_M2 = 3'b100, COMPLETE = 3'b101 
+    case(state) begin
+    3'b000 : begin
+            next_state = (csb0==1'b0 & web == 1'b1) ? 3'b001 : (csb0==1'b0 & web == 1'b0) ? 3'b010 : (csb1==1'b0 & web == 1'b1) ? 3'b011 : (csb1==1'b0 & web == 1'b0) ? 3'b100 : 3'b00;
+     	     wmask <= 4'h0;
+     	     din <= 32'h00000000;
+     	     count <= 3'h0;      
+            end
+            
+     3'b001 : begin
+     	     next_state = (count <= 3'h7) : 3'b101 :  
+      */ 
+              
    //=========================================================================-
    // RTL instance
    //=========================================================================-
-eb1_brqrv_wrapper brqrv_top (
-`ifdef USE_POWER_PINS
+
+ram_generic_nr1w 
+ram_2r1w_256x32 ( `ifdef USE_POWER_PINS
     .vccd1		     ( vccd1	      ),
     .vssd1                   ( vssd1         ),
-`endif
-    .rst_l                  ( rst           ),
-    .dbg_rst_l              ( ~wb_rst_i     ),
-    .clk                    ( clk           ),
-    .rst_vec                ( reset_vector[31:1]  ),
-    .nmi_int                ( nmi_int       ),
-    .nmi_vec                ( nmi_vector[31:1]),
-    .jtag_id                ( jtag_id[31:1]),
-    .uart_rx		     ( rx_i          ),
-    .CLKS_PER_BIT           ( la_data_in[47:32]),
-
-`ifdef RV_BUILD_AHB_LITE
-    .haddr                  (      ),
-    .hburst                 (      ),
-    .hmastlock              (      ),
-    .hprot                  (      ),
-    .hsize                  (      ),
-    .htrans                 (      ),
-    .hwrite                 (      ),
-
-    .hrdata                 (      ),
-    .hready                 (      ),
-    .hresp                  (      ),
-
-    //---------------------------------------------------------------
-    // Debug AHB Master
-    //---------------------------------------------------------------
-    .sb_haddr               (      ),
-    .sb_hburst              (      ),
-    .sb_hmastlock           (      ),
-    .sb_hprot               (      ),
-    .sb_hsize               (      ),
-    .sb_htrans              (      ),
-    .sb_hwrite              (      ),
-    .sb_hwdata              (      ),
-
-    .sb_hrdata              (      ),
-    .sb_hready              (      ),
-    .sb_hresp               (      ),
-
-    //---------------------------------------------------------------
-    // LSU AHB Master
-    //---------------------------------------------------------------
-    .lsu_haddr              (      ),
-    .lsu_hburst             (      ),
-    .lsu_hmastlock          (      ),
-    .lsu_hprot              (      ),
-    .lsu_hsize              (      ),
-    .lsu_htrans             (      ),
-    .lsu_hwrite             (      ),
-    .lsu_hwdata             (      ),
-
-    .lsu_hrdata             (      ),
-    .lsu_hready             (      ),
-    .lsu_hresp              (      ),
-
-    //---------------------------------------------------------------
-    // DMA Slave
-    //---------------------------------------------------------------
-    .dma_haddr              ( '0 ),
-    .dma_hburst             ( '0 ),
-    .dma_hmastlock          ( '0 ),
-    .dma_hprot              ( '0 ),
-    .dma_hsize              ( '0 ),
-    .dma_htrans             ( '0 ),
-    .dma_hwrite             ( '0 ),
-    .dma_hwdata             ( '0 ),
-
-    .dma_hrdata             (    ),
-    .dma_hresp              (    ),
-    .dma_hsel               (1'b1),
-    .dma_hreadyin           (    ),
-    .dma_hreadyout          (    ),
-`endif
-
-    //-------------------------- LSU AXI signals--------------------------
-    // AXI Write Channels
-    .lsu_axi_awvalid        (),
-    .lsu_axi_awready        (1'b1),
-    .lsu_axi_awid           (),
-    .lsu_axi_awaddr         (),
-    .lsu_axi_awregion       (),
-    .lsu_axi_awlen          (),
-    .lsu_axi_awsize         (),
-    .lsu_axi_awburst        (),
-    .lsu_axi_awlock         (),
-    .lsu_axi_awcache        (),
-    .lsu_axi_awprot         (),
-    .lsu_axi_awqos          (),
-
-    .lsu_axi_wvalid         (lsu_axi_wvalid),
-    .lsu_axi_wready         (1'b1),
-    .lsu_axi_wdata          (lsu_axi_wdata),
-    .lsu_axi_wstrb          (lsu_axi_wstrb),
-    .lsu_axi_wlast          (),
-
-    .lsu_axi_bvalid         (lsu_axi_bvalid),
-    .lsu_axi_bready         (),
-    .lsu_axi_bresp          (2'b00),
-    .lsu_axi_bid            (3'b000),
-
-
-    .lsu_axi_arvalid        (),
-    .lsu_axi_arready        (),
-    .lsu_axi_arid           (),
-    .lsu_axi_araddr         (),
-    .lsu_axi_arregion       (),
-    .lsu_axi_arlen          (),
-    .lsu_axi_arsize         (),
-    .lsu_axi_arburst        (),
-    .lsu_axi_arlock         (),
-    .lsu_axi_arcache        (),
-    .lsu_axi_arprot         (),
-    .lsu_axi_arqos          (),
-
-    .lsu_axi_rvalid         (),
-    .lsu_axi_rready         (),
-    .lsu_axi_rid            (),
-    .lsu_axi_rdata          (),
-    .lsu_axi_rresp          (),
-    .lsu_axi_rlast          (),
-    
-    //-------------------------- IFU AXI signals--------------------------
-    // AXI Write Channels
-    .ifu_axi_awvalid        (),
-    .ifu_axi_awready        (1'b0),
-    .ifu_axi_awid           (),
-    .ifu_axi_awaddr         (),
-    .ifu_axi_awregion       (),
-    .ifu_axi_awlen          (),
-    .ifu_axi_awsize         (),
-    .ifu_axi_awburst        (),
-    .ifu_axi_awlock         (),
-    .ifu_axi_awcache        (),
-    .ifu_axi_awprot         (),
-    .ifu_axi_awqos          (),
-
-    .ifu_axi_wvalid         (),
-    .ifu_axi_wready         (1'b0),
-    .ifu_axi_wdata          (),
-    .ifu_axi_wstrb          (),
-    .ifu_axi_wlast          (),
-
-    .ifu_axi_bvalid         (1'b0),
-    .ifu_axi_bready         (),
-    .ifu_axi_bresp          (2'b0),
-    .ifu_axi_bid            (3'b0),
-
-    .ifu_axi_arvalid        (),
-    .ifu_axi_arready        (),
-    .ifu_axi_arid           (),
-    .ifu_axi_araddr         (),
-    .ifu_axi_arregion       (),
-    .ifu_axi_arlen          (),
-    .ifu_axi_arsize         (),
-    .ifu_axi_arburst        (),
-    .ifu_axi_arlock         (),
-    .ifu_axi_arcache        (),
-    .ifu_axi_arprot         (),
-    .ifu_axi_arqos          (),
-
-    .ifu_axi_rvalid         (),
-    .ifu_axi_rready         (),
-    .ifu_axi_rid            (),
-    .ifu_axi_rdata          (),
-    .ifu_axi_rresp          (),
-    .ifu_axi_rlast          (),
-
-    //-------------------------- SB AXI signals--------------------------
-    // AXI Write Channels
-    .sb_axi_awvalid         (),
-    .sb_axi_awready         (1'b0),
-    .sb_axi_awid            (),
-    .sb_axi_awaddr          (),
-    .sb_axi_awregion        (),
-    .sb_axi_awlen           (),
-    .sb_axi_awsize          (),
-    .sb_axi_awburst         (),
-    .sb_axi_awlock          (),
-    .sb_axi_awcache         (),
-    .sb_axi_awprot          (),
-    .sb_axi_awqos           (),
-
-    .sb_axi_wvalid          (),
-    .sb_axi_wready          (1'b0),
-    .sb_axi_wdata           (),
-    .sb_axi_wstrb           (),
-    .sb_axi_wlast           (),
-
-    .sb_axi_bvalid          (1'b0),
-    .sb_axi_bready          (),
-    .sb_axi_bresp           (2'b0),
-    .sb_axi_bid             (1'b0),
-
-
-    .sb_axi_arvalid         (),
-    .sb_axi_arready         (1'b0),
-    .sb_axi_arid            (),
-    .sb_axi_araddr          (),
-    .sb_axi_arregion        (),
-    .sb_axi_arlen           (),
-    .sb_axi_arsize          (),
-    .sb_axi_arburst         (),
-    .sb_axi_arlock          (),
-    .sb_axi_arcache         (),
-    .sb_axi_arprot          (),
-    .sb_axi_arqos           (),
-
-    .sb_axi_rvalid          (1'b0),
-    .sb_axi_rready          (),
-    .sb_axi_rid             (1'b0),
-    .sb_axi_rdata           (64'b0),
-    .sb_axi_rresp           (2'b0),
-    .sb_axi_rlast           (1'b0),
-
-    //-------------------------- DMA AXI signals--------------------------
-    // AXI Write Channels
-    .dma_axi_awvalid        (1'b0),
-    .dma_axi_awready        (),
-    .dma_axi_awid           (1'b0),
-    .dma_axi_awaddr         (32'b0),
-    .dma_axi_awsize         (3'b0),
-    .dma_axi_awprot         (3'b0),
-    .dma_axi_awlen          (8'b0),
-    .dma_axi_awburst        (2'b0),
-
-
-    .dma_axi_wvalid         (1'b0),
-    .dma_axi_wready         (),
-    .dma_axi_wdata          (64'b0),
-    .dma_axi_wstrb          (8'b0),
-    .dma_axi_wlast          (1'b0),
-
-    .dma_axi_bvalid         (),
-    .dma_axi_bready         (1'b0),
-    .dma_axi_bresp          (),
-    .dma_axi_bid            (),
-
-
-    .dma_axi_arvalid        (1'b0),
-    .dma_axi_arready        (),
-    .dma_axi_arid           (1'b0),
-    .dma_axi_araddr         (32'b0),
-    .dma_axi_arsize         (3'b0),
-    .dma_axi_arprot         (3'b0),
-    .dma_axi_arlen          (8'b0),
-    .dma_axi_arburst        (2'b0),
-
-    .dma_axi_rvalid         (),
-    .dma_axi_rready         (1'b0),
-    .dma_axi_rid            (),
-    .dma_axi_rdata          (),
-    .dma_axi_rresp          (),
-    .dma_axi_rlast          (),
-
-    .timer_int              ( 1'b0 ),
-    .extintsrc_req          ( 31'b0   ),
-
-    .lsu_bus_clk_en         ( 1'b1  ),// Clock ratio b/w cpu core clk & AHB master interface
-    .ifu_bus_clk_en         ( 1'b1  ),// Clock ratio b/w cpu core clk & AHB master interface
-    .dbg_bus_clk_en         ( 1'b1  ),// Clock ratio b/w cpu core clk & AHB Debug master interface
-    .dma_bus_clk_en         ( 1'b1  ),// Clock ratio b/w cpu core clk & AHB slave interface
-
-    .trace_rv_i_insn_ip     (),
-    .trace_rv_i_address_ip  (),
-    .trace_rv_i_valid_ip    (),
-    .trace_rv_i_exception_ip(),
-    .trace_rv_i_ecause_ip   (),
-    .trace_rv_i_interrupt_ip(),
-    .trace_rv_i_tval_ip     (),
-
-    .jtag_tck               ( io_in[0] ),
-    .jtag_tms               ( io_in[1] ),
-    .jtag_tdi               ( io_in[3] ),
-    .jtag_trst_n            ( io_in[2] ),
-    .jtag_tdo               ( io_out[4]),
-
-    .mpc_debug_halt_ack     ( ),
-    .mpc_debug_halt_req     ( 1'b0),
-    .mpc_debug_run_ack      ( ),
-    .mpc_debug_run_req      ( 1'b1),
-    .mpc_reset_run_req      ( 1'b1),             // Start running after reset
-     .debug_brkpt_status    ( ),
-
-    .i_cpu_halt_req         ( 1'b0  ),    // Async halt req to CPU
-    .o_cpu_halt_ack         (  ),    // core response to halt
-    .o_cpu_halt_status      (  ), // 1'b1 indicates core is halted
-    .i_cpu_run_req          ( 1'b0  ),     // Async restart req to CPU
-    .o_debug_mode_status    (  ),
-    .o_cpu_run_ack          (  ),     // Core response to run req
-
-    .dec_tlu_perfcnt0       (),
-    .dec_tlu_perfcnt1       (),
-    .dec_tlu_perfcnt2       (),
-    .dec_tlu_perfcnt3       (),
-
-// remove mems DFT pins for opensource
-    .dccm_ext_in_pkt        ( 48'b0),
-    .iccm_ext_in_pkt        ( 48'b0),
-    .ic_data_ext_in_pkt     ( 48'b0),
-    .ic_tag_ext_in_pkt      ( 24'b0),
-
-    .soft_int               ( 1'b0),
-    .core_id                ( 28'b0),
-    .scan_mode              ( 1'b0 ),         // To enable scan mode
-    .mbist_mode             ( 1'b0 )        // to enable mbist
-
-);
-
-
-/*    counter #(
-        .BITS(BITS)
-    ) counter(
-        .clk(clk),
-        .reset(rst),
-        .ready(wbs_ack_o),
-        .valid(valid),
-        .rdata(rdata),
-        .wdata(wbs_dat_i),
-        .wstrb(wstrb),
-        .la_write(la_write),
-        .la_input(la_data_in[63:32]),
-        .count(count)
+  `endif
+    .clk(clk),
+    .csb(csb0),
+    .web(web),
+    .wmask(4'hF),
+    .din(din),
+    .addr(addr),
+    .dout(dout0),
+    .addr1(addr), 
+    .csb1(1'b1),
+    .clk1(clk), 
+    .dout1()
     );
-*/
+
+sky130_sram_1kbyte_1rw1r_32x256_8 sram (`ifdef USE_POWER_PINS
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+`endif
+					 .clk0(clk),
+					 .csb0(csb1),
+					 .web0(web),
+					 .wmask0(4'hf),
+					 .addr0(addr[7:0]),
+					 .din0(din),
+					 .dout0(dout1),
+    					 .clk1(clk),
+    					 .csb1(1'b1),
+    					 .addr1(addr[7:0]),
+    					 .dout1() 
+    					 );				 
 endmodule
 
-/*module counter #(
-    parameter BITS = 32
-)(
-    input clk,
-    input reset,
-    input valid,
-    input [3:0] wstrb,
-    input [BITS-1:0] wdata,
-    input [BITS-1:0] la_write,
-    input [BITS-1:0] la_input,
-    output ready,
-    output [BITS-1:0] rdata,
-    output [BITS-1:0] count
-);
-    reg ready;
-    reg [BITS-1:0] count;
-    reg [BITS-1:0] rdata;
 
-    always @(posedge clk) begin
-        if (reset) begin
-            count <= 0;
-            ready <= 0;
-        end else begin
-            ready <= 1'b0;
-            if (~|la_write) begin
-                count <= count + 1;
-            end
-            if (valid && !ready) begin
-                ready <= 1'b1;
-                rdata <= count;
-                if (wstrb[0]) count[7:0]   <= wdata[7:0];
-                if (wstrb[1]) count[15:8]  <= wdata[15:8];
-                if (wstrb[2]) count[23:16] <= wdata[23:16];
-                if (wstrb[3]) count[31:24] <= wdata[31:24];
-            end else if (|la_write) begin
-                count <= la_write & la_input;
-            end
-        end
-    end
-
-endmodule
-*/
 `default_nettype wire