diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3b7eac0..3534e4f 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -3,6 +3,8 @@
 `include "defines.v"
 
 `ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
     `include "gl/user_project_wrapper.v"
     `include "gl/user_proj_example.v"
 `else
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 44e8eda..7741210 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -155,18 +155,11 @@
                 if (wstrb[1]) count[15:8]  <= wdata[15:8];
                 if (wstrb[2]) count[23:16] <= wdata[23:16];
                 if (wstrb[3]) count[31:24] <= wdata[31:24];
+            end else if (|la_write) begin
+                count <= la_write & la_input;
             end
         end
     end
 
-    genvar i;
-    generate 
-        for(i=0; i<BITS; i=i+1) begin
-          always @(posedge clk) begin
-              if (la_write[i]) count[i] <= la_input[i];
-          end
-        end
-    endgenerate
-
 endmodule
 `default_nettype wire