8-bit SAR-ADC with offset calibration

This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.

Layout

The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.

Architecture

The ADC is composed of a differential top-plate sampled dac, which is made from an array of MIM capacitors. The comparator is a regenerative comparator, which is followed by a latch to retain the output state during reset. The latch output is fed into the logic section, which performs the standard binary search algorithm.

Simulation

The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.

The Schematics are created using xschem, which also serves as the simulation framework.

The SAR schematic:

The simulation output can then be viewed in both analog and digital domain.

Digital waveforms displayed using GTKWave

Analog waveforms displayed using Gnuplot in interactive mode.