added config.tcl + pin.cfg for openlane flow
diff --git a/verilog/config.tcl b/verilog/config.tcl
new file mode 100644
index 0000000..a21ff87
--- /dev/null
+++ b/verilog/config.tcl
@@ -0,0 +1,44 @@
+# User config
+set ::env(DESIGN_NAME) sarlogic
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+# Fill this
+set ::env(CLOCK_PERIOD) "0.1"
+set ::env(CLOCK_PORT) "clk"
+
+
+# set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+
+
+# My Options
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0 0 80 70"
+
+set ::env(FP_IO_MODE) 0
+set ::env(FP_IO_MIN_DISTANCE) 1
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin.cfg
+set ::env(FP_IO_VLENGTH) 1
+set ::env(FP_IO_HLENGTH) 1
+
+set ::env(FP_IO_VTHICKNESS_MULT) 2
+set ::env(FP_IO_HTHICKNESS_MULT) 1
+
+set ::env(TOP_MARGIN_MULT) 1
+set ::env(BOTTOM_MARGIN_MULT) 1
+set ::env(LEFT_MARGIN_MULT) 1
+set ::env(RIGHT_MARGIN_MULT) 1
+
+set ::env(FP_IO_VMETAL) "3"
+
+# set ::env(PL_TARGET_DENSITY) 0.01
+# set ::env(FP_CORE_UTIL) 1
+# set ::env(DESIGN_IS_CORE) 0
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
+
diff --git a/verilog/pin.cfg b/verilog/pin.cfg
new file mode 100644
index 0000000..dd34f1d
--- /dev/null
+++ b/verilog/pin.cfg
@@ -0,0 +1,42 @@
+#N
+ctlp\[0\]
+ctlp\[1\]
+ctlp\[7\]
+ctlp\[6\]
+ctlp\[5\]
+ctlp\[4\]
+ctlp\[3\]
+ctlp\[2\]
+
+#S
+ctln\[0\]
+ctln\[1\]
+ctln\[7\]
+ctln\[6\]
+ctln\[5\]
+ctln\[4\]
+ctln\[3\]
+ctln\[2\]
+
+#E
+trim\[3\]
+trim\[2\]
+trim\[0\]
+trim\[1\]
+trim\[4\]
+clkc
+comp
+trimb\[4\]
+trimb\[1\]
+trimb\[0\]
+trimb\[2\]
+trimb\[3\]
+
+#W
+rstn
+clk
+en
+cal
+valid
+sample
+result.*
diff --git a/verilog/sarlogic.v b/verilog/src/sarlogic.v
similarity index 100%
rename from verilog/sarlogic.v
rename to verilog/src/sarlogic.v
