diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index 1fd06f9..2e360ce 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -7407,7 +7407,7 @@
       NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 190000 )
       NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 190000 ) ;
 END SPECIALNETS
-NETS 679 ;
+NETS 678 ;
     - analog_io[0] ( PIN analog_io[0] ) + USE SIGNAL ;
     - analog_io[10] ( PIN analog_io[10] ) + USE SIGNAL ;
     - analog_io[11] ( PIN analog_io[11] ) + USE SIGNAL ;
@@ -7438,16 +7438,16 @@
     - analog_io[8] ( PIN analog_io[8] ) + USE SIGNAL ;
     - analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ;
     - imem_data\[0\] ( mprj imem_data[0] ) ( mem dout0[0] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 2759780 0 ) ( 2504930 * )
-      NEW met2 ( 2504930 200430 ) ( * 2759780 )
+      + ROUTED met3 ( 2499180 2759780 0 ) ( 2505390 * )
+      NEW met2 ( 2505390 200430 ) ( * 2759780 )
       NEW met2 ( 1143330 200260 ) ( * 200430 )
       NEW met3 ( 1142180 200260 ) ( 1143330 * )
       NEW met4 ( 1142180 198900 ) ( * 200260 )
       NEW met4 ( 1140950 198900 ) ( 1142180 * )
       NEW met4 ( 1140950 198900 ) ( * 202300 0 )
-      NEW met1 ( 1143330 200430 ) ( 2504930 * )
-      NEW met1 ( 2504930 200430 ) M1M2_PR
-      NEW met2 ( 2504930 2759780 ) M2M3_PR_M
+      NEW met1 ( 1143330 200430 ) ( 2505390 * )
+      NEW met1 ( 2505390 200430 ) M1M2_PR
+      NEW met2 ( 2505390 2759780 ) M2M3_PR_M
       NEW met1 ( 1143330 200430 ) M1M2_PR
       NEW met2 ( 1143330 200260 ) M2M3_PR_M
       NEW met3 ( 1142180 200260 ) M3M4_PR_M ;
@@ -7457,16 +7457,16 @@
       NEW met4 ( 1272820 198900 ) ( * 199580 )
       NEW met4 ( 1272190 198900 ) ( 1272820 * )
       NEW met4 ( 1272190 198900 ) ( * 202300 0 )
-      NEW met2 ( 1081230 1489370 ) ( * 1500420 0 )
+      NEW met2 ( 1081230 1487330 ) ( * 1500420 0 )
       NEW met1 ( 1007170 202470 ) ( 1272590 * )
-      NEW met2 ( 1007170 202470 ) ( * 1489370 )
-      NEW met1 ( 1007170 1489370 ) ( 1081230 * )
+      NEW met2 ( 1007170 202470 ) ( * 1487330 )
+      NEW met1 ( 1007170 1487330 ) ( 1081230 * )
       NEW met1 ( 1272590 202470 ) M1M2_PR
       NEW met2 ( 1272590 199580 ) M2M3_PR_M
       NEW met3 ( 1272820 199580 ) M3M4_PR_M
-      NEW met1 ( 1081230 1489370 ) M1M2_PR
+      NEW met1 ( 1081230 1487330 ) M1M2_PR
       NEW met1 ( 1007170 202470 ) M1M2_PR
-      NEW met1 ( 1007170 1489370 ) M1M2_PR
+      NEW met1 ( 1007170 1487330 ) M1M2_PR
       NEW met3 ( 1272590 199580 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[11\] ( mprj imem_data[11] ) ( mem dout0[11] ) + USE SIGNAL
       + ROUTED met2 ( 1284550 198220 ) ( * 202130 )
@@ -7474,103 +7474,94 @@
       NEW met4 ( 1284780 198220 ) ( * 198900 )
       NEW met4 ( 1284780 198900 ) ( 1285110 * )
       NEW met4 ( 1285110 198900 ) ( * 202300 0 )
-      NEW met2 ( 996130 202130 ) ( * 2698580 )
-      NEW met3 ( 996130 2698580 ) ( 1000500 * 0 )
-      NEW met1 ( 996130 202130 ) ( 1284550 * )
-      NEW met1 ( 996130 202130 ) M1M2_PR
-      NEW met2 ( 996130 2698580 ) M2M3_PR_M
+      NEW met2 ( 997050 202130 ) ( * 2698580 )
+      NEW met3 ( 997050 2698580 ) ( 1000500 * 0 )
+      NEW met1 ( 997050 202130 ) ( 1284550 * )
+      NEW met1 ( 997050 202130 ) M1M2_PR
+      NEW met2 ( 997050 2698580 ) M2M3_PR_M
       NEW met1 ( 1284550 202130 ) M1M2_PR
       NEW met2 ( 1284550 198220 ) M2M3_PR_M
       NEW met3 ( 1284780 198220 ) M3M4_PR_M
       NEW met3 ( 1284550 198220 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[12\] ( mprj imem_data[12] ) ( mem dout0[12] ) + USE SIGNAL
-      + ROUTED met2 ( 1052710 576130 ) ( * 580890 )
-      NEW met1 ( 1052710 580890 ) ( 1066970 * )
-      NEW met1 ( 1083530 771290 ) ( 1090430 * )
-      NEW met2 ( 1090430 771290 ) ( * 790330 )
-      NEW met1 ( 1066970 620670 ) ( 1072950 * )
-      NEW met2 ( 1066970 580890 ) ( * 620670 )
-      NEW met1 ( 1072950 728110 ) ( 1083530 * )
-      NEW met2 ( 1072950 620670 ) ( * 728110 )
-      NEW met2 ( 1083530 728110 ) ( * 771290 )
+      + ROUTED met1 ( 1052250 703970 ) ( 1068350 * )
+      NEW met1 ( 1086750 770950 ) ( 1093650 * )
+      NEW met2 ( 1052250 634950 ) ( * 703970 )
+      NEW met1 ( 1068350 717570 ) ( 1086750 * )
+      NEW met2 ( 1068350 703970 ) ( * 717570 )
+      NEW met2 ( 1086750 717570 ) ( * 770950 )
+      NEW met2 ( 1093650 770950 ) ( * 941630 )
       NEW met2 ( 1242230 1500420 ) ( 1243150 * 0 )
-      NEW met2 ( 1242230 851870 ) ( * 1500420 )
+      NEW met2 ( 1242230 941630 ) ( * 1500420 )
       NEW met1 ( 1006710 213690 ) ( 1007630 * )
       NEW met2 ( 1007630 201110 ) ( * 213690 )
-      NEW met1 ( 1006710 576130 ) ( 1052710 * )
-      NEW met1 ( 1090430 790330 ) ( 1100550 * )
+      NEW met1 ( 1006710 586330 ) ( 1021430 * )
+      NEW met1 ( 1021430 586330 ) ( * 586670 )
+      NEW met1 ( 1021430 586670 ) ( 1028330 * )
+      NEW met2 ( 1028330 586670 ) ( * 607410 )
+      NEW met1 ( 1028330 607410 ) ( 1038450 * )
       NEW met2 ( 1297890 198220 ) ( * 201110 )
       NEW met3 ( 1297660 198220 ) ( 1297890 * )
       NEW met4 ( 1297660 198220 ) ( * 198900 )
       NEW met4 ( 1297660 198900 ) ( 1298030 * )
       NEW met4 ( 1298030 198900 ) ( * 202300 0 )
       NEW met1 ( 1007630 201110 ) ( 1297890 * )
-      NEW met2 ( 1006710 213690 ) ( * 576130 )
-      NEW met2 ( 1100550 790330 ) ( * 851870 )
-      NEW met1 ( 1100550 851870 ) ( 1242230 * )
-      NEW met1 ( 1052710 576130 ) M1M2_PR
-      NEW met1 ( 1052710 580890 ) M1M2_PR
-      NEW met1 ( 1066970 580890 ) M1M2_PR
-      NEW met1 ( 1083530 771290 ) M1M2_PR
-      NEW met1 ( 1090430 771290 ) M1M2_PR
-      NEW met1 ( 1090430 790330 ) M1M2_PR
-      NEW met1 ( 1066970 620670 ) M1M2_PR
-      NEW met1 ( 1072950 620670 ) M1M2_PR
-      NEW met1 ( 1072950 728110 ) M1M2_PR
-      NEW met1 ( 1083530 728110 ) M1M2_PR
-      NEW met1 ( 1242230 851870 ) M1M2_PR
+      NEW met2 ( 1006710 213690 ) ( * 586330 )
+      NEW met1 ( 1048800 634950 ) ( 1052250 * )
+      NEW met1 ( 1038450 634610 ) ( 1048800 * )
+      NEW met1 ( 1048800 634610 ) ( * 634950 )
+      NEW met2 ( 1038450 607410 ) ( * 634610 )
+      NEW met1 ( 1093650 941630 ) ( 1242230 * )
+      NEW met1 ( 1052250 703970 ) M1M2_PR
+      NEW met1 ( 1068350 703970 ) M1M2_PR
+      NEW met1 ( 1086750 770950 ) M1M2_PR
+      NEW met1 ( 1093650 770950 ) M1M2_PR
+      NEW met1 ( 1052250 634950 ) M1M2_PR
+      NEW met1 ( 1068350 717570 ) M1M2_PR
+      NEW met1 ( 1086750 717570 ) M1M2_PR
+      NEW met1 ( 1093650 941630 ) M1M2_PR
+      NEW met1 ( 1242230 941630 ) M1M2_PR
       NEW met1 ( 1006710 213690 ) M1M2_PR
       NEW met1 ( 1007630 213690 ) M1M2_PR
       NEW met1 ( 1007630 201110 ) M1M2_PR
-      NEW met1 ( 1006710 576130 ) M1M2_PR
-      NEW met1 ( 1100550 790330 ) M1M2_PR
+      NEW met1 ( 1006710 586330 ) M1M2_PR
+      NEW met1 ( 1028330 586670 ) M1M2_PR
+      NEW met1 ( 1028330 607410 ) M1M2_PR
+      NEW met1 ( 1038450 607410 ) M1M2_PR
       NEW met1 ( 1297890 201110 ) M1M2_PR
       NEW met2 ( 1297890 198220 ) M2M3_PR_M
       NEW met3 ( 1297660 198220 ) M3M4_PR_M
-      NEW met1 ( 1100550 851870 ) M1M2_PR
+      NEW met1 ( 1038450 634610 ) M1M2_PR
       NEW met3 ( 1297890 198220 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[13\] ( mprj imem_data[13] ) ( mem dout0[13] ) + USE SIGNAL
-      + ROUTED met2 ( 1532030 203660 ) ( 1532490 * )
-      NEW met2 ( 1532490 200260 ) ( * 203660 )
-      NEW met2 ( 1532490 200260 ) ( 1533410 * )
-      NEW met3 ( 1533410 200260 ) ( 1535940 * )
-      NEW met3 ( 1535940 199580 ) ( * 200260 )
-      NEW met3 ( 1535940 199580 ) ( 1537780 * )
-      NEW met3 ( 1537780 199580 ) ( * 200260 )
-      NEW met3 ( 1537780 200260 ) ( 1578260 * )
-      NEW met3 ( 1578260 200260 ) ( * 204340 )
-      NEW met2 ( 1851270 2999820 0 ) ( * 3010700 )
+      + ROUTED met2 ( 1532030 200260 ) ( * 203660 )
+      NEW met2 ( 1532030 200260 ) ( 1533410 * )
+      NEW met3 ( 1533410 200260 ) ( 1577340 * )
+      NEW met3 ( 1577340 200260 ) ( * 200940 )
+      NEW met2 ( 1851270 2999820 0 ) ( * 3010020 )
       NEW met2 ( 1312610 199580 ) ( * 204170 )
       NEW met3 ( 1312380 199580 ) ( 1312610 * )
       NEW met4 ( 1312380 198900 ) ( * 199580 )
       NEW met4 ( 1311630 198900 ) ( 1312380 * )
       NEW met4 ( 1311630 198900 ) ( * 202300 0 )
-      NEW met3 ( 1578260 204340 ) ( 1582860 * )
-      NEW met3 ( 1582860 3010700 ) ( 1851270 * )
-      NEW met4 ( 1582860 204340 ) ( * 3010700 )
+      NEW met3 ( 1577340 200940 ) ( 1598500 * )
+      NEW met3 ( 1598500 3010020 ) ( 1851270 * )
+      NEW met4 ( 1598500 200940 ) ( * 3010020 )
       NEW met2 ( 1318590 204170 ) ( * 205020 )
       NEW met2 ( 1318590 205020 ) ( 1319510 * )
       NEW met2 ( 1319510 203660 ) ( * 205020 )
-      NEW met3 ( 1319510 203660 ) ( 1337910 * )
-      NEW met2 ( 1337910 203150 ) ( * 203660 )
-      NEW met1 ( 1337910 203150 ) ( 1365970 * )
-      NEW met2 ( 1365970 203150 ) ( * 203660 )
       NEW met1 ( 1312610 204170 ) ( 1318590 * )
-      NEW met3 ( 1365970 203660 ) ( 1532030 * )
+      NEW met3 ( 1319510 203660 ) ( 1532030 * )
       NEW met2 ( 1532030 203660 ) M2M3_PR_M
       NEW met2 ( 1533410 200260 ) M2M3_PR_M
-      NEW met2 ( 1851270 3010700 ) M2M3_PR_M
+      NEW met2 ( 1851270 3010020 ) M2M3_PR_M
       NEW met1 ( 1312610 204170 ) M1M2_PR
       NEW met2 ( 1312610 199580 ) M2M3_PR_M
       NEW met3 ( 1312380 199580 ) M3M4_PR_M
-      NEW met3 ( 1582860 204340 ) M3M4_PR_M
-      NEW met3 ( 1582860 3010700 ) M3M4_PR_M
+      NEW met3 ( 1598500 200940 ) M3M4_PR_M
+      NEW met3 ( 1598500 3010020 ) M3M4_PR_M
       NEW met1 ( 1318590 204170 ) M1M2_PR
       NEW met2 ( 1319510 203660 ) M2M3_PR_M
-      NEW met2 ( 1337910 203660 ) M2M3_PR_M
-      NEW met1 ( 1337910 203150 ) M1M2_PR
-      NEW met1 ( 1365970 203150 ) M1M2_PR
-      NEW met2 ( 1365970 203660 ) M2M3_PR_M
       NEW met3 ( 1312610 199580 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[14\] ( mprj imem_data[14] ) ( mem dout0[14] ) + USE SIGNAL
       + ROUTED met2 ( 2297930 1500420 ) ( 2298390 * 0 )
@@ -7586,86 +7577,79 @@
       NEW met3 ( 1324340 198900 ) M3M4_PR_M
       NEW met3 ( 1324570 198900 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[15\] ( mprj imem_data[15] ) ( mem dout0[15] ) + USE SIGNAL
-      + ROUTED met2 ( 1532030 200090 ) ( * 200260 )
-      NEW met1 ( 1532030 200090 ) ( 1578950 * )
-      NEW met2 ( 1578950 200090 ) ( * 203660 )
-      NEW met3 ( 1338370 207060 ) ( 1339290 * )
-      NEW met3 ( 1578950 203660 ) ( 1598500 * )
-      NEW met2 ( 2013190 2999820 0 ) ( * 3009340 )
-      NEW met3 ( 1598500 3009340 ) ( 2013190 * )
-      NEW met4 ( 1598500 203660 ) ( * 3009340 )
-      NEW met3 ( 1339290 203660 ) ( 1365050 * )
-      NEW met2 ( 1365050 203660 ) ( * 206890 )
+      + ROUTED met4 ( 1532260 197540 ) ( * 200260 )
+      NEW met3 ( 1532260 197540 ) ( 1576190 * )
+      NEW met2 ( 1576190 197540 ) ( * 205700 )
+      NEW met3 ( 1338370 207060 ) ( 1386670 * )
+      NEW met3 ( 1576190 205700 ) ( 1590220 * )
+      NEW met2 ( 2013190 2999820 0 ) ( * 3011380 )
+      NEW met3 ( 1590220 3011380 ) ( 2013190 * )
+      NEW met4 ( 1590220 205700 ) ( * 3011380 )
       NEW met4 ( 1337470 198900 ) ( * 202300 0 )
       NEW met4 ( 1337470 198900 ) ( 1338140 * )
       NEW met3 ( 1338140 198900 ) ( 1338370 * )
       NEW met2 ( 1338370 198900 ) ( * 207060 )
-      NEW met2 ( 1339290 203660 ) ( * 207060 )
-      NEW met3 ( 1414500 200260 ) ( 1532030 * )
-      NEW met2 ( 1407370 198900 ) ( * 206890 )
-      NEW met3 ( 1407370 198900 ) ( 1414500 * )
+      NEW met3 ( 1414500 200260 ) ( 1532260 * )
+      NEW met3 ( 1386670 197540 ) ( 1413580 * )
+      NEW met4 ( 1413580 197540 ) ( * 198900 )
+      NEW met4 ( 1413580 198900 ) ( 1414500 * )
       NEW met4 ( 1414500 198900 ) ( * 200260 )
-      NEW met1 ( 1365050 206890 ) ( 1407370 * )
-      NEW met2 ( 1339290 207060 ) M2M3_PR_M
-      NEW met2 ( 1532030 200260 ) M2M3_PR_M
-      NEW met1 ( 1532030 200090 ) M1M2_PR
-      NEW met1 ( 1578950 200090 ) M1M2_PR
-      NEW met2 ( 1578950 203660 ) M2M3_PR_M
+      NEW met2 ( 1386670 197540 ) ( * 207060 )
+      NEW met2 ( 1386670 207060 ) M2M3_PR_M
+      NEW met3 ( 1532260 200260 ) M3M4_PR_M
+      NEW met3 ( 1532260 197540 ) M3M4_PR_M
+      NEW met2 ( 1576190 197540 ) M2M3_PR_M
+      NEW met2 ( 1576190 205700 ) M2M3_PR_M
       NEW met2 ( 1338370 207060 ) M2M3_PR_M
-      NEW met3 ( 1598500 203660 ) M3M4_PR_M
-      NEW met3 ( 1598500 3009340 ) M3M4_PR_M
-      NEW met2 ( 2013190 3009340 ) M2M3_PR_M
-      NEW met2 ( 1339290 203660 ) M2M3_PR_M
-      NEW met2 ( 1365050 203660 ) M2M3_PR_M
-      NEW met1 ( 1365050 206890 ) M1M2_PR
+      NEW met3 ( 1590220 205700 ) M3M4_PR_M
+      NEW met3 ( 1590220 3011380 ) M3M4_PR_M
+      NEW met2 ( 2013190 3011380 ) M2M3_PR_M
       NEW met3 ( 1338140 198900 ) M3M4_PR_M
       NEW met2 ( 1338370 198900 ) M2M3_PR_M
-      NEW met1 ( 1407370 206890 ) M1M2_PR
-      NEW met2 ( 1407370 198900 ) M2M3_PR_M
-      NEW met3 ( 1414500 198900 ) M3M4_PR_M
+      NEW met2 ( 1386670 197540 ) M2M3_PR_M
+      NEW met3 ( 1413580 197540 ) M3M4_PR_M
       NEW met3 ( 1414500 200260 ) M3M4_PR_M
       NEW met3 ( 1338140 198900 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[16\] ( mprj imem_data[16] ) ( mem dout0[16] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 2160020 0 ) ( 2505390 * )
-      NEW met2 ( 2505390 201110 ) ( * 2160020 )
+      + ROUTED met3 ( 2499180 2160020 0 ) ( 2514130 * )
+      NEW met2 ( 2514130 201110 ) ( * 2160020 )
       NEW met2 ( 1351250 198900 ) ( * 201110 )
       NEW met3 ( 1351020 198900 ) ( 1351250 * )
       NEW met4 ( 1351020 198900 ) ( 1351070 * )
       NEW met4 ( 1351070 198900 ) ( * 202300 0 )
-      NEW met1 ( 1351250 201110 ) ( 2505390 * )
-      NEW met1 ( 2505390 201110 ) M1M2_PR
-      NEW met2 ( 2505390 2160020 ) M2M3_PR_M
+      NEW met1 ( 1351250 201110 ) ( 2514130 * )
+      NEW met1 ( 2514130 201110 ) M1M2_PR
+      NEW met2 ( 2514130 2160020 ) M2M3_PR_M
       NEW met1 ( 1351250 201110 ) M1M2_PR
       NEW met2 ( 1351250 198900 ) M2M3_PR_M
       NEW met3 ( 1351020 198900 ) M3M4_PR_M
       NEW met3 ( 1351250 198900 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[17\] ( mprj imem_data[17] ) ( mem dout0[17] ) + USE SIGNAL
-      + ROUTED met2 ( 1532950 203660 ) ( * 207060 )
-      NEW met3 ( 1532950 203660 ) ( 1574580 * )
-      NEW met3 ( 1574580 203660 ) ( * 205020 )
-      NEW met2 ( 1770310 2999820 0 ) ( * 3011380 )
-      NEW met3 ( 1363990 207060 ) ( 1532950 * )
-      NEW met3 ( 1574580 205020 ) ( 1590220 * )
-      NEW met3 ( 1590220 3011380 ) ( 1770310 * )
-      NEW met4 ( 1590220 205020 ) ( * 3011380 )
-      NEW met4 ( 1363990 207000 ) ( * 207060 )
-      NEW met4 ( 1363990 205700 0 ) ( * 207000 )
-      NEW met3 ( 1363990 207060 ) M3M4_PR_M
-      NEW met2 ( 1532950 207060 ) M2M3_PR_M
-      NEW met2 ( 1532950 203660 ) M2M3_PR_M
-      NEW met2 ( 1770310 3011380 ) M2M3_PR_M
-      NEW met3 ( 1590220 205020 ) M3M4_PR_M
-      NEW met3 ( 1590220 3011380 ) M3M4_PR_M ;
+      + ROUTED met2 ( 1770310 2999820 0 ) ( * 3010700 )
+      NEW met4 ( 1569980 199580 ) ( * 3010700 )
+      NEW met3 ( 1569980 3010700 ) ( 1770310 * )
+      NEW met4 ( 1363900 198220 ) ( * 198900 )
+      NEW met4 ( 1363900 198900 ) ( 1363990 * )
+      NEW met4 ( 1363990 198900 ) ( * 202300 0 )
+      NEW met2 ( 1369650 198220 ) ( * 199580 )
+      NEW met3 ( 1363900 198220 ) ( 1369650 * )
+      NEW met3 ( 1369650 199580 ) ( 1569980 * )
+      NEW met3 ( 1569980 199580 ) M3M4_PR_M
+      NEW met3 ( 1569980 3010700 ) M3M4_PR_M
+      NEW met2 ( 1770310 3010700 ) M2M3_PR_M
+      NEW met3 ( 1363900 198220 ) M3M4_PR_M
+      NEW met2 ( 1369650 198220 ) M2M3_PR_M
+      NEW met2 ( 1369650 199580 ) M2M3_PR_M ;
     - imem_data\[18\] ( mprj imem_data[18] ) ( mem dout0[18] ) + USE SIGNAL
-      + ROUTED met2 ( 992910 201790 ) ( * 2819620 )
-      NEW met3 ( 992910 2819620 ) ( 1000500 * 0 )
+      + ROUTED met2 ( 996130 201790 ) ( * 2819620 )
+      NEW met3 ( 996130 2819620 ) ( 1000500 * 0 )
       NEW met2 ( 1377470 198900 ) ( * 201790 )
       NEW met3 ( 1377470 198900 ) ( 1377700 * )
       NEW met4 ( 1377590 198900 ) ( 1377700 * )
       NEW met4 ( 1377590 198900 ) ( * 202300 0 )
-      NEW met1 ( 992910 201790 ) ( 1377470 * )
-      NEW met1 ( 992910 201790 ) M1M2_PR
-      NEW met2 ( 992910 2819620 ) M2M3_PR_M
+      NEW met1 ( 996130 201790 ) ( 1377470 * )
+      NEW met1 ( 996130 201790 ) M1M2_PR
+      NEW met2 ( 996130 2819620 ) M2M3_PR_M
       NEW met1 ( 1377470 201790 ) M1M2_PR
       NEW met2 ( 1377470 198900 ) M2M3_PR_M
       NEW met3 ( 1377700 198900 ) M3M4_PR_M
@@ -7689,43 +7673,41 @@
       NEW met4 ( 1155060 198900 ) ( * 200260 )
       NEW met4 ( 1153870 198900 ) ( 1155060 * )
       NEW met4 ( 1153870 198900 ) ( * 202300 0 )
-      NEW met2 ( 1576650 276000 ) ( 1577110 * )
-      NEW met2 ( 1577110 204510 ) ( * 276000 )
-      NEW met2 ( 1576650 276000 ) ( * 341530 )
-      NEW met1 ( 1576650 341530 ) ( 1973630 * )
+      NEW met2 ( 1583550 204510 ) ( * 341530 )
+      NEW met1 ( 1583550 341530 ) ( 1973630 * )
       NEW met2 ( 1973630 341530 ) ( * 1500420 0 )
-      NEW met1 ( 1158970 204510 ) ( 1577110 * )
+      NEW met1 ( 1158970 204510 ) ( 1583550 * )
       NEW met1 ( 1158970 204510 ) M1M2_PR
       NEW met2 ( 1158970 200260 ) M2M3_PR_M
       NEW met3 ( 1155060 200260 ) M3M4_PR_M
-      NEW met1 ( 1577110 204510 ) M1M2_PR
-      NEW met1 ( 1576650 341530 ) M1M2_PR
+      NEW met1 ( 1583550 204510 ) M1M2_PR
+      NEW met1 ( 1583550 341530 ) M1M2_PR
       NEW met1 ( 1973630 341530 ) M1M2_PR ;
     - imem_data\[20\] ( mprj imem_data[20] ) ( mem dout0[20] ) + USE SIGNAL
-      + ROUTED met2 ( 991990 201450 ) ( * 2339540 )
-      NEW met3 ( 991990 2339540 ) ( 1000500 * 0 )
+      + ROUTED met2 ( 992450 201450 ) ( * 2339540 )
+      NEW met3 ( 992450 2339540 ) ( 1000500 * 0 )
       NEW met2 ( 1403230 198900 ) ( * 201450 )
       NEW met3 ( 1403230 198900 ) ( 1403460 * )
       NEW met4 ( 1403430 198900 ) ( 1403460 * )
       NEW met4 ( 1403430 198900 ) ( * 202300 0 )
-      NEW met1 ( 991990 201450 ) ( 1403230 * )
-      NEW met1 ( 991990 201450 ) M1M2_PR
-      NEW met2 ( 991990 2339540 ) M2M3_PR_M
+      NEW met1 ( 992450 201450 ) ( 1403230 * )
+      NEW met1 ( 992450 201450 ) M1M2_PR
+      NEW met2 ( 992450 2339540 ) M2M3_PR_M
       NEW met1 ( 1403230 201450 ) M1M2_PR
       NEW met2 ( 1403230 198900 ) M2M3_PR_M
       NEW met3 ( 1403460 198900 ) M3M4_PR_M
       NEW met3 ( 1403230 198900 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[21\] ( mprj imem_data[21] ) ( mem dout0[21] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 2400740 0 ) ( 2513670 * )
-      NEW met2 ( 2513670 201450 ) ( * 2400740 )
+      + ROUTED met3 ( 2499180 2400740 0 ) ( 2513210 * )
+      NEW met2 ( 2513210 201450 ) ( * 2400740 )
       NEW met2 ( 1418410 198220 ) ( * 201450 )
       NEW met3 ( 1418180 198220 ) ( 1418410 * )
       NEW met4 ( 1418180 198220 ) ( * 198900 )
       NEW met4 ( 1417710 198900 ) ( 1418180 * )
       NEW met4 ( 1417710 198900 ) ( * 202300 0 )
-      NEW met1 ( 1418410 201450 ) ( 2513670 * )
-      NEW met1 ( 2513670 201450 ) M1M2_PR
-      NEW met2 ( 2513670 2400740 ) M2M3_PR_M
+      NEW met1 ( 1418410 201450 ) ( 2513210 * )
+      NEW met1 ( 2513210 201450 ) M1M2_PR
+      NEW met2 ( 2513210 2400740 ) M2M3_PR_M
       NEW met1 ( 1418410 201450 ) M1M2_PR
       NEW met2 ( 1418410 198220 ) M2M3_PR_M
       NEW met3 ( 1418180 198220 ) M3M4_PR_M
@@ -7749,23 +7731,34 @@
       NEW met1 ( 1890830 204170 ) M1M2_PR
       NEW met3 ( 1431290 198220 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[23\] ( mprj imem_data[23] ) ( mem dout0[23] ) + USE SIGNAL
-      + ROUTED met2 ( 1480510 197540 ) ( * 199580 )
-      NEW met3 ( 1443940 197540 ) ( 1480510 * )
-      NEW met4 ( 1443940 197540 ) ( * 198900 )
+      + ROUTED met2 ( 1448770 206550 ) ( * 207060 )
+      NEW met1 ( 1444170 206550 ) ( 1448770 * )
+      NEW met2 ( 1444170 198220 ) ( * 206550 )
+      NEW met3 ( 1443940 198220 ) ( 1444170 * )
+      NEW met4 ( 1443940 198220 ) ( * 198900 )
       NEW met4 ( 1443550 198900 ) ( 1443940 * )
       NEW met4 ( 1443550 198900 ) ( * 202300 0 )
-      NEW met3 ( 1533180 198220 ) ( * 199580 )
-      NEW met3 ( 1533180 198220 ) ( 1569980 * )
-      NEW met4 ( 1569980 198220 ) ( * 3008660 )
-      NEW met3 ( 1480510 199580 ) ( 1533180 * )
+      NEW met2 ( 1532950 203660 ) ( * 207060 )
+      NEW met3 ( 1532950 203660 ) ( 1574580 * )
+      NEW met3 ( 1574580 203660 ) ( * 206380 )
+      NEW met4 ( 2120140 205700 ) ( * 3008660 )
+      NEW met3 ( 1448770 207060 ) ( 1532950 * )
+      NEW met3 ( 1628400 205700 ) ( * 206380 )
+      NEW met3 ( 1574580 206380 ) ( 1628400 * )
+      NEW met3 ( 1628400 205700 ) ( 2120140 * )
       NEW met2 ( 2095070 2999820 0 ) ( * 3008660 )
-      NEW met3 ( 1569980 3008660 ) ( 2095070 * )
-      NEW met2 ( 1480510 199580 ) M2M3_PR_M
-      NEW met2 ( 1480510 197540 ) M2M3_PR_M
-      NEW met3 ( 1443940 197540 ) M3M4_PR_M
-      NEW met3 ( 1569980 198220 ) M3M4_PR_M
-      NEW met3 ( 1569980 3008660 ) M3M4_PR_M
-      NEW met2 ( 2095070 3008660 ) M2M3_PR_M ;
+      NEW met3 ( 2095070 3008660 ) ( 2120140 * )
+      NEW met2 ( 1448770 207060 ) M2M3_PR_M
+      NEW met1 ( 1448770 206550 ) M1M2_PR
+      NEW met1 ( 1444170 206550 ) M1M2_PR
+      NEW met2 ( 1444170 198220 ) M2M3_PR_M
+      NEW met3 ( 1443940 198220 ) M3M4_PR_M
+      NEW met2 ( 1532950 207060 ) M2M3_PR_M
+      NEW met2 ( 1532950 203660 ) M2M3_PR_M
+      NEW met3 ( 2120140 205700 ) M3M4_PR_M
+      NEW met3 ( 2120140 3008660 ) M3M4_PR_M
+      NEW met2 ( 2095070 3008660 ) M2M3_PR_M
+      NEW met3 ( 1444170 198220 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[24\] ( mprj imem_data[24] ) ( mem dout0[24] ) + USE SIGNAL
       + ROUTED met2 ( 1457050 198220 ) ( * 201790 )
       NEW met3 ( 1456820 198220 ) ( 1457050 * )
@@ -7789,18 +7782,19 @@
       NEW li1 ( 1522370 202810 ) L1M1_PR_MR
       NEW met3 ( 1457050 198220 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[25\] ( mprj imem_data[25] ) ( mem dout0[25] ) + USE SIGNAL
-      + ROUTED met2 ( 1469470 198900 ) ( * 202470 )
-      NEW met3 ( 1469470 198900 ) ( 1469700 * )
+      + ROUTED met2 ( 1469470 198220 ) ( * 202470 )
+      NEW met3 ( 1469470 198220 ) ( 1469700 * )
+      NEW met4 ( 1469700 198220 ) ( * 198900 )
       NEW met4 ( 1469390 198900 ) ( 1469700 * )
       NEW met4 ( 1469390 198900 ) ( * 202300 0 )
       NEW met1 ( 1469470 202470 ) ( 2373830 * )
       NEW met2 ( 2373830 1500420 ) ( 2379350 * 0 )
       NEW met2 ( 2373830 202470 ) ( * 1500420 )
       NEW met1 ( 1469470 202470 ) M1M2_PR
-      NEW met2 ( 1469470 198900 ) M2M3_PR_M
-      NEW met3 ( 1469700 198900 ) M3M4_PR_M
+      NEW met2 ( 1469470 198220 ) M2M3_PR_M
+      NEW met3 ( 1469700 198220 ) M3M4_PR_M
       NEW met1 ( 2373830 202470 ) M1M2_PR
-      NEW met3 ( 1469470 198900 ) RECT ( -390 -150 0 150 )  ;
+      NEW met3 ( 1469470 198220 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[26\] ( mprj imem_data[26] ) ( mem dout0[26] ) + USE SIGNAL
       + ROUTED met2 ( 1482810 198220 ) ( * 205530 )
       NEW met3 ( 1482580 198220 ) ( 1482810 * )
@@ -7816,16 +7810,16 @@
       NEW met1 ( 1725230 205530 ) M1M2_PR
       NEW met3 ( 1482810 198220 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[27\] ( mprj imem_data[27] ) ( mem dout0[27] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 1560260 0 ) ( 2515050 * )
-      NEW met2 ( 2515050 201790 ) ( * 1560260 )
+      + ROUTED met3 ( 2499180 1560260 0 ) ( 2506310 * )
+      NEW met2 ( 2506310 201790 ) ( * 1560260 )
       NEW met2 ( 1496610 198220 ) ( * 201790 )
       NEW met3 ( 1496380 198220 ) ( 1496610 * )
       NEW met4 ( 1496380 198220 ) ( * 198900 )
       NEW met4 ( 1495910 198900 ) ( 1496380 * )
       NEW met4 ( 1495910 198900 ) ( * 202300 0 )
-      NEW met1 ( 1496610 201790 ) ( 2515050 * )
-      NEW met1 ( 2515050 201790 ) M1M2_PR
-      NEW met2 ( 2515050 1560260 ) M2M3_PR_M
+      NEW met1 ( 1496610 201790 ) ( 2506310 * )
+      NEW met1 ( 2506310 201790 ) M1M2_PR
+      NEW met2 ( 2506310 1560260 ) M2M3_PR_M
       NEW met1 ( 1496610 201790 ) M1M2_PR
       NEW met2 ( 1496610 198220 ) M2M3_PR_M
       NEW met3 ( 1496380 198220 ) M3M4_PR_M
@@ -7834,9 +7828,9 @@
       + ROUTED met2 ( 993370 203830 ) ( * 2939300 )
       NEW met2 ( 1509030 198220 ) ( * 203830 )
       NEW met3 ( 1509030 198220 ) ( 1509260 * )
-      NEW met4 ( 1509260 198220 ) ( * 198900 )
-      NEW met4 ( 1509260 198900 ) ( 1509510 * )
-      NEW met4 ( 1509510 198900 ) ( * 202300 0 )
+      NEW met4 ( 1509260 198220 ) ( * 200260 )
+      NEW met4 ( 1509260 200260 ) ( 1509510 * )
+      NEW met4 ( 1509510 200260 ) ( * 202300 0 )
       NEW met3 ( 993370 2939300 ) ( 1000500 * 0 )
       NEW met1 ( 993370 203830 ) ( 1509030 * )
       NEW met1 ( 993370 203830 ) M1M2_PR
@@ -7846,21 +7840,21 @@
       NEW met3 ( 1509260 198220 ) M3M4_PR_M
       NEW met3 ( 1509030 198220 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[29\] ( mprj imem_data[29] ) ( mem dout0[29] ) + USE SIGNAL
-      + ROUTED met2 ( 992450 203490 ) ( * 2459220 )
-      NEW li1 ( 1485570 202810 ) ( * 203490 )
-      NEW li1 ( 1485570 202810 ) ( 1486490 * )
-      NEW met1 ( 1486490 202810 ) ( 1521910 * )
+      + ROUTED met2 ( 992910 203490 ) ( * 2459220 )
+      NEW li1 ( 1483730 202810 ) ( * 203490 )
+      NEW li1 ( 1483730 202810 ) ( 1484650 * )
+      NEW met1 ( 1484650 202810 ) ( 1521910 * )
       NEW met2 ( 1521910 198220 ) ( * 202810 )
       NEW met3 ( 1521910 198220 ) ( 1522140 * )
-      NEW met4 ( 1522140 198220 ) ( * 198900 )
-      NEW met4 ( 1522140 198900 ) ( 1522430 * )
-      NEW met4 ( 1522430 198900 ) ( * 202300 0 )
-      NEW met3 ( 992450 2459220 ) ( 1000500 * 0 )
-      NEW met1 ( 992450 203490 ) ( 1485570 * )
-      NEW met1 ( 992450 203490 ) M1M2_PR
-      NEW met2 ( 992450 2459220 ) M2M3_PR_M
-      NEW li1 ( 1485570 203490 ) L1M1_PR_MR
-      NEW li1 ( 1486490 202810 ) L1M1_PR_MR
+      NEW met4 ( 1522140 198220 ) ( * 200260 )
+      NEW met4 ( 1522140 200260 ) ( 1522430 * )
+      NEW met4 ( 1522430 200260 ) ( * 202300 0 )
+      NEW met3 ( 992910 2459220 ) ( 1000500 * 0 )
+      NEW met1 ( 992910 203490 ) ( 1483730 * )
+      NEW met1 ( 992910 203490 ) M1M2_PR
+      NEW met2 ( 992910 2459220 ) M2M3_PR_M
+      NEW li1 ( 1483730 203490 ) L1M1_PR_MR
+      NEW li1 ( 1484650 202810 ) L1M1_PR_MR
       NEW met1 ( 1521910 202810 ) M1M2_PR
       NEW met2 ( 1521910 198220 ) M2M3_PR_M
       NEW met3 ( 1522140 198220 ) M3M4_PR_M
@@ -7871,55 +7865,51 @@
       NEW met4 ( 1166100 198900 ) ( * 200260 )
       NEW met4 ( 1166100 198900 ) ( 1166790 * )
       NEW met4 ( 1166790 198900 ) ( * 202300 0 )
-      NEW met2 ( 996590 200770 ) ( * 2219860 )
-      NEW met3 ( 996590 2219860 ) ( 1000500 * 0 )
-      NEW met1 ( 996590 200770 ) ( 1166330 * )
-      NEW met1 ( 996590 200770 ) M1M2_PR
-      NEW met2 ( 996590 2219860 ) M2M3_PR_M
+      NEW met2 ( 997510 200770 ) ( * 2219860 )
+      NEW met3 ( 997510 2219860 ) ( 1000500 * 0 )
+      NEW met1 ( 997510 200770 ) ( 1166330 * )
+      NEW met1 ( 997510 200770 ) M1M2_PR
+      NEW met2 ( 997510 2219860 ) M2M3_PR_M
       NEW met1 ( 1166330 200770 ) M1M2_PR
       NEW met2 ( 1166330 200260 ) M2M3_PR_M
       NEW met3 ( 1166100 200260 ) M3M4_PR_M
       NEW met3 ( 1166330 200260 ) RECT ( 0 -150 390 150 )  ;
     - imem_data\[30\] ( mprj imem_data[30] ) ( mem dout0[30] ) + USE SIGNAL
       + ROUTED met4 ( 1535350 198900 ) ( * 202300 0 )
-      NEW met4 ( 1535350 198900 ) ( 1536860 * )
-      NEW met4 ( 1536860 198900 ) ( * 200260 )
-      NEW met3 ( 1536860 200260 ) ( 1537090 * )
-      NEW met2 ( 1537090 200260 ) ( * 203830 )
-      NEW met1 ( 1537090 203830 ) ( 1573890 * )
-      NEW met3 ( 1574580 549100 ) ( * 549780 )
-      NEW met3 ( 1574350 549780 ) ( 1574580 * )
-      NEW met2 ( 1573890 549780 ) ( 1574350 * )
-      NEW met2 ( 1573890 203830 ) ( * 549780 )
+      NEW met3 ( 1535250 198900 ) ( 1535350 * )
+      NEW met2 ( 1535250 198900 ) ( * 203830 )
+      NEW met1 ( 1535250 203830 ) ( 1575730 * )
+      NEW met2 ( 1575730 549100 ) ( 1576190 * )
+      NEW met2 ( 1575730 203830 ) ( * 549100 )
       NEW met3 ( 1203130 2996420 ) ( 1206580 * )
       NEW met2 ( 1201750 2996420 0 ) ( 1203130 * )
       NEW met4 ( 1206580 552500 ) ( * 2996420 )
       NEW met2 ( 1215550 549100 ) ( * 552500 )
       NEW met3 ( 1206580 552500 ) ( 1215550 * )
-      NEW met3 ( 1215550 549100 ) ( 1574580 * )
-      NEW met3 ( 1536860 200260 ) M3M4_PR_M
-      NEW met2 ( 1537090 200260 ) M2M3_PR_M
-      NEW met1 ( 1537090 203830 ) M1M2_PR
-      NEW met1 ( 1573890 203830 ) M1M2_PR
-      NEW met2 ( 1574350 549780 ) M2M3_PR_M
+      NEW met3 ( 1215550 549100 ) ( 1576190 * )
+      NEW met3 ( 1535350 198900 ) M3M4_PR_M
+      NEW met2 ( 1535250 198900 ) M2M3_PR_M
+      NEW met1 ( 1535250 203830 ) M1M2_PR
+      NEW met1 ( 1575730 203830 ) M1M2_PR
+      NEW met2 ( 1576190 549100 ) M2M3_PR_M
       NEW met3 ( 1206580 2996420 ) M3M4_PR_M
       NEW met2 ( 1203130 2996420 ) M2M3_PR_M
       NEW met3 ( 1206580 552500 ) M3M4_PR_M
       NEW met2 ( 1215550 552500 ) M2M3_PR_M
       NEW met2 ( 1215550 549100 ) M2M3_PR_M
-      NEW met3 ( 1536860 200260 ) RECT ( -390 -150 0 150 )  ;
+      NEW met3 ( 1535250 198900 ) RECT ( -520 -150 0 150 )  ;
     - imem_data\[31\] ( mprj imem_data[31] ) ( mem dout0[31] ) + USE SIGNAL
-      + ROUTED met1 ( 1573430 254830 ) ( 1576650 * )
+      + ROUTED met1 ( 1574810 254830 ) ( 1576650 * )
       NEW met2 ( 1576650 234260 ) ( * 254830 )
       NEW met3 ( 1576420 234260 ) ( 1576650 * )
       NEW met3 ( 1576420 233510 0 ) ( * 234260 )
-      NEW met1 ( 1567910 1490390 ) ( 1573430 * )
+      NEW met1 ( 1567910 1490390 ) ( 1574810 * )
       NEW met2 ( 1567910 1490390 ) ( * 1500420 0 )
-      NEW met2 ( 1573430 254830 ) ( * 1490390 )
-      NEW met1 ( 1573430 254830 ) M1M2_PR
+      NEW met2 ( 1574810 254830 ) ( * 1490390 )
+      NEW met1 ( 1574810 254830 ) M1M2_PR
       NEW met1 ( 1576650 254830 ) M1M2_PR
       NEW met2 ( 1576650 234260 ) M2M3_PR_M
-      NEW met1 ( 1573430 1490390 ) M1M2_PR
+      NEW met1 ( 1574810 1490390 ) M1M2_PR
       NEW met1 ( 1567910 1490390 ) M1M2_PR ;
     - imem_data\[3\] ( mprj imem_data[3] ) ( mem dout0[3] ) + USE SIGNAL
       + ROUTED met2 ( 1186570 200260 ) ( * 203660 )
@@ -7930,13 +7920,13 @@
       NEW li1 ( 1435430 202470 ) ( * 204170 )
       NEW met1 ( 1435430 202470 ) ( 1459810 * )
       NEW met1 ( 1459810 202470 ) ( * 202810 )
-      NEW met2 ( 1579870 200260 ) ( * 203490 )
+      NEW met2 ( 1578030 200260 ) ( * 203490 )
       NEW met4 ( 2255380 203660 ) ( * 2996420 )
-      NEW met2 ( 1486030 202810 ) ( * 203490 )
-      NEW met1 ( 1459810 202810 ) ( 1486030 * )
-      NEW met1 ( 1486030 203490 ) ( 1579870 * )
+      NEW met2 ( 1484190 202810 ) ( * 203490 )
+      NEW met1 ( 1459810 202810 ) ( 1484190 * )
+      NEW met1 ( 1484190 203490 ) ( 1578030 * )
       NEW met3 ( 1628400 200260 ) ( * 203660 )
-      NEW met3 ( 1579870 200260 ) ( 1628400 * )
+      NEW met3 ( 1578030 200260 ) ( 1628400 * )
       NEW met3 ( 1628400 203660 ) ( 2255380 * )
       NEW met2 ( 2256530 2996420 ) ( 2256990 * 0 )
       NEW met3 ( 2255380 2996420 ) ( 2256530 * )
@@ -7954,12 +7944,12 @@
       NEW met3 ( 1180820 200260 ) M3M4_PR_M
       NEW li1 ( 1435430 204170 ) L1M1_PR_MR
       NEW li1 ( 1435430 202470 ) L1M1_PR_MR
-      NEW met1 ( 1579870 203490 ) M1M2_PR
-      NEW met2 ( 1579870 200260 ) M2M3_PR_M
+      NEW met1 ( 1578030 203490 ) M1M2_PR
+      NEW met2 ( 1578030 200260 ) M2M3_PR_M
       NEW met3 ( 2255380 203660 ) M3M4_PR_M
       NEW met3 ( 2255380 2996420 ) M3M4_PR_M
-      NEW met1 ( 1486030 202810 ) M1M2_PR
-      NEW met1 ( 1486030 203490 ) M1M2_PR
+      NEW met1 ( 1484190 202810 ) M1M2_PR
+      NEW met1 ( 1484190 203490 ) M1M2_PR
       NEW met2 ( 2256530 2996420 ) M2M3_PR_M
       NEW met2 ( 1318130 203660 ) M2M3_PR_M
       NEW met1 ( 1319050 204170 ) M1M2_PR
@@ -7973,62 +7963,64 @@
       NEW met4 ( 1191860 198900 ) ( * 200260 )
       NEW met4 ( 1191860 198900 ) ( 1193310 * )
       NEW met4 ( 1193310 198900 ) ( * 202300 0 )
-      NEW met2 ( 1574350 204850 ) ( * 517500 )
       NEW met3 ( 1574580 551820 ) ( * 552500 )
-      NEW met3 ( 1574580 551820 ) ( 1574810 * )
-      NEW met2 ( 1574810 517500 ) ( * 551820 )
-      NEW met2 ( 1574350 517500 ) ( 1574810 * )
+      NEW met3 ( 1574580 551820 ) ( 1575270 * )
+      NEW met2 ( 1575270 204850 ) ( * 551820 )
       NEW met3 ( 1527890 2996420 ) ( 1531340 * )
       NEW met2 ( 1526510 2996420 0 ) ( 1527890 * )
       NEW met3 ( 1531340 552500 ) ( 1574580 * )
       NEW met4 ( 1531340 552500 ) ( * 2996420 )
-      NEW met1 ( 1193470 204850 ) ( 1574350 * )
+      NEW met1 ( 1193470 204850 ) ( 1575270 * )
       NEW met1 ( 1193470 204850 ) M1M2_PR
       NEW met2 ( 1193470 200260 ) M2M3_PR_M
       NEW met3 ( 1191860 200260 ) M3M4_PR_M
-      NEW met1 ( 1574350 204850 ) M1M2_PR
-      NEW met2 ( 1574810 551820 ) M2M3_PR_M
+      NEW met1 ( 1575270 204850 ) M1M2_PR
+      NEW met2 ( 1575270 551820 ) M2M3_PR_M
       NEW met3 ( 1531340 2996420 ) M3M4_PR_M
       NEW met2 ( 1527890 2996420 ) M2M3_PR_M
       NEW met3 ( 1531340 552500 ) M3M4_PR_M ;
     - imem_data\[5\] ( mprj imem_data[5] ) ( mem dout0[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 2640100 0 ) ( 2512750 * )
-      NEW met2 ( 2512750 200770 ) ( * 2640100 )
+      + ROUTED met3 ( 2499180 2640100 0 ) ( 2512290 * )
+      NEW met2 ( 2512290 200770 ) ( * 2640100 )
       NEW met2 ( 1207270 200260 ) ( * 200770 )
       NEW met3 ( 1207270 200260 ) ( 1207500 * )
       NEW met4 ( 1206230 200260 ) ( 1207500 * )
       NEW met4 ( 1206230 200260 ) ( * 202300 0 )
-      NEW met1 ( 1207270 200770 ) ( 2512750 * )
-      NEW met1 ( 2512750 200770 ) M1M2_PR
-      NEW met2 ( 2512750 2640100 ) M2M3_PR_M
+      NEW met1 ( 1207270 200770 ) ( 2512290 * )
+      NEW met1 ( 2512290 200770 ) M1M2_PR
+      NEW met2 ( 2512290 2640100 ) M2M3_PR_M
       NEW met1 ( 1207270 200770 ) M1M2_PR
       NEW met2 ( 1207270 200260 ) M2M3_PR_M
       NEW met3 ( 1207500 200260 ) M3M4_PR_M
       NEW met3 ( 1207270 200260 ) RECT ( -390 -150 0 150 )  ;
     - imem_data\[6\] ( mprj imem_data[6] ) ( mem dout0[6] ) + USE SIGNAL
-      + ROUTED met3 ( 1242460 199580 ) ( * 200260 )
-      NEW met3 ( 1471540 198900 ) ( * 199580 )
-      NEW met3 ( 1532260 197540 ) ( * 198900 )
-      NEW met3 ( 1532260 197540 ) ( 1574580 * )
-      NEW met2 ( 1932230 2999820 0 ) ( * 3010020 )
-      NEW met4 ( 1574580 197540 ) ( * 3010020 )
-      NEW met3 ( 1241540 199580 ) ( * 200260 )
-      NEW met3 ( 1232340 200260 ) ( 1241540 * )
+      + ROUTED met3 ( 1245220 199580 ) ( * 200260 )
+      NEW met3 ( 1532260 198220 ) ( * 198900 )
+      NEW met3 ( 1532260 198220 ) ( 1574580 * )
+      NEW met2 ( 1932230 2999820 0 ) ( * 3009340 )
+      NEW met4 ( 1574580 198220 ) ( * 3009340 )
+      NEW met3 ( 1242000 199580 ) ( 1245220 * )
+      NEW met3 ( 1242000 199580 ) ( * 200260 )
+      NEW met3 ( 1232340 200260 ) ( 1242000 * )
       NEW met3 ( 1232340 199580 ) ( * 200260 )
       NEW met3 ( 1227740 199580 ) ( 1232340 * )
       NEW met3 ( 1227740 199580 ) ( * 200260 )
       NEW met3 ( 1220380 200260 ) ( 1227740 * )
       NEW met4 ( 1219150 200260 ) ( 1220380 * )
       NEW met4 ( 1219150 200260 ) ( * 202300 0 )
-      NEW met3 ( 1241540 199580 ) ( 1242460 * )
-      NEW met3 ( 1471540 198900 ) ( 1532260 * )
-      NEW met3 ( 1574580 3010020 ) ( 1932230 * )
-      NEW met3 ( 1242460 200260 ) ( 1366200 * )
+      NEW met3 ( 1574580 3009340 ) ( 1932230 * )
+      NEW met3 ( 1245220 200260 ) ( 1366200 * )
+      NEW met3 ( 1414500 198900 ) ( 1532260 * )
       NEW met3 ( 1366200 199580 ) ( * 200260 )
-      NEW met3 ( 1366200 199580 ) ( 1471540 * )
-      NEW met3 ( 1574580 197540 ) M3M4_PR_M
-      NEW met3 ( 1574580 3010020 ) M3M4_PR_M
-      NEW met2 ( 1932230 3010020 ) M2M3_PR_M
+      NEW met3 ( 1366200 199580 ) ( 1368500 * )
+      NEW met3 ( 1368500 198900 ) ( * 199580 )
+      NEW met3 ( 1368500 198900 ) ( 1372180 * )
+      NEW met3 ( 1372180 198220 ) ( * 198900 )
+      NEW met3 ( 1372180 198220 ) ( 1414500 * )
+      NEW met3 ( 1414500 198220 ) ( * 198900 )
+      NEW met3 ( 1574580 198220 ) M3M4_PR_M
+      NEW met3 ( 1574580 3009340 ) M3M4_PR_M
+      NEW met2 ( 1932230 3009340 ) M2M3_PR_M
       NEW met3 ( 1220380 200260 ) M3M4_PR_M ;
     - imem_data\[7\] ( mprj imem_data[7] ) ( mem dout0[7] ) + USE SIGNAL
       + ROUTED met2 ( 999810 203150 ) ( * 3008490 )
@@ -8046,62 +8038,57 @@
       NEW met2 ( 1228430 200260 ) M2M3_PR_M
       NEW met3 ( 1231420 200260 ) M3M4_PR_M ;
     - imem_data\[8\] ( mprj imem_data[8] ) ( mem dout0[8] ) + USE SIGNAL
-      + ROUTED met2 ( 1244990 198220 ) ( * 202810 )
-      NEW met3 ( 1244990 198220 ) ( 1245220 * )
-      NEW met4 ( 1245220 198220 ) ( * 198900 )
-      NEW met4 ( 1245220 198900 ) ( 1245670 * )
+      + ROUTED met2 ( 1243610 200260 ) ( * 202810 )
+      NEW met3 ( 1243610 200260 ) ( 1244300 * )
+      NEW met4 ( 1244300 198900 ) ( * 200260 )
+      NEW met4 ( 1244300 198900 ) ( 1245670 * )
       NEW met4 ( 1245670 198900 ) ( * 202300 0 )
-      NEW met2 ( 1000270 202810 ) ( * 1500420 0 )
-      NEW met1 ( 1000270 202810 ) ( 1244990 * )
-      NEW met1 ( 1000270 202810 ) M1M2_PR
-      NEW met1 ( 1244990 202810 ) M1M2_PR
-      NEW met2 ( 1244990 198220 ) M2M3_PR_M
-      NEW met3 ( 1245220 198220 ) M3M4_PR_M
-      NEW met3 ( 1244990 198220 ) RECT ( -390 -150 0 150 )  ;
+      NEW met2 ( 1000270 1483590 ) ( * 1500420 0 )
+      NEW met1 ( 1003950 202810 ) ( 1243610 * )
+      NEW met1 ( 1000270 1483590 ) ( 1003950 * )
+      NEW met2 ( 1003950 202810 ) ( * 1483590 )
+      NEW met1 ( 1243610 202810 ) M1M2_PR
+      NEW met2 ( 1243610 200260 ) M2M3_PR_M
+      NEW met3 ( 1244300 200260 ) M3M4_PR_M
+      NEW met1 ( 1000270 1483590 ) M1M2_PR
+      NEW met1 ( 1003950 202810 ) M1M2_PR
+      NEW met1 ( 1003950 1483590 ) M1M2_PR ;
     - imem_data\[9\] ( mprj imem_data[9] ) ( mem dout0[9] ) + USE SIGNAL
       + ROUTED met2 ( 1259250 198220 ) ( * 205190 )
       NEW met3 ( 1259020 198220 ) ( 1259250 * )
       NEW met4 ( 1259020 198220 ) ( * 198900 )
       NEW met4 ( 1258590 198900 ) ( 1259020 * )
       NEW met4 ( 1258590 198900 ) ( * 202300 0 )
-      NEW met3 ( 1365970 2996420 ) ( 1375860 * )
-      NEW met2 ( 1364590 2996420 0 ) ( 1365970 * )
-      NEW met2 ( 1543990 1062330 ) ( * 1076270 )
-      NEW met1 ( 1543990 1062330 ) ( 1556870 * )
-      NEW met4 ( 1375860 1458940 ) ( * 2996420 )
-      NEW met1 ( 1438650 1214310 ) ( 1466250 * )
-      NEW met2 ( 1466250 1190170 ) ( * 1214310 )
-      NEW met2 ( 1438650 1214310 ) ( * 1421370 )
-      NEW met1 ( 1556870 1041930 ) ( 1570210 * )
-      NEW met2 ( 1556870 1041930 ) ( * 1062330 )
-      NEW met2 ( 1570210 205190 ) ( * 1041930 )
-      NEW met3 ( 1375860 1458940 ) ( 1411050 * )
-      NEW met1 ( 1528350 1076270 ) ( 1543990 * )
-      NEW met1 ( 1466250 1190170 ) ( 1528350 * )
-      NEW met2 ( 1411050 1421370 ) ( * 1458940 )
-      NEW met1 ( 1411050 1421370 ) ( 1438650 * )
-      NEW met2 ( 1528350 1076270 ) ( * 1190170 )
+      NEW met2 ( 1364590 2999820 0 ) ( * 3008660 )
+      NEW met1 ( 1452450 1317670 ) ( 1476830 * )
+      NEW met2 ( 1476830 1300670 ) ( * 1317670 )
+      NEW met2 ( 1452450 1317670 ) ( * 1424260 )
+      NEW met1 ( 1562850 1133050 ) ( 1570210 * )
+      NEW met2 ( 1570210 205190 ) ( * 1133050 )
+      NEW met2 ( 1562850 1133050 ) ( * 1265990 )
+      NEW met3 ( 1364590 3008660 ) ( 1389660 * )
+      NEW met1 ( 1507650 1265990 ) ( 1562850 * )
+      NEW met3 ( 1389660 1424260 ) ( 1452450 * )
+      NEW met4 ( 1389660 1424260 ) ( * 3008660 )
+      NEW met1 ( 1476830 1300670 ) ( 1507650 * )
+      NEW met2 ( 1507650 1265990 ) ( * 1300670 )
       NEW met1 ( 1259250 205190 ) ( 1570210 * )
       NEW met1 ( 1259250 205190 ) M1M2_PR
       NEW met2 ( 1259250 198220 ) M2M3_PR_M
       NEW met3 ( 1259020 198220 ) M3M4_PR_M
-      NEW met3 ( 1375860 1458940 ) M3M4_PR_M
-      NEW met3 ( 1375860 2996420 ) M3M4_PR_M
-      NEW met2 ( 1365970 2996420 ) M2M3_PR_M
-      NEW met1 ( 1466250 1190170 ) M1M2_PR
+      NEW met2 ( 1364590 3008660 ) M2M3_PR_M
       NEW met1 ( 1570210 205190 ) M1M2_PR
-      NEW met1 ( 1543990 1076270 ) M1M2_PR
-      NEW met1 ( 1543990 1062330 ) M1M2_PR
-      NEW met1 ( 1556870 1062330 ) M1M2_PR
-      NEW met1 ( 1438650 1214310 ) M1M2_PR
-      NEW met1 ( 1466250 1214310 ) M1M2_PR
-      NEW met1 ( 1438650 1421370 ) M1M2_PR
-      NEW met1 ( 1556870 1041930 ) M1M2_PR
-      NEW met1 ( 1570210 1041930 ) M1M2_PR
-      NEW met2 ( 1411050 1458940 ) M2M3_PR_M
-      NEW met1 ( 1528350 1076270 ) M1M2_PR
-      NEW met1 ( 1528350 1190170 ) M1M2_PR
-      NEW met1 ( 1411050 1421370 ) M1M2_PR
+      NEW met1 ( 1562850 1265990 ) M1M2_PR
+      NEW met1 ( 1452450 1317670 ) M1M2_PR
+      NEW met1 ( 1476830 1317670 ) M1M2_PR
+      NEW met1 ( 1476830 1300670 ) M1M2_PR
+      NEW met2 ( 1452450 1424260 ) M2M3_PR_M
+      NEW met1 ( 1562850 1133050 ) M1M2_PR
+      NEW met1 ( 1570210 1133050 ) M1M2_PR
+      NEW met3 ( 1389660 3008660 ) M3M4_PR_M
+      NEW met1 ( 1507650 1265990 ) M1M2_PR
+      NEW met3 ( 1389660 1424260 ) M3M4_PR_M
+      NEW met1 ( 1507650 1300670 ) M1M2_PR
       NEW met3 ( 1259250 198220 ) RECT ( 0 -150 390 150 )  ;
     - io_in[0] ( PIN io_in[0] ) + USE SIGNAL ;
     - io_in[10] ( PIN io_in[10] ) + USE SIGNAL ;
@@ -8217,7 +8204,19 @@
     - io_out[7] ( PIN io_out[7] ) + USE SIGNAL ;
     - io_out[8] ( PIN io_out[8] ) + USE SIGNAL ;
     - io_out[9] ( PIN io_out[9] ) + USE SIGNAL ;
-    - la_data_in[0] ( PIN la_data_in[0] ) + USE SIGNAL ;
+    - la_data_in[0] ( PIN la_data_in[0] ) ( mem din0[0] ) + USE SIGNAL
+      + ROUTED met2 ( 629510 2380 0 ) ( * 17510 )
+      NEW met1 ( 1107450 17170 ) ( * 17510 )
+      NEW met1 ( 1107450 17170 ) ( 1125390 * )
+      NEW met1 ( 629510 17510 ) ( 1107450 * )
+      NEW met3 ( 1125390 198900 ) ( 1131140 * )
+      NEW met4 ( 1131140 198900 ) ( 1131430 * )
+      NEW met4 ( 1131430 198900 ) ( * 202300 0 )
+      NEW met2 ( 1125390 17170 ) ( * 198900 )
+      NEW met1 ( 629510 17510 ) M1M2_PR
+      NEW met1 ( 1125390 17170 ) M1M2_PR
+      NEW met2 ( 1125390 198900 ) M2M3_PR_M
+      NEW met3 ( 1131140 198900 ) M3M4_PR_M ;
     - la_data_in[100] ( PIN la_data_in[100] ) + USE SIGNAL ;
     - la_data_in[101] ( PIN la_data_in[101] ) + USE SIGNAL ;
     - la_data_in[102] ( PIN la_data_in[102] ) + USE SIGNAL ;
@@ -8228,7 +8227,18 @@
     - la_data_in[107] ( PIN la_data_in[107] ) + USE SIGNAL ;
     - la_data_in[108] ( PIN la_data_in[108] ) + USE SIGNAL ;
     - la_data_in[109] ( PIN la_data_in[109] ) + USE SIGNAL ;
-    - la_data_in[10] ( PIN la_data_in[10] ) + USE SIGNAL ;
+    - la_data_in[10] ( PIN la_data_in[10] ) ( mem din0[10] ) + USE SIGNAL
+      + ROUTED met2 ( 806610 2380 0 ) ( * 17850 )
+      NEW met3 ( 1262700 198900 ) ( 1262930 * )
+      NEW met4 ( 1262670 198900 ) ( 1262700 * )
+      NEW met4 ( 1262670 198900 ) ( * 202300 0 )
+      NEW met2 ( 1262930 17850 ) ( * 198900 )
+      NEW met1 ( 806610 17850 ) ( 1262930 * )
+      NEW met1 ( 806610 17850 ) M1M2_PR
+      NEW met1 ( 1262930 17850 ) M1M2_PR
+      NEW met2 ( 1262930 198900 ) M2M3_PR_M
+      NEW met3 ( 1262700 198900 ) M3M4_PR_M
+      NEW met3 ( 1262930 198900 ) RECT ( 0 -150 390 150 )  ;
     - la_data_in[110] ( PIN la_data_in[110] ) + USE SIGNAL ;
     - la_data_in[111] ( PIN la_data_in[111] ) + USE SIGNAL ;
     - la_data_in[112] ( PIN la_data_in[112] ) + USE SIGNAL ;
@@ -8239,7 +8249,17 @@
     - la_data_in[117] ( PIN la_data_in[117] ) + USE SIGNAL ;
     - la_data_in[118] ( PIN la_data_in[118] ) + USE SIGNAL ;
     - la_data_in[119] ( PIN la_data_in[119] ) + USE SIGNAL ;
-    - la_data_in[11] ( PIN la_data_in[11] ) + USE SIGNAL ;
+    - la_data_in[11] ( PIN la_data_in[11] ) ( mem din0[11] ) + USE SIGNAL
+      + ROUTED met3 ( 1269830 198900 ) ( 1275580 * )
+      NEW met4 ( 1275580 198900 ) ( 1275590 * )
+      NEW met4 ( 1275590 198900 ) ( * 202300 0 )
+      NEW met2 ( 1269830 18190 ) ( * 198900 )
+      NEW met2 ( 824550 2380 0 ) ( * 18190 )
+      NEW met1 ( 824550 18190 ) ( 1269830 * )
+      NEW met1 ( 1269830 18190 ) M1M2_PR
+      NEW met2 ( 1269830 198900 ) M2M3_PR_M
+      NEW met3 ( 1275580 198900 ) M3M4_PR_M
+      NEW met1 ( 824550 18190 ) M1M2_PR ;
     - la_data_in[120] ( PIN la_data_in[120] ) + USE SIGNAL ;
     - la_data_in[121] ( PIN la_data_in[121] ) + USE SIGNAL ;
     - la_data_in[122] ( PIN la_data_in[122] ) + USE SIGNAL ;
@@ -8248,50 +8268,453 @@
     - la_data_in[125] ( PIN la_data_in[125] ) + USE SIGNAL ;
     - la_data_in[126] ( PIN la_data_in[126] ) + USE SIGNAL ;
     - la_data_in[127] ( PIN la_data_in[127] ) + USE SIGNAL ;
-    - la_data_in[12] ( PIN la_data_in[12] ) + USE SIGNAL ;
-    - la_data_in[13] ( PIN la_data_in[13] ) + USE SIGNAL ;
-    - la_data_in[14] ( PIN la_data_in[14] ) + USE SIGNAL ;
-    - la_data_in[15] ( PIN la_data_in[15] ) + USE SIGNAL ;
-    - la_data_in[16] ( PIN la_data_in[16] ) + USE SIGNAL ;
-    - la_data_in[17] ( PIN la_data_in[17] ) + USE SIGNAL ;
-    - la_data_in[18] ( PIN la_data_in[18] ) + USE SIGNAL ;
-    - la_data_in[19] ( PIN la_data_in[19] ) + USE SIGNAL ;
-    - la_data_in[1] ( PIN la_data_in[1] ) + USE SIGNAL ;
-    - la_data_in[20] ( PIN la_data_in[20] ) + USE SIGNAL ;
-    - la_data_in[21] ( PIN la_data_in[21] ) + USE SIGNAL ;
-    - la_data_in[22] ( PIN la_data_in[22] ) + USE SIGNAL ;
-    - la_data_in[23] ( PIN la_data_in[23] ) + USE SIGNAL ;
-    - la_data_in[24] ( PIN la_data_in[24] ) + USE SIGNAL ;
-    - la_data_in[25] ( PIN la_data_in[25] ) + USE SIGNAL ;
-    - la_data_in[26] ( PIN la_data_in[26] ) + USE SIGNAL ;
-    - la_data_in[27] ( PIN la_data_in[27] ) + USE SIGNAL ;
-    - la_data_in[28] ( PIN la_data_in[28] ) + USE SIGNAL ;
-    - la_data_in[29] ( PIN la_data_in[29] ) + USE SIGNAL ;
-    - la_data_in[2] ( PIN la_data_in[2] ) + USE SIGNAL ;
-    - la_data_in[30] ( PIN la_data_in[30] ) + USE SIGNAL ;
-    - la_data_in[31] ( PIN la_data_in[31] ) + USE SIGNAL ;
-    - la_data_in[32] ( PIN la_data_in[32] ) + USE SIGNAL ;
+    - la_data_in[12] ( PIN la_data_in[12] ) ( mem din0[12] ) + USE SIGNAL
+      + ROUTED met3 ( 1283630 198900 ) ( 1288460 * )
+      NEW met4 ( 1288460 198900 ) ( 1288510 * )
+      NEW met4 ( 1288510 198900 ) ( * 202300 0 )
+      NEW met2 ( 1283630 19550 ) ( * 198900 )
+      NEW met2 ( 842030 2380 0 ) ( * 19550 )
+      NEW met1 ( 842030 19550 ) ( 1283630 * )
+      NEW met1 ( 1283630 19550 ) M1M2_PR
+      NEW met2 ( 1283630 198900 ) M2M3_PR_M
+      NEW met3 ( 1288460 198900 ) M3M4_PR_M
+      NEW met1 ( 842030 19550 ) M1M2_PR ;
+    - la_data_in[13] ( PIN la_data_in[13] ) ( mem din0[13] ) + USE SIGNAL
+      + ROUTED met2 ( 859970 2380 0 ) ( * 19890 )
+      NEW met1 ( 859970 19890 ) ( 1297430 * )
+      NEW met3 ( 1297430 198900 ) ( 1301340 * )
+      NEW met4 ( 1301340 198900 ) ( 1301430 * )
+      NEW met4 ( 1301430 198900 ) ( * 202300 0 )
+      NEW met2 ( 1297430 19890 ) ( * 198900 )
+      NEW met1 ( 859970 19890 ) M1M2_PR
+      NEW met1 ( 1297430 19890 ) M1M2_PR
+      NEW met2 ( 1297430 198900 ) M2M3_PR_M
+      NEW met3 ( 1301340 198900 ) M3M4_PR_M ;
+    - la_data_in[14] ( PIN la_data_in[14] ) ( mem din0[14] ) + USE SIGNAL
+      + ROUTED met2 ( 877450 2380 0 ) ( * 20570 )
+      NEW met1 ( 877450 20570 ) ( 1311230 * )
+      NEW met3 ( 1311230 198900 ) ( 1315140 * )
+      NEW met4 ( 1315030 198900 ) ( 1315140 * )
+      NEW met4 ( 1315030 198900 ) ( * 202300 0 )
+      NEW met2 ( 1311230 20570 ) ( * 198900 )
+      NEW met1 ( 877450 20570 ) M1M2_PR
+      NEW met1 ( 1311230 20570 ) M1M2_PR
+      NEW met2 ( 1311230 198900 ) M2M3_PR_M
+      NEW met3 ( 1315140 198900 ) M3M4_PR_M ;
+    - la_data_in[15] ( PIN la_data_in[15] ) ( mem din0[15] ) + USE SIGNAL
+      + ROUTED met2 ( 895390 2380 0 ) ( * 20230 )
+      NEW met1 ( 895390 20230 ) ( 1325030 * )
+      NEW met3 ( 1325030 193460 ) ( 1328020 * )
+      NEW met4 ( 1328020 193460 ) ( * 198900 )
+      NEW met4 ( 1328020 198900 ) ( 1328630 * )
+      NEW met4 ( 1328630 198900 ) ( * 202300 0 )
+      NEW met2 ( 1325030 20230 ) ( * 193460 )
+      NEW met1 ( 895390 20230 ) M1M2_PR
+      NEW met1 ( 1325030 20230 ) M1M2_PR
+      NEW met2 ( 1325030 193460 ) M2M3_PR_M
+      NEW met3 ( 1328020 193460 ) M3M4_PR_M ;
+    - la_data_in[16] ( PIN la_data_in[16] ) ( mem din0[16] ) + USE SIGNAL
+      + ROUTED met2 ( 912870 2380 0 ) ( * 16830 )
+      NEW met1 ( 912870 16830 ) ( 1338830 * )
+      NEW met3 ( 1338830 193460 ) ( 1340900 * )
+      NEW met4 ( 1340900 193460 ) ( * 198900 )
+      NEW met4 ( 1340870 198900 ) ( 1340900 * )
+      NEW met4 ( 1340870 198900 ) ( * 202300 0 )
+      NEW met2 ( 1338830 16830 ) ( * 193460 )
+      NEW met1 ( 1338830 16830 ) M1M2_PR
+      NEW met1 ( 912870 16830 ) M1M2_PR
+      NEW met2 ( 1338830 193460 ) M2M3_PR_M
+      NEW met3 ( 1340900 193460 ) M3M4_PR_M ;
+    - la_data_in[17] ( PIN la_data_in[17] ) ( mem din0[17] ) + USE SIGNAL
+      + ROUTED met2 ( 930810 2380 0 ) ( * 16490 )
+      NEW met1 ( 930810 16490 ) ( 1352630 * )
+      NEW met3 ( 1352630 198900 ) ( 1354700 * )
+      NEW met4 ( 1354470 198900 ) ( 1354700 * )
+      NEW met4 ( 1354470 198900 ) ( * 202300 0 )
+      NEW met2 ( 1352630 16490 ) ( * 198900 )
+      NEW met1 ( 1352630 16490 ) M1M2_PR
+      NEW met1 ( 930810 16490 ) M1M2_PR
+      NEW met2 ( 1352630 198900 ) M2M3_PR_M
+      NEW met3 ( 1354700 198900 ) M3M4_PR_M ;
+    - la_data_in[18] ( PIN la_data_in[18] ) ( mem din0[18] ) + USE SIGNAL
+      + ROUTED met2 ( 948750 2380 0 ) ( * 16150 )
+      NEW met1 ( 948750 16150 ) ( 1366430 * )
+      NEW met3 ( 1366430 198900 ) ( 1367580 * )
+      NEW met4 ( 1367390 198900 ) ( 1367580 * )
+      NEW met4 ( 1367390 198900 ) ( * 202300 0 )
+      NEW met2 ( 1366430 16150 ) ( * 198900 )
+      NEW met1 ( 1366430 16150 ) M1M2_PR
+      NEW met1 ( 948750 16150 ) M1M2_PR
+      NEW met2 ( 1366430 198900 ) M2M3_PR_M
+      NEW met3 ( 1367580 198900 ) M3M4_PR_M ;
+    - la_data_in[19] ( PIN la_data_in[19] ) ( mem din0[19] ) + USE SIGNAL
+      + ROUTED met2 ( 966230 2380 0 ) ( * 18530 )
+      NEW met1 ( 966230 18530 ) ( 972670 * )
+      NEW met2 ( 972670 18530 ) ( * 196010 )
+      NEW met2 ( 1380230 196010 ) ( * 196180 )
+      NEW met3 ( 1380230 196180 ) ( 1380460 * )
+      NEW met4 ( 1380460 196180 ) ( * 198900 )
+      NEW met4 ( 1380460 198900 ) ( 1380990 * )
+      NEW met4 ( 1380990 198900 ) ( * 202300 0 )
+      NEW met1 ( 972670 196010 ) ( 1380230 * )
+      NEW met1 ( 966230 18530 ) M1M2_PR
+      NEW met1 ( 972670 18530 ) M1M2_PR
+      NEW met1 ( 972670 196010 ) M1M2_PR
+      NEW met1 ( 1380230 196010 ) M1M2_PR
+      NEW met2 ( 1380230 196180 ) M2M3_PR_M
+      NEW met3 ( 1380460 196180 ) M3M4_PR_M
+      NEW met3 ( 1380230 196180 ) RECT ( -390 -150 0 150 )  ;
+    - la_data_in[1] ( PIN la_data_in[1] ) ( mem din0[1] ) + USE SIGNAL
+      + ROUTED met2 ( 1138730 193290 ) ( * 193460 )
+      NEW met3 ( 1138730 193460 ) ( 1143100 * )
+      NEW met4 ( 1143100 193460 ) ( * 198900 )
+      NEW met4 ( 1143100 198900 ) ( 1143670 * )
+      NEW met4 ( 1143670 198900 ) ( * 202300 0 )
+      NEW met1 ( 648370 193290 ) ( 1138730 * )
+      NEW met2 ( 646990 2380 0 ) ( * 34500 )
+      NEW met2 ( 646990 34500 ) ( 648370 * )
+      NEW met2 ( 648370 34500 ) ( * 193290 )
+      NEW met1 ( 648370 193290 ) M1M2_PR
+      NEW met1 ( 1138730 193290 ) M1M2_PR
+      NEW met2 ( 1138730 193460 ) M2M3_PR_M
+      NEW met3 ( 1143100 193460 ) M3M4_PR_M ;
+    - la_data_in[20] ( PIN la_data_in[20] ) ( mem din0[20] ) + USE SIGNAL
+      + ROUTED met2 ( 984170 2380 0 ) ( * 18530 )
+      NEW met1 ( 984170 18530 ) ( 986470 * )
+      NEW met2 ( 986470 18530 ) ( * 196350 )
+      NEW met2 ( 1392650 196350 ) ( * 198900 )
+      NEW met3 ( 1392650 198900 ) ( 1393340 * )
+      NEW met4 ( 1393230 198900 ) ( 1393340 * )
+      NEW met4 ( 1393230 198900 ) ( * 202300 0 )
+      NEW met1 ( 986470 196350 ) ( 1392650 * )
+      NEW met1 ( 984170 18530 ) M1M2_PR
+      NEW met1 ( 986470 18530 ) M1M2_PR
+      NEW met1 ( 986470 196350 ) M1M2_PR
+      NEW met1 ( 1392650 196350 ) M1M2_PR
+      NEW met2 ( 1392650 198900 ) M2M3_PR_M
+      NEW met3 ( 1393340 198900 ) M3M4_PR_M ;
+    - la_data_in[21] ( PIN la_data_in[21] ) ( mem din0[21] ) + USE SIGNAL
+      + ROUTED met2 ( 1001650 2380 0 ) ( * 18530 )
+      NEW met1 ( 1001650 18530 ) ( 1007170 * )
+      NEW met2 ( 1007170 18530 ) ( * 198050 )
+      NEW met2 ( 1404150 198050 ) ( * 198900 )
+      NEW met3 ( 1404150 198900 ) ( 1407140 * )
+      NEW met4 ( 1406830 198900 ) ( 1407140 * )
+      NEW met4 ( 1406830 198900 ) ( * 202300 0 )
+      NEW met1 ( 1007170 198050 ) ( 1404150 * )
+      NEW met1 ( 1001650 18530 ) M1M2_PR
+      NEW met1 ( 1007170 18530 ) M1M2_PR
+      NEW met1 ( 1007170 198050 ) M1M2_PR
+      NEW met1 ( 1404150 198050 ) M1M2_PR
+      NEW met2 ( 1404150 198900 ) M2M3_PR_M
+      NEW met3 ( 1407140 198900 ) M3M4_PR_M ;
+    - la_data_in[22] ( PIN la_data_in[22] ) ( mem din0[22] ) + USE SIGNAL
+      + ROUTED met2 ( 1414730 196690 ) ( * 196860 )
+      NEW met3 ( 1414730 196860 ) ( 1420020 * )
+      NEW met4 ( 1420020 196860 ) ( * 198900 )
+      NEW met4 ( 1420020 198900 ) ( 1420430 * )
+      NEW met4 ( 1420430 198900 ) ( * 202300 0 )
+      NEW met2 ( 1019590 2380 0 ) ( * 34500 )
+      NEW met2 ( 1019590 34500 ) ( 1020970 * )
+      NEW met2 ( 1020970 34500 ) ( * 196690 )
+      NEW met1 ( 1020970 196690 ) ( 1414730 * )
+      NEW met1 ( 1020970 196690 ) M1M2_PR
+      NEW met1 ( 1414730 196690 ) M1M2_PR
+      NEW met2 ( 1414730 196860 ) M2M3_PR_M
+      NEW met3 ( 1420020 196860 ) M3M4_PR_M ;
+    - la_data_in[23] ( PIN la_data_in[23] ) ( mem din0[23] ) + USE SIGNAL
+      + ROUTED met2 ( 1037070 2380 0 ) ( * 17170 )
+      NEW met1 ( 1037070 17170 ) ( 1041670 * )
+      NEW met2 ( 1428530 197030 ) ( * 197540 )
+      NEW met3 ( 1428530 197540 ) ( 1432900 * )
+      NEW met4 ( 1432900 197540 ) ( * 198900 )
+      NEW met4 ( 1432900 198900 ) ( 1433350 * )
+      NEW met4 ( 1433350 198900 ) ( * 202300 0 )
+      NEW met2 ( 1041670 17170 ) ( * 197030 )
+      NEW met1 ( 1041670 197030 ) ( 1428530 * )
+      NEW met1 ( 1037070 17170 ) M1M2_PR
+      NEW met1 ( 1041670 17170 ) M1M2_PR
+      NEW met1 ( 1041670 197030 ) M1M2_PR
+      NEW met1 ( 1428530 197030 ) M1M2_PR
+      NEW met2 ( 1428530 197540 ) M2M3_PR_M
+      NEW met3 ( 1432900 197540 ) M3M4_PR_M ;
+    - la_data_in[24] ( PIN la_data_in[24] ) ( mem din0[24] ) + USE SIGNAL
+      + ROUTED met2 ( 1442330 194310 ) ( * 196180 )
+      NEW met3 ( 1442330 196180 ) ( 1445780 * )
+      NEW met4 ( 1445780 196180 ) ( * 198900 )
+      NEW met4 ( 1445590 198900 ) ( 1445780 * )
+      NEW met4 ( 1445590 198900 ) ( * 202300 0 )
+      NEW met2 ( 1055010 2380 0 ) ( * 34500 )
+      NEW met2 ( 1055010 34500 ) ( 1055470 * )
+      NEW met2 ( 1055470 34500 ) ( * 194310 )
+      NEW met1 ( 1055470 194310 ) ( 1442330 * )
+      NEW met1 ( 1055470 194310 ) M1M2_PR
+      NEW met1 ( 1442330 194310 ) M1M2_PR
+      NEW met2 ( 1442330 196180 ) M2M3_PR_M
+      NEW met3 ( 1445780 196180 ) M3M4_PR_M ;
+    - la_data_in[25] ( PIN la_data_in[25] ) ( mem din0[25] ) + USE SIGNAL
+      + ROUTED met2 ( 1072490 2380 0 ) ( * 17170 )
+      NEW met1 ( 1072490 17170 ) ( 1076170 * )
+      NEW met2 ( 1456130 193970 ) ( * 194140 )
+      NEW met3 ( 1456130 194140 ) ( 1458660 * )
+      NEW met4 ( 1458660 194140 ) ( * 198900 )
+      NEW met4 ( 1458660 198900 ) ( 1459190 * )
+      NEW met4 ( 1459190 198900 ) ( * 202300 0 )
+      NEW met2 ( 1076170 17170 ) ( * 193970 )
+      NEW met1 ( 1076170 193970 ) ( 1456130 * )
+      NEW met1 ( 1072490 17170 ) M1M2_PR
+      NEW met1 ( 1076170 17170 ) M1M2_PR
+      NEW met1 ( 1076170 193970 ) M1M2_PR
+      NEW met1 ( 1456130 193970 ) M1M2_PR
+      NEW met2 ( 1456130 194140 ) M2M3_PR_M
+      NEW met3 ( 1458660 194140 ) M3M4_PR_M ;
+    - la_data_in[26] ( PIN la_data_in[26] ) ( mem din0[26] ) + USE SIGNAL
+      + ROUTED met2 ( 1090430 2380 0 ) ( * 17170 )
+      NEW met1 ( 1090430 17170 ) ( 1096870 * )
+      NEW met2 ( 1470390 198220 ) ( * 199070 )
+      NEW met3 ( 1470390 198220 ) ( 1471540 * )
+      NEW met4 ( 1471540 198220 ) ( * 198900 )
+      NEW met4 ( 1471540 198900 ) ( 1472110 * )
+      NEW met4 ( 1472110 198900 ) ( * 202300 0 )
+      NEW met2 ( 1096870 17170 ) ( * 199070 )
+      NEW met1 ( 1096870 199070 ) ( 1470390 * )
+      NEW met1 ( 1090430 17170 ) M1M2_PR
+      NEW met1 ( 1096870 17170 ) M1M2_PR
+      NEW met1 ( 1096870 199070 ) M1M2_PR
+      NEW met1 ( 1470390 199070 ) M1M2_PR
+      NEW met2 ( 1470390 198220 ) M2M3_PR_M
+      NEW met3 ( 1471540 198220 ) M3M4_PR_M ;
+    - la_data_in[27] ( PIN la_data_in[27] ) ( mem din0[27] ) + USE SIGNAL
+      + ROUTED met2 ( 1107910 2380 0 ) ( * 17510 )
+      NEW met1 ( 1107910 17510 ) ( 1110670 * )
+      NEW met2 ( 1484190 194990 ) ( * 197540 )
+      NEW met3 ( 1484190 197540 ) ( 1485340 * )
+      NEW met4 ( 1485340 197540 ) ( * 200260 )
+      NEW met4 ( 1485030 200260 ) ( 1485340 * )
+      NEW met4 ( 1485030 200260 ) ( * 202300 0 )
+      NEW met2 ( 1110670 17510 ) ( * 194990 )
+      NEW met1 ( 1110670 194990 ) ( 1484190 * )
+      NEW met1 ( 1107910 17510 ) M1M2_PR
+      NEW met1 ( 1110670 17510 ) M1M2_PR
+      NEW met1 ( 1110670 194990 ) M1M2_PR
+      NEW met1 ( 1484190 194990 ) M1M2_PR
+      NEW met2 ( 1484190 197540 ) M2M3_PR_M
+      NEW met3 ( 1485340 197540 ) M3M4_PR_M ;
+    - la_data_in[28] ( PIN la_data_in[28] ) ( mem din0[28] ) + USE SIGNAL
+      + ROUTED met2 ( 1125850 2380 0 ) ( * 17510 )
+      NEW met1 ( 1125850 17510 ) ( 1131370 * )
+      NEW met2 ( 1497530 197370 ) ( * 197540 )
+      NEW met3 ( 1497530 197540 ) ( 1499140 * )
+      NEW met4 ( 1499140 197540 ) ( * 200260 )
+      NEW met4 ( 1499140 200260 ) ( 1499310 * )
+      NEW met4 ( 1499310 200260 ) ( * 202300 0 )
+      NEW met2 ( 1131370 17510 ) ( * 197370 )
+      NEW met1 ( 1131370 197370 ) ( 1497530 * )
+      NEW met1 ( 1125850 17510 ) M1M2_PR
+      NEW met1 ( 1131370 17510 ) M1M2_PR
+      NEW met1 ( 1131370 197370 ) M1M2_PR
+      NEW met1 ( 1497530 197370 ) M1M2_PR
+      NEW met2 ( 1497530 197540 ) M2M3_PR_M
+      NEW met3 ( 1499140 197540 ) M3M4_PR_M ;
+    - la_data_in[29] ( PIN la_data_in[29] ) ( mem din0[29] ) + USE SIGNAL
+      + ROUTED met2 ( 1511330 195330 ) ( * 195500 )
+      NEW met3 ( 1511330 195500 ) ( 1512020 * )
+      NEW met4 ( 1512020 195500 ) ( * 200260 )
+      NEW met4 ( 1512020 200260 ) ( 1512230 * )
+      NEW met4 ( 1512230 200260 ) ( * 202300 0 )
+      NEW met2 ( 1143790 2380 0 ) ( * 34500 )
+      NEW met2 ( 1143790 34500 ) ( 1145170 * )
+      NEW met2 ( 1145170 34500 ) ( * 195330 )
+      NEW met1 ( 1145170 195330 ) ( 1511330 * )
+      NEW met1 ( 1145170 195330 ) M1M2_PR
+      NEW met1 ( 1511330 195330 ) M1M2_PR
+      NEW met2 ( 1511330 195500 ) M2M3_PR_M
+      NEW met3 ( 1512020 195500 ) M3M4_PR_M ;
+    - la_data_in[2] ( PIN la_data_in[2] ) ( mem din0[2] ) + USE SIGNAL
+      + ROUTED met2 ( 664930 2380 0 ) ( * 17850 )
+      NEW met1 ( 664930 17850 ) ( 669070 * )
+      NEW met2 ( 1152530 197710 ) ( * 198900 )
+      NEW met3 ( 1152530 198900 ) ( 1157820 * )
+      NEW met4 ( 1157820 198900 ) ( 1157950 * )
+      NEW met4 ( 1157950 198900 ) ( * 202300 0 )
+      NEW met2 ( 669070 17850 ) ( * 197710 )
+      NEW met1 ( 669070 197710 ) ( 1152530 * )
+      NEW met1 ( 664930 17850 ) M1M2_PR
+      NEW met1 ( 669070 17850 ) M1M2_PR
+      NEW met1 ( 669070 197710 ) M1M2_PR
+      NEW met1 ( 1152530 197710 ) M1M2_PR
+      NEW met2 ( 1152530 198900 ) M2M3_PR_M
+      NEW met3 ( 1157820 198900 ) M3M4_PR_M ;
+    - la_data_in[30] ( PIN la_data_in[30] ) ( mem din0[30] ) + USE SIGNAL
+      + ROUTED met2 ( 1161270 2380 0 ) ( * 17510 )
+      NEW met1 ( 1161270 17510 ) ( 1165870 * )
+      NEW met2 ( 1165870 17510 ) ( * 195670 )
+      NEW met2 ( 1518230 195670 ) ( * 196180 )
+      NEW met3 ( 1518230 196180 ) ( 1523980 * )
+      NEW met4 ( 1523980 196180 ) ( * 198900 )
+      NEW met4 ( 1523980 198900 ) ( 1524470 * )
+      NEW met4 ( 1524470 198900 ) ( * 202300 0 )
+      NEW met1 ( 1165870 195670 ) ( 1518230 * )
+      NEW met1 ( 1161270 17510 ) M1M2_PR
+      NEW met1 ( 1165870 17510 ) M1M2_PR
+      NEW met1 ( 1165870 195670 ) M1M2_PR
+      NEW met1 ( 1518230 195670 ) M1M2_PR
+      NEW met2 ( 1518230 196180 ) M2M3_PR_M
+      NEW met3 ( 1523980 196180 ) M3M4_PR_M ;
+    - la_data_in[31] ( PIN la_data_in[31] ) ( mem din0[31] ) + USE SIGNAL
+      + ROUTED met2 ( 1536170 197710 ) ( * 198900 )
+      NEW met3 ( 1536170 198900 ) ( 1537780 * )
+      NEW met4 ( 1537780 198900 ) ( 1538070 * )
+      NEW met4 ( 1538070 198900 ) ( * 202300 0 )
+      NEW met2 ( 1179210 2380 0 ) ( * 34500 )
+      NEW met2 ( 1179210 34500 ) ( 1179670 * )
+      NEW met2 ( 1179670 34500 ) ( * 197710 )
+      NEW met1 ( 1179670 197710 ) ( 1536170 * )
+      NEW met1 ( 1179670 197710 ) M1M2_PR
+      NEW met1 ( 1536170 197710 ) M1M2_PR
+      NEW met2 ( 1536170 198900 ) M2M3_PR_M
+      NEW met3 ( 1537780 198900 ) M3M4_PR_M ;
+    - la_data_in[32] ( PIN la_data_in[32] ) ( mprj reset ) + USE SIGNAL
+      + ROUTED met3 ( 2499180 2040340 0 ) ( 2513670 * )
+      NEW met2 ( 2513670 17170 ) ( * 2040340 )
+      NEW met2 ( 1196690 2380 0 ) ( * 17170 )
+      NEW met1 ( 1196690 17170 ) ( 2513670 * )
+      NEW met1 ( 2513670 17170 ) M1M2_PR
+      NEW met2 ( 2513670 2040340 ) M2M3_PR_M
+      NEW met1 ( 1196690 17170 ) M1M2_PR ;
     - la_data_in[33] ( PIN la_data_in[33] ) + USE SIGNAL ;
     - la_data_in[34] ( PIN la_data_in[34] ) + USE SIGNAL ;
     - la_data_in[35] ( PIN la_data_in[35] ) + USE SIGNAL ;
-    - la_data_in[36] ( PIN la_data_in[36] ) + USE SIGNAL ;
+    - la_data_in[36] ( PIN la_data_in[36] ) ( mprj init_en ) + USE SIGNAL
+      + ROUTED met2 ( 1267530 2380 0 ) ( * 14790 )
+      NEW met2 ( 996590 14790 ) ( * 2578900 )
+      NEW met1 ( 996590 14790 ) ( 1267530 * )
+      NEW met3 ( 996590 2578900 ) ( 1000500 * 0 )
+      NEW met1 ( 996590 14790 ) M1M2_PR
+      NEW met1 ( 1267530 14790 ) M1M2_PR
+      NEW met2 ( 996590 2578900 ) M2M3_PR_M ;
     - la_data_in[37] ( PIN la_data_in[37] ) + USE SIGNAL ;
     - la_data_in[38] ( PIN la_data_in[38] ) + USE SIGNAL ;
     - la_data_in[39] ( PIN la_data_in[39] ) + USE SIGNAL ;
-    - la_data_in[3] ( PIN la_data_in[3] ) + USE SIGNAL ;
-    - la_data_in[40] ( PIN la_data_in[40] ) + USE SIGNAL ;
+    - la_data_in[3] ( PIN la_data_in[3] ) ( mem din0[3] ) + USE SIGNAL
+      + ROUTED met2 ( 1166330 198220 ) ( * 198390 )
+      NEW met3 ( 1166330 198220 ) ( 1169780 * )
+      NEW met4 ( 1169780 198220 ) ( * 198900 )
+      NEW met4 ( 1169780 198900 ) ( 1170190 * )
+      NEW met4 ( 1170190 198900 ) ( * 202300 0 )
+      NEW met2 ( 682410 2380 0 ) ( * 34500 )
+      NEW met2 ( 682410 34500 ) ( 682870 * )
+      NEW met2 ( 682870 34500 ) ( * 198390 )
+      NEW met1 ( 682870 198390 ) ( 1166330 * )
+      NEW met1 ( 682870 198390 ) M1M2_PR
+      NEW met1 ( 1166330 198390 ) M1M2_PR
+      NEW met2 ( 1166330 198220 ) M2M3_PR_M
+      NEW met3 ( 1169780 198220 ) M3M4_PR_M ;
+    - la_data_in[40] ( PIN la_data_in[40] ) ( mem csb0 ) + USE SIGNAL
+      + ROUTED met2 ( 1338830 2380 0 ) ( * 15130 )
+      NEW met2 ( 993830 14450 ) ( * 217940 )
+      NEW li1 ( 1024650 14450 ) ( * 15130 )
+      NEW met1 ( 993830 14450 ) ( 1024650 * )
+      NEW met3 ( 993830 217940 ) ( 1000500 * )
+      NEW met3 ( 1000500 217940 ) ( * 220590 0 )
+      NEW met1 ( 1024650 15130 ) ( 1338830 * )
+      NEW met1 ( 993830 14450 ) M1M2_PR
+      NEW met2 ( 993830 217940 ) M2M3_PR_M
+      NEW met1 ( 1338830 15130 ) M1M2_PR
+      NEW li1 ( 1024650 14450 ) L1M1_PR_MR
+      NEW li1 ( 1024650 15130 ) L1M1_PR_MR ;
     - la_data_in[41] ( PIN la_data_in[41] ) + USE SIGNAL ;
     - la_data_in[42] ( PIN la_data_in[42] ) + USE SIGNAL ;
     - la_data_in[43] ( PIN la_data_in[43] ) + USE SIGNAL ;
-    - la_data_in[44] ( PIN la_data_in[44] ) + USE SIGNAL ;
-    - la_data_in[45] ( PIN la_data_in[45] ) + USE SIGNAL ;
-    - la_data_in[46] ( PIN la_data_in[46] ) + USE SIGNAL ;
-    - la_data_in[47] ( PIN la_data_in[47] ) + USE SIGNAL ;
-    - la_data_in[48] ( PIN la_data_in[48] ) + USE SIGNAL ;
-    - la_data_in[49] ( PIN la_data_in[49] ) + USE SIGNAL ;
-    - la_data_in[4] ( PIN la_data_in[4] ) + USE SIGNAL ;
-    - la_data_in[50] ( PIN la_data_in[50] ) + USE SIGNAL ;
-    - la_data_in[51] ( PIN la_data_in[51] ) + USE SIGNAL ;
+    - la_data_in[44] ( PIN la_data_in[44] ) ( mprj init_addr[0] ) + USE SIGNAL
+      + ROUTED met2 ( 2499870 2996420 0 ) ( 2500330 * )
+      NEW met2 ( 2500330 17510 ) ( * 2996420 )
+      NEW met2 ( 1409670 2380 0 ) ( * 17510 )
+      NEW met1 ( 1409670 17510 ) ( 2500330 * )
+      NEW met1 ( 2500330 17510 ) M1M2_PR
+      NEW met1 ( 1409670 17510 ) M1M2_PR ;
+    - la_data_in[45] ( PIN la_data_in[45] ) ( mprj init_addr[1] ) + USE SIGNAL
+      + ROUTED met2 ( 1573890 19890 ) ( * 1488350 )
+      NEW met2 ( 1427150 2380 0 ) ( * 19890 )
+      NEW met1 ( 1427150 19890 ) ( 1573890 * )
+      NEW met2 ( 1486950 1488350 ) ( * 1500420 0 )
+      NEW met1 ( 1486950 1488350 ) ( 1573890 * )
+      NEW met1 ( 1573890 19890 ) M1M2_PR
+      NEW met1 ( 1573890 1488350 ) M1M2_PR
+      NEW met1 ( 1427150 19890 ) M1M2_PR
+      NEW met1 ( 1486950 1488350 ) M1M2_PR ;
+    - la_data_in[46] ( PIN la_data_in[46] ) ( mprj init_addr[2] ) + USE SIGNAL
+      + ROUTED met2 ( 1445090 2380 0 ) ( * 17850 )
+      NEW met3 ( 2499180 2520420 0 ) ( 2511830 * )
+      NEW met2 ( 2511830 17850 ) ( * 2520420 )
+      NEW met1 ( 1445090 17850 ) ( 2511830 * )
+      NEW met1 ( 1445090 17850 ) M1M2_PR
+      NEW met1 ( 2511830 17850 ) M1M2_PR
+      NEW met2 ( 2511830 2520420 ) M2M3_PR_M ;
+    - la_data_in[47] ( PIN la_data_in[47] ) ( mprj init_addr[3] ) + USE SIGNAL
+      + ROUTED met2 ( 1463030 2380 0 ) ( * 19550 )
+      NEW met2 ( 1749150 19550 ) ( * 1488010 )
+      NEW met2 ( 2216510 1488010 ) ( * 1500420 0 )
+      NEW met1 ( 1463030 19550 ) ( 1749150 * )
+      NEW met1 ( 1749150 1488010 ) ( 2216510 * )
+      NEW met1 ( 1463030 19550 ) M1M2_PR
+      NEW met1 ( 1749150 19550 ) M1M2_PR
+      NEW met1 ( 1749150 1488010 ) M1M2_PR
+      NEW met1 ( 2216510 1488010 ) M1M2_PR ;
+    - la_data_in[48] ( PIN la_data_in[48] ) ( mprj init_addr[4] ) + USE SIGNAL
+      + ROUTED met2 ( 1480510 2380 0 ) ( * 16660 )
+      NEW met3 ( 1480510 16660 ) ( 1582860 * )
+      NEW met2 ( 1689350 2999820 0 ) ( * 3008660 )
+      NEW met3 ( 1582860 3008660 ) ( 1689350 * )
+      NEW met4 ( 1582860 16660 ) ( * 3008660 )
+      NEW met2 ( 1480510 16660 ) M2M3_PR_M
+      NEW met3 ( 1582860 16660 ) M3M4_PR_M
+      NEW met3 ( 1582860 3008660 ) M3M4_PR_M
+      NEW met2 ( 1689350 3008660 ) M2M3_PR_M ;
+    - la_data_in[49] ( PIN la_data_in[49] ) ( mprj init_addr[5] ) + USE SIGNAL
+      + ROUTED met3 ( 2499180 1920660 0 ) ( 2514590 * )
+      NEW met2 ( 2514590 18190 ) ( * 1920660 )
+      NEW met2 ( 1498450 2380 0 ) ( * 18190 )
+      NEW met1 ( 1498450 18190 ) ( 2514590 * )
+      NEW met1 ( 2514590 18190 ) M1M2_PR
+      NEW met2 ( 2514590 1920660 ) M2M3_PR_M
+      NEW met1 ( 1498450 18190 ) M1M2_PR ;
+    - la_data_in[4] ( PIN la_data_in[4] ) ( mem din0[4] ) + USE SIGNAL
+      + ROUTED met2 ( 700350 2380 0 ) ( * 17850 )
+      NEW met1 ( 700350 17850 ) ( 703570 * )
+      NEW met2 ( 1180130 194650 ) ( * 194820 )
+      NEW met3 ( 1180130 194820 ) ( 1182660 * )
+      NEW met4 ( 1182660 194820 ) ( * 198900 )
+      NEW met4 ( 1182660 198900 ) ( 1183110 * )
+      NEW met4 ( 1183110 198900 ) ( * 202300 0 )
+      NEW met2 ( 703570 17850 ) ( * 194650 )
+      NEW met1 ( 703570 194650 ) ( 1180130 * )
+      NEW met1 ( 700350 17850 ) M1M2_PR
+      NEW met1 ( 703570 17850 ) M1M2_PR
+      NEW met1 ( 703570 194650 ) M1M2_PR
+      NEW met1 ( 1180130 194650 ) M1M2_PR
+      NEW met2 ( 1180130 194820 ) M2M3_PR_M
+      NEW met3 ( 1182660 194820 ) M3M4_PR_M ;
+    - la_data_in[50] ( PIN la_data_in[50] ) ( mprj init_addr[6] ) + USE SIGNAL
+      + ROUTED met2 ( 1162190 1487330 ) ( * 1500420 0 )
+      NEW met2 ( 1574350 20230 ) ( * 1487330 )
+      NEW met2 ( 1515930 2380 0 ) ( * 20230 )
+      NEW met1 ( 1515930 20230 ) ( 1574350 * )
+      NEW met1 ( 1162190 1487330 ) ( 1574350 * )
+      NEW met1 ( 1574350 20230 ) M1M2_PR
+      NEW met1 ( 1162190 1487330 ) M1M2_PR
+      NEW met1 ( 1574350 1487330 ) M1M2_PR
+      NEW met1 ( 1515930 20230 ) M1M2_PR ;
+    - la_data_in[51] ( PIN la_data_in[51] ) ( mprj init_addr[7] ) + USE SIGNAL
+      + ROUTED met2 ( 1533870 2380 0 ) ( * 16490 )
+      NEW met1 ( 1533870 16490 ) ( 1573430 * )
+      NEW met2 ( 1573430 16490 ) ( * 1488010 )
+      NEW met2 ( 1405070 1488010 ) ( * 1500420 0 )
+      NEW met1 ( 1405070 1488010 ) ( 1573430 * )
+      NEW met1 ( 1533870 16490 ) M1M2_PR
+      NEW met1 ( 1573430 16490 ) M1M2_PR
+      NEW met1 ( 1573430 1488010 ) M1M2_PR
+      NEW met1 ( 1405070 1488010 ) M1M2_PR ;
     - la_data_in[52] ( PIN la_data_in[52] ) + USE SIGNAL ;
     - la_data_in[53] ( PIN la_data_in[53] ) + USE SIGNAL ;
     - la_data_in[54] ( PIN la_data_in[54] ) + USE SIGNAL ;
@@ -8300,7 +8723,22 @@
     - la_data_in[57] ( PIN la_data_in[57] ) + USE SIGNAL ;
     - la_data_in[58] ( PIN la_data_in[58] ) + USE SIGNAL ;
     - la_data_in[59] ( PIN la_data_in[59] ) + USE SIGNAL ;
-    - la_data_in[5] ( PIN la_data_in[5] ) + USE SIGNAL ;
+    - la_data_in[5] ( PIN la_data_in[5] ) ( mem din0[5] ) + USE SIGNAL
+      + ROUTED met2 ( 717830 2380 0 ) ( * 17850 )
+      NEW met1 ( 717830 17850 ) ( 724270 * )
+      NEW met2 ( 1195310 198730 ) ( * 198900 )
+      NEW met3 ( 1195310 198900 ) ( 1196460 * )
+      NEW met4 ( 1196460 198900 ) ( * 200260 )
+      NEW met4 ( 1196460 200260 ) ( 1196710 * )
+      NEW met4 ( 1196710 200260 ) ( * 202300 0 )
+      NEW met1 ( 724270 198730 ) ( 1195310 * )
+      NEW met2 ( 724270 17850 ) ( * 198730 )
+      NEW met1 ( 717830 17850 ) M1M2_PR
+      NEW met1 ( 724270 17850 ) M1M2_PR
+      NEW met1 ( 724270 198730 ) M1M2_PR
+      NEW met1 ( 1195310 198730 ) M1M2_PR
+      NEW met2 ( 1195310 198900 ) M2M3_PR_M
+      NEW met3 ( 1196460 198900 ) M3M4_PR_M ;
     - la_data_in[60] ( PIN la_data_in[60] ) + USE SIGNAL ;
     - la_data_in[61] ( PIN la_data_in[61] ) + USE SIGNAL ;
     - la_data_in[62] ( PIN la_data_in[62] ) + USE SIGNAL ;
@@ -8311,7 +8749,22 @@
     - la_data_in[67] ( PIN la_data_in[67] ) + USE SIGNAL ;
     - la_data_in[68] ( PIN la_data_in[68] ) + USE SIGNAL ;
     - la_data_in[69] ( PIN la_data_in[69] ) + USE SIGNAL ;
-    - la_data_in[6] ( PIN la_data_in[6] ) + USE SIGNAL ;
+    - la_data_in[6] ( PIN la_data_in[6] ) ( mem din0[6] ) + USE SIGNAL
+      + ROUTED met2 ( 735770 2380 0 ) ( * 17850 )
+      NEW met1 ( 735770 17850 ) ( 738070 * )
+      NEW met2 ( 1207730 198900 ) ( * 200090 )
+      NEW met3 ( 1207730 198900 ) ( 1209340 * )
+      NEW met4 ( 1209340 198900 ) ( * 200260 )
+      NEW met4 ( 1209340 200260 ) ( 1209630 * )
+      NEW met4 ( 1209630 200260 ) ( * 202300 0 )
+      NEW met1 ( 738070 200090 ) ( 1207730 * )
+      NEW met2 ( 738070 17850 ) ( * 200090 )
+      NEW met1 ( 735770 17850 ) M1M2_PR
+      NEW met1 ( 738070 17850 ) M1M2_PR
+      NEW met1 ( 738070 200090 ) M1M2_PR
+      NEW met1 ( 1207730 200090 ) M1M2_PR
+      NEW met2 ( 1207730 198900 ) M2M3_PR_M
+      NEW met3 ( 1209340 198900 ) M3M4_PR_M ;
     - la_data_in[70] ( PIN la_data_in[70] ) + USE SIGNAL ;
     - la_data_in[71] ( PIN la_data_in[71] ) + USE SIGNAL ;
     - la_data_in[72] ( PIN la_data_in[72] ) + USE SIGNAL ;
@@ -8322,7 +8775,22 @@
     - la_data_in[77] ( PIN la_data_in[77] ) + USE SIGNAL ;
     - la_data_in[78] ( PIN la_data_in[78] ) + USE SIGNAL ;
     - la_data_in[79] ( PIN la_data_in[79] ) + USE SIGNAL ;
-    - la_data_in[7] ( PIN la_data_in[7] ) + USE SIGNAL ;
+    - la_data_in[7] ( PIN la_data_in[7] ) ( mem din0[7] ) + USE SIGNAL
+      + ROUTED met2 ( 753250 2380 0 ) ( * 15470 )
+      NEW met1 ( 753250 15470 ) ( 1141950 * )
+      NEW met2 ( 1221530 193290 ) ( * 193460 )
+      NEW met3 ( 1221530 193460 ) ( 1222220 * )
+      NEW met4 ( 1222220 193460 ) ( * 200260 )
+      NEW met4 ( 1222220 200260 ) ( 1222550 * )
+      NEW met4 ( 1222550 200260 ) ( * 202300 0 )
+      NEW met1 ( 1141950 193290 ) ( 1221530 * )
+      NEW met2 ( 1141950 15470 ) ( * 193290 )
+      NEW met1 ( 753250 15470 ) M1M2_PR
+      NEW met1 ( 1141950 15470 ) M1M2_PR
+      NEW met1 ( 1141950 193290 ) M1M2_PR
+      NEW met1 ( 1221530 193290 ) M1M2_PR
+      NEW met2 ( 1221530 193460 ) M2M3_PR_M
+      NEW met3 ( 1222220 193460 ) M3M4_PR_M ;
     - la_data_in[80] ( PIN la_data_in[80] ) + USE SIGNAL ;
     - la_data_in[81] ( PIN la_data_in[81] ) + USE SIGNAL ;
     - la_data_in[82] ( PIN la_data_in[82] ) + USE SIGNAL ;
@@ -8333,7 +8801,20 @@
     - la_data_in[87] ( PIN la_data_in[87] ) + USE SIGNAL ;
     - la_data_in[88] ( PIN la_data_in[88] ) + USE SIGNAL ;
     - la_data_in[89] ( PIN la_data_in[89] ) + USE SIGNAL ;
-    - la_data_in[8] ( PIN la_data_in[8] ) + USE SIGNAL ;
+    - la_data_in[8] ( PIN la_data_in[8] ) ( mem din0[8] ) + USE SIGNAL
+      + ROUTED met2 ( 771190 2380 0 ) ( * 34500 )
+      NEW met2 ( 771190 34500 ) ( 772570 * )
+      NEW met2 ( 772570 34500 ) ( * 199410 )
+      NEW met2 ( 1235330 198900 ) ( * 199410 )
+      NEW met3 ( 1235330 198900 ) ( 1236020 * )
+      NEW met4 ( 1236020 198900 ) ( * 200260 )
+      NEW met4 ( 1236020 200260 ) ( 1236150 * )
+      NEW met4 ( 1236150 200260 ) ( * 202300 0 )
+      NEW met1 ( 772570 199410 ) ( 1235330 * )
+      NEW met1 ( 772570 199410 ) M1M2_PR
+      NEW met1 ( 1235330 199410 ) M1M2_PR
+      NEW met2 ( 1235330 198900 ) M2M3_PR_M
+      NEW met3 ( 1236020 198900 ) M3M4_PR_M ;
     - la_data_in[90] ( PIN la_data_in[90] ) + USE SIGNAL ;
     - la_data_in[91] ( PIN la_data_in[91] ) + USE SIGNAL ;
     - la_data_in[92] ( PIN la_data_in[92] ) + USE SIGNAL ;
@@ -8344,7 +8825,21 @@
     - la_data_in[97] ( PIN la_data_in[97] ) + USE SIGNAL ;
     - la_data_in[98] ( PIN la_data_in[98] ) + USE SIGNAL ;
     - la_data_in[99] ( PIN la_data_in[99] ) + USE SIGNAL ;
-    - la_data_in[9] ( PIN la_data_in[9] ) + USE SIGNAL ;
+    - la_data_in[9] ( PIN la_data_in[9] ) ( mem din0[9] ) + USE SIGNAL
+      + ROUTED met2 ( 789130 2380 0 ) ( * 15810 )
+      NEW met2 ( 1249130 193630 ) ( * 198900 )
+      NEW met3 ( 1249130 198900 ) ( 1249820 * )
+      NEW met4 ( 1249750 198900 ) ( 1249820 * )
+      NEW met4 ( 1249750 198900 ) ( * 202300 0 )
+      NEW met2 ( 1183350 15810 ) ( * 193630 )
+      NEW met1 ( 789130 15810 ) ( 1183350 * )
+      NEW met1 ( 1183350 193630 ) ( 1249130 * )
+      NEW met1 ( 789130 15810 ) M1M2_PR
+      NEW met1 ( 1183350 15810 ) M1M2_PR
+      NEW met1 ( 1183350 193630 ) M1M2_PR
+      NEW met1 ( 1249130 193630 ) M1M2_PR
+      NEW met2 ( 1249130 198900 ) M2M3_PR_M
+      NEW met3 ( 1249820 198900 ) M3M4_PR_M ;
     - la_data_out[0] ( PIN la_data_out[0] ) + USE SIGNAL ;
     - la_data_out[100] ( PIN la_data_out[100] ) + USE SIGNAL ;
     - la_data_out[101] ( PIN la_data_out[101] ) + USE SIGNAL ;
@@ -8433,17 +8928,101 @@
     - la_data_out[61] ( PIN la_data_out[61] ) + USE SIGNAL ;
     - la_data_out[62] ( PIN la_data_out[62] ) + USE SIGNAL ;
     - la_data_out[63] ( PIN la_data_out[63] ) + USE SIGNAL ;
-    - la_data_out[64] ( PIN la_data_out[64] ) + USE SIGNAL ;
-    - la_data_out[65] ( PIN la_data_out[65] ) + USE SIGNAL ;
-    - la_data_out[66] ( PIN la_data_out[66] ) + USE SIGNAL ;
-    - la_data_out[67] ( PIN la_data_out[67] ) + USE SIGNAL ;
-    - la_data_out[68] ( PIN la_data_out[68] ) + USE SIGNAL ;
-    - la_data_out[69] ( PIN la_data_out[69] ) + USE SIGNAL ;
+    - la_data_out[64] ( PIN la_data_out[64] ) ( mprj OUT[0] ) + USE SIGNAL
+      + ROUTED met2 ( 1770310 2380 0 ) ( * 19550 )
+      NEW met3 ( 2499180 2279700 0 ) ( 2512750 * )
+      NEW met2 ( 2512750 19550 ) ( * 2279700 )
+      NEW met1 ( 1770310 19550 ) ( 2512750 * )
+      NEW met1 ( 1770310 19550 ) M1M2_PR
+      NEW met1 ( 2512750 19550 ) M1M2_PR
+      NEW met2 ( 2512750 2279700 ) M2M3_PR_M ;
+    - la_data_out[65] ( PIN la_data_out[65] ) ( mprj OUT[1] ) + USE SIGNAL
+      + ROUTED met4 ( 2114620 16660 ) ( * 3009340 )
+      NEW met2 ( 1787790 2380 0 ) ( * 16660 )
+      NEW met3 ( 1787790 16660 ) ( 2114620 * )
+      NEW met2 ( 2176030 2999820 0 ) ( * 3009340 )
+      NEW met3 ( 2114620 3009340 ) ( 2176030 * )
+      NEW met3 ( 2114620 16660 ) M3M4_PR_M
+      NEW met3 ( 2114620 3009340 ) M3M4_PR_M
+      NEW met2 ( 1787790 16660 ) M2M3_PR_M
+      NEW met2 ( 2176030 3009340 ) M2M3_PR_M ;
+    - la_data_out[66] ( PIN la_data_out[66] ) ( mprj OUT[2] ) + USE SIGNAL
+      + ROUTED met2 ( 1805730 2380 0 ) ( * 3060 )
+      NEW met2 ( 1805730 3060 ) ( 1806650 * )
+      NEW met2 ( 1806650 2380 ) ( * 3060 )
+      NEW met2 ( 1806650 2380 ) ( 1807570 * )
+      NEW met2 ( 1807570 2380 ) ( * 1487330 )
+      NEW met2 ( 2460310 1487330 ) ( * 1500420 0 )
+      NEW met1 ( 1807570 1487330 ) ( 2460310 * )
+      NEW met1 ( 1807570 1487330 ) M1M2_PR
+      NEW met1 ( 2460310 1487330 ) M1M2_PR ;
+    - la_data_out[67] ( PIN la_data_out[67] ) ( mprj OUT[3] ) + USE SIGNAL
+      + ROUTED met2 ( 1823210 2380 0 ) ( * 19890 )
+      NEW met3 ( 2499180 2879460 0 ) ( 2504930 * )
+      NEW met2 ( 2504930 19890 ) ( * 2879460 )
+      NEW met1 ( 1823210 19890 ) ( 2504930 * )
+      NEW met1 ( 1823210 19890 ) M1M2_PR
+      NEW met1 ( 2504930 19890 ) M1M2_PR
+      NEW met2 ( 2504930 2879460 ) M2M3_PR_M ;
+    - la_data_out[68] ( PIN la_data_out[68] ) ( mprj OUT[4] ) + USE SIGNAL
+      + ROUTED met2 ( 1841150 2380 0 ) ( * 20230 )
+      NEW met3 ( 2499180 1679940 0 ) ( 2505850 * )
+      NEW met2 ( 2505850 20230 ) ( * 1679940 )
+      NEW met1 ( 1841150 20230 ) ( 2505850 * )
+      NEW met1 ( 1841150 20230 ) M1M2_PR
+      NEW met1 ( 2505850 20230 ) M1M2_PR
+      NEW met2 ( 2505850 1679940 ) M2M3_PR_M ;
+    - la_data_out[69] ( PIN la_data_out[69] ) ( mprj OUT[5] ) + USE SIGNAL
+      + ROUTED met2 ( 1858630 2380 0 ) ( * 19210 )
+      NEW met2 ( 991990 18870 ) ( * 1979140 )
+      NEW met1 ( 991990 18870 ) ( 1000500 * )
+      NEW met1 ( 1000500 18870 ) ( * 19210 )
+      NEW met1 ( 1000500 19210 ) ( 1858630 * )
+      NEW met3 ( 991990 1979140 ) ( 1000500 * 0 )
+      NEW met1 ( 991990 18870 ) M1M2_PR
+      NEW met1 ( 1858630 19210 ) M1M2_PR
+      NEW met2 ( 991990 1979140 ) M2M3_PR_M ;
     - la_data_out[6] ( PIN la_data_out[6] ) + USE SIGNAL ;
-    - la_data_out[70] ( PIN la_data_out[70] ) + USE SIGNAL ;
-    - la_data_out[71] ( PIN la_data_out[71] ) + USE SIGNAL ;
-    - la_data_out[72] ( PIN la_data_out[72] ) + USE SIGNAL ;
-    - la_data_out[73] ( PIN la_data_out[73] ) + USE SIGNAL ;
+    - la_data_out[70] ( PIN la_data_out[70] ) ( mprj OUT[6] ) + USE SIGNAL
+      + ROUTED met2 ( 1859550 16830 ) ( * 1487670 )
+      NEW met2 ( 1876570 2380 0 ) ( * 16830 )
+      NEW met1 ( 1859550 16830 ) ( 1876570 * )
+      NEW met2 ( 1324110 1487670 ) ( * 1500420 0 )
+      NEW met1 ( 1324110 1487670 ) ( 1859550 * )
+      NEW met1 ( 1859550 16830 ) M1M2_PR
+      NEW met1 ( 1859550 1487670 ) M1M2_PR
+      NEW met1 ( 1876570 16830 ) M1M2_PR
+      NEW met1 ( 1324110 1487670 ) M1M2_PR ;
+    - la_data_out[71] ( PIN la_data_out[71] ) ( mprj OUT[7] ) + USE SIGNAL
+      + ROUTED met2 ( 991530 18530 ) ( * 1859460 )
+      NEW met1 ( 1001190 18530 ) ( * 18870 )
+      NEW met1 ( 991530 18530 ) ( 1001190 * )
+      NEW met3 ( 991530 1859460 ) ( 1000500 * 0 )
+      NEW met2 ( 1894510 2380 0 ) ( * 18870 )
+      NEW met1 ( 1001190 18870 ) ( 1894510 * )
+      NEW met1 ( 991530 18530 ) M1M2_PR
+      NEW met2 ( 991530 1859460 ) M2M3_PR_M
+      NEW met1 ( 1894510 18870 ) M1M2_PR ;
+    - la_data_out[72] ( PIN la_data_out[72] ) ( mprj OUT[8] ) + USE SIGNAL
+      + ROUTED met2 ( 990610 15130 ) ( * 1739780 )
+      NEW li1 ( 1024190 15130 ) ( * 18530 )
+      NEW met1 ( 990610 15130 ) ( 1024190 * )
+      NEW met3 ( 990610 1739780 ) ( 1000500 * 0 )
+      NEW met2 ( 1911990 2380 0 ) ( * 18530 )
+      NEW met1 ( 1024190 18530 ) ( 1911990 * )
+      NEW met1 ( 990610 15130 ) M1M2_PR
+      NEW met2 ( 990610 1739780 ) M2M3_PR_M
+      NEW li1 ( 1024190 15130 ) L1M1_PR_MR
+      NEW li1 ( 1024190 18530 ) L1M1_PR_MR
+      NEW met1 ( 1911990 18530 ) M1M2_PR ;
+    - la_data_out[73] ( PIN la_data_out[73] ) ( mprj OUT[9] ) + USE SIGNAL
+      + ROUTED met2 ( 1929930 2380 0 ) ( * 18530 )
+      NEW met3 ( 2499180 1800980 0 ) ( 2515050 * )
+      NEW met2 ( 2515050 18530 ) ( * 1800980 )
+      NEW met1 ( 1929930 18530 ) ( 2515050 * )
+      NEW met1 ( 1929930 18530 ) M1M2_PR
+      NEW met1 ( 2515050 18530 ) M1M2_PR
+      NEW met2 ( 2515050 1800980 ) M2M3_PR_M ;
     - la_data_out[74] ( PIN la_data_out[74] ) + USE SIGNAL ;
     - la_data_out[75] ( PIN la_data_out[75] ) + USE SIGNAL ;
     - la_data_out[76] ( PIN la_data_out[76] ) + USE SIGNAL ;
@@ -8602,97 +9181,97 @@
     - la_oenb[99] ( PIN la_oenb[99] ) + USE SIGNAL ;
     - la_oenb[9] ( PIN la_oenb[9] ) + USE SIGNAL ;
     - mem_addr\[0\] ( mprj mem_addr[0] ) ( mem addr0[0] ) + USE SIGNAL
-      + ROUTED met2 ( 991070 199070 ) ( * 1620100 )
-      NEW met2 ( 1104230 198220 ) ( * 199070 )
-      NEW met3 ( 1104230 198220 ) ( 1104460 * )
-      NEW met4 ( 1104460 198220 ) ( * 198900 )
+      + ROUTED met2 ( 990150 193630 ) ( * 1620100 )
+      NEW met2 ( 1104230 193630 ) ( * 194140 )
+      NEW met3 ( 1104230 194140 ) ( 1104460 * )
+      NEW met4 ( 1104460 194140 ) ( * 198900 )
       NEW met4 ( 1104460 198900 ) ( 1104910 * )
       NEW met4 ( 1104910 198900 ) ( * 202300 0 )
-      NEW met1 ( 991070 199070 ) ( 1104230 * )
-      NEW met3 ( 991070 1620100 ) ( 1000500 * 0 )
-      NEW met1 ( 991070 199070 ) M1M2_PR
-      NEW met2 ( 991070 1620100 ) M2M3_PR_M
-      NEW met1 ( 1104230 199070 ) M1M2_PR
-      NEW met2 ( 1104230 198220 ) M2M3_PR_M
-      NEW met3 ( 1104460 198220 ) M3M4_PR_M
-      NEW met3 ( 1104230 198220 ) RECT ( -390 -150 0 150 )  ;
+      NEW met1 ( 990150 193630 ) ( 1104230 * )
+      NEW met3 ( 990150 1620100 ) ( 1000500 * 0 )
+      NEW met1 ( 990150 193630 ) M1M2_PR
+      NEW met2 ( 990150 1620100 ) M2M3_PR_M
+      NEW met1 ( 1104230 193630 ) M1M2_PR
+      NEW met2 ( 1104230 194140 ) M2M3_PR_M
+      NEW met3 ( 1104460 194140 ) M3M4_PR_M
+      NEW met3 ( 1104230 194140 ) RECT ( -390 -150 0 150 )  ;
     - mem_addr\[1\] ( mprj mem_addr[1] ) ( mem addr0[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1648870 1487670 ) ( * 1500420 0 )
-      NEW met2 ( 1124470 198220 ) ( * 199070 )
+      + ROUTED met2 ( 1648870 1487330 ) ( * 1500420 0 )
+      NEW met2 ( 1124470 198220 ) ( * 199750 )
       NEW met3 ( 1118260 198220 ) ( 1124470 * )
       NEW met4 ( 1118260 198220 ) ( * 198900 )
       NEW met4 ( 1117830 198900 ) ( 1118260 * )
       NEW met4 ( 1117830 198900 ) ( * 202300 0 )
-      NEW met2 ( 1604250 199070 ) ( * 1487670 )
-      NEW met1 ( 1604250 1487670 ) ( 1648870 * )
-      NEW met1 ( 1124470 199070 ) ( 1604250 * )
-      NEW met1 ( 1648870 1487670 ) M1M2_PR
-      NEW met1 ( 1124470 199070 ) M1M2_PR
+      NEW met2 ( 1604250 199750 ) ( * 1487330 )
+      NEW met1 ( 1604250 1487330 ) ( 1648870 * )
+      NEW met1 ( 1124470 199750 ) ( 1604250 * )
+      NEW met1 ( 1648870 1487330 ) M1M2_PR
+      NEW met1 ( 1124470 199750 ) M1M2_PR
       NEW met2 ( 1124470 198220 ) M2M3_PR_M
       NEW met3 ( 1118260 198220 ) M3M4_PR_M
-      NEW met1 ( 1604250 199070 ) M1M2_PR
-      NEW met1 ( 1604250 1487670 ) M1M2_PR ;
+      NEW met1 ( 1604250 199750 ) M1M2_PR
+      NEW met1 ( 1604250 1487330 ) M1M2_PR ;
     - mem_addr\[2\] ( mprj mem_addr[2] ) ( mem addr0[2] ) + USE SIGNAL
-      + ROUTED met2 ( 2418910 2999820 0 ) ( * 3009510 )
-      NEW met2 ( 994290 334220 ) ( * 3009510 )
-      NEW met1 ( 994290 3009510 ) ( 2418910 * )
+      + ROUTED met2 ( 2418910 2999820 0 ) ( * 3010190 )
+      NEW met2 ( 994290 334220 ) ( * 3010190 )
+      NEW met1 ( 994290 3010190 ) ( 2418910 * )
       NEW met3 ( 994290 334220 ) ( 1000500 * )
       NEW met3 ( 1000500 332790 0 ) ( * 334220 )
-      NEW met1 ( 994290 3009510 ) M1M2_PR
-      NEW met1 ( 2418910 3009510 ) M1M2_PR
+      NEW met1 ( 994290 3010190 ) M1M2_PR
+      NEW met1 ( 2418910 3010190 ) M1M2_PR
       NEW met2 ( 994290 334220 ) M2M3_PR_M ;
     - mem_addr\[3\] ( mprj mem_addr[3] ) ( mem addr0[3] ) + USE SIGNAL
-      + ROUTED met2 ( 2337950 2999820 0 ) ( * 3009850 )
-      NEW met2 ( 995210 337620 ) ( * 3009850 )
-      NEW met1 ( 995210 3009850 ) ( 2337950 * )
+      + ROUTED met2 ( 2337950 2999820 0 ) ( * 3008830 )
+      NEW met2 ( 995210 337620 ) ( * 3008830 )
+      NEW met1 ( 995210 3008830 ) ( 2337950 * )
       NEW met3 ( 995210 337620 ) ( 1000500 * )
       NEW met3 ( 1000500 335510 0 ) ( * 337620 )
-      NEW met1 ( 995210 3009850 ) M1M2_PR
-      NEW met1 ( 2337950 3009850 ) M1M2_PR
+      NEW met1 ( 995210 3008830 ) M1M2_PR
+      NEW met1 ( 2337950 3008830 ) M1M2_PR
       NEW met2 ( 995210 337620 ) M2M3_PR_M ;
     - mem_addr\[4\] ( mprj mem_addr[4] ) ( mem addr0[4] ) + USE SIGNAL
-      + ROUTED met2 ( 1445550 2999820 0 ) ( * 3010530 )
-      NEW met2 ( 994750 342380 ) ( * 3010530 )
-      NEW met1 ( 994750 3010530 ) ( 1445550 * )
+      + ROUTED met2 ( 1445550 2999820 0 ) ( * 3009510 )
+      NEW met2 ( 994750 342380 ) ( * 3009510 )
+      NEW met1 ( 994750 3009510 ) ( 1445550 * )
       NEW met3 ( 994750 342380 ) ( 1000500 * )
       NEW met3 ( 1000500 341630 0 ) ( * 342380 )
-      NEW met1 ( 994750 3010530 ) M1M2_PR
-      NEW met1 ( 1445550 3010530 ) M1M2_PR
+      NEW met1 ( 994750 3009510 ) M1M2_PR
+      NEW met1 ( 1445550 3009510 ) M1M2_PR
       NEW met2 ( 994750 342380 ) M2M3_PR_M ;
     - mem_addr\[5\] ( mprj mem_addr[5] ) ( mem addr0[5] ) + USE SIGNAL
-      + ROUTED met2 ( 995670 344420 ) ( * 3010190 )
-      NEW met2 ( 1607470 2999820 0 ) ( * 3010190 )
-      NEW met1 ( 995670 3010190 ) ( 1607470 * )
+      + ROUTED met2 ( 995670 344420 ) ( * 3009170 )
+      NEW met2 ( 1607470 2999820 0 ) ( * 3009170 )
+      NEW met1 ( 995670 3009170 ) ( 1607470 * )
       NEW met3 ( 995670 344420 ) ( 1000500 * )
       NEW met3 ( 1000500 343670 0 ) ( * 344420 )
-      NEW met1 ( 995670 3010190 ) M1M2_PR
+      NEW met1 ( 995670 3009170 ) M1M2_PR
       NEW met2 ( 995670 344420 ) M2M3_PR_M
-      NEW met1 ( 1607470 3010190 ) M1M2_PR ;
+      NEW met1 ( 1607470 3009170 ) M1M2_PR ;
     - mem_addr\[6\] ( mprj mem_addr[6] ) ( mem addr0[6] ) + USE SIGNAL
       + ROUTED met3 ( 1000500 349180 ) ( 1000730 * )
       NEW met3 ( 1000500 349180 ) ( * 350470 0 )
-      NEW met2 ( 1000730 349180 ) ( * 1489030 )
-      NEW met2 ( 1810790 1489030 ) ( * 1500420 0 )
-      NEW met1 ( 1000730 1489030 ) ( 1810790 * )
+      NEW met2 ( 1000730 349180 ) ( * 1486990 )
+      NEW met2 ( 1810790 1486990 ) ( * 1500420 0 )
+      NEW met1 ( 1000730 1486990 ) ( 1810790 * )
       NEW met2 ( 1000730 349180 ) M2M3_PR_M
-      NEW met1 ( 1000730 1489030 ) M1M2_PR
-      NEW met1 ( 1810790 1489030 ) M1M2_PR ;
+      NEW met1 ( 1000730 1486990 ) M1M2_PR
+      NEW met1 ( 1810790 1486990 ) M1M2_PR ;
     - mem_addr\[7\] ( mprj mem_addr[7] ) ( mem addr0[7] ) + USE SIGNAL
-      + ROUTED met2 ( 991530 354620 ) ( * 2098820 )
-      NEW met3 ( 991530 354620 ) ( 1000500 * )
+      + ROUTED met2 ( 991070 354620 ) ( * 2098820 )
+      NEW met3 ( 991070 354620 ) ( 1000500 * )
       NEW met3 ( 1000500 351830 0 ) ( * 354620 )
-      NEW met3 ( 991530 2098820 ) ( 1000500 * 0 )
-      NEW met2 ( 991530 354620 ) M2M3_PR_M
-      NEW met2 ( 991530 2098820 ) M2M3_PR_M ;
+      NEW met3 ( 991070 2098820 ) ( 1000500 * 0 )
+      NEW met2 ( 991070 354620 ) M2M3_PR_M
+      NEW met2 ( 991070 2098820 ) M2M3_PR_M ;
     - mem_wr ( mprj mem_wr ) ( mem web0 ) + USE SIGNAL
-      + ROUTED met2 ( 997050 225420 ) ( * 3010870 )
-      NEW met3 ( 997050 225420 ) ( 1000500 * )
+      + ROUTED met2 ( 993830 225420 ) ( * 3009850 )
+      NEW met3 ( 993830 225420 ) ( 1000500 * )
       NEW met3 ( 1000500 222630 0 ) ( * 225420 )
-      NEW met2 ( 1120790 2999820 0 ) ( * 3010870 )
-      NEW met1 ( 997050 3010870 ) ( 1120790 * )
-      NEW met2 ( 997050 225420 ) M2M3_PR_M
-      NEW met1 ( 997050 3010870 ) M1M2_PR
-      NEW met1 ( 1120790 3010870 ) M1M2_PR ;
+      NEW met2 ( 1120790 2999820 0 ) ( * 3009850 )
+      NEW met1 ( 993830 3009850 ) ( 1120790 * )
+      NEW met2 ( 993830 225420 ) M2M3_PR_M
+      NEW met1 ( 993830 3009850 ) M1M2_PR
+      NEW met1 ( 1120790 3009850 ) M1M2_PR ;
     - user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
     - user_irq[0] ( PIN user_irq[0] ) + USE SIGNAL ;
     - user_irq[1] ( PIN user_irq[1] ) + USE SIGNAL ;
@@ -8717,25 +9296,9 @@
       NEW met2 ( 1035230 192780 ) M2M3_PR_M
       NEW met3 ( 1004180 3008660 ) M3M4_PR_M
       NEW met3 ( 1035230 192780 ) RECT ( -800 -150 0 150 )  ;
-    - wb_rst_i ( PIN wb_rst_i ) ( mprj reset ) + USE SIGNAL
-      + ROUTED met2 ( 8510 2380 0 ) ( * 17510 )
-      NEW met3 ( 2499180 2040340 0 ) ( 2514130 * )
-      NEW met2 ( 2514130 17510 ) ( * 2040340 )
-      NEW met1 ( 8510 17510 ) ( 2514130 * )
-      NEW met1 ( 8510 17510 ) M1M2_PR
-      NEW met1 ( 2514130 17510 ) M1M2_PR
-      NEW met2 ( 2514130 2040340 ) M2M3_PR_M ;
+    - wb_rst_i ( PIN wb_rst_i ) + USE SIGNAL ;
     - wbs_ack_o ( PIN wbs_ack_o ) + USE SIGNAL ;
-    - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj init_addr[0] ) + USE SIGNAL
-      + ROUTED met2 ( 2499870 2999820 0 ) ( * 3011210 )
-      NEW met2 ( 38410 2380 0 ) ( * 17850 )
-      NEW met1 ( 38410 17850 ) ( 41170 * )
-      NEW met1 ( 41170 3011210 ) ( 2499870 * )
-      NEW met2 ( 41170 17850 ) ( * 3011210 )
-      NEW met1 ( 2499870 3011210 ) M1M2_PR
-      NEW met1 ( 38410 17850 ) M1M2_PR
-      NEW met1 ( 41170 17850 ) M1M2_PR
-      NEW met1 ( 41170 3011210 ) M1M2_PR ;
+    - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) + USE SIGNAL ;
     - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) + USE SIGNAL ;
     - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) + USE SIGNAL ;
     - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) + USE SIGNAL ;
@@ -8746,16 +9309,7 @@
     - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) + USE SIGNAL ;
     - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) + USE SIGNAL ;
     - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) + USE SIGNAL ;
-    - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj init_addr[1] ) + USE SIGNAL
-      + ROUTED met2 ( 61870 2380 0 ) ( * 17340 )
-      NEW met2 ( 60950 17340 ) ( 61870 * )
-      NEW met2 ( 60950 82800 ) ( 61410 * )
-      NEW met2 ( 60950 17340 ) ( * 82800 )
-      NEW met2 ( 61410 82800 ) ( * 1487670 )
-      NEW met2 ( 1486950 1487670 ) ( * 1500420 0 )
-      NEW met1 ( 61410 1487670 ) ( 1486950 * )
-      NEW met1 ( 61410 1487670 ) M1M2_PR
-      NEW met1 ( 1486950 1487670 ) M1M2_PR ;
+    - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) + USE SIGNAL ;
     - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) + USE SIGNAL ;
     - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) + USE SIGNAL ;
     - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) + USE SIGNAL ;
@@ -8766,505 +9320,50 @@
     - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) + USE SIGNAL ;
     - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) + USE SIGNAL ;
     - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) + USE SIGNAL ;
-    - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj init_addr[2] ) + USE SIGNAL
-      + ROUTED met2 ( 85330 2380 0 ) ( * 17340 )
-      NEW met3 ( 2499180 2520420 0 ) ( 2512290 * )
-      NEW met2 ( 2512290 17340 ) ( * 2520420 )
-      NEW met3 ( 85330 17340 ) ( 2512290 * )
-      NEW met2 ( 85330 17340 ) M2M3_PR_M
-      NEW met2 ( 2512290 17340 ) M2M3_PR_M
-      NEW met2 ( 2512290 2520420 ) M2M3_PR_M ;
+    - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) + USE SIGNAL ;
     - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) + USE SIGNAL ;
     - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) + USE SIGNAL ;
-    - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj init_addr[3] ) + USE SIGNAL
-      + ROUTED met2 ( 109250 2380 0 ) ( * 34500 )
-      NEW met2 ( 109250 34500 ) ( 110170 * )
-      NEW met2 ( 110170 34500 ) ( * 1487330 )
-      NEW met2 ( 2216510 1487330 ) ( * 1500420 0 )
-      NEW met1 ( 110170 1487330 ) ( 2216510 * )
-      NEW met1 ( 110170 1487330 ) M1M2_PR
-      NEW met1 ( 2216510 1487330 ) M1M2_PR ;
-    - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj init_addr[4] ) + USE SIGNAL
-      + ROUTED met2 ( 132710 2380 0 ) ( * 17850 )
-      NEW met1 ( 132710 17850 ) ( 137770 * )
-      NEW met2 ( 1689350 2999820 0 ) ( * 3009170 )
-      NEW met1 ( 137770 3009170 ) ( 1689350 * )
-      NEW met2 ( 137770 17850 ) ( * 3009170 )
-      NEW met1 ( 132710 17850 ) M1M2_PR
-      NEW met1 ( 137770 17850 ) M1M2_PR
-      NEW met1 ( 137770 3009170 ) M1M2_PR
-      NEW met1 ( 1689350 3009170 ) M1M2_PR ;
-    - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj init_addr[5] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 1920660 0 ) ( 2514590 * )
-      NEW met2 ( 2514590 17850 ) ( * 1920660 )
-      NEW met2 ( 150650 2380 0 ) ( * 18190 )
-      NEW met1 ( 150650 18190 ) ( 172730 * )
-      NEW met1 ( 172730 17850 ) ( * 18190 )
-      NEW met1 ( 172730 17850 ) ( 2514590 * )
-      NEW met1 ( 2514590 17850 ) M1M2_PR
-      NEW met2 ( 2514590 1920660 ) M2M3_PR_M
-      NEW met1 ( 150650 18190 ) M1M2_PR ;
-    - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj init_addr[6] ) + USE SIGNAL
-      + ROUTED met2 ( 1162190 1488690 ) ( * 1500420 0 )
-      NEW met2 ( 168130 2380 0 ) ( * 17850 )
-      NEW met1 ( 168130 17850 ) ( 172270 * )
-      NEW met2 ( 172270 17850 ) ( * 1488690 )
-      NEW met1 ( 172270 1488690 ) ( 1162190 * )
-      NEW met1 ( 1162190 1488690 ) M1M2_PR
-      NEW met1 ( 168130 17850 ) M1M2_PR
-      NEW met1 ( 172270 17850 ) M1M2_PR
-      NEW met1 ( 172270 1488690 ) M1M2_PR ;
-    - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj init_addr[7] ) + USE SIGNAL
-      + ROUTED met2 ( 186070 2380 0 ) ( * 17340 )
-      NEW met2 ( 185150 17340 ) ( 186070 * )
-      NEW met2 ( 185150 82800 ) ( 185610 * )
-      NEW met2 ( 185150 17340 ) ( * 82800 )
-      NEW met2 ( 185610 82800 ) ( * 1488010 )
-      NEW met2 ( 1405070 1488010 ) ( * 1500420 0 )
-      NEW met1 ( 185610 1488010 ) ( 1405070 * )
-      NEW met1 ( 185610 1488010 ) M1M2_PR
-      NEW met1 ( 1405070 1488010 ) M1M2_PR ;
+    - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) + USE SIGNAL ;
+    - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) + USE SIGNAL ;
+    - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) + USE SIGNAL ;
+    - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) + USE SIGNAL ;
+    - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) + USE SIGNAL ;
     - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) + USE SIGNAL ;
     - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) + USE SIGNAL ;
     - wbs_cyc_i ( PIN wbs_cyc_i ) + USE SIGNAL ;
-    - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mem din0[0] ) + USE SIGNAL
-      + ROUTED met2 ( 43930 2380 0 ) ( * 18870 )
-      NEW met1 ( 43930 18870 ) ( 1124930 * )
-      NEW met3 ( 1124930 198900 ) ( 1131140 * )
-      NEW met4 ( 1131140 198900 ) ( 1131430 * )
-      NEW met4 ( 1131430 198900 ) ( * 202300 0 )
-      NEW met2 ( 1124930 18870 ) ( * 198900 )
-      NEW met1 ( 43930 18870 ) M1M2_PR
-      NEW met1 ( 1124930 18870 ) M1M2_PR
-      NEW met2 ( 1124930 198900 ) M2M3_PR_M
-      NEW met3 ( 1131140 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mem din0[10] ) + USE SIGNAL
-      + ROUTED met3 ( 1262700 198900 ) ( 1262930 * )
-      NEW met4 ( 1262670 198900 ) ( 1262700 * )
-      NEW met4 ( 1262670 198900 ) ( * 202300 0 )
-      NEW met2 ( 1262930 20570 ) ( * 198900 )
-      NEW met2 ( 244950 2380 0 ) ( * 20570 )
-      NEW met1 ( 244950 20570 ) ( 1262930 * )
-      NEW met1 ( 1262930 20570 ) M1M2_PR
-      NEW met2 ( 1262930 198900 ) M2M3_PR_M
-      NEW met3 ( 1262700 198900 ) M3M4_PR_M
-      NEW met1 ( 244950 20570 ) M1M2_PR
-      NEW met3 ( 1262930 198900 ) RECT ( 0 -150 390 150 )  ;
-    - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mem din0[11] ) + USE SIGNAL
-      + ROUTED met3 ( 1269830 198900 ) ( 1275580 * )
-      NEW met4 ( 1275580 198900 ) ( 1275590 * )
-      NEW met4 ( 1275590 198900 ) ( * 202300 0 )
-      NEW met2 ( 1269830 16830 ) ( * 198900 )
-      NEW met2 ( 262890 2380 0 ) ( * 16830 )
-      NEW met1 ( 262890 16830 ) ( 1269830 * )
-      NEW met1 ( 1269830 16830 ) M1M2_PR
-      NEW met2 ( 1269830 198900 ) M2M3_PR_M
-      NEW met3 ( 1275580 198900 ) M3M4_PR_M
-      NEW met1 ( 262890 16830 ) M1M2_PR ;
-    - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mem din0[12] ) + USE SIGNAL
-      + ROUTED met2 ( 280370 2380 0 ) ( * 16490 )
-      NEW met3 ( 1283630 198900 ) ( 1288460 * )
-      NEW met4 ( 1288460 198900 ) ( 1288510 * )
-      NEW met4 ( 1288510 198900 ) ( * 202300 0 )
-      NEW met2 ( 1283630 16490 ) ( * 198900 )
-      NEW met1 ( 280370 16490 ) ( 1283630 * )
-      NEW met1 ( 280370 16490 ) M1M2_PR
-      NEW met1 ( 1283630 16490 ) M1M2_PR
-      NEW met2 ( 1283630 198900 ) M2M3_PR_M
-      NEW met3 ( 1288460 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mem din0[13] ) + USE SIGNAL
-      + ROUTED met2 ( 298310 2380 0 ) ( * 16150 )
-      NEW met1 ( 298310 16150 ) ( 1297430 * )
-      NEW met3 ( 1297430 198900 ) ( 1301340 * )
-      NEW met4 ( 1301340 198900 ) ( 1301430 * )
-      NEW met4 ( 1301430 198900 ) ( * 202300 0 )
-      NEW met2 ( 1297430 16150 ) ( * 198900 )
-      NEW met1 ( 298310 16150 ) M1M2_PR
-      NEW met1 ( 1297430 16150 ) M1M2_PR
-      NEW met2 ( 1297430 198900 ) M2M3_PR_M
-      NEW met3 ( 1301340 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mem din0[14] ) + USE SIGNAL
-      + ROUTED met2 ( 316250 2380 0 ) ( * 15810 )
-      NEW met1 ( 316250 15810 ) ( 1311230 * )
-      NEW met3 ( 1311230 198900 ) ( 1315140 * )
-      NEW met4 ( 1315030 198900 ) ( 1315140 * )
-      NEW met4 ( 1315030 198900 ) ( * 202300 0 )
-      NEW met2 ( 1311230 15810 ) ( * 198900 )
-      NEW met1 ( 316250 15810 ) M1M2_PR
-      NEW met1 ( 1311230 15810 ) M1M2_PR
-      NEW met2 ( 1311230 198900 ) M2M3_PR_M
-      NEW met3 ( 1315140 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mem din0[15] ) + USE SIGNAL
-      + ROUTED met2 ( 333730 2380 0 ) ( * 15470 )
-      NEW met1 ( 333730 15470 ) ( 1325030 * )
-      NEW met3 ( 1325030 193460 ) ( 1328020 * )
-      NEW met4 ( 1328020 193460 ) ( * 198900 )
-      NEW met4 ( 1328020 198900 ) ( 1328630 * )
-      NEW met4 ( 1328630 198900 ) ( * 202300 0 )
-      NEW met2 ( 1325030 15470 ) ( * 193460 )
-      NEW met1 ( 333730 15470 ) M1M2_PR
-      NEW met1 ( 1325030 15470 ) M1M2_PR
-      NEW met2 ( 1325030 193460 ) M2M3_PR_M
-      NEW met3 ( 1328020 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mem din0[16] ) + USE SIGNAL
-      + ROUTED met2 ( 351670 2380 0 ) ( * 15130 )
-      NEW met1 ( 351670 15130 ) ( 1338830 * )
-      NEW met3 ( 1338830 193460 ) ( 1340900 * )
-      NEW met4 ( 1340900 193460 ) ( * 198900 )
-      NEW met4 ( 1340870 198900 ) ( 1340900 * )
-      NEW met4 ( 1340870 198900 ) ( * 202300 0 )
-      NEW met2 ( 1338830 15130 ) ( * 193460 )
-      NEW met1 ( 1338830 15130 ) M1M2_PR
-      NEW met1 ( 351670 15130 ) M1M2_PR
-      NEW met2 ( 1338830 193460 ) M2M3_PR_M
-      NEW met3 ( 1340900 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mem din0[17] ) + USE SIGNAL
-      + ROUTED met2 ( 369150 2380 0 ) ( * 14790 )
-      NEW met1 ( 369150 14790 ) ( 1352630 * )
-      NEW met3 ( 1352630 198900 ) ( 1354700 * )
-      NEW met4 ( 1354470 198900 ) ( 1354700 * )
-      NEW met4 ( 1354470 198900 ) ( * 202300 0 )
-      NEW met2 ( 1352630 14790 ) ( * 198900 )
-      NEW met1 ( 1352630 14790 ) M1M2_PR
-      NEW met1 ( 369150 14790 ) M1M2_PR
-      NEW met2 ( 1352630 198900 ) M2M3_PR_M
-      NEW met3 ( 1354700 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mem din0[18] ) + USE SIGNAL
-      + ROUTED met2 ( 387090 2380 0 ) ( * 14450 )
-      NEW met1 ( 387090 14450 ) ( 393070 * )
-      NEW met2 ( 393070 14450 ) ( * 195330 )
-      NEW met2 ( 1366890 195330 ) ( * 198900 )
-      NEW met3 ( 1366890 198900 ) ( 1367580 * )
-      NEW met4 ( 1367390 198900 ) ( 1367580 * )
-      NEW met4 ( 1367390 198900 ) ( * 202300 0 )
-      NEW met1 ( 393070 195330 ) ( 1366890 * )
-      NEW met1 ( 387090 14450 ) M1M2_PR
-      NEW met1 ( 393070 14450 ) M1M2_PR
-      NEW met1 ( 393070 195330 ) M1M2_PR
-      NEW met1 ( 1366890 195330 ) M1M2_PR
-      NEW met2 ( 1366890 198900 ) M2M3_PR_M
-      NEW met3 ( 1367580 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mem din0[19] ) + USE SIGNAL
-      + ROUTED met2 ( 404570 2380 0 ) ( * 14450 )
-      NEW met1 ( 404570 14450 ) ( 406870 * )
-      NEW met2 ( 406870 14450 ) ( * 194990 )
-      NEW met2 ( 1380230 194990 ) ( * 195500 )
-      NEW met3 ( 1380230 195500 ) ( 1380460 * )
-      NEW met4 ( 1380460 195500 ) ( * 198900 )
-      NEW met4 ( 1380460 198900 ) ( 1380990 * )
-      NEW met4 ( 1380990 198900 ) ( * 202300 0 )
-      NEW met1 ( 406870 194990 ) ( 1380230 * )
-      NEW met1 ( 404570 14450 ) M1M2_PR
-      NEW met1 ( 406870 14450 ) M1M2_PR
-      NEW met1 ( 406870 194990 ) M1M2_PR
-      NEW met1 ( 1380230 194990 ) M1M2_PR
-      NEW met2 ( 1380230 195500 ) M2M3_PR_M
-      NEW met3 ( 1380460 195500 ) M3M4_PR_M
-      NEW met3 ( 1380230 195500 ) RECT ( -390 -150 0 150 )  ;
-    - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mem din0[1] ) + USE SIGNAL
-      + ROUTED met2 ( 1138730 193290 ) ( * 193460 )
-      NEW met3 ( 1138730 193460 ) ( 1143100 * )
-      NEW met4 ( 1143100 193460 ) ( * 198900 )
-      NEW met4 ( 1143100 198900 ) ( 1143670 * )
-      NEW met4 ( 1143670 198900 ) ( * 202300 0 )
-      NEW met1 ( 68770 193290 ) ( 1138730 * )
-      NEW met2 ( 67850 2380 0 ) ( * 34500 )
-      NEW met2 ( 67850 34500 ) ( 68770 * )
-      NEW met2 ( 68770 34500 ) ( * 193290 )
-      NEW met1 ( 68770 193290 ) M1M2_PR
-      NEW met1 ( 1138730 193290 ) M1M2_PR
-      NEW met2 ( 1138730 193460 ) M2M3_PR_M
-      NEW met3 ( 1143100 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mem din0[20] ) + USE SIGNAL
-      + ROUTED met2 ( 422510 2380 0 ) ( * 14450 )
-      NEW met1 ( 422510 14450 ) ( 427570 * )
-      NEW met2 ( 427570 14450 ) ( * 196010 )
-      NEW met2 ( 1392650 196010 ) ( * 198900 )
-      NEW met3 ( 1392650 198900 ) ( 1393340 * )
-      NEW met4 ( 1393230 198900 ) ( 1393340 * )
-      NEW met4 ( 1393230 198900 ) ( * 202300 0 )
-      NEW met1 ( 427570 196010 ) ( 1392650 * )
-      NEW met1 ( 422510 14450 ) M1M2_PR
-      NEW met1 ( 427570 14450 ) M1M2_PR
-      NEW met1 ( 427570 196010 ) M1M2_PR
-      NEW met1 ( 1392650 196010 ) M1M2_PR
-      NEW met2 ( 1392650 198900 ) M2M3_PR_M
-      NEW met3 ( 1393340 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mem din0[21] ) + USE SIGNAL
-      + ROUTED met2 ( 439990 2380 0 ) ( * 34500 )
-      NEW met2 ( 439990 34500 ) ( 441370 * )
-      NEW met2 ( 441370 34500 ) ( * 195670 )
-      NEW met2 ( 1400930 195670 ) ( * 196180 )
-      NEW met3 ( 1400930 196180 ) ( 1406220 * )
-      NEW met4 ( 1406220 196180 ) ( * 198900 )
-      NEW met4 ( 1406220 198900 ) ( 1406830 * )
-      NEW met4 ( 1406830 198900 ) ( * 202300 0 )
-      NEW met1 ( 441370 195670 ) ( 1400930 * )
-      NEW met1 ( 441370 195670 ) M1M2_PR
-      NEW met1 ( 1400930 195670 ) M1M2_PR
-      NEW met2 ( 1400930 196180 ) M2M3_PR_M
-      NEW met3 ( 1406220 196180 ) M3M4_PR_M ;
-    - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mem din0[22] ) + USE SIGNAL
-      + ROUTED met2 ( 457930 2380 0 ) ( * 14450 )
-      NEW met1 ( 457930 14450 ) ( 462070 * )
-      NEW met2 ( 1414730 196350 ) ( * 196860 )
-      NEW met3 ( 1414730 196860 ) ( 1420020 * )
-      NEW met4 ( 1420020 196860 ) ( * 198900 )
-      NEW met4 ( 1420020 198900 ) ( 1420430 * )
-      NEW met4 ( 1420430 198900 ) ( * 202300 0 )
-      NEW met2 ( 462070 14450 ) ( * 196350 )
-      NEW met1 ( 462070 196350 ) ( 1414730 * )
-      NEW met1 ( 457930 14450 ) M1M2_PR
-      NEW met1 ( 462070 14450 ) M1M2_PR
-      NEW met1 ( 462070 196350 ) M1M2_PR
-      NEW met1 ( 1414730 196350 ) M1M2_PR
-      NEW met2 ( 1414730 196860 ) M2M3_PR_M
-      NEW met3 ( 1420020 196860 ) M3M4_PR_M ;
-    - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mem din0[23] ) + USE SIGNAL
-      + ROUTED met2 ( 475870 2380 0 ) ( * 196690 )
-      NEW met2 ( 1428530 196690 ) ( * 196860 )
-      NEW met3 ( 1428530 196860 ) ( 1432900 * )
-      NEW met4 ( 1432900 196860 ) ( * 198900 )
-      NEW met4 ( 1432900 198900 ) ( 1433350 * )
-      NEW met4 ( 1433350 198900 ) ( * 202300 0 )
-      NEW met1 ( 475870 196690 ) ( 1428530 * )
-      NEW met1 ( 475870 196690 ) M1M2_PR
-      NEW met1 ( 1428530 196690 ) M1M2_PR
-      NEW met2 ( 1428530 196860 ) M2M3_PR_M
-      NEW met3 ( 1432900 196860 ) M3M4_PR_M ;
-    - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mem din0[24] ) + USE SIGNAL
-      + ROUTED met2 ( 493350 2380 0 ) ( * 14450 )
-      NEW met1 ( 493350 14450 ) ( 496570 * )
-      NEW met2 ( 1442330 197030 ) ( * 198900 )
-      NEW met3 ( 1442330 198900 ) ( 1445780 * )
-      NEW met4 ( 1445590 198900 ) ( 1445780 * )
-      NEW met4 ( 1445590 198900 ) ( * 202300 0 )
-      NEW met2 ( 496570 14450 ) ( * 197030 )
-      NEW met1 ( 496570 197030 ) ( 1442330 * )
-      NEW met1 ( 493350 14450 ) M1M2_PR
-      NEW met1 ( 496570 14450 ) M1M2_PR
-      NEW met1 ( 496570 197030 ) M1M2_PR
-      NEW met1 ( 1442330 197030 ) M1M2_PR
-      NEW met2 ( 1442330 198900 ) M2M3_PR_M
-      NEW met3 ( 1445780 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mem din0[25] ) + USE SIGNAL
-      + ROUTED met2 ( 511290 2380 0 ) ( * 14450 )
-      NEW met1 ( 511290 14450 ) ( 517270 * )
-      NEW met2 ( 1457970 197370 ) ( * 198220 )
-      NEW met3 ( 1457970 198220 ) ( 1458660 * )
-      NEW met4 ( 1458660 198220 ) ( * 198900 )
-      NEW met4 ( 1458660 198900 ) ( 1459190 * )
-      NEW met4 ( 1459190 198900 ) ( * 202300 0 )
-      NEW met2 ( 517270 14450 ) ( * 197370 )
-      NEW met1 ( 517270 197370 ) ( 1457970 * )
-      NEW met1 ( 511290 14450 ) M1M2_PR
-      NEW met1 ( 517270 14450 ) M1M2_PR
-      NEW met1 ( 517270 197370 ) M1M2_PR
-      NEW met1 ( 1457970 197370 ) M1M2_PR
-      NEW met2 ( 1457970 198220 ) M2M3_PR_M
-      NEW met3 ( 1458660 198220 ) M3M4_PR_M ;
-    - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mem din0[26] ) + USE SIGNAL
-      + ROUTED met2 ( 1469930 197710 ) ( * 198220 )
-      NEW met3 ( 1469930 198220 ) ( 1471540 * )
-      NEW met4 ( 1471540 198220 ) ( * 198900 )
-      NEW met4 ( 1471540 198900 ) ( 1472110 * )
-      NEW met4 ( 1472110 198900 ) ( * 202300 0 )
-      NEW met2 ( 528770 2380 0 ) ( * 14450 )
-      NEW met1 ( 528770 14450 ) ( 531070 * )
-      NEW met2 ( 531070 14450 ) ( * 197710 )
-      NEW met1 ( 531070 197710 ) ( 1469930 * )
-      NEW met1 ( 1469930 197710 ) M1M2_PR
-      NEW met2 ( 1469930 198220 ) M2M3_PR_M
-      NEW met3 ( 1471540 198220 ) M3M4_PR_M
-      NEW met1 ( 528770 14450 ) M1M2_PR
-      NEW met1 ( 531070 14450 ) M1M2_PR
-      NEW met1 ( 531070 197710 ) M1M2_PR ;
-    - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mem din0[27] ) + USE SIGNAL
-      + ROUTED met2 ( 546710 2380 0 ) ( * 14450 )
-      NEW met1 ( 546710 14450 ) ( 551770 * )
-      NEW met2 ( 1484190 198050 ) ( * 198220 )
-      NEW met3 ( 1484190 198220 ) ( 1484420 * )
-      NEW met4 ( 1484420 198220 ) ( * 198900 )
-      NEW met4 ( 1484420 198900 ) ( 1485030 * )
-      NEW met4 ( 1485030 198900 ) ( * 202300 0 )
-      NEW met2 ( 551770 14450 ) ( * 198050 )
-      NEW met1 ( 551770 198050 ) ( 1484190 * )
-      NEW met1 ( 546710 14450 ) M1M2_PR
-      NEW met1 ( 551770 14450 ) M1M2_PR
-      NEW met1 ( 551770 198050 ) M1M2_PR
-      NEW met1 ( 1484190 198050 ) M1M2_PR
-      NEW met2 ( 1484190 198220 ) M2M3_PR_M
-      NEW met3 ( 1484420 198220 ) M3M4_PR_M
-      NEW met3 ( 1484190 198220 ) RECT ( -390 -150 0 150 )  ;
-    - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mem din0[28] ) + USE SIGNAL
-      + ROUTED met2 ( 1497530 198220 ) ( * 198390 )
-      NEW met3 ( 1497530 198220 ) ( 1499140 * )
-      NEW met4 ( 1499140 198220 ) ( * 198900 )
-      NEW met4 ( 1499140 198900 ) ( 1499310 * )
-      NEW met4 ( 1499310 198900 ) ( * 202300 0 )
-      NEW met2 ( 564190 2380 0 ) ( * 34500 )
-      NEW met2 ( 564190 34500 ) ( 565570 * )
-      NEW met2 ( 565570 34500 ) ( * 198390 )
-      NEW met1 ( 565570 198390 ) ( 1497530 * )
-      NEW met1 ( 565570 198390 ) M1M2_PR
-      NEW met1 ( 1497530 198390 ) M1M2_PR
-      NEW met2 ( 1497530 198220 ) M2M3_PR_M
-      NEW met3 ( 1499140 198220 ) M3M4_PR_M ;
-    - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mem din0[29] ) + USE SIGNAL
-      + ROUTED met2 ( 582130 2380 0 ) ( * 14450 )
-      NEW met1 ( 582130 14450 ) ( 1511330 * )
-      NEW met3 ( 1511330 193460 ) ( 1512020 * )
-      NEW met4 ( 1512020 193460 ) ( * 198900 )
-      NEW met4 ( 1512020 198900 ) ( 1512230 * )
-      NEW met4 ( 1512230 198900 ) ( * 202300 0 )
-      NEW met2 ( 1511330 14450 ) ( * 193460 )
-      NEW met1 ( 582130 14450 ) M1M2_PR
-      NEW met1 ( 1511330 14450 ) M1M2_PR
-      NEW met2 ( 1511330 193460 ) M2M3_PR_M
-      NEW met3 ( 1512020 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mem din0[2] ) + USE SIGNAL
-      + ROUTED met2 ( 91310 2380 0 ) ( * 14450 )
-      NEW met1 ( 91310 14450 ) ( 96370 * )
-      NEW met2 ( 1152530 193630 ) ( * 198900 )
-      NEW met3 ( 1152530 198900 ) ( 1157820 * )
-      NEW met4 ( 1157820 198900 ) ( 1157950 * )
-      NEW met4 ( 1157950 198900 ) ( * 202300 0 )
-      NEW met2 ( 96370 14450 ) ( * 193630 )
-      NEW met1 ( 96370 193630 ) ( 1152530 * )
-      NEW met1 ( 91310 14450 ) M1M2_PR
-      NEW met1 ( 96370 14450 ) M1M2_PR
-      NEW met1 ( 96370 193630 ) M1M2_PR
-      NEW met1 ( 1152530 193630 ) M1M2_PR
-      NEW met2 ( 1152530 198900 ) M2M3_PR_M
-      NEW met3 ( 1157820 198900 ) M3M4_PR_M ;
-    - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mem din0[30] ) + USE SIGNAL
-      + ROUTED met2 ( 599610 2380 0 ) ( * 14110 )
-      NEW met1 ( 599610 14110 ) ( 1518230 * )
-      NEW met3 ( 1518230 193460 ) ( 1523980 * )
-      NEW met4 ( 1523980 193460 ) ( * 198900 )
-      NEW met4 ( 1523980 198900 ) ( 1524470 * )
-      NEW met4 ( 1524470 198900 ) ( * 202300 0 )
-      NEW met2 ( 1518230 14110 ) ( * 193460 )
-      NEW met1 ( 599610 14110 ) M1M2_PR
-      NEW met1 ( 1518230 14110 ) M1M2_PR
-      NEW met2 ( 1518230 193460 ) M2M3_PR_M
-      NEW met3 ( 1523980 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mem din0[31] ) + USE SIGNAL
-      + ROUTED met2 ( 1535250 198730 ) ( * 198900 )
-      NEW met3 ( 1535250 198900 ) ( 1537780 * )
-      NEW met4 ( 1537780 198900 ) ( 1538070 * )
-      NEW met4 ( 1538070 198900 ) ( * 202300 0 )
-      NEW met2 ( 617550 2380 0 ) ( * 34500 )
-      NEW met2 ( 617550 34500 ) ( 620770 * )
-      NEW met2 ( 620770 34500 ) ( * 198730 )
-      NEW met1 ( 620770 198730 ) ( 1535250 * )
-      NEW met1 ( 1535250 198730 ) M1M2_PR
-      NEW met2 ( 1535250 198900 ) M2M3_PR_M
-      NEW met3 ( 1537780 198900 ) M3M4_PR_M
-      NEW met1 ( 620770 198730 ) M1M2_PR ;
-    - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mem din0[3] ) + USE SIGNAL
-      + ROUTED met2 ( 115230 2380 0 ) ( * 19210 )
-      NEW met3 ( 1166330 193460 ) ( 1169780 * )
-      NEW met4 ( 1169780 193460 ) ( * 198900 )
-      NEW met4 ( 1169780 198900 ) ( 1170190 * )
-      NEW met4 ( 1170190 198900 ) ( * 202300 0 )
-      NEW met2 ( 1166330 19210 ) ( * 193460 )
-      NEW met1 ( 115230 19210 ) ( 1166330 * )
-      NEW met1 ( 115230 19210 ) M1M2_PR
-      NEW met1 ( 1166330 19210 ) M1M2_PR
-      NEW met2 ( 1166330 193460 ) M2M3_PR_M
-      NEW met3 ( 1169780 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mem din0[4] ) + USE SIGNAL
-      + ROUTED met2 ( 1180130 193970 ) ( * 194140 )
-      NEW met3 ( 1180130 194140 ) ( 1182660 * )
-      NEW met4 ( 1182660 194140 ) ( * 198900 )
-      NEW met4 ( 1182660 198900 ) ( 1183110 * )
-      NEW met4 ( 1183110 198900 ) ( * 202300 0 )
-      NEW met2 ( 138690 2380 0 ) ( * 17850 )
-      NEW met1 ( 138690 17850 ) ( 144670 * )
-      NEW met1 ( 144670 193970 ) ( 1180130 * )
-      NEW met2 ( 144670 17850 ) ( * 193970 )
-      NEW met1 ( 1180130 193970 ) M1M2_PR
-      NEW met2 ( 1180130 194140 ) M2M3_PR_M
-      NEW met3 ( 1182660 194140 ) M3M4_PR_M
-      NEW met1 ( 138690 17850 ) M1M2_PR
-      NEW met1 ( 144670 17850 ) M1M2_PR
-      NEW met1 ( 144670 193970 ) M1M2_PR ;
-    - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mem din0[5] ) + USE SIGNAL
-      + ROUTED met2 ( 156630 2380 0 ) ( * 19550 )
-      NEW met1 ( 156630 19550 ) ( 1193930 * )
-      NEW met3 ( 1193930 193460 ) ( 1196460 * )
-      NEW met4 ( 1196460 193460 ) ( * 200260 )
-      NEW met4 ( 1196460 200260 ) ( 1196710 * )
-      NEW met4 ( 1196710 200260 ) ( * 202300 0 )
-      NEW met2 ( 1193930 19550 ) ( * 193460 )
-      NEW met1 ( 156630 19550 ) M1M2_PR
-      NEW met1 ( 1193930 19550 ) M1M2_PR
-      NEW met2 ( 1193930 193460 ) M2M3_PR_M
-      NEW met3 ( 1196460 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mem din0[6] ) + USE SIGNAL
-      + ROUTED met2 ( 174110 2380 0 ) ( * 16830 )
-      NEW met1 ( 174110 16830 ) ( 179170 * )
-      NEW met2 ( 1207730 194310 ) ( * 198220 )
-      NEW met3 ( 1207730 198220 ) ( 1209340 * )
-      NEW met4 ( 1209340 198220 ) ( * 200260 )
-      NEW met4 ( 1209340 200260 ) ( 1209630 * )
-      NEW met4 ( 1209630 200260 ) ( * 202300 0 )
-      NEW met1 ( 179170 194310 ) ( 1207730 * )
-      NEW met2 ( 179170 16830 ) ( * 194310 )
-      NEW met1 ( 174110 16830 ) M1M2_PR
-      NEW met1 ( 179170 16830 ) M1M2_PR
-      NEW met1 ( 179170 194310 ) M1M2_PR
-      NEW met1 ( 1207730 194310 ) M1M2_PR
-      NEW met2 ( 1207730 198220 ) M2M3_PR_M
-      NEW met3 ( 1209340 198220 ) M3M4_PR_M ;
-    - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mem din0[7] ) + USE SIGNAL
-      + ROUTED met2 ( 192050 2380 0 ) ( * 19890 )
-      NEW met1 ( 192050 19890 ) ( 1221530 * )
-      NEW met3 ( 1221530 193460 ) ( 1222220 * )
-      NEW met4 ( 1222220 193460 ) ( * 200260 )
-      NEW met4 ( 1222220 200260 ) ( 1222550 * )
-      NEW met4 ( 1222550 200260 ) ( * 202300 0 )
-      NEW met2 ( 1221530 19890 ) ( * 193460 )
-      NEW met1 ( 192050 19890 ) M1M2_PR
-      NEW met1 ( 1221530 19890 ) M1M2_PR
-      NEW met2 ( 1221530 193460 ) M2M3_PR_M
-      NEW met3 ( 1222220 193460 ) M3M4_PR_M ;
-    - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mem din0[8] ) + USE SIGNAL
-      + ROUTED met2 ( 209530 2380 0 ) ( * 16830 )
-      NEW met1 ( 209530 16830 ) ( 213670 * )
-      NEW met2 ( 213670 16830 ) ( * 194650 )
-      NEW met2 ( 1235330 194650 ) ( * 194820 )
-      NEW met3 ( 1235330 194820 ) ( 1236020 * )
-      NEW met4 ( 1236020 194820 ) ( * 200260 )
-      NEW met4 ( 1236020 200260 ) ( 1236150 * )
-      NEW met4 ( 1236150 200260 ) ( * 202300 0 )
-      NEW met1 ( 213670 194650 ) ( 1235330 * )
-      NEW met1 ( 209530 16830 ) M1M2_PR
-      NEW met1 ( 213670 16830 ) M1M2_PR
-      NEW met1 ( 213670 194650 ) M1M2_PR
-      NEW met1 ( 1235330 194650 ) M1M2_PR
-      NEW met2 ( 1235330 194820 ) M2M3_PR_M
-      NEW met3 ( 1236020 194820 ) M3M4_PR_M ;
-    - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mem din0[9] ) + USE SIGNAL
-      + ROUTED met2 ( 227470 2380 0 ) ( * 20230 )
-      NEW met3 ( 1249130 198900 ) ( 1249820 * )
-      NEW met4 ( 1249750 198900 ) ( 1249820 * )
-      NEW met4 ( 1249750 198900 ) ( * 202300 0 )
-      NEW met2 ( 1249130 20230 ) ( * 198900 )
-      NEW met1 ( 227470 20230 ) ( 1249130 * )
-      NEW met1 ( 227470 20230 ) M1M2_PR
-      NEW met1 ( 1249130 20230 ) M1M2_PR
-      NEW met2 ( 1249130 198900 ) M2M3_PR_M
-      NEW met3 ( 1249820 198900 ) M3M4_PR_M ;
-    - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj OUT[0] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 2279700 0 ) ( 2513210 * )
-      NEW met2 ( 2513210 16660 ) ( * 2279700 )
-      NEW met2 ( 49910 2380 0 ) ( * 16660 )
-      NEW met3 ( 49910 16660 ) ( 2513210 * )
-      NEW met2 ( 2513210 16660 ) M2M3_PR_M
-      NEW met2 ( 2513210 2279700 ) M2M3_PR_M
-      NEW met2 ( 49910 16660 ) M2M3_PR_M ;
+    - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) + USE SIGNAL ;
+    - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) + USE SIGNAL ;
+    - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) + USE SIGNAL ;
+    - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) + USE SIGNAL ;
+    - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) + USE SIGNAL ;
+    - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) + USE SIGNAL ;
+    - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) + USE SIGNAL ;
+    - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) + USE SIGNAL ;
+    - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) + USE SIGNAL ;
+    - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) + USE SIGNAL ;
+    - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) + USE SIGNAL ;
+    - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) + USE SIGNAL ;
+    - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) + USE SIGNAL ;
+    - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) + USE SIGNAL ;
+    - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) + USE SIGNAL ;
+    - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) + USE SIGNAL ;
+    - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) + USE SIGNAL ;
+    - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) + USE SIGNAL ;
+    - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) + USE SIGNAL ;
+    - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) + USE SIGNAL ;
+    - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) + USE SIGNAL ;
+    - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) + USE SIGNAL ;
+    - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) + USE SIGNAL ;
+    - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) + USE SIGNAL ;
+    - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) + USE SIGNAL ;
+    - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) + USE SIGNAL ;
+    - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) + USE SIGNAL ;
+    - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) + USE SIGNAL ;
+    - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) + USE SIGNAL ;
+    - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) + USE SIGNAL ;
+    - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) + USE SIGNAL ;
+    - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) + USE SIGNAL ;
+    - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) + USE SIGNAL ;
     - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) + USE SIGNAL ;
     - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) + USE SIGNAL ;
     - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) + USE SIGNAL ;
@@ -9275,14 +9374,7 @@
     - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) + USE SIGNAL ;
     - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) + USE SIGNAL ;
     - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) + USE SIGNAL ;
-    - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj OUT[1] ) + USE SIGNAL
-      + ROUTED met2 ( 2176030 2999820 0 ) ( * 3008830 )
-      NEW met1 ( 75670 3008830 ) ( 2176030 * )
-      NEW met2 ( 73830 2380 0 ) ( * 34500 )
-      NEW met2 ( 73830 34500 ) ( 75670 * )
-      NEW met2 ( 75670 34500 ) ( * 3008830 )
-      NEW met1 ( 75670 3008830 ) M1M2_PR
-      NEW met1 ( 2176030 3008830 ) M1M2_PR ;
+    - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) + USE SIGNAL ;
     - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) + USE SIGNAL ;
     - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) + USE SIGNAL ;
     - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) + USE SIGNAL ;
@@ -9293,111 +9385,21 @@
     - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) + USE SIGNAL ;
     - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) + USE SIGNAL ;
     - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) + USE SIGNAL ;
-    - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj OUT[2] ) + USE SIGNAL
-      + ROUTED met2 ( 97290 2380 0 ) ( * 15130 )
-      NEW met1 ( 97290 15130 ) ( 103270 * )
-      NEW met2 ( 103270 15130 ) ( * 1486990 )
-      NEW met2 ( 2460310 1486990 ) ( * 1500420 0 )
-      NEW met1 ( 103270 1486990 ) ( 2460310 * )
-      NEW met1 ( 97290 15130 ) M1M2_PR
-      NEW met1 ( 103270 15130 ) M1M2_PR
-      NEW met1 ( 103270 1486990 ) M1M2_PR
-      NEW met1 ( 2460310 1486990 ) M1M2_PR ;
+    - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) + USE SIGNAL ;
     - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) + USE SIGNAL ;
     - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) + USE SIGNAL ;
-    - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj OUT[3] ) + USE SIGNAL
-      + ROUTED met2 ( 121210 2380 0 ) ( * 18020 )
-      NEW met3 ( 2499180 2879460 0 ) ( 2511830 * )
-      NEW met2 ( 2511830 18020 ) ( * 2879460 )
-      NEW met3 ( 121210 18020 ) ( 2511830 * )
-      NEW met2 ( 121210 18020 ) M2M3_PR_M
-      NEW met2 ( 2511830 18020 ) M2M3_PR_M
-      NEW met2 ( 2511830 2879460 ) M2M3_PR_M ;
-    - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj OUT[4] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 1679940 0 ) ( 2506310 * )
-      NEW met2 ( 2506310 18190 ) ( * 1679940 )
-      NEW met2 ( 144670 2380 0 ) ( * 9180 )
-      NEW met2 ( 144210 9180 ) ( 144670 * )
-      NEW met2 ( 144210 9180 ) ( * 18530 )
-      NEW met1 ( 144210 18530 ) ( 179400 * )
-      NEW met1 ( 179400 18190 ) ( * 18530 )
-      NEW met1 ( 179400 18190 ) ( 2506310 * )
-      NEW met1 ( 2506310 18190 ) M1M2_PR
-      NEW met2 ( 2506310 1679940 ) M2M3_PR_M
-      NEW met1 ( 144210 18530 ) M1M2_PR ;
-    - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj OUT[5] ) + USE SIGNAL
-      + ROUTED met2 ( 987850 1973530 ) ( * 1979140 )
-      NEW met2 ( 162150 2380 0 ) ( * 17850 )
-      NEW met1 ( 162150 17850 ) ( 165370 * )
-      NEW met2 ( 165370 17850 ) ( * 1973530 )
-      NEW met1 ( 165370 1973530 ) ( 987850 * )
-      NEW met3 ( 987850 1979140 ) ( 1000500 * 0 )
-      NEW met2 ( 987850 1979140 ) M2M3_PR_M
-      NEW met1 ( 987850 1973530 ) M1M2_PR
-      NEW met1 ( 162150 17850 ) M1M2_PR
-      NEW met1 ( 165370 17850 ) M1M2_PR
-      NEW met1 ( 165370 1973530 ) M1M2_PR ;
-    - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj OUT[6] ) + USE SIGNAL
-      + ROUTED met2 ( 180090 2380 0 ) ( * 18530 )
-      NEW met1 ( 180090 18530 ) ( 185610 * )
-      NEW met2 ( 185610 18530 ) ( * 34500 )
-      NEW met2 ( 185610 34500 ) ( 186070 * )
-      NEW met2 ( 186070 34500 ) ( * 1488350 )
-      NEW met2 ( 1324110 1488350 ) ( * 1500420 0 )
-      NEW met1 ( 186070 1488350 ) ( 1324110 * )
-      NEW met1 ( 180090 18530 ) M1M2_PR
-      NEW met1 ( 185610 18530 ) M1M2_PR
-      NEW met1 ( 186070 1488350 ) M1M2_PR
-      NEW met1 ( 1324110 1488350 ) M1M2_PR ;
-    - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj OUT[7] ) + USE SIGNAL
-      + ROUTED met2 ( 989230 1856230 ) ( * 1859460 )
-      NEW met2 ( 198030 2380 0 ) ( * 34500 )
-      NEW met2 ( 198030 34500 ) ( 199870 * )
-      NEW met2 ( 199870 34500 ) ( * 1856230 )
-      NEW met1 ( 199870 1856230 ) ( 989230 * )
-      NEW met3 ( 989230 1859460 ) ( 1000500 * 0 )
-      NEW met1 ( 199870 1856230 ) M1M2_PR
-      NEW met2 ( 989230 1859460 ) M2M3_PR_M
-      NEW met1 ( 989230 1856230 ) M1M2_PR ;
-    - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj OUT[8] ) + USE SIGNAL
-      + ROUTED met2 ( 215510 2380 0 ) ( * 16830 )
-      NEW met1 ( 215510 16830 ) ( 220570 * )
-      NEW met2 ( 986930 1738930 ) ( * 1739780 )
-      NEW met2 ( 220570 16830 ) ( * 1738930 )
-      NEW met1 ( 220570 1738930 ) ( 986930 * )
-      NEW met3 ( 986930 1739780 ) ( 1000500 * 0 )
-      NEW met1 ( 215510 16830 ) M1M2_PR
-      NEW met1 ( 220570 16830 ) M1M2_PR
-      NEW met1 ( 220570 1738930 ) M1M2_PR
-      NEW met2 ( 986930 1739780 ) M2M3_PR_M
-      NEW met1 ( 986930 1738930 ) M1M2_PR ;
-    - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj OUT[9] ) + USE SIGNAL
-      + ROUTED met3 ( 2499180 1800980 0 ) ( 2505850 * )
-      NEW met2 ( 2505850 18530 ) ( * 1800980 )
-      NEW met2 ( 233450 2380 0 ) ( * 18530 )
-      NEW met1 ( 233450 18530 ) ( 2505850 * )
-      NEW met1 ( 2505850 18530 ) M1M2_PR
-      NEW met2 ( 2505850 1800980 ) M2M3_PR_M
-      NEW met1 ( 233450 18530 ) M1M2_PR ;
-    - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj init_en ) + USE SIGNAL
-      + ROUTED met2 ( 987850 2573970 ) ( * 2578900 )
-      NEW met2 ( 55890 2380 0 ) ( * 17850 )
-      NEW met1 ( 55890 17850 ) ( 61410 * )
-      NEW met2 ( 61410 17850 ) ( * 34500 )
-      NEW met2 ( 61410 34500 ) ( 61870 * )
-      NEW met2 ( 61870 34500 ) ( * 2573970 )
-      NEW met1 ( 61870 2573970 ) ( 987850 * )
-      NEW met3 ( 987850 2578900 ) ( 1000500 * 0 )
-      NEW met2 ( 987850 2578900 ) M2M3_PR_M
-      NEW met1 ( 987850 2573970 ) M1M2_PR
-      NEW met1 ( 55890 17850 ) M1M2_PR
-      NEW met1 ( 61410 17850 ) M1M2_PR
-      NEW met1 ( 61870 2573970 ) M1M2_PR ;
+    - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) + USE SIGNAL ;
+    - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) + USE SIGNAL ;
+    - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) + USE SIGNAL ;
+    - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) + USE SIGNAL ;
+    - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) + USE SIGNAL ;
+    - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) + USE SIGNAL ;
+    - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) + USE SIGNAL ;
+    - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) + USE SIGNAL ;
     - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) + USE SIGNAL ;
     - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) + USE SIGNAL ;
     - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) + USE SIGNAL ;
     - wbs_stb_i ( PIN wbs_stb_i ) + USE SIGNAL ;
     - wbs_we_i ( PIN wbs_we_i ) + USE SIGNAL ;
-    - zero_ ( mem csb0 ) + USE GROUND ;
 END NETS
 END DESIGN
diff --git a/gds/sram_32_256_sky130A.gds b/gds/sram_32_256_sky130A.gds
deleted file mode 100644
index 17f5412..0000000
--- a/gds/sram_32_256_sky130A.gds
+++ /dev/null
Binary files differ
diff --git a/gds/sram_32_256_sky130A.gds.gz b/gds/sram_32_256_sky130A.gds.gz
new file mode 100644
index 0000000..5ace880
--- /dev/null
+++ b/gds/sram_32_256_sky130A.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index adc6c88..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..41c8686
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index d7ccd07..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..0acc120
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index 9fb6c1f..eedd96e 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -6789,438 +6789,438 @@
   END wbs_we_i
   OBS
       LAYER li1 ;
-        RECT 1005.520 201.705 2494.080 2987.925 ;
+        RECT 1005.520 14.365 2494.080 2987.925 ;
       LAYER met1 ;
-        RECT 2.830 13.980 2515.210 3011.340 ;
+        RECT 2.830 14.320 2515.210 3010.320 ;
       LAYER met2 ;
         RECT 2.860 2.680 2515.190 3011.565 ;
-        RECT 3.550 2.400 7.950 2.680 ;
-        RECT 9.070 2.400 13.930 2.680 ;
-        RECT 15.050 2.400 19.910 2.680 ;
-        RECT 21.030 2.400 25.890 2.680 ;
-        RECT 27.010 2.400 31.870 2.680 ;
-        RECT 32.990 2.400 37.850 2.680 ;
-        RECT 38.970 2.400 43.370 2.680 ;
-        RECT 44.490 2.400 49.350 2.680 ;
-        RECT 50.470 2.400 55.330 2.680 ;
-        RECT 56.450 2.400 61.310 2.680 ;
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       LAYER met4 ;
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@@ -7317,47 +7317,74 @@
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   END
 END user_project_wrapper
 END LIBRARY
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index 242522c..1a1538d 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag
Binary files differ
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 19828c9..21927e7 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,82 +1,67 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636003697
+timestamp 1636199702
 << locali >>
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 << viali >>
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 << metal2 >>
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 rect 342490 345218 342726 345454
 rect 342490 344898 342726 345134
 rect 373210 345218 373446 345454
 rect 373210 344898 373446 345134
 rect 403930 345218 404166 345454
 rect 403930 344898 404166 345134
-rect 434650 345218 434886 345454
-rect 434650 344898 434886 345134
 rect 327130 327218 327366 327454
 rect 327130 326898 327366 327134
 rect 357850 327218 358086 327454
@@ -33028,16 +33040,12 @@
 rect 388570 326898 388806 327134
 rect 419290 327218 419526 327454
 rect 419290 326898 419526 327134
-rect 450010 327218 450246 327454
-rect 450010 326898 450246 327134
 rect 342490 309218 342726 309454
 rect 342490 308898 342726 309134
 rect 373210 309218 373446 309454
 rect 373210 308898 373446 309134
 rect 403930 309218 404166 309454
 rect 403930 308898 404166 309134
-rect 434650 309218 434886 309454
-rect 434650 308898 434886 309134
 rect 325826 291218 326062 291454
 rect 326146 291218 326382 291454
 rect 325826 290898 326062 291134
@@ -33070,6 +33078,10 @@
 rect 319306 32378 319542 32614
 rect 318986 32058 319222 32294
 rect 319306 32058 319542 32294
+rect 315266 -5382 315502 -5146
+rect 315586 -5382 315822 -5146
+rect 315266 -5702 315502 -5466
+rect 315586 -5702 315822 -5466
 rect 300986 -6342 301222 -6106
 rect 301306 -6342 301542 -6106
 rect 300986 -6662 301222 -6426
@@ -33858,10 +33870,6 @@
 rect 419866 24938 420102 25174
 rect 419546 24618 419782 24854
 rect 419866 24618 420102 24854
-rect 419546 -3462 419782 -3226
-rect 419866 -3462 420102 -3226
-rect 419546 -3782 419782 -3546
-rect 419866 -3782 420102 -3546
 rect 423266 280658 423502 280894
 rect 423586 280658 423822 280894
 rect 423266 280338 423502 280574
@@ -33890,14 +33898,40 @@
 rect 423586 64658 423822 64894
 rect 423266 64338 423502 64574
 rect 423586 64338 423822 64574
-rect 423266 28658 423502 28894
-rect 423586 28658 423822 28894
-rect 423266 28338 423502 28574
-rect 423586 28338 423822 28574
-rect 423266 -5382 423502 -5146
-rect 423586 -5382 423822 -5146
-rect 423266 -5702 423502 -5466
-rect 423586 -5702 423822 -5466
+rect 434650 597218 434886 597454
+rect 434650 596898 434886 597134
+rect 450010 579218 450246 579454
+rect 450010 578898 450246 579134
+rect 434650 561218 434886 561454
+rect 434650 560898 434886 561134
+rect 450010 543218 450246 543454
+rect 450010 542898 450246 543134
+rect 434650 525218 434886 525454
+rect 434650 524898 434886 525134
+rect 450010 507218 450246 507454
+rect 450010 506898 450246 507134
+rect 434650 489218 434886 489454
+rect 434650 488898 434886 489134
+rect 450010 471218 450246 471454
+rect 450010 470898 450246 471134
+rect 434650 453218 434886 453454
+rect 434650 452898 434886 453134
+rect 450010 435218 450246 435454
+rect 450010 434898 450246 435134
+rect 434650 417218 434886 417454
+rect 434650 416898 434886 417134
+rect 450010 399218 450246 399454
+rect 450010 398898 450246 399134
+rect 434650 381218 434886 381454
+rect 434650 380898 434886 381134
+rect 450010 363218 450246 363454
+rect 450010 362898 450246 363134
+rect 434650 345218 434886 345454
+rect 434650 344898 434886 345134
+rect 450010 327218 450246 327454
+rect 450010 326898 450246 327134
+rect 434650 309218 434886 309454
+rect 434650 308898 434886 309134
 rect 426986 284378 427222 284614
 rect 427306 284378 427542 284614
 rect 426986 284058 427222 284294
@@ -33926,6 +33960,18 @@
 rect 427306 68378 427542 68614
 rect 426986 68058 427222 68294
 rect 427306 68058 427542 68294
+rect 423266 28658 423502 28894
+rect 423586 28658 423822 28894
+rect 423266 28338 423502 28574
+rect 423586 28338 423822 28574
+rect 419546 -3462 419782 -3226
+rect 419866 -3462 420102 -3226
+rect 419546 -3782 419782 -3546
+rect 419866 -3782 420102 -3546
+rect 423266 -5382 423502 -5146
+rect 423586 -5382 423822 -5146
+rect 423266 -5702 423502 -5466
+rect 423586 -5702 423822 -5466
 rect 426986 32378 427222 32614
 rect 427306 32378 427542 32614
 rect 426986 32058 427222 32294
@@ -48028,11 +48074,11 @@
 rect 592618 -7622 592650 -7386
 rect -8726 -7654 592650 -7622
 use user_proj_example  mprj
-timestamp 1636003697
+timestamp 1636199702
 transform 1 0 200000 0 1 300000
 box 0 0 300000 300000
 use sram_32_256_sky130A  mem
-timestamp 1636003697
+timestamp 1636199702
 transform 1 0 200000 0 1 40000
 box 0 0 115676 71068
 << labels >>
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index 3fbfba5..e775690 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1635995321
+timestamp 1636138118
 << obsli1 >>
 rect 1104 2159 298816 297585
 << obsm1 >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 3b91305..7eb69ac 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,11 +1,11 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636003760
+timestamp 1636199764
 << obsli1 >>
-rect 201104 40341 498816 597585
+rect 201104 2873 498816 597585
 << obsm1 >>
-rect 566 2796 503042 602268
+rect 566 2864 503042 602064
 << metal2 >>
 rect 8086 703520 8198 704960
 rect 24278 703520 24390 704960
@@ -539,431 +539,431 @@
 rect 583362 -960 583474 480
 << obsm2 >>
 rect 572 536 503038 602313
-rect 710 480 1590 536
-rect 1814 480 2786 536
-rect 3010 480 3982 536
-rect 4206 480 5178 536
-rect 5402 480 6374 536
-rect 6598 480 7570 536
-rect 7794 480 8674 536
-rect 8898 480 9870 536
-rect 10094 480 11066 536
-rect 11290 480 12262 536
-rect 12486 480 13458 536
-rect 13682 480 14654 536
-rect 14878 480 15850 536
-rect 16074 480 16954 536
-rect 17178 480 18150 536
-rect 18374 480 19346 536
-rect 19570 480 20542 536
-rect 20766 480 21738 536
-rect 21962 480 22934 536
-rect 23158 480 24130 536
-rect 24354 480 25234 536
-rect 25458 480 26430 536
-rect 26654 480 27626 536
-rect 27850 480 28822 536
-rect 29046 480 30018 536
-rect 30242 480 31214 536
-rect 31438 480 32318 536
-rect 32542 480 33514 536
-rect 33738 480 34710 536
-rect 34934 480 35906 536
-rect 36130 480 37102 536
-rect 37326 480 38298 536
-rect 38522 480 39494 536
-rect 39718 480 40598 536
-rect 40822 480 41794 536
-rect 42018 480 42990 536
-rect 43214 480 44186 536
-rect 44410 480 45382 536
-rect 45606 480 46578 536
-rect 46802 480 47774 536
-rect 47998 480 48878 536
-rect 49102 480 50074 536
-rect 50298 480 51270 536
-rect 51494 480 52466 536
-rect 52690 480 53662 536
-rect 53886 480 54858 536
-rect 55082 480 55962 536
-rect 56186 480 57158 536
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-rect 64466 480 65438 536
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-rect 68054 480 69026 536
-rect 69250 480 70222 536
-rect 70446 480 71418 536
-rect 71642 480 72522 536
-rect 72746 480 73718 536
-rect 73942 480 74914 536
-rect 75138 480 76110 536
-rect 76334 480 77306 536
-rect 77530 480 78502 536
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-rect 90502 480 91474 536
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-rect 95286 480 96166 536
-rect 96390 480 97362 536
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-rect 102370 480 103250 536
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-rect 115342 480 116314 536
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-rect 117734 480 118706 536
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-rect 120034 480 121006 536
-rect 121230 480 122202 536
-rect 122426 480 123398 536
-rect 123622 480 124594 536
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-rect 127118 480 128090 536
-rect 128314 480 129286 536
-rect 129510 480 130482 536
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-rect 133098 480 134070 536
-rect 134294 480 135174 536
-rect 135398 480 136370 536
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-rect 137790 480 138762 536
-rect 138986 480 139958 536
-rect 140182 480 141154 536
-rect 141378 480 142350 536
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-rect 150762 480 151734 536
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-rect 154350 480 155322 536
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-rect 156742 480 157714 536
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-rect 175602 480 176574 536
-rect 176798 480 177770 536
-rect 177994 480 178966 536
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-rect 189862 480 190742 536
-rect 190966 480 191938 536
-rect 192162 480 193134 536
-rect 193358 480 194330 536
-rect 194554 480 195526 536
-rect 195750 480 196722 536
-rect 196946 480 197826 536
-rect 198050 480 199022 536
-rect 199246 480 200218 536
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-rect 201638 480 202610 536
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-rect 209918 480 210890 536
-rect 211114 480 212086 536
-rect 212310 480 213282 536
-rect 213506 480 214386 536
-rect 214610 480 215582 536
-rect 215806 480 216778 536
-rect 217002 480 217974 536
-rect 218198 480 219170 536
-rect 219394 480 220366 536
-rect 220590 480 221470 536
-rect 221694 480 222666 536
-rect 222890 480 223862 536
-rect 224086 480 225058 536
-rect 225282 480 226254 536
-rect 226478 480 227450 536
-rect 227674 480 228646 536
-rect 228870 480 229750 536
-rect 229974 480 230946 536
-rect 231170 480 232142 536
-rect 232366 480 233338 536
-rect 233562 480 234534 536
-rect 234758 480 235730 536
-rect 235954 480 236926 536
-rect 237150 480 238030 536
-rect 238254 480 239226 536
-rect 239450 480 240422 536
-rect 240646 480 241618 536
-rect 241842 480 242814 536
-rect 243038 480 244010 536
-rect 244234 480 245114 536
-rect 245338 480 246310 536
-rect 246534 480 247506 536
-rect 247730 480 248702 536
-rect 248926 480 249898 536
-rect 250122 480 251094 536
-rect 251318 480 252290 536
-rect 252514 480 253394 536
-rect 253618 480 254590 536
-rect 254814 480 255786 536
-rect 256010 480 256982 536
-rect 257206 480 258178 536
-rect 258402 480 259374 536
-rect 259598 480 260570 536
-rect 260794 480 261674 536
-rect 261898 480 262870 536
-rect 263094 480 264066 536
-rect 264290 480 265262 536
-rect 265486 480 266458 536
-rect 266682 480 267654 536
-rect 267878 480 268758 536
-rect 268982 480 269954 536
-rect 270178 480 271150 536
-rect 271374 480 272346 536
-rect 272570 480 273542 536
-rect 273766 480 274738 536
-rect 274962 480 275934 536
-rect 276158 480 277038 536
-rect 277262 480 278234 536
-rect 278458 480 279430 536
-rect 279654 480 280626 536
-rect 280850 480 281822 536
-rect 282046 480 283018 536
-rect 283242 480 284214 536
-rect 284438 480 285318 536
-rect 285542 480 286514 536
-rect 286738 480 287710 536
-rect 287934 480 288906 536
-rect 289130 480 290102 536
-rect 290326 480 291298 536
-rect 291522 480 292494 536
-rect 292718 480 293598 536
-rect 293822 480 294794 536
-rect 295018 480 295990 536
-rect 296214 480 297186 536
-rect 297410 480 298382 536
-rect 298606 480 299578 536
-rect 299802 480 300682 536
-rect 300906 480 301878 536
-rect 302102 480 303074 536
-rect 303298 480 304270 536
-rect 304494 480 305466 536
-rect 305690 480 306662 536
-rect 306886 480 307858 536
-rect 308082 480 308962 536
-rect 309186 480 310158 536
-rect 310382 480 311354 536
-rect 311578 480 312550 536
-rect 312774 480 313746 536
-rect 313970 480 314942 536
-rect 315166 480 316138 536
-rect 316362 480 317242 536
-rect 317466 480 318438 536
-rect 318662 480 319634 536
-rect 319858 480 320830 536
-rect 321054 480 322026 536
-rect 322250 480 323222 536
-rect 323446 480 324326 536
-rect 324550 480 325522 536
-rect 325746 480 326718 536
-rect 326942 480 327914 536
-rect 328138 480 329110 536
-rect 329334 480 330306 536
-rect 330530 480 331502 536
-rect 331726 480 332606 536
-rect 332830 480 333802 536
-rect 334026 480 334998 536
-rect 335222 480 336194 536
-rect 336418 480 337390 536
-rect 337614 480 338586 536
-rect 338810 480 339782 536
-rect 340006 480 340886 536
-rect 341110 480 342082 536
-rect 342306 480 343278 536
-rect 343502 480 344474 536
-rect 344698 480 345670 536
-rect 345894 480 346866 536
-rect 347090 480 347970 536
-rect 348194 480 349166 536
-rect 349390 480 350362 536
-rect 350586 480 351558 536
-rect 351782 480 352754 536
-rect 352978 480 353950 536
-rect 354174 480 355146 536
-rect 355370 480 356250 536
-rect 356474 480 357446 536
-rect 357670 480 358642 536
-rect 358866 480 359838 536
-rect 360062 480 361034 536
-rect 361258 480 362230 536
-rect 362454 480 363426 536
-rect 363650 480 364530 536
-rect 364754 480 365726 536
-rect 365950 480 366922 536
-rect 367146 480 368118 536
-rect 368342 480 369314 536
-rect 369538 480 370510 536
-rect 370734 480 371614 536
-rect 371838 480 372810 536
-rect 373034 480 374006 536
-rect 374230 480 375202 536
-rect 375426 480 376398 536
-rect 376622 480 377594 536
-rect 377818 480 378790 536
-rect 379014 480 379894 536
-rect 380118 480 381090 536
-rect 381314 480 382286 536
-rect 382510 480 383482 536
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-rect 384902 480 385874 536
-rect 386098 480 387070 536
-rect 387294 480 388174 536
-rect 388398 480 389370 536
-rect 389594 480 390566 536
-rect 390790 480 391762 536
-rect 391986 480 392958 536
-rect 393182 480 394154 536
-rect 394378 480 395258 536
-rect 395482 480 396454 536
-rect 396678 480 397650 536
-rect 397874 480 398846 536
-rect 399070 480 400042 536
-rect 400266 480 401238 536
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-rect 403762 480 404734 536
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-rect 406154 480 407126 536
-rect 407350 480 408322 536
-rect 408546 480 409518 536
-rect 409742 480 410714 536
-rect 410938 480 411818 536
-rect 412042 480 413014 536
-rect 413238 480 414210 536
-rect 414434 480 415406 536
-rect 415630 480 416602 536
-rect 416826 480 417798 536
-rect 418022 480 418902 536
-rect 419126 480 420098 536
-rect 420322 480 421294 536
-rect 421518 480 422490 536
-rect 422714 480 423686 536
-rect 423910 480 424882 536
-rect 425106 480 426078 536
-rect 426302 480 427182 536
-rect 427406 480 428378 536
-rect 428602 480 429574 536
-rect 429798 480 430770 536
-rect 430994 480 431966 536
-rect 432190 480 433162 536
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-rect 434582 480 435462 536
-rect 435686 480 436658 536
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-rect 438078 480 439050 536
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-rect 443966 480 444938 536
-rect 445162 480 446134 536
-rect 446358 480 447330 536
-rect 447554 480 448526 536
-rect 448750 480 449722 536
-rect 449946 480 450826 536
-rect 451050 480 452022 536
-rect 452246 480 453218 536
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-rect 454638 480 455610 536
-rect 455834 480 456806 536
-rect 457030 480 458002 536
-rect 458226 480 459106 536
-rect 459330 480 460302 536
-rect 460526 480 461498 536
-rect 461722 480 462694 536
-rect 462918 480 463890 536
-rect 464114 480 465086 536
-rect 465310 480 466190 536
-rect 466414 480 467386 536
-rect 467610 480 468582 536
-rect 468806 480 469778 536
-rect 470002 480 470974 536
-rect 471198 480 472170 536
-rect 472394 480 473366 536
-rect 473590 480 474470 536
-rect 474694 480 475666 536
-rect 475890 480 476862 536
-rect 477086 480 478058 536
-rect 478282 480 479254 536
-rect 479478 480 480450 536
-rect 480674 480 481646 536
-rect 481870 480 482750 536
-rect 482974 480 483946 536
-rect 484170 480 485142 536
-rect 485366 480 486338 536
-rect 486562 480 487534 536
-rect 487758 480 488730 536
-rect 488954 480 489834 536
-rect 490058 480 491030 536
-rect 491254 480 492226 536
-rect 492450 480 493422 536
-rect 493646 480 494618 536
-rect 494842 480 495814 536
-rect 496038 480 497010 536
-rect 497234 480 498114 536
-rect 498338 480 499310 536
-rect 499534 480 500506 536
-rect 500730 480 501702 536
-rect 501926 480 502898 536
+rect 710 462 1590 536
+rect 1814 462 2786 536
+rect 3010 462 3982 536
+rect 4206 462 5178 536
+rect 5402 462 6374 536
+rect 6598 462 7570 536
+rect 7794 462 8674 536
+rect 8898 462 9870 536
+rect 10094 462 11066 536
+rect 11290 462 12262 536
+rect 12486 462 13458 536
+rect 13682 462 14654 536
+rect 14878 462 15850 536
+rect 16074 462 16954 536
+rect 17178 462 18150 536
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+rect 23158 462 24130 536
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+rect 25458 462 26430 536
+rect 26654 462 27626 536
+rect 27850 462 28822 536
+rect 29046 462 30018 536
+rect 30242 462 31214 536
+rect 31438 462 32318 536
+rect 32542 462 33514 536
+rect 33738 462 34710 536
+rect 34934 462 35906 536
+rect 36130 462 37102 536
+rect 37326 462 38298 536
+rect 38522 462 39494 536
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+rect 40822 462 41794 536
+rect 42018 462 42990 536
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+rect 44410 462 45382 536
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+rect 46802 462 47774 536
+rect 47998 462 48878 536
+rect 49102 462 50074 536
+rect 50298 462 51270 536
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+rect 55082 462 55962 536
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+rect 64466 462 65438 536
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+rect 68054 462 69026 536
+rect 69250 462 70222 536
+rect 70446 462 71418 536
+rect 71642 462 72522 536
+rect 72746 462 73718 536
+rect 73942 462 74914 536
+rect 75138 462 76110 536
+rect 76334 462 77306 536
+rect 77530 462 78502 536
+rect 78726 462 79606 536
+rect 79830 462 80802 536
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+rect 82222 462 83194 536
+rect 83418 462 84390 536
+rect 84614 462 85586 536
+rect 85810 462 86782 536
+rect 87006 462 87886 536
+rect 88110 462 89082 536
+rect 89306 462 90278 536
+rect 90502 462 91474 536
+rect 91698 462 92670 536
+rect 92894 462 93866 536
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+rect 95286 462 96166 536
+rect 96390 462 97362 536
+rect 97586 462 98558 536
+rect 98782 462 99754 536
+rect 99978 462 100950 536
+rect 101174 462 102146 536
+rect 102370 462 103250 536
+rect 103474 462 104446 536
+rect 104670 462 105642 536
+rect 105866 462 106838 536
+rect 107062 462 108034 536
+rect 108258 462 109230 536
+rect 109454 462 110426 536
+rect 110650 462 111530 536
+rect 111754 462 112726 536
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+rect 114146 462 115118 536
+rect 115342 462 116314 536
+rect 116538 462 117510 536
+rect 117734 462 118706 536
+rect 118930 462 119810 536
+rect 120034 462 121006 536
+rect 121230 462 122202 536
+rect 122426 462 123398 536
+rect 123622 462 124594 536
+rect 124818 462 125790 536
+rect 126014 462 126894 536
+rect 127118 462 128090 536
+rect 128314 462 129286 536
+rect 129510 462 130482 536
+rect 130706 462 131678 536
+rect 131902 462 132874 536
+rect 133098 462 134070 536
+rect 134294 462 135174 536
+rect 135398 462 136370 536
+rect 136594 462 137566 536
+rect 137790 462 138762 536
+rect 138986 462 139958 536
+rect 140182 462 141154 536
+rect 141378 462 142350 536
+rect 142574 462 143454 536
+rect 143678 462 144650 536
+rect 144874 462 145846 536
+rect 146070 462 147042 536
+rect 147266 462 148238 536
+rect 148462 462 149434 536
+rect 149658 462 150538 536
+rect 150762 462 151734 536
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 << metal3 >>
 rect -960 697220 480 697460
 rect 583520 697084 584960 697324
@@ -1073,7 +1073,7 @@
 rect 583520 19668 584960 19908
 rect 583520 6476 584960 6716
 << obsm3 >>
-rect 9949 3299 503043 602309
+rect 197997 3299 503043 602309
 << metal4 >>
 rect -8726 -7654 -8106 711590
 rect -7766 -6694 -7146 710630
@@ -1412,47 +1412,74 @@
 rect 308494 112988 311434 298080
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 << metal5 >>
 rect -8726 710970 592650 711590
 rect -7766 710010 591690 710630
@@ -3732,7 +3759,7 @@
 string FIXED_BBOX 0 0 584000 704000
 string LEFview TRUE
 string GDS_FILE /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.gds
-string GDS_END 71540146
+string GDS_END 71541042
 string GDS_START 70505550
 << end >>
 
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 71545ce..580d926 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -26,7 +26,7 @@
 	$script_dir/../../verilog/rtl/clk_gate.v \
 	$script_dir/../../verilog/rtl/rvmyth.v"
 set ::env(VERILOG_INCLUDE_DIRS) "\
-	$script_dir/../../verilog/include"
+	$script_dir/../../verilog/rtl/include"
 
 set ::env(DESIGN_IS_CORE) 0
 
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv
index 3a995d1..9fdfbff 100644
--- a/signoff/user_proj_example/final_summary_report.csv
+++ b/signoff/user_proj_example/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h55m31s,-1,10616.0,2.25,5308.0,5.6,1606.75,11943,0,0,0,0,0,0,0,17,0,0,-1,865563,136959,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,613459023.0,0.1,10.22,8.84,0.12,0.2,-1,9113,11620,311,2818,0,0,0,11242,0,0,0,0,0,0,0,4,2161,2532,23,1086,31337,0,32423,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.2,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,1h11m38s,-1,10616.0,2.25,5308.0,5.6,1606.68,11943,0,0,0,0,0,0,0,17,0,0,-1,865563,136959,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,613459023.0,0.1,10.22,8.84,0.12,0.2,-1,9113,11620,311,2818,0,0,0,11242,0,0,0,0,0,0,0,4,2161,2532,23,1086,31337,0,32423,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.2,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7882249..dc6eddc 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h21m23s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,495.0,2,0,0,0,0,0,0,0,0,0,-1,-1,231408,495,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.36,0.64,0.11,0.3,-1,30,686,30,686,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h21m16s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,494.03,2,0,0,0,0,0,0,0,0,0,-1,-1,192116,500,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.22,0.61,0.05,0.37,-1,31,687,31,687,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice b/spi/lvs/user_project_wrapper.spice
index 0a94a4f..1f51158 100644
--- a/spi/lvs/user_project_wrapper.spice
+++ b/spi/lvs/user_project_wrapper.spice
@@ -126,28 +126,29 @@
 + wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3]
 + wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0]
 + wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
-Xmprj wb_clk_i wbs_dat_o[0] wbs_dat_o[1] wbs_dat_o[2] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5]
-+ wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] mem/dout0[0] mem/dout0[10] mem/dout0[11]
-+ mem/dout0[12] mem/dout0[13] mem/dout0[14] mem/dout0[15] mem/dout0[16] mem/dout0[17]
-+ mem/dout0[18] mem/dout0[19] mem/dout0[1] mem/dout0[20] mem/dout0[21] mem/dout0[22]
-+ mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26] mem/dout0[27] mem/dout0[28]
-+ mem/dout0[29] mem/dout0[2] mem/dout0[30] mem/dout0[31] mem/dout0[3] mem/dout0[4]
-+ mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8] mem/dout0[9] wbs_adr_i[0] wbs_adr_i[1]
-+ wbs_adr_i[2] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_sel_i[0]
-+ mem/addr0[0] mem/addr0[1] mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6]
-+ mem/addr0[7] mem/web0 wb_rst_i vccd1 vssd1 user_proj_example
-Xmem mem/csb0 mem/web0 wb_clk_i wbs_dat_i[0] wbs_dat_i[1] wbs_dat_i[2] wbs_dat_i[3]
-+ wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_i[10]
-+ wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16]
-+ wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22]
-+ wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28]
-+ wbs_dat_i[29] wbs_dat_i[30] wbs_dat_i[31] mem/dout0[0] mem/dout0[1] mem/dout0[2]
-+ mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8] mem/dout0[9]
-+ mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14] mem/dout0[15]
-+ mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[20] mem/dout0[21]
-+ mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26] mem/dout0[27]
-+ mem/dout0[28] mem/dout0[29] mem/dout0[30] mem/dout0[31] mem/addr0[0] mem/addr0[1]
-+ mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7] vccd1
-+ vssd1 sram_32_256_sky130A
+Xmprj wb_clk_i la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68]
++ la_data_out[69] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73]
++ mem/dout0[0] mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14]
++ mem/dout0[15] mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[1]
++ mem/dout0[20] mem/dout0[21] mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25]
++ mem/dout0[26] mem/dout0[27] mem/dout0[28] mem/dout0[29] mem/dout0[2] mem/dout0[30]
++ mem/dout0[31] mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8]
++ mem/dout0[9] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48]
++ la_data_in[49] la_data_in[50] la_data_in[51] la_data_in[36] mem/addr0[0] mem/addr0[1]
++ mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7] mem/web0
++ la_data_in[32] vccd1 vssd1 user_proj_example
+Xmem la_data_in[40] mem/web0 wb_clk_i la_data_in[0] la_data_in[1] la_data_in[2] la_data_in[3]
++ la_data_in[4] la_data_in[5] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9]
++ la_data_in[10] la_data_in[11] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15]
++ la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[30] la_data_in[31] mem/dout0[0] mem/dout0[1]
++ mem/dout0[2] mem/dout0[3] mem/dout0[4] mem/dout0[5] mem/dout0[6] mem/dout0[7] mem/dout0[8]
++ mem/dout0[9] mem/dout0[10] mem/dout0[11] mem/dout0[12] mem/dout0[13] mem/dout0[14]
++ mem/dout0[15] mem/dout0[16] mem/dout0[17] mem/dout0[18] mem/dout0[19] mem/dout0[20]
++ mem/dout0[21] mem/dout0[22] mem/dout0[23] mem/dout0[24] mem/dout0[25] mem/dout0[26]
++ mem/dout0[27] mem/dout0[28] mem/dout0[29] mem/dout0[30] mem/dout0[31] mem/addr0[0]
++ mem/addr0[1] mem/addr0[2] mem/addr0[3] mem/addr0[4] mem/addr0[5] mem/addr0[6] mem/addr0[7]
++ vccd1 vssd1 sram_32_256_sky130A
 .ends
 
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d87238f..42dec11 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = la_test
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
deleted file mode 100644
index 5237a05..0000000
--- a/verilog/dv/io_ports/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = io_ports
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
-	$(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
-	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
-	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
deleted file mode 100644
index 0b23571..0000000
--- a/verilog/dv/io_ports/io_ports.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
-	IO Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
-	/* 
-	IO Control Registers
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
-
-	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
-	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-
-	*/
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-	// Configure lower 8-IOs as user output
-	// Observe counter value in the testbench
-	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-}
-
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
deleted file mode 100644
index f7628bc..0000000
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
-module io_ports_tb;
-	reg clock;
-	reg RSTB;
-	reg CSB;
-	reg power1, power2;
-	reg power3, power4;
-
-    	wire gpio;
-    	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-
-	assign mprj_io_0 = mprj_io[7:0];
-	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
-
-	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-	// assign mprj_io[3] = 1'b1;
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("io_ports.vcd");
-		$dumpvars(0, io_ports_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-	    // Observe Output pins [7:0]
-	    wait(mprj_io_0 == 8'h01);
-	    wait(mprj_io_0 == 8'h02);
-	    wait(mprj_io_0 == 8'h03);
-    	    wait(mprj_io_0 == 8'h04);
-	    wait(mprj_io_0 == 8'h05);
-            wait(mprj_io_0 == 8'h06);
-	    wait(mprj_io_0 == 8'h07);
-            wait(mprj_io_0 == 8'h08);
-	    wait(mprj_io_0 == 8'h09);
-            wait(mprj_io_0 == 8'h0A);   
-	    wait(mprj_io_0 == 8'hFF);
-	    wait(mprj_io_0 == 8'h00);
-		
-		`ifdef GL
-	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
-		`else
-		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
-		`endif
-	    $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#170000;
-		CSB = 1'b0;		// CSB can be released
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
-		#100;
-		power1 <= 1'b1;
-		#100;
-		power2 <= 1'b1;
-		#100;
-		power3 <= 1'b1;
-		#100;
-		power4 <= 1'b1;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("io_ports.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/la_test/Makefile
similarity index 92%
rename from verilog/dv/wb_port/Makefile
rename to verilog/dv/la_test/Makefile
index 1c784c6..2f7b008 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/la_test/Makefile
@@ -28,6 +28,7 @@
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_INCLUDE_PATH = $(UPRJ_RTL_PATH)/include
 UPRJ_BEHAVIOURAL_MODELS = ../
 
 ## RISCV GCC 
@@ -40,7 +41,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = la_test
 
 all:  ${PATTERN:=.vcd}
 
@@ -50,12 +51,12 @@
 ifeq ($(SIM),RTL)
 	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_INCLUDE_PATH) \
 	$< -o $@ 
 else  
 	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
 endif
 
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
new file mode 100644
index 0000000..a8d1a94
--- /dev/null
+++ b/verilog/dv/la_test/la_test.c
@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	MPRJ LA Test:
+                - Sets MPRJ initial data through LA[31:0]
+		- Sets MPRJ clk through LA[32]
+		- Sets MPRJ rst through LA[36]
+                - Sets MPRJ initial write enable through LA[40]
+                - Sets MPRJ initial address through LA[51:44]
+		- Observes 10-bit result of the initial program (e.g. sum of 0 to 9) which will be written on r17 through LA[73:64]
+*/
+
+int clk = 0;
+
+int getIMemContent(int addr) {
+        return 
+                addr == 0x0 ? 0b00000000000100000000010010010011 :
+		addr == 0x1 ? 0b00000010101100000000010100010011 :
+		addr == 0x2 ? 0b00000000000000000000010110010011 :
+		addr == 0x3 ? 0b00000000000000000000100010010011 :
+		addr == 0x4 ? 0b00000000101110001000100010110011 :
+		addr == 0x5 ? 0b00000000000101011000010110010011 :
+		addr == 0x6 ? 0b11111110101001011001110011100011 :
+		addr == 0x7 ? 0b00000000101110001000100010110011 :
+		addr == 0x8 ? 0b01000000101110001000100010110011 :
+		addr == 0x9 ? 0b01000000100101011000010110110011 :
+		addr == 0xA ? 0b11111110100101011001110011100011 :
+		addr == 0xB ? 0b01000000101110001000100010110011 :
+		addr == 0xC ? 0b11111110000000000000000011100011 :
+	                      0b00000000000000000000000000000000 ;
+}
+
+void main()
+{
+        /* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+
+	// All GPIO pins are configured to be output
+	// Used to flad the start/end of a test 
+
+        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+	// Configure All LA probes 
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]   => Output from the CPU
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]  => Output from the CPU
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]  => Input to the CPU
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96] => Input to the CPU
+
+	// Flag start of the test
+	reg_mprj_datal = 0xAB600000;
+
+	// [31: 0] => DAT_IN 
+        reg_la0_data = 0x00000000;
+
+        // [ 3: 0] => RST // Active High
+        // [ 7: 4] => WEN // Active High
+        // [11: 8] => CSB // Active Low
+        // [19:12] => ADR
+	reg_la1_data = 0x00000000;
+
+        // Delay
+        for (int i = 0; i < 5; i++);
+
+	// IMem initiation
+	for (int i = 0; i < 13; i++) {
+                reg_la1_data = 0x00000011 | i << 12;
+                reg_la0_data = 
+                        i == 0x0        ?       0b00000000000100000000010010010011      :
+                        i == 0x1        ?       0b00000010101100000000010100010011      :
+                        i == 0x2        ?       0b00000000000000000000010110010011      :
+                        i == 0x3        ?       0b00000000000000000000100010010011      :
+                        i == 0x4        ?       0b00000000101110001000100010110011      :
+                        i == 0x5        ?       0b00000000000101011000010110010011      :
+                        i == 0x6        ?       0b11111110101001011001110011100011      :
+                        i == 0x7        ?       0b00000000101110001000100010110011      :
+                        i == 0x8        ?       0b01000000101110001000100010110011      :
+                        i == 0x9        ?       0b01000000100101011000010110110011      :
+                        i == 0xA        ?       0b11111110100101011001110011100011      :
+                        i == 0xB        ?       0b01000000101110001000100010110011      :
+                        i == 0xC        ?       0b11111110000000000000000011100011      :
+                                                0b00000000000000000000000000000000      ;
+	}
+
+        // Write enable signal de-assert and keep reset asserted
+        reg_la1_data = 0x00000001;
+        // Wait for a few clocks to propagate signals
+        for (int i = 0; i < 2; i++);
+        // Reset signal de-assert and RVMYTH starts
+        reg_la1_data = 0x00000000;
+        // Wait for the expected result
+        while ((reg_la2_data & 0x000003FF) != 0x2D);
+        // Test has been done successfully
+	reg_mprj_datal = 0xAB610000;
+}
+
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test/la_test_tb.v
similarity index 88%
rename from verilog/dv/la_test2/la_test2_tb.v
rename to verilog/dv/la_test/la_test_tb.v
index e09905e..2fd892d 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -21,15 +21,15 @@
 `include "caravel_netlists.v"
 `include "spiflash.v"
 
-module la_test2_tb;
+module la_test_tb;
 	reg clock;
 	reg RSTB;
 	reg CSB;
 
 	reg power1, power2;
 
-    	wire gpio;
-    	wire [37:0] mprj_io;
+    wire gpio;
+    wire [37:0] mprj_io;
 	wire [15:0] checkbits;
 
 	assign checkbits = mprj_io[31:16];
@@ -42,11 +42,12 @@
 	end
 
 	initial begin
-		$dumpfile("la_test2.vcd");
-		$dumpvars(0, la_test2_tb);
+		$dumpfile("la_test.vcd");
+		$dumpvars(0, la_test_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
+		// Clock preiod is 25ns => 60 * 1000 * 25 = 1,500,000ns (whole simulation time)
+		repeat (60) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
@@ -70,9 +71,9 @@
 
 	initial begin
 		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
+		CSB  <= 1'b1;	// Force CSB high
 		#2000;
-		RSTB <= 1'b1;	    	// Release reset
+		RSTB <= 1'b1;	// Release reset
 		#170000;
 		CSB = 1'b0;		// CSB can be released
 	end
@@ -116,7 +117,7 @@
 		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
+        .mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
@@ -125,7 +126,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("la_test2.hex")
+		.FILENAME("la_test.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
deleted file mode 100644
index ba979f7..0000000
--- a/verilog/dv/la_test1/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = la_test1
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
-	$(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
-	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
-	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
deleted file mode 100644
index 220bdfe..0000000
--- a/verilog/dv/la_test1/la_test1.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-// --------------------------------------------------------
-
-/*
-	MPRJ Logic Analyzer Test:
-		- Observes counter value through LA probes [31:0] 
-		- Sets counter initial value through LA probes [63:32]
-		- Flags when counter value exceeds 500 through the management SoC gpio
-		- Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-	// The upper GPIO pins are configured to be output
-	// and accessble to the management SoC.
-	// Used to flad the start/end of a test 
-	// The lower GPIO pins are configured to be output
-	// and accessible to the user project.  They show
-	// the project count value, although this test is
-	// designed to read the project count through the
-	// logic analyzer probes.
-	// I/O 6 is configured for the UART Tx line
-
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-        reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	// Set UART clock to 64 kbaud (enable before I/O configuration)
-	reg_uart_clkdiv = 625;
-	reg_uart_enable = 1;
-
-        /* Apply configuration */
-        reg_mprj_xfer = 1;
-        while (reg_mprj_xfer == 1);
-
-	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
-	// Configure LA probes [63:32] as outputs from the cpu
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
-
-	// Flag start of the test 
-	reg_mprj_datal = 0xAB400000;
-
-	// Set Counter value to zero through LA probes [63:32]
-	reg_la1_data = 0x00000000;
-
-	// Configure LA probes from [63:32] as inputs to disable counter write
-	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    
-
-	while (1) {
-		if (reg_la0_data > 0x1F4) {
-			reg_mprj_datal = 0xAB410000;
-			break;
-		}
-	}
-	print("\n");
-	print("Monitor: Test 2 Passed\n\n");	// Makes simulation very long!
-	reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
deleted file mode 100644
index 626e390..0000000
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module la_test1_tb;
-	reg clock;
-    reg RSTB;
-	reg CSB;
-
-	reg power1, power2;
-
-    	wire gpio;
-	wire uart_tx;
-    	wire [37:0] mprj_io;
-	wire [15:0] checkbits;
-
-	assign checkbits  = mprj_io[31:16];
-	assign uart_tx = mprj_io[6];
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-	initial begin
-		// $dumpfile("la_test1.vcd");
-		// $dumpvars(0, la_test1_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (200) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test LA (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test LA (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		wait(checkbits == 16'hAB40);
-		$display("LA Test 1 started");
-		wait(checkbits == 16'hAB41);
-		wait(checkbits == 16'hAB51);
-		#10000;
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#170000;
-		CSB = 1'b0;		// CSB can be released
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-    	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD1V8;
-    	wire VDD3V3;
-	wire VSS;
-    
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("la_test1.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-	// Testbench UART
-	tbuart tbuart (
-		.ser_rx(uart_tx)
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
deleted file mode 100644
index 0435500..0000000
--- a/verilog/dv/la_test2/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = la_test2
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
-	$(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
-	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
-	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
deleted file mode 100644
index 5875432..0000000
--- a/verilog/dv/la_test2/la_test2.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
-	MPRJ LA Test:
-		- Sets counter clk through LA[64]
-		- Sets counter rst through LA[65] 
-		- Observes count value for five clk cycle through LA[31:0]
-*/
-
-int clk = 0;
-int i;
-
-void main()
-{
-        /* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-
-	// All GPIO pins are configured to be output
-	// Used to flad the start/end of a test 
-
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-        /* Apply configuration */
-        reg_mprj_xfer = 1;
-        while (reg_mprj_xfer == 1);
-
-	// Configure All LA probes as inputs to the cpu 
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
-
-	// Flag start of the test
-	reg_mprj_datal = 0xAB600000;
-
-	// Configure LA[64] LA[65] as outputs from the cpu
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; 
-
-	// Set clk & reset to one
-	reg_la2_data = 0x00000003;
-
-        // DELAY
-        for (i=0; i<5; i=i+1) {}
-
-	// Toggle clk & de-assert reset
-	for (i=0; i<11; i=i+1) {
-		clk = !clk;
-		reg_la2_data = 0x00000000 | clk;
-	}
-
-	if (reg_la0_data >= 0x05) {
-		reg_mprj_datal = 0xAB610000;
-	}
-
-}
-
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
deleted file mode 100644
index 3a73b99..0000000
--- a/verilog/dv/mprj_stimulus/Makefile
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = mprj_stimulus
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
-	$(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
-	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
-	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
deleted file mode 100644
index e4d0a2d..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-
-// --------------------------------------------------------
-
-void main()
-{
-    // The upper GPIO pins are configured to be output
-    // and accessble to the management SoC.
-    // Used to flag the start/end of a test
-    // The lower GPIO pins are configured to be output
-    // and accessible to the user project.  They show
-    // the project count value, although this test is
-    // designed to read the project count through the
-    // logic analyzer probes.
-    // I/O 6 is configured for the UART Tx line
-    uint32_t testval;
-
-    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2
-
-    reg_mprj_datal = 0x00000000;
-    reg_mprj_datah = 0x00000000;
-
-    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
-    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
-    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Set UART clock to 64 kbaud (enable before I/O configuration)
-    reg_uart_clkdiv = 625;
-    reg_uart_enable = 1;
-
-    /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    /* TEST:  Recast channels 35 to 32 to allow input to user project	*/
-    /* This is done locally only:  Do not run reg_mprj_xfer!		*/
-    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Configure LA probes [31:0], [127:64] as inputs to the cpu
-    // Configure LA probes [63:32] as outputs from the cpu
-    reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-    reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-    reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
-
-    // Flag start of the test
-    reg_mprj_datal = 0xAB400000;
-
-    // Set Counter value to zero through LA probes [63:32]
-    reg_la1_data = 0x00000000;
-
-    // Configure LA probes from [63:32] as inputs to disable counter write
-    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
-
-    reg_mprj_datal = 0xAB410000;
-    reg_mprj_datah = 0x00000000;
-
-    // Test ability to force data on channel 37
-    // NOTE:  Only the low 6 bits of reg_mprj_datah are meaningful
-    reg_mprj_datah = 0xffffffca;
-    reg_mprj_datah = 0x00000000;
-    reg_mprj_datah = 0x0f0f0fc5;
-    reg_mprj_datah = 0x00000000;
-
-    // Test ability to read back data generated by the user project
-    // on the "monitored" outputs.  Read from the lower 16 bits and
-    // copy the value to the upper 16 bits.
-
-    testval = reg_mprj_datal;
-    reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
-
-    // Flag end of the test
-    reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
deleted file mode 100644
index 1409015..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype wire
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module mprj_stimulus_tb;
-    // Signals declaration
-    reg clock;
-    reg RSTB;
-    reg CSB;
-    reg power1, power2;
-    reg power3, power4;
-
-    wire HIGH;
-    wire LOW;
-    wire TRI;
-    assign HIGH = 1'b1;
-    assign LOW = 1'b0;
-    assign TRI = 1'bz;
-
-    wire gpio;
-    wire uart_tx;
-    wire [37:0] mprj_io;
-    wire [15:0] checkbits;
-    wire [3:0] status;
-
-    // Signals Assignment
-    assign checkbits  = mprj_io[31:16];
-    assign status = mprj_io[35:32];
-    assign uart_tx = mprj_io[6];
-    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-    always #12.5 clock <= (clock === 1'b0);
-
-    initial begin
-        clock = 0;
-    end
-
-    initial begin
-        $dumpfile("mprj_stimulus.vcd");
-        $dumpvars(0, mprj_stimulus_tb);
-
-        // Repeat cycles of 1000 clock edges as needed to complete testbench
-        repeat (150) begin
-            repeat (1000) @(posedge clock);
-        end
-        $display("%c[1;31m",27);
-        $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
-        $display("%c[0m",27);
-        $finish;
-    end
-
-    initial begin
-        wait(checkbits == 16'hAB40);
-        $display("Monitor: mprj_stimulus test started");
-        wait(status == 4'ha);
-        wait(status == 4'h5);
-	// Value 0009 reflects copying user-controlled outputs to memory and back
-	// to management-controlled outputs.
-        wait(checkbits == 16'h0009);
-        wait(checkbits == 16'hAB51);
-        $display("Monitor: mprj_stimulus test Passed");
-        #10000;
-        $finish;
-    end
-
-   // Reset Operation
-    initial begin
-        RSTB <= 1'b0;
-        CSB  <= 1'b1;       // Force CSB high
-        #2000;
-        RSTB <= 1'b1;       // Release reset
-        #170000;
-        CSB = 1'b0;         // CSB can be released
-    end
-
-    initial begin		// Power-up sequence
-        power1 <= 1'b0;
-        power2 <= 1'b0;
-        #200;
-        power1 <= 1'b1;
-        #200;
-        power2 <= 1'b1;
-    end
-
-    wire flash_csb;
-    wire flash_clk;
-    wire flash_io0;
-    wire flash_io1;
-
-    wire VDD3V3 = power1;
-    wire VDD1V8 = power2;
-    wire VSS = 1'b0;
-
-    caravel uut (
-        .vddio	  (VDD3V3),
-        .vssio	  (VSS),
-        .vdda	  (VDD3V3),
-        .vssa	  (VSS),
-        .vccd	  (VDD1V8),
-        .vssd	  (VSS),
-        .vdda1    (VDD3V3),
-        .vdda2    (VDD3V3),
-        .vssa1	  (VSS),
-        .vssa2	  (VSS),
-        .vccd1	  (VDD1V8),
-        .vccd2	  (VDD1V8),
-        .vssd1	  (VSS),
-        .vssd2	  (VSS),
-        .clock	  (clock),
-        .gpio     (gpio),
-        .mprj_io  (mprj_io),
-        .flash_csb(flash_csb),
-        .flash_clk(flash_clk),
-        .flash_io0(flash_io0),
-        .flash_io1(flash_io1),
-        .resetb	  (RSTB)
-    );
-
-
-    spiflash #(
-        .FILENAME("mprj_stimulus.hex")
-    ) spiflash (
-        .csb(flash_csb),
-        .clk(flash_clk),
-        .io0(flash_io0),
-        .io1(flash_io1),
-        .io2(),         // not used
-        .io3()          // not used
-    );
-
-    // Testbench UART
-    tbuart tbuart (
-        .ser_rx(uart_tx)
-    );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
deleted file mode 100644
index 425c115..0000000
--- a/verilog/dv/wb_port/wb_port.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
-	Wishbone Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Checks counter value through the wishbone port
-*/
-int i = 0; 
-int clk = 0;
-
-void main()
-{
-
-	/* 
-	IO Control Registers
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
-	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
-	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-	*/
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-     /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-
-    // Flag start of the test
-	reg_mprj_datal = 0xAB600000;
-
-    reg_mprj_slave = 0x00002710;
-    if (reg_mprj_slave == 0x2752) {
-        reg_mprj_datal = 0xAB610000;
-    } else {
-        reg_mprj_datal = 0xAB600000;
-    }
-}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
deleted file mode 100644
index b32f900..0000000
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
-module wb_port_tb;
-	reg clock;
-	reg RSTB;
-	reg CSB;
-	reg power1, power2;
-	reg power3, power4;
-
-	wire gpio;
-	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-	wire [15:0] checkbits;
-
-	assign checkbits = mprj_io[31:16];
-
-	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("wb_port.vcd");
-		$dumpvars(0, wb_port_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-	   wait(checkbits == 16'h AB60);
-		$display("Monitor: MPRJ-Logic WB Started");
-		wait(checkbits == 16'h AB61);
-		`ifdef GL
-	    	$display("Monitor: Mega-Project WB (GL) Passed");
-		`else
-		    $display("Monitor: Mega-Project WB (RTL) Passed");
-		`endif
-	    $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#170000;
-		CSB = 1'b0;		// CSB can be released
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
-		#100;
-		power1 <= 1'b1;
-		#100;
-		power2 <= 1'b1;
-		#100;
-		power3 <= 1'b1;
-		#100;
-		power4 <= 1'b1;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        .mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("wb_port.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
\ No newline at end of file
diff --git a/verilog/gl/clk_gate.v b/verilog/gl/clk_gate.v
deleted file mode 100644
index 6df5b7d..0000000
--- a/verilog/gl/clk_gate.v
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-Copyright (c) 2015, Steven F. Hoover
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    * Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * The name of Steven F. Hoover
-      may not be used to endorse or promote products derived from this software
-      without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-`include "sp_verilog.vh"
-
-
-// Clock gate module used by SandPiper default project.
-
-module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
-
-   assign gated_clk = free_clk;
-endmodule
diff --git a/verilog/gl/rvmyth.v b/verilog/gl/rvmyth.v
deleted file mode 100644
index 9e96890..0000000
--- a/verilog/gl/rvmyth.v
+++ /dev/null
@@ -1,269 +0,0 @@
-//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta
-`include "sp_verilog.vh" //_\SV
-   // Included URL: "https://raw.githubusercontent.com/shivanishah269/risc-v-core/master/FPGA_Implementation/riscv_shell_lib.tlv"// Included URL: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv"
-
-   module rvmyth (
-      output reg [9:0] OUT,
-      input CLK,
-      input reset,
-      
-      output [7:0] imem_addr,
-      input [31:0] imem_data
-   );
-
-   wire clk = CLK;
-   
-`include "rvmyth_gen.v"
-generate //_\TLV
-   //_|cpu
-      //_@0
-         assign CPU_reset_a0 = reset;
-      
-      //Fetch
-         // Next PC
-         assign CPU_pc_a0[31:0] = (CPU_reset_a1) ? 32'd0 : 
-                     (CPU_valid_taken_br_a3) ? CPU_br_tgt_pc_a3 : 
-                     (CPU_valid_load_a3) ? CPU_inc_pc_a3 : 
-                     (CPU_valid_jump_a3 && CPU_is_jal_a3) ? CPU_br_tgt_pc_a3 :
-                     (CPU_valid_jump_a3 && CPU_is_jalr_a3) ? CPU_jalr_tgt_pc_a3 : CPU_inc_pc_a1;
-         
-      //_@1
-         assign imem_addr = CPU_pc_a0[9:2];
-         assign CPU_instr_a1[31:0] = imem_data;
-         assign CPU_inc_pc_a1[31:0] = CPU_pc_a1 + 32'd4;
-                   
-      // Decode   
-         assign CPU_is_i_instr_a1 = CPU_instr_a1[6:2] == 5'b00000 ||
-                     CPU_instr_a1[6:2] == 5'b00001 ||
-                     CPU_instr_a1[6:2] == 5'b00100 ||
-                     CPU_instr_a1[6:2] == 5'b00110 ||
-                     CPU_instr_a1[6:2] == 5'b11001;
-         assign CPU_is_r_instr_a1 = CPU_instr_a1[6:2] == 5'b01011 ||
-                     CPU_instr_a1[6:2] == 5'b10100 ||
-                     CPU_instr_a1[6:2] == 5'b01100 ||
-                     CPU_instr_a1[6:2] == 5'b01101;                       
-         assign CPU_is_b_instr_a1 = CPU_instr_a1[6:2] == 5'b11000;
-         assign CPU_is_u_instr_a1 = CPU_instr_a1[6:2] == 5'b00101 ||
-                     CPU_instr_a1[6:2] == 5'b01101;
-         assign CPU_is_s_instr_a1 = CPU_instr_a1[6:2] == 5'b01000 ||
-                     CPU_instr_a1[6:2] == 5'b01001;
-         assign CPU_is_j_instr_a1 = CPU_instr_a1[6:2] == 5'b11011;
-         
-         assign CPU_imm_a1[31:0] = CPU_is_i_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:20] } :
-                     CPU_is_s_instr_a1 ? { {21{CPU_instr_a1[31]}} , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , CPU_instr_a1[7] } :
-                     CPU_is_b_instr_a1 ? { {20{CPU_instr_a1[31]}} , CPU_instr_a1[7] , CPU_instr_a1[30:25] , CPU_instr_a1[11:8] , 1'b0} :
-                     CPU_is_u_instr_a1 ? { CPU_instr_a1[31:12] , 12'b0} : 
-                     CPU_is_j_instr_a1 ? { {12{CPU_instr_a1[31]}} , CPU_instr_a1[19:12] , CPU_instr_a1[20] , CPU_instr_a1[30:21] , 1'b0} : 32'b0;
-         
-         assign CPU_rs2_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1;
-         assign CPU_rs1_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1;
-         assign CPU_rd_valid_a1 = CPU_is_r_instr_a1 || CPU_is_i_instr_a1 || CPU_is_u_instr_a1 || CPU_is_j_instr_a1;
-         assign CPU_funct3_valid_a1 = CPU_is_r_instr_a1 || CPU_is_s_instr_a1 || CPU_is_b_instr_a1 || CPU_is_i_instr_a1;
-         assign CPU_funct7_valid_a1 = CPU_is_r_instr_a1;
-         
-         //_?$rs2_valid
-            assign CPU_rs2_a1[4:0] = CPU_instr_a1[24:20];
-         //_?$rs1_valid
-            assign CPU_rs1_a1[4:0] = CPU_instr_a1[19:15];
-         //_?$rd_valid
-            assign CPU_rd_a1[4:0] = CPU_instr_a1[11:7];
-         //_?$funct3_valid
-            assign CPU_funct3_a1[2:0] = CPU_instr_a1[14:12];
-         //_?$funct7_valid
-            assign CPU_funct7_a1[6:0] = CPU_instr_a1[31:25];
-               
-         assign CPU_opcode_a1[6:0] = CPU_instr_a1[6:0];
-         
-         assign CPU_dec_bits_a1[10:0] = {CPU_funct7_a1[5],CPU_funct3_a1,CPU_opcode_a1};
-         
-         // Branch Instruction
-         assign CPU_is_beq_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100011;
-         assign CPU_is_bne_a1 = CPU_dec_bits_a1[9:0] == 10'b001_1100011;
-         assign CPU_is_blt_a1 = CPU_dec_bits_a1[9:0] == 10'b100_1100011;
-         assign CPU_is_bge_a1 = CPU_dec_bits_a1[9:0] == 10'b101_1100011;
-         assign CPU_is_bltu_a1 = CPU_dec_bits_a1[9:0] == 10'b110_1100011;
-         assign CPU_is_bgeu_a1 = CPU_dec_bits_a1[9:0] == 10'b111_1100011;
-         
-         // Arithmetic Instruction
-         assign CPU_is_add_a1 = CPU_dec_bits_a1 == 11'b0_000_0110011;
-         assign CPU_is_addi_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0010011;
-         assign CPU_is_or_a1 = CPU_dec_bits_a1 == 11'b0_110_0110011;
-         assign CPU_is_ori_a1 = CPU_dec_bits_a1[9:0] == 10'b110_0010011;
-         assign CPU_is_xor_a1 = CPU_dec_bits_a1 == 11'b0_100_0110011;
-         assign CPU_is_xori_a1 = CPU_dec_bits_a1[9:0] == 10'b100_0010011;
-         assign CPU_is_and_a1 = CPU_dec_bits_a1 == 11'b0_111_0110011;
-         assign CPU_is_andi_a1 = CPU_dec_bits_a1[9:0] == 10'b111_0010011;
-         assign CPU_is_sub_a1 = CPU_dec_bits_a1 == 11'b1_000_0110011;
-         assign CPU_is_slti_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0010011;
-         assign CPU_is_sltiu_a1 = CPU_dec_bits_a1[9:0] == 10'b011_0010011;
-         assign CPU_is_slli_a1 = CPU_dec_bits_a1 == 11'b0_001_0010011;
-         assign CPU_is_srli_a1 = CPU_dec_bits_a1 == 11'b0_101_0010011;
-         assign CPU_is_srai_a1 = CPU_dec_bits_a1 == 11'b1_101_0010011;
-         assign CPU_is_sll_a1 = CPU_dec_bits_a1 == 11'b0_001_0110011;
-         assign CPU_is_slt_a1 = CPU_dec_bits_a1 == 11'b0_010_0110011;
-         assign CPU_is_sltu_a1 = CPU_dec_bits_a1 == 11'b0_011_0110011;
-         assign CPU_is_srl_a1 = CPU_dec_bits_a1 == 11'b0_101_0110011;
-         assign CPU_is_sra_a1 = CPU_dec_bits_a1 == 11'b1_101_0110011;
-         
-         // Load Instruction
-         assign CPU_is_load_a1 = CPU_dec_bits_a1[6:0] == 7'b0000011;
-         
-         // Store Instruction
-         assign CPU_is_sb_a1 = CPU_dec_bits_a1[9:0] == 10'b000_0100011;
-         assign CPU_is_sh_a1 = CPU_dec_bits_a1[9:0] == 10'b001_0100011;
-         assign CPU_is_sw_a1 = CPU_dec_bits_a1[9:0] == 10'b010_0100011;
-         
-         // Jump Instruction
-         assign CPU_is_lui_a1 = CPU_dec_bits_a1[6:0] == 7'b0110111;
-         assign CPU_is_auipc_a1 = CPU_dec_bits_a1[6:0] == 7'b0010111;
-         assign CPU_is_jal_a1 = CPU_dec_bits_a1[6:0] == 7'b1101111;
-         assign CPU_is_jalr_a1 = CPU_dec_bits_a1[9:0] == 10'b000_1100111;
-         
-         assign CPU_is_jump_a1 = CPU_is_jal_a1 || CPU_is_jalr_a1;
-         
-      //_@2   
-      // Register File Read
-         assign CPU_rf_rd_en1_a2 = CPU_rs1_valid_a2;
-         //_?$rf_rd_en1
-            assign CPU_rf_rd_index1_a2[4:0] = CPU_rs1_a2[4:0];
-         
-         assign CPU_rf_rd_en2_a2 = CPU_rs2_valid_a2;
-         //_?$rf_rd_en2
-            assign CPU_rf_rd_index2_a2[4:0] = CPU_rs2_a2[4:0];
-               
-      // Branch Target PC       
-         assign CPU_br_tgt_pc_a2[31:0] = CPU_pc_a2 + CPU_imm_a2;
-      
-      // Jump Target PC
-         assign CPU_jalr_tgt_pc_a2[31:0] = CPU_src1_value_a2 + CPU_imm_a2;
-         
-      // Input signals to ALU
-         assign CPU_src1_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs1_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data1_a2[31:0];
-         assign CPU_src2_value_a2[31:0] = ((CPU_rd_a3 == CPU_rs2_a2) && CPU_rf_wr_en_a3) ? CPU_result_a3 : CPU_rf_rd_data2_a2[31:0];
-         
-      //_@3   
-         
-      // ALU
-         assign CPU_sltu_result_a3 = CPU_src1_value_a3 < CPU_src2_value_a3 ;
-         assign CPU_sltiu_result_a3 = CPU_src1_value_a3 < CPU_imm_a3 ;
-         
-         assign CPU_result_a3[31:0] = CPU_is_addi_a3 ? CPU_src1_value_a3 + CPU_imm_a3 :
-                           CPU_is_add_a3 ? CPU_src1_value_a3 + CPU_src2_value_a3 : 
-                           CPU_is_or_a3 ? CPU_src1_value_a3 | CPU_src2_value_a3 : 
-                           CPU_is_ori_a3 ? CPU_src1_value_a3 | CPU_imm_a3 :
-                           CPU_is_xor_a3 ? CPU_src1_value_a3 ^ CPU_src2_value_a3 :
-                           CPU_is_xori_a3 ? CPU_src1_value_a3 ^ CPU_imm_a3 :
-                           CPU_is_and_a3 ? CPU_src1_value_a3 & CPU_src2_value_a3 :
-                           CPU_is_andi_a3 ? CPU_src1_value_a3 & CPU_imm_a3 :
-                           CPU_is_sub_a3 ? CPU_src1_value_a3 - CPU_src2_value_a3 :
-                           CPU_is_slti_a3 ? ((CPU_src1_value_a3[31] == CPU_imm_a3[31]) ? CPU_sltiu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) :
-                           CPU_is_sltiu_a3 ? CPU_sltiu_result_a3 :
-                           CPU_is_slli_a3 ? CPU_src1_value_a3 << CPU_imm_a3[5:0] :
-                           CPU_is_srli_a3 ? CPU_src1_value_a3 >> CPU_imm_a3[5:0] :
-                           CPU_is_srai_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_imm_a3[4:0]) :
-                           CPU_is_sll_a3 ? CPU_src1_value_a3 << CPU_src2_value_a3[4:0] :
-                           CPU_is_slt_a3 ? ((CPU_src1_value_a3[31] == CPU_src2_value_a3[31]) ? CPU_sltu_result_a3 : {31'b0,CPU_src1_value_a3[31]}) :
-                           CPU_is_sltu_a3 ? CPU_sltu_result_a3 :
-                           CPU_is_srl_a3 ? CPU_src1_value_a3 >> CPU_src2_value_a3[5:0] :
-                           CPU_is_sra_a3 ? ({{32{CPU_src1_value_a3[31]}}, CPU_src1_value_a3} >> CPU_src2_value_a3[4:0]) :
-                           CPU_is_lui_a3 ? ({CPU_imm_a3[31:12], 12'b0}) :
-                           CPU_is_auipc_a3 ? CPU_pc_a3 + CPU_imm_a3 :
-                           CPU_is_jal_a3 ? CPU_pc_a3 + 4 :
-                           CPU_is_jalr_a3 ? CPU_pc_a3 + 4 : 
-                           (CPU_is_load_a3 || CPU_is_s_instr_a3) ? CPU_src1_value_a3 + CPU_imm_a3 : 32'bx;
-                           
-      // Register File Write
-         assign CPU_rf_wr_en_a3 = (CPU_rd_valid_a3 && CPU_valid_a3 && CPU_rd_a3 != 5'b0) || CPU_valid_load_a5;
-         //_?$rf_wr_en
-            assign CPU_rf_wr_index_a3[4:0] = !CPU_valid_a3 ? CPU_rd_a5[4:0] : CPU_rd_a3[4:0];
-      
-         assign CPU_rf_wr_data_a3[31:0] = !CPU_valid_a3 ? CPU_ld_data_a5[31:0] : CPU_result_a3[31:0];
-      
-      // Branch
-         assign CPU_taken_br_a3 = CPU_is_beq_a3 ? (CPU_src1_value_a3 == CPU_src2_value_a3) :
-                     CPU_is_bne_a3 ? (CPU_src1_value_a3 != CPU_src2_value_a3) :
-                     CPU_is_blt_a3 ? ((CPU_src1_value_a3 < CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) :
-                     CPU_is_bge_a3 ? ((CPU_src1_value_a3 >= CPU_src2_value_a3) ^ (CPU_src1_value_a3[31] != CPU_src2_value_a3[31])) :
-                     CPU_is_bltu_a3 ? (CPU_src1_value_a3 < CPU_src2_value_a3) :
-                     CPU_is_bgeu_a3 ? (CPU_src1_value_a3 >= CPU_src2_value_a3) : 1'b0;
-                     
-         assign CPU_valid_taken_br_a3 = CPU_valid_a3 && CPU_taken_br_a3;
-         
-      // Load
-         assign CPU_valid_load_a3 = CPU_valid_a3 && CPU_is_load_a3;
-         assign CPU_valid_a3 = !(CPU_valid_taken_br_a4 || CPU_valid_taken_br_a5 || CPU_valid_load_a4 || CPU_valid_load_a5 || CPU_valid_jump_a4 || CPU_valid_jump_a5);
-      
-      // Jump
-         assign CPU_valid_jump_a3 = CPU_valid_a3 && CPU_is_jump_a3;
-                  
-      //_@4
-         assign CPU_dmem_rd_en_a4 = CPU_valid_load_a4;
-         assign CPU_dmem_wr_en_a4 = CPU_valid_a4 && CPU_is_s_instr_a4;
-         assign CPU_dmem_addr_a4[3:0] = CPU_result_a4[5:2];
-         assign CPU_dmem_wr_data_a4[31:0] = CPU_src2_value_a4[31:0];
-         
-      //_@5   
-         assign CPU_ld_data_a5[31:0] = CPU_dmem_rd_data_a5[31:0];
-         
-      // Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
-      //       be sure to avoid having unassigned signals (which you might be using for random inputs)
-      //       other than those specifically expected in the labs. You'll get strange errors for these.
-
-         `BOGUS_USE(CPU_is_beq_a5 CPU_is_bne_a5 CPU_is_blt_a5 CPU_is_bge_a5 CPU_is_bltu_a5 CPU_is_bgeu_a5)
-         `BOGUS_USE(CPU_is_sb_a5 CPU_is_sh_a5 CPU_is_sw_a5)
-   // Assert these to end simulation (before Makerchip cycle limit).
-   /*SV_plus*/
-      always @ (posedge CLK) begin
-         OUT = CPU_Xreg_value_a5[17];                
-      end
-   
-   // Macro instantiations for:
-   //  o instruction memory
-   //  o register file
-   //  o data memory
-   //  o CPU visualization
-   //_|cpu
-      // m4+imem(@1)    // Args: (read stage)
-      //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 31   // Instantiated from rvmyth.tlv, 226 as: m4+rf(@2, @3)
-         // Reg File
-         //_@3
-            for (xreg = 0; xreg <= 31; xreg=xreg+1) begin : L1_CPU_Xreg //_/xreg
-
-               // For $wr.
-               wire L1_wr_a3;
-
-               assign L1_wr_a3 = CPU_rf_wr_en_a3 && (CPU_rf_wr_index_a3 != 5'b0) && (CPU_rf_wr_index_a3 == xreg);
-               assign CPU_Xreg_value_a3[xreg][31:0] = CPU_reset_a3 ?   xreg           :
-                              L1_wr_a3        ?   CPU_rf_wr_data_a3 :
-                                             CPU_Xreg_value_a4[xreg][31:0];
-            end
-         //_@2
-            //_?$rf_rd_en1
-               assign CPU_rf_rd_data1_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index1_a2];
-            //_?$rf_rd_en2
-               assign CPU_rf_rd_data2_a2[31:0] = CPU_Xreg_value_a4[CPU_rf_rd_index2_a2];
-            `BOGUS_USE(CPU_rf_rd_data1_a2 CPU_rf_rd_data2_a2) 
-      //_\end_source  // Args: (read stage, write stage) - if equal, no register bypass is required
-      //_\source /raw.githubusercontent.com/shivanishah269/riscvcore/master/FPGAImplementation/riscvshelllib.tlv 48   // Instantiated from rvmyth.tlv, 227 as: m4+dmem(@4)
-         // Data Memory
-         //_@4
-            for (dmem = 0; dmem <= 15; dmem=dmem+1) begin : L1_CPU_Dmem //_/dmem
-
-               // For $wr.
-               wire L1_wr_a4;
-
-               assign L1_wr_a4 = CPU_dmem_wr_en_a4 && (CPU_dmem_addr_a4 == dmem);
-               assign CPU_Dmem_value_a4[dmem][31:0] = CPU_reset_a4 ?   dmem :
-                              L1_wr_a4        ?   CPU_dmem_wr_data_a4 :
-                                             CPU_Dmem_value_a5[dmem][31:0];
-                                        
-            end
-            //_?$dmem_rd_en
-               assign CPU_dmem_rd_data_a4[31:0] = CPU_Dmem_value_a5[CPU_dmem_addr_a4];
-            //`BOGUS_USE($dmem_rd_data)
-      //_\end_source    // Args: (read/write stage)
-endgenerate
-
-//_\SV
-   
-   endmodule
diff --git a/verilog/gl/sram_32_256_sky130A.v b/verilog/gl/sram_32_256_sky130A.v
deleted file mode 100644
index d45d17e..0000000
--- a/verilog/gl/sram_32_256_sky130A.v
+++ /dev/null
@@ -1,72 +0,0 @@
-// OpenRAM SRAM model
-// Words: 256
-// Word size: 32
-
-module sram_32_256_sky130A(
-`ifdef USE_POWER_PINS
-    vccd1,
-    vssd1,
-`endif
-// Port 0: RW
-    clk0,csb0,web0,addr0,din0,dout0
-  );
-
-  parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 8 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  // FIXME: This delay is arbitrary.
-  parameter DELAY = 3 ;
-  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
-  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
-
-`ifdef USE_POWER_PINS
-    inout vccd1;
-    inout vssd1;
-`endif
-  input  clk0; // clock
-  input   csb0; // active low chip select
-  input  web0; // active low write control
-  input [ADDR_WIDTH-1:0]  addr0;
-  input [DATA_WIDTH-1:0]  din0;
-  output [DATA_WIDTH-1:0] dout0;
-
-  reg  csb0_reg;
-  reg  web0_reg;
-  reg [ADDR_WIDTH-1:0]  addr0_reg;
-  reg [DATA_WIDTH-1:0]  din0_reg;
-  reg [DATA_WIDTH-1:0]  dout0;
-
-  // All inputs are registers
-  always @(posedge clk0)
-  begin
-    csb0_reg = csb0;
-    web0_reg = web0;
-    addr0_reg = addr0;
-    din0_reg = din0;
-    #(T_HOLD) dout0 = 32'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
-      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
-    if ( !csb0_reg && !web0_reg && VERBOSE )
-      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
-  end
-
-reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
-
-  // Memory Write Block Port 0
-  // Write Operation : When web0 = 0, csb0 = 0
-  always @ (negedge clk0)
-  begin : MEM_WRITE0
-    if ( !csb0_reg && !web0_reg ) begin
-        mem[addr0_reg][31:0] = din0_reg[31:0];
-    end
-  end
-
-  // Memory Read Block Port 0
-  // Read Operation : When web0 = 1, csb0 = 0
-  always @ (negedge clk0)
-  begin : MEM_READ0
-    if (!csb0_reg && web0_reg)
-       dout0 <= #(DELAY) mem[addr0_reg];
-  end
-
-endmodule
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 427a612..32231cf 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -94,9 +94,8 @@
  wire \mem_addr[6] ;
  wire \mem_addr[7] ;
  wire mem_wr;
- wire zero_;
 
- sram_32_256_sky130A mem (.csb0(zero_),
+ sram_32_256_sky130A mem (.csb0(la_data_in[40]),
     .web0(mem_wr),
     .clk0(wb_clk_i),
     .vccd1(vccd1),
@@ -109,38 +108,38 @@
     \mem_addr[2] ,
     \mem_addr[1] ,
     \mem_addr[0] }),
-    .din0({wbs_dat_i[31],
-    wbs_dat_i[30],
-    wbs_dat_i[29],
-    wbs_dat_i[28],
-    wbs_dat_i[27],
-    wbs_dat_i[26],
-    wbs_dat_i[25],
-    wbs_dat_i[24],
-    wbs_dat_i[23],
-    wbs_dat_i[22],
-    wbs_dat_i[21],
-    wbs_dat_i[20],
-    wbs_dat_i[19],
-    wbs_dat_i[18],
-    wbs_dat_i[17],
-    wbs_dat_i[16],
-    wbs_dat_i[15],
-    wbs_dat_i[14],
-    wbs_dat_i[13],
-    wbs_dat_i[12],
-    wbs_dat_i[11],
-    wbs_dat_i[10],
-    wbs_dat_i[9],
-    wbs_dat_i[8],
-    wbs_dat_i[7],
-    wbs_dat_i[6],
-    wbs_dat_i[5],
-    wbs_dat_i[4],
-    wbs_dat_i[3],
-    wbs_dat_i[2],
-    wbs_dat_i[1],
-    wbs_dat_i[0]}),
+    .din0({la_data_in[31],
+    la_data_in[30],
+    la_data_in[29],
+    la_data_in[28],
+    la_data_in[27],
+    la_data_in[26],
+    la_data_in[25],
+    la_data_in[24],
+    la_data_in[23],
+    la_data_in[22],
+    la_data_in[21],
+    la_data_in[20],
+    la_data_in[19],
+    la_data_in[18],
+    la_data_in[17],
+    la_data_in[16],
+    la_data_in[15],
+    la_data_in[14],
+    la_data_in[13],
+    la_data_in[12],
+    la_data_in[11],
+    la_data_in[10],
+    la_data_in[9],
+    la_data_in[8],
+    la_data_in[7],
+    la_data_in[6],
+    la_data_in[5],
+    la_data_in[4],
+    la_data_in[3],
+    la_data_in[2],
+    la_data_in[1],
+    la_data_in[0]}),
     .dout0({\imem_data[31] ,
     \imem_data[30] ,
     \imem_data[29] ,
@@ -174,21 +173,21 @@
     \imem_data[1] ,
     \imem_data[0] }));
  user_proj_example mprj (.CLK(wb_clk_i),
-    .init_en(wbs_sel_i[0]),
+    .init_en(la_data_in[36]),
     .mem_wr(mem_wr),
-    .reset(wb_rst_i),
+    .reset(la_data_in[32]),
     .vccd1(vccd1),
     .vssd1(vssd1),
-    .OUT({wbs_dat_o[9],
-    wbs_dat_o[8],
-    wbs_dat_o[7],
-    wbs_dat_o[6],
-    wbs_dat_o[5],
-    wbs_dat_o[4],
-    wbs_dat_o[3],
-    wbs_dat_o[2],
-    wbs_dat_o[1],
-    wbs_dat_o[0]}),
+    .OUT({la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64]}),
     .imem_data({\imem_data[31] ,
     \imem_data[30] ,
     \imem_data[29] ,
@@ -221,14 +220,14 @@
     \imem_data[2] ,
     \imem_data[1] ,
     \imem_data[0] }),
-    .init_addr({wbs_adr_i[7],
-    wbs_adr_i[6],
-    wbs_adr_i[5],
-    wbs_adr_i[4],
-    wbs_adr_i[3],
-    wbs_adr_i[2],
-    wbs_adr_i[1],
-    wbs_adr_i[0]}),
+    .init_addr({la_data_in[51],
+    la_data_in[50],
+    la_data_in[49],
+    la_data_in[48],
+    la_data_in[47],
+    la_data_in[46],
+    la_data_in[45],
+    la_data_in[44]}),
     .mem_addr({\mem_addr[7] ,
     \mem_addr[6] ,
     \mem_addr[5] ,
diff --git a/verilog/include/rvmyth_gen.v b/verilog/rtl/include/rvmyth_gen.v
similarity index 100%
rename from verilog/include/rvmyth_gen.v
rename to verilog/rtl/include/rvmyth_gen.v
diff --git a/verilog/include/sandpiper.vh b/verilog/rtl/include/sandpiper.vh
similarity index 100%
rename from verilog/include/sandpiper.vh
rename to verilog/rtl/include/sandpiper.vh
diff --git a/verilog/include/sandpiper_gen.vh b/verilog/rtl/include/sandpiper_gen.vh
similarity index 100%
rename from verilog/include/sandpiper_gen.vh
rename to verilog/rtl/include/sandpiper_gen.vh
diff --git a/verilog/include/sp_default.vh b/verilog/rtl/include/sp_default.vh
similarity index 100%
rename from verilog/include/sp_default.vh
rename to verilog/rtl/include/sp_default.vh
diff --git a/verilog/include/sp_verilog.vh b/verilog/rtl/include/sp_verilog.vh
similarity index 100%
rename from verilog/include/sp_verilog.vh
rename to verilog/rtl/include/sp_verilog.vh
diff --git a/verilog/rtl/sram_32_256_sky130A.v b/verilog/rtl/sram_32_256_sky130A.v
index d45d17e..0699ff6 100644
--- a/verilog/rtl/sram_32_256_sky130A.v
+++ b/verilog/rtl/sram_32_256_sky130A.v
@@ -16,7 +16,7 @@
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
   parameter DELAY = 3 ;
-  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter VERBOSE = 0 ; //Set to 0 to only display warnings
   parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
 
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..ea72bbe 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -22,7 +22,11 @@
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
     `include "gl/user_proj_example.v"
+    `include "sram_32_256_sky130A.v"
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
+    `include "sram_32_256_sky130A.v"
+    `include "rvmyth.v"
+    `include "clk_gate.v"
 `endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index c08f62d..f4e42e9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -77,6 +77,8 @@
 /*--------------------------------------*/
 /* User project is instantiated  here   */
 /*--------------------------------------*/
+    wire global_clk = wb_clk_i;
+
     wire        mem_wr;
     wire [7:0]  mem_addr;
     
@@ -87,14 +89,14 @@
         .vccd1(vccd1),	// User area 1 1.8V supply
         .vssd1(vssd1),	// User area 1 digital ground
 `endif
-        .OUT(wbs_dat_o[9:0]),
-        .CLK(wb_clk_i),
-        .reset(wb_rst_i),
+        .OUT(la_data_out[73:64]),
+        .CLK(global_clk),
+        .reset(la_data_in[32]),
 
         .mem_wr(mem_wr),
         .mem_addr(mem_addr),
-        .init_en(wbs_sel_i[0]),
-        .init_addr(wbs_adr_i[7:0]),
+        .init_en(la_data_in[36]),
+        .init_addr(la_data_in[51:44]),
         .imem_data(imem_data)
     );
 
@@ -103,11 +105,11 @@
         .vccd1(vccd1),	// User area 1 1.8V supply
         .vssd1(vssd1),	// User area 1 digital ground
 `endif
-        .clk0(wb_clk_i),
-        .csb0(1'b0),
+        .clk0(global_clk),
+        .csb0(la_data_in[40]),
         .web0(mem_wr),
         .addr0(mem_addr),
-        .din0(wbs_dat_i),
+        .din0(la_data_in[31:0]),
         .dout0(imem_data)
     );