| /root/vsdbabysoc/Makefile |
| /root/vsdbabysoc/docs/environment.yml |
| /root/vsdbabysoc/docs/Makefile |
| /root/vsdbabysoc/docs/source/index.rst |
| /root/vsdbabysoc/docs/source/conf.py |
| /root/vsdbabysoc/verilog/dv/Makefile |
| /root/vsdbabysoc/verilog/dv/io_ports/Makefile |
| /root/vsdbabysoc/verilog/dv/io_ports/io_ports_tb.v |
| /root/vsdbabysoc/verilog/dv/io_ports/io_ports.c |
| /root/vsdbabysoc/verilog/rtl/avsddac.v |
| /root/vsdbabysoc/verilog/rtl/rvmyth.v |
| /root/vsdbabysoc/verilog/rtl/uprj_netlists.v |
| /root/vsdbabysoc/verilog/rtl/user_proj_example.v |
| /root/vsdbabysoc/verilog/rtl/user_project_wrapper.v |
| /root/vsdbabysoc/verilog/rtl/clk_gate.v |
| /root/vsdbabysoc/verilog/rtl/avsdpll.v |
| /root/vsdbabysoc/verilog/rtl/include/rvmyth_gen.v |
| /root/vsdbabysoc/verilog/rtl/include/sp_default.vh |
| /root/vsdbabysoc/verilog/rtl/include/sp_verilog.vh |
| /root/vsdbabysoc/verilog/rtl/include/sandpiper.vh |
| /root/vsdbabysoc/verilog/rtl/include/sandpiper_gen.vh |
| /root/vsdbabysoc/openlane/Makefile |
| /root/vsdbabysoc/openlane/user_proj_example/config.json |
| /root/vsdbabysoc/openlane/user_proj_example/config.tcl |
| /root/vsdbabysoc/openlane/user_project_wrapper/config.json |
| /root/vsdbabysoc/openlane/user_project_wrapper/config.tcl |
