)]}' { "commit": "c89cfac0317e3cf6d10861ed55791e276f058401", "tree": "44c81553242237c4a665430cbedf10d63dc3581b", "parents": [ "9a624e3d5d5b522b023229bb4c1191a4a9b4df1d" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Fri Apr 23 15:16:09 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Fri Apr 23 15:16:09 2021 -0400" }, "message": "Update to coincide with the most recent commit to the caravel\nproject. Added C code to control the input enable lines for\ninputs coming from the user project. Since the example code assumes\none-way traffic, the output enable is just the inverse of the input\nenable.\n", "tree_diff": [ { "type": "modify", "old_id": "b77c8d529e8524c5453f6c4e10ab60ac50b7ae4b", "old_mode": 33188, "old_path": "verilog/dv/la_test1/la_test1.c", "new_id": "220bdfe3e258c752feb43b388a87c37771a5ddd5", "new_mode": 33188, "new_path": "verilog/dv/la_test1/la_test1.c" }, { "type": "modify", "old_id": "1b8a3837fee8fb3d0cc51a3c33ea7b231425c034", "old_mode": 33188, "old_path": "verilog/dv/la_test2/la_test2.c", "new_id": "f9a293c71025bbc7cbb26da9c72fe491bcf46de5", "new_mode": 33188, "new_path": "verilog/dv/la_test2/la_test2.c" }, { "type": "modify", "old_id": "2fae0f1343ce15256d607d10e9a7c33d4f01eef0", "old_mode": 33188, "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c", "new_id": "e4d0a2db6978cc43067e60cc415bf677eba9f84a", "new_mode": 33188, "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c" }, { "type": "modify", "old_id": "46d778321900cd3fdb5b3e260e2aadd0f8b3bc83", "old_mode": 33188, "old_path": "verilog/dv/wb_port/wb_port.c", "new_id": "6c8129d131a983e8a78cfcf5dde8d129786d9a9e", "new_mode": 33188, "new_path": "verilog/dv/wb_port/wb_port.c" }, { "type": "modify", "old_id": "b9495832244a528c97b0c674a178f17c12a091f0", "old_mode": 33188, "old_path": "verilog/rtl/user_proj_example.v", "new_id": "b33e0324fe1a30327fe4115c985100b60754d9eb", "new_mode": 33188, "new_path": "verilog/rtl/user_proj_example.v" }, { "type": "modify", "old_id": "17c25111b40caf9fa07516d8f536f84a568a2888", "old_mode": 33188, "old_path": "verilog/rtl/user_project_wrapper.v", "new_id": "2a3462baf975342c4ec340411bbcf7a2e8aa1354", "new_mode": 33188, "new_path": "verilog/rtl/user_project_wrapper.v" } ] }