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/root/vsdbabysoc/verilog/dv/Makefile
/root/vsdbabysoc/verilog/dv/io_ports/Makefile
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/root/vsdbabysoc/verilog/rtl/user_proj_example.v
/root/vsdbabysoc/verilog/rtl/user_project_wrapper.v
/root/vsdbabysoc/verilog/rtl/clk_gate.v
/root/vsdbabysoc/verilog/rtl/avsdpll.v
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/root/vsdbabysoc/openlane/Makefile
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/root/vsdbabysoc/openlane/user_proj_example/config.tcl
/root/vsdbabysoc/openlane/user_project_wrapper/config.json
/root/vsdbabysoc/openlane/user_project_wrapper/config.tcl