---
project:
  description: "VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH."
  foundry: "SkyWater"
  git_url: "https://github.com/manili/vsdbabysoc_mpw3.git"
  organization: "VLSI System Design"
  organization_url: "https://www.vlsisystemdesign.com"
  owner: "Mohammad A. Nili"
  process: "SKY130"
  project_name: "VSDBabySoC"
  project_id: "00000000"
  tags:
    - "MPW3"
    - "VSD"
    - "RVMYTH"
    - "AVSDPLL"
    - "AVSDDAC"
    - "VSDBabySoC"
  category: "Test Harness"
  top_level_netlist: "caravel/verilog/gl/caravel.v"
  user_level_netlist: "verilog/gl/user_project_wrapper.v"
  version: "1.00"
  cover_image: "docs/source/_static/vsdbabysoc_layout.png"