#BUS_SORT

#S
wb_clk_i
wb_rst_i
la_data_in
la_oenb
la_data_out
wbs_dat_o
clk
rst
reset_core
is_loading_memory_into_core
read_enable_to_Elpis
read_value_to_Elpis
is_ready_print_core0
req_out_core0
core0_data_print
data_out_to_core
is_ready_dataout_core0
read_interactive_req_core0
we
addr_in
wr_data
requested
reset_mem_req
rd_data_out
ready

#E
data_to_core_mem
addr_to_core_mem
we_to_sram 
csb0_to_sram
spare_wen0_to_sram
addr0_to_sram
din0_to_sram 
dout0_to_sram