diff --git a/signoff/custom_sram/final_summary_report.csv b/signoff/custom_sram/final_summary_report.csv
index 23210d3..714fe5b 100644
--- a/signoff/custom_sram/final_summary_report.csv
+++ b/signoff/custom_sram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/custom_sram,custom_sram,custom_sram,flow_completed,0h54m30s,-1,51945.555555555555,1.8,25972.777777777777,40.1,2320.63,46751,0,0,0,0,0,0,0,30,0,0,-1,2776445,528493,-84.33,-151.49,-1,0.0,-1,-1157368.12,-2053896.75,-1,0.0,-1,1453041291.0,0.42,37.73,35.68,2.14,0.92,-1,17938,33922,520,16504,0,0,0,33866,0,0,0,0,0,0,0,4,16426,16384,10,1086,25070,0,26156,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.46,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/custom_sram,custom_sram,custom_sram,flow_completed,0h54m31s,-1,51945.555555555555,1.8,25972.777777777777,40.1,2327.98,46751,0,0,0,0,0,0,0,30,0,0,-1,2776445,528493,-84.33,-151.49,-1,0.0,-1,-1157368.12,-2053896.75,-1,0.0,-1,1453041291.0,0.42,37.73,35.68,2.14,0.92,-1,17938,33922,520,16504,0,0,0,33866,0,0,0,0,0,0,0,4,16426,16384,10,1086,25070,0,26156,19.607843137254903,51,50,AREA 0,5,50,1,153.6,153.18,0.46,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/elpis/definitions.v b/verilog/rtl/elpis/definitions.v
index 601ff56..4803a28 100644
--- a/verilog/rtl/elpis/definitions.v
+++ b/verilog/rtl/elpis/definitions.v
@@ -90,7 +90,7 @@
 
 // Constants for memory
 `define MEMORY_DELAY_CYCLES	5
-`define MEMORY_SIZE		8192  		// 2^20 - 2^5 = 2^15.
+`define MEMORY_SIZE		512  		// 2^20 - 2^5 = 2^15.
 
 // Constants for cache
 `define CACHE_LINE_SIZE		128