diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 3d19a16..606a591 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,8 +1,4 @@
 #mprj 1175 1690 N
-# chip_controller 2400 1000 N      #200x200 -> 2500 900
 chip_controller 200 2300 N      #200x200 -> 2500 900
 custom_sram 1500 1800 N         #1200 1500 -> 2700 3300
-core0 1300 200 N                 # 1500 1500 --> 1700 1700
-# sram_wrapper 200 1800 N         #200 200 -> 2100 900
-# io_input_arbiter 1900 200 N     #75 75 --> 1975 275
-# io_output_arbiter 2100 200 N    #75 75 --> 2175 275
\ No newline at end of file
+core0 1300 200 N                 # 1500 1500 --> 1700 1700
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f8bb3a8..38989ab 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -186,94 +186,6 @@
 		.is_mem_req(is_mem_req)
 	);
 
-// 	sram_wrapper sram_wrapper(
-// `ifdef USE_POWER_PINS
-// 	    .vccd1(vccd1),	// User area 1 1.8V power
-// 	    .vssd1(vssd1),	// User area 1 digital ground
-// `endif
-// 		.clk(clk),
-// 		.reset(rst),
-// 		.we(core0_is_mem_we),
-// 		.addr_in(core0_to_mem_address),
-// 		.wr_data(core0_to_mem_data),
-// 		.requested(is_mem_req),
-// 		.reset_mem_req(core0_need_reset_mem_req),
-//     	.is_loading_memory_into_core(is_loading_memory_into_core),
-// 		.addr_to_core_mem(addr_to_core_mem),
-// 		.data_to_core_mem(data_to_core_mem),
-// 		.rd_data_out(read_data_from_mem),
-// 		.ready(is_mem_ready),
-// 	 	.we_to_sram(we_to_sram),
-//     	.csb0_to_sram(csb0_to_sram),
-//     	.spare_wen0_to_sram(spare_wen0_to_sram),
-//     	.addr0_to_sram(addr0_to_sram),
-//     	.din0_to_sram(din0_to_sram), 
-//     	.dout0_to_sram(dout0_to_sram)
-// 	);
-
-// 	io_input_arbiter io_input_arbiter(
-// // `ifdef USE_POWER_PINS
-// // 	    .vccd1(vccd1),	// User area 1 1.8V power
-// // 	    .vssd1(vssd1),	// User area 1 digital ground
-// // `endif
-// 		.clk(clk),
-// 		.reset(rst),
-// 		.req_core0(read_interactive_req_core0),
-// 		.read_value(read_value_to_Elpis),
-// 		.read_enable(read_enable_to_Elpis),
-// 		.is_ready_core0(is_ready_dataout_core0),
-// 		.data_out(data_out_to_core)
-// 	);
-
-// 	io_output_arbiter io_output_arbiter(
-// // `ifdef USE_POWER_PINS
-// // 	    .vccd1(vccd1),	// User area 1 1.8V power
-// // 	    .vssd1(vssd1),	// User area 1 digital ground
-// // `endif
-// 		.clk(clk),
-// 		.reset(rst),
-// 		.req_core0(req_out_core0),
-// 		.data_core0(core0_data_print),
-// 		.print_hex_enable(print_hex_enable),
-// 		.print_output(print_output),
-// 		.is_ready_core0(is_ready_print_core0)
-// 	);
-
-// user_proj_example mprj (
-// `ifdef USE_POWER_PINS
-// 	.vccd1(vccd1),	// User area 1 1.8V power
-// 	.vssd1(vssd1),	// User area 1 digital ground
-// `endif
-
-//     .wb_clk_i(wb_clk_i),
-//     .wb_rst_i(wb_rst_i),
-
-//     // MGMT SoC Wishbone Slave
-
-//     .wbs_cyc_i(wbs_cyc_i),
-//     .wbs_stb_i(wbs_stb_i),
-//     .wbs_we_i(wbs_we_i),
-//     .wbs_sel_i(wbs_sel_i),
-//     .wbs_adr_i(wbs_adr_i),
-//     .wbs_dat_i(wbs_dat_i),
-//     .wbs_ack_o(wbs_ack_o),
-//     .wbs_dat_o(wbs_dat_o),
-
-//     // Logic Analyzer
-
-//     .la_data_in(la_data_in),
-//     .la_data_out(la_data_out),
-//     .la_oenb (la_oenb),
-
-//     // IO Pads
-
-//     .io_in (io_in),
-//     .io_out(io_out),
-//     .io_oeb(io_oeb),
-
-//     // IRQ
-//     .irq(user_irq)
-// );
 
 endmodule	// user_project_wrapper
 
diff --git a/workflow.sh b/workflow.sh
index a67c49b..c35d03d 100755
--- a/workflow.sh
+++ b/workflow.sh
@@ -1,9 +1,6 @@
 #!/bin/bash
 
-make i_arbiter
-make o_arbiter
 make custom_sram
-make sram_wrapper
 make chip_controller
 make core 
 make user_project_wrapper
\ No newline at end of file