diff --git a/.github/workflows/caravel_example_ci.yml b/.github/workflows/caravel_example_ci.yml
index 8e72fb9..2999eac 100644
--- a/.github/workflows/caravel_example_ci.yml
+++ b/.github/workflows/caravel_example_ci.yml
@@ -70,8 +70,8 @@
          run:  docker pull efabless/dv_setup:latest
        
        - name: Run DV tests
-         # Run test number 0,1,2,3 in one job                               <test-ids>   <sim-mode>
-         run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3      RTL
+         # Run test number 0,1,2,3,4 in one job                            <test-ids>   <sim-mode>
+         run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4      RTL
 
   dv_gl:
     runs-on: ubuntu-latest
@@ -95,5 +95,5 @@
          run:  docker pull efabless/dv_setup:latest
        
        - name: Run DV tests
-         # Run test number 0,1,2,3 in one job                               <test-ids>   <sim-mode>
-         run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3      GL
+         # Run test number 0,1,2,3,4 in one job                             <test-ids>   <sim-mode>
+         run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4      GL
diff --git a/caravel b/caravel
index b93aeb1..df92502 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit b93aeb102b9c5f2674bc1fdcd82732b414438771
+Subproject commit df925026fa0020d67bc458e912665763a15a6afe
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
new file mode 100644
index 0000000..8c5f729
--- /dev/null
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -0,0 +1,77 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_PATH ?= ../../../caravel
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_stimulus
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
new file mode 100644
index 0000000..4b6d899
--- /dev/null
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -0,0 +1,133 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../../caravel/verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+    // The upper GPIO pins are configured to be output
+    // and accessble to the management SoC.
+    // Used to flad the start/end of a test
+    // The lower GPIO pins are configured to be output
+    // and accessible to the user project.  They show
+    // the project count value, although this test is
+    // designed to read the project count through the
+    // logic analyzer probes.
+    // I/O 6 is configured for the UART Tx line
+    uint32_t testval;
+
+    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2
+
+    reg_mprj_datal = 0x00000000;
+    reg_mprj_datah = 0x00000000;
+
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUT_MONITORED;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Set UART clock to 64 kbaud (enable before I/O configuration)
+    reg_uart_clkdiv = 625;
+    reg_uart_enable = 1;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    /* TEST:  Recast channels 37 to 34 to allow input to user project	*/
+    /* This is done locally only:  Do not run reg_mprj_xfer!		*/
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Configure LA probes [31:0], [127:64] as inputs to the cpu
+    // Configure LA probes [63:32] as outputs from the cpu
+    reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+    reg_la1_ena = 0x00000000;    // [63:32]
+    reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+    reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
+    // Flag start of the test
+    reg_mprj_datal = 0xAB400000;
+
+    // Set Counter value to zero through LA probes [63:32]
+    reg_la1_data = 0x00000000;
+
+    // Configure LA probes from [63:32] as inputs to disable counter write
+    reg_la1_ena  = 0xFFFFFFFF;
+
+    reg_mprj_datal = 0xAB410000;
+    reg_mprj_datah = 0x00000000;
+
+    // Test ability to force data on channel 37
+    // NOTE:  Only the low 6 bits of reg_mprj_datah are meaningful
+    reg_mprj_datah = 0xffffff28;
+    reg_mprj_datah = 0x00000000;
+    reg_mprj_datah = 0x0f0f0f14;
+    reg_mprj_datah = 0x00000000;
+
+    // Test ability to read back data generated by the user project
+    // on the "monitored" outputs.  Read from the lower 16 bits and
+    // copy the value to the upper 16 bits.
+
+    testval = reg_mprj_datal;
+    reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
+
+    // Flag end of the test
+    reg_mprj_datal = 0xAB510000;
+}
+
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
new file mode 100644
index 0000000..0aaca76
--- /dev/null
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -0,0 +1,157 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_stimulus_tb;
+    // Signals declaration
+    reg clock;
+    reg RSTB;
+    reg CSB;
+    reg power1, power2;
+    reg power3, power4;
+
+    wire HIGH;
+    wire LOW;
+    wire TRI;
+    assign HIGH = 1'b1;
+    assign LOW = 1'b0;
+    assign TRI = 1'bz;
+
+    wire gpio;
+    wire uart_tx;
+    wire [37:0] mprj_io;
+    wire [15:0] checkbits;
+    wire [3:0] status;
+
+    // Signals Assignment
+    assign checkbits  = mprj_io[31:16];
+    assign status = mprj_io[37:34];
+    assign uart_tx = mprj_io[6];
+    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+    always #12.5 clock <= (clock === 1'b0);
+
+    initial begin
+        clock = 0;
+    end
+
+    initial begin
+        $dumpfile("mprj_stimulus.vcd");
+        $dumpvars(0, mprj_stimulus_tb);
+
+        // Repeat cycles of 1000 clock edges as needed to complete testbench
+        repeat (150) begin
+            repeat (1000) @(posedge clock);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    initial begin
+        wait(checkbits == 16'hAB40);
+        $display("Monitor: mprj_stimulus test started");
+        wait(status == 4'ha);
+        wait(status == 4'h5);
+	// Value 0009 reflects copying user-controlled outputs to memory and back
+	// to management-controlled outputs.
+        wait(checkbits == 16'h0009);
+        wait(checkbits == 16'hAB51);
+        $display("Monitor: mprj_stimulus test Passed");
+        #10000;
+        $finish;
+    end
+
+   // Reset Operation
+    initial begin
+        RSTB <= 1'b0;
+        CSB  <= 1'b1;       // Force CSB high
+        #2000;
+        RSTB <= 1'b1;       // Release reset
+        #170000;
+        CSB = 1'b0;         // CSB can be released
+    end
+
+    initial begin		// Power-up sequence
+        power1 <= 1'b0;
+        power2 <= 1'b0;
+        #200;
+        power1 <= 1'b1;
+        #200;
+        power2 <= 1'b1;
+    end
+
+    wire flash_csb;
+    wire flash_clk;
+    wire flash_io0;
+    wire flash_io1;
+
+    wire VDD3V3 = power1;
+    wire VDD1V8 = power2;
+    wire VSS = 1'b0;
+
+    caravel uut (
+        .vddio	  (VDD3V3),
+        .vssio	  (VSS),
+        .vdda	  (VDD3V3),
+        .vssa	  (VSS),
+        .vccd	  (VDD1V8),
+        .vssd	  (VSS),
+        .vdda1    (VDD3V3),
+        .vdda2    (VDD3V3),
+        .vssa1	  (VSS),
+        .vssa2	  (VSS),
+        .vccd1	  (VDD1V8),
+        .vccd2	  (VDD1V8),
+        .vssd1	  (VSS),
+        .vssd2	  (VSS),
+        .clock	  (clock),
+        .gpio     (gpio),
+        .mprj_io  (mprj_io),
+        .flash_csb(flash_csb),
+        .flash_clk(flash_clk),
+        .flash_io0(flash_io0),
+        .flash_io1(flash_io1),
+        .resetb	  (RSTB)
+    );
+
+
+    spiflash #(
+        .FILENAME("mprj_stimulus.hex")
+    ) spiflash (
+        .csb(flash_csb),
+        .clk(flash_clk),
+        .io0(flash_io0),
+        .io1(flash_io1),
+        .io2(),         // not used
+        .io3()          // not used
+    );
+
+    // Testbench UART
+    tbuart tbuart (
+        .ser_rx(uart_tx)
+    );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3534e4f..450b220 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -1,6 +1,7 @@
 
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
+`define USE_POWER_PINS
 
 `ifdef GL
     // Assume default net type to be wire because GL netlists don't have the wire definitions