)]}'
{
  "commit": "ee54cee7d38c1a0aff6c626ada4bdd127da64964",
  "tree": "3d9c8cd9b59b133a3bda7f1fa6549b369d245e8e",
  "parents": [
    "04f926db1b3e56b065cf4fe85d5df7ef68d8cd50"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Sep 02 19:14:06 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Sep 02 19:14:06 2021 +0200"
  },
  "message": "Update Makefile to work with efabless style\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e3560d76a9127923cf0cdae78c822b7e2f77dff0",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/Makefile",
      "new_id": "5237a05a6ff7f5acfd0d9853ae8c6ea24f3736ac",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "14d6ee63eb43e7b6d1169656bbc4e87fd7d77b40",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "ba979f7a9ff6183fc0e0cbce245fa8ec9190fa78",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "46f127bf112fbcdd77693ab3e18f58d06d37d905",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "0435500a3e89bb3d2242890df799c4ed301c04e5",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "72818e32ad1560a2876efed5d9a81ecb5b7ace04",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "3a73b997f14ebde920620c2e20ff382b986a4c7d",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/Makefile"
    },
    {
      "type": "modify",
      "old_id": "27c97151b96780cee9c80ef2616e5fe51aed2678",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "1c784c6d7c5e2a9fb157d670649e53f2f80a033b",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    }
  ]
}
