| # High Speed Adder | |
| This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node. | |
| ## Specifications | |
| Inputs: in1, in2 each of 18 bits | |
| Mode for add/sub selection | |
| Output: Sum which is of 19 bits. | |
| ## Block Diagram | |
| ## EDA Tools and Environment | |
| ## Pre-Synthesis Simulation | |
| ## Post-Synthesis Simulation | |
| ## RTL to GDSII | |