diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
new file mode 100644
index 0000000..5237a05
--- /dev/null
+++ b/verilog/dv/io_ports/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK 
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = io_ports
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
new file mode 100644
index 0000000..0b23571
--- /dev/null
+++ b/verilog/dv/io_ports/io_ports.c
@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	IO Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+}
+
diff --git a/verilog/dv/io_ports/io_ports.hex b/verilog/dv/io_ports/io_ports.hex
new file mode 100644
index 0000000..0f184fa
--- /dev/null
+++ b/verilog/dv/io_ports/io_ports.hex
@@ -0,0 +1,39 @@
+@00000000
+93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 
+13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 
+13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 
+13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 
+13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 
+13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 
+13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 
+13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 1E 
+93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 
+11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 
+63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 
+01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 
+A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 
+23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 
+F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F 
+00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 
+93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 
+93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 
+23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC 
+FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 
+A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC 
+00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 
+F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE 
+98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE 
+22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 
+17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 
+C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 
+82 80 41 11 22 C6 00 08 B7 07 00 24 29 67 09 07 
+98 C3 B7 07 00 26 93 87 47 02 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 87 02 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 C7 02 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 07 03 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 47 03 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 87 03 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 C7 03 09 67 13 07 87 80 
+98 C3 B7 07 00 26 93 87 07 04 09 67 13 07 87 80 
+98 C3 B7 07 00 26 05 47 98 C3 01 00 B7 07 00 26 
+98 43 85 47 E3 0C F7 FE 01 00 32 44 41 01 82 80 
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
new file mode 100644
index 0000000..f7628bc
--- /dev/null
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module io_ports_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+	// assign mprj_io[3] = 1'b1;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("io_ports.vcd");
+		$dumpvars(0, io_ports_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+	    // Observe Output pins [7:0]
+	    wait(mprj_io_0 == 8'h01);
+	    wait(mprj_io_0 == 8'h02);
+	    wait(mprj_io_0 == 8'h03);
+    	    wait(mprj_io_0 == 8'h04);
+	    wait(mprj_io_0 == 8'h05);
+            wait(mprj_io_0 == 8'h06);
+	    wait(mprj_io_0 == 8'h07);
+            wait(mprj_io_0 == 8'h08);
+	    wait(mprj_io_0 == 8'h09);
+            wait(mprj_io_0 == 8'h0A);   
+	    wait(mprj_io_0 == 8'hFF);
+	    wait(mprj_io_0 == 8'h00);
+		
+		`ifdef GL
+	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+		`else
+		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+		`endif
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (USER_VDD3V3),
+		.vdda2    (USER_VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (USER_VDD1V8),
+		.vccd2	  (USER_VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("io_ports.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire