diff --git "a/Simulations/post_synthesis/Screenshot \050461\051.png" "b/Simulations/post_synthesis/Screenshot \050461\051.png"
new file mode 100644
index 0000000..ac52bc8
--- /dev/null
+++ "b/Simulations/post_synthesis/Screenshot \050461\051.png"
Binary files differ
diff --git a/Simulations/post_synthesis/a.out b/Simulations/post_synthesis/a.out
new file mode 100644
index 0000000..62b5b94
--- /dev/null
+++ b/Simulations/post_synthesis/a.out
@@ -0,0 +1,41012 @@
+#! c:/iverilog-x64/bin/vvp
+:ivl_version "10.1 (stable)" "(v10_1_1)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_000000000282f200 .scope module, "gls" "gls" 2 1;
+ .timescale 0 0;
+L_0000000004189028 .functor BUFT 1, C4<0000000>, C4<0>, C4<0>, C4<0>;
+v0000000003cc9910_0 .net *"_s3", 6 0, L_0000000004189028;  1 drivers
+L_0000000004189070 .functor BUFT 1, C4<0000000>, C4<0>, C4<0>, C4<0>;
+v0000000003cc7d90_0 .net *"_s8", 6 0, L_0000000004189070;  1 drivers
+v0000000003cc9af0_0 .var "mode", 0 0;
+v0000000003cc8ab0_0 .var "p", 17 0;
+v0000000003cc9b90_0 .var "q", 17 0;
+v0000000003cc9c30_0 .net "sum", 18 0, L_0000000003f93860;  1 drivers
+L_0000000003f92320 .concat [ 18 7 0 0], v0000000003cc8ab0_0, L_0000000004189028;
+L_0000000003f93fe0 .concat [ 18 7 0 0], v0000000003cc9b90_0, L_0000000004189070;
+L_0000000003f93860 .part L_0000000003f94440, 0, 19;
+S_00000000028e54a0 .scope module, "u1" "adder" 2 6, 3 3 0, S_000000000282f200;
+ .timescale 0 0;
+    .port_info 0 /INPUT 25 "p"
+    .port_info 1 /INPUT 25 "q"
+    .port_info 2 /INPUT 1 "mode"
+    .port_info 3 /OUTPUT 26 "sum"
+v0000000003c3cb10_0 .net "_0000_", 0 0, L_000000000413b0b0;  1 drivers
+v0000000003c3f090_0 .net "_0001_", 0 0, L_000000000413b820;  1 drivers
+v0000000003c3cf70_0 .net "_0002_", 0 0, L_000000000413a7f0;  1 drivers
+v0000000003c3e9b0_0 .net "_0003_", 0 0, L_0000000004139ec0;  1 drivers
+v0000000003c3ced0_0 .net "_0004_", 0 0, L_000000000413af60;  1 drivers
+v0000000003c3da10_0 .net "_0005_", 0 0, L_000000000413b510;  1 drivers
+v0000000003c3e730_0 .net "_0006_", 0 0, L_000000000413a470;  1 drivers
+v0000000003c3eaf0_0 .net "_0007_", 0 0, L_000000000413cee0;  1 drivers
+v0000000003c3cc50_0 .net "_0008_", 0 0, L_000000000413b900;  1 drivers
+v0000000003c3d6f0_0 .net "_0009_", 0 0, L_000000000413d260;  1 drivers
+v0000000003c3ccf0_0 .net "_0010_", 0 0, L_000000000413c7e0;  1 drivers
+v0000000003c3d510_0 .net "_0011_", 0 0, L_000000000413db20;  1 drivers
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+v0000000003c3e0f0_0 .net "_0013_", 0 0, L_000000000413e610;  1 drivers
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+v0000000003c3d8d0_0 .net "_0016_", 0 0, L_0000000004140bb0;  1 drivers
+v0000000003c3cd90_0 .net "_0017_", 0 0, L_000000000413f1e0;  1 drivers
+v0000000003c3d650_0 .net "_0018_", 0 0, L_00000000041400c0;  1 drivers
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+v0000000003c3eeb0_0 .net "_0020_", 0 0, L_000000000413fdb0;  1 drivers
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+v0000000003c3db50_0 .net "_0022_", 0 0, L_0000000004141400;  1 drivers
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+v0000000003cc5bd0_0 .net "_0479_", 0 0, L_000000000415a320;  1 drivers
+v0000000003cc8c90_0 .net "_0480_", 0 0, L_00000000041590c0;  1 drivers
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+v0000000003cca090_0 .net "_0484_", 0 0, L_0000000004159de0;  1 drivers
+v0000000003cc92d0_0 .net "_0485_", 0 0, L_0000000004159f30;  1 drivers
+v0000000003cc7f70_0 .net "_0486_", 0 0, L_0000000004159750;  1 drivers
+v0000000003cc81f0_0 .net "_0487_", 0 0, L_000000000415a0f0;  1 drivers
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+v0000000003cc86f0_0 .net "_0490_", 0 0, L_000000000415bb30;  1 drivers
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+v0000000003cc8bf0_0 .net "_0494_", 0 0, L_000000000415b970;  1 drivers
+v0000000003cc95f0_0 .net "_0495_", 0 0, L_000000000415b7b0;  1 drivers
+v0000000003cc88d0_0 .net "_0496_", 0 0, L_000000000415bc80;  1 drivers
+v0000000003cc7c50_0 .net "_0497_", 0 0, L_000000000415ae80;  1 drivers
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+v0000000003cc8010_0 .net "_0501_", 0 0, L_000000000415b270;  1 drivers
+v0000000003cc9870_0 .net "_0502_", 0 0, L_000000000415b2e0;  1 drivers
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+v0000000003cc8830_0 .net "_0505_", 0 0, L_000000000415c150;  1 drivers
+v0000000003cc8970_0 .net "mode", 0 0, v0000000003cc9af0_0;  1 drivers
+v0000000003cc8dd0_0 .net "p", 24 0, L_0000000003f92320;  1 drivers
+v0000000003cc80b0_0 .net "q", 24 0, L_0000000003f93fe0;  1 drivers
+v0000000003cc9730_0 .net "sum", 25 0, L_0000000003f94440;  1 drivers
+L_0000000003f8eea0 .part L_0000000003f92320, 24, 1;
+L_0000000003f8d1e0 .part L_0000000003f93fe0, 24, 1;
+L_0000000003f8d460 .part L_0000000003f93fe0, 24, 1;
+L_0000000003f8e400 .part L_0000000003f93fe0, 23, 1;
+L_0000000003f8e4a0 .part L_0000000003f92320, 23, 1;
+L_0000000003f8efe0 .part L_0000000003f92320, 23, 1;
+L_0000000003f8d320 .part L_0000000003f93fe0, 23, 1;
+L_0000000003f8de60 .part L_0000000003f93fe0, 23, 1;
+L_0000000003f8d640 .part L_0000000003f93fe0, 22, 1;
+L_0000000003f8d780 .part L_0000000003f92320, 22, 1;
+L_0000000003f8d820 .part L_0000000003f92320, 22, 1;
+L_0000000003f8d8c0 .part L_0000000003f93fe0, 22, 1;
+L_0000000003f8d960 .part L_0000000003f93fe0, 21, 1;
+L_0000000003f8daa0 .part L_0000000003f92320, 21, 1;
+L_0000000003f8dc80 .part L_0000000003f92320, 21, 1;
+L_0000000003f914c0 .part L_0000000003f93fe0, 21, 1;
+L_0000000003f91560 .part L_0000000003f93fe0, 21, 1;
+L_0000000003f90340 .part L_0000000003f93fe0, 20, 1;
+L_0000000003f8fe40 .part L_0000000003f92320, 20, 1;
+L_0000000003f90840 .part L_0000000003f92320, 20, 1;
+L_0000000003f90520 .part L_0000000003f93fe0, 20, 1;
+L_0000000003f91e20 .part L_0000000003f93fe0, 22, 1;
+L_0000000003f90020 .part L_0000000003f93fe0, 19, 1;
+L_0000000003f91ec0 .part L_0000000003f92320, 19, 1;
+L_0000000003f90160 .part L_0000000003f92320, 19, 1;
+L_0000000003f91a60 .part L_0000000003f93fe0, 19, 1;
+L_0000000003f90ca0 .part L_0000000003f93fe0, 19, 1;
+L_0000000003f92000 .part L_0000000003f93fe0, 18, 1;
+L_0000000003f920a0 .part L_0000000003f92320, 18, 1;
+L_0000000003f91ce0 .part L_0000000003f92320, 18, 1;
+L_0000000003f905c0 .part L_0000000003f93fe0, 18, 1;
+L_0000000003f917e0 .part L_0000000003f93fe0, 20, 1;
+L_0000000003f90980 .part L_0000000003f93fe0, 16, 1;
+L_0000000003f90d40 .part L_0000000003f92320, 16, 1;
+L_0000000003f90f20 .part L_0000000003f92320, 16, 1;
+L_0000000003f8fda0 .part L_0000000003f93fe0, 16, 1;
+L_0000000003f90480 .part L_0000000003f93fe0, 16, 1;
+L_0000000003f919c0 .part L_0000000003f93fe0, 15, 1;
+L_0000000003f90a20 .part L_0000000003f92320, 15, 1;
+L_0000000003f903e0 .part L_0000000003f92320, 15, 1;
+L_0000000003f91880 .part L_0000000003f93fe0, 15, 1;
+L_0000000003f90de0 .part L_0000000003f93fe0, 14, 1;
+L_0000000003f91f60 .part L_0000000003f92320, 14, 1;
+L_0000000003f90660 .part L_0000000003f92320, 14, 1;
+L_0000000003f91920 .part L_0000000003f93fe0, 14, 1;
+L_0000000003f8fd00 .part L_0000000003f93fe0, 15, 1;
+L_0000000003f91c40 .part L_0000000003f93fe0, 13, 1;
+L_0000000003f911a0 .part L_0000000003f92320, 13, 1;
+L_0000000003f90e80 .part L_0000000003f92320, 13, 1;
+L_0000000003f90700 .part L_0000000003f93fe0, 13, 1;
+L_0000000003f90200 .part L_0000000003f93fe0, 13, 1;
+L_0000000003f907a0 .part L_0000000003f93fe0, 12, 1;
+L_0000000003f8f940 .part L_0000000003f92320, 12, 1;
+L_0000000003f8f9e0 .part L_0000000003f92320, 12, 1;
+L_0000000003f8fbc0 .part L_0000000003f93fe0, 12, 1;
+L_0000000003f91d80 .part L_0000000003f93fe0, 14, 1;
+L_0000000003f908e0 .part L_0000000003f93fe0, 17, 1;
+L_0000000003f90ac0 .part L_0000000003f92320, 17, 1;
+L_0000000003f91240 .part L_0000000003f92320, 17, 1;
+L_0000000003f90b60 .part L_0000000003f93fe0, 17, 1;
+L_0000000003f8fa80 .part L_0000000003f93fe0, 17, 1;
+L_0000000003f90c00 .part L_0000000003f93fe0, 18, 1;
+L_0000000003f91600 .part L_0000000003f93fe0, 12, 1;
+L_0000000003f90fc0 .part L_0000000003f93fe0, 11, 1;
+L_0000000003f91060 .part L_0000000003f92320, 11, 1;
+L_0000000003f902a0 .part L_0000000003f92320, 11, 1;
+L_0000000003f8fc60 .part L_0000000003f93fe0, 11, 1;
+L_0000000003f91380 .part L_0000000003f93fe0, 10, 1;
+L_0000000003f91100 .part L_0000000003f92320, 10, 1;
+L_0000000003f912e0 .part L_0000000003f92320, 10, 1;
+L_0000000003f8fee0 .part L_0000000003f93fe0, 10, 1;
+L_0000000003f916a0 .part L_0000000003f93fe0, 11, 1;
+L_0000000003f8fb20 .part L_0000000003f93fe0, 9, 1;
+L_0000000003f91b00 .part L_0000000003f92320, 9, 1;
+L_0000000003f91ba0 .part L_0000000003f92320, 9, 1;
+L_0000000003f8ff80 .part L_0000000003f93fe0, 9, 1;
+L_0000000003f900c0 .part L_0000000003f93fe0, 9, 1;
+L_0000000003f91420 .part L_0000000003f93fe0, 8, 1;
+L_0000000003f91740 .part L_0000000003f92320, 8, 1;
+L_0000000003f92d20 .part L_0000000003f92320, 8, 1;
+L_0000000003f941c0 .part L_0000000003f93fe0, 8, 1;
+L_0000000003f94260 .part L_0000000003f93fe0, 10, 1;
+L_0000000003f92460 .part L_0000000003f93fe0, 8, 1;
+L_0000000003f93b80 .part L_0000000003f93fe0, 7, 1;
+L_0000000003f92500 .part L_0000000003f92320, 7, 1;
+L_0000000003f93220 .part L_0000000003f92320, 7, 1;
+L_0000000003f932c0 .part L_0000000003f93fe0, 7, 1;
+L_0000000003f92fa0 .part L_0000000003f93fe0, 6, 1;
+L_0000000003f93360 .part L_0000000003f92320, 6, 1;
+L_0000000003f928c0 .part L_0000000003f92320, 6, 1;
+L_0000000003f93400 .part L_0000000003f93fe0, 6, 1;
+L_0000000003f93c20 .part L_0000000003f93fe0, 7, 1;
+L_0000000003f935e0 .part L_0000000003f93fe0, 6, 1;
+L_0000000003f92140 .part L_0000000003f93fe0, 5, 1;
+L_0000000003f93cc0 .part L_0000000003f92320, 5, 1;
+L_0000000003f94620 .part L_0000000003f92320, 5, 1;
+L_0000000003f94080 .part L_0000000003f93fe0, 5, 1;
+L_0000000003f92820 .part L_0000000003f93fe0, 5, 1;
+L_0000000003f94300 .part L_0000000003f93fe0, 4, 1;
+L_0000000003f944e0 .part L_0000000003f92320, 4, 1;
+L_0000000003f939a0 .part L_0000000003f92320, 4, 1;
+L_0000000003f93180 .part L_0000000003f93fe0, 4, 1;
+L_0000000003f93040 .part L_0000000003f93fe0, 4, 1;
+L_0000000003f925a0 .part L_0000000003f93fe0, 3, 1;
+L_0000000003f94120 .part L_0000000003f92320, 3, 1;
+L_0000000003f923c0 .part L_0000000003f92320, 3, 1;
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+L_0000000003f92f00 .part L_0000000003f93fe0, 2, 1;
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+L_0000000003f92e60 .part L_0000000003f93fe0, 2, 1;
+L_0000000003f93d60 .part L_0000000003f93fe0, 3, 1;
+L_0000000003f921e0 .part L_0000000003f93fe0, 1, 1;
+L_0000000003f943a0 .part L_0000000003f92320, 1, 1;
+L_0000000003f92960 .part L_0000000003f92320, 24, 1;
+L_0000000003f93e00 .part L_0000000003f92320, 1, 1;
+L_0000000003f92a00 .part L_0000000003f93fe0, 1, 1;
+L_0000000003f934a0 .part L_0000000003f93fe0, 1, 1;
+L_0000000003f93540 .part L_0000000003f93fe0, 2, 1;
+L_0000000003f93ea0 .part L_0000000003f93fe0, 0, 1;
+L_0000000003f930e0 .part L_0000000003f92320, 0, 1;
+L_0000000003f93720 .part L_0000000003f92320, 0, 1;
+L_0000000003f92280 .part L_0000000003f93fe0, 0, 1;
+L_0000000003f93f40 .part L_0000000003f93fe0, 0, 1;
+L_0000000003f946c0 .part L_0000000003f94440, 25, 1;
+L_0000000003f92b40 .part L_0000000003f92320, 0, 1;
+L_0000000003f93680 .part L_0000000003f93fe0, 0, 1;
+L_0000000003f937c0 .part L_0000000003f94440, 0, 1;
+L_0000000003f92aa0 .part L_0000000003f94440, 0, 1;
+LS_0000000003f94440_0_0 .concat8 [ 1 1 1 1], L_000000000413b3c0, L_000000000415cd90, L_000000000415d340, L_000000000415cf50;
+LS_0000000003f94440_0_4 .concat8 [ 1 1 1 1], L_000000000415d880, L_000000000415d960, L_000000000415d9d0, L_000000000415df80;
+LS_0000000003f94440_0_8 .concat8 [ 1 1 1 1], L_000000000415c850, L_000000000415d500, L_000000000415c7e0, L_000000000415dff0;
+LS_0000000003f94440_0_12 .concat8 [ 1 1 1 1], L_000000000415dc00, L_000000000415cb60, L_000000000415d420, L_000000000415c930;
+LS_0000000003f94440_0_16 .concat8 [ 1 1 1 1], L_000000000415cbd0, L_000000000415d180, L_000000000415ce70, L_000000000415d1f0;
+LS_0000000003f94440_0_20 .concat8 [ 1 1 1 1], L_000000000415de30, L_000000000415d650, L_000000000415d6c0, L_000000000415caf0;
+LS_0000000003f94440_0_24 .concat8 [ 1 1 0 0], L_000000000415d7a0, L_000000000413a940;
+LS_0000000003f94440_1_0 .concat8 [ 4 4 4 4], LS_0000000003f94440_0_0, LS_0000000003f94440_0_4, LS_0000000003f94440_0_8, LS_0000000003f94440_0_12;
+LS_0000000003f94440_1_4 .concat8 [ 4 4 2 0], LS_0000000003f94440_0_16, LS_0000000003f94440_0_20, LS_0000000003f94440_0_24;
+L_0000000003f94440 .concat8 [ 16 10 0 0], LS_0000000003f94440_1_0, LS_0000000003f94440_1_4;
+S_00000000028e72a0 .scope module, "_0506_" "sky130_fd_sc_hd__buf_1" 3 514, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ab450_0 .net "A", 0 0, L_0000000003f8eea0;  1 drivers
+L_0000000003aa1690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aaeb0_0 .net8 "VGND", 0 0, L_0000000003aa1690;  1 drivers, strength-aware
+L_0000000003aa1850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a98d0_0 .net8 "VNB", 0 0, L_0000000003aa1850;  1 drivers, strength-aware
+L_0000000003aa18c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab810_0 .net8 "VPB", 0 0, L_0000000003aa18c0;  1 drivers, strength-aware
+L_0000000003aa1930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039a9150_0 .net8 "VPWR", 0 0, L_0000000003aa1930;  1 drivers, strength-aware
+v00000000039aaf50_0 .net "X", 0 0, L_0000000004126430;  alias, 1 drivers
+S_00000000028e6fa0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e72a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041263c0 .functor BUF 1, L_0000000003f8eea0, C4<0>, C4<0>, C4<0>;
+L_0000000004126430 .functor BUF 1, L_00000000041263c0, C4<0>, C4<0>, C4<0>;
+v00000000039a9bf0_0 .net "A", 0 0, L_0000000003f8eea0;  alias, 1 drivers
+L_0000000003aa1a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9330_0 .net8 "VGND", 0 0, L_0000000003aa1a10;  1 drivers, strength-aware
+L_0000000003aa1a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9470_0 .net8 "VNB", 0 0, L_0000000003aa1a80;  1 drivers, strength-aware
+L_0000000003aa1af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab6d0_0 .net8 "VPB", 0 0, L_0000000003aa1af0;  1 drivers, strength-aware
+L_0000000003aa1b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa230_0 .net8 "VPWR", 0 0, L_0000000003aa1b60;  1 drivers, strength-aware
+v00000000039ab3b0_0 .net "X", 0 0, L_0000000004126430;  alias, 1 drivers
+v00000000039a9510_0 .net "buf0_out_X", 0 0, L_00000000041263c0;  1 drivers
+S_00000000028e4a20 .scope module, "_0507_" "sky130_fd_sc_hd__buf_1" 3 518, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ab090_0 .net "A", 0 0, L_0000000004126430;  alias, 1 drivers
+L_0000000003aa3d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aa690_0 .net8 "VGND", 0 0, L_0000000003aa3d10;  1 drivers, strength-aware
+L_0000000003aa2ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9dd0_0 .net8 "VNB", 0 0, L_0000000003aa2ff0;  1 drivers, strength-aware
+L_0000000003aa3b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab130_0 .net8 "VPB", 0 0, L_0000000003aa3b50;  1 drivers, strength-aware
+L_0000000003aa37d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab270_0 .net8 "VPWR", 0 0, L_0000000003aa37d0;  1 drivers, strength-aware
+v00000000039aad70_0 .net "X", 0 0, L_0000000004125be0;  alias, 1 drivers
+S_00000000028e6520 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e4a20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041266d0 .functor BUF 1, L_0000000004126430, C4<0>, C4<0>, C4<0>;
+L_0000000004125be0 .functor BUF 1, L_00000000041266d0, C4<0>, C4<0>, C4<0>;
+v00000000039a9290_0 .net "A", 0 0, L_0000000004126430;  alias, 1 drivers
+L_0000000003aa3fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ab1d0_0 .net8 "VGND", 0 0, L_0000000003aa3fb0;  1 drivers, strength-aware
+L_0000000003aa38b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aaff0_0 .net8 "VNB", 0 0, L_0000000003aa38b0;  1 drivers, strength-aware
+L_0000000003aa31b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039a95b0_0 .net8 "VPB", 0 0, L_0000000003aa31b0;  1 drivers, strength-aware
+L_0000000003aa2c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa910_0 .net8 "VPWR", 0 0, L_0000000003aa2c70;  1 drivers, strength-aware
+v00000000039aacd0_0 .net "X", 0 0, L_0000000004125be0;  alias, 1 drivers
+v00000000039a91f0_0 .net "buf0_out_X", 0 0, L_00000000041266d0;  1 drivers
+S_00000000028e4ea0 .scope module, "_0508_" "sky130_fd_sc_hd__buf_1" 3 522, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ab770_0 .net "A", 0 0, L_0000000004125be0;  alias, 1 drivers
+L_0000000003aa2e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a96f0_0 .net8 "VGND", 0 0, L_0000000003aa2e30;  1 drivers, strength-aware
+L_0000000003aa3840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9790_0 .net8 "VNB", 0 0, L_0000000003aa3840;  1 drivers, strength-aware
+L_0000000003aa2dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa7d0_0 .net8 "VPB", 0 0, L_0000000003aa2dc0;  1 drivers, strength-aware
+L_0000000003aa2b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039a9c90_0 .net8 "VPWR", 0 0, L_0000000003aa2b20;  1 drivers, strength-aware
+v00000000039a9ab0_0 .net "X", 0 0, L_0000000004126510;  alias, 1 drivers
+S_00000000028e3520 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e4ea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004125710 .functor BUF 1, L_0000000004125be0, C4<0>, C4<0>, C4<0>;
+L_0000000004126510 .functor BUF 1, L_0000000004125710, C4<0>, C4<0>, C4<0>;
+v00000000039ab310_0 .net "A", 0 0, L_0000000004125be0;  alias, 1 drivers
+L_0000000003aa3bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9a10_0 .net8 "VGND", 0 0, L_0000000003aa3bc0;  1 drivers, strength-aware
+L_0000000003aa36f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ab4f0_0 .net8 "VNB", 0 0, L_0000000003aa36f0;  1 drivers, strength-aware
+L_0000000003aa2f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa730_0 .net8 "VPB", 0 0, L_0000000003aa2f10;  1 drivers, strength-aware
+L_0000000003aa3ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab590_0 .net8 "VPWR", 0 0, L_0000000003aa3ae0;  1 drivers, strength-aware
+v00000000039a9650_0 .net "X", 0 0, L_0000000004126510;  alias, 1 drivers
+v00000000039ab630_0 .net "buf0_out_X", 0 0, L_0000000004125710;  1 drivers
+S_00000000028e33a0 .scope module, "_0509_" "sky130_fd_sc_hd__buf_1" 3 526, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039aab90_0 .net "A", 0 0, L_0000000004126510;  alias, 1 drivers
+L_0000000003aa30d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aa190_0 .net8 "VGND", 0 0, L_0000000003aa30d0;  1 drivers, strength-aware
+L_0000000003aa2ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aa2d0_0 .net8 "VNB", 0 0, L_0000000003aa2ab0;  1 drivers, strength-aware
+L_0000000003aa2b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa370_0 .net8 "VPB", 0 0, L_0000000003aa2b90;  1 drivers, strength-aware
+L_0000000003aa29d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa410_0 .net8 "VPWR", 0 0, L_0000000003aa29d0;  1 drivers, strength-aware
+v00000000039aa4b0_0 .net "X", 0 0, L_00000000041258d0;  alias, 1 drivers
+S_00000000028e81a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e33a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126040 .functor BUF 1, L_0000000004126510, C4<0>, C4<0>, C4<0>;
+L_00000000041258d0 .functor BUF 1, L_0000000004126040, C4<0>, C4<0>, C4<0>;
+v00000000039a9e70_0 .net "A", 0 0, L_0000000004126510;  alias, 1 drivers
+L_0000000003aa25e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9830_0 .net8 "VGND", 0 0, L_0000000003aa25e0;  1 drivers, strength-aware
+L_0000000003aa3220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039a9970_0 .net8 "VNB", 0 0, L_0000000003aa3220;  1 drivers, strength-aware
+L_0000000003aa2ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039a9b50_0 .net8 "VPB", 0 0, L_0000000003aa2ea0;  1 drivers, strength-aware
+L_0000000003aa3680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039a9f10_0 .net8 "VPWR", 0 0, L_0000000003aa3680;  1 drivers, strength-aware
+v00000000039a9fb0_0 .net "X", 0 0, L_00000000041258d0;  alias, 1 drivers
+v00000000039aa0f0_0 .net "buf0_out_X", 0 0, L_0000000004126040;  1 drivers
+S_00000000028e8020 .scope module, "_0510_" "sky130_fd_sc_hd__buf_1" 3 530, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039abef0_0 .net "A", 0 0, L_00000000041258d0;  alias, 1 drivers
+L_0000000003aa2f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039add90_0 .net8 "VGND", 0 0, L_0000000003aa2f80;  1 drivers, strength-aware
+L_0000000003aa3a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ada70_0 .net8 "VNB", 0 0, L_0000000003aa3a70;  1 drivers, strength-aware
+L_0000000003aa2730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ad890_0 .net8 "VPB", 0 0, L_0000000003aa2730;  1 drivers, strength-aware
+L_0000000003aa3d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ac490_0 .net8 "VPWR", 0 0, L_0000000003aa3d80;  1 drivers, strength-aware
+v00000000039adcf0_0 .net "X", 0 0, L_0000000004126740;  alias, 1 drivers
+S_00000000028e39a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e8020;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041264a0 .functor BUF 1, L_00000000041258d0, C4<0>, C4<0>, C4<0>;
+L_0000000004126740 .functor BUF 1, L_00000000041264a0, C4<0>, C4<0>, C4<0>;
+v00000000039aa550_0 .net "A", 0 0, L_00000000041258d0;  alias, 1 drivers
+L_0000000003aa2490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aa5f0_0 .net8 "VGND", 0 0, L_0000000003aa2490;  1 drivers, strength-aware
+L_0000000003aa3140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aac30_0 .net8 "VNB", 0 0, L_0000000003aa3140;  1 drivers, strength-aware
+L_0000000003aa3920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa870_0 .net8 "VPB", 0 0, L_0000000003aa3920;  1 drivers, strength-aware
+L_0000000003aa2650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aa9b0_0 .net8 "VPWR", 0 0, L_0000000003aa2650;  1 drivers, strength-aware
+v00000000039aaa50_0 .net "X", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039abe50_0 .net "buf0_out_X", 0 0, L_00000000041264a0;  1 drivers
+S_00000000028e8aa0 .scope module, "_0511_" "sky130_fd_sc_hd__a2bb2o_2" 3 534, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039acc10_0 .net "A1_N", 0 0, L_0000000003f8d1e0;  1 drivers
+v00000000039ad4d0_0 .net "A2_N", 0 0, v0000000003cc9af0_0;  alias, 1 drivers
+v00000000039ac5d0_0 .net "B1", 0 0, L_0000000003f8d460;  1 drivers
+v00000000039ade30_0 .net "B2", 0 0, v0000000003cc9af0_0;  alias, 1 drivers
+L_0000000003aa3290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ad250_0 .net8 "VGND", 0 0, L_0000000003aa3290;  1 drivers, strength-aware
+L_0000000003aa3300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ac3f0_0 .net8 "VNB", 0 0, L_0000000003aa3300;  1 drivers, strength-aware
+L_0000000003aa3060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039abb30_0 .net8 "VPB", 0 0, L_0000000003aa3060;  1 drivers, strength-aware
+L_0000000003aa27a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039abdb0_0 .net8 "VPWR", 0 0, L_0000000003aa27a0;  1 drivers, strength-aware
+v00000000039ac350_0 .net "X", 0 0, L_0000000004125400;  alias, 1 drivers
+S_00000000028e36a0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_00000000028e8aa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004124d00 .functor AND 1, L_0000000003f8d460, v0000000003cc9af0_0, C4<1>, C4<1>;
+L_0000000004125e10 .functor NOR 1, L_0000000003f8d1e0, v0000000003cc9af0_0, C4<0>, C4<0>;
+L_0000000004125390 .functor OR 1, L_0000000004125e10, L_0000000004124d00, C4<0>, C4<0>;
+L_0000000004125400 .functor BUF 1, L_0000000004125390, C4<0>, C4<0>, C4<0>;
+v00000000039acd50_0 .net "A1_N", 0 0, L_0000000003f8d1e0;  alias, 1 drivers
+v00000000039adc50_0 .net "A2_N", 0 0, v0000000003cc9af0_0;  alias, 1 drivers
+v00000000039ae010_0 .net "B1", 0 0, L_0000000003f8d460;  alias, 1 drivers
+v00000000039ac2b0_0 .net "B2", 0 0, v0000000003cc9af0_0;  alias, 1 drivers
+L_0000000003aa3610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039adb10_0 .net8 "VGND", 0 0, L_0000000003aa3610;  1 drivers, strength-aware
+L_0000000003aa3370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ad750_0 .net8 "VNB", 0 0, L_0000000003aa3370;  1 drivers, strength-aware
+L_0000000003aa2810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ad2f0_0 .net8 "VPB", 0 0, L_0000000003aa2810;  1 drivers, strength-aware
+L_0000000003aa3760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ac670_0 .net8 "VPWR", 0 0, L_0000000003aa3760;  1 drivers, strength-aware
+v00000000039ad9d0_0 .net "X", 0 0, L_0000000004125400;  alias, 1 drivers
+v00000000039ad430_0 .net "and0_out", 0 0, L_0000000004124d00;  1 drivers
+v00000000039ac530_0 .net "nor0_out", 0 0, L_0000000004125e10;  1 drivers
+v00000000039ac710_0 .net "or0_out_X", 0 0, L_0000000004125390;  1 drivers
+S_00000000028e3820 .scope module, "_0512_" "sky130_fd_sc_hd__inv_2" 3 541, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ac850_0 .net "A", 0 0, L_0000000004125400;  alias, 1 drivers
+L_0000000003aa2a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ac170_0 .net8 "VGND", 0 0, L_0000000003aa2a40;  1 drivers, strength-aware
+L_0000000003aa33e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039acad0_0 .net8 "VNB", 0 0, L_0000000003aa33e0;  1 drivers, strength-aware
+L_0000000003aa3c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039adf70_0 .net8 "VPB", 0 0, L_0000000003aa3c30;  1 drivers, strength-aware
+L_0000000003aa26c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039abf90_0 .net8 "VPWR", 0 0, L_0000000003aa26c0;  1 drivers, strength-aware
+v00000000039adbb0_0 .net "Y", 0 0, L_0000000004125780;  alias, 1 drivers
+S_00000000028e8c20 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028e3820;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126580 .functor NOT 1, L_0000000004125400, C4<0>, C4<0>, C4<0>;
+L_0000000004125780 .functor BUF 1, L_0000000004126580, C4<0>, C4<0>, C4<0>;
+v00000000039ad570_0 .net "A", 0 0, L_0000000004125400;  alias, 1 drivers
+L_0000000003aa3450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039acb70_0 .net8 "VGND", 0 0, L_0000000003aa3450;  1 drivers, strength-aware
+L_0000000003aa3ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aded0_0 .net8 "VNB", 0 0, L_0000000003aa3ca0;  1 drivers, strength-aware
+L_0000000003aa2ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab9f0_0 .net8 "VPB", 0 0, L_0000000003aa2ce0;  1 drivers, strength-aware
+L_0000000003aa34c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ad7f0_0 .net8 "VPWR", 0 0, L_0000000003aa34c0;  1 drivers, strength-aware
+v00000000039ac7b0_0 .net "Y", 0 0, L_0000000004125780;  alias, 1 drivers
+v00000000039abc70_0 .net "not0_out_Y", 0 0, L_0000000004126580;  1 drivers
+S_00000000028e4d20 .scope module, "_0513_" "sky130_fd_sc_hd__buf_1" 3 545, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039acdf0_0 .net "A", 0 0, L_0000000004125780;  alias, 1 drivers
+L_0000000003aa2c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ac8f0_0 .net8 "VGND", 0 0, L_0000000003aa2c00;  1 drivers, strength-aware
+L_0000000003aa3530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ac990_0 .net8 "VNB", 0 0, L_0000000003aa3530;  1 drivers, strength-aware
+L_0000000003aa4020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ad390_0 .net8 "VPB", 0 0, L_0000000003aa4020;  1 drivers, strength-aware
+L_0000000003aa2880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ad930_0 .net8 "VPWR", 0 0, L_0000000003aa2880;  1 drivers, strength-aware
+v00000000039aca30_0 .net "X", 0 0, L_00000000041265f0;  alias, 1 drivers
+S_00000000028e42a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e4d20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041260b0 .functor BUF 1, L_0000000004125780, C4<0>, C4<0>, C4<0>;
+L_00000000041265f0 .functor BUF 1, L_00000000041260b0, C4<0>, C4<0>, C4<0>;
+v00000000039ac030_0 .net "A", 0 0, L_0000000004125780;  alias, 1 drivers
+L_0000000003aa2500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ae0b0_0 .net8 "VGND", 0 0, L_0000000003aa2500;  1 drivers, strength-aware
+L_0000000003aa3990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ac210_0 .net8 "VNB", 0 0, L_0000000003aa3990;  1 drivers, strength-aware
+L_0000000003aa35a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ab950_0 .net8 "VPB", 0 0, L_0000000003aa35a0;  1 drivers, strength-aware
+L_0000000003aa3df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039abbd0_0 .net8 "VPWR", 0 0, L_0000000003aa3df0;  1 drivers, strength-aware
+v00000000039ac0d0_0 .net "X", 0 0, L_00000000041265f0;  alias, 1 drivers
+v00000000039ad610_0 .net "buf0_out_X", 0 0, L_00000000041260b0;  1 drivers
+S_00000000028e8da0 .scope module, "_0514_" "sky130_fd_sc_hd__buf_1" 3 549, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ad070_0 .net "A", 0 0, L_00000000041265f0;  alias, 1 drivers
+L_0000000003aa3a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ad110_0 .net8 "VGND", 0 0, L_0000000003aa3a00;  1 drivers, strength-aware
+L_0000000003aa28f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ad1b0_0 .net8 "VNB", 0 0, L_0000000003aa28f0;  1 drivers, strength-aware
+L_0000000003aa2960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ae6f0_0 .net8 "VPB", 0 0, L_0000000003aa2960;  1 drivers, strength-aware
+L_0000000003aa3e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0590_0 .net8 "VPWR", 0 0, L_0000000003aa3e60;  1 drivers, strength-aware
+v00000000039b0270_0 .net "X", 0 0, L_0000000004126660;  alias, 1 drivers
+S_00000000028e57a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e8da0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041267b0 .functor BUF 1, L_00000000041265f0, C4<0>, C4<0>, C4<0>;
+L_0000000004126660 .functor BUF 1, L_00000000041267b0, C4<0>, C4<0>, C4<0>;
+v00000000039aba90_0 .net "A", 0 0, L_00000000041265f0;  alias, 1 drivers
+L_0000000003aa2d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039abd10_0 .net8 "VGND", 0 0, L_0000000003aa2d50;  1 drivers, strength-aware
+L_0000000003aa3ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039accb0_0 .net8 "VNB", 0 0, L_0000000003aa3ed0;  1 drivers, strength-aware
+L_0000000003aa3f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ace90_0 .net8 "VPB", 0 0, L_0000000003aa3f40;  1 drivers, strength-aware
+L_0000000003aa2570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039acf30_0 .net8 "VPWR", 0 0, L_0000000003aa2570;  1 drivers, strength-aware
+v00000000039ad6b0_0 .net "X", 0 0, L_0000000004126660;  alias, 1 drivers
+v00000000039acfd0_0 .net "buf0_out_X", 0 0, L_00000000041267b0;  1 drivers
+S_00000000028e5020 .scope module, "_0515_" "sky130_fd_sc_hd__buf_1" 3 553, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039afeb0_0 .net "A", 0 0, L_0000000004126660;  alias, 1 drivers
+L_0000000003aa4e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b04f0_0 .net8 "VGND", 0 0, L_0000000003aa4e90;  1 drivers, strength-aware
+L_0000000003aa4f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aee70_0 .net8 "VNB", 0 0, L_0000000003aa4f00;  1 drivers, strength-aware
+L_0000000003aa42c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0130_0 .net8 "VPB", 0 0, L_0000000003aa42c0;  1 drivers, strength-aware
+L_0000000003aa4aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039afc30_0 .net8 "VPWR", 0 0, L_0000000003aa4aa0;  1 drivers, strength-aware
+v00000000039afa50_0 .net "X", 0 0, L_0000000004125470;  alias, 1 drivers
+S_00000000028e3ca0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e5020;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041250f0 .functor BUF 1, L_0000000004126660, C4<0>, C4<0>, C4<0>;
+L_0000000004125470 .functor BUF 1, L_00000000041250f0, C4<0>, C4<0>, C4<0>;
+v00000000039b0090_0 .net "A", 0 0, L_0000000004126660;  alias, 1 drivers
+L_0000000003aa4b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b0810_0 .net8 "VGND", 0 0, L_0000000003aa4b80;  1 drivers, strength-aware
+L_0000000003aa4480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af2d0_0 .net8 "VNB", 0 0, L_0000000003aa4480;  1 drivers, strength-aware
+L_0000000003aa4170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039afcd0_0 .net8 "VPB", 0 0, L_0000000003aa4170;  1 drivers, strength-aware
+L_0000000003aa4bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0450_0 .net8 "VPWR", 0 0, L_0000000003aa4bf0;  1 drivers, strength-aware
+v00000000039b08b0_0 .net "X", 0 0, L_0000000004125470;  alias, 1 drivers
+v00000000039af0f0_0 .net "buf0_out_X", 0 0, L_00000000041250f0;  1 drivers
+S_00000000028e5920 .scope module, "_0516_" "sky130_fd_sc_hd__buf_1" 3 557, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b03b0_0 .net "A", 0 0, L_0000000004125470;  alias, 1 drivers
+L_0000000003aa4090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ae3d0_0 .net8 "VGND", 0 0, L_0000000003aa4090;  1 drivers, strength-aware
+L_0000000003aa4870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aff50_0 .net8 "VNB", 0 0, L_0000000003aa4870;  1 drivers, strength-aware
+L_0000000003aa4950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aebf0_0 .net8 "VPB", 0 0, L_0000000003aa4950;  1 drivers, strength-aware
+L_0000000003aa4b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039afff0_0 .net8 "VPWR", 0 0, L_0000000003aa4b10;  1 drivers, strength-aware
+v00000000039ae8d0_0 .net "X", 0 0, L_0000000004125860;  alias, 1 drivers
+S_00000000028e5f20 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e5920;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041257f0 .functor BUF 1, L_0000000004125470, C4<0>, C4<0>, C4<0>;
+L_0000000004125860 .functor BUF 1, L_00000000041257f0, C4<0>, C4<0>, C4<0>;
+v00000000039afd70_0 .net "A", 0 0, L_0000000004125470;  alias, 1 drivers
+L_0000000003aa43a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af9b0_0 .net8 "VGND", 0 0, L_0000000003aa43a0;  1 drivers, strength-aware
+L_0000000003aa4720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af4b0_0 .net8 "VNB", 0 0, L_0000000003aa4720;  1 drivers, strength-aware
+L_0000000003aa4250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039afaf0_0 .net8 "VPB", 0 0, L_0000000003aa4250;  1 drivers, strength-aware
+L_0000000003aa4790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039afe10_0 .net8 "VPWR", 0 0, L_0000000003aa4790;  1 drivers, strength-aware
+v00000000039aeb50_0 .net "X", 0 0, L_0000000004125860;  alias, 1 drivers
+v00000000039b06d0_0 .net "buf0_out_X", 0 0, L_00000000041257f0;  1 drivers
+S_00000000028e3b20 .scope module, "_0517_" "sky130_fd_sc_hd__buf_1" 3 561, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b0770_0 .net "A", 0 0, L_0000000004125860;  alias, 1 drivers
+L_0000000003aa45d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b0310_0 .net8 "VGND", 0 0, L_0000000003aa45d0;  1 drivers, strength-aware
+L_0000000003aa4c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aea10_0 .net8 "VNB", 0 0, L_0000000003aa4c60;  1 drivers, strength-aware
+L_0000000003aa48e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0630_0 .net8 "VPB", 0 0, L_0000000003aa48e0;  1 drivers, strength-aware
+L_0000000003aa4800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ae150_0 .net8 "VPWR", 0 0, L_0000000003aa4800;  1 drivers, strength-aware
+v00000000039ae1f0_0 .net "X", 0 0, L_0000000004126190;  alias, 1 drivers
+S_00000000028e7a20 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e3b20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004125f60 .functor BUF 1, L_0000000004125860, C4<0>, C4<0>, C4<0>;
+L_0000000004126190 .functor BUF 1, L_0000000004125f60, C4<0>, C4<0>, C4<0>;
+v00000000039ae470_0 .net "A", 0 0, L_0000000004125860;  alias, 1 drivers
+L_0000000003aa4f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b01d0_0 .net8 "VGND", 0 0, L_0000000003aa4f70;  1 drivers, strength-aware
+L_0000000003aa4100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aef10_0 .net8 "VNB", 0 0, L_0000000003aa4100;  1 drivers, strength-aware
+L_0000000003aa49c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ae290_0 .net8 "VPB", 0 0, L_0000000003aa49c0;  1 drivers, strength-aware
+L_0000000003aa4cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aed30_0 .net8 "VPWR", 0 0, L_0000000003aa4cd0;  1 drivers, strength-aware
+v00000000039ae970_0 .net "X", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039aeab0_0 .net "buf0_out_X", 0 0, L_0000000004125f60;  1 drivers
+S_00000000028e84a0 .scope module, "_0518_" "sky130_fd_sc_hd__buf_1" 3 565, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039aedd0_0 .net "A", 0 0, L_0000000004126190;  alias, 1 drivers
+L_0000000003aa4640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ae790_0 .net8 "VGND", 0 0, L_0000000003aa4640;  1 drivers, strength-aware
+L_0000000003aa41e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af550_0 .net8 "VNB", 0 0, L_0000000003aa41e0;  1 drivers, strength-aware
+L_0000000003aa4e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039af230_0 .net8 "VPB", 0 0, L_0000000003aa4e20;  1 drivers, strength-aware
+L_0000000003aa4330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039aefb0_0 .net8 "VPWR", 0 0, L_0000000003aa4330;  1 drivers, strength-aware
+v00000000039ae830_0 .net "X", 0 0, L_0000000004126890;  alias, 1 drivers
+S_00000000028e78a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e84a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126820 .functor BUF 1, L_0000000004126190, C4<0>, C4<0>, C4<0>;
+L_0000000004126890 .functor BUF 1, L_0000000004126820, C4<0>, C4<0>, C4<0>;
+v00000000039ae330_0 .net "A", 0 0, L_0000000004126190;  alias, 1 drivers
+L_0000000003aa4a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039afb90_0 .net8 "VGND", 0 0, L_0000000003aa4a30;  1 drivers, strength-aware
+L_0000000003aa4410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039aec90_0 .net8 "VNB", 0 0, L_0000000003aa4410;  1 drivers, strength-aware
+L_0000000003aa4d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ae510_0 .net8 "VPB", 0 0, L_0000000003aa4d40;  1 drivers, strength-aware
+L_0000000003aa44f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ae5b0_0 .net8 "VPWR", 0 0, L_0000000003aa44f0;  1 drivers, strength-aware
+v00000000039ae650_0 .net "X", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039af410_0 .net "buf0_out_X", 0 0, L_0000000004126820;  1 drivers
+S_00000000028e3e20 .scope module, "_0519_" "sky130_fd_sc_hd__buf_1" 3 569, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039af7d0_0 .net "A", 0 0, L_0000000004126890;  alias, 1 drivers
+L_0000000003aa4db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af910_0 .net8 "VGND", 0 0, L_0000000003aa4db0;  1 drivers, strength-aware
+L_0000000003aa4560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1ad0_0 .net8 "VNB", 0 0, L_0000000003aa4560;  1 drivers, strength-aware
+L_0000000003aa46b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2cf0_0 .net8 "VPB", 0 0, L_0000000003aa46b0;  1 drivers, strength-aware
+L_0000000003a9e670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1710_0 .net8 "VPWR", 0 0, L_0000000003a9e670;  1 drivers, strength-aware
+v00000000039b29d0_0 .net "X", 0 0, L_0000000004126270;  alias, 1 drivers
+S_00000000028e8320 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e3e20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126200 .functor BUF 1, L_0000000004126890, C4<0>, C4<0>, C4<0>;
+L_0000000004126270 .functor BUF 1, L_0000000004126200, C4<0>, C4<0>, C4<0>;
+v00000000039af050_0 .net "A", 0 0, L_0000000004126890;  alias, 1 drivers
+L_0000000003a9d800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af870_0 .net8 "VGND", 0 0, L_0000000003a9d800;  1 drivers, strength-aware
+L_0000000003a9e980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039af190_0 .net8 "VNB", 0 0, L_0000000003a9e980;  1 drivers, strength-aware
+L_0000000003a9e1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039af370_0 .net8 "VPB", 0 0, L_0000000003a9e1a0;  1 drivers, strength-aware
+L_0000000003a9e750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039af5f0_0 .net8 "VPWR", 0 0, L_0000000003a9e750;  1 drivers, strength-aware
+v00000000039af690_0 .net "X", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039af730_0 .net "buf0_out_X", 0 0, L_0000000004126200;  1 drivers
+S_00000000028e5aa0 .scope module, "_0520_" "sky130_fd_sc_hd__buf_1" 3 573, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b09f0_0 .net "A", 0 0, L_0000000004126270;  alias, 1 drivers
+L_0000000003a9d950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1490_0 .net8 "VGND", 0 0, L_0000000003a9d950;  1 drivers, strength-aware
+L_0000000003a9d790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1670_0 .net8 "VNB", 0 0, L_0000000003a9d790;  1 drivers, strength-aware
+L_0000000003a9d870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0bd0_0 .net8 "VPB", 0 0, L_0000000003a9d870;  1 drivers, strength-aware
+L_0000000003a9da30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b15d0_0 .net8 "VPWR", 0 0, L_0000000003a9da30;  1 drivers, strength-aware
+v00000000039b2bb0_0 .net "X", 0 0, L_0000000004127230;  alias, 1 drivers
+S_00000000028e7120 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e5aa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004124de0 .functor BUF 1, L_0000000004126270, C4<0>, C4<0>, C4<0>;
+L_0000000004127230 .functor BUF 1, L_0000000004124de0, C4<0>, C4<0>, C4<0>;
+v00000000039b24d0_0 .net "A", 0 0, L_0000000004126270;  alias, 1 drivers
+L_0000000003a9e440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2d90_0 .net8 "VGND", 0 0, L_0000000003a9e440;  1 drivers, strength-aware
+L_0000000003a9d9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2570_0 .net8 "VNB", 0 0, L_0000000003a9d9c0;  1 drivers, strength-aware
+L_0000000003a9d720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b21b0_0 .net8 "VPB", 0 0, L_0000000003a9d720;  1 drivers, strength-aware
+L_0000000003a9e7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2250_0 .net8 "VPWR", 0 0, L_0000000003a9e7c0;  1 drivers, strength-aware
+v00000000039b13f0_0 .net "X", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039b0b30_0 .net "buf0_out_X", 0 0, L_0000000004124de0;  1 drivers
+S_00000000028e3fa0 .scope module, "_0521_" "sky130_fd_sc_hd__buf_1" 3 577, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b27f0_0 .net "A", 0 0, L_0000000004127230;  alias, 1 drivers
+L_0000000003a9e2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2a70_0 .net8 "VGND", 0 0, L_0000000003a9e2f0;  1 drivers, strength-aware
+L_0000000003a9db10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2110_0 .net8 "VNB", 0 0, L_0000000003a9db10;  1 drivers, strength-aware
+L_0000000003a9e6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2930_0 .net8 "VPB", 0 0, L_0000000003a9e6e0;  1 drivers, strength-aware
+L_0000000003a9dcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b30b0_0 .net8 "VPWR", 0 0, L_0000000003a9dcd0;  1 drivers, strength-aware
+v00000000039b1530_0 .net "X", 0 0, L_0000000004127e70;  alias, 1 drivers
+S_00000000028e4120 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e3fa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126ac0 .functor BUF 1, L_0000000004127230, C4<0>, C4<0>, C4<0>;
+L_0000000004127e70 .functor BUF 1, L_0000000004126ac0, C4<0>, C4<0>, C4<0>;
+v00000000039b2610_0 .net "A", 0 0, L_0000000004127230;  alias, 1 drivers
+L_0000000003a9d6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b3010_0 .net8 "VGND", 0 0, L_0000000003a9d6b0;  1 drivers, strength-aware
+L_0000000003a9d8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b0c70_0 .net8 "VNB", 0 0, L_0000000003a9d8e0;  1 drivers, strength-aware
+L_0000000003a9d5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2750_0 .net8 "VPB", 0 0, L_0000000003a9d5d0;  1 drivers, strength-aware
+L_0000000003a9d1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2890_0 .net8 "VPWR", 0 0, L_0000000003a9d1e0;  1 drivers, strength-aware
+v00000000039b26b0_0 .net "X", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039b17b0_0 .net "buf0_out_X", 0 0, L_0000000004126ac0;  1 drivers
+S_00000000028e60a0 .scope module, "_0522_" "sky130_fd_sc_hd__inv_2" 3 581, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b0f90_0 .net "A", 0 0, L_0000000003f8e400;  1 drivers
+L_0000000003a9de20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2c50_0 .net8 "VGND", 0 0, L_0000000003a9de20;  1 drivers, strength-aware
+L_0000000003a9daa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1210_0 .net8 "VNB", 0 0, L_0000000003a9daa0;  1 drivers, strength-aware
+L_0000000003a9e280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b2e30_0 .net8 "VPB", 0 0, L_0000000003a9e280;  1 drivers, strength-aware
+L_0000000003a9db80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0d10_0 .net8 "VPWR", 0 0, L_0000000003a9db80;  1 drivers, strength-aware
+v00000000039b10d0_0 .net "Y", 0 0, L_0000000004127f50;  alias, 1 drivers
+S_00000000028e4420 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028e60a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126900 .functor NOT 1, L_0000000003f8e400, C4<0>, C4<0>, C4<0>;
+L_0000000004127f50 .functor BUF 1, L_0000000004126900, C4<0>, C4<0>, C4<0>;
+v00000000039b2b10_0 .net "A", 0 0, L_0000000003f8e400;  alias, 1 drivers
+L_0000000003a9e830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b0ef0_0 .net8 "VGND", 0 0, L_0000000003a9e830;  1 drivers, strength-aware
+L_0000000003a9d330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1990_0 .net8 "VNB", 0 0, L_0000000003a9d330;  1 drivers, strength-aware
+L_0000000003a9e9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b0a90_0 .net8 "VPB", 0 0, L_0000000003a9e9f0;  1 drivers, strength-aware
+L_0000000003a9d090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b22f0_0 .net8 "VPWR", 0 0, L_0000000003a9d090;  1 drivers, strength-aware
+v00000000039b2070_0 .net "Y", 0 0, L_0000000004127f50;  alias, 1 drivers
+v00000000039b1030_0 .net "not0_out_Y", 0 0, L_0000000004126900;  1 drivers
+S_00000000028e45a0 .scope module, "_0523_" "sky130_fd_sc_hd__buf_1" 3 585, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b0e50_0 .net "A", 0 0, L_0000000004125400;  alias, 1 drivers
+L_0000000003a9dd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1b70_0 .net8 "VGND", 0 0, L_0000000003a9dd40;  1 drivers, strength-aware
+L_0000000003a9e520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2f70_0 .net8 "VNB", 0 0, L_0000000003a9e520;  1 drivers, strength-aware
+L_0000000003a9d250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b12b0_0 .net8 "VPB", 0 0, L_0000000003a9d250;  1 drivers, strength-aware
+L_0000000003a9de90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1c10_0 .net8 "VPWR", 0 0, L_0000000003a9de90;  1 drivers, strength-aware
+v00000000039b1350_0 .net "X", 0 0, L_00000000041270e0;  alias, 1 drivers
+S_00000000028e63a0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e45a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126a50 .functor BUF 1, L_0000000004125400, C4<0>, C4<0>, C4<0>;
+L_00000000041270e0 .functor BUF 1, L_0000000004126a50, C4<0>, C4<0>, C4<0>;
+v00000000039b0db0_0 .net "A", 0 0, L_0000000004125400;  alias, 1 drivers
+L_0000000003a9ddb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b2ed0_0 .net8 "VGND", 0 0, L_0000000003a9ddb0;  1 drivers, strength-aware
+L_0000000003a9dbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1170_0 .net8 "VNB", 0 0, L_0000000003a9dbf0;  1 drivers, strength-aware
+L_0000000003a9d3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1850_0 .net8 "VPB", 0 0, L_0000000003a9d3a0;  1 drivers, strength-aware
+L_0000000003a9e210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1cb0_0 .net8 "VPWR", 0 0, L_0000000003a9e210;  1 drivers, strength-aware
+v00000000039b1a30_0 .net "X", 0 0, L_00000000041270e0;  alias, 1 drivers
+v00000000039b18f0_0 .net "buf0_out_X", 0 0, L_0000000004126a50;  1 drivers
+S_00000000028e4720 .scope module, "_0524_" "sky130_fd_sc_hd__buf_1" 3 589, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b2430_0 .net "A", 0 0, L_00000000041270e0;  alias, 1 drivers
+L_0000000003a9dc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b49b0_0 .net8 "VGND", 0 0, L_0000000003a9dc60;  1 drivers, strength-aware
+L_0000000003a9d410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b3e70_0 .net8 "VNB", 0 0, L_0000000003a9d410;  1 drivers, strength-aware
+L_0000000003a9e360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b4050_0 .net8 "VPB", 0 0, L_0000000003a9e360;  1 drivers, strength-aware
+L_0000000003a9d640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b36f0_0 .net8 "VPWR", 0 0, L_0000000003a9d640;  1 drivers, strength-aware
+v00000000039b4410_0 .net "X", 0 0, L_00000000041271c0;  alias, 1 drivers
+S_00000000028e7ba0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e4720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126ba0 .functor BUF 1, L_00000000041270e0, C4<0>, C4<0>, C4<0>;
+L_00000000041271c0 .functor BUF 1, L_0000000004126ba0, C4<0>, C4<0>, C4<0>;
+v00000000039b0950_0 .net "A", 0 0, L_00000000041270e0;  alias, 1 drivers
+L_0000000003a9df00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1f30_0 .net8 "VGND", 0 0, L_0000000003a9df00;  1 drivers, strength-aware
+L_0000000003a9d100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b1d50_0 .net8 "VNB", 0 0, L_0000000003a9d100;  1 drivers, strength-aware
+L_0000000003a9d480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1df0_0 .net8 "VPB", 0 0, L_0000000003a9d480;  1 drivers, strength-aware
+L_0000000003a9df70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b1e90_0 .net8 "VPWR", 0 0, L_0000000003a9df70;  1 drivers, strength-aware
+v00000000039b1fd0_0 .net "X", 0 0, L_00000000041271c0;  alias, 1 drivers
+v00000000039b2390_0 .net "buf0_out_X", 0 0, L_0000000004126ba0;  1 drivers
+S_00000000028e75a0 .scope module, "_0525_" "sky130_fd_sc_hd__buf_1" 3 593, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b3fb0_0 .net "A", 0 0, L_00000000041271c0;  alias, 1 drivers
+L_0000000003a9dfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4c30_0 .net8 "VGND", 0 0, L_0000000003a9dfe0;  1 drivers, strength-aware
+L_0000000003a9e4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4370_0 .net8 "VNB", 0 0, L_0000000003a9e4b0;  1 drivers, strength-aware
+L_0000000003a9e050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5630_0 .net8 "VPB", 0 0, L_0000000003a9e050;  1 drivers, strength-aware
+L_0000000003a9e0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3790_0 .net8 "VPWR", 0 0, L_0000000003a9e0c0;  1 drivers, strength-aware
+v00000000039b4f50_0 .net "X", 0 0, L_0000000004127620;  alias, 1 drivers
+S_00000000028e4ba0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e75a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127850 .functor BUF 1, L_00000000041271c0, C4<0>, C4<0>, C4<0>;
+L_0000000004127620 .functor BUF 1, L_0000000004127850, C4<0>, C4<0>, C4<0>;
+v00000000039b4a50_0 .net "A", 0 0, L_00000000041271c0;  alias, 1 drivers
+L_0000000003a9e8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b35b0_0 .net8 "VGND", 0 0, L_0000000003a9e8a0;  1 drivers, strength-aware
+L_0000000003a9ea60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b31f0_0 .net8 "VNB", 0 0, L_0000000003a9ea60;  1 drivers, strength-aware
+L_0000000003a9d170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b4230_0 .net8 "VPB", 0 0, L_0000000003a9d170;  1 drivers, strength-aware
+L_0000000003a9d4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3f10_0 .net8 "VPWR", 0 0, L_0000000003a9d4f0;  1 drivers, strength-aware
+v00000000039b33d0_0 .net "X", 0 0, L_0000000004127620;  alias, 1 drivers
+v00000000039b3dd0_0 .net "buf0_out_X", 0 0, L_0000000004127850;  1 drivers
+S_00000000028e66a0 .scope module, "_0526_" "sky130_fd_sc_hd__buf_1" 3 597, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b5090_0 .net "A", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003a9ead0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4690_0 .net8 "VGND", 0 0, L_0000000003a9ead0;  1 drivers, strength-aware
+L_0000000003a9d560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b40f0_0 .net8 "VNB", 0 0, L_0000000003a9d560;  1 drivers, strength-aware
+L_0000000003a9e130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3970_0 .net8 "VPB", 0 0, L_0000000003a9e130;  1 drivers, strength-aware
+L_0000000003a9e3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b4af0_0 .net8 "VPWR", 0 0, L_0000000003a9e3d0;  1 drivers, strength-aware
+v00000000039b54f0_0 .net "X", 0 0, L_0000000004127930;  alias, 1 drivers
+S_00000000028e6820 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e66a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041272a0 .functor BUF 1, L_0000000004127620, C4<0>, C4<0>, C4<0>;
+L_0000000004127930 .functor BUF 1, L_00000000041272a0, C4<0>, C4<0>, C4<0>;
+v00000000039b3290_0 .net "A", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003a9e590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b51d0_0 .net8 "VGND", 0 0, L_0000000003a9e590;  1 drivers, strength-aware
+L_0000000003a9d2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4ff0_0 .net8 "VNB", 0 0, L_0000000003a9d2c0;  1 drivers, strength-aware
+L_0000000003a9e600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3330_0 .net8 "VPB", 0 0, L_0000000003a9e600;  1 drivers, strength-aware
+L_0000000003a9e910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b4910_0 .net8 "VPWR", 0 0, L_0000000003a9e910;  1 drivers, strength-aware
+v00000000039b4cd0_0 .net "X", 0 0, L_0000000004127930;  alias, 1 drivers
+v00000000039b58b0_0 .net "buf0_out_X", 0 0, L_00000000041272a0;  1 drivers
+S_00000000028e6b20 .scope module, "_0527_" "sky130_fd_sc_hd__buf_1" 3 601, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b44b0_0 .net "A", 0 0, L_0000000004127930;  alias, 1 drivers
+L_0000000003a9eb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4e10_0 .net8 "VGND", 0 0, L_0000000003a9eb40;  1 drivers, strength-aware
+L_0000000003a9ebb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4eb0_0 .net8 "VNB", 0 0, L_0000000003a9ebb0;  1 drivers, strength-aware
+L_0000000003a9ec20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b4190_0 .net8 "VPB", 0 0, L_0000000003a9ec20;  1 drivers, strength-aware
+L_0000000003fcfcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5810_0 .net8 "VPWR", 0 0, L_0000000003fcfcd0;  1 drivers, strength-aware
+v00000000039b5770_0 .net "X", 0 0, L_0000000004127a80;  alias, 1 drivers
+S_00000000028e7420 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028e6b20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127540 .functor BUF 1, L_0000000004127930, C4<0>, C4<0>, C4<0>;
+L_0000000004127a80 .functor BUF 1, L_0000000004127540, C4<0>, C4<0>, C4<0>;
+v00000000039b3ab0_0 .net "A", 0 0, L_0000000004127930;  alias, 1 drivers
+L_0000000003fcf6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4d70_0 .net8 "VGND", 0 0, L_0000000003fcf6b0;  1 drivers, strength-aware
+L_0000000003fcf250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b3830_0 .net8 "VNB", 0 0, L_0000000003fcf250;  1 drivers, strength-aware
+L_0000000003fcf950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5270_0 .net8 "VPB", 0 0, L_0000000003fcf950;  1 drivers, strength-aware
+L_0000000003fd0c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3650_0 .net8 "VPWR", 0 0, L_0000000003fd0c20;  1 drivers, strength-aware
+v00000000039b3d30_0 .net "X", 0 0, L_0000000004127a80;  alias, 1 drivers
+v00000000039b4730_0 .net "buf0_out_X", 0 0, L_0000000004127540;  1 drivers
+S_0000000002a23560 .scope module, "_0528_" "sky130_fd_sc_hd__buf_1" 3 605, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b38d0_0 .net "A", 0 0, L_0000000004127a80;  alias, 1 drivers
+L_0000000003fcffe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b5130_0 .net8 "VGND", 0 0, L_0000000003fcffe0;  1 drivers, strength-aware
+L_0000000003fcfe90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b5590_0 .net8 "VNB", 0 0, L_0000000003fcfe90;  1 drivers, strength-aware
+L_0000000003fd02f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5310_0 .net8 "VPB", 0 0, L_0000000003fd02f0;  1 drivers, strength-aware
+L_0000000003fcfb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3c90_0 .net8 "VPWR", 0 0, L_0000000003fcfb10;  1 drivers, strength-aware
+v00000000039b4b90_0 .net "X", 0 0, L_0000000004127ee0;  alias, 1 drivers
+S_0000000002a239e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a23560;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041278c0 .functor BUF 1, L_0000000004127a80, C4<0>, C4<0>, C4<0>;
+L_0000000004127ee0 .functor BUF 1, L_00000000041278c0, C4<0>, C4<0>, C4<0>;
+v00000000039b42d0_0 .net "A", 0 0, L_0000000004127a80;  alias, 1 drivers
+L_0000000003fd06e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4550_0 .net8 "VGND", 0 0, L_0000000003fd06e0;  1 drivers, strength-aware
+L_0000000003fcfd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b5450_0 .net8 "VNB", 0 0, L_0000000003fcfd40;  1 drivers, strength-aware
+L_0000000003fcf720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3470_0 .net8 "VPB", 0 0, L_0000000003fcf720;  1 drivers, strength-aware
+L_0000000003fcf790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3150_0 .net8 "VPWR", 0 0, L_0000000003fcf790;  1 drivers, strength-aware
+v00000000039b45f0_0 .net "X", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039b47d0_0 .net "buf0_out_X", 0 0, L_00000000041278c0;  1 drivers
+S_0000000002a20560 .scope module, "_0529_" "sky130_fd_sc_hd__buf_1" 3 609, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b5f90_0 .net "A", 0 0, L_0000000004127ee0;  alias, 1 drivers
+L_0000000003fcf5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b7610_0 .net8 "VGND", 0 0, L_0000000003fcf5d0;  1 drivers, strength-aware
+L_0000000003fcf1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8010_0 .net8 "VNB", 0 0, L_0000000003fcf1e0;  1 drivers, strength-aware
+L_0000000003fcfe20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5c70_0 .net8 "VPB", 0 0, L_0000000003fcfe20;  1 drivers, strength-aware
+L_0000000003fcf9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6fd0_0 .net8 "VPWR", 0 0, L_0000000003fcf9c0;  1 drivers, strength-aware
+v00000000039b7890_0 .net "X", 0 0, L_0000000004127b60;  alias, 1 drivers
+S_0000000002a218e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a20560;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127d20 .functor BUF 1, L_0000000004127ee0, C4<0>, C4<0>, C4<0>;
+L_0000000004127b60 .functor BUF 1, L_0000000004127d20, C4<0>, C4<0>, C4<0>;
+v00000000039b3a10_0 .net "A", 0 0, L_0000000004127ee0;  alias, 1 drivers
+L_0000000003fd0280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b53b0_0 .net8 "VGND", 0 0, L_0000000003fd0280;  1 drivers, strength-aware
+L_0000000003fcfa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b4870_0 .net8 "VNB", 0 0, L_0000000003fcfa30;  1 drivers, strength-aware
+L_0000000003fd0670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b56d0_0 .net8 "VPB", 0 0, L_0000000003fd0670;  1 drivers, strength-aware
+L_0000000003fcf330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b3510_0 .net8 "VPWR", 0 0, L_0000000003fcf330;  1 drivers, strength-aware
+v00000000039b3b50_0 .net "X", 0 0, L_0000000004127b60;  alias, 1 drivers
+v00000000039b3bf0_0 .net "buf0_out_X", 0 0, L_0000000004127d20;  1 drivers
+S_0000000002a221e0 .scope module, "_0530_" "sky130_fd_sc_hd__buf_1" 3 613, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b72f0_0 .net "A", 0 0, L_0000000004127b60;  alias, 1 drivers
+L_0000000003fd0980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b76b0_0 .net8 "VGND", 0 0, L_0000000003fd0980;  1 drivers, strength-aware
+L_0000000003fcf090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b5ef0_0 .net8 "VNB", 0 0, L_0000000003fcf090;  1 drivers, strength-aware
+L_0000000003fcfdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6990_0 .net8 "VPB", 0 0, L_0000000003fcfdb0;  1 drivers, strength-aware
+L_0000000003fd0520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7f70_0 .net8 "VPWR", 0 0, L_0000000003fd0520;  1 drivers, strength-aware
+v00000000039b7250_0 .net "X", 0 0, L_0000000004127310;  alias, 1 drivers
+S_0000000002a212e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a221e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041283b0 .functor BUF 1, L_0000000004127b60, C4<0>, C4<0>, C4<0>;
+L_0000000004127310 .functor BUF 1, L_00000000041283b0, C4<0>, C4<0>, C4<0>;
+v00000000039b7bb0_0 .net "A", 0 0, L_0000000004127b60;  alias, 1 drivers
+L_0000000003fcf2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6030_0 .net8 "VGND", 0 0, L_0000000003fcf2c0;  1 drivers, strength-aware
+L_0000000003fcff00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b80b0_0 .net8 "VNB", 0 0, L_0000000003fcff00;  1 drivers, strength-aware
+L_0000000003fcff70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6490_0 .net8 "VPB", 0 0, L_0000000003fcff70;  1 drivers, strength-aware
+L_0000000003fcfaa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b77f0_0 .net8 "VPWR", 0 0, L_0000000003fcfaa0;  1 drivers, strength-aware
+v00000000039b6530_0 .net "X", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039b65d0_0 .net "buf0_out_X", 0 0, L_00000000041283b0;  1 drivers
+S_0000000002a21160 .scope module, "_0531_" "sky130_fd_sc_hd__buf_1" 3 617, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b5950_0 .net "A", 0 0, L_0000000004127310;  alias, 1 drivers
+L_0000000003fcf3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6710_0 .net8 "VGND", 0 0, L_0000000003fcf3a0;  1 drivers, strength-aware
+L_0000000003fd0210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6e90_0 .net8 "VNB", 0 0, L_0000000003fd0210;  1 drivers, strength-aware
+L_0000000003fcfb80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6d50_0 .net8 "VPB", 0 0, L_0000000003fcfb80;  1 drivers, strength-aware
+L_0000000003fcf410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7930_0 .net8 "VPWR", 0 0, L_0000000003fcf410;  1 drivers, strength-aware
+v00000000039b7110_0 .net "X", 0 0, L_0000000004128260;  alias, 1 drivers
+S_0000000002a20260 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a21160;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127380 .functor BUF 1, L_0000000004127310, C4<0>, C4<0>, C4<0>;
+L_0000000004128260 .functor BUF 1, L_0000000004127380, C4<0>, C4<0>, C4<0>;
+v00000000039b71b0_0 .net "A", 0 0, L_0000000004127310;  alias, 1 drivers
+L_0000000003fd0360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b7ed0_0 .net8 "VGND", 0 0, L_0000000003fd0360;  1 drivers, strength-aware
+L_0000000003fcf640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6f30_0 .net8 "VNB", 0 0, L_0000000003fcf640;  1 drivers, strength-aware
+L_0000000003fcfbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6c10_0 .net8 "VPB", 0 0, L_0000000003fcfbf0;  1 drivers, strength-aware
+L_0000000003fcf100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6cb0_0 .net8 "VPWR", 0 0, L_0000000003fcf100;  1 drivers, strength-aware
+v00000000039b6670_0 .net "X", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039b74d0_0 .net "buf0_out_X", 0 0, L_0000000004127380;  1 drivers
+S_0000000002a224e0 .scope module, "_0532_" "sky130_fd_sc_hd__inv_2" 3 621, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b5e50_0 .net "A", 0 0, L_0000000004126430;  alias, 1 drivers
+L_0000000003fcf480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b68f0_0 .net8 "VGND", 0 0, L_0000000003fcf480;  1 drivers, strength-aware
+L_0000000003fd0050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6170_0 .net8 "VNB", 0 0, L_0000000003fd0050;  1 drivers, strength-aware
+L_0000000003fcfc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6850_0 .net8 "VPB", 0 0, L_0000000003fcfc60;  1 drivers, strength-aware
+L_0000000003fd0440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7a70_0 .net8 "VPWR", 0 0, L_0000000003fd0440;  1 drivers, strength-aware
+v00000000039b79d0_0 .net "Y", 0 0, L_0000000004127a10;  alias, 1 drivers
+S_0000000002a24d60 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a224e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126970 .functor NOT 1, L_0000000004126430, C4<0>, C4<0>, C4<0>;
+L_0000000004127a10 .functor BUF 1, L_0000000004126970, C4<0>, C4<0>, C4<0>;
+v00000000039b5d10_0 .net "A", 0 0, L_0000000004126430;  alias, 1 drivers
+L_0000000003fd00c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6350_0 .net8 "VGND", 0 0, L_0000000003fd00c0;  1 drivers, strength-aware
+L_0000000003fd0130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b5bd0_0 .net8 "VNB", 0 0, L_0000000003fd0130;  1 drivers, strength-aware
+L_0000000003fd0750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7750_0 .net8 "VPB", 0 0, L_0000000003fd0750;  1 drivers, strength-aware
+L_0000000003fd0a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b63f0_0 .net8 "VPWR", 0 0, L_0000000003fd0a60;  1 drivers, strength-aware
+v00000000039b59f0_0 .net "Y", 0 0, L_0000000004127a10;  alias, 1 drivers
+v00000000039b60d0_0 .net "not0_out_Y", 0 0, L_0000000004126970;  1 drivers
+S_0000000002a25660 .scope module, "_0533_" "sky130_fd_sc_hd__buf_1" 3 625, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b7390_0 .net "A", 0 0, L_0000000004127a10;  alias, 1 drivers
+L_0000000003fcf170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b67b0_0 .net8 "VGND", 0 0, L_0000000003fcf170;  1 drivers, strength-aware
+L_0000000003fcf4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b7c50_0 .net8 "VNB", 0 0, L_0000000003fcf4f0;  1 drivers, strength-aware
+L_0000000003fd0ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5db0_0 .net8 "VPB", 0 0, L_0000000003fd0ad0;  1 drivers, strength-aware
+L_0000000003fcf560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7430_0 .net8 "VPWR", 0 0, L_0000000003fcf560;  1 drivers, strength-aware
+v00000000039b6df0_0 .net "X", 0 0, L_0000000004126dd0;  alias, 1 drivers
+S_0000000002a24be0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a25660;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041273f0 .functor BUF 1, L_0000000004127a10, C4<0>, C4<0>, C4<0>;
+L_0000000004126dd0 .functor BUF 1, L_00000000041273f0, C4<0>, C4<0>, C4<0>;
+v00000000039b5a90_0 .net "A", 0 0, L_0000000004127a10;  alias, 1 drivers
+L_0000000003fcf800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6ad0_0 .net8 "VGND", 0 0, L_0000000003fcf800;  1 drivers, strength-aware
+L_0000000003fd0b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b7570_0 .net8 "VNB", 0 0, L_0000000003fd0b40;  1 drivers, strength-aware
+L_0000000003fd07c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7070_0 .net8 "VPB", 0 0, L_0000000003fd07c0;  1 drivers, strength-aware
+L_0000000003fcf870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b5b30_0 .net8 "VPWR", 0 0, L_0000000003fcf870;  1 drivers, strength-aware
+v00000000039b62b0_0 .net "X", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v00000000039b7b10_0 .net "buf0_out_X", 0 0, L_00000000041273f0;  1 drivers
+S_0000000002a20e60 .scope module, "_0534_" "sky130_fd_sc_hd__buf_1" 3 629, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b9410_0 .net "A", 0 0, L_0000000004126dd0;  alias, 1 drivers
+L_0000000003fd0600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ba4f0_0 .net8 "VGND", 0 0, L_0000000003fd0600;  1 drivers, strength-aware
+L_0000000003fd01a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9d70_0 .net8 "VNB", 0 0, L_0000000003fd01a0;  1 drivers, strength-aware
+L_0000000003fd0bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b99b0_0 .net8 "VPB", 0 0, L_0000000003fd0bb0;  1 drivers, strength-aware
+L_0000000003fd04b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b9a50_0 .net8 "VPWR", 0 0, L_0000000003fd04b0;  1 drivers, strength-aware
+v00000000039b8bf0_0 .net "X", 0 0, L_00000000041279a0;  alias, 1 drivers
+S_0000000002a21760 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a20e60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127fc0 .functor BUF 1, L_0000000004126dd0, C4<0>, C4<0>, C4<0>;
+L_00000000041279a0 .functor BUF 1, L_0000000004127fc0, C4<0>, C4<0>, C4<0>;
+v00000000039b7cf0_0 .net "A", 0 0, L_0000000004126dd0;  alias, 1 drivers
+L_0000000003fcf8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b6a30_0 .net8 "VGND", 0 0, L_0000000003fcf8e0;  1 drivers, strength-aware
+L_0000000003fd03d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b7d90_0 .net8 "VNB", 0 0, L_0000000003fd03d0;  1 drivers, strength-aware
+L_0000000003fd0590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b7e30_0 .net8 "VPB", 0 0, L_0000000003fd0590;  1 drivers, strength-aware
+L_0000000003fd0830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b6b70_0 .net8 "VPWR", 0 0, L_0000000003fd0830;  1 drivers, strength-aware
+v00000000039b6210_0 .net "X", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039b9050_0 .net "buf0_out_X", 0 0, L_0000000004127fc0;  1 drivers
+S_0000000002a20860 .scope module, "_0535_" "sky130_fd_sc_hd__buf_1" 3 633, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b9ff0_0 .net "A", 0 0, L_00000000041279a0;  alias, 1 drivers
+L_0000000003fd08a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ba810_0 .net8 "VGND", 0 0, L_0000000003fd08a0;  1 drivers, strength-aware
+L_0000000003fd0910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8470_0 .net8 "VNB", 0 0, L_0000000003fd0910;  1 drivers, strength-aware
+L_0000000003fd09f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba090_0 .net8 "VPB", 0 0, L_0000000003fd09f0;  1 drivers, strength-aware
+L_0000000003fd19b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba130_0 .net8 "VPWR", 0 0, L_0000000003fd19b0;  1 drivers, strength-aware
+v00000000039b9e10_0 .net "X", 0 0, L_0000000004128030;  alias, 1 drivers
+S_0000000002a21be0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a20860;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004128420 .functor BUF 1, L_00000000041279a0, C4<0>, C4<0>, C4<0>;
+L_0000000004128030 .functor BUF 1, L_0000000004128420, C4<0>, C4<0>, C4<0>;
+v00000000039b9b90_0 .net "A", 0 0, L_00000000041279a0;  alias, 1 drivers
+L_0000000003fd1470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8dd0_0 .net8 "VGND", 0 0, L_0000000003fd1470;  1 drivers, strength-aware
+L_0000000003fd1630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ba3b0_0 .net8 "VNB", 0 0, L_0000000003fd1630;  1 drivers, strength-aware
+L_0000000003fd2040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b9eb0_0 .net8 "VPB", 0 0, L_0000000003fd2040;  1 drivers, strength-aware
+L_0000000003fd15c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba6d0_0 .net8 "VPWR", 0 0, L_0000000003fd15c0;  1 drivers, strength-aware
+v00000000039b9f50_0 .net "X", 0 0, L_0000000004128030;  alias, 1 drivers
+v00000000039ba630_0 .net "buf0_out_X", 0 0, L_0000000004128420;  1 drivers
+S_0000000002a21d60 .scope module, "_0536_" "sky130_fd_sc_hd__buf_1" 3 637, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039ba590_0 .net "A", 0 0, L_0000000004128030;  alias, 1 drivers
+L_0000000003fd1320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b86f0_0 .net8 "VGND", 0 0, L_0000000003fd1320;  1 drivers, strength-aware
+L_0000000003fd2350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9190_0 .net8 "VNB", 0 0, L_0000000003fd2350;  1 drivers, strength-aware
+L_0000000003fd0f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b81f0_0 .net8 "VPB", 0 0, L_0000000003fd0f30;  1 drivers, strength-aware
+L_0000000003fd2580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b9af0_0 .net8 "VPWR", 0 0, L_0000000003fd2580;  1 drivers, strength-aware
+v00000000039b9870_0 .net "X", 0 0, L_0000000004126c10;  alias, 1 drivers
+S_0000000002a24ee0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a21d60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041269e0 .functor BUF 1, L_0000000004128030, C4<0>, C4<0>, C4<0>;
+L_0000000004126c10 .functor BUF 1, L_00000000041269e0, C4<0>, C4<0>, C4<0>;
+v00000000039b8830_0 .net "A", 0 0, L_0000000004128030;  alias, 1 drivers
+L_0000000003fd0c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ba8b0_0 .net8 "VGND", 0 0, L_0000000003fd0c90;  1 drivers, strength-aware
+L_0000000003fd18d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8c90_0 .net8 "VNB", 0 0, L_0000000003fd18d0;  1 drivers, strength-aware
+L_0000000003fd2120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba1d0_0 .net8 "VPB", 0 0, L_0000000003fd2120;  1 drivers, strength-aware
+L_0000000003fd0e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b8d30_0 .net8 "VPWR", 0 0, L_0000000003fd0e50;  1 drivers, strength-aware
+v00000000039b8e70_0 .net "X", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039b8970_0 .net "buf0_out_X", 0 0, L_00000000041269e0;  1 drivers
+S_0000000002a22360 .scope module, "_0537_" "sky130_fd_sc_hd__buf_1" 3 641, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039b8150_0 .net "A", 0 0, L_0000000004126c10;  alias, 1 drivers
+L_0000000003fd1a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9690_0 .net8 "VGND", 0 0, L_0000000003fd1a20;  1 drivers, strength-aware
+L_0000000003fd1940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9550_0 .net8 "VNB", 0 0, L_0000000003fd1940;  1 drivers, strength-aware
+L_0000000003fd16a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b8290_0 .net8 "VPB", 0 0, L_0000000003fd16a0;  1 drivers, strength-aware
+L_0000000003fd0fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b9910_0 .net8 "VPWR", 0 0, L_0000000003fd0fa0;  1 drivers, strength-aware
+v00000000039b97d0_0 .net "X", 0 0, L_00000000041280a0;  alias, 1 drivers
+S_0000000002a22660 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a22360;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127690 .functor BUF 1, L_0000000004126c10, C4<0>, C4<0>, C4<0>;
+L_00000000041280a0 .functor BUF 1, L_0000000004127690, C4<0>, C4<0>, C4<0>;
+v00000000039ba770_0 .net "A", 0 0, L_0000000004126c10;  alias, 1 drivers
+L_0000000003fd1e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9730_0 .net8 "VGND", 0 0, L_0000000003fd1e10;  1 drivers, strength-aware
+L_0000000003fd1710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b94b0_0 .net8 "VNB", 0 0, L_0000000003fd1710;  1 drivers, strength-aware
+L_0000000003fd1010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba270_0 .net8 "VPB", 0 0, L_0000000003fd1010;  1 drivers, strength-aware
+L_0000000003fd1e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b8f10_0 .net8 "VPWR", 0 0, L_0000000003fd1e80;  1 drivers, strength-aware
+v00000000039b95f0_0 .net "X", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039b8fb0_0 .net "buf0_out_X", 0 0, L_0000000004127690;  1 drivers
+S_0000000002a230e0 .scope module, "_0538_" "sky130_fd_sc_hd__a2bb2o_2" 3 645, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039b83d0_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039b85b0_0 .net "A2_N", 0 0, L_0000000003f8e4a0;  1 drivers
+v00000000039b8650_0 .net "B1", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039b8790_0 .net "B2", 0 0, L_0000000003f8efe0;  1 drivers
+L_0000000003fd1240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b88d0_0 .net8 "VGND", 0 0, L_0000000003fd1240;  1 drivers, strength-aware
+L_0000000003fd17f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8a10_0 .net8 "VNB", 0 0, L_0000000003fd17f0;  1 drivers, strength-aware
+L_0000000003fd0d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bb2b0_0 .net8 "VPB", 0 0, L_0000000003fd0d00;  1 drivers, strength-aware
+L_0000000003fd1080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bca70_0 .net8 "VPWR", 0 0, L_0000000003fd1080;  1 drivers, strength-aware
+v00000000039bc6b0_0 .net "X", 0 0, L_0000000004127150;  alias, 1 drivers
+S_0000000002a22ae0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002a230e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004127c40 .functor AND 1, L_00000000041280a0, L_0000000003f8efe0, C4<1>, C4<1>;
+L_0000000004127460 .functor NOR 1, L_00000000041280a0, L_0000000003f8e4a0, C4<0>, C4<0>;
+L_0000000004127af0 .functor OR 1, L_0000000004127460, L_0000000004127c40, C4<0>, C4<0>;
+L_0000000004127150 .functor BUF 1, L_0000000004127af0, C4<0>, C4<0>, C4<0>;
+v00000000039b8330_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039b9370_0 .net "A2_N", 0 0, L_0000000003f8e4a0;  alias, 1 drivers
+v00000000039b8b50_0 .net "B1", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039b90f0_0 .net "B2", 0 0, L_0000000003f8efe0;  alias, 1 drivers
+L_0000000003fd1b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b9230_0 .net8 "VGND", 0 0, L_0000000003fd1b00;  1 drivers, strength-aware
+L_0000000003fd1550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039b8ab0_0 .net8 "VNB", 0 0, L_0000000003fd1550;  1 drivers, strength-aware
+L_0000000003fd20b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b92d0_0 .net8 "VPB", 0 0, L_0000000003fd20b0;  1 drivers, strength-aware
+L_0000000003fd1780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039b9c30_0 .net8 "VPWR", 0 0, L_0000000003fd1780;  1 drivers, strength-aware
+v00000000039b9cd0_0 .net "X", 0 0, L_0000000004127150;  alias, 1 drivers
+v00000000039b8510_0 .net "and0_out", 0 0, L_0000000004127c40;  1 drivers
+v00000000039ba310_0 .net "nor0_out", 0 0, L_0000000004127460;  1 drivers
+v00000000039ba450_0 .net "or0_out_X", 0 0, L_0000000004127af0;  1 drivers
+S_0000000002a20b60 .scope module, "_0539_" "sky130_fd_sc_hd__o221a_2" 3 652, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039bb3f0_0 .net "A1", 0 0, L_0000000003f8d320;  1 drivers
+v00000000039bc430_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039bb0d0_0 .net "B1", 0 0, L_0000000004127f50;  alias, 1 drivers
+v00000000039bc7f0_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039bd010_0 .net "C1", 0 0, L_0000000004127150;  alias, 1 drivers
+L_0000000003fd1860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bd0b0_0 .net8 "VGND", 0 0, L_0000000003fd1860;  1 drivers, strength-aware
+L_0000000003fd23c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ba9f0_0 .net8 "VNB", 0 0, L_0000000003fd23c0;  1 drivers, strength-aware
+L_0000000003fd2660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bc890_0 .net8 "VPB", 0 0, L_0000000003fd2660;  1 drivers, strength-aware
+L_0000000003fd0d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ba950_0 .net8 "VPWR", 0 0, L_0000000003fd0d70;  1 drivers, strength-aware
+v00000000039bac70_0 .net "X", 0 0, L_0000000004127700;  alias, 1 drivers
+S_0000000002a23ce0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000002a20b60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004127770 .functor OR 1, L_0000000004128260, L_0000000004127f50, C4<0>, C4<0>;
+L_00000000041274d0 .functor OR 1, L_0000000004127e70, L_0000000003f8d320, C4<0>, C4<0>;
+L_0000000004126b30 .functor AND 1, L_0000000004127770, L_00000000041274d0, L_0000000004127150, C4<1>;
+L_0000000004127700 .functor BUF 1, L_0000000004126b30, C4<0>, C4<0>, C4<0>;
+v00000000039bb5d0_0 .net "A1", 0 0, L_0000000003f8d320;  alias, 1 drivers
+v00000000039bc4d0_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039bccf0_0 .net "B1", 0 0, L_0000000004127f50;  alias, 1 drivers
+v00000000039bc570_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039bb490_0 .net "C1", 0 0, L_0000000004127150;  alias, 1 drivers
+L_0000000003fd10f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bc250_0 .net8 "VGND", 0 0, L_0000000003fd10f0;  1 drivers, strength-aware
+L_0000000003fd26d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bc610_0 .net8 "VNB", 0 0, L_0000000003fd26d0;  1 drivers, strength-aware
+L_0000000003fd1160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bc1b0_0 .net8 "VPB", 0 0, L_0000000003fd1160;  1 drivers, strength-aware
+L_0000000003fd1390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bc750_0 .net8 "VPWR", 0 0, L_0000000003fd1390;  1 drivers, strength-aware
+v00000000039bb350_0 .net "X", 0 0, L_0000000004127700;  alias, 1 drivers
+v00000000039bced0_0 .net "and0_out_X", 0 0, L_0000000004126b30;  1 drivers
+v00000000039bba30_0 .net "or0_out", 0 0, L_0000000004127770;  1 drivers
+v00000000039bb670_0 .net "or1_out", 0 0, L_00000000041274d0;  1 drivers
+S_0000000002a203e0 .scope module, "_0540_" "sky130_fd_sc_hd__buf_1" 3 660, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039bcd90_0 .net "A", 0 0, L_0000000004125be0;  alias, 1 drivers
+L_0000000003fd2740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bbad0_0 .net8 "VGND", 0 0, L_0000000003fd2740;  1 drivers, strength-aware
+L_0000000003fd2270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bce30_0 .net8 "VNB", 0 0, L_0000000003fd2270;  1 drivers, strength-aware
+L_0000000003fd12b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039babd0_0 .net8 "VPB", 0 0, L_0000000003fd12b0;  1 drivers, strength-aware
+L_0000000003fd2200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bcbb0_0 .net8 "VPWR", 0 0, L_0000000003fd2200;  1 drivers, strength-aware
+v00000000039bbf30_0 .net "X", 0 0, L_0000000004126d60;  alias, 1 drivers
+S_0000000002a21ee0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a203e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126cf0 .functor BUF 1, L_0000000004125be0, C4<0>, C4<0>, C4<0>;
+L_0000000004126d60 .functor BUF 1, L_0000000004126cf0, C4<0>, C4<0>, C4<0>;
+v00000000039baa90_0 .net "A", 0 0, L_0000000004125be0;  alias, 1 drivers
+L_0000000003fd1be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bcf70_0 .net8 "VGND", 0 0, L_0000000003fd1be0;  1 drivers, strength-aware
+L_0000000003fd27b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bcb10_0 .net8 "VNB", 0 0, L_0000000003fd27b0;  1 drivers, strength-aware
+L_0000000003fd2190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bab30_0 .net8 "VPB", 0 0, L_0000000003fd2190;  1 drivers, strength-aware
+L_0000000003fd11d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bc930_0 .net8 "VPWR", 0 0, L_0000000003fd11d0;  1 drivers, strength-aware
+v00000000039bbe90_0 .net "X", 0 0, L_0000000004126d60;  alias, 1 drivers
+v00000000039bc9d0_0 .net "buf0_out_X", 0 0, L_0000000004126cf0;  1 drivers
+S_0000000002a21a60 .scope module, "_0541_" "sky130_fd_sc_hd__buf_1" 3 664, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039bb530_0 .net "A", 0 0, L_0000000004126660;  alias, 1 drivers
+L_0000000003fd1da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bb710_0 .net8 "VGND", 0 0, L_0000000003fd1da0;  1 drivers, strength-aware
+L_0000000003fd1400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bc390_0 .net8 "VNB", 0 0, L_0000000003fd1400;  1 drivers, strength-aware
+L_0000000003fd2430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bae50_0 .net8 "VPB", 0 0, L_0000000003fd2430;  1 drivers, strength-aware
+L_0000000003fd1fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bbfd0_0 .net8 "VPWR", 0 0, L_0000000003fd1fd0;  1 drivers, strength-aware
+v00000000039baf90_0 .net "X", 0 0, L_0000000004127e00;  alias, 1 drivers
+S_0000000002a227e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a21a60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127bd0 .functor BUF 1, L_0000000004126660, C4<0>, C4<0>, C4<0>;
+L_0000000004127e00 .functor BUF 1, L_0000000004127bd0, C4<0>, C4<0>, C4<0>;
+v00000000039bcc50_0 .net "A", 0 0, L_0000000004126660;  alias, 1 drivers
+L_0000000003fd2820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bb210_0 .net8 "VGND", 0 0, L_0000000003fd2820;  1 drivers, strength-aware
+L_0000000003fd22e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bad10_0 .net8 "VNB", 0 0, L_0000000003fd22e0;  1 drivers, strength-aware
+L_0000000003fd1a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bc2f0_0 .net8 "VPB", 0 0, L_0000000003fd1a90;  1 drivers, strength-aware
+L_0000000003fd14e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bb170_0 .net8 "VPWR", 0 0, L_0000000003fd14e0;  1 drivers, strength-aware
+v00000000039badb0_0 .net "X", 0 0, L_0000000004127e00;  alias, 1 drivers
+v00000000039baef0_0 .net "buf0_out_X", 0 0, L_0000000004127bd0;  1 drivers
+S_0000000002a200e0 .scope module, "_0542_" "sky130_fd_sc_hd__o22a_2" 3 668, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039bf090_0 .net "A1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v00000000039bdc90_0 .net "A2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v00000000039bf1d0_0 .net "B1", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039bd5b0_0 .net "B2", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003fd1b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bf310_0 .net8 "VGND", 0 0, L_0000000003fd1b70;  1 drivers, strength-aware
+L_0000000003fd24a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bf630_0 .net8 "VNB", 0 0, L_0000000003fd24a0;  1 drivers, strength-aware
+L_0000000003fd1c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039be2d0_0 .net8 "VPB", 0 0, L_0000000003fd1c50;  1 drivers, strength-aware
+L_0000000003fd1cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bf810_0 .net8 "VPWR", 0 0, L_0000000003fd1cc0;  1 drivers, strength-aware
+v00000000039be9b0_0 .net "X", 0 0, L_0000000004127d90;  alias, 1 drivers
+S_0000000002a23260 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000002a200e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041275b0 .functor OR 1, L_0000000004127e00, L_0000000004126d60, C4<0>, C4<0>;
+L_00000000041277e0 .functor OR 1, L_0000000004127620, L_00000000041279a0, C4<0>, C4<0>;
+L_0000000004128490 .functor AND 1, L_00000000041275b0, L_00000000041277e0, C4<1>, C4<1>;
+L_0000000004127d90 .functor BUF 1, L_0000000004128490, C4<0>, C4<0>, C4<0>;
+v00000000039bbdf0_0 .net "A1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v00000000039bb030_0 .net "A2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v00000000039bb7b0_0 .net "B1", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039bbb70_0 .net "B2", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003fd2510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bb850_0 .net8 "VGND", 0 0, L_0000000003fd2510;  1 drivers, strength-aware
+L_0000000003fd1ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bb8f0_0 .net8 "VNB", 0 0, L_0000000003fd1ef0;  1 drivers, strength-aware
+L_0000000003fd1d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bb990_0 .net8 "VPB", 0 0, L_0000000003fd1d30;  1 drivers, strength-aware
+L_0000000003fd25f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bbcb0_0 .net8 "VPWR", 0 0, L_0000000003fd25f0;  1 drivers, strength-aware
+v00000000039bbc10_0 .net "X", 0 0, L_0000000004127d90;  alias, 1 drivers
+v00000000039bbd50_0 .net "and0_out_X", 0 0, L_0000000004128490;  1 drivers
+v00000000039bc070_0 .net "or0_out", 0 0, L_00000000041275b0;  1 drivers
+v00000000039bc110_0 .net "or1_out", 0 0, L_00000000041277e0;  1 drivers
+S_0000000002a248e0 .scope module, "_0543_" "sky130_fd_sc_hd__buf_1" 3 675, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039bf8b0_0 .net "A", 0 0, L_0000000004127d90;  alias, 1 drivers
+L_0000000003fd1f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bd330_0 .net8 "VGND", 0 0, L_0000000003fd1f60;  1 drivers, strength-aware
+L_0000000003fd0de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bf130_0 .net8 "VNB", 0 0, L_0000000003fd0de0;  1 drivers, strength-aware
+L_0000000003fd0ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bddd0_0 .net8 "VPB", 0 0, L_0000000003fd0ec0;  1 drivers, strength-aware
+L_0000000003fd2dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bde70_0 .net8 "VPWR", 0 0, L_0000000003fd2dd0;  1 drivers, strength-aware
+v00000000039bd970_0 .net "X", 0 0, L_0000000004128110;  alias, 1 drivers
+S_0000000002a22060 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000002a248e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004127cb0 .functor BUF 1, L_0000000004127d90, C4<0>, C4<0>, C4<0>;
+L_0000000004128110 .functor BUF 1, L_0000000004127cb0, C4<0>, C4<0>, C4<0>;
+v00000000039be690_0 .net "A", 0 0, L_0000000004127d90;  alias, 1 drivers
+L_0000000003fd29e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bf450_0 .net8 "VGND", 0 0, L_0000000003fd29e0;  1 drivers, strength-aware
+L_0000000003fd3620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bdf10_0 .net8 "VNB", 0 0, L_0000000003fd3620;  1 drivers, strength-aware
+L_0000000003fd31c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bdd30_0 .net8 "VPB", 0 0, L_0000000003fd31c0;  1 drivers, strength-aware
+L_0000000003fd3a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039beff0_0 .net8 "VPWR", 0 0, L_0000000003fd3a80;  1 drivers, strength-aware
+v00000000039bd290_0 .net "X", 0 0, L_0000000004128110;  alias, 1 drivers
+v00000000039be910_0 .net "buf0_out_X", 0 0, L_0000000004127cb0;  1 drivers
+S_0000000002a257e0 .scope module, "_0544_" "sky130_fd_sc_hd__nand2_2" 3 679, 4 8552 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039be410_0 .net "A", 0 0, L_0000000004127700;  alias, 1 drivers
+v00000000039be4b0_0 .net "B", 0 0, L_0000000004128110;  alias, 1 drivers
+L_0000000003fd3230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039becd0_0 .net8 "VGND", 0 0, L_0000000003fd3230;  1 drivers, strength-aware
+L_0000000003fd3e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bed70_0 .net8 "VNB", 0 0, L_0000000003fd3e70;  1 drivers, strength-aware
+L_0000000003fd3460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bf4f0_0 .net8 "VPB", 0 0, L_0000000003fd3460;  1 drivers, strength-aware
+L_0000000003fd3e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bd150_0 .net8 "VPWR", 0 0, L_0000000003fd3e00;  1 drivers, strength-aware
+v00000000039be050_0 .net "Y", 0 0, L_0000000004126e40;  alias, 1 drivers
+S_0000000002a25f60 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000002a257e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004126c80 .functor NAND 1, L_0000000004128110, L_0000000004127700, C4<1>, C4<1>;
+L_0000000004126e40 .functor BUF 1, L_0000000004126c80, C4<0>, C4<0>, C4<0>;
+v00000000039be730_0 .net "A", 0 0, L_0000000004127700;  alias, 1 drivers
+v00000000039bf270_0 .net "B", 0 0, L_0000000004128110;  alias, 1 drivers
+L_0000000003fd3070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bd830_0 .net8 "VGND", 0 0, L_0000000003fd3070;  1 drivers, strength-aware
+L_0000000003fd2b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bdfb0_0 .net8 "VNB", 0 0, L_0000000003fd2b30;  1 drivers, strength-aware
+L_0000000003fd32a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bd6f0_0 .net8 "VPB", 0 0, L_0000000003fd32a0;  1 drivers, strength-aware
+L_0000000003fd3150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bf3b0_0 .net8 "VPWR", 0 0, L_0000000003fd3150;  1 drivers, strength-aware
+v00000000039bd650_0 .net "Y", 0 0, L_0000000004126e40;  alias, 1 drivers
+v00000000039bf6d0_0 .net "nand0_out_Y", 0 0, L_0000000004126c80;  1 drivers
+S_0000000002a233e0 .scope module, "_0545_" "sky130_fd_sc_hd__a221oi_2" 3 684, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039bf590_0 .net "A1", 0 0, L_0000000004127f50;  alias, 1 drivers
+v00000000039bd510_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039bd790_0 .net "B1", 0 0, L_0000000003f8de60;  1 drivers
+v00000000039bd8d0_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039be230_0 .net "C1", 0 0, L_0000000004127150;  alias, 1 drivers
+L_0000000003fd35b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bda10_0 .net8 "VGND", 0 0, L_0000000003fd35b0;  1 drivers, strength-aware
+L_0000000003fd3310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bdab0_0 .net8 "VNB", 0 0, L_0000000003fd3310;  1 drivers, strength-aware
+L_0000000003fd39a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039beaf0_0 .net8 "VPB", 0 0, L_0000000003fd39a0;  1 drivers, strength-aware
+L_0000000003fd2900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bdb50_0 .net8 "VPWR", 0 0, L_0000000003fd2900;  1 drivers, strength-aware
+v00000000039beb90_0 .net "Y", 0 0, L_0000000004128340;  alias, 1 drivers
+S_0000000002a24460 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000002a233e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004128180 .functor AND 1, L_0000000003f8de60, L_0000000004128260, C4<1>, C4<1>;
+L_00000000041281f0 .functor AND 1, L_0000000004127f50, L_0000000004127e70, C4<1>, C4<1>;
+L_00000000041282d0 .functor NOR 1, L_0000000004128180, L_0000000004127150, L_00000000041281f0, C4<0>;
+L_0000000004128340 .functor BUF 1, L_00000000041282d0, C4<0>, C4<0>, C4<0>;
+v00000000039bd1f0_0 .net "A1", 0 0, L_0000000004127f50;  alias, 1 drivers
+v00000000039bea50_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039be550_0 .net "B1", 0 0, L_0000000003f8de60;  alias, 1 drivers
+v00000000039be5f0_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039be0f0_0 .net "C1", 0 0, L_0000000004127150;  alias, 1 drivers
+L_0000000003fd3a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039be7d0_0 .net8 "VGND", 0 0, L_0000000003fd3a10;  1 drivers, strength-aware
+L_0000000003fd37e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bd3d0_0 .net8 "VNB", 0 0, L_0000000003fd37e0;  1 drivers, strength-aware
+L_0000000003fd3ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039be370_0 .net8 "VPB", 0 0, L_0000000003fd3ee0;  1 drivers, strength-aware
+L_0000000003fd3cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bd470_0 .net8 "VPWR", 0 0, L_0000000003fd3cb0;  1 drivers, strength-aware
+v00000000039be190_0 .net "Y", 0 0, L_0000000004128340;  alias, 1 drivers
+v00000000039bdbf0_0 .net "and0_out", 0 0, L_0000000004128180;  1 drivers
+v00000000039be870_0 .net "and1_out", 0 0, L_00000000041281f0;  1 drivers
+v00000000039bf770_0 .net "nor0_out_Y", 0 0, L_00000000041282d0;  1 drivers
+S_0000000002a254e0 .scope module, "_0546_" "sky130_fd_sc_hd__nor2_2" 3 692, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039c0530_0 .net "A", 0 0, L_0000000004127700;  alias, 1 drivers
+v00000000039c14d0_0 .net "B", 0 0, L_0000000004128340;  alias, 1 drivers
+L_0000000003fd3af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1570_0 .net8 "VGND", 0 0, L_0000000003fd3af0;  1 drivers, strength-aware
+L_0000000003fd4340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c11b0_0 .net8 "VNB", 0 0, L_0000000003fd4340;  1 drivers, strength-aware
+L_0000000003fd42d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c12f0_0 .net8 "VPB", 0 0, L_0000000003fd42d0;  1 drivers, strength-aware
+L_0000000003fd3c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c03f0_0 .net8 "VPWR", 0 0, L_0000000003fd3c40;  1 drivers, strength-aware
+v00000000039bfb30_0 .net "Y", 0 0, L_0000000004126f20;  alias, 1 drivers
+S_0000000002a20ce0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000002a254e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004126eb0 .functor NOR 1, L_0000000004127700, L_0000000004128340, C4<0>, C4<0>;
+L_0000000004126f20 .functor BUF 1, L_0000000004126eb0, C4<0>, C4<0>, C4<0>;
+v00000000039bec30_0 .net "A", 0 0, L_0000000004127700;  alias, 1 drivers
+v00000000039bee10_0 .net "B", 0 0, L_0000000004128340;  alias, 1 drivers
+L_0000000003fd3b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039beeb0_0 .net8 "VGND", 0 0, L_0000000003fd3b60;  1 drivers, strength-aware
+L_0000000003fd3f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bef50_0 .net8 "VNB", 0 0, L_0000000003fd3f50;  1 drivers, strength-aware
+L_0000000003fd3bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1430_0 .net8 "VPB", 0 0, L_0000000003fd3bd0;  1 drivers, strength-aware
+L_0000000003fd3380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1250_0 .net8 "VPWR", 0 0, L_0000000003fd3380;  1 drivers, strength-aware
+v00000000039c0850_0 .net "Y", 0 0, L_0000000004126f20;  alias, 1 drivers
+v00000000039c08f0_0 .net "nor0_out_Y", 0 0, L_0000000004126eb0;  1 drivers
+S_0000000002a25ae0 .scope module, "_0547_" "sky130_fd_sc_hd__inv_2" 3 697, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039bfbd0_0 .net "A", 0 0, L_0000000003f8d640;  1 drivers
+L_0000000003fd2d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1d90_0 .net8 "VGND", 0 0, L_0000000003fd2d60;  1 drivers, strength-aware
+L_0000000003fd2ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1a70_0 .net8 "VNB", 0 0, L_0000000003fd2ac0;  1 drivers, strength-aware
+L_0000000003fd2ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1890_0 .net8 "VPB", 0 0, L_0000000003fd2ba0;  1 drivers, strength-aware
+L_0000000003fd3770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c0490_0 .net8 "VPWR", 0 0, L_0000000003fd3770;  1 drivers, strength-aware
+v00000000039c1cf0_0 .net "Y", 0 0, L_0000000004127000;  alias, 1 drivers
+S_0000000002a22960 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a25ae0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004126f90 .functor NOT 1, L_0000000003f8d640, C4<0>, C4<0>, C4<0>;
+L_0000000004127000 .functor BUF 1, L_0000000004126f90, C4<0>, C4<0>, C4<0>;
+v00000000039c05d0_0 .net "A", 0 0, L_0000000003f8d640;  alias, 1 drivers
+L_0000000003fd41f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1bb0_0 .net8 "VGND", 0 0, L_0000000003fd41f0;  1 drivers, strength-aware
+L_0000000003fd33f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c16b0_0 .net8 "VNB", 0 0, L_0000000003fd33f0;  1 drivers, strength-aware
+L_0000000003fd4180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c00d0_0 .net8 "VPB", 0 0, L_0000000003fd4180;  1 drivers, strength-aware
+L_0000000003fd3fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1750_0 .net8 "VPWR", 0 0, L_0000000003fd3fc0;  1 drivers, strength-aware
+v00000000039c20b0_0 .net "Y", 0 0, L_0000000004127000;  alias, 1 drivers
+v00000000039c0a30_0 .net "not0_out_Y", 0 0, L_0000000004126f90;  1 drivers
+S_0000000002a25960 .scope module, "_0548_" "sky130_fd_sc_hd__a2bb2o_2" 3 701, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039c07b0_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039c0c10_0 .net "A2_N", 0 0, L_0000000003f8d780;  1 drivers
+v00000000039c19d0_0 .net "B1", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039c1b10_0 .net "B2", 0 0, L_0000000003f8d820;  1 drivers
+L_0000000003fd3d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c0990_0 .net8 "VGND", 0 0, L_0000000003fd3d90;  1 drivers, strength-aware
+L_0000000003fd40a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1c50_0 .net8 "VNB", 0 0, L_0000000003fd40a0;  1 drivers, strength-aware
+L_0000000003fd4030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1e30_0 .net8 "VPB", 0 0, L_0000000003fd4030;  1 drivers, strength-aware
+L_0000000003fd34d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1ed0_0 .net8 "VPWR", 0 0, L_0000000003fd34d0;  1 drivers, strength-aware
+v00000000039c1f70_0 .net "X", 0 0, L_0000000004129450;  alias, 1 drivers
+S_0000000002a25de0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002a25960;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004127070 .functor AND 1, L_00000000041280a0, L_0000000003f8d820, C4<1>, C4<1>;
+L_00000000041288f0 .functor NOR 1, L_00000000041280a0, L_0000000003f8d780, C4<0>, C4<0>;
+L_0000000004129990 .functor OR 1, L_00000000041288f0, L_0000000004127070, C4<0>, C4<0>;
+L_0000000004129450 .functor BUF 1, L_0000000004129990, C4<0>, C4<0>, C4<0>;
+v00000000039c0d50_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039c0210_0 .net "A2_N", 0 0, L_0000000003f8d780;  alias, 1 drivers
+v00000000039bfef0_0 .net "B1", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039bfe50_0 .net "B2", 0 0, L_0000000003f8d820;  alias, 1 drivers
+L_0000000003fd3540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c02b0_0 .net8 "VGND", 0 0, L_0000000003fd3540;  1 drivers, strength-aware
+L_0000000003fd3690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c0ad0_0 .net8 "VNB", 0 0, L_0000000003fd3690;  1 drivers, strength-aware
+L_0000000003fd3d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c17f0_0 .net8 "VPB", 0 0, L_0000000003fd3d20;  1 drivers, strength-aware
+L_0000000003fd4260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c1390_0 .net8 "VPWR", 0 0, L_0000000003fd4260;  1 drivers, strength-aware
+v00000000039c0670_0 .net "X", 0 0, L_0000000004129450;  alias, 1 drivers
+v00000000039c1930_0 .net "and0_out", 0 0, L_0000000004127070;  1 drivers
+v00000000039c1610_0 .net "nor0_out", 0 0, L_00000000041288f0;  1 drivers
+v00000000039c0710_0 .net "or0_out_X", 0 0, L_0000000004129990;  1 drivers
+S_0000000002a22c60 .scope module, "_0549_" "sky130_fd_sc_hd__o221a_2" 3 708, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039c0170_0 .net "A1", 0 0, L_0000000003f8d8c0;  1 drivers
+v00000000039c0e90_0 .net "A2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039c0f30_0 .net "B1", 0 0, L_0000000004127000;  alias, 1 drivers
+v00000000039c0fd0_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039c1070_0 .net "C1", 0 0, L_0000000004129450;  alias, 1 drivers
+L_0000000003fd2e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c1110_0 .net8 "VGND", 0 0, L_0000000003fd2e40;  1 drivers, strength-aware
+L_0000000003fd3700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3ff0_0 .net8 "VNB", 0 0, L_0000000003fd3700;  1 drivers, strength-aware
+L_0000000003fd4110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c3690_0 .net8 "VPB", 0 0, L_0000000003fd4110;  1 drivers, strength-aware
+L_0000000003fd43b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4090_0 .net8 "VPWR", 0 0, L_0000000003fd43b0;  1 drivers, strength-aware
+v00000000039c2470_0 .net "X", 0 0, L_0000000004128730;  alias, 1 drivers
+S_0000000002a24a60 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000002a22c60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004129370 .functor OR 1, L_0000000004128260, L_0000000004127000, C4<0>, C4<0>;
+L_0000000004129df0 .functor OR 1, L_0000000004127230, L_0000000003f8d8c0, C4<0>, C4<0>;
+L_0000000004129840 .functor AND 1, L_0000000004129370, L_0000000004129df0, L_0000000004129450, C4<1>;
+L_0000000004128730 .functor BUF 1, L_0000000004129840, C4<0>, C4<0>, C4<0>;
+v00000000039c0350_0 .net "A1", 0 0, L_0000000003f8d8c0;  alias, 1 drivers
+v00000000039c2010_0 .net "A2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039c0b70_0 .net "B1", 0 0, L_0000000004127000;  alias, 1 drivers
+v00000000039bf950_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039bf9f0_0 .net "C1", 0 0, L_0000000004129450;  alias, 1 drivers
+L_0000000003fd4420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039bfa90_0 .net8 "VGND", 0 0, L_0000000003fd4420;  1 drivers, strength-aware
+L_0000000003fd30e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c0cb0_0 .net8 "VNB", 0 0, L_0000000003fd30e0;  1 drivers, strength-aware
+L_0000000003fd2890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c0df0_0 .net8 "VPB", 0 0, L_0000000003fd2890;  1 drivers, strength-aware
+L_0000000003fd3850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039bfc70_0 .net8 "VPWR", 0 0, L_0000000003fd3850;  1 drivers, strength-aware
+v00000000039bfd10_0 .net "X", 0 0, L_0000000004128730;  alias, 1 drivers
+v00000000039bfdb0_0 .net "and0_out_X", 0 0, L_0000000004129840;  1 drivers
+v00000000039bff90_0 .net "or0_out", 0 0, L_0000000004129370;  1 drivers
+v00000000039c0030_0 .net "or1_out", 0 0, L_0000000004129df0;  1 drivers
+S_0000000002a20fe0 .scope module, "_0550_" "sky130_fd_sc_hd__and2_2" 3 716, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039c3d70_0 .net "A", 0 0, L_0000000004126f20;  alias, 1 drivers
+v00000000039c2dd0_0 .net "B", 0 0, L_0000000004128730;  alias, 1 drivers
+L_0000000003fd2970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3cd0_0 .net8 "VGND", 0 0, L_0000000003fd2970;  1 drivers, strength-aware
+L_0000000003fd2a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c2e70_0 .net8 "VNB", 0 0, L_0000000003fd2a50;  1 drivers, strength-aware
+L_0000000003fd2c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4810_0 .net8 "VPB", 0 0, L_0000000003fd2c10;  1 drivers, strength-aware
+L_0000000003fd38c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4770_0 .net8 "VPWR", 0 0, L_0000000003fd38c0;  1 drivers, strength-aware
+v00000000039c37d0_0 .net "X", 0 0, L_00000000041298b0;  alias, 1 drivers
+S_0000000002a25c60 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000002a20fe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004129220 .functor AND 1, L_0000000004126f20, L_0000000004128730, C4<1>, C4<1>;
+L_00000000041298b0 .functor BUF 1, L_0000000004129220, C4<0>, C4<0>, C4<0>;
+v00000000039c4130_0 .net "A", 0 0, L_0000000004126f20;  alias, 1 drivers
+v00000000039c2830_0 .net "B", 0 0, L_0000000004128730;  alias, 1 drivers
+L_0000000003fd2eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c2fb0_0 .net8 "VGND", 0 0, L_0000000003fd2eb0;  1 drivers, strength-aware
+L_0000000003fd2c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3af0_0 .net8 "VNB", 0 0, L_0000000003fd2c80;  1 drivers, strength-aware
+L_0000000003fd3930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4270_0 .net8 "VPB", 0 0, L_0000000003fd3930;  1 drivers, strength-aware
+L_0000000003fd2cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c2a10_0 .net8 "VPWR", 0 0, L_0000000003fd2cf0;  1 drivers, strength-aware
+v00000000039c2d30_0 .net "X", 0 0, L_00000000041298b0;  alias, 1 drivers
+v00000000039c3730_0 .net "and0_out_X", 0 0, L_0000000004129220;  1 drivers
+S_0000000002a206e0 .scope module, "_0551_" "sky130_fd_sc_hd__inv_2" 3 721, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039c48b0_0 .net "A", 0 0, L_0000000003f8d960;  1 drivers
+L_0000000003fd2f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3870_0 .net8 "VGND", 0 0, L_0000000003fd2f20;  1 drivers, strength-aware
+L_0000000003fd2f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c32d0_0 .net8 "VNB", 0 0, L_0000000003fd2f90;  1 drivers, strength-aware
+L_0000000003fd3000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c3e10_0 .net8 "VPB", 0 0, L_0000000003fd3000;  1 drivers, strength-aware
+L_0000000003fd5060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c3370_0 .net8 "VPWR", 0 0, L_0000000003fd5060;  1 drivers, strength-aware
+v00000000039c3f50_0 .net "Y", 0 0, L_0000000004129610;  alias, 1 drivers
+S_0000000002a21460 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a206e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004129f40 .functor NOT 1, L_0000000003f8d960, C4<0>, C4<0>, C4<0>;
+L_0000000004129610 .functor BUF 1, L_0000000004129f40, C4<0>, C4<0>, C4<0>;
+v00000000039c3a50_0 .net "A", 0 0, L_0000000003f8d960;  alias, 1 drivers
+L_0000000003fd4490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3410_0 .net8 "VGND", 0 0, L_0000000003fd4490;  1 drivers, strength-aware
+L_0000000003fd4500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c35f0_0 .net8 "VNB", 0 0, L_0000000003fd4500;  1 drivers, strength-aware
+L_0000000003fd58b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4450_0 .net8 "VPB", 0 0, L_0000000003fd58b0;  1 drivers, strength-aware
+L_0000000003fd4960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c3550_0 .net8 "VPWR", 0 0, L_0000000003fd4960;  1 drivers, strength-aware
+v00000000039c34b0_0 .net "Y", 0 0, L_0000000004129610;  alias, 1 drivers
+v00000000039c3eb0_0 .net "not0_out_Y", 0 0, L_0000000004129f40;  1 drivers
+S_0000000002a209e0 .scope module, "_0552_" "sky130_fd_sc_hd__a2bb2o_2" 3 725, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039c39b0_0 .net "A1_N", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039c25b0_0 .net "A2_N", 0 0, L_0000000003f8daa0;  1 drivers
+v00000000039c21f0_0 .net "B1", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039c2c90_0 .net "B2", 0 0, L_0000000003f8dc80;  1 drivers
+L_0000000003fd5220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c28d0_0 .net8 "VGND", 0 0, L_0000000003fd5220;  1 drivers, strength-aware
+L_0000000003fd5610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3b90_0 .net8 "VNB", 0 0, L_0000000003fd5610;  1 drivers, strength-aware
+L_0000000003fd55a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c43b0_0 .net8 "VPB", 0 0, L_0000000003fd55a0;  1 drivers, strength-aware
+L_0000000003fd4a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4630_0 .net8 "VPWR", 0 0, L_0000000003fd4a40;  1 drivers, strength-aware
+v00000000039c46d0_0 .net "X", 0 0, L_0000000004128d50;  alias, 1 drivers
+S_0000000002a215e0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002a209e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004129680 .functor AND 1, L_0000000004126740, L_0000000003f8dc80, C4<1>, C4<1>;
+L_00000000041287a0 .functor NOR 1, L_0000000004126740, L_0000000003f8daa0, C4<0>, C4<0>;
+L_0000000004128b20 .functor OR 1, L_00000000041287a0, L_0000000004129680, C4<0>, C4<0>;
+L_0000000004128d50 .functor BUF 1, L_0000000004128b20, C4<0>, C4<0>, C4<0>;
+v00000000039c44f0_0 .net "A1_N", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039c2f10_0 .net "A2_N", 0 0, L_0000000003f8daa0;  alias, 1 drivers
+v00000000039c41d0_0 .net "B1", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039c3c30_0 .net "B2", 0 0, L_0000000003f8dc80;  alias, 1 drivers
+L_0000000003fd5b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c3050_0 .net8 "VGND", 0 0, L_0000000003fd5b50;  1 drivers, strength-aware
+L_0000000003fd57d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c30f0_0 .net8 "VNB", 0 0, L_0000000003fd57d0;  1 drivers, strength-aware
+L_0000000003fd5fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c3190_0 .net8 "VPB", 0 0, L_0000000003fd5fb0;  1 drivers, strength-aware
+L_0000000003fd5920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c26f0_0 .net8 "VPWR", 0 0, L_0000000003fd5920;  1 drivers, strength-aware
+v00000000039c4310_0 .net "X", 0 0, L_0000000004128d50;  alias, 1 drivers
+v00000000039c4590_0 .net "and0_out", 0 0, L_0000000004129680;  1 drivers
+v00000000039c2bf0_0 .net "nor0_out", 0 0, L_00000000041287a0;  1 drivers
+v00000000039c3230_0 .net "or0_out_X", 0 0, L_0000000004128b20;  1 drivers
+S_0000000002a22de0 .scope module, "_0553_" "sky130_fd_sc_hd__a221o_2" 3 732, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039c55d0_0 .net "A1", 0 0, L_0000000004129610;  alias, 1 drivers
+v00000000039c4c70_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039c6d90_0 .net "B1", 0 0, L_0000000003f914c0;  1 drivers
+v00000000039c6610_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039c6cf0_0 .net "C1", 0 0, L_0000000004128d50;  alias, 1 drivers
+L_0000000003fd51b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c4ef0_0 .net8 "VGND", 0 0, L_0000000003fd51b0;  1 drivers, strength-aware
+L_0000000003fd4c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c70b0_0 .net8 "VNB", 0 0, L_0000000003fd4c70;  1 drivers, strength-aware
+L_0000000003fd4e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c6b10_0 .net8 "VPB", 0 0, L_0000000003fd4e30;  1 drivers, strength-aware
+L_0000000003fd5840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c49f0_0 .net8 "VPWR", 0 0, L_0000000003fd5840;  1 drivers, strength-aware
+v00000000039c5490_0 .net "X", 0 0, L_00000000041285e0;  alias, 1 drivers
+S_0000000002a22f60 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000002a22de0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041296f0 .functor AND 1, L_0000000003f914c0, L_0000000004127230, C4<1>, C4<1>;
+L_0000000004128960 .functor AND 1, L_0000000004129610, L_0000000004127310, C4<1>, C4<1>;
+L_0000000004129ed0 .functor OR 1, L_0000000004128960, L_00000000041296f0, L_0000000004128d50, C4<0>;
+L_00000000041285e0 .functor BUF 1, L_0000000004129ed0, C4<0>, C4<0>, C4<0>;
+v00000000039c3910_0 .net "A1", 0 0, L_0000000004129610;  alias, 1 drivers
+v00000000039c2150_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039c2290_0 .net "B1", 0 0, L_0000000003f914c0;  alias, 1 drivers
+v00000000039c2330_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039c23d0_0 .net "C1", 0 0, L_0000000004128d50;  alias, 1 drivers
+L_0000000003fd4dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c2510_0 .net8 "VGND", 0 0, L_0000000003fd4dc0;  1 drivers, strength-aware
+L_0000000003fd4b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c2650_0 .net8 "VNB", 0 0, L_0000000003fd4b20;  1 drivers, strength-aware
+L_0000000003fd5bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c2790_0 .net8 "VPB", 0 0, L_0000000003fd5bc0;  1 drivers, strength-aware
+L_0000000003fd56f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c2970_0 .net8 "VPWR", 0 0, L_0000000003fd56f0;  1 drivers, strength-aware
+v00000000039c2ab0_0 .net "X", 0 0, L_00000000041285e0;  alias, 1 drivers
+v00000000039c2b50_0 .net "and0_out", 0 0, L_00000000041296f0;  1 drivers
+v00000000039c6a70_0 .net "and1_out", 0 0, L_0000000004128960;  1 drivers
+v00000000039c5210_0 .net "or0_out_X", 0 0, L_0000000004129ed0;  1 drivers
+S_0000000002a236e0 .scope module, "_0554_" "sky130_fd_sc_hd__inv_2" 3 740, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039c5e90_0 .net "A", 0 0, L_00000000041285e0;  alias, 1 drivers
+L_0000000003fd4f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c4d10_0 .net8 "VGND", 0 0, L_0000000003fd4f10;  1 drivers, strength-aware
+L_0000000003fd5ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c67f0_0 .net8 "VNB", 0 0, L_0000000003fd5ae0;  1 drivers, strength-aware
+L_0000000003fd50d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c6110_0 .net8 "VPB", 0 0, L_0000000003fd50d0;  1 drivers, strength-aware
+L_0000000003fd4ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4e50_0 .net8 "VPWR", 0 0, L_0000000003fd4ab0;  1 drivers, strength-aware
+v00000000039c5850_0 .net "Y", 0 0, L_0000000004129fb0;  alias, 1 drivers
+S_0000000002a23b60 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a236e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004129300 .functor NOT 1, L_00000000041285e0, C4<0>, C4<0>, C4<0>;
+L_0000000004129fb0 .functor BUF 1, L_0000000004129300, C4<0>, C4<0>, C4<0>;
+v00000000039c6bb0_0 .net "A", 0 0, L_00000000041285e0;  alias, 1 drivers
+L_0000000003fd4b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c62f0_0 .net8 "VGND", 0 0, L_0000000003fd4b90;  1 drivers, strength-aware
+L_0000000003fd49d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c5cb0_0 .net8 "VNB", 0 0, L_0000000003fd49d0;  1 drivers, strength-aware
+L_0000000003fd45e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c5530_0 .net8 "VPB", 0 0, L_0000000003fd45e0;  1 drivers, strength-aware
+L_0000000003fd5290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c64d0_0 .net8 "VPWR", 0 0, L_0000000003fd5290;  1 drivers, strength-aware
+v00000000039c5670_0 .net "Y", 0 0, L_0000000004129fb0;  alias, 1 drivers
+v00000000039c7010_0 .net "not0_out_Y", 0 0, L_0000000004129300;  1 drivers
+S_0000000002a23860 .scope module, "_0555_" "sky130_fd_sc_hd__o221a_2" 3 744, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039c6c50_0 .net "A1", 0 0, L_0000000003f91560;  1 drivers
+v00000000039c4bd0_0 .net "A2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039c5170_0 .net "B1", 0 0, L_0000000004129610;  alias, 1 drivers
+v00000000039c50d0_0 .net "B2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039c53f0_0 .net "C1", 0 0, L_0000000004128d50;  alias, 1 drivers
+L_0000000003fd4ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c5df0_0 .net8 "VGND", 0 0, L_0000000003fd4ea0;  1 drivers, strength-aware
+L_0000000003fd5680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c52b0_0 .net8 "VNB", 0 0, L_0000000003fd5680;  1 drivers, strength-aware
+L_0000000003fd4f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c5350_0 .net8 "VPB", 0 0, L_0000000003fd4f80;  1 drivers, strength-aware
+L_0000000003fd5a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c5990_0 .net8 "VPWR", 0 0, L_0000000003fd5a70;  1 drivers, strength-aware
+v00000000039c57b0_0 .net "X", 0 0, L_0000000004129bc0;  alias, 1 drivers
+S_0000000002a23e60 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000002a23860;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004129ae0 .functor OR 1, L_0000000004127e70, L_0000000004129610, C4<0>, C4<0>;
+L_0000000004129760 .functor OR 1, L_0000000004128260, L_0000000003f91560, C4<0>, C4<0>;
+L_0000000004128650 .functor AND 1, L_0000000004129ae0, L_0000000004129760, L_0000000004128d50, C4<1>;
+L_0000000004129bc0 .functor BUF 1, L_0000000004128650, C4<0>, C4<0>, C4<0>;
+v00000000039c6f70_0 .net "A1", 0 0, L_0000000003f91560;  alias, 1 drivers
+v00000000039c5b70_0 .net "A2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039c4a90_0 .net "B1", 0 0, L_0000000004129610;  alias, 1 drivers
+v00000000039c5710_0 .net "B2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039c4950_0 .net "C1", 0 0, L_0000000004128d50;  alias, 1 drivers
+L_0000000003fd4730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c5d50_0 .net8 "VGND", 0 0, L_0000000003fd4730;  1 drivers, strength-aware
+L_0000000003fd5d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c4b30_0 .net8 "VNB", 0 0, L_0000000003fd5d80;  1 drivers, strength-aware
+L_0000000003fd4570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c4f90_0 .net8 "VPB", 0 0, L_0000000003fd4570;  1 drivers, strength-aware
+L_0000000003fd5140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c58f0_0 .net8 "VPWR", 0 0, L_0000000003fd5140;  1 drivers, strength-aware
+v00000000039c5030_0 .net "X", 0 0, L_0000000004129bc0;  alias, 1 drivers
+v00000000039c6e30_0 .net "and0_out_X", 0 0, L_0000000004128650;  1 drivers
+v00000000039c4db0_0 .net "or0_out", 0 0, L_0000000004129ae0;  1 drivers
+v00000000039c6ed0_0 .net "or1_out", 0 0, L_0000000004129760;  1 drivers
+S_0000000002a23fe0 .scope module, "_0556_" "sky130_fd_sc_hd__nor2_2" 3 752, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039c6390_0 .net "A", 0 0, L_0000000004129fb0;  alias, 1 drivers
+v00000000039c6430_0 .net "B", 0 0, L_0000000004129bc0;  alias, 1 drivers
+L_0000000003fd5990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c6570_0 .net8 "VGND", 0 0, L_0000000003fd5990;  1 drivers, strength-aware
+L_0000000003fd4650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c66b0_0 .net8 "VNB", 0 0, L_0000000003fd4650;  1 drivers, strength-aware
+L_0000000003fd5300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c6750_0 .net8 "VPB", 0 0, L_0000000003fd5300;  1 drivers, strength-aware
+L_0000000003fd5370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c6890_0 .net8 "VPWR", 0 0, L_0000000003fd5370;  1 drivers, strength-aware
+v00000000039c6930_0 .net "Y", 0 0, L_0000000004128810;  alias, 1 drivers
+S_0000000002a24160 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000002a23fe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004129290 .functor NOR 1, L_0000000004129fb0, L_0000000004129bc0, C4<0>, C4<0>;
+L_0000000004128810 .functor BUF 1, L_0000000004129290, C4<0>, C4<0>, C4<0>;
+v00000000039c5a30_0 .net "A", 0 0, L_0000000004129fb0;  alias, 1 drivers
+v00000000039c5ad0_0 .net "B", 0 0, L_0000000004129bc0;  alias, 1 drivers
+L_0000000003fd4ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c61b0_0 .net8 "VGND", 0 0, L_0000000003fd4ff0;  1 drivers, strength-aware
+L_0000000003fd47a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c5f30_0 .net8 "VNB", 0 0, L_0000000003fd47a0;  1 drivers, strength-aware
+L_0000000003fd5760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c5c10_0 .net8 "VPB", 0 0, L_0000000003fd5760;  1 drivers, strength-aware
+L_0000000003fd53e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c5fd0_0 .net8 "VPWR", 0 0, L_0000000003fd53e0;  1 drivers, strength-aware
+v00000000039c6070_0 .net "Y", 0 0, L_0000000004128810;  alias, 1 drivers
+v00000000039c6250_0 .net "nor0_out_Y", 0 0, L_0000000004129290;  1 drivers
+S_0000000002a242e0 .scope module, "_0557_" "sky130_fd_sc_hd__inv_2" 3 757, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039c7dd0_0 .net "A", 0 0, L_0000000003f90340;  1 drivers
+L_0000000003fd4810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c93b0_0 .net8 "VGND", 0 0, L_0000000003fd4810;  1 drivers, strength-aware
+L_0000000003fd5a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8eb0_0 .net8 "VNB", 0 0, L_0000000003fd5a00;  1 drivers, strength-aware
+L_0000000003fd4c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c78d0_0 .net8 "VPB", 0 0, L_0000000003fd4c00;  1 drivers, strength-aware
+L_0000000003fd5450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c8f50_0 .net8 "VPWR", 0 0, L_0000000003fd5450;  1 drivers, strength-aware
+v00000000039c98b0_0 .net "Y", 0 0, L_000000000412a020;  alias, 1 drivers
+S_0000000002a245e0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a242e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041294c0 .functor NOT 1, L_0000000003f90340, C4<0>, C4<0>, C4<0>;
+L_000000000412a020 .functor BUF 1, L_00000000041294c0, C4<0>, C4<0>, C4<0>;
+v00000000039c69d0_0 .net "A", 0 0, L_0000000003f90340;  alias, 1 drivers
+L_0000000003fd46c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8d70_0 .net8 "VGND", 0 0, L_0000000003fd46c0;  1 drivers, strength-aware
+L_0000000003fd4880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c7330_0 .net8 "VNB", 0 0, L_0000000003fd4880;  1 drivers, strength-aware
+L_0000000003fd54c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c7470_0 .net8 "VPB", 0 0, L_0000000003fd54c0;  1 drivers, strength-aware
+L_0000000003fd4d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c71f0_0 .net8 "VPWR", 0 0, L_0000000003fd4d50;  1 drivers, strength-aware
+v00000000039c8230_0 .net "Y", 0 0, L_000000000412a020;  alias, 1 drivers
+v00000000039c7e70_0 .net "not0_out_Y", 0 0, L_00000000041294c0;  1 drivers
+S_0000000002a24760 .scope module, "_0558_" "sky130_fd_sc_hd__a2bb2o_2" 3 761, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039c9590_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039c82d0_0 .net "A2_N", 0 0, L_0000000003f8fe40;  1 drivers
+v00000000039c94f0_0 .net "B1", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039c75b0_0 .net "B2", 0 0, L_0000000003f90840;  1 drivers
+L_0000000003fd5c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8190_0 .net8 "VGND", 0 0, L_0000000003fd5c30;  1 drivers, strength-aware
+L_0000000003fd5530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c7510_0 .net8 "VNB", 0 0, L_0000000003fd5530;  1 drivers, strength-aware
+L_0000000003fd5ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c8a50_0 .net8 "VPB", 0 0, L_0000000003fd5ca0;  1 drivers, strength-aware
+L_0000000003fd5d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9130_0 .net8 "VPWR", 0 0, L_0000000003fd5d10;  1 drivers, strength-aware
+v00000000039c7ab0_0 .net "X", 0 0, L_00000000041293e0;  alias, 1 drivers
+S_0000000002a25060 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002a24760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004129a00 .functor AND 1, L_0000000004126c10, L_0000000003f90840, C4<1>, C4<1>;
+L_0000000004128880 .functor NOR 1, L_00000000041280a0, L_0000000003f8fe40, C4<0>, C4<0>;
+L_0000000004128e30 .functor OR 1, L_0000000004128880, L_0000000004129a00, C4<0>, C4<0>;
+L_00000000041293e0 .functor BUF 1, L_0000000004128e30, C4<0>, C4<0>, C4<0>;
+v00000000039c9090_0 .net "A1_N", 0 0, L_00000000041280a0;  alias, 1 drivers
+v00000000039c9450_0 .net "A2_N", 0 0, L_0000000003f8fe40;  alias, 1 drivers
+v00000000039c7f10_0 .net "B1", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039c7d30_0 .net "B2", 0 0, L_0000000003f90840;  alias, 1 drivers
+L_0000000003fd5e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8ff0_0 .net8 "VGND", 0 0, L_0000000003fd5e60;  1 drivers, strength-aware
+L_0000000003fd48f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c7290_0 .net8 "VNB", 0 0, L_0000000003fd48f0;  1 drivers, strength-aware
+L_0000000003fd4ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c8910_0 .net8 "VPB", 0 0, L_0000000003fd4ce0;  1 drivers, strength-aware
+L_0000000003fd5ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c7830_0 .net8 "VPWR", 0 0, L_0000000003fd5ed0;  1 drivers, strength-aware
+v00000000039c9270_0 .net "X", 0 0, L_00000000041293e0;  alias, 1 drivers
+v00000000039c73d0_0 .net "and0_out", 0 0, L_0000000004129a00;  1 drivers
+v00000000039c8e10_0 .net "nor0_out", 0 0, L_0000000004128880;  1 drivers
+v00000000039c91d0_0 .net "or0_out_X", 0 0, L_0000000004128e30;  1 drivers
+S_0000000002a251e0 .scope module, "_0559_" "sky130_fd_sc_hd__o221a_2" 3 768, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039c89b0_0 .net "A1", 0 0, L_0000000003f90520;  1 drivers
+v00000000039c8370_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039c9810_0 .net "B1", 0 0, L_000000000412a020;  alias, 1 drivers
+v00000000039c7150_0 .net "B2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v00000000039c76f0_0 .net "C1", 0 0, L_00000000041293e0;  alias, 1 drivers
+L_0000000003fd5df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8410_0 .net8 "VGND", 0 0, L_0000000003fd5df0;  1 drivers, strength-aware
+L_0000000003fd5f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c7970_0 .net8 "VNB", 0 0, L_0000000003fd5f40;  1 drivers, strength-aware
+L_0000000003fd6020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c7c90_0 .net8 "VPB", 0 0, L_0000000003fd6020;  1 drivers, strength-aware
+L_0000000003fd6c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c7a10_0 .net8 "VPWR", 0 0, L_0000000003fd6c60;  1 drivers, strength-aware
+v00000000039c8730_0 .net "X", 0 0, L_0000000004128a40;  alias, 1 drivers
+S_0000000002a25360 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000002a251e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041297d0 .functor OR 1, L_0000000004127b60, L_000000000412a020, C4<0>, C4<0>;
+L_00000000041286c0 .functor OR 1, L_0000000004126270, L_0000000003f90520, C4<0>, C4<0>;
+L_0000000004129920 .functor AND 1, L_00000000041297d0, L_00000000041286c0, L_00000000041293e0, C4<1>;
+L_0000000004128a40 .functor BUF 1, L_0000000004129920, C4<0>, C4<0>, C4<0>;
+v00000000039c8af0_0 .net "A1", 0 0, L_0000000003f90520;  alias, 1 drivers
+v00000000039c84b0_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039c7fb0_0 .net "B1", 0 0, L_000000000412a020;  alias, 1 drivers
+v00000000039c85f0_0 .net "B2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v00000000039c8050_0 .net "C1", 0 0, L_00000000041293e0;  alias, 1 drivers
+L_0000000003fd63a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c80f0_0 .net8 "VGND", 0 0, L_0000000003fd63a0;  1 drivers, strength-aware
+L_0000000003fd6cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c9770_0 .net8 "VNB", 0 0, L_0000000003fd6cd0;  1 drivers, strength-aware
+L_0000000003fd68e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c8690_0 .net8 "VPB", 0 0, L_0000000003fd68e0;  1 drivers, strength-aware
+L_0000000003fd6f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c7650_0 .net8 "VPWR", 0 0, L_0000000003fd6f00;  1 drivers, strength-aware
+v00000000039c9310_0 .net "X", 0 0, L_0000000004128a40;  alias, 1 drivers
+v00000000039c9630_0 .net "and0_out_X", 0 0, L_0000000004129920;  1 drivers
+v00000000039c7790_0 .net "or0_out", 0 0, L_00000000041297d0;  1 drivers
+v00000000039c8550_0 .net "or1_out", 0 0, L_00000000041286c0;  1 drivers
+S_0000000002a27ee0 .scope module, "_0560_" "sky130_fd_sc_hd__and2_2" 3 776, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039cb4d0_0 .net "A", 0 0, L_0000000004128810;  alias, 1 drivers
+v00000000039cb9d0_0 .net "B", 0 0, L_0000000004128a40;  alias, 1 drivers
+L_0000000003fd6b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ca2b0_0 .net8 "VGND", 0 0, L_0000000003fd6b80;  1 drivers, strength-aware
+L_0000000003fd61e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ca490_0 .net8 "VNB", 0 0, L_0000000003fd61e0;  1 drivers, strength-aware
+L_0000000003fd64f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cb2f0_0 .net8 "VPB", 0 0, L_0000000003fd64f0;  1 drivers, strength-aware
+L_0000000003fd6aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9d10_0 .net8 "VPWR", 0 0, L_0000000003fd6aa0;  1 drivers, strength-aware
+v00000000039caf30_0 .net "X", 0 0, L_00000000041295a0;  alias, 1 drivers
+S_0000000002a26860 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000002a27ee0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004129530 .functor AND 1, L_0000000004128810, L_0000000004128a40, C4<1>, C4<1>;
+L_00000000041295a0 .functor BUF 1, L_0000000004129530, C4<0>, C4<0>, C4<0>;
+v00000000039c7b50_0 .net "A", 0 0, L_0000000004128810;  alias, 1 drivers
+v00000000039c7bf0_0 .net "B", 0 0, L_0000000004128a40;  alias, 1 drivers
+L_0000000003fd6870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c87d0_0 .net8 "VGND", 0 0, L_0000000003fd6870;  1 drivers, strength-aware
+L_0000000003fd6090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039c8870_0 .net8 "VNB", 0 0, L_0000000003fd6090;  1 drivers, strength-aware
+L_0000000003fd6560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c96d0_0 .net8 "VPB", 0 0, L_0000000003fd6560;  1 drivers, strength-aware
+L_0000000003fd6d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c8b90_0 .net8 "VPWR", 0 0, L_0000000003fd6d40;  1 drivers, strength-aware
+v00000000039c8c30_0 .net "X", 0 0, L_00000000041295a0;  alias, 1 drivers
+v00000000039c8cd0_0 .net "and0_out_X", 0 0, L_0000000004129530;  1 drivers
+S_0000000002a263e0 .scope module, "_0561_" "sky130_fd_sc_hd__a221oi_2" 3 781, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039ca5d0_0 .net "A1", 0 0, L_0000000004127000;  alias, 1 drivers
+v00000000039c9db0_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039ca7b0_0 .net "B1", 0 0, L_0000000003f91e20;  1 drivers
+v00000000039c9e50_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039cbb10_0 .net "C1", 0 0, L_0000000004129450;  alias, 1 drivers
+L_0000000003fd65d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb890_0 .net8 "VGND", 0 0, L_0000000003fd65d0;  1 drivers, strength-aware
+L_0000000003fd6e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb930_0 .net8 "VNB", 0 0, L_0000000003fd6e90;  1 drivers, strength-aware
+L_0000000003fd6a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9950_0 .net8 "VPB", 0 0, L_0000000003fd6a30;  1 drivers, strength-aware
+L_0000000003fd6db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cb610_0 .net8 "VPWR", 0 0, L_0000000003fd6db0;  1 drivers, strength-aware
+v00000000039cb430_0 .net "Y", 0 0, L_0000000004128f10;  alias, 1 drivers
+S_0000000002a26ce0 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000002a263e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004128ea0 .functor AND 1, L_0000000003f91e20, L_0000000004128260, C4<1>, C4<1>;
+L_0000000004129a70 .functor AND 1, L_0000000004127000, L_0000000004127e70, C4<1>, C4<1>;
+L_0000000004128dc0 .functor NOR 1, L_0000000004128ea0, L_0000000004129450, L_0000000004129a70, C4<0>;
+L_0000000004128f10 .functor BUF 1, L_0000000004128dc0, C4<0>, C4<0>, C4<0>;
+v00000000039c9bd0_0 .net "A1", 0 0, L_0000000004127000;  alias, 1 drivers
+v00000000039caad0_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v00000000039cbc50_0 .net "B1", 0 0, L_0000000003f91e20;  alias, 1 drivers
+v00000000039cbf70_0 .net "B2", 0 0, L_0000000004128260;  alias, 1 drivers
+v00000000039c9c70_0 .net "C1", 0 0, L_0000000004129450;  alias, 1 drivers
+L_0000000003fd6640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb6b0_0 .net8 "VGND", 0 0, L_0000000003fd6640;  1 drivers, strength-aware
+L_0000000003fd6480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ca350_0 .net8 "VNB", 0 0, L_0000000003fd6480;  1 drivers, strength-aware
+L_0000000003fd6e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ca670_0 .net8 "VPB", 0 0, L_0000000003fd6e20;  1 drivers, strength-aware
+L_0000000003fd6250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ca3f0_0 .net8 "VPWR", 0 0, L_0000000003fd6250;  1 drivers, strength-aware
+v00000000039ca530_0 .net "Y", 0 0, L_0000000004128f10;  alias, 1 drivers
+v00000000039caa30_0 .net "and0_out", 0 0, L_0000000004128ea0;  1 drivers
+v00000000039ca710_0 .net "and1_out", 0 0, L_0000000004129a70;  1 drivers
+v00000000039cafd0_0 .net "nor0_out_Y", 0 0, L_0000000004128dc0;  1 drivers
+S_0000000002a26e60 .scope module, "_0562_" "sky130_fd_sc_hd__or2_2" 3 789, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039cacb0_0 .net "A", 0 0, L_0000000004128730;  alias, 1 drivers
+v00000000039cb1b0_0 .net "B", 0 0, L_0000000004128f10;  alias, 1 drivers
+L_0000000003fd6720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb390_0 .net8 "VGND", 0 0, L_0000000003fd6720;  1 drivers, strength-aware
+L_0000000003fd6f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cad50_0 .net8 "VNB", 0 0, L_0000000003fd6f70;  1 drivers, strength-aware
+L_0000000003fd66b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9b30_0 .net8 "VPB", 0 0, L_0000000003fd66b0;  1 drivers, strength-aware
+L_0000000003fd6790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9ef0_0 .net8 "VPWR", 0 0, L_0000000003fd6790;  1 drivers, strength-aware
+v00000000039c99f0_0 .net "X", 0 0, L_0000000004129c30;  alias, 1 drivers
+S_0000000002a26fe0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000002a26e60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004129b50 .functor OR 1, L_0000000004128f10, L_0000000004128730, C4<0>, C4<0>;
+L_0000000004129c30 .functor BUF 1, L_0000000004129b50, C4<0>, C4<0>, C4<0>;
+v00000000039ca850_0 .net "A", 0 0, L_0000000004128730;  alias, 1 drivers
+v00000000039cba70_0 .net "B", 0 0, L_0000000004128f10;  alias, 1 drivers
+L_0000000003fd6b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb570_0 .net8 "VGND", 0 0, L_0000000003fd6b10;  1 drivers, strength-aware
+L_0000000003fd6410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb250_0 .net8 "VNB", 0 0, L_0000000003fd6410;  1 drivers, strength-aware
+L_0000000003fd6100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ca8f0_0 .net8 "VPB", 0 0, L_0000000003fd6100;  1 drivers, strength-aware
+L_0000000003fd62c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ca990_0 .net8 "VPWR", 0 0, L_0000000003fd62c0;  1 drivers, strength-aware
+v00000000039cab70_0 .net "X", 0 0, L_0000000004129c30;  alias, 1 drivers
+v00000000039cac10_0 .net "or0_out_X", 0 0, L_0000000004129b50;  1 drivers
+S_0000000002a27be0 .scope module, "_0563_" "sky130_fd_sc_hd__inv_2" 3 794, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039cb7f0_0 .net "A", 0 0, L_0000000004129c30;  alias, 1 drivers
+L_0000000003fd6170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cbbb0_0 .net8 "VGND", 0 0, L_0000000003fd6170;  1 drivers, strength-aware
+L_0000000003fd6330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cbcf0_0 .net8 "VNB", 0 0, L_0000000003fd6330;  1 drivers, strength-aware
+L_0000000003fd6800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cb110_0 .net8 "VPB", 0 0, L_0000000003fd6800;  1 drivers, strength-aware
+L_0000000003fd6950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cbd90_0 .net8 "VPWR", 0 0, L_0000000003fd6950;  1 drivers, strength-aware
+v00000000039cbe30_0 .net "Y", 0 0, L_000000000412a090;  alias, 1 drivers
+S_0000000002a269e0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a27be0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004129ca0 .functor NOT 1, L_0000000004129c30, C4<0>, C4<0>, C4<0>;
+L_000000000412a090 .functor BUF 1, L_0000000004129ca0, C4<0>, C4<0>, C4<0>;
+v00000000039cadf0_0 .net "A", 0 0, L_0000000004129c30;  alias, 1 drivers
+L_0000000003fd69c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cbed0_0 .net8 "VGND", 0 0, L_0000000003fd69c0;  1 drivers, strength-aware
+L_0000000003fd6bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cb750_0 .net8 "VNB", 0 0, L_0000000003fd6bf0;  1 drivers, strength-aware
+L_0000000003fd8fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc0b0_0 .net8 "VPB", 0 0, L_0000000003fd8fd0;  1 drivers, strength-aware
+L_0000000003fd9a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039c9a90_0 .net8 "VPWR", 0 0, L_0000000003fd9a50;  1 drivers, strength-aware
+v00000000039cae90_0 .net "Y", 0 0, L_000000000412a090;  alias, 1 drivers
+v00000000039cb070_0 .net "not0_out_Y", 0 0, L_0000000004129ca0;  1 drivers
+S_0000000002a27d60 .scope module, "_0564_" "sky130_fd_sc_hd__o21a_2" 3 798, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v00000000039ccb50_0 .net "A1", 0 0, L_0000000004129fb0;  alias, 1 drivers
+v00000000039cce70_0 .net "A2", 0 0, L_00000000041295a0;  alias, 1 drivers
+v00000000039ccbf0_0 .net "B1", 0 0, L_000000000412a090;  alias, 1 drivers
+L_0000000003fda380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cd4b0_0 .net8 "VGND", 0 0, L_0000000003fda380;  1 drivers, strength-aware
+L_0000000003fda000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce770_0 .net8 "VNB", 0 0, L_0000000003fda000;  1 drivers, strength-aware
+L_0000000003fda7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ccfb0_0 .net8 "VPB", 0 0, L_0000000003fda7e0;  1 drivers, strength-aware
+L_0000000003fda0e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cd7d0_0 .net8 "VPWR", 0 0, L_0000000003fda0e0;  1 drivers, strength-aware
+v00000000039cc6f0_0 .net "X", 0 0, L_0000000004128570;  alias, 1 drivers
+S_0000000002a260e0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000002a27d60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004128500 .functor OR 1, L_00000000041295a0, L_0000000004129fb0, C4<0>, C4<0>;
+L_0000000004128f80 .functor AND 1, L_0000000004128500, L_000000000412a090, C4<1>, C4<1>;
+L_0000000004128570 .functor BUF 1, L_0000000004128f80, C4<0>, C4<0>, C4<0>;
+v00000000039cc010_0 .net "A1", 0 0, L_0000000004129fb0;  alias, 1 drivers
+v00000000039c9f90_0 .net "A2", 0 0, L_00000000041295a0;  alias, 1 drivers
+v00000000039ca030_0 .net "B1", 0 0, L_000000000412a090;  alias, 1 drivers
+L_0000000003fd99e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ca0d0_0 .net8 "VGND", 0 0, L_0000000003fd99e0;  1 drivers, strength-aware
+L_0000000003fd94a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ca170_0 .net8 "VNB", 0 0, L_0000000003fd94a0;  1 drivers, strength-aware
+L_0000000003fd9660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ca210_0 .net8 "VPB", 0 0, L_0000000003fd9660;  1 drivers, strength-aware
+L_0000000003fda070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc3d0_0 .net8 "VPWR", 0 0, L_0000000003fda070;  1 drivers, strength-aware
+v00000000039cd5f0_0 .net "X", 0 0, L_0000000004128570;  alias, 1 drivers
+v00000000039ccf10_0 .net "and0_out_X", 0 0, L_0000000004128f80;  1 drivers
+v00000000039cd550_0 .net "or0_out", 0 0, L_0000000004128500;  1 drivers
+S_0000000002a26b60 .scope module, "_0565_" "sky130_fd_sc_hd__inv_2" 3 804, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039cca10_0 .net "A", 0 0, L_0000000003f90020;  1 drivers
+L_0000000003fd95f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cdeb0_0 .net8 "VGND", 0 0, L_0000000003fd95f0;  1 drivers, strength-aware
+L_0000000003fd9350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cdaf0_0 .net8 "VNB", 0 0, L_0000000003fd9350;  1 drivers, strength-aware
+L_0000000003fda3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc150_0 .net8 "VPB", 0 0, L_0000000003fda3f0;  1 drivers, strength-aware
+L_0000000003fd9f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ce130_0 .net8 "VPWR", 0 0, L_0000000003fd9f20;  1 drivers, strength-aware
+v00000000039cd9b0_0 .net "Y", 0 0, L_0000000004128ff0;  alias, 1 drivers
+S_0000000002a27160 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a26b60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004129d10 .functor NOT 1, L_0000000003f90020, C4<0>, C4<0>, C4<0>;
+L_0000000004128ff0 .functor BUF 1, L_0000000004129d10, C4<0>, C4<0>, C4<0>;
+v00000000039cd870_0 .net "A", 0 0, L_0000000003f90020;  alias, 1 drivers
+L_0000000003fd9740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce090_0 .net8 "VGND", 0 0, L_0000000003fd9740;  1 drivers, strength-aware
+L_0000000003fda310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce810_0 .net8 "VNB", 0 0, L_0000000003fda310;  1 drivers, strength-aware
+L_0000000003fd9900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cd2d0_0 .net8 "VPB", 0 0, L_0000000003fd9900;  1 drivers, strength-aware
+L_0000000003fd92e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cd690_0 .net8 "VPWR", 0 0, L_0000000003fd92e0;  1 drivers, strength-aware
+v00000000039ce450_0 .net "Y", 0 0, L_0000000004128ff0;  alias, 1 drivers
+v00000000039cc790_0 .net "not0_out_Y", 0 0, L_0000000004129d10;  1 drivers
+S_0000000002a275e0 .scope module, "_0566_" "sky130_fd_sc_hd__a2bb2o_2" 3 808, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039cdf50_0 .net "A1_N", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039ce8b0_0 .net "A2_N", 0 0, L_0000000003f91ec0;  1 drivers
+v00000000039cdff0_0 .net "B1", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039ce630_0 .net "B2", 0 0, L_0000000003f90160;  1 drivers
+L_0000000003fd93c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cc830_0 .net8 "VGND", 0 0, L_0000000003fd93c0;  1 drivers, strength-aware
+L_0000000003fd9200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce1d0_0 .net8 "VNB", 0 0, L_0000000003fd9200;  1 drivers, strength-aware
+L_0000000003fd8e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc1f0_0 .net8 "VPB", 0 0, L_0000000003fd8e10;  1 drivers, strength-aware
+L_0000000003fd9ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ccd30_0 .net8 "VPWR", 0 0, L_0000000003fd9ac0;  1 drivers, strength-aware
+v00000000039cdcd0_0 .net "X", 0 0, L_0000000004128ab0;  alias, 1 drivers
+S_0000000002a272e0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002a275e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004129d80 .functor AND 1, L_0000000004126740, L_0000000003f90160, C4<1>, C4<1>;
+L_00000000041289d0 .functor NOR 1, L_0000000004126740, L_0000000003f91ec0, C4<0>, C4<0>;
+L_0000000004129e60 .functor OR 1, L_00000000041289d0, L_0000000004129d80, C4<0>, C4<0>;
+L_0000000004128ab0 .functor BUF 1, L_0000000004129e60, C4<0>, C4<0>, C4<0>;
+v00000000039cdc30_0 .net "A1_N", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039cdd70_0 .net "A2_N", 0 0, L_0000000003f91ec0;  alias, 1 drivers
+v00000000039cda50_0 .net "B1", 0 0, L_0000000004126740;  alias, 1 drivers
+v00000000039cdb90_0 .net "B2", 0 0, L_0000000003f90160;  alias, 1 drivers
+L_0000000003fd96d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cde10_0 .net8 "VGND", 0 0, L_0000000003fd96d0;  1 drivers, strength-aware
+L_0000000003fd9eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cc330_0 .net8 "VNB", 0 0, L_0000000003fd9eb0;  1 drivers, strength-aware
+L_0000000003fd97b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc5b0_0 .net8 "VPB", 0 0, L_0000000003fd97b0;  1 drivers, strength-aware
+L_0000000003fda2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ccc90_0 .net8 "VPWR", 0 0, L_0000000003fda2a0;  1 drivers, strength-aware
+v00000000039ce6d0_0 .net "X", 0 0, L_0000000004128ab0;  alias, 1 drivers
+v00000000039cc8d0_0 .net "and0_out", 0 0, L_0000000004129d80;  1 drivers
+v00000000039ce3b0_0 .net "nor0_out", 0 0, L_00000000041289d0;  1 drivers
+v00000000039cc470_0 .net "or0_out_X", 0 0, L_0000000004129e60;  1 drivers
+S_0000000002a27460 .scope module, "_0567_" "sky130_fd_sc_hd__a221o_2" 3 815, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039cd230_0 .net "A1", 0 0, L_0000000004128ff0;  alias, 1 drivers
+v00000000039cd370_0 .net "A2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v00000000039cd410_0 .net "B1", 0 0, L_0000000003f91a60;  1 drivers
+v00000000039cd730_0 .net "B2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039cd910_0 .net "C1", 0 0, L_0000000004128ab0;  alias, 1 drivers
+L_0000000003fd8f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cf850_0 .net8 "VGND", 0 0, L_0000000003fd8f60;  1 drivers, strength-aware
+L_0000000003fda5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d01b0_0 .net8 "VNB", 0 0, L_0000000003fda5b0;  1 drivers, strength-aware
+L_0000000003fd8cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf210_0 .net8 "VPB", 0 0, L_0000000003fd8cc0;  1 drivers, strength-aware
+L_0000000003fd9970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf530_0 .net8 "VPWR", 0 0, L_0000000003fd9970;  1 drivers, strength-aware
+v00000000039cebd0_0 .net "X", 0 0, L_0000000004128c70;  alias, 1 drivers
+S_0000000002a266e0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000002a27460;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004128b90 .functor AND 1, L_0000000003f91a60, L_0000000004126270, C4<1>, C4<1>;
+L_0000000004129060 .functor AND 1, L_0000000004128ff0, L_0000000004127b60, C4<1>, C4<1>;
+L_0000000004128c00 .functor OR 1, L_0000000004129060, L_0000000004128b90, L_0000000004128ab0, C4<0>;
+L_0000000004128c70 .functor BUF 1, L_0000000004128c00, C4<0>, C4<0>, C4<0>;
+v00000000039ce4f0_0 .net "A1", 0 0, L_0000000004128ff0;  alias, 1 drivers
+v00000000039cc970_0 .net "A2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v00000000039ce270_0 .net "B1", 0 0, L_0000000003f91a60;  alias, 1 drivers
+v00000000039cc290_0 .net "B2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039ccdd0_0 .net "C1", 0 0, L_0000000004128ab0;  alias, 1 drivers
+L_0000000003fda150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce310_0 .net8 "VGND", 0 0, L_0000000003fda150;  1 drivers, strength-aware
+L_0000000003fd8e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cd050_0 .net8 "VNB", 0 0, L_0000000003fd8e80;  1 drivers, strength-aware
+L_0000000003fd9b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cd0f0_0 .net8 "VPB", 0 0, L_0000000003fd9b30;  1 drivers, strength-aware
+L_0000000003fd9ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cc510_0 .net8 "VPWR", 0 0, L_0000000003fd9ba0;  1 drivers, strength-aware
+v00000000039ce590_0 .net "X", 0 0, L_0000000004128c70;  alias, 1 drivers
+v00000000039cc650_0 .net "and0_out", 0 0, L_0000000004128b90;  1 drivers
+v00000000039ccab0_0 .net "and1_out", 0 0, L_0000000004129060;  1 drivers
+v00000000039cd190_0 .net "or0_out_X", 0 0, L_0000000004128c00;  1 drivers
+S_0000000002a27760 .scope module, "_0568_" "sky130_fd_sc_hd__inv_2" 3 823, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039d0d90_0 .net "A", 0 0, L_0000000004128c70;  alias, 1 drivers
+L_0000000003fd9820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cedb0_0 .net8 "VGND", 0 0, L_0000000003fd9820;  1 drivers, strength-aware
+L_0000000003fda460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cf5d0_0 .net8 "VNB", 0 0, L_0000000003fda460;  1 drivers, strength-aware
+L_0000000003fd9430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf490_0 .net8 "VPB", 0 0, L_0000000003fd9430;  1 drivers, strength-aware
+L_0000000003fda620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d09d0_0 .net8 "VPWR", 0 0, L_0000000003fda620;  1 drivers, strength-aware
+v00000000039d0b10_0 .net "Y", 0 0, L_0000000004129140;  alias, 1 drivers
+S_0000000002a278e0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000002a27760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041290d0 .functor NOT 1, L_0000000004128c70, C4<0>, C4<0>, C4<0>;
+L_0000000004129140 .functor BUF 1, L_00000000041290d0, C4<0>, C4<0>, C4<0>;
+v00000000039d02f0_0 .net "A", 0 0, L_0000000004128c70;  alias, 1 drivers
+L_0000000003fd9dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ced10_0 .net8 "VGND", 0 0, L_0000000003fd9dd0;  1 drivers, strength-aware
+L_0000000003fda4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d07f0_0 .net8 "VNB", 0 0, L_0000000003fda4d0;  1 drivers, strength-aware
+L_0000000003fd9580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf0d0_0 .net8 "VPB", 0 0, L_0000000003fd9580;  1 drivers, strength-aware
+L_0000000003fd9510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf2b0_0 .net8 "VPWR", 0 0, L_0000000003fd9510;  1 drivers, strength-aware
+v00000000039cee50_0 .net "Y", 0 0, L_0000000004129140;  alias, 1 drivers
+v00000000039cf8f0_0 .net "not0_out_Y", 0 0, L_00000000041290d0;  1 drivers
+S_0000000002a27a60 .scope module, "_0569_" "sky130_fd_sc_hd__o221a_2" 3 827, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039d0570_0 .net "A1", 0 0, L_0000000003f90ca0;  1 drivers
+v00000000039cf990_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039d0250_0 .net "B1", 0 0, L_0000000004128ff0;  alias, 1 drivers
+v00000000039d0610_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039cfcb0_0 .net "C1", 0 0, L_0000000004128ab0;  alias, 1 drivers
+L_0000000003fda540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cfa30_0 .net8 "VGND", 0 0, L_0000000003fda540;  1 drivers, strength-aware
+L_0000000003fd8ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ceb30_0 .net8 "VNB", 0 0, L_0000000003fd8ef0;  1 drivers, strength-aware
+L_0000000003fd9890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf030_0 .net8 "VPB", 0 0, L_0000000003fd9890;  1 drivers, strength-aware
+L_0000000003fda690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cfad0_0 .net8 "VPWR", 0 0, L_0000000003fda690;  1 drivers, strength-aware
+v00000000039cfb70_0 .net "X", 0 0, L_000000000412a5d0;  alias, 1 drivers
+S_0000000002a26260 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000002a27a60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004128ce0 .functor OR 1, L_0000000004127230, L_0000000004128ff0, C4<0>, C4<0>;
+L_00000000041291b0 .functor OR 1, L_0000000004127310, L_0000000003f90ca0, C4<0>, C4<0>;
+L_000000000412ab80 .functor AND 1, L_0000000004128ce0, L_00000000041291b0, L_0000000004128ab0, C4<1>;
+L_000000000412a5d0 .functor BUF 1, L_000000000412ab80, C4<0>, C4<0>, C4<0>;
+v00000000039cf350_0 .net "A1", 0 0, L_0000000003f90ca0;  alias, 1 drivers
+v00000000039ceef0_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039cef90_0 .net "B1", 0 0, L_0000000004128ff0;  alias, 1 drivers
+v00000000039cf3f0_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v00000000039d0a70_0 .net "C1", 0 0, L_0000000004128ab0;  alias, 1 drivers
+L_0000000003fd9c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d0750_0 .net8 "VGND", 0 0, L_0000000003fd9c10;  1 drivers, strength-aware
+L_0000000003fd9c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d0390_0 .net8 "VNB", 0 0, L_0000000003fd9c80;  1 drivers, strength-aware
+L_0000000003fd9e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cf670_0 .net8 "VPB", 0 0, L_0000000003fd9e40;  1 drivers, strength-aware
+L_0000000003fd9190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d0bb0_0 .net8 "VPWR", 0 0, L_0000000003fd9190;  1 drivers, strength-aware
+v00000000039d0430_0 .net "X", 0 0, L_000000000412a5d0;  alias, 1 drivers
+v00000000039cf710_0 .net "and0_out_X", 0 0, L_000000000412ab80;  1 drivers
+v00000000039cf7b0_0 .net "or0_out", 0 0, L_0000000004128ce0;  1 drivers
+v00000000039d04d0_0 .net "or1_out", 0 0, L_00000000041291b0;  1 drivers
+S_0000000002a26560 .scope module, "_0570_" "sky130_fd_sc_hd__nor2_2" 3 835, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039d0c50_0 .net "A", 0 0, L_0000000004129140;  alias, 1 drivers
+v00000000039cf170_0 .net "B", 0 0, L_000000000412a5d0;  alias, 1 drivers
+L_0000000003fda850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039cff30_0 .net8 "VGND", 0 0, L_0000000003fda850;  1 drivers, strength-aware
+L_0000000003fd9040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d0cf0_0 .net8 "VNB", 0 0, L_0000000003fd9040;  1 drivers, strength-aware
+L_0000000003fd8d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d0ed0_0 .net8 "VPB", 0 0, L_0000000003fd8d30;  1 drivers, strength-aware
+L_0000000003fda1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d0e30_0 .net8 "VPWR", 0 0, L_0000000003fda1c0;  1 drivers, strength-aware
+v00000000039d0070_0 .net "Y", 0 0, L_000000000412a720;  alias, 1 drivers
+S_0000000003a1ee80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000002a26560;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412a4f0 .functor NOR 1, L_0000000004129140, L_000000000412a5d0, C4<0>, C4<0>;
+L_000000000412a720 .functor BUF 1, L_000000000412a4f0, C4<0>, C4<0>, C4<0>;
+v00000000039cfc10_0 .net "A", 0 0, L_0000000004129140;  alias, 1 drivers
+v00000000039d10b0_0 .net "B", 0 0, L_000000000412a5d0;  alias, 1 drivers
+L_0000000003fd9cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d06b0_0 .net8 "VGND", 0 0, L_0000000003fd9cf0;  1 drivers, strength-aware
+L_0000000003fda700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1010_0 .net8 "VNB", 0 0, L_0000000003fda700;  1 drivers, strength-aware
+L_0000000003fd9d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cfd50_0 .net8 "VPB", 0 0, L_0000000003fd9d60;  1 drivers, strength-aware
+L_0000000003fd90b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039cffd0_0 .net8 "VPWR", 0 0, L_0000000003fd90b0;  1 drivers, strength-aware
+v00000000039cfe90_0 .net "Y", 0 0, L_000000000412a720;  alias, 1 drivers
+v00000000039cfdf0_0 .net "nor0_out_Y", 0 0, L_000000000412a4f0;  1 drivers
+S_0000000003a20380 .scope module, "_0571_" "sky130_fd_sc_hd__inv_2" 3 840, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039cec70_0 .net "A", 0 0, L_0000000003f92000;  1 drivers
+L_0000000003fd9120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d2050_0 .net8 "VGND", 0 0, L_0000000003fd9120;  1 drivers, strength-aware
+L_0000000003fd9270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1650_0 .net8 "VNB", 0 0, L_0000000003fd9270;  1 drivers, strength-aware
+L_0000000003fd9f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d1d30_0 .net8 "VPB", 0 0, L_0000000003fd9f90;  1 drivers, strength-aware
+L_0000000003fda230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d2730_0 .net8 "VPWR", 0 0, L_0000000003fda230;  1 drivers, strength-aware
+v00000000039d2410_0 .net "Y", 0 0, L_000000000412abf0;  alias, 1 drivers
+S_0000000003a1eb80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a20380;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412a640 .functor NOT 1, L_0000000003f92000, C4<0>, C4<0>, C4<0>;
+L_000000000412abf0 .functor BUF 1, L_000000000412a640, C4<0>, C4<0>, C4<0>;
+v00000000039d0110_0 .net "A", 0 0, L_0000000003f92000;  alias, 1 drivers
+L_0000000003fda770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d0f70_0 .net8 "VGND", 0 0, L_0000000003fda770;  1 drivers, strength-aware
+L_0000000003fd8da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ce950_0 .net8 "VNB", 0 0, L_0000000003fd8da0;  1 drivers, strength-aware
+L_0000000003fdc290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ce9f0_0 .net8 "VPB", 0 0, L_0000000003fdc290;  1 drivers, strength-aware
+L_0000000003fdc300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d0890_0 .net8 "VPWR", 0 0, L_0000000003fdc300;  1 drivers, strength-aware
+v00000000039d0930_0 .net "Y", 0 0, L_000000000412abf0;  alias, 1 drivers
+v00000000039cea90_0 .net "not0_out_Y", 0 0, L_000000000412a640;  1 drivers
+S_0000000003a1ed00 .scope module, "_0572_" "sky130_fd_sc_hd__a2bb2o_2" 3 844, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039d2370_0 .net "A1_N", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d1290_0 .net "A2_N", 0 0, L_0000000003f920a0;  1 drivers
+v00000000039d1e70_0 .net "B1", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d1bf0_0 .net "B2", 0 0, L_0000000003f91ce0;  1 drivers
+L_0000000003fdacb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d2b90_0 .net8 "VGND", 0 0, L_0000000003fdacb0;  1 drivers, strength-aware
+L_0000000003fdbb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d16f0_0 .net8 "VNB", 0 0, L_0000000003fdbb20;  1 drivers, strength-aware
+L_0000000003fdbce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d2cd0_0 .net8 "VPB", 0 0, L_0000000003fdbce0;  1 drivers, strength-aware
+L_0000000003fdafc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d1dd0_0 .net8 "VPWR", 0 0, L_0000000003fdafc0;  1 drivers, strength-aware
+v00000000039d2c30_0 .net "X", 0 0, L_000000000412bbb0;  alias, 1 drivers
+S_0000000003a21e80 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a1ed00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412ae20 .functor AND 1, L_0000000004126c10, L_0000000003f91ce0, C4<1>, C4<1>;
+L_000000000412b2f0 .functor NOR 1, L_0000000004126c10, L_0000000003f920a0, C4<0>, C4<0>;
+L_000000000412b280 .functor OR 1, L_000000000412b2f0, L_000000000412ae20, C4<0>, C4<0>;
+L_000000000412bbb0 .functor BUF 1, L_000000000412b280, C4<0>, C4<0>, C4<0>;
+v00000000039d1c90_0 .net "A1_N", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d2af0_0 .net "A2_N", 0 0, L_0000000003f920a0;  alias, 1 drivers
+v00000000039d1510_0 .net "B1", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d27d0_0 .net "B2", 0 0, L_0000000003f91ce0;  alias, 1 drivers
+L_0000000003fdaa80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d34f0_0 .net8 "VGND", 0 0, L_0000000003fdaa80;  1 drivers, strength-aware
+L_0000000003fdbe30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1790_0 .net8 "VNB", 0 0, L_0000000003fdbe30;  1 drivers, strength-aware
+L_0000000003fda8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d24b0_0 .net8 "VPB", 0 0, L_0000000003fda8c0;  1 drivers, strength-aware
+L_0000000003fdb6c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d20f0_0 .net8 "VPWR", 0 0, L_0000000003fdb6c0;  1 drivers, strength-aware
+v00000000039d2a50_0 .net "X", 0 0, L_000000000412bbb0;  alias, 1 drivers
+v00000000039d2550_0 .net "and0_out", 0 0, L_000000000412ae20;  1 drivers
+v00000000039d2910_0 .net "nor0_out", 0 0, L_000000000412b2f0;  1 drivers
+v00000000039d22d0_0 .net "or0_out_X", 0 0, L_000000000412b280;  1 drivers
+S_0000000003a21400 .scope module, "_0573_" "sky130_fd_sc_hd__o221a_2" 3 851, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039d2230_0 .net "A1", 0 0, L_0000000003f905c0;  1 drivers
+v00000000039d1330_0 .net "A2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039d25f0_0 .net "B1", 0 0, L_000000000412abf0;  alias, 1 drivers
+v00000000039d2690_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039d1970_0 .net "C1", 0 0, L_000000000412bbb0;  alias, 1 drivers
+L_0000000003fdb810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1ab0_0 .net8 "VGND", 0 0, L_0000000003fdb810;  1 drivers, strength-aware
+L_0000000003fdbb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d13d0_0 .net8 "VNB", 0 0, L_0000000003fdbb90;  1 drivers, strength-aware
+L_0000000003fdad90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d29b0_0 .net8 "VPB", 0 0, L_0000000003fdad90;  1 drivers, strength-aware
+L_0000000003fdb490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d1830_0 .net8 "VPWR", 0 0, L_0000000003fdb490;  1 drivers, strength-aware
+v00000000039d1150_0 .net "X", 0 0, L_000000000412ab10;  alias, 1 drivers
+S_0000000003a21580 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a21400;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412bad0 .functor OR 1, L_0000000004127ee0, L_000000000412abf0, C4<0>, C4<0>;
+L_000000000412b520 .functor OR 1, L_0000000004126890, L_0000000003f905c0, C4<0>, C4<0>;
+L_000000000412a8e0 .functor AND 1, L_000000000412bad0, L_000000000412b520, L_000000000412bbb0, C4<1>;
+L_000000000412ab10 .functor BUF 1, L_000000000412a8e0, C4<0>, C4<0>, C4<0>;
+v00000000039d36d0_0 .net "A1", 0 0, L_0000000003f905c0;  alias, 1 drivers
+v00000000039d18d0_0 .net "A2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039d2d70_0 .net "B1", 0 0, L_000000000412abf0;  alias, 1 drivers
+v00000000039d1f10_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039d3630_0 .net "C1", 0 0, L_000000000412bbb0;  alias, 1 drivers
+L_0000000003fdabd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1fb0_0 .net8 "VGND", 0 0, L_0000000003fdabd0;  1 drivers, strength-aware
+L_0000000003fdb500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d2e10_0 .net8 "VNB", 0 0, L_0000000003fdb500;  1 drivers, strength-aware
+L_0000000003fdb1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d2eb0_0 .net8 "VPB", 0 0, L_0000000003fdb1f0;  1 drivers, strength-aware
+L_0000000003fdbd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d2190_0 .net8 "VPWR", 0 0, L_0000000003fdbd50;  1 drivers, strength-aware
+v00000000039d38b0_0 .net "X", 0 0, L_000000000412ab10;  alias, 1 drivers
+v00000000039d11f0_0 .net "and0_out_X", 0 0, L_000000000412a8e0;  1 drivers
+v00000000039d2f50_0 .net "or0_out", 0 0, L_000000000412bad0;  1 drivers
+v00000000039d3810_0 .net "or1_out", 0 0, L_000000000412b520;  1 drivers
+S_0000000003a21b80 .scope module, "_0574_" "sky130_fd_sc_hd__nand2_2" 3 859, 4 8552 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039d3130_0 .net "A", 0 0, L_000000000412a720;  alias, 1 drivers
+v00000000039d31d0_0 .net "B", 0 0, L_000000000412ab10;  alias, 1 drivers
+L_0000000003fdb730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d3270_0 .net8 "VGND", 0 0, L_0000000003fdb730;  1 drivers, strength-aware
+L_0000000003fdb5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d1470_0 .net8 "VNB", 0 0, L_0000000003fdb5e0;  1 drivers, strength-aware
+L_0000000003fdc370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d33b0_0 .net8 "VPB", 0 0, L_0000000003fdc370;  1 drivers, strength-aware
+L_0000000003fdc450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d3450_0 .net8 "VPWR", 0 0, L_0000000003fdc450;  1 drivers, strength-aware
+v00000000039d3770_0 .net "Y", 0 0, L_000000000412a2c0;  alias, 1 drivers
+S_0000000003a1e400 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003a21b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412ac60 .functor NAND 1, L_000000000412ab10, L_000000000412a720, C4<1>, C4<1>;
+L_000000000412a2c0 .functor BUF 1, L_000000000412ac60, C4<0>, C4<0>, C4<0>;
+v00000000039d3590_0 .net "A", 0 0, L_000000000412a720;  alias, 1 drivers
+v00000000039d15b0_0 .net "B", 0 0, L_000000000412ab10;  alias, 1 drivers
+L_0000000003fdb570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d3310_0 .net8 "VGND", 0 0, L_0000000003fdb570;  1 drivers, strength-aware
+L_0000000003fdb9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d2870_0 .net8 "VNB", 0 0, L_0000000003fdb9d0;  1 drivers, strength-aware
+L_0000000003fdb0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d2ff0_0 .net8 "VPB", 0 0, L_0000000003fdb0a0;  1 drivers, strength-aware
+L_0000000003fda930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d1b50_0 .net8 "VPWR", 0 0, L_0000000003fda930;  1 drivers, strength-aware
+v00000000039d1a10_0 .net "Y", 0 0, L_000000000412a2c0;  alias, 1 drivers
+v00000000039d3090_0 .net "nand0_out_Y", 0 0, L_000000000412ac60;  1 drivers
+S_0000000003a1e700 .scope module, "_0575_" "sky130_fd_sc_hd__inv_2" 3 864, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039d6010_0 .net "A", 0 0, L_000000000412a2c0;  alias, 1 drivers
+L_0000000003fdbdc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5f70_0 .net8 "VGND", 0 0, L_0000000003fdbdc0;  1 drivers, strength-aware
+L_0000000003fdbea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d4b70_0 .net8 "VNB", 0 0, L_0000000003fdbea0;  1 drivers, strength-aware
+L_0000000003fdb260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4350_0 .net8 "VPB", 0 0, L_0000000003fdb260;  1 drivers, strength-aware
+L_0000000003fdbf10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4670_0 .net8 "VPWR", 0 0, L_0000000003fdbf10;  1 drivers, strength-aware
+v00000000039d40d0_0 .net "Y", 0 0, L_000000000412b360;  alias, 1 drivers
+S_0000000003a22c00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a1e700;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412af00 .functor NOT 1, L_000000000412a2c0, C4<0>, C4<0>, C4<0>;
+L_000000000412b360 .functor BUF 1, L_000000000412af00, C4<0>, C4<0>, C4<0>;
+v00000000039d4d50_0 .net "A", 0 0, L_000000000412a2c0;  alias, 1 drivers
+L_0000000003fdb110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5110_0 .net8 "VGND", 0 0, L_0000000003fdb110;  1 drivers, strength-aware
+L_0000000003fdbc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d3e50_0 .net8 "VNB", 0 0, L_0000000003fdbc00;  1 drivers, strength-aware
+L_0000000003fdb7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4850_0 .net8 "VPB", 0 0, L_0000000003fdb7a0;  1 drivers, strength-aware
+L_0000000003fda9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d5250_0 .net8 "VPWR", 0 0, L_0000000003fda9a0;  1 drivers, strength-aware
+v00000000039d4c10_0 .net "Y", 0 0, L_000000000412b360;  alias, 1 drivers
+v00000000039d51b0_0 .net "not0_out_Y", 0 0, L_000000000412af00;  1 drivers
+S_0000000003a1dc80 .scope module, "_0576_" "sky130_fd_sc_hd__a221oi_2" 3 868, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039d4710_0 .net "A1", 0 0, L_000000000412a020;  alias, 1 drivers
+v00000000039d39f0_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039d5930_0 .net "B1", 0 0, L_0000000003f917e0;  1 drivers
+v00000000039d52f0_0 .net "B2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039d45d0_0 .net "C1", 0 0, L_00000000041293e0;  alias, 1 drivers
+L_0000000003fdb180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d47b0_0 .net8 "VGND", 0 0, L_0000000003fdb180;  1 drivers, strength-aware
+L_0000000003fdb2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5430_0 .net8 "VNB", 0 0, L_0000000003fdb2d0;  1 drivers, strength-aware
+L_0000000003fdb030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d5570_0 .net8 "VPB", 0 0, L_0000000003fdb030;  1 drivers, strength-aware
+L_0000000003fdbf80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4490_0 .net8 "VPWR", 0 0, L_0000000003fdbf80;  1 drivers, strength-aware
+v00000000039d5390_0 .net "Y", 0 0, L_000000000412b670;  alias, 1 drivers
+S_0000000003a1d680 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a1dc80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412acd0 .functor AND 1, L_0000000003f917e0, L_0000000004127310, C4<1>, C4<1>;
+L_000000000412a870 .functor AND 1, L_000000000412a020, L_0000000004126270, C4<1>, C4<1>;
+L_000000000412a560 .functor NOR 1, L_000000000412acd0, L_00000000041293e0, L_000000000412a870, C4<0>;
+L_000000000412b670 .functor BUF 1, L_000000000412a560, C4<0>, C4<0>, C4<0>;
+v00000000039d3d10_0 .net "A1", 0 0, L_000000000412a020;  alias, 1 drivers
+v00000000039d4530_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v00000000039d3ef0_0 .net "B1", 0 0, L_0000000003f917e0;  alias, 1 drivers
+v00000000039d4e90_0 .net "B2", 0 0, L_0000000004127310;  alias, 1 drivers
+v00000000039d4030_0 .net "C1", 0 0, L_00000000041293e0;  alias, 1 drivers
+L_0000000003fdaaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5890_0 .net8 "VGND", 0 0, L_0000000003fdaaf0;  1 drivers, strength-aware
+L_0000000003fdb420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d3950_0 .net8 "VNB", 0 0, L_0000000003fdb420;  1 drivers, strength-aware
+L_0000000003fdc060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d5610_0 .net8 "VPB", 0 0, L_0000000003fdc060;  1 drivers, strength-aware
+L_0000000003fdb340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4ad0_0 .net8 "VPWR", 0 0, L_0000000003fdb340;  1 drivers, strength-aware
+v00000000039d54d0_0 .net "Y", 0 0, L_000000000412b670;  alias, 1 drivers
+v00000000039d5c50_0 .net "and0_out", 0 0, L_000000000412acd0;  1 drivers
+v00000000039d3f90_0 .net "and1_out", 0 0, L_000000000412a870;  1 drivers
+v00000000039d4170_0 .net "nor0_out_Y", 0 0, L_000000000412a560;  1 drivers
+S_0000000003a1e880 .scope module, "_0577_" "sky130_fd_sc_hd__or2_2" 3 876, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039d48f0_0 .net "A", 0 0, L_0000000004128a40;  alias, 1 drivers
+v00000000039d5a70_0 .net "B", 0 0, L_000000000412b670;  alias, 1 drivers
+L_0000000003fdb3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5b10_0 .net8 "VGND", 0 0, L_0000000003fdb3b0;  1 drivers, strength-aware
+L_0000000003fdba40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d4990_0 .net8 "VNB", 0 0, L_0000000003fdba40;  1 drivers, strength-aware
+L_0000000003fdae00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d5bb0_0 .net8 "VPB", 0 0, L_0000000003fdae00;  1 drivers, strength-aware
+L_0000000003fdc3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4a30_0 .net8 "VPWR", 0 0, L_0000000003fdc3e0;  1 drivers, strength-aware
+v00000000039d4cb0_0 .net "X", 0 0, L_000000000412bb40;  alias, 1 drivers
+S_0000000003a1f900 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a1e880;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412b050 .functor OR 1, L_000000000412b670, L_0000000004128a40, C4<0>, C4<0>;
+L_000000000412bb40 .functor BUF 1, L_000000000412b050, C4<0>, C4<0>, C4<0>;
+v00000000039d3bd0_0 .net "A", 0 0, L_0000000004128a40;  alias, 1 drivers
+v00000000039d56b0_0 .net "B", 0 0, L_000000000412b670;  alias, 1 drivers
+L_0000000003fdab60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d43f0_0 .net8 "VGND", 0 0, L_0000000003fdab60;  1 drivers, strength-aware
+L_0000000003fdaa10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5750_0 .net8 "VNB", 0 0, L_0000000003fdaa10;  1 drivers, strength-aware
+L_0000000003fdbc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d57f0_0 .net8 "VPB", 0 0, L_0000000003fdbc70;  1 drivers, strength-aware
+L_0000000003fdb880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d59d0_0 .net8 "VPWR", 0 0, L_0000000003fdb880;  1 drivers, strength-aware
+v00000000039d60b0_0 .net "X", 0 0, L_000000000412bb40;  alias, 1 drivers
+v00000000039d3a90_0 .net "or0_out_X", 0 0, L_000000000412b050;  1 drivers
+S_0000000003a22300 .scope module, "_0578_" "sky130_fd_sc_hd__inv_2" 3 881, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039d3db0_0 .net "A", 0 0, L_000000000412bb40;  alias, 1 drivers
+L_0000000003fdbff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d4210_0 .net8 "VGND", 0 0, L_0000000003fdbff0;  1 drivers, strength-aware
+L_0000000003fdb650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d4f30_0 .net8 "VNB", 0 0, L_0000000003fdb650;  1 drivers, strength-aware
+L_0000000003fdad20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d42b0_0 .net8 "VPB", 0 0, L_0000000003fdad20;  1 drivers, strength-aware
+L_0000000003fdac40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d4fd0_0 .net8 "VPWR", 0 0, L_0000000003fdac40;  1 drivers, strength-aware
+v00000000039d5070_0 .net "Y", 0 0, L_000000000412ad40;  alias, 1 drivers
+S_0000000003a21280 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a22300;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412af70 .functor NOT 1, L_000000000412bb40, C4<0>, C4<0>, C4<0>;
+L_000000000412ad40 .functor BUF 1, L_000000000412af70, C4<0>, C4<0>, C4<0>;
+v00000000039d4df0_0 .net "A", 0 0, L_000000000412bb40;  alias, 1 drivers
+L_0000000003fdae70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5cf0_0 .net8 "VGND", 0 0, L_0000000003fdae70;  1 drivers, strength-aware
+L_0000000003fdaee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d5d90_0 .net8 "VNB", 0 0, L_0000000003fdaee0;  1 drivers, strength-aware
+L_0000000003fdb8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d3c70_0 .net8 "VPB", 0 0, L_0000000003fdb8f0;  1 drivers, strength-aware
+L_0000000003fdaf50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d5e30_0 .net8 "VPWR", 0 0, L_0000000003fdaf50;  1 drivers, strength-aware
+v00000000039d5ed0_0 .net "Y", 0 0, L_000000000412ad40;  alias, 1 drivers
+v00000000039d3b30_0 .net "not0_out_Y", 0 0, L_000000000412af70;  1 drivers
+S_0000000003a20b00 .scope module, "_0579_" "sky130_fd_sc_hd__o21ai_2" 3 885, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v00000000039d7050_0 .net "A1", 0 0, L_0000000004129140;  alias, 1 drivers
+v00000000039d7a50_0 .net "A2", 0 0, L_000000000412b360;  alias, 1 drivers
+v00000000039d8130_0 .net "B1", 0 0, L_000000000412ad40;  alias, 1 drivers
+L_0000000003fdc220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d63d0_0 .net8 "VGND", 0 0, L_0000000003fdc220;  1 drivers, strength-aware
+L_0000000003fdb960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d75f0_0 .net8 "VNB", 0 0, L_0000000003fdb960;  1 drivers, strength-aware
+L_0000000003fdbab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d8450_0 .net8 "VPB", 0 0, L_0000000003fdbab0;  1 drivers, strength-aware
+L_0000000003fdc0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d7550_0 .net8 "VPWR", 0 0, L_0000000003fdc0d0;  1 drivers, strength-aware
+v00000000039d6470_0 .net "Y", 0 0, L_000000000412b7c0;  alias, 1 drivers
+S_0000000003a1f000 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a20b00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412a410 .functor OR 1, L_000000000412b360, L_0000000004129140, C4<0>, C4<0>;
+L_000000000412b830 .functor NAND 1, L_000000000412ad40, L_000000000412a410, C4<1>, C4<1>;
+L_000000000412b7c0 .functor BUF 1, L_000000000412b830, C4<0>, C4<0>, C4<0>;
+v00000000039d7410_0 .net "A1", 0 0, L_0000000004129140;  alias, 1 drivers
+v00000000039d7d70_0 .net "A2", 0 0, L_000000000412b360;  alias, 1 drivers
+v00000000039d66f0_0 .net "B1", 0 0, L_000000000412ad40;  alias, 1 drivers
+L_0000000003fdc140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d81d0_0 .net8 "VGND", 0 0, L_0000000003fdc140;  1 drivers, strength-aware
+L_0000000003fdc1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d6ab0_0 .net8 "VNB", 0 0, L_0000000003fdc1b0;  1 drivers, strength-aware
+L_0000000003fdcbc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d6c90_0 .net8 "VPB", 0 0, L_0000000003fdcbc0;  1 drivers, strength-aware
+L_0000000003fdc680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d7af0_0 .net8 "VPWR", 0 0, L_0000000003fdc680;  1 drivers, strength-aware
+v00000000039d7f50_0 .net "Y", 0 0, L_000000000412b7c0;  alias, 1 drivers
+v00000000039d6150_0 .net "nand0_out_Y", 0 0, L_000000000412b830;  1 drivers
+v00000000039d6330_0 .net "or0_out", 0 0, L_000000000412a410;  1 drivers
+S_0000000003a1f180 .scope module, "_0580_" "sky130_fd_sc_hd__inv_2" 3 891, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039d7e10_0 .net "A", 0 0, L_000000000412b7c0;  alias, 1 drivers
+L_0000000003fdda30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8090_0 .net8 "VGND", 0 0, L_0000000003fdda30;  1 drivers, strength-aware
+L_0000000003fdc4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8810_0 .net8 "VNB", 0 0, L_0000000003fdc4c0;  1 drivers, strength-aware
+L_0000000003fdd2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d72d0_0 .net8 "VPB", 0 0, L_0000000003fdd2c0;  1 drivers, strength-aware
+L_0000000003fdd410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d7730_0 .net8 "VPWR", 0 0, L_0000000003fdd410;  1 drivers, strength-aware
+v00000000039d84f0_0 .net "Y", 0 0, L_000000000412b9f0;  alias, 1 drivers
+S_0000000003a1ff00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a1f180;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412bc20 .functor NOT 1, L_000000000412b7c0, C4<0>, C4<0>, C4<0>;
+L_000000000412b9f0 .functor BUF 1, L_000000000412bc20, C4<0>, C4<0>, C4<0>;
+v00000000039d6f10_0 .net "A", 0 0, L_000000000412b7c0;  alias, 1 drivers
+L_0000000003fdd720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d6510_0 .net8 "VGND", 0 0, L_0000000003fdd720;  1 drivers, strength-aware
+L_0000000003fdc990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8590_0 .net8 "VNB", 0 0, L_0000000003fdc990;  1 drivers, strength-aware
+L_0000000003fdd090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d8270_0 .net8 "VPB", 0 0, L_0000000003fdd090;  1 drivers, strength-aware
+L_0000000003fdc7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d6d30_0 .net8 "VPWR", 0 0, L_0000000003fdc7d0;  1 drivers, strength-aware
+v00000000039d7690_0 .net "Y", 0 0, L_000000000412b9f0;  alias, 1 drivers
+v00000000039d83b0_0 .net "not0_out_Y", 0 0, L_000000000412bc20;  1 drivers
+S_0000000003a20e00 .scope module, "_0581_" "sky130_fd_sc_hd__inv_2" 3 895, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039d7cd0_0 .net "A", 0 0, L_0000000003f90980;  1 drivers
+L_0000000003fdd100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8630_0 .net8 "VGND", 0 0, L_0000000003fdd100;  1 drivers, strength-aware
+L_0000000003fdcdf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d65b0_0 .net8 "VNB", 0 0, L_0000000003fdcdf0;  1 drivers, strength-aware
+L_0000000003fdd950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d86d0_0 .net8 "VPB", 0 0, L_0000000003fdd950;  1 drivers, strength-aware
+L_0000000003fdd330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d61f0_0 .net8 "VPWR", 0 0, L_0000000003fdd330;  1 drivers, strength-aware
+v00000000039d6e70_0 .net "Y", 0 0, L_000000000412a6b0;  alias, 1 drivers
+S_0000000003a22d80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a20e00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412afe0 .functor NOT 1, L_0000000003f90980, C4<0>, C4<0>, C4<0>;
+L_000000000412a6b0 .functor BUF 1, L_000000000412afe0, C4<0>, C4<0>, C4<0>;
+v00000000039d6fb0_0 .net "A", 0 0, L_0000000003f90980;  alias, 1 drivers
+L_0000000003fdd1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8310_0 .net8 "VGND", 0 0, L_0000000003fdd1e0;  1 drivers, strength-aware
+L_0000000003fddf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d7c30_0 .net8 "VNB", 0 0, L_0000000003fddf70;  1 drivers, strength-aware
+L_0000000003fde050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d7b90_0 .net8 "VPB", 0 0, L_0000000003fde050;  1 drivers, strength-aware
+L_0000000003fdd170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d70f0_0 .net8 "VPWR", 0 0, L_0000000003fdd170;  1 drivers, strength-aware
+v00000000039d6dd0_0 .net "Y", 0 0, L_000000000412a6b0;  alias, 1 drivers
+v00000000039d7190_0 .net "not0_out_Y", 0 0, L_000000000412afe0;  1 drivers
+S_0000000003a1e100 .scope module, "_0582_" "sky130_fd_sc_hd__a2bb2o_2" 3 899, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039d6830_0 .net "A1_N", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d6290_0 .net "A2_N", 0 0, L_0000000003f90d40;  1 drivers
+v00000000039d68d0_0 .net "B1", 0 0, L_0000000004128030;  alias, 1 drivers
+v00000000039d6970_0 .net "B2", 0 0, L_0000000003f90f20;  1 drivers
+L_0000000003fdd5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d6a10_0 .net8 "VGND", 0 0, L_0000000003fdd5d0;  1 drivers, strength-aware
+L_0000000003fdcca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d7910_0 .net8 "VNB", 0 0, L_0000000003fdcca0;  1 drivers, strength-aware
+L_0000000003fdc530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d6bf0_0 .net8 "VPB", 0 0, L_0000000003fdc530;  1 drivers, strength-aware
+L_0000000003fdd9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d79b0_0 .net8 "VPWR", 0 0, L_0000000003fdd9c0;  1 drivers, strength-aware
+v00000000039d8bd0_0 .net "X", 0 0, L_000000000412b4b0;  alias, 1 drivers
+S_0000000003a1de00 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a1e100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412a790 .functor AND 1, L_0000000004128030, L_0000000003f90f20, C4<1>, C4<1>;
+L_000000000412bc90 .functor NOR 1, L_0000000004126c10, L_0000000003f90d40, C4<0>, C4<0>;
+L_000000000412b440 .functor OR 1, L_000000000412bc90, L_000000000412a790, C4<0>, C4<0>;
+L_000000000412b4b0 .functor BUF 1, L_000000000412b440, C4<0>, C4<0>, C4<0>;
+v00000000039d6650_0 .net "A1_N", 0 0, L_0000000004126c10;  alias, 1 drivers
+v00000000039d8770_0 .net "A2_N", 0 0, L_0000000003f90d40;  alias, 1 drivers
+v00000000039d77d0_0 .net "B1", 0 0, L_0000000004128030;  alias, 1 drivers
+v00000000039d74b0_0 .net "B2", 0 0, L_0000000003f90f20;  alias, 1 drivers
+L_0000000003fdd8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d7870_0 .net8 "VGND", 0 0, L_0000000003fdd8e0;  1 drivers, strength-aware
+L_0000000003fdce60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d7230_0 .net8 "VNB", 0 0, L_0000000003fdce60;  1 drivers, strength-aware
+L_0000000003fddb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d7eb0_0 .net8 "VPB", 0 0, L_0000000003fddb10;  1 drivers, strength-aware
+L_0000000003fdcd10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d88b0_0 .net8 "VPWR", 0 0, L_0000000003fdcd10;  1 drivers, strength-aware
+v00000000039d6b50_0 .net "X", 0 0, L_000000000412b4b0;  alias, 1 drivers
+v00000000039d7ff0_0 .net "and0_out", 0 0, L_000000000412a790;  1 drivers
+v00000000039d7370_0 .net "nor0_out", 0 0, L_000000000412bc90;  1 drivers
+v00000000039d6790_0 .net "or0_out_X", 0 0, L_000000000412b440;  1 drivers
+S_0000000003a1ea00 .scope module, "_0583_" "sky130_fd_sc_hd__o221a_2" 3 906, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039da2f0_0 .net "A1", 0 0, L_0000000003f8fda0;  1 drivers
+v00000000039d9c10_0 .net "A2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039d95d0_0 .net "B1", 0 0, L_000000000412a6b0;  alias, 1 drivers
+v00000000039dacf0_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039da390_0 .net "C1", 0 0, L_000000000412b4b0;  alias, 1 drivers
+L_0000000003fdd790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d9670_0 .net8 "VGND", 0 0, L_0000000003fdd790;  1 drivers, strength-aware
+L_0000000003fdd3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039da9d0_0 .net8 "VNB", 0 0, L_0000000003fdd3a0;  1 drivers, strength-aware
+L_0000000003fdc5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d8db0_0 .net8 "VPB", 0 0, L_0000000003fdc5a0;  1 drivers, strength-aware
+L_0000000003fdcd80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039da250_0 .net8 "VPWR", 0 0, L_0000000003fdcd80;  1 drivers, strength-aware
+v00000000039d9710_0 .net "X", 0 0, L_000000000412a800;  alias, 1 drivers
+S_0000000003a22f00 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a1ea00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412b3d0 .functor OR 1, L_0000000004127ee0, L_000000000412a6b0, C4<0>, C4<0>;
+L_000000000412a100 .functor OR 1, L_0000000004126190, L_0000000003f8fda0, C4<0>, C4<0>;
+L_000000000412a170 .functor AND 1, L_000000000412b3d0, L_000000000412a100, L_000000000412b4b0, C4<1>;
+L_000000000412a800 .functor BUF 1, L_000000000412a170, C4<0>, C4<0>, C4<0>;
+v00000000039d9fd0_0 .net "A1", 0 0, L_0000000003f8fda0;  alias, 1 drivers
+v00000000039d8c70_0 .net "A2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039d8d10_0 .net "B1", 0 0, L_000000000412a6b0;  alias, 1 drivers
+v00000000039d9530_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039da890_0 .net "C1", 0 0, L_000000000412b4b0;  alias, 1 drivers
+L_0000000003fddaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8e50_0 .net8 "VGND", 0 0, L_0000000003fddaa0;  1 drivers, strength-aware
+L_0000000003fdcc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d8f90_0 .net8 "VNB", 0 0, L_0000000003fdcc30;  1 drivers, strength-aware
+L_0000000003fdddb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d9030_0 .net8 "VPB", 0 0, L_0000000003fdddb0;  1 drivers, strength-aware
+L_0000000003fdd640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039da610_0 .net8 "VPWR", 0 0, L_0000000003fdd640;  1 drivers, strength-aware
+v00000000039d9ad0_0 .net "X", 0 0, L_000000000412a800;  alias, 1 drivers
+v00000000039db010_0 .net "and0_out_X", 0 0, L_000000000412a170;  1 drivers
+v00000000039da1b0_0 .net "or0_out", 0 0, L_000000000412b3d0;  1 drivers
+v00000000039da430_0 .net "or1_out", 0 0, L_000000000412a100;  1 drivers
+S_0000000003a1f300 .scope module, "_0584_" "sky130_fd_sc_hd__a221oi_2" 3 914, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039da6b0_0 .net "A1", 0 0, L_000000000412a6b0;  alias, 1 drivers
+v00000000039d9490_0 .net "A2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039d98f0_0 .net "B1", 0 0, L_0000000003f90480;  1 drivers
+v00000000039da7f0_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039da070_0 .net "C1", 0 0, L_000000000412b4b0;  alias, 1 drivers
+L_0000000003fddb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d9e90_0 .net8 "VGND", 0 0, L_0000000003fddb80;  1 drivers, strength-aware
+L_0000000003fdced0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d9990_0 .net8 "VNB", 0 0, L_0000000003fdced0;  1 drivers, strength-aware
+L_0000000003fdc610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039da930_0 .net8 "VPB", 0 0, L_0000000003fdc610;  1 drivers, strength-aware
+L_0000000003fdd480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d9b70_0 .net8 "VPWR", 0 0, L_0000000003fdd480;  1 drivers, strength-aware
+v00000000039d9cb0_0 .net "Y", 0 0, L_000000000412ae90;  alias, 1 drivers
+S_0000000003a21700 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a1f300;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412b8a0 .functor AND 1, L_0000000003f90480, L_0000000004127ee0, C4<1>, C4<1>;
+L_000000000412a950 .functor AND 1, L_000000000412a6b0, L_0000000004126890, C4<1>, C4<1>;
+L_000000000412a330 .functor NOR 1, L_000000000412b8a0, L_000000000412b4b0, L_000000000412a950, C4<0>;
+L_000000000412ae90 .functor BUF 1, L_000000000412a330, C4<0>, C4<0>, C4<0>;
+v00000000039da4d0_0 .net "A1", 0 0, L_000000000412a6b0;  alias, 1 drivers
+v00000000039d93f0_0 .net "A2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039d8b30_0 .net "B1", 0 0, L_0000000003f90480;  alias, 1 drivers
+v00000000039d8ef0_0 .net "B2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039d89f0_0 .net "C1", 0 0, L_000000000412b4b0;  alias, 1 drivers
+L_0000000003fdd4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d9a30_0 .net8 "VGND", 0 0, L_0000000003fdd4f0;  1 drivers, strength-aware
+L_0000000003fdde20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d97b0_0 .net8 "VNB", 0 0, L_0000000003fdde20;  1 drivers, strength-aware
+L_0000000003fdd250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039da570_0 .net8 "VPB", 0 0, L_0000000003fdd250;  1 drivers, strength-aware
+L_0000000003fdc6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039da750_0 .net8 "VPWR", 0 0, L_0000000003fdc6f0;  1 drivers, strength-aware
+v00000000039dae30_0 .net "Y", 0 0, L_000000000412ae90;  alias, 1 drivers
+v00000000039d9350_0 .net "and0_out", 0 0, L_000000000412b8a0;  1 drivers
+v00000000039d9850_0 .net "and1_out", 0 0, L_000000000412a950;  1 drivers
+v00000000039dac50_0 .net "nor0_out_Y", 0 0, L_000000000412a330;  1 drivers
+S_0000000003a1e280 .scope module, "_0585_" "sky130_fd_sc_hd__or2_2" 3 922, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039da110_0 .net "A", 0 0, L_000000000412a800;  alias, 1 drivers
+v00000000039daed0_0 .net "B", 0 0, L_000000000412ae90;  alias, 1 drivers
+L_0000000003fdc760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039daf70_0 .net8 "VGND", 0 0, L_0000000003fdc760;  1 drivers, strength-aware
+L_0000000003fddbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039db0b0_0 .net8 "VNB", 0 0, L_0000000003fddbf0;  1 drivers, strength-aware
+L_0000000003fdca00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d8950_0 .net8 "VPB", 0 0, L_0000000003fdca00;  1 drivers, strength-aware
+L_0000000003fdd560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039d8a90_0 .net8 "VPWR", 0 0, L_0000000003fdd560;  1 drivers, strength-aware
+v00000000039d9170_0 .net "X", 0 0, L_000000000412b590;  alias, 1 drivers
+S_0000000003a1e580 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a1e280;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412b0c0 .functor OR 1, L_000000000412ae90, L_000000000412a800, C4<0>, C4<0>;
+L_000000000412b590 .functor BUF 1, L_000000000412b0c0, C4<0>, C4<0>, C4<0>;
+v00000000039daa70_0 .net "A", 0 0, L_000000000412a800;  alias, 1 drivers
+v00000000039dab10_0 .net "B", 0 0, L_000000000412ae90;  alias, 1 drivers
+L_0000000003fdd6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d90d0_0 .net8 "VGND", 0 0, L_0000000003fdd6b0;  1 drivers, strength-aware
+L_0000000003fdd800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d9d50_0 .net8 "VNB", 0 0, L_0000000003fdd800;  1 drivers, strength-aware
+L_0000000003fddc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dabb0_0 .net8 "VPB", 0 0, L_0000000003fddc60;  1 drivers, strength-aware
+L_0000000003fdcf40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dad90_0 .net8 "VPWR", 0 0, L_0000000003fdcf40;  1 drivers, strength-aware
+v00000000039d9df0_0 .net "X", 0 0, L_000000000412b590;  alias, 1 drivers
+v00000000039d9f30_0 .net "or0_out_X", 0 0, L_000000000412b0c0;  1 drivers
+S_0000000003a1d800 .scope module, "_0586_" "sky130_fd_sc_hd__inv_2" 3 927, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039dcf50_0 .net "A", 0 0, L_0000000003f919c0;  1 drivers
+L_0000000003fdc840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dbc90_0 .net8 "VGND", 0 0, L_0000000003fdc840;  1 drivers, strength-aware
+L_0000000003fdcfb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dcb90_0 .net8 "VNB", 0 0, L_0000000003fdcfb0;  1 drivers, strength-aware
+L_0000000003fdd020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dc690_0 .net8 "VPB", 0 0, L_0000000003fdd020;  1 drivers, strength-aware
+L_0000000003fdd870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dbe70_0 .net8 "VPWR", 0 0, L_0000000003fdd870;  1 drivers, strength-aware
+v00000000039db290_0 .net "Y", 0 0, L_000000000412adb0;  alias, 1 drivers
+S_0000000003a1f480 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a1d800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412b130 .functor NOT 1, L_0000000003f919c0, C4<0>, C4<0>, C4<0>;
+L_000000000412adb0 .functor BUF 1, L_000000000412b130, C4<0>, C4<0>, C4<0>;
+v00000000039d9210_0 .net "A", 0 0, L_0000000003f919c0;  alias, 1 drivers
+L_0000000003fddcd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039d92b0_0 .net8 "VGND", 0 0, L_0000000003fddcd0;  1 drivers, strength-aware
+L_0000000003fddd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dd3b0_0 .net8 "VNB", 0 0, L_0000000003fddd40;  1 drivers, strength-aware
+L_0000000003fdc8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dbdd0_0 .net8 "VPB", 0 0, L_0000000003fdc8b0;  1 drivers, strength-aware
+L_0000000003fdde90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dd450_0 .net8 "VPWR", 0 0, L_0000000003fdde90;  1 drivers, strength-aware
+v00000000039dbbf0_0 .net "Y", 0 0, L_000000000412adb0;  alias, 1 drivers
+v00000000039dc2d0_0 .net "not0_out_Y", 0 0, L_000000000412b130;  1 drivers
+S_0000000003a1f600 .scope module, "_0587_" "sky130_fd_sc_hd__a2bb2o_2" 3 931, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039dbab0_0 .net "A1_N", 0 0, L_00000000041258d0;  alias, 1 drivers
+v00000000039db830_0 .net "A2_N", 0 0, L_0000000003f90a20;  1 drivers
+v00000000039db1f0_0 .net "B1", 0 0, L_00000000041258d0;  alias, 1 drivers
+v00000000039dcc30_0 .net "B2", 0 0, L_0000000003f903e0;  1 drivers
+L_0000000003fddf00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dd270_0 .net8 "VGND", 0 0, L_0000000003fddf00;  1 drivers, strength-aware
+L_0000000003fddfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dbb50_0 .net8 "VNB", 0 0, L_0000000003fddfe0;  1 drivers, strength-aware
+L_0000000003fdc920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dbfb0_0 .net8 "VPB", 0 0, L_0000000003fdc920;  1 drivers, strength-aware
+L_0000000003fdca70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dc730_0 .net8 "VPWR", 0 0, L_0000000003fdca70;  1 drivers, strength-aware
+v00000000039dceb0_0 .net "X", 0 0, L_000000000412a9c0;  alias, 1 drivers
+S_0000000003a1d380 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a1f600;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412b910 .functor AND 1, L_00000000041258d0, L_0000000003f903e0, C4<1>, C4<1>;
+L_000000000412b1a0 .functor NOR 1, L_00000000041258d0, L_0000000003f90a20, C4<0>, C4<0>;
+L_000000000412a480 .functor OR 1, L_000000000412b1a0, L_000000000412b910, C4<0>, C4<0>;
+L_000000000412a9c0 .functor BUF 1, L_000000000412a480, C4<0>, C4<0>, C4<0>;
+v00000000039dccd0_0 .net "A1_N", 0 0, L_00000000041258d0;  alias, 1 drivers
+v00000000039dba10_0 .net "A2_N", 0 0, L_0000000003f90a20;  alias, 1 drivers
+v00000000039dcd70_0 .net "B1", 0 0, L_00000000041258d0;  alias, 1 drivers
+v00000000039dd1d0_0 .net "B2", 0 0, L_0000000003f903e0;  alias, 1 drivers
+L_0000000003fdcae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dbd30_0 .net8 "VGND", 0 0, L_0000000003fdcae0;  1 drivers, strength-aware
+L_0000000003fdcb50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dbf10_0 .net8 "VNB", 0 0, L_0000000003fdcb50;  1 drivers, strength-aware
+L_0000000003fdf470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039db970_0 .net8 "VPB", 0 0, L_0000000003fdf470;  1 drivers, strength-aware
+L_0000000003fdf2b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dcaf0_0 .net8 "VPWR", 0 0, L_0000000003fdf2b0;  1 drivers, strength-aware
+v00000000039dce10_0 .net "X", 0 0, L_000000000412a9c0;  alias, 1 drivers
+v00000000039db6f0_0 .net "and0_out", 0 0, L_000000000412b910;  1 drivers
+v00000000039dd8b0_0 .net "nor0_out", 0 0, L_000000000412b1a0;  1 drivers
+v00000000039dd310_0 .net "or0_out_X", 0 0, L_000000000412a480;  1 drivers
+S_0000000003a20200 .scope module, "_0588_" "sky130_fd_sc_hd__a221o_2" 3 938, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039dc190_0 .net "A1", 0 0, L_000000000412adb0;  alias, 1 drivers
+v00000000039dc4b0_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v00000000039dd770_0 .net "B1", 0 0, L_0000000003f91880;  1 drivers
+v00000000039dc230_0 .net "B2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039dc410_0 .net "C1", 0 0, L_000000000412a9c0;  alias, 1 drivers
+L_0000000003fdf780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039db5b0_0 .net8 "VGND", 0 0, L_0000000003fdf780;  1 drivers, strength-aware
+L_0000000003fdf1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039db790_0 .net8 "VNB", 0 0, L_0000000003fdf1d0;  1 drivers, strength-aware
+L_0000000003fdeb40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dc5f0_0 .net8 "VPB", 0 0, L_0000000003fdeb40;  1 drivers, strength-aware
+L_0000000003fde590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dd590_0 .net8 "VPWR", 0 0, L_0000000003fde590;  1 drivers, strength-aware
+v00000000039dd090_0 .net "X", 0 0, L_000000000412b210;  alias, 1 drivers
+S_0000000003a21a00 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a20200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412aa30 .functor AND 1, L_0000000003f91880, L_0000000004126190, C4<1>, C4<1>;
+L_000000000412a3a0 .functor AND 1, L_000000000412adb0, L_0000000004127a80, C4<1>, C4<1>;
+L_000000000412aaa0 .functor OR 1, L_000000000412a3a0, L_000000000412aa30, L_000000000412a9c0, C4<0>;
+L_000000000412b210 .functor BUF 1, L_000000000412aaa0, C4<0>, C4<0>, C4<0>;
+v00000000039dc050_0 .net "A1", 0 0, L_000000000412adb0;  alias, 1 drivers
+v00000000039db150_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v00000000039db330_0 .net "B1", 0 0, L_0000000003f91880;  alias, 1 drivers
+v00000000039db510_0 .net "B2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039db650_0 .net "C1", 0 0, L_000000000412a9c0;  alias, 1 drivers
+L_0000000003fde2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dc0f0_0 .net8 "VGND", 0 0, L_0000000003fde2f0;  1 drivers, strength-aware
+L_0000000003fde360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dca50_0 .net8 "VNB", 0 0, L_0000000003fde360;  1 drivers, strength-aware
+L_0000000003fdefa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dd130_0 .net8 "VPB", 0 0, L_0000000003fdefa0;  1 drivers, strength-aware
+L_0000000003fdfa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039db3d0_0 .net8 "VPWR", 0 0, L_0000000003fdfa20;  1 drivers, strength-aware
+v00000000039dc370_0 .net "X", 0 0, L_000000000412b210;  alias, 1 drivers
+v00000000039dd4f0_0 .net "and0_out", 0 0, L_000000000412aa30;  1 drivers
+v00000000039dc550_0 .net "and1_out", 0 0, L_000000000412a3a0;  1 drivers
+v00000000039db470_0 .net "or0_out_X", 0 0, L_000000000412aaa0;  1 drivers
+S_0000000003a21880 .scope module, "_0589_" "sky130_fd_sc_hd__nor2_2" 3 946, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039dd810_0 .net "A", 0 0, L_000000000412b590;  alias, 1 drivers
+v00000000039dfbb0_0 .net "B", 0 0, L_000000000412b210;  alias, 1 drivers
+L_0000000003fdebb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ddbd0_0 .net8 "VGND", 0 0, L_0000000003fdebb0;  1 drivers, strength-aware
+L_0000000003fdf9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039df570_0 .net8 "VNB", 0 0, L_0000000003fdf9b0;  1 drivers, strength-aware
+L_0000000003fdf630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dfc50_0 .net8 "VPB", 0 0, L_0000000003fdf630;  1 drivers, strength-aware
+L_0000000003fdf5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de5d0_0 .net8 "VPWR", 0 0, L_0000000003fdf5c0;  1 drivers, strength-aware
+v00000000039dfcf0_0 .net "Y", 0 0, L_000000000412b6e0;  alias, 1 drivers
+S_0000000003a1d080 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a21880;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412a1e0 .functor NOR 1, L_000000000412b590, L_000000000412b210, C4<0>, C4<0>;
+L_000000000412b6e0 .functor BUF 1, L_000000000412a1e0, C4<0>, C4<0>, C4<0>;
+v00000000039dcff0_0 .net "A", 0 0, L_000000000412b590;  alias, 1 drivers
+v00000000039dc7d0_0 .net "B", 0 0, L_000000000412b210;  alias, 1 drivers
+L_0000000003fdf8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039db8d0_0 .net8 "VGND", 0 0, L_0000000003fdf8d0;  1 drivers, strength-aware
+L_0000000003fdf7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dd630_0 .net8 "VNB", 0 0, L_0000000003fdf7f0;  1 drivers, strength-aware
+L_0000000003fdea60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dc870_0 .net8 "VPB", 0 0, L_0000000003fdea60;  1 drivers, strength-aware
+L_0000000003fdec20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dc910_0 .net8 "VPWR", 0 0, L_0000000003fdec20;  1 drivers, strength-aware
+v00000000039dd6d0_0 .net "Y", 0 0, L_000000000412b6e0;  alias, 1 drivers
+v00000000039dc9b0_0 .net "nor0_out_Y", 0 0, L_000000000412a1e0;  1 drivers
+S_0000000003a1d200 .scope module, "_0590_" "sky130_fd_sc_hd__inv_2" 3 951, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039dfed0_0 .net "A", 0 0, L_0000000003f90de0;  1 drivers
+L_0000000003fdeec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dfa70_0 .net8 "VGND", 0 0, L_0000000003fdeec0;  1 drivers, strength-aware
+L_0000000003fdf4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039ddb30_0 .net8 "VNB", 0 0, L_0000000003fdf4e0;  1 drivers, strength-aware
+L_0000000003fdfa90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039df7f0_0 .net8 "VPB", 0 0, L_0000000003fdfa90;  1 drivers, strength-aware
+L_0000000003fde670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dee90_0 .net8 "VPWR", 0 0, L_0000000003fde670;  1 drivers, strength-aware
+v00000000039de710_0 .net "Y", 0 0, L_000000000412b600;  alias, 1 drivers
+S_0000000003a21d00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a1d200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412a250 .functor NOT 1, L_0000000003f90de0, C4<0>, C4<0>, C4<0>;
+L_000000000412b600 .functor BUF 1, L_000000000412a250, C4<0>, C4<0>, C4<0>;
+v00000000039ddc70_0 .net "A", 0 0, L_0000000003f90de0;  alias, 1 drivers
+L_0000000003fdec90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039df750_0 .net8 "VGND", 0 0, L_0000000003fdec90;  1 drivers, strength-aware
+L_0000000003fdf240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039de670_0 .net8 "VNB", 0 0, L_0000000003fdf240;  1 drivers, strength-aware
+L_0000000003fdfb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039dda90_0 .net8 "VPB", 0 0, L_0000000003fdfb00;  1 drivers, strength-aware
+L_0000000003fdf860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de530_0 .net8 "VPWR", 0 0, L_0000000003fdf860;  1 drivers, strength-aware
+v00000000039de0d0_0 .net "Y", 0 0, L_000000000412b600;  alias, 1 drivers
+v00000000039de2b0_0 .net "not0_out_Y", 0 0, L_000000000412a250;  1 drivers
+S_0000000003a20f80 .scope module, "_0591_" "sky130_fd_sc_hd__a2bb2o_2" 3 955, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039ddf90_0 .net "A1_N", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039df9d0_0 .net "A2_N", 0 0, L_0000000003f91f60;  1 drivers
+v00000000039df890_0 .net "B1", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039dddb0_0 .net "B2", 0 0, L_0000000003f90660;  1 drivers
+L_0000000003fde8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039df430_0 .net8 "VGND", 0 0, L_0000000003fde8a0;  1 drivers, strength-aware
+L_0000000003fdf550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dde50_0 .net8 "VNB", 0 0, L_0000000003fdf550;  1 drivers, strength-aware
+L_0000000003fdef30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039decb0_0 .net8 "VPB", 0 0, L_0000000003fdef30;  1 drivers, strength-aware
+L_0000000003fdf320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de170_0 .net8 "VPWR", 0 0, L_0000000003fdf320;  1 drivers, strength-aware
+v00000000039dfe30_0 .net "X", 0 0, L_000000000412d6d0;  alias, 1 drivers
+S_0000000003a22600 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a20f80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412b750 .functor AND 1, L_00000000041279a0, L_0000000003f90660, C4<1>, C4<1>;
+L_000000000412b980 .functor NOR 1, L_00000000041279a0, L_0000000003f91f60, C4<0>, C4<0>;
+L_000000000412ba60 .functor OR 1, L_000000000412b980, L_000000000412b750, C4<0>, C4<0>;
+L_000000000412d6d0 .functor BUF 1, L_000000000412ba60, C4<0>, C4<0>, C4<0>;
+v00000000039dfb10_0 .net "A1_N", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039dd9f0_0 .net "A2_N", 0 0, L_0000000003f91f60;  alias, 1 drivers
+v00000000039de490_0 .net "B1", 0 0, L_00000000041279a0;  alias, 1 drivers
+v00000000039df070_0 .net "B2", 0 0, L_0000000003f90660;  alias, 1 drivers
+L_0000000003fdfb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039de030_0 .net8 "VGND", 0 0, L_0000000003fdfb70;  1 drivers, strength-aware
+L_0000000003fded70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039de7b0_0 .net8 "VNB", 0 0, L_0000000003fded70;  1 drivers, strength-aware
+L_0000000003fde210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039ddef0_0 .net8 "VPB", 0 0, L_0000000003fde210;  1 drivers, strength-aware
+L_0000000003fde6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de850_0 .net8 "VPWR", 0 0, L_0000000003fde6e0;  1 drivers, strength-aware
+v00000000039df1b0_0 .net "X", 0 0, L_000000000412d6d0;  alias, 1 drivers
+v00000000039dff70_0 .net "and0_out", 0 0, L_000000000412b750;  1 drivers
+v00000000039dfd90_0 .net "nor0_out", 0 0, L_000000000412b980;  1 drivers
+v00000000039ddd10_0 .net "or0_out_X", 0 0, L_000000000412ba60;  1 drivers
+S_0000000003a22000 .scope module, "_0592_" "sky130_fd_sc_hd__o221a_2" 3 962, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039deb70_0 .net "A1", 0 0, L_0000000003f91920;  1 drivers
+v00000000039def30_0 .net "A2", 0 0, L_0000000004125470;  alias, 1 drivers
+v00000000039defd0_0 .net "B1", 0 0, L_000000000412b600;  alias, 1 drivers
+v00000000039df110_0 .net "B2", 0 0, L_0000000004127620;  alias, 1 drivers
+v00000000039df610_0 .net "C1", 0 0, L_000000000412d6d0;  alias, 1 drivers
+L_0000000003fde280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039df250_0 .net8 "VGND", 0 0, L_0000000003fde280;  1 drivers, strength-aware
+L_0000000003fdfbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039df2f0_0 .net8 "VNB", 0 0, L_0000000003fdfbe0;  1 drivers, strength-aware
+L_0000000003fdf6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039df390_0 .net8 "VPB", 0 0, L_0000000003fdf6a0;  1 drivers, strength-aware
+L_0000000003fdf710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039df4d0_0 .net8 "VPWR", 0 0, L_0000000003fdf710;  1 drivers, strength-aware
+v00000000039df6b0_0 .net "X", 0 0, L_000000000412bec0;  alias, 1 drivers
+S_0000000003a20500 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a22000;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412cb00 .functor OR 1, L_0000000004127620, L_000000000412b600, C4<0>, C4<0>;
+L_000000000412cda0 .functor OR 1, L_0000000004125470, L_0000000003f91920, C4<0>, C4<0>;
+L_000000000412d740 .functor AND 1, L_000000000412cb00, L_000000000412cda0, L_000000000412d6d0, C4<1>;
+L_000000000412bec0 .functor BUF 1, L_000000000412d740, C4<0>, C4<0>, C4<0>;
+v00000000039ded50_0 .net "A1", 0 0, L_0000000003f91920;  alias, 1 drivers
+v00000000039dec10_0 .net "A2", 0 0, L_0000000004125470;  alias, 1 drivers
+v00000000039de210_0 .net "B1", 0 0, L_000000000412b600;  alias, 1 drivers
+v00000000039de8f0_0 .net "B2", 0 0, L_0000000004127620;  alias, 1 drivers
+v00000000039e0010_0 .net "C1", 0 0, L_000000000412d6d0;  alias, 1 drivers
+L_0000000003fdf940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039dedf0_0 .net8 "VGND", 0 0, L_0000000003fdf940;  1 drivers, strength-aware
+L_0000000003fdfc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e00b0_0 .net8 "VNB", 0 0, L_0000000003fdfc50;  1 drivers, strength-aware
+L_0000000003fdead0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de350_0 .net8 "VPB", 0 0, L_0000000003fdead0;  1 drivers, strength-aware
+L_0000000003fded00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039de990_0 .net8 "VPWR", 0 0, L_0000000003fded00;  1 drivers, strength-aware
+v00000000039de3f0_0 .net "X", 0 0, L_000000000412bec0;  alias, 1 drivers
+v00000000039dd950_0 .net "and0_out_X", 0 0, L_000000000412d740;  1 drivers
+v00000000039dea30_0 .net "or0_out", 0 0, L_000000000412cb00;  1 drivers
+v00000000039dead0_0 .net "or1_out", 0 0, L_000000000412cda0;  1 drivers
+S_0000000003a21100 .scope module, "_0593_" "sky130_fd_sc_hd__inv_2" 3 970, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e14b0_0 .net "A", 0 0, L_000000000412b210;  alias, 1 drivers
+L_0000000003fdf010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e0c90_0 .net8 "VGND", 0 0, L_0000000003fdf010;  1 drivers, strength-aware
+L_0000000003fde0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1e10_0 .net8 "VNB", 0 0, L_0000000003fde0c0;  1 drivers, strength-aware
+L_0000000003fde130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e23b0_0 .net8 "VPB", 0 0, L_0000000003fde130;  1 drivers, strength-aware
+L_0000000003fde750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e0fb0_0 .net8 "VPWR", 0 0, L_0000000003fde750;  1 drivers, strength-aware
+v00000000039e2450_0 .net "Y", 0 0, L_000000000412c780;  alias, 1 drivers
+S_0000000003a22180 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a21100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412cf60 .functor NOT 1, L_000000000412b210, C4<0>, C4<0>, C4<0>;
+L_000000000412c780 .functor BUF 1, L_000000000412cf60, C4<0>, C4<0>, C4<0>;
+v00000000039df930_0 .net "A", 0 0, L_000000000412b210;  alias, 1 drivers
+L_0000000003fdede0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1050_0 .net8 "VGND", 0 0, L_0000000003fdede0;  1 drivers, strength-aware
+L_0000000003fdf390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e0dd0_0 .net8 "VNB", 0 0, L_0000000003fdf390;  1 drivers, strength-aware
+L_0000000003fde1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e1cd0_0 .net8 "VPB", 0 0, L_0000000003fde1a0;  1 drivers, strength-aware
+L_0000000003fde3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e0d30_0 .net8 "VPWR", 0 0, L_0000000003fde3d0;  1 drivers, strength-aware
+v00000000039e0bf0_0 .net "Y", 0 0, L_000000000412c780;  alias, 1 drivers
+v00000000039e0e70_0 .net "not0_out_Y", 0 0, L_000000000412cf60;  1 drivers
+S_0000000003a1fa80 .scope module, "_0594_" "sky130_fd_sc_hd__o221a_2" 3 974, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039e0f10_0 .net "A1", 0 0, L_0000000003f8fd00;  1 drivers
+v00000000039e2590_0 .net "A2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039e12d0_0 .net "B1", 0 0, L_000000000412adb0;  alias, 1 drivers
+v00000000039e2630_0 .net "B2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039e2770_0 .net "C1", 0 0, L_000000000412a9c0;  alias, 1 drivers
+L_0000000003fde910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e05b0_0 .net8 "VGND", 0 0, L_0000000003fde910;  1 drivers, strength-aware
+L_0000000003fde440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1190_0 .net8 "VNB", 0 0, L_0000000003fde440;  1 drivers, strength-aware
+L_0000000003fdf080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e2810_0 .net8 "VPB", 0 0, L_0000000003fdf080;  1 drivers, strength-aware
+L_0000000003fdf400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e1730_0 .net8 "VPWR", 0 0, L_0000000003fdf400;  1 drivers, strength-aware
+v00000000039e2090_0 .net "X", 0 0, L_000000000412c8d0;  alias, 1 drivers
+S_0000000003a22480 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a1fa80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412d350 .functor OR 1, L_0000000004126890, L_000000000412adb0, C4<0>, C4<0>;
+L_000000000412be50 .functor OR 1, L_0000000004127ee0, L_0000000003f8fd00, C4<0>, C4<0>;
+L_000000000412cfd0 .functor AND 1, L_000000000412d350, L_000000000412be50, L_000000000412a9c0, C4<1>;
+L_000000000412c8d0 .functor BUF 1, L_000000000412cfd0, C4<0>, C4<0>, C4<0>;
+v00000000039e0b50_0 .net "A1", 0 0, L_0000000003f8fd00;  alias, 1 drivers
+v00000000039e17d0_0 .net "A2", 0 0, L_0000000004127ee0;  alias, 1 drivers
+v00000000039e1690_0 .net "B1", 0 0, L_000000000412adb0;  alias, 1 drivers
+v00000000039e24f0_0 .net "B2", 0 0, L_0000000004126890;  alias, 1 drivers
+v00000000039e0290_0 .net "C1", 0 0, L_000000000412a9c0;  alias, 1 drivers
+L_0000000003fde4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e21d0_0 .net8 "VGND", 0 0, L_0000000003fde4b0;  1 drivers, strength-aware
+L_0000000003fdee50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e08d0_0 .net8 "VNB", 0 0, L_0000000003fdee50;  1 drivers, strength-aware
+L_0000000003fde520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e0ab0_0 .net8 "VPB", 0 0, L_0000000003fde520;  1 drivers, strength-aware
+L_0000000003fde7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e0330_0 .net8 "VPWR", 0 0, L_0000000003fde7c0;  1 drivers, strength-aware
+v00000000039e26d0_0 .net "X", 0 0, L_000000000412c8d0;  alias, 1 drivers
+v00000000039e1d70_0 .net "and0_out_X", 0 0, L_000000000412cfd0;  1 drivers
+v00000000039e28b0_0 .net "or0_out", 0 0, L_000000000412d350;  1 drivers
+v00000000039e03d0_0 .net "or1_out", 0 0, L_000000000412be50;  1 drivers
+S_0000000003a22780 .scope module, "_0595_" "sky130_fd_sc_hd__nor2_2" 3 982, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039e1550_0 .net "A", 0 0, L_000000000412c780;  alias, 1 drivers
+v00000000039e0470_0 .net "B", 0 0, L_000000000412c8d0;  alias, 1 drivers
+L_0000000003fde600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e0150_0 .net8 "VGND", 0 0, L_0000000003fde600;  1 drivers, strength-aware
+L_0000000003fde980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1910_0 .net8 "VNB", 0 0, L_0000000003fde980;  1 drivers, strength-aware
+L_0000000003fde830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e10f0_0 .net8 "VPB", 0 0, L_0000000003fde830;  1 drivers, strength-aware
+L_0000000003fdf0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e1a50_0 .net8 "VPWR", 0 0, L_0000000003fdf0f0;  1 drivers, strength-aware
+v00000000039e1af0_0 .net "Y", 0 0, L_000000000412c010;  alias, 1 drivers
+S_0000000003a1df80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a22780;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412c550 .functor NOR 1, L_000000000412c780, L_000000000412c8d0, C4<0>, C4<0>;
+L_000000000412c010 .functor BUF 1, L_000000000412c550, C4<0>, C4<0>, C4<0>;
+v00000000039e1870_0 .net "A", 0 0, L_000000000412c780;  alias, 1 drivers
+v00000000039e1410_0 .net "B", 0 0, L_000000000412c8d0;  alias, 1 drivers
+L_0000000003fdf160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1eb0_0 .net8 "VGND", 0 0, L_0000000003fdf160;  1 drivers, strength-aware
+L_0000000003fde9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e06f0_0 .net8 "VNB", 0 0, L_0000000003fde9f0;  1 drivers, strength-aware
+L_0000000003fe0890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e15f0_0 .net8 "VPB", 0 0, L_0000000003fe0890;  1 drivers, strength-aware
+L_0000000003fdfcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e1370_0 .net8 "VPWR", 0 0, L_0000000003fdfcc0;  1 drivers, strength-aware
+v00000000039e19b0_0 .net "Y", 0 0, L_000000000412c010;  alias, 1 drivers
+v00000000039e1f50_0 .net "nor0_out_Y", 0 0, L_000000000412c550;  1 drivers
+S_0000000003a22900 .scope module, "_0596_" "sky130_fd_sc_hd__or2_2" 3 987, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039e0790_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v00000000039e0830_0 .net "B", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000003fdfd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e0970_0 .net8 "VGND", 0 0, L_0000000003fdfd30;  1 drivers, strength-aware
+L_0000000003fe10e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e0a10_0 .net8 "VNB", 0 0, L_0000000003fe10e0;  1 drivers, strength-aware
+L_0000000003fe0190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e2270_0 .net8 "VPB", 0 0, L_0000000003fe0190;  1 drivers, strength-aware
+L_0000000003fe0a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e2310_0 .net8 "VPWR", 0 0, L_0000000003fe0a50;  1 drivers, strength-aware
+v00000000039e4610_0 .net "X", 0 0, L_000000000412cef0;  alias, 1 drivers
+S_0000000003a1d980 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a22900;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412c630 .functor OR 1, L_000000000412c010, L_000000000412bec0, C4<0>, C4<0>;
+L_000000000412cef0 .functor BUF 1, L_000000000412c630, C4<0>, C4<0>, C4<0>;
+v00000000039e1230_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v00000000039e01f0_0 .net "B", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000003fe0e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1b90_0 .net8 "VGND", 0 0, L_0000000003fe0e40;  1 drivers, strength-aware
+L_0000000003fe0900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e1c30_0 .net8 "VNB", 0 0, L_0000000003fe0900;  1 drivers, strength-aware
+L_0000000003fe1230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e1ff0_0 .net8 "VPB", 0 0, L_0000000003fe1230;  1 drivers, strength-aware
+L_0000000003fe04a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e0510_0 .net8 "VPWR", 0 0, L_0000000003fe04a0;  1 drivers, strength-aware
+v00000000039e0650_0 .net "X", 0 0, L_000000000412cef0;  alias, 1 drivers
+v00000000039e2130_0 .net "or0_out_X", 0 0, L_000000000412c630;  1 drivers
+S_0000000003a1f780 .scope module, "_0597_" "sky130_fd_sc_hd__inv_2" 3 992, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e2ef0_0 .net "A", 0 0, L_000000000412b590;  alias, 1 drivers
+L_0000000003fdff60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e44d0_0 .net8 "VGND", 0 0, L_0000000003fdff60;  1 drivers, strength-aware
+L_0000000003fe06d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e4cf0_0 .net8 "VNB", 0 0, L_0000000003fe06d0;  1 drivers, strength-aware
+L_0000000003fe0580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e4570_0 .net8 "VPB", 0 0, L_0000000003fe0580;  1 drivers, strength-aware
+L_0000000003fe09e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3490_0 .net8 "VPWR", 0 0, L_0000000003fe09e0;  1 drivers, strength-aware
+v00000000039e4250_0 .net "Y", 0 0, L_000000000412d820;  alias, 1 drivers
+S_0000000003a1d500 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a1f780;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412c860 .functor NOT 1, L_000000000412b590, C4<0>, C4<0>, C4<0>;
+L_000000000412d820 .functor BUF 1, L_000000000412c860, C4<0>, C4<0>, C4<0>;
+v00000000039e3c10_0 .net "A", 0 0, L_000000000412b590;  alias, 1 drivers
+L_0000000003fe05f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e4750_0 .net8 "VGND", 0 0, L_0000000003fe05f0;  1 drivers, strength-aware
+L_0000000003fe0cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e3710_0 .net8 "VNB", 0 0, L_0000000003fe0cf0;  1 drivers, strength-aware
+L_0000000003fe12a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e49d0_0 .net8 "VPB", 0 0, L_0000000003fe12a0;  1 drivers, strength-aware
+L_0000000003fe1770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e2db0_0 .net8 "VPWR", 0 0, L_0000000003fe1770;  1 drivers, strength-aware
+v00000000039e3530_0 .net "Y", 0 0, L_000000000412d820;  alias, 1 drivers
+v00000000039e3670_0 .net "not0_out_Y", 0 0, L_000000000412c860;  1 drivers
+S_0000000003a1db00 .scope module, "_0598_" "sky130_fd_sc_hd__or2_2" 3 996, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039e33f0_0 .net "A", 0 0, L_000000000412d820;  alias, 1 drivers
+v00000000039e2b30_0 .net "B", 0 0, L_000000000412c780;  alias, 1 drivers
+L_0000000003fe1850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e2e50_0 .net8 "VGND", 0 0, L_0000000003fe1850;  1 drivers, strength-aware
+L_0000000003fe0970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e29f0_0 .net8 "VNB", 0 0, L_0000000003fe0970;  1 drivers, strength-aware
+L_0000000003fe0dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e38f0_0 .net8 "VPB", 0 0, L_0000000003fe0dd0;  1 drivers, strength-aware
+L_0000000003fe0510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3990_0 .net8 "VPWR", 0 0, L_0000000003fe0510;  1 drivers, strength-aware
+v00000000039e47f0_0 .net "X", 0 0, L_000000000412d7b0;  alias, 1 drivers
+S_0000000003a1fc00 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a1db00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412bfa0 .functor OR 1, L_000000000412c780, L_000000000412d820, C4<0>, C4<0>;
+L_000000000412d7b0 .functor BUF 1, L_000000000412bfa0, C4<0>, C4<0>, C4<0>;
+v00000000039e30d0_0 .net "A", 0 0, L_000000000412d820;  alias, 1 drivers
+v00000000039e4390_0 .net "B", 0 0, L_000000000412c780;  alias, 1 drivers
+L_0000000003fdfda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e35d0_0 .net8 "VGND", 0 0, L_0000000003fdfda0;  1 drivers, strength-aware
+L_0000000003fe1150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e37b0_0 .net8 "VNB", 0 0, L_0000000003fe1150;  1 drivers, strength-aware
+L_0000000003fe11c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3cb0_0 .net8 "VPB", 0 0, L_0000000003fe11c0;  1 drivers, strength-aware
+L_0000000003fe0660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e4430_0 .net8 "VPWR", 0 0, L_0000000003fe0660;  1 drivers, strength-aware
+v00000000039e46b0_0 .net "X", 0 0, L_000000000412d7b0;  alias, 1 drivers
+v00000000039e3850_0 .net "or0_out_X", 0 0, L_000000000412bfa0;  1 drivers
+S_0000000003a22a80 .scope module, "_0599_" "sky130_fd_sc_hd__o21ai_2" 3 1001, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v00000000039e4d90_0 .net "A1", 0 0, L_000000000412b6e0;  alias, 1 drivers
+v00000000039e4ed0_0 .net "A2", 0 0, L_000000000412cef0;  alias, 1 drivers
+v00000000039e4e30_0 .net "B1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+L_0000000003fe1310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e50b0_0 .net8 "VGND", 0 0, L_0000000003fe1310;  1 drivers, strength-aware
+L_0000000003fe0740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e2bd0_0 .net8 "VNB", 0 0, L_0000000003fe0740;  1 drivers, strength-aware
+L_0000000003fe0f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e4f70_0 .net8 "VPB", 0 0, L_0000000003fe0f20;  1 drivers, strength-aware
+L_0000000003fe0ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3e90_0 .net8 "VPWR", 0 0, L_0000000003fe0ba0;  1 drivers, strength-aware
+v00000000039e5010_0 .net "Y", 0 0, L_000000000412bd00;  alias, 1 drivers
+S_0000000003a1fd80 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a22a80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412d890 .functor OR 1, L_000000000412cef0, L_000000000412b6e0, C4<0>, C4<0>;
+L_000000000412d040 .functor NAND 1, L_000000000412d7b0, L_000000000412d890, C4<1>, C4<1>;
+L_000000000412bd00 .functor BUF 1, L_000000000412d040, C4<0>, C4<0>, C4<0>;
+v00000000039e4890_0 .net "A1", 0 0, L_000000000412b6e0;  alias, 1 drivers
+v00000000039e2f90_0 .net "A2", 0 0, L_000000000412cef0;  alias, 1 drivers
+v00000000039e4930_0 .net "B1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+L_0000000003fdfe10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e3a30_0 .net8 "VGND", 0 0, L_0000000003fdfe10;  1 drivers, strength-aware
+L_0000000003fe07b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e2c70_0 .net8 "VNB", 0 0, L_0000000003fe07b0;  1 drivers, strength-aware
+L_0000000003fe1380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e4a70_0 .net8 "VPB", 0 0, L_0000000003fe1380;  1 drivers, strength-aware
+L_0000000003fe0430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e4b10_0 .net8 "VPWR", 0 0, L_0000000003fe0430;  1 drivers, strength-aware
+v00000000039e4c50_0 .net "Y", 0 0, L_000000000412bd00;  alias, 1 drivers
+v00000000039e2a90_0 .net "nand0_out_Y", 0 0, L_000000000412d040;  1 drivers
+v00000000039e4bb0_0 .net "or0_out", 0 0, L_000000000412d890;  1 drivers
+S_0000000003a20080 .scope module, "_0600_" "sky130_fd_sc_hd__inv_2" 3 1007, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e3b70_0 .net "A", 0 0, L_0000000003f91c40;  1 drivers
+L_0000000003fe15b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e3210_0 .net8 "VGND", 0 0, L_0000000003fe15b0;  1 drivers, strength-aware
+L_0000000003fdffd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e32b0_0 .net8 "VNB", 0 0, L_0000000003fdffd0;  1 drivers, strength-aware
+L_0000000003fe1620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3350_0 .net8 "VPB", 0 0, L_0000000003fe1620;  1 drivers, strength-aware
+L_0000000003fdfe80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3d50_0 .net8 "VPWR", 0 0, L_0000000003fdfe80;  1 drivers, strength-aware
+v00000000039e3df0_0 .net "Y", 0 0, L_000000000412d120;  alias, 1 drivers
+S_0000000003a20680 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a20080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412bd70 .functor NOT 1, L_0000000003f91c40, C4<0>, C4<0>, C4<0>;
+L_000000000412d120 .functor BUF 1, L_000000000412bd70, C4<0>, C4<0>, C4<0>;
+v00000000039e2950_0 .net "A", 0 0, L_0000000003f91c40;  alias, 1 drivers
+L_0000000003fe0ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e42f0_0 .net8 "VGND", 0 0, L_0000000003fe0ac0;  1 drivers, strength-aware
+L_0000000003fe13f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e4070_0 .net8 "VNB", 0 0, L_0000000003fe13f0;  1 drivers, strength-aware
+L_0000000003fdfef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3030_0 .net8 "VPB", 0 0, L_0000000003fdfef0;  1 drivers, strength-aware
+L_0000000003fe0b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e3ad0_0 .net8 "VPWR", 0 0, L_0000000003fe0b30;  1 drivers, strength-aware
+v00000000039e2d10_0 .net "Y", 0 0, L_000000000412d120;  alias, 1 drivers
+v00000000039e3170_0 .net "not0_out_Y", 0 0, L_000000000412bd70;  1 drivers
+S_0000000003a20800 .scope module, "_0601_" "sky130_fd_sc_hd__buf_1" 3 1011, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e7770_0 .net "A", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003fe0c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e6410_0 .net8 "VGND", 0 0, L_0000000003fe0c10;  1 drivers, strength-aware
+L_0000000003fe0820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e5290_0 .net8 "VNB", 0 0, L_0000000003fe0820;  1 drivers, strength-aware
+L_0000000003fe0040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e5e70_0 .net8 "VPB", 0 0, L_0000000003fe0040;  1 drivers, strength-aware
+L_0000000003fe0eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e5bf0_0 .net8 "VPWR", 0 0, L_0000000003fe0eb0;  1 drivers, strength-aware
+v00000000039e5ab0_0 .net "X", 0 0, L_000000000412d0b0;  alias, 1 drivers
+S_0000000003a20980 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a20800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412bde0 .functor BUF 1, L_0000000004127620, C4<0>, C4<0>, C4<0>;
+L_000000000412d0b0 .functor BUF 1, L_000000000412bde0, C4<0>, C4<0>, C4<0>;
+v00000000039e3f30_0 .net "A", 0 0, L_0000000004127620;  alias, 1 drivers
+L_0000000003fe0c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e3fd0_0 .net8 "VGND", 0 0, L_0000000003fe0c80;  1 drivers, strength-aware
+L_0000000003fe00b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e4110_0 .net8 "VNB", 0 0, L_0000000003fe00b0;  1 drivers, strength-aware
+L_0000000003fe0f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e41b0_0 .net8 "VPB", 0 0, L_0000000003fe0f90;  1 drivers, strength-aware
+L_0000000003fe0270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7130_0 .net8 "VPWR", 0 0, L_0000000003fe0270;  1 drivers, strength-aware
+v00000000039e6910_0 .net "X", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v00000000039e62d0_0 .net "buf0_out_X", 0 0, L_000000000412bde0;  1 drivers
+S_0000000003a20c80 .scope module, "_0602_" "sky130_fd_sc_hd__buf_1" 3 1015, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e6c30_0 .net "A", 0 0, L_0000000004125470;  alias, 1 drivers
+L_0000000003fe0d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e6cd0_0 .net8 "VGND", 0 0, L_0000000003fe0d60;  1 drivers, strength-aware
+L_0000000003fe0120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e6730_0 .net8 "VNB", 0 0, L_0000000003fe0120;  1 drivers, strength-aware
+L_0000000003fe0200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7590_0 .net8 "VPB", 0 0, L_0000000003fe0200;  1 drivers, strength-aware
+L_0000000003fe1000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e5f10_0 .net8 "VPWR", 0 0, L_0000000003fe1000;  1 drivers, strength-aware
+v00000000039e7810_0 .net "X", 0 0, L_000000000412c1d0;  alias, 1 drivers
+S_0000000003a23200 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a20c80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412c6a0 .functor BUF 1, L_0000000004125470, C4<0>, C4<0>, C4<0>;
+L_000000000412c1d0 .functor BUF 1, L_000000000412c6a0, C4<0>, C4<0>, C4<0>;
+v00000000039e74f0_0 .net "A", 0 0, L_0000000004125470;  alias, 1 drivers
+L_0000000003fe1070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e7090_0 .net8 "VGND", 0 0, L_0000000003fe1070;  1 drivers, strength-aware
+L_0000000003fe1460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e5650_0 .net8 "VNB", 0 0, L_0000000003fe1460;  1 drivers, strength-aware
+L_0000000003fe14d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e6690_0 .net8 "VPB", 0 0, L_0000000003fe14d0;  1 drivers, strength-aware
+L_0000000003fe1540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e5830_0 .net8 "VPWR", 0 0, L_0000000003fe1540;  1 drivers, strength-aware
+v00000000039e71d0_0 .net "X", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v00000000039e5150_0 .net "buf0_out_X", 0 0, L_000000000412c6a0;  1 drivers
+S_0000000003a23b00 .scope module, "_0603_" "sky130_fd_sc_hd__a2bb2o_2" 3 1019, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v00000000039e58d0_0 .net "A1_N", 0 0, L_0000000004126510;  alias, 1 drivers
+v00000000039e6d70_0 .net "A2_N", 0 0, L_0000000003f911a0;  1 drivers
+v00000000039e56f0_0 .net "B1", 0 0, L_0000000004126510;  alias, 1 drivers
+v00000000039e6050_0 .net "B2", 0 0, L_0000000003f90e80;  1 drivers
+L_0000000003fe1690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e69b0_0 .net8 "VGND", 0 0, L_0000000003fe1690;  1 drivers, strength-aware
+L_0000000003fe1700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e51f0_0 .net8 "VNB", 0 0, L_0000000003fe1700;  1 drivers, strength-aware
+L_0000000003fe02e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7310_0 .net8 "VPB", 0 0, L_0000000003fe02e0;  1 drivers, strength-aware
+L_0000000003fe0350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e53d0_0 .net8 "VPWR", 0 0, L_0000000003fe0350;  1 drivers, strength-aware
+v00000000039e64b0_0 .net "X", 0 0, L_000000000412d5f0;  alias, 1 drivers
+S_0000000003a24880 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a23b00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412d580 .functor AND 1, L_0000000004126510, L_0000000003f90e80, C4<1>, C4<1>;
+L_000000000412c4e0 .functor NOR 1, L_0000000004126510, L_0000000003f911a0, C4<0>, C4<0>;
+L_000000000412d3c0 .functor OR 1, L_000000000412c4e0, L_000000000412d580, C4<0>, C4<0>;
+L_000000000412d5f0 .functor BUF 1, L_000000000412d3c0, C4<0>, C4<0>, C4<0>;
+v00000000039e6a50_0 .net "A1_N", 0 0, L_0000000004126510;  alias, 1 drivers
+v00000000039e6b90_0 .net "A2_N", 0 0, L_0000000003f911a0;  alias, 1 drivers
+v00000000039e6ff0_0 .net "B1", 0 0, L_0000000004126510;  alias, 1 drivers
+v00000000039e67d0_0 .net "B2", 0 0, L_0000000003f90e80;  alias, 1 drivers
+L_0000000003fe17e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e7270_0 .net8 "VGND", 0 0, L_0000000003fe17e0;  1 drivers, strength-aware
+L_0000000003fe03c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e5470_0 .net8 "VNB", 0 0, L_0000000003fe03c0;  1 drivers, strength-aware
+L_0000000003fe1fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7630_0 .net8 "VPB", 0 0, L_0000000003fe1fc0;  1 drivers, strength-aware
+L_0000000003fe3370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e6370_0 .net8 "VPWR", 0 0, L_0000000003fe3370;  1 drivers, strength-aware
+v00000000039e76d0_0 .net "X", 0 0, L_000000000412d5f0;  alias, 1 drivers
+v00000000039e55b0_0 .net "and0_out", 0 0, L_000000000412d580;  1 drivers
+v00000000039e6190_0 .net "nor0_out", 0 0, L_000000000412c4e0;  1 drivers
+v00000000039e78b0_0 .net "or0_out_X", 0 0, L_000000000412d3c0;  1 drivers
+S_0000000003a24a00 .scope module, "_0604_" "sky130_fd_sc_hd__a221o_2" 3 1026, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039e5a10_0 .net "A1", 0 0, L_000000000412d120;  alias, 1 drivers
+v00000000039e5b50_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v00000000039e5c90_0 .net "B1", 0 0, L_0000000003f90700;  1 drivers
+v00000000039e5d30_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v00000000039e5dd0_0 .net "C1", 0 0, L_000000000412d5f0;  alias, 1 drivers
+L_0000000003fe2ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e5fb0_0 .net8 "VGND", 0 0, L_0000000003fe2ea0;  1 drivers, strength-aware
+L_0000000003fe1ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e60f0_0 .net8 "VNB", 0 0, L_0000000003fe1ee0;  1 drivers, strength-aware
+L_0000000003fe2e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e6230_0 .net8 "VPB", 0 0, L_0000000003fe2e30;  1 drivers, strength-aware
+L_0000000003fe2810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e8490_0 .net8 "VPWR", 0 0, L_0000000003fe2810;  1 drivers, strength-aware
+v00000000039e8d50_0 .net "X", 0 0, L_000000000412bf30;  alias, 1 drivers
+S_0000000003a24280 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a24a00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412cb70 .functor AND 1, L_0000000003f90700, L_000000000412c1d0, C4<1>, C4<1>;
+L_000000000412c9b0 .functor AND 1, L_000000000412d120, L_000000000412d0b0, C4<1>, C4<1>;
+L_000000000412d270 .functor OR 1, L_000000000412c9b0, L_000000000412cb70, L_000000000412d5f0, C4<0>;
+L_000000000412bf30 .functor BUF 1, L_000000000412d270, C4<0>, C4<0>, C4<0>;
+v00000000039e6e10_0 .net "A1", 0 0, L_000000000412d120;  alias, 1 drivers
+v00000000039e6550_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v00000000039e6af0_0 .net "B1", 0 0, L_0000000003f90700;  alias, 1 drivers
+v00000000039e5790_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v00000000039e5330_0 .net "C1", 0 0, L_000000000412d5f0;  alias, 1 drivers
+L_0000000003fe33e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e6eb0_0 .net8 "VGND", 0 0, L_0000000003fe33e0;  1 drivers, strength-aware
+L_0000000003fe2ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e73b0_0 .net8 "VNB", 0 0, L_0000000003fe2ce0;  1 drivers, strength-aware
+L_0000000003fe1bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e5510_0 .net8 "VPB", 0 0, L_0000000003fe1bd0;  1 drivers, strength-aware
+L_0000000003fe1c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e65f0_0 .net8 "VPWR", 0 0, L_0000000003fe1c40;  1 drivers, strength-aware
+v00000000039e7450_0 .net "X", 0 0, L_000000000412bf30;  alias, 1 drivers
+v00000000039e6870_0 .net "and0_out", 0 0, L_000000000412cb70;  1 drivers
+v00000000039e5970_0 .net "and1_out", 0 0, L_000000000412c9b0;  1 drivers
+v00000000039e6f50_0 .net "or0_out_X", 0 0, L_000000000412d270;  1 drivers
+S_0000000003a24b80 .scope module, "_0605_" "sky130_fd_sc_hd__inv_2" 3 1034, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e7db0_0 .net "A", 0 0, L_000000000412bf30;  alias, 1 drivers
+L_0000000003fe2650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e9070_0 .net8 "VGND", 0 0, L_0000000003fe2650;  1 drivers, strength-aware
+L_0000000003fe2f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e85d0_0 .net8 "VNB", 0 0, L_0000000003fe2f80;  1 drivers, strength-aware
+L_0000000003fe2c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e87b0_0 .net8 "VPB", 0 0, L_0000000003fe2c00;  1 drivers, strength-aware
+L_0000000003fe3450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7ef0_0 .net8 "VPWR", 0 0, L_0000000003fe3450;  1 drivers, strength-aware
+v00000000039e8b70_0 .net "Y", 0 0, L_000000000412d430;  alias, 1 drivers
+S_0000000003a24700 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a24b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412c710 .functor NOT 1, L_000000000412bf30, C4<0>, C4<0>, C4<0>;
+L_000000000412d430 .functor BUF 1, L_000000000412c710, C4<0>, C4<0>, C4<0>;
+v00000000039e9390_0 .net "A", 0 0, L_000000000412bf30;  alias, 1 drivers
+L_0000000003fe2d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e8df0_0 .net8 "VGND", 0 0, L_0000000003fe2d50;  1 drivers, strength-aware
+L_0000000003fe25e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e9b10_0 .net8 "VNB", 0 0, L_0000000003fe25e0;  1 drivers, strength-aware
+L_0000000003fe20a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e8710_0 .net8 "VPB", 0 0, L_0000000003fe20a0;  1 drivers, strength-aware
+L_0000000003fe2260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e9d90_0 .net8 "VPWR", 0 0, L_0000000003fe2260;  1 drivers, strength-aware
+v00000000039e9bb0_0 .net "Y", 0 0, L_000000000412d430;  alias, 1 drivers
+v00000000039e8670_0 .net "not0_out_Y", 0 0, L_000000000412c710;  1 drivers
+S_0000000003a24580 .scope module, "_0606_" "sky130_fd_sc_hd__o221a_2" 3 1038, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v00000000039e8850_0 .net "A1", 0 0, L_0000000003f90200;  1 drivers
+v00000000039e92f0_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v00000000039e9750_0 .net "B1", 0 0, L_000000000412d120;  alias, 1 drivers
+v00000000039e97f0_0 .net "B2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039e88f0_0 .net "C1", 0 0, L_000000000412d5f0;  alias, 1 drivers
+L_0000000003fe2c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e94d0_0 .net8 "VGND", 0 0, L_0000000003fe2c70;  1 drivers, strength-aware
+L_0000000003fe21f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e8990_0 .net8 "VNB", 0 0, L_0000000003fe21f0;  1 drivers, strength-aware
+L_0000000003fe1f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e9890_0 .net8 "VPB", 0 0, L_0000000003fe1f50;  1 drivers, strength-aware
+L_0000000003fe2ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e80d0_0 .net8 "VPWR", 0 0, L_0000000003fe2ff0;  1 drivers, strength-aware
+v00000000039e9930_0 .net "X", 0 0, L_000000000412c0f0;  alias, 1 drivers
+S_0000000003a24d00 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a24580;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412d190 .functor OR 1, L_0000000004126190, L_000000000412d120, C4<0>, C4<0>;
+L_000000000412c7f0 .functor OR 1, L_0000000004127a80, L_0000000003f90200, C4<0>, C4<0>;
+L_000000000412c240 .functor AND 1, L_000000000412d190, L_000000000412c7f0, L_000000000412d5f0, C4<1>;
+L_000000000412c0f0 .functor BUF 1, L_000000000412c240, C4<0>, C4<0>, C4<0>;
+v00000000039e9110_0 .net "A1", 0 0, L_0000000003f90200;  alias, 1 drivers
+v00000000039e7d10_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v00000000039e82b0_0 .net "B1", 0 0, L_000000000412d120;  alias, 1 drivers
+v00000000039e83f0_0 .net "B2", 0 0, L_0000000004126190;  alias, 1 drivers
+v00000000039e8030_0 .net "C1", 0 0, L_000000000412d5f0;  alias, 1 drivers
+L_0000000003fe2b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e9250_0 .net8 "VGND", 0 0, L_0000000003fe2b20;  1 drivers, strength-aware
+L_0000000003fe2340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e9570_0 .net8 "VNB", 0 0, L_0000000003fe2340;  1 drivers, strength-aware
+L_0000000003fe2f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e9430_0 .net8 "VPB", 0 0, L_0000000003fe2f10;  1 drivers, strength-aware
+L_0000000003fe2500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e99d0_0 .net8 "VPWR", 0 0, L_0000000003fe2500;  1 drivers, strength-aware
+v00000000039e8530_0 .net "X", 0 0, L_000000000412c0f0;  alias, 1 drivers
+v00000000039e9a70_0 .net "and0_out_X", 0 0, L_000000000412c240;  1 drivers
+v00000000039e7950_0 .net "or0_out", 0 0, L_000000000412d190;  1 drivers
+v00000000039e96b0_0 .net "or1_out", 0 0, L_000000000412c7f0;  1 drivers
+S_0000000003a23680 .scope module, "_0607_" "sky130_fd_sc_hd__nor2_2" 3 1046, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v00000000039e8ad0_0 .net "A", 0 0, L_000000000412d430;  alias, 1 drivers
+v00000000039e8170_0 .net "B", 0 0, L_000000000412c0f0;  alias, 1 drivers
+L_0000000003fe2030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e8c10_0 .net8 "VGND", 0 0, L_0000000003fe2030;  1 drivers, strength-aware
+L_0000000003fe2110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e8210_0 .net8 "VNB", 0 0, L_0000000003fe2110;  1 drivers, strength-aware
+L_0000000003fe1e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e9ed0_0 .net8 "VPB", 0 0, L_0000000003fe1e00;  1 drivers, strength-aware
+L_0000000003fe1a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e8f30_0 .net8 "VPWR", 0 0, L_0000000003fe1a10;  1 drivers, strength-aware
+v00000000039e7a90_0 .net "Y", 0 0, L_000000000412c940;  alias, 1 drivers
+S_0000000003a24100 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a23680;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412d200 .functor NOR 1, L_000000000412d430, L_000000000412c0f0, C4<0>, C4<0>;
+L_000000000412c940 .functor BUF 1, L_000000000412d200, C4<0>, C4<0>, C4<0>;
+v00000000039e7e50_0 .net "A", 0 0, L_000000000412d430;  alias, 1 drivers
+v00000000039e9610_0 .net "B", 0 0, L_000000000412c0f0;  alias, 1 drivers
+L_0000000003fe26c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e9c50_0 .net8 "VGND", 0 0, L_0000000003fe26c0;  1 drivers, strength-aware
+L_0000000003fe22d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e7f90_0 .net8 "VNB", 0 0, L_0000000003fe22d0;  1 drivers, strength-aware
+L_0000000003fe2ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e8a30_0 .net8 "VPB", 0 0, L_0000000003fe2ab0;  1 drivers, strength-aware
+L_0000000003fe18c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e79f0_0 .net8 "VPWR", 0 0, L_0000000003fe18c0;  1 drivers, strength-aware
+v00000000039e9cf0_0 .net "Y", 0 0, L_000000000412c940;  alias, 1 drivers
+v00000000039e9e30_0 .net "nor0_out_Y", 0 0, L_000000000412d200;  1 drivers
+S_0000000003a23980 .scope module, "_0608_" "sky130_fd_sc_hd__inv_2" 3 1051, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v00000000039e7c70_0 .net "A", 0 0, L_0000000003f907a0;  1 drivers
+L_0000000003fe30d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c00720_0 .net8 "VGND", 0 0, L_0000000003fe30d0;  1 drivers, strength-aware
+L_0000000003fe1930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c01800_0 .net8 "VNB", 0 0, L_0000000003fe1930;  1 drivers, strength-aware
+L_0000000003fe2dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bffb40_0 .net8 "VPB", 0 0, L_0000000003fe2dc0;  1 drivers, strength-aware
+L_0000000003fe2730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c00ae0_0 .net8 "VPWR", 0 0, L_0000000003fe2730;  1 drivers, strength-aware
+v0000000002c002c0_0 .net "Y", 0 0, L_000000000412ca90;  alias, 1 drivers
+S_0000000003a24e80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a23980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412ca20 .functor NOT 1, L_0000000003f907a0, C4<0>, C4<0>, C4<0>;
+L_000000000412ca90 .functor BUF 1, L_000000000412ca20, C4<0>, C4<0>, C4<0>;
+v00000000039e8350_0 .net "A", 0 0, L_0000000003f907a0;  alias, 1 drivers
+L_0000000003fe3060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e8cb0_0 .net8 "VGND", 0 0, L_0000000003fe3060;  1 drivers, strength-aware
+L_0000000003fe2570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000039e7b30_0 .net8 "VNB", 0 0, L_0000000003fe2570;  1 drivers, strength-aware
+L_0000000003fe1cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e8e90_0 .net8 "VPB", 0 0, L_0000000003fe1cb0;  1 drivers, strength-aware
+L_0000000003fe1d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000039e7bd0_0 .net8 "VPWR", 0 0, L_0000000003fe1d20;  1 drivers, strength-aware
+v00000000039e8fd0_0 .net "Y", 0 0, L_000000000412ca90;  alias, 1 drivers
+v00000000039e91b0_0 .net "not0_out_Y", 0 0, L_000000000412ca20;  1 drivers
+S_0000000003a23500 .scope module, "_0609_" "sky130_fd_sc_hd__a2bb2o_2" 3 1055, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000002bffe60_0 .net "A1_N", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000002c007c0_0 .net "A2_N", 0 0, L_0000000003f8f940;  1 drivers
+v0000000002c02020_0 .net "B1", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000002c01d00_0 .net "B2", 0 0, L_0000000003f8f9e0;  1 drivers
+L_0000000003fe1d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c01260_0 .net8 "VGND", 0 0, L_0000000003fe1d90;  1 drivers, strength-aware
+L_0000000003fe1e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bff8c0_0 .net8 "VNB", 0 0, L_0000000003fe1e70;  1 drivers, strength-aware
+L_0000000003fe23b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c01940_0 .net8 "VPB", 0 0, L_0000000003fe23b0;  1 drivers, strength-aware
+L_0000000003fe3290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c013a0_0 .net8 "VPWR", 0 0, L_0000000003fe3290;  1 drivers, strength-aware
+v0000000002c004a0_0 .net "X", 0 0, L_000000000412d660;  alias, 1 drivers
+S_0000000003a23c80 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a23500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412d2e0 .functor AND 1, L_0000000004128030, L_0000000003f8f9e0, C4<1>, C4<1>;
+L_000000000412ce80 .functor NOR 1, L_0000000004128030, L_0000000003f8f940, C4<0>, C4<0>;
+L_000000000412d4a0 .functor OR 1, L_000000000412ce80, L_000000000412d2e0, C4<0>, C4<0>;
+L_000000000412d660 .functor BUF 1, L_000000000412d4a0, C4<0>, C4<0>, C4<0>;
+v0000000002bffbe0_0 .net "A1_N", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000002bffc80_0 .net "A2_N", 0 0, L_0000000003f8f940;  alias, 1 drivers
+v0000000002bffd20_0 .net "B1", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000002c01c60_0 .net "B2", 0 0, L_0000000003f8f9e0;  alias, 1 drivers
+L_0000000003fe3220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c018a0_0 .net8 "VGND", 0 0, L_0000000003fe3220;  1 drivers, strength-aware
+L_0000000003fe3300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bffdc0_0 .net8 "VNB", 0 0, L_0000000003fe3300;  1 drivers, strength-aware
+L_0000000003fe19a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfff00_0 .net8 "VPB", 0 0, L_0000000003fe19a0;  1 drivers, strength-aware
+L_0000000003fe2180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfffa0_0 .net8 "VPWR", 0 0, L_0000000003fe2180;  1 drivers, strength-aware
+v0000000002c01580_0 .net "X", 0 0, L_000000000412d660;  alias, 1 drivers
+v0000000002c00a40_0 .net "and0_out", 0 0, L_000000000412d2e0;  1 drivers
+v0000000002c01f80_0 .net "nor0_out", 0 0, L_000000000412ce80;  1 drivers
+v0000000002c01120_0 .net "or0_out_X", 0 0, L_000000000412d4a0;  1 drivers
+S_0000000003a23080 .scope module, "_0610_" "sky130_fd_sc_hd__o221a_2" 3 1062, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002bff960_0 .net "A1", 0 0, L_0000000003f8fbc0;  1 drivers
+v0000000002c00540_0 .net "A2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000002c005e0_0 .net "B1", 0 0, L_000000000412ca90;  alias, 1 drivers
+v0000000002c00220_0 .net "B2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000002c01620_0 .net "C1", 0 0, L_000000000412d660;  alias, 1 drivers
+L_0000000003fe2b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c016c0_0 .net8 "VGND", 0 0, L_0000000003fe2b90;  1 drivers, strength-aware
+L_0000000003fe3140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c019e0_0 .net8 "VNB", 0 0, L_0000000003fe3140;  1 drivers, strength-aware
+L_0000000003fe2420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c01da0_0 .net8 "VPB", 0 0, L_0000000003fe2420;  1 drivers, strength-aware
+L_0000000003fe1a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bffa00_0 .net8 "VPWR", 0 0, L_0000000003fe1a80;  1 drivers, strength-aware
+v0000000002c01a80_0 .net "X", 0 0, L_000000000412cbe0;  alias, 1 drivers
+S_0000000003a23380 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a23080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412d510 .functor OR 1, L_000000000412d0b0, L_000000000412ca90, C4<0>, C4<0>;
+L_000000000412c5c0 .functor OR 1, L_000000000412c1d0, L_0000000003f8fbc0, C4<0>, C4<0>;
+L_000000000412c080 .functor AND 1, L_000000000412d510, L_000000000412c5c0, L_000000000412d660, C4<1>;
+L_000000000412cbe0 .functor BUF 1, L_000000000412c080, C4<0>, C4<0>, C4<0>;
+v0000000002c011c0_0 .net "A1", 0 0, L_0000000003f8fbc0;  alias, 1 drivers
+v0000000002c00c20_0 .net "A2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000002c01300_0 .net "B1", 0 0, L_000000000412ca90;  alias, 1 drivers
+v0000000002c00040_0 .net "B2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000002c00360_0 .net "C1", 0 0, L_000000000412d660;  alias, 1 drivers
+L_0000000003fe31b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c00400_0 .net8 "VGND", 0 0, L_0000000003fe31b0;  1 drivers, strength-aware
+L_0000000003fe1af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c000e0_0 .net8 "VNB", 0 0, L_0000000003fe1af0;  1 drivers, strength-aware
+L_0000000003fe27a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c01b20_0 .net8 "VPB", 0 0, L_0000000003fe27a0;  1 drivers, strength-aware
+L_0000000003fe2880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c00180_0 .net8 "VPWR", 0 0, L_0000000003fe2880;  1 drivers, strength-aware
+v0000000002c014e0_0 .net "X", 0 0, L_000000000412cbe0;  alias, 1 drivers
+v0000000002c01bc0_0 .net "and0_out_X", 0 0, L_000000000412c080;  1 drivers
+v0000000002c00860_0 .net "or0_out", 0 0, L_000000000412d510;  1 drivers
+v0000000002c01440_0 .net "or1_out", 0 0, L_000000000412c5c0;  1 drivers
+S_0000000003a23800 .scope module, "_0611_" "sky130_fd_sc_hd__and2_2" 3 1070, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c009a0_0 .net "A", 0 0, L_000000000412c940;  alias, 1 drivers
+v0000000002c00d60_0 .net "B", 0 0, L_000000000412cbe0;  alias, 1 drivers
+L_0000000003fe1b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c00e00_0 .net8 "VGND", 0 0, L_0000000003fe1b60;  1 drivers, strength-aware
+L_0000000003fe2490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c00ea0_0 .net8 "VNB", 0 0, L_0000000003fe2490;  1 drivers, strength-aware
+L_0000000003fe28f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c00f40_0 .net8 "VPB", 0 0, L_0000000003fe28f0;  1 drivers, strength-aware
+L_0000000003fe2960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c00fe0_0 .net8 "VPWR", 0 0, L_0000000003fe2960;  1 drivers, strength-aware
+v0000000002c01080_0 .net "X", 0 0, L_000000000412c2b0;  alias, 1 drivers
+S_0000000003a23e00 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a23800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412c160 .functor AND 1, L_000000000412c940, L_000000000412cbe0, C4<1>, C4<1>;
+L_000000000412c2b0 .functor BUF 1, L_000000000412c160, C4<0>, C4<0>, C4<0>;
+v0000000002c01760_0 .net "A", 0 0, L_000000000412c940;  alias, 1 drivers
+v0000000002c00b80_0 .net "B", 0 0, L_000000000412cbe0;  alias, 1 drivers
+L_0000000003fe29d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c01e40_0 .net8 "VGND", 0 0, L_0000000003fe29d0;  1 drivers, strength-aware
+L_0000000003fe2a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c00680_0 .net8 "VNB", 0 0, L_0000000003fe2a40;  1 drivers, strength-aware
+L_0000000003fe4950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c01ee0_0 .net8 "VPB", 0 0, L_0000000003fe4950;  1 drivers, strength-aware
+L_0000000003fe44f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c00cc0_0 .net8 "VPWR", 0 0, L_0000000003fe44f0;  1 drivers, strength-aware
+v0000000002c00900_0 .net "X", 0 0, L_000000000412c2b0;  alias, 1 drivers
+v0000000002bffaa0_0 .net "and0_out_X", 0 0, L_000000000412c160;  1 drivers
+S_0000000003a23f80 .scope module, "_0612_" "sky130_fd_sc_hd__buf_1" 3 1075, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c02200_0 .net "A", 0 0, L_0000000004127e00;  alias, 1 drivers
+L_0000000003fe4a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03880_0 .net8 "VGND", 0 0, L_0000000003fe4a30;  1 drivers, strength-aware
+L_0000000003fe4f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03c40_0 .net8 "VNB", 0 0, L_0000000003fe4f70;  1 drivers, strength-aware
+L_0000000003fe5050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c02980_0 .net8 "VPB", 0 0, L_0000000003fe5050;  1 drivers, strength-aware
+L_0000000003fe4100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c02c00_0 .net8 "VPWR", 0 0, L_0000000003fe4100;  1 drivers, strength-aware
+v0000000002c04140_0 .net "X", 0 0, L_000000000412cc50;  alias, 1 drivers
+S_0000000003a24400 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a23f80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412c320 .functor BUF 1, L_0000000004127e00, C4<0>, C4<0>, C4<0>;
+L_000000000412cc50 .functor BUF 1, L_000000000412c320, C4<0>, C4<0>, C4<0>;
+v0000000002c04780_0 .net "A", 0 0, L_0000000004127e00;  alias, 1 drivers
+L_0000000003fe45d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c023e0_0 .net8 "VGND", 0 0, L_0000000003fe45d0;  1 drivers, strength-aware
+L_0000000003fe3ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03ec0_0 .net8 "VNB", 0 0, L_0000000003fe3ca0;  1 drivers, strength-aware
+L_0000000003fe34c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c02de0_0 .net8 "VPB", 0 0, L_0000000003fe34c0;  1 drivers, strength-aware
+L_0000000003fe49c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c03ce0_0 .net8 "VPWR", 0 0, L_0000000003fe49c0;  1 drivers, strength-aware
+v0000000002c02ca0_0 .net "X", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000002c02d40_0 .net "buf0_out_X", 0 0, L_000000000412c320;  1 drivers
+S_0000000003a29b90 .scope module, "_0613_" "sky130_fd_sc_hd__a221oi_2" 3 1079, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c03560_0 .net "A1", 0 0, L_000000000412b600;  alias, 1 drivers
+v0000000002c02f20_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000002c03f60_0 .net "B1", 0 0, L_0000000003f91d80;  1 drivers
+v0000000002c040a0_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000002c03d80_0 .net "C1", 0 0, L_000000000412d6d0;  alias, 1 drivers
+L_0000000003fe48e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03e20_0 .net8 "VGND", 0 0, L_0000000003fe48e0;  1 drivers, strength-aware
+L_0000000003fe3e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c020c0_0 .net8 "VNB", 0 0, L_0000000003fe3e60;  1 drivers, strength-aware
+L_0000000003fe4b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c02fc0_0 .net8 "VPB", 0 0, L_0000000003fe4b10;  1 drivers, strength-aware
+L_0000000003fe3d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c03920_0 .net8 "VPWR", 0 0, L_0000000003fe3d10;  1 drivers, strength-aware
+v0000000002c025c0_0 .net "Y", 0 0, L_000000000412ccc0;  alias, 1 drivers
+S_0000000003a27a90 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a29b90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412c390 .functor AND 1, L_0000000003f91d80, L_0000000004127930, C4<1>, C4<1>;
+L_000000000412c400 .functor AND 1, L_000000000412b600, L_000000000412cc50, C4<1>, C4<1>;
+L_000000000412c470 .functor NOR 1, L_000000000412c390, L_000000000412d6d0, L_000000000412c400, C4<0>;
+L_000000000412ccc0 .functor BUF 1, L_000000000412c470, C4<0>, C4<0>, C4<0>;
+v0000000002c02520_0 .net "A1", 0 0, L_000000000412b600;  alias, 1 drivers
+v0000000002c04280_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000002c03600_0 .net "B1", 0 0, L_0000000003f91d80;  alias, 1 drivers
+v0000000002c04000_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000002c02a20_0 .net "C1", 0 0, L_000000000412d6d0;  alias, 1 drivers
+L_0000000003fe4720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03ba0_0 .net8 "VGND", 0 0, L_0000000003fe4720;  1 drivers, strength-aware
+L_0000000003fe43a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c02160_0 .net8 "VNB", 0 0, L_0000000003fe43a0;  1 drivers, strength-aware
+L_0000000003fe3530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c03a60_0 .net8 "VPB", 0 0, L_0000000003fe3530;  1 drivers, strength-aware
+L_0000000003fe3d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c041e0_0 .net8 "VPWR", 0 0, L_0000000003fe3d80;  1 drivers, strength-aware
+v0000000002c02ac0_0 .net "Y", 0 0, L_000000000412ccc0;  alias, 1 drivers
+v0000000002c02e80_0 .net "and0_out", 0 0, L_000000000412c390;  1 drivers
+v0000000002c036a0_0 .net "and1_out", 0 0, L_000000000412c400;  1 drivers
+v0000000002c03b00_0 .net "nor0_out_Y", 0 0, L_000000000412c470;  1 drivers
+S_0000000003a26d10 .scope module, "_0614_" "sky130_fd_sc_hd__or2_2" 3 1087, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c02480_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000002c04460_0 .net "B", 0 0, L_000000000412ccc0;  alias, 1 drivers
+L_0000000003fe4aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c043c0_0 .net8 "VGND", 0 0, L_0000000003fe4aa0;  1 drivers, strength-aware
+L_0000000003fe3c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c02660_0 .net8 "VNB", 0 0, L_0000000003fe3c30;  1 drivers, strength-aware
+L_0000000003fe4db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c02700_0 .net8 "VPB", 0 0, L_0000000003fe4db0;  1 drivers, strength-aware
+L_0000000003fe4640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c027a0_0 .net8 "VPWR", 0 0, L_0000000003fe4640;  1 drivers, strength-aware
+v0000000002c045a0_0 .net "X", 0 0, L_000000000412ce10;  alias, 1 drivers
+S_0000000003a26110 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a26d10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412cd30 .functor OR 1, L_000000000412ccc0, L_000000000412bec0, C4<0>, C4<0>;
+L_000000000412ce10 .functor BUF 1, L_000000000412cd30, C4<0>, C4<0>, C4<0>;
+v0000000002c02340_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000002c04320_0 .net "B", 0 0, L_000000000412ccc0;  alias, 1 drivers
+L_0000000003fe4b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c028e0_0 .net8 "VGND", 0 0, L_0000000003fe4b80;  1 drivers, strength-aware
+L_0000000003fe3df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c02b60_0 .net8 "VNB", 0 0, L_0000000003fe3df0;  1 drivers, strength-aware
+L_0000000003fe3bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c03420_0 .net8 "VPB", 0 0, L_0000000003fe3bc0;  1 drivers, strength-aware
+L_0000000003fe4bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c031a0_0 .net8 "VPWR", 0 0, L_0000000003fe4bf0;  1 drivers, strength-aware
+v0000000002c03060_0 .net "X", 0 0, L_000000000412ce10;  alias, 1 drivers
+v0000000002c03740_0 .net "or0_out_X", 0 0, L_000000000412cd30;  1 drivers
+S_0000000003a28b10 .scope module, "_0615_" "sky130_fd_sc_hd__inv_2" 3 1092, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c032e0_0 .net "A", 0 0, L_000000000412ce10;  alias, 1 drivers
+L_0000000003fe36f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c046e0_0 .net8 "VGND", 0 0, L_0000000003fe36f0;  1 drivers, strength-aware
+L_0000000003fe4020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03380_0 .net8 "VNB", 0 0, L_0000000003fe4020;  1 drivers, strength-aware
+L_0000000003fe4c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c034c0_0 .net8 "VPB", 0 0, L_0000000003fe4c60;  1 drivers, strength-aware
+L_0000000003fe3ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c037e0_0 .net8 "VPWR", 0 0, L_0000000003fe3ed0;  1 drivers, strength-aware
+v0000000002c039c0_0 .net "Y", 0 0, L_000000000412dc10;  alias, 1 drivers
+S_0000000003a29290 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a28b10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412e1c0 .functor NOT 1, L_000000000412ce10, C4<0>, C4<0>, C4<0>;
+L_000000000412dc10 .functor BUF 1, L_000000000412e1c0, C4<0>, C4<0>, C4<0>;
+v0000000002c04820_0 .net "A", 0 0, L_000000000412ce10;  alias, 1 drivers
+L_0000000003fe3f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c03100_0 .net8 "VGND", 0 0, L_0000000003fe3f40;  1 drivers, strength-aware
+L_0000000003fe46b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c022a0_0 .net8 "VNB", 0 0, L_0000000003fe46b0;  1 drivers, strength-aware
+L_0000000003fe3990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c04500_0 .net8 "VPB", 0 0, L_0000000003fe3990;  1 drivers, strength-aware
+L_0000000003fe4fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c03240_0 .net8 "VPWR", 0 0, L_0000000003fe4fe0;  1 drivers, strength-aware
+v0000000002c04640_0 .net "Y", 0 0, L_000000000412dc10;  alias, 1 drivers
+v0000000002c02840_0 .net "not0_out_Y", 0 0, L_000000000412e1c0;  1 drivers
+S_0000000003a25690 .scope module, "_0616_" "sky130_fd_sc_hd__o21ai_2" 3 1096, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002c06080_0 .net "A1", 0 0, L_000000000412d430;  alias, 1 drivers
+v0000000002c05720_0 .net "A2", 0 0, L_000000000412c2b0;  alias, 1 drivers
+v0000000002c061c0_0 .net "B1", 0 0, L_000000000412dc10;  alias, 1 drivers
+L_0000000003fe3760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c05cc0_0 .net8 "VGND", 0 0, L_0000000003fe3760;  1 drivers, strength-aware
+L_0000000003fe37d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c04b40_0 .net8 "VNB", 0 0, L_0000000003fe37d0;  1 drivers, strength-aware
+L_0000000003fe4e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c06620_0 .net8 "VPB", 0 0, L_0000000003fe4e20;  1 drivers, strength-aware
+L_0000000003fe35a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c052c0_0 .net8 "VPWR", 0 0, L_0000000003fe35a0;  1 drivers, strength-aware
+v0000000002c055e0_0 .net "Y", 0 0, L_000000000412e460;  alias, 1 drivers
+S_0000000003a27f10 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a25690;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412e2a0 .functor OR 1, L_000000000412c2b0, L_000000000412d430, C4<0>, C4<0>;
+L_000000000412e7e0 .functor NAND 1, L_000000000412dc10, L_000000000412e2a0, C4<1>, C4<1>;
+L_000000000412e460 .functor BUF 1, L_000000000412e7e0, C4<0>, C4<0>, C4<0>;
+v0000000002c06440_0 .net "A1", 0 0, L_000000000412d430;  alias, 1 drivers
+v0000000002c054a0_0 .net "A2", 0 0, L_000000000412c2b0;  alias, 1 drivers
+v0000000002c06120_0 .net "B1", 0 0, L_000000000412dc10;  alias, 1 drivers
+L_0000000003fe4170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c063a0_0 .net8 "VGND", 0 0, L_0000000003fe4170;  1 drivers, strength-aware
+L_0000000003fe4cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c06300_0 .net8 "VNB", 0 0, L_0000000003fe4cd0;  1 drivers, strength-aware
+L_0000000003fe3680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05c20_0 .net8 "VPB", 0 0, L_0000000003fe3680;  1 drivers, strength-aware
+L_0000000003fe4250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c04aa0_0 .net8 "VPWR", 0 0, L_0000000003fe4250;  1 drivers, strength-aware
+v0000000002c06bc0_0 .net "Y", 0 0, L_000000000412e460;  alias, 1 drivers
+v0000000002c04dc0_0 .net "nand0_out_Y", 0 0, L_000000000412e7e0;  1 drivers
+v0000000002c057c0_0 .net "or0_out", 0 0, L_000000000412e2a0;  1 drivers
+S_0000000003a27910 .scope module, "_0617_" "sky130_fd_sc_hd__and2_2" 3 1102, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c064e0_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000002c06580_0 .net "B", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000003fe41e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c06c60_0 .net8 "VGND", 0 0, L_0000000003fe41e0;  1 drivers, strength-aware
+L_0000000003fe3fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c06f80_0 .net8 "VNB", 0 0, L_0000000003fe3fb0;  1 drivers, strength-aware
+L_0000000003fe3840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05040_0 .net8 "VPB", 0 0, L_0000000003fe3840;  1 drivers, strength-aware
+L_0000000003fe4790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07020_0 .net8 "VPWR", 0 0, L_0000000003fe4790;  1 drivers, strength-aware
+v0000000002c06e40_0 .net "X", 0 0, L_000000000412e150;  alias, 1 drivers
+S_0000000003a28690 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a27910;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412f0a0 .functor AND 1, L_000000000412bec0, L_000000000412c010, C4<1>, C4<1>;
+L_000000000412e150 .functor BUF 1, L_000000000412f0a0, C4<0>, C4<0>, C4<0>;
+v0000000002c05860_0 .net "A", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000002c069e0_0 .net "B", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000003fe4090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c06800_0 .net8 "VGND", 0 0, L_0000000003fe4090;  1 drivers, strength-aware
+L_0000000003fe38b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c04e60_0 .net8 "VNB", 0 0, L_0000000003fe38b0;  1 drivers, strength-aware
+L_0000000003fe4800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c04f00_0 .net8 "VPB", 0 0, L_0000000003fe4800;  1 drivers, strength-aware
+L_0000000003fe3a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c04fa0_0 .net8 "VPWR", 0 0, L_0000000003fe3a70;  1 drivers, strength-aware
+v0000000002c06da0_0 .net "X", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000002c05a40_0 .net "and0_out_X", 0 0, L_000000000412f0a0;  1 drivers
+S_0000000003a25090 .scope module, "_0618_" "sky130_fd_sc_hd__o21ai_2" 3 1107, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002c05400_0 .net "A1", 0 0, L_000000000412c780;  alias, 1 drivers
+v0000000002c050e0_0 .net "A2", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000002c06b20_0 .net "B1", 0 0, L_000000000412d820;  alias, 1 drivers
+L_0000000003fe42c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c04c80_0 .net8 "VGND", 0 0, L_0000000003fe42c0;  1 drivers, strength-aware
+L_0000000003fe3610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c05b80_0 .net8 "VNB", 0 0, L_0000000003fe3610;  1 drivers, strength-aware
+L_0000000003fe3920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c06d00_0 .net8 "VPB", 0 0, L_0000000003fe3920;  1 drivers, strength-aware
+L_0000000003fe4330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05d60_0 .net8 "VPWR", 0 0, L_0000000003fe4330;  1 drivers, strength-aware
+v0000000002c06940_0 .net "Y", 0 0, L_000000000412e000;  alias, 1 drivers
+S_0000000003a29110 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a25090;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412e310 .functor OR 1, L_000000000412e150, L_000000000412c780, C4<0>, C4<0>;
+L_000000000412ea10 .functor NAND 1, L_000000000412d820, L_000000000412e310, C4<1>, C4<1>;
+L_000000000412e000 .functor BUF 1, L_000000000412ea10, C4<0>, C4<0>, C4<0>;
+v0000000002c05900_0 .net "A1", 0 0, L_000000000412c780;  alias, 1 drivers
+v0000000002c059a0_0 .net "A2", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000002c05ae0_0 .net "B1", 0 0, L_000000000412d820;  alias, 1 drivers
+L_0000000003fe4410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c05540_0 .net8 "VGND", 0 0, L_0000000003fe4410;  1 drivers, strength-aware
+L_0000000003fe4870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c066c0_0 .net8 "VNB", 0 0, L_0000000003fe4870;  1 drivers, strength-aware
+L_0000000003fe4480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05680_0 .net8 "VPB", 0 0, L_0000000003fe4480;  1 drivers, strength-aware
+L_0000000003fe4560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c06260_0 .net8 "VPWR", 0 0, L_0000000003fe4560;  1 drivers, strength-aware
+v0000000002c06760_0 .net "Y", 0 0, L_000000000412e000;  alias, 1 drivers
+v0000000002c068a0_0 .net "nand0_out_Y", 0 0, L_000000000412ea10;  1 drivers
+v0000000002c04be0_0 .net "or0_out", 0 0, L_000000000412e310;  1 drivers
+S_0000000003a2af10 .scope module, "_0619_" "sky130_fd_sc_hd__o21a_2" 3 1113, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002c04960_0 .net "A1", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000002c05f40_0 .net "A2", 0 0, L_000000000412e460;  alias, 1 drivers
+v0000000002c05fe0_0 .net "B1", 0 0, L_000000000412e000;  alias, 1 drivers
+L_0000000003fe4d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c084c0_0 .net8 "VGND", 0 0, L_0000000003fe4d40;  1 drivers, strength-aware
+L_0000000003fe4e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c096e0_0 .net8 "VNB", 0 0, L_0000000003fe4e90;  1 drivers, strength-aware
+L_0000000003fe3a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c08240_0 .net8 "VPB", 0 0, L_0000000003fe3a00;  1 drivers, strength-aware
+L_0000000003fe3ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c09460_0 .net8 "VPWR", 0 0, L_0000000003fe3ae0;  1 drivers, strength-aware
+v0000000002c07660_0 .net "X", 0 0, L_000000000412d9e0;  alias, 1 drivers
+S_0000000003a29890 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a2af10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412f3b0 .functor OR 1, L_000000000412e460, L_000000000412bd00, C4<0>, C4<0>;
+L_000000000412eee0 .functor AND 1, L_000000000412f3b0, L_000000000412e000, C4<1>, C4<1>;
+L_000000000412d9e0 .functor BUF 1, L_000000000412eee0, C4<0>, C4<0>, C4<0>;
+v0000000002c04d20_0 .net "A1", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000002c06a80_0 .net "A2", 0 0, L_000000000412e460;  alias, 1 drivers
+v0000000002c05e00_0 .net "B1", 0 0, L_000000000412e000;  alias, 1 drivers
+L_0000000003fe4f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c04a00_0 .net8 "VGND", 0 0, L_0000000003fe4f00;  1 drivers, strength-aware
+L_0000000003fe3b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c05ea0_0 .net8 "VNB", 0 0, L_0000000003fe3b50;  1 drivers, strength-aware
+L_0000000003fe57c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05180_0 .net8 "VPB", 0 0, L_0000000003fe57c0;  1 drivers, strength-aware
+L_0000000003fe6b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c05220_0 .net8 "VPWR", 0 0, L_0000000003fe6b70;  1 drivers, strength-aware
+v0000000002c05360_0 .net "X", 0 0, L_000000000412d9e0;  alias, 1 drivers
+v0000000002c06ee0_0 .net "and0_out_X", 0 0, L_000000000412eee0;  1 drivers
+v0000000002c048c0_0 .net "or0_out", 0 0, L_000000000412f3b0;  1 drivers
+S_0000000003a28390 .scope module, "_0620_" "sky130_fd_sc_hd__nor2_2" 3 1119, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c07200_0 .net "A", 0 0, L_000000000412ad40;  alias, 1 drivers
+v0000000002c07ca0_0 .net "B", 0 0, L_0000000004129140;  alias, 1 drivers
+L_0000000003fe66a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c07d40_0 .net8 "VGND", 0 0, L_0000000003fe66a0;  1 drivers, strength-aware
+L_0000000003fe56e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c07a20_0 .net8 "VNB", 0 0, L_0000000003fe56e0;  1 drivers, strength-aware
+L_0000000003fe6630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c072a0_0 .net8 "VPB", 0 0, L_0000000003fe6630;  1 drivers, strength-aware
+L_0000000003fe6010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c09640_0 .net8 "VPWR", 0 0, L_0000000003fe6010;  1 drivers, strength-aware
+v0000000002c08c40_0 .net "Y", 0 0, L_000000000412ea80;  alias, 1 drivers
+S_0000000003a28810 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a28390;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412ec40 .functor NOR 1, L_000000000412ad40, L_0000000004129140, C4<0>, C4<0>;
+L_000000000412ea80 .functor BUF 1, L_000000000412ec40, C4<0>, C4<0>, C4<0>;
+v0000000002c07f20_0 .net "A", 0 0, L_000000000412ad40;  alias, 1 drivers
+v0000000002c08ec0_0 .net "B", 0 0, L_0000000004129140;  alias, 1 drivers
+L_0000000003fe6be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c09820_0 .net8 "VGND", 0 0, L_0000000003fe6be0;  1 drivers, strength-aware
+L_0000000003fe64e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c08d80_0 .net8 "VNB", 0 0, L_0000000003fe64e0;  1 drivers, strength-aware
+L_0000000003fe53d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07b60_0 .net8 "VPB", 0 0, L_0000000003fe53d0;  1 drivers, strength-aware
+L_0000000003fe5440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07ac0_0 .net8 "VPWR", 0 0, L_0000000003fe5440;  1 drivers, strength-aware
+v0000000002c08b00_0 .net "Y", 0 0, L_000000000412ea80;  alias, 1 drivers
+v0000000002c08f60_0 .net "nor0_out_Y", 0 0, L_000000000412ec40;  1 drivers
+S_0000000003a29410 .scope module, "_0621_" "sky130_fd_sc_hd__nor2_2" 3 1124, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c07160_0 .net "A", 0 0, L_000000000412a720;  alias, 1 drivers
+v0000000002c08a60_0 .net "B", 0 0, L_000000000412ab10;  alias, 1 drivers
+L_0000000003fe5e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c091e0_0 .net8 "VGND", 0 0, L_0000000003fe5e50;  1 drivers, strength-aware
+L_0000000003fe6780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c07980_0 .net8 "VNB", 0 0, L_0000000003fe6780;  1 drivers, strength-aware
+L_0000000003fe6400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07de0_0 .net8 "VPB", 0 0, L_0000000003fe6400;  1 drivers, strength-aware
+L_0000000003fe6c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07340_0 .net8 "VPWR", 0 0, L_0000000003fe6c50;  1 drivers, strength-aware
+v0000000002c08380_0 .net "Y", 0 0, L_000000000412e770;  alias, 1 drivers
+S_0000000003a28090 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a29410;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412da50 .functor NOR 1, L_000000000412a720, L_000000000412ab10, C4<0>, C4<0>;
+L_000000000412e770 .functor BUF 1, L_000000000412da50, C4<0>, C4<0>, C4<0>;
+v0000000002c09780_0 .net "A", 0 0, L_000000000412a720;  alias, 1 drivers
+v0000000002c082e0_0 .net "B", 0 0, L_000000000412ab10;  alias, 1 drivers
+L_0000000003fe6550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c09500_0 .net8 "VGND", 0 0, L_0000000003fe6550;  1 drivers, strength-aware
+L_0000000003fe5de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c070c0_0 .net8 "VNB", 0 0, L_0000000003fe5de0;  1 drivers, strength-aware
+L_0000000003fe58a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c09280_0 .net8 "VPB", 0 0, L_0000000003fe58a0;  1 drivers, strength-aware
+L_0000000003fe5a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c08600_0 .net8 "VPWR", 0 0, L_0000000003fe5a60;  1 drivers, strength-aware
+v0000000002c07c00_0 .net "Y", 0 0, L_000000000412e770;  alias, 1 drivers
+v0000000002c087e0_0 .net "nor0_out_Y", 0 0, L_000000000412da50;  1 drivers
+S_0000000003a25e10 .scope module, "_0622_" "sky130_fd_sc_hd__or2_2" 3 1129, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c07fc0_0 .net "A", 0 0, L_000000000412bb40;  alias, 1 drivers
+v0000000002c08920_0 .net "B", 0 0, L_0000000004128c70;  alias, 1 drivers
+L_0000000003fe6470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c086a0_0 .net8 "VGND", 0 0, L_0000000003fe6470;  1 drivers, strength-aware
+L_0000000003fe59f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c08740_0 .net8 "VNB", 0 0, L_0000000003fe59f0;  1 drivers, strength-aware
+L_0000000003fe5750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c08e20_0 .net8 "VPB", 0 0, L_0000000003fe5750;  1 drivers, strength-aware
+L_0000000003fe67f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c078e0_0 .net8 "VPWR", 0 0, L_0000000003fe67f0;  1 drivers, strength-aware
+v0000000002c07520_0 .net "X", 0 0, L_000000000412ee00;  alias, 1 drivers
+S_0000000003a26e90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a25e10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412eaf0 .functor OR 1, L_0000000004128c70, L_000000000412bb40, C4<0>, C4<0>;
+L_000000000412ee00 .functor BUF 1, L_000000000412eaf0, C4<0>, C4<0>, C4<0>;
+v0000000002c09000_0 .net "A", 0 0, L_000000000412bb40;  alias, 1 drivers
+v0000000002c08ba0_0 .net "B", 0 0, L_0000000004128c70;  alias, 1 drivers
+L_0000000003fe6320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c08420_0 .net8 "VGND", 0 0, L_0000000003fe6320;  1 drivers, strength-aware
+L_0000000003fe5b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c08880_0 .net8 "VNB", 0 0, L_0000000003fe5b40;  1 drivers, strength-aware
+L_0000000003fe6710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c07480_0 .net8 "VPB", 0 0, L_0000000003fe6710;  1 drivers, strength-aware
+L_0000000003fe5d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c073e0_0 .net8 "VPWR", 0 0, L_0000000003fe5d00;  1 drivers, strength-aware
+v0000000002c08060_0 .net "X", 0 0, L_000000000412ee00;  alias, 1 drivers
+v0000000002c08560_0 .net "or0_out_X", 0 0, L_000000000412eaf0;  1 drivers
+S_0000000003a27c10 .scope module, "_0623_" "sky130_fd_sc_hd__o21a_2" 3 1134, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002c077a0_0 .net "A1", 0 0, L_000000000412ea80;  alias, 1 drivers
+v0000000002c07840_0 .net "A2", 0 0, L_000000000412e770;  alias, 1 drivers
+v0000000002c081a0_0 .net "B1", 0 0, L_000000000412ee00;  alias, 1 drivers
+L_0000000003fe5830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c07e80_0 .net8 "VGND", 0 0, L_0000000003fe5830;  1 drivers, strength-aware
+L_0000000003fe5910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0bd00_0 .net8 "VNB", 0 0, L_0000000003fe5910;  1 drivers, strength-aware
+L_0000000003fe5600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a680_0 .net8 "VPB", 0 0, L_0000000003fe5600;  1 drivers, strength-aware
+L_0000000003fe5210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c098c0_0 .net8 "VPWR", 0 0, L_0000000003fe5210;  1 drivers, strength-aware
+v0000000002c0b8a0_0 .net "X", 0 0, L_000000000412e380;  alias, 1 drivers
+S_0000000003a28990 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a27c10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412e700 .functor OR 1, L_000000000412e770, L_000000000412ea80, C4<0>, C4<0>;
+L_000000000412e850 .functor AND 1, L_000000000412e700, L_000000000412ee00, C4<1>, C4<1>;
+L_000000000412e380 .functor BUF 1, L_000000000412e850, C4<0>, C4<0>, C4<0>;
+v0000000002c08100_0 .net "A1", 0 0, L_000000000412ea80;  alias, 1 drivers
+v0000000002c095a0_0 .net "A2", 0 0, L_000000000412e770;  alias, 1 drivers
+v0000000002c075c0_0 .net "B1", 0 0, L_000000000412ee00;  alias, 1 drivers
+L_0000000003fe5ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c09320_0 .net8 "VGND", 0 0, L_0000000003fe5ec0;  1 drivers, strength-aware
+L_0000000003fe5ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c089c0_0 .net8 "VNB", 0 0, L_0000000003fe5ad0;  1 drivers, strength-aware
+L_0000000003fe62b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c090a0_0 .net8 "VPB", 0 0, L_0000000003fe62b0;  1 drivers, strength-aware
+L_0000000003fe50c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c09140_0 .net8 "VPWR", 0 0, L_0000000003fe50c0;  1 drivers, strength-aware
+v0000000002c07700_0 .net "X", 0 0, L_000000000412e380;  alias, 1 drivers
+v0000000002c093c0_0 .net "and0_out_X", 0 0, L_000000000412e850;  1 drivers
+v0000000002c08ce0_0 .net "or0_out", 0 0, L_000000000412e700;  1 drivers
+S_0000000003a27490 .scope module, "_0624_" "sky130_fd_sc_hd__inv_2" 3 1140, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c0a9a0_0 .net "A", 0 0, L_0000000003f908e0;  1 drivers
+L_0000000003fe68d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0bb20_0 .net8 "VGND", 0 0, L_0000000003fe68d0;  1 drivers, strength-aware
+L_0000000003fe5280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b6c0_0 .net8 "VNB", 0 0, L_0000000003fe5280;  1 drivers, strength-aware
+L_0000000003fe5f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0bda0_0 .net8 "VPB", 0 0, L_0000000003fe5f30;  1 drivers, strength-aware
+L_0000000003fe5bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a2c0_0 .net8 "VPWR", 0 0, L_0000000003fe5bb0;  1 drivers, strength-aware
+v0000000002c0b3a0_0 .net "Y", 0 0, L_000000000412e620;  alias, 1 drivers
+S_0000000003a25f90 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a27490;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412e3f0 .functor NOT 1, L_0000000003f908e0, C4<0>, C4<0>, C4<0>;
+L_000000000412e620 .functor BUF 1, L_000000000412e3f0, C4<0>, C4<0>, C4<0>;
+v0000000002c0bc60_0 .net "A", 0 0, L_0000000003f908e0;  alias, 1 drivers
+L_0000000003fe6390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b4e0_0 .net8 "VGND", 0 0, L_0000000003fe6390;  1 drivers, strength-aware
+L_0000000003fe5130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b120_0 .net8 "VNB", 0 0, L_0000000003fe5130;  1 drivers, strength-aware
+L_0000000003fe6940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ac20_0 .net8 "VPB", 0 0, L_0000000003fe6940;  1 drivers, strength-aware
+L_0000000003fe5360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a360_0 .net8 "VPWR", 0 0, L_0000000003fe5360;  1 drivers, strength-aware
+v0000000002c0b580_0 .net "Y", 0 0, L_000000000412e620;  alias, 1 drivers
+v0000000002c09be0_0 .net "not0_out_Y", 0 0, L_000000000412e3f0;  1 drivers
+S_0000000003a26b90 .scope module, "_0625_" "sky130_fd_sc_hd__a2bb2o_2" 3 1144, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000002c0b940_0 .net "A1_N", 0 0, L_00000000041258d0;  alias, 1 drivers
+v0000000002c0a040_0 .net "A2_N", 0 0, L_0000000003f90ac0;  1 drivers
+v0000000002c0b9e0_0 .net "B1", 0 0, L_00000000041258d0;  alias, 1 drivers
+v0000000002c0bbc0_0 .net "B2", 0 0, L_0000000003f91240;  1 drivers
+L_0000000003fe69b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0be40_0 .net8 "VGND", 0 0, L_0000000003fe69b0;  1 drivers, strength-aware
+L_0000000003fe51a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ba80_0 .net8 "VNB", 0 0, L_0000000003fe51a0;  1 drivers, strength-aware
+L_0000000003fe5d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a180_0 .net8 "VPB", 0 0, L_0000000003fe5d70;  1 drivers, strength-aware
+L_0000000003fe65c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a540_0 .net8 "VPWR", 0 0, L_0000000003fe65c0;  1 drivers, strength-aware
+v0000000002c0bee0_0 .net "X", 0 0, L_000000000412dc80;  alias, 1 drivers
+S_0000000003a2a310 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a26b90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412e8c0 .functor AND 1, L_00000000041258d0, L_0000000003f91240, C4<1>, C4<1>;
+L_000000000412e230 .functor NOR 1, L_00000000041258d0, L_0000000003f90ac0, C4<0>, C4<0>;
+L_000000000412dac0 .functor OR 1, L_000000000412e230, L_000000000412e8c0, C4<0>, C4<0>;
+L_000000000412dc80 .functor BUF 1, L_000000000412dac0, C4<0>, C4<0>, C4<0>;
+v0000000002c0b620_0 .net "A1_N", 0 0, L_00000000041258d0;  alias, 1 drivers
+v0000000002c0a400_0 .net "A2_N", 0 0, L_0000000003f90ac0;  alias, 1 drivers
+v0000000002c0b440_0 .net "B1", 0 0, L_00000000041258d0;  alias, 1 drivers
+v0000000002c0b760_0 .net "B2", 0 0, L_0000000003f91240;  alias, 1 drivers
+L_0000000003fe52f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a4a0_0 .net8 "VGND", 0 0, L_0000000003fe52f0;  1 drivers, strength-aware
+L_0000000003fe5fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c020_0 .net8 "VNB", 0 0, L_0000000003fe5fa0;  1 drivers, strength-aware
+L_0000000003fe6080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c09960_0 .net8 "VPB", 0 0, L_0000000003fe6080;  1 drivers, strength-aware
+L_0000000003fe5c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b800_0 .net8 "VPWR", 0 0, L_0000000003fe5c20;  1 drivers, strength-aware
+v0000000002c0bf80_0 .net "X", 0 0, L_000000000412dc80;  alias, 1 drivers
+v0000000002c09c80_0 .net "and0_out", 0 0, L_000000000412e8c0;  1 drivers
+v0000000002c0af40_0 .net "nor0_out", 0 0, L_000000000412e230;  1 drivers
+v0000000002c0ae00_0 .net "or0_out_X", 0 0, L_000000000412dac0;  1 drivers
+S_0000000003a2a790 .scope module, "_0626_" "sky130_fd_sc_hd__a221o_2" 3 1151, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c09dc0_0 .net "A1", 0 0, L_000000000412e620;  alias, 1 drivers
+v0000000002c0aae0_0 .net "A2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v0000000002c0b260_0 .net "B1", 0 0, L_0000000003f90b60;  1 drivers
+v0000000002c09f00_0 .net "B2", 0 0, L_0000000004126890;  alias, 1 drivers
+v0000000002c0a860_0 .net "C1", 0 0, L_000000000412dc80;  alias, 1 drivers
+L_0000000003fe54b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a0e0_0 .net8 "VGND", 0 0, L_0000000003fe54b0;  1 drivers, strength-aware
+L_0000000003fe6240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0acc0_0 .net8 "VNB", 0 0, L_0000000003fe6240;  1 drivers, strength-aware
+L_0000000003fe5c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0aa40_0 .net8 "VPB", 0 0, L_0000000003fe5c90;  1 drivers, strength-aware
+L_0000000003fe5520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ad60_0 .net8 "VPWR", 0 0, L_0000000003fe5520;  1 drivers, strength-aware
+v0000000002c0aea0_0 .net "X", 0 0, L_000000000412de40;  alias, 1 drivers
+S_0000000003a2a610 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a2a790;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412e930 .functor AND 1, L_0000000003f90b60, L_0000000004126890, C4<1>, C4<1>;
+L_000000000412db30 .functor AND 1, L_000000000412e620, L_0000000004127b60, C4<1>, C4<1>;
+L_000000000412ebd0 .functor OR 1, L_000000000412db30, L_000000000412e930, L_000000000412dc80, C4<0>;
+L_000000000412de40 .functor BUF 1, L_000000000412ebd0, C4<0>, C4<0>, C4<0>;
+v0000000002c0a900_0 .net "A1", 0 0, L_000000000412e620;  alias, 1 drivers
+v0000000002c09a00_0 .net "A2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v0000000002c0a5e0_0 .net "B1", 0 0, L_0000000003f90b60;  alias, 1 drivers
+v0000000002c0a220_0 .net "B2", 0 0, L_0000000004126890;  alias, 1 drivers
+v0000000002c09fa0_0 .net "C1", 0 0, L_000000000412dc80;  alias, 1 drivers
+L_0000000003fe6860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a720_0 .net8 "VGND", 0 0, L_0000000003fe6860;  1 drivers, strength-aware
+L_0000000003fe5670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c09e60_0 .net8 "VNB", 0 0, L_0000000003fe5670;  1 drivers, strength-aware
+L_0000000003fe60f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0a7c0_0 .net8 "VPB", 0 0, L_0000000003fe60f0;  1 drivers, strength-aware
+L_0000000003fe5590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b1c0_0 .net8 "VPWR", 0 0, L_0000000003fe5590;  1 drivers, strength-aware
+v0000000002c09aa0_0 .net "X", 0 0, L_000000000412de40;  alias, 1 drivers
+v0000000002c09b40_0 .net "and0_out", 0 0, L_000000000412e930;  1 drivers
+v0000000002c09d20_0 .net "and1_out", 0 0, L_000000000412db30;  1 drivers
+v0000000002c0ab80_0 .net "or0_out_X", 0 0, L_000000000412ebd0;  1 drivers
+S_0000000003a28c90 .scope module, "_0627_" "sky130_fd_sc_hd__inv_2" 3 1159, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c0e500_0 .net "A", 0 0, L_000000000412de40;  alias, 1 drivers
+L_0000000003fe5980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c480_0 .net8 "VGND", 0 0, L_0000000003fe5980;  1 drivers, strength-aware
+L_0000000003fe6160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0cca0_0 .net8 "VNB", 0 0, L_0000000003fe6160;  1 drivers, strength-aware
+L_0000000003fe61d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d600_0 .net8 "VPB", 0 0, L_0000000003fe61d0;  1 drivers, strength-aware
+L_0000000003fe6a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e320_0 .net8 "VPWR", 0 0, L_0000000003fe6a20;  1 drivers, strength-aware
+v0000000002c0c7a0_0 .net "Y", 0 0, L_000000000412e690;  alias, 1 drivers
+S_0000000003a28e10 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a28c90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412e4d0 .functor NOT 1, L_000000000412de40, C4<0>, C4<0>, C4<0>;
+L_000000000412e690 .functor BUF 1, L_000000000412e4d0, C4<0>, C4<0>, C4<0>;
+v0000000002c0afe0_0 .net "A", 0 0, L_000000000412de40;  alias, 1 drivers
+L_0000000003fe6a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b080_0 .net8 "VGND", 0 0, L_0000000003fe6a90;  1 drivers, strength-aware
+L_0000000003fe6b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0b300_0 .net8 "VNB", 0 0, L_0000000003fe6b00;  1 drivers, strength-aware
+L_0000000003fe6ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c840_0 .net8 "VPB", 0 0, L_0000000003fe6ef0;  1 drivers, strength-aware
+L_0000000003fe6f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ca20_0 .net8 "VPWR", 0 0, L_0000000003fe6f60;  1 drivers, strength-aware
+v0000000002c0c5c0_0 .net "Y", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000002c0d060_0 .net "not0_out_Y", 0 0, L_000000000412e4d0;  1 drivers
+S_0000000003a27d90 .scope module, "_0628_" "sky130_fd_sc_hd__o221a_2" 3 1163, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c0dc40_0 .net "A1", 0 0, L_0000000003f8fa80;  1 drivers
+v0000000002c0cf20_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v0000000002c0d920_0 .net "B1", 0 0, L_000000000412e620;  alias, 1 drivers
+v0000000002c0d9c0_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v0000000002c0d420_0 .net "C1", 0 0, L_000000000412dc80;  alias, 1 drivers
+L_0000000003fe6cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0cb60_0 .net8 "VGND", 0 0, L_0000000003fe6cc0;  1 drivers, strength-aware
+L_0000000003fe6d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c2a0_0 .net8 "VNB", 0 0, L_0000000003fe6d30;  1 drivers, strength-aware
+L_0000000003fe6da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c520_0 .net8 "VPB", 0 0, L_0000000003fe6da0;  1 drivers, strength-aware
+L_0000000003fe6e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0cac0_0 .net8 "VPWR", 0 0, L_0000000003fe6e80;  1 drivers, strength-aware
+v0000000002c0d6a0_0 .net "X", 0 0, L_000000000412eb60;  alias, 1 drivers
+S_0000000003a28f90 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a27d90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412e540 .functor OR 1, L_0000000004127230, L_000000000412e620, C4<0>, C4<0>;
+L_000000000412e9a0 .functor OR 1, L_0000000004127310, L_0000000003f8fa80, C4<0>, C4<0>;
+L_000000000412e5b0 .functor AND 1, L_000000000412e540, L_000000000412e9a0, L_000000000412dc80, C4<1>;
+L_000000000412eb60 .functor BUF 1, L_000000000412e5b0, C4<0>, C4<0>, C4<0>;
+v0000000002c0c980_0 .net "A1", 0 0, L_0000000003f8fa80;  alias, 1 drivers
+v0000000002c0c660_0 .net "A2", 0 0, L_0000000004127310;  alias, 1 drivers
+v0000000002c0e820_0 .net "B1", 0 0, L_000000000412e620;  alias, 1 drivers
+v0000000002c0d100_0 .net "B2", 0 0, L_0000000004127230;  alias, 1 drivers
+v0000000002c0e780_0 .net "C1", 0 0, L_000000000412dc80;  alias, 1 drivers
+L_0000000003fe6e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e5a0_0 .net8 "VGND", 0 0, L_0000000003fe6e10;  1 drivers, strength-aware
+L_0000000003fd8b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0da60_0 .net8 "VNB", 0 0, L_0000000003fd8b70;  1 drivers, strength-aware
+L_0000000003fd86a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0cde0_0 .net8 "VPB", 0 0, L_0000000003fd86a0;  1 drivers, strength-aware
+L_0000000003fd76e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e140_0 .net8 "VPWR", 0 0, L_0000000003fd76e0;  1 drivers, strength-aware
+v0000000002c0dba0_0 .net "X", 0 0, L_000000000412eb60;  alias, 1 drivers
+v0000000002c0cd40_0 .net "and0_out_X", 0 0, L_000000000412e5b0;  1 drivers
+v0000000002c0ce80_0 .net "or0_out", 0 0, L_000000000412e540;  1 drivers
+v0000000002c0db00_0 .net "or1_out", 0 0, L_000000000412e9a0;  1 drivers
+S_0000000003a27310 .scope module, "_0629_" "sky130_fd_sc_hd__nor2_2" 3 1171, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c0dd80_0 .net "A", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000002c0c0c0_0 .net "B", 0 0, L_000000000412eb60;  alias, 1 drivers
+L_0000000003fd8630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d240_0 .net8 "VGND", 0 0, L_0000000003fd8630;  1 drivers, strength-aware
+L_0000000003fd8010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e3c0_0 .net8 "VNB", 0 0, L_0000000003fd8010;  1 drivers, strength-aware
+L_0000000003fd8be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c700_0 .net8 "VPB", 0 0, L_0000000003fd8be0;  1 drivers, strength-aware
+L_0000000003fd84e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d2e0_0 .net8 "VPWR", 0 0, L_0000000003fd84e0;  1 drivers, strength-aware
+v0000000002c0de20_0 .net "Y", 0 0, L_000000000412ed20;  alias, 1 drivers
+S_0000000003a27610 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a27310;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412ef50 .functor NOR 1, L_000000000412e690, L_000000000412eb60, C4<0>, C4<0>;
+L_000000000412ed20 .functor BUF 1, L_000000000412ef50, C4<0>, C4<0>, C4<0>;
+v0000000002c0e640_0 .net "A", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000002c0d740_0 .net "B", 0 0, L_000000000412eb60;  alias, 1 drivers
+L_0000000003fd73d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d380_0 .net8 "VGND", 0 0, L_0000000003fd73d0;  1 drivers, strength-aware
+L_0000000003fd7440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0dce0_0 .net8 "VNB", 0 0, L_0000000003fd7440;  1 drivers, strength-aware
+L_0000000003fd7e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0cfc0_0 .net8 "VPB", 0 0, L_0000000003fd7e50;  1 drivers, strength-aware
+L_0000000003fd8780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d560_0 .net8 "VPWR", 0 0, L_0000000003fd8780;  1 drivers, strength-aware
+v0000000002c0d1a0_0 .net "Y", 0 0, L_000000000412ed20;  alias, 1 drivers
+v0000000002c0df60_0 .net "nor0_out_Y", 0 0, L_000000000412ef50;  1 drivers
+S_0000000003a29590 .scope module, "_0630_" "sky130_fd_sc_hd__and2_2" 3 1176, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c0e460_0 .net "A", 0 0, L_000000000412ed20;  alias, 1 drivers
+v0000000002c0e000_0 .net "B", 0 0, L_000000000412a800;  alias, 1 drivers
+L_0000000003fd8400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e0a0_0 .net8 "VGND", 0 0, L_0000000003fd8400;  1 drivers, strength-aware
+L_0000000003fd8c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e1e0_0 .net8 "VNB", 0 0, L_0000000003fd8c50;  1 drivers, strength-aware
+L_0000000003fd8550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e280_0 .net8 "VPB", 0 0, L_0000000003fd8550;  1 drivers, strength-aware
+L_0000000003fd7de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c200_0 .net8 "VPWR", 0 0, L_0000000003fd7de0;  1 drivers, strength-aware
+v0000000002c0c340_0 .net "X", 0 0, L_000000000412f420;  alias, 1 drivers
+S_0000000003a29d10 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a29590;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412ecb0 .functor AND 1, L_000000000412ed20, L_000000000412a800, C4<1>, C4<1>;
+L_000000000412f420 .functor BUF 1, L_000000000412ecb0, C4<0>, C4<0>, C4<0>;
+v0000000002c0d4c0_0 .net "A", 0 0, L_000000000412ed20;  alias, 1 drivers
+v0000000002c0cc00_0 .net "B", 0 0, L_000000000412a800;  alias, 1 drivers
+L_0000000003fd78a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0e6e0_0 .net8 "VGND", 0 0, L_0000000003fd78a0;  1 drivers, strength-aware
+L_0000000003fd7a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d7e0_0 .net8 "VNB", 0 0, L_0000000003fd7a60;  1 drivers, strength-aware
+L_0000000003fd8470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0c160_0 .net8 "VPB", 0 0, L_0000000003fd8470;  1 drivers, strength-aware
+L_0000000003fd79f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0d880_0 .net8 "VPWR", 0 0, L_0000000003fd79f0;  1 drivers, strength-aware
+v0000000002c0dec0_0 .net "X", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000002c0c8e0_0 .net "and0_out_X", 0 0, L_000000000412ecb0;  1 drivers
+S_0000000003a29710 .scope module, "_0631_" "sky130_fd_sc_hd__a221oi_2" 3 1181, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c10d00_0 .net "A1", 0 0, L_000000000412abf0;  alias, 1 drivers
+v0000000002c0fc20_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v0000000002c0f360_0 .net "B1", 0 0, L_0000000003f90c00;  1 drivers
+v0000000002c10580_0 .net "B2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v0000000002c0edc0_0 .net "C1", 0 0, L_000000000412bbb0;  alias, 1 drivers
+L_0000000003fd7750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f2c0_0 .net8 "VGND", 0 0, L_0000000003fd7750;  1 drivers, strength-aware
+L_0000000003fd87f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c10e40_0 .net8 "VNB", 0 0, L_0000000003fd87f0;  1 drivers, strength-aware
+L_0000000003fd8320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f9a0_0 .net8 "VPB", 0 0, L_0000000003fd8320;  1 drivers, strength-aware
+L_0000000003fd7b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f5e0_0 .net8 "VPWR", 0 0, L_0000000003fd7b40;  1 drivers, strength-aware
+v0000000002c0eb40_0 .net "Y", 0 0, L_000000000412efc0;  alias, 1 drivers
+S_0000000003a2a490 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a29710;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412ed90 .functor AND 1, L_0000000003f90c00, L_0000000004127b60, C4<1>, C4<1>;
+L_000000000412ee70 .functor AND 1, L_000000000412abf0, L_0000000004126270, C4<1>, C4<1>;
+L_000000000412dba0 .functor NOR 1, L_000000000412ed90, L_000000000412bbb0, L_000000000412ee70, C4<0>;
+L_000000000412efc0 .functor BUF 1, L_000000000412dba0, C4<0>, C4<0>, C4<0>;
+v0000000002c0c3e0_0 .net "A1", 0 0, L_000000000412abf0;  alias, 1 drivers
+v0000000002c10f80_0 .net "A2", 0 0, L_0000000004126270;  alias, 1 drivers
+v0000000002c10da0_0 .net "B1", 0 0, L_0000000003f90c00;  alias, 1 drivers
+v0000000002c10260_0 .net "B2", 0 0, L_0000000004127b60;  alias, 1 drivers
+v0000000002c0f680_0 .net "C1", 0 0, L_000000000412bbb0;  alias, 1 drivers
+L_0000000003fd8710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c10940_0 .net8 "VGND", 0 0, L_0000000003fd8710;  1 drivers, strength-aware
+L_0000000003fd7d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ed20_0 .net8 "VNB", 0 0, L_0000000003fd7d00;  1 drivers, strength-aware
+L_0000000003fd77c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c10120_0 .net8 "VPB", 0 0, L_0000000003fd77c0;  1 drivers, strength-aware
+L_0000000003fd7830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c101c0_0 .net8 "VPWR", 0 0, L_0000000003fd7830;  1 drivers, strength-aware
+v0000000002c10300_0 .net "Y", 0 0, L_000000000412efc0;  alias, 1 drivers
+v0000000002c0f540_0 .net "and0_out", 0 0, L_000000000412ed90;  1 drivers
+v0000000002c0f720_0 .net "and1_out", 0 0, L_000000000412ee70;  1 drivers
+v0000000002c0fb80_0 .net "nor0_out_Y", 0 0, L_000000000412dba0;  1 drivers
+S_0000000003a29a10 .scope module, "_0632_" "sky130_fd_sc_hd__or2_2" 3 1189, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c0f220_0 .net "A", 0 0, L_000000000412ab10;  alias, 1 drivers
+v0000000002c0ea00_0 .net "B", 0 0, L_000000000412efc0;  alias, 1 drivers
+L_0000000003fd7600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c10080_0 .net8 "VGND", 0 0, L_0000000003fd7600;  1 drivers, strength-aware
+L_0000000003fd7280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c10440_0 .net8 "VNB", 0 0, L_0000000003fd7280;  1 drivers, strength-aware
+L_0000000003fd7980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c11020_0 .net8 "VPB", 0 0, L_0000000003fd7980;  1 drivers, strength-aware
+L_0000000003fd70c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f4a0_0 .net8 "VPWR", 0 0, L_0000000003fd70c0;  1 drivers, strength-aware
+v0000000002c10800_0 .net "X", 0 0, L_000000000412ddd0;  alias, 1 drivers
+S_0000000003a26a10 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a29a10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412f030 .functor OR 1, L_000000000412efc0, L_000000000412ab10, C4<0>, C4<0>;
+L_000000000412ddd0 .functor BUF 1, L_000000000412f030, C4<0>, C4<0>, C4<0>;
+v0000000002c0e960_0 .net "A", 0 0, L_000000000412ab10;  alias, 1 drivers
+v0000000002c106c0_0 .net "B", 0 0, L_000000000412efc0;  alias, 1 drivers
+L_0000000003fd8080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f400_0 .net8 "VGND", 0 0, L_0000000003fd8080;  1 drivers, strength-aware
+L_0000000003fd7ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c103a0_0 .net8 "VNB", 0 0, L_0000000003fd7ec0;  1 drivers, strength-aware
+L_0000000003fd8a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c10760_0 .net8 "VPB", 0 0, L_0000000003fd8a20;  1 drivers, strength-aware
+L_0000000003fd7c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f7c0_0 .net8 "VPWR", 0 0, L_0000000003fd7c90;  1 drivers, strength-aware
+v0000000002c104e0_0 .net "X", 0 0, L_000000000412ddd0;  alias, 1 drivers
+v0000000002c0f860_0 .net "or0_out_X", 0 0, L_000000000412f030;  1 drivers
+S_0000000003a28210 .scope module, "_0633_" "sky130_fd_sc_hd__inv_2" 3 1194, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c0e8c0_0 .net "A", 0 0, L_000000000412ddd0;  alias, 1 drivers
+L_0000000003fd7130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0fae0_0 .net8 "VGND", 0 0, L_0000000003fd7130;  1 drivers, strength-aware
+L_0000000003fd71a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c10b20_0 .net8 "VNB", 0 0, L_0000000003fd71a0;  1 drivers, strength-aware
+L_0000000003fd85c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c109e0_0 .net8 "VPB", 0 0, L_0000000003fd85c0;  1 drivers, strength-aware
+L_0000000003fd7590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c10a80_0 .net8 "VPWR", 0 0, L_0000000003fd7590;  1 drivers, strength-aware
+v0000000002c0fd60_0 .net "Y", 0 0, L_000000000412e0e0;  alias, 1 drivers
+S_0000000003a29e90 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a28210;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412f180 .functor NOT 1, L_000000000412ddd0, C4<0>, C4<0>, C4<0>;
+L_000000000412e0e0 .functor BUF 1, L_000000000412f180, C4<0>, C4<0>, C4<0>;
+v0000000002c0ee60_0 .net "A", 0 0, L_000000000412ddd0;  alias, 1 drivers
+L_0000000003fd7f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f900_0 .net8 "VGND", 0 0, L_0000000003fd7f30;  1 drivers, strength-aware
+L_0000000003fd8240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0fa40_0 .net8 "VNB", 0 0, L_0000000003fd8240;  1 drivers, strength-aware
+L_0000000003fd7d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c10ee0_0 .net8 "VPB", 0 0, L_0000000003fd7d70;  1 drivers, strength-aware
+L_0000000003fd8860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0fcc0_0 .net8 "VPWR", 0 0, L_0000000003fd8860;  1 drivers, strength-aware
+v0000000002c10620_0 .net "Y", 0 0, L_000000000412e0e0;  alias, 1 drivers
+v0000000002c108a0_0 .net "not0_out_Y", 0 0, L_000000000412f180;  1 drivers
+S_0000000003a2a010 .scope module, "_0634_" "sky130_fd_sc_hd__o21ai_2" 3 1198, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002c0efa0_0 .net "A1", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000002c0f040_0 .net "A2", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000002c0f0e0_0 .net "B1", 0 0, L_000000000412e0e0;  alias, 1 drivers
+L_0000000003fd7910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0f180_0 .net8 "VGND", 0 0, L_0000000003fd7910;  1 drivers, strength-aware
+L_0000000003fd7360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c124c0_0 .net8 "VNB", 0 0, L_0000000003fd7360;  1 drivers, strength-aware
+L_0000000003fd7ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c12560_0 .net8 "VPB", 0 0, L_0000000003fd7ad0;  1 drivers, strength-aware
+L_0000000003fd7bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c136e0_0 .net8 "VPWR", 0 0, L_0000000003fd7bb0;  1 drivers, strength-aware
+v0000000002c12a60_0 .net "Y", 0 0, L_000000000412deb0;  alias, 1 drivers
+S_0000000003a28510 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a2a010;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412f110 .functor OR 1, L_000000000412f420, L_000000000412e690, C4<0>, C4<0>;
+L_000000000412f1f0 .functor NAND 1, L_000000000412e0e0, L_000000000412f110, C4<1>, C4<1>;
+L_000000000412deb0 .functor BUF 1, L_000000000412f1f0, C4<0>, C4<0>, C4<0>;
+v0000000002c10bc0_0 .net "A1", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000002c0fe00_0 .net "A2", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000002c10c60_0 .net "B1", 0 0, L_000000000412e0e0;  alias, 1 drivers
+L_0000000003fd7fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0fea0_0 .net8 "VGND", 0 0, L_0000000003fd7fa0;  1 drivers, strength-aware
+L_0000000003fd7c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ff40_0 .net8 "VNB", 0 0, L_0000000003fd7c20;  1 drivers, strength-aware
+L_0000000003fd80f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0eaa0_0 .net8 "VPB", 0 0, L_0000000003fd80f0;  1 drivers, strength-aware
+L_0000000003fd8160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c0ffe0_0 .net8 "VPWR", 0 0, L_0000000003fd8160;  1 drivers, strength-aware
+v0000000002c0ebe0_0 .net "Y", 0 0, L_000000000412deb0;  alias, 1 drivers
+v0000000002c0ec80_0 .net "nand0_out_Y", 0 0, L_000000000412f1f0;  1 drivers
+v0000000002c0ef00_0 .net "or0_out", 0 0, L_000000000412f110;  1 drivers
+S_0000000003a25210 .scope module, "_0635_" "sky130_fd_sc_hd__or2_2" 3 1204, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c12c40_0 .net "A", 0 0, L_000000000412e380;  alias, 1 drivers
+v0000000002c11660_0 .net "B", 0 0, L_000000000412deb0;  alias, 1 drivers
+L_0000000003fd82b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c12600_0 .net8 "VGND", 0 0, L_0000000003fd82b0;  1 drivers, strength-aware
+L_0000000003fd81d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c122e0_0 .net8 "VNB", 0 0, L_0000000003fd81d0;  1 drivers, strength-aware
+L_0000000003fd88d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c129c0_0 .net8 "VPB", 0 0, L_0000000003fd88d0;  1 drivers, strength-aware
+L_0000000003fd8940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c12ba0_0 .net8 "VPWR", 0 0, L_0000000003fd8940;  1 drivers, strength-aware
+v0000000002c12b00_0 .net "X", 0 0, L_000000000412f2d0;  alias, 1 drivers
+S_0000000003a25390 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a25210;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412f260 .functor OR 1, L_000000000412deb0, L_000000000412e380, C4<0>, C4<0>;
+L_000000000412f2d0 .functor BUF 1, L_000000000412f260, C4<0>, C4<0>, C4<0>;
+v0000000002c127e0_0 .net "A", 0 0, L_000000000412e380;  alias, 1 drivers
+v0000000002c117a0_0 .net "B", 0 0, L_000000000412deb0;  alias, 1 drivers
+L_0000000003fd8390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c11160_0 .net8 "VGND", 0 0, L_0000000003fd8390;  1 drivers, strength-aware
+L_0000000003fd7210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c11fc0_0 .net8 "VNB", 0 0, L_0000000003fd7210;  1 drivers, strength-aware
+L_0000000003fd8b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c12920_0 .net8 "VPB", 0 0, L_0000000003fd8b00;  1 drivers, strength-aware
+L_0000000003fd89b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13640_0 .net8 "VPWR", 0 0, L_0000000003fd89b0;  1 drivers, strength-aware
+v0000000002c13280_0 .net "X", 0 0, L_000000000412f2d0;  alias, 1 drivers
+v0000000002c11340_0 .net "or0_out_X", 0 0, L_000000000412f260;  1 drivers
+S_0000000003a2a190 .scope module, "_0636_" "sky130_fd_sc_hd__a221oi_2" 3 1209, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c131e0_0 .net "A1", 0 0, L_000000000412ca90;  alias, 1 drivers
+v0000000002c11d40_0 .net "A2", 0 0, L_0000000004126190;  alias, 1 drivers
+v0000000002c11520_0 .net "B1", 0 0, L_0000000003f91600;  1 drivers
+v0000000002c13320_0 .net "B2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v0000000002c11700_0 .net "C1", 0 0, L_000000000412d660;  alias, 1 drivers
+L_0000000003fd8a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c118e0_0 .net8 "VGND", 0 0, L_0000000003fd8a90;  1 drivers, strength-aware
+L_0000000003fd72f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c12d80_0 .net8 "VNB", 0 0, L_0000000003fd72f0;  1 drivers, strength-aware
+L_0000000003fd74b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13000_0 .net8 "VPB", 0 0, L_0000000003fd74b0;  1 drivers, strength-aware
+L_0000000003fd7520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c110c0_0 .net8 "VPWR", 0 0, L_0000000003fd7520;  1 drivers, strength-aware
+v0000000002c12ec0_0 .net "Y", 0 0, L_000000000412d970;  alias, 1 drivers
+S_0000000003a2a910 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a2a190;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412f340 .functor AND 1, L_0000000003f91600, L_0000000004127a80, C4<1>, C4<1>;
+L_000000000412f490 .functor AND 1, L_000000000412ca90, L_0000000004126190, C4<1>, C4<1>;
+L_000000000412d900 .functor NOR 1, L_000000000412f340, L_000000000412d660, L_000000000412f490, C4<0>;
+L_000000000412d970 .functor BUF 1, L_000000000412d900, C4<0>, C4<0>, C4<0>;
+v0000000002c126a0_0 .net "A1", 0 0, L_000000000412ca90;  alias, 1 drivers
+v0000000002c11ca0_0 .net "A2", 0 0, L_0000000004126190;  alias, 1 drivers
+v0000000002c12ce0_0 .net "B1", 0 0, L_0000000003f91600;  alias, 1 drivers
+v0000000002c12880_0 .net "B2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v0000000002c12740_0 .net "C1", 0 0, L_000000000412d660;  alias, 1 drivers
+L_0000000003fd7670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c12380_0 .net8 "VGND", 0 0, L_0000000003fd7670;  1 drivers, strength-aware
+L_0000000003ff99d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c12e20_0 .net8 "VNB", 0 0, L_0000000003ff99d0;  1 drivers, strength-aware
+L_0000000003ff98f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c11ac0_0 .net8 "VPB", 0 0, L_0000000003ff98f0;  1 drivers, strength-aware
+L_0000000003ffa680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c11de0_0 .net8 "VPWR", 0 0, L_0000000003ffa680;  1 drivers, strength-aware
+v0000000002c11840_0 .net "Y", 0 0, L_000000000412d970;  alias, 1 drivers
+v0000000002c11a20_0 .net "and0_out", 0 0, L_000000000412f340;  1 drivers
+v0000000002c121a0_0 .net "and1_out", 0 0, L_000000000412f490;  1 drivers
+v0000000002c11e80_0 .net "nor0_out_Y", 0 0, L_000000000412d900;  1 drivers
+S_0000000003a2ad90 .scope module, "_0637_" "sky130_fd_sc_hd__or2_2" 3 1217, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c11b60_0 .net "A", 0 0, L_000000000412cbe0;  alias, 1 drivers
+v0000000002c12240_0 .net "B", 0 0, L_000000000412d970;  alias, 1 drivers
+L_0000000003ff9810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13500_0 .net8 "VGND", 0 0, L_0000000003ff9810;  1 drivers, strength-aware
+L_0000000003ffa990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c135a0_0 .net8 "VNB", 0 0, L_0000000003ffa990;  1 drivers, strength-aware
+L_0000000003ffa1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13780_0 .net8 "VPB", 0 0, L_0000000003ffa1b0;  1 drivers, strength-aware
+L_0000000003ffa760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c11980_0 .net8 "VPWR", 0 0, L_0000000003ffa760;  1 drivers, strength-aware
+v0000000002c13820_0 .net "X", 0 0, L_000000000412dd60;  alias, 1 drivers
+S_0000000003a27790 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a2ad90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412dcf0 .functor OR 1, L_000000000412d970, L_000000000412cbe0, C4<0>, C4<0>;
+L_000000000412dd60 .functor BUF 1, L_000000000412dcf0, C4<0>, C4<0>, C4<0>;
+v0000000002c13460_0 .net "A", 0 0, L_000000000412cbe0;  alias, 1 drivers
+v0000000002c11f20_0 .net "B", 0 0, L_000000000412d970;  alias, 1 drivers
+L_0000000003ff9960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c130a0_0 .net8 "VGND", 0 0, L_0000000003ff9960;  1 drivers, strength-aware
+L_0000000003ff97a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c12f60_0 .net8 "VNB", 0 0, L_0000000003ff97a0;  1 drivers, strength-aware
+L_0000000003ffa6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13140_0 .net8 "VPB", 0 0, L_0000000003ffa6f0;  1 drivers, strength-aware
+L_0000000003ff92d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c133c0_0 .net8 "VPWR", 0 0, L_0000000003ff92d0;  1 drivers, strength-aware
+v0000000002c12060_0 .net "X", 0 0, L_000000000412dd60;  alias, 1 drivers
+v0000000002c12100_0 .net "or0_out_X", 0 0, L_000000000412dcf0;  1 drivers
+S_0000000003a2aa90 .scope module, "_0638_" "sky130_fd_sc_hd__inv_2" 3 1222, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c13f00_0 .net "A", 0 0, L_000000000412dd60;  alias, 1 drivers
+L_0000000003ff9c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13fa0_0 .net8 "VGND", 0 0, L_0000000003ff9c00;  1 drivers, strength-aware
+L_0000000003ffa840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c15da0_0 .net8 "VNB", 0 0, L_0000000003ffa840;  1 drivers, strength-aware
+L_0000000003ff9a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c138c0_0 .net8 "VPB", 0 0, L_0000000003ff9a40;  1 drivers, strength-aware
+L_0000000003ff9ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15580_0 .net8 "VPWR", 0 0, L_0000000003ff9ab0;  1 drivers, strength-aware
+v0000000002c153a0_0 .net "Y", 0 0, L_000000000412df90;  alias, 1 drivers
+S_0000000003a27010 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2aa90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412df20 .functor NOT 1, L_000000000412dd60, C4<0>, C4<0>, C4<0>;
+L_000000000412df90 .functor BUF 1, L_000000000412df20, C4<0>, C4<0>, C4<0>;
+v0000000002c11c00_0 .net "A", 0 0, L_000000000412dd60;  alias, 1 drivers
+L_0000000003ffa220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c115c0_0 .net8 "VGND", 0 0, L_0000000003ffa220;  1 drivers, strength-aware
+L_0000000003ff9570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c11200_0 .net8 "VNB", 0 0, L_0000000003ff9570;  1 drivers, strength-aware
+L_0000000003ffabc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c113e0_0 .net8 "VPB", 0 0, L_0000000003ffabc0;  1 drivers, strength-aware
+L_0000000003ff9340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c12420_0 .net8 "VPWR", 0 0, L_0000000003ff9340;  1 drivers, strength-aware
+v0000000002c112a0_0 .net "Y", 0 0, L_000000000412df90;  alias, 1 drivers
+v0000000002c11480_0 .net "not0_out_Y", 0 0, L_000000000412df20;  1 drivers
+S_0000000003a2ac10 .scope module, "_0639_" "sky130_fd_sc_hd__inv_2" 3 1226, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c15440_0 .net "A", 0 0, L_0000000003f90fc0;  1 drivers
+L_0000000003ffac30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c15c60_0 .net8 "VGND", 0 0, L_0000000003ffac30;  1 drivers, strength-aware
+L_0000000003ffa450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c154e0_0 .net8 "VNB", 0 0, L_0000000003ffa450;  1 drivers, strength-aware
+L_0000000003ff9ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c151c0_0 .net8 "VPB", 0 0, L_0000000003ff9ea0;  1 drivers, strength-aware
+L_0000000003ffa7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15620_0 .net8 "VPWR", 0 0, L_0000000003ffa7d0;  1 drivers, strength-aware
+v0000000002c14360_0 .net "Y", 0 0, L_0000000004130c30;  alias, 1 drivers
+S_0000000003a26290 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2ac10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412e070 .functor NOT 1, L_0000000003f90fc0, C4<0>, C4<0>, C4<0>;
+L_0000000004130c30 .functor BUF 1, L_000000000412e070, C4<0>, C4<0>, C4<0>;
+v0000000002c15e40_0 .net "A", 0 0, L_0000000003f90fc0;  alias, 1 drivers
+L_0000000003ff9ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c15260_0 .net8 "VGND", 0 0, L_0000000003ff9ce0;  1 drivers, strength-aware
+L_0000000003ff9490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13960_0 .net8 "VNB", 0 0, L_0000000003ff9490;  1 drivers, strength-aware
+L_0000000003ff9420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13d20_0 .net8 "VPB", 0 0, L_0000000003ff9420;  1 drivers, strength-aware
+L_0000000003ff95e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15120_0 .net8 "VPWR", 0 0, L_0000000003ff95e0;  1 drivers, strength-aware
+v0000000002c145e0_0 .net "Y", 0 0, L_0000000004130c30;  alias, 1 drivers
+v0000000002c15300_0 .net "not0_out_Y", 0 0, L_000000000412e070;  1 drivers
+S_0000000003a25810 .scope module, "_0640_" "sky130_fd_sc_hd__buf_1" 3 1230, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c15760_0 .net "A", 0 0, L_00000000041270e0;  alias, 1 drivers
+L_0000000003ff93b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c15f80_0 .net8 "VGND", 0 0, L_0000000003ff93b0;  1 drivers, strength-aware
+L_0000000003ff9500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13be0_0 .net8 "VNB", 0 0, L_0000000003ff9500;  1 drivers, strength-aware
+L_0000000003ffa300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15800_0 .net8 "VPB", 0 0, L_0000000003ffa300;  1 drivers, strength-aware
+L_0000000003ffa4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c158a0_0 .net8 "VPWR", 0 0, L_0000000003ffa4c0;  1 drivers, strength-aware
+v0000000002c15940_0 .net "X", 0 0, L_0000000004130300;  alias, 1 drivers
+S_0000000003a27190 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a25810;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041308b0 .functor BUF 1, L_00000000041270e0, C4<0>, C4<0>, C4<0>;
+L_0000000004130300 .functor BUF 1, L_00000000041308b0, C4<0>, C4<0>, C4<0>;
+v0000000002c156c0_0 .net "A", 0 0, L_00000000041270e0;  alias, 1 drivers
+L_0000000003ff9880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c14540_0 .net8 "VGND", 0 0, L_0000000003ff9880;  1 drivers, strength-aware
+L_0000000003ff9260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c15b20_0 .net8 "VNB", 0 0, L_0000000003ff9260;  1 drivers, strength-aware
+L_0000000003ffa610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c14680_0 .net8 "VPB", 0 0, L_0000000003ffa610;  1 drivers, strength-aware
+L_0000000003ff90a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15bc0_0 .net8 "VPWR", 0 0, L_0000000003ff90a0;  1 drivers, strength-aware
+v0000000002c14400_0 .net "X", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000002c14a40_0 .net "buf0_out_X", 0 0, L_00000000041308b0;  1 drivers
+S_0000000003a25510 .scope module, "_0641_" "sky130_fd_sc_hd__buf_1" 3 1234, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c15d00_0 .net "A", 0 0, L_0000000004130300;  alias, 1 drivers
+L_0000000003ff9f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13e60_0 .net8 "VGND", 0 0, L_0000000003ff9f10;  1 drivers, strength-aware
+L_0000000003ff9ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c14900_0 .net8 "VNB", 0 0, L_0000000003ff9ff0;  1 drivers, strength-aware
+L_0000000003ffa370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13a00_0 .net8 "VPB", 0 0, L_0000000003ffa370;  1 drivers, strength-aware
+L_0000000003ff9650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15a80_0 .net8 "VPWR", 0 0, L_0000000003ff9650;  1 drivers, strength-aware
+v0000000002c14fe0_0 .net "X", 0 0, L_0000000004130f40;  alias, 1 drivers
+S_0000000003a25990 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a25510;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004130ae0 .functor BUF 1, L_0000000004130300, C4<0>, C4<0>, C4<0>;
+L_0000000004130f40 .functor BUF 1, L_0000000004130ae0, C4<0>, C4<0>, C4<0>;
+v0000000002c14040_0 .net "A", 0 0, L_0000000004130300;  alias, 1 drivers
+L_0000000003ff9c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c16020_0 .net8 "VGND", 0 0, L_0000000003ff9c70;  1 drivers, strength-aware
+L_0000000003ff96c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c144a0_0 .net8 "VNB", 0 0, L_0000000003ff96c0;  1 drivers, strength-aware
+L_0000000003ff9d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c159e0_0 .net8 "VPB", 0 0, L_0000000003ff9d50;  1 drivers, strength-aware
+L_0000000003ff9b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c14cc0_0 .net8 "VPWR", 0 0, L_0000000003ff9b20;  1 drivers, strength-aware
+v0000000002c14d60_0 .net "X", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000002c15ee0_0 .net "buf0_out_X", 0 0, L_0000000004130ae0;  1 drivers
+S_0000000003a25b10 .scope module, "_0642_" "sky130_fd_sc_hd__a2bb2o_2" 3 1238, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000002c14e00_0 .net "A1_N", 0 0, L_0000000004126510;  alias, 1 drivers
+v0000000002c14720_0 .net "A2_N", 0 0, L_0000000003f91060;  1 drivers
+v0000000002c147c0_0 .net "B1", 0 0, L_0000000004126510;  alias, 1 drivers
+v0000000002c14860_0 .net "B2", 0 0, L_0000000003f902a0;  1 drivers
+L_0000000003ffa530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c149a0_0 .net8 "VGND", 0 0, L_0000000003ffa530;  1 drivers, strength-aware
+L_0000000003ffa0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c14f40_0 .net8 "VNB", 0 0, L_0000000003ffa0d0;  1 drivers, strength-aware
+L_0000000003ffa8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c15080_0 .net8 "VPB", 0 0, L_0000000003ffa8b0;  1 drivers, strength-aware
+L_0000000003ffab50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17240_0 .net8 "VPWR", 0 0, L_0000000003ffab50;  1 drivers, strength-aware
+v0000000002c16700_0 .net "X", 0 0, L_000000000412ff10;  alias, 1 drivers
+S_0000000003a25c90 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a25b10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004130d80 .functor AND 1, L_0000000004126510, L_0000000003f902a0, C4<1>, C4<1>;
+L_000000000412f810 .functor NOR 1, L_0000000004126510, L_0000000003f91060, C4<0>, C4<0>;
+L_0000000004130370 .functor OR 1, L_000000000412f810, L_0000000004130d80, C4<0>, C4<0>;
+L_000000000412ff10 .functor BUF 1, L_0000000004130370, C4<0>, C4<0>, C4<0>;
+v0000000002c13aa0_0 .net "A1_N", 0 0, L_0000000004126510;  alias, 1 drivers
+v0000000002c14ea0_0 .net "A2_N", 0 0, L_0000000003f91060;  alias, 1 drivers
+v0000000002c14b80_0 .net "B1", 0 0, L_0000000004126510;  alias, 1 drivers
+v0000000002c14c20_0 .net "B2", 0 0, L_0000000003f902a0;  alias, 1 drivers
+L_0000000003ff9110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13b40_0 .net8 "VGND", 0 0, L_0000000003ff9110;  1 drivers, strength-aware
+L_0000000003ff9dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c13c80_0 .net8 "VNB", 0 0, L_0000000003ff9dc0;  1 drivers, strength-aware
+L_0000000003ffa290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c13dc0_0 .net8 "VPB", 0 0, L_0000000003ffa290;  1 drivers, strength-aware
+L_0000000003ff9b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c14ae0_0 .net8 "VPWR", 0 0, L_0000000003ff9b90;  1 drivers, strength-aware
+v0000000002c140e0_0 .net "X", 0 0, L_000000000412ff10;  alias, 1 drivers
+v0000000002c14180_0 .net "and0_out", 0 0, L_0000000004130d80;  1 drivers
+v0000000002c14220_0 .net "nor0_out", 0 0, L_000000000412f810;  1 drivers
+v0000000002c142c0_0 .net "or0_out_X", 0 0, L_0000000004130370;  1 drivers
+S_0000000003a26410 .scope module, "_0643_" "sky130_fd_sc_hd__a221o_2" 3 1245, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c17100_0 .net "A1", 0 0, L_0000000004130c30;  alias, 1 drivers
+v0000000002c186e0_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000002c17600_0 .net "B1", 0 0, L_0000000003f8fc60;  1 drivers
+v0000000002c180a0_0 .net "B2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000002c177e0_0 .net "C1", 0 0, L_000000000412ff10;  alias, 1 drivers
+L_0000000003ff9180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c167a0_0 .net8 "VGND", 0 0, L_0000000003ff9180;  1 drivers, strength-aware
+L_0000000003ffa5a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17ba0_0 .net8 "VNB", 0 0, L_0000000003ffa5a0;  1 drivers, strength-aware
+L_0000000003ffa920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c16160_0 .net8 "VPB", 0 0, L_0000000003ffa920;  1 drivers, strength-aware
+L_0000000003ff9e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17a60_0 .net8 "VPWR", 0 0, L_0000000003ff9e30;  1 drivers, strength-aware
+v0000000002c17920_0 .net "X", 0 0, L_000000000412fdc0;  alias, 1 drivers
+S_0000000003a26590 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a26410;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004130060 .functor AND 1, L_0000000003f8fc60, L_0000000004125860, C4<1>, C4<1>;
+L_0000000004130450 .functor AND 1, L_0000000004130c30, L_0000000004130f40, C4<1>, C4<1>;
+L_0000000004130fb0 .functor OR 1, L_0000000004130450, L_0000000004130060, L_000000000412ff10, C4<0>;
+L_000000000412fdc0 .functor BUF 1, L_0000000004130fb0, C4<0>, C4<0>, C4<0>;
+v0000000002c16e80_0 .net "A1", 0 0, L_0000000004130c30;  alias, 1 drivers
+v0000000002c16ca0_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000002c16a20_0 .net "B1", 0 0, L_0000000003f8fc60;  alias, 1 drivers
+v0000000002c18320_0 .net "B2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000002c18640_0 .net "C1", 0 0, L_000000000412ff10;  alias, 1 drivers
+L_0000000003ffaa00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c181e0_0 .net8 "VGND", 0 0, L_0000000003ffaa00;  1 drivers, strength-aware
+L_0000000003ff9f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c16980_0 .net8 "VNB", 0 0, L_0000000003ff9f80;  1 drivers, strength-aware
+L_0000000003ffa3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c16c00_0 .net8 "VPB", 0 0, L_0000000003ffa3e0;  1 drivers, strength-aware
+L_0000000003ffaa70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17f60_0 .net8 "VPWR", 0 0, L_0000000003ffaa70;  1 drivers, strength-aware
+v0000000002c174c0_0 .net "X", 0 0, L_000000000412fdc0;  alias, 1 drivers
+v0000000002c179c0_0 .net "and0_out", 0 0, L_0000000004130060;  1 drivers
+v0000000002c18000_0 .net "and1_out", 0 0, L_0000000004130450;  1 drivers
+v0000000002c18500_0 .net "or0_out_X", 0 0, L_0000000004130fb0;  1 drivers
+S_0000000003a26710 .scope module, "_0644_" "sky130_fd_sc_hd__inv_2" 3 1253, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c16fc0_0 .net "A", 0 0, L_000000000412fdc0;  alias, 1 drivers
+L_0000000003ffa060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17c40_0 .net8 "VGND", 0 0, L_0000000003ffa060;  1 drivers, strength-aware
+L_0000000003ffa140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c18460_0 .net8 "VNB", 0 0, L_0000000003ffa140;  1 drivers, strength-aware
+L_0000000003ffaae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17ce0_0 .net8 "VPB", 0 0, L_0000000003ffaae0;  1 drivers, strength-aware
+L_0000000003ff91f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c16840_0 .net8 "VPWR", 0 0, L_0000000003ff91f0;  1 drivers, strength-aware
+v0000000002c17560_0 .net "Y", 0 0, L_000000000412f9d0;  alias, 1 drivers
+S_0000000003a26890 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a26710;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412fff0 .functor NOT 1, L_000000000412fdc0, C4<0>, C4<0>, C4<0>;
+L_000000000412f9d0 .functor BUF 1, L_000000000412fff0, C4<0>, C4<0>, C4<0>;
+v0000000002c18140_0 .net "A", 0 0, L_000000000412fdc0;  alias, 1 drivers
+L_0000000003ff9730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c18280_0 .net8 "VGND", 0 0, L_0000000003ff9730;  1 drivers, strength-aware
+L_0000000003ffbdb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17ec0_0 .net8 "VNB", 0 0, L_0000000003ffbdb0;  1 drivers, strength-aware
+L_0000000003ffc360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17b00_0 .net8 "VPB", 0 0, L_0000000003ffc360;  1 drivers, strength-aware
+L_0000000003ffb560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c160c0_0 .net8 "VPWR", 0 0, L_0000000003ffb560;  1 drivers, strength-aware
+v0000000002c162a0_0 .net "Y", 0 0, L_000000000412f9d0;  alias, 1 drivers
+v0000000002c183c0_0 .net "not0_out_Y", 0 0, L_000000000412fff0;  1 drivers
+S_0000000003a2c710 .scope module, "_0645_" "sky130_fd_sc_hd__nor2_2" 3 1257, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c168e0_0 .net "A", 0 0, L_000000000412df90;  alias, 1 drivers
+v0000000002c18820_0 .net "B", 0 0, L_000000000412f9d0;  alias, 1 drivers
+L_0000000003ffb3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c172e0_0 .net8 "VGND", 0 0, L_0000000003ffb3a0;  1 drivers, strength-aware
+L_0000000003ffc280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17d80_0 .net8 "VNB", 0 0, L_0000000003ffc280;  1 drivers, strength-aware
+L_0000000003ffaed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17380_0 .net8 "VPB", 0 0, L_0000000003ffaed0;  1 drivers, strength-aware
+L_0000000003ffb800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17e20_0 .net8 "VPWR", 0 0, L_0000000003ffb800;  1 drivers, strength-aware
+v0000000002c16200_0 .net "Y", 0 0, L_00000000041300d0;  alias, 1 drivers
+S_0000000003a2b990 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2c710;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412fe30 .functor NOR 1, L_000000000412df90, L_000000000412f9d0, C4<0>, C4<0>;
+L_00000000041300d0 .functor BUF 1, L_000000000412fe30, C4<0>, C4<0>, C4<0>;
+v0000000002c16ac0_0 .net "A", 0 0, L_000000000412df90;  alias, 1 drivers
+v0000000002c165c0_0 .net "B", 0 0, L_000000000412f9d0;  alias, 1 drivers
+L_0000000003ffc440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17740_0 .net8 "VGND", 0 0, L_0000000003ffc440;  1 drivers, strength-aware
+L_0000000003ffb4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c163e0_0 .net8 "VNB", 0 0, L_0000000003ffb4f0;  1 drivers, strength-aware
+L_0000000003ffb6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17060_0 .net8 "VPB", 0 0, L_0000000003ffb6b0;  1 drivers, strength-aware
+L_0000000003ffbe20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c185a0_0 .net8 "VPWR", 0 0, L_0000000003ffbe20;  1 drivers, strength-aware
+v0000000002c18780_0 .net "Y", 0 0, L_00000000041300d0;  alias, 1 drivers
+v0000000002c176a0_0 .net "nor0_out_Y", 0 0, L_000000000412fe30;  1 drivers
+S_0000000003a2bb10 .scope module, "_0646_" "sky130_fd_sc_hd__inv_2" 3 1262, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c16d40_0 .net "A", 0 0, L_0000000003f91380;  1 drivers
+L_0000000003ffb170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c171a0_0 .net8 "VGND", 0 0, L_0000000003ffb170;  1 drivers, strength-aware
+L_0000000003ffc7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c17420_0 .net8 "VNB", 0 0, L_0000000003ffc7c0;  1 drivers, strength-aware
+L_0000000003ffaf40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c17880_0 .net8 "VPB", 0 0, L_0000000003ffaf40;  1 drivers, strength-aware
+L_0000000003ffc830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c18aa0_0 .net8 "VPWR", 0 0, L_0000000003ffc830;  1 drivers, strength-aware
+v0000000002c18be0_0 .net "Y", 0 0, L_0000000004130bc0;  alias, 1 drivers
+S_0000000003a2cd10 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2bb10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412fea0 .functor NOT 1, L_0000000003f91380, C4<0>, C4<0>, C4<0>;
+L_0000000004130bc0 .functor BUF 1, L_000000000412fea0, C4<0>, C4<0>, C4<0>;
+v0000000002c16de0_0 .net "A", 0 0, L_0000000003f91380;  alias, 1 drivers
+L_0000000003ffc050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c16340_0 .net8 "VGND", 0 0, L_0000000003ffc050;  1 drivers, strength-aware
+L_0000000003ffbaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c16480_0 .net8 "VNB", 0 0, L_0000000003ffbaa0;  1 drivers, strength-aware
+L_0000000003ffc2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c16f20_0 .net8 "VPB", 0 0, L_0000000003ffc2f0;  1 drivers, strength-aware
+L_0000000003ffb8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c16520_0 .net8 "VPWR", 0 0, L_0000000003ffb8e0;  1 drivers, strength-aware
+v0000000002c16660_0 .net "Y", 0 0, L_0000000004130bc0;  alias, 1 drivers
+v0000000002c16b60_0 .net "not0_out_Y", 0 0, L_000000000412fea0;  1 drivers
+S_0000000003a2be10 .scope module, "_0647_" "sky130_fd_sc_hd__buf_1" 3 1266, 4 81154 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+v0000000002c1a8a0_0 .net "A", 0 0, L_00000000041279a0;  alias, 1 drivers
+L_0000000003ffb090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1a3a0_0 .net8 "VGND", 0 0, L_0000000003ffb090;  1 drivers, strength-aware
+L_0000000003ffb020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1a1c0_0 .net8 "VNB", 0 0, L_0000000003ffb020;  1 drivers, strength-aware
+L_0000000003ffb1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1a300_0 .net8 "VPB", 0 0, L_0000000003ffb1e0;  1 drivers, strength-aware
+L_0000000003ffafb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c19540_0 .net8 "VPWR", 0 0, L_0000000003ffafb0;  1 drivers, strength-aware
+v0000000002c1a4e0_0 .net "X", 0 0, L_0000000004130140;  alias, 1 drivers
+S_0000000003a2c410 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_0000000003a2be10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412f880 .functor BUF 1, L_00000000041279a0, C4<0>, C4<0>, C4<0>;
+L_0000000004130140 .functor BUF 1, L_000000000412f880, C4<0>, C4<0>, C4<0>;
+v0000000002c1a440_0 .net "A", 0 0, L_00000000041279a0;  alias, 1 drivers
+L_0000000003ffb720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1abc0_0 .net8 "VGND", 0 0, L_0000000003ffb720;  1 drivers, strength-aware
+L_0000000003ffc670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1af80_0 .net8 "VNB", 0 0, L_0000000003ffc670;  1 drivers, strength-aware
+L_0000000003ffc600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c19720_0 .net8 "VPB", 0 0, L_0000000003ffc600;  1 drivers, strength-aware
+L_0000000003ffc6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b020_0 .net8 "VPWR", 0 0, L_0000000003ffc6e0;  1 drivers, strength-aware
+v0000000002c1ad00_0 .net "X", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000002c1a260_0 .net "buf0_out_X", 0 0, L_000000000412f880;  1 drivers
+S_0000000003a2b810 .scope module, "_0648_" "sky130_fd_sc_hd__a2bb2o_2" 3 1270, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000002c1a760_0 .net "A1_N", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000002c188c0_0 .net "A2_N", 0 0, L_0000000003f91100;  1 drivers
+v0000000002c18c80_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000002c19f40_0 .net "B2", 0 0, L_0000000003f912e0;  1 drivers
+L_0000000003ffc750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c19e00_0 .net8 "VGND", 0 0, L_0000000003ffc750;  1 drivers, strength-aware
+L_0000000003ffc210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1ac60_0 .net8 "VNB", 0 0, L_0000000003ffc210;  1 drivers, strength-aware
+L_0000000003ffb480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c18a00_0 .net8 "VPB", 0 0, L_0000000003ffb480;  1 drivers, strength-aware
+L_0000000003ffb100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c194a0_0 .net8 "VPWR", 0 0, L_0000000003ffb100;  1 drivers, strength-aware
+v0000000002c19680_0 .net "X", 0 0, L_000000000412ff80;  alias, 1 drivers
+S_0000000003a2c290 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a2b810;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412f6c0 .functor AND 1, L_0000000004130140, L_0000000003f912e0, C4<1>, C4<1>;
+L_0000000004130290 .functor NOR 1, L_0000000004130140, L_0000000003f91100, C4<0>, C4<0>;
+L_000000000412fa40 .functor OR 1, L_0000000004130290, L_000000000412f6c0, C4<0>, C4<0>;
+L_000000000412ff80 .functor BUF 1, L_000000000412fa40, C4<0>, C4<0>, C4<0>;
+v0000000002c19360_0 .net "A1_N", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000002c1a580_0 .net "A2_N", 0 0, L_0000000003f91100;  alias, 1 drivers
+v0000000002c192c0_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000002c1ae40_0 .net "B2", 0 0, L_0000000003f912e0;  alias, 1 drivers
+L_0000000003ffb790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c199a0_0 .net8 "VGND", 0 0, L_0000000003ffb790;  1 drivers, strength-aware
+L_0000000003ffb5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1ab20_0 .net8 "VNB", 0 0, L_0000000003ffb5d0;  1 drivers, strength-aware
+L_0000000003ffb9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c18b40_0 .net8 "VPB", 0 0, L_0000000003ffb9c0;  1 drivers, strength-aware
+L_0000000003ffb640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c195e0_0 .net8 "VPWR", 0 0, L_0000000003ffb640;  1 drivers, strength-aware
+v0000000002c1ada0_0 .net "X", 0 0, L_000000000412ff80;  alias, 1 drivers
+v0000000002c197c0_0 .net "and0_out", 0 0, L_000000000412f6c0;  1 drivers
+v0000000002c1a620_0 .net "nor0_out", 0 0, L_0000000004130290;  1 drivers
+v0000000002c1a6c0_0 .net "or0_out_X", 0 0, L_000000000412fa40;  1 drivers
+S_0000000003a2b510 .scope module, "_0649_" "sky130_fd_sc_hd__o221a_2" 3 1277, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c19180_0 .net "A1", 0 0, L_0000000003f8fee0;  1 drivers
+v0000000002c18f00_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000002c19040_0 .net "B1", 0 0, L_0000000004130bc0;  alias, 1 drivers
+v0000000002c19b80_0 .net "B2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000002c190e0_0 .net "C1", 0 0, L_000000000412ff80;  alias, 1 drivers
+L_0000000003ffb2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c19220_0 .net8 "VGND", 0 0, L_0000000003ffb2c0;  1 drivers, strength-aware
+L_0000000003ffb330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c19860_0 .net8 "VNB", 0 0, L_0000000003ffb330;  1 drivers, strength-aware
+L_0000000003ffbe90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c19900_0 .net8 "VPB", 0 0, L_0000000003ffbe90;  1 drivers, strength-aware
+L_0000000003ffbbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c19a40_0 .net8 "VPWR", 0 0, L_0000000003ffbbf0;  1 drivers, strength-aware
+v0000000002c19ae0_0 .net "X", 0 0, L_0000000004131020;  alias, 1 drivers
+S_0000000003a2b690 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a2b510;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041303e0 .functor OR 1, L_0000000004130f40, L_0000000004130bc0, C4<0>, C4<0>;
+L_00000000041301b0 .functor OR 1, L_000000000412cc50, L_0000000003f8fee0, C4<0>, C4<0>;
+L_00000000041304c0 .functor AND 1, L_00000000041303e0, L_00000000041301b0, L_000000000412ff80, C4<1>;
+L_0000000004131020 .functor BUF 1, L_00000000041304c0, C4<0>, C4<0>, C4<0>;
+v0000000002c1a800_0 .net "A1", 0 0, L_0000000003f8fee0;  alias, 1 drivers
+v0000000002c19ea0_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000002c1a940_0 .net "B1", 0 0, L_0000000004130bc0;  alias, 1 drivers
+v0000000002c1a9e0_0 .net "B2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000002c1aa80_0 .net "C1", 0 0, L_000000000412ff80;  alias, 1 drivers
+L_0000000003ffc3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c18e60_0 .net8 "VGND", 0 0, L_0000000003ffc3d0;  1 drivers, strength-aware
+L_0000000003ffc0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c18960_0 .net8 "VNB", 0 0, L_0000000003ffc0c0;  1 drivers, strength-aware
+L_0000000003ffbf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1aee0_0 .net8 "VPB", 0 0, L_0000000003ffbf00;  1 drivers, strength-aware
+L_0000000003ffaca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c18d20_0 .net8 "VPWR", 0 0, L_0000000003ffaca0;  1 drivers, strength-aware
+v0000000002c19400_0 .net "X", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000002c19fe0_0 .net "and0_out_X", 0 0, L_00000000041304c0;  1 drivers
+v0000000002c18fa0_0 .net "or0_out", 0 0, L_00000000041303e0;  1 drivers
+v0000000002c18dc0_0 .net "or1_out", 0 0, L_00000000041301b0;  1 drivers
+S_0000000003a2bf90 .scope module, "_0650_" "sky130_fd_sc_hd__o221a_2" 3 1285, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000002c1b2a0_0 .net "A1", 0 0, L_0000000003f916a0;  1 drivers
+v0000000002c1b3e0_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v0000000002c1cc40_0 .net "B1", 0 0, L_0000000004130c30;  alias, 1 drivers
+v0000000002c1c9c0_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000002c1b480_0 .net "C1", 0 0, L_000000000412ff10;  alias, 1 drivers
+L_0000000003ffad10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b520_0 .net8 "VGND", 0 0, L_0000000003ffad10;  1 drivers, strength-aware
+L_0000000003ffc130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b5c0_0 .net8 "VNB", 0 0, L_0000000003ffc130;  1 drivers, strength-aware
+L_0000000003ffbf70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b7a0_0 .net8 "VPB", 0 0, L_0000000003ffbf70;  1 drivers, strength-aware
+L_0000000003ffc4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c6a0_0 .net8 "VPWR", 0 0, L_0000000003ffc4b0;  1 drivers, strength-aware
+v0000000002c1bde0_0 .net "X", 0 0, L_0000000004130530;  alias, 1 drivers
+S_0000000003a2cb90 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a2bf90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004130220 .functor OR 1, L_000000000412c1d0, L_0000000004130c30, C4<0>, C4<0>;
+L_0000000004130b50 .functor OR 1, L_0000000004127a80, L_0000000003f916a0, C4<0>, C4<0>;
+L_0000000004130610 .functor AND 1, L_0000000004130220, L_0000000004130b50, L_000000000412ff10, C4<1>;
+L_0000000004130530 .functor BUF 1, L_0000000004130610, C4<0>, C4<0>, C4<0>;
+v0000000002c19c20_0 .net "A1", 0 0, L_0000000003f916a0;  alias, 1 drivers
+v0000000002c19cc0_0 .net "A2", 0 0, L_0000000004127a80;  alias, 1 drivers
+v0000000002c19d60_0 .net "B1", 0 0, L_0000000004130c30;  alias, 1 drivers
+v0000000002c1a080_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000002c1a120_0 .net "C1", 0 0, L_000000000412ff10;  alias, 1 drivers
+L_0000000003ffbfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c920_0 .net8 "VGND", 0 0, L_0000000003ffbfe0;  1 drivers, strength-aware
+L_0000000003ffb870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1ce20_0 .net8 "VNB", 0 0, L_0000000003ffb870;  1 drivers, strength-aware
+L_0000000003ffb250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1bf20_0 .net8 "VPB", 0 0, L_0000000003ffb250;  1 drivers, strength-aware
+L_0000000003ffc520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c740_0 .net8 "VPWR", 0 0, L_0000000003ffc520;  1 drivers, strength-aware
+v0000000002c1b700_0 .net "X", 0 0, L_0000000004130530;  alias, 1 drivers
+v0000000002c1cec0_0 .net "and0_out_X", 0 0, L_0000000004130610;  1 drivers
+v0000000002c1b660_0 .net "or0_out", 0 0, L_0000000004130220;  1 drivers
+v0000000002c1b840_0 .net "or1_out", 0 0, L_0000000004130b50;  1 drivers
+S_0000000003a2bc90 .scope module, "_0651_" "sky130_fd_sc_hd__nor2_2" 3 1293, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c1c880_0 .net "A", 0 0, L_000000000412f9d0;  alias, 1 drivers
+v0000000002c1cba0_0 .net "B", 0 0, L_0000000004130530;  alias, 1 drivers
+L_0000000003ffb410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c060_0 .net8 "VGND", 0 0, L_0000000003ffb410;  1 drivers, strength-aware
+L_0000000003ffbb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c100_0 .net8 "VNB", 0 0, L_0000000003ffbb80;  1 drivers, strength-aware
+L_0000000003ffad80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b0c0_0 .net8 "VPB", 0 0, L_0000000003ffad80;  1 drivers, strength-aware
+L_0000000003ffb950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1be80_0 .net8 "VPWR", 0 0, L_0000000003ffb950;  1 drivers, strength-aware
+v0000000002c1cce0_0 .net "Y", 0 0, L_0000000004130680;  alias, 1 drivers
+S_0000000003a2b210 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2bc90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041305a0 .functor NOR 1, L_000000000412f9d0, L_0000000004130530, C4<0>, C4<0>;
+L_0000000004130680 .functor BUF 1, L_00000000041305a0, C4<0>, C4<0>, C4<0>;
+v0000000002c1ca60_0 .net "A", 0 0, L_000000000412f9d0;  alias, 1 drivers
+v0000000002c1c7e0_0 .net "B", 0 0, L_0000000004130530;  alias, 1 drivers
+L_0000000003ffc590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1ba20_0 .net8 "VGND", 0 0, L_0000000003ffc590;  1 drivers, strength-aware
+L_0000000003ffadf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b8e0_0 .net8 "VNB", 0 0, L_0000000003ffadf0;  1 drivers, strength-aware
+L_0000000003ffc1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b980_0 .net8 "VPB", 0 0, L_0000000003ffc1a0;  1 drivers, strength-aware
+L_0000000003ffae60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1cb00_0 .net8 "VPWR", 0 0, L_0000000003ffae60;  1 drivers, strength-aware
+v0000000002c1cf60_0 .net "Y", 0 0, L_0000000004130680;  alias, 1 drivers
+v0000000002c1c600_0 .net "nor0_out_Y", 0 0, L_00000000041305a0;  1 drivers
+S_0000000003a2ca10 .scope module, "_0652_" "sky130_fd_sc_hd__nor2_2" 3 1298, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002c1bca0_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000002c1c1a0_0 .net "B", 0 0, L_0000000004130680;  alias, 1 drivers
+L_0000000003ffba30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1bd40_0 .net8 "VGND", 0 0, L_0000000003ffba30;  1 drivers, strength-aware
+L_0000000003ffbb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c4c0_0 .net8 "VNB", 0 0, L_0000000003ffbb10;  1 drivers, strength-aware
+L_0000000003ffbc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b160_0 .net8 "VPB", 0 0, L_0000000003ffbc60;  1 drivers, strength-aware
+L_0000000003ffbcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1b200_0 .net8 "VPWR", 0 0, L_0000000003ffbcd0;  1 drivers, strength-aware
+v0000000002c1c240_0 .net "Y", 0 0, L_000000000412f570;  alias, 1 drivers
+S_0000000003a2c590 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2ca10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004130e60 .functor NOR 1, L_0000000004131020, L_0000000004130680, C4<0>, C4<0>;
+L_000000000412f570 .functor BUF 1, L_0000000004130e60, C4<0>, C4<0>, C4<0>;
+v0000000002c1bac0_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000002c1bc00_0 .net "B", 0 0, L_0000000004130680;  alias, 1 drivers
+L_0000000003ffbd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c560_0 .net8 "VGND", 0 0, L_0000000003ffbd40;  1 drivers, strength-aware
+L_0000000003ffe270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002c1c420_0 .net8 "VNB", 0 0, L_0000000003ffe270;  1 drivers, strength-aware
+L_0000000003ffce50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1bb60_0 .net8 "VPB", 0 0, L_0000000003ffce50;  1 drivers, strength-aware
+L_0000000003ffd400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002c1cd80_0 .net8 "VPWR", 0 0, L_0000000003ffd400;  1 drivers, strength-aware
+v0000000002c1b340_0 .net "Y", 0 0, L_000000000412f570;  alias, 1 drivers
+v0000000002c1bfc0_0 .net "nor0_out_Y", 0 0, L_0000000004130e60;  1 drivers
+S_0000000003a2b390 .scope module, "_0653_" "sky130_fd_sc_hd__or2_2" 3 1303, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000002bfe1a0_0 .net "A", 0 0, L_000000000412dd60;  alias, 1 drivers
+v0000000002bfde80_0 .net "B", 0 0, L_000000000412fdc0;  alias, 1 drivers
+L_0000000003ffd9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfe740_0 .net8 "VGND", 0 0, L_0000000003ffd9b0;  1 drivers, strength-aware
+L_0000000003ffe2e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd3e0_0 .net8 "VNB", 0 0, L_0000000003ffe2e0;  1 drivers, strength-aware
+L_0000000003ffdfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfdfc0_0 .net8 "VPB", 0 0, L_0000000003ffdfd0;  1 drivers, strength-aware
+L_0000000003ffd080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bff460_0 .net8 "VPWR", 0 0, L_0000000003ffd080;  1 drivers, strength-aware
+v0000000002bff000_0 .net "X", 0 0, L_0000000004130760;  alias, 1 drivers
+S_0000000003a2c110 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a2b390;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041306f0 .functor OR 1, L_000000000412fdc0, L_000000000412dd60, C4<0>, C4<0>;
+L_0000000004130760 .functor BUF 1, L_00000000041306f0, C4<0>, C4<0>, C4<0>;
+v0000000002c1c2e0_0 .net "A", 0 0, L_000000000412dd60;  alias, 1 drivers
+v0000000002c1c380_0 .net "B", 0 0, L_000000000412fdc0;  alias, 1 drivers
+L_0000000003ffdc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfe880_0 .net8 "VGND", 0 0, L_0000000003ffdc50;  1 drivers, strength-aware
+L_0000000003ffd6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bff6e0_0 .net8 "VNB", 0 0, L_0000000003ffd6a0;  1 drivers, strength-aware
+L_0000000003ffda90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfe380_0 .net8 "VPB", 0 0, L_0000000003ffda90;  1 drivers, strength-aware
+L_0000000003ffe190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd200_0 .net8 "VPWR", 0 0, L_0000000003ffe190;  1 drivers, strength-aware
+v0000000002bfd8e0_0 .net "X", 0 0, L_0000000004130760;  alias, 1 drivers
+v0000000002bff780_0 .net "or0_out_X", 0 0, L_00000000041306f0;  1 drivers
+S_0000000003a2c890 .scope module, "_0654_" "sky130_fd_sc_hd__o21a_2" 3 1308, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000002bfe9c0_0 .net "A1", 0 0, L_00000000041300d0;  alias, 1 drivers
+v0000000002bfe060_0 .net "A2", 0 0, L_000000000412f570;  alias, 1 drivers
+v0000000002bfe240_0 .net "B1", 0 0, L_0000000004130760;  alias, 1 drivers
+L_0000000003ffd550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd700_0 .net8 "VGND", 0 0, L_0000000003ffd550;  1 drivers, strength-aware
+L_0000000003ffc9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfec40_0 .net8 "VNB", 0 0, L_0000000003ffc9f0;  1 drivers, strength-aware
+L_0000000003ffcec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bff5a0_0 .net8 "VPB", 0 0, L_0000000003ffcec0;  1 drivers, strength-aware
+L_0000000003ffca60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfdb60_0 .net8 "VPWR", 0 0, L_0000000003ffca60;  1 drivers, strength-aware
+v0000000002bfdca0_0 .net "X", 0 0, L_0000000004131090;  alias, 1 drivers
+S_0000000003a2ce90 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a2c890;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000412fab0 .functor OR 1, L_000000000412f570, L_00000000041300d0, C4<0>, C4<0>;
+L_00000000041307d0 .functor AND 1, L_000000000412fab0, L_0000000004130760, C4<1>, C4<1>;
+L_0000000004131090 .functor BUF 1, L_00000000041307d0, C4<0>, C4<0>, C4<0>;
+v0000000002bfed80_0 .net "A1", 0 0, L_00000000041300d0;  alias, 1 drivers
+v0000000002bfeba0_0 .net "A2", 0 0, L_000000000412f570;  alias, 1 drivers
+v0000000002bfd980_0 .net "B1", 0 0, L_0000000004130760;  alias, 1 drivers
+L_0000000003ffd160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd660_0 .net8 "VGND", 0 0, L_0000000003ffd160;  1 drivers, strength-aware
+L_0000000003ffe430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bff820_0 .net8 "VNB", 0 0, L_0000000003ffe430;  1 drivers, strength-aware
+L_0000000003ffd7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfe100_0 .net8 "VPB", 0 0, L_0000000003ffd7f0;  1 drivers, strength-aware
+L_0000000003ffd710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd0c0_0 .net8 "VPWR", 0 0, L_0000000003ffd710;  1 drivers, strength-aware
+v0000000002bff500_0 .net "X", 0 0, L_0000000004131090;  alias, 1 drivers
+v0000000002bfea60_0 .net "and0_out_X", 0 0, L_00000000041307d0;  1 drivers
+v0000000002bfd160_0 .net "or0_out", 0 0, L_000000000412fab0;  1 drivers
+S_0000000003a2b090 .scope module, "_0655_" "sky130_fd_sc_hd__inv_2" 3 1314, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000002bfd2a0_0 .net "A", 0 0, L_0000000003f8fb20;  1 drivers
+L_0000000003ffe200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd340_0 .net8 "VGND", 0 0, L_0000000003ffe200;  1 drivers, strength-aware
+L_0000000003ffd470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfef60_0 .net8 "VNB", 0 0, L_0000000003ffd470;  1 drivers, strength-aware
+L_0000000003ffc8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfda20_0 .net8 "VPB", 0 0, L_0000000003ffc8a0;  1 drivers, strength-aware
+L_0000000003ffc910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd480_0 .net8 "VPWR", 0 0, L_0000000003ffc910;  1 drivers, strength-aware
+v0000000002bfe420_0 .net "Y", 0 0, L_000000000412f5e0;  alias, 1 drivers
+S_0000000003a30b20 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2b090;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004130ca0 .functor NOT 1, L_0000000003f8fb20, C4<0>, C4<0>, C4<0>;
+L_000000000412f5e0 .functor BUF 1, L_0000000004130ca0, C4<0>, C4<0>, C4<0>;
+v0000000002bfe2e0_0 .net "A", 0 0, L_0000000003f8fb20;  alias, 1 drivers
+L_0000000003ffdcc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bff320_0 .net8 "VGND", 0 0, L_0000000003ffdcc0;  1 drivers, strength-aware
+L_0000000003ffcd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfeec0_0 .net8 "VNB", 0 0, L_0000000003ffcd70;  1 drivers, strength-aware
+L_0000000003ffd630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bff640_0 .net8 "VPB", 0 0, L_0000000003ffd630;  1 drivers, strength-aware
+L_0000000003ffda20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfdac0_0 .net8 "VPWR", 0 0, L_0000000003ffda20;  1 drivers, strength-aware
+v0000000002bfece0_0 .net "Y", 0 0, L_000000000412f5e0;  alias, 1 drivers
+v0000000002bfee20_0 .net "not0_out_Y", 0 0, L_0000000004130ca0;  1 drivers
+S_0000000003a2f1a0 .scope module, "_0656_" "sky130_fd_sc_hd__a2bb2o_2" 3 1318, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000002bfdde0_0 .net "A1_N", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000002bfdf20_0 .net "A2_N", 0 0, L_0000000003f91b00;  1 drivers
+v0000000002bfe600_0 .net "B1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000002bfe7e0_0 .net "B2", 0 0, L_0000000003f91ba0;  1 drivers
+L_0000000003ffd4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bff140_0 .net8 "VGND", 0 0, L_0000000003ffd4e0;  1 drivers, strength-aware
+L_0000000003ffcc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfeb00_0 .net8 "VNB", 0 0, L_0000000003ffcc90;  1 drivers, strength-aware
+L_0000000003ffcc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bff280_0 .net8 "VPB", 0 0, L_0000000003ffcc20;  1 drivers, strength-aware
+L_0000000003ffcde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bff3c0_0 .net8 "VPWR", 0 0, L_0000000003ffcde0;  1 drivers, strength-aware
+v0000000003a35fe0_0 .net "X", 0 0, L_0000000004130990;  alias, 1 drivers
+S_0000000003a2de20 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a2f1a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004130840 .functor AND 1, L_0000000004126d60, L_0000000003f91ba0, C4<1>, C4<1>;
+L_0000000004130920 .functor NOR 1, L_0000000004126d60, L_0000000003f91b00, C4<0>, C4<0>;
+L_000000000412f650 .functor OR 1, L_0000000004130920, L_0000000004130840, C4<0>, C4<0>;
+L_0000000004130990 .functor BUF 1, L_000000000412f650, C4<0>, C4<0>, C4<0>;
+v0000000002bff1e0_0 .net "A1_N", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000002bff0a0_0 .net "A2_N", 0 0, L_0000000003f91b00;  alias, 1 drivers
+v0000000002bfd5c0_0 .net "B1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000002bfd7a0_0 .net "B2", 0 0, L_0000000003f91ba0;  alias, 1 drivers
+L_0000000003ffcbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd840_0 .net8 "VGND", 0 0, L_0000000003ffcbb0;  1 drivers, strength-aware
+L_0000000003ffd2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002bfd520_0 .net8 "VNB", 0 0, L_0000000003ffd2b0;  1 drivers, strength-aware
+L_0000000003ffe350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfe4c0_0 .net8 "VPB", 0 0, L_0000000003ffe350;  1 drivers, strength-aware
+L_0000000003ffe3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002bfdc00_0 .net8 "VPWR", 0 0, L_0000000003ffe3c0;  1 drivers, strength-aware
+v0000000002bfe920_0 .net "X", 0 0, L_0000000004130990;  alias, 1 drivers
+v0000000002bfe560_0 .net "and0_out", 0 0, L_0000000004130840;  1 drivers
+v0000000002bfdd40_0 .net "nor0_out", 0 0, L_0000000004130920;  1 drivers
+v0000000002bfe6a0_0 .net "or0_out_X", 0 0, L_000000000412f650;  1 drivers
+S_0000000003a31420 .scope module, "_0657_" "sky130_fd_sc_hd__a221o_2" 3 1325, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a37840_0 .net "A1", 0 0, L_000000000412f5e0;  alias, 1 drivers
+v0000000003a35b80_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a36bc0_0 .net "B1", 0 0, L_0000000003f8ff80;  1 drivers
+v0000000003a366c0_0 .net "B2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a370c0_0 .net "C1", 0 0, L_0000000004130990;  alias, 1 drivers
+L_0000000003ffc980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37480_0 .net8 "VGND", 0 0, L_0000000003ffc980;  1 drivers, strength-aware
+L_0000000003ffcad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a352c0_0 .net8 "VNB", 0 0, L_0000000003ffcad0;  1 drivers, strength-aware
+L_0000000003ffcd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a35d60_0 .net8 "VPB", 0 0, L_0000000003ffcd00;  1 drivers, strength-aware
+L_0000000003ffdb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a35ea0_0 .net8 "VPWR", 0 0, L_0000000003ffdb00;  1 drivers, strength-aware
+v0000000003a35ae0_0 .net "X", 0 0, L_000000000412f730;  alias, 1 drivers
+S_0000000003a327a0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a31420;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004130a00 .functor AND 1, L_0000000003f8ff80, L_000000000412cc50, C4<1>, C4<1>;
+L_000000000412f500 .functor AND 1, L_000000000412f5e0, L_0000000004130f40, C4<1>, C4<1>;
+L_0000000004130ed0 .functor OR 1, L_000000000412f500, L_0000000004130a00, L_0000000004130990, C4<0>;
+L_000000000412f730 .functor BUF 1, L_0000000004130ed0, C4<0>, C4<0>, C4<0>;
+v0000000003a36440_0 .net "A1", 0 0, L_000000000412f5e0;  alias, 1 drivers
+v0000000003a36300_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a37520_0 .net "B1", 0 0, L_0000000003f8ff80;  alias, 1 drivers
+v0000000003a35cc0_0 .net "B2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a36260_0 .net "C1", 0 0, L_0000000004130990;  alias, 1 drivers
+L_0000000003ffdd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a373e0_0 .net8 "VGND", 0 0, L_0000000003ffdd30;  1 drivers, strength-aware
+L_0000000003ffcfa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a35400_0 .net8 "VNB", 0 0, L_0000000003ffcfa0;  1 drivers, strength-aware
+L_0000000003ffcb40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a35e00_0 .net8 "VPB", 0 0, L_0000000003ffcb40;  1 drivers, strength-aware
+L_0000000003ffde10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a37660_0 .net8 "VPWR", 0 0, L_0000000003ffde10;  1 drivers, strength-aware
+v0000000003a36080_0 .net "X", 0 0, L_000000000412f730;  alias, 1 drivers
+v0000000003a36c60_0 .net "and0_out", 0 0, L_0000000004130a00;  1 drivers
+v0000000003a36e40_0 .net "and1_out", 0 0, L_000000000412f500;  1 drivers
+v0000000003a35c20_0 .net "or0_out_X", 0 0, L_0000000004130ed0;  1 drivers
+S_0000000003a32f20 .scope module, "_0658_" "sky130_fd_sc_hd__inv_2" 3 1333, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a37200_0 .net "A", 0 0, L_000000000412f730;  alias, 1 drivers
+L_0000000003ffcf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a35f40_0 .net8 "VGND", 0 0, L_0000000003ffcf30;  1 drivers, strength-aware
+L_0000000003ffd780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a36d00_0 .net8 "VNB", 0 0, L_0000000003ffd780;  1 drivers, strength-aware
+L_0000000003ffd860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a357c0_0 .net8 "VPB", 0 0, L_0000000003ffd860;  1 drivers, strength-aware
+L_0000000003ffdb70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a36120_0 .net8 "VPWR", 0 0, L_0000000003ffdb70;  1 drivers, strength-aware
+v0000000003a35680_0 .net "Y", 0 0, L_000000000412f7a0;  alias, 1 drivers
+S_0000000003a315a0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a32f20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004130a70 .functor NOT 1, L_000000000412f730, C4<0>, C4<0>, C4<0>;
+L_000000000412f7a0 .functor BUF 1, L_0000000004130a70, C4<0>, C4<0>, C4<0>;
+v0000000003a36760_0 .net "A", 0 0, L_000000000412f730;  alias, 1 drivers
+L_0000000003ffd010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37160_0 .net8 "VGND", 0 0, L_0000000003ffd010;  1 drivers, strength-aware
+L_0000000003ffd5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a36b20_0 .net8 "VNB", 0 0, L_0000000003ffd5c0;  1 drivers, strength-aware
+L_0000000003ffd0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a375c0_0 .net8 "VPB", 0 0, L_0000000003ffd0f0;  1 drivers, strength-aware
+L_0000000003ffd8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a35720_0 .net8 "VPWR", 0 0, L_0000000003ffd8d0;  1 drivers, strength-aware
+v0000000003a361c0_0 .net "Y", 0 0, L_000000000412f7a0;  alias, 1 drivers
+v0000000003a377a0_0 .net "not0_out_Y", 0 0, L_0000000004130a70;  1 drivers
+S_0000000003a30520 .scope module, "_0659_" "sky130_fd_sc_hd__o221a_2" 3 1337, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a35a40_0 .net "A1", 0 0, L_0000000003f900c0;  1 drivers
+v0000000003a35900_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a378e0_0 .net "B1", 0 0, L_000000000412f5e0;  alias, 1 drivers
+v0000000003a36800_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000003a368a0_0 .net "C1", 0 0, L_0000000004130990;  alias, 1 drivers
+L_0000000003ffd1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a35180_0 .net8 "VGND", 0 0, L_0000000003ffd1d0;  1 drivers, strength-aware
+L_0000000003ffdda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a35220_0 .net8 "VNB", 0 0, L_0000000003ffdda0;  1 drivers, strength-aware
+L_0000000003ffd940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a36ee0_0 .net8 "VPB", 0 0, L_0000000003ffd940;  1 drivers, strength-aware
+L_0000000003ffde80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a36940_0 .net8 "VPWR", 0 0, L_0000000003ffde80;  1 drivers, strength-aware
+v0000000003a355e0_0 .net "X", 0 0, L_000000000412f960;  alias, 1 drivers
+S_0000000003a2e2a0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a30520;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000412f8f0 .functor OR 1, L_000000000412c1d0, L_000000000412f5e0, C4<0>, C4<0>;
+L_0000000004130d10 .functor OR 1, L_000000000412d0b0, L_0000000003f900c0, C4<0>, C4<0>;
+L_0000000004130df0 .functor AND 1, L_000000000412f8f0, L_0000000004130d10, L_0000000004130990, C4<1>;
+L_000000000412f960 .functor BUF 1, L_0000000004130df0, C4<0>, C4<0>, C4<0>;
+v0000000003a35860_0 .net "A1", 0 0, L_0000000003f900c0;  alias, 1 drivers
+v0000000003a372a0_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a363a0_0 .net "B1", 0 0, L_000000000412f5e0;  alias, 1 drivers
+v0000000003a354a0_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000003a36da0_0 .net "C1", 0 0, L_0000000004130990;  alias, 1 drivers
+L_0000000003ffd240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a35540_0 .net8 "VGND", 0 0, L_0000000003ffd240;  1 drivers, strength-aware
+L_0000000003ffd320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a364e0_0 .net8 "VNB", 0 0, L_0000000003ffd320;  1 drivers, strength-aware
+L_0000000003ffdbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a35360_0 .net8 "VPB", 0 0, L_0000000003ffdbe0;  1 drivers, strength-aware
+L_0000000003ffdef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a37700_0 .net8 "VPWR", 0 0, L_0000000003ffdef0;  1 drivers, strength-aware
+v0000000003a36580_0 .net "X", 0 0, L_000000000412f960;  alias, 1 drivers
+v0000000003a36620_0 .net "and0_out_X", 0 0, L_0000000004130df0;  1 drivers
+v0000000003a36a80_0 .net "or0_out", 0 0, L_000000000412f8f0;  1 drivers
+v0000000003a37340_0 .net "or1_out", 0 0, L_0000000004130d10;  1 drivers
+S_0000000003a2f4a0 .scope module, "_0660_" "sky130_fd_sc_hd__nor2_2" 3 1345, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a37c00_0 .net "A", 0 0, L_000000000412f7a0;  alias, 1 drivers
+v0000000003a38600_0 .net "B", 0 0, L_000000000412f960;  alias, 1 drivers
+L_0000000003ffd390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a39e60_0 .net8 "VGND", 0 0, L_0000000003ffd390;  1 drivers, strength-aware
+L_0000000003ffdf60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a387e0_0 .net8 "VNB", 0 0, L_0000000003ffdf60;  1 drivers, strength-aware
+L_0000000003ffe040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a39460_0 .net8 "VPB", 0 0, L_0000000003ffe040;  1 drivers, strength-aware
+L_0000000003ffe0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a37ac0_0 .net8 "VPWR", 0 0, L_0000000003ffe0b0;  1 drivers, strength-aware
+v0000000003a39780_0 .net "Y", 0 0, L_000000000412fb90;  alias, 1 drivers
+S_0000000003a2db20 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2f4a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000412fb20 .functor NOR 1, L_000000000412f7a0, L_000000000412f960, C4<0>, C4<0>;
+L_000000000412fb90 .functor BUF 1, L_000000000412fb20, C4<0>, C4<0>, C4<0>;
+v0000000003a369e0_0 .net "A", 0 0, L_000000000412f7a0;  alias, 1 drivers
+v0000000003a36f80_0 .net "B", 0 0, L_000000000412f960;  alias, 1 drivers
+L_0000000003ffe120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37020_0 .net8 "VGND", 0 0, L_0000000003ffe120;  1 drivers, strength-aware
+L_0000000003fffaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a359a0_0 .net8 "VNB", 0 0, L_0000000003fffaf0;  1 drivers, strength-aware
+L_0000000003ffecf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a38ba0_0 .net8 "VPB", 0 0, L_0000000003ffecf0;  1 drivers, strength-aware
+L_0000000003fff700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a391e0_0 .net8 "VPWR", 0 0, L_0000000003fff700;  1 drivers, strength-aware
+v0000000003a37a20_0 .net "Y", 0 0, L_000000000412fb90;  alias, 1 drivers
+v0000000003a384c0_0 .net "nor0_out_Y", 0 0, L_000000000412fb20;  1 drivers
+S_0000000003a318a0 .scope module, "_0661_" "sky130_fd_sc_hd__inv_2" 3 1350, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a3a0e0_0 .net "A", 0 0, L_0000000003f91420;  1 drivers
+L_0000000003fff770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a386a0_0 .net8 "VGND", 0 0, L_0000000003fff770;  1 drivers, strength-aware
+L_0000000003ffedd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a39500_0 .net8 "VNB", 0 0, L_0000000003ffedd0;  1 drivers, strength-aware
+L_0000000003ffed60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a38f60_0 .net8 "VPB", 0 0, L_0000000003ffed60;  1 drivers, strength-aware
+L_0000000003fffa80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a38d80_0 .net8 "VPWR", 0 0, L_0000000003fffa80;  1 drivers, strength-aware
+v0000000003a39dc0_0 .net "Y", 0 0, L_000000000412fc70;  alias, 1 drivers
+S_0000000003a2e8a0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a318a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000412fc00 .functor NOT 1, L_0000000003f91420, C4<0>, C4<0>, C4<0>;
+L_000000000412fc70 .functor BUF 1, L_000000000412fc00, C4<0>, C4<0>, C4<0>;
+v0000000003a38ec0_0 .net "A", 0 0, L_0000000003f91420;  alias, 1 drivers
+L_0000000003ffec10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a39c80_0 .net8 "VGND", 0 0, L_0000000003ffec10;  1 drivers, strength-aware
+L_0000000003fffd90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a38740_0 .net8 "VNB", 0 0, L_0000000003fffd90;  1 drivers, strength-aware
+L_0000000003fff5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a38560_0 .net8 "VPB", 0 0, L_0000000003fff5b0;  1 drivers, strength-aware
+L_0000000003fffb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a39820_0 .net8 "VPWR", 0 0, L_0000000003fffb60;  1 drivers, strength-aware
+v0000000003a37b60_0 .net "Y", 0 0, L_000000000412fc70;  alias, 1 drivers
+v0000000003a39140_0 .net "not0_out_Y", 0 0, L_000000000412fc00;  1 drivers
+S_0000000003a32620 .scope module, "_0662_" "sky130_fd_sc_hd__a2bb2o_2" 3 1354, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a389c0_0 .net "A1_N", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a393c0_0 .net "A2_N", 0 0, L_0000000003f91740;  1 drivers
+v0000000003a39640_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a396e0_0 .net "B2", 0 0, L_0000000003f92d20;  1 drivers
+L_0000000003ffee40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37980_0 .net8 "VGND", 0 0, L_0000000003ffee40;  1 drivers, strength-aware
+L_0000000003ffeba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37de0_0 .net8 "VNB", 0 0, L_0000000003ffeba0;  1 drivers, strength-aware
+L_0000000003fffbd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a39d20_0 .net8 "VPB", 0 0, L_0000000003fffbd0;  1 drivers, strength-aware
+L_0000000003ffe6d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a37e80_0 .net8 "VPWR", 0 0, L_0000000003ffe6d0;  1 drivers, strength-aware
+v0000000003a37f20_0 .net "X", 0 0, L_0000000004131170;  alias, 1 drivers
+S_0000000003a2f7a0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a32620;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000412fce0 .functor AND 1, L_0000000004130140, L_0000000003f92d20, C4<1>, C4<1>;
+L_000000000412fd50 .functor NOR 1, L_0000000004130140, L_0000000003f91740, C4<0>, C4<0>;
+L_0000000004131330 .functor OR 1, L_000000000412fd50, L_000000000412fce0, C4<0>, C4<0>;
+L_0000000004131170 .functor BUF 1, L_0000000004131330, C4<0>, C4<0>, C4<0>;
+v0000000003a39280_0 .net "A1_N", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a398c0_0 .net "A2_N", 0 0, L_0000000003f91740;  alias, 1 drivers
+v0000000003a38060_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a395a0_0 .net "B2", 0 0, L_0000000003f92d20;  alias, 1 drivers
+L_0000000003fff000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a37ca0_0 .net8 "VGND", 0 0, L_0000000003fff000;  1 drivers, strength-aware
+L_0000000003fffc40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a38880_0 .net8 "VNB", 0 0, L_0000000003fffc40;  1 drivers, strength-aware
+L_0000000003ffeeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a39320_0 .net8 "VPB", 0 0, L_0000000003ffeeb0;  1 drivers, strength-aware
+L_0000000003ffef20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a38240_0 .net8 "VPWR", 0 0, L_0000000003ffef20;  1 drivers, strength-aware
+v0000000003a38920_0 .net "X", 0 0, L_0000000004131170;  alias, 1 drivers
+v0000000003a37d40_0 .net "and0_out", 0 0, L_000000000412fce0;  1 drivers
+v0000000003a38c40_0 .net "nor0_out", 0 0, L_000000000412fd50;  1 drivers
+v0000000003a38ce0_0 .net "or0_out_X", 0 0, L_0000000004131330;  1 drivers
+S_0000000003a30ca0 .scope module, "_0663_" "sky130_fd_sc_hd__o221a_2" 3 1361, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a39960_0 .net "A1", 0 0, L_0000000003f941c0;  1 drivers
+v0000000003a39a00_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a39b40_0 .net "B1", 0 0, L_000000000412fc70;  alias, 1 drivers
+v0000000003a39be0_0 .net "B2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a382e0_0 .net "C1", 0 0, L_0000000004131170;  alias, 1 drivers
+L_0000000003fff620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a38420_0 .net8 "VGND", 0 0, L_0000000003fff620;  1 drivers, strength-aware
+L_0000000003ffe970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b760_0 .net8 "VNB", 0 0, L_0000000003ffe970;  1 drivers, strength-aware
+L_0000000003ffffc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3bb20_0 .net8 "VPB", 0 0, L_0000000003ffffc0;  1 drivers, strength-aware
+L_0000000003ffe740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a900_0 .net8 "VPWR", 0 0, L_0000000003ffe740;  1 drivers, strength-aware
+v0000000003a3bd00_0 .net "X", 0 0, L_0000000004132c90;  alias, 1 drivers
+S_0000000003a31ba0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a30ca0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004132280 .functor OR 1, L_0000000004130f40, L_000000000412fc70, C4<0>, C4<0>;
+L_0000000004132910 .functor OR 1, L_000000000412cc50, L_0000000003f941c0, C4<0>, C4<0>;
+L_0000000004132980 .functor AND 1, L_0000000004132280, L_0000000004132910, L_0000000004131170, C4<1>;
+L_0000000004132c90 .functor BUF 1, L_0000000004132980, C4<0>, C4<0>, C4<0>;
+v0000000003a38e20_0 .net "A1", 0 0, L_0000000003f941c0;  alias, 1 drivers
+v0000000003a38380_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a39fa0_0 .net "B1", 0 0, L_000000000412fc70;  alias, 1 drivers
+v0000000003a39000_0 .net "B2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a3a040_0 .net "C1", 0 0, L_0000000004131170;  alias, 1 drivers
+L_0000000004000030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a38a60_0 .net8 "VGND", 0 0, L_0000000004000030;  1 drivers, strength-aware
+L_0000000003fff850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a390a0_0 .net8 "VNB", 0 0, L_0000000003fff850;  1 drivers, strength-aware
+L_0000000003fff2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a37fc0_0 .net8 "VPB", 0 0, L_0000000003fff2a0;  1 drivers, strength-aware
+L_0000000003fffcb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a39f00_0 .net8 "VPWR", 0 0, L_0000000003fffcb0;  1 drivers, strength-aware
+v0000000003a39aa0_0 .net "X", 0 0, L_0000000004132c90;  alias, 1 drivers
+v0000000003a38b00_0 .net "and0_out_X", 0 0, L_0000000004132980;  1 drivers
+v0000000003a38100_0 .net "or0_out", 0 0, L_0000000004132280;  1 drivers
+v0000000003a381a0_0 .net "or1_out", 0 0, L_0000000004132910;  1 drivers
+S_0000000003a30e20 .scope module, "_0664_" "sky130_fd_sc_hd__and2_2" 3 1369, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a3b440_0 .net "A", 0 0, L_000000000412fb90;  alias, 1 drivers
+v0000000003a3bee0_0 .net "B", 0 0, L_0000000004132c90;  alias, 1 drivers
+L_0000000003fff0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ab80_0 .net8 "VGND", 0 0, L_0000000003fff0e0;  1 drivers, strength-aware
+L_0000000003ffeac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c7a0_0 .net8 "VNB", 0 0, L_0000000003ffeac0;  1 drivers, strength-aware
+L_0000000003ffe660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a9a0_0 .net8 "VPB", 0 0, L_0000000003ffe660;  1 drivers, strength-aware
+L_0000000003ffef90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c840_0 .net8 "VPWR", 0 0, L_0000000003ffef90;  1 drivers, strength-aware
+v0000000003a3a680_0 .net "X", 0 0, L_00000000041311e0;  alias, 1 drivers
+S_0000000003a2f320 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a30e20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004131950 .functor AND 1, L_000000000412fb90, L_0000000004132c90, C4<1>, C4<1>;
+L_00000000041311e0 .functor BUF 1, L_0000000004131950, C4<0>, C4<0>, C4<0>;
+v0000000003a3ae00_0 .net "A", 0 0, L_000000000412fb90;  alias, 1 drivers
+v0000000003a3c480_0 .net "B", 0 0, L_0000000004132c90;  alias, 1 drivers
+L_0000000003ffe4a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b4e0_0 .net8 "VGND", 0 0, L_0000000003ffe4a0;  1 drivers, strength-aware
+L_0000000003fff3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b120_0 .net8 "VNB", 0 0, L_0000000003fff3f0;  1 drivers, strength-aware
+L_0000000003fff310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b580_0 .net8 "VPB", 0 0, L_0000000003fff310;  1 drivers, strength-aware
+L_0000000003fffe00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ad60_0 .net8 "VPWR", 0 0, L_0000000003fffe00;  1 drivers, strength-aware
+v0000000003a3ba80_0 .net "X", 0 0, L_00000000041311e0;  alias, 1 drivers
+v0000000003a3a860_0 .net "and0_out_X", 0 0, L_0000000004131950;  1 drivers
+S_0000000003a2d820 .scope module, "_0665_" "sky130_fd_sc_hd__a221oi_2" 3 1374, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a3a220_0 .net "A1", 0 0, L_0000000004130bc0;  alias, 1 drivers
+v0000000003a3c160_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a3be40_0 .net "B1", 0 0, L_0000000003f94260;  1 drivers
+v0000000003a3bbc0_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a3aea0_0 .net "C1", 0 0, L_000000000412ff80;  alias, 1 drivers
+L_0000000003fff070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3bf80_0 .net8 "VGND", 0 0, L_0000000003fff070;  1 drivers, strength-aware
+L_0000000003ffe510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3afe0_0 .net8 "VNB", 0 0, L_0000000003ffe510;  1 drivers, strength-aware
+L_0000000003ffe580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b8a0_0 .net8 "VPB", 0 0, L_0000000003ffe580;  1 drivers, strength-aware
+L_0000000003fff8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b620_0 .net8 "VPWR", 0 0, L_0000000003fff8c0;  1 drivers, strength-aware
+v0000000003a3c020_0 .net "Y", 0 0, L_0000000004131cd0;  alias, 1 drivers
+S_0000000003a32020 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a2d820;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041329f0 .functor AND 1, L_0000000003f94260, L_0000000004127930, C4<1>, C4<1>;
+L_00000000041319c0 .functor AND 1, L_0000000004130bc0, L_0000000004125860, C4<1>, C4<1>;
+L_0000000004131100 .functor NOR 1, L_00000000041329f0, L_000000000412ff80, L_00000000041319c0, C4<0>;
+L_0000000004131cd0 .functor BUF 1, L_0000000004131100, C4<0>, C4<0>, C4<0>;
+v0000000003a3b6c0_0 .net "A1", 0 0, L_0000000004130bc0;  alias, 1 drivers
+v0000000003a3a7c0_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a3aa40_0 .net "B1", 0 0, L_0000000003f94260;  alias, 1 drivers
+v0000000003a3c660_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a3c0c0_0 .net "C1", 0 0, L_000000000412ff80;  alias, 1 drivers
+L_0000000003ffe9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c8e0_0 .net8 "VGND", 0 0, L_0000000003ffe9e0;  1 drivers, strength-aware
+L_0000000003fff230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b9e0_0 .net8 "VNB", 0 0, L_0000000003fff230;  1 drivers, strength-aware
+L_0000000003fff690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3bc60_0 .net8 "VPB", 0 0, L_0000000003fff690;  1 drivers, strength-aware
+L_0000000003fff150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3bda0_0 .net8 "VPWR", 0 0, L_0000000003fff150;  1 drivers, strength-aware
+v0000000003a3b800_0 .net "Y", 0 0, L_0000000004131cd0;  alias, 1 drivers
+v0000000003a3a180_0 .net "and0_out", 0 0, L_00000000041329f0;  1 drivers
+v0000000003a3aae0_0 .net "and1_out", 0 0, L_00000000041319c0;  1 drivers
+v0000000003a3b1c0_0 .net "nor0_out_Y", 0 0, L_0000000004131100;  1 drivers
+S_0000000003a31720 .scope module, "_0666_" "sky130_fd_sc_hd__or2_2" 3 1382, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a3acc0_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003a3c3e0_0 .net "B", 0 0, L_0000000004131cd0;  alias, 1 drivers
+L_0000000003fffa10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b260_0 .net8 "VGND", 0 0, L_0000000003fffa10;  1 drivers, strength-aware
+L_0000000003ffec80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b300_0 .net8 "VNB", 0 0, L_0000000003ffec80;  1 drivers, strength-aware
+L_0000000003ffe7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c520_0 .net8 "VPB", 0 0, L_0000000003ffe7b0;  1 drivers, strength-aware
+L_0000000003fff1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b940_0 .net8 "VPWR", 0 0, L_0000000003fff1c0;  1 drivers, strength-aware
+v0000000003a3b3a0_0 .net "X", 0 0, L_0000000004131e20;  alias, 1 drivers
+S_0000000003a2d9a0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a31720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004132830 .functor OR 1, L_0000000004131cd0, L_0000000004131020, C4<0>, C4<0>;
+L_0000000004131e20 .functor BUF 1, L_0000000004132830, C4<0>, C4<0>, C4<0>;
+v0000000003a3c700_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003a3ac20_0 .net "B", 0 0, L_0000000004131cd0;  alias, 1 drivers
+L_0000000003fff380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c200_0 .net8 "VGND", 0 0, L_0000000003fff380;  1 drivers, strength-aware
+L_0000000003fff460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3af40_0 .net8 "VNB", 0 0, L_0000000003fff460;  1 drivers, strength-aware
+L_0000000003fff4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a2c0_0 .net8 "VPB", 0 0, L_0000000003fff4d0;  1 drivers, strength-aware
+L_0000000003ffeb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3b080_0 .net8 "VPWR", 0 0, L_0000000003ffeb30;  1 drivers, strength-aware
+v0000000003a3c2a0_0 .net "X", 0 0, L_0000000004131e20;  alias, 1 drivers
+v0000000003a3c340_0 .net "or0_out_X", 0 0, L_0000000004132830;  1 drivers
+S_0000000003a31ea0 .scope module, "_0667_" "sky130_fd_sc_hd__inv_2" 3 1387, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a3e640_0 .net "A", 0 0, L_0000000004131e20;  alias, 1 drivers
+L_0000000003fff540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ed20_0 .net8 "VGND", 0 0, L_0000000003fff540;  1 drivers, strength-aware
+L_0000000003fff7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f0e0_0 .net8 "VNB", 0 0, L_0000000003fff7e0;  1 drivers, strength-aware
+L_0000000003fff930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3efa0_0 .net8 "VPB", 0 0, L_0000000003fff930;  1 drivers, strength-aware
+L_0000000003fffd20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3dec0_0 .net8 "VPWR", 0 0, L_0000000003fffd20;  1 drivers, strength-aware
+v0000000003a3e8c0_0 .net "Y", 0 0, L_0000000004132ad0;  alias, 1 drivers
+S_0000000003a2e720 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a31ea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004132a60 .functor NOT 1, L_0000000004131e20, C4<0>, C4<0>, C4<0>;
+L_0000000004132ad0 .functor BUF 1, L_0000000004132a60, C4<0>, C4<0>, C4<0>;
+v0000000003a3a360_0 .net "A", 0 0, L_0000000004131e20;  alias, 1 drivers
+L_0000000003fff9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3c5c0_0 .net8 "VGND", 0 0, L_0000000003fff9a0;  1 drivers, strength-aware
+L_0000000003fffe70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a400_0 .net8 "VNB", 0 0, L_0000000003fffe70;  1 drivers, strength-aware
+L_0000000003ffff50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a4a0_0 .net8 "VPB", 0 0, L_0000000003ffff50;  1 drivers, strength-aware
+L_0000000003fffee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3a540_0 .net8 "VPWR", 0 0, L_0000000003fffee0;  1 drivers, strength-aware
+v0000000003a3a5e0_0 .net "Y", 0 0, L_0000000004132ad0;  alias, 1 drivers
+v0000000003a3a720_0 .net "not0_out_Y", 0 0, L_0000000004132a60;  1 drivers
+S_0000000003a31120 .scope module, "_0668_" "sky130_fd_sc_hd__o21ai_2" 3 1391, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a3f040_0 .net "A1", 0 0, L_000000000412f7a0;  alias, 1 drivers
+v0000000003a3dc40_0 .net "A2", 0 0, L_00000000041311e0;  alias, 1 drivers
+v0000000003a3e6e0_0 .net "B1", 0 0, L_0000000004132ad0;  alias, 1 drivers
+L_0000000003ffe5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d380_0 .net8 "VGND", 0 0, L_0000000003ffe5f0;  1 drivers, strength-aware
+L_0000000003ffe820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d6a0_0 .net8 "VNB", 0 0, L_0000000003ffe820;  1 drivers, strength-aware
+L_0000000003ffe890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d100_0 .net8 "VPB", 0 0, L_0000000003ffe890;  1 drivers, strength-aware
+L_0000000003ffe900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d2e0_0 .net8 "VPWR", 0 0, L_0000000003ffe900;  1 drivers, strength-aware
+v0000000003a3da60_0 .net "Y", 0 0, L_0000000004132bb0;  alias, 1 drivers
+S_0000000003a30fa0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a31120;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004131720 .functor OR 1, L_00000000041311e0, L_000000000412f7a0, C4<0>, C4<0>;
+L_0000000004131480 .functor NAND 1, L_0000000004132ad0, L_0000000004131720, C4<1>, C4<1>;
+L_0000000004132bb0 .functor BUF 1, L_0000000004131480, C4<0>, C4<0>, C4<0>;
+v0000000003a3d240_0 .net "A1", 0 0, L_000000000412f7a0;  alias, 1 drivers
+v0000000003a3d740_0 .net "A2", 0 0, L_00000000041311e0;  alias, 1 drivers
+v0000000003a3c980_0 .net "B1", 0 0, L_0000000004132ad0;  alias, 1 drivers
+L_0000000003ffea50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3cb60_0 .net8 "VGND", 0 0, L_0000000003ffea50;  1 drivers, strength-aware
+L_0000000004000570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ec80_0 .net8 "VNB", 0 0, L_0000000004000570;  1 drivers, strength-aware
+L_0000000004001920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3dce0_0 .net8 "VPB", 0 0, L_0000000004001920;  1 drivers, strength-aware
+L_0000000004000340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d880_0 .net8 "VPWR", 0 0, L_0000000004000340;  1 drivers, strength-aware
+v0000000003a3e280_0 .net "Y", 0 0, L_0000000004132bb0;  alias, 1 drivers
+v0000000003a3e960_0 .net "nand0_out_Y", 0 0, L_0000000004131480;  1 drivers
+v0000000003a3e140_0 .net "or0_out", 0 0, L_0000000004131720;  1 drivers
+S_0000000003a2dca0 .scope module, "_0669_" "sky130_fd_sc_hd__and2_2" 3 1397, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a3ca20_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003a3d1a0_0 .net "B", 0 0, L_0000000004130680;  alias, 1 drivers
+L_0000000004000f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d9c0_0 .net8 "VGND", 0 0, L_0000000004000f80;  1 drivers, strength-aware
+L_0000000004001a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ef00_0 .net8 "VNB", 0 0, L_0000000004001a00;  1 drivers, strength-aware
+L_0000000004000b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3edc0_0 .net8 "VPB", 0 0, L_0000000004000b20;  1 drivers, strength-aware
+L_0000000004001990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d7e0_0 .net8 "VPWR", 0 0, L_0000000004001990;  1 drivers, strength-aware
+v0000000003a3ea00_0 .net "X", 0 0, L_0000000004131790;  alias, 1 drivers
+S_0000000003a321a0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a2dca0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041326e0 .functor AND 1, L_0000000004131020, L_0000000004130680, C4<1>, C4<1>;
+L_0000000004131790 .functor BUF 1, L_00000000041326e0, C4<0>, C4<0>, C4<0>;
+v0000000003a3df60_0 .net "A", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003a3ebe0_0 .net "B", 0 0, L_0000000004130680;  alias, 1 drivers
+L_0000000004001610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d060_0 .net8 "VGND", 0 0, L_0000000004001610;  1 drivers, strength-aware
+L_00000000040015a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3ee60_0 .net8 "VNB", 0 0, L_00000000040015a0;  1 drivers, strength-aware
+L_00000000040018b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3db00_0 .net8 "VPB", 0 0, L_00000000040018b0;  1 drivers, strength-aware
+L_00000000040017d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e780_0 .net8 "VPWR", 0 0, L_00000000040017d0;  1 drivers, strength-aware
+v0000000003a3dba0_0 .net "X", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003a3dd80_0 .net "and0_out_X", 0 0, L_00000000041326e0;  1 drivers
+S_0000000003a312a0 .scope module, "_0670_" "sky130_fd_sc_hd__o21ai_2" 3 1402, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a3e820_0 .net "A1", 0 0, L_000000000412f9d0;  alias, 1 drivers
+v0000000003a3eaa0_0 .net "A2", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003a3cca0_0 .net "B1", 0 0, L_000000000412df90;  alias, 1 drivers
+L_0000000004000a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d920_0 .net8 "VGND", 0 0, L_0000000004000a40;  1 drivers, strength-aware
+L_0000000004000c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e460_0 .net8 "VNB", 0 0, L_0000000004000c00;  1 drivers, strength-aware
+L_0000000004000ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3cd40_0 .net8 "VPB", 0 0, L_0000000004000ea0;  1 drivers, strength-aware
+L_0000000004001450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3eb40_0 .net8 "VPWR", 0 0, L_0000000004001450;  1 drivers, strength-aware
+v0000000003a3cde0_0 .net "Y", 0 0, L_0000000004131250;  alias, 1 drivers
+S_0000000003a2f620 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a312a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004132670 .functor OR 1, L_0000000004131790, L_000000000412f9d0, C4<0>, C4<0>;
+L_0000000004132050 .functor NAND 1, L_000000000412df90, L_0000000004132670, C4<1>, C4<1>;
+L_0000000004131250 .functor BUF 1, L_0000000004132050, C4<0>, C4<0>, C4<0>;
+v0000000003a3de20_0 .net "A1", 0 0, L_000000000412f9d0;  alias, 1 drivers
+v0000000003a3cac0_0 .net "A2", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003a3e5a0_0 .net "B1", 0 0, L_000000000412df90;  alias, 1 drivers
+L_0000000004001a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e1e0_0 .net8 "VGND", 0 0, L_0000000004001a70;  1 drivers, strength-aware
+L_0000000004000650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e320_0 .net8 "VNB", 0 0, L_0000000004000650;  1 drivers, strength-aware
+L_0000000004000c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e000_0 .net8 "VPB", 0 0, L_0000000004000c70;  1 drivers, strength-aware
+L_00000000040011b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3e0a0_0 .net8 "VPWR", 0 0, L_00000000040011b0;  1 drivers, strength-aware
+v0000000003a3e3c0_0 .net "Y", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003a3cc00_0 .net "nand0_out_Y", 0 0, L_0000000004132050;  1 drivers
+v0000000003a3d4c0_0 .net "or0_out", 0 0, L_0000000004132670;  1 drivers
+S_0000000003a2eba0 .scope module, "_0671_" "sky130_fd_sc_hd__o21ai_2" 3 1408, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a410c0_0 .net "A1", 0 0, L_0000000004131090;  alias, 1 drivers
+v0000000003a415c0_0 .net "A2", 0 0, L_0000000004132bb0;  alias, 1 drivers
+v0000000003a40300_0 .net "B1", 0 0, L_0000000004131250;  alias, 1 drivers
+L_0000000004001ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41520_0 .net8 "VGND", 0 0, L_0000000004001ae0;  1 drivers, strength-aware
+L_0000000004001840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f720_0 .net8 "VNB", 0 0, L_0000000004001840;  1 drivers, strength-aware
+L_0000000004000880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a401c0_0 .net8 "VPB", 0 0, L_0000000004000880;  1 drivers, strength-aware
+L_00000000040014c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a417a0_0 .net8 "VPWR", 0 0, L_00000000040014c0;  1 drivers, strength-aware
+v0000000003a406c0_0 .net "Y", 0 0, L_00000000041312c0;  alias, 1 drivers
+S_0000000003a306a0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a2eba0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004131f70 .functor OR 1, L_0000000004132bb0, L_0000000004131090, C4<0>, C4<0>;
+L_00000000041322f0 .functor NAND 1, L_0000000004131250, L_0000000004131f70, C4<1>, C4<1>;
+L_00000000041312c0 .functor BUF 1, L_00000000041322f0, C4<0>, C4<0>, C4<0>;
+v0000000003a3ce80_0 .net "A1", 0 0, L_0000000004131090;  alias, 1 drivers
+v0000000003a3e500_0 .net "A2", 0 0, L_0000000004132bb0;  alias, 1 drivers
+v0000000003a3d560_0 .net "B1", 0 0, L_0000000004131250;  alias, 1 drivers
+L_0000000004000f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d420_0 .net8 "VGND", 0 0, L_0000000004000f10;  1 drivers, strength-aware
+L_0000000004001290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3cf20_0 .net8 "VNB", 0 0, L_0000000004001290;  1 drivers, strength-aware
+L_0000000004001b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3cfc0_0 .net8 "VPB", 0 0, L_0000000004001b50;  1 drivers, strength-aware
+L_0000000004000d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3d600_0 .net8 "VPWR", 0 0, L_0000000004000d50;  1 drivers, strength-aware
+v0000000003a418e0_0 .net "Y", 0 0, L_00000000041312c0;  alias, 1 drivers
+v0000000003a3f2c0_0 .net "nand0_out_Y", 0 0, L_00000000041322f0;  1 drivers
+v0000000003a41020_0 .net "or0_out", 0 0, L_0000000004131f70;  1 drivers
+S_0000000003a2e120 .scope module, "_0672_" "sky130_fd_sc_hd__a221oi_2" 3 1414, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a3ff40_0 .net "A1", 0 0, L_000000000412fc70;  alias, 1 drivers
+v0000000003a3f180_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a41160_0 .net "B1", 0 0, L_0000000003f92460;  1 drivers
+v0000000003a40a80_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a3fd60_0 .net "C1", 0 0, L_0000000004131170;  alias, 1 drivers
+L_00000000040001f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3fea0_0 .net8 "VGND", 0 0, L_00000000040001f0;  1 drivers, strength-aware
+L_0000000004001bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a40bc0_0 .net8 "VNB", 0 0, L_0000000004001bc0;  1 drivers, strength-aware
+L_0000000004001300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a40120_0 .net8 "VPB", 0 0, L_0000000004001300;  1 drivers, strength-aware
+L_0000000004001680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a40800_0 .net8 "VPWR", 0 0, L_0000000004001680;  1 drivers, strength-aware
+v0000000003a3f4a0_0 .net "Y", 0 0, L_0000000004132360;  alias, 1 drivers
+S_0000000003a2dfa0 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a2e120;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004131800 .functor AND 1, L_0000000003f92460, L_0000000004127930, C4<1>, C4<1>;
+L_0000000004131b10 .functor AND 1, L_000000000412fc70, L_0000000004125860, C4<1>, C4<1>;
+L_0000000004131b80 .functor NOR 1, L_0000000004131800, L_0000000004131170, L_0000000004131b10, C4<0>;
+L_0000000004132360 .functor BUF 1, L_0000000004131b80, C4<0>, C4<0>, C4<0>;
+v0000000003a3f680_0 .net "A1", 0 0, L_000000000412fc70;  alias, 1 drivers
+v0000000003a40080_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a3fcc0_0 .net "B1", 0 0, L_0000000003f92460;  alias, 1 drivers
+v0000000003a3ffe0_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a40d00_0 .net "C1", 0 0, L_0000000004131170;  alias, 1 drivers
+L_0000000004000ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a40da0_0 .net8 "VGND", 0 0, L_0000000004000ff0;  1 drivers, strength-aware
+L_0000000004001060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41200_0 .net8 "VNB", 0 0, L_0000000004001060;  1 drivers, strength-aware
+L_0000000004000b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a403a0_0 .net8 "VPB", 0 0, L_0000000004000b90;  1 drivers, strength-aware
+L_00000000040008f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a409e0_0 .net8 "VPWR", 0 0, L_00000000040008f0;  1 drivers, strength-aware
+v0000000003a3fa40_0 .net "Y", 0 0, L_0000000004132360;  alias, 1 drivers
+v0000000003a40760_0 .net "and0_out", 0 0, L_0000000004131800;  1 drivers
+v0000000003a41840_0 .net "and1_out", 0 0, L_0000000004131b10;  1 drivers
+v0000000003a3f860_0 .net "nor0_out_Y", 0 0, L_0000000004131b80;  1 drivers
+S_0000000003a31a20 .scope module, "_0673_" "sky130_fd_sc_hd__or2_2" 3 1422, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a40580_0 .net "A", 0 0, L_0000000004132c90;  alias, 1 drivers
+v0000000003a3f7c0_0 .net "B", 0 0, L_0000000004132360;  alias, 1 drivers
+L_0000000004001370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a40e40_0 .net8 "VGND", 0 0, L_0000000004001370;  1 drivers, strength-aware
+L_00000000040002d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f220_0 .net8 "VNB", 0 0, L_00000000040002d0;  1 drivers, strength-aware
+L_0000000004001760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3fb80_0 .net8 "VPB", 0 0, L_0000000004001760;  1 drivers, strength-aware
+L_00000000040013e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a408a0_0 .net8 "VPWR", 0 0, L_00000000040013e0;  1 drivers, strength-aware
+v0000000003a40940_0 .net "X", 0 0, L_00000000041315d0;  alias, 1 drivers
+S_0000000003a2fda0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a31a20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004131f00 .functor OR 1, L_0000000004132360, L_0000000004132c90, C4<0>, C4<0>;
+L_00000000041315d0 .functor BUF 1, L_0000000004131f00, C4<0>, C4<0>, C4<0>;
+v0000000003a41660_0 .net "A", 0 0, L_0000000004132c90;  alias, 1 drivers
+v0000000003a3fe00_0 .net "B", 0 0, L_0000000004132360;  alias, 1 drivers
+L_0000000004001530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a40260_0 .net8 "VGND", 0 0, L_0000000004001530;  1 drivers, strength-aware
+L_00000000040006c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f400_0 .net8 "VNB", 0 0, L_00000000040006c0;  1 drivers, strength-aware
+L_0000000004000730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a40440_0 .net8 "VPB", 0 0, L_0000000004000730;  1 drivers, strength-aware
+L_00000000040010d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a413e0_0 .net8 "VPWR", 0 0, L_00000000040010d0;  1 drivers, strength-aware
+v0000000003a404e0_0 .net "X", 0 0, L_00000000041315d0;  alias, 1 drivers
+v0000000003a40c60_0 .net "or0_out_X", 0 0, L_0000000004131f00;  1 drivers
+S_0000000003a2f920 .scope module, "_0674_" "sky130_fd_sc_hd__inv_2" 3 1427, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a40f80_0 .net "A", 0 0, L_00000000041315d0;  alias, 1 drivers
+L_0000000004000420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41340_0 .net8 "VGND", 0 0, L_0000000004000420;  1 drivers, strength-aware
+L_0000000004000ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f9a0_0 .net8 "VNB", 0 0, L_0000000004000ce0;  1 drivers, strength-aware
+L_0000000004000dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a41700_0 .net8 "VPB", 0 0, L_0000000004000dc0;  1 drivers, strength-aware
+L_00000000040016f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f540_0 .net8 "VPWR", 0 0, L_00000000040016f0;  1 drivers, strength-aware
+v0000000003a3f5e0_0 .net "Y", 0 0, L_0000000004131bf0;  alias, 1 drivers
+S_0000000003a2e420 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2f920;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004131a30 .functor NOT 1, L_00000000041315d0, C4<0>, C4<0>, C4<0>;
+L_0000000004131bf0 .functor BUF 1, L_0000000004131a30, C4<0>, C4<0>, C4<0>;
+v0000000003a41480_0 .net "A", 0 0, L_00000000041315d0;  alias, 1 drivers
+L_0000000004001c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f900_0 .net8 "VGND", 0 0, L_0000000004001c30;  1 drivers, strength-aware
+L_00000000040000a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3f360_0 .net8 "VNB", 0 0, L_00000000040000a0;  1 drivers, strength-aware
+L_00000000040003b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a40620_0 .net8 "VPB", 0 0, L_00000000040003b0;  1 drivers, strength-aware
+L_0000000004000110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a412a0_0 .net8 "VPWR", 0 0, L_0000000004000110;  1 drivers, strength-aware
+v0000000003a40b20_0 .net "Y", 0 0, L_0000000004131bf0;  alias, 1 drivers
+v0000000003a40ee0_0 .net "not0_out_Y", 0 0, L_0000000004131a30;  1 drivers
+S_0000000003a2e5a0 .scope module, "_0675_" "sky130_fd_sc_hd__inv_2" 3 1431, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a43820_0 .net "A", 0 0, L_0000000003f93b80;  1 drivers
+L_0000000004000180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a43780_0 .net8 "VGND", 0 0, L_0000000004000180;  1 drivers, strength-aware
+L_0000000004000e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a433c0_0 .net8 "VNB", 0 0, L_0000000004000e30;  1 drivers, strength-aware
+L_0000000004000490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42ce0_0 .net8 "VPB", 0 0, L_0000000004000490;  1 drivers, strength-aware
+L_00000000040007a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a41b60_0 .net8 "VPWR", 0 0, L_00000000040007a0;  1 drivers, strength-aware
+v0000000003a41d40_0 .net "Y", 0 0, L_00000000041327c0;  alias, 1 drivers
+S_0000000003a2d220 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2e5a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004131aa0 .functor NOT 1, L_0000000003f93b80, C4<0>, C4<0>, C4<0>;
+L_00000000041327c0 .functor BUF 1, L_0000000004131aa0, C4<0>, C4<0>, C4<0>;
+v0000000003a3fae0_0 .net "A", 0 0, L_0000000003f93b80;  alias, 1 drivers
+L_0000000004000260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a3fc20_0 .net8 "VGND", 0 0, L_0000000004000260;  1 drivers, strength-aware
+L_00000000040009d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a43d20_0 .net8 "VNB", 0 0, L_00000000040009d0;  1 drivers, strength-aware
+L_0000000004000500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42740_0 .net8 "VPB", 0 0, L_0000000004000500;  1 drivers, strength-aware
+L_00000000040005e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a427e0_0 .net8 "VPWR", 0 0, L_00000000040005e0;  1 drivers, strength-aware
+v0000000003a42560_0 .net "Y", 0 0, L_00000000041327c0;  alias, 1 drivers
+v0000000003a43500_0 .net "not0_out_Y", 0 0, L_0000000004131aa0;  1 drivers
+S_0000000003a2faa0 .scope module, "_0676_" "sky130_fd_sc_hd__a2bb2o_2" 3 1435, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a43960_0 .net "A1_N", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a41e80_0 .net "A2_N", 0 0, L_0000000003f92500;  1 drivers
+v0000000003a42ec0_0 .net "B1", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a42100_0 .net "B2", 0 0, L_0000000003f93220;  1 drivers
+L_0000000004000960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a43e60_0 .net8 "VGND", 0 0, L_0000000004000960;  1 drivers, strength-aware
+L_0000000004000ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41980_0 .net8 "VNB", 0 0, L_0000000004000ab0;  1 drivers, strength-aware
+L_0000000004001140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a43640_0 .net8 "VPB", 0 0, L_0000000004001140;  1 drivers, strength-aware
+L_0000000004000810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42b00_0 .net8 "VPWR", 0 0, L_0000000004000810;  1 drivers, strength-aware
+v0000000003a42e20_0 .net "X", 0 0, L_00000000041318e0;  alias, 1 drivers
+S_0000000003a31d20 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a2faa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041314f0 .functor AND 1, L_0000000004125be0, L_0000000003f93220, C4<1>, C4<1>;
+L_0000000004131fe0 .functor NOR 1, L_0000000004125be0, L_0000000003f92500, C4<0>, C4<0>;
+L_00000000041313a0 .functor OR 1, L_0000000004131fe0, L_00000000041314f0, C4<0>, C4<0>;
+L_00000000041318e0 .functor BUF 1, L_00000000041313a0, C4<0>, C4<0>, C4<0>;
+v0000000003a42060_0 .net "A1_N", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a438c0_0 .net "A2_N", 0 0, L_0000000003f92500;  alias, 1 drivers
+v0000000003a41c00_0 .net "B1", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a42ba0_0 .net "B2", 0 0, L_0000000003f93220;  alias, 1 drivers
+L_0000000004001220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41ac0_0 .net8 "VGND", 0 0, L_0000000004001220;  1 drivers, strength-aware
+L_0000000004001ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a426a0_0 .net8 "VNB", 0 0, L_0000000004001ca0;  1 drivers, strength-aware
+L_0000000004002f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42420_0 .net8 "VPB", 0 0, L_0000000004002f70;  1 drivers, strength-aware
+L_00000000040025d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42d80_0 .net8 "VPWR", 0 0, L_00000000040025d0;  1 drivers, strength-aware
+v0000000003a43fa0_0 .net "X", 0 0, L_00000000041318e0;  alias, 1 drivers
+v0000000003a42880_0 .net "and0_out", 0 0, L_00000000041314f0;  1 drivers
+v0000000003a43000_0 .net "nor0_out", 0 0, L_0000000004131fe0;  1 drivers
+v0000000003a41f20_0 .net "or0_out_X", 0 0, L_00000000041313a0;  1 drivers
+S_0000000003a32320 .scope module, "_0677_" "sky130_fd_sc_hd__a221o_2" 3 1442, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a421a0_0 .net "A1", 0 0, L_00000000041327c0;  alias, 1 drivers
+v0000000003a43460_0 .net "A2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a41a20_0 .net "B1", 0 0, L_0000000003f932c0;  1 drivers
+v0000000003a42920_0 .net "B2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a43be0_0 .net "C1", 0 0, L_00000000041318e0;  alias, 1 drivers
+L_00000000040034b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a42240_0 .net8 "VGND", 0 0, L_00000000040034b0;  1 drivers, strength-aware
+L_0000000004002410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a41de0_0 .net8 "VNB", 0 0, L_0000000004002410;  1 drivers, strength-aware
+L_00000000040036e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a429c0_0 .net8 "VPB", 0 0, L_00000000040036e0;  1 drivers, strength-aware
+L_0000000004001f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a436e0_0 .net8 "VPWR", 0 0, L_0000000004001f40;  1 drivers, strength-aware
+v0000000003a422e0_0 .net "X", 0 0, L_0000000004132130;  alias, 1 drivers
+S_0000000003a2ea20 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a32320;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004131640 .functor AND 1, L_0000000003f932c0, L_0000000004127e00, C4<1>, C4<1>;
+L_00000000041320c0 .functor AND 1, L_00000000041327c0, L_0000000004130300, C4<1>, C4<1>;
+L_0000000004131c60 .functor OR 1, L_00000000041320c0, L_0000000004131640, L_00000000041318e0, C4<0>;
+L_0000000004132130 .functor BUF 1, L_0000000004131c60, C4<0>, C4<0>, C4<0>;
+v0000000003a43f00_0 .net "A1", 0 0, L_00000000041327c0;  alias, 1 drivers
+v0000000003a43aa0_0 .net "A2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a41ca0_0 .net "B1", 0 0, L_0000000003f932c0;  alias, 1 drivers
+v0000000003a43a00_0 .net "B2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a435a0_0 .net "C1", 0 0, L_00000000041318e0;  alias, 1 drivers
+L_0000000004002bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a42f60_0 .net8 "VGND", 0 0, L_0000000004002bf0;  1 drivers, strength-aware
+L_0000000004001df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a430a0_0 .net8 "VNB", 0 0, L_0000000004001df0;  1 drivers, strength-aware
+L_0000000004002250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44040_0 .net8 "VPB", 0 0, L_0000000004002250;  1 drivers, strength-aware
+L_0000000004002b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a43320_0 .net8 "VPWR", 0 0, L_0000000004002b10;  1 drivers, strength-aware
+v0000000003a43dc0_0 .net "X", 0 0, L_0000000004132130;  alias, 1 drivers
+v0000000003a41fc0_0 .net "and0_out", 0 0, L_0000000004131640;  1 drivers
+v0000000003a440e0_0 .net "and1_out", 0 0, L_00000000041320c0;  1 drivers
+v0000000003a43b40_0 .net "or0_out_X", 0 0, L_0000000004131c60;  1 drivers
+S_0000000003a2ed20 .scope module, "_0678_" "sky130_fd_sc_hd__inv_2" 3 1450, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a42c40_0 .net "A", 0 0, L_0000000004132130;  alias, 1 drivers
+L_0000000004001e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a43280_0 .net8 "VGND", 0 0, L_0000000004001e60;  1 drivers, strength-aware
+L_0000000004003670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a44400_0 .net8 "VNB", 0 0, L_0000000004003670;  1 drivers, strength-aware
+L_0000000004002640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a45ee0_0 .net8 "VPB", 0 0, L_0000000004002640;  1 drivers, strength-aware
+L_0000000004002b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44b80_0 .net8 "VPWR", 0 0, L_0000000004002b80;  1 drivers, strength-aware
+v0000000003a467a0_0 .net "Y", 0 0, L_0000000004131410;  alias, 1 drivers
+S_0000000003a2eea0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2ed20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004131d40 .functor NOT 1, L_0000000004132130, C4<0>, C4<0>, C4<0>;
+L_0000000004131410 .functor BUF 1, L_0000000004131d40, C4<0>, C4<0>, C4<0>;
+v0000000003a42380_0 .net "A", 0 0, L_0000000004132130;  alias, 1 drivers
+L_00000000040033d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a42600_0 .net8 "VGND", 0 0, L_00000000040033d0;  1 drivers, strength-aware
+L_00000000040029c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a43c80_0 .net8 "VNB", 0 0, L_00000000040029c0;  1 drivers, strength-aware
+L_0000000004003590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a43140_0 .net8 "VPB", 0 0, L_0000000004003590;  1 drivers, strength-aware
+L_0000000004002c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a42a60_0 .net8 "VPWR", 0 0, L_0000000004002c60;  1 drivers, strength-aware
+v0000000003a431e0_0 .net "Y", 0 0, L_0000000004131410;  alias, 1 drivers
+v0000000003a424c0_0 .net "not0_out_Y", 0 0, L_0000000004131d40;  1 drivers
+S_0000000003a32c20 .scope module, "_0679_" "sky130_fd_sc_hd__nor2_2" 3 1454, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a45c60_0 .net "A", 0 0, L_0000000004131bf0;  alias, 1 drivers
+v0000000003a45d00_0 .net "B", 0 0, L_0000000004131410;  alias, 1 drivers
+L_00000000040030c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a46480_0 .net8 "VGND", 0 0, L_00000000040030c0;  1 drivers, strength-aware
+L_0000000004002020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a46840_0 .net8 "VNB", 0 0, L_0000000004002020;  1 drivers, strength-aware
+L_0000000004002100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44900_0 .net8 "VPB", 0 0, L_0000000004002100;  1 drivers, strength-aware
+L_0000000004002fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a468e0_0 .net8 "VPWR", 0 0, L_0000000004002fe0;  1 drivers, strength-aware
+v0000000003a46700_0 .net "Y", 0 0, L_0000000004132c20;  alias, 1 drivers
+S_0000000003a2fc20 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a32c20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004132b40 .functor NOR 1, L_0000000004131bf0, L_0000000004131410, C4<0>, C4<0>;
+L_0000000004132c20 .functor BUF 1, L_0000000004132b40, C4<0>, C4<0>, C4<0>;
+v0000000003a465c0_0 .net "A", 0 0, L_0000000004131bf0;  alias, 1 drivers
+v0000000003a462a0_0 .net "B", 0 0, L_0000000004131410;  alias, 1 drivers
+L_0000000004003050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a460c0_0 .net8 "VGND", 0 0, L_0000000004003050;  1 drivers, strength-aware
+L_0000000004001d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a44680_0 .net8 "VNB", 0 0, L_0000000004001d80;  1 drivers, strength-aware
+L_0000000004003130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a447c0_0 .net8 "VPB", 0 0, L_0000000004003130;  1 drivers, strength-aware
+L_0000000004002e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44860_0 .net8 "VPWR", 0 0, L_0000000004002e20;  1 drivers, strength-aware
+v0000000003a46660_0 .net "Y", 0 0, L_0000000004132c20;  alias, 1 drivers
+v0000000003a45300_0 .net "nor0_out_Y", 0 0, L_0000000004132b40;  1 drivers
+S_0000000003a2d0a0 .scope module, "_0680_" "sky130_fd_sc_hd__inv_2" 3 1459, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a45440_0 .net "A", 0 0, L_0000000003f92fa0;  1 drivers
+L_0000000004003600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a453a0_0 .net8 "VGND", 0 0, L_0000000004003600;  1 drivers, strength-aware
+L_0000000004002480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a442c0_0 .net8 "VNB", 0 0, L_0000000004002480;  1 drivers, strength-aware
+L_0000000004003750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a45260_0 .net8 "VPB", 0 0, L_0000000004003750;  1 drivers, strength-aware
+L_0000000004002db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44ea0_0 .net8 "VPWR", 0 0, L_0000000004002db0;  1 drivers, strength-aware
+v0000000003a444a0_0 .net "Y", 0 0, L_0000000004131560;  alias, 1 drivers
+S_0000000003a324a0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a2d0a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004131db0 .functor NOT 1, L_0000000003f92fa0, C4<0>, C4<0>, C4<0>;
+L_0000000004131560 .functor BUF 1, L_0000000004131db0, C4<0>, C4<0>, C4<0>;
+v0000000003a45080_0 .net "A", 0 0, L_0000000003f92fa0;  alias, 1 drivers
+L_0000000004003360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a44fe0_0 .net8 "VGND", 0 0, L_0000000004003360;  1 drivers, strength-aware
+L_0000000004002560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a445e0_0 .net8 "VNB", 0 0, L_0000000004002560;  1 drivers, strength-aware
+L_00000000040023a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44180_0 .net8 "VPB", 0 0, L_00000000040023a0;  1 drivers, strength-aware
+L_0000000004003280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44c20_0 .net8 "VPWR", 0 0, L_0000000004003280;  1 drivers, strength-aware
+v0000000003a44cc0_0 .net "Y", 0 0, L_0000000004131560;  alias, 1 drivers
+v0000000003a44220_0 .net "not0_out_Y", 0 0, L_0000000004131db0;  1 drivers
+S_0000000003a32920 .scope module, "_0681_" "sky130_fd_sc_hd__a2bb2o_2" 3 1463, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a46160_0 .net "A1_N", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000003a454e0_0 .net "A2_N", 0 0, L_0000000003f93360;  1 drivers
+v0000000003a45a80_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a46200_0 .net "B2", 0 0, L_0000000003f928c0;  1 drivers
+L_0000000004001ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a45580_0 .net8 "VGND", 0 0, L_0000000004001ed0;  1 drivers, strength-aware
+L_0000000004002800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a45620_0 .net8 "VNB", 0 0, L_0000000004002800;  1 drivers, strength-aware
+L_0000000004003440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a46520_0 .net8 "VPB", 0 0, L_0000000004003440;  1 drivers, strength-aware
+L_00000000040024f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a44540_0 .net8 "VPWR", 0 0, L_00000000040024f0;  1 drivers, strength-aware
+v0000000003a456c0_0 .net "X", 0 0, L_0000000004131870;  alias, 1 drivers
+S_0000000003a32aa0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a32920;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041316b0 .functor AND 1, L_0000000004130140, L_0000000003f928c0, C4<1>, C4<1>;
+L_0000000004132520 .functor NOR 1, L_0000000004128030, L_0000000003f93360, C4<0>, C4<0>;
+L_0000000004131e90 .functor OR 1, L_0000000004132520, L_00000000041316b0, C4<0>, C4<0>;
+L_0000000004131870 .functor BUF 1, L_0000000004131e90, C4<0>, C4<0>, C4<0>;
+v0000000003a45f80_0 .net "A1_N", 0 0, L_0000000004128030;  alias, 1 drivers
+v0000000003a44360_0 .net "A2_N", 0 0, L_0000000003f93360;  alias, 1 drivers
+v0000000003a45e40_0 .net "B1", 0 0, L_0000000004130140;  alias, 1 drivers
+v0000000003a44d60_0 .net "B2", 0 0, L_0000000003f928c0;  alias, 1 drivers
+L_00000000040026b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a44e00_0 .net8 "VGND", 0 0, L_00000000040026b0;  1 drivers, strength-aware
+L_0000000004002e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a45bc0_0 .net8 "VNB", 0 0, L_0000000004002e90;  1 drivers, strength-aware
+L_0000000004002170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a46020_0 .net8 "VPB", 0 0, L_0000000004002170;  1 drivers, strength-aware
+L_00000000040037c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a45da0_0 .net8 "VPWR", 0 0, L_00000000040037c0;  1 drivers, strength-aware
+v0000000003a44f40_0 .net "X", 0 0, L_0000000004131870;  alias, 1 drivers
+v0000000003a45120_0 .net "and0_out", 0 0, L_00000000041316b0;  1 drivers
+v0000000003a451c0_0 .net "nor0_out", 0 0, L_0000000004132520;  1 drivers
+v0000000003a449a0_0 .net "or0_out_X", 0 0, L_0000000004131e90;  1 drivers
+S_0000000003a32da0 .scope module, "_0682_" "sky130_fd_sc_hd__o221a_2" 3 1470, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a48aa0_0 .net "A1", 0 0, L_0000000003f93400;  1 drivers
+v0000000003a46ac0_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a485a0_0 .net "B1", 0 0, L_0000000004131560;  alias, 1 drivers
+v0000000003a48500_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a48640_0 .net "C1", 0 0, L_0000000004131870;  alias, 1 drivers
+L_0000000004001fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47f60_0 .net8 "VGND", 0 0, L_0000000004001fb0;  1 drivers, strength-aware
+L_0000000004003830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47d80_0 .net8 "VNB", 0 0, L_0000000004003830;  1 drivers, strength-aware
+L_00000000040031a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48fa0_0 .net8 "VPB", 0 0, L_00000000040031a0;  1 drivers, strength-aware
+L_0000000004002aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48320_0 .net8 "VPWR", 0 0, L_0000000004002aa0;  1 drivers, strength-aware
+v0000000003a48d20_0 .net "X", 0 0, L_0000000004132440;  alias, 1 drivers
+S_0000000003a2f020 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a32da0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041321a0 .functor OR 1, L_0000000004127930, L_0000000004131560, C4<0>, C4<0>;
+L_0000000004132210 .functor OR 1, L_000000000412cc50, L_0000000003f93400, C4<0>, C4<0>;
+L_00000000041323d0 .functor AND 1, L_00000000041321a0, L_0000000004132210, L_0000000004131870, C4<1>;
+L_0000000004132440 .functor BUF 1, L_00000000041323d0, C4<0>, C4<0>, C4<0>;
+v0000000003a45760_0 .net "A1", 0 0, L_0000000003f93400;  alias, 1 drivers
+v0000000003a44720_0 .net "A2", 0 0, L_000000000412cc50;  alias, 1 drivers
+v0000000003a44a40_0 .net "B1", 0 0, L_0000000004131560;  alias, 1 drivers
+v0000000003a45800_0 .net "B2", 0 0, L_0000000004127930;  alias, 1 drivers
+v0000000003a44ae0_0 .net "C1", 0 0, L_0000000004131870;  alias, 1 drivers
+L_00000000040032f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a458a0_0 .net8 "VGND", 0 0, L_00000000040032f0;  1 drivers, strength-aware
+L_00000000040028e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a45940_0 .net8 "VNB", 0 0, L_00000000040028e0;  1 drivers, strength-aware
+L_0000000004002090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a459e0_0 .net8 "VPB", 0 0, L_0000000004002090;  1 drivers, strength-aware
+L_00000000040021e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a45b20_0 .net8 "VPWR", 0 0, L_00000000040021e0;  1 drivers, strength-aware
+v0000000003a46340_0 .net "X", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a463e0_0 .net "and0_out_X", 0 0, L_00000000041323d0;  1 drivers
+v0000000003a47560_0 .net "or0_out", 0 0, L_00000000041321a0;  1 drivers
+v0000000003a48820_0 .net "or1_out", 0 0, L_0000000004132210;  1 drivers
+S_0000000003a303a0 .scope module, "_0683_" "sky130_fd_sc_hd__o221a_2" 3 1478, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a47600_0 .net "A1", 0 0, L_0000000003f93c20;  1 drivers
+v0000000003a48c80_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a46e80_0 .net "B1", 0 0, L_00000000041327c0;  alias, 1 drivers
+v0000000003a46980_0 .net "B2", 0 0, L_0000000004125470;  alias, 1 drivers
+v0000000003a47920_0 .net "C1", 0 0, L_00000000041318e0;  alias, 1 drivers
+L_00000000040022c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a48280_0 .net8 "VGND", 0 0, L_00000000040022c0;  1 drivers, strength-aware
+L_0000000004002330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a48960_0 .net8 "VNB", 0 0, L_0000000004002330;  1 drivers, strength-aware
+L_0000000004002720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a476a0_0 .net8 "VPB", 0 0, L_0000000004002720;  1 drivers, strength-aware
+L_0000000004001d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48460_0 .net8 "VPWR", 0 0, L_0000000004001d10;  1 drivers, strength-aware
+v0000000003a48140_0 .net "X", 0 0, L_0000000004132750;  alias, 1 drivers
+S_0000000003a30820 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a303a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041324b0 .functor OR 1, L_0000000004125470, L_00000000041327c0, C4<0>, C4<0>;
+L_0000000004132590 .functor OR 1, L_0000000004130f40, L_0000000003f93c20, C4<0>, C4<0>;
+L_0000000004132600 .functor AND 1, L_00000000041324b0, L_0000000004132590, L_00000000041318e0, C4<1>;
+L_0000000004132750 .functor BUF 1, L_0000000004132600, C4<0>, C4<0>, C4<0>;
+v0000000003a477e0_0 .net "A1", 0 0, L_0000000003f93c20;  alias, 1 drivers
+v0000000003a483c0_0 .net "A2", 0 0, L_0000000004130f40;  alias, 1 drivers
+v0000000003a48b40_0 .net "B1", 0 0, L_00000000041327c0;  alias, 1 drivers
+v0000000003a47240_0 .net "B2", 0 0, L_0000000004125470;  alias, 1 drivers
+v0000000003a46ca0_0 .net "C1", 0 0, L_00000000041318e0;  alias, 1 drivers
+L_0000000004002790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a486e0_0 .net8 "VGND", 0 0, L_0000000004002790;  1 drivers, strength-aware
+L_0000000004002870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47740_0 .net8 "VNB", 0 0, L_0000000004002870;  1 drivers, strength-aware
+L_0000000004002950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a47880_0 .net8 "VPB", 0 0, L_0000000004002950;  1 drivers, strength-aware
+L_0000000004002a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48780_0 .net8 "VPWR", 0 0, L_0000000004002a30;  1 drivers, strength-aware
+v0000000003a488c0_0 .net "X", 0 0, L_0000000004132750;  alias, 1 drivers
+v0000000003a48a00_0 .net "and0_out_X", 0 0, L_0000000004132600;  1 drivers
+v0000000003a47ba0_0 .net "or0_out", 0 0, L_00000000041324b0;  1 drivers
+v0000000003a481e0_0 .net "or1_out", 0 0, L_0000000004132590;  1 drivers
+S_0000000003a2ff20 .scope module, "_0684_" "sky130_fd_sc_hd__nor2_2" 3 1486, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a48f00_0 .net "A", 0 0, L_0000000004131410;  alias, 1 drivers
+v0000000003a47c40_0 .net "B", 0 0, L_0000000004132750;  alias, 1 drivers
+L_0000000004002f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a49040_0 .net8 "VGND", 0 0, L_0000000004002f00;  1 drivers, strength-aware
+L_0000000004003210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47ce0_0 .net8 "VNB", 0 0, L_0000000004003210;  1 drivers, strength-aware
+L_0000000004002cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a47e20_0 .net8 "VPB", 0 0, L_0000000004002cd0;  1 drivers, strength-aware
+L_0000000004002d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a490e0_0 .net8 "VPWR", 0 0, L_0000000004002d40;  1 drivers, strength-aware
+v0000000003a46fc0_0 .net "Y", 0 0, L_0000000004134890;  alias, 1 drivers
+S_0000000003a300a0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2ff20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041328a0 .functor NOR 1, L_0000000004131410, L_0000000004132750, C4<0>, C4<0>;
+L_0000000004134890 .functor BUF 1, L_00000000041328a0, C4<0>, C4<0>, C4<0>;
+v0000000003a47a60_0 .net "A", 0 0, L_0000000004131410;  alias, 1 drivers
+v0000000003a479c0_0 .net "B", 0 0, L_0000000004132750;  alias, 1 drivers
+L_0000000004003520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a46f20_0 .net8 "VGND", 0 0, L_0000000004003520;  1 drivers, strength-aware
+L_00000000040038a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47b00_0 .net8 "VNB", 0 0, L_00000000040038a0;  1 drivers, strength-aware
+L_00000000040046a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48be0_0 .net8 "VPB", 0 0, L_00000000040046a0;  1 drivers, strength-aware
+L_00000000040047f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48dc0_0 .net8 "VPWR", 0 0, L_00000000040047f0;  1 drivers, strength-aware
+v0000000003a47ec0_0 .net "Y", 0 0, L_0000000004134890;  alias, 1 drivers
+v0000000003a48e60_0 .net "nor0_out_Y", 0 0, L_00000000041328a0;  1 drivers
+S_0000000003a2d3a0 .scope module, "_0685_" "sky130_fd_sc_hd__nor2_2" 3 1491, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a474c0_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a46de0_0 .net "B", 0 0, L_0000000004134890;  alias, 1 drivers
+L_0000000004004b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47060_0 .net8 "VGND", 0 0, L_0000000004004b00;  1 drivers, strength-aware
+L_0000000004003d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47100_0 .net8 "VNB", 0 0, L_0000000004003d70;  1 drivers, strength-aware
+L_0000000004004470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a471a0_0 .net8 "VPB", 0 0, L_0000000004004470;  1 drivers, strength-aware
+L_0000000004003bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a472e0_0 .net8 "VPWR", 0 0, L_0000000004003bb0;  1 drivers, strength-aware
+v0000000003a49f40_0 .net "Y", 0 0, L_0000000004133780;  alias, 1 drivers
+S_0000000003a2d520 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a2d3a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004132d00 .functor NOR 1, L_0000000004132440, L_0000000004134890, C4<0>, C4<0>;
+L_0000000004133780 .functor BUF 1, L_0000000004132d00, C4<0>, C4<0>, C4<0>;
+v0000000003a46a20_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a46c00_0 .net "B", 0 0, L_0000000004134890;  alias, 1 drivers
+L_00000000040044e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a46b60_0 .net8 "VGND", 0 0, L_00000000040044e0;  1 drivers, strength-aware
+L_00000000040041d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a47380_0 .net8 "VNB", 0 0, L_00000000040041d0;  1 drivers, strength-aware
+L_0000000004004d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a48000_0 .net8 "VPB", 0 0, L_0000000004004d30;  1 drivers, strength-aware
+L_00000000040048d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a46d40_0 .net8 "VPWR", 0 0, L_00000000040048d0;  1 drivers, strength-aware
+v0000000003a47420_0 .net "Y", 0 0, L_0000000004133780;  alias, 1 drivers
+v0000000003a480a0_0 .net "nor0_out_Y", 0 0, L_0000000004132d00;  1 drivers
+S_0000000003a30220 .scope module, "_0686_" "sky130_fd_sc_hd__or2_2" 3 1496, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a4b340_0 .net "A", 0 0, L_00000000041315d0;  alias, 1 drivers
+v0000000003a49220_0 .net "B", 0 0, L_0000000004132130;  alias, 1 drivers
+L_0000000004004e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4aa80_0 .net8 "VGND", 0 0, L_0000000004004e10;  1 drivers, strength-aware
+L_0000000004005350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a8a0_0 .net8 "VNB", 0 0, L_0000000004005350;  1 drivers, strength-aware
+L_0000000004005430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a49860_0 .net8 "VPB", 0 0, L_0000000004005430;  1 drivers, strength-aware
+L_0000000004004550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a49fe0_0 .net8 "VPWR", 0 0, L_0000000004004550;  1 drivers, strength-aware
+v0000000003a49720_0 .net "X", 0 0, L_0000000004133b00;  alias, 1 drivers
+S_0000000003a309a0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a30220;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004132ec0 .functor OR 1, L_0000000004132130, L_00000000041315d0, C4<0>, C4<0>;
+L_0000000004133b00 .functor BUF 1, L_0000000004132ec0, C4<0>, C4<0>, C4<0>;
+v0000000003a4b8e0_0 .net "A", 0 0, L_00000000041315d0;  alias, 1 drivers
+v0000000003a49cc0_0 .net "B", 0 0, L_0000000004132130;  alias, 1 drivers
+L_00000000040049b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ad00_0 .net8 "VGND", 0 0, L_00000000040049b0;  1 drivers, strength-aware
+L_0000000004004080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a760_0 .net8 "VNB", 0 0, L_0000000004004080;  1 drivers, strength-aware
+L_0000000004003910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a580_0 .net8 "VPB", 0 0, L_0000000004003910;  1 drivers, strength-aware
+L_0000000004004da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b5c0_0 .net8 "VPWR", 0 0, L_0000000004004da0;  1 drivers, strength-aware
+v0000000003a4a300_0 .net "X", 0 0, L_0000000004133b00;  alias, 1 drivers
+v0000000003a4b520_0 .net "or0_out_X", 0 0, L_0000000004132ec0;  1 drivers
+S_0000000003a2d6a0 .scope module, "_0687_" "sky130_fd_sc_hd__o21a_2" 3 1501, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a4ab20_0 .net "A1", 0 0, L_0000000004132c20;  alias, 1 drivers
+v0000000003a4b160_0 .net "A2", 0 0, L_0000000004133780;  alias, 1 drivers
+v0000000003a49ea0_0 .net "B1", 0 0, L_0000000004133b00;  alias, 1 drivers
+L_0000000004004cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ada0_0 .net8 "VGND", 0 0, L_0000000004004cc0;  1 drivers, strength-aware
+L_0000000004004240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a49900_0 .net8 "VNB", 0 0, L_0000000004004240;  1 drivers, strength-aware
+L_0000000004004ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a6c0_0 .net8 "VPB", 0 0, L_0000000004004ef0;  1 drivers, strength-aware
+L_00000000040040f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a49400_0 .net8 "VPWR", 0 0, L_00000000040040f0;  1 drivers, strength-aware
+v0000000003a4a440_0 .net "X", 0 0, L_0000000004134580;  alias, 1 drivers
+S_0000000003a34ba0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a2d6a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004133550 .functor OR 1, L_0000000004133780, L_0000000004132c20, C4<0>, C4<0>;
+L_00000000041337f0 .functor AND 1, L_0000000004133550, L_0000000004133b00, C4<1>, C4<1>;
+L_0000000004134580 .functor BUF 1, L_00000000041337f0, C4<0>, C4<0>, C4<0>;
+v0000000003a4a080_0 .net "A1", 0 0, L_0000000004132c20;  alias, 1 drivers
+v0000000003a49d60_0 .net "A2", 0 0, L_0000000004133780;  alias, 1 drivers
+v0000000003a4a620_0 .net "B1", 0 0, L_0000000004133b00;  alias, 1 drivers
+L_0000000004004b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a3a0_0 .net8 "VGND", 0 0, L_0000000004004b70;  1 drivers, strength-aware
+L_0000000004004be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a9e0_0 .net8 "VNB", 0 0, L_0000000004004be0;  1 drivers, strength-aware
+L_00000000040042b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ac60_0 .net8 "VPB", 0 0, L_00000000040042b0;  1 drivers, strength-aware
+L_0000000004004160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4abc0_0 .net8 "VPWR", 0 0, L_0000000004004160;  1 drivers, strength-aware
+v0000000003a49180_0 .net "X", 0 0, L_0000000004134580;  alias, 1 drivers
+v0000000003a49e00_0 .net "and0_out_X", 0 0, L_00000000041337f0;  1 drivers
+v0000000003a4b480_0 .net "or0_out", 0 0, L_0000000004133550;  1 drivers
+S_0000000003a34720 .scope module, "_0688_" "sky130_fd_sc_hd__a221oi_2" 3 1507, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a4a1c0_0 .net "A1", 0 0, L_0000000004131560;  alias, 1 drivers
+v0000000003a4b840_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a4b7a0_0 .net "B1", 0 0, L_0000000003f935e0;  1 drivers
+v0000000003a4aee0_0 .net "B2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a4a260_0 .net "C1", 0 0, L_0000000004131870;  alias, 1 drivers
+L_0000000004004e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a49360_0 .net8 "VGND", 0 0, L_0000000004004e80;  1 drivers, strength-aware
+L_00000000040045c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b200_0 .net8 "VNB", 0 0, L_00000000040045c0;  1 drivers, strength-aware
+L_00000000040039f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4af80_0 .net8 "VPB", 0 0, L_00000000040039f0;  1 drivers, strength-aware
+L_0000000004003ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b020_0 .net8 "VPWR", 0 0, L_0000000004003ec0;  1 drivers, strength-aware
+v0000000003a4b0c0_0 .net "Y", 0 0, L_00000000041332b0;  alias, 1 drivers
+S_0000000003a33ca0 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a34720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004133010 .functor AND 1, L_0000000003f935e0, L_000000000412d0b0, C4<1>, C4<1>;
+L_0000000004134270 .functor AND 1, L_0000000004131560, L_0000000004125860, C4<1>, C4<1>;
+L_00000000041342e0 .functor NOR 1, L_0000000004133010, L_0000000004131870, L_0000000004134270, C4<0>;
+L_00000000041332b0 .functor BUF 1, L_00000000041342e0, C4<0>, C4<0>, C4<0>;
+v0000000003a494a0_0 .net "A1", 0 0, L_0000000004131560;  alias, 1 drivers
+v0000000003a4b660_0 .net "A2", 0 0, L_0000000004125860;  alias, 1 drivers
+v0000000003a49540_0 .net "B1", 0 0, L_0000000003f935e0;  alias, 1 drivers
+v0000000003a4a120_0 .net "B2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a495e0_0 .net "C1", 0 0, L_0000000004131870;  alias, 1 drivers
+L_0000000004003a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b3e0_0 .net8 "VGND", 0 0, L_0000000004003a60;  1 drivers, strength-aware
+L_0000000004004320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4a800_0 .net8 "VNB", 0 0, L_0000000004004320;  1 drivers, strength-aware
+L_0000000004003980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a499a0_0 .net8 "VPB", 0 0, L_0000000004003980;  1 drivers, strength-aware
+L_0000000004004860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b700_0 .net8 "VPWR", 0 0, L_0000000004004860;  1 drivers, strength-aware
+v0000000003a492c0_0 .net "Y", 0 0, L_00000000041332b0;  alias, 1 drivers
+v0000000003a4ae40_0 .net "and0_out", 0 0, L_0000000004133010;  1 drivers
+v0000000003a4a4e0_0 .net "and1_out", 0 0, L_0000000004134270;  1 drivers
+v0000000003a4a940_0 .net "nor0_out_Y", 0 0, L_00000000041342e0;  1 drivers
+S_0000000003a330a0 .scope module, "_0689_" "sky130_fd_sc_hd__or2_2" 3 1515, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a4cb00_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a4bfc0_0 .net "B", 0 0, L_00000000041332b0;  alias, 1 drivers
+L_0000000004004710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d640_0 .net8 "VGND", 0 0, L_0000000004004710;  1 drivers, strength-aware
+L_0000000004005200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e040_0 .net8 "VNB", 0 0, L_0000000004005200;  1 drivers, strength-aware
+L_0000000004004630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c380_0 .net8 "VPB", 0 0, L_0000000004004630;  1 drivers, strength-aware
+L_0000000004003ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d000_0 .net8 "VPWR", 0 0, L_0000000004003ad0;  1 drivers, strength-aware
+v0000000003a4cec0_0 .net "X", 0 0, L_00000000041335c0;  alias, 1 drivers
+S_0000000003a33b20 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a330a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004134350 .functor OR 1, L_00000000041332b0, L_0000000004132440, C4<0>, C4<0>;
+L_00000000041335c0 .functor BUF 1, L_0000000004134350, C4<0>, C4<0>, C4<0>;
+v0000000003a4b2a0_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a49680_0 .net "B", 0 0, L_00000000041332b0;  alias, 1 drivers
+L_0000000004003b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a497c0_0 .net8 "VGND", 0 0, L_0000000004003b40;  1 drivers, strength-aware
+L_0000000004004f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a49a40_0 .net8 "VNB", 0 0, L_0000000004004f60;  1 drivers, strength-aware
+L_0000000004003de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a49ae0_0 .net8 "VPB", 0 0, L_0000000004003de0;  1 drivers, strength-aware
+L_0000000004004780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a49b80_0 .net8 "VPWR", 0 0, L_0000000004004780;  1 drivers, strength-aware
+v0000000003a49c20_0 .net "X", 0 0, L_00000000041335c0;  alias, 1 drivers
+v0000000003a4d460_0 .net "or0_out_X", 0 0, L_0000000004134350;  1 drivers
+S_0000000003a33e20 .scope module, "_0690_" "sky130_fd_sc_hd__inv_2" 3 1520, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a4d320_0 .net "A", 0 0, L_00000000041335c0;  alias, 1 drivers
+L_0000000004004a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d6e0_0 .net8 "VGND", 0 0, L_0000000004004a20;  1 drivers, strength-aware
+L_0000000004004940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4bf20_0 .net8 "VNB", 0 0, L_0000000004004940;  1 drivers, strength-aware
+L_0000000004004fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c9c0_0 .net8 "VPB", 0 0, L_0000000004004fd0;  1 drivers, strength-aware
+L_0000000004004390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4dfa0_0 .net8 "VPWR", 0 0, L_0000000004004390;  1 drivers, strength-aware
+v0000000003a4d3c0_0 .net "Y", 0 0, L_00000000041343c0;  alias, 1 drivers
+S_0000000003a336a0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a33e20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004132d70 .functor NOT 1, L_00000000041335c0, C4<0>, C4<0>, C4<0>;
+L_00000000041343c0 .functor BUF 1, L_0000000004132d70, C4<0>, C4<0>, C4<0>;
+v0000000003a4dbe0_0 .net "A", 0 0, L_00000000041335c0;  alias, 1 drivers
+L_0000000004003c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c060_0 .net8 "VGND", 0 0, L_0000000004003c20;  1 drivers, strength-aware
+L_0000000004004400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e0e0_0 .net8 "VNB", 0 0, L_0000000004004400;  1 drivers, strength-aware
+L_0000000004004a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c4c0_0 .net8 "VPB", 0 0, L_0000000004004a90;  1 drivers, strength-aware
+L_0000000004004c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d820_0 .net8 "VPWR", 0 0, L_0000000004004c50;  1 drivers, strength-aware
+v0000000003a4cd80_0 .net "Y", 0 0, L_00000000041343c0;  alias, 1 drivers
+v0000000003a4d280_0 .net "not0_out_Y", 0 0, L_0000000004132d70;  1 drivers
+S_0000000003a33820 .scope module, "_0691_" "sky130_fd_sc_hd__inv_2" 3 1524, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a4d8c0_0 .net "A", 0 0, L_0000000003f92140;  1 drivers
+L_0000000004005040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d780_0 .net8 "VGND", 0 0, L_0000000004005040;  1 drivers, strength-aware
+L_0000000004003f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d5a0_0 .net8 "VNB", 0 0, L_0000000004003f30;  1 drivers, strength-aware
+L_0000000004003fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4cce0_0 .net8 "VPB", 0 0, L_0000000004003fa0;  1 drivers, strength-aware
+L_00000000040050b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4bb60_0 .net8 "VPWR", 0 0, L_00000000040050b0;  1 drivers, strength-aware
+v0000000003a4bd40_0 .net "Y", 0 0, L_00000000041346d0;  alias, 1 drivers
+S_0000000003a33220 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a33820;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004132f30 .functor NOT 1, L_0000000003f92140, C4<0>, C4<0>, C4<0>;
+L_00000000041346d0 .functor BUF 1, L_0000000004132f30, C4<0>, C4<0>, C4<0>;
+v0000000003a4d1e0_0 .net "A", 0 0, L_0000000003f92140;  alias, 1 drivers
+L_0000000004005120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4df00_0 .net8 "VGND", 0 0, L_0000000004005120;  1 drivers, strength-aware
+L_0000000004005190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4dd20_0 .net8 "VNB", 0 0, L_0000000004005190;  1 drivers, strength-aware
+L_0000000004005270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c740_0 .net8 "VPB", 0 0, L_0000000004005270;  1 drivers, strength-aware
+L_00000000040052e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c7e0_0 .net8 "VPWR", 0 0, L_00000000040052e0;  1 drivers, strength-aware
+v0000000003a4c560_0 .net "Y", 0 0, L_00000000041346d0;  alias, 1 drivers
+v0000000003a4d500_0 .net "not0_out_Y", 0 0, L_0000000004132f30;  1 drivers
+S_0000000003a33fa0 .scope module, "_0692_" "sky130_fd_sc_hd__a2bb2o_2" 3 1528, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a4be80_0 .net "A1_N", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000003a4c1a0_0 .net "A2_N", 0 0, L_0000000003f93cc0;  1 drivers
+v0000000003a4cf60_0 .net "B1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000003a4c240_0 .net "B2", 0 0, L_0000000003f94620;  1 drivers
+L_00000000040053c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4de60_0 .net8 "VGND", 0 0, L_00000000040053c0;  1 drivers, strength-aware
+L_0000000004003c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4b980_0 .net8 "VNB", 0 0, L_0000000004003c90;  1 drivers, strength-aware
+L_0000000004003d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4daa0_0 .net8 "VPB", 0 0, L_0000000004003d00;  1 drivers, strength-aware
+L_0000000004003e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4d0a0_0 .net8 "VPWR", 0 0, L_0000000004003e50;  1 drivers, strength-aware
+v0000000003a4d140_0 .net "X", 0 0, L_0000000004133160;  alias, 1 drivers
+S_0000000003a34a20 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a33fa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041345f0 .functor AND 1, L_0000000004126d60, L_0000000003f94620, C4<1>, C4<1>;
+L_0000000004134740 .functor NOR 1, L_0000000004126d60, L_0000000003f93cc0, C4<0>, C4<0>;
+L_0000000004133b70 .functor OR 1, L_0000000004134740, L_00000000041345f0, C4<0>, C4<0>;
+L_0000000004133160 .functor BUF 1, L_0000000004133b70, C4<0>, C4<0>, C4<0>;
+v0000000003a4c100_0 .net "A1_N", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000003a4ce20_0 .net "A2_N", 0 0, L_0000000003f93cc0;  alias, 1 drivers
+v0000000003a4cc40_0 .net "B1", 0 0, L_0000000004126d60;  alias, 1 drivers
+v0000000003a4d960_0 .net "B2", 0 0, L_0000000003f94620;  alias, 1 drivers
+L_0000000004004010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c420_0 .net8 "VGND", 0 0, L_0000000004004010;  1 drivers, strength-aware
+L_00000000040065b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4bde0_0 .net8 "VNB", 0 0, L_00000000040065b0;  1 drivers, strength-aware
+L_0000000004005f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4da00_0 .net8 "VPB", 0 0, L_0000000004005f20;  1 drivers, strength-aware
+L_0000000004005970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4cba0_0 .net8 "VPWR", 0 0, L_0000000004005970;  1 drivers, strength-aware
+v0000000003a4ca60_0 .net "X", 0 0, L_0000000004133160;  alias, 1 drivers
+v0000000003a4c920_0 .net "and0_out", 0 0, L_00000000041345f0;  1 drivers
+v0000000003a4bc00_0 .net "nor0_out", 0 0, L_0000000004134740;  1 drivers
+v0000000003a4bca0_0 .net "or0_out_X", 0 0, L_0000000004133b70;  1 drivers
+S_0000000003a34120 .scope module, "_0693_" "sky130_fd_sc_hd__a221o_2" 3 1535, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a50520_0 .net "A1", 0 0, L_00000000041346d0;  alias, 1 drivers
+v0000000003a50700_0 .net "A2", 0 0, L_0000000004127620;  alias, 1 drivers
+v0000000003a4f260_0 .net "B1", 0 0, L_0000000003f94080;  1 drivers
+v0000000003a503e0_0 .net "B2", 0 0, L_0000000004125470;  alias, 1 drivers
+v0000000003a4fbc0_0 .net "C1", 0 0, L_0000000004133160;  alias, 1 drivers
+L_0000000004006d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ff80_0 .net8 "VGND", 0 0, L_0000000004006d20;  1 drivers, strength-aware
+L_0000000004005740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4fda0_0 .net8 "VNB", 0 0, L_0000000004005740;  1 drivers, strength-aware
+L_0000000004006380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a50480_0 .net8 "VPB", 0 0, L_0000000004006380;  1 drivers, strength-aware
+L_0000000004006e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4fd00_0 .net8 "VPWR", 0 0, L_0000000004006e00;  1 drivers, strength-aware
+v0000000003a4f760_0 .net "X", 0 0, L_00000000041347b0;  alias, 1 drivers
+S_0000000003a333a0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a34120;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004132fa0 .functor AND 1, L_0000000003f94080, L_0000000004125470, C4<1>, C4<1>;
+L_0000000004133320 .functor AND 1, L_00000000041346d0, L_0000000004127620, C4<1>, C4<1>;
+L_0000000004134040 .functor OR 1, L_0000000004133320, L_0000000004132fa0, L_0000000004133160, C4<0>;
+L_00000000041347b0 .functor BUF 1, L_0000000004134040, C4<0>, C4<0>, C4<0>;
+v0000000003a4c6a0_0 .net "A1", 0 0, L_00000000041346d0;  alias, 1 drivers
+v0000000003a4db40_0 .net "A2", 0 0, L_0000000004127620;  alias, 1 drivers
+v0000000003a4dc80_0 .net "B1", 0 0, L_0000000003f94080;  alias, 1 drivers
+v0000000003a4ddc0_0 .net "B2", 0 0, L_0000000004125470;  alias, 1 drivers
+v0000000003a4c880_0 .net "C1", 0 0, L_0000000004133160;  alias, 1 drivers
+L_0000000004005f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ba20_0 .net8 "VGND", 0 0, L_0000000004005f90;  1 drivers, strength-aware
+L_0000000004006d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c2e0_0 .net8 "VNB", 0 0, L_0000000004006d90;  1 drivers, strength-aware
+L_0000000004006a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4c600_0 .net8 "VPB", 0 0, L_0000000004006a10;  1 drivers, strength-aware
+L_00000000040069a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4bac0_0 .net8 "VPWR", 0 0, L_00000000040069a0;  1 drivers, strength-aware
+v0000000003a4ec20_0 .net "X", 0 0, L_00000000041347b0;  alias, 1 drivers
+v0000000003a4ed60_0 .net "and0_out", 0 0, L_0000000004132fa0;  1 drivers
+v0000000003a4f9e0_0 .net "and1_out", 0 0, L_0000000004133320;  1 drivers
+v0000000003a4fa80_0 .net "or0_out_X", 0 0, L_0000000004134040;  1 drivers
+S_0000000003a33520 .scope module, "_0694_" "sky130_fd_sc_hd__inv_2" 3 1543, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a4fc60_0 .net "A", 0 0, L_00000000041347b0;  alias, 1 drivers
+L_0000000004006cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4fe40_0 .net8 "VGND", 0 0, L_0000000004006cb0;  1 drivers, strength-aware
+L_0000000004006bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f620_0 .net8 "VNB", 0 0, L_0000000004006bd0;  1 drivers, strength-aware
+L_0000000004005e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e540_0 .net8 "VPB", 0 0, L_0000000004005e40;  1 drivers, strength-aware
+L_0000000004006000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4fee0_0 .net8 "VPWR", 0 0, L_0000000004006000;  1 drivers, strength-aware
+v0000000003a507a0_0 .net "Y", 0 0, L_00000000041339b0;  alias, 1 drivers
+S_0000000003a34420 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a33520;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004133be0 .functor NOT 1, L_00000000041347b0, C4<0>, C4<0>, C4<0>;
+L_00000000041339b0 .functor BUF 1, L_0000000004133be0, C4<0>, C4<0>, C4<0>;
+v0000000003a4e5e0_0 .net "A", 0 0, L_00000000041347b0;  alias, 1 drivers
+L_00000000040062a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ee00_0 .net8 "VGND", 0 0, L_00000000040062a0;  1 drivers, strength-aware
+L_0000000004006850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f080_0 .net8 "VNB", 0 0, L_0000000004006850;  1 drivers, strength-aware
+L_0000000004006e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4efe0_0 .net8 "VPB", 0 0, L_0000000004006e70;  1 drivers, strength-aware
+L_0000000004005a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f6c0_0 .net8 "VPWR", 0 0, L_0000000004005a50;  1 drivers, strength-aware
+v0000000003a4e4a0_0 .net "Y", 0 0, L_00000000041339b0;  alias, 1 drivers
+v0000000003a4fb20_0 .net "not0_out_Y", 0 0, L_0000000004133be0;  1 drivers
+S_0000000003a339a0 .scope module, "_0695_" "sky130_fd_sc_hd__nor2_2" 3 1547, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a4f1c0_0 .net "A", 0 0, L_00000000041343c0;  alias, 1 drivers
+v0000000003a50020_0 .net "B", 0 0, L_00000000041339b0;  alias, 1 drivers
+L_0000000004006070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f300_0 .net8 "VGND", 0 0, L_0000000004006070;  1 drivers, strength-aware
+L_0000000004006620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f3a0_0 .net8 "VNB", 0 0, L_0000000004006620;  1 drivers, strength-aware
+L_0000000004006ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a500c0_0 .net8 "VPB", 0 0, L_0000000004006ee0;  1 drivers, strength-aware
+L_0000000004006c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e2c0_0 .net8 "VPWR", 0 0, L_0000000004006c40;  1 drivers, strength-aware
+v0000000003a4f940_0 .net "Y", 0 0, L_0000000004133080;  alias, 1 drivers
+S_0000000003a34d20 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a339a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004132e50 .functor NOR 1, L_00000000041343c0, L_00000000041339b0, C4<0>, C4<0>;
+L_0000000004133080 .functor BUF 1, L_0000000004132e50, C4<0>, C4<0>, C4<0>;
+v0000000003a4f120_0 .net "A", 0 0, L_00000000041343c0;  alias, 1 drivers
+v0000000003a505c0_0 .net "B", 0 0, L_00000000041339b0;  alias, 1 drivers
+L_0000000004005c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4ecc0_0 .net8 "VGND", 0 0, L_0000000004005c80;  1 drivers, strength-aware
+L_00000000040068c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a508e0_0 .net8 "VNB", 0 0, L_00000000040068c0;  1 drivers, strength-aware
+L_0000000004006310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e220_0 .net8 "VPB", 0 0, L_0000000004006310;  1 drivers, strength-aware
+L_0000000004006690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4eea0_0 .net8 "VPWR", 0 0, L_0000000004006690;  1 drivers, strength-aware
+v0000000003a4ef40_0 .net "Y", 0 0, L_0000000004133080;  alias, 1 drivers
+v0000000003a4e680_0 .net "nor0_out_Y", 0 0, L_0000000004132e50;  1 drivers
+S_0000000003a348a0 .scope module, "_0696_" "sky130_fd_sc_hd__o221a_2" 3 1552, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a4e900_0 .net "A1", 0 0, L_0000000003f92820;  1 drivers
+v0000000003a4e9a0_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a4f440_0 .net "B1", 0 0, L_00000000041346d0;  alias, 1 drivers
+v0000000003a4f4e0_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000003a4ea40_0 .net "C1", 0 0, L_0000000004133160;  alias, 1 drivers
+L_0000000004006f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f580_0 .net8 "VGND", 0 0, L_0000000004006f50;  1 drivers, strength-aware
+L_00000000040060e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4eae0_0 .net8 "VNB", 0 0, L_00000000040060e0;  1 drivers, strength-aware
+L_0000000004005dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4eb80_0 .net8 "VPB", 0 0, L_0000000004005dd0;  1 drivers, strength-aware
+L_00000000040057b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4f800_0 .net8 "VPWR", 0 0, L_00000000040057b0;  1 drivers, strength-aware
+v0000000003a50ca0_0 .net "X", 0 0, L_0000000004133cc0;  alias, 1 drivers
+S_0000000003a342a0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a348a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004133710 .functor OR 1, L_000000000412c1d0, L_00000000041346d0, C4<0>, C4<0>;
+L_0000000004133860 .functor OR 1, L_000000000412d0b0, L_0000000003f92820, C4<0>, C4<0>;
+L_0000000004133c50 .functor AND 1, L_0000000004133710, L_0000000004133860, L_0000000004133160, C4<1>;
+L_0000000004133cc0 .functor BUF 1, L_0000000004133c50, C4<0>, C4<0>, C4<0>;
+v0000000003a50160_0 .net "A1", 0 0, L_0000000003f92820;  alias, 1 drivers
+v0000000003a50840_0 .net "A2", 0 0, L_000000000412d0b0;  alias, 1 drivers
+v0000000003a50200_0 .net "B1", 0 0, L_00000000041346d0;  alias, 1 drivers
+v0000000003a50660_0 .net "B2", 0 0, L_000000000412c1d0;  alias, 1 drivers
+v0000000003a4e180_0 .net "C1", 0 0, L_0000000004133160;  alias, 1 drivers
+L_0000000004006700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e360_0 .net8 "VGND", 0 0, L_0000000004006700;  1 drivers, strength-aware
+L_0000000004006150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a50340_0 .net8 "VNB", 0 0, L_0000000004006150;  1 drivers, strength-aware
+L_0000000004005510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a4e400_0 .net8 "VPB", 0 0, L_0000000004005510;  1 drivers, strength-aware
+L_00000000040059e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a502a0_0 .net8 "VPWR", 0 0, L_00000000040059e0;  1 drivers, strength-aware
+v0000000003a4f8a0_0 .net "X", 0 0, L_0000000004133cc0;  alias, 1 drivers
+v0000000003a4e860_0 .net "and0_out_X", 0 0, L_0000000004133c50;  1 drivers
+v0000000003a4e720_0 .net "or0_out", 0 0, L_0000000004133710;  1 drivers
+v0000000003a4e7c0_0 .net "or1_out", 0 0, L_0000000004133860;  1 drivers
+S_0000000003a34ea0 .scope module, "_0697_" "sky130_fd_sc_hd__nor2_2" 3 1560, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a51600_0 .net "A", 0 0, L_00000000041339b0;  alias, 1 drivers
+v0000000003a51ce0_0 .net "B", 0 0, L_0000000004133cc0;  alias, 1 drivers
+L_0000000004005ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a50e80_0 .net8 "VGND", 0 0, L_0000000004005ac0;  1 drivers, strength-aware
+L_00000000040061c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52000_0 .net8 "VNB", 0 0, L_00000000040061c0;  1 drivers, strength-aware
+L_00000000040054a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a50f20_0 .net8 "VPB", 0 0, L_00000000040054a0;  1 drivers, strength-aware
+L_0000000004005890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a51880_0 .net8 "VPWR", 0 0, L_0000000004005890;  1 drivers, strength-aware
+v0000000003a52aa0_0 .net "Y", 0 0, L_0000000004133da0;  alias, 1 drivers
+S_0000000003a345a0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a34ea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004133400 .functor NOR 1, L_00000000041339b0, L_0000000004133cc0, C4<0>, C4<0>;
+L_0000000004133da0 .functor BUF 1, L_0000000004133400, C4<0>, C4<0>, C4<0>;
+v0000000003a52280_0 .net "A", 0 0, L_00000000041339b0;  alias, 1 drivers
+v0000000003a52780_0 .net "B", 0 0, L_0000000004133cc0;  alias, 1 drivers
+L_00000000040063f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52320_0 .net8 "VGND", 0 0, L_00000000040063f0;  1 drivers, strength-aware
+L_0000000004005d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52140_0 .net8 "VNB", 0 0, L_0000000004005d60;  1 drivers, strength-aware
+L_0000000004006930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a51d80_0 .net8 "VPB", 0 0, L_0000000004006930;  1 drivers, strength-aware
+L_0000000004005eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a51c40_0 .net8 "VPWR", 0 0, L_0000000004005eb0;  1 drivers, strength-aware
+v0000000003a526e0_0 .net "Y", 0 0, L_0000000004133da0;  alias, 1 drivers
+v0000000003a51380_0 .net "nor0_out_Y", 0 0, L_0000000004133400;  1 drivers
+S_0000000003a92bf0 .scope module, "_0698_" "sky130_fd_sc_hd__inv_2" 3 1565, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a525a0_0 .net "A", 0 0, L_0000000003f94300;  1 drivers
+L_0000000004006230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52640_0 .net8 "VGND", 0 0, L_0000000004006230;  1 drivers, strength-aware
+L_0000000004006b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a523c0_0 .net8 "VNB", 0 0, L_0000000004006b60;  1 drivers, strength-aware
+L_0000000004006fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a52fa0_0 .net8 "VPB", 0 0, L_0000000004006fc0;  1 drivers, strength-aware
+L_0000000004005580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a52460_0 .net8 "VPWR", 0 0, L_0000000004005580;  1 drivers, strength-aware
+v0000000003a52d20_0 .net "Y", 0 0, L_00000000041330f0;  alias, 1 drivers
+S_0000000003a92ef0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a92bf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041338d0 .functor NOT 1, L_0000000003f94300, C4<0>, C4<0>, C4<0>;
+L_00000000041330f0 .functor BUF 1, L_00000000041338d0, C4<0>, C4<0>, C4<0>;
+v0000000003a50980_0 .net "A", 0 0, L_0000000003f94300;  alias, 1 drivers
+L_0000000004005820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a521e0_0 .net8 "VGND", 0 0, L_0000000004005820;  1 drivers, strength-aware
+L_0000000004007030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a51e20_0 .net8 "VNB", 0 0, L_0000000004007030;  1 drivers, strength-aware
+L_0000000004005b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a52a00_0 .net8 "VPB", 0 0, L_0000000004005b30;  1 drivers, strength-aware
+L_0000000004005ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a52be0_0 .net8 "VPWR", 0 0, L_0000000004005ba0;  1 drivers, strength-aware
+v0000000003a51060_0 .net "Y", 0 0, L_00000000041330f0;  alias, 1 drivers
+v0000000003a52b40_0 .net "not0_out_Y", 0 0, L_00000000041338d0;  1 drivers
+S_0000000003a8f770 .scope module, "_0699_" "sky130_fd_sc_hd__a2bb2o_2" 3 1569, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a52dc0_0 .net "A1_N", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a517e0_0 .net "A2_N", 0 0, L_0000000003f944e0;  1 drivers
+v0000000003a50a20_0 .net "B1", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a516a0_0 .net "B2", 0 0, L_0000000003f939a0;  1 drivers
+L_00000000040055f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52e60_0 .net8 "VGND", 0 0, L_00000000040055f0;  1 drivers, strength-aware
+L_0000000004006a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a51100_0 .net8 "VNB", 0 0, L_0000000004006a80;  1 drivers, strength-aware
+L_0000000004005c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a50ac0_0 .net8 "VPB", 0 0, L_0000000004005c10;  1 drivers, strength-aware
+L_0000000004006af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a51a60_0 .net8 "VPWR", 0 0, L_0000000004006af0;  1 drivers, strength-aware
+v0000000003a51ec0_0 .net "X", 0 0, L_0000000004132de0;  alias, 1 drivers
+S_0000000003a90370 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a8f770;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004133d30 .functor AND 1, L_0000000004127a10, L_0000000003f939a0, C4<1>, C4<1>;
+L_0000000004133a90 .functor NOR 1, L_0000000004127a10, L_0000000003f944e0, C4<0>, C4<0>;
+L_0000000004133e10 .functor OR 1, L_0000000004133a90, L_0000000004133d30, C4<0>, C4<0>;
+L_0000000004132de0 .functor BUF 1, L_0000000004133e10, C4<0>, C4<0>, C4<0>;
+v0000000003a512e0_0 .net "A1_N", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a52500_0 .net "A2_N", 0 0, L_0000000003f944e0;  alias, 1 drivers
+v0000000003a50fc0_0 .net "B1", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a51920_0 .net "B2", 0 0, L_0000000003f939a0;  alias, 1 drivers
+L_0000000004006460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52820_0 .net8 "VGND", 0 0, L_0000000004006460;  1 drivers, strength-aware
+L_0000000004005660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a52f00_0 .net8 "VNB", 0 0, L_0000000004005660;  1 drivers, strength-aware
+L_00000000040056d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a519c0_0 .net8 "VPB", 0 0, L_00000000040056d0;  1 drivers, strength-aware
+L_0000000004005900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a528c0_0 .net8 "VPWR", 0 0, L_0000000004005900;  1 drivers, strength-aware
+v0000000003a51740_0 .net "X", 0 0, L_0000000004132de0;  alias, 1 drivers
+v0000000003a52960_0 .net "and0_out", 0 0, L_0000000004133d30;  1 drivers
+v0000000003a51560_0 .net "nor0_out", 0 0, L_0000000004133a90;  1 drivers
+v0000000003a52c80_0 .net "or0_out_X", 0 0, L_0000000004133e10;  1 drivers
+S_0000000003a91b70 .scope module, "_0700_" "sky130_fd_sc_hd__o221a_2" 3 1576, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a514c0_0 .net "A1", 0 0, L_0000000003f93180;  1 drivers
+v0000000003a54c60_0 .net "A2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a54d00_0 .net "B1", 0 0, L_00000000041330f0;  alias, 1 drivers
+v0000000003a55480_0 .net "B2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a54760_0 .net "C1", 0 0, L_0000000004132de0;  alias, 1 drivers
+L_0000000004005cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55840_0 .net8 "VGND", 0 0, L_0000000004005cf0;  1 drivers, strength-aware
+L_00000000040064d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53860_0 .net8 "VNB", 0 0, L_00000000040064d0;  1 drivers, strength-aware
+L_0000000004006540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a541c0_0 .net8 "VPB", 0 0, L_0000000004006540;  1 drivers, strength-aware
+L_00000000040067e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a558e0_0 .net8 "VPWR", 0 0, L_00000000040067e0;  1 drivers, strength-aware
+v0000000003a55520_0 .net "X", 0 0, L_00000000041336a0;  alias, 1 drivers
+S_0000000003a8fd70 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a91b70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004133e80 .functor OR 1, L_00000000041270e0, L_00000000041330f0, C4<0>, C4<0>;
+L_0000000004133630 .functor OR 1, L_00000000041265f0, L_0000000003f93180, C4<0>, C4<0>;
+L_0000000004133240 .functor AND 1, L_0000000004133e80, L_0000000004133630, L_0000000004132de0, C4<1>;
+L_00000000041336a0 .functor BUF 1, L_0000000004133240, C4<0>, C4<0>, C4<0>;
+v0000000003a50de0_0 .net "A1", 0 0, L_0000000003f93180;  alias, 1 drivers
+v0000000003a50b60_0 .net "A2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a51b00_0 .net "B1", 0 0, L_00000000041330f0;  alias, 1 drivers
+v0000000003a511a0_0 .net "B2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a51ba0_0 .net "C1", 0 0, L_0000000004132de0;  alias, 1 drivers
+L_0000000004006770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a50c00_0 .net8 "VGND", 0 0, L_0000000004006770;  1 drivers, strength-aware
+L_00000000040084c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a50d40_0 .net8 "VNB", 0 0, L_00000000040084c0;  1 drivers, strength-aware
+L_0000000004007dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a51f60_0 .net8 "VPB", 0 0, L_0000000004007dc0;  1 drivers, strength-aware
+L_0000000004007880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a53040_0 .net8 "VPWR", 0 0, L_0000000004007880;  1 drivers, strength-aware
+v0000000003a530e0_0 .net "X", 0 0, L_00000000041336a0;  alias, 1 drivers
+v0000000003a51240_0 .net "and0_out_X", 0 0, L_0000000004133240;  1 drivers
+v0000000003a51420_0 .net "or0_out", 0 0, L_0000000004133e80;  1 drivers
+v0000000003a520a0_0 .net "or1_out", 0 0, L_0000000004133630;  1 drivers
+S_0000000003a90af0 .scope module, "_0701_" "sky130_fd_sc_hd__or2_2" 3 1584, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a53d60_0 .net "A", 0 0, L_0000000004133da0;  alias, 1 drivers
+v0000000003a53900_0 .net "B", 0 0, L_00000000041336a0;  alias, 1 drivers
+L_0000000004007a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a553e0_0 .net8 "VGND", 0 0, L_0000000004007a40;  1 drivers, strength-aware
+L_0000000004008450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a54f80_0 .net8 "VNB", 0 0, L_0000000004008450;  1 drivers, strength-aware
+L_00000000040079d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a54da0_0 .net8 "VPB", 0 0, L_00000000040079d0;  1 drivers, strength-aware
+L_0000000004007730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a53b80_0 .net8 "VPWR", 0 0, L_0000000004007730;  1 drivers, strength-aware
+v0000000003a53e00_0 .net "X", 0 0, L_00000000041344a0;  alias, 1 drivers
+S_0000000003a8f470 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a90af0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004133940 .functor OR 1, L_00000000041336a0, L_0000000004133da0, C4<0>, C4<0>;
+L_00000000041344a0 .functor BUF 1, L_0000000004133940, C4<0>, C4<0>, C4<0>;
+v0000000003a546c0_0 .net "A", 0 0, L_0000000004133da0;  alias, 1 drivers
+v0000000003a534a0_0 .net "B", 0 0, L_00000000041336a0;  alias, 1 drivers
+L_0000000004008760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53c20_0 .net8 "VGND", 0 0, L_0000000004008760;  1 drivers, strength-aware
+L_0000000004008300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53cc0_0 .net8 "VNB", 0 0, L_0000000004008300;  1 drivers, strength-aware
+L_0000000004007b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a555c0_0 .net8 "VPB", 0 0, L_0000000004007b20;  1 drivers, strength-aware
+L_00000000040086f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a54ee0_0 .net8 "VPWR", 0 0, L_00000000040086f0;  1 drivers, strength-aware
+v0000000003a54440_0 .net "X", 0 0, L_00000000041344a0;  alias, 1 drivers
+v0000000003a53540_0 .net "or0_out_X", 0 0, L_0000000004133940;  1 drivers
+S_0000000003a91870 .scope module, "_0702_" "sky130_fd_sc_hd__inv_2" 3 1589, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a54300_0 .net "A", 0 0, L_00000000041344a0;  alias, 1 drivers
+L_0000000004007ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55700_0 .net8 "VGND", 0 0, L_0000000004007ce0;  1 drivers, strength-aware
+L_00000000040076c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53f40_0 .net8 "VNB", 0 0, L_00000000040076c0;  1 drivers, strength-aware
+L_00000000040077a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a53fe0_0 .net8 "VPB", 0 0, L_00000000040077a0;  1 drivers, strength-aware
+L_00000000040075e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a54e40_0 .net8 "VPWR", 0 0, L_00000000040075e0;  1 drivers, strength-aware
+v0000000003a54080_0 .net "Y", 0 0, L_0000000004134820;  alias, 1 drivers
+S_0000000003a8d1f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a91870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004133a20 .functor NOT 1, L_00000000041344a0, C4<0>, C4<0>, C4<0>;
+L_0000000004134820 .functor BUF 1, L_0000000004133a20, C4<0>, C4<0>, C4<0>;
+v0000000003a53ea0_0 .net "A", 0 0, L_00000000041344a0;  alias, 1 drivers
+L_00000000040071f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a54bc0_0 .net8 "VGND", 0 0, L_00000000040071f0;  1 drivers, strength-aware
+L_0000000004007e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a54800_0 .net8 "VNB", 0 0, L_0000000004007e30;  1 drivers, strength-aware
+L_0000000004007ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a55660_0 .net8 "VPB", 0 0, L_0000000004007ab0;  1 drivers, strength-aware
+L_0000000004008290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a532c0_0 .net8 "VPWR", 0 0, L_0000000004008290;  1 drivers, strength-aware
+v0000000003a55200_0 .net "Y", 0 0, L_0000000004134820;  alias, 1 drivers
+v0000000003a539a0_0 .net "not0_out_Y", 0 0, L_0000000004133a20;  1 drivers
+S_0000000003a8f2f0 .scope module, "_0703_" "sky130_fd_sc_hd__or2_2" 3 1593, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a55160_0 .net "A", 0 0, L_00000000041335c0;  alias, 1 drivers
+v0000000003a552a0_0 .net "B", 0 0, L_00000000041347b0;  alias, 1 drivers
+L_0000000004008b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53400_0 .net8 "VGND", 0 0, L_0000000004008b50;  1 drivers, strength-aware
+L_00000000040088b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53a40_0 .net8 "VNB", 0 0, L_00000000040088b0;  1 drivers, strength-aware
+L_0000000004007340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a55340_0 .net8 "VPB", 0 0, L_0000000004007340;  1 drivers, strength-aware
+L_0000000004008990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a53680_0 .net8 "VPWR", 0 0, L_0000000004008990;  1 drivers, strength-aware
+v0000000003a53720_0 .net "X", 0 0, L_00000000041340b0;  alias, 1 drivers
+S_0000000003a91570 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a8f2f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004133ef0 .functor OR 1, L_00000000041347b0, L_00000000041335c0, C4<0>, C4<0>;
+L_00000000041340b0 .functor BUF 1, L_0000000004133ef0, C4<0>, C4<0>, C4<0>;
+v0000000003a53180_0 .net "A", 0 0, L_00000000041335c0;  alias, 1 drivers
+v0000000003a55020_0 .net "B", 0 0, L_00000000041347b0;  alias, 1 drivers
+L_00000000040070a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a53220_0 .net8 "VGND", 0 0, L_00000000040070a0;  1 drivers, strength-aware
+L_0000000004007d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a535e0_0 .net8 "VNB", 0 0, L_0000000004007d50;  1 drivers, strength-aware
+L_0000000004008530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a548a0_0 .net8 "VPB", 0 0, L_0000000004008530;  1 drivers, strength-aware
+L_0000000004007260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a550c0_0 .net8 "VPWR", 0 0, L_0000000004007260;  1 drivers, strength-aware
+v0000000003a557a0_0 .net "X", 0 0, L_00000000041340b0;  alias, 1 drivers
+v0000000003a53360_0 .net "or0_out_X", 0 0, L_0000000004133ef0;  1 drivers
+S_0000000003a90c70 .scope module, "_0704_" "sky130_fd_sc_hd__o21a_2" 3 1598, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a54620_0 .net "A1", 0 0, L_0000000004133080;  alias, 1 drivers
+v0000000003a54940_0 .net "A2", 0 0, L_0000000004134820;  alias, 1 drivers
+v0000000003a567e0_0 .net "B1", 0 0, L_00000000041340b0;  alias, 1 drivers
+L_0000000004007ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57500_0 .net8 "VGND", 0 0, L_0000000004007ea0;  1 drivers, strength-aware
+L_0000000004008370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55f20_0 .net8 "VNB", 0 0, L_0000000004008370;  1 drivers, strength-aware
+L_00000000040083e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a57a00_0 .net8 "VPB", 0 0, L_00000000040083e0;  1 drivers, strength-aware
+L_0000000004007b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56ba0_0 .net8 "VPWR", 0 0, L_0000000004007b90;  1 drivers, strength-aware
+v0000000003a571e0_0 .net "X", 0 0, L_0000000004134190;  alias, 1 drivers
+S_0000000003a92770 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a90c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041331d0 .functor OR 1, L_0000000004134820, L_0000000004133080, C4<0>, C4<0>;
+L_0000000004134120 .functor AND 1, L_00000000041331d0, L_00000000041340b0, C4<1>, C4<1>;
+L_0000000004134190 .functor BUF 1, L_0000000004134120, C4<0>, C4<0>, C4<0>;
+v0000000003a537c0_0 .net "A1", 0 0, L_0000000004133080;  alias, 1 drivers
+v0000000003a53ae0_0 .net "A2", 0 0, L_0000000004134820;  alias, 1 drivers
+v0000000003a54120_0 .net "B1", 0 0, L_00000000041340b0;  alias, 1 drivers
+L_00000000040078f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a54a80_0 .net8 "VGND", 0 0, L_00000000040078f0;  1 drivers, strength-aware
+L_0000000004008680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a54260_0 .net8 "VNB", 0 0, L_0000000004008680;  1 drivers, strength-aware
+L_0000000004007810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a543a0_0 .net8 "VPB", 0 0, L_0000000004007810;  1 drivers, strength-aware
+L_0000000004008a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a544e0_0 .net8 "VPWR", 0 0, L_0000000004008a00;  1 drivers, strength-aware
+v0000000003a54580_0 .net "X", 0 0, L_0000000004134190;  alias, 1 drivers
+v0000000003a54b20_0 .net "and0_out_X", 0 0, L_0000000004134120;  1 drivers
+v0000000003a549e0_0 .net "or0_out", 0 0, L_00000000041331d0;  1 drivers
+S_0000000003a8d070 .scope module, "_0705_" "sky130_fd_sc_hd__or2_2" 3 1604, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a55de0_0 .net "A", 0 0, L_0000000004134580;  alias, 1 drivers
+v0000000003a576e0_0 .net "B", 0 0, L_0000000004134190;  alias, 1 drivers
+L_00000000040081b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a56b00_0 .net8 "VGND", 0 0, L_00000000040081b0;  1 drivers, strength-aware
+L_00000000040087d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55e80_0 .net8 "VNB", 0 0, L_00000000040087d0;  1 drivers, strength-aware
+L_0000000004007960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56920_0 .net8 "VPB", 0 0, L_0000000004007960;  1 drivers, strength-aware
+L_0000000004007c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a55fc0_0 .net8 "VPWR", 0 0, L_0000000004007c00;  1 drivers, strength-aware
+v0000000003a57dc0_0 .net "X", 0 0, L_0000000004134430;  alias, 1 drivers
+S_0000000003a90970 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a8d070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004133f60 .functor OR 1, L_0000000004134190, L_0000000004134580, C4<0>, C4<0>;
+L_0000000004134430 .functor BUF 1, L_0000000004133f60, C4<0>, C4<0>, C4<0>;
+v0000000003a55980_0 .net "A", 0 0, L_0000000004134580;  alias, 1 drivers
+v0000000003a57280_0 .net "B", 0 0, L_0000000004134190;  alias, 1 drivers
+L_0000000004008840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57780_0 .net8 "VGND", 0 0, L_0000000004008840;  1 drivers, strength-aware
+L_00000000040072d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57320_0 .net8 "VNB", 0 0, L_00000000040072d0;  1 drivers, strength-aware
+L_0000000004007c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56060_0 .net8 "VPB", 0 0, L_0000000004007c70;  1 drivers, strength-aware
+L_0000000004008920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56d80_0 .net8 "VPWR", 0 0, L_0000000004008920;  1 drivers, strength-aware
+v0000000003a55c00_0 .net "X", 0 0, L_0000000004134430;  alias, 1 drivers
+v0000000003a56c40_0 .net "or0_out_X", 0 0, L_0000000004133f60;  1 drivers
+S_0000000003a91cf0 .scope module, "_0706_" "sky130_fd_sc_hd__a221oi_2" 3 1609, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a56740_0 .net "A1", 0 0, L_00000000041330f0;  alias, 1 drivers
+v0000000003a57460_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a569c0_0 .net "B1", 0 0, L_0000000003f93040;  1 drivers
+v0000000003a561a0_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a56f60_0 .net "C1", 0 0, L_0000000004132de0;  alias, 1 drivers
+L_0000000004007f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55ac0_0 .net8 "VGND", 0 0, L_0000000004007f10;  1 drivers, strength-aware
+L_0000000004007f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a56420_0 .net8 "VNB", 0 0, L_0000000004007f80;  1 drivers, strength-aware
+L_0000000004008220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56560_0 .net8 "VPB", 0 0, L_0000000004008220;  1 drivers, strength-aware
+L_0000000004007570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a575a0_0 .net8 "VPWR", 0 0, L_0000000004007570;  1 drivers, strength-aware
+v0000000003a57000_0 .net "Y", 0 0, L_00000000041334e0;  alias, 1 drivers
+S_0000000003a92d70 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a91cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004133390 .functor AND 1, L_0000000003f93040, L_00000000041271c0, C4<1>, C4<1>;
+L_0000000004133470 .functor AND 1, L_00000000041330f0, L_0000000004126660, C4<1>, C4<1>;
+L_0000000004134200 .functor NOR 1, L_0000000004133390, L_0000000004132de0, L_0000000004133470, C4<0>;
+L_00000000041334e0 .functor BUF 1, L_0000000004134200, C4<0>, C4<0>, C4<0>;
+v0000000003a57d20_0 .net "A1", 0 0, L_00000000041330f0;  alias, 1 drivers
+v0000000003a56ce0_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a58040_0 .net "B1", 0 0, L_0000000003f93040;  alias, 1 drivers
+v0000000003a56e20_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a56ec0_0 .net "C1", 0 0, L_0000000004132de0;  alias, 1 drivers
+L_0000000004008bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57c80_0 .net8 "VGND", 0 0, L_0000000004008bc0;  1 drivers, strength-aware
+L_00000000040073b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a56100_0 .net8 "VNB", 0 0, L_00000000040073b0;  1 drivers, strength-aware
+L_0000000004008c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a580e0_0 .net8 "VPB", 0 0, L_0000000004008c30;  1 drivers, strength-aware
+L_00000000040085a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56880_0 .net8 "VPWR", 0 0, L_00000000040085a0;  1 drivers, strength-aware
+v0000000003a55a20_0 .net "Y", 0 0, L_00000000041334e0;  alias, 1 drivers
+v0000000003a57e60_0 .net "and0_out", 0 0, L_0000000004133390;  1 drivers
+v0000000003a573c0_0 .net "and1_out", 0 0, L_0000000004133470;  1 drivers
+v0000000003a566a0_0 .net "nor0_out_Y", 0 0, L_0000000004134200;  1 drivers
+S_0000000003a91e70 .scope module, "_0707_" "sky130_fd_sc_hd__or2_2" 3 1617, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a56240_0 .net "A", 0 0, L_00000000041336a0;  alias, 1 drivers
+v0000000003a55ca0_0 .net "B", 0 0, L_00000000041334e0;  alias, 1 drivers
+L_0000000004007ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57b40_0 .net8 "VGND", 0 0, L_0000000004007ff0;  1 drivers, strength-aware
+L_0000000004008a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a570a0_0 .net8 "VNB", 0 0, L_0000000004008a70;  1 drivers, strength-aware
+L_0000000004008060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a564c0_0 .net8 "VPB", 0 0, L_0000000004008060;  1 drivers, strength-aware
+L_0000000004007490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a562e0_0 .net8 "VPWR", 0 0, L_0000000004007490;  1 drivers, strength-aware
+v0000000003a56380_0 .net "X", 0 0, L_0000000004133fd0;  alias, 1 drivers
+S_0000000003a8e6f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a91e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004134510 .functor OR 1, L_00000000041334e0, L_00000000041336a0, C4<0>, C4<0>;
+L_0000000004133fd0 .functor BUF 1, L_0000000004134510, C4<0>, C4<0>, C4<0>;
+v0000000003a57f00_0 .net "A", 0 0, L_00000000041336a0;  alias, 1 drivers
+v0000000003a57aa0_0 .net "B", 0 0, L_00000000041334e0;  alias, 1 drivers
+L_0000000004007420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55b60_0 .net8 "VGND", 0 0, L_0000000004007420;  1 drivers, strength-aware
+L_0000000004007650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a57820_0 .net8 "VNB", 0 0, L_0000000004007650;  1 drivers, strength-aware
+L_0000000004007500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a57640_0 .net8 "VPB", 0 0, L_0000000004007500;  1 drivers, strength-aware
+L_00000000040080d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a578c0_0 .net8 "VPWR", 0 0, L_00000000040080d0;  1 drivers, strength-aware
+v0000000003a57960_0 .net "X", 0 0, L_0000000004133fd0;  alias, 1 drivers
+v0000000003a57fa0_0 .net "or0_out_X", 0 0, L_0000000004134510;  1 drivers
+S_0000000003a8f5f0 .scope module, "_0708_" "sky130_fd_sc_hd__inv_2" 3 1622, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a58540_0 .net "A", 0 0, L_0000000004133fd0;  alias, 1 drivers
+L_0000000004008ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a594e0_0 .net8 "VGND", 0 0, L_0000000004008ae0;  1 drivers, strength-aware
+L_0000000004007110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a59940_0 .net8 "VNB", 0 0, L_0000000004007110;  1 drivers, strength-aware
+L_0000000004007180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a58680_0 .net8 "VPB", 0 0, L_0000000004007180;  1 drivers, strength-aware
+L_0000000004008140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a58180_0 .net8 "VPWR", 0 0, L_0000000004008140;  1 drivers, strength-aware
+v0000000003a59a80_0 .net "Y", 0 0, L_0000000004134b30;  alias, 1 drivers
+S_0000000003a8e570 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a8f5f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004134660 .functor NOT 1, L_0000000004133fd0, C4<0>, C4<0>, C4<0>;
+L_0000000004134b30 .functor BUF 1, L_0000000004134660, C4<0>, C4<0>, C4<0>;
+v0000000003a57be0_0 .net "A", 0 0, L_0000000004133fd0;  alias, 1 drivers
+L_0000000004008610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a56600_0 .net8 "VGND", 0 0, L_0000000004008610;  1 drivers, strength-aware
+L_0000000004008e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a55d40_0 .net8 "VNB", 0 0, L_0000000004008e60;  1 drivers, strength-aware
+L_0000000004008ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a56a60_0 .net8 "VPB", 0 0, L_0000000004008ed0;  1 drivers, strength-aware
+L_0000000004008d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a57140_0 .net8 "VPWR", 0 0, L_0000000004008d10;  1 drivers, strength-aware
+v0000000003a5a020_0 .net "Y", 0 0, L_0000000004134b30;  alias, 1 drivers
+v0000000003a584a0_0 .net "not0_out_Y", 0 0, L_0000000004134660;  1 drivers
+S_0000000003a90df0 .scope module, "_0709_" "sky130_fd_sc_hd__inv_2" 3 1626, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a5a5c0_0 .net "A", 0 0, L_0000000003f925a0;  1 drivers
+L_0000000004008ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a2a0_0 .net8 "VGND", 0 0, L_0000000004008ca0;  1 drivers, strength-aware
+L_0000000004008d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a0c0_0 .net8 "VNB", 0 0, L_0000000004008d80;  1 drivers, strength-aware
+L_0000000004008df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a59b20_0 .net8 "VPB", 0 0, L_0000000004008df0;  1 drivers, strength-aware
+L_0000000004008f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a585e0_0 .net8 "VPWR", 0 0, L_0000000004008f40;  1 drivers, strength-aware
+v0000000003a5a8e0_0 .net "Y", 0 0, L_00000000041351c0;  alias, 1 drivers
+S_0000000003a90f70 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a90df0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004135700 .functor NOT 1, L_0000000003f925a0, C4<0>, C4<0>, C4<0>;
+L_00000000041351c0 .functor BUF 1, L_0000000004135700, C4<0>, C4<0>, C4<0>;
+v0000000003a59440_0 .net "A", 0 0, L_0000000003f925a0;  alias, 1 drivers
+L_000000000400b7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a582c0_0 .net8 "VGND", 0 0, L_000000000400b7a0;  1 drivers, strength-aware
+L_000000000400bdc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a58fe0_0 .net8 "VNB", 0 0, L_000000000400bdc0;  1 drivers, strength-aware
+L_000000000400b2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a59ee0_0 .net8 "VPB", 0 0, L_000000000400b2d0;  1 drivers, strength-aware
+L_000000000400b1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a59300_0 .net8 "VPWR", 0 0, L_000000000400b1f0;  1 drivers, strength-aware
+v0000000003a58720_0 .net "Y", 0 0, L_00000000041351c0;  alias, 1 drivers
+v0000000003a59120_0 .net "not0_out_Y", 0 0, L_0000000004135700;  1 drivers
+S_0000000003a8d370 .scope module, "_0710_" "sky130_fd_sc_hd__a2bb2o_2" 3 1630, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a58900_0 .net "A1_N", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a58c20_0 .net "A2_N", 0 0, L_0000000003f94120;  1 drivers
+v0000000003a58cc0_0 .net "B1", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a5a660_0 .net "B2", 0 0, L_0000000003f923c0;  1 drivers
+L_000000000400ae00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a59580_0 .net8 "VGND", 0 0, L_000000000400ae00;  1 drivers, strength-aware
+L_000000000400ba40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a59620_0 .net8 "VNB", 0 0, L_000000000400ba40;  1 drivers, strength-aware
+L_000000000400b5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a589a0_0 .net8 "VPB", 0 0, L_000000000400b5e0;  1 drivers, strength-aware
+L_000000000400bea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a59c60_0 .net8 "VPWR", 0 0, L_000000000400bea0;  1 drivers, strength-aware
+v0000000003a58400_0 .net "X", 0 0, L_0000000004135380;  alias, 1 drivers
+S_0000000003a8fa70 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a8d370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041353f0 .functor AND 1, L_0000000004126430, L_0000000003f923c0, C4<1>, C4<1>;
+L_0000000004134f20 .functor NOR 1, L_0000000004126430, L_0000000003f94120, C4<0>, C4<0>;
+L_0000000004134dd0 .functor OR 1, L_0000000004134f20, L_00000000041353f0, C4<0>, C4<0>;
+L_0000000004135380 .functor BUF 1, L_0000000004134dd0, C4<0>, C4<0>, C4<0>;
+v0000000003a5a480_0 .net "A1_N", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a587c0_0 .net "A2_N", 0 0, L_0000000003f94120;  alias, 1 drivers
+v0000000003a58860_0 .net "B1", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a591c0_0 .net "B2", 0 0, L_0000000003f923c0;  alias, 1 drivers
+L_000000000400c760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a58220_0 .net8 "VGND", 0 0, L_000000000400c760;  1 drivers, strength-aware
+L_000000000400c4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a520_0 .net8 "VNB", 0 0, L_000000000400c4c0;  1 drivers, strength-aware
+L_000000000400af50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a58f40_0 .net8 "VPB", 0 0, L_000000000400af50;  1 drivers, strength-aware
+L_000000000400c5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a58360_0 .net8 "VPWR", 0 0, L_000000000400c5a0;  1 drivers, strength-aware
+v0000000003a5a160_0 .net "X", 0 0, L_0000000004135380;  alias, 1 drivers
+v0000000003a599e0_0 .net "and0_out", 0 0, L_00000000041353f0;  1 drivers
+v0000000003a59bc0_0 .net "nor0_out", 0 0, L_0000000004134f20;  1 drivers
+v0000000003a59080_0 .net "or0_out_X", 0 0, L_0000000004134dd0;  1 drivers
+S_0000000003a919f0 .scope module, "_0711_" "sky130_fd_sc_hd__a221o_2" 3 1637, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a593a0_0 .net "A1", 0 0, L_00000000041351c0;  alias, 1 drivers
+v0000000003a59760_0 .net "A2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a5a7a0_0 .net "B1", 0 0, L_0000000003f92640;  1 drivers
+v0000000003a598a0_0 .net "B2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a59da0_0 .net "C1", 0 0, L_0000000004135380;  alias, 1 drivers
+L_000000000400acb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a59e40_0 .net8 "VGND", 0 0, L_000000000400acb0;  1 drivers, strength-aware
+L_000000000400b8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a340_0 .net8 "VNB", 0 0, L_000000000400b8f0;  1 drivers, strength-aware
+L_000000000400c140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a3e0_0 .net8 "VPB", 0 0, L_000000000400c140;  1 drivers, strength-aware
+L_000000000400ae70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a840_0 .net8 "VPWR", 0 0, L_000000000400ae70;  1 drivers, strength-aware
+v0000000003a5af20_0 .net "X", 0 0, L_0000000004135150;  alias, 1 drivers
+S_0000000003a922f0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a919f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004134e40 .functor AND 1, L_0000000003f92640, L_00000000041265f0, C4<1>, C4<1>;
+L_0000000004134cf0 .functor AND 1, L_00000000041351c0, L_00000000041270e0, C4<1>, C4<1>;
+L_0000000004135e00 .functor OR 1, L_0000000004134cf0, L_0000000004134e40, L_0000000004135380, C4<0>;
+L_0000000004135150 .functor BUF 1, L_0000000004135e00, C4<0>, C4<0>, C4<0>;
+v0000000003a596c0_0 .net "A1", 0 0, L_00000000041351c0;  alias, 1 drivers
+v0000000003a58a40_0 .net "A2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a58ae0_0 .net "B1", 0 0, L_0000000003f92640;  alias, 1 drivers
+v0000000003a59f80_0 .net "B2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a58d60_0 .net "C1", 0 0, L_0000000004135380;  alias, 1 drivers
+L_000000000400bab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a58b80_0 .net8 "VGND", 0 0, L_000000000400bab0;  1 drivers, strength-aware
+L_000000000400b960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a59d00_0 .net8 "VNB", 0 0, L_000000000400b960;  1 drivers, strength-aware
+L_000000000400b650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5a200_0 .net8 "VPB", 0 0, L_000000000400b650;  1 drivers, strength-aware
+L_000000000400afc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a58e00_0 .net8 "VPWR", 0 0, L_000000000400afc0;  1 drivers, strength-aware
+v0000000003a59800_0 .net "X", 0 0, L_0000000004135150;  alias, 1 drivers
+v0000000003a58ea0_0 .net "and0_out", 0 0, L_0000000004134e40;  1 drivers
+v0000000003a5a700_0 .net "and1_out", 0 0, L_0000000004134cf0;  1 drivers
+v0000000003a59260_0 .net "or0_out_X", 0 0, L_0000000004135e00;  1 drivers
+S_0000000003a928f0 .scope module, "_0712_" "sky130_fd_sc_hd__inv_2" 3 1645, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a5cdc0_0 .net "A", 0 0, L_0000000004135150;  alias, 1 drivers
+L_000000000400be30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5bce0_0 .net8 "VGND", 0 0, L_000000000400be30;  1 drivers, strength-aware
+L_000000000400bf10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5bc40_0 .net8 "VNB", 0 0, L_000000000400bf10;  1 drivers, strength-aware
+L_000000000400c370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5bb00_0 .net8 "VPB", 0 0, L_000000000400c370;  1 drivers, strength-aware
+L_000000000400bf80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5cd20_0 .net8 "VPWR", 0 0, L_000000000400bf80;  1 drivers, strength-aware
+v0000000003a5b4c0_0 .net "Y", 0 0, L_0000000004135230;  alias, 1 drivers
+S_0000000003a8eff0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a928f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004136420 .functor NOT 1, L_0000000004135150, C4<0>, C4<0>, C4<0>;
+L_0000000004135230 .functor BUF 1, L_0000000004136420, C4<0>, C4<0>, C4<0>;
+v0000000003a5c460_0 .net "A", 0 0, L_0000000004135150;  alias, 1 drivers
+L_000000000400b730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c280_0 .net8 "VGND", 0 0, L_000000000400b730;  1 drivers, strength-aware
+L_000000000400b180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c3c0_0 .net8 "VNB", 0 0, L_000000000400b180;  1 drivers, strength-aware
+L_000000000400c530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b060_0 .net8 "VPB", 0 0, L_000000000400c530;  1 drivers, strength-aware
+L_000000000400b030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ade0_0 .net8 "VPWR", 0 0, L_000000000400b030;  1 drivers, strength-aware
+v0000000003a5a980_0 .net "Y", 0 0, L_0000000004135230;  alias, 1 drivers
+v0000000003a5b420_0 .net "not0_out_Y", 0 0, L_0000000004136420;  1 drivers
+S_0000000003a910f0 .scope module, "_0713_" "sky130_fd_sc_hd__or2_2" 3 1649, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a5cc80_0 .net "A", 0 0, L_0000000004134b30;  alias, 1 drivers
+v0000000003a5aac0_0 .net "B", 0 0, L_0000000004135230;  alias, 1 drivers
+L_000000000400bb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b560_0 .net8 "VGND", 0 0, L_000000000400bb90;  1 drivers, strength-aware
+L_000000000400c610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b100_0 .net8 "VNB", 0 0, L_000000000400c610;  1 drivers, strength-aware
+L_000000000400b810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b2e0_0 .net8 "VPB", 0 0, L_000000000400b810;  1 drivers, strength-aware
+L_000000000400c680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5cbe0_0 .net8 "VPWR", 0 0, L_000000000400c680;  1 drivers, strength-aware
+v0000000003a5cf00_0 .net "X", 0 0, L_00000000041352a0;  alias, 1 drivers
+S_0000000003a913f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a910f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004135930 .functor OR 1, L_0000000004135230, L_0000000004134b30, C4<0>, C4<0>;
+L_00000000041352a0 .functor BUF 1, L_0000000004135930, C4<0>, C4<0>, C4<0>;
+v0000000003a5bf60_0 .net "A", 0 0, L_0000000004134b30;  alias, 1 drivers
+v0000000003a5bd80_0 .net "B", 0 0, L_0000000004135230;  alias, 1 drivers
+L_000000000400c220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5aa20_0 .net8 "VGND", 0 0, L_000000000400c220;  1 drivers, strength-aware
+L_000000000400c1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5afc0_0 .net8 "VNB", 0 0, L_000000000400c1b0;  1 drivers, strength-aware
+L_000000000400c6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c640_0 .net8 "VPB", 0 0, L_000000000400c6f0;  1 drivers, strength-aware
+L_000000000400c3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d040_0 .net8 "VPWR", 0 0, L_000000000400c3e0;  1 drivers, strength-aware
+v0000000003a5b380_0 .net "X", 0 0, L_00000000041352a0;  alias, 1 drivers
+v0000000003a5c500_0 .net "or0_out_X", 0 0, L_0000000004135930;  1 drivers
+S_0000000003a8d4f0 .scope module, "_0714_" "sky130_fd_sc_hd__inv_2" 3 1654, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a5b600_0 .net "A", 0 0, L_00000000041352a0;  alias, 1 drivers
+L_000000000400b6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b240_0 .net8 "VGND", 0 0, L_000000000400b6c0;  1 drivers, strength-aware
+L_000000000400b880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ab60_0 .net8 "VNB", 0 0, L_000000000400b880;  1 drivers, strength-aware
+L_000000000400bb20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b880_0 .net8 "VPB", 0 0, L_000000000400bb20;  1 drivers, strength-aware
+L_000000000400c060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c1e0_0 .net8 "VPWR", 0 0, L_000000000400c060;  1 drivers, strength-aware
+v0000000003a5ac00_0 .net "Y", 0 0, L_00000000041361f0;  alias, 1 drivers
+S_0000000003a91270 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a8d4f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041363b0 .functor NOT 1, L_00000000041352a0, C4<0>, C4<0>, C4<0>;
+L_00000000041361f0 .functor BUF 1, L_00000000041363b0, C4<0>, C4<0>, C4<0>;
+v0000000003a5be20_0 .net "A", 0 0, L_00000000041352a0;  alias, 1 drivers
+L_000000000400c7d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ce60_0 .net8 "VGND", 0 0, L_000000000400c7d0;  1 drivers, strength-aware
+L_000000000400b260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c6e0_0 .net8 "VNB", 0 0, L_000000000400b260;  1 drivers, strength-aware
+L_000000000400b9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b1a0_0 .net8 "VPB", 0 0, L_000000000400b9d0;  1 drivers, strength-aware
+L_000000000400bff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d0e0_0 .net8 "VPWR", 0 0, L_000000000400bff0;  1 drivers, strength-aware
+v0000000003a5cfa0_0 .net "Y", 0 0, L_00000000041361f0;  alias, 1 drivers
+v0000000003a5bec0_0 .net "not0_out_Y", 0 0, L_00000000041363b0;  1 drivers
+S_0000000003a8eb70 .scope module, "_0715_" "sky130_fd_sc_hd__inv_2" 3 1658, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a5ae80_0 .net "A", 0 0, L_0000000003f92f00;  1 drivers
+L_000000000400c840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c320_0 .net8 "VGND", 0 0, L_000000000400c840;  1 drivers, strength-aware
+L_000000000400c450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c780_0 .net8 "VNB", 0 0, L_000000000400c450;  1 drivers, strength-aware
+L_000000000400b490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5c5a0_0 .net8 "VPB", 0 0, L_000000000400b490;  1 drivers, strength-aware
+L_000000000400c0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b7e0_0 .net8 "VPWR", 0 0, L_000000000400c0d0;  1 drivers, strength-aware
+v0000000003a5c0a0_0 .net "Y", 0 0, L_0000000004135310;  alias, 1 drivers
+S_0000000003a916f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a8eb70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004134900 .functor NOT 1, L_0000000003f92f00, C4<0>, C4<0>, C4<0>;
+L_0000000004135310 .functor BUF 1, L_0000000004134900, C4<0>, C4<0>, C4<0>;
+v0000000003a5c000_0 .net "A", 0 0, L_0000000003f92f00;  alias, 1 drivers
+L_000000000400bc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5bba0_0 .net8 "VGND", 0 0, L_000000000400bc00;  1 drivers, strength-aware
+L_000000000400c290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5aca0_0 .net8 "VNB", 0 0, L_000000000400c290;  1 drivers, strength-aware
+L_000000000400ad20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b740_0 .net8 "VPB", 0 0, L_000000000400ad20;  1 drivers, strength-aware
+L_000000000400bc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ad40_0 .net8 "VPWR", 0 0, L_000000000400bc70;  1 drivers, strength-aware
+v0000000003a5b6a0_0 .net "Y", 0 0, L_0000000004135310;  alias, 1 drivers
+v0000000003a5c140_0 .net "not0_out_Y", 0 0, L_0000000004134900;  1 drivers
+S_0000000003a91ff0 .scope module, "_0716_" "sky130_fd_sc_hd__a2bb2o_2" 3 1662, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a5f660_0 .net "A1_N", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a5db80_0 .net "A2_N", 0 0, L_0000000003f93a40;  1 drivers
+v0000000003a5e9e0_0 .net "B1", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a5e4e0_0 .net "B2", 0 0, L_0000000003f92dc0;  1 drivers
+L_000000000400aee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e120_0 .net8 "VGND", 0 0, L_000000000400aee0;  1 drivers, strength-aware
+L_000000000400b340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5f8e0_0 .net8 "VNB", 0 0, L_000000000400b340;  1 drivers, strength-aware
+L_000000000400b0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d2c0_0 .net8 "VPB", 0 0, L_000000000400b0a0;  1 drivers, strength-aware
+L_000000000400b570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ef80_0 .net8 "VPWR", 0 0, L_000000000400b570;  1 drivers, strength-aware
+v0000000003a5f840_0 .net "X", 0 0, L_00000000041349e0;  alias, 1 drivers
+S_0000000003a8f8f0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a91ff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004136490 .functor AND 1, L_0000000004127a10, L_0000000003f92dc0, C4<1>, C4<1>;
+L_0000000004134970 .functor NOR 1, L_0000000004126dd0, L_0000000003f93a40, C4<0>, C4<0>;
+L_0000000004135d20 .functor OR 1, L_0000000004134970, L_0000000004136490, C4<0>, C4<0>;
+L_00000000041349e0 .functor BUF 1, L_0000000004135d20, C4<0>, C4<0>, C4<0>;
+v0000000003a5c820_0 .net "A1_N", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a5c8c0_0 .net "A2_N", 0 0, L_0000000003f93a40;  alias, 1 drivers
+v0000000003a5c960_0 .net "B1", 0 0, L_0000000004127a10;  alias, 1 drivers
+v0000000003a5b920_0 .net "B2", 0 0, L_0000000003f92dc0;  alias, 1 drivers
+L_000000000400ad90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ca00_0 .net8 "VGND", 0 0, L_000000000400ad90;  1 drivers, strength-aware
+L_000000000400bce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5caa0_0 .net8 "VNB", 0 0, L_000000000400bce0;  1 drivers, strength-aware
+L_000000000400bd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5cb40_0 .net8 "VPB", 0 0, L_000000000400bd50;  1 drivers, strength-aware
+L_000000000400b110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5b9c0_0 .net8 "VPWR", 0 0, L_000000000400b110;  1 drivers, strength-aware
+v0000000003a5ba60_0 .net "X", 0 0, L_00000000041349e0;  alias, 1 drivers
+v0000000003a5d220_0 .net "and0_out", 0 0, L_0000000004136490;  1 drivers
+v0000000003a5dcc0_0 .net "nor0_out", 0 0, L_0000000004134970;  1 drivers
+v0000000003a5d900_0 .net "or0_out_X", 0 0, L_0000000004135d20;  1 drivers
+S_0000000003a8f170 .scope module, "_0717_" "sky130_fd_sc_hd__o221a_2" 3 1669, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a5e6c0_0 .net "A1", 0 0, L_0000000003f92e60;  1 drivers
+v0000000003a5f200_0 .net "A2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a5dae0_0 .net "B1", 0 0, L_0000000004135310;  alias, 1 drivers
+v0000000003a5d860_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a5ec60_0 .net "C1", 0 0, L_00000000041349e0;  alias, 1 drivers
+L_000000000400c300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d400_0 .net8 "VGND", 0 0, L_000000000400c300;  1 drivers, strength-aware
+L_000000000400b3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5eb20_0 .net8 "VNB", 0 0, L_000000000400b3b0;  1 drivers, strength-aware
+L_000000000400b420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5f340_0 .net8 "VPB", 0 0, L_000000000400b420;  1 drivers, strength-aware
+L_000000000400b500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d680_0 .net8 "VPWR", 0 0, L_000000000400b500;  1 drivers, strength-aware
+v0000000003a5d4a0_0 .net "X", 0 0, L_0000000004135d90;  alias, 1 drivers
+S_0000000003a8fbf0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a8f170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004135a80 .functor OR 1, L_00000000041271c0, L_0000000004135310, C4<0>, C4<0>;
+L_0000000004134eb0 .functor OR 1, L_00000000041265f0, L_0000000003f92e60, C4<0>, C4<0>;
+L_0000000004135460 .functor AND 1, L_0000000004135a80, L_0000000004134eb0, L_00000000041349e0, C4<1>;
+L_0000000004135d90 .functor BUF 1, L_0000000004135460, C4<0>, C4<0>, C4<0>;
+v0000000003a5f020_0 .net "A1", 0 0, L_0000000003f92e60;  alias, 1 drivers
+v0000000003a5d360_0 .net "A2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a5f700_0 .net "B1", 0 0, L_0000000004135310;  alias, 1 drivers
+v0000000003a5f2a0_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a5d180_0 .net "C1", 0 0, L_00000000041349e0;  alias, 1 drivers
+L_000000000400cd80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5dd60_0 .net8 "VGND", 0 0, L_000000000400cd80;  1 drivers, strength-aware
+L_000000000400d640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5f0c0_0 .net8 "VNB", 0 0, L_000000000400d640;  1 drivers, strength-aware
+L_000000000400da30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5eda0_0 .net8 "VPB", 0 0, L_000000000400da30;  1 drivers, strength-aware
+L_000000000400db80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e760_0 .net8 "VPWR", 0 0, L_000000000400db80;  1 drivers, strength-aware
+v0000000003a5f160_0 .net "X", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a5f5c0_0 .net "and0_out_X", 0 0, L_0000000004135460;  1 drivers
+v0000000003a5e300_0 .net "or0_out", 0 0, L_0000000004135a80;  1 drivers
+v0000000003a5f520_0 .net "or1_out", 0 0, L_0000000004134eb0;  1 drivers
+S_0000000003a92170 .scope module, "_0718_" "sky130_fd_sc_hd__o221a_2" 3 1677, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a5dc20_0 .net "A1", 0 0, L_0000000003f93d60;  1 drivers
+v0000000003a5d720_0 .net "A2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a5f480_0 .net "B1", 0 0, L_00000000041351c0;  alias, 1 drivers
+v0000000003a5e3a0_0 .net "B2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a5e800_0 .net "C1", 0 0, L_0000000004135380;  alias, 1 drivers
+L_000000000400ca00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d7c0_0 .net8 "VGND", 0 0, L_000000000400ca00;  1 drivers, strength-aware
+L_000000000400d090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e1c0_0 .net8 "VNB", 0 0, L_000000000400d090;  1 drivers, strength-aware
+L_000000000400cb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d9a0_0 .net8 "VPB", 0 0, L_000000000400cb50;  1 drivers, strength-aware
+L_000000000400d2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5da40_0 .net8 "VPWR", 0 0, L_000000000400d2c0;  1 drivers, strength-aware
+v0000000003a5de00_0 .net "X", 0 0, L_0000000004135690;  alias, 1 drivers
+S_0000000003a901f0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a92170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004135e70 .functor OR 1, L_0000000004127e00, L_00000000041351c0, C4<0>, C4<0>;
+L_0000000004134c80 .functor OR 1, L_0000000004130300, L_0000000003f93d60, C4<0>, C4<0>;
+L_0000000004135770 .functor AND 1, L_0000000004135e70, L_0000000004134c80, L_0000000004135380, C4<1>;
+L_0000000004135690 .functor BUF 1, L_0000000004135770, C4<0>, C4<0>, C4<0>;
+v0000000003a5ea80_0 .net "A1", 0 0, L_0000000003f93d60;  alias, 1 drivers
+v0000000003a5ed00_0 .net "A2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a5ebc0_0 .net "B1", 0 0, L_00000000041351c0;  alias, 1 drivers
+v0000000003a5e580_0 .net "B2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a5d540_0 .net "C1", 0 0, L_0000000004135380;  alias, 1 drivers
+L_000000000400d170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5d5e0_0 .net8 "VGND", 0 0, L_000000000400d170;  1 drivers, strength-aware
+L_000000000400d5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e620_0 .net8 "VNB", 0 0, L_000000000400d5d0;  1 drivers, strength-aware
+L_000000000400d1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e080_0 .net8 "VPB", 0 0, L_000000000400d1e0;  1 drivers, strength-aware
+L_000000000400ced0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ee40_0 .net8 "VPWR", 0 0, L_000000000400ced0;  1 drivers, strength-aware
+v0000000003a5f3e0_0 .net "X", 0 0, L_0000000004135690;  alias, 1 drivers
+v0000000003a5e940_0 .net "and0_out_X", 0 0, L_0000000004135770;  1 drivers
+v0000000003a5dfe0_0 .net "or0_out", 0 0, L_0000000004135e70;  1 drivers
+v0000000003a5eee0_0 .net "or1_out", 0 0, L_0000000004134c80;  1 drivers
+S_0000000003a8d970 .scope module, "_0719_" "sky130_fd_sc_hd__nor2_2" 3 1685, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a5f980_0 .net "A", 0 0, L_0000000004135230;  alias, 1 drivers
+v0000000003a61960_0 .net "B", 0 0, L_0000000004135690;  alias, 1 drivers
+L_000000000400cf40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61460_0 .net8 "VGND", 0 0, L_000000000400cf40;  1 drivers, strength-aware
+L_000000000400daa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61280_0 .net8 "VNB", 0 0, L_000000000400daa0;  1 drivers, strength-aware
+L_000000000400d800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60880_0 .net8 "VPB", 0 0, L_000000000400d800;  1 drivers, strength-aware
+L_000000000400de90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a607e0_0 .net8 "VPWR", 0 0, L_000000000400de90;  1 drivers, strength-aware
+v0000000003a60ec0_0 .net "Y", 0 0, L_0000000004134ba0;  alias, 1 drivers
+S_0000000003a925f0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a8d970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041350e0 .functor NOR 1, L_0000000004135230, L_0000000004135690, C4<0>, C4<0>;
+L_0000000004134ba0 .functor BUF 1, L_00000000041350e0, C4<0>, C4<0>, C4<0>;
+v0000000003a5dea0_0 .net "A", 0 0, L_0000000004135230;  alias, 1 drivers
+v0000000003a5e440_0 .net "B", 0 0, L_0000000004135690;  alias, 1 drivers
+L_000000000400dcd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5f7a0_0 .net8 "VGND", 0 0, L_000000000400dcd0;  1 drivers, strength-aware
+L_000000000400db10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e8a0_0 .net8 "VNB", 0 0, L_000000000400db10;  1 drivers, strength-aware
+L_000000000400e360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5df40_0 .net8 "VPB", 0 0, L_000000000400e360;  1 drivers, strength-aware
+L_000000000400e2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5e260_0 .net8 "VPWR", 0 0, L_000000000400e2f0;  1 drivers, strength-aware
+v0000000003a62040_0 .net "Y", 0 0, L_0000000004134ba0;  alias, 1 drivers
+v0000000003a61e60_0 .net "nor0_out_Y", 0 0, L_00000000041350e0;  1 drivers
+S_0000000003a8fef0 .scope module, "_0720_" "sky130_fd_sc_hd__or2_2" 3 1690, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a61a00_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a5fde0_0 .net "B", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_000000000400dc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a611e0_0 .net8 "VGND", 0 0, L_000000000400dc60;  1 drivers, strength-aware
+L_000000000400cfb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a606a0_0 .net8 "VNB", 0 0, L_000000000400cfb0;  1 drivers, strength-aware
+L_000000000400de20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a613c0_0 .net8 "VPB", 0 0, L_000000000400de20;  1 drivers, strength-aware
+L_000000000400d870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60060_0 .net8 "VPWR", 0 0, L_000000000400d870;  1 drivers, strength-aware
+v0000000003a5fe80_0 .net "X", 0 0, L_0000000004135850;  alias, 1 drivers
+S_0000000003a92a70 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a8fef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041354d0 .functor OR 1, L_0000000004134ba0, L_0000000004135d90, C4<0>, C4<0>;
+L_0000000004135850 .functor BUF 1, L_00000000041354d0, C4<0>, C4<0>, C4<0>;
+v0000000003a61640_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a61500_0 .net "B", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_000000000400e3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a60240_0 .net8 "VGND", 0 0, L_000000000400e3d0;  1 drivers, strength-aware
+L_000000000400dd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ff20_0 .net8 "VNB", 0 0, L_000000000400dd40;  1 drivers, strength-aware
+L_000000000400cbc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a620e0_0 .net8 "VPB", 0 0, L_000000000400cbc0;  1 drivers, strength-aware
+L_000000000400cc30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a609c0_0 .net8 "VPWR", 0 0, L_000000000400cc30;  1 drivers, strength-aware
+v0000000003a5fa20_0 .net "X", 0 0, L_0000000004135850;  alias, 1 drivers
+v0000000003a61dc0_0 .net "or0_out_X", 0 0, L_00000000041354d0;  1 drivers
+S_0000000003a92470 .scope module, "_0721_" "sky130_fd_sc_hd__inv_2" 3 1695, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a60920_0 .net "A", 0 0, L_0000000004135850;  alias, 1 drivers
+L_000000000400d6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61320_0 .net8 "VGND", 0 0, L_000000000400d6b0;  1 drivers, strength-aware
+L_000000000400df70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5fb60_0 .net8 "VNB", 0 0, L_000000000400df70;  1 drivers, strength-aware
+L_000000000400dbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a604c0_0 .net8 "VPB", 0 0, L_000000000400dbf0;  1 drivers, strength-aware
+L_000000000400e440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a5ffc0_0 .net8 "VPWR", 0 0, L_000000000400e440;  1 drivers, strength-aware
+v0000000003a61780_0 .net "Y", 0 0, L_0000000004135ee0;  alias, 1 drivers
+S_0000000003a8d670 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a92470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004135620 .functor NOT 1, L_0000000004135850, C4<0>, C4<0>, C4<0>;
+L_0000000004135ee0 .functor BUF 1, L_0000000004135620, C4<0>, C4<0>, C4<0>;
+v0000000003a60c40_0 .net "A", 0 0, L_0000000004135850;  alias, 1 drivers
+L_000000000400ddb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a60b00_0 .net8 "VGND", 0 0, L_000000000400ddb0;  1 drivers, strength-aware
+L_000000000400d720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5fac0_0 .net8 "VNB", 0 0, L_000000000400d720;  1 drivers, strength-aware
+L_000000000400d100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60a60_0 .net8 "VPB", 0 0, L_000000000400d100;  1 drivers, strength-aware
+L_000000000400d250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60740_0 .net8 "VPWR", 0 0, L_000000000400d250;  1 drivers, strength-aware
+v0000000003a5fc00_0 .net "Y", 0 0, L_0000000004135ee0;  alias, 1 drivers
+v0000000003a60600_0 .net "not0_out_Y", 0 0, L_0000000004135620;  1 drivers
+S_0000000003a8d7f0 .scope module, "_0722_" "sky130_fd_sc_hd__or2_2" 3 1699, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a60d80_0 .net "A", 0 0, L_0000000004133fd0;  alias, 1 drivers
+v0000000003a616e0_0 .net "B", 0 0, L_0000000004135150;  alias, 1 drivers
+L_000000000400df00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a618c0_0 .net8 "VGND", 0 0, L_000000000400df00;  1 drivers, strength-aware
+L_000000000400d330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61b40_0 .net8 "VNB", 0 0, L_000000000400d330;  1 drivers, strength-aware
+L_000000000400d020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a61be0_0 .net8 "VPB", 0 0, L_000000000400d020;  1 drivers, strength-aware
+L_000000000400dfe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a602e0_0 .net8 "VPWR", 0 0, L_000000000400dfe0;  1 drivers, strength-aware
+v0000000003a60380_0 .net "X", 0 0, L_0000000004135540;  alias, 1 drivers
+S_0000000003a904f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a8d7f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041358c0 .functor OR 1, L_0000000004135150, L_0000000004133fd0, C4<0>, C4<0>;
+L_0000000004135540 .functor BUF 1, L_00000000041358c0, C4<0>, C4<0>, C4<0>;
+v0000000003a5fca0_0 .net "A", 0 0, L_0000000004133fd0;  alias, 1 drivers
+v0000000003a61aa0_0 .net "B", 0 0, L_0000000004135150;  alias, 1 drivers
+L_000000000400e050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61820_0 .net8 "VGND", 0 0, L_000000000400e050;  1 drivers, strength-aware
+L_000000000400d3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a5fd40_0 .net8 "VNB", 0 0, L_000000000400d3a0;  1 drivers, strength-aware
+L_000000000400e0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a61140_0 .net8 "VPB", 0 0, L_000000000400e0c0;  1 drivers, strength-aware
+L_000000000400d410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a615a0_0 .net8 "VPWR", 0 0, L_000000000400d410;  1 drivers, strength-aware
+v0000000003a60100_0 .net "X", 0 0, L_0000000004135540;  alias, 1 drivers
+v0000000003a601a0_0 .net "or0_out_X", 0 0, L_00000000041358c0;  1 drivers
+S_0000000003a8daf0 .scope module, "_0723_" "sky130_fd_sc_hd__o21a_2" 3 1704, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a61fa0_0 .net "A1", 0 0, L_00000000041361f0;  alias, 1 drivers
+v0000000003a610a0_0 .net "A2", 0 0, L_0000000004135ee0;  alias, 1 drivers
+v0000000003a62180_0 .net "B1", 0 0, L_0000000004135540;  alias, 1 drivers
+L_000000000400d9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a62e00_0 .net8 "VGND", 0 0, L_000000000400d9c0;  1 drivers, strength-aware
+L_000000000400d480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a63940_0 .net8 "VNB", 0 0, L_000000000400d480;  1 drivers, strength-aware
+L_000000000400cdf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62680_0 .net8 "VPB", 0 0, L_000000000400cdf0;  1 drivers, strength-aware
+L_000000000400ca70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62220_0 .net8 "VPWR", 0 0, L_000000000400ca70;  1 drivers, strength-aware
+v0000000003a63120_0 .net "X", 0 0, L_0000000004135f50;  alias, 1 drivers
+S_0000000003a8e870 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a8daf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004134a50 .functor OR 1, L_0000000004135ee0, L_00000000041361f0, C4<0>, C4<0>;
+L_0000000004136260 .functor AND 1, L_0000000004134a50, L_0000000004135540, C4<1>, C4<1>;
+L_0000000004135f50 .functor BUF 1, L_0000000004136260, C4<0>, C4<0>, C4<0>;
+v0000000003a60420_0 .net "A1", 0 0, L_00000000041361f0;  alias, 1 drivers
+v0000000003a60ba0_0 .net "A2", 0 0, L_0000000004135ee0;  alias, 1 drivers
+v0000000003a60560_0 .net "B1", 0 0, L_0000000004135540;  alias, 1 drivers
+L_000000000400d790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a60ce0_0 .net8 "VGND", 0 0, L_000000000400d790;  1 drivers, strength-aware
+L_000000000400d4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a61d20_0 .net8 "VNB", 0 0, L_000000000400d4f0;  1 drivers, strength-aware
+L_000000000400e130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60e20_0 .net8 "VPB", 0 0, L_000000000400e130;  1 drivers, strength-aware
+L_000000000400c8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a60f60_0 .net8 "VPWR", 0 0, L_000000000400c8b0;  1 drivers, strength-aware
+v0000000003a61c80_0 .net "X", 0 0, L_0000000004135f50;  alias, 1 drivers
+v0000000003a61000_0 .net "and0_out_X", 0 0, L_0000000004136260;  1 drivers
+v0000000003a61f00_0 .net "or0_out", 0 0, L_0000000004134a50;  1 drivers
+S_0000000003a8dc70 .scope module, "_0724_" "sky130_fd_sc_hd__inv_2" 3 1710, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a63080_0 .net "A", 0 0, L_0000000003f921e0;  1 drivers
+L_000000000400e1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a64520_0 .net8 "VGND", 0 0, L_000000000400e1a0;  1 drivers, strength-aware
+L_000000000400cca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a62720_0 .net8 "VNB", 0 0, L_000000000400cca0;  1 drivers, strength-aware
+L_000000000400e210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a63760_0 .net8 "VPB", 0 0, L_000000000400e210;  1 drivers, strength-aware
+L_000000000400c920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a63580_0 .net8 "VPWR", 0 0, L_000000000400c920;  1 drivers, strength-aware
+v0000000003a645c0_0 .net "Y", 0 0, L_0000000004134ac0;  alias, 1 drivers
+S_0000000003a8ddf0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a8dc70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004135b60 .functor NOT 1, L_0000000003f921e0, C4<0>, C4<0>, C4<0>;
+L_0000000004134ac0 .functor BUF 1, L_0000000004135b60, C4<0>, C4<0>, C4<0>;
+v0000000003a633a0_0 .net "A", 0 0, L_0000000003f921e0;  alias, 1 drivers
+L_000000000400d560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a62b80_0 .net8 "VGND", 0 0, L_000000000400d560;  1 drivers, strength-aware
+L_000000000400e280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a625e0_0 .net8 "VNB", 0 0, L_000000000400e280;  1 drivers, strength-aware
+L_000000000400cae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62ea0_0 .net8 "VPB", 0 0, L_000000000400cae0;  1 drivers, strength-aware
+L_000000000400d8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a634e0_0 .net8 "VPWR", 0 0, L_000000000400d8e0;  1 drivers, strength-aware
+v0000000003a62f40_0 .net "Y", 0 0, L_0000000004134ac0;  alias, 1 drivers
+v0000000003a63800_0 .net "not0_out_Y", 0 0, L_0000000004135b60;  1 drivers
+S_0000000003a8df70 .scope module, "_0725_" "sky130_fd_sc_hd__a2bb2o_2" 3 1714, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a63440_0 .net "A1_N", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a639e0_0 .net "A2_N", 0 0, L_0000000003f943a0;  1 drivers
+v0000000003a63c60_0 .net "B1", 0 0, L_0000000003f92960;  1 drivers
+v0000000003a62540_0 .net "B2", 0 0, L_0000000003f93e00;  1 drivers
+L_000000000400d950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a63620_0 .net8 "VGND", 0 0, L_000000000400d950;  1 drivers, strength-aware
+L_000000000400c990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a63b20_0 .net8 "VNB", 0 0, L_000000000400c990;  1 drivers, strength-aware
+L_000000000400cd10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62a40_0 .net8 "VPB", 0 0, L_000000000400cd10;  1 drivers, strength-aware
+L_000000000400ce60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a636c0_0 .net8 "VPWR", 0 0, L_000000000400ce60;  1 drivers, strength-aware
+v0000000003a63260_0 .net "X", 0 0, L_00000000041355b0;  alias, 1 drivers
+S_0000000003a90070 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003a8df70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041360a0 .functor AND 1, L_0000000003f92960, L_0000000003f93e00, C4<1>, C4<1>;
+L_00000000041362d0 .functor NOR 1, L_0000000004126430, L_0000000003f943a0, C4<0>, C4<0>;
+L_00000000041357e0 .functor OR 1, L_00000000041362d0, L_00000000041360a0, C4<0>, C4<0>;
+L_00000000041355b0 .functor BUF 1, L_00000000041357e0, C4<0>, C4<0>, C4<0>;
+v0000000003a63a80_0 .net "A1_N", 0 0, L_0000000004126430;  alias, 1 drivers
+v0000000003a640c0_0 .net "A2_N", 0 0, L_0000000003f943a0;  alias, 1 drivers
+v0000000003a62860_0 .net "B1", 0 0, L_0000000003f92960;  alias, 1 drivers
+v0000000003a62fe0_0 .net "B2", 0 0, L_0000000003f93e00;  alias, 1 drivers
+L_000000000400ef30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a627c0_0 .net8 "VGND", 0 0, L_000000000400ef30;  1 drivers, strength-aware
+L_000000000400e520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a642a0_0 .net8 "VNB", 0 0, L_000000000400e520;  1 drivers, strength-aware
+L_000000000400e980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62900_0 .net8 "VPB", 0 0, L_000000000400e980;  1 drivers, strength-aware
+L_000000000400ea60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a64700_0 .net8 "VPWR", 0 0, L_000000000400ea60;  1 drivers, strength-aware
+v0000000003a631c0_0 .net "X", 0 0, L_00000000041355b0;  alias, 1 drivers
+v0000000003a62cc0_0 .net "and0_out", 0 0, L_00000000041360a0;  1 drivers
+v0000000003a629a0_0 .net "nor0_out", 0 0, L_00000000041362d0;  1 drivers
+v0000000003a63da0_0 .net "or0_out_X", 0 0, L_00000000041357e0;  1 drivers
+S_0000000003a90670 .scope module, "_0726_" "sky130_fd_sc_hd__a221o_2" 3 1721, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a64160_0 .net "A1", 0 0, L_0000000004134ac0;  alias, 1 drivers
+v0000000003a64840_0 .net "A2", 0 0, L_0000000004125400;  alias, 1 drivers
+v0000000003a64200_0 .net "B1", 0 0, L_0000000003f92a00;  1 drivers
+v0000000003a643e0_0 .net "B2", 0 0, L_0000000004125780;  alias, 1 drivers
+v0000000003a64480_0 .net "C1", 0 0, L_00000000041355b0;  alias, 1 drivers
+L_000000000400f010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a647a0_0 .net8 "VGND", 0 0, L_000000000400f010;  1 drivers, strength-aware
+L_000000000400e4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a648e0_0 .net8 "VNB", 0 0, L_000000000400e4b0;  1 drivers, strength-aware
+L_000000000400e8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a622c0_0 .net8 "VPB", 0 0, L_000000000400e8a0;  1 drivers, strength-aware
+L_000000000400f320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62360_0 .net8 "VPWR", 0 0, L_000000000400f320;  1 drivers, strength-aware
+v0000000003a62400_0 .net "X", 0 0, L_00000000041359a0;  alias, 1 drivers
+S_0000000003a907f0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a90670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004134c10 .functor AND 1, L_0000000003f92a00, L_0000000004125780, C4<1>, C4<1>;
+L_0000000004134d60 .functor AND 1, L_0000000004134ac0, L_0000000004125400, C4<1>, C4<1>;
+L_0000000004135fc0 .functor OR 1, L_0000000004134d60, L_0000000004134c10, L_00000000041355b0, C4<0>;
+L_00000000041359a0 .functor BUF 1, L_0000000004135fc0, C4<0>, C4<0>, C4<0>;
+v0000000003a63ee0_0 .net "A1", 0 0, L_0000000004134ac0;  alias, 1 drivers
+v0000000003a62ae0_0 .net "A2", 0 0, L_0000000004125400;  alias, 1 drivers
+v0000000003a62c20_0 .net "B1", 0 0, L_0000000003f92a00;  alias, 1 drivers
+v0000000003a63300_0 .net "B2", 0 0, L_0000000004125780;  alias, 1 drivers
+v0000000003a638a0_0 .net "C1", 0 0, L_00000000041355b0;  alias, 1 drivers
+L_000000000400ed70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a63bc0_0 .net8 "VGND", 0 0, L_000000000400ed70;  1 drivers, strength-aware
+L_000000000400f860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a63d00_0 .net8 "VNB", 0 0, L_000000000400f860;  1 drivers, strength-aware
+L_000000000400eec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a62d60_0 .net8 "VPB", 0 0, L_000000000400eec0;  1 drivers, strength-aware
+L_000000000400f080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a64660_0 .net8 "VPWR", 0 0, L_000000000400f080;  1 drivers, strength-aware
+v0000000003a64340_0 .net "X", 0 0, L_00000000041359a0;  alias, 1 drivers
+v0000000003a63e40_0 .net "and0_out", 0 0, L_0000000004134c10;  1 drivers
+v0000000003a63f80_0 .net "and1_out", 0 0, L_0000000004134d60;  1 drivers
+v0000000003a64020_0 .net "or0_out_X", 0 0, L_0000000004135fc0;  1 drivers
+S_0000000003a8e0f0 .scope module, "_0727_" "sky130_fd_sc_hd__inv_2" 3 1729, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a64d40_0 .net "A", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_000000000400fb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a661e0_0 .net8 "VGND", 0 0, L_000000000400fb70;  1 drivers, strength-aware
+L_000000000400fe80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66f00_0 .net8 "VNB", 0 0, L_000000000400fe80;  1 drivers, strength-aware
+L_000000000400e590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65100_0 .net8 "VPB", 0 0, L_000000000400e590;  1 drivers, strength-aware
+L_000000000400e7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a66be0_0 .net8 "VPWR", 0 0, L_000000000400e7c0;  1 drivers, strength-aware
+v0000000003a66780_0 .net "Y", 0 0, L_0000000004136030;  alias, 1 drivers
+S_0000000003a8ecf0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a8e0f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004136340 .functor NOT 1, L_00000000041359a0, C4<0>, C4<0>, C4<0>;
+L_0000000004136030 .functor BUF 1, L_0000000004136340, C4<0>, C4<0>, C4<0>;
+v0000000003a624a0_0 .net "A", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_000000000400fef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a65ec0_0 .net8 "VGND", 0 0, L_000000000400fef0;  1 drivers, strength-aware
+L_000000000400e9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a64ca0_0 .net8 "VNB", 0 0, L_000000000400e9f0;  1 drivers, strength-aware
+L_000000000400ebb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65420_0 .net8 "VPB", 0 0, L_000000000400ebb0;  1 drivers, strength-aware
+L_000000000400ff60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65560_0 .net8 "VPWR", 0 0, L_000000000400ff60;  1 drivers, strength-aware
+v0000000003a66dc0_0 .net "Y", 0 0, L_0000000004136030;  alias, 1 drivers
+v0000000003a65ce0_0 .net "not0_out_Y", 0 0, L_0000000004136340;  1 drivers
+S_0000000003a8e9f0 .scope module, "_0728_" "sky130_fd_sc_hd__o221a_2" 3 1733, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a64c00_0 .net "A1", 0 0, L_0000000003f934a0;  1 drivers
+v0000000003a66960_0 .net "A2", 0 0, L_0000000004125400;  alias, 1 drivers
+v0000000003a66000_0 .net "B1", 0 0, L_0000000004134ac0;  alias, 1 drivers
+v0000000003a65f60_0 .net "B2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a66aa0_0 .net "C1", 0 0, L_00000000041355b0;  alias, 1 drivers
+L_000000000400fa90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66d20_0 .net8 "VGND", 0 0, L_000000000400fa90;  1 drivers, strength-aware
+L_0000000004010040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a64e80_0 .net8 "VNB", 0 0, L_0000000004010040;  1 drivers, strength-aware
+L_000000000400f0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a656a0_0 .net8 "VPB", 0 0, L_000000000400f0f0;  1 drivers, strength-aware
+L_000000000400f5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65740_0 .net8 "VPWR", 0 0, L_000000000400f5c0;  1 drivers, strength-aware
+v0000000003a657e0_0 .net "X", 0 0, L_0000000004136180;  alias, 1 drivers
+S_0000000003a8e270 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a8e9f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004135a10 .functor OR 1, L_00000000041265f0, L_0000000004134ac0, C4<0>, C4<0>;
+L_0000000004134f90 .functor OR 1, L_0000000004125400, L_0000000003f934a0, C4<0>, C4<0>;
+L_0000000004136110 .functor AND 1, L_0000000004135a10, L_0000000004134f90, L_00000000041355b0, C4<1>;
+L_0000000004136180 .functor BUF 1, L_0000000004136110, C4<0>, C4<0>, C4<0>;
+v0000000003a654c0_0 .net "A1", 0 0, L_0000000003f934a0;  alias, 1 drivers
+v0000000003a64a20_0 .net "A2", 0 0, L_0000000004125400;  alias, 1 drivers
+v0000000003a65600_0 .net "B1", 0 0, L_0000000004134ac0;  alias, 1 drivers
+v0000000003a65380_0 .net "B2", 0 0, L_00000000041265f0;  alias, 1 drivers
+v0000000003a64de0_0 .net "C1", 0 0, L_00000000041355b0;  alias, 1 drivers
+L_000000000400ec90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66820_0 .net8 "VGND", 0 0, L_000000000400ec90;  1 drivers, strength-aware
+L_000000000400e600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a668c0_0 .net8 "VNB", 0 0, L_000000000400e600;  1 drivers, strength-aware
+L_000000000400f940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a66c80_0 .net8 "VPB", 0 0, L_000000000400f940;  1 drivers, strength-aware
+L_000000000400f8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a64ac0_0 .net8 "VPWR", 0 0, L_000000000400f8d0;  1 drivers, strength-aware
+v0000000003a66a00_0 .net "X", 0 0, L_0000000004136180;  alias, 1 drivers
+v0000000003a651a0_0 .net "and0_out_X", 0 0, L_0000000004136110;  1 drivers
+v0000000003a652e0_0 .net "or0_out", 0 0, L_0000000004135a10;  1 drivers
+v0000000003a64b60_0 .net "or1_out", 0 0, L_0000000004134f90;  1 drivers
+S_0000000003a8e3f0 .scope module, "_0729_" "sky130_fd_sc_hd__or2_2" 3 1741, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a65060_0 .net "A", 0 0, L_0000000004136030;  alias, 1 drivers
+v0000000003a66460_0 .net "B", 0 0, L_0000000004136180;  alias, 1 drivers
+L_000000000400ee50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a64fc0_0 .net8 "VGND", 0 0, L_000000000400ee50;  1 drivers, strength-aware
+L_000000000400fb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a65880_0 .net8 "VNB", 0 0, L_000000000400fb00;  1 drivers, strength-aware
+L_000000000400ed00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a66280_0 .net8 "VPB", 0 0, L_000000000400ed00;  1 drivers, strength-aware
+L_000000000400f710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67040_0 .net8 "VPWR", 0 0, L_000000000400f710;  1 drivers, strength-aware
+v0000000003a65920_0 .net "X", 0 0, L_0000000004135bd0;  alias, 1 drivers
+S_0000000003a8ee70 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a8e3f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004135af0 .functor OR 1, L_0000000004136180, L_0000000004136030, C4<0>, C4<0>;
+L_0000000004135bd0 .functor BUF 1, L_0000000004135af0, C4<0>, C4<0>, C4<0>;
+v0000000003a660a0_0 .net "A", 0 0, L_0000000004136030;  alias, 1 drivers
+v0000000003a66b40_0 .net "B", 0 0, L_0000000004136180;  alias, 1 drivers
+L_000000000400f780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66320_0 .net8 "VGND", 0 0, L_000000000400f780;  1 drivers, strength-aware
+L_000000000400ede0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66e60_0 .net8 "VNB", 0 0, L_000000000400ede0;  1 drivers, strength-aware
+L_000000000400efa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a64f20_0 .net8 "VPB", 0 0, L_000000000400efa0;  1 drivers, strength-aware
+L_000000000400fbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a659c0_0 .net8 "VPWR", 0 0, L_000000000400fbe0;  1 drivers, strength-aware
+v0000000003a66fa0_0 .net "X", 0 0, L_0000000004135bd0;  alias, 1 drivers
+v0000000003a66140_0 .net "or0_out_X", 0 0, L_0000000004135af0;  1 drivers
+S_0000000003a952f0 .scope module, "_0730_" "sky130_fd_sc_hd__o21ai_2" 3 1746, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a65d80_0 .net "A1", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a66640_0 .net "A2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a65e20_0 .net "B1", 0 0, L_0000000004135bd0;  alias, 1 drivers
+L_000000000400ec20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a666e0_0 .net8 "VGND", 0 0, L_000000000400ec20;  1 drivers, strength-aware
+L_000000000400fda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a683a0_0 .net8 "VNB", 0 0, L_000000000400fda0;  1 drivers, strength-aware
+L_000000000400f630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67b80_0 .net8 "VPB", 0 0, L_000000000400f630;  1 drivers, strength-aware
+L_000000000400fc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67fe0_0 .net8 "VPWR", 0 0, L_000000000400fc50;  1 drivers, strength-aware
+v0000000003a67540_0 .net "Y", 0 0, L_0000000004135000;  alias, 1 drivers
+S_0000000003a93df0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a952f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004135c40 .functor OR 1, L_00000000041270e0, L_0000000004126dd0, C4<0>, C4<0>;
+L_0000000004135cb0 .functor NAND 1, L_0000000004135bd0, L_0000000004135c40, C4<1>, C4<1>;
+L_0000000004135000 .functor BUF 1, L_0000000004135cb0, C4<0>, C4<0>, C4<0>;
+v0000000003a65ba0_0 .net "A1", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a663c0_0 .net "A2", 0 0, L_00000000041270e0;  alias, 1 drivers
+v0000000003a670e0_0 .net "B1", 0 0, L_0000000004135bd0;  alias, 1 drivers
+L_000000000400f160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a66500_0 .net8 "VGND", 0 0, L_000000000400f160;  1 drivers, strength-aware
+L_000000000400f1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a64980_0 .net8 "VNB", 0 0, L_000000000400f1d0;  1 drivers, strength-aware
+L_000000000400fcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65240_0 .net8 "VPB", 0 0, L_000000000400fcc0;  1 drivers, strength-aware
+L_000000000400e6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a65a60_0 .net8 "VPWR", 0 0, L_000000000400e6e0;  1 drivers, strength-aware
+v0000000003a65b00_0 .net "Y", 0 0, L_0000000004135000;  alias, 1 drivers
+v0000000003a65c40_0 .net "nand0_out_Y", 0 0, L_0000000004135cb0;  1 drivers
+v0000000003a665a0_0 .net "or0_out", 0 0, L_0000000004135c40;  1 drivers
+S_0000000003a96c70 .scope module, "_0731_" "sky130_fd_sc_hd__inv_2" 3 1752, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a695c0_0 .net "A", 0 0, L_0000000004135000;  alias, 1 drivers
+L_000000000400f240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68b20_0 .net8 "VGND", 0 0, L_000000000400f240;  1 drivers, strength-aware
+L_000000000400fd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a67180_0 .net8 "VNB", 0 0, L_000000000400fd30;  1 drivers, strength-aware
+L_000000000400f2b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a675e0_0 .net8 "VPB", 0 0, L_000000000400f2b0;  1 drivers, strength-aware
+L_000000000400f390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a689e0_0 .net8 "VPWR", 0 0, L_000000000400f390;  1 drivers, strength-aware
+v0000000003a67ea0_0 .net "Y", 0 0, L_0000000004138090;  alias, 1 drivers
+S_0000000003a964f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a96c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004135070 .functor NOT 1, L_0000000004135000, C4<0>, C4<0>, C4<0>;
+L_0000000004138090 .functor BUF 1, L_0000000004135070, C4<0>, C4<0>, C4<0>;
+v0000000003a68300_0 .net "A", 0 0, L_0000000004135000;  alias, 1 drivers
+L_000000000400f6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68e40_0 .net8 "VGND", 0 0, L_000000000400f6a0;  1 drivers, strength-aware
+L_000000000400ead0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68c60_0 .net8 "VNB", 0 0, L_000000000400ead0;  1 drivers, strength-aware
+L_000000000400ffd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67a40_0 .net8 "VPB", 0 0, L_000000000400ffd0;  1 drivers, strength-aware
+L_000000000400e750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a68760_0 .net8 "VPWR", 0 0, L_000000000400e750;  1 drivers, strength-aware
+v0000000003a698e0_0 .net "Y", 0 0, L_0000000004138090;  alias, 1 drivers
+v0000000003a68080_0 .net "not0_out_Y", 0 0, L_0000000004135070;  1 drivers
+S_0000000003a940f0 .scope module, "_0732_" "sky130_fd_sc_hd__a221oi_2" 3 1756, 4 2486 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a672c0_0 .net "A1", 0 0, L_0000000004135310;  alias, 1 drivers
+v0000000003a67360_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a69020_0 .net "B1", 0 0, L_0000000003f93540;  1 drivers
+v0000000003a67e00_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a67c20_0 .net "C1", 0 0, L_00000000041349e0;  alias, 1 drivers
+L_000000000400e670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68bc0_0 .net8 "VGND", 0 0, L_000000000400e670;  1 drivers, strength-aware
+L_000000000400f9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a690c0_0 .net8 "VNB", 0 0, L_000000000400f9b0;  1 drivers, strength-aware
+L_000000000400f400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69160_0 .net8 "VPB", 0 0, L_000000000400f400;  1 drivers, strength-aware
+L_000000000400fe10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69520_0 .net8 "VPWR", 0 0, L_000000000400fe10;  1 drivers, strength-aware
+v0000000003a67f40_0 .net "Y", 0 0, L_0000000004136960;  alias, 1 drivers
+S_0000000003a937f0 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_0000000003a940f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041378b0 .functor AND 1, L_0000000003f93540, L_00000000041271c0, C4<1>, C4<1>;
+L_0000000004137450 .functor AND 1, L_0000000004135310, L_0000000004126660, C4<1>, C4<1>;
+L_0000000004137fb0 .functor NOR 1, L_00000000041378b0, L_00000000041349e0, L_0000000004137450, C4<0>;
+L_0000000004136960 .functor BUF 1, L_0000000004137fb0, C4<0>, C4<0>, C4<0>;
+v0000000003a67d60_0 .net "A1", 0 0, L_0000000004135310;  alias, 1 drivers
+v0000000003a69660_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a68ee0_0 .net "B1", 0 0, L_0000000003f93540;  alias, 1 drivers
+v0000000003a68440_0 .net "B2", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a684e0_0 .net "C1", 0 0, L_00000000041349e0;  alias, 1 drivers
+L_000000000400f470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a67220_0 .net8 "VGND", 0 0, L_000000000400f470;  1 drivers, strength-aware
+L_000000000400e910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a67cc0_0 .net8 "VNB", 0 0, L_000000000400e910;  1 drivers, strength-aware
+L_000000000400e830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67900_0 .net8 "VPB", 0 0, L_000000000400e830;  1 drivers, strength-aware
+L_000000000400eb40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a693e0_0 .net8 "VPWR", 0 0, L_000000000400eb40;  1 drivers, strength-aware
+v0000000003a68f80_0 .net "Y", 0 0, L_0000000004136960;  alias, 1 drivers
+v0000000003a68da0_0 .net "and0_out", 0 0, L_00000000041378b0;  1 drivers
+v0000000003a69480_0 .net "and1_out", 0 0, L_0000000004137450;  1 drivers
+v0000000003a68120_0 .net "nor0_out_Y", 0 0, L_0000000004137fb0;  1 drivers
+S_0000000003a98d70 .scope module, "_0733_" "sky130_fd_sc_hd__or2_2" 3 1764, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a68580_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a68620_0 .net "B", 0 0, L_0000000004136960;  alias, 1 drivers
+L_000000000400f4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a69340_0 .net8 "VGND", 0 0, L_000000000400f4e0;  1 drivers, strength-aware
+L_000000000400f550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68800_0 .net8 "VNB", 0 0, L_000000000400f550;  1 drivers, strength-aware
+L_000000000400f7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a688a0_0 .net8 "VPB", 0 0, L_000000000400f7f0;  1 drivers, strength-aware
+L_000000000400fa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a674a0_0 .net8 "VPWR", 0 0, L_000000000400fa20;  1 drivers, strength-aware
+v0000000003a697a0_0 .net "X", 0 0, L_00000000041369d0;  alias, 1 drivers
+S_0000000003a95770 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a98d70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004136880 .functor OR 1, L_0000000004136960, L_0000000004135d90, C4<0>, C4<0>;
+L_00000000041369d0 .functor BUF 1, L_0000000004136880, C4<0>, C4<0>, C4<0>;
+v0000000003a69700_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a681c0_0 .net "B", 0 0, L_0000000004136960;  alias, 1 drivers
+L_0000000004011a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a69200_0 .net8 "VGND", 0 0, L_0000000004011a80;  1 drivers, strength-aware
+L_0000000004011af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a68a80_0 .net8 "VNB", 0 0, L_0000000004011af0;  1 drivers, strength-aware
+L_00000000040104a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a68d00_0 .net8 "VPB", 0 0, L_00000000040104a0;  1 drivers, strength-aware
+L_0000000004011310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a692a0_0 .net8 "VPWR", 0 0, L_0000000004011310;  1 drivers, strength-aware
+v0000000003a68260_0 .net "X", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003a686c0_0 .net "or0_out_X", 0 0, L_0000000004136880;  1 drivers
+S_0000000003a94270 .scope module, "_0734_" "sky130_fd_sc_hd__nand2_2" 3 1769, 4 8552 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a67ae0_0 .net "A", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003a6a6a0_0 .net "B", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_00000000040114d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b5a0_0 .net8 "VGND", 0 0, L_00000000040114d0;  1 drivers, strength-aware
+L_00000000040107b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a560_0 .net8 "VNB", 0 0, L_00000000040107b0;  1 drivers, strength-aware
+L_0000000004010270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a600_0 .net8 "VPB", 0 0, L_0000000004010270;  1 drivers, strength-aware
+L_0000000004011620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a2e0_0 .net8 "VPWR", 0 0, L_0000000004011620;  1 drivers, strength-aware
+v0000000003a69ac0_0 .net "Y", 0 0, L_0000000004136f10;  alias, 1 drivers
+S_0000000003a93670 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003a94270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004136810 .functor NAND 1, L_00000000041359a0, L_00000000041369d0, C4<1>, C4<1>;
+L_0000000004136f10 .functor BUF 1, L_0000000004136810, C4<0>, C4<0>, C4<0>;
+v0000000003a69840_0 .net "A", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003a68940_0 .net "B", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_00000000040100b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a67400_0 .net8 "VGND", 0 0, L_00000000040100b0;  1 drivers, strength-aware
+L_0000000004010eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a67680_0 .net8 "VNB", 0 0, L_0000000004010eb0;  1 drivers, strength-aware
+L_0000000004010660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a67720_0 .net8 "VPB", 0 0, L_0000000004010660;  1 drivers, strength-aware
+L_0000000004011000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a677c0_0 .net8 "VPWR", 0 0, L_0000000004011000;  1 drivers, strength-aware
+v0000000003a67860_0 .net "Y", 0 0, L_0000000004136f10;  alias, 1 drivers
+v0000000003a679a0_0 .net "nand0_out_Y", 0 0, L_0000000004136810;  1 drivers
+S_0000000003a97ff0 .scope module, "_0735_" "sky130_fd_sc_hd__inv_2" 3 1774, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a69d40_0 .net "A", 0 0, L_0000000004136f10;  alias, 1 drivers
+L_0000000004010580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b0a0_0 .net8 "VGND", 0 0, L_0000000004010580;  1 drivers, strength-aware
+L_0000000004010c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a060_0 .net8 "VNB", 0 0, L_0000000004010c80;  1 drivers, strength-aware
+L_00000000040103c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69a20_0 .net8 "VPB", 0 0, L_00000000040103c0;  1 drivers, strength-aware
+L_0000000004010cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b320_0 .net8 "VPWR", 0 0, L_0000000004010cf0;  1 drivers, strength-aware
+v0000000003a6b1e0_0 .net "Y", 0 0, L_0000000004137370;  alias, 1 drivers
+S_0000000003a94b70 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a97ff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004136f80 .functor NOT 1, L_0000000004136f10, C4<0>, C4<0>, C4<0>;
+L_0000000004137370 .functor BUF 1, L_0000000004136f80, C4<0>, C4<0>, C4<0>;
+v0000000003a6ad80_0 .net "A", 0 0, L_0000000004136f10;  alias, 1 drivers
+L_00000000040109e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ae20_0 .net8 "VGND", 0 0, L_00000000040109e0;  1 drivers, strength-aware
+L_0000000004011540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6bdc0_0 .net8 "VNB", 0 0, L_0000000004011540;  1 drivers, strength-aware
+L_00000000040110e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b640_0 .net8 "VPB", 0 0, L_00000000040110e0;  1 drivers, strength-aware
+L_0000000004011690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6bd20_0 .net8 "VPWR", 0 0, L_0000000004011690;  1 drivers, strength-aware
+v0000000003a6aa60_0 .net "Y", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003a6c040_0 .net "not0_out_Y", 0 0, L_0000000004136f80;  1 drivers
+S_0000000003a96af0 .scope module, "_0736_" "sky130_fd_sc_hd__inv_2" 3 1778, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a69e80_0 .net "A", 0 0, L_0000000003f93ea0;  1 drivers
+L_0000000004011b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a69980_0 .net8 "VGND", 0 0, L_0000000004011b60;  1 drivers, strength-aware
+L_0000000004011c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b280_0 .net8 "VNB", 0 0, L_0000000004011c40;  1 drivers, strength-aware
+L_0000000004011460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b780_0 .net8 "VPB", 0 0, L_0000000004011460;  1 drivers, strength-aware
+L_0000000004010f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b140_0 .net8 "VPWR", 0 0, L_0000000004010f20;  1 drivers, strength-aware
+v0000000003a6a100_0 .net "Y", 0 0, L_0000000004137300;  alias, 1 drivers
+S_0000000003a949f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a96af0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004137220 .functor NOT 1, L_0000000003f93ea0, C4<0>, C4<0>, C4<0>;
+L_0000000004137300 .functor BUF 1, L_0000000004137220, C4<0>, C4<0>, C4<0>;
+v0000000003a6a740_0 .net "A", 0 0, L_0000000003f93ea0;  alias, 1 drivers
+L_0000000004011700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6aec0_0 .net8 "VGND", 0 0, L_0000000004011700;  1 drivers, strength-aware
+L_0000000004010d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6aba0_0 .net8 "VNB", 0 0, L_0000000004010d60;  1 drivers, strength-aware
+L_0000000004010510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69ca0_0 .net8 "VPB", 0 0, L_0000000004010510;  1 drivers, strength-aware
+L_0000000004010430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b460_0 .net8 "VPWR", 0 0, L_0000000004010430;  1 drivers, strength-aware
+v0000000003a69de0_0 .net "Y", 0 0, L_0000000004137300;  alias, 1 drivers
+v0000000003a6ace0_0 .net "not0_out_Y", 0 0, L_0000000004137220;  1 drivers
+S_0000000003a93970 .scope module, "_0737_" "sky130_fd_sc_hd__inv_2" 3 1782, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a6bf00_0 .net "A", 0 0, L_0000000003f930e0;  1 drivers
+L_00000000040105f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a1a0_0 .net8 "VGND", 0 0, L_00000000040105f0;  1 drivers, strength-aware
+L_00000000040106d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c0e0_0 .net8 "VNB", 0 0, L_00000000040106d0;  1 drivers, strength-aware
+L_0000000004010ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b8c0_0 .net8 "VPB", 0 0, L_0000000004010ac0;  1 drivers, strength-aware
+L_0000000004011bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69c00_0 .net8 "VPWR", 0 0, L_0000000004011bd0;  1 drivers, strength-aware
+v0000000003a6b3c0_0 .net "Y", 0 0, L_0000000004136ff0;  alias, 1 drivers
+S_0000000003a93370 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a93970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004136dc0 .functor NOT 1, L_0000000003f930e0, C4<0>, C4<0>, C4<0>;
+L_0000000004136ff0 .functor BUF 1, L_0000000004136dc0, C4<0>, C4<0>, C4<0>;
+v0000000003a69b60_0 .net "A", 0 0, L_0000000003f930e0;  alias, 1 drivers
+L_0000000004011a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ab00_0 .net8 "VGND", 0 0, L_0000000004011a10;  1 drivers, strength-aware
+L_0000000004010120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a69f20_0 .net8 "VNB", 0 0, L_0000000004010120;  1 drivers, strength-aware
+L_0000000004010190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6b000_0 .net8 "VPB", 0 0, L_0000000004010190;  1 drivers, strength-aware
+L_0000000004010740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a69fc0_0 .net8 "VPWR", 0 0, L_0000000004010740;  1 drivers, strength-aware
+v0000000003a6a880_0 .net "Y", 0 0, L_0000000004136ff0;  alias, 1 drivers
+v0000000003a6baa0_0 .net "not0_out_Y", 0 0, L_0000000004136dc0;  1 drivers
+S_0000000003a95470 .scope module, "_0738_" "sky130_fd_sc_hd__o22a_2" 3 1786, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003a6b960_0 .net "A1", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a6a4c0_0 .net "A2", 0 0, L_0000000003f93720;  1 drivers
+v0000000003a6ba00_0 .net "B1", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a6bb40_0 .net "B2", 0 0, L_0000000004136ff0;  alias, 1 drivers
+L_0000000004011380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6bbe0_0 .net8 "VGND", 0 0, L_0000000004011380;  1 drivers, strength-aware
+L_00000000040115b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6bc80_0 .net8 "VNB", 0 0, L_00000000040115b0;  1 drivers, strength-aware
+L_0000000004010820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6be60_0 .net8 "VPB", 0 0, L_0000000004010820;  1 drivers, strength-aware
+L_00000000040102e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6de40_0 .net8 "VPWR", 0 0, L_00000000040102e0;  1 drivers, strength-aware
+v0000000003a6d300_0 .net "X", 0 0, L_0000000004137680;  alias, 1 drivers
+S_0000000003a97cf0 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000003a95470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004136730 .functor OR 1, L_0000000003f93720, L_0000000004125be0, C4<0>, C4<0>;
+L_00000000041373e0 .functor OR 1, L_0000000004136ff0, L_0000000004126dd0, C4<0>, C4<0>;
+L_0000000004137060 .functor AND 1, L_0000000004136730, L_00000000041373e0, C4<1>, C4<1>;
+L_0000000004137680 .functor BUF 1, L_0000000004137060, C4<0>, C4<0>, C4<0>;
+v0000000003a6a7e0_0 .net "A1", 0 0, L_0000000004125be0;  alias, 1 drivers
+v0000000003a6b500_0 .net "A2", 0 0, L_0000000003f93720;  alias, 1 drivers
+v0000000003a6bfa0_0 .net "B1", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a6ac40_0 .net "B2", 0 0, L_0000000004136ff0;  alias, 1 drivers
+L_0000000004011770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a240_0 .net8 "VGND", 0 0, L_0000000004011770;  1 drivers, strength-aware
+L_0000000004010200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a920_0 .net8 "VNB", 0 0, L_0000000004010200;  1 drivers, strength-aware
+L_0000000004010f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a380_0 .net8 "VPB", 0 0, L_0000000004010f90;  1 drivers, strength-aware
+L_0000000004010890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6a9c0_0 .net8 "VPWR", 0 0, L_0000000004010890;  1 drivers, strength-aware
+v0000000003a6af60_0 .net "X", 0 0, L_0000000004137680;  alias, 1 drivers
+v0000000003a6b6e0_0 .net "and0_out_X", 0 0, L_0000000004137060;  1 drivers
+v0000000003a6b820_0 .net "or0_out", 0 0, L_0000000004136730;  1 drivers
+v0000000003a6a420_0 .net "or1_out", 0 0, L_00000000041373e0;  1 drivers
+S_0000000003a98ef0 .scope module, "_0739_" "sky130_fd_sc_hd__a221o_2" 3 1793, 4 98245 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a6dd00_0 .net "A1", 0 0, L_0000000004137300;  alias, 1 drivers
+v0000000003a6c220_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a6cd60_0 .net "B1", 0 0, L_0000000003f92280;  1 drivers
+v0000000003a6cea0_0 .net "B2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a6e3e0_0 .net "C1", 0 0, L_0000000004137680;  alias, 1 drivers
+L_0000000004011070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c400_0 .net8 "VGND", 0 0, L_0000000004011070;  1 drivers, strength-aware
+L_0000000004010900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ce00_0 .net8 "VNB", 0 0, L_0000000004010900;  1 drivers, strength-aware
+L_0000000004010dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e660_0 .net8 "VPB", 0 0, L_0000000004010dd0;  1 drivers, strength-aware
+L_0000000004010970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6cb80_0 .net8 "VPWR", 0 0, L_0000000004010970;  1 drivers, strength-aware
+v0000000003a6dee0_0 .net "X", 0 0, L_00000000041365e0;  alias, 1 drivers
+S_0000000003a93070 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000003a98ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004136500 .functor AND 1, L_0000000003f92280, L_0000000004130300, C4<1>, C4<1>;
+L_0000000004136570 .functor AND 1, L_0000000004137300, L_0000000004126660, C4<1>, C4<1>;
+L_0000000004137140 .functor OR 1, L_0000000004136570, L_0000000004136500, L_0000000004137680, C4<0>;
+L_00000000041365e0 .functor BUF 1, L_0000000004137140, C4<0>, C4<0>, C4<0>;
+v0000000003a6db20_0 .net "A1", 0 0, L_0000000004137300;  alias, 1 drivers
+v0000000003a6c180_0 .net "A2", 0 0, L_0000000004126660;  alias, 1 drivers
+v0000000003a6e160_0 .net "B1", 0 0, L_0000000003f92280;  alias, 1 drivers
+v0000000003a6d9e0_0 .net "B2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a6da80_0 .net "C1", 0 0, L_0000000004137680;  alias, 1 drivers
+L_0000000004010e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6dbc0_0 .net8 "VGND", 0 0, L_0000000004010e40;  1 drivers, strength-aware
+L_0000000004010a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6cfe0_0 .net8 "VNB", 0 0, L_0000000004010a50;  1 drivers, strength-aware
+L_00000000040117e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d6c0_0 .net8 "VPB", 0 0, L_00000000040117e0;  1 drivers, strength-aware
+L_0000000004011150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d620_0 .net8 "VPWR", 0 0, L_0000000004011150;  1 drivers, strength-aware
+v0000000003a6dc60_0 .net "X", 0 0, L_00000000041365e0;  alias, 1 drivers
+v0000000003a6dda0_0 .net "and0_out", 0 0, L_0000000004136500;  1 drivers
+v0000000003a6ccc0_0 .net "and1_out", 0 0, L_0000000004136570;  1 drivers
+v0000000003a6e5c0_0 .net "or0_out_X", 0 0, L_0000000004137140;  1 drivers
+S_0000000003a931f0 .scope module, "_0740_" "sky130_fd_sc_hd__o221a_2" 3 1801, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003a6e7a0_0 .net "A1", 0 0, L_0000000003f93f40;  1 drivers
+v0000000003a6d3a0_0 .net "A2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a6e520_0 .net "B1", 0 0, L_0000000004137300;  alias, 1 drivers
+v0000000003a6c720_0 .net "B2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a6c5e0_0 .net "C1", 0 0, L_0000000004137680;  alias, 1 drivers
+L_0000000004011850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d120_0 .net8 "VGND", 0 0, L_0000000004011850;  1 drivers, strength-aware
+L_0000000004010350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e200_0 .net8 "VNB", 0 0, L_0000000004010350;  1 drivers, strength-aware
+L_0000000004010b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e2a0_0 .net8 "VPB", 0 0, L_0000000004010b30;  1 drivers, strength-aware
+L_00000000040111c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c540_0 .net8 "VPWR", 0 0, L_00000000040111c0;  1 drivers, strength-aware
+v0000000003a6cc20_0 .net "X", 0 0, L_0000000004136d50;  alias, 1 drivers
+S_0000000003a934f0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003a931f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004137ca0 .functor OR 1, L_0000000004130300, L_0000000004137300, C4<0>, C4<0>;
+L_0000000004137920 .functor OR 1, L_0000000004127e00, L_0000000003f93f40, C4<0>, C4<0>;
+L_0000000004138020 .functor AND 1, L_0000000004137ca0, L_0000000004137920, L_0000000004137680, C4<1>;
+L_0000000004136d50 .functor BUF 1, L_0000000004138020, C4<0>, C4<0>, C4<0>;
+v0000000003a6d800_0 .net "A1", 0 0, L_0000000003f93f40;  alias, 1 drivers
+v0000000003a6e0c0_0 .net "A2", 0 0, L_0000000004127e00;  alias, 1 drivers
+v0000000003a6e480_0 .net "B1", 0 0, L_0000000004137300;  alias, 1 drivers
+v0000000003a6cf40_0 .net "B2", 0 0, L_0000000004130300;  alias, 1 drivers
+v0000000003a6d080_0 .net "C1", 0 0, L_0000000004137680;  alias, 1 drivers
+L_0000000004011230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c900_0 .net8 "VGND", 0 0, L_0000000004011230;  1 drivers, strength-aware
+L_0000000004010ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6cae0_0 .net8 "VNB", 0 0, L_0000000004010ba0;  1 drivers, strength-aware
+L_0000000004010c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c2c0_0 .net8 "VPB", 0 0, L_0000000004010c10;  1 drivers, strength-aware
+L_00000000040118c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d940_0 .net8 "VPWR", 0 0, L_00000000040118c0;  1 drivers, strength-aware
+v0000000003a6df80_0 .net "X", 0 0, L_0000000004136d50;  alias, 1 drivers
+v0000000003a6e8e0_0 .net "and0_out_X", 0 0, L_0000000004138020;  1 drivers
+v0000000003a6c360_0 .net "or0_out", 0 0, L_0000000004137ca0;  1 drivers
+v0000000003a6e020_0 .net "or1_out", 0 0, L_0000000004137920;  1 drivers
+S_0000000003a98170 .scope module, "_0741_" "sky130_fd_sc_hd__a21oi_2" 3 1809, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a6c4a0_0 .net "A1", 0 0, L_0000000004127d90;  alias, 1 drivers
+v0000000003a6e840_0 .net "A2", 0 0, L_00000000041365e0;  alias, 1 drivers
+v0000000003a6c7c0_0 .net "B1", 0 0, L_0000000004136d50;  alias, 1 drivers
+L_0000000004011930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c860_0 .net8 "VGND", 0 0, L_0000000004011930;  1 drivers, strength-aware
+L_00000000040112a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6c9a0_0 .net8 "VNB", 0 0, L_00000000040112a0;  1 drivers, strength-aware
+L_00000000040119a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ca40_0 .net8 "VPB", 0 0, L_00000000040119a0;  1 drivers, strength-aware
+L_00000000040113f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6eca0_0 .net8 "VPWR", 0 0, L_00000000040113f0;  1 drivers, strength-aware
+v0000000003a70460_0 .net "Y", 0 0, L_0000000004136ce0;  alias, 1 drivers
+S_0000000003a98a70 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003a98170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041370d0 .functor AND 1, L_0000000004127d90, L_00000000041365e0, C4<1>, C4<1>;
+L_0000000004136c70 .functor NOR 1, L_0000000004136d50, L_00000000041370d0, C4<0>, C4<0>;
+L_0000000004136ce0 .functor BUF 1, L_0000000004136c70, C4<0>, C4<0>, C4<0>;
+v0000000003a6d1c0_0 .net "A1", 0 0, L_0000000004127d90;  alias, 1 drivers
+v0000000003a6d260_0 .net "A2", 0 0, L_00000000041365e0;  alias, 1 drivers
+v0000000003a6d440_0 .net "B1", 0 0, L_0000000004136d50;  alias, 1 drivers
+L_0000000004012f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d760_0 .net8 "VGND", 0 0, L_0000000004012f10;  1 drivers, strength-aware
+L_0000000004012f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6d4e0_0 .net8 "VNB", 0 0, L_0000000004012f80;  1 drivers, strength-aware
+L_00000000040125e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e340_0 .net8 "VPB", 0 0, L_00000000040125e0;  1 drivers, strength-aware
+L_0000000004012500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e700_0 .net8 "VPWR", 0 0, L_0000000004012500;  1 drivers, strength-aware
+v0000000003a6d580_0 .net "Y", 0 0, L_0000000004136ce0;  alias, 1 drivers
+v0000000003a6c680_0 .net "and0_out", 0 0, L_00000000041370d0;  1 drivers
+v0000000003a6d8a0_0 .net "nor0_out_Y", 0 0, L_0000000004136c70;  1 drivers
+S_0000000003a93af0 .scope module, "_0742_" "sky130_fd_sc_hd__nor3_2" 3 1815, 4 16300 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003a6fce0_0 .net "A", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a6ee80_0 .net "B", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a6f920_0 .net "C", 0 0, L_0000000004135bd0;  alias, 1 drivers
+L_0000000004013370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ec00_0 .net8 "VGND", 0 0, L_0000000004013370;  1 drivers, strength-aware
+L_0000000004011cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ed40_0 .net8 "VNB", 0 0, L_0000000004011cb0;  1 drivers, strength-aware
+L_00000000040120a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6ede0_0 .net8 "VPB", 0 0, L_00000000040120a0;  1 drivers, strength-aware
+L_0000000004012b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a70d20_0 .net8 "VPWR", 0 0, L_0000000004012b20;  1 drivers, strength-aware
+v0000000003a708c0_0 .net "Y", 0 0, L_0000000004137ae0;  alias, 1 drivers
+S_0000000003a93c70 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16318, 4 16616 1, S_0000000003a93af0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004137a70 .functor NOR 1, L_0000000004135bd0, L_0000000004126dd0, L_00000000041271c0, C4<0>;
+L_0000000004137ae0 .functor BUF 1, L_0000000004137a70, C4<0>, C4<0>, C4<0>;
+v0000000003a70280_0 .net "A", 0 0, L_0000000004126dd0;  alias, 1 drivers
+v0000000003a70960_0 .net "B", 0 0, L_00000000041271c0;  alias, 1 drivers
+v0000000003a6f560_0 .net "C", 0 0, L_0000000004135bd0;  alias, 1 drivers
+L_0000000004012570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f7e0_0 .net8 "VGND", 0 0, L_0000000004012570;  1 drivers, strength-aware
+L_0000000004013060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a70140_0 .net8 "VNB", 0 0, L_0000000004013060;  1 drivers, strength-aware
+L_00000000040126c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a70fa0_0 .net8 "VPB", 0 0, L_00000000040126c0;  1 drivers, strength-aware
+L_0000000004012880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6fc40_0 .net8 "VPWR", 0 0, L_0000000004012880;  1 drivers, strength-aware
+v0000000003a706e0_0 .net "Y", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003a6f380_0 .net "nor0_out_Y", 0 0, L_0000000004137a70;  1 drivers
+S_0000000003a96670 .scope module, "_0743_" "sky130_fd_sc_hd__nor2_2" 3 1821, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a70a00_0 .net "A", 0 0, L_0000000004136030;  alias, 1 drivers
+v0000000003a70500_0 .net "B", 0 0, L_0000000004137ae0;  alias, 1 drivers
+L_00000000040133e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f600_0 .net8 "VGND", 0 0, L_00000000040133e0;  1 drivers, strength-aware
+L_0000000004013680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f880_0 .net8 "VNB", 0 0, L_0000000004013680;  1 drivers, strength-aware
+L_0000000004011d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f9c0_0 .net8 "VPB", 0 0, L_0000000004011d20;  1 drivers, strength-aware
+L_0000000004011fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6fec0_0 .net8 "VPWR", 0 0, L_0000000004011fc0;  1 drivers, strength-aware
+v0000000003a6fe20_0 .net "Y", 0 0, L_0000000004137610;  alias, 1 drivers
+S_0000000003a97b70 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a96670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004137d80 .functor NOR 1, L_0000000004136030, L_0000000004137ae0, C4<0>, C4<0>;
+L_0000000004137610 .functor BUF 1, L_0000000004137d80, C4<0>, C4<0>, C4<0>;
+v0000000003a701e0_0 .net "A", 0 0, L_0000000004136030;  alias, 1 drivers
+v0000000003a6fd80_0 .net "B", 0 0, L_0000000004137ae0;  alias, 1 drivers
+L_00000000040136f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a70c80_0 .net8 "VGND", 0 0, L_00000000040136f0;  1 drivers, strength-aware
+L_0000000004012180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71040_0 .net8 "VNB", 0 0, L_0000000004012180;  1 drivers, strength-aware
+L_00000000040123b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f060_0 .net8 "VPB", 0 0, L_00000000040123b0;  1 drivers, strength-aware
+L_0000000004013760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a710e0_0 .net8 "VPWR", 0 0, L_0000000004013760;  1 drivers, strength-aware
+v0000000003a70e60_0 .net "Y", 0 0, L_0000000004137610;  alias, 1 drivers
+v0000000003a70dc0_0 .net "nor0_out_Y", 0 0, L_0000000004137d80;  1 drivers
+S_0000000003a94cf0 .scope module, "_0744_" "sky130_fd_sc_hd__o32a_2" 3 1826, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003a6ef20_0 .net "A1", 0 0, L_0000000004138090;  alias, 1 drivers
+v0000000003a70000_0 .net "A2", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003a6ff60_0 .net "A3", 0 0, L_0000000004136ce0;  alias, 1 drivers
+v0000000003a6f6a0_0 .net "B1", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003a6efc0_0 .net "B2", 0 0, L_0000000004137610;  alias, 1 drivers
+L_0000000004012ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f1a0_0 .net8 "VGND", 0 0, L_0000000004012ab0;  1 drivers, strength-aware
+L_0000000004013610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f740_0 .net8 "VNB", 0 0, L_0000000004013610;  1 drivers, strength-aware
+L_00000000040128f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a700a0_0 .net8 "VPB", 0 0, L_00000000040128f0;  1 drivers, strength-aware
+L_0000000004011d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a70820_0 .net8 "VPWR", 0 0, L_0000000004011d90;  1 drivers, strength-aware
+v0000000003a6f240_0 .net "X", 0 0, L_00000000041374c0;  alias, 1 drivers
+S_0000000003a96df0 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003a94cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004137bc0 .functor OR 1, L_0000000004137370, L_0000000004138090, L_0000000004136ce0, C4<0>;
+L_0000000004136e30 .functor OR 1, L_0000000004137610, L_00000000041369d0, C4<0>, C4<0>;
+L_0000000004136a40 .functor AND 1, L_0000000004137bc0, L_0000000004136e30, C4<1>, C4<1>;
+L_00000000041374c0 .functor BUF 1, L_0000000004136a40, C4<0>, C4<0>, C4<0>;
+v0000000003a6fba0_0 .net "A1", 0 0, L_0000000004138090;  alias, 1 drivers
+v0000000003a70320_0 .net "A2", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003a70f00_0 .net "A3", 0 0, L_0000000004136ce0;  alias, 1 drivers
+v0000000003a6f100_0 .net "B1", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003a70be0_0 .net "B2", 0 0, L_0000000004137610;  alias, 1 drivers
+L_0000000004011e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a70780_0 .net8 "VGND", 0 0, L_0000000004011e00;  1 drivers, strength-aware
+L_00000000040130d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a705a0_0 .net8 "VNB", 0 0, L_00000000040130d0;  1 drivers, strength-aware
+L_00000000040121f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6e980_0 .net8 "VPB", 0 0, L_00000000040121f0;  1 drivers, strength-aware
+L_0000000004012a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6fa60_0 .net8 "VPWR", 0 0, L_0000000004012a40;  1 drivers, strength-aware
+v0000000003a6fb00_0 .net "X", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003a6ea20_0 .net "and0_out_X", 0 0, L_0000000004136a40;  1 drivers
+v0000000003a6eac0_0 .net "or0_out", 0 0, L_0000000004137bc0;  1 drivers
+v0000000003a6eb60_0 .net "or1_out", 0 0, L_0000000004136e30;  1 drivers
+S_0000000003a93f70 .scope module, "_0745_" "sky130_fd_sc_hd__and2_2" 3 1834, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a71860_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a71fe0_0 .net "B", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_0000000004012e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71720_0 .net8 "VGND", 0 0, L_0000000004012e30;  1 drivers, strength-aware
+L_0000000004012ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a73340_0 .net8 "VNB", 0 0, L_0000000004012ff0;  1 drivers, strength-aware
+L_0000000004011e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a71680_0 .net8 "VPB", 0 0, L_0000000004011e70;  1 drivers, strength-aware
+L_0000000004012490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72a80_0 .net8 "VPWR", 0 0, L_0000000004012490;  1 drivers, strength-aware
+v0000000003a735c0_0 .net "X", 0 0, L_0000000004137290;  alias, 1 drivers
+S_0000000003a97270 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a93f70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004137c30 .functor AND 1, L_0000000004135d90, L_0000000004134ba0, C4<1>, C4<1>;
+L_0000000004137290 .functor BUF 1, L_0000000004137c30, C4<0>, C4<0>, C4<0>;
+v0000000003a703c0_0 .net "A", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003a6f2e0_0 .net "B", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_0000000004011f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a70640_0 .net8 "VGND", 0 0, L_0000000004011f50;  1 drivers, strength-aware
+L_0000000004012730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f420_0 .net8 "VNB", 0 0, L_0000000004012730;  1 drivers, strength-aware
+L_0000000004012650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a6f4c0_0 .net8 "VPB", 0 0, L_0000000004012650;  1 drivers, strength-aware
+L_00000000040129d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a70aa0_0 .net8 "VPWR", 0 0, L_00000000040129d0;  1 drivers, strength-aware
+v0000000003a70b40_0 .net "X", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003a732a0_0 .net "and0_out_X", 0 0, L_0000000004137c30;  1 drivers
+S_0000000003a943f0 .scope module, "_0746_" "sky130_fd_sc_hd__o21ai_2" 3 1839, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a717c0_0 .net "A1", 0 0, L_0000000004135230;  alias, 1 drivers
+v0000000003a72080_0 .net "A2", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003a729e0_0 .net "B1", 0 0, L_0000000004134b30;  alias, 1 drivers
+L_00000000040127a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71a40_0 .net8 "VGND", 0 0, L_00000000040127a0;  1 drivers, strength-aware
+L_00000000040122d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a72b20_0 .net8 "VNB", 0 0, L_00000000040122d0;  1 drivers, strength-aware
+L_0000000004012340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a73700_0 .net8 "VPB", 0 0, L_0000000004012340;  1 drivers, strength-aware
+L_0000000004012ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a71c20_0 .net8 "VPWR", 0 0, L_0000000004012ea0;  1 drivers, strength-aware
+v0000000003a71b80_0 .net "Y", 0 0, L_0000000004136b20;  alias, 1 drivers
+S_0000000003a973f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a943f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004137df0 .functor OR 1, L_0000000004137290, L_0000000004135230, C4<0>, C4<0>;
+L_0000000004137530 .functor NAND 1, L_0000000004134b30, L_0000000004137df0, C4<1>, C4<1>;
+L_0000000004136b20 .functor BUF 1, L_0000000004137530, C4<0>, C4<0>, C4<0>;
+v0000000003a72760_0 .net "A1", 0 0, L_0000000004135230;  alias, 1 drivers
+v0000000003a72580_0 .net "A2", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003a73660_0 .net "B1", 0 0, L_0000000004134b30;  alias, 1 drivers
+L_0000000004012c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a72e40_0 .net8 "VGND", 0 0, L_0000000004012c00;  1 drivers, strength-aware
+L_0000000004013290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a73520_0 .net8 "VNB", 0 0, L_0000000004013290;  1 drivers, strength-aware
+L_0000000004013140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72260_0 .net8 "VPB", 0 0, L_0000000004013140;  1 drivers, strength-aware
+L_00000000040131b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a73840_0 .net8 "VPWR", 0 0, L_00000000040131b0;  1 drivers, strength-aware
+v0000000003a733e0_0 .net "Y", 0 0, L_0000000004136b20;  alias, 1 drivers
+v0000000003a73480_0 .net "nand0_out_Y", 0 0, L_0000000004137530;  1 drivers
+v0000000003a728a0_0 .net "or0_out", 0 0, L_0000000004137df0;  1 drivers
+S_0000000003a97e70 .scope module, "_0747_" "sky130_fd_sc_hd__o21ai_2" 3 1845, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a72ee0_0 .net "A1", 0 0, L_0000000004135f50;  alias, 1 drivers
+v0000000003a71cc0_0 .net "A2", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003a72120_0 .net "B1", 0 0, L_0000000004136b20;  alias, 1 drivers
+L_00000000040137d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71360_0 .net8 "VGND", 0 0, L_00000000040137d0;  1 drivers, strength-aware
+L_0000000004013840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71e00_0 .net8 "VNB", 0 0, L_0000000004013840;  1 drivers, strength-aware
+L_0000000004013220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72300_0 .net8 "VPB", 0 0, L_0000000004013220;  1 drivers, strength-aware
+L_0000000004013300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a71f40_0 .net8 "VPWR", 0 0, L_0000000004013300;  1 drivers, strength-aware
+v0000000003a72800_0 .net "Y", 0 0, L_0000000004137840;  alias, 1 drivers
+S_0000000003a96f70 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a97e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041368f0 .functor OR 1, L_00000000041374c0, L_0000000004135f50, C4<0>, C4<0>;
+L_0000000004136650 .functor NAND 1, L_0000000004136b20, L_00000000041368f0, C4<1>, C4<1>;
+L_0000000004137840 .functor BUF 1, L_0000000004136650, C4<0>, C4<0>, C4<0>;
+v0000000003a72bc0_0 .net "A1", 0 0, L_0000000004135f50;  alias, 1 drivers
+v0000000003a724e0_0 .net "A2", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003a72940_0 .net "B1", 0 0, L_0000000004136b20;  alias, 1 drivers
+L_0000000004013450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71900_0 .net8 "VGND", 0 0, L_0000000004013450;  1 drivers, strength-aware
+L_0000000004012dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71180_0 .net8 "VNB", 0 0, L_0000000004012dc0;  1 drivers, strength-aware
+L_0000000004012810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72c60_0 .net8 "VPB", 0 0, L_0000000004012810;  1 drivers, strength-aware
+L_0000000004012260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a73160_0 .net8 "VPWR", 0 0, L_0000000004012260;  1 drivers, strength-aware
+v0000000003a71d60_0 .net "Y", 0 0, L_0000000004137840;  alias, 1 drivers
+v0000000003a72d00_0 .net "nand0_out_Y", 0 0, L_0000000004136650;  1 drivers
+v0000000003a72da0_0 .net "or0_out", 0 0, L_00000000041368f0;  1 drivers
+S_0000000003a982f0 .scope module, "_0748_" "sky130_fd_sc_hd__inv_2" 3 1851, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003a719a0_0 .net "A", 0 0, L_0000000004137840;  alias, 1 drivers
+L_0000000004013530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a721c0_0 .net8 "VGND", 0 0, L_0000000004013530;  1 drivers, strength-aware
+L_0000000004012030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71220_0 .net8 "VNB", 0 0, L_0000000004012030;  1 drivers, strength-aware
+L_00000000040134c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a730c0_0 .net8 "VPB", 0 0, L_00000000040134c0;  1 drivers, strength-aware
+L_0000000004011ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72620_0 .net8 "VPWR", 0 0, L_0000000004011ee0;  1 drivers, strength-aware
+v0000000003a73200_0 .net "Y", 0 0, L_0000000004137990;  alias, 1 drivers
+S_0000000003a94570 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a982f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041366c0 .functor NOT 1, L_0000000004137840, C4<0>, C4<0>, C4<0>;
+L_0000000004137990 .functor BUF 1, L_00000000041366c0, C4<0>, C4<0>, C4<0>;
+v0000000003a71ea0_0 .net "A", 0 0, L_0000000004137840;  alias, 1 drivers
+L_0000000004012960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a737a0_0 .net8 "VGND", 0 0, L_0000000004012960;  1 drivers, strength-aware
+L_00000000040135a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a723a0_0 .net8 "VNB", 0 0, L_00000000040135a0;  1 drivers, strength-aware
+L_0000000004012110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72f80_0 .net8 "VPB", 0 0, L_0000000004012110;  1 drivers, strength-aware
+L_0000000004012420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a72440_0 .net8 "VPWR", 0 0, L_0000000004012420;  1 drivers, strength-aware
+v0000000003a73020_0 .net "Y", 0 0, L_0000000004137990;  alias, 1 drivers
+v0000000003a738e0_0 .net "not0_out_Y", 0 0, L_00000000041366c0;  1 drivers
+S_0000000003a970f0 .scope module, "_0749_" "sky130_fd_sc_hd__and2_2" 3 1855, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a749c0_0 .net "A", 0 0, L_0000000004133da0;  alias, 1 drivers
+v0000000003a74600_0 .net "B", 0 0, L_00000000041336a0;  alias, 1 drivers
+L_0000000004012b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75280_0 .net8 "VGND", 0 0, L_0000000004012b90;  1 drivers, strength-aware
+L_0000000004012c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a74560_0 .net8 "VNB", 0 0, L_0000000004012c70;  1 drivers, strength-aware
+L_0000000004012ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75c80_0 .net8 "VPB", 0 0, L_0000000004012ce0;  1 drivers, strength-aware
+L_0000000004012d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a746a0_0 .net8 "VPWR", 0 0, L_0000000004012d50;  1 drivers, strength-aware
+v0000000003a750a0_0 .net "X", 0 0, L_00000000041367a0;  alias, 1 drivers
+S_0000000003a955f0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a970f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041376f0 .functor AND 1, L_0000000004133da0, L_00000000041336a0, C4<1>, C4<1>;
+L_00000000041367a0 .functor BUF 1, L_00000000041376f0, C4<0>, C4<0>, C4<0>;
+v0000000003a726c0_0 .net "A", 0 0, L_0000000004133da0;  alias, 1 drivers
+v0000000003a712c0_0 .net "B", 0 0, L_00000000041336a0;  alias, 1 drivers
+L_00000000040146b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a71400_0 .net8 "VGND", 0 0, L_00000000040146b0;  1 drivers, strength-aware
+L_0000000004014c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a714a0_0 .net8 "VNB", 0 0, L_0000000004014c60;  1 drivers, strength-aware
+L_0000000004015280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a71540_0 .net8 "VPB", 0 0, L_0000000004015280;  1 drivers, strength-aware
+L_0000000004013e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a715e0_0 .net8 "VPWR", 0 0, L_0000000004013e60;  1 drivers, strength-aware
+v0000000003a71ae0_0 .net "X", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003a74a60_0 .net "and0_out_X", 0 0, L_00000000041376f0;  1 drivers
+S_0000000003a94e70 .scope module, "_0750_" "sky130_fd_sc_hd__o21ai_2" 3 1860, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a74880_0 .net "A1", 0 0, L_00000000041339b0;  alias, 1 drivers
+v0000000003a74c40_0 .net "A2", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003a75640_0 .net "B1", 0 0, L_00000000041343c0;  alias, 1 drivers
+L_0000000004014410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75000_0 .net8 "VGND", 0 0, L_0000000004014410;  1 drivers, strength-aware
+L_00000000040149c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a74740_0 .net8 "VNB", 0 0, L_00000000040149c0;  1 drivers, strength-aware
+L_00000000040152f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a756e0_0 .net8 "VPB", 0 0, L_00000000040152f0;  1 drivers, strength-aware
+L_0000000004014fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75dc0_0 .net8 "VPWR", 0 0, L_0000000004014fe0;  1 drivers, strength-aware
+v0000000003a74ba0_0 .net "Y", 0 0, L_0000000004136ab0;  alias, 1 drivers
+S_0000000003a97570 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a94e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041375a0 .functor OR 1, L_00000000041367a0, L_00000000041339b0, C4<0>, C4<0>;
+L_0000000004137760 .functor NAND 1, L_00000000041343c0, L_00000000041375a0, C4<1>, C4<1>;
+L_0000000004136ab0 .functor BUF 1, L_0000000004137760, C4<0>, C4<0>, C4<0>;
+v0000000003a742e0_0 .net "A1", 0 0, L_00000000041339b0;  alias, 1 drivers
+v0000000003a75320_0 .net "A2", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003a74d80_0 .net "B1", 0 0, L_00000000041343c0;  alias, 1 drivers
+L_0000000004014090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75aa0_0 .net8 "VGND", 0 0, L_0000000004014090;  1 drivers, strength-aware
+L_0000000004014cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a73a20_0 .net8 "VNB", 0 0, L_0000000004014cd0;  1 drivers, strength-aware
+L_0000000004014720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75820_0 .net8 "VPB", 0 0, L_0000000004014720;  1 drivers, strength-aware
+L_0000000004014aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a74060_0 .net8 "VPWR", 0 0, L_0000000004014aa0;  1 drivers, strength-aware
+v0000000003a74240_0 .net "Y", 0 0, L_0000000004136ab0;  alias, 1 drivers
+v0000000003a73ac0_0 .net "nand0_out_Y", 0 0, L_0000000004137760;  1 drivers
+v0000000003a75d20_0 .net "or0_out", 0 0, L_00000000041375a0;  1 drivers
+S_0000000003a946f0 .scope module, "_0751_" "sky130_fd_sc_hd__and2_2" 3 1866, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003a74b00_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a73980_0 .net "B", 0 0, L_0000000004134890;  alias, 1 drivers
+L_00000000040151a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a753c0_0 .net8 "VGND", 0 0, L_00000000040151a0;  1 drivers, strength-aware
+L_0000000004014560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a74ec0_0 .net8 "VNB", 0 0, L_0000000004014560;  1 drivers, strength-aware
+L_0000000004013a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a74420_0 .net8 "VPB", 0 0, L_0000000004013a00;  1 drivers, strength-aware
+L_0000000004013ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a74100_0 .net8 "VPWR", 0 0, L_0000000004013ed0;  1 drivers, strength-aware
+v0000000003a73c00_0 .net "X", 0 0, L_0000000004136c00;  alias, 1 drivers
+S_0000000003a95a70 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a946f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004136b90 .functor AND 1, L_0000000004132440, L_0000000004134890, C4<1>, C4<1>;
+L_0000000004136c00 .functor BUF 1, L_0000000004136b90, C4<0>, C4<0>, C4<0>;
+v0000000003a747e0_0 .net "A", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003a73b60_0 .net "B", 0 0, L_0000000004134890;  alias, 1 drivers
+L_0000000004013a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75be0_0 .net8 "VGND", 0 0, L_0000000004013a70;  1 drivers, strength-aware
+L_0000000004014170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a758c0_0 .net8 "VNB", 0 0, L_0000000004014170;  1 drivers, strength-aware
+L_0000000004015440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a744c0_0 .net8 "VPB", 0 0, L_0000000004015440;  1 drivers, strength-aware
+L_0000000004014800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75e60_0 .net8 "VPWR", 0 0, L_0000000004014800;  1 drivers, strength-aware
+v0000000003a75f00_0 .net "X", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003a74920_0 .net "and0_out_X", 0 0, L_0000000004136b90;  1 drivers
+S_0000000003a988f0 .scope module, "_0752_" "sky130_fd_sc_hd__o21ai_2" 3 1871, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003a75500_0 .net "A1", 0 0, L_0000000004131410;  alias, 1 drivers
+v0000000003a755a0_0 .net "A2", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003a73e80_0 .net "B1", 0 0, L_0000000004131bf0;  alias, 1 drivers
+L_0000000004014e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75780_0 .net8 "VGND", 0 0, L_0000000004014e20;  1 drivers, strength-aware
+L_0000000004015360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a75960_0 .net8 "VNB", 0 0, L_0000000004015360;  1 drivers, strength-aware
+L_00000000040138b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75a00_0 .net8 "VPB", 0 0, L_00000000040138b0;  1 drivers, strength-aware
+L_00000000040144f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75b40_0 .net8 "VPWR", 0 0, L_00000000040144f0;  1 drivers, strength-aware
+v0000000003a73de0_0 .net "Y", 0 0, L_0000000004137ed0;  alias, 1 drivers
+S_0000000003a95170 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a988f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041377d0 .functor OR 1, L_0000000004136c00, L_0000000004131410, C4<0>, C4<0>;
+L_0000000004136ea0 .functor NAND 1, L_0000000004131bf0, L_00000000041377d0, C4<1>, C4<1>;
+L_0000000004137ed0 .functor BUF 1, L_0000000004136ea0, C4<0>, C4<0>, C4<0>;
+v0000000003a741a0_0 .net "A1", 0 0, L_0000000004131410;  alias, 1 drivers
+v0000000003a75460_0 .net "A2", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003a74ce0_0 .net "B1", 0 0, L_0000000004131bf0;  alias, 1 drivers
+L_0000000004014a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a74e20_0 .net8 "VGND", 0 0, L_0000000004014a30;  1 drivers, strength-aware
+L_0000000004014100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003a74380_0 .net8 "VNB", 0 0, L_0000000004014100;  1 drivers, strength-aware
+L_0000000004013920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a75140_0 .net8 "VPB", 0 0, L_0000000004013920;  1 drivers, strength-aware
+L_0000000004014d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003a73ca0_0 .net8 "VPWR", 0 0, L_0000000004014d40;  1 drivers, strength-aware
+v0000000003a74f60_0 .net "Y", 0 0, L_0000000004137ed0;  alias, 1 drivers
+v0000000003a751e0_0 .net "nand0_out_Y", 0 0, L_0000000004136ea0;  1 drivers
+v0000000003a73d40_0 .net "or0_out", 0 0, L_00000000041377d0;  1 drivers
+S_0000000003a958f0 .scope module, "_0753_" "sky130_fd_sc_hd__o21ai_2" 3 1877, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003afb8a0_0 .net "A1", 0 0, L_0000000004134580;  alias, 1 drivers
+v0000000003af9460_0 .net "A2", 0 0, L_0000000004136ab0;  alias, 1 drivers
+v0000000003afad60_0 .net "B1", 0 0, L_0000000004137ed0;  alias, 1 drivers
+L_0000000004014db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afacc0_0 .net8 "VGND", 0 0, L_0000000004014db0;  1 drivers, strength-aware
+L_0000000004014250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afa5e0_0 .net8 "VNB", 0 0, L_0000000004014250;  1 drivers, strength-aware
+L_0000000004014f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa680_0 .net8 "VPB", 0 0, L_0000000004014f00;  1 drivers, strength-aware
+L_00000000040141e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb760_0 .net8 "VPWR", 0 0, L_00000000040141e0;  1 drivers, strength-aware
+v0000000003afaae0_0 .net "Y", 0 0, L_0000000004137d10;  alias, 1 drivers
+S_0000000003a94870 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a958f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004137f40 .functor OR 1, L_0000000004136ab0, L_0000000004134580, C4<0>, C4<0>;
+L_00000000041371b0 .functor NAND 1, L_0000000004137ed0, L_0000000004137f40, C4<1>, C4<1>;
+L_0000000004137d10 .functor BUF 1, L_00000000041371b0, C4<0>, C4<0>, C4<0>;
+v0000000003a73f20_0 .net "A1", 0 0, L_0000000004134580;  alias, 1 drivers
+v0000000003a73fc0_0 .net "A2", 0 0, L_0000000004136ab0;  alias, 1 drivers
+v0000000003afa540_0 .net "B1", 0 0, L_0000000004137ed0;  alias, 1 drivers
+L_0000000004014b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afa400_0 .net8 "VGND", 0 0, L_0000000004014b10;  1 drivers, strength-aware
+L_0000000004014b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af93c0_0 .net8 "VNB", 0 0, L_0000000004014b80;  1 drivers, strength-aware
+L_00000000040142c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003af9280_0 .net8 "VPB", 0 0, L_00000000040142c0;  1 drivers, strength-aware
+L_0000000004014330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003af9d20_0 .net8 "VPWR", 0 0, L_0000000004014330;  1 drivers, strength-aware
+v0000000003af9dc0_0 .net "Y", 0 0, L_0000000004137d10;  alias, 1 drivers
+v0000000003afafe0_0 .net "nand0_out_Y", 0 0, L_00000000041371b0;  1 drivers
+v0000000003af9320_0 .net "or0_out", 0 0, L_0000000004137f40;  1 drivers
+S_0000000003a95bf0 .scope module, "_0754_" "sky130_fd_sc_hd__inv_2" 3 1883, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003afaea0_0 .net "A", 0 0, L_0000000004137d10;  alias, 1 drivers
+L_0000000004014e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afae00_0 .net8 "VGND", 0 0, L_0000000004014e90;  1 drivers, strength-aware
+L_0000000004014020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af96e0_0 .net8 "VNB", 0 0, L_0000000004014020;  1 drivers, strength-aware
+L_0000000004015210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb1c0_0 .net8 "VPB", 0 0, L_0000000004015210;  1 drivers, strength-aware
+L_0000000004014bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa360_0 .net8 "VPWR", 0 0, L_0000000004014bf0;  1 drivers, strength-aware
+v0000000003af9500_0 .net "Y", 0 0, L_0000000004137b50;  alias, 1 drivers
+S_0000000003a98470 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a95bf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004137a00 .functor NOT 1, L_0000000004137d10, C4<0>, C4<0>, C4<0>;
+L_0000000004137b50 .functor BUF 1, L_0000000004137a00, C4<0>, C4<0>, C4<0>;
+v0000000003afa860_0 .net "A", 0 0, L_0000000004137d10;  alias, 1 drivers
+L_0000000004014f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af9820_0 .net8 "VGND", 0 0, L_0000000004014f70;  1 drivers, strength-aware
+L_00000000040143a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af91e0_0 .net8 "VNB", 0 0, L_00000000040143a0;  1 drivers, strength-aware
+L_0000000004013fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa040_0 .net8 "VPB", 0 0, L_0000000004013fb0;  1 drivers, strength-aware
+L_0000000004015050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa9a0_0 .net8 "VPWR", 0 0, L_0000000004015050;  1 drivers, strength-aware
+v0000000003afb6c0_0 .net "Y", 0 0, L_0000000004137b50;  alias, 1 drivers
+v0000000003afaa40_0 .net "not0_out_Y", 0 0, L_0000000004137a00;  1 drivers
+S_0000000003a94ff0 .scope module, "_0755_" "sky130_fd_sc_hd__o21ai_2" 3 1887, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003afac20_0 .net "A1", 0 0, L_0000000004134430;  alias, 1 drivers
+v0000000003af9640_0 .net "A2", 0 0, L_0000000004137990;  alias, 1 drivers
+v0000000003afaf40_0 .net "B1", 0 0, L_0000000004137b50;  alias, 1 drivers
+L_0000000004013ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afb300_0 .net8 "VGND", 0 0, L_0000000004013ae0;  1 drivers, strength-aware
+L_0000000004014480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af9780_0 .net8 "VNB", 0 0, L_0000000004014480;  1 drivers, strength-aware
+L_00000000040150c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb120_0 .net8 "VPB", 0 0, L_00000000040150c0;  1 drivers, strength-aware
+L_00000000040145d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb620_0 .net8 "VPWR", 0 0, L_00000000040145d0;  1 drivers, strength-aware
+v0000000003af9e60_0 .net "Y", 0 0, L_00000000041382c0;  alias, 1 drivers
+S_0000000003a95d70 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a94ff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004137e60 .functor OR 1, L_0000000004137990, L_0000000004134430, C4<0>, C4<0>;
+L_0000000004138100 .functor NAND 1, L_0000000004137b50, L_0000000004137e60, C4<1>, C4<1>;
+L_00000000041382c0 .functor BUF 1, L_0000000004138100, C4<0>, C4<0>, C4<0>;
+v0000000003afb080_0 .net "A1", 0 0, L_0000000004134430;  alias, 1 drivers
+v0000000003afa720_0 .net "A2", 0 0, L_0000000004137990;  alias, 1 drivers
+v0000000003afa7c0_0 .net "B1", 0 0, L_0000000004137b50;  alias, 1 drivers
+L_0000000004014640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afb580_0 .net8 "VGND", 0 0, L_0000000004014640;  1 drivers, strength-aware
+L_0000000004015130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afa2c0_0 .net8 "VNB", 0 0, L_0000000004015130;  1 drivers, strength-aware
+L_0000000004013d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb4e0_0 .net8 "VPB", 0 0, L_0000000004013d80;  1 drivers, strength-aware
+L_00000000040153d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003af95a0_0 .net8 "VPWR", 0 0, L_00000000040153d0;  1 drivers, strength-aware
+v0000000003af9fa0_0 .net "Y", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003afab80_0 .net "nand0_out_Y", 0 0, L_0000000004138100;  1 drivers
+v0000000003afb260_0 .net "or0_out", 0 0, L_0000000004137e60;  1 drivers
+S_0000000003a95ef0 .scope module, "_0756_" "sky130_fd_sc_hd__nor2_2" 3 1893, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003af9a00_0 .net "A", 0 0, L_0000000004132ad0;  alias, 1 drivers
+v0000000003af9aa0_0 .net "B", 0 0, L_000000000412f7a0;  alias, 1 drivers
+L_0000000004013b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af9b40_0 .net8 "VGND", 0 0, L_0000000004013b50;  1 drivers, strength-aware
+L_0000000004013990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af9be0_0 .net8 "VNB", 0 0, L_0000000004013990;  1 drivers, strength-aware
+L_0000000004013bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa900_0 .net8 "VPB", 0 0, L_0000000004013bc0;  1 drivers, strength-aware
+L_0000000004014790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003af9c80_0 .net8 "VPWR", 0 0, L_0000000004014790;  1 drivers, strength-aware
+v0000000003afa180_0 .net "Y", 0 0, L_00000000041393d0;  alias, 1 drivers
+S_0000000003a96070 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a95ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138e90 .functor NOR 1, L_0000000004132ad0, L_000000000412f7a0, C4<0>, C4<0>;
+L_00000000041393d0 .functor BUF 1, L_0000000004138e90, C4<0>, C4<0>, C4<0>;
+v0000000003afb3a0_0 .net "A", 0 0, L_0000000004132ad0;  alias, 1 drivers
+v0000000003afb440_0 .net "B", 0 0, L_000000000412f7a0;  alias, 1 drivers
+L_0000000004013c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af9140_0 .net8 "VGND", 0 0, L_0000000004013c30;  1 drivers, strength-aware
+L_0000000004014870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003af98c0_0 .net8 "VNB", 0 0, L_0000000004014870;  1 drivers, strength-aware
+L_0000000004013ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afb800_0 .net8 "VPB", 0 0, L_0000000004013ca0;  1 drivers, strength-aware
+L_0000000004013d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afa4a0_0 .net8 "VPWR", 0 0, L_0000000004013d10;  1 drivers, strength-aware
+v0000000003afa0e0_0 .net "Y", 0 0, L_00000000041393d0;  alias, 1 drivers
+v0000000003af9960_0 .net "nor0_out_Y", 0 0, L_0000000004138e90;  1 drivers
+S_0000000003a961f0 .scope module, "_0757_" "sky130_fd_sc_hd__nor2_2" 3 1898, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003afcac0_0 .net "A", 0 0, L_000000000412fb90;  alias, 1 drivers
+v0000000003afcd40_0 .net "B", 0 0, L_0000000004132c90;  alias, 1 drivers
+L_0000000004013df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afc200_0 .net8 "VGND", 0 0, L_0000000004013df0;  1 drivers, strength-aware
+L_0000000004013f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afbee0_0 .net8 "VNB", 0 0, L_0000000004013f40;  1 drivers, strength-aware
+L_00000000040148e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe0a0_0 .net8 "VPB", 0 0, L_00000000040148e0;  1 drivers, strength-aware
+L_0000000004014950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afc980_0 .net8 "VPWR", 0 0, L_0000000004014950;  1 drivers, strength-aware
+v0000000003afb940_0 .net "Y", 0 0, L_0000000004138b80;  alias, 1 drivers
+S_0000000003a96370 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a961f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004139600 .functor NOR 1, L_000000000412fb90, L_0000000004132c90, C4<0>, C4<0>;
+L_0000000004138b80 .functor BUF 1, L_0000000004139600, C4<0>, C4<0>, C4<0>;
+v0000000003af9f00_0 .net "A", 0 0, L_000000000412fb90;  alias, 1 drivers
+v0000000003afa220_0 .net "B", 0 0, L_0000000004132c90;  alias, 1 drivers
+L_0000000004016e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afc520_0 .net8 "VGND", 0 0, L_0000000004016e10;  1 drivers, strength-aware
+L_0000000004016e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afdec0_0 .net8 "VNB", 0 0, L_0000000004016e80;  1 drivers, strength-aware
+L_0000000004016ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afdf60_0 .net8 "VPB", 0 0, L_0000000004016ef0;  1 drivers, strength-aware
+L_00000000040158a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afcf20_0 .net8 "VPWR", 0 0, L_00000000040158a0;  1 drivers, strength-aware
+v0000000003afdce0_0 .net "Y", 0 0, L_0000000004138b80;  alias, 1 drivers
+v0000000003afd880_0 .net "nor0_out_Y", 0 0, L_0000000004139600;  1 drivers
+S_0000000003a967f0 .scope module, "_0758_" "sky130_fd_sc_hd__or2_2" 3 1903, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003afbd00_0 .net "A", 0 0, L_0000000004131e20;  alias, 1 drivers
+v0000000003afd380_0 .net "B", 0 0, L_000000000412f730;  alias, 1 drivers
+L_0000000004016710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afb9e0_0 .net8 "VGND", 0 0, L_0000000004016710;  1 drivers, strength-aware
+L_00000000040168d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afca20_0 .net8 "VNB", 0 0, L_00000000040168d0;  1 drivers, strength-aware
+L_0000000004015bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afc700_0 .net8 "VPB", 0 0, L_0000000004015bb0;  1 drivers, strength-aware
+L_0000000004015670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afbbc0_0 .net8 "VPWR", 0 0, L_0000000004015670;  1 drivers, strength-aware
+v0000000003afc7a0_0 .net "X", 0 0, L_0000000004139c20;  alias, 1 drivers
+S_0000000003a96970 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a967f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138bf0 .functor OR 1, L_000000000412f730, L_0000000004131e20, C4<0>, C4<0>;
+L_0000000004139c20 .functor BUF 1, L_0000000004138bf0, C4<0>, C4<0>, C4<0>;
+v0000000003afc660_0 .net "A", 0 0, L_0000000004131e20;  alias, 1 drivers
+v0000000003afc840_0 .net "B", 0 0, L_000000000412f730;  alias, 1 drivers
+L_0000000004016a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afce80_0 .net8 "VGND", 0 0, L_0000000004016a20;  1 drivers, strength-aware
+L_00000000040154b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afbc60_0 .net8 "VNB", 0 0, L_00000000040154b0;  1 drivers, strength-aware
+L_00000000040162b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afd240_0 .net8 "VPB", 0 0, L_00000000040162b0;  1 drivers, strength-aware
+L_0000000004015a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afc5c0_0 .net8 "VPWR", 0 0, L_0000000004015a60;  1 drivers, strength-aware
+v0000000003afd1a0_0 .net "X", 0 0, L_0000000004139c20;  alias, 1 drivers
+v0000000003afd2e0_0 .net "or0_out_X", 0 0, L_0000000004138bf0;  1 drivers
+S_0000000003a976f0 .scope module, "_0759_" "sky130_fd_sc_hd__o21a_2" 3 1908, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003afc020_0 .net "A1", 0 0, L_00000000041393d0;  alias, 1 drivers
+v0000000003afda60_0 .net "A2", 0 0, L_0000000004138b80;  alias, 1 drivers
+v0000000003afc2a0_0 .net "B1", 0 0, L_0000000004139c20;  alias, 1 drivers
+L_0000000004016400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afcb60_0 .net8 "VGND", 0 0, L_0000000004016400;  1 drivers, strength-aware
+L_0000000004015980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afd4c0_0 .net8 "VNB", 0 0, L_0000000004015980;  1 drivers, strength-aware
+L_0000000004016080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afc0c0_0 .net8 "VPB", 0 0, L_0000000004016080;  1 drivers, strength-aware
+L_00000000040157c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afbe40_0 .net8 "VPWR", 0 0, L_00000000040157c0;  1 drivers, strength-aware
+v0000000003afc160_0 .net "X", 0 0, L_0000000004138170;  alias, 1 drivers
+S_0000000003a97870 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a976f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004138c60 .functor OR 1, L_0000000004138b80, L_00000000041393d0, C4<0>, C4<0>;
+L_0000000004138f70 .functor AND 1, L_0000000004138c60, L_0000000004139c20, C4<1>, C4<1>;
+L_0000000004138170 .functor BUF 1, L_0000000004138f70, C4<0>, C4<0>, C4<0>;
+v0000000003afbf80_0 .net "A1", 0 0, L_00000000041393d0;  alias, 1 drivers
+v0000000003afd740_0 .net "A2", 0 0, L_0000000004138b80;  alias, 1 drivers
+v0000000003afc480_0 .net "B1", 0 0, L_0000000004139c20;  alias, 1 drivers
+L_00000000040160f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afcde0_0 .net8 "VGND", 0 0, L_00000000040160f0;  1 drivers, strength-aware
+L_0000000004015de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afd420_0 .net8 "VNB", 0 0, L_0000000004015de0;  1 drivers, strength-aware
+L_0000000004016940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afbda0_0 .net8 "VPB", 0 0, L_0000000004016940;  1 drivers, strength-aware
+L_00000000040164e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afd560_0 .net8 "VPWR", 0 0, L_00000000040164e0;  1 drivers, strength-aware
+v0000000003afc8e0_0 .net "X", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003afd9c0_0 .net "and0_out_X", 0 0, L_0000000004138f70;  1 drivers
+v0000000003afd7e0_0 .net "or0_out", 0 0, L_0000000004138c60;  1 drivers
+S_0000000003a979f0 .scope module, "_0760_" "sky130_fd_sc_hd__or2_2" 3 1914, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003afd060_0 .net "A", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003afd100_0 .net "B", 0 0, L_0000000004131090;  alias, 1 drivers
+L_0000000004016f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afc3e0_0 .net8 "VGND", 0 0, L_0000000004016f60;  1 drivers, strength-aware
+L_0000000004016fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afd920_0 .net8 "VNB", 0 0, L_0000000004016fd0;  1 drivers, strength-aware
+L_0000000004017040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe000_0 .net8 "VPB", 0 0, L_0000000004017040;  1 drivers, strength-aware
+L_0000000004015910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afd6a0_0 .net8 "VPWR", 0 0, L_0000000004015910;  1 drivers, strength-aware
+v0000000003afdb00_0 .net "X", 0 0, L_0000000004138330;  alias, 1 drivers
+S_0000000003a985f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a979f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138f00 .functor OR 1, L_0000000004131090, L_0000000004138170, C4<0>, C4<0>;
+L_0000000004138330 .functor BUF 1, L_0000000004138f00, C4<0>, C4<0>, C4<0>;
+v0000000003afcc00_0 .net "A", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003afba80_0 .net "B", 0 0, L_0000000004131090;  alias, 1 drivers
+L_0000000004016780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afcca0_0 .net8 "VGND", 0 0, L_0000000004016780;  1 drivers, strength-aware
+L_00000000040169b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afdba0_0 .net8 "VNB", 0 0, L_00000000040169b0;  1 drivers, strength-aware
+L_0000000004015c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afc340_0 .net8 "VPB", 0 0, L_0000000004015c20;  1 drivers, strength-aware
+L_00000000040156e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afd600_0 .net8 "VPWR", 0 0, L_00000000040156e0;  1 drivers, strength-aware
+v0000000003afdc40_0 .net "X", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003afcfc0_0 .net "or0_out_X", 0 0, L_0000000004138f00;  1 drivers
+S_0000000003a98770 .scope module, "_0761_" "sky130_fd_sc_hd__or2_2" 3 1919, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003affae0_0 .net "A", 0 0, L_000000000412dc10;  alias, 1 drivers
+v0000000003affe00_0 .net "B", 0 0, L_000000000412d430;  alias, 1 drivers
+L_0000000004016a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b004e0_0 .net8 "VGND", 0 0, L_0000000004016a90;  1 drivers, strength-aware
+L_0000000004015520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003aff220_0 .net8 "VNB", 0 0, L_0000000004015520;  1 drivers, strength-aware
+L_0000000004016320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b00800_0 .net8 "VPB", 0 0, L_0000000004016320;  1 drivers, strength-aware
+L_0000000004015ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003aff9a0_0 .net8 "VPWR", 0 0, L_0000000004015ad0;  1 drivers, strength-aware
+v0000000003afe500_0 .net "X", 0 0, L_00000000041385d0;  alias, 1 drivers
+S_0000000003a98bf0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a98770;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138db0 .functor OR 1, L_000000000412d430, L_000000000412dc10, C4<0>, C4<0>;
+L_00000000041385d0 .functor BUF 1, L_0000000004138db0, C4<0>, C4<0>, C4<0>;
+v0000000003afdd80_0 .net "A", 0 0, L_000000000412dc10;  alias, 1 drivers
+v0000000003afde20_0 .net "B", 0 0, L_000000000412d430;  alias, 1 drivers
+L_0000000004016470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afbb20_0 .net8 "VGND", 0 0, L_0000000004016470;  1 drivers, strength-aware
+L_00000000040159f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b008a0_0 .net8 "VNB", 0 0, L_00000000040159f0;  1 drivers, strength-aware
+L_0000000004016160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe280_0 .net8 "VPB", 0 0, L_0000000004016160;  1 drivers, strength-aware
+L_0000000004015830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afffe0_0 .net8 "VPWR", 0 0, L_0000000004015830;  1 drivers, strength-aware
+v0000000003affd60_0 .net "X", 0 0, L_00000000041385d0;  alias, 1 drivers
+v0000000003aff720_0 .net "or0_out_X", 0 0, L_0000000004138db0;  1 drivers
+S_0000000003a9ba70 .scope module, "_0762_" "sky130_fd_sc_hd__inv_2" 3 1924, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003affc20_0 .net "A", 0 0, L_00000000041385d0;  alias, 1 drivers
+L_00000000040161d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003affb80_0 .net8 "VGND", 0 0, L_00000000040161d0;  1 drivers, strength-aware
+L_0000000004015e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003aff4a0_0 .net8 "VNB", 0 0, L_0000000004015e50;  1 drivers, strength-aware
+L_0000000004016b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003aff900_0 .net8 "VPB", 0 0, L_0000000004016b00;  1 drivers, strength-aware
+L_0000000004016550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe5a0_0 .net8 "VPWR", 0 0, L_0000000004016550;  1 drivers, strength-aware
+v0000000003afe140_0 .net "Y", 0 0, L_0000000004138950;  alias, 1 drivers
+S_0000000003a9c4f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003a9ba70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004138cd0 .functor NOT 1, L_00000000041385d0, C4<0>, C4<0>, C4<0>;
+L_0000000004138950 .functor BUF 1, L_0000000004138cd0, C4<0>, C4<0>, C4<0>;
+v0000000003affa40_0 .net "A", 0 0, L_00000000041385d0;  alias, 1 drivers
+L_0000000004016b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b003a0_0 .net8 "VGND", 0 0, L_0000000004016b70;  1 drivers, strength-aware
+L_0000000004015590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003affea0_0 .net8 "VNB", 0 0, L_0000000004015590;  1 drivers, strength-aware
+L_0000000004015600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003affcc0_0 .net8 "VPB", 0 0, L_0000000004015600;  1 drivers, strength-aware
+L_0000000004016240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe6e0_0 .net8 "VPWR", 0 0, L_0000000004016240;  1 drivers, strength-aware
+v0000000003b001c0_0 .net "Y", 0 0, L_0000000004138950;  alias, 1 drivers
+v0000000003aff360_0 .net "not0_out_Y", 0 0, L_0000000004138cd0;  1 drivers
+S_0000000003a9c1f0 .scope module, "_0763_" "sky130_fd_sc_hd__nor2_2" 3 1928, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003afe460_0 .net "A", 0 0, L_000000000412c940;  alias, 1 drivers
+v0000000003aff040_0 .net "B", 0 0, L_000000000412cbe0;  alias, 1 drivers
+L_00000000040165c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00260_0 .net8 "VGND", 0 0, L_00000000040165c0;  1 drivers, strength-aware
+L_0000000004015c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00080_0 .net8 "VNB", 0 0, L_0000000004015c90;  1 drivers, strength-aware
+L_0000000004015750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b006c0_0 .net8 "VPB", 0 0, L_0000000004015750;  1 drivers, strength-aware
+L_0000000004016be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe8c0_0 .net8 "VPWR", 0 0, L_0000000004016be0;  1 drivers, strength-aware
+v0000000003aff7c0_0 .net "Y", 0 0, L_0000000004138a30;  alias, 1 drivers
+S_0000000003a9b770 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a9c1f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138410 .functor NOR 1, L_000000000412c940, L_000000000412cbe0, C4<0>, C4<0>;
+L_0000000004138a30 .functor BUF 1, L_0000000004138410, C4<0>, C4<0>, C4<0>;
+v0000000003aff540_0 .net "A", 0 0, L_000000000412c940;  alias, 1 drivers
+v0000000003aff400_0 .net "B", 0 0, L_000000000412cbe0;  alias, 1 drivers
+L_0000000004016c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afff40_0 .net8 "VGND", 0 0, L_0000000004016c50;  1 drivers, strength-aware
+L_0000000004015ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afe640_0 .net8 "VNB", 0 0, L_0000000004015ec0;  1 drivers, strength-aware
+L_0000000004016cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afe780_0 .net8 "VPB", 0 0, L_0000000004016cc0;  1 drivers, strength-aware
+L_0000000004015d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afedc0_0 .net8 "VPWR", 0 0, L_0000000004015d00;  1 drivers, strength-aware
+v0000000003aff5e0_0 .net "Y", 0 0, L_0000000004138a30;  alias, 1 drivers
+v0000000003afe820_0 .net "nor0_out_Y", 0 0, L_0000000004138410;  1 drivers
+S_0000000003a99070 .scope module, "_0764_" "sky130_fd_sc_hd__or2_2" 3 1933, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003afee60_0 .net "A", 0 0, L_000000000412ce10;  alias, 1 drivers
+v0000000003b00300_0 .net "B", 0 0, L_000000000412bf30;  alias, 1 drivers
+L_00000000040167f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00620_0 .net8 "VGND", 0 0, L_00000000040167f0;  1 drivers, strength-aware
+L_0000000004016860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00760_0 .net8 "VNB", 0 0, L_0000000004016860;  1 drivers, strength-aware
+L_0000000004015f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003aff0e0_0 .net8 "VPB", 0 0, L_0000000004015f30;  1 drivers, strength-aware
+L_0000000004015d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003aff180_0 .net8 "VPWR", 0 0, L_0000000004015d70;  1 drivers, strength-aware
+v0000000003aff680_0 .net "X", 0 0, L_0000000004138d40;  alias, 1 drivers
+S_0000000003a9acf0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a99070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041392f0 .functor OR 1, L_000000000412bf30, L_000000000412ce10, C4<0>, C4<0>;
+L_0000000004138d40 .functor BUF 1, L_00000000041392f0, C4<0>, C4<0>, C4<0>;
+v0000000003b00440_0 .net "A", 0 0, L_000000000412ce10;  alias, 1 drivers
+v0000000003afe1e0_0 .net "B", 0 0, L_000000000412bf30;  alias, 1 drivers
+L_0000000004016d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afefa0_0 .net8 "VGND", 0 0, L_0000000004016d30;  1 drivers, strength-aware
+L_0000000004015fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afe320_0 .net8 "VNB", 0 0, L_0000000004015fa0;  1 drivers, strength-aware
+L_0000000004016da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b00580_0 .net8 "VPB", 0 0, L_0000000004016da0;  1 drivers, strength-aware
+L_0000000004016630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afef00_0 .net8 "VPWR", 0 0, L_0000000004016630;  1 drivers, strength-aware
+v0000000003afe3c0_0 .net "X", 0 0, L_0000000004138d40;  alias, 1 drivers
+v0000000003b00120_0 .net "or0_out_X", 0 0, L_00000000041392f0;  1 drivers
+S_0000000003a9a270 .scope module, "_0765_" "sky130_fd_sc_hd__o21a_2" 3 1938, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b01480_0 .net "A1", 0 0, L_0000000004138950;  alias, 1 drivers
+v0000000003b00f80_0 .net "A2", 0 0, L_0000000004138a30;  alias, 1 drivers
+v0000000003b02600_0 .net "B1", 0 0, L_0000000004138d40;  alias, 1 drivers
+L_0000000004015b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b013e0_0 .net8 "VGND", 0 0, L_0000000004015b40;  1 drivers, strength-aware
+L_0000000004016010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b01520_0 .net8 "VNB", 0 0, L_0000000004016010;  1 drivers, strength-aware
+L_0000000004016390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b01d40_0 .net8 "VPB", 0 0, L_0000000004016390;  1 drivers, strength-aware
+L_00000000040166a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02420_0 .net8 "VPWR", 0 0, L_00000000040166a0;  1 drivers, strength-aware
+v0000000003b015c0_0 .net "X", 0 0, L_00000000041381e0;  alias, 1 drivers
+S_0000000003a9b8f0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003a9a270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004139c90 .functor OR 1, L_0000000004138a30, L_0000000004138950, C4<0>, C4<0>;
+L_0000000004139050 .functor AND 1, L_0000000004139c90, L_0000000004138d40, C4<1>, C4<1>;
+L_00000000041381e0 .functor BUF 1, L_0000000004139050, C4<0>, C4<0>, C4<0>;
+v0000000003aff860_0 .net "A1", 0 0, L_0000000004138950;  alias, 1 drivers
+v0000000003afe960_0 .net "A2", 0 0, L_0000000004138a30;  alias, 1 drivers
+v0000000003afea00_0 .net "B1", 0 0, L_0000000004138d40;  alias, 1 drivers
+L_00000000040172e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afec80_0 .net8 "VGND", 0 0, L_00000000040172e0;  1 drivers, strength-aware
+L_0000000004017c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003afeaa0_0 .net8 "VNB", 0 0, L_0000000004017c10;  1 drivers, strength-aware
+L_0000000004018850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afeb40_0 .net8 "VPB", 0 0, L_0000000004018850;  1 drivers, strength-aware
+L_0000000004017900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003afebe0_0 .net8 "VPWR", 0 0, L_0000000004017900;  1 drivers, strength-aware
+v0000000003afed20_0 .net "X", 0 0, L_00000000041381e0;  alias, 1 drivers
+v0000000003aff2c0_0 .net "and0_out_X", 0 0, L_0000000004139050;  1 drivers
+v0000000003b01f20_0 .net "or0_out", 0 0, L_0000000004139c90;  1 drivers
+S_0000000003a9c670 .scope module, "_0766_" "sky130_fd_sc_hd__or2_2" 3 1944, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b00ee0_0 .net "A", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000003b01a20_0 .net "B", 0 0, L_00000000041381e0;  alias, 1 drivers
+L_0000000004017ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03000_0 .net8 "VGND", 0 0, L_0000000004017ac0;  1 drivers, strength-aware
+L_00000000040181c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b021a0_0 .net8 "VNB", 0 0, L_00000000040181c0;  1 drivers, strength-aware
+L_0000000004017580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b00d00_0 .net8 "VPB", 0 0, L_0000000004017580;  1 drivers, strength-aware
+L_0000000004018bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b012a0_0 .net8 "VPWR", 0 0, L_0000000004018bd0;  1 drivers, strength-aware
+v0000000003b01020_0 .net "X", 0 0, L_0000000004139590;  alias, 1 drivers
+S_0000000003a9a0f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a9c670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138e20 .functor OR 1, L_00000000041381e0, L_000000000412bd00, C4<0>, C4<0>;
+L_0000000004139590 .functor BUF 1, L_0000000004138e20, C4<0>, C4<0>, C4<0>;
+v0000000003b02ec0_0 .net "A", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000003b02a60_0 .net "B", 0 0, L_00000000041381e0;  alias, 1 drivers
+L_0000000004017350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00a80_0 .net8 "VGND", 0 0, L_0000000004017350;  1 drivers, strength-aware
+L_0000000004018c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b027e0_0 .net8 "VNB", 0 0, L_0000000004018c40;  1 drivers, strength-aware
+L_0000000004018460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02560_0 .net8 "VPB", 0 0, L_0000000004018460;  1 drivers, strength-aware
+L_0000000004017eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02240_0 .net8 "VPWR", 0 0, L_0000000004017eb0;  1 drivers, strength-aware
+v0000000003b02880_0 .net "X", 0 0, L_0000000004139590;  alias, 1 drivers
+v0000000003b02d80_0 .net "or0_out_X", 0 0, L_0000000004138e20;  1 drivers
+S_0000000003a9cc70 .scope module, "_0767_" "sky130_fd_sc_hd__and2_2" 3 1949, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b01660_0 .net "A", 0 0, L_000000000412e000;  alias, 1 drivers
+v0000000003b02100_0 .net "B", 0 0, L_0000000004139590;  alias, 1 drivers
+L_0000000004018690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00da0_0 .net8 "VGND", 0 0, L_0000000004018690;  1 drivers, strength-aware
+L_0000000004017cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b00940_0 .net8 "VNB", 0 0, L_0000000004017cf0;  1 drivers, strength-aware
+L_00000000040174a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b018e0_0 .net8 "VPB", 0 0, L_00000000040174a0;  1 drivers, strength-aware
+L_0000000004017430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02c40_0 .net8 "VPWR", 0 0, L_0000000004017430;  1 drivers, strength-aware
+v0000000003b01700_0 .net "X", 0 0, L_0000000004138fe0;  alias, 1 drivers
+S_0000000003a9c070 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003a9cc70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041383a0 .functor AND 1, L_000000000412e000, L_0000000004139590, C4<1>, C4<1>;
+L_0000000004138fe0 .functor BUF 1, L_00000000041383a0, C4<0>, C4<0>, C4<0>;
+v0000000003b02ba0_0 .net "A", 0 0, L_000000000412e000;  alias, 1 drivers
+v0000000003b026a0_0 .net "B", 0 0, L_0000000004139590;  alias, 1 drivers
+L_00000000040175f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b024c0_0 .net8 "VGND", 0 0, L_00000000040175f0;  1 drivers, strength-aware
+L_00000000040173c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b02740_0 .net8 "VNB", 0 0, L_00000000040173c0;  1 drivers, strength-aware
+L_0000000004017b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b029c0_0 .net8 "VPB", 0 0, L_0000000004017b30;  1 drivers, strength-aware
+L_0000000004018a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02920_0 .net8 "VPWR", 0 0, L_0000000004018a80;  1 drivers, strength-aware
+v0000000003b00c60_0 .net "X", 0 0, L_0000000004138fe0;  alias, 1 drivers
+v0000000003b02b00_0 .net "and0_out_X", 0 0, L_00000000041383a0;  1 drivers
+S_0000000003a9c370 .scope module, "_0768_" "sky130_fd_sc_hd__a21oi_2" 3 1954, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b030a0_0 .net "A1", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003b02f60_0 .net "A2", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003b01b60_0 .net "B1", 0 0, L_0000000004138fe0;  alias, 1 drivers
+L_0000000004017d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b009e0_0 .net8 "VGND", 0 0, L_0000000004017d60;  1 drivers, strength-aware
+L_0000000004018540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b022e0_0 .net8 "VNB", 0 0, L_0000000004018540;  1 drivers, strength-aware
+L_0000000004017270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b01de0_0 .net8 "VPB", 0 0, L_0000000004017270;  1 drivers, strength-aware
+L_0000000004017e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b017a0_0 .net8 "VPWR", 0 0, L_0000000004017e40;  1 drivers, strength-aware
+v0000000003b01fc0_0 .net "Y", 0 0, L_00000000041389c0;  alias, 1 drivers
+S_0000000003a9aff0 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003a9c370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041398a0 .functor AND 1, L_0000000004131250, L_0000000004138330, C4<1>, C4<1>;
+L_0000000004138250 .functor NOR 1, L_0000000004138fe0, L_00000000041398a0, C4<0>, C4<0>;
+L_00000000041389c0 .functor BUF 1, L_0000000004138250, C4<0>, C4<0>, C4<0>;
+v0000000003b00e40_0 .net "A1", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003b00b20_0 .net "A2", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003b01ac0_0 .net "B1", 0 0, L_0000000004138fe0;  alias, 1 drivers
+L_0000000004017dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b010c0_0 .net8 "VGND", 0 0, L_0000000004017dd0;  1 drivers, strength-aware
+L_00000000040179e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b01980_0 .net8 "VNB", 0 0, L_00000000040179e0;  1 drivers, strength-aware
+L_0000000004017510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b01160_0 .net8 "VPB", 0 0, L_0000000004017510;  1 drivers, strength-aware
+L_0000000004018230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02e20_0 .net8 "VPWR", 0 0, L_0000000004018230;  1 drivers, strength-aware
+v0000000003b01200_0 .net "Y", 0 0, L_00000000041389c0;  alias, 1 drivers
+v0000000003b02ce0_0 .net "and0_out", 0 0, L_00000000041398a0;  1 drivers
+v0000000003b01340_0 .net "nor0_out_Y", 0 0, L_0000000004138250;  1 drivers
+S_0000000003a991f0 .scope module, "_0769_" "sky130_fd_sc_hd__o21ai_2" 3 1960, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b04d60_0 .net "A1", 0 0, L_00000000041312c0;  alias, 1 drivers
+v0000000003b04720_0 .net "A2", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b04540_0 .net "B1", 0 0, L_00000000041389c0;  alias, 1 drivers
+L_0000000004017ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b05760_0 .net8 "VGND", 0 0, L_0000000004017ba0;  1 drivers, strength-aware
+L_0000000004017120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04ae0_0 .net8 "VNB", 0 0, L_0000000004017120;  1 drivers, strength-aware
+L_0000000004017660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b054e0_0 .net8 "VPB", 0 0, L_0000000004017660;  1 drivers, strength-aware
+L_0000000004018700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b036e0_0 .net8 "VPWR", 0 0, L_0000000004018700;  1 drivers, strength-aware
+v0000000003b04220_0 .net "Y", 0 0, L_00000000041384f0;  alias, 1 drivers
+S_0000000003a9caf0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a991f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004139360 .functor OR 1, L_00000000041382c0, L_00000000041312c0, C4<0>, C4<0>;
+L_0000000004138480 .functor NAND 1, L_00000000041389c0, L_0000000004139360, C4<1>, C4<1>;
+L_00000000041384f0 .functor BUF 1, L_0000000004138480, C4<0>, C4<0>, C4<0>;
+v0000000003b00bc0_0 .net "A1", 0 0, L_00000000041312c0;  alias, 1 drivers
+v0000000003b01840_0 .net "A2", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b01c00_0 .net "B1", 0 0, L_00000000041389c0;  alias, 1 drivers
+L_0000000004018770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b01ca0_0 .net8 "VGND", 0 0, L_0000000004018770;  1 drivers, strength-aware
+L_00000000040170b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b01e80_0 .net8 "VNB", 0 0, L_00000000040170b0;  1 drivers, strength-aware
+L_00000000040176d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02060_0 .net8 "VPB", 0 0, L_00000000040176d0;  1 drivers, strength-aware
+L_0000000004017f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b02380_0 .net8 "VPWR", 0 0, L_0000000004017f20;  1 drivers, strength-aware
+v0000000003b04900_0 .net "Y", 0 0, L_00000000041384f0;  alias, 1 drivers
+v0000000003b03820_0 .net "nand0_out_Y", 0 0, L_0000000004138480;  1 drivers
+v0000000003b058a0_0 .net "or0_out", 0 0, L_0000000004139360;  1 drivers
+S_0000000003a997f0 .scope module, "_0770_" "sky130_fd_sc_hd__nor2_2" 3 1966, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b05080_0 .net "A", 0 0, L_000000000412de40;  alias, 1 drivers
+v0000000003b03460_0 .net "B", 0 0, L_000000000412ddd0;  alias, 1 drivers
+L_0000000004017970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04c20_0 .net8 "VGND", 0 0, L_0000000004017970;  1 drivers, strength-aware
+L_00000000040184d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03500_0 .net8 "VNB", 0 0, L_00000000040184d0;  1 drivers, strength-aware
+L_0000000004017c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b044a0_0 .net8 "VPB", 0 0, L_0000000004017c80;  1 drivers, strength-aware
+L_0000000004017f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b04a40_0 .net8 "VPWR", 0 0, L_0000000004017f90;  1 drivers, strength-aware
+v0000000003b035a0_0 .net "Y", 0 0, L_0000000004138aa0;  alias, 1 drivers
+S_0000000003a99df0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a997f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004139670 .functor NOR 1, L_000000000412de40, L_000000000412ddd0, C4<0>, C4<0>;
+L_0000000004138aa0 .functor BUF 1, L_0000000004139670, C4<0>, C4<0>, C4<0>;
+v0000000003b03640_0 .net "A", 0 0, L_000000000412de40;  alias, 1 drivers
+v0000000003b049a0_0 .net "B", 0 0, L_000000000412ddd0;  alias, 1 drivers
+L_00000000040187e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04fe0_0 .net8 "VGND", 0 0, L_00000000040187e0;  1 drivers, strength-aware
+L_0000000004018af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b05580_0 .net8 "VNB", 0 0, L_0000000004018af0;  1 drivers, strength-aware
+L_0000000004017190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b03d20_0 .net8 "VPB", 0 0, L_0000000004017190;  1 drivers, strength-aware
+L_0000000004017740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b03b40_0 .net8 "VPWR", 0 0, L_0000000004017740;  1 drivers, strength-aware
+v0000000003b04cc0_0 .net "Y", 0 0, L_0000000004138aa0;  alias, 1 drivers
+v0000000003b03780_0 .net "nor0_out_Y", 0 0, L_0000000004139670;  1 drivers
+S_0000000003a9bbf0 .scope module, "_0771_" "sky130_fd_sc_hd__or2_2" 3 1971, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b033c0_0 .net "A", 0 0, L_000000000412ed20;  alias, 1 drivers
+v0000000003b03960_0 .net "B", 0 0, L_000000000412a800;  alias, 1 drivers
+L_0000000004018b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04040_0 .net8 "VGND", 0 0, L_0000000004018b60;  1 drivers, strength-aware
+L_00000000040177b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b05620_0 .net8 "VNB", 0 0, L_00000000040177b0;  1 drivers, strength-aware
+L_0000000004017820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b05120_0 .net8 "VPB", 0 0, L_0000000004017820;  1 drivers, strength-aware
+L_0000000004017200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b04e00_0 .net8 "VPWR", 0 0, L_0000000004017200;  1 drivers, strength-aware
+v0000000003b03a00_0 .net "X", 0 0, L_00000000041399f0;  alias, 1 drivers
+S_0000000003a9a570 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a9bbf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138560 .functor OR 1, L_000000000412a800, L_000000000412ed20, C4<0>, C4<0>;
+L_00000000041399f0 .functor BUF 1, L_0000000004138560, C4<0>, C4<0>, C4<0>;
+v0000000003b04b80_0 .net "A", 0 0, L_000000000412ed20;  alias, 1 drivers
+v0000000003b05800_0 .net "B", 0 0, L_000000000412a800;  alias, 1 drivers
+L_00000000040188c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04400_0 .net8 "VGND", 0 0, L_00000000040188c0;  1 drivers, strength-aware
+L_0000000004017890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03280_0 .net8 "VNB", 0 0, L_0000000004017890;  1 drivers, strength-aware
+L_0000000004018620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b038c0_0 .net8 "VPB", 0 0, L_0000000004018620;  1 drivers, strength-aware
+L_0000000004018000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b03320_0 .net8 "VPWR", 0 0, L_0000000004018000;  1 drivers, strength-aware
+v0000000003b03dc0_0 .net "X", 0 0, L_00000000041399f0;  alias, 1 drivers
+v0000000003b045e0_0 .net "or0_out_X", 0 0, L_0000000004138560;  1 drivers
+S_0000000003a9c7f0 .scope module, "_0772_" "sky130_fd_sc_hd__or2_2" 3 1976, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b051c0_0 .net "A", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000003b05260_0 .net "B", 0 0, L_000000000412e0e0;  alias, 1 drivers
+L_0000000004017a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b040e0_0 .net8 "VGND", 0 0, L_0000000004017a50;  1 drivers, strength-aware
+L_00000000040185b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b04180_0 .net8 "VNB", 0 0, L_00000000040185b0;  1 drivers, strength-aware
+L_0000000004018070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b04680_0 .net8 "VPB", 0 0, L_0000000004018070;  1 drivers, strength-aware
+L_00000000040180e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b03aa0_0 .net8 "VPWR", 0 0, L_00000000040180e0;  1 drivers, strength-aware
+v0000000003b05300_0 .net "X", 0 0, L_0000000004138b10;  alias, 1 drivers
+S_0000000003a9c970 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a9c7f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041396e0 .functor OR 1, L_000000000412e0e0, L_000000000412e690, C4<0>, C4<0>;
+L_0000000004138b10 .functor BUF 1, L_00000000041396e0, C4<0>, C4<0>, C4<0>;
+v0000000003b04ea0_0 .net "A", 0 0, L_000000000412e690;  alias, 1 drivers
+v0000000003b05440_0 .net "B", 0 0, L_000000000412e0e0;  alias, 1 drivers
+L_0000000004018150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03140_0 .net8 "VGND", 0 0, L_0000000004018150;  1 drivers, strength-aware
+L_0000000004018930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03fa0_0 .net8 "VNB", 0 0, L_0000000004018930;  1 drivers, strength-aware
+L_00000000040183f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b031e0_0 .net8 "VPB", 0 0, L_00000000040183f0;  1 drivers, strength-aware
+L_00000000040182a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b056c0_0 .net8 "VPWR", 0 0, L_00000000040182a0;  1 drivers, strength-aware
+v0000000003b04f40_0 .net "X", 0 0, L_0000000004138b10;  alias, 1 drivers
+v0000000003b03e60_0 .net "or0_out_X", 0 0, L_00000000041396e0;  1 drivers
+S_0000000003a9cdf0 .scope module, "_0773_" "sky130_fd_sc_hd__o21ai_2" 3 1981, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b07740_0 .net "A1", 0 0, L_0000000004138aa0;  alias, 1 drivers
+v0000000003b08000_0 .net "A2", 0 0, L_00000000041399f0;  alias, 1 drivers
+v0000000003b05bc0_0 .net "B1", 0 0, L_0000000004138b10;  alias, 1 drivers
+L_00000000040189a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06d40_0 .net8 "VGND", 0 0, L_00000000040189a0;  1 drivers, strength-aware
+L_0000000004018310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06ca0_0 .net8 "VNB", 0 0, L_0000000004018310;  1 drivers, strength-aware
+L_0000000004018380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b06c00_0 .net8 "VPB", 0 0, L_0000000004018380;  1 drivers, strength-aware
+L_0000000004018a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b05c60_0 .net8 "VPWR", 0 0, L_0000000004018a10;  1 drivers, strength-aware
+v0000000003b071a0_0 .net "Y", 0 0, L_00000000041397c0;  alias, 1 drivers
+S_0000000003a9b2f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003a9cdf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004138640 .functor OR 1, L_00000000041399f0, L_0000000004138aa0, C4<0>, C4<0>;
+L_0000000004139830 .functor NAND 1, L_0000000004138b10, L_0000000004138640, C4<1>, C4<1>;
+L_00000000041397c0 .functor BUF 1, L_0000000004139830, C4<0>, C4<0>, C4<0>;
+v0000000003b053a0_0 .net "A1", 0 0, L_0000000004138aa0;  alias, 1 drivers
+v0000000003b03be0_0 .net "A2", 0 0, L_00000000041399f0;  alias, 1 drivers
+v0000000003b03c80_0 .net "B1", 0 0, L_0000000004138b10;  alias, 1 drivers
+L_0000000004018e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b03f00_0 .net8 "VGND", 0 0, L_0000000004018e70;  1 drivers, strength-aware
+L_0000000004018d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b042c0_0 .net8 "VNB", 0 0, L_0000000004018d90;  1 drivers, strength-aware
+L_0000000004018d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b04360_0 .net8 "VPB", 0 0, L_0000000004018d20;  1 drivers, strength-aware
+L_0000000004018ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b047c0_0 .net8 "VPWR", 0 0, L_0000000004018ee0;  1 drivers, strength-aware
+v0000000003b04860_0 .net "Y", 0 0, L_00000000041397c0;  alias, 1 drivers
+v0000000003b068e0_0 .net "nand0_out_Y", 0 0, L_0000000004139830;  1 drivers
+v0000000003b06980_0 .net "or0_out", 0 0, L_0000000004138640;  1 drivers
+S_0000000003a9a870 .scope module, "_0774_" "sky130_fd_sc_hd__or2_2" 3 1987, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b063e0_0 .net "A", 0 0, L_000000000412e380;  alias, 1 drivers
+v0000000003b07c40_0 .net "B", 0 0, L_00000000041397c0;  alias, 1 drivers
+L_0000000004018f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b05a80_0 .net8 "VGND", 0 0, L_0000000004018f50;  1 drivers, strength-aware
+L_0000000004018e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b079c0_0 .net8 "VNB", 0 0, L_0000000004018e00;  1 drivers, strength-aware
+L_0000000004018cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b060c0_0 .net8 "VPB", 0 0, L_0000000004018cb0;  1 drivers, strength-aware
+L_0000000004009ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b07a60_0 .net8 "VPWR", 0 0, L_0000000004009ba0;  1 drivers, strength-aware
+v0000000003b07ba0_0 .net "X", 0 0, L_00000000041386b0;  alias, 1 drivers
+S_0000000003a99370 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a9a870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004139ad0 .functor OR 1, L_00000000041397c0, L_000000000412e380, C4<0>, C4<0>;
+L_00000000041386b0 .functor BUF 1, L_0000000004139ad0, C4<0>, C4<0>, C4<0>;
+v0000000003b06340_0 .net "A", 0 0, L_000000000412e380;  alias, 1 drivers
+v0000000003b07240_0 .net "B", 0 0, L_00000000041397c0;  alias, 1 drivers
+L_000000000400a1c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b080a0_0 .net8 "VGND", 0 0, L_000000000400a1c0;  1 drivers, strength-aware
+L_00000000040096d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06480_0 .net8 "VNB", 0 0, L_00000000040096d0;  1 drivers, strength-aware
+L_00000000040095f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b05f80_0 .net8 "VPB", 0 0, L_00000000040095f0;  1 drivers, strength-aware
+L_0000000004009200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b077e0_0 .net8 "VPWR", 0 0, L_0000000004009200;  1 drivers, strength-aware
+v0000000003b05940_0 .net "X", 0 0, L_00000000041386b0;  alias, 1 drivers
+v0000000003b05d00_0 .net "or0_out_X", 0 0, L_0000000004139ad0;  1 drivers
+S_0000000003a994f0 .scope module, "_0775_" "sky130_fd_sc_hd__a31oi_2" 3 1992, 4 72663 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+v0000000003b074c0_0 .net "A1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+v0000000003b07560_0 .net "A2", 0 0, L_000000000412f2d0;  alias, 1 drivers
+v0000000003b07600_0 .net "A3", 0 0, L_00000000041384f0;  alias, 1 drivers
+v0000000003b07d80_0 .net "B1", 0 0, L_00000000041386b0;  alias, 1 drivers
+L_0000000004009e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b07e20_0 .net8 "VGND", 0 0, L_0000000004009e40;  1 drivers, strength-aware
+L_00000000040099e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b076a0_0 .net8 "VNB", 0 0, L_00000000040099e0;  1 drivers, strength-aware
+L_000000000400a2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b07920_0 .net8 "VPB", 0 0, L_000000000400a2a0;  1 drivers, strength-aware
+L_000000000400ab60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b06520_0 .net8 "VPWR", 0 0, L_000000000400ab60;  1 drivers, strength-aware
+v0000000003b07b00_0 .net "Y", 0 0, L_0000000004138790;  alias, 1 drivers
+S_0000000003a99670 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72683, 4 72538 1, S_0000000003a994f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004138720 .functor AND 1, L_00000000041384f0, L_000000000412d9e0, L_000000000412f2d0, C4<1>;
+L_0000000004139a60 .functor NOR 1, L_00000000041386b0, L_0000000004138720, C4<0>, C4<0>;
+L_0000000004138790 .functor BUF 1, L_0000000004139a60, C4<0>, C4<0>, C4<0>;
+v0000000003b06f20_0 .net "A1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+v0000000003b07880_0 .net "A2", 0 0, L_000000000412f2d0;  alias, 1 drivers
+v0000000003b072e0_0 .net "A3", 0 0, L_00000000041384f0;  alias, 1 drivers
+v0000000003b07ce0_0 .net "B1", 0 0, L_00000000041386b0;  alias, 1 drivers
+L_000000000400a8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b05ee0_0 .net8 "VGND", 0 0, L_000000000400a8c0;  1 drivers, strength-aware
+L_0000000004009350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b067a0_0 .net8 "VNB", 0 0, L_0000000004009350;  1 drivers, strength-aware
+L_000000000400a9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b07380_0 .net8 "VPB", 0 0, L_000000000400a9a0;  1 drivers, strength-aware
+L_00000000040090b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b07420_0 .net8 "VPWR", 0 0, L_00000000040090b0;  1 drivers, strength-aware
+v0000000003b05da0_0 .net "Y", 0 0, L_0000000004138790;  alias, 1 drivers
+v0000000003b062a0_0 .net "and0_out", 0 0, L_0000000004138720;  1 drivers
+v0000000003b06020_0 .net "nor0_out_Y", 0 0, L_0000000004139a60;  1 drivers
+S_0000000003a99970 .scope module, "_0776_" "sky130_fd_sc_hd__nor2_2" 3 1999, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b05b20_0 .net "A", 0 0, L_0000000004129c30;  alias, 1 drivers
+v0000000003b05e40_0 .net "B", 0 0, L_00000000041285e0;  alias, 1 drivers
+L_0000000004009cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06160_0 .net8 "VGND", 0 0, L_0000000004009cf0;  1 drivers, strength-aware
+L_0000000004009a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06660_0 .net8 "VNB", 0 0, L_0000000004009a50;  1 drivers, strength-aware
+L_000000000400a540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b06fc0_0 .net8 "VPB", 0 0, L_000000000400a540;  1 drivers, strength-aware
+L_000000000400a0e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b06700_0 .net8 "VPWR", 0 0, L_000000000400a0e0;  1 drivers, strength-aware
+v0000000003b07060_0 .net "Y", 0 0, L_0000000004138870;  alias, 1 drivers
+S_0000000003a99af0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a99970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004138800 .functor NOR 1, L_0000000004129c30, L_00000000041285e0, C4<0>, C4<0>;
+L_0000000004138870 .functor BUF 1, L_0000000004138800, C4<0>, C4<0>, C4<0>;
+v0000000003b07ec0_0 .net "A", 0 0, L_0000000004129c30;  alias, 1 drivers
+v0000000003b06de0_0 .net "B", 0 0, L_00000000041285e0;  alias, 1 drivers
+L_000000000400a620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06a20_0 .net8 "VGND", 0 0, L_000000000400a620;  1 drivers, strength-aware
+L_000000000400abd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b07f60_0 .net8 "VNB", 0 0, L_000000000400abd0;  1 drivers, strength-aware
+L_000000000400ac40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b065c0_0 .net8 "VPB", 0 0, L_000000000400ac40;  1 drivers, strength-aware
+L_0000000004009d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b06840_0 .net8 "VPWR", 0 0, L_0000000004009d60;  1 drivers, strength-aware
+v0000000003b07100_0 .net "Y", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003b06e80_0 .net "nor0_out_Y", 0 0, L_0000000004138800;  1 drivers
+S_0000000003a9a3f0 .scope module, "_0777_" "sky130_fd_sc_hd__nor2_2" 3 2004, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b08fa0_0 .net "A", 0 0, L_000000000412a090;  alias, 1 drivers
+v0000000003b0a800_0 .net "B", 0 0, L_0000000004129fb0;  alias, 1 drivers
+L_000000000400a230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a620_0 .net8 "VGND", 0 0, L_000000000400a230;  1 drivers, strength-aware
+L_0000000004009890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b09ae0_0 .net8 "VNB", 0 0, L_0000000004009890;  1 drivers, strength-aware
+L_0000000004009120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08e60_0 .net8 "VPB", 0 0, L_0000000004009120;  1 drivers, strength-aware
+L_000000000400a5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a120_0 .net8 "VPWR", 0 0, L_000000000400a5b0;  1 drivers, strength-aware
+v0000000003b09d60_0 .net "Y", 0 0, L_00000000041394b0;  alias, 1 drivers
+S_0000000003a99c70 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a9a3f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041388e0 .functor NOR 1, L_000000000412a090, L_0000000004129fb0, C4<0>, C4<0>;
+L_00000000041394b0 .functor BUF 1, L_00000000041388e0, C4<0>, C4<0>, C4<0>;
+v0000000003b06200_0 .net "A", 0 0, L_000000000412a090;  alias, 1 drivers
+v0000000003b059e0_0 .net "B", 0 0, L_0000000004129fb0;  alias, 1 drivers
+L_000000000400a4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06ac0_0 .net8 "VGND", 0 0, L_000000000400a4d0;  1 drivers, strength-aware
+L_0000000004009ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b06b60_0 .net8 "VNB", 0 0, L_0000000004009ac0;  1 drivers, strength-aware
+L_000000000400a700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b09e00_0 .net8 "VPB", 0 0, L_000000000400a700;  1 drivers, strength-aware
+L_0000000004009900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b09c20_0 .net8 "VPWR", 0 0, L_0000000004009900;  1 drivers, strength-aware
+v0000000003b09cc0_0 .net "Y", 0 0, L_00000000041394b0;  alias, 1 drivers
+v0000000003b0a440_0 .net "nor0_out_Y", 0 0, L_00000000041388e0;  1 drivers
+S_0000000003a99f70 .scope module, "_0778_" "sky130_fd_sc_hd__nor2_2" 3 2009, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b09fe0_0 .net "A", 0 0, L_0000000004128810;  alias, 1 drivers
+v0000000003b08f00_0 .net "B", 0 0, L_0000000004128a40;  alias, 1 drivers
+L_000000000400a310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a1c0_0 .net8 "VGND", 0 0, L_000000000400a310;  1 drivers, strength-aware
+L_000000000400a380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a080_0 .net8 "VNB", 0 0, L_000000000400a380;  1 drivers, strength-aware
+L_0000000004009b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a260_0 .net8 "VPB", 0 0, L_0000000004009b30;  1 drivers, strength-aware
+L_0000000004009970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b09900_0 .net8 "VPWR", 0 0, L_0000000004009970;  1 drivers, strength-aware
+v0000000003b08820_0 .net "Y", 0 0, L_0000000004139750;  alias, 1 drivers
+S_0000000003a9a6f0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a99f70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041390c0 .functor NOR 1, L_0000000004128810, L_0000000004128a40, C4<0>, C4<0>;
+L_0000000004139750 .functor BUF 1, L_00000000041390c0, C4<0>, C4<0>, C4<0>;
+v0000000003b09a40_0 .net "A", 0 0, L_0000000004128810;  alias, 1 drivers
+v0000000003b08d20_0 .net "B", 0 0, L_0000000004128a40;  alias, 1 drivers
+L_000000000400a690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b099a0_0 .net8 "VGND", 0 0, L_000000000400a690;  1 drivers, strength-aware
+L_0000000004009820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b081e0_0 .net8 "VNB", 0 0, L_0000000004009820;  1 drivers, strength-aware
+L_000000000400aa10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b09f40_0 .net8 "VPB", 0 0, L_000000000400aa10;  1 drivers, strength-aware
+L_000000000400a3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08c80_0 .net8 "VPWR", 0 0, L_000000000400a3f0;  1 drivers, strength-aware
+v0000000003b08dc0_0 .net "Y", 0 0, L_0000000004139750;  alias, 1 drivers
+v0000000003b09ea0_0 .net "nor0_out_Y", 0 0, L_00000000041390c0;  1 drivers
+S_0000000003a9bd70 .scope module, "_0779_" "sky130_fd_sc_hd__nor2_2" 3 2014, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b090e0_0 .net "A", 0 0, L_00000000041394b0;  alias, 1 drivers
+v0000000003b0a760_0 .net "B", 0 0, L_0000000004139750;  alias, 1 drivers
+L_000000000400a770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b08500_0 .net8 "VGND", 0 0, L_000000000400a770;  1 drivers, strength-aware
+L_0000000004009c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b094a0_0 .net8 "VNB", 0 0, L_0000000004009c10;  1 drivers, strength-aware
+L_00000000040097b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a8a0_0 .net8 "VPB", 0 0, L_00000000040097b0;  1 drivers, strength-aware
+L_000000000400a7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08140_0 .net8 "VPWR", 0 0, L_000000000400a7e0;  1 drivers, strength-aware
+v0000000003b09180_0 .net "Y", 0 0, L_0000000004139980;  alias, 1 drivers
+S_0000000003a9a9f0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003a9bd70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004139b40 .functor NOR 1, L_00000000041394b0, L_0000000004139750, C4<0>, C4<0>;
+L_0000000004139980 .functor BUF 1, L_0000000004139b40, C4<0>, C4<0>, C4<0>;
+v0000000003b0a300_0 .net "A", 0 0, L_00000000041394b0;  alias, 1 drivers
+v0000000003b09b80_0 .net "B", 0 0, L_0000000004139750;  alias, 1 drivers
+L_00000000040092e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a4e0_0 .net8 "VGND", 0 0, L_00000000040092e0;  1 drivers, strength-aware
+L_0000000004009c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b085a0_0 .net8 "VNB", 0 0, L_0000000004009c80;  1 drivers, strength-aware
+L_000000000400a850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b09040_0 .net8 "VPB", 0 0, L_000000000400a850;  1 drivers, strength-aware
+L_0000000004009dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0a3a0_0 .net8 "VPWR", 0 0, L_0000000004009dd0;  1 drivers, strength-aware
+v0000000003b0a580_0 .net "Y", 0 0, L_0000000004139980;  alias, 1 drivers
+v0000000003b0a6c0_0 .net "nor0_out_Y", 0 0, L_0000000004139b40;  1 drivers
+S_0000000003a9bef0 .scope module, "_0780_" "sky130_fd_sc_hd__o32a_2" 3 2019, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003b09400_0 .net "A1", 0 0, L_0000000004128570;  alias, 1 drivers
+v0000000003b08960_0 .net "A2", 0 0, L_000000000412b9f0;  alias, 1 drivers
+v0000000003b09680_0 .net "A3", 0 0, L_0000000004138790;  alias, 1 drivers
+v0000000003b09720_0 .net "B1", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003b097c0_0 .net "B2", 0 0, L_0000000004139980;  alias, 1 drivers
+L_0000000004009eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b09860_0 .net8 "VGND", 0 0, L_0000000004009eb0;  1 drivers, strength-aware
+L_000000000400a460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b08a00_0 .net8 "VNB", 0 0, L_000000000400a460;  1 drivers, strength-aware
+L_0000000004009580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08aa0_0 .net8 "VPB", 0 0, L_0000000004009580;  1 drivers, strength-aware
+L_0000000004009190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08b40_0 .net8 "VPWR", 0 0, L_0000000004009190;  1 drivers, strength-aware
+v0000000003b08be0_0 .net "X", 0 0, L_0000000004139280;  alias, 1 drivers
+S_0000000003a9ab70 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003a9bef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004139130 .functor OR 1, L_000000000412b9f0, L_0000000004128570, L_0000000004138790, C4<0>;
+L_00000000041391a0 .functor OR 1, L_0000000004139980, L_0000000004138870, C4<0>, C4<0>;
+L_0000000004139210 .functor AND 1, L_0000000004139130, L_00000000041391a0, C4<1>, C4<1>;
+L_0000000004139280 .functor BUF 1, L_0000000004139210, C4<0>, C4<0>, C4<0>;
+v0000000003b08460_0 .net "A1", 0 0, L_0000000004128570;  alias, 1 drivers
+v0000000003b09220_0 .net "A2", 0 0, L_000000000412b9f0;  alias, 1 drivers
+v0000000003b08280_0 .net "A3", 0 0, L_0000000004138790;  alias, 1 drivers
+v0000000003b08320_0 .net "B1", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003b083c0_0 .net "B2", 0 0, L_0000000004139980;  alias, 1 drivers
+L_00000000040093c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b09540_0 .net8 "VGND", 0 0, L_00000000040093c0;  1 drivers, strength-aware
+L_0000000004009270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b092c0_0 .net8 "VNB", 0 0, L_0000000004009270;  1 drivers, strength-aware
+L_000000000400a930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b08640_0 .net8 "VPB", 0 0, L_000000000400a930;  1 drivers, strength-aware
+L_0000000004009f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b086e0_0 .net8 "VPWR", 0 0, L_0000000004009f20;  1 drivers, strength-aware
+v0000000003b08780_0 .net "X", 0 0, L_0000000004139280;  alias, 1 drivers
+v0000000003b09360_0 .net "and0_out_X", 0 0, L_0000000004139210;  1 drivers
+v0000000003b088c0_0 .net "or0_out", 0 0, L_0000000004139130;  1 drivers
+v0000000003b095e0_0 .net "or1_out", 0 0, L_00000000041391a0;  1 drivers
+S_0000000003a9ae70 .scope module, "_0781_" "sky130_fd_sc_hd__or2_2" 3 2027, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b0a940_0 .net "A", 0 0, L_0000000004126f20;  alias, 1 drivers
+v0000000003b0c920_0 .net "B", 0 0, L_0000000004128730;  alias, 1 drivers
+L_000000000400aa80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c560_0 .net8 "VGND", 0 0, L_000000000400aa80;  1 drivers, strength-aware
+L_0000000004009f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c240_0 .net8 "VNB", 0 0, L_0000000004009f90;  1 drivers, strength-aware
+L_00000000040094a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b840_0 .net8 "VPB", 0 0, L_00000000040094a0;  1 drivers, strength-aware
+L_0000000004009430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b8e0_0 .net8 "VPWR", 0 0, L_0000000004009430;  1 drivers, strength-aware
+v0000000003b0be80_0 .net "X", 0 0, L_0000000004139520;  alias, 1 drivers
+S_0000000003a9b170 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003a9ae70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004139440 .functor OR 1, L_0000000004128730, L_0000000004126f20, C4<0>, C4<0>;
+L_0000000004139520 .functor BUF 1, L_0000000004139440, C4<0>, C4<0>, C4<0>;
+v0000000003b0c600_0 .net "A", 0 0, L_0000000004126f20;  alias, 1 drivers
+v0000000003b0c420_0 .net "B", 0 0, L_0000000004128730;  alias, 1 drivers
+L_0000000004009660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c4c0_0 .net8 "VGND", 0 0, L_0000000004009660;  1 drivers, strength-aware
+L_0000000004009510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0bf20_0 .net8 "VNB", 0 0, L_0000000004009510;  1 drivers, strength-aware
+L_000000000400a000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d000_0 .net8 "VPB", 0 0, L_000000000400a000;  1 drivers, strength-aware
+L_000000000400aaf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b7a0_0 .net8 "VPWR", 0 0, L_000000000400aaf0;  1 drivers, strength-aware
+v0000000003b0d0a0_0 .net "X", 0 0, L_0000000004139520;  alias, 1 drivers
+v0000000003b0ce20_0 .net "or0_out_X", 0 0, L_0000000004139440;  1 drivers
+S_0000000003a9b470 .scope module, "_0782_" "sky130_fd_sc_hd__o221ai_2" 3 2032, 4 23614 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003b0cd80_0 .net "A1", 0 0, L_0000000004127700;  alias, 1 drivers
+v0000000003b0c380_0 .net "A2", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003b0b660_0 .net "B1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003b0c9c0_0 .net "B2", 0 0, L_0000000004139280;  alias, 1 drivers
+v0000000003b0ca60_0 .net "C1", 0 0, L_0000000004139520;  alias, 1 drivers
+L_0000000004009740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c6a0_0 .net8 "VGND", 0 0, L_0000000004009740;  1 drivers, strength-aware
+L_000000000400a070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b520_0 .net8 "VNB", 0 0, L_000000000400a070;  1 drivers, strength-aware
+L_000000000400a150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b700_0 .net8 "VPB", 0 0, L_000000000400a150;  1 drivers, strength-aware
+L_000000000402b7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c740_0 .net8 "VPWR", 0 0, L_000000000402b7a0;  1 drivers, strength-aware
+v0000000003b0b020_0 .net "Y", 0 0, L_000000000413b740;  alias, 1 drivers
+S_0000000003a9b5f0 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23636, 4 23482 1, S_0000000003a9b470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004139910 .functor OR 1, L_0000000004139280, L_00000000041298b0, C4<0>, C4<0>;
+L_0000000004139bb0 .functor OR 1, L_0000000004128110, L_0000000004127700, C4<0>, C4<0>;
+L_000000000413b190 .functor NAND 1, L_0000000004139bb0, L_0000000004139910, L_0000000004139520, C4<1>;
+L_000000000413b740 .functor BUF 1, L_000000000413b190, C4<0>, C4<0>, C4<0>;
+v0000000003b0bde0_0 .net "A1", 0 0, L_0000000004127700;  alias, 1 drivers
+v0000000003b0bb60_0 .net "A2", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003b0c1a0_0 .net "B1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003b0cec0_0 .net "B2", 0 0, L_0000000004139280;  alias, 1 drivers
+v0000000003b0ba20_0 .net "C1", 0 0, L_0000000004139520;  alias, 1 drivers
+L_000000000402b180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0cba0_0 .net8 "VGND", 0 0, L_000000000402b180;  1 drivers, strength-aware
+L_000000000402b9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0abc0_0 .net8 "VNB", 0 0, L_000000000402b9d0;  1 drivers, strength-aware
+L_000000000402b730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b5c0_0 .net8 "VPB", 0 0, L_000000000402b730;  1 drivers, strength-aware
+L_000000000402c760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0cf60_0 .net8 "VPWR", 0 0, L_000000000402c760;  1 drivers, strength-aware
+v0000000003b0b980_0 .net "Y", 0 0, L_000000000413b740;  alias, 1 drivers
+v0000000003b0c2e0_0 .net "nand0_out_Y", 0 0, L_000000000413b190;  1 drivers
+v0000000003b0bca0_0 .net "or0_out", 0 0, L_0000000004139910;  1 drivers
+v0000000003b0bac0_0 .net "or1_out", 0 0, L_0000000004139bb0;  1 drivers
+S_0000000003b54410 .scope module, "_0783_" "sky130_fd_sc_hd__o211a_2" 3 2040, 4 77704 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003b0cce0_0 .net "A1", 0 0, L_0000000004126740;  alias, 1 drivers
+v0000000003b0ab20_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v0000000003b0ad00_0 .net "B1", 0 0, L_0000000004126e40;  alias, 1 drivers
+v0000000003b0c060_0 .net "C1", 0 0, L_000000000413b740;  alias, 1 drivers
+L_000000000402c300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0ada0_0 .net8 "VGND", 0 0, L_000000000402c300;  1 drivers, strength-aware
+L_000000000402bb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b3e0_0 .net8 "VNB", 0 0, L_000000000402bb20;  1 drivers, strength-aware
+L_000000000402c6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0ae40_0 .net8 "VPB", 0 0, L_000000000402c6f0;  1 drivers, strength-aware
+L_000000000402bb90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0aee0_0 .net8 "VPWR", 0 0, L_000000000402bb90;  1 drivers, strength-aware
+v0000000003b0af80_0 .net "X", 0 0, L_000000000413a940;  1 drivers
+S_0000000003b55790 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_0000000003b54410;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004139f30 .functor OR 1, L_0000000004127e70, L_0000000004126740, C4<0>, C4<0>;
+L_000000000413a6a0 .functor AND 1, L_0000000004139f30, L_0000000004126e40, L_000000000413b740, C4<1>;
+L_000000000413a940 .functor BUF 1, L_000000000413a6a0, C4<0>, C4<0>, C4<0>;
+v0000000003b0ac60_0 .net "A1", 0 0, L_0000000004126740;  alias, 1 drivers
+v0000000003b0c7e0_0 .net "A2", 0 0, L_0000000004127e70;  alias, 1 drivers
+v0000000003b0a9e0_0 .net "B1", 0 0, L_0000000004126e40;  alias, 1 drivers
+v0000000003b0bc00_0 .net "C1", 0 0, L_000000000413b740;  alias, 1 drivers
+L_000000000402c1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c100_0 .net8 "VGND", 0 0, L_000000000402c1b0;  1 drivers, strength-aware
+L_000000000402b6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0c880_0 .net8 "VNB", 0 0, L_000000000402b6c0;  1 drivers, strength-aware
+L_000000000402b5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0cb00_0 .net8 "VPB", 0 0, L_000000000402b5e0;  1 drivers, strength-aware
+L_000000000402b1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0cc40_0 .net8 "VPWR", 0 0, L_000000000402b1f0;  1 drivers, strength-aware
+v0000000003b0bd40_0 .net "X", 0 0, L_000000000413a940;  alias, 1 drivers
+v0000000003b0bfc0_0 .net "and0_out_X", 0 0, L_000000000413a6a0;  1 drivers
+v0000000003b0aa80_0 .net "or0_out", 0 0, L_0000000004139f30;  1 drivers
+S_0000000003b56990 .scope module, "_0784_" "sky130_fd_sc_hd__inv_2" 3 2047, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b0ea40_0 .net "A", 0 0, L_0000000003f946c0;  1 drivers
+L_000000000402cb50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f260_0 .net8 "VGND", 0 0, L_000000000402cb50;  1 drivers, strength-aware
+L_000000000402c680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e860_0 .net8 "VNB", 0 0, L_000000000402c680;  1 drivers, strength-aware
+L_000000000402b810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d820_0 .net8 "VPB", 0 0, L_000000000402b810;  1 drivers, strength-aware
+L_000000000402c610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0dfa0_0 .net8 "VPWR", 0 0, L_000000000402c610;  1 drivers, strength-aware
+v0000000003b0eb80_0 .net "Y", 0 0, L_000000000413b0b0;  alias, 1 drivers
+S_0000000003b58010 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b56990;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413aa20 .functor NOT 1, L_0000000003f946c0, C4<0>, C4<0>, C4<0>;
+L_000000000413b0b0 .functor BUF 1, L_000000000413aa20, C4<0>, C4<0>, C4<0>;
+v0000000003b0b0c0_0 .net "A", 0 0, L_0000000003f946c0;  alias, 1 drivers
+L_000000000402bff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b160_0 .net8 "VGND", 0 0, L_000000000402bff0;  1 drivers, strength-aware
+L_000000000402cbc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b200_0 .net8 "VNB", 0 0, L_000000000402cbc0;  1 drivers, strength-aware
+L_000000000402c4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b2a0_0 .net8 "VPB", 0 0, L_000000000402c4c0;  1 drivers, strength-aware
+L_000000000402b3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0b340_0 .net8 "VPWR", 0 0, L_000000000402b3b0;  1 drivers, strength-aware
+v0000000003b0b480_0 .net "Y", 0 0, L_000000000413b0b0;  alias, 1 drivers
+v0000000003b0d6e0_0 .net "not0_out_Y", 0 0, L_000000000413aa20;  1 drivers
+S_0000000003b57290 .scope module, "_0785_" "sky130_fd_sc_hd__inv_2" 3 2051, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b0d320_0 .net "A", 0 0, L_0000000004136ce0;  alias, 1 drivers
+L_000000000402b420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f440_0 .net8 "VGND", 0 0, L_000000000402b420;  1 drivers, strength-aware
+L_000000000402be30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e4a0_0 .net8 "VNB", 0 0, L_000000000402be30;  1 drivers, strength-aware
+L_000000000402c7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e0e0_0 .net8 "VPB", 0 0, L_000000000402c7d0;  1 drivers, strength-aware
+L_000000000402c3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e540_0 .net8 "VPWR", 0 0, L_000000000402c3e0;  1 drivers, strength-aware
+v0000000003b0ddc0_0 .net "Y", 0 0, L_000000000413ac50;  alias, 1 drivers
+S_0000000003b58790 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b57290;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413b6d0 .functor NOT 1, L_0000000004136ce0, C4<0>, C4<0>, C4<0>;
+L_000000000413ac50 .functor BUF 1, L_000000000413b6d0, C4<0>, C4<0>, C4<0>;
+v0000000003b0db40_0 .net "A", 0 0, L_0000000004136ce0;  alias, 1 drivers
+L_000000000402cc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0dd20_0 .net8 "VGND", 0 0, L_000000000402cc30;  1 drivers, strength-aware
+L_000000000402c530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e5e0_0 .net8 "VNB", 0 0, L_000000000402c530;  1 drivers, strength-aware
+L_000000000402bdc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e360_0 .net8 "VPB", 0 0, L_000000000402bdc0;  1 drivers, strength-aware
+L_000000000402b880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e9a0_0 .net8 "VPWR", 0 0, L_000000000402b880;  1 drivers, strength-aware
+v0000000003b0ec20_0 .net "Y", 0 0, L_000000000413ac50;  alias, 1 drivers
+v0000000003b0ecc0_0 .net "not0_out_Y", 0 0, L_000000000413b6d0;  1 drivers
+S_0000000003b56b10 .scope module, "_0786_" "sky130_fd_sc_hd__nor2_2" 3 2055, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b0d640_0 .net "A", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b0eae0_0 .net "B", 0 0, L_0000000004138090;  alias, 1 drivers
+L_000000000402b8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d500_0 .net8 "VGND", 0 0, L_000000000402b8f0;  1 drivers, strength-aware
+L_000000000402b260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f8a0_0 .net8 "VNB", 0 0, L_000000000402b260;  1 drivers, strength-aware
+L_000000000402ba40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f620_0 .net8 "VPB", 0 0, L_000000000402ba40;  1 drivers, strength-aware
+L_000000000402b960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d140_0 .net8 "VPWR", 0 0, L_000000000402b960;  1 drivers, strength-aware
+v0000000003b0ee00_0 .net "Y", 0 0, L_000000000413b7b0;  alias, 1 drivers
+S_0000000003b53690 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003b56b10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413b040 .functor NOR 1, L_0000000004137ae0, L_0000000004138090, C4<0>, C4<0>;
+L_000000000413b7b0 .functor BUF 1, L_000000000413b040, C4<0>, C4<0>, C4<0>;
+v0000000003b0dbe0_0 .net "A", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b0d5a0_0 .net "B", 0 0, L_0000000004138090;  alias, 1 drivers
+L_000000000402c840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0de60_0 .net8 "VGND", 0 0, L_000000000402c840;  1 drivers, strength-aware
+L_000000000402c370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e220_0 .net8 "VNB", 0 0, L_000000000402c370;  1 drivers, strength-aware
+L_000000000402bc00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0df00_0 .net8 "VPB", 0 0, L_000000000402bc00;  1 drivers, strength-aware
+L_000000000402c8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d3c0_0 .net8 "VPWR", 0 0, L_000000000402c8b0;  1 drivers, strength-aware
+v0000000003b0d460_0 .net "Y", 0 0, L_000000000413b7b0;  alias, 1 drivers
+v0000000003b0e040_0 .net "nor0_out_Y", 0 0, L_000000000413b040;  1 drivers
+S_0000000003b54590 .scope module, "_0787_" "sky130_fd_sc_hd__o32a_2" 3 2060, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003b0f580_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b0e180_0 .net "A2", 0 0, L_0000000004138090;  alias, 1 drivers
+v0000000003b0f120_0 .net "A3", 0 0, L_0000000004136ce0;  alias, 1 drivers
+v0000000003b0f1c0_0 .net "B1", 0 0, L_000000000413ac50;  alias, 1 drivers
+v0000000003b0f6c0_0 .net "B2", 0 0, L_000000000413b7b0;  alias, 1 drivers
+L_000000000402bc70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d960_0 .net8 "VGND", 0 0, L_000000000402bc70;  1 drivers, strength-aware
+L_000000000402c220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e680_0 .net8 "VNB", 0 0, L_000000000402c220;  1 drivers, strength-aware
+L_000000000402bab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e2c0_0 .net8 "VPB", 0 0, L_000000000402bab0;  1 drivers, strength-aware
+L_000000000402b650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0d280_0 .net8 "VPWR", 0 0, L_000000000402b650;  1 drivers, strength-aware
+v0000000003b0da00_0 .net "X", 0 0, L_000000000413b820;  alias, 1 drivers
+S_0000000003b58d90 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003b54590;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_000000000413b2e0 .functor OR 1, L_0000000004138090, L_0000000004137ae0, L_0000000004136ce0, C4<0>;
+L_0000000004139de0 .functor OR 1, L_000000000413b7b0, L_000000000413ac50, C4<0>, C4<0>;
+L_000000000413b120 .functor AND 1, L_000000000413b2e0, L_0000000004139de0, C4<1>, C4<1>;
+L_000000000413b820 .functor BUF 1, L_000000000413b120, C4<0>, C4<0>, C4<0>;
+v0000000003b0f760_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b0ed60_0 .net "A2", 0 0, L_0000000004138090;  alias, 1 drivers
+v0000000003b0eea0_0 .net "A3", 0 0, L_0000000004136ce0;  alias, 1 drivers
+v0000000003b0f4e0_0 .net "B1", 0 0, L_000000000413ac50;  alias, 1 drivers
+v0000000003b0d780_0 .net "B2", 0 0, L_000000000413b7b0;  alias, 1 drivers
+L_000000000402b2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f800_0 .net8 "VGND", 0 0, L_000000000402b2d0;  1 drivers, strength-aware
+L_000000000402bea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f3a0_0 .net8 "VNB", 0 0, L_000000000402bea0;  1 drivers, strength-aware
+L_000000000402bce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f300_0 .net8 "VPB", 0 0, L_000000000402bce0;  1 drivers, strength-aware
+L_000000000402c290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f080_0 .net8 "VPWR", 0 0, L_000000000402c290;  1 drivers, strength-aware
+v0000000003b0d8c0_0 .net "X", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003b0ef40_0 .net "and0_out_X", 0 0, L_000000000413b120;  1 drivers
+v0000000003b0d1e0_0 .net "or0_out", 0 0, L_000000000413b2e0;  1 drivers
+v0000000003b0efe0_0 .net "or1_out", 0 0, L_0000000004139de0;  1 drivers
+S_0000000003b56c90 .scope module, "_0788_" "sky130_fd_sc_hd__o22a_2" 3 2068, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b11d80_0 .net "A1", 0 0, L_0000000003f92b40;  1 drivers
+v0000000003b11a60_0 .net "A2", 0 0, L_0000000003f93680;  1 drivers
+v0000000003b11880_0 .net "B1", 0 0, L_0000000004136ff0;  alias, 1 drivers
+v0000000003b11ec0_0 .net "B2", 0 0, L_0000000004137300;  alias, 1 drivers
+L_000000000402b0a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b11240_0 .net8 "VGND", 0 0, L_000000000402b0a0;  1 drivers, strength-aware
+L_000000000402c920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b10660_0 .net8 "VNB", 0 0, L_000000000402c920;  1 drivers, strength-aware
+L_000000000402b340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b120a0_0 .net8 "VPB", 0 0, L_000000000402b340;  1 drivers, strength-aware
+L_000000000402c990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b11e20_0 .net8 "VPWR", 0 0, L_000000000402c990;  1 drivers, strength-aware
+v0000000003b10b60_0 .net "X", 0 0, L_000000000413b3c0;  1 drivers
+S_0000000003b55f10 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000003b56c90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413b350 .functor OR 1, L_0000000003f93680, L_0000000003f92b40, C4<0>, C4<0>;
+L_000000000413a9b0 .functor OR 1, L_0000000004137300, L_0000000004136ff0, C4<0>, C4<0>;
+L_0000000004139e50 .functor AND 1, L_000000000413b350, L_000000000413a9b0, C4<1>, C4<1>;
+L_000000000413b3c0 .functor BUF 1, L_0000000004139e50, C4<0>, C4<0>, C4<0>;
+v0000000003b0e720_0 .net "A1", 0 0, L_0000000003f92b40;  alias, 1 drivers
+v0000000003b0e400_0 .net "A2", 0 0, L_0000000003f93680;  alias, 1 drivers
+v0000000003b0e7c0_0 .net "B1", 0 0, L_0000000004136ff0;  alias, 1 drivers
+v0000000003b0daa0_0 .net "B2", 0 0, L_0000000004137300;  alias, 1 drivers
+L_000000000402b110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0e900_0 .net8 "VGND", 0 0, L_000000000402b110;  1 drivers, strength-aware
+L_000000000402bd50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0dc80_0 .net8 "VNB", 0 0, L_000000000402bd50;  1 drivers, strength-aware
+L_000000000402c5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b116a0_0 .net8 "VPB", 0 0, L_000000000402c5a0;  1 drivers, strength-aware
+L_000000000402b490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b10340_0 .net8 "VPWR", 0 0, L_000000000402b490;  1 drivers, strength-aware
+v0000000003b107a0_0 .net "X", 0 0, L_000000000413b3c0;  alias, 1 drivers
+v0000000003b11740_0 .net "and0_out_X", 0 0, L_0000000004139e50;  1 drivers
+v0000000003b10ac0_0 .net "or0_out", 0 0, L_000000000413b350;  1 drivers
+v0000000003b10a20_0 .net "or1_out", 0 0, L_000000000413a9b0;  1 drivers
+S_0000000003b54710 .scope module, "_0789_" "sky130_fd_sc_hd__or2_2" 3 2075, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b10de0_0 .net "A", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003b0f940_0 .net "B", 0 0, L_0000000003f937c0;  1 drivers
+L_000000000402bf10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fd00_0 .net8 "VGND", 0 0, L_000000000402bf10;  1 drivers, strength-aware
+L_000000000402bf80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fe40_0 .net8 "VNB", 0 0, L_000000000402bf80;  1 drivers, strength-aware
+L_000000000402c060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b11920_0 .net8 "VPB", 0 0, L_000000000402c060;  1 drivers, strength-aware
+L_000000000402b500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b10e80_0 .net8 "VPWR", 0 0, L_000000000402b500;  1 drivers, strength-aware
+v0000000003b10c00_0 .net "X", 0 0, L_000000000413ab70;  alias, 1 drivers
+S_0000000003b58f10 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b54710;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413a710 .functor OR 1, L_0000000003f937c0, L_000000000413b820, C4<0>, C4<0>;
+L_000000000413ab70 .functor BUF 1, L_000000000413a710, C4<0>, C4<0>, C4<0>;
+v0000000003b12000_0 .net "A", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003b11f60_0 .net "B", 0 0, L_0000000003f937c0;  alias, 1 drivers
+L_000000000402c450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b10700_0 .net8 "VGND", 0 0, L_000000000402c450;  1 drivers, strength-aware
+L_000000000402c0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b119c0_0 .net8 "VNB", 0 0, L_000000000402c0d0;  1 drivers, strength-aware
+L_000000000402b570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fda0_0 .net8 "VPB", 0 0, L_000000000402b570;  1 drivers, strength-aware
+L_000000000402c140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b10520_0 .net8 "VPWR", 0 0, L_000000000402c140;  1 drivers, strength-aware
+v0000000003b10840_0 .net "X", 0 0, L_000000000413ab70;  alias, 1 drivers
+v0000000003b11380_0 .net "or0_out_X", 0 0, L_000000000413a710;  1 drivers
+S_0000000003b53510 .scope module, "_0790_" "sky130_fd_sc_hd__a21boi_2" 3 2080, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b0fbc0_0 .net "A1", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003b10d40_0 .net "A2", 0 0, L_0000000003f92aa0;  1 drivers
+v0000000003b100c0_0 .net "B1_N", 0 0, L_000000000413ab70;  alias, 1 drivers
+L_000000000402ca00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b102a0_0 .net8 "VGND", 0 0, L_000000000402ca00;  1 drivers, strength-aware
+L_000000000402ca70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fc60_0 .net8 "VNB", 0 0, L_000000000402ca70;  1 drivers, strength-aware
+L_000000000402cae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fee0_0 .net8 "VPB", 0 0, L_000000000402cae0;  1 drivers, strength-aware
+L_000000000402d090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b114c0_0 .net8 "VPWR", 0 0, L_000000000402d090;  1 drivers, strength-aware
+v0000000003b0ff80_0 .net "Y", 0 0, L_000000000413a7f0;  alias, 1 drivers
+S_0000000003b56e10 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b53510;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413ab00 .functor NOT 1, L_000000000413ab70, C4<0>, C4<0>, C4<0>;
+L_000000000413a1d0 .functor AND 1, L_000000000413b820, L_0000000003f92aa0, C4<1>, C4<1>;
+L_000000000413ada0 .functor NOR 1, L_000000000413ab00, L_000000000413a1d0, C4<0>, C4<0>;
+L_000000000413a7f0 .functor BUF 1, L_000000000413ada0, C4<0>, C4<0>, C4<0>;
+v0000000003b105c0_0 .net "A1", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003b11ba0_0 .net "A2", 0 0, L_0000000003f92aa0;  alias, 1 drivers
+v0000000003b10f20_0 .net "B1_N", 0 0, L_000000000413ab70;  alias, 1 drivers
+L_000000000402db10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b10ca0_0 .net8 "VGND", 0 0, L_000000000402db10;  1 drivers, strength-aware
+L_000000000402d560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b108e0_0 .net8 "VNB", 0 0, L_000000000402d560;  1 drivers, strength-aware
+L_000000000402e050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0f9e0_0 .net8 "VPB", 0 0, L_000000000402e050;  1 drivers, strength-aware
+L_000000000402d6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b0fa80_0 .net8 "VPWR", 0 0, L_000000000402d6b0;  1 drivers, strength-aware
+v0000000003b117e0_0 .net "Y", 0 0, L_000000000413a7f0;  alias, 1 drivers
+v0000000003b0fb20_0 .net "and0_out", 0 0, L_000000000413a1d0;  1 drivers
+v0000000003b10980_0 .net "b", 0 0, L_000000000413ab00;  1 drivers
+v0000000003b11560_0 .net "nor0_out_Y", 0 0, L_000000000413ada0;  1 drivers
+S_0000000003b57410 .scope module, "_0791_" "sky130_fd_sc_hd__nor2_2" 3 2086, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b11420_0 .net "A", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003b11600_0 .net "B", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_000000000402d870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b10020_0 .net8 "VGND", 0 0, L_000000000402d870;  1 drivers, strength-aware
+L_000000000402e360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b11ce0_0 .net8 "VNB", 0 0, L_000000000402e360;  1 drivers, strength-aware
+L_000000000402e670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b10160_0 .net8 "VPB", 0 0, L_000000000402e670;  1 drivers, strength-aware
+L_000000000402cca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b10200_0 .net8 "VPWR", 0 0, L_000000000402cca0;  1 drivers, strength-aware
+v0000000003b10480_0 .net "Y", 0 0, L_000000000413a240;  alias, 1 drivers
+S_0000000003b53090 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003b57410;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413b200 .functor NOR 1, L_00000000041369d0, L_00000000041359a0, C4<0>, C4<0>;
+L_000000000413a240 .functor BUF 1, L_000000000413b200, C4<0>, C4<0>, C4<0>;
+v0000000003b11b00_0 .net "A", 0 0, L_00000000041369d0;  alias, 1 drivers
+v0000000003b10fc0_0 .net "B", 0 0, L_00000000041359a0;  alias, 1 drivers
+L_000000000402cfb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b112e0_0 .net8 "VGND", 0 0, L_000000000402cfb0;  1 drivers, strength-aware
+L_000000000402e6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b11100_0 .net8 "VNB", 0 0, L_000000000402e6e0;  1 drivers, strength-aware
+L_000000000402d170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b11060_0 .net8 "VPB", 0 0, L_000000000402d170;  1 drivers, strength-aware
+L_000000000402d3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b111a0_0 .net8 "VPWR", 0 0, L_000000000402d3a0;  1 drivers, strength-aware
+v0000000003b11c40_0 .net "Y", 0 0, L_000000000413a240;  alias, 1 drivers
+v0000000003b103e0_0 .net "nor0_out_Y", 0 0, L_000000000413b200;  1 drivers
+S_0000000003b56f90 .scope module, "_0792_" "sky130_fd_sc_hd__and2_2" 3 2091, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b12f00_0 .net "A", 0 0, L_00000000041365e0;  alias, 1 drivers
+v0000000003b12140_0 .net "B", 0 0, L_000000000413b7b0;  alias, 1 drivers
+L_000000000402d1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b14120_0 .net8 "VGND", 0 0, L_000000000402d1e0;  1 drivers, strength-aware
+L_000000000402da30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b139a0_0 .net8 "VNB", 0 0, L_000000000402da30;  1 drivers, strength-aware
+L_000000000402de20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13a40_0 .net8 "VPB", 0 0, L_000000000402de20;  1 drivers, strength-aware
+L_000000000402df70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13b80_0 .net8 "VPWR", 0 0, L_000000000402df70;  1 drivers, strength-aware
+v0000000003b13040_0 .net "X", 0 0, L_000000000413ae80;  alias, 1 drivers
+S_0000000003b56510 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003b56f90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413aa90 .functor AND 1, L_00000000041365e0, L_000000000413b7b0, C4<1>, C4<1>;
+L_000000000413ae80 .functor BUF 1, L_000000000413aa90, C4<0>, C4<0>, C4<0>;
+v0000000003b132c0_0 .net "A", 0 0, L_00000000041365e0;  alias, 1 drivers
+v0000000003b13e00_0 .net "B", 0 0, L_000000000413b7b0;  alias, 1 drivers
+L_000000000402cdf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b13c20_0 .net8 "VGND", 0 0, L_000000000402cdf0;  1 drivers, strength-aware
+L_000000000402d480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12a00_0 .net8 "VNB", 0 0, L_000000000402d480;  1 drivers, strength-aware
+L_000000000402cf40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13720_0 .net8 "VPB", 0 0, L_000000000402cf40;  1 drivers, strength-aware
+L_000000000402d720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b148a0_0 .net8 "VPWR", 0 0, L_000000000402d720;  1 drivers, strength-aware
+v0000000003b12fa0_0 .net "X", 0 0, L_000000000413ae80;  alias, 1 drivers
+v0000000003b14800_0 .net "and0_out_X", 0 0, L_000000000413aa90;  1 drivers
+S_0000000003b53210 .scope module, "_0793_" "sky130_fd_sc_hd__o21ai_2" 3 2096, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b130e0_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b12c80_0 .net "A2", 0 0, L_0000000004136d50;  alias, 1 drivers
+v0000000003b12780_0 .net "B1", 0 0, L_0000000004135000;  alias, 1 drivers
+L_000000000402d5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b13ea0_0 .net8 "VGND", 0 0, L_000000000402d5d0;  1 drivers, strength-aware
+L_000000000402d9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12be0_0 .net8 "VNB", 0 0, L_000000000402d9c0;  1 drivers, strength-aware
+L_000000000402d640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b123c0_0 .net8 "VPB", 0 0, L_000000000402d640;  1 drivers, strength-aware
+L_000000000402d2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13540_0 .net8 "VPWR", 0 0, L_000000000402d2c0;  1 drivers, strength-aware
+v0000000003b13cc0_0 .net "Y", 0 0, L_000000000413a320;  alias, 1 drivers
+S_0000000003b54d10 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b53210;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413a2b0 .functor OR 1, L_0000000004136d50, L_0000000004137ae0, C4<0>, C4<0>;
+L_000000000413abe0 .functor NAND 1, L_0000000004135000, L_000000000413a2b0, C4<1>, C4<1>;
+L_000000000413a320 .functor BUF 1, L_000000000413abe0, C4<0>, C4<0>, C4<0>;
+v0000000003b13180_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b13400_0 .net "A2", 0 0, L_0000000004136d50;  alias, 1 drivers
+v0000000003b13360_0 .net "B1", 0 0, L_0000000004135000;  alias, 1 drivers
+L_000000000402d330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b137c0_0 .net8 "VGND", 0 0, L_000000000402d330;  1 drivers, strength-aware
+L_000000000402de90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b125a0_0 .net8 "VNB", 0 0, L_000000000402de90;  1 drivers, strength-aware
+L_000000000402dbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13ae0_0 .net8 "VPB", 0 0, L_000000000402dbf0;  1 drivers, strength-aware
+L_000000000402e280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b121e0_0 .net8 "VPWR", 0 0, L_000000000402e280;  1 drivers, strength-aware
+v0000000003b13f40_0 .net "Y", 0 0, L_000000000413a320;  alias, 1 drivers
+v0000000003b13d60_0 .net "nand0_out_Y", 0 0, L_000000000413abe0;  1 drivers
+v0000000003b12b40_0 .net "or0_out", 0 0, L_000000000413a2b0;  1 drivers
+S_0000000003b55190 .scope module, "_0794_" "sky130_fd_sc_hd__a21bo_2" 3 2102, 4 91108 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b13220_0 .net "A1", 0 0, L_0000000004127d90;  alias, 1 drivers
+v0000000003b141c0_0 .net "A2", 0 0, L_000000000413ae80;  alias, 1 drivers
+v0000000003b14300_0 .net "B1_N", 0 0, L_000000000413a320;  alias, 1 drivers
+L_000000000402e0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12500_0 .net8 "VGND", 0 0, L_000000000402e0c0;  1 drivers, strength-aware
+L_000000000402df00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b13900_0 .net8 "VNB", 0 0, L_000000000402df00;  1 drivers, strength-aware
+L_000000000402e750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b12820_0 .net8 "VPB", 0 0, L_000000000402e750;  1 drivers, strength-aware
+L_000000000402e7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13680_0 .net8 "VPWR", 0 0, L_000000000402e7c0;  1 drivers, strength-aware
+v0000000003b14440_0 .net "X", 0 0, L_000000000413acc0;  alias, 1 drivers
+S_0000000003b54290 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91126, 4 91435 1, S_0000000003b55190;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413a8d0 .functor NAND 1, L_000000000413ae80, L_0000000004127d90, C4<1>, C4<1>;
+L_000000000413a550 .functor NAND 1, L_000000000413a320, L_000000000413a8d0, C4<1>, C4<1>;
+L_000000000413acc0 .functor BUF 1, L_000000000413a550, C4<0>, C4<0>, C4<0>;
+v0000000003b143a0_0 .net "A1", 0 0, L_0000000004127d90;  alias, 1 drivers
+v0000000003b146c0_0 .net "A2", 0 0, L_000000000413ae80;  alias, 1 drivers
+v0000000003b14260_0 .net "B1_N", 0 0, L_000000000413a320;  alias, 1 drivers
+L_000000000402e130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12280_0 .net8 "VGND", 0 0, L_000000000402e130;  1 drivers, strength-aware
+L_000000000402dfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b13fe0_0 .net8 "VNB", 0 0, L_000000000402dfe0;  1 drivers, strength-aware
+L_000000000402e3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b14080_0 .net8 "VPB", 0 0, L_000000000402e3d0;  1 drivers, strength-aware
+L_000000000402ddb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b13860_0 .net8 "VPWR", 0 0, L_000000000402ddb0;  1 drivers, strength-aware
+v0000000003b135e0_0 .net "X", 0 0, L_000000000413acc0;  alias, 1 drivers
+v0000000003b14760_0 .net "nand0_out", 0 0, L_000000000413a8d0;  1 drivers
+v0000000003b134a0_0 .net "nand1_out_X", 0 0, L_000000000413a550;  1 drivers
+S_0000000003b57a10 .scope module, "_0795_" "sky130_fd_sc_hd__inv_2" 3 2108, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b128c0_0 .net "A", 0 0, L_000000000413acc0;  alias, 1 drivers
+L_000000000402d790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12960_0 .net8 "VGND", 0 0, L_000000000402d790;  1 drivers, strength-aware
+L_000000000402d250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b12aa0_0 .net8 "VNB", 0 0, L_000000000402d250;  1 drivers, strength-aware
+L_000000000402e520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b12d20_0 .net8 "VPB", 0 0, L_000000000402e520;  1 drivers, strength-aware
+L_000000000402d020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b12dc0_0 .net8 "VPWR", 0 0, L_000000000402d020;  1 drivers, strength-aware
+v0000000003b12e60_0 .net "Y", 0 0, L_000000000413ad30;  alias, 1 drivers
+S_0000000003b58310 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b57a10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413a630 .functor NOT 1, L_000000000413acc0, C4<0>, C4<0>, C4<0>;
+L_000000000413ad30 .functor BUF 1, L_000000000413a630, C4<0>, C4<0>, C4<0>;
+v0000000003b144e0_0 .net "A", 0 0, L_000000000413acc0;  alias, 1 drivers
+L_000000000402e1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b126e0_0 .net8 "VGND", 0 0, L_000000000402e1a0;  1 drivers, strength-aware
+L_000000000402e600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b14580_0 .net8 "VNB", 0 0, L_000000000402e600;  1 drivers, strength-aware
+L_000000000402d800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b14620_0 .net8 "VPB", 0 0, L_000000000402d800;  1 drivers, strength-aware
+L_000000000402e590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b12460_0 .net8 "VPWR", 0 0, L_000000000402e590;  1 drivers, strength-aware
+v0000000003b12320_0 .net "Y", 0 0, L_000000000413ad30;  alias, 1 drivers
+v0000000003b12640_0 .net "not0_out_Y", 0 0, L_000000000413a630;  1 drivers
+S_0000000003b58c10 .scope module, "_0796_" "sky130_fd_sc_hd__nor2_2" 3 2112, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b16f60_0 .net "A", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003b15660_0 .net "B", 0 0, L_000000000413a240;  alias, 1 drivers
+L_000000000402e210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b170a0_0 .net8 "VGND", 0 0, L_000000000402e210;  1 drivers, strength-aware
+L_000000000402e2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b16880_0 .net8 "VNB", 0 0, L_000000000402e2f0;  1 drivers, strength-aware
+L_000000000402e4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b14940_0 .net8 "VPB", 0 0, L_000000000402e4b0;  1 drivers, strength-aware
+L_000000000402e440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b161a0_0 .net8 "VPWR", 0 0, L_000000000402e440;  1 drivers, strength-aware
+v0000000003b16420_0 .net "Y", 0 0, L_000000000413b890;  alias, 1 drivers
+S_0000000003b57710 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003b58c10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413a5c0 .functor NOR 1, L_0000000004137370, L_000000000413a240, C4<0>, C4<0>;
+L_000000000413b890 .functor BUF 1, L_000000000413a5c0, C4<0>, C4<0>, C4<0>;
+v0000000003b14da0_0 .net "A", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003b155c0_0 .net "B", 0 0, L_000000000413a240;  alias, 1 drivers
+L_000000000402d8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b15a20_0 .net8 "VGND", 0 0, L_000000000402d8e0;  1 drivers, strength-aware
+L_000000000402d950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b158e0_0 .net8 "VNB", 0 0, L_000000000402d950;  1 drivers, strength-aware
+L_000000000402daa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b14bc0_0 .net8 "VPB", 0 0, L_000000000402daa0;  1 drivers, strength-aware
+L_000000000402e830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b16d80_0 .net8 "VPWR", 0 0, L_000000000402e830;  1 drivers, strength-aware
+v0000000003b14d00_0 .net "Y", 0 0, L_000000000413b890;  alias, 1 drivers
+v0000000003b16ce0_0 .net "nor0_out_Y", 0 0, L_000000000413a5c0;  1 drivers
+S_0000000003b53e10 .scope module, "_0797_" "sky130_fd_sc_hd__o32a_2" 3 2117, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003b14f80_0 .net "A1", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003b16560_0 .net "A2", 0 0, L_000000000413a240;  alias, 1 drivers
+v0000000003b15f20_0 .net "A3", 0 0, L_000000000413ad30;  alias, 1 drivers
+v0000000003b15020_0 .net "B1", 0 0, L_000000000413b890;  alias, 1 drivers
+v0000000003b16060_0 .net "B2", 0 0, L_000000000413acc0;  alias, 1 drivers
+L_000000000402cd10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b16600_0 .net8 "VGND", 0 0, L_000000000402cd10;  1 drivers, strength-aware
+L_000000000402d410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b14a80_0 .net8 "VNB", 0 0, L_000000000402d410;  1 drivers, strength-aware
+L_000000000402db80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b16740_0 .net8 "VPB", 0 0, L_000000000402db80;  1 drivers, strength-aware
+L_000000000402cd80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b166a0_0 .net8 "VPWR", 0 0, L_000000000402cd80;  1 drivers, strength-aware
+v0000000003b15340_0 .net "X", 0 0, L_0000000004139ec0;  alias, 1 drivers
+S_0000000003b55310 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003b53e10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004139d00 .functor OR 1, L_000000000413a240, L_0000000004137370, L_000000000413ad30, C4<0>;
+L_0000000004139d70 .functor OR 1, L_000000000413acc0, L_000000000413b890, C4<0>, C4<0>;
+L_000000000413ae10 .functor AND 1, L_0000000004139d00, L_0000000004139d70, C4<1>, C4<1>;
+L_0000000004139ec0 .functor BUF 1, L_000000000413ae10, C4<0>, C4<0>, C4<0>;
+v0000000003b16e20_0 .net "A1", 0 0, L_0000000004137370;  alias, 1 drivers
+v0000000003b162e0_0 .net "A2", 0 0, L_000000000413a240;  alias, 1 drivers
+v0000000003b149e0_0 .net "A3", 0 0, L_000000000413ad30;  alias, 1 drivers
+v0000000003b14e40_0 .net "B1", 0 0, L_000000000413b890;  alias, 1 drivers
+v0000000003b16240_0 .net "B2", 0 0, L_000000000413acc0;  alias, 1 drivers
+L_000000000402ce60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b15700_0 .net8 "VGND", 0 0, L_000000000402ce60;  1 drivers, strength-aware
+L_000000000402ced0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b16380_0 .net8 "VNB", 0 0, L_000000000402ced0;  1 drivers, strength-aware
+L_000000000402d4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b157a0_0 .net8 "VPB", 0 0, L_000000000402d4f0;  1 drivers, strength-aware
+L_000000000402d100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b15e80_0 .net8 "VPWR", 0 0, L_000000000402d100;  1 drivers, strength-aware
+v0000000003b14c60_0 .net "X", 0 0, L_0000000004139ec0;  alias, 1 drivers
+v0000000003b164c0_0 .net "and0_out_X", 0 0, L_000000000413ae10;  1 drivers
+v0000000003b14ee0_0 .net "or0_out", 0 0, L_0000000004139d00;  1 drivers
+v0000000003b15160_0 .net "or1_out", 0 0, L_0000000004139d70;  1 drivers
+S_0000000003b54b90 .scope module, "_0798_" "sky130_fd_sc_hd__or2_2" 3 2125, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b16b00_0 .net "A", 0 0, L_000000000413ab70;  alias, 1 drivers
+v0000000003b14b20_0 .net "B", 0 0, L_0000000004139ec0;  alias, 1 drivers
+L_000000000402dc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b15200_0 .net8 "VGND", 0 0, L_000000000402dc60;  1 drivers, strength-aware
+L_000000000402dcd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b16ba0_0 .net8 "VNB", 0 0, L_000000000402dcd0;  1 drivers, strength-aware
+L_000000000402dd40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b16c40_0 .net8 "VPB", 0 0, L_000000000402dd40;  1 drivers, strength-aware
+L_000000000402f550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b16ec0_0 .net8 "VPWR", 0 0, L_000000000402f550;  1 drivers, strength-aware
+v0000000003b17000_0 .net "X", 0 0, L_000000000413a860;  alias, 1 drivers
+S_0000000003b57590 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b54b90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413a780 .functor OR 1, L_0000000004139ec0, L_000000000413ab70, C4<0>, C4<0>;
+L_000000000413a860 .functor BUF 1, L_000000000413a780, C4<0>, C4<0>, C4<0>;
+v0000000003b150c0_0 .net "A", 0 0, L_000000000413ab70;  alias, 1 drivers
+v0000000003b167e0_0 .net "B", 0 0, L_0000000004139ec0;  alias, 1 drivers
+L_000000000402e9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b153e0_0 .net8 "VGND", 0 0, L_000000000402e9f0;  1 drivers, strength-aware
+L_000000000402eec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b16920_0 .net8 "VNB", 0 0, L_000000000402eec0;  1 drivers, strength-aware
+L_000000000402ea60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b15840_0 .net8 "VPB", 0 0, L_000000000402ea60;  1 drivers, strength-aware
+L_000000000402f160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b15520_0 .net8 "VPWR", 0 0, L_000000000402f160;  1 drivers, strength-aware
+v0000000003b169c0_0 .net "X", 0 0, L_000000000413a860;  alias, 1 drivers
+v0000000003b16a60_0 .net "or0_out_X", 0 0, L_000000000413a780;  1 drivers
+S_0000000003b58610 .scope module, "_0799_" "sky130_fd_sc_hd__a21boi_2" 3 2130, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b18cc0_0 .net "A1", 0 0, L_000000000413ab70;  alias, 1 drivers
+v0000000003b191c0_0 .net "A2", 0 0, L_0000000004139ec0;  alias, 1 drivers
+v0000000003b18360_0 .net "B1_N", 0 0, L_000000000413a860;  alias, 1 drivers
+L_0000000004030430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b189a0_0 .net8 "VGND", 0 0, L_0000000004030430;  1 drivers, strength-aware
+L_000000000402f7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b18f40_0 .net8 "VNB", 0 0, L_000000000402f7f0;  1 drivers, strength-aware
+L_000000000402f6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b18b80_0 .net8 "VPB", 0 0, L_000000000402f6a0;  1 drivers, strength-aware
+L_000000000402e8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17140_0 .net8 "VPWR", 0 0, L_000000000402e8a0;  1 drivers, strength-aware
+v0000000003b17dc0_0 .net "Y", 0 0, L_000000000413af60;  alias, 1 drivers
+S_0000000003b55910 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b58610;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413b660 .functor NOT 1, L_000000000413a860, C4<0>, C4<0>, C4<0>;
+L_0000000004139fa0 .functor AND 1, L_000000000413ab70, L_0000000004139ec0, C4<1>, C4<1>;
+L_000000000413aef0 .functor NOR 1, L_000000000413b660, L_0000000004139fa0, C4<0>, C4<0>;
+L_000000000413af60 .functor BUF 1, L_000000000413aef0, C4<0>, C4<0>, C4<0>;
+v0000000003b152a0_0 .net "A1", 0 0, L_000000000413ab70;  alias, 1 drivers
+v0000000003b15480_0 .net "A2", 0 0, L_0000000004139ec0;  alias, 1 drivers
+v0000000003b15980_0 .net "B1_N", 0 0, L_000000000413a860;  alias, 1 drivers
+L_0000000004030040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b15ac0_0 .net8 "VGND", 0 0, L_0000000004030040;  1 drivers, strength-aware
+L_000000000402e910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b15b60_0 .net8 "VNB", 0 0, L_000000000402e910;  1 drivers, strength-aware
+L_000000000402e980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b15c00_0 .net8 "VPB", 0 0, L_000000000402e980;  1 drivers, strength-aware
+L_000000000402fcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b15ca0_0 .net8 "VPWR", 0 0, L_000000000402fcc0;  1 drivers, strength-aware
+v0000000003b15d40_0 .net "Y", 0 0, L_000000000413af60;  alias, 1 drivers
+v0000000003b15de0_0 .net "and0_out", 0 0, L_0000000004139fa0;  1 drivers
+v0000000003b15fc0_0 .net "b", 0 0, L_000000000413b660;  1 drivers
+v0000000003b16100_0 .net "nor0_out_Y", 0 0, L_000000000413aef0;  1 drivers
+S_0000000003b53390 .scope module, "_0800_" "sky130_fd_sc_hd__inv_2" 3 2136, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b19300_0 .net "A", 0 0, L_00000000041374c0;  alias, 1 drivers
+L_000000000402f1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b193a0_0 .net8 "VGND", 0 0, L_000000000402f1d0;  1 drivers, strength-aware
+L_000000000402fbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b17820_0 .net8 "VNB", 0 0, L_000000000402fbe0;  1 drivers, strength-aware
+L_0000000004030190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b198a0_0 .net8 "VPB", 0 0, L_0000000004030190;  1 drivers, strength-aware
+L_000000000402ead0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17280_0 .net8 "VPWR", 0 0, L_000000000402ead0;  1 drivers, strength-aware
+v0000000003b18fe0_0 .net "Y", 0 0, L_000000000413a390;  alias, 1 drivers
+S_0000000003b53810 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b53390;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413a010 .functor NOT 1, L_00000000041374c0, C4<0>, C4<0>, C4<0>;
+L_000000000413a390 .functor BUF 1, L_000000000413a010, C4<0>, C4<0>, C4<0>;
+v0000000003b17be0_0 .net "A", 0 0, L_00000000041374c0;  alias, 1 drivers
+L_000000000402fb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b173c0_0 .net8 "VGND", 0 0, L_000000000402fb70;  1 drivers, strength-aware
+L_000000000402f240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b18d60_0 .net8 "VNB", 0 0, L_000000000402f240;  1 drivers, strength-aware
+L_00000000040300b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17c80_0 .net8 "VPB", 0 0, L_00000000040300b0;  1 drivers, strength-aware
+L_000000000402f010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19440_0 .net8 "VPWR", 0 0, L_000000000402f010;  1 drivers, strength-aware
+v0000000003b17f00_0 .net "Y", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003b19260_0 .net "not0_out_Y", 0 0, L_000000000413a010;  1 drivers
+S_0000000003b57110 .scope module, "_0801_" "sky130_fd_sc_hd__nor2_2" 3 2140, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b184a0_0 .net "A", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b19120_0 .net "B", 0 0, L_0000000004135ee0;  alias, 1 drivers
+L_000000000402ec90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b18ae0_0 .net8 "VGND", 0 0, L_000000000402ec90;  1 drivers, strength-aware
+L_000000000402eb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b17d20_0 .net8 "VNB", 0 0, L_000000000402eb40;  1 drivers, strength-aware
+L_000000000402f860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b18ea0_0 .net8 "VPB", 0 0, L_000000000402f860;  1 drivers, strength-aware
+L_000000000402ebb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b18e00_0 .net8 "VPWR", 0 0, L_000000000402ebb0;  1 drivers, strength-aware
+v0000000003b176e0_0 .net "Y", 0 0, L_000000000413b4a0;  alias, 1 drivers
+S_0000000003b58910 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003b57110;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413b430 .functor NOR 1, L_0000000004137290, L_0000000004135ee0, C4<0>, C4<0>;
+L_000000000413b4a0 .functor BUF 1, L_000000000413b430, C4<0>, C4<0>, C4<0>;
+v0000000003b194e0_0 .net "A", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b18220_0 .net "B", 0 0, L_0000000004135ee0;  alias, 1 drivers
+L_000000000402ee50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b18a40_0 .net8 "VGND", 0 0, L_000000000402ee50;  1 drivers, strength-aware
+L_000000000402f710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19580_0 .net8 "VNB", 0 0, L_000000000402f710;  1 drivers, strength-aware
+L_000000000402ec20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19080_0 .net8 "VPB", 0 0, L_000000000402ec20;  1 drivers, strength-aware
+L_0000000004030270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b178c0_0 .net8 "VPWR", 0 0, L_0000000004030270;  1 drivers, strength-aware
+v0000000003b18c20_0 .net "Y", 0 0, L_000000000413b4a0;  alias, 1 drivers
+v0000000003b171e0_0 .net "nor0_out_Y", 0 0, L_000000000413b430;  1 drivers
+S_0000000003b57b90 .scope module, "_0802_" "sky130_fd_sc_hd__o32a_2" 3 2145, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003b17fa0_0 .net "A1", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b18680_0 .net "A2", 0 0, L_0000000004135ee0;  alias, 1 drivers
+v0000000003b17780_0 .net "A3", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003b180e0_0 .net "B1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003b187c0_0 .net "B2", 0 0, L_000000000413b4a0;  alias, 1 drivers
+L_000000000402f2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b17960_0 .net8 "VGND", 0 0, L_000000000402f2b0;  1 drivers, strength-aware
+L_000000000402f780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b175a0_0 .net8 "VNB", 0 0, L_000000000402f780;  1 drivers, strength-aware
+L_000000000402ffd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17a00_0 .net8 "VPB", 0 0, L_000000000402ffd0;  1 drivers, strength-aware
+L_000000000402f5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17aa0_0 .net8 "VPWR", 0 0, L_000000000402f5c0;  1 drivers, strength-aware
+v0000000003b17b40_0 .net "X", 0 0, L_000000000413b510;  alias, 1 drivers
+S_0000000003b57890 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003b57b90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_000000000413afd0 .functor OR 1, L_0000000004135ee0, L_0000000004137290, L_00000000041374c0, C4<0>;
+L_000000000413a080 .functor OR 1, L_000000000413b4a0, L_000000000413a390, C4<0>, C4<0>;
+L_000000000413b270 .functor AND 1, L_000000000413afd0, L_000000000413a080, C4<1>, C4<1>;
+L_000000000413b510 .functor BUF 1, L_000000000413b270, C4<0>, C4<0>, C4<0>;
+v0000000003b18540_0 .net "A1", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b17320_0 .net "A2", 0 0, L_0000000004135ee0;  alias, 1 drivers
+v0000000003b19620_0 .net "A3", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003b17640_0 .net "B1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003b17460_0 .net "B2", 0 0, L_000000000413b4a0;  alias, 1 drivers
+L_0000000004030200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b196c0_0 .net8 "VGND", 0 0, L_0000000004030200;  1 drivers, strength-aware
+L_000000000402f8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19760_0 .net8 "VNB", 0 0, L_000000000402f8d0;  1 drivers, strength-aware
+L_000000000402fd30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b17e60_0 .net8 "VPB", 0 0, L_000000000402fd30;  1 drivers, strength-aware
+L_000000000402ed00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19800_0 .net8 "VPWR", 0 0, L_000000000402ed00;  1 drivers, strength-aware
+v0000000003b18900_0 .net "X", 0 0, L_000000000413b510;  alias, 1 drivers
+v0000000003b185e0_0 .net "and0_out_X", 0 0, L_000000000413b270;  1 drivers
+v0000000003b17500_0 .net "or0_out", 0 0, L_000000000413afd0;  1 drivers
+v0000000003b18400_0 .net "or1_out", 0 0, L_000000000413a080;  1 drivers
+S_0000000003b58a90 .scope module, "_0803_" "sky130_fd_sc_hd__or2_2" 3 2153, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b1b1a0_0 .net "A", 0 0, L_000000000413a860;  alias, 1 drivers
+v0000000003b1b240_0 .net "B", 0 0, L_000000000413b510;  alias, 1 drivers
+L_000000000402ed70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a840_0 .net8 "VGND", 0 0, L_000000000402ed70;  1 drivers, strength-aware
+L_000000000402fc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a7a0_0 .net8 "VNB", 0 0, L_000000000402fc50;  1 drivers, strength-aware
+L_000000000402fda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ae80_0 .net8 "VPB", 0 0, L_000000000402fda0;  1 drivers, strength-aware
+L_000000000402ede0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19c60_0 .net8 "VPWR", 0 0, L_000000000402ede0;  1 drivers, strength-aware
+v0000000003b1b380_0 .net "X", 0 0, L_000000000413b580;  alias, 1 drivers
+S_0000000003b53990 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b58a90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413a0f0 .functor OR 1, L_000000000413b510, L_000000000413a860, C4<0>, C4<0>;
+L_000000000413b580 .functor BUF 1, L_000000000413a0f0, C4<0>, C4<0>, C4<0>;
+v0000000003b18720_0 .net "A", 0 0, L_000000000413a860;  alias, 1 drivers
+v0000000003b18040_0 .net "B", 0 0, L_000000000413b510;  alias, 1 drivers
+L_000000000402fe10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b18180_0 .net8 "VGND", 0 0, L_000000000402fe10;  1 drivers, strength-aware
+L_000000000402fa20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b182c0_0 .net8 "VNB", 0 0, L_000000000402fa20;  1 drivers, strength-aware
+L_00000000040302e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b18860_0 .net8 "VPB", 0 0, L_00000000040302e0;  1 drivers, strength-aware
+L_0000000004030350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1bd80_0 .net8 "VPWR", 0 0, L_0000000004030350;  1 drivers, strength-aware
+v0000000003b1b2e0_0 .net "X", 0 0, L_000000000413b580;  alias, 1 drivers
+v0000000003b1a660_0 .net "or0_out_X", 0 0, L_000000000413a0f0;  1 drivers
+S_0000000003b56390 .scope module, "_0804_" "sky130_fd_sc_hd__a21boi_2" 3 2158, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b1ac00_0 .net "A1", 0 0, L_000000000413a860;  alias, 1 drivers
+v0000000003b19d00_0 .net "A2", 0 0, L_000000000413b510;  alias, 1 drivers
+v0000000003b1b600_0 .net "B1_N", 0 0, L_000000000413b580;  alias, 1 drivers
+L_000000000402fa90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1afc0_0 .net8 "VGND", 0 0, L_000000000402fa90;  1 drivers, strength-aware
+L_000000000402fe80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19da0_0 .net8 "VNB", 0 0, L_000000000402fe80;  1 drivers, strength-aware
+L_000000000402f940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b6a0_0 .net8 "VPB", 0 0, L_000000000402f940;  1 drivers, strength-aware
+L_000000000402f9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19940_0 .net8 "VPWR", 0 0, L_000000000402f9b0;  1 drivers, strength-aware
+v0000000003b1b740_0 .net "Y", 0 0, L_000000000413a470;  alias, 1 drivers
+S_0000000003b56210 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b56390;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413a400 .functor NOT 1, L_000000000413b580, C4<0>, C4<0>, C4<0>;
+L_000000000413b5f0 .functor AND 1, L_000000000413a860, L_000000000413b510, C4<1>, C4<1>;
+L_000000000413a160 .functor NOR 1, L_000000000413a400, L_000000000413b5f0, C4<0>, C4<0>;
+L_000000000413a470 .functor BUF 1, L_000000000413a160, C4<0>, C4<0>, C4<0>;
+v0000000003b1b420_0 .net "A1", 0 0, L_000000000413a860;  alias, 1 drivers
+v0000000003b1af20_0 .net "A2", 0 0, L_000000000413b510;  alias, 1 drivers
+v0000000003b1b060_0 .net "B1_N", 0 0, L_000000000413b580;  alias, 1 drivers
+L_000000000402f320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b100_0 .net8 "VGND", 0 0, L_000000000402f320;  1 drivers, strength-aware
+L_000000000402f080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19bc0_0 .net8 "VNB", 0 0, L_000000000402f080;  1 drivers, strength-aware
+L_000000000402fb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b560_0 .net8 "VPB", 0 0, L_000000000402fb00;  1 drivers, strength-aware
+L_000000000402ef30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1bba0_0 .net8 "VPWR", 0 0, L_000000000402ef30;  1 drivers, strength-aware
+v0000000003b1a8e0_0 .net "Y", 0 0, L_000000000413a470;  alias, 1 drivers
+v0000000003b1b4c0_0 .net "and0_out", 0 0, L_000000000413b5f0;  1 drivers
+v0000000003b1c000_0 .net "b", 0 0, L_000000000413a400;  1 drivers
+v0000000003b1a160_0 .net "nor0_out_Y", 0 0, L_000000000413a160;  1 drivers
+S_0000000003b56690 .scope module, "_0805_" "sky130_fd_sc_hd__inv_2" 3 2164, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b1a520_0 .net "A", 0 0, L_0000000004135540;  alias, 1 drivers
+L_00000000040303c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b9c0_0 .net8 "VGND", 0 0, L_00000000040303c0;  1 drivers, strength-aware
+L_000000000402efa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19a80_0 .net8 "VNB", 0 0, L_000000000402efa0;  1 drivers, strength-aware
+L_000000000402fef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1bec0_0 .net8 "VPB", 0 0, L_000000000402fef0;  1 drivers, strength-aware
+L_000000000402f0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ba60_0 .net8 "VPWR", 0 0, L_000000000402f0f0;  1 drivers, strength-aware
+v0000000003b1a200_0 .net "Y", 0 0, L_000000000413c9a0;  alias, 1 drivers
+S_0000000003b53b10 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b56690;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413a4e0 .functor NOT 1, L_0000000004135540, C4<0>, C4<0>, C4<0>;
+L_000000000413c9a0 .functor BUF 1, L_000000000413a4e0, C4<0>, C4<0>, C4<0>;
+v0000000003b19f80_0 .net "A", 0 0, L_0000000004135540;  alias, 1 drivers
+L_000000000402f390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b7e0_0 .net8 "VGND", 0 0, L_000000000402f390;  1 drivers, strength-aware
+L_000000000402ff60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a480_0 .net8 "VNB", 0 0, L_000000000402ff60;  1 drivers, strength-aware
+L_000000000402f400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ad40_0 .net8 "VPB", 0 0, L_000000000402f400;  1 drivers, strength-aware
+L_000000000402f470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1b880_0 .net8 "VPWR", 0 0, L_000000000402f470;  1 drivers, strength-aware
+v0000000003b19e40_0 .net "Y", 0 0, L_000000000413c9a0;  alias, 1 drivers
+v0000000003b1b920_0 .net "not0_out_Y", 0 0, L_000000000413a4e0;  1 drivers
+S_0000000003b57d10 .scope module, "_0806_" "sky130_fd_sc_hd__or2_2" 3 2168, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b1bf60_0 .net "A", 0 0, L_000000000413c9a0;  alias, 1 drivers
+v0000000003b1aca0_0 .net "B", 0 0, L_00000000041361f0;  alias, 1 drivers
+L_000000000402f4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ade0_0 .net8 "VGND", 0 0, L_000000000402f4e0;  1 drivers, strength-aware
+L_000000000402f630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b199e0_0 .net8 "VNB", 0 0, L_000000000402f630;  1 drivers, strength-aware
+L_0000000004030120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b19b20_0 .net8 "VPB", 0 0, L_0000000004030120;  1 drivers, strength-aware
+L_00000000040319a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a3e0_0 .net8 "VPWR", 0 0, L_00000000040319a0;  1 drivers, strength-aware
+v0000000003b1a340_0 .net "X", 0 0, L_000000000413bb30;  alias, 1 drivers
+S_0000000003b57e90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b57d10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413c3f0 .functor OR 1, L_00000000041361f0, L_000000000413c9a0, C4<0>, C4<0>;
+L_000000000413bb30 .functor BUF 1, L_000000000413c3f0, C4<0>, C4<0>, C4<0>;
+v0000000003b1bb00_0 .net "A", 0 0, L_000000000413c9a0;  alias, 1 drivers
+v0000000003b1bce0_0 .net "B", 0 0, L_00000000041361f0;  alias, 1 drivers
+L_00000000040307b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b19ee0_0 .net8 "VGND", 0 0, L_00000000040307b0;  1 drivers, strength-aware
+L_0000000004031930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c0a0_0 .net8 "VNB", 0 0, L_0000000004031930;  1 drivers, strength-aware
+L_0000000004031fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1bc40_0 .net8 "VPB", 0 0, L_0000000004031fc0;  1 drivers, strength-aware
+L_0000000004030f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a020_0 .net8 "VPWR", 0 0, L_0000000004030f20;  1 drivers, strength-aware
+v0000000003b1be20_0 .net "X", 0 0, L_000000000413bb30;  alias, 1 drivers
+v0000000003b1a0c0_0 .net "or0_out_X", 0 0, L_000000000413c3f0;  1 drivers
+S_0000000003b56810 .scope module, "_0807_" "sky130_fd_sc_hd__inv_2" 3 2173, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b1da40_0 .net "A", 0 0, L_0000000004127d90;  alias, 1 drivers
+L_0000000004030740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c820_0 .net8 "VGND", 0 0, L_0000000004030740;  1 drivers, strength-aware
+L_0000000004030a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1d540_0 .net8 "VNB", 0 0, L_0000000004030a50;  1 drivers, strength-aware
+L_0000000004031ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1d400_0 .net8 "VPB", 0 0, L_0000000004031ee0;  1 drivers, strength-aware
+L_0000000004030dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1dea0_0 .net8 "VPWR", 0 0, L_0000000004030dd0;  1 drivers, strength-aware
+v0000000003b1c5a0_0 .net "Y", 0 0, L_000000000413cb60;  alias, 1 drivers
+S_0000000003b58190 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b56810;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413cfc0 .functor NOT 1, L_0000000004127d90, C4<0>, C4<0>, C4<0>;
+L_000000000413cb60 .functor BUF 1, L_000000000413cfc0, C4<0>, C4<0>, C4<0>;
+v0000000003b1a700_0 .net "A", 0 0, L_0000000004127d90;  alias, 1 drivers
+L_0000000004031e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a2a0_0 .net8 "VGND", 0 0, L_0000000004031e70;  1 drivers, strength-aware
+L_0000000004032030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a5c0_0 .net8 "VNB", 0 0, L_0000000004032030;  1 drivers, strength-aware
+L_0000000004030d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1a980_0 .net8 "VPB", 0 0, L_0000000004030d60;  1 drivers, strength-aware
+L_0000000004030e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1aa20_0 .net8 "VPWR", 0 0, L_0000000004030e40;  1 drivers, strength-aware
+v0000000003b1aac0_0 .net "Y", 0 0, L_000000000413cb60;  alias, 1 drivers
+v0000000003b1ab60_0 .net "not0_out_Y", 0 0, L_000000000413cfc0;  1 drivers
+S_0000000003b54e90 .scope module, "_0808_" "sky130_fd_sc_hd__o21ai_2" 3 2177, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b1e440_0 .net "A1", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b1c780_0 .net "A2", 0 0, L_0000000004136f10;  alias, 1 drivers
+v0000000003b1c140_0 .net "B1", 0 0, L_0000000004135850;  alias, 1 drivers
+L_0000000004031850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1cfa0_0 .net8 "VGND", 0 0, L_0000000004031850;  1 drivers, strength-aware
+L_00000000040312a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e800_0 .net8 "VNB", 0 0, L_00000000040312a0;  1 drivers, strength-aware
+L_0000000004031a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e580_0 .net8 "VPB", 0 0, L_0000000004031a80;  1 drivers, strength-aware
+L_00000000040310e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1db80_0 .net8 "VPWR", 0 0, L_00000000040310e0;  1 drivers, strength-aware
+v0000000003b1cf00_0 .net "Y", 0 0, L_000000000413c690;  alias, 1 drivers
+S_0000000003b53c90 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b54e90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413c380 .functor OR 1, L_0000000004136f10, L_0000000004137290, C4<0>, C4<0>;
+L_000000000413cf50 .functor NAND 1, L_0000000004135850, L_000000000413c380, C4<1>, C4<1>;
+L_000000000413c690 .functor BUF 1, L_000000000413cf50, C4<0>, C4<0>, C4<0>;
+v0000000003b1c6e0_0 .net "A1", 0 0, L_0000000004137290;  alias, 1 drivers
+v0000000003b1d040_0 .net "A2", 0 0, L_0000000004136f10;  alias, 1 drivers
+v0000000003b1e4e0_0 .net "B1", 0 0, L_0000000004135850;  alias, 1 drivers
+L_0000000004030890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c640_0 .net8 "VGND", 0 0, L_0000000004030890;  1 drivers, strength-aware
+L_0000000004030820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1dae0_0 .net8 "VNB", 0 0, L_0000000004030820;  1 drivers, strength-aware
+L_0000000004030970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ce60_0 .net8 "VPB", 0 0, L_0000000004030970;  1 drivers, strength-aware
+L_0000000004030900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e8a0_0 .net8 "VPWR", 0 0, L_0000000004030900;  1 drivers, strength-aware
+v0000000003b1e620_0 .net "Y", 0 0, L_000000000413c690;  alias, 1 drivers
+v0000000003b1d2c0_0 .net "nand0_out_Y", 0 0, L_000000000413cf50;  1 drivers
+v0000000003b1de00_0 .net "or0_out", 0 0, L_000000000413c380;  1 drivers
+S_0000000003b55010 .scope module, "_0809_" "sky130_fd_sc_hd__o21bai_2" 3 2183, 4 60892 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b1d4a0_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b1d0e0_0 .net "A2", 0 0, L_000000000413ae80;  alias, 1 drivers
+v0000000003b1cc80_0 .net "B1_N", 0 0, L_000000000413c690;  alias, 1 drivers
+L_0000000004030eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c960_0 .net8 "VGND", 0 0, L_0000000004030eb0;  1 drivers, strength-aware
+L_0000000004031f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1df40_0 .net8 "VNB", 0 0, L_0000000004031f50;  1 drivers, strength-aware
+L_0000000004031e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c280_0 .net8 "VPB", 0 0, L_0000000004031e00;  1 drivers, strength-aware
+L_00000000040304a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c3c0_0 .net8 "VPWR", 0 0, L_00000000040304a0;  1 drivers, strength-aware
+v0000000003b1d5e0_0 .net "Y", 0 0, L_000000000413c700;  alias, 1 drivers
+S_0000000003b58490 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 60910, 4 61340 1, S_0000000003b55010;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413cbd0 .functor NOT 1, L_000000000413c690, C4<0>, C4<0>, C4<0>;
+L_000000000413ce00 .functor OR 1, L_000000000413ae80, L_0000000004137ae0, C4<0>, C4<0>;
+L_000000000413c460 .functor NAND 1, L_000000000413cbd0, L_000000000413ce00, C4<1>, C4<1>;
+L_000000000413c700 .functor BUF 1, L_000000000413c460, C4<0>, C4<0>, C4<0>;
+v0000000003b1c8c0_0 .net "A1", 0 0, L_0000000004137ae0;  alias, 1 drivers
+v0000000003b1c460_0 .net "A2", 0 0, L_000000000413ae80;  alias, 1 drivers
+v0000000003b1e6c0_0 .net "B1_N", 0 0, L_000000000413c690;  alias, 1 drivers
+L_0000000004030510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c500_0 .net8 "VGND", 0 0, L_0000000004030510;  1 drivers, strength-aware
+L_0000000004030f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1d9a0_0 .net8 "VNB", 0 0, L_0000000004030f90;  1 drivers, strength-aware
+L_0000000004031000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1c320_0 .net8 "VPB", 0 0, L_0000000004031000;  1 drivers, strength-aware
+L_00000000040318c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1d860_0 .net8 "VPWR", 0 0, L_00000000040318c0;  1 drivers, strength-aware
+v0000000003b1dc20_0 .net "Y", 0 0, L_000000000413c700;  alias, 1 drivers
+v0000000003b1c1e0_0 .net "b", 0 0, L_000000000413cbd0;  1 drivers
+v0000000003b1cdc0_0 .net "nand0_out_Y", 0 0, L_000000000413c460;  1 drivers
+v0000000003b1e760_0 .net "or0_out", 0 0, L_000000000413ce00;  1 drivers
+S_0000000003b53f90 .scope module, "_0810_" "sky130_fd_sc_hd__o21ai_2" 3 2189, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b1cbe0_0 .net "A1", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003b1d220_0 .net "A2", 0 0, L_000000000413a240;  alias, 1 drivers
+v0000000003b1cd20_0 .net "B1", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_0000000004030ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e3a0_0 .net8 "VGND", 0 0, L_0000000004030ba0;  1 drivers, strength-aware
+L_0000000004030660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e300_0 .net8 "VNB", 0 0, L_0000000004030660;  1 drivers, strength-aware
+L_0000000004031a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e080_0 .net8 "VPB", 0 0, L_0000000004031a10;  1 drivers, strength-aware
+L_0000000004030580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1d180_0 .net8 "VPWR", 0 0, L_0000000004030580;  1 drivers, strength-aware
+v0000000003b1e120_0 .net "Y", 0 0, L_000000000413c4d0;  alias, 1 drivers
+S_0000000003b54110 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b53f90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413c230 .functor OR 1, L_000000000413a240, L_0000000004135d90, C4<0>, C4<0>;
+L_000000000413cd90 .functor NAND 1, L_0000000004134ba0, L_000000000413c230, C4<1>, C4<1>;
+L_000000000413c4d0 .functor BUF 1, L_000000000413cd90, C4<0>, C4<0>, C4<0>;
+v0000000003b1e1c0_0 .net "A1", 0 0, L_0000000004135d90;  alias, 1 drivers
+v0000000003b1d900_0 .net "A2", 0 0, L_000000000413a240;  alias, 1 drivers
+v0000000003b1ca00_0 .net "B1", 0 0, L_0000000004134ba0;  alias, 1 drivers
+L_0000000004031310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e260_0 .net8 "VGND", 0 0, L_0000000004031310;  1 drivers, strength-aware
+L_0000000004030ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1caa0_0 .net8 "VNB", 0 0, L_0000000004030ac0;  1 drivers, strength-aware
+L_00000000040313f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1dd60_0 .net8 "VPB", 0 0, L_00000000040313f0;  1 drivers, strength-aware
+L_00000000040309e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1dcc0_0 .net8 "VPWR", 0 0, L_00000000040309e0;  1 drivers, strength-aware
+v0000000003b1d680_0 .net "Y", 0 0, L_000000000413c4d0;  alias, 1 drivers
+v0000000003b1dfe0_0 .net "nand0_out_Y", 0 0, L_000000000413cd90;  1 drivers
+v0000000003b1cb40_0 .net "or0_out", 0 0, L_000000000413c230;  1 drivers
+S_0000000003b54890 .scope module, "_0811_" "sky130_fd_sc_hd__o21a_2" 3 2195, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b1f840_0 .net "A1", 0 0, L_000000000413a320;  alias, 1 drivers
+v0000000003b20240_0 .net "A2", 0 0, L_000000000413c690;  alias, 1 drivers
+v0000000003b20920_0 .net "B1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+L_0000000004031070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f520_0 .net8 "VGND", 0 0, L_0000000004031070;  1 drivers, strength-aware
+L_0000000004030cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b202e0_0 .net8 "VNB", 0 0, L_0000000004030cf0;  1 drivers, strength-aware
+L_0000000004030b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20100_0 .net8 "VPB", 0 0, L_0000000004030b30;  1 drivers, strength-aware
+L_0000000004031150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fd40_0 .net8 "VPWR", 0 0, L_0000000004031150;  1 drivers, strength-aware
+v0000000003b1ebc0_0 .net "X", 0 0, L_000000000413d2d0;  alias, 1 drivers
+S_0000000003b54a10 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003b54890;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413d420 .functor OR 1, L_000000000413c690, L_000000000413a320, C4<0>, C4<0>;
+L_000000000413bba0 .functor AND 1, L_000000000413d420, L_000000000413c4d0, C4<1>, C4<1>;
+L_000000000413d2d0 .functor BUF 1, L_000000000413bba0, C4<0>, C4<0>, C4<0>;
+v0000000003b1d360_0 .net "A1", 0 0, L_000000000413a320;  alias, 1 drivers
+v0000000003b1d720_0 .net "A2", 0 0, L_000000000413c690;  alias, 1 drivers
+v0000000003b1d7c0_0 .net "B1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+L_0000000004031690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b209c0_0 .net8 "VGND", 0 0, L_0000000004031690;  1 drivers, strength-aware
+L_00000000040305f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fb60_0 .net8 "VNB", 0 0, L_00000000040305f0;  1 drivers, strength-aware
+L_0000000004031cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ec60_0 .net8 "VPB", 0 0, L_0000000004031cb0;  1 drivers, strength-aware
+L_0000000004030c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20420_0 .net8 "VPWR", 0 0, L_0000000004030c10;  1 drivers, strength-aware
+v0000000003b20380_0 .net "X", 0 0, L_000000000413d2d0;  alias, 1 drivers
+v0000000003b1e940_0 .net "and0_out_X", 0 0, L_000000000413bba0;  1 drivers
+v0000000003b1eb20_0 .net "or0_out", 0 0, L_000000000413d420;  1 drivers
+S_0000000003b55490 .scope module, "_0812_" "sky130_fd_sc_hd__o21ai_2" 3 2201, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b204c0_0 .net "A1", 0 0, L_000000000413cb60;  alias, 1 drivers
+v0000000003b20560_0 .net "A2", 0 0, L_000000000413c700;  alias, 1 drivers
+v0000000003b20c40_0 .net "B1", 0 0, L_000000000413d2d0;  alias, 1 drivers
+L_0000000004031d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1eee0_0 .net8 "VGND", 0 0, L_0000000004031d90;  1 drivers, strength-aware
+L_00000000040306d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1e9e0_0 .net8 "VNB", 0 0, L_00000000040306d0;  1 drivers, strength-aware
+L_00000000040311c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f980_0 .net8 "VPB", 0 0, L_00000000040311c0;  1 drivers, strength-aware
+L_0000000004031af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ea80_0 .net8 "VPWR", 0 0, L_0000000004031af0;  1 drivers, strength-aware
+v0000000003b20e20_0 .net "Y", 0 0, L_000000000413bac0;  alias, 1 drivers
+S_0000000003b55610 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b55490;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413d490 .functor OR 1, L_000000000413c700, L_000000000413cb60, C4<0>, C4<0>;
+L_000000000413cc40 .functor NAND 1, L_000000000413d2d0, L_000000000413d490, C4<1>, C4<1>;
+L_000000000413bac0 .functor BUF 1, L_000000000413cc40, C4<0>, C4<0>, C4<0>;
+v0000000003b1f700_0 .net "A1", 0 0, L_000000000413cb60;  alias, 1 drivers
+v0000000003b1ed00_0 .net "A2", 0 0, L_000000000413c700;  alias, 1 drivers
+v0000000003b20d80_0 .net "B1", 0 0, L_000000000413d2d0;  alias, 1 drivers
+L_0000000004030c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b20a60_0 .net8 "VGND", 0 0, L_0000000004030c80;  1 drivers, strength-aware
+L_0000000004031230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f5c0_0 .net8 "VNB", 0 0, L_0000000004031230;  1 drivers, strength-aware
+L_0000000004031380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20ec0_0 .net8 "VPB", 0 0, L_0000000004031380;  1 drivers, strength-aware
+L_0000000004031460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20f60_0 .net8 "VPWR", 0 0, L_0000000004031460;  1 drivers, strength-aware
+v0000000003b1f660_0 .net "Y", 0 0, L_000000000413bac0;  alias, 1 drivers
+v0000000003b210a0_0 .net "nand0_out_Y", 0 0, L_000000000413cc40;  1 drivers
+v0000000003b20880_0 .net "or0_out", 0 0, L_000000000413d490;  1 drivers
+S_0000000003b55a90 .scope module, "_0813_" "sky130_fd_sc_hd__inv_2" 3 2207, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b1ffc0_0 .net "A", 0 0, L_000000000413bac0;  alias, 1 drivers
+L_00000000040314d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fac0_0 .net8 "VGND", 0 0, L_00000000040314d0;  1 drivers, strength-aware
+L_0000000004031620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fc00_0 .net8 "VNB", 0 0, L_0000000004031620;  1 drivers, strength-aware
+L_0000000004031540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fca0_0 .net8 "VPB", 0 0, L_0000000004031540;  1 drivers, strength-aware
+L_00000000040315b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20ce0_0 .net8 "VPWR", 0 0, L_00000000040315b0;  1 drivers, strength-aware
+v0000000003b1ee40_0 .net "Y", 0 0, L_000000000413cd20;  alias, 1 drivers
+S_0000000003b55c10 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b55a90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413d0a0 .functor NOT 1, L_000000000413bac0, C4<0>, C4<0>, C4<0>;
+L_000000000413cd20 .functor BUF 1, L_000000000413d0a0, C4<0>, C4<0>, C4<0>;
+v0000000003b1f8e0_0 .net "A", 0 0, L_000000000413bac0;  alias, 1 drivers
+L_0000000004031700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fe80_0 .net8 "VGND", 0 0, L_0000000004031700;  1 drivers, strength-aware
+L_0000000004031b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1eda0_0 .net8 "VNB", 0 0, L_0000000004031b60;  1 drivers, strength-aware
+L_0000000004031bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b21000_0 .net8 "VPB", 0 0, L_0000000004031bd0;  1 drivers, strength-aware
+L_0000000004031770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f7a0_0 .net8 "VPWR", 0 0, L_0000000004031770;  1 drivers, strength-aware
+v0000000003b1ff20_0 .net "Y", 0 0, L_000000000413cd20;  alias, 1 drivers
+v0000000003b1fa20_0 .net "not0_out_Y", 0 0, L_000000000413d0a0;  1 drivers
+S_0000000003b55d90 .scope module, "_0814_" "sky130_fd_sc_hd__inv_2" 3 2211, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b201a0_0 .net "A", 0 0, L_000000000413bb30;  alias, 1 drivers
+L_00000000040317e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f200_0 .net8 "VGND", 0 0, L_00000000040317e0;  1 drivers, strength-aware
+L_0000000004031c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f2a0_0 .net8 "VNB", 0 0, L_0000000004031c40;  1 drivers, strength-aware
+L_0000000004031d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20b00_0 .net8 "VPB", 0 0, L_0000000004031d20;  1 drivers, strength-aware
+L_0000000004033450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f340_0 .net8 "VPWR", 0 0, L_0000000004033450;  1 drivers, strength-aware
+v0000000003b20ba0_0 .net "Y", 0 0, L_000000000413ccb0;  alias, 1 drivers
+S_0000000003b56090 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b55d90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413d180 .functor NOT 1, L_000000000413bb30, C4<0>, C4<0>, C4<0>;
+L_000000000413ccb0 .functor BUF 1, L_000000000413d180, C4<0>, C4<0>, C4<0>;
+v0000000003b20060_0 .net "A", 0 0, L_000000000413bb30;  alias, 1 drivers
+L_0000000004032ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1fde0_0 .net8 "VGND", 0 0, L_0000000004032ab0;  1 drivers, strength-aware
+L_0000000004032c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1ef80_0 .net8 "VNB", 0 0, L_0000000004032c70;  1 drivers, strength-aware
+L_0000000004033760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f020_0 .net8 "VPB", 0 0, L_0000000004033760;  1 drivers, strength-aware
+L_0000000004033a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b20600_0 .net8 "VPWR", 0 0, L_0000000004033a70;  1 drivers, strength-aware
+v0000000003b1f0c0_0 .net "Y", 0 0, L_000000000413ccb0;  alias, 1 drivers
+v0000000003b1f160_0 .net "not0_out_Y", 0 0, L_000000000413d180;  1 drivers
+S_0000000003b5a110 .scope module, "_0815_" "sky130_fd_sc_hd__o22a_2" 3 2215, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b22400_0 .net "A1", 0 0, L_000000000413bb30;  alias, 1 drivers
+v0000000003b224a0_0 .net "A2", 0 0, L_000000000413cd20;  alias, 1 drivers
+v0000000003b22fe0_0 .net "B1", 0 0, L_000000000413ccb0;  alias, 1 drivers
+v0000000003b229a0_0 .net "B2", 0 0, L_000000000413bac0;  alias, 1 drivers
+L_00000000040320a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b23580_0 .net8 "VGND", 0 0, L_00000000040320a0;  1 drivers, strength-aware
+L_00000000040323b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21be0_0 .net8 "VNB", 0 0, L_00000000040323b0;  1 drivers, strength-aware
+L_0000000004033ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b21b40_0 .net8 "VPB", 0 0, L_0000000004033ae0;  1 drivers, strength-aware
+L_0000000004032570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22cc0_0 .net8 "VPWR", 0 0, L_0000000004032570;  1 drivers, strength-aware
+v0000000003b21780_0 .net "X", 0 0, L_000000000413cee0;  alias, 1 drivers
+S_0000000003b5a590 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000003b5a110;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413c2a0 .functor OR 1, L_000000000413cd20, L_000000000413bb30, C4<0>, C4<0>;
+L_000000000413bdd0 .functor OR 1, L_000000000413bac0, L_000000000413ccb0, C4<0>, C4<0>;
+L_000000000413d1f0 .functor AND 1, L_000000000413c2a0, L_000000000413bdd0, C4<1>, C4<1>;
+L_000000000413cee0 .functor BUF 1, L_000000000413d1f0, C4<0>, C4<0>, C4<0>;
+v0000000003b206a0_0 .net "A1", 0 0, L_000000000413bb30;  alias, 1 drivers
+v0000000003b20740_0 .net "A2", 0 0, L_000000000413cd20;  alias, 1 drivers
+v0000000003b1f3e0_0 .net "B1", 0 0, L_000000000413ccb0;  alias, 1 drivers
+v0000000003b207e0_0 .net "B2", 0 0, L_000000000413bac0;  alias, 1 drivers
+L_00000000040327a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b1f480_0 .net8 "VGND", 0 0, L_00000000040327a0;  1 drivers, strength-aware
+L_0000000004033b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b216e0_0 .net8 "VNB", 0 0, L_0000000004033b50;  1 drivers, strength-aware
+L_0000000004033680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22220_0 .net8 "VPB", 0 0, L_0000000004033680;  1 drivers, strength-aware
+L_00000000040326c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b23800_0 .net8 "VPWR", 0 0, L_00000000040326c0;  1 drivers, strength-aware
+v0000000003b233a0_0 .net "X", 0 0, L_000000000413cee0;  alias, 1 drivers
+v0000000003b21500_0 .net "and0_out_X", 0 0, L_000000000413d1f0;  1 drivers
+v0000000003b22860_0 .net "or0_out", 0 0, L_000000000413c2a0;  1 drivers
+v0000000003b21820_0 .net "or1_out", 0 0, L_000000000413bdd0;  1 drivers
+S_0000000003b5d890 .scope module, "_0816_" "sky130_fd_sc_hd__or2_2" 3 2222, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b22ea0_0 .net "A", 0 0, L_000000000413b580;  alias, 1 drivers
+v0000000003b21c80_0 .net "B", 0 0, L_000000000413cee0;  alias, 1 drivers
+L_0000000004033990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21fa0_0 .net8 "VGND", 0 0, L_0000000004033990;  1 drivers, strength-aware
+L_0000000004033290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b23120_0 .net8 "VNB", 0 0, L_0000000004033290;  1 drivers, strength-aware
+L_00000000040335a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b222c0_0 .net8 "VPB", 0 0, L_00000000040335a0;  1 drivers, strength-aware
+L_0000000004032ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b21960_0 .net8 "VPWR", 0 0, L_0000000004032ea0;  1 drivers, strength-aware
+v0000000003b220e0_0 .net "X", 0 0, L_000000000413c850;  alias, 1 drivers
+S_0000000003b59990 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5d890;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413d030 .functor OR 1, L_000000000413cee0, L_000000000413b580, C4<0>, C4<0>;
+L_000000000413c850 .functor BUF 1, L_000000000413d030, C4<0>, C4<0>, C4<0>;
+v0000000003b22900_0 .net "A", 0 0, L_000000000413b580;  alias, 1 drivers
+v0000000003b21640_0 .net "B", 0 0, L_000000000413cee0;  alias, 1 drivers
+L_0000000004032f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b22040_0 .net8 "VGND", 0 0, L_0000000004032f10;  1 drivers, strength-aware
+L_0000000004032b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b22540_0 .net8 "VNB", 0 0, L_0000000004032b20;  1 drivers, strength-aware
+L_0000000004032880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22f40_0 .net8 "VPB", 0 0, L_0000000004032880;  1 drivers, strength-aware
+L_0000000004033300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22a40_0 .net8 "VPWR", 0 0, L_0000000004033300;  1 drivers, strength-aware
+v0000000003b218c0_0 .net "X", 0 0, L_000000000413c850;  alias, 1 drivers
+v0000000003b23080_0 .net "or0_out_X", 0 0, L_000000000413d030;  1 drivers
+S_0000000003b5b490 .scope module, "_0817_" "sky130_fd_sc_hd__a21boi_2" 3 2227, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b22ae0_0 .net "A1", 0 0, L_000000000413b580;  alias, 1 drivers
+v0000000003b21f00_0 .net "A2", 0 0, L_000000000413cee0;  alias, 1 drivers
+v0000000003b231c0_0 .net "B1_N", 0 0, L_000000000413c850;  alias, 1 drivers
+L_00000000040322d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b215a0_0 .net8 "VGND", 0 0, L_00000000040322d0;  1 drivers, strength-aware
+L_0000000004033a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b22b80_0 .net8 "VNB", 0 0, L_0000000004033a00;  1 drivers, strength-aware
+L_0000000004033bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b227c0_0 .net8 "VPB", 0 0, L_0000000004033bc0;  1 drivers, strength-aware
+L_00000000040334c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22c20_0 .net8 "VPWR", 0 0, L_00000000040334c0;  1 drivers, strength-aware
+v0000000003b22d60_0 .net "Y", 0 0, L_000000000413b900;  alias, 1 drivers
+S_0000000003b5ad10 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b5b490;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413d340 .functor NOT 1, L_000000000413c850, C4<0>, C4<0>, C4<0>;
+L_000000000413c770 .functor AND 1, L_000000000413b580, L_000000000413cee0, C4<1>, C4<1>;
+L_000000000413c1c0 .functor NOR 1, L_000000000413d340, L_000000000413c770, C4<0>, C4<0>;
+L_000000000413b900 .functor BUF 1, L_000000000413c1c0, C4<0>, C4<0>, C4<0>;
+v0000000003b23760_0 .net "A1", 0 0, L_000000000413b580;  alias, 1 drivers
+v0000000003b21e60_0 .net "A2", 0 0, L_000000000413cee0;  alias, 1 drivers
+v0000000003b234e0_0 .net "B1_N", 0 0, L_000000000413c850;  alias, 1 drivers
+L_0000000004032730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b22360_0 .net8 "VGND", 0 0, L_0000000004032730;  1 drivers, strength-aware
+L_0000000004032810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b238a0_0 .net8 "VNB", 0 0, L_0000000004032810;  1 drivers, strength-aware
+L_0000000004032f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b225e0_0 .net8 "VPB", 0 0, L_0000000004032f80;  1 drivers, strength-aware
+L_0000000004032420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b22680_0 .net8 "VPWR", 0 0, L_0000000004032420;  1 drivers, strength-aware
+v0000000003b21a00_0 .net "Y", 0 0, L_000000000413b900;  alias, 1 drivers
+v0000000003b22720_0 .net "and0_out", 0 0, L_000000000413c770;  1 drivers
+v0000000003b21140_0 .net "b", 0 0, L_000000000413d340;  1 drivers
+v0000000003b22180_0 .net "nor0_out_Y", 0 0, L_000000000413c1c0;  1 drivers
+S_0000000003b5cc90 .scope module, "_0818_" "sky130_fd_sc_hd__or2_2" 3 2233, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b23440_0 .net "A", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003b211e0_0 .net "B", 0 0, L_0000000004134820;  alias, 1 drivers
+L_0000000004032b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21280_0 .net8 "VGND", 0 0, L_0000000004032b90;  1 drivers, strength-aware
+L_0000000004032490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21320_0 .net8 "VNB", 0 0, L_0000000004032490;  1 drivers, strength-aware
+L_0000000004032500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b213c0_0 .net8 "VPB", 0 0, L_0000000004032500;  1 drivers, strength-aware
+L_0000000004033370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b21460_0 .net8 "VPWR", 0 0, L_0000000004033370;  1 drivers, strength-aware
+v0000000003b23940_0 .net "X", 0 0, L_000000000413bc80;  alias, 1 drivers
+S_0000000003b5a410 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5cc90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413beb0 .functor OR 1, L_0000000004134820, L_00000000041367a0, C4<0>, C4<0>;
+L_000000000413bc80 .functor BUF 1, L_000000000413beb0, C4<0>, C4<0>, C4<0>;
+v0000000003b22e00_0 .net "A", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003b21aa0_0 .net "B", 0 0, L_0000000004134820;  alias, 1 drivers
+L_0000000004033610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21d20_0 .net8 "VGND", 0 0, L_0000000004033610;  1 drivers, strength-aware
+L_0000000004032c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b21dc0_0 .net8 "VNB", 0 0, L_0000000004032c00;  1 drivers, strength-aware
+L_0000000004032ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b23260_0 .net8 "VPB", 0 0, L_0000000004032ce0;  1 drivers, strength-aware
+L_0000000004033c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b23620_0 .net8 "VPWR", 0 0, L_0000000004033c30;  1 drivers, strength-aware
+v0000000003b236c0_0 .net "X", 0 0, L_000000000413bc80;  alias, 1 drivers
+v0000000003b23300_0 .net "or0_out_X", 0 0, L_000000000413beb0;  1 drivers
+S_0000000003b59b10 .scope module, "_0819_" "sky130_fd_sc_hd__a2bb2o_2" 3 2238, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b260a0_0 .net "A1_N", 0 0, L_0000000004137840;  alias, 1 drivers
+v0000000003b23bc0_0 .net "A2_N", 0 0, L_000000000413bc80;  alias, 1 drivers
+v0000000003b25600_0 .net "B1", 0 0, L_0000000004137840;  alias, 1 drivers
+v0000000003b24c00_0 .net "B2", 0 0, L_000000000413bc80;  alias, 1 drivers
+L_0000000004032d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b243e0_0 .net8 "VGND", 0 0, L_0000000004032d50;  1 drivers, strength-aware
+L_0000000004032340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b256a0_0 .net8 "VNB", 0 0, L_0000000004032340;  1 drivers, strength-aware
+L_0000000004032650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b24700_0 .net8 "VPB", 0 0, L_0000000004032650;  1 drivers, strength-aware
+L_0000000004032110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b259c0_0 .net8 "VPWR", 0 0, L_0000000004032110;  1 drivers, strength-aware
+v0000000003b240c0_0 .net "X", 0 0, L_000000000413d260;  alias, 1 drivers
+S_0000000003b5d710 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003b59b10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413c540 .functor AND 1, L_0000000004137840, L_000000000413bc80, C4<1>, C4<1>;
+L_000000000413d110 .functor NOR 1, L_0000000004137840, L_000000000413bc80, C4<0>, C4<0>;
+L_000000000413c150 .functor OR 1, L_000000000413d110, L_000000000413c540, C4<0>, C4<0>;
+L_000000000413d260 .functor BUF 1, L_000000000413c150, C4<0>, C4<0>, C4<0>;
+v0000000003b24ac0_0 .net "A1_N", 0 0, L_0000000004137840;  alias, 1 drivers
+v0000000003b24f20_0 .net "A2_N", 0 0, L_000000000413bc80;  alias, 1 drivers
+v0000000003b25060_0 .net "B1", 0 0, L_0000000004137840;  alias, 1 drivers
+v0000000003b252e0_0 .net "B2", 0 0, L_000000000413bc80;  alias, 1 drivers
+L_00000000040329d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25100_0 .net8 "VGND", 0 0, L_00000000040329d0;  1 drivers, strength-aware
+L_0000000004032180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25740_0 .net8 "VNB", 0 0, L_0000000004032180;  1 drivers, strength-aware
+L_00000000040321f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b25560_0 .net8 "VPB", 0 0, L_00000000040321f0;  1 drivers, strength-aware
+L_0000000004032960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b25ba0_0 .net8 "VPWR", 0 0, L_0000000004032960;  1 drivers, strength-aware
+v0000000003b247a0_0 .net "X", 0 0, L_000000000413d260;  alias, 1 drivers
+v0000000003b248e0_0 .net "and0_out", 0 0, L_000000000413c540;  1 drivers
+v0000000003b26000_0 .net "nor0_out", 0 0, L_000000000413d110;  1 drivers
+v0000000003b239e0_0 .net "or0_out_X", 0 0, L_000000000413c150;  1 drivers
+S_0000000003b5d290 .scope module, "_0820_" "sky130_fd_sc_hd__or2_2" 3 2245, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b251a0_0 .net "A", 0 0, L_000000000413c850;  alias, 1 drivers
+v0000000003b24020_0 .net "B", 0 0, L_000000000413d260;  alias, 1 drivers
+L_0000000004032a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25420_0 .net8 "VGND", 0 0, L_0000000004032a40;  1 drivers, strength-aware
+L_0000000004032dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25920_0 .net8 "VNB", 0 0, L_0000000004032dc0;  1 drivers, strength-aware
+L_00000000040333e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b23d00_0 .net8 "VPB", 0 0, L_00000000040333e0;  1 drivers, strength-aware
+L_0000000004032260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b24ca0_0 .net8 "VPWR", 0 0, L_0000000004032260;  1 drivers, strength-aware
+v0000000003b25880_0 .net "X", 0 0, L_000000000413bd60;  alias, 1 drivers
+S_0000000003b59390 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5d290;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413b970 .functor OR 1, L_000000000413d260, L_000000000413c850, C4<0>, C4<0>;
+L_000000000413bd60 .functor BUF 1, L_000000000413b970, C4<0>, C4<0>, C4<0>;
+v0000000003b257e0_0 .net "A", 0 0, L_000000000413c850;  alias, 1 drivers
+v0000000003b25240_0 .net "B", 0 0, L_000000000413d260;  alias, 1 drivers
+L_00000000040325e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25f60_0 .net8 "VGND", 0 0, L_00000000040325e0;  1 drivers, strength-aware
+L_0000000004033530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b24b60_0 .net8 "VNB", 0 0, L_0000000004033530;  1 drivers, strength-aware
+L_0000000004032e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b25ce0_0 .net8 "VPB", 0 0, L_0000000004032e30;  1 drivers, strength-aware
+L_00000000040338b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b23da0_0 .net8 "VPWR", 0 0, L_00000000040338b0;  1 drivers, strength-aware
+v0000000003b24840_0 .net "X", 0 0, L_000000000413bd60;  alias, 1 drivers
+v0000000003b25380_0 .net "or0_out_X", 0 0, L_000000000413b970;  1 drivers
+S_0000000003b5aa10 .scope module, "_0821_" "sky130_fd_sc_hd__a21boi_2" 3 2250, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b25d80_0 .net "A1", 0 0, L_000000000413c850;  alias, 1 drivers
+v0000000003b24de0_0 .net "A2", 0 0, L_000000000413d260;  alias, 1 drivers
+v0000000003b23f80_0 .net "B1_N", 0 0, L_000000000413bd60;  alias, 1 drivers
+L_00000000040328f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b24e80_0 .net8 "VGND", 0 0, L_00000000040328f0;  1 drivers, strength-aware
+L_0000000004032ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b23b20_0 .net8 "VNB", 0 0, L_0000000004032ff0;  1 drivers, strength-aware
+L_0000000004033060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b24a20_0 .net8 "VPB", 0 0, L_0000000004033060;  1 drivers, strength-aware
+L_00000000040330d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b24160_0 .net8 "VPWR", 0 0, L_00000000040330d0;  1 drivers, strength-aware
+v0000000003b24660_0 .net "Y", 0 0, L_000000000413c7e0;  alias, 1 drivers
+S_0000000003b5d410 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b5aa10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413ce70 .functor NOT 1, L_000000000413bd60, C4<0>, C4<0>, C4<0>;
+L_000000000413d3b0 .functor AND 1, L_000000000413c850, L_000000000413d260, C4<1>, C4<1>;
+L_000000000413b9e0 .functor NOR 1, L_000000000413ce70, L_000000000413d3b0, C4<0>, C4<0>;
+L_000000000413c7e0 .functor BUF 1, L_000000000413b9e0, C4<0>, C4<0>, C4<0>;
+v0000000003b25a60_0 .net "A1", 0 0, L_000000000413c850;  alias, 1 drivers
+v0000000003b24d40_0 .net "A2", 0 0, L_000000000413d260;  alias, 1 drivers
+v0000000003b23c60_0 .net "B1_N", 0 0, L_000000000413bd60;  alias, 1 drivers
+L_0000000004033140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b24980_0 .net8 "VGND", 0 0, L_0000000004033140;  1 drivers, strength-aware
+L_00000000040331b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b23e40_0 .net8 "VNB", 0 0, L_00000000040331b0;  1 drivers, strength-aware
+L_0000000004033220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b245c0_0 .net8 "VPB", 0 0, L_0000000004033220;  1 drivers, strength-aware
+L_00000000040336f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b254c0_0 .net8 "VPWR", 0 0, L_00000000040336f0;  1 drivers, strength-aware
+v0000000003b23ee0_0 .net "Y", 0 0, L_000000000413c7e0;  alias, 1 drivers
+v0000000003b23a80_0 .net "and0_out", 0 0, L_000000000413d3b0;  1 drivers
+v0000000003b25b00_0 .net "b", 0 0, L_000000000413ce70;  1 drivers
+v0000000003b25c40_0 .net "nor0_out_Y", 0 0, L_000000000413b9e0;  1 drivers
+S_0000000003b5c690 .scope module, "_0822_" "sky130_fd_sc_hd__inv_2" 3 2256, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b24fc0_0 .net "A", 0 0, L_00000000041340b0;  alias, 1 drivers
+L_00000000040337d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27ea0_0 .net8 "VGND", 0 0, L_00000000040337d0;  1 drivers, strength-aware
+L_0000000004033840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27cc0_0 .net8 "VNB", 0 0, L_0000000004033840;  1 drivers, strength-aware
+L_0000000004033920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27d60_0 .net8 "VPB", 0 0, L_0000000004033920;  1 drivers, strength-aware
+L_00000000040353d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b281c0_0 .net8 "VPWR", 0 0, L_00000000040353d0;  1 drivers, strength-aware
+v0000000003b27fe0_0 .net "Y", 0 0, L_000000000413bc10;  alias, 1 drivers
+S_0000000003b5e790 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b5c690;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413ba50 .functor NOT 1, L_00000000041340b0, C4<0>, C4<0>, C4<0>;
+L_000000000413bc10 .functor BUF 1, L_000000000413ba50, C4<0>, C4<0>, C4<0>;
+v0000000003b24520_0 .net "A", 0 0, L_00000000041340b0;  alias, 1 drivers
+L_00000000040349c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b25ec0_0 .net8 "VGND", 0 0, L_00000000040349c0;  1 drivers, strength-aware
+L_0000000004035590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b24200_0 .net8 "VNB", 0 0, L_0000000004035590;  1 drivers, strength-aware
+L_0000000004034b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b242a0_0 .net8 "VPB", 0 0, L_0000000004034b80;  1 drivers, strength-aware
+L_00000000040350c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b25e20_0 .net8 "VPWR", 0 0, L_00000000040350c0;  1 drivers, strength-aware
+v0000000003b24340_0 .net "Y", 0 0, L_000000000413bc10;  alias, 1 drivers
+v0000000003b24480_0 .net "not0_out_Y", 0 0, L_000000000413ba50;  1 drivers
+S_0000000003b5b190 .scope module, "_0823_" "sky130_fd_sc_hd__or2_2" 3 2260, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b26b40_0 .net "A", 0 0, L_000000000413bc10;  alias, 1 drivers
+v0000000003b26fa0_0 .net "B", 0 0, L_0000000004133080;  alias, 1 drivers
+L_0000000004034020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b26320_0 .net8 "VGND", 0 0, L_0000000004034020;  1 drivers, strength-aware
+L_0000000004034100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b272c0_0 .net8 "VNB", 0 0, L_0000000004034100;  1 drivers, strength-aware
+L_0000000004034fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27220_0 .net8 "VPB", 0 0, L_0000000004034fe0;  1 drivers, strength-aware
+L_0000000004035050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b270e0_0 .net8 "VPWR", 0 0, L_0000000004035050;  1 drivers, strength-aware
+v0000000003b263c0_0 .net "X", 0 0, L_000000000413be40;  alias, 1 drivers
+S_0000000003b5ab90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5b190;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413bcf0 .functor OR 1, L_0000000004133080, L_000000000413bc10, C4<0>, C4<0>;
+L_000000000413be40 .functor BUF 1, L_000000000413bcf0, C4<0>, C4<0>, C4<0>;
+v0000000003b28080_0 .net "A", 0 0, L_000000000413bc10;  alias, 1 drivers
+v0000000003b26140_0 .net "B", 0 0, L_0000000004133080;  alias, 1 drivers
+L_0000000004033d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27a40_0 .net8 "VGND", 0 0, L_0000000004033d80;  1 drivers, strength-aware
+L_0000000004035130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27f40_0 .net8 "VNB", 0 0, L_0000000004035130;  1 drivers, strength-aware
+L_0000000004034e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27900_0 .net8 "VPB", 0 0, L_0000000004034e20;  1 drivers, strength-aware
+L_0000000004035600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26820_0 .net8 "VPWR", 0 0, L_0000000004035600;  1 drivers, strength-aware
+v0000000003b28120_0 .net "X", 0 0, L_000000000413be40;  alias, 1 drivers
+v0000000003b28760_0 .net "or0_out_X", 0 0, L_000000000413bcf0;  1 drivers
+S_0000000003b5e010 .scope module, "_0824_" "sky130_fd_sc_hd__o21ai_2" 3 2265, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b27ae0_0 .net "A1", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003b26f00_0 .net "A2", 0 0, L_00000000041352a0;  alias, 1 drivers
+v0000000003b28300_0 .net "B1", 0 0, L_00000000041344a0;  alias, 1 drivers
+L_0000000004034170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b265a0_0 .net8 "VGND", 0 0, L_0000000004034170;  1 drivers, strength-aware
+L_00000000040357c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27b80_0 .net8 "VNB", 0 0, L_00000000040357c0;  1 drivers, strength-aware
+L_0000000004033ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27180_0 .net8 "VPB", 0 0, L_0000000004033ed0;  1 drivers, strength-aware
+L_0000000004035830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27c20_0 .net8 "VPWR", 0 0, L_0000000004035830;  1 drivers, strength-aware
+v0000000003b27360_0 .net "Y", 0 0, L_000000000413bf90;  alias, 1 drivers
+S_0000000003b59c90 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b5e010;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413c8c0 .functor OR 1, L_00000000041352a0, L_00000000041367a0, C4<0>, C4<0>;
+L_000000000413bf20 .functor NAND 1, L_00000000041344a0, L_000000000413c8c0, C4<1>, C4<1>;
+L_000000000413bf90 .functor BUF 1, L_000000000413bf20, C4<0>, C4<0>, C4<0>;
+v0000000003b26e60_0 .net "A1", 0 0, L_00000000041367a0;  alias, 1 drivers
+v0000000003b288a0_0 .net "A2", 0 0, L_00000000041352a0;  alias, 1 drivers
+v0000000003b28260_0 .net "B1", 0 0, L_00000000041344a0;  alias, 1 drivers
+L_00000000040351a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28800_0 .net8 "VGND", 0 0, L_00000000040351a0;  1 drivers, strength-aware
+L_0000000004034aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b279a0_0 .net8 "VNB", 0 0, L_0000000004034aa0;  1 drivers, strength-aware
+L_0000000004035280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27540_0 .net8 "VPB", 0 0, L_0000000004035280;  1 drivers, strength-aware
+L_00000000040348e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26a00_0 .net8 "VPWR", 0 0, L_00000000040348e0;  1 drivers, strength-aware
+v0000000003b27720_0 .net "Y", 0 0, L_000000000413bf90;  alias, 1 drivers
+v0000000003b261e0_0 .net "nand0_out_Y", 0 0, L_000000000413bf20;  1 drivers
+v0000000003b27040_0 .net "or0_out", 0 0, L_000000000413c8c0;  1 drivers
+S_0000000003b5ce10 .scope module, "_0825_" "sky130_fd_sc_hd__or2_2" 3 2271, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b275e0_0 .net "A", 0 0, L_000000000413c690;  alias, 1 drivers
+v0000000003b284e0_0 .net "B", 0 0, L_000000000413bf90;  alias, 1 drivers
+L_0000000004034090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b27680_0 .net8 "VGND", 0 0, L_0000000004034090;  1 drivers, strength-aware
+L_00000000040341e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b26460_0 .net8 "VNB", 0 0, L_00000000040341e0;  1 drivers, strength-aware
+L_0000000004034250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26500_0 .net8 "VPB", 0 0, L_0000000004034250;  1 drivers, strength-aware
+L_0000000004033fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b28580_0 .net8 "VPWR", 0 0, L_0000000004033fb0;  1 drivers, strength-aware
+v0000000003b26be0_0 .net "X", 0 0, L_000000000413c070;  alias, 1 drivers
+S_0000000003b5a710 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5ce10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413c000 .functor OR 1, L_000000000413bf90, L_000000000413c690, C4<0>, C4<0>;
+L_000000000413c070 .functor BUF 1, L_000000000413c000, C4<0>, C4<0>, C4<0>;
+v0000000003b283a0_0 .net "A", 0 0, L_000000000413c690;  alias, 1 drivers
+v0000000003b27400_0 .net "B", 0 0, L_000000000413bf90;  alias, 1 drivers
+L_00000000040346b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b274a0_0 .net8 "VGND", 0 0, L_00000000040346b0;  1 drivers, strength-aware
+L_0000000004035670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b277c0_0 .net8 "VNB", 0 0, L_0000000004035670;  1 drivers, strength-aware
+L_00000000040356e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26640_0 .net8 "VPB", 0 0, L_00000000040356e0;  1 drivers, strength-aware
+L_0000000004035750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b27e00_0 .net8 "VPWR", 0 0, L_0000000004035750;  1 drivers, strength-aware
+v0000000003b26280_0 .net "X", 0 0, L_000000000413c070;  alias, 1 drivers
+v0000000003b28440_0 .net "or0_out_X", 0 0, L_000000000413c000;  1 drivers
+S_0000000003b5d590 .scope module, "_0826_" "sky130_fd_sc_hd__o21ai_2" 3 2276, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b26dc0_0 .net "A1", 0 0, L_00000000041336a0;  alias, 1 drivers
+v0000000003b2ace0_0 .net "A2", 0 0, L_000000000413c9a0;  alias, 1 drivers
+v0000000003b28ee0_0 .net "B1", 0 0, L_0000000004133da0;  alias, 1 drivers
+L_0000000004033ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29a20_0 .net8 "VGND", 0 0, L_0000000004033ca0;  1 drivers, strength-aware
+L_0000000004034790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b000_0 .net8 "VNB", 0 0, L_0000000004034790;  1 drivers, strength-aware
+L_00000000040345d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a1a0_0 .net8 "VPB", 0 0, L_00000000040345d0;  1 drivers, strength-aware
+L_0000000004035210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b28d00_0 .net8 "VPWR", 0 0, L_0000000004035210;  1 drivers, strength-aware
+v0000000003b2a060_0 .net "Y", 0 0, L_000000000413c310;  alias, 1 drivers
+S_0000000003b59690 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b5d590;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413c0e0 .functor OR 1, L_000000000413c9a0, L_00000000041336a0, C4<0>, C4<0>;
+L_000000000413ca80 .functor NAND 1, L_0000000004133da0, L_000000000413c0e0, C4<1>, C4<1>;
+L_000000000413c310 .functor BUF 1, L_000000000413ca80, C4<0>, C4<0>, C4<0>;
+v0000000003b26d20_0 .net "A1", 0 0, L_00000000041336a0;  alias, 1 drivers
+v0000000003b28620_0 .net "A2", 0 0, L_000000000413c9a0;  alias, 1 drivers
+v0000000003b266e0_0 .net "B1", 0 0, L_0000000004133da0;  alias, 1 drivers
+L_00000000040343a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b286c0_0 .net8 "VGND", 0 0, L_00000000040343a0;  1 drivers, strength-aware
+L_0000000004033e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b268c0_0 .net8 "VNB", 0 0, L_0000000004033e60;  1 drivers, strength-aware
+L_00000000040352f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26780_0 .net8 "VPB", 0 0, L_00000000040352f0;  1 drivers, strength-aware
+L_0000000004033d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b26960_0 .net8 "VPWR", 0 0, L_0000000004033d10;  1 drivers, strength-aware
+v0000000003b26aa0_0 .net "Y", 0 0, L_000000000413c310;  alias, 1 drivers
+v0000000003b26c80_0 .net "nand0_out_Y", 0 0, L_000000000413ca80;  1 drivers
+v0000000003b27860_0 .net "or0_out", 0 0, L_000000000413c0e0;  1 drivers
+S_0000000003b5dd10 .scope module, "_0827_" "sky130_fd_sc_hd__o221a_2" 3 2282, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003b293e0_0 .net "A1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+v0000000003b29340_0 .net "A2", 0 0, L_000000000413bf90;  alias, 1 drivers
+v0000000003b2a4c0_0 .net "B1", 0 0, L_000000000413ad30;  alias, 1 drivers
+v0000000003b28f80_0 .net "B2", 0 0, L_000000000413c070;  alias, 1 drivers
+v0000000003b2a560_0 .net "C1", 0 0, L_000000000413c310;  alias, 1 drivers
+L_0000000004034b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a9c0_0 .net8 "VGND", 0 0, L_0000000004034b10;  1 drivers, strength-aware
+L_00000000040342c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29c00_0 .net8 "VNB", 0 0, L_00000000040342c0;  1 drivers, strength-aware
+L_0000000004034bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a380_0 .net8 "VPB", 0 0, L_0000000004034bf0;  1 drivers, strength-aware
+L_0000000004034330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a740_0 .net8 "VPWR", 0 0, L_0000000004034330;  1 drivers, strength-aware
+v0000000003b2a420_0 .net "X", 0 0, L_000000000413ca10;  alias, 1 drivers
+S_0000000003b5cb10 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003b5dd10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000413c5b0 .functor OR 1, L_000000000413c070, L_000000000413ad30, C4<0>, C4<0>;
+L_000000000413c620 .functor OR 1, L_000000000413bf90, L_000000000413c4d0, C4<0>, C4<0>;
+L_000000000413c930 .functor AND 1, L_000000000413c5b0, L_000000000413c620, L_000000000413c310, C4<1>;
+L_000000000413ca10 .functor BUF 1, L_000000000413c930, C4<0>, C4<0>, C4<0>;
+v0000000003b2af60_0 .net "A1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+v0000000003b29ac0_0 .net "A2", 0 0, L_000000000413bf90;  alias, 1 drivers
+v0000000003b2ad80_0 .net "B1", 0 0, L_000000000413ad30;  alias, 1 drivers
+v0000000003b29b60_0 .net "B2", 0 0, L_000000000413c070;  alias, 1 drivers
+v0000000003b2b0a0_0 .net "C1", 0 0, L_000000000413c310;  alias, 1 drivers
+L_0000000004034870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a240_0 .net8 "VGND", 0 0, L_0000000004034870;  1 drivers, strength-aware
+L_0000000004033f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28da0_0 .net8 "VNB", 0 0, L_0000000004033f40;  1 drivers, strength-aware
+L_0000000004034c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a100_0 .net8 "VPB", 0 0, L_0000000004034c60;  1 drivers, strength-aware
+L_0000000004034640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b29020_0 .net8 "VPWR", 0 0, L_0000000004034640;  1 drivers, strength-aware
+v0000000003b297a0_0 .net "X", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003b2a920_0 .net "and0_out_X", 0 0, L_000000000413c930;  1 drivers
+v0000000003b28e40_0 .net "or0_out", 0 0, L_000000000413c5b0;  1 drivers
+v0000000003b2a2e0_0 .net "or1_out", 0 0, L_000000000413c620;  1 drivers
+S_0000000003b59e10 .scope module, "_0828_" "sky130_fd_sc_hd__inv_2" 3 2290, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b29d40_0 .net "A", 0 0, L_000000000413be40;  alias, 1 drivers
+L_0000000004035360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29de0_0 .net8 "VGND", 0 0, L_0000000004035360;  1 drivers, strength-aware
+L_0000000004034cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29980_0 .net8 "VNB", 0 0, L_0000000004034cd0;  1 drivers, strength-aware
+L_0000000004035440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b290c0_0 .net8 "VPB", 0 0, L_0000000004035440;  1 drivers, strength-aware
+L_0000000004033df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ae20_0 .net8 "VPWR", 0 0, L_0000000004033df0;  1 drivers, strength-aware
+v0000000003b2aa60_0 .net "Y", 0 0, L_000000000413d730;  alias, 1 drivers
+S_0000000003b5b610 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b59e10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413caf0 .functor NOT 1, L_000000000413be40, C4<0>, C4<0>, C4<0>;
+L_000000000413d730 .functor BUF 1, L_000000000413caf0, C4<0>, C4<0>, C4<0>;
+v0000000003b29520_0 .net "A", 0 0, L_000000000413be40;  alias, 1 drivers
+L_0000000004034410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29840_0 .net8 "VGND", 0 0, L_0000000004034410;  1 drivers, strength-aware
+L_0000000004034950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a880_0 .net8 "VNB", 0 0, L_0000000004034950;  1 drivers, strength-aware
+L_0000000004034db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b28bc0_0 .net8 "VPB", 0 0, L_0000000004034db0;  1 drivers, strength-aware
+L_0000000004034480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b29ca0_0 .net8 "VPWR", 0 0, L_0000000004034480;  1 drivers, strength-aware
+v0000000003b29480_0 .net "Y", 0 0, L_000000000413d730;  alias, 1 drivers
+v0000000003b298e0_0 .net "not0_out_Y", 0 0, L_000000000413caf0;  1 drivers
+S_0000000003b5ea90 .scope module, "_0829_" "sky130_fd_sc_hd__inv_2" 3 2294, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b2aec0_0 .net "A", 0 0, L_000000000413ca10;  alias, 1 drivers
+L_00000000040344f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28a80_0 .net8 "VGND", 0 0, L_00000000040344f0;  1 drivers, strength-aware
+L_00000000040354b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29660_0 .net8 "VNB", 0 0, L_00000000040354b0;  1 drivers, strength-aware
+L_0000000004035520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2aba0_0 .net8 "VPB", 0 0, L_0000000004035520;  1 drivers, strength-aware
+L_0000000004034720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a6a0_0 .net8 "VPWR", 0 0, L_0000000004034720;  1 drivers, strength-aware
+v0000000003b2a7e0_0 .net "Y", 0 0, L_000000000413e300;  alias, 1 drivers
+S_0000000003b5b010 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b5ea90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413e450 .functor NOT 1, L_000000000413ca10, C4<0>, C4<0>, C4<0>;
+L_000000000413e300 .functor BUF 1, L_000000000413e450, C4<0>, C4<0>, C4<0>;
+v0000000003b2ab00_0 .net "A", 0 0, L_000000000413ca10;  alias, 1 drivers
+L_0000000004034560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28940_0 .net8 "VGND", 0 0, L_0000000004034560;  1 drivers, strength-aware
+L_0000000004034800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b29e80_0 .net8 "VNB", 0 0, L_0000000004034800;  1 drivers, strength-aware
+L_0000000004034f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2a600_0 .net8 "VPB", 0 0, L_0000000004034f00;  1 drivers, strength-aware
+L_0000000004034f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ac40_0 .net8 "VPWR", 0 0, L_0000000004034f70;  1 drivers, strength-aware
+v0000000003b289e0_0 .net "Y", 0 0, L_000000000413e300;  alias, 1 drivers
+v0000000003b29160_0 .net "not0_out_Y", 0 0, L_000000000413e450;  1 drivers
+S_0000000003b5b310 .scope module, "_0830_" "sky130_fd_sc_hd__o22a_2" 3 2298, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b2d800_0 .net "A1", 0 0, L_000000000413be40;  alias, 1 drivers
+v0000000003b2b140_0 .net "A2", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003b2d8a0_0 .net "B1", 0 0, L_000000000413d730;  alias, 1 drivers
+v0000000003b2b1e0_0 .net "B2", 0 0, L_000000000413e300;  alias, 1 drivers
+L_0000000004034a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ce00_0 .net8 "VGND", 0 0, L_0000000004034a30;  1 drivers, strength-aware
+L_0000000004034d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b280_0 .net8 "VNB", 0 0, L_0000000004034d40;  1 drivers, strength-aware
+L_0000000004034e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b460_0 .net8 "VPB", 0 0, L_0000000004034e90;  1 drivers, strength-aware
+L_0000000004036010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c540_0 .net8 "VPWR", 0 0, L_0000000004036010;  1 drivers, strength-aware
+v0000000003b2cc20_0 .net "X", 0 0, L_000000000413db20;  alias, 1 drivers
+S_0000000003b5c210 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000003b5b310;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413d9d0 .functor OR 1, L_000000000413ca10, L_000000000413be40, C4<0>, C4<0>;
+L_000000000413ddc0 .functor OR 1, L_000000000413e300, L_000000000413d730, C4<0>, C4<0>;
+L_000000000413dff0 .functor AND 1, L_000000000413d9d0, L_000000000413ddc0, C4<1>, C4<1>;
+L_000000000413db20 .functor BUF 1, L_000000000413dff0, C4<0>, C4<0>, C4<0>;
+v0000000003b29200_0 .net "A1", 0 0, L_000000000413be40;  alias, 1 drivers
+v0000000003b292a0_0 .net "A2", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003b29f20_0 .net "B1", 0 0, L_000000000413d730;  alias, 1 drivers
+v0000000003b29fc0_0 .net "B2", 0 0, L_000000000413e300;  alias, 1 drivers
+L_0000000004037190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28c60_0 .net8 "VGND", 0 0, L_0000000004037190;  1 drivers, strength-aware
+L_00000000040369b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b28b20_0 .net8 "VNB", 0 0, L_00000000040369b0;  1 drivers, strength-aware
+L_0000000004036f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b295c0_0 .net8 "VPB", 0 0, L_0000000004036f60;  1 drivers, strength-aware
+L_0000000004036160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b29700_0 .net8 "VPWR", 0 0, L_0000000004036160;  1 drivers, strength-aware
+v0000000003b2cae0_0 .net "X", 0 0, L_000000000413db20;  alias, 1 drivers
+v0000000003b2b3c0_0 .net "and0_out_X", 0 0, L_000000000413dff0;  1 drivers
+v0000000003b2bdc0_0 .net "or0_out", 0 0, L_000000000413d9d0;  1 drivers
+v0000000003b2d620_0 .net "or1_out", 0 0, L_000000000413ddc0;  1 drivers
+S_0000000003b5b790 .scope module, "_0831_" "sky130_fd_sc_hd__or2_2" 3 2305, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b2cb80_0 .net "A", 0 0, L_000000000413bd60;  alias, 1 drivers
+v0000000003b2c9a0_0 .net "B", 0 0, L_000000000413db20;  alias, 1 drivers
+L_0000000004035fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b500_0 .net8 "VGND", 0 0, L_0000000004035fa0;  1 drivers, strength-aware
+L_0000000004036e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2baa0_0 .net8 "VNB", 0 0, L_0000000004036e80;  1 drivers, strength-aware
+L_0000000004035ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b820_0 .net8 "VPB", 0 0, L_0000000004035ad0;  1 drivers, strength-aware
+L_0000000004036400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b5a0_0 .net8 "VPWR", 0 0, L_0000000004036400;  1 drivers, strength-aware
+v0000000003b2ccc0_0 .net "X", 0 0, L_000000000413d880;  alias, 1 drivers
+S_0000000003b5a890 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5b790;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413e370 .functor OR 1, L_000000000413db20, L_000000000413bd60, C4<0>, C4<0>;
+L_000000000413d880 .functor BUF 1, L_000000000413e370, C4<0>, C4<0>, C4<0>;
+v0000000003b2d6c0_0 .net "A", 0 0, L_000000000413bd60;  alias, 1 drivers
+v0000000003b2d260_0 .net "B", 0 0, L_000000000413db20;  alias, 1 drivers
+L_0000000004037040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b320_0 .net8 "VGND", 0 0, L_0000000004037040;  1 drivers, strength-aware
+L_00000000040360f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2cfe0_0 .net8 "VNB", 0 0, L_00000000040360f0;  1 drivers, strength-aware
+L_00000000040362b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2cd60_0 .net8 "VPB", 0 0, L_00000000040362b0;  1 drivers, strength-aware
+L_0000000004036a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ca40_0 .net8 "VPWR", 0 0, L_0000000004036a20;  1 drivers, strength-aware
+v0000000003b2cea0_0 .net "X", 0 0, L_000000000413d880;  alias, 1 drivers
+v0000000003b2d4e0_0 .net "or0_out_X", 0 0, L_000000000413e370;  1 drivers
+S_0000000003b5da10 .scope module, "_0832_" "sky130_fd_sc_hd__a21boi_2" 3 2310, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b2d300_0 .net "A1", 0 0, L_000000000413bd60;  alias, 1 drivers
+v0000000003b2be60_0 .net "A2", 0 0, L_000000000413db20;  alias, 1 drivers
+v0000000003b2d3a0_0 .net "B1_N", 0 0, L_000000000413d880;  alias, 1 drivers
+L_0000000004035bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b8c0_0 .net8 "VGND", 0 0, L_0000000004035bb0;  1 drivers, strength-aware
+L_0000000004035c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d440_0 .net8 "VNB", 0 0, L_0000000004035c20;  1 drivers, strength-aware
+L_0000000004036630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2b780_0 .net8 "VPB", 0 0, L_0000000004036630;  1 drivers, strength-aware
+L_0000000004036fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c400_0 .net8 "VPWR", 0 0, L_0000000004036fd0;  1 drivers, strength-aware
+v0000000003b2b960_0 .net "Y", 0 0, L_000000000413da40;  alias, 1 drivers
+S_0000000003b5e310 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b5da10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413e060 .functor NOT 1, L_000000000413d880, C4<0>, C4<0>, C4<0>;
+L_000000000413d6c0 .functor AND 1, L_000000000413bd60, L_000000000413db20, C4<1>, C4<1>;
+L_000000000413e290 .functor NOR 1, L_000000000413e060, L_000000000413d6c0, C4<0>, C4<0>;
+L_000000000413da40 .functor BUF 1, L_000000000413e290, C4<0>, C4<0>, C4<0>;
+v0000000003b2cf40_0 .net "A1", 0 0, L_000000000413bd60;  alias, 1 drivers
+v0000000003b2bd20_0 .net "A2", 0 0, L_000000000413db20;  alias, 1 drivers
+v0000000003b2c5e0_0 .net "B1_N", 0 0, L_000000000413d880;  alias, 1 drivers
+L_0000000004036be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c360_0 .net8 "VGND", 0 0, L_0000000004036be0;  1 drivers, strength-aware
+L_00000000040373c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d080_0 .net8 "VNB", 0 0, L_00000000040373c0;  1 drivers, strength-aware
+L_0000000004036cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d120_0 .net8 "VPB", 0 0, L_0000000004036cc0;  1 drivers, strength-aware
+L_00000000040365c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d1c0_0 .net8 "VPWR", 0 0, L_00000000040365c0;  1 drivers, strength-aware
+v0000000003b2d580_0 .net "Y", 0 0, L_000000000413da40;  alias, 1 drivers
+v0000000003b2b640_0 .net "and0_out", 0 0, L_000000000413d6c0;  1 drivers
+v0000000003b2c900_0 .net "b", 0 0, L_000000000413e060;  1 drivers
+v0000000003b2b6e0_0 .net "nor0_out_Y", 0 0, L_000000000413e290;  1 drivers
+S_0000000003b5ae90 .scope module, "_0833_" "sky130_fd_sc_hd__or2_2" 3 2316, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b2c0e0_0 .net "A", 0 0, L_0000000004134190;  alias, 1 drivers
+v0000000003b2c180_0 .net "B", 0 0, L_0000000004135f50;  alias, 1 drivers
+L_0000000004036080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c220_0 .net8 "VGND", 0 0, L_0000000004036080;  1 drivers, strength-aware
+L_00000000040361d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c720_0 .net8 "VNB", 0 0, L_00000000040361d0;  1 drivers, strength-aware
+L_0000000004035980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c2c0_0 .net8 "VPB", 0 0, L_0000000004035980;  1 drivers, strength-aware
+L_0000000004036240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2c4a0_0 .net8 "VPWR", 0 0, L_0000000004036240;  1 drivers, strength-aware
+v0000000003b2c680_0 .net "X", 0 0, L_000000000413d7a0;  alias, 1 drivers
+S_0000000003b59f90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5ae90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413e0d0 .functor OR 1, L_0000000004135f50, L_0000000004134190, C4<0>, C4<0>;
+L_000000000413d7a0 .functor BUF 1, L_000000000413e0d0, C4<0>, C4<0>, C4<0>;
+v0000000003b2ba00_0 .net "A", 0 0, L_0000000004134190;  alias, 1 drivers
+v0000000003b2c040_0 .net "B", 0 0, L_0000000004135f50;  alias, 1 drivers
+L_0000000004035f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d760_0 .net8 "VGND", 0 0, L_0000000004035f30;  1 drivers, strength-aware
+L_00000000040370b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2bb40_0 .net8 "VNB", 0 0, L_00000000040370b0;  1 drivers, strength-aware
+L_0000000004036b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2bbe0_0 .net8 "VPB", 0 0, L_0000000004036b00;  1 drivers, strength-aware
+L_0000000004036320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2bf00_0 .net8 "VPWR", 0 0, L_0000000004036320;  1 drivers, strength-aware
+v0000000003b2bc80_0 .net "X", 0 0, L_000000000413d7a0;  alias, 1 drivers
+v0000000003b2bfa0_0 .net "or0_out_X", 0 0, L_000000000413e0d0;  1 drivers
+S_0000000003b5b910 .scope module, "_0834_" "sky130_fd_sc_hd__o21ai_2" 3 2321, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b2ef20_0 .net "A1", 0 0, L_0000000004134190;  alias, 1 drivers
+v0000000003b2de40_0 .net "A2", 0 0, L_0000000004136b20;  alias, 1 drivers
+v0000000003b2fc40_0 .net "B1", 0 0, L_0000000004136ab0;  alias, 1 drivers
+L_0000000004036ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f100_0 .net8 "VGND", 0 0, L_0000000004036ef0;  1 drivers, strength-aware
+L_0000000004036390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2dbc0_0 .net8 "VNB", 0 0, L_0000000004036390;  1 drivers, strength-aware
+L_0000000004036a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f560_0 .net8 "VPB", 0 0, L_0000000004036a90;  1 drivers, strength-aware
+L_0000000004035ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2fba0_0 .net8 "VPWR", 0 0, L_0000000004035ec0;  1 drivers, strength-aware
+v0000000003b2e840_0 .net "Y", 0 0, L_000000000413e6f0;  alias, 1 drivers
+S_0000000003b5de90 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b5b910;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413e3e0 .functor OR 1, L_0000000004136b20, L_0000000004134190, C4<0>, C4<0>;
+L_000000000413de30 .functor NAND 1, L_0000000004136ab0, L_000000000413e3e0, C4<1>, C4<1>;
+L_000000000413e6f0 .functor BUF 1, L_000000000413de30, C4<0>, C4<0>, C4<0>;
+v0000000003b2c7c0_0 .net "A1", 0 0, L_0000000004134190;  alias, 1 drivers
+v0000000003b2c860_0 .net "A2", 0 0, L_0000000004136b20;  alias, 1 drivers
+v0000000003b2e7a0_0 .net "B1", 0 0, L_0000000004136ab0;  alias, 1 drivers
+L_0000000004035de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2dda0_0 .net8 "VGND", 0 0, L_0000000004035de0;  1 drivers, strength-aware
+L_0000000004036470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2dc60_0 .net8 "VNB", 0 0, L_0000000004036470;  1 drivers, strength-aware
+L_0000000004035c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2fec0_0 .net8 "VPB", 0 0, L_0000000004035c90;  1 drivers, strength-aware
+L_00000000040364e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e520_0 .net8 "VPWR", 0 0, L_00000000040364e0;  1 drivers, strength-aware
+v0000000003b2dd00_0 .net "Y", 0 0, L_000000000413e6f0;  alias, 1 drivers
+v0000000003b2f880_0 .net "nand0_out_Y", 0 0, L_000000000413de30;  1 drivers
+v0000000003b2ede0_0 .net "or0_out", 0 0, L_000000000413e3e0;  1 drivers
+S_0000000003b59090 .scope module, "_0835_" "sky130_fd_sc_hd__inv_2" 3 2327, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b2fce0_0 .net "A", 0 0, L_000000000413e6f0;  alias, 1 drivers
+L_0000000004036b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ff60_0 .net8 "VGND", 0 0, L_0000000004036b70;  1 drivers, strength-aware
+L_0000000004037350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2fa60_0 .net8 "VNB", 0 0, L_0000000004037350;  1 drivers, strength-aware
+L_0000000004037120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2da80_0 .net8 "VPB", 0 0, L_0000000004037120;  1 drivers, strength-aware
+L_0000000004035b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f600_0 .net8 "VPWR", 0 0, L_0000000004035b40;  1 drivers, strength-aware
+v0000000003b2f6a0_0 .net "Y", 0 0, L_000000000413ef40;  alias, 1 drivers
+S_0000000003b59210 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b59090;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413e140 .functor NOT 1, L_000000000413e6f0, C4<0>, C4<0>, C4<0>;
+L_000000000413ef40 .functor BUF 1, L_000000000413e140, C4<0>, C4<0>, C4<0>;
+v0000000003b2e480_0 .net "A", 0 0, L_000000000413e6f0;  alias, 1 drivers
+L_0000000004037200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ed40_0 .net8 "VGND", 0 0, L_0000000004037200;  1 drivers, strength-aware
+L_00000000040358a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ec00_0 .net8 "VNB", 0 0, L_00000000040358a0;  1 drivers, strength-aware
+L_0000000004036550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e160_0 .net8 "VPB", 0 0, L_0000000004036550;  1 drivers, strength-aware
+L_0000000004036d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e5c0_0 .net8 "VPWR", 0 0, L_0000000004036d30;  1 drivers, strength-aware
+v0000000003b2e8e0_0 .net "Y", 0 0, L_000000000413ef40;  alias, 1 drivers
+v0000000003b2dee0_0 .net "not0_out_Y", 0 0, L_000000000413e140;  1 drivers
+S_0000000003b5db90 .scope module, "_0836_" "sky130_fd_sc_hd__o21a_2" 3 2331, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b30000_0 .net "A1", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003b2e0c0_0 .net "A2", 0 0, L_000000000413d7a0;  alias, 1 drivers
+v0000000003b2d940_0 .net "B1", 0 0, L_000000000413ef40;  alias, 1 drivers
+L_0000000004035a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ea20_0 .net8 "VGND", 0 0, L_0000000004035a60;  1 drivers, strength-aware
+L_00000000040366a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2d9e0_0 .net8 "VNB", 0 0, L_00000000040366a0;  1 drivers, strength-aware
+L_0000000004036710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2db20_0 .net8 "VPB", 0 0, L_0000000004036710;  1 drivers, strength-aware
+L_0000000004036780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f2e0_0 .net8 "VPWR", 0 0, L_0000000004036780;  1 drivers, strength-aware
+v0000000003b2e700_0 .net "X", 0 0, L_000000000413e1b0;  alias, 1 drivers
+S_0000000003b5a290 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003b5db90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413dea0 .functor OR 1, L_000000000413d7a0, L_00000000041374c0, C4<0>, C4<0>;
+L_000000000413eae0 .functor AND 1, L_000000000413dea0, L_000000000413ef40, C4<1>, C4<1>;
+L_000000000413e1b0 .functor BUF 1, L_000000000413eae0, C4<0>, C4<0>, C4<0>;
+v0000000003b2df80_0 .net "A1", 0 0, L_00000000041374c0;  alias, 1 drivers
+v0000000003b2e980_0 .net "A2", 0 0, L_000000000413d7a0;  alias, 1 drivers
+v0000000003b2fd80_0 .net "B1", 0 0, L_000000000413ef40;  alias, 1 drivers
+L_0000000004035d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e020_0 .net8 "VGND", 0 0, L_0000000004035d00;  1 drivers, strength-aware
+L_0000000004036c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f240_0 .net8 "VNB", 0 0, L_0000000004036c50;  1 drivers, strength-aware
+L_00000000040367f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e660_0 .net8 "VPB", 0 0, L_00000000040367f0;  1 drivers, strength-aware
+L_0000000004035910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b300a0_0 .net8 "VPWR", 0 0, L_0000000004035910;  1 drivers, strength-aware
+v0000000003b2fe20_0 .net "X", 0 0, L_000000000413e1b0;  alias, 1 drivers
+v0000000003b2eac0_0 .net "and0_out_X", 0 0, L_000000000413eae0;  1 drivers
+v0000000003b2f740_0 .net "or0_out", 0 0, L_000000000413dea0;  1 drivers
+S_0000000003b5ba90 .scope module, "_0837_" "sky130_fd_sc_hd__or2_2" 3 2337, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b2f060_0 .net "A", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003b2f380_0 .net "B", 0 0, L_0000000004133780;  alias, 1 drivers
+L_0000000004035d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2efc0_0 .net8 "VGND", 0 0, L_0000000004035d70;  1 drivers, strength-aware
+L_0000000004037270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f1a0_0 .net8 "VNB", 0 0, L_0000000004037270;  1 drivers, strength-aware
+L_00000000040372e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f420_0 .net8 "VPB", 0 0, L_00000000040372e0;  1 drivers, strength-aware
+L_00000000040359f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f4c0_0 .net8 "VPWR", 0 0, L_00000000040359f0;  1 drivers, strength-aware
+v0000000003b2f7e0_0 .net "X", 0 0, L_000000000413d810;  alias, 1 drivers
+S_0000000003b5cf90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5ba90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413e990 .functor OR 1, L_0000000004133780, L_0000000004136c00, C4<0>, C4<0>;
+L_000000000413d810 .functor BUF 1, L_000000000413e990, C4<0>, C4<0>, C4<0>;
+v0000000003b2e200_0 .net "A", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003b2e2a0_0 .net "B", 0 0, L_0000000004133780;  alias, 1 drivers
+L_0000000004035e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e340_0 .net8 "VGND", 0 0, L_0000000004035e50;  1 drivers, strength-aware
+L_0000000004036860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b2e3e0_0 .net8 "VNB", 0 0, L_0000000004036860;  1 drivers, strength-aware
+L_00000000040368d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2f920_0 .net8 "VPB", 0 0, L_00000000040368d0;  1 drivers, strength-aware
+L_0000000004036da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b2ee80_0 .net8 "VPWR", 0 0, L_0000000004036da0;  1 drivers, strength-aware
+v0000000003b2eb60_0 .net "X", 0 0, L_000000000413d810;  alias, 1 drivers
+v0000000003b2eca0_0 .net "or0_out_X", 0 0, L_000000000413e990;  1 drivers
+S_0000000003b5bc10 .scope module, "_0838_" "sky130_fd_sc_hd__a2bb2oi_2" 3 2342, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b31d60_0 .net "A1_N", 0 0, L_000000000413e1b0;  alias, 1 drivers
+v0000000003b31a40_0 .net "A2_N", 0 0, L_000000000413d810;  alias, 1 drivers
+v0000000003b32760_0 .net "B1", 0 0, L_000000000413e1b0;  alias, 1 drivers
+v0000000003b31ae0_0 .net "B2", 0 0, L_000000000413d810;  alias, 1 drivers
+L_0000000004036940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b312c0_0 .net8 "VGND", 0 0, L_0000000004036940;  1 drivers, strength-aware
+L_0000000004036e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b324e0_0 .net8 "VNB", 0 0, L_0000000004036e10;  1 drivers, strength-aware
+L_0000000004037430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b305a0_0 .net8 "VPB", 0 0, L_0000000004037430;  1 drivers, strength-aware
+L_0000000004038e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b30fa0_0 .net8 "VPWR", 0 0, L_0000000004038e70;  1 drivers, strength-aware
+v0000000003b31b80_0 .net "Y", 0 0, L_000000000413e610;  alias, 1 drivers
+S_0000000003b5e190 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003b5bc10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413eca0 .functor AND 1, L_000000000413e1b0, L_000000000413d810, C4<1>, C4<1>;
+L_000000000413e920 .functor NOR 1, L_000000000413e1b0, L_000000000413d810, C4<0>, C4<0>;
+L_000000000413ed80 .functor NOR 1, L_000000000413e920, L_000000000413eca0, C4<0>, C4<0>;
+L_000000000413e610 .functor BUF 1, L_000000000413ed80, C4<0>, C4<0>, C4<0>;
+v0000000003b2f9c0_0 .net "A1_N", 0 0, L_000000000413e1b0;  alias, 1 drivers
+v0000000003b2fb00_0 .net "A2_N", 0 0, L_000000000413d810;  alias, 1 drivers
+v0000000003b30be0_0 .net "B1", 0 0, L_000000000413e1b0;  alias, 1 drivers
+v0000000003b30960_0 .net "B2", 0 0, L_000000000413d810;  alias, 1 drivers
+L_00000000040374a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b310e0_0 .net8 "VGND", 0 0, L_00000000040374a0;  1 drivers, strength-aware
+L_00000000040377b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32620_0 .net8 "VNB", 0 0, L_00000000040377b0;  1 drivers, strength-aware
+L_0000000004038ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b30c80_0 .net8 "VPB", 0 0, L_0000000004038ee0;  1 drivers, strength-aware
+L_0000000004037970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b31fe0_0 .net8 "VPWR", 0 0, L_0000000004037970;  1 drivers, strength-aware
+v0000000003b321c0_0 .net "Y", 0 0, L_000000000413e610;  alias, 1 drivers
+v0000000003b31900_0 .net "and0_out", 0 0, L_000000000413eca0;  1 drivers
+v0000000003b30820_0 .net "nor0_out", 0 0, L_000000000413e920;  1 drivers
+v0000000003b32260_0 .net "nor1_out_Y", 0 0, L_000000000413ed80;  1 drivers
+S_0000000003b5bd90 .scope module, "_0839_" "sky130_fd_sc_hd__or2_2" 3 2349, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b31cc0_0 .net "A", 0 0, L_000000000413d880;  alias, 1 drivers
+v0000000003b31f40_0 .net "B", 0 0, L_000000000413e610;  alias, 1 drivers
+L_0000000004037ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32580_0 .net8 "VGND", 0 0, L_0000000004037ba0;  1 drivers, strength-aware
+L_0000000004038f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b326c0_0 .net8 "VNB", 0 0, L_0000000004038f50;  1 drivers, strength-aware
+L_0000000004038a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b319a0_0 .net8 "VPB", 0 0, L_0000000004038a80;  1 drivers, strength-aware
+L_0000000004037ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b31540_0 .net8 "VPWR", 0 0, L_0000000004037ac0;  1 drivers, strength-aware
+v0000000003b31040_0 .net "X", 0 0, L_000000000413dab0;  alias, 1 drivers
+S_0000000003b5e490 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5bd90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413df80 .functor OR 1, L_000000000413e610, L_000000000413d880, C4<0>, C4<0>;
+L_000000000413dab0 .functor BUF 1, L_000000000413df80, C4<0>, C4<0>, C4<0>;
+v0000000003b314a0_0 .net "A", 0 0, L_000000000413d880;  alias, 1 drivers
+v0000000003b31c20_0 .net "B", 0 0, L_000000000413e610;  alias, 1 drivers
+L_0000000004038a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b323a0_0 .net8 "VGND", 0 0, L_0000000004038a10;  1 drivers, strength-aware
+L_00000000040383f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b31ea0_0 .net8 "VNB", 0 0, L_00000000040383f0;  1 drivers, strength-aware
+L_0000000004038fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b31e00_0 .net8 "VPB", 0 0, L_0000000004038fc0;  1 drivers, strength-aware
+L_00000000040388c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b306e0_0 .net8 "VPWR", 0 0, L_00000000040388c0;  1 drivers, strength-aware
+v0000000003b315e0_0 .net "X", 0 0, L_000000000413dab0;  alias, 1 drivers
+v0000000003b30d20_0 .net "or0_out_X", 0 0, L_000000000413df80;  1 drivers
+S_0000000003b5bf10 .scope module, "_0840_" "sky130_fd_sc_hd__a21boi_2" 3 2354, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b32440_0 .net "A1", 0 0, L_000000000413d880;  alias, 1 drivers
+v0000000003b30460_0 .net "A2", 0 0, L_000000000413e610;  alias, 1 drivers
+v0000000003b30dc0_0 .net "B1_N", 0 0, L_000000000413dab0;  alias, 1 drivers
+L_0000000004038930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b328a0_0 .net8 "VGND", 0 0, L_0000000004038930;  1 drivers, strength-aware
+L_0000000004037820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b30e60_0 .net8 "VNB", 0 0, L_0000000004037820;  1 drivers, strength-aware
+L_0000000004037890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b30140_0 .net8 "VPB", 0 0, L_0000000004037890;  1 drivers, strength-aware
+L_0000000004038230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b317c0_0 .net8 "VPWR", 0 0, L_0000000004038230;  1 drivers, strength-aware
+v0000000003b31180_0 .net "Y", 0 0, L_000000000413e4c0;  alias, 1 drivers
+S_0000000003b5c090 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b5bf10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000413edf0 .functor NOT 1, L_000000000413dab0, C4<0>, C4<0>, C4<0>;
+L_000000000413d8f0 .functor AND 1, L_000000000413d880, L_000000000413e610, C4<1>, C4<1>;
+L_000000000413ea00 .functor NOR 1, L_000000000413edf0, L_000000000413d8f0, C4<0>, C4<0>;
+L_000000000413e4c0 .functor BUF 1, L_000000000413ea00, C4<0>, C4<0>, C4<0>;
+v0000000003b303c0_0 .net "A1", 0 0, L_000000000413d880;  alias, 1 drivers
+v0000000003b31360_0 .net "A2", 0 0, L_000000000413e610;  alias, 1 drivers
+v0000000003b30b40_0 .net "B1_N", 0 0, L_000000000413dab0;  alias, 1 drivers
+L_0000000004038b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b30640_0 .net8 "VGND", 0 0, L_0000000004038b60;  1 drivers, strength-aware
+L_00000000040387e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32080_0 .net8 "VNB", 0 0, L_00000000040387e0;  1 drivers, strength-aware
+L_0000000004039030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b31680_0 .net8 "VPB", 0 0, L_0000000004039030;  1 drivers, strength-aware
+L_00000000040389a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b32120_0 .net8 "VPWR", 0 0, L_00000000040389a0;  1 drivers, strength-aware
+v0000000003b32300_0 .net "Y", 0 0, L_000000000413e4c0;  alias, 1 drivers
+v0000000003b31400_0 .net "and0_out", 0 0, L_000000000413d8f0;  1 drivers
+v0000000003b31720_0 .net "b", 0 0, L_000000000413edf0;  1 drivers
+v0000000003b32800_0 .net "nor0_out_Y", 0 0, L_000000000413ea00;  1 drivers
+S_0000000003b5e610 .scope module, "_0841_" "sky130_fd_sc_hd__inv_2" 3 2360, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b30780_0 .net "A", 0 0, L_0000000004133b00;  alias, 1 drivers
+L_00000000040381c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b308c0_0 .net8 "VGND", 0 0, L_00000000040381c0;  1 drivers, strength-aware
+L_0000000004037c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b30aa0_0 .net8 "VNB", 0 0, L_0000000004037c80;  1 drivers, strength-aware
+L_0000000004037c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b31220_0 .net8 "VPB", 0 0, L_0000000004037c10;  1 drivers, strength-aware
+L_0000000004037580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34240_0 .net8 "VPWR", 0 0, L_0000000004037580;  1 drivers, strength-aware
+v0000000003b34f60_0 .net "Y", 0 0, L_000000000413e530;  alias, 1 drivers
+S_0000000003b59810 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b5e610;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413eed0 .functor NOT 1, L_0000000004133b00, C4<0>, C4<0>, C4<0>;
+L_000000000413e530 .functor BUF 1, L_000000000413eed0, C4<0>, C4<0>, C4<0>;
+v0000000003b31860_0 .net "A", 0 0, L_0000000004133b00;  alias, 1 drivers
+L_0000000004037dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b30a00_0 .net8 "VGND", 0 0, L_0000000004037dd0;  1 drivers, strength-aware
+L_0000000004037b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b301e0_0 .net8 "VNB", 0 0, L_0000000004037b30;  1 drivers, strength-aware
+L_0000000004038bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b30f00_0 .net8 "VPB", 0 0, L_0000000004038bd0;  1 drivers, strength-aware
+L_0000000004038700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b30280_0 .net8 "VPWR", 0 0, L_0000000004038700;  1 drivers, strength-aware
+v0000000003b30320_0 .net "Y", 0 0, L_000000000413e530;  alias, 1 drivers
+v0000000003b30500_0 .net "not0_out_Y", 0 0, L_000000000413eed0;  1 drivers
+S_0000000003b5e910 .scope module, "_0842_" "sky130_fd_sc_hd__or2_2" 3 2364, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b333e0_0 .net "A", 0 0, L_000000000413e530;  alias, 1 drivers
+v0000000003b33340_0 .net "B", 0 0, L_0000000004132c20;  alias, 1 drivers
+L_0000000004037f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b344c0_0 .net8 "VGND", 0 0, L_0000000004037f20;  1 drivers, strength-aware
+L_0000000004038af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b34560_0 .net8 "VNB", 0 0, L_0000000004038af0;  1 drivers, strength-aware
+L_0000000004037f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b349c0_0 .net8 "VPB", 0 0, L_0000000004037f90;  1 drivers, strength-aware
+L_00000000040385b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34a60_0 .net8 "VPWR", 0 0, L_00000000040385b0;  1 drivers, strength-aware
+v0000000003b32c60_0 .net "X", 0 0, L_000000000413d650;  alias, 1 drivers
+S_0000000003b5c390 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5e910;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413df10 .functor OR 1, L_0000000004132c20, L_000000000413e530, C4<0>, C4<0>;
+L_000000000413d650 .functor BUF 1, L_000000000413df10, C4<0>, C4<0>, C4<0>;
+v0000000003b341a0_0 .net "A", 0 0, L_000000000413e530;  alias, 1 drivers
+v0000000003b34880_0 .net "B", 0 0, L_0000000004132c20;  alias, 1 drivers
+L_0000000004037cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33020_0 .net8 "VGND", 0 0, L_0000000004037cf0;  1 drivers, strength-aware
+L_00000000040379e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b337a0_0 .net8 "VNB", 0 0, L_00000000040379e0;  1 drivers, strength-aware
+L_0000000004037d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34920_0 .net8 "VPB", 0 0, L_0000000004037d60;  1 drivers, strength-aware
+L_0000000004037900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33c00_0 .net8 "VPWR", 0 0, L_0000000004037900;  1 drivers, strength-aware
+v0000000003b33ca0_0 .net "X", 0 0, L_000000000413d650;  alias, 1 drivers
+v0000000003b347e0_0 .net "or0_out_X", 0 0, L_000000000413df10;  1 drivers
+S_0000000003b5ec10 .scope module, "_0843_" "sky130_fd_sc_hd__o21ai_2" 3 2369, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b33de0_0 .net "A1", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003b32e40_0 .net "A2", 0 0, L_000000000413bc10;  alias, 1 drivers
+v0000000003b338e0_0 .net "B1", 0 0, L_0000000004134890;  alias, 1 drivers
+L_0000000004037e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32bc0_0 .net8 "VGND", 0 0, L_0000000004037e40;  1 drivers, strength-aware
+L_0000000004038690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32d00_0 .net8 "VNB", 0 0, L_0000000004038690;  1 drivers, strength-aware
+L_0000000004037510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b32ee0_0 .net8 "VPB", 0 0, L_0000000004037510;  1 drivers, strength-aware
+L_0000000004038cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34ce0_0 .net8 "VPWR", 0 0, L_0000000004038cb0;  1 drivers, strength-aware
+v0000000003b34ba0_0 .net "Y", 0 0, L_000000000413e220;  alias, 1 drivers
+S_0000000003b59510 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b5ec10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413d570 .functor OR 1, L_000000000413bc10, L_0000000004132440, C4<0>, C4<0>;
+L_000000000413e7d0 .functor NAND 1, L_0000000004134890, L_000000000413d570, C4<1>, C4<1>;
+L_000000000413e220 .functor BUF 1, L_000000000413e7d0, C4<0>, C4<0>, C4<0>;
+v0000000003b32940_0 .net "A1", 0 0, L_0000000004132440;  alias, 1 drivers
+v0000000003b342e0_0 .net "A2", 0 0, L_000000000413bc10;  alias, 1 drivers
+v0000000003b34740_0 .net "B1", 0 0, L_0000000004134890;  alias, 1 drivers
+L_0000000004037740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b34100_0 .net8 "VGND", 0 0, L_0000000004037740;  1 drivers, strength-aware
+L_0000000004038d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33840_0 .net8 "VNB", 0 0, L_0000000004038d90;  1 drivers, strength-aware
+L_00000000040375f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34b00_0 .net8 "VPB", 0 0, L_00000000040375f0;  1 drivers, strength-aware
+L_00000000040380e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35000_0 .net8 "VPWR", 0 0, L_00000000040380e0;  1 drivers, strength-aware
+v0000000003b33d40_0 .net "Y", 0 0, L_000000000413e220;  alias, 1 drivers
+v0000000003b346a0_0 .net "nand0_out_Y", 0 0, L_000000000413e7d0;  1 drivers
+v0000000003b32da0_0 .net "or0_out", 0 0, L_000000000413d570;  1 drivers
+S_0000000003b5c510 .scope module, "_0844_" "sky130_fd_sc_hd__or2_2" 3 2375, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b32a80_0 .net "A", 0 0, L_0000000004133080;  alias, 1 drivers
+v0000000003b34c40_0 .net "B", 0 0, L_000000000413d810;  alias, 1 drivers
+L_0000000004038c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b34d80_0 .net8 "VGND", 0 0, L_0000000004038c40;  1 drivers, strength-aware
+L_0000000004037660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b34ec0_0 .net8 "VNB", 0 0, L_0000000004037660;  1 drivers, strength-aware
+L_00000000040382a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33a20_0 .net8 "VPB", 0 0, L_00000000040382a0;  1 drivers, strength-aware
+L_0000000004038150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33ac0_0 .net8 "VPWR", 0 0, L_0000000004038150;  1 drivers, strength-aware
+v0000000003b33e80_0 .net "X", 0 0, L_000000000413e8b0;  alias, 1 drivers
+S_0000000003b5ed90 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5c510;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413e5a0 .functor OR 1, L_000000000413d810, L_0000000004133080, C4<0>, C4<0>;
+L_000000000413e8b0 .functor BUF 1, L_000000000413e5a0, C4<0>, C4<0>, C4<0>;
+v0000000003b34380_0 .net "A", 0 0, L_0000000004133080;  alias, 1 drivers
+v0000000003b34420_0 .net "B", 0 0, L_000000000413d810;  alias, 1 drivers
+L_0000000004037eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b34600_0 .net8 "VGND", 0 0, L_0000000004037eb0;  1 drivers, strength-aware
+L_0000000004037a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33f20_0 .net8 "VNB", 0 0, L_0000000004037a50;  1 drivers, strength-aware
+L_0000000004038620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b350a0_0 .net8 "VPB", 0 0, L_0000000004038620;  1 drivers, strength-aware
+L_0000000004038000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33980_0 .net8 "VPWR", 0 0, L_0000000004038000;  1 drivers, strength-aware
+v0000000003b329e0_0 .net "X", 0 0, L_000000000413e8b0;  alias, 1 drivers
+v0000000003b34e20_0 .net "or0_out_X", 0 0, L_000000000413e5a0;  1 drivers
+S_0000000003b5ef10 .scope module, "_0845_" "sky130_fd_sc_hd__or2_2" 3 2380, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b33520_0 .net "A", 0 0, L_000000000413bf90;  alias, 1 drivers
+v0000000003b335c0_0 .net "B", 0 0, L_000000000413e8b0;  alias, 1 drivers
+L_00000000040376d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33660_0 .net8 "VGND", 0 0, L_00000000040376d0;  1 drivers, strength-aware
+L_0000000004038070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33fc0_0 .net8 "VNB", 0 0, L_0000000004038070;  1 drivers, strength-aware
+L_0000000004038d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33700_0 .net8 "VPB", 0 0, L_0000000004038d20;  1 drivers, strength-aware
+L_0000000004038e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b34060_0 .net8 "VPWR", 0 0, L_0000000004038e00;  1 drivers, strength-aware
+v0000000003b373a0_0 .net "X", 0 0, L_000000000413db90;  alias, 1 drivers
+S_0000000003b5c810 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5ef10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413efb0 .functor OR 1, L_000000000413e8b0, L_000000000413bf90, C4<0>, C4<0>;
+L_000000000413db90 .functor BUF 1, L_000000000413efb0, C4<0>, C4<0>, C4<0>;
+v0000000003b33b60_0 .net "A", 0 0, L_000000000413bf90;  alias, 1 drivers
+v0000000003b32b20_0 .net "B", 0 0, L_000000000413e8b0;  alias, 1 drivers
+L_0000000004038310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b32f80_0 .net8 "VGND", 0 0, L_0000000004038310;  1 drivers, strength-aware
+L_0000000004038380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b33480_0 .net8 "VNB", 0 0, L_0000000004038380;  1 drivers, strength-aware
+L_0000000004038460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b330c0_0 .net8 "VPB", 0 0, L_0000000004038460;  1 drivers, strength-aware
+L_00000000040384d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b33160_0 .net8 "VPWR", 0 0, L_00000000040384d0;  1 drivers, strength-aware
+v0000000003b33200_0 .net "X", 0 0, L_000000000413db90;  alias, 1 drivers
+v0000000003b332a0_0 .net "or0_out_X", 0 0, L_000000000413efb0;  1 drivers
+S_0000000003b5c990 .scope module, "_0846_" "sky130_fd_sc_hd__and2_2" 3 2385, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b35820_0 .net "A", 0 0, L_000000000413e220;  alias, 1 drivers
+v0000000003b36c20_0 .net "B", 0 0, L_000000000413db90;  alias, 1 drivers
+L_0000000004038850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b351e0_0 .net8 "VGND", 0 0, L_0000000004038850;  1 drivers, strength-aware
+L_0000000004038540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35500_0 .net8 "VNB", 0 0, L_0000000004038540;  1 drivers, strength-aware
+L_0000000004038770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b36b80_0 .net8 "VPB", 0 0, L_0000000004038770;  1 drivers, strength-aware
+L_000000000403a760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b36fe0_0 .net8 "VPWR", 0 0, L_000000000403a760;  1 drivers, strength-aware
+v0000000003b36cc0_0 .net "X", 0 0, L_000000000413e680;  alias, 1 drivers
+S_0000000003b5d110 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003b5c990;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413d960 .functor AND 1, L_000000000413e220, L_000000000413db90, C4<1>, C4<1>;
+L_000000000413e680 .functor BUF 1, L_000000000413d960, C4<0>, C4<0>, C4<0>;
+v0000000003b36720_0 .net "A", 0 0, L_000000000413e220;  alias, 1 drivers
+v0000000003b37080_0 .net "B", 0 0, L_000000000413db90;  alias, 1 drivers
+L_000000000403aa70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b36ae0_0 .net8 "VGND", 0 0, L_000000000403aa70;  1 drivers, strength-aware
+L_00000000040390a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b374e0_0 .net8 "VNB", 0 0, L_00000000040390a0;  1 drivers, strength-aware
+L_00000000040393b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b356e0_0 .net8 "VPB", 0 0, L_00000000040393b0;  1 drivers, strength-aware
+L_000000000403aae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35fa0_0 .net8 "VPWR", 0 0, L_000000000403aae0;  1 drivers, strength-aware
+v0000000003b36a40_0 .net "X", 0 0, L_000000000413e680;  alias, 1 drivers
+v0000000003b369a0_0 .net "and0_out_X", 0 0, L_000000000413d960;  1 drivers
+S_0000000003b5ff90 .scope module, "_0847_" "sky130_fd_sc_hd__a21oi_2" 3 2390, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b358c0_0 .net "A1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+v0000000003b371c0_0 .net "A2", 0 0, L_000000000413c700;  alias, 1 drivers
+v0000000003b37760_0 .net "B1", 0 0, L_000000000413e680;  alias, 1 drivers
+L_0000000004039570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b36400_0 .net8 "VGND", 0 0, L_0000000004039570;  1 drivers, strength-aware
+L_00000000040397a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b36ea0_0 .net8 "VNB", 0 0, L_00000000040397a0;  1 drivers, strength-aware
+L_000000000403ab50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35640_0 .net8 "VPB", 0 0, L_000000000403ab50;  1 drivers, strength-aware
+L_000000000403a680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35780_0 .net8 "VPWR", 0 0, L_000000000403a680;  1 drivers, strength-aware
+v0000000003b36f40_0 .net "Y", 0 0, L_000000000413d500;  alias, 1 drivers
+S_0000000003b5f810 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003b5ff90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413e760 .functor AND 1, L_000000000413c4d0, L_000000000413c700, C4<1>, C4<1>;
+L_000000000413e840 .functor NOR 1, L_000000000413e680, L_000000000413e760, C4<0>, C4<0>;
+L_000000000413d500 .functor BUF 1, L_000000000413e840, C4<0>, C4<0>, C4<0>;
+v0000000003b36360_0 .net "A1", 0 0, L_000000000413c4d0;  alias, 1 drivers
+v0000000003b36d60_0 .net "A2", 0 0, L_000000000413c700;  alias, 1 drivers
+v0000000003b36e00_0 .net "B1", 0 0, L_000000000413e680;  alias, 1 drivers
+L_00000000040396c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b355a0_0 .net8 "VGND", 0 0, L_00000000040396c0;  1 drivers, strength-aware
+L_000000000403a610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35c80_0 .net8 "VNB", 0 0, L_000000000403a610;  1 drivers, strength-aware
+L_0000000004039ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35320_0 .net8 "VPB", 0 0, L_0000000004039ff0;  1 drivers, strength-aware
+L_000000000403abc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b37120_0 .net8 "VPWR", 0 0, L_000000000403abc0;  1 drivers, strength-aware
+v0000000003b364a0_0 .net "Y", 0 0, L_000000000413d500;  alias, 1 drivers
+v0000000003b36040_0 .net "and0_out", 0 0, L_000000000413e760;  1 drivers
+v0000000003b36540_0 .net "nor0_out_Y", 0 0, L_000000000413e840;  1 drivers
+S_0000000003b60890 .scope module, "_0848_" "sky130_fd_sc_hd__o21ai_2" 3 2396, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b360e0_0 .net "A1", 0 0, L_000000000413c310;  alias, 1 drivers
+v0000000003b35140_0 .net "A2", 0 0, L_000000000413e8b0;  alias, 1 drivers
+v0000000003b376c0_0 .net "B1", 0 0, L_000000000413e220;  alias, 1 drivers
+L_0000000004039ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35280_0 .net8 "VGND", 0 0, L_0000000004039ab0;  1 drivers, strength-aware
+L_0000000004039c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35f00_0 .net8 "VNB", 0 0, L_0000000004039c70;  1 drivers, strength-aware
+L_000000000403a7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b37440_0 .net8 "VPB", 0 0, L_000000000403a7d0;  1 drivers, strength-aware
+L_000000000403ac30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35aa0_0 .net8 "VPWR", 0 0, L_000000000403ac30;  1 drivers, strength-aware
+v0000000003b353c0_0 .net "Y", 0 0, L_000000000413ebc0;  alias, 1 drivers
+S_0000000003b5f510 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b60890;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413ea70 .functor OR 1, L_000000000413e8b0, L_000000000413c310, C4<0>, C4<0>;
+L_000000000413eb50 .functor NAND 1, L_000000000413e220, L_000000000413ea70, C4<1>, C4<1>;
+L_000000000413ebc0 .functor BUF 1, L_000000000413eb50, C4<0>, C4<0>, C4<0>;
+v0000000003b37580_0 .net "A1", 0 0, L_000000000413c310;  alias, 1 drivers
+v0000000003b35960_0 .net "A2", 0 0, L_000000000413e8b0;  alias, 1 drivers
+v0000000003b37800_0 .net "B1", 0 0, L_000000000413e220;  alias, 1 drivers
+L_0000000004039110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b367c0_0 .net8 "VGND", 0 0, L_0000000004039110;  1 drivers, strength-aware
+L_0000000004039420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b37620_0 .net8 "VNB", 0 0, L_0000000004039420;  1 drivers, strength-aware
+L_0000000004039180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b362c0_0 .net8 "VPB", 0 0, L_0000000004039180;  1 drivers, strength-aware
+L_00000000040395e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b378a0_0 .net8 "VPWR", 0 0, L_00000000040395e0;  1 drivers, strength-aware
+v0000000003b37260_0 .net "Y", 0 0, L_000000000413ebc0;  alias, 1 drivers
+v0000000003b37300_0 .net "nand0_out_Y", 0 0, L_000000000413eb50;  1 drivers
+v0000000003b35a00_0 .net "or0_out", 0 0, L_000000000413ea70;  1 drivers
+S_0000000003b60710 .scope module, "_0849_" "sky130_fd_sc_hd__inv_2" 3 2402, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b36900_0 .net "A", 0 0, L_000000000413ebc0;  alias, 1 drivers
+L_0000000004039810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35e60_0 .net8 "VGND", 0 0, L_0000000004039810;  1 drivers, strength-aware
+L_00000000040391f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b36220_0 .net8 "VNB", 0 0, L_00000000040391f0;  1 drivers, strength-aware
+L_000000000403a6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b36680_0 .net8 "VPB", 0 0, L_000000000403a6f0;  1 drivers, strength-aware
+L_0000000004039730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b36860_0 .net8 "VPWR", 0 0, L_0000000004039730;  1 drivers, strength-aware
+v0000000003b37da0_0 .net "Y", 0 0, L_000000000413ed10;  alias, 1 drivers
+S_0000000003b61010 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b60710;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413ec30 .functor NOT 1, L_000000000413ebc0, C4<0>, C4<0>, C4<0>;
+L_000000000413ed10 .functor BUF 1, L_000000000413ec30, C4<0>, C4<0>, C4<0>;
+v0000000003b35b40_0 .net "A", 0 0, L_000000000413ebc0;  alias, 1 drivers
+L_000000000403a840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b35be0_0 .net8 "VGND", 0 0, L_000000000403a840;  1 drivers, strength-aware
+L_000000000403a060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b36180_0 .net8 "VNB", 0 0, L_000000000403a060;  1 drivers, strength-aware
+L_0000000004039260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b365e0_0 .net8 "VPB", 0 0, L_0000000004039260;  1 drivers, strength-aware
+L_000000000403a4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b35460_0 .net8 "VPWR", 0 0, L_000000000403a4c0;  1 drivers, strength-aware
+v0000000003b35d20_0 .net "Y", 0 0, L_000000000413ed10;  alias, 1 drivers
+v0000000003b35dc0_0 .net "not0_out_Y", 0 0, L_000000000413ec30;  1 drivers
+S_0000000003b60410 .scope module, "_0850_" "sky130_fd_sc_hd__o21ai_2" 3 2406, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b392e0_0 .net "A1", 0 0, L_000000000413d2d0;  alias, 1 drivers
+v0000000003b38980_0 .net "A2", 0 0, L_000000000413db90;  alias, 1 drivers
+v0000000003b38a20_0 .net "B1", 0 0, L_000000000413ed10;  alias, 1 drivers
+L_0000000004039490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b38200_0 .net8 "VGND", 0 0, L_0000000004039490;  1 drivers, strength-aware
+L_0000000004039500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b37ee0_0 .net8 "VNB", 0 0, L_0000000004039500;  1 drivers, strength-aware
+L_0000000004039e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b37a80_0 .net8 "VPB", 0 0, L_0000000004039e30;  1 drivers, strength-aware
+L_000000000403a8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b37b20_0 .net8 "VPWR", 0 0, L_000000000403a8b0;  1 drivers, strength-aware
+v0000000003b38700_0 .net "Y", 0 0, L_000000000413f090;  alias, 1 drivers
+S_0000000003b62b10 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b60410;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413f020 .functor OR 1, L_000000000413db90, L_000000000413d2d0, C4<0>, C4<0>;
+L_000000000413ee60 .functor NAND 1, L_000000000413ed10, L_000000000413f020, C4<1>, C4<1>;
+L_000000000413f090 .functor BUF 1, L_000000000413ee60, C4<0>, C4<0>, C4<0>;
+v0000000003b39560_0 .net "A1", 0 0, L_000000000413d2d0;  alias, 1 drivers
+v0000000003b39380_0 .net "A2", 0 0, L_000000000413db90;  alias, 1 drivers
+v0000000003b38160_0 .net "B1", 0 0, L_000000000413ed10;  alias, 1 drivers
+L_000000000403a3e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b37e40_0 .net8 "VGND", 0 0, L_000000000403a3e0;  1 drivers, strength-aware
+L_00000000040392d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b39f60_0 .net8 "VNB", 0 0, L_00000000040392d0;  1 drivers, strength-aware
+L_000000000403a530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b388e0_0 .net8 "VPB", 0 0, L_000000000403a530;  1 drivers, strength-aware
+L_0000000004039dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b37940_0 .net8 "VPWR", 0 0, L_0000000004039dc0;  1 drivers, strength-aware
+v0000000003b39ce0_0 .net "Y", 0 0, L_000000000413f090;  alias, 1 drivers
+v0000000003b39240_0 .net "nand0_out_Y", 0 0, L_000000000413ee60;  1 drivers
+v0000000003b379e0_0 .net "or0_out", 0 0, L_000000000413f020;  1 drivers
+S_0000000003b61190 .scope module, "_0851_" "sky130_fd_sc_hd__a21oi_2" 3 2412, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b38b60_0 .net "A1", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003b38ca0_0 .net "A2", 0 0, L_000000000413d500;  alias, 1 drivers
+v0000000003b39b00_0 .net "B1", 0 0, L_000000000413f090;  alias, 1 drivers
+L_0000000004039880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b394c0_0 .net8 "VGND", 0 0, L_0000000004039880;  1 drivers, strength-aware
+L_00000000040398f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b382a0_0 .net8 "VNB", 0 0, L_00000000040398f0;  1 drivers, strength-aware
+L_0000000004039340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b38d40_0 .net8 "VPB", 0 0, L_0000000004039340;  1 drivers, strength-aware
+L_00000000040399d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b38020_0 .net8 "VPWR", 0 0, L_00000000040399d0;  1 drivers, strength-aware
+v0000000003b38de0_0 .net "Y", 0 0, L_000000000413dc70;  alias, 1 drivers
+S_0000000003b60b90 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003b61190;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413d5e0 .functor AND 1, L_0000000004128110, L_000000000413d500, C4<1>, C4<1>;
+L_000000000413dc00 .functor NOR 1, L_000000000413f090, L_000000000413d5e0, C4<0>, C4<0>;
+L_000000000413dc70 .functor BUF 1, L_000000000413dc00, C4<0>, C4<0>, C4<0>;
+v0000000003b37f80_0 .net "A1", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003b39d80_0 .net "A2", 0 0, L_000000000413d500;  alias, 1 drivers
+v0000000003b37bc0_0 .net "B1", 0 0, L_000000000413f090;  alias, 1 drivers
+L_0000000004039960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b38840_0 .net8 "VGND", 0 0, L_0000000004039960;  1 drivers, strength-aware
+L_000000000403a920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b37c60_0 .net8 "VNB", 0 0, L_000000000403a920;  1 drivers, strength-aware
+L_000000000403a300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b38ac0_0 .net8 "VPB", 0 0, L_000000000403a300;  1 drivers, strength-aware
+L_0000000004039b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b39420_0 .net8 "VPWR", 0 0, L_0000000004039b20;  1 drivers, strength-aware
+v0000000003b38fc0_0 .net "Y", 0 0, L_000000000413dc70;  alias, 1 drivers
+v0000000003b38c00_0 .net "and0_out", 0 0, L_000000000413d5e0;  1 drivers
+v0000000003b37d00_0 .net "nor0_out_Y", 0 0, L_000000000413dc00;  1 drivers
+S_0000000003b61610 .scope module, "_0852_" "sky130_fd_sc_hd__inv_2" 3 2418, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b39ec0_0 .net "A", 0 0, L_000000000413d650;  alias, 1 drivers
+L_000000000403a990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b383e0_0 .net8 "VGND", 0 0, L_000000000403a990;  1 drivers, strength-aware
+L_0000000004039b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b38480_0 .net8 "VNB", 0 0, L_0000000004039b90;  1 drivers, strength-aware
+L_000000000403a1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b38f20_0 .net8 "VPB", 0 0, L_000000000403a1b0;  1 drivers, strength-aware
+L_0000000004039a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b38520_0 .net8 "VPWR", 0 0, L_0000000004039a40;  1 drivers, strength-aware
+v0000000003b385c0_0 .net "Y", 0 0, L_000000000413dd50;  alias, 1 drivers
+S_0000000003b62510 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b61610;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413dce0 .functor NOT 1, L_000000000413d650, C4<0>, C4<0>, C4<0>;
+L_000000000413dd50 .functor BUF 1, L_000000000413dce0, C4<0>, C4<0>, C4<0>;
+v0000000003b39c40_0 .net "A", 0 0, L_000000000413d650;  alias, 1 drivers
+L_0000000004039650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b39ba0_0 .net8 "VGND", 0 0, L_0000000004039650;  1 drivers, strength-aware
+L_0000000004039c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b39920_0 .net8 "VNB", 0 0, L_0000000004039c00;  1 drivers, strength-aware
+L_0000000004039ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b380c0_0 .net8 "VPB", 0 0, L_0000000004039ce0;  1 drivers, strength-aware
+L_0000000004039d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b39e20_0 .net8 "VPWR", 0 0, L_0000000004039d50;  1 drivers, strength-aware
+v0000000003b38340_0 .net "Y", 0 0, L_000000000413dd50;  alias, 1 drivers
+v0000000003b38e80_0 .net "not0_out_Y", 0 0, L_000000000413dce0;  1 drivers
+S_0000000003b60e90 .scope module, "_0853_" "sky130_fd_sc_hd__inv_2" 3 2422, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b39740_0 .net "A", 0 0, L_000000000413dc70;  alias, 1 drivers
+L_000000000403a290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b399c0_0 .net8 "VGND", 0 0, L_000000000403a290;  1 drivers, strength-aware
+L_0000000004039ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b397e0_0 .net8 "VNB", 0 0, L_0000000004039ea0;  1 drivers, strength-aware
+L_000000000403aa00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b39880_0 .net8 "VPB", 0 0, L_000000000403aa00;  1 drivers, strength-aware
+L_0000000004039f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b39a60_0 .net8 "VPWR", 0 0, L_0000000004039f10;  1 drivers, strength-aware
+v0000000003b9a0c0_0 .net "Y", 0 0, L_000000000413f330;  alias, 1 drivers
+S_0000000003b61790 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b60e90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413ff70 .functor NOT 1, L_000000000413dc70, C4<0>, C4<0>, C4<0>;
+L_000000000413f330 .functor BUF 1, L_000000000413ff70, C4<0>, C4<0>, C4<0>;
+v0000000003b38660_0 .net "A", 0 0, L_000000000413dc70;  alias, 1 drivers
+L_0000000004039f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b387a0_0 .net8 "VGND", 0 0, L_0000000004039f80;  1 drivers, strength-aware
+L_000000000403a0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b39060_0 .net8 "VNB", 0 0, L_000000000403a0d0;  1 drivers, strength-aware
+L_000000000403a140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b39100_0 .net8 "VPB", 0 0, L_000000000403a140;  1 drivers, strength-aware
+L_000000000403a5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b391a0_0 .net8 "VPWR", 0 0, L_000000000403a5a0;  1 drivers, strength-aware
+v0000000003b39600_0 .net "Y", 0 0, L_000000000413f330;  alias, 1 drivers
+v0000000003b396a0_0 .net "not0_out_Y", 0 0, L_000000000413ff70;  1 drivers
+S_0000000003b62990 .scope module, "_0854_" "sky130_fd_sc_hd__o22a_2" 3 2426, 4 50766 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b9b560_0 .net "A1", 0 0, L_000000000413d650;  alias, 1 drivers
+v0000000003b9b4c0_0 .net "A2", 0 0, L_000000000413dc70;  alias, 1 drivers
+v0000000003b9ad40_0 .net "B1", 0 0, L_000000000413dd50;  alias, 1 drivers
+v0000000003b9b240_0 .net "B2", 0 0, L_000000000413f330;  alias, 1 drivers
+L_000000000403a220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ade0_0 .net8 "VGND", 0 0, L_000000000403a220;  1 drivers, strength-aware
+L_000000000403a370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9bd80_0 .net8 "VNB", 0 0, L_000000000403a370;  1 drivers, strength-aware
+L_000000000403a450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9aac0_0 .net8 "VPB", 0 0, L_000000000403a450;  1 drivers, strength-aware
+L_000000000403ad80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9bce0_0 .net8 "VPWR", 0 0, L_000000000403ad80;  1 drivers, strength-aware
+v0000000003b99f80_0 .net "X", 0 0, L_0000000004140ad0;  alias, 1 drivers
+S_0000000003b5f390 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_0000000003b62990;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413f250 .functor OR 1, L_000000000413dc70, L_000000000413d650, C4<0>, C4<0>;
+L_000000000413f170 .functor OR 1, L_000000000413f330, L_000000000413dd50, C4<0>, C4<0>;
+L_000000000413f480 .functor AND 1, L_000000000413f250, L_000000000413f170, C4<1>, C4<1>;
+L_0000000004140ad0 .functor BUF 1, L_000000000413f480, C4<0>, C4<0>, C4<0>;
+v0000000003b9a340_0 .net "A1", 0 0, L_000000000413d650;  alias, 1 drivers
+v0000000003b99da0_0 .net "A2", 0 0, L_000000000413dc70;  alias, 1 drivers
+v0000000003b9a5c0_0 .net "B1", 0 0, L_000000000413dd50;  alias, 1 drivers
+v0000000003b9aa20_0 .net "B2", 0 0, L_000000000413f330;  alias, 1 drivers
+L_000000000403aca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a700_0 .net8 "VGND", 0 0, L_000000000403aca0;  1 drivers, strength-aware
+L_000000000403aed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b99bc0_0 .net8 "VNB", 0 0, L_000000000403aed0;  1 drivers, strength-aware
+L_000000000403adf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b99c60_0 .net8 "VPB", 0 0, L_000000000403adf0;  1 drivers, strength-aware
+L_000000000403ad10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a840_0 .net8 "VPWR", 0 0, L_000000000403ad10;  1 drivers, strength-aware
+v0000000003b99ee0_0 .net "X", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003b9b9c0_0 .net "and0_out_X", 0 0, L_000000000413f480;  1 drivers
+v0000000003b9bba0_0 .net "or0_out", 0 0, L_000000000413f250;  1 drivers
+v0000000003b9bec0_0 .net "or1_out", 0 0, L_000000000413f170;  1 drivers
+S_0000000003b5f690 .scope module, "_0855_" "sky130_fd_sc_hd__or2_2" 3 2433, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b9ab60_0 .net "A", 0 0, L_000000000413dab0;  alias, 1 drivers
+v0000000003b9b2e0_0 .net "B", 0 0, L_0000000004140ad0;  alias, 1 drivers
+L_000000000403af40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b7e0_0 .net8 "VGND", 0 0, L_000000000403af40;  1 drivers, strength-aware
+L_000000000403ae60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b380_0 .net8 "VNB", 0 0, L_000000000403ae60;  1 drivers, strength-aware
+L_0000000004047d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9be20_0 .net8 "VPB", 0 0, L_0000000004047d90;  1 drivers, strength-aware
+L_00000000040487a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9bf60_0 .net8 "VPWR", 0 0, L_00000000040487a0;  1 drivers, strength-aware
+v0000000003b9b100_0 .net "X", 0 0, L_000000000413f410;  alias, 1 drivers
+S_0000000003b5fb10 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b5f690;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413f100 .functor OR 1, L_0000000004140ad0, L_000000000413dab0, C4<0>, C4<0>;
+L_000000000413f410 .functor BUF 1, L_000000000413f100, C4<0>, C4<0>, C4<0>;
+v0000000003b9b920_0 .net "A", 0 0, L_000000000413dab0;  alias, 1 drivers
+v0000000003b9ac00_0 .net "B", 0 0, L_0000000004140ad0;  alias, 1 drivers
+L_00000000040472a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b600_0 .net8 "VGND", 0 0, L_00000000040472a0;  1 drivers, strength-aware
+L_0000000004047b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b1a0_0 .net8 "VNB", 0 0, L_0000000004047b60;  1 drivers, strength-aware
+L_0000000004046eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9bc40_0 .net8 "VPB", 0 0, L_0000000004046eb0;  1 drivers, strength-aware
+L_00000000040486c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b6a0_0 .net8 "VPWR", 0 0, L_00000000040486c0;  1 drivers, strength-aware
+v0000000003b9b740_0 .net "X", 0 0, L_000000000413f410;  alias, 1 drivers
+v0000000003b9a520_0 .net "or0_out_X", 0 0, L_000000000413f100;  1 drivers
+S_0000000003b60a10 .scope module, "_0856_" "sky130_fd_sc_hd__a21boi_2" 3 2438, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b9c0a0_0 .net "A1", 0 0, L_000000000413dab0;  alias, 1 drivers
+v0000000003b9bb00_0 .net "A2", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003b99940_0 .net "B1_N", 0 0, L_000000000413f410;  alias, 1 drivers
+L_0000000004047af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b999e0_0 .net8 "VGND", 0 0, L_0000000004047af0;  1 drivers, strength-aware
+L_00000000040482d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a660_0 .net8 "VNB", 0 0, L_00000000040482d0;  1 drivers, strength-aware
+L_0000000004047930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b99a80_0 .net8 "VPB", 0 0, L_0000000004047930;  1 drivers, strength-aware
+L_00000000040470e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b99b20_0 .net8 "VPWR", 0 0, L_00000000040470e0;  1 drivers, strength-aware
+v0000000003b9a200_0 .net "Y", 0 0, L_0000000004140bb0;  alias, 1 drivers
+S_0000000003b62090 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b60a10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_0000000004140b40 .functor NOT 1, L_000000000413f410, C4<0>, C4<0>, C4<0>;
+L_0000000004140050 .functor AND 1, L_000000000413dab0, L_0000000004140ad0, C4<1>, C4<1>;
+L_0000000004140440 .functor NOR 1, L_0000000004140b40, L_0000000004140050, C4<0>, C4<0>;
+L_0000000004140bb0 .functor BUF 1, L_0000000004140440, C4<0>, C4<0>, C4<0>;
+v0000000003b99d00_0 .net "A1", 0 0, L_000000000413dab0;  alias, 1 drivers
+v0000000003b9c000_0 .net "A2", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003b99e40_0 .net "B1_N", 0 0, L_000000000413f410;  alias, 1 drivers
+L_0000000004047070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b880_0 .net8 "VGND", 0 0, L_0000000004047070;  1 drivers, strength-aware
+L_00000000040471c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a3e0_0 .net8 "VNB", 0 0, L_00000000040471c0;  1 drivers, strength-aware
+L_0000000004047000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a020_0 .net8 "VPB", 0 0, L_0000000004047000;  1 drivers, strength-aware
+L_0000000004047700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ba60_0 .net8 "VPWR", 0 0, L_0000000004047700;  1 drivers, strength-aware
+v0000000003b9aca0_0 .net "Y", 0 0, L_0000000004140bb0;  alias, 1 drivers
+v0000000003b9ae80_0 .net "and0_out", 0 0, L_0000000004140050;  1 drivers
+v0000000003b9a8e0_0 .net "b", 0 0, L_0000000004140b40;  1 drivers
+v0000000003b9a160_0 .net "nor0_out_Y", 0 0, L_0000000004140440;  1 drivers
+S_0000000003b61c10 .scope module, "_0857_" "sky130_fd_sc_hd__or2_2" 3 2444, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b9c5a0_0 .net "A", 0 0, L_0000000004138b80;  alias, 1 drivers
+v0000000003b9c460_0 .net "B", 0 0, L_00000000041311e0;  alias, 1 drivers
+L_0000000004048730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9da40_0 .net8 "VGND", 0 0, L_0000000004048730;  1 drivers, strength-aware
+L_0000000004048650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9cd20_0 .net8 "VNB", 0 0, L_0000000004048650;  1 drivers, strength-aware
+L_0000000004048810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c500_0 .net8 "VPB", 0 0, L_0000000004048810;  1 drivers, strength-aware
+L_0000000004048880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d180_0 .net8 "VPWR", 0 0, L_0000000004048880;  1 drivers, strength-aware
+v0000000003b9d5e0_0 .net "X", 0 0, L_000000000413f8e0;  alias, 1 drivers
+S_0000000003b5f990 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b61c10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004140830 .functor OR 1, L_00000000041311e0, L_0000000004138b80, C4<0>, C4<0>;
+L_000000000413f8e0 .functor BUF 1, L_0000000004140830, C4<0>, C4<0>, C4<0>;
+v0000000003b9a980_0 .net "A", 0 0, L_0000000004138b80;  alias, 1 drivers
+v0000000003b9a2a0_0 .net "B", 0 0, L_00000000041311e0;  alias, 1 drivers
+L_00000000040477e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9b420_0 .net8 "VGND", 0 0, L_00000000040477e0;  1 drivers, strength-aware
+L_0000000004047620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a480_0 .net8 "VNB", 0 0, L_0000000004047620;  1 drivers, strength-aware
+L_0000000004048110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9a7a0_0 .net8 "VPB", 0 0, L_0000000004048110;  1 drivers, strength-aware
+L_00000000040473f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9af20_0 .net8 "VPWR", 0 0, L_00000000040473f0;  1 drivers, strength-aware
+v0000000003b9afc0_0 .net "X", 0 0, L_000000000413f8e0;  alias, 1 drivers
+v0000000003b9b060_0 .net "or0_out_X", 0 0, L_0000000004140830;  1 drivers
+S_0000000003b62810 .scope module, "_0858_" "sky130_fd_sc_hd__a2bb2o_2" 3 2449, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003b9d0e0_0 .net "A1_N", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b9c280_0 .net "A2_N", 0 0, L_000000000413f8e0;  alias, 1 drivers
+v0000000003b9ca00_0 .net "B1", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b9d7c0_0 .net "B2", 0 0, L_000000000413f8e0;  alias, 1 drivers
+L_0000000004046f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c6e0_0 .net8 "VGND", 0 0, L_0000000004046f20;  1 drivers, strength-aware
+L_0000000004048260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c820_0 .net8 "VNB", 0 0, L_0000000004048260;  1 drivers, strength-aware
+L_0000000004046cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d220_0 .net8 "VPB", 0 0, L_0000000004046cf0;  1 drivers, strength-aware
+L_0000000004047bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c320_0 .net8 "VPWR", 0 0, L_0000000004047bd0;  1 drivers, strength-aware
+v0000000003b9e580_0 .net "X", 0 0, L_000000000413f1e0;  alias, 1 drivers
+S_0000000003b61490 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003b62810;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041404b0 .functor AND 1, L_00000000041382c0, L_000000000413f8e0, C4<1>, C4<1>;
+L_000000000413ff00 .functor NOR 1, L_00000000041382c0, L_000000000413f8e0, C4<0>, C4<0>;
+L_00000000041406e0 .functor OR 1, L_000000000413ff00, L_00000000041404b0, C4<0>, C4<0>;
+L_000000000413f1e0 .functor BUF 1, L_00000000041406e0, C4<0>, C4<0>, C4<0>;
+v0000000003b9c3c0_0 .net "A1_N", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b9dd60_0 .net "A2_N", 0 0, L_000000000413f8e0;  alias, 1 drivers
+v0000000003b9cb40_0 .net "B1", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003b9d720_0 .net "B2", 0 0, L_000000000413f8e0;  alias, 1 drivers
+L_0000000004047310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d9a0_0 .net8 "VGND", 0 0, L_0000000004047310;  1 drivers, strength-aware
+L_0000000004047c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e800_0 .net8 "VNB", 0 0, L_0000000004047c40;  1 drivers, strength-aware
+L_0000000004047230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c140_0 .net8 "VPB", 0 0, L_0000000004047230;  1 drivers, strength-aware
+L_00000000040478c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e8a0_0 .net8 "VPWR", 0 0, L_00000000040478c0;  1 drivers, strength-aware
+v0000000003b9c1e0_0 .net "X", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003b9cbe0_0 .net "and0_out", 0 0, L_00000000041404b0;  1 drivers
+v0000000003b9cc80_0 .net "nor0_out", 0 0, L_000000000413ff00;  1 drivers
+v0000000003b9cdc0_0 .net "or0_out_X", 0 0, L_00000000041406e0;  1 drivers
+S_0000000003b61a90 .scope module, "_0859_" "sky130_fd_sc_hd__or2_2" 3 2456, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b9c780_0 .net "A", 0 0, L_000000000413f410;  alias, 1 drivers
+v0000000003b9d900_0 .net "B", 0 0, L_000000000413f1e0;  alias, 1 drivers
+L_0000000004046f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9db80_0 .net8 "VGND", 0 0, L_0000000004046f90;  1 drivers, strength-aware
+L_0000000004047cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c960_0 .net8 "VNB", 0 0, L_0000000004047cb0;  1 drivers, strength-aware
+L_0000000004047690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9cf00_0 .net8 "VPB", 0 0, L_0000000004047690;  1 drivers, strength-aware
+L_0000000004048180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e3a0_0 .net8 "VPWR", 0 0, L_0000000004048180;  1 drivers, strength-aware
+v0000000003b9cfa0_0 .net "X", 0 0, L_000000000413fe90;  alias, 1 drivers
+S_0000000003b60590 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b61a90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413f4f0 .functor OR 1, L_000000000413f1e0, L_000000000413f410, C4<0>, C4<0>;
+L_000000000413fe90 .functor BUF 1, L_000000000413f4f0, C4<0>, C4<0>, C4<0>;
+v0000000003b9c8c0_0 .net "A", 0 0, L_000000000413f410;  alias, 1 drivers
+v0000000003b9d680_0 .net "B", 0 0, L_000000000413f1e0;  alias, 1 drivers
+L_0000000004047d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9dae0_0 .net8 "VGND", 0 0, L_0000000004047d20;  1 drivers, strength-aware
+L_0000000004048340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ce60_0 .net8 "VNB", 0 0, L_0000000004048340;  1 drivers, strength-aware
+L_0000000004046d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9c640_0 .net8 "VPB", 0 0, L_0000000004046d60;  1 drivers, strength-aware
+L_0000000004046dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d2c0_0 .net8 "VPWR", 0 0, L_0000000004046dd0;  1 drivers, strength-aware
+v0000000003b9d860_0 .net "X", 0 0, L_000000000413fe90;  alias, 1 drivers
+v0000000003b9d360_0 .net "or0_out_X", 0 0, L_000000000413f4f0;  1 drivers
+S_0000000003b60d10 .scope module, "_0860_" "sky130_fd_sc_hd__a21boi_2" 3 2461, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003b9df40_0 .net "A1", 0 0, L_000000000413f410;  alias, 1 drivers
+v0000000003b9dfe0_0 .net "A2", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003b9e080_0 .net "B1_N", 0 0, L_000000000413fe90;  alias, 1 drivers
+L_00000000040479a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e120_0 .net8 "VGND", 0 0, L_00000000040479a0;  1 drivers, strength-aware
+L_0000000004047e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e1c0_0 .net8 "VNB", 0 0, L_0000000004047e00;  1 drivers, strength-aware
+L_00000000040474d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e620_0 .net8 "VPB", 0 0, L_00000000040474d0;  1 drivers, strength-aware
+L_0000000004046e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e260_0 .net8 "VPWR", 0 0, L_0000000004046e40;  1 drivers, strength-aware
+v0000000003b9e4e0_0 .net "Y", 0 0, L_00000000041400c0;  alias, 1 drivers
+S_0000000003b5fc90 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003b60d10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_00000000041407c0 .functor NOT 1, L_000000000413fe90, C4<0>, C4<0>, C4<0>;
+L_0000000004140520 .functor AND 1, L_000000000413f410, L_000000000413f1e0, C4<1>, C4<1>;
+L_000000000413f6b0 .functor NOR 1, L_00000000041407c0, L_0000000004140520, C4<0>, C4<0>;
+L_00000000041400c0 .functor BUF 1, L_000000000413f6b0, C4<0>, C4<0>, C4<0>;
+v0000000003b9caa0_0 .net "A1", 0 0, L_000000000413f410;  alias, 1 drivers
+v0000000003b9d040_0 .net "A2", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003b9de00_0 .net "B1_N", 0 0, L_000000000413fe90;  alias, 1 drivers
+L_00000000040481f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d400_0 .net8 "VGND", 0 0, L_00000000040481f0;  1 drivers, strength-aware
+L_00000000040483b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d4a0_0 .net8 "VNB", 0 0, L_00000000040483b0;  1 drivers, strength-aware
+L_0000000004047770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9d540_0 .net8 "VPB", 0 0, L_0000000004047770;  1 drivers, strength-aware
+L_0000000004048420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9dc20_0 .net8 "VPWR", 0 0, L_0000000004048420;  1 drivers, strength-aware
+v0000000003b9dcc0_0 .net "Y", 0 0, L_00000000041400c0;  alias, 1 drivers
+v0000000003b9dea0_0 .net "and0_out", 0 0, L_0000000004140520;  1 drivers
+v0000000003b9e440_0 .net "b", 0 0, L_00000000041407c0;  1 drivers
+v0000000003b9e6c0_0 .net "nor0_out_Y", 0 0, L_000000000413f6b0;  1 drivers
+S_0000000003b61910 .scope module, "_0861_" "sky130_fd_sc_hd__inv_2" 3 2467, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003ba04c0_0 .net "A", 0 0, L_0000000004139c20;  alias, 1 drivers
+L_0000000004047540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9eee0_0 .net8 "VGND", 0 0, L_0000000004047540;  1 drivers, strength-aware
+L_0000000004047f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba09c0_0 .net8 "VNB", 0 0, L_0000000004047f50;  1 drivers, strength-aware
+L_0000000004047fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0880_0 .net8 "VPB", 0 0, L_0000000004047fc0;  1 drivers, strength-aware
+L_0000000004047850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ec60_0 .net8 "VPWR", 0 0, L_0000000004047850;  1 drivers, strength-aware
+v0000000003b9f700_0 .net "Y", 0 0, L_000000000413f5d0;  alias, 1 drivers
+S_0000000003b5fe10 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b61910;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000413ffe0 .functor NOT 1, L_0000000004139c20, C4<0>, C4<0>, C4<0>;
+L_000000000413f5d0 .functor BUF 1, L_000000000413ffe0, C4<0>, C4<0>, C4<0>;
+v0000000003b9e300_0 .net "A", 0 0, L_0000000004139c20;  alias, 1 drivers
+L_00000000040475b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e760_0 .net8 "VGND", 0 0, L_00000000040475b0;  1 drivers, strength-aware
+L_0000000004048490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ed00_0 .net8 "VNB", 0 0, L_0000000004048490;  1 drivers, strength-aware
+L_0000000004048500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fca0_0 .net8 "VPB", 0 0, L_0000000004048500;  1 drivers, strength-aware
+L_0000000004047150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba07e0_0 .net8 "VPWR", 0 0, L_0000000004047150;  1 drivers, strength-aware
+v0000000003ba0d80_0 .net "Y", 0 0, L_000000000413f5d0;  alias, 1 drivers
+v0000000003b9f520_0 .net "not0_out_Y", 0 0, L_000000000413ffe0;  1 drivers
+S_0000000003b60110 .scope module, "_0862_" "sky130_fd_sc_hd__or2_2" 3 2471, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba06a0_0 .net "A", 0 0, L_000000000413f5d0;  alias, 1 drivers
+v0000000003b9fac0_0 .net "B", 0 0, L_00000000041393d0;  alias, 1 drivers
+L_0000000004047e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fa20_0 .net8 "VGND", 0 0, L_0000000004047e70;  1 drivers, strength-aware
+L_0000000004048570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f980_0 .net8 "VNB", 0 0, L_0000000004048570;  1 drivers, strength-aware
+L_0000000004047a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ee40_0 .net8 "VPB", 0 0, L_0000000004047a10;  1 drivers, strength-aware
+L_0000000004047460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0e20_0 .net8 "VPWR", 0 0, L_0000000004047460;  1 drivers, strength-aware
+v0000000003b9ef80_0 .net "X", 0 0, L_000000000413fbf0;  alias, 1 drivers
+S_0000000003b62210 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b60110;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413f9c0 .functor OR 1, L_00000000041393d0, L_000000000413f5d0, C4<0>, C4<0>;
+L_000000000413fbf0 .functor BUF 1, L_000000000413f9c0, C4<0>, C4<0>, C4<0>;
+v0000000003b9f8e0_0 .net "A", 0 0, L_000000000413f5d0;  alias, 1 drivers
+v0000000003ba0920_0 .net "B", 0 0, L_00000000041393d0;  alias, 1 drivers
+L_00000000040485e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f020_0 .net8 "VGND", 0 0, L_00000000040485e0;  1 drivers, strength-aware
+L_0000000004047380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9eda0_0 .net8 "VNB", 0 0, L_0000000004047380;  1 drivers, strength-aware
+L_0000000004047a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1000_0 .net8 "VPB", 0 0, L_0000000004047a80;  1 drivers, strength-aware
+L_0000000004047ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9ebc0_0 .net8 "VPWR", 0 0, L_0000000004047ee0;  1 drivers, strength-aware
+v0000000003b9fb60_0 .net "X", 0 0, L_000000000413fbf0;  alias, 1 drivers
+v0000000003b9ea80_0 .net "or0_out_X", 0 0, L_000000000413f9c0;  1 drivers
+S_0000000003b62c90 .scope module, "_0863_" "sky130_fd_sc_hd__or2_2" 3 2476, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba01a0_0 .net "A", 0 0, L_0000000004132c20;  alias, 1 drivers
+v0000000003ba0560_0 .net "B", 0 0, L_000000000413f8e0;  alias, 1 drivers
+L_0000000004048030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0240_0 .net8 "VGND", 0 0, L_0000000004048030;  1 drivers, strength-aware
+L_00000000040480a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0ba0_0 .net8 "VNB", 0 0, L_00000000040480a0;  1 drivers, strength-aware
+L_0000000004049a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f3e0_0 .net8 "VPB", 0 0, L_0000000004049a00;  1 drivers, strength-aware
+L_0000000004048dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0740_0 .net8 "VPWR", 0 0, L_0000000004048dc0;  1 drivers, strength-aware
+v0000000003b9f5c0_0 .net "X", 0 0, L_000000000413f2c0;  alias, 1 drivers
+S_0000000003b61310 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003b62c90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413fa30 .functor OR 1, L_000000000413f8e0, L_0000000004132c20, C4<0>, C4<0>;
+L_000000000413f2c0 .functor BUF 1, L_000000000413fa30, C4<0>, C4<0>, C4<0>;
+v0000000003ba0a60_0 .net "A", 0 0, L_0000000004132c20;  alias, 1 drivers
+v0000000003b9e940_0 .net "B", 0 0, L_000000000413f8e0;  alias, 1 drivers
+L_000000000404a410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0600_0 .net8 "VGND", 0 0, L_000000000404a410;  1 drivers, strength-aware
+L_0000000004048b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0420_0 .net8 "VNB", 0 0, L_0000000004048b20;  1 drivers, strength-aware
+L_000000000404a480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f0c0_0 .net8 "VPB", 0 0, L_000000000404a480;  1 drivers, strength-aware
+L_0000000004049ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f2a0_0 .net8 "VPWR", 0 0, L_0000000004049ca0;  1 drivers, strength-aware
+v0000000003b9f160_0 .net "X", 0 0, L_000000000413f2c0;  alias, 1 drivers
+v0000000003b9f7a0_0 .net "or0_out_X", 0 0, L_000000000413fa30;  1 drivers
+S_0000000003b61d90 .scope module, "_0864_" "sky130_fd_sc_hd__o21ai_2" 3 2481, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b9eb20_0 .net "A1", 0 0, L_0000000004132c90;  alias, 1 drivers
+v0000000003b9f340_0 .net "A2", 0 0, L_000000000413e530;  alias, 1 drivers
+v0000000003b9f480_0 .net "B1", 0 0, L_000000000412fb90;  alias, 1 drivers
+L_00000000040488f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9e9e0_0 .net8 "VGND", 0 0, L_00000000040488f0;  1 drivers, strength-aware
+L_0000000004049bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fc00_0 .net8 "VNB", 0 0, L_0000000004049bc0;  1 drivers, strength-aware
+L_0000000004049220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f660_0 .net8 "VPB", 0 0, L_0000000004049220;  1 drivers, strength-aware
+L_000000000404a100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fe80_0 .net8 "VPWR", 0 0, L_000000000404a100;  1 drivers, strength-aware
+v0000000003b9ff20_0 .net "Y", 0 0, L_0000000004140750;  alias, 1 drivers
+S_0000000003b61f10 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b61d90;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004140670 .functor OR 1, L_000000000413e530, L_0000000004132c90, C4<0>, C4<0>;
+L_000000000413f3a0 .functor NAND 1, L_000000000412fb90, L_0000000004140670, C4<1>, C4<1>;
+L_0000000004140750 .functor BUF 1, L_000000000413f3a0, C4<0>, C4<0>, C4<0>;
+v0000000003ba0ec0_0 .net "A1", 0 0, L_0000000004132c90;  alias, 1 drivers
+v0000000003ba0ce0_0 .net "A2", 0 0, L_000000000413e530;  alias, 1 drivers
+v0000000003ba0b00_0 .net "B1", 0 0, L_000000000412fb90;  alias, 1 drivers
+L_0000000004049060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fd40_0 .net8 "VGND", 0 0, L_0000000004049060;  1 drivers, strength-aware
+L_0000000004048ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b9f840_0 .net8 "VNB", 0 0, L_0000000004048ce0;  1 drivers, strength-aware
+L_0000000004048960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b9fde0_0 .net8 "VPB", 0 0, L_0000000004048960;  1 drivers, strength-aware
+L_0000000004049990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0c40_0 .net8 "VPWR", 0 0, L_0000000004049990;  1 drivers, strength-aware
+v0000000003b9f200_0 .net "Y", 0 0, L_0000000004140750;  alias, 1 drivers
+v0000000003ba0f60_0 .net "nand0_out_Y", 0 0, L_000000000413f3a0;  1 drivers
+v0000000003ba10a0_0 .net "or0_out", 0 0, L_0000000004140670;  1 drivers
+S_0000000003b62e10 .scope module, "_0865_" "sky130_fd_sc_hd__o21ai_2" 3 2487, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba1f00_0 .net "A1", 0 0, L_000000000413e220;  alias, 1 drivers
+v0000000003ba1140_0 .net "A2", 0 0, L_000000000413f2c0;  alias, 1 drivers
+v0000000003ba3120_0 .net "B1", 0 0, L_0000000004140750;  alias, 1 drivers
+L_000000000404a3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2c20_0 .net8 "VGND", 0 0, L_000000000404a3a0;  1 drivers, strength-aware
+L_0000000004048ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1d20_0 .net8 "VNB", 0 0, L_0000000004048ea0;  1 drivers, strength-aware
+L_0000000004049760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2040_0 .net8 "VPB", 0 0, L_0000000004049760;  1 drivers, strength-aware
+L_0000000004048ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba20e0_0 .net8 "VPWR", 0 0, L_0000000004048ab0;  1 drivers, strength-aware
+v0000000003ba1820_0 .net "Y", 0 0, L_000000000413f720;  alias, 1 drivers
+S_0000000003b5f090 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003b62e10;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413f560 .functor OR 1, L_000000000413f2c0, L_000000000413e220, C4<0>, C4<0>;
+L_000000000413f640 .functor NAND 1, L_0000000004140750, L_000000000413f560, C4<1>, C4<1>;
+L_000000000413f720 .functor BUF 1, L_000000000413f640, C4<0>, C4<0>, C4<0>;
+v0000000003b9ffc0_0 .net "A1", 0 0, L_000000000413e220;  alias, 1 drivers
+v0000000003ba0060_0 .net "A2", 0 0, L_000000000413f2c0;  alias, 1 drivers
+v0000000003ba0100_0 .net "B1", 0 0, L_0000000004140750;  alias, 1 drivers
+L_000000000404a2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba02e0_0 .net8 "VGND", 0 0, L_000000000404a2c0;  1 drivers, strength-aware
+L_0000000004049290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba0380_0 .net8 "VNB", 0 0, L_0000000004049290;  1 drivers, strength-aware
+L_00000000040497d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2cc0_0 .net8 "VPB", 0 0, L_00000000040497d0;  1 drivers, strength-aware
+L_000000000404a020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3440_0 .net8 "VPWR", 0 0, L_000000000404a020;  1 drivers, strength-aware
+v0000000003ba16e0_0 .net "Y", 0 0, L_000000000413f720;  alias, 1 drivers
+v0000000003ba38a0_0 .net "nand0_out_Y", 0 0, L_000000000413f640;  1 drivers
+v0000000003ba2180_0 .net "or0_out", 0 0, L_000000000413f560;  1 drivers
+S_0000000003b5f210 .scope module, "_0866_" "sky130_fd_sc_hd__and2b_2" 3 2493, 4 34253 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba2220_0 .net "A_N", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003ba3800_0 .net "B", 0 0, L_000000000413e8b0;  alias, 1 drivers
+L_0000000004049610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1280_0 .net8 "VGND", 0 0, L_0000000004049610;  1 drivers, strength-aware
+L_000000000404a1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1780_0 .net8 "VNB", 0 0, L_000000000404a1e0;  1 drivers, strength-aware
+L_0000000004049840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2e00_0 .net8 "VPB", 0 0, L_0000000004049840;  1 drivers, strength-aware
+L_0000000004049d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1320_0 .net8 "VPWR", 0 0, L_0000000004049d10;  1 drivers, strength-aware
+v0000000003ba13c0_0 .net "X", 0 0, L_000000000413fb10;  alias, 1 drivers
+S_0000000003b62390 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34269, 4 34662 1, S_0000000003b5f210;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_000000000413faa0 .functor NOT 1, L_0000000004136c00, C4<0>, C4<0>, C4<0>;
+L_0000000004140130 .functor AND 1, L_000000000413faa0, L_000000000413e8b0, C4<1>, C4<1>;
+L_000000000413fb10 .functor BUF 1, L_0000000004140130, C4<0>, C4<0>, C4<0>;
+v0000000003ba25e0_0 .net "A_N", 0 0, L_0000000004136c00;  alias, 1 drivers
+v0000000003ba2360_0 .net "B", 0 0, L_000000000413e8b0;  alias, 1 drivers
+L_0000000004048c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba22c0_0 .net8 "VGND", 0 0, L_0000000004048c70;  1 drivers, strength-aware
+L_0000000004048d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2720_0 .net8 "VNB", 0 0, L_0000000004048d50;  1 drivers, strength-aware
+L_0000000004049c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba15a0_0 .net8 "VPB", 0 0, L_0000000004049c30;  1 drivers, strength-aware
+L_0000000004049d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2ae0_0 .net8 "VPWR", 0 0, L_0000000004049d80;  1 drivers, strength-aware
+v0000000003ba11e0_0 .net "X", 0 0, L_000000000413fb10;  alias, 1 drivers
+v0000000003ba2f40_0 .net "and0_out_X", 0 0, L_0000000004140130;  1 drivers
+v0000000003ba2d60_0 .net "not0_out", 0 0, L_000000000413faa0;  1 drivers
+S_0000000003b62690 .scope module, "_0867_" "sky130_fd_sc_hd__inv_2" 3 2498, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003ba2a40_0 .net "A", 0 0, L_000000000413f720;  alias, 1 drivers
+L_00000000040489d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3080_0 .net8 "VGND", 0 0, L_00000000040489d0;  1 drivers, strength-aware
+L_0000000004049df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2b80_0 .net8 "VNB", 0 0, L_0000000004049df0;  1 drivers, strength-aware
+L_0000000004049a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba34e0_0 .net8 "VPB", 0 0, L_0000000004049a70;  1 drivers, strength-aware
+L_000000000404a250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1960_0 .net8 "VPWR", 0 0, L_000000000404a250;  1 drivers, strength-aware
+v0000000003ba1fa0_0 .net "Y", 0 0, L_000000000413fe20;  alias, 1 drivers
+S_0000000003b60290 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003b62690;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004140590 .functor NOT 1, L_000000000413f720, C4<0>, C4<0>, C4<0>;
+L_000000000413fe20 .functor BUF 1, L_0000000004140590, C4<0>, C4<0>, C4<0>;
+v0000000003ba18c0_0 .net "A", 0 0, L_000000000413f720;  alias, 1 drivers
+L_000000000404a330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba31c0_0 .net8 "VGND", 0 0, L_000000000404a330;  1 drivers, strength-aware
+L_0000000004049ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2900_0 .net8 "VNB", 0 0, L_0000000004049ae0;  1 drivers, strength-aware
+L_0000000004049e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2ea0_0 .net8 "VPB", 0 0, L_0000000004049e60;  1 drivers, strength-aware
+L_00000000040496f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1460_0 .net8 "VPWR", 0 0, L_00000000040496f0;  1 drivers, strength-aware
+v0000000003ba1c80_0 .net "Y", 0 0, L_000000000413fe20;  alias, 1 drivers
+v0000000003ba2fe0_0 .net "not0_out_Y", 0 0, L_0000000004140590;  1 drivers
+S_0000000003bd9970 .scope module, "_0868_" "sky130_fd_sc_hd__o21ai_2" 3 2502, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba1a00_0 .net "A1", 0 0, L_000000000413f2c0;  alias, 1 drivers
+v0000000003ba29a0_0 .net "A2", 0 0, L_000000000413fb10;  alias, 1 drivers
+v0000000003ba3300_0 .net "B1", 0 0, L_000000000413fe20;  alias, 1 drivers
+L_00000000040498b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba33a0_0 .net8 "VGND", 0 0, L_00000000040498b0;  1 drivers, strength-aware
+L_0000000004049370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3620_0 .net8 "VNB", 0 0, L_0000000004049370;  1 drivers, strength-aware
+L_00000000040490d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1aa0_0 .net8 "VPB", 0 0, L_00000000040490d0;  1 drivers, strength-aware
+L_0000000004049b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1b40_0 .net8 "VPWR", 0 0, L_0000000004049b50;  1 drivers, strength-aware
+v0000000003ba2540_0 .net "Y", 0 0, L_000000000413f950;  alias, 1 drivers
+S_0000000003bdb2f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003bd9970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000413fb80 .functor OR 1, L_000000000413fb10, L_000000000413f2c0, C4<0>, C4<0>;
+L_00000000041401a0 .functor NAND 1, L_000000000413fe20, L_000000000413fb80, C4<1>, C4<1>;
+L_000000000413f950 .functor BUF 1, L_00000000041401a0, C4<0>, C4<0>, C4<0>;
+v0000000003ba2400_0 .net "A1", 0 0, L_000000000413f2c0;  alias, 1 drivers
+v0000000003ba1640_0 .net "A2", 0 0, L_000000000413fb10;  alias, 1 drivers
+v0000000003ba27c0_0 .net "B1", 0 0, L_000000000413fe20;  alias, 1 drivers
+L_0000000004048b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba1500_0 .net8 "VGND", 0 0, L_0000000004048b90;  1 drivers, strength-aware
+L_0000000004048a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba24a0_0 .net8 "VNB", 0 0, L_0000000004048a40;  1 drivers, strength-aware
+L_0000000004048c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3580_0 .net8 "VPB", 0 0, L_0000000004048c00;  1 drivers, strength-aware
+L_0000000004049ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3260_0 .net8 "VPWR", 0 0, L_0000000004049ed0;  1 drivers, strength-aware
+v0000000003ba36c0_0 .net "Y", 0 0, L_000000000413f950;  alias, 1 drivers
+v0000000003ba3760_0 .net "nand0_out_Y", 0 0, L_00000000041401a0;  1 drivers
+v0000000003ba2860_0 .net "or0_out", 0 0, L_000000000413fb80;  1 drivers
+S_0000000003bdb170 .scope module, "_0869_" "sky130_fd_sc_hd__o21a_2" 3 2508, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba3b20_0 .net "A1", 0 0, L_000000000413e300;  alias, 1 drivers
+v0000000003ba5060_0 .net "A2", 0 0, L_000000000413f720;  alias, 1 drivers
+v0000000003ba52e0_0 .net "B1", 0 0, L_000000000413f950;  alias, 1 drivers
+L_0000000004048f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba39e0_0 .net8 "VGND", 0 0, L_0000000004048f10;  1 drivers, strength-aware
+L_0000000004048f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5740_0 .net8 "VNB", 0 0, L_0000000004048f80;  1 drivers, strength-aware
+L_0000000004049920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5e20_0 .net8 "VPB", 0 0, L_0000000004049920;  1 drivers, strength-aware
+L_0000000004048e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4340_0 .net8 "VPWR", 0 0, L_0000000004048e30;  1 drivers, strength-aware
+v0000000003ba4f20_0 .net "X", 0 0, L_000000000413f790;  alias, 1 drivers
+S_0000000003bddcf0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003bdb170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004140c20 .functor OR 1, L_000000000413f720, L_000000000413e300, C4<0>, C4<0>;
+L_0000000004140c90 .functor AND 1, L_0000000004140c20, L_000000000413f950, C4<1>, C4<1>;
+L_000000000413f790 .functor BUF 1, L_0000000004140c90, C4<0>, C4<0>, C4<0>;
+v0000000003ba1be0_0 .net "A1", 0 0, L_000000000413e300;  alias, 1 drivers
+v0000000003ba1dc0_0 .net "A2", 0 0, L_000000000413f720;  alias, 1 drivers
+v0000000003ba1e60_0 .net "B1", 0 0, L_000000000413f950;  alias, 1 drivers
+L_00000000040493e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba2680_0 .net8 "VGND", 0 0, L_00000000040493e0;  1 drivers, strength-aware
+L_0000000004048ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3940_0 .net8 "VNB", 0 0, L_0000000004048ff0;  1 drivers, strength-aware
+L_0000000004049140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3d00_0 .net8 "VPB", 0 0, L_0000000004049140;  1 drivers, strength-aware
+L_0000000004049f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4160_0 .net8 "VPWR", 0 0, L_0000000004049f40;  1 drivers, strength-aware
+v0000000003ba4e80_0 .net "X", 0 0, L_000000000413f790;  alias, 1 drivers
+v0000000003ba4980_0 .net "and0_out_X", 0 0, L_0000000004140c90;  1 drivers
+v0000000003ba4c00_0 .net "or0_out", 0 0, L_0000000004140c20;  1 drivers
+S_0000000003bdab70 .scope module, "_0870_" "sky130_fd_sc_hd__a2bb2o_2" 3 2514, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003ba5600_0 .net "A1_N", 0 0, L_000000000413fbf0;  alias, 1 drivers
+v0000000003ba5240_0 .net "A2_N", 0 0, L_000000000413f790;  alias, 1 drivers
+v0000000003ba5f60_0 .net "B1", 0 0, L_000000000413fbf0;  alias, 1 drivers
+v0000000003ba5380_0 .net "B2", 0 0, L_000000000413f790;  alias, 1 drivers
+L_0000000004049fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4ac0_0 .net8 "VGND", 0 0, L_0000000004049fb0;  1 drivers, strength-aware
+L_0000000004049450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5ce0_0 .net8 "VNB", 0 0, L_0000000004049450;  1 drivers, strength-aware
+L_00000000040494c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3da0_0 .net8 "VPB", 0 0, L_00000000040494c0;  1 drivers, strength-aware
+L_00000000040491b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba47a0_0 .net8 "VPWR", 0 0, L_00000000040491b0;  1 drivers, strength-aware
+v0000000003ba5420_0 .net "X", 0 0, L_0000000004140600;  alias, 1 drivers
+S_0000000003bdd570 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003bdab70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000413fd40 .functor AND 1, L_000000000413fbf0, L_000000000413f790, C4<1>, C4<1>;
+L_000000000413f800 .functor NOR 1, L_000000000413fbf0, L_000000000413f790, C4<0>, C4<0>;
+L_000000000413fc60 .functor OR 1, L_000000000413f800, L_000000000413fd40, C4<0>, C4<0>;
+L_0000000004140600 .functor BUF 1, L_000000000413fc60, C4<0>, C4<0>, C4<0>;
+v0000000003ba3bc0_0 .net "A1_N", 0 0, L_000000000413fbf0;  alias, 1 drivers
+v0000000003ba5560_0 .net "A2_N", 0 0, L_000000000413f790;  alias, 1 drivers
+v0000000003ba43e0_0 .net "B1", 0 0, L_000000000413fbf0;  alias, 1 drivers
+v0000000003ba4200_0 .net "B2", 0 0, L_000000000413f790;  alias, 1 drivers
+L_0000000004049530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba48e0_0 .net8 "VGND", 0 0, L_0000000004049530;  1 drivers, strength-aware
+L_0000000004049300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5ec0_0 .net8 "VNB", 0 0, L_0000000004049300;  1 drivers, strength-aware
+L_00000000040495a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4480_0 .net8 "VPB", 0 0, L_00000000040495a0;  1 drivers, strength-aware
+L_0000000004049680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba57e0_0 .net8 "VPWR", 0 0, L_0000000004049680;  1 drivers, strength-aware
+v0000000003ba59c0_0 .net "X", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003ba5100_0 .net "and0_out", 0 0, L_000000000413fd40;  1 drivers
+v0000000003ba4020_0 .net "nor0_out", 0 0, L_000000000413f800;  1 drivers
+v0000000003ba5a60_0 .net "or0_out_X", 0 0, L_000000000413fc60;  1 drivers
+S_0000000003bda0f0 .scope module, "_0871_" "sky130_fd_sc_hd__nor2_2" 3 2521, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba5920_0 .net "A", 0 0, L_000000000413fe90;  alias, 1 drivers
+v0000000003ba5b00_0 .net "B", 0 0, L_0000000004140600;  alias, 1 drivers
+L_000000000404a090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5d80_0 .net8 "VGND", 0 0, L_000000000404a090;  1 drivers, strength-aware
+L_000000000404a170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6000_0 .net8 "VNB", 0 0, L_000000000404a170;  1 drivers, strength-aware
+L_000000000404c010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba51a0_0 .net8 "VPB", 0 0, L_000000000404c010;  1 drivers, strength-aware
+L_000000000404adb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4d40_0 .net8 "VPWR", 0 0, L_000000000404adb0;  1 drivers, strength-aware
+v0000000003ba4840_0 .net "Y", 0 0, L_000000000413f870;  alias, 1 drivers
+S_0000000003bdde70 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003bda0f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004140980 .functor NOR 1, L_000000000413fe90, L_0000000004140600, C4<0>, C4<0>;
+L_000000000413f870 .functor BUF 1, L_0000000004140980, C4<0>, C4<0>, C4<0>;
+v0000000003ba4ca0_0 .net "A", 0 0, L_000000000413fe90;  alias, 1 drivers
+v0000000003ba54c0_0 .net "B", 0 0, L_0000000004140600;  alias, 1 drivers
+L_000000000404ae90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5ba0_0 .net8 "VGND", 0 0, L_000000000404ae90;  1 drivers, strength-aware
+L_000000000404ae20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba56a0_0 .net8 "VNB", 0 0, L_000000000404ae20;  1 drivers, strength-aware
+L_000000000404b830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5880_0 .net8 "VPB", 0 0, L_000000000404b830;  1 drivers, strength-aware
+L_000000000404bde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3ee0_0 .net8 "VPWR", 0 0, L_000000000404bde0;  1 drivers, strength-aware
+v0000000003ba4de0_0 .net "Y", 0 0, L_000000000413f870;  alias, 1 drivers
+v0000000003ba4520_0 .net "nor0_out_Y", 0 0, L_0000000004140980;  1 drivers
+S_0000000003bda270 .scope module, "_0872_" "sky130_fd_sc_hd__a21oi_2" 3 2526, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba3e40_0 .net "A1", 0 0, L_000000000413fe90;  alias, 1 drivers
+v0000000003ba3f80_0 .net "A2", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003ba4fc0_0 .net "B1", 0 0, L_000000000413f870;  alias, 1 drivers
+L_000000000404b8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba42a0_0 .net8 "VGND", 0 0, L_000000000404b8a0;  1 drivers, strength-aware
+L_000000000404b910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8080_0 .net8 "VNB", 0 0, L_000000000404b910;  1 drivers, strength-aware
+L_000000000404a5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba75e0_0 .net8 "VPB", 0 0, L_000000000404a5d0;  1 drivers, strength-aware
+L_000000000404b980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7360_0 .net8 "VPWR", 0 0, L_000000000404b980;  1 drivers, strength-aware
+v0000000003ba72c0_0 .net "Y", 0 0, L_000000000413fdb0;  alias, 1 drivers
+S_0000000003bd9af0 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003bda270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004140280 .functor AND 1, L_000000000413fe90, L_0000000004140600, C4<1>, C4<1>;
+L_000000000413fcd0 .functor NOR 1, L_000000000413f870, L_0000000004140280, C4<0>, C4<0>;
+L_000000000413fdb0 .functor BUF 1, L_000000000413fcd0, C4<0>, C4<0>, C4<0>;
+v0000000003ba40c0_0 .net "A1", 0 0, L_000000000413fe90;  alias, 1 drivers
+v0000000003ba4a20_0 .net "A2", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003ba60a0_0 .net "B1", 0 0, L_000000000413f870;  alias, 1 drivers
+L_000000000404b670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba5c40_0 .net8 "VGND", 0 0, L_000000000404b670;  1 drivers, strength-aware
+L_000000000404be50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba4660_0 .net8 "VNB", 0 0, L_000000000404be50;  1 drivers, strength-aware
+L_000000000404bec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3a80_0 .net8 "VPB", 0 0, L_000000000404bec0;  1 drivers, strength-aware
+L_000000000404b6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba3c60_0 .net8 "VPWR", 0 0, L_000000000404b6e0;  1 drivers, strength-aware
+v0000000003ba45c0_0 .net "Y", 0 0, L_000000000413fdb0;  alias, 1 drivers
+v0000000003ba4700_0 .net "and0_out", 0 0, L_0000000004140280;  1 drivers
+v0000000003ba4b60_0 .net "nor0_out_Y", 0 0, L_000000000413fcd0;  1 drivers
+S_0000000003bde470 .scope module, "_0873_" "sky130_fd_sc_hd__or2_2" 3 2532, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba7400_0 .net "A", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003ba63c0_0 .net "B", 0 0, L_000000000412f570;  alias, 1 drivers
+L_000000000404b9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba70e0_0 .net8 "VGND", 0 0, L_000000000404b9f0;  1 drivers, strength-aware
+L_000000000404b2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8620_0 .net8 "VNB", 0 0, L_000000000404b2f0;  1 drivers, strength-aware
+L_000000000404b360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6d20_0 .net8 "VPB", 0 0, L_000000000404b360;  1 drivers, strength-aware
+L_000000000404af70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6aa0_0 .net8 "VPWR", 0 0, L_000000000404af70;  1 drivers, strength-aware
+v0000000003ba6280_0 .net "X", 0 0, L_00000000041402f0;  alias, 1 drivers
+S_0000000003bd9670 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bde470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004140210 .functor OR 1, L_000000000412f570, L_0000000004131790, C4<0>, C4<0>;
+L_00000000041402f0 .functor BUF 1, L_0000000004140210, C4<0>, C4<0>, C4<0>;
+v0000000003ba83a0_0 .net "A", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003ba7720_0 .net "B", 0 0, L_000000000412f570;  alias, 1 drivers
+L_000000000404acd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba74a0_0 .net8 "VGND", 0 0, L_000000000404acd0;  1 drivers, strength-aware
+L_000000000404b750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6140_0 .net8 "VNB", 0 0, L_000000000404b750;  1 drivers, strength-aware
+L_000000000404a720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba88a0_0 .net8 "VPB", 0 0, L_000000000404a720;  1 drivers, strength-aware
+L_000000000404bf30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7e00_0 .net8 "VPWR", 0 0, L_000000000404bf30;  1 drivers, strength-aware
+v0000000003ba6be0_0 .net "X", 0 0, L_00000000041402f0;  alias, 1 drivers
+v0000000003ba6c80_0 .net "or0_out_X", 0 0, L_0000000004140210;  1 drivers
+S_0000000003bddff0 .scope module, "_0874_" "sky130_fd_sc_hd__or2_2" 3 2537, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba7860_0 .net "A", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003ba6820_0 .net "B", 0 0, L_0000000004134580;  alias, 1 drivers
+L_000000000404bfa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7c20_0 .net8 "VGND", 0 0, L_000000000404bfa0;  1 drivers, strength-aware
+L_000000000404ba60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8120_0 .net8 "VNB", 0 0, L_000000000404ba60;  1 drivers, strength-aware
+L_000000000404ab10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6500_0 .net8 "VPB", 0 0, L_000000000404ab10;  1 drivers, strength-aware
+L_000000000404ab80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7900_0 .net8 "VPWR", 0 0, L_000000000404ab80;  1 drivers, strength-aware
+v0000000003ba7fe0_0 .net "X", 0 0, L_0000000004140360;  alias, 1 drivers
+S_0000000003bdacf0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bddff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041408a0 .functor OR 1, L_0000000004134580, L_0000000004138170, C4<0>, C4<0>;
+L_0000000004140360 .functor BUF 1, L_00000000041408a0, C4<0>, C4<0>, C4<0>;
+v0000000003ba7540_0 .net "A", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003ba7680_0 .net "B", 0 0, L_0000000004134580;  alias, 1 drivers
+L_000000000404b3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8760_0 .net8 "VGND", 0 0, L_000000000404b3d0;  1 drivers, strength-aware
+L_000000000404a870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba77c0_0 .net8 "VNB", 0 0, L_000000000404a870;  1 drivers, strength-aware
+L_000000000404afe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba84e0_0 .net8 "VPB", 0 0, L_000000000404afe0;  1 drivers, strength-aware
+L_000000000404a8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba65a0_0 .net8 "VPWR", 0 0, L_000000000404a8e0;  1 drivers, strength-aware
+v0000000003ba6fa0_0 .net "X", 0 0, L_0000000004140360;  alias, 1 drivers
+v0000000003ba7a40_0 .net "or0_out_X", 0 0, L_00000000041408a0;  1 drivers
+S_0000000003bda9f0 .scope module, "_0875_" "sky130_fd_sc_hd__and2_2" 3 2542, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003ba7ae0_0 .net "A", 0 0, L_0000000004132bb0;  alias, 1 drivers
+v0000000003ba8300_0 .net "B", 0 0, L_0000000004140360;  alias, 1 drivers
+L_000000000404a950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba68c0_0 .net8 "VGND", 0 0, L_000000000404a950;  1 drivers, strength-aware
+L_000000000404b7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba66e0_0 .net8 "VNB", 0 0, L_000000000404b7c0;  1 drivers, strength-aware
+L_000000000404bad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8800_0 .net8 "VPB", 0 0, L_000000000404bad0;  1 drivers, strength-aware
+L_000000000404b050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6960_0 .net8 "VPWR", 0 0, L_000000000404b050;  1 drivers, strength-aware
+v0000000003ba8440_0 .net "X", 0 0, L_0000000004140910;  alias, 1 drivers
+S_0000000003bdd270 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003bda9f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041403d0 .functor AND 1, L_0000000004132bb0, L_0000000004140360, C4<1>, C4<1>;
+L_0000000004140910 .functor BUF 1, L_00000000041403d0, C4<0>, C4<0>, C4<0>;
+v0000000003ba81c0_0 .net "A", 0 0, L_0000000004132bb0;  alias, 1 drivers
+v0000000003ba8260_0 .net "B", 0 0, L_0000000004140360;  alias, 1 drivers
+L_000000000404b0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7f40_0 .net8 "VGND", 0 0, L_000000000404b0c0;  1 drivers, strength-aware
+L_000000000404c080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7b80_0 .net8 "VNB", 0 0, L_000000000404c080;  1 drivers, strength-aware
+L_000000000404b130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8580_0 .net8 "VPB", 0 0, L_000000000404b130;  1 drivers, strength-aware
+L_000000000404a790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba86c0_0 .net8 "VPWR", 0 0, L_000000000404a790;  1 drivers, strength-aware
+v0000000003ba79a0_0 .net "X", 0 0, L_0000000004140910;  alias, 1 drivers
+v0000000003ba6640_0 .net "and0_out_X", 0 0, L_00000000041403d0;  1 drivers
+S_0000000003bd9c70 .scope module, "_0876_" "sky130_fd_sc_hd__a21oi_2" 3 2547, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba7cc0_0 .net "A1", 0 0, L_0000000004136ab0;  alias, 1 drivers
+v0000000003ba7d60_0 .net "A2", 0 0, L_000000000413d7a0;  alias, 1 drivers
+v0000000003ba7040_0 .net "B1", 0 0, L_0000000004140910;  alias, 1 drivers
+L_000000000404aaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7220_0 .net8 "VGND", 0 0, L_000000000404aaa0;  1 drivers, strength-aware
+L_000000000404a4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba7ea0_0 .net8 "VNB", 0 0, L_000000000404a4f0;  1 drivers, strength-aware
+L_000000000404af00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9f20_0 .net8 "VPB", 0 0, L_000000000404af00;  1 drivers, strength-aware
+L_000000000404a560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9d40_0 .net8 "VPWR", 0 0, L_000000000404a560;  1 drivers, strength-aware
+v0000000003baaf60_0 .net "Y", 0 0, L_0000000004141940;  alias, 1 drivers
+S_0000000003bdba70 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003bd9c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041409f0 .functor AND 1, L_0000000004136ab0, L_000000000413d7a0, C4<1>, C4<1>;
+L_0000000004140a60 .functor NOR 1, L_0000000004140910, L_00000000041409f0, C4<0>, C4<0>;
+L_0000000004141940 .functor BUF 1, L_0000000004140a60, C4<0>, C4<0>, C4<0>;
+v0000000003ba7180_0 .net "A1", 0 0, L_0000000004136ab0;  alias, 1 drivers
+v0000000003ba6460_0 .net "A2", 0 0, L_000000000413d7a0;  alias, 1 drivers
+v0000000003ba61e0_0 .net "B1", 0 0, L_0000000004140910;  alias, 1 drivers
+L_000000000404a640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6320_0 .net8 "VGND", 0 0, L_000000000404a640;  1 drivers, strength-aware
+L_000000000404b1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6dc0_0 .net8 "VNB", 0 0, L_000000000404b1a0;  1 drivers, strength-aware
+L_000000000404b210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6780_0 .net8 "VPB", 0 0, L_000000000404b210;  1 drivers, strength-aware
+L_000000000404b280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba6a00_0 .net8 "VPWR", 0 0, L_000000000404b280;  1 drivers, strength-aware
+v0000000003ba6e60_0 .net "Y", 0 0, L_0000000004141940;  alias, 1 drivers
+v0000000003ba6b40_0 .net "and0_out", 0 0, L_00000000041409f0;  1 drivers
+v0000000003ba6f00_0 .net "nor0_out_Y", 0 0, L_0000000004140a60;  1 drivers
+S_0000000003bd9df0 .scope module, "_0877_" "sky130_fd_sc_hd__o21a_2" 3 2553, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba8ee0_0 .net "A1", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003ba9de0_0 .net "A2", 0 0, L_0000000004137ed0;  alias, 1 drivers
+v0000000003ba95c0_0 .net "B1", 0 0, L_0000000004132bb0;  alias, 1 drivers
+L_000000000404bb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baa880_0 .net8 "VGND", 0 0, L_000000000404bb40;  1 drivers, strength-aware
+L_000000000404a6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8c60_0 .net8 "VNB", 0 0, L_000000000404a6b0;  1 drivers, strength-aware
+L_000000000404a800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9700_0 .net8 "VPB", 0 0, L_000000000404a800;  1 drivers, strength-aware
+L_000000000404bbb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8da0_0 .net8 "VPWR", 0 0, L_000000000404bbb0;  1 drivers, strength-aware
+v0000000003ba9480_0 .net "X", 0 0, L_00000000041425f0;  alias, 1 drivers
+S_0000000003bded70 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003bd9df0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041419b0 .functor OR 1, L_0000000004137ed0, L_0000000004138170, C4<0>, C4<0>;
+L_00000000041426d0 .functor AND 1, L_00000000041419b0, L_0000000004132bb0, C4<1>, C4<1>;
+L_00000000041425f0 .functor BUF 1, L_00000000041426d0, C4<0>, C4<0>, C4<0>;
+v0000000003ba8d00_0 .net "A1", 0 0, L_0000000004138170;  alias, 1 drivers
+v0000000003baa060_0 .net "A2", 0 0, L_0000000004137ed0;  alias, 1 drivers
+v0000000003ba9020_0 .net "B1", 0 0, L_0000000004132bb0;  alias, 1 drivers
+L_000000000404b440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba97a0_0 .net8 "VGND", 0 0, L_000000000404b440;  1 drivers, strength-aware
+L_000000000404bd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baa920_0 .net8 "VNB", 0 0, L_000000000404bd00;  1 drivers, strength-aware
+L_000000000404ac60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9c00_0 .net8 "VPB", 0 0, L_000000000404ac60;  1 drivers, strength-aware
+L_000000000404a9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9ca0_0 .net8 "VPWR", 0 0, L_000000000404a9c0;  1 drivers, strength-aware
+v0000000003baa7e0_0 .net "X", 0 0, L_00000000041425f0;  alias, 1 drivers
+v0000000003baa1a0_0 .net "and0_out_X", 0 0, L_00000000041426d0;  1 drivers
+v0000000003ba9520_0 .net "or0_out", 0 0, L_00000000041419b0;  1 drivers
+S_0000000003bdbef0 .scope module, "_0878_" "sky130_fd_sc_hd__o21ai_2" 3 2559, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003baad80_0 .net "A1", 0 0, L_0000000004140360;  alias, 1 drivers
+v0000000003ba93e0_0 .net "A2", 0 0, L_000000000413ef40;  alias, 1 drivers
+v0000000003baace0_0 .net "B1", 0 0, L_00000000041425f0;  alias, 1 drivers
+L_000000000404aa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baa9c0_0 .net8 "VGND", 0 0, L_000000000404aa30;  1 drivers, strength-aware
+L_000000000404b590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baaec0_0 .net8 "VNB", 0 0, L_000000000404b590;  1 drivers, strength-aware
+L_000000000404abf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9660_0 .net8 "VPB", 0 0, L_000000000404abf0;  1 drivers, strength-aware
+L_000000000404ad40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9fc0_0 .net8 "VPWR", 0 0, L_000000000404ad40;  1 drivers, strength-aware
+v0000000003baae20_0 .net "Y", 0 0, L_0000000004141080;  alias, 1 drivers
+S_0000000003bdcc70 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003bdbef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004141be0 .functor OR 1, L_000000000413ef40, L_0000000004140360, C4<0>, C4<0>;
+L_0000000004142660 .functor NAND 1, L_00000000041425f0, L_0000000004141be0, C4<1>, C4<1>;
+L_0000000004141080 .functor BUF 1, L_0000000004142660, C4<0>, C4<0>, C4<0>;
+v0000000003ba90c0_0 .net "A1", 0 0, L_0000000004140360;  alias, 1 drivers
+v0000000003ba8e40_0 .net "A2", 0 0, L_000000000413ef40;  alias, 1 drivers
+v0000000003baa420_0 .net "B1", 0 0, L_00000000041425f0;  alias, 1 drivers
+L_000000000404b4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9200_0 .net8 "VGND", 0 0, L_000000000404b4b0;  1 drivers, strength-aware
+L_000000000404b520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8f80_0 .net8 "VNB", 0 0, L_000000000404b520;  1 drivers, strength-aware
+L_000000000404b600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9160_0 .net8 "VPB", 0 0, L_000000000404b600;  1 drivers, strength-aware
+L_000000000404bc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba92a0_0 .net8 "VPWR", 0 0, L_000000000404bc20;  1 drivers, strength-aware
+v0000000003baa6a0_0 .net "Y", 0 0, L_0000000004141080;  alias, 1 drivers
+v0000000003ba9ac0_0 .net "nand0_out_Y", 0 0, L_0000000004142660;  1 drivers
+v0000000003ba9340_0 .net "or0_out", 0 0, L_0000000004141be0;  1 drivers
+S_0000000003bdcaf0 .scope module, "_0879_" "sky130_fd_sc_hd__a21o_2" 3 2565, 4 46093 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003ba9a20_0 .net "A1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003baa4c0_0 .net "A2", 0 0, L_0000000004141940;  alias, 1 drivers
+v0000000003ba9b60_0 .net "B1", 0 0, L_0000000004141080;  alias, 1 drivers
+L_000000000404bc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9e80_0 .net8 "VGND", 0 0, L_000000000404bc90;  1 drivers, strength-aware
+L_000000000404bd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baa100_0 .net8 "VNB", 0 0, L_000000000404bd70;  1 drivers, strength-aware
+L_000000000404ce10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baa740_0 .net8 "VPB", 0 0, L_000000000404ce10;  1 drivers, strength-aware
+L_000000000404d9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baa560_0 .net8 "VPWR", 0 0, L_000000000404d9e0;  1 drivers, strength-aware
+v0000000003baa600_0 .net "X", 0 0, L_0000000004141320;  alias, 1 drivers
+S_0000000003bdd3f0 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46111, 4 46415 1, S_0000000003bdcaf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004141e10 .functor AND 1, L_000000000413a390, L_0000000004141940, C4<1>, C4<1>;
+L_0000000004140f30 .functor OR 1, L_0000000004141e10, L_0000000004141080, C4<0>, C4<0>;
+L_0000000004141320 .functor BUF 1, L_0000000004140f30, C4<0>, C4<0>, C4<0>;
+v0000000003bab000_0 .net "A1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003ba9840_0 .net "A2", 0 0, L_0000000004141940;  alias, 1 drivers
+v0000000003bab0a0_0 .net "B1", 0 0, L_0000000004141080;  alias, 1 drivers
+L_000000000404cfd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8940_0 .net8 "VGND", 0 0, L_000000000404cfd0;  1 drivers, strength-aware
+L_000000000404d510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba98e0_0 .net8 "VNB", 0 0, L_000000000404d510;  1 drivers, strength-aware
+L_000000000404c470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baaa60_0 .net8 "VPB", 0 0, L_000000000404c470;  1 drivers, strength-aware
+L_000000000404c550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba9980_0 .net8 "VPWR", 0 0, L_000000000404c550;  1 drivers, strength-aware
+v0000000003baa240_0 .net "X", 0 0, L_0000000004141320;  alias, 1 drivers
+v0000000003baa2e0_0 .net "and0_out", 0 0, L_0000000004141e10;  1 drivers
+v0000000003baa380_0 .net "or0_out_X", 0 0, L_0000000004140f30;  1 drivers
+S_0000000003bdc7f0 .scope module, "_0880_" "sky130_fd_sc_hd__a2bb2o_2" 3 2571, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bac040_0 .net "A1_N", 0 0, L_00000000041402f0;  alias, 1 drivers
+v0000000003bacfe0_0 .net "A2_N", 0 0, L_0000000004141320;  alias, 1 drivers
+v0000000003bab280_0 .net "B1", 0 0, L_00000000041402f0;  alias, 1 drivers
+v0000000003bac900_0 .net "B2", 0 0, L_0000000004141320;  alias, 1 drivers
+L_000000000404d900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bad6c0_0 .net8 "VGND", 0 0, L_000000000404d900;  1 drivers, strength-aware
+L_000000000404c860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bad260_0 .net8 "VNB", 0 0, L_000000000404c860;  1 drivers, strength-aware
+L_000000000404c4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baba00_0 .net8 "VPB", 0 0, L_000000000404c4e0;  1 drivers, strength-aware
+L_000000000404dc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003babc80_0 .net8 "VPWR", 0 0, L_000000000404dc80;  1 drivers, strength-aware
+v0000000003bad080_0 .net "X", 0 0, L_0000000004142580;  alias, 1 drivers
+S_0000000003bd9070 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003bdc7f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004142270 .functor AND 1, L_00000000041402f0, L_0000000004141320, C4<1>, C4<1>;
+L_0000000004141e80 .functor NOR 1, L_00000000041402f0, L_0000000004141320, C4<0>, C4<0>;
+L_0000000004140de0 .functor OR 1, L_0000000004141e80, L_0000000004142270, C4<0>, C4<0>;
+L_0000000004142580 .functor BUF 1, L_0000000004140de0, C4<0>, C4<0>, C4<0>;
+v0000000003ba89e0_0 .net "A1_N", 0 0, L_00000000041402f0;  alias, 1 drivers
+v0000000003baab00_0 .net "A2_N", 0 0, L_0000000004141320;  alias, 1 drivers
+v0000000003baaba0_0 .net "B1", 0 0, L_00000000041402f0;  alias, 1 drivers
+v0000000003ba8a80_0 .net "B2", 0 0, L_0000000004141320;  alias, 1 drivers
+L_000000000404d190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baac40_0 .net8 "VGND", 0 0, L_000000000404d190;  1 drivers, strength-aware
+L_000000000404dba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8b20_0 .net8 "VNB", 0 0, L_000000000404dba0;  1 drivers, strength-aware
+L_000000000404c6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ba8bc0_0 .net8 "VPB", 0 0, L_000000000404c6a0;  1 drivers, strength-aware
+L_000000000404cf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bacf40_0 .net8 "VPWR", 0 0, L_000000000404cf60;  1 drivers, strength-aware
+v0000000003bad800_0 .net "X", 0 0, L_0000000004142580;  alias, 1 drivers
+v0000000003babd20_0 .net "and0_out", 0 0, L_0000000004142270;  1 drivers
+v0000000003bacd60_0 .net "nor0_out", 0 0, L_0000000004141e80;  1 drivers
+v0000000003bac400_0 .net "or0_out_X", 0 0, L_0000000004140de0;  1 drivers
+S_0000000003bdae70 .scope module, "_0881_" "sky130_fd_sc_hd__a2bb2o_2" 3 2578, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bad8a0_0 .net "A1_N", 0 0, L_000000000413f870;  alias, 1 drivers
+v0000000003babe60_0 .net "A2_N", 0 0, L_0000000004142580;  alias, 1 drivers
+v0000000003bad440_0 .net "B1", 0 0, L_000000000413f870;  alias, 1 drivers
+v0000000003bac220_0 .net "B2", 0 0, L_0000000004142580;  alias, 1 drivers
+L_000000000404c2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab8c0_0 .net8 "VGND", 0 0, L_000000000404c2b0;  1 drivers, strength-aware
+L_000000000404dac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab5a0_0 .net8 "VNB", 0 0, L_000000000404dac0;  1 drivers, strength-aware
+L_000000000404ca90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bacea0_0 .net8 "VPB", 0 0, L_000000000404ca90;  1 drivers, strength-aware
+L_000000000404d040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bac2c0_0 .net8 "VPWR", 0 0, L_000000000404d040;  1 drivers, strength-aware
+v0000000003bac360_0 .net "X", 0 0, L_0000000004141400;  alias, 1 drivers
+S_0000000003bdd6f0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003bdae70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041410f0 .functor AND 1, L_000000000413f870, L_0000000004142580, C4<1>, C4<1>;
+L_00000000041411d0 .functor NOR 1, L_000000000413f870, L_0000000004142580, C4<0>, C4<0>;
+L_0000000004141010 .functor OR 1, L_00000000041411d0, L_00000000041410f0, C4<0>, C4<0>;
+L_0000000004141400 .functor BUF 1, L_0000000004141010, C4<0>, C4<0>, C4<0>;
+v0000000003bad1c0_0 .net "A1_N", 0 0, L_000000000413f870;  alias, 1 drivers
+v0000000003bad120_0 .net "A2_N", 0 0, L_0000000004142580;  alias, 1 drivers
+v0000000003bad300_0 .net "B1", 0 0, L_000000000413f870;  alias, 1 drivers
+v0000000003babf00_0 .net "B2", 0 0, L_0000000004142580;  alias, 1 drivers
+L_000000000404d820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bacb80_0 .net8 "VGND", 0 0, L_000000000404d820;  1 drivers, strength-aware
+L_000000000404ce80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003babdc0_0 .net8 "VNB", 0 0, L_000000000404ce80;  1 drivers, strength-aware
+L_000000000404da50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bad4e0_0 .net8 "VPB", 0 0, L_000000000404da50;  1 drivers, strength-aware
+L_000000000404d0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bac9a0_0 .net8 "VPWR", 0 0, L_000000000404d0b0;  1 drivers, strength-aware
+v0000000003bab640_0 .net "X", 0 0, L_0000000004141400;  alias, 1 drivers
+v0000000003bac0e0_0 .net "and0_out", 0 0, L_00000000041410f0;  1 drivers
+v0000000003baca40_0 .net "nor0_out", 0 0, L_00000000041411d0;  1 drivers
+v0000000003bad3a0_0 .net "or0_out_X", 0 0, L_0000000004141010;  1 drivers
+S_0000000003bdb470 .scope module, "_0882_" "sky130_fd_sc_hd__inv_2" 3 2585, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bab1e0_0 .net "A", 0 0, L_0000000004130760;  alias, 1 drivers
+L_000000000404d580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab820_0 .net8 "VGND", 0 0, L_000000000404d580;  1 drivers, strength-aware
+L_000000000404c5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab320_0 .net8 "VNB", 0 0, L_000000000404c5c0;  1 drivers, strength-aware
+L_000000000404c630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bad580_0 .net8 "VPB", 0 0, L_000000000404c630;  1 drivers, strength-aware
+L_000000000404d430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bacae0_0 .net8 "VPWR", 0 0, L_000000000404d430;  1 drivers, strength-aware
+v0000000003bab3c0_0 .net "Y", 0 0, L_0000000004141f60;  alias, 1 drivers
+S_0000000003bdaff0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003bdb470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004141860 .functor NOT 1, L_0000000004130760, C4<0>, C4<0>, C4<0>;
+L_0000000004141f60 .functor BUF 1, L_0000000004141860, C4<0>, C4<0>, C4<0>;
+v0000000003bad760_0 .net "A", 0 0, L_0000000004130760;  alias, 1 drivers
+L_000000000404d4a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bac720_0 .net8 "VGND", 0 0, L_000000000404d4a0;  1 drivers, strength-aware
+L_000000000404c1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bad620_0 .net8 "VNB", 0 0, L_000000000404c1d0;  1 drivers, strength-aware
+L_000000000404d5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bab140_0 .net8 "VPB", 0 0, L_000000000404d5f0;  1 drivers, strength-aware
+L_000000000404d270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bace00_0 .net8 "VPWR", 0 0, L_000000000404d270;  1 drivers, strength-aware
+v0000000003bacc20_0 .net "Y", 0 0, L_0000000004141f60;  alias, 1 drivers
+v0000000003baccc0_0 .net "not0_out_Y", 0 0, L_0000000004141860;  1 drivers
+S_0000000003bdcdf0 .scope module, "_0883_" "sky130_fd_sc_hd__or2_2" 3 2589, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003babaa0_0 .net "A", 0 0, L_0000000004141f60;  alias, 1 drivers
+v0000000003babb40_0 .net "B", 0 0, L_00000000041300d0;  alias, 1 drivers
+L_000000000404db30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003babbe0_0 .net8 "VGND", 0 0, L_000000000404db30;  1 drivers, strength-aware
+L_000000000404dc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003babfa0_0 .net8 "VNB", 0 0, L_000000000404dc10;  1 drivers, strength-aware
+L_000000000404d2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bac180_0 .net8 "VPB", 0 0, L_000000000404d2e0;  1 drivers, strength-aware
+L_000000000404d660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bac540_0 .net8 "VPWR", 0 0, L_000000000404d660;  1 drivers, strength-aware
+v0000000003bac860_0 .net "X", 0 0, L_0000000004141240;  alias, 1 drivers
+S_0000000003bdb5f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bdcdf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004140fa0 .functor OR 1, L_00000000041300d0, L_0000000004141f60, C4<0>, C4<0>;
+L_0000000004141240 .functor BUF 1, L_0000000004140fa0, C4<0>, C4<0>, C4<0>;
+v0000000003bac680_0 .net "A", 0 0, L_0000000004141f60;  alias, 1 drivers
+v0000000003bab460_0 .net "B", 0 0, L_00000000041300d0;  alias, 1 drivers
+L_000000000404cef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab500_0 .net8 "VGND", 0 0, L_000000000404cef0;  1 drivers, strength-aware
+L_000000000404d120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bab960_0 .net8 "VNB", 0 0, L_000000000404d120;  1 drivers, strength-aware
+L_000000000404cb70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bac7c0_0 .net8 "VPB", 0 0, L_000000000404cb70;  1 drivers, strength-aware
+L_000000000404c8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bab6e0_0 .net8 "VPWR", 0 0, L_000000000404c8d0;  1 drivers, strength-aware
+v0000000003bac4a0_0 .net "X", 0 0, L_0000000004141240;  alias, 1 drivers
+v0000000003bab780_0 .net "or0_out_X", 0 0, L_0000000004140fa0;  1 drivers
+S_0000000003bd91f0 .scope module, "_0884_" "sky130_fd_sc_hd__inv_2" 3 2594, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bada80_0 .net "A", 0 0, L_000000000413f2c0;  alias, 1 drivers
+L_000000000404d350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baf100_0 .net8 "VGND", 0 0, L_000000000404d350;  1 drivers, strength-aware
+L_000000000404c320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baf4c0_0 .net8 "VNB", 0 0, L_000000000404c320;  1 drivers, strength-aware
+L_000000000404c0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae200_0 .net8 "VPB", 0 0, L_000000000404c0f0;  1 drivers, strength-aware
+L_000000000404c160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae480_0 .net8 "VPWR", 0 0, L_000000000404c160;  1 drivers, strength-aware
+v0000000003baf560_0 .net "Y", 0 0, L_0000000004141160;  alias, 1 drivers
+S_0000000003bd9370 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003bd91f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041415c0 .functor NOT 1, L_000000000413f2c0, C4<0>, C4<0>, C4<0>;
+L_0000000004141160 .functor BUF 1, L_00000000041415c0, C4<0>, C4<0>, C4<0>;
+v0000000003bac5e0_0 .net "A", 0 0, L_000000000413f2c0;  alias, 1 drivers
+L_000000000404d6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bae520_0 .net8 "VGND", 0 0, L_000000000404d6d0;  1 drivers, strength-aware
+L_000000000404c710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baf420_0 .net8 "VNB", 0 0, L_000000000404c710;  1 drivers, strength-aware
+L_000000000404c780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003badbc0_0 .net8 "VPB", 0 0, L_000000000404c780;  1 drivers, strength-aware
+L_000000000404d200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae8e0_0 .net8 "VPWR", 0 0, L_000000000404d200;  1 drivers, strength-aware
+v0000000003bafe20_0 .net "Y", 0 0, L_0000000004141160;  alias, 1 drivers
+v0000000003bae3e0_0 .net "not0_out_Y", 0 0, L_00000000041415c0;  1 drivers
+S_0000000003bdc070 .scope module, "_0885_" "sky130_fd_sc_hd__or2_2" 3 2598, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003baf240_0 .net "A", 0 0, L_00000000041393d0;  alias, 1 drivers
+v0000000003baf600_0 .net "B", 0 0, L_00000000041402f0;  alias, 1 drivers
+L_000000000404c7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baf740_0 .net8 "VGND", 0 0, L_000000000404c7f0;  1 drivers, strength-aware
+L_000000000404cbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bafec0_0 .net8 "VNB", 0 0, L_000000000404cbe0;  1 drivers, strength-aware
+L_000000000404c940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae340_0 .net8 "VPB", 0 0, L_000000000404c940;  1 drivers, strength-aware
+L_000000000404c9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baf2e0_0 .net8 "VPWR", 0 0, L_000000000404c9b0;  1 drivers, strength-aware
+v0000000003baeca0_0 .net "X", 0 0, L_0000000004142120;  alias, 1 drivers
+S_0000000003bdcf70 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bdc070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004141550 .functor OR 1, L_00000000041402f0, L_00000000041393d0, C4<0>, C4<0>;
+L_0000000004142120 .functor BUF 1, L_0000000004141550, C4<0>, C4<0>, C4<0>;
+v0000000003badee0_0 .net "A", 0 0, L_00000000041393d0;  alias, 1 drivers
+v0000000003baea20_0 .net "B", 0 0, L_00000000041402f0;  alias, 1 drivers
+L_000000000404d3c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0000_0 .net8 "VGND", 0 0, L_000000000404d3c0;  1 drivers, strength-aware
+L_000000000404d740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baf1a0_0 .net8 "VNB", 0 0, L_000000000404d740;  1 drivers, strength-aware
+L_000000000404cc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003badd00_0 .net8 "VPB", 0 0, L_000000000404cc50;  1 drivers, strength-aware
+L_000000000404ccc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae2a0_0 .net8 "VPWR", 0 0, L_000000000404ccc0;  1 drivers, strength-aware
+v0000000003bae020_0 .net "X", 0 0, L_0000000004142120;  alias, 1 drivers
+v0000000003bae7a0_0 .net "or0_out_X", 0 0, L_0000000004141550;  1 drivers
+S_0000000003bd9f70 .scope module, "_0886_" "sky130_fd_sc_hd__inv_2" 3 2603, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bae0c0_0 .net "A", 0 0, L_0000000004142120;  alias, 1 drivers
+L_000000000404c240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bafa60_0 .net8 "VGND", 0 0, L_000000000404c240;  1 drivers, strength-aware
+L_000000000404cd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003badb20_0 .net8 "VNB", 0 0, L_000000000404cd30;  1 drivers, strength-aware
+L_000000000404c390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baf880_0 .net8 "VPB", 0 0, L_000000000404c390;  1 drivers, strength-aware
+L_000000000404ca20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baf6a0_0 .net8 "VPWR", 0 0, L_000000000404ca20;  1 drivers, strength-aware
+v0000000003baf380_0 .net "Y", 0 0, L_0000000004140d00;  alias, 1 drivers
+S_0000000003bdb770 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003bd9f70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041412b0 .functor NOT 1, L_0000000004142120, C4<0>, C4<0>, C4<0>;
+L_0000000004140d00 .functor BUF 1, L_00000000041412b0, C4<0>, C4<0>, C4<0>;
+v0000000003baed40_0 .net "A", 0 0, L_0000000004142120;  alias, 1 drivers
+L_000000000404d7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baec00_0 .net8 "VGND", 0 0, L_000000000404d7b0;  1 drivers, strength-aware
+L_000000000404d890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bae160_0 .net8 "VNB", 0 0, L_000000000404d890;  1 drivers, strength-aware
+L_000000000404d970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bad9e0_0 .net8 "VPB", 0 0, L_000000000404d970;  1 drivers, strength-aware
+L_000000000404c400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bae840_0 .net8 "VPWR", 0 0, L_000000000404c400;  1 drivers, strength-aware
+v0000000003baf7e0_0 .net "Y", 0 0, L_0000000004140d00;  alias, 1 drivers
+v0000000003baf9c0_0 .net "not0_out_Y", 0 0, L_00000000041412b0;  1 drivers
+S_0000000003bdd0f0 .scope module, "_0887_" "sky130_fd_sc_hd__o21ai_2" 3 2607, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bae700_0 .net "A1", 0 0, L_00000000041311e0;  alias, 1 drivers
+v0000000003bafc40_0 .net "A2", 0 0, L_0000000004141160;  alias, 1 drivers
+v0000000003badf80_0 .net "B1", 0 0, L_0000000004140d00;  alias, 1 drivers
+L_000000000404cb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003baef20_0 .net8 "VGND", 0 0, L_000000000404cb00;  1 drivers, strength-aware
+L_000000000404cda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bae980_0 .net8 "VNB", 0 0, L_000000000404cda0;  1 drivers, strength-aware
+L_000000000404f730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bafce0_0 .net8 "VPB", 0 0, L_000000000404f730;  1 drivers, strength-aware
+L_000000000404f0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bafd80_0 .net8 "VPWR", 0 0, L_000000000404f0a0;  1 drivers, strength-aware
+v0000000003baeac0_0 .net "Y", 0 0, L_0000000004141fd0;  alias, 1 drivers
+S_0000000003bde5f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003bdd0f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004141b00 .functor OR 1, L_0000000004141160, L_00000000041311e0, C4<0>, C4<0>;
+L_0000000004141390 .functor NAND 1, L_0000000004140d00, L_0000000004141b00, C4<1>, C4<1>;
+L_0000000004141fd0 .functor BUF 1, L_0000000004141390, C4<0>, C4<0>, C4<0>;
+v0000000003bb00a0_0 .net "A1", 0 0, L_00000000041311e0;  alias, 1 drivers
+v0000000003bafba0_0 .net "A2", 0 0, L_0000000004141160;  alias, 1 drivers
+v0000000003badda0_0 .net "B1", 0 0, L_0000000004140d00;  alias, 1 drivers
+L_000000000404eee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bae5c0_0 .net8 "VGND", 0 0, L_000000000404eee0;  1 drivers, strength-aware
+L_000000000404f3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bae660_0 .net8 "VNB", 0 0, L_000000000404f3b0;  1 drivers, strength-aware
+L_000000000404ee00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003badc60_0 .net8 "VPB", 0 0, L_000000000404ee00;  1 drivers, strength-aware
+L_000000000404e4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baf920_0 .net8 "VPWR", 0 0, L_000000000404e4d0;  1 drivers, strength-aware
+v0000000003baede0_0 .net "Y", 0 0, L_0000000004141fd0;  alias, 1 drivers
+v0000000003baee80_0 .net "nand0_out_Y", 0 0, L_0000000004141390;  1 drivers
+v0000000003bafb00_0 .net "or0_out", 0 0, L_0000000004141b00;  1 drivers
+S_0000000003bd94f0 .scope module, "_0888_" "sky130_fd_sc_hd__o21ai_2" 3 2613, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bb10e0_0 .net "A1", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003bb03c0_0 .net "A2", 0 0, L_000000000413f5d0;  alias, 1 drivers
+v0000000003bb0460_0 .net "B1", 0 0, L_0000000004130680;  alias, 1 drivers
+L_000000000404df90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1040_0 .net8 "VGND", 0 0, L_000000000404df90;  1 drivers, strength-aware
+L_000000000404e5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2260_0 .net8 "VNB", 0 0, L_000000000404e5b0;  1 drivers, strength-aware
+L_000000000404ec40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2080_0 .net8 "VPB", 0 0, L_000000000404ec40;  1 drivers, strength-aware
+L_000000000404ea10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb26c0_0 .net8 "VPWR", 0 0, L_000000000404ea10;  1 drivers, strength-aware
+v0000000003bb2760_0 .net "Y", 0 0, L_0000000004141c50;  alias, 1 drivers
+S_0000000003bdc1f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003bd94f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004142200 .functor OR 1, L_000000000413f5d0, L_0000000004131020, C4<0>, C4<0>;
+L_0000000004141780 .functor NAND 1, L_0000000004130680, L_0000000004142200, C4<1>, C4<1>;
+L_0000000004141c50 .functor BUF 1, L_0000000004141780, C4<0>, C4<0>, C4<0>;
+v0000000003baefc0_0 .net "A1", 0 0, L_0000000004131020;  alias, 1 drivers
+v0000000003baeb60_0 .net "A2", 0 0, L_000000000413f5d0;  alias, 1 drivers
+v0000000003baff60_0 .net "B1", 0 0, L_0000000004130680;  alias, 1 drivers
+L_000000000404e620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bad940_0 .net8 "VGND", 0 0, L_000000000404e620;  1 drivers, strength-aware
+L_000000000404e930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bade40_0 .net8 "VNB", 0 0, L_000000000404e930;  1 drivers, strength-aware
+L_000000000404e000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003baf060_0 .net8 "VPB", 0 0, L_000000000404e000;  1 drivers, strength-aware
+L_000000000404ee70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0500_0 .net8 "VPWR", 0 0, L_000000000404ee70;  1 drivers, strength-aware
+v0000000003bb08c0_0 .net "Y", 0 0, L_0000000004141c50;  alias, 1 drivers
+v0000000003bb0fa0_0 .net "nand0_out_Y", 0 0, L_0000000004141780;  1 drivers
+v0000000003bb1ea0_0 .net "or0_out", 0 0, L_0000000004142200;  1 drivers
+S_0000000003bddb70 .scope module, "_0889_" "sky130_fd_sc_hd__and2_2" 3 2619, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bb0d20_0 .net "A", 0 0, L_0000000004141fd0;  alias, 1 drivers
+v0000000003bb0e60_0 .net "B", 0 0, L_0000000004141c50;  alias, 1 drivers
+L_000000000404ecb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1b80_0 .net8 "VGND", 0 0, L_000000000404ecb0;  1 drivers, strength-aware
+L_000000000404f2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0820_0 .net8 "VNB", 0 0, L_000000000404f2d0;  1 drivers, strength-aware
+L_000000000404f110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb05a0_0 .net8 "VPB", 0 0, L_000000000404f110;  1 drivers, strength-aware
+L_000000000404ef50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0280_0 .net8 "VPWR", 0 0, L_000000000404ef50;  1 drivers, strength-aware
+v0000000003bb2800_0 .net "X", 0 0, L_0000000004141b70;  alias, 1 drivers
+S_0000000003bdd870 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003bddb70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142740 .functor AND 1, L_0000000004141fd0, L_0000000004141c50, C4<1>, C4<1>;
+L_0000000004141b70 .functor BUF 1, L_0000000004142740, C4<0>, C4<0>, C4<0>;
+v0000000003bb1cc0_0 .net "A", 0 0, L_0000000004141fd0;  alias, 1 drivers
+v0000000003bb1720_0 .net "B", 0 0, L_0000000004141c50;  alias, 1 drivers
+L_000000000404f7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb28a0_0 .net8 "VGND", 0 0, L_000000000404f7a0;  1 drivers, strength-aware
+L_000000000404f810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1180_0 .net8 "VNB", 0 0, L_000000000404f810;  1 drivers, strength-aware
+L_000000000404f180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0140_0 .net8 "VPB", 0 0, L_000000000404f180;  1 drivers, strength-aware
+L_000000000404efc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb24e0_0 .net8 "VPWR", 0 0, L_000000000404efc0;  1 drivers, strength-aware
+v0000000003bb0f00_0 .net "X", 0 0, L_0000000004141b70;  alias, 1 drivers
+v0000000003bb01e0_0 .net "and0_out_X", 0 0, L_0000000004142740;  1 drivers
+S_0000000003bde170 .scope module, "_0890_" "sky130_fd_sc_hd__or2_2" 3 2624, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bb1d60_0 .net "A", 0 0, L_000000000413e680;  alias, 1 drivers
+v0000000003bb0780_0 .net "B", 0 0, L_0000000004141b70;  alias, 1 drivers
+L_000000000404f420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb15e0_0 .net8 "VGND", 0 0, L_000000000404f420;  1 drivers, strength-aware
+L_000000000404f030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1360_0 .net8 "VNB", 0 0, L_000000000404f030;  1 drivers, strength-aware
+L_000000000404e770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1c20_0 .net8 "VPB", 0 0, L_000000000404e770;  1 drivers, strength-aware
+L_000000000404e1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1e00_0 .net8 "VPWR", 0 0, L_000000000404e1c0;  1 drivers, strength-aware
+v0000000003bb1f40_0 .net "X", 0 0, L_00000000041417f0;  alias, 1 drivers
+S_0000000003bdbd70 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bde170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004141630 .functor OR 1, L_0000000004141b70, L_000000000413e680, C4<0>, C4<0>;
+L_00000000041417f0 .functor BUF 1, L_0000000004141630, C4<0>, C4<0>, C4<0>;
+v0000000003bb2580_0 .net "A", 0 0, L_000000000413e680;  alias, 1 drivers
+v0000000003bb0640_0 .net "B", 0 0, L_0000000004141b70;  alias, 1 drivers
+L_000000000404f570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1ae0_0 .net8 "VGND", 0 0, L_000000000404f570;  1 drivers, strength-aware
+L_000000000404e070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb06e0_0 .net8 "VNB", 0 0, L_000000000404e070;  1 drivers, strength-aware
+L_000000000404f1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb19a0_0 .net8 "VPB", 0 0, L_000000000404f1f0;  1 drivers, strength-aware
+L_000000000404e540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1fe0_0 .net8 "VPWR", 0 0, L_000000000404e540;  1 drivers, strength-aware
+v0000000003bb1a40_0 .net "X", 0 0, L_00000000041417f0;  alias, 1 drivers
+v0000000003bb23a0_0 .net "or0_out_X", 0 0, L_0000000004141630;  1 drivers
+S_0000000003bd97f0 .scope module, "_0891_" "sky130_fd_sc_hd__o21ai_2" 3 2629, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bb17c0_0 .net "A1", 0 0, L_0000000004140750;  alias, 1 drivers
+v0000000003bb0b40_0 .net "A2", 0 0, L_0000000004142120;  alias, 1 drivers
+v0000000003bb2620_0 .net "B1", 0 0, L_0000000004141c50;  alias, 1 drivers
+L_000000000404ed20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0be0_0 .net8 "VGND", 0 0, L_000000000404ed20;  1 drivers, strength-aware
+L_000000000404f5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb12c0_0 .net8 "VNB", 0 0, L_000000000404f5e0;  1 drivers, strength-aware
+L_000000000404f260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1400_0 .net8 "VPB", 0 0, L_000000000404f260;  1 drivers, strength-aware
+L_000000000404f340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2300_0 .net8 "VPWR", 0 0, L_000000000404f340;  1 drivers, strength-aware
+v0000000003bb14a0_0 .net "Y", 0 0, L_0000000004142890;  alias, 1 drivers
+S_0000000003bdc370 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003bd97f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004140d70 .functor OR 1, L_0000000004142120, L_0000000004140750, C4<0>, C4<0>;
+L_0000000004141470 .functor NAND 1, L_0000000004141c50, L_0000000004140d70, C4<1>, C4<1>;
+L_0000000004142890 .functor BUF 1, L_0000000004141470, C4<0>, C4<0>, C4<0>;
+v0000000003bb1540_0 .net "A1", 0 0, L_0000000004140750;  alias, 1 drivers
+v0000000003bb0960_0 .net "A2", 0 0, L_0000000004142120;  alias, 1 drivers
+v0000000003bb2120_0 .net "B1", 0 0, L_0000000004141c50;  alias, 1 drivers
+L_000000000404f500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0320_0 .net8 "VGND", 0 0, L_000000000404f500;  1 drivers, strength-aware
+L_000000000404f490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb0c80_0 .net8 "VNB", 0 0, L_000000000404f490;  1 drivers, strength-aware
+L_000000000404e690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb21c0_0 .net8 "VPB", 0 0, L_000000000404e690;  1 drivers, strength-aware
+L_000000000404e850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1220_0 .net8 "VPWR", 0 0, L_000000000404e850;  1 drivers, strength-aware
+v0000000003bb0a00_0 .net "Y", 0 0, L_0000000004142890;  alias, 1 drivers
+v0000000003bb0aa0_0 .net "nand0_out_Y", 0 0, L_0000000004141470;  1 drivers
+v0000000003bb0dc0_0 .net "or0_out", 0 0, L_0000000004140d70;  1 drivers
+S_0000000003bdbbf0 .scope module, "_0892_" "sky130_fd_sc_hd__inv_2" 3 2635, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bb4420_0 .net "A", 0 0, L_0000000004142890;  alias, 1 drivers
+L_000000000404eaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3520_0 .net8 "VGND", 0 0, L_000000000404eaf0;  1 drivers, strength-aware
+L_000000000404f650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3840_0 .net8 "VNB", 0 0, L_000000000404f650;  1 drivers, strength-aware
+L_000000000404f6c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb37a0_0 .net8 "VPB", 0 0, L_000000000404f6c0;  1 drivers, strength-aware
+L_000000000404e2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3e80_0 .net8 "VPWR", 0 0, L_000000000404e2a0;  1 drivers, strength-aware
+v0000000003bb2c60_0 .net "Y", 0 0, L_0000000004140e50;  alias, 1 drivers
+S_0000000003bdd9f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003bdbbf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041423c0 .functor NOT 1, L_0000000004142890, C4<0>, C4<0>, C4<0>;
+L_0000000004140e50 .functor BUF 1, L_00000000041423c0, C4<0>, C4<0>, C4<0>;
+v0000000003bb1680_0 .net "A", 0 0, L_0000000004142890;  alias, 1 drivers
+L_000000000404e8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1860_0 .net8 "VGND", 0 0, L_000000000404e8c0;  1 drivers, strength-aware
+L_000000000404f880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb1900_0 .net8 "VNB", 0 0, L_000000000404f880;  1 drivers, strength-aware
+L_000000000404dcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2440_0 .net8 "VPB", 0 0, L_000000000404dcf0;  1 drivers, strength-aware
+L_000000000404dd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4e20_0 .net8 "VPWR", 0 0, L_000000000404dd60;  1 drivers, strength-aware
+v0000000003bb42e0_0 .net "Y", 0 0, L_0000000004140e50;  alias, 1 drivers
+v0000000003bb3660_0 .net "not0_out_Y", 0 0, L_00000000041423c0;  1 drivers
+S_0000000003bdb8f0 .scope module, "_0893_" "sky130_fd_sc_hd__o221a_2" 3 2639, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003bb35c0_0 .net "A1", 0 0, L_000000000413ed10;  alias, 1 drivers
+v0000000003bb4600_0 .net "A2", 0 0, L_0000000004141fd0;  alias, 1 drivers
+v0000000003bb3c00_0 .net "B1", 0 0, L_000000000413cd20;  alias, 1 drivers
+v0000000003bb2bc0_0 .net "B2", 0 0, L_00000000041417f0;  alias, 1 drivers
+v0000000003bb3160_0 .net "C1", 0 0, L_0000000004140e50;  alias, 1 drivers
+L_000000000404e700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3480_0 .net8 "VGND", 0 0, L_000000000404e700;  1 drivers, strength-aware
+L_000000000404ddd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4ec0_0 .net8 "VNB", 0 0, L_000000000404ddd0;  1 drivers, strength-aware
+L_000000000404eb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb33e0_0 .net8 "VPB", 0 0, L_000000000404eb60;  1 drivers, strength-aware
+L_000000000404de40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb47e0_0 .net8 "VPWR", 0 0, L_000000000404de40;  1 drivers, strength-aware
+v0000000003bb2a80_0 .net "X", 0 0, L_0000000004140ec0;  alias, 1 drivers
+S_0000000003bde2f0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003bdb8f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041427b0 .functor OR 1, L_00000000041417f0, L_000000000413cd20, C4<0>, C4<0>;
+L_0000000004142430 .functor OR 1, L_0000000004141fd0, L_000000000413ed10, C4<0>, C4<0>;
+L_00000000041414e0 .functor AND 1, L_00000000041427b0, L_0000000004142430, L_0000000004140e50, C4<1>;
+L_0000000004140ec0 .functor BUF 1, L_00000000041414e0, C4<0>, C4<0>, C4<0>;
+v0000000003bb3b60_0 .net "A1", 0 0, L_000000000413ed10;  alias, 1 drivers
+v0000000003bb41a0_0 .net "A2", 0 0, L_0000000004141fd0;  alias, 1 drivers
+v0000000003bb2b20_0 .net "B1", 0 0, L_000000000413cd20;  alias, 1 drivers
+v0000000003bb4c40_0 .net "B2", 0 0, L_00000000041417f0;  alias, 1 drivers
+v0000000003bb4100_0 .net "C1", 0 0, L_0000000004140e50;  alias, 1 drivers
+L_000000000404deb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4740_0 .net8 "VGND", 0 0, L_000000000404deb0;  1 drivers, strength-aware
+L_000000000404e9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4560_0 .net8 "VNB", 0 0, L_000000000404e9a0;  1 drivers, strength-aware
+L_000000000404df20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4ba0_0 .net8 "VPB", 0 0, L_000000000404df20;  1 drivers, strength-aware
+L_000000000404e310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb38e0_0 .net8 "VPWR", 0 0, L_000000000404e310;  1 drivers, strength-aware
+v0000000003bb3980_0 .net "X", 0 0, L_0000000004140ec0;  alias, 1 drivers
+v0000000003bb5000_0 .net "and0_out_X", 0 0, L_00000000041414e0;  1 drivers
+v0000000003bb2940_0 .net "or0_out", 0 0, L_00000000041427b0;  1 drivers
+v0000000003bb50a0_0 .net "or1_out", 0 0, L_0000000004142430;  1 drivers
+S_0000000003bda3f0 .scope module, "_0894_" "sky130_fd_sc_hd__a2bb2oi_2" 3 2647, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bb4880_0 .net "A1_N", 0 0, L_0000000004141240;  alias, 1 drivers
+v0000000003bb30c0_0 .net "A2_N", 0 0, L_0000000004140ec0;  alias, 1 drivers
+v0000000003bb2da0_0 .net "B1", 0 0, L_0000000004141240;  alias, 1 drivers
+v0000000003bb4920_0 .net "B2", 0 0, L_0000000004140ec0;  alias, 1 drivers
+L_000000000404e0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3700_0 .net8 "VGND", 0 0, L_000000000404e0e0;  1 drivers, strength-aware
+L_000000000404e7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3ca0_0 .net8 "VNB", 0 0, L_000000000404e7e0;  1 drivers, strength-aware
+L_000000000404e150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3de0_0 .net8 "VPB", 0 0, L_000000000404e150;  1 drivers, strength-aware
+L_000000000404ed90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3fc0_0 .net8 "VPWR", 0 0, L_000000000404ed90;  1 drivers, strength-aware
+v0000000003bb2f80_0 .net "Y", 0 0, L_0000000004141cc0;  alias, 1 drivers
+S_0000000003bde770 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003bda3f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004142040 .functor AND 1, L_0000000004141240, L_0000000004140ec0, C4<1>, C4<1>;
+L_00000000041418d0 .functor NOR 1, L_0000000004141240, L_0000000004140ec0, C4<0>, C4<0>;
+L_00000000041424a0 .functor NOR 1, L_00000000041418d0, L_0000000004142040, C4<0>, C4<0>;
+L_0000000004141cc0 .functor BUF 1, L_00000000041424a0, C4<0>, C4<0>, C4<0>;
+v0000000003bb3d40_0 .net "A1_N", 0 0, L_0000000004141240;  alias, 1 drivers
+v0000000003bb4d80_0 .net "A2_N", 0 0, L_0000000004140ec0;  alias, 1 drivers
+v0000000003bb46a0_0 .net "B1", 0 0, L_0000000004141240;  alias, 1 drivers
+v0000000003bb4ce0_0 .net "B2", 0 0, L_0000000004140ec0;  alias, 1 drivers
+L_000000000404ebd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2ee0_0 .net8 "VGND", 0 0, L_000000000404ebd0;  1 drivers, strength-aware
+L_000000000404e230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb3a20_0 .net8 "VNB", 0 0, L_000000000404e230;  1 drivers, strength-aware
+L_000000000404e380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4240_0 .net8 "VPB", 0 0, L_000000000404e380;  1 drivers, strength-aware
+L_000000000404e3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4380_0 .net8 "VPWR", 0 0, L_000000000404e3f0;  1 drivers, strength-aware
+v0000000003bb2d00_0 .net "Y", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bb32a0_0 .net "and0_out", 0 0, L_0000000004142040;  1 drivers
+v0000000003bb3020_0 .net "nor0_out", 0 0, L_00000000041418d0;  1 drivers
+v0000000003bb3ac0_0 .net "nor1_out_Y", 0 0, L_00000000041424a0;  1 drivers
+S_0000000003bda570 .scope module, "_0895_" "sky130_fd_sc_hd__or2_2" 3 2654, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bb49c0_0 .net "A", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003bb4a60_0 .net "B", 0 0, L_0000000004142580;  alias, 1 drivers
+L_000000000404e460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4b00_0 .net8 "VGND", 0 0, L_000000000404e460;  1 drivers, strength-aware
+L_000000000404ea80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb71c0_0 .net8 "VNB", 0 0, L_000000000404ea80;  1 drivers, strength-aware
+L_000000000404fdc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb55a0_0 .net8 "VPB", 0 0, L_000000000404fdc0;  1 drivers, strength-aware
+L_0000000004050680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5d20_0 .net8 "VPWR", 0 0, L_0000000004050680;  1 drivers, strength-aware
+v0000000003bb5e60_0 .net "X", 0 0, L_00000000041416a0;  alias, 1 drivers
+S_0000000003bda6f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bda570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142820 .functor OR 1, L_0000000004142580, L_000000000413f1e0, C4<0>, C4<0>;
+L_00000000041416a0 .functor BUF 1, L_0000000004142820, C4<0>, C4<0>, C4<0>;
+v0000000003bb4f60_0 .net "A", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003bb3f20_0 .net "B", 0 0, L_0000000004142580;  alias, 1 drivers
+L_0000000004050a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb29e0_0 .net8 "VGND", 0 0, L_0000000004050a70;  1 drivers, strength-aware
+L_0000000004050bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb4060_0 .net8 "VNB", 0 0, L_0000000004050bc0;  1 drivers, strength-aware
+L_000000000404fa40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb44c0_0 .net8 "VPB", 0 0, L_000000000404fa40;  1 drivers, strength-aware
+L_0000000004050d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb2e40_0 .net8 "VPWR", 0 0, L_0000000004050d10;  1 drivers, strength-aware
+v0000000003bb3200_0 .net "X", 0 0, L_00000000041416a0;  alias, 1 drivers
+v0000000003bb3340_0 .net "or0_out_X", 0 0, L_0000000004142820;  1 drivers
+S_0000000003bdc4f0 .scope module, "_0896_" "sky130_fd_sc_hd__or4_2" 3 2659, 4 87422 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+v0000000003bb6720_0 .net "A", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003bb60e0_0 .net "B", 0 0, L_00000000041416a0;  alias, 1 drivers
+v0000000003bb7800_0 .net "C", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003bb5140_0 .net "D", 0 0, L_000000000413dab0;  alias, 1 drivers
+L_0000000004050290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5c80_0 .net8 "VGND", 0 0, L_0000000004050290;  1 drivers, strength-aware
+L_0000000004050f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb51e0_0 .net8 "VNB", 0 0, L_0000000004050f40;  1 drivers, strength-aware
+L_0000000004050140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6f40_0 .net8 "VPB", 0 0, L_0000000004050140;  1 drivers, strength-aware
+L_0000000004050b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb78a0_0 .net8 "VPWR", 0 0, L_0000000004050b50;  1 drivers, strength-aware
+v0000000003bb5500_0 .net "X", 0 0, L_00000000041420b0;  alias, 1 drivers
+S_0000000003bda870 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87442, 4 87301 1, S_0000000003bdc4f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004141710 .functor OR 1, L_000000000413dab0, L_0000000004140600, L_00000000041416a0, L_0000000004140ad0;
+L_00000000041420b0 .functor BUF 1, L_0000000004141710, C4<0>, C4<0>, C4<0>;
+v0000000003bb5960_0 .net "A", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003bb6680_0 .net "B", 0 0, L_00000000041416a0;  alias, 1 drivers
+v0000000003bb6ea0_0 .net "C", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003bb6400_0 .net "D", 0 0, L_000000000413dab0;  alias, 1 drivers
+L_0000000004050c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5460_0 .net8 "VGND", 0 0, L_0000000004050c30;  1 drivers, strength-aware
+L_0000000004050220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb74e0_0 .net8 "VNB", 0 0, L_0000000004050220;  1 drivers, strength-aware
+L_00000000040500d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5320_0 .net8 "VPB", 0 0, L_00000000040500d0;  1 drivers, strength-aware
+L_0000000004050e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6860_0 .net8 "VPWR", 0 0, L_0000000004050e60;  1 drivers, strength-aware
+v0000000003bb6ae0_0 .net "X", 0 0, L_00000000041420b0;  alias, 1 drivers
+v0000000003bb53c0_0 .net "or0_out_X", 0 0, L_0000000004141710;  1 drivers
+S_0000000003bdc670 .scope module, "_0897_" "sky130_fd_sc_hd__or2_2" 3 2666, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bb62c0_0 .net "A", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bb7580_0 .net "B", 0 0, L_00000000041420b0;  alias, 1 drivers
+L_0000000004051090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb56e0_0 .net8 "VGND", 0 0, L_0000000004051090;  1 drivers, strength-aware
+L_0000000004051480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5fa0_0 .net8 "VNB", 0 0, L_0000000004051480;  1 drivers, strength-aware
+L_0000000004050a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6b80_0 .net8 "VPB", 0 0, L_0000000004050a00;  1 drivers, strength-aware
+L_0000000004050fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7300_0 .net8 "VPWR", 0 0, L_0000000004050fb0;  1 drivers, strength-aware
+v0000000003bb7080_0 .net "X", 0 0, L_0000000004141a20;  alias, 1 drivers
+S_0000000003bdc970 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bdc670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142190 .functor OR 1, L_00000000041420b0, L_0000000004141cc0, C4<0>, C4<0>;
+L_0000000004141a20 .functor BUF 1, L_0000000004142190, C4<0>, C4<0>, C4<0>;
+v0000000003bb7260_0 .net "A", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bb6900_0 .net "B", 0 0, L_00000000041420b0;  alias, 1 drivers
+L_00000000040501b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6cc0_0 .net8 "VGND", 0 0, L_00000000040501b0;  1 drivers, strength-aware
+L_000000000404fff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5a00_0 .net8 "VNB", 0 0, L_000000000404fff0;  1 drivers, strength-aware
+L_0000000004050ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5dc0_0 .net8 "VPB", 0 0, L_0000000004050ed0;  1 drivers, strength-aware
+L_000000000404fb20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6d60_0 .net8 "VPWR", 0 0, L_000000000404fb20;  1 drivers, strength-aware
+v0000000003bb6540_0 .net "X", 0 0, L_0000000004141a20;  alias, 1 drivers
+v0000000003bb6a40_0 .net "or0_out_X", 0 0, L_0000000004142190;  1 drivers
+S_0000000003bde8f0 .scope module, "_0898_" "sky130_fd_sc_hd__a21boi_2" 3 2671, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003bb73a0_0 .net "A1", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bb64a0_0 .net "A2", 0 0, L_00000000041420b0;  alias, 1 drivers
+v0000000003bb6220_0 .net "B1_N", 0 0, L_0000000004141a20;  alias, 1 drivers
+L_0000000004050450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6c20_0 .net8 "VGND", 0 0, L_0000000004050450;  1 drivers, strength-aware
+L_0000000004051100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7440_0 .net8 "VNB", 0 0, L_0000000004051100;  1 drivers, strength-aware
+L_0000000004050300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5820_0 .net8 "VPB", 0 0, L_0000000004050300;  1 drivers, strength-aware
+L_0000000004050370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb76c0_0 .net8 "VPWR", 0 0, L_0000000004050370;  1 drivers, strength-aware
+v0000000003bb7760_0 .net "Y", 0 0, L_0000000004141d30;  alias, 1 drivers
+S_0000000003bdea70 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003bde8f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_00000000041422e0 .functor NOT 1, L_0000000004141a20, C4<0>, C4<0>, C4<0>;
+L_0000000004141ef0 .functor AND 1, L_0000000004141cc0, L_00000000041420b0, C4<1>, C4<1>;
+L_0000000004141a90 .functor NOR 1, L_00000000041422e0, L_0000000004141ef0, C4<0>, C4<0>;
+L_0000000004141d30 .functor BUF 1, L_0000000004141a90, C4<0>, C4<0>, C4<0>;
+v0000000003bb6fe0_0 .net "A1", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bb7620_0 .net "A2", 0 0, L_00000000041420b0;  alias, 1 drivers
+v0000000003bb5be0_0 .net "B1_N", 0 0, L_0000000004141a20;  alias, 1 drivers
+L_0000000004050ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6e00_0 .net8 "VGND", 0 0, L_0000000004050ae0;  1 drivers, strength-aware
+L_000000000404fe30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5f00_0 .net8 "VNB", 0 0, L_000000000404fe30;  1 drivers, strength-aware
+L_0000000004051410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb65e0_0 .net8 "VPB", 0 0, L_0000000004051410;  1 drivers, strength-aware
+L_000000000404fb90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6040_0 .net8 "VPWR", 0 0, L_000000000404fb90;  1 drivers, strength-aware
+v0000000003bb7120_0 .net "Y", 0 0, L_0000000004141d30;  alias, 1 drivers
+v0000000003bb5640_0 .net "and0_out", 0 0, L_0000000004141ef0;  1 drivers
+v0000000003bb6180_0 .net "b", 0 0, L_00000000041422e0;  1 drivers
+v0000000003bb5780_0 .net "nor0_out_Y", 0 0, L_0000000004141a90;  1 drivers
+S_0000000003bdebf0 .scope module, "_0899_" "sky130_fd_sc_hd__or2_2" 3 2677, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bb9380_0 .net "A", 0 0, L_0000000004138a30;  alias, 1 drivers
+v0000000003bb87a0_0 .net "B", 0 0, L_000000000412c2b0;  alias, 1 drivers
+L_000000000404f8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8e80_0 .net8 "VGND", 0 0, L_000000000404f8f0;  1 drivers, strength-aware
+L_0000000004050ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7c60_0 .net8 "VNB", 0 0, L_0000000004050ca0;  1 drivers, strength-aware
+L_00000000040506f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9240_0 .net8 "VPB", 0 0, L_00000000040506f0;  1 drivers, strength-aware
+L_0000000004051020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8520_0 .net8 "VPWR", 0 0, L_0000000004051020;  1 drivers, strength-aware
+v0000000003bb7d00_0 .net "X", 0 0, L_0000000004142350;  alias, 1 drivers
+S_0000000003bdeef0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003bdebf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004141da0 .functor OR 1, L_000000000412c2b0, L_0000000004138a30, C4<0>, C4<0>;
+L_0000000004142350 .functor BUF 1, L_0000000004141da0, C4<0>, C4<0>, C4<0>;
+v0000000003bb58c0_0 .net "A", 0 0, L_0000000004138a30;  alias, 1 drivers
+v0000000003bb5aa0_0 .net "B", 0 0, L_000000000412c2b0;  alias, 1 drivers
+L_0000000004050530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5280_0 .net8 "VGND", 0 0, L_0000000004050530;  1 drivers, strength-aware
+L_000000000404fce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb5b40_0 .net8 "VNB", 0 0, L_000000000404fce0;  1 drivers, strength-aware
+L_000000000404fc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb6360_0 .net8 "VPB", 0 0, L_000000000404fc70;  1 drivers, strength-aware
+L_000000000404fea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb67c0_0 .net8 "VPWR", 0 0, L_000000000404fea0;  1 drivers, strength-aware
+v0000000003bb69a0_0 .net "X", 0 0, L_0000000004142350;  alias, 1 drivers
+v0000000003bb9420_0 .net "or0_out_X", 0 0, L_0000000004141da0;  1 drivers
+S_0000000003be1d70 .scope module, "_0900_" "sky130_fd_sc_hd__a22o_2" 3 2682, 4 92017 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bb94c0_0 .net "A1", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003bb83e0_0 .net "A2", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003bb8160_0 .net "B1", 0 0, L_0000000004137ed0;  alias, 1 drivers
+v0000000003bb8480_0 .net "B2", 0 0, L_0000000004134430;  alias, 1 drivers
+L_000000000404fc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7a80_0 .net8 "VGND", 0 0, L_000000000404fc00;  1 drivers, strength-aware
+L_00000000040503e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8660_0 .net8 "VNB", 0 0, L_00000000040503e0;  1 drivers, strength-aware
+L_00000000040512c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb97e0_0 .net8 "VPB", 0 0, L_00000000040512c0;  1 drivers, strength-aware
+L_0000000004051250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb99c0_0 .net8 "VPWR", 0 0, L_0000000004051250;  1 drivers, strength-aware
+v0000000003bb9ba0_0 .net "X", 0 0, L_00000000041437e0;  alias, 1 drivers
+S_0000000003be2af0 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92037, 4 91890 1, S_0000000003be1d70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004142510 .functor AND 1, L_0000000004137ed0, L_0000000004134430, C4<1>, C4<1>;
+L_0000000004143150 .functor AND 1, L_0000000004131250, L_0000000004138330, C4<1>, C4<1>;
+L_00000000041430e0 .functor OR 1, L_0000000004143150, L_0000000004142510, C4<0>, C4<0>;
+L_00000000041437e0 .functor BUF 1, L_00000000041430e0, C4<0>, C4<0>, C4<0>;
+v0000000003bb9060_0 .net "A1", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003bb92e0_0 .net "A2", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003bb7bc0_0 .net "B1", 0 0, L_0000000004137ed0;  alias, 1 drivers
+v0000000003bb85c0_0 .net "B2", 0 0, L_0000000004134430;  alias, 1 drivers
+L_0000000004051330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9e20_0 .net8 "VGND", 0 0, L_0000000004051330;  1 drivers, strength-aware
+L_00000000040513a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8840_0 .net8 "VNB", 0 0, L_00000000040513a0;  1 drivers, strength-aware
+L_00000000040504c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb91a0_0 .net8 "VPB", 0 0, L_00000000040504c0;  1 drivers, strength-aware
+L_00000000040505a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8ca0_0 .net8 "VPWR", 0 0, L_00000000040505a0;  1 drivers, strength-aware
+v0000000003bb88e0_0 .net "X", 0 0, L_00000000041437e0;  alias, 1 drivers
+v0000000003bba0a0_0 .net "and0_out", 0 0, L_0000000004142510;  1 drivers
+v0000000003bb79e0_0 .net "and1_out", 0 0, L_0000000004143150;  1 drivers
+v0000000003bb9740_0 .net "or0_out_X", 0 0, L_00000000041430e0;  1 drivers
+S_0000000003be0b70 .scope module, "_0901_" "sky130_fd_sc_hd__inv_2" 3 2689, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bb8020_0 .net "A", 0 0, L_00000000041312c0;  alias, 1 drivers
+L_0000000004050d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9600_0 .net8 "VGND", 0 0, L_0000000004050d80;  1 drivers, strength-aware
+L_0000000004050060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9920_0 .net8 "VNB", 0 0, L_0000000004050060;  1 drivers, strength-aware
+L_000000000404fab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8c00_0 .net8 "VPB", 0 0, L_000000000404fab0;  1 drivers, strength-aware
+L_0000000004051170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8d40_0 .net8 "VPWR", 0 0, L_0000000004051170;  1 drivers, strength-aware
+v0000000003bb96a0_0 .net "Y", 0 0, L_0000000004143460;  alias, 1 drivers
+S_0000000003be33f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be0b70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004142ac0 .functor NOT 1, L_00000000041312c0, C4<0>, C4<0>, C4<0>;
+L_0000000004143460 .functor BUF 1, L_0000000004142ac0, C4<0>, C4<0>, C4<0>;
+v0000000003bb9880_0 .net "A", 0 0, L_00000000041312c0;  alias, 1 drivers
+L_000000000404f960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9560_0 .net8 "VGND", 0 0, L_000000000404f960;  1 drivers, strength-aware
+L_0000000004050760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9ce0_0 .net8 "VNB", 0 0, L_0000000004050760;  1 drivers, strength-aware
+L_000000000404ff10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7da0_0 .net8 "VPB", 0 0, L_000000000404ff10;  1 drivers, strength-aware
+L_0000000004050840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8980_0 .net8 "VPWR", 0 0, L_0000000004050840;  1 drivers, strength-aware
+v0000000003bb9c40_0 .net "Y", 0 0, L_0000000004143460;  alias, 1 drivers
+v0000000003bb9a60_0 .net "not0_out_Y", 0 0, L_0000000004142ac0;  1 drivers
+S_0000000003be09f0 .scope module, "_0902_" "sky130_fd_sc_hd__o221ai_2" 3 2693, 4 23614 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003bb8200_0 .net "A1", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003bb82a0_0 .net "A2", 0 0, L_0000000004137b50;  alias, 1 drivers
+v0000000003bb8340_0 .net "B1", 0 0, L_0000000004137990;  alias, 1 drivers
+v0000000003bb8ac0_0 .net "B2", 0 0, L_00000000041437e0;  alias, 1 drivers
+v0000000003bb8fc0_0 .net "C1", 0 0, L_0000000004143460;  alias, 1 drivers
+L_000000000404ff80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9f60_0 .net8 "VGND", 0 0, L_000000000404ff80;  1 drivers, strength-aware
+L_0000000004050610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9100_0 .net8 "VNB", 0 0, L_0000000004050610;  1 drivers, strength-aware
+L_000000000404fd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bba000_0 .net8 "VPB", 0 0, L_000000000404fd50;  1 drivers, strength-aware
+L_00000000040507d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7940_0 .net8 "VPWR", 0 0, L_00000000040507d0;  1 drivers, strength-aware
+v0000000003bba3c0_0 .net "Y", 0 0, L_0000000004143b60;  alias, 1 drivers
+S_0000000003be3270 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23636, 4 23482 1, S_0000000003be09f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041439a0 .functor OR 1, L_00000000041437e0, L_0000000004137990, C4<0>, C4<0>;
+L_0000000004142b30 .functor OR 1, L_0000000004137b50, L_0000000004138330, C4<0>, C4<0>;
+L_0000000004142f90 .functor NAND 1, L_0000000004142b30, L_00000000041439a0, L_0000000004143460, C4<1>;
+L_0000000004143b60 .functor BUF 1, L_0000000004142f90, C4<0>, C4<0>, C4<0>;
+v0000000003bb9b00_0 .net "A1", 0 0, L_0000000004138330;  alias, 1 drivers
+v0000000003bb8b60_0 .net "A2", 0 0, L_0000000004137b50;  alias, 1 drivers
+v0000000003bb7e40_0 .net "B1", 0 0, L_0000000004137990;  alias, 1 drivers
+v0000000003bb8700_0 .net "B2", 0 0, L_00000000041437e0;  alias, 1 drivers
+v0000000003bb7ee0_0 .net "C1", 0 0, L_0000000004143460;  alias, 1 drivers
+L_00000000040508b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7f80_0 .net8 "VGND", 0 0, L_00000000040508b0;  1 drivers, strength-aware
+L_0000000004050df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bb7b20_0 .net8 "VNB", 0 0, L_0000000004050df0;  1 drivers, strength-aware
+L_0000000004050920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb9d80_0 .net8 "VPB", 0 0, L_0000000004050920;  1 drivers, strength-aware
+L_0000000004050990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bb8de0_0 .net8 "VPWR", 0 0, L_0000000004050990;  1 drivers, strength-aware
+v0000000003bb8a20_0 .net "Y", 0 0, L_0000000004143b60;  alias, 1 drivers
+v0000000003bb8f20_0 .net "nand0_out_Y", 0 0, L_0000000004142f90;  1 drivers
+v0000000003bb9ec0_0 .net "or0_out", 0 0, L_00000000041439a0;  1 drivers
+v0000000003bb80c0_0 .net "or1_out", 0 0, L_0000000004142b30;  1 drivers
+S_0000000003be3b70 .scope module, "_0903_" "sky130_fd_sc_hd__a2bb2o_2" 3 2701, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bbc760_0 .net "A1_N", 0 0, L_0000000004142350;  alias, 1 drivers
+v0000000003bbb720_0 .net "A2_N", 0 0, L_0000000004143b60;  alias, 1 drivers
+v0000000003bbc620_0 .net "B1", 0 0, L_0000000004142350;  alias, 1 drivers
+v0000000003bbb2c0_0 .net "B2", 0 0, L_0000000004143b60;  alias, 1 drivers
+L_000000000404f9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bba140_0 .net8 "VGND", 0 0, L_000000000404f9d0;  1 drivers, strength-aware
+L_00000000040511e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb9a0_0 .net8 "VNB", 0 0, L_00000000040511e0;  1 drivers, strength-aware
+L_0000000004052130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbbc20_0 .net8 "VPB", 0 0, L_0000000004052130;  1 drivers, strength-aware
+L_0000000004052600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbbcc0_0 .net8 "VPWR", 0 0, L_0000000004052600;  1 drivers, strength-aware
+v0000000003bbc440_0 .net "X", 0 0, L_0000000004143310;  alias, 1 drivers
+S_0000000003be4bf0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003be3b70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004143850 .functor AND 1, L_0000000004142350, L_0000000004143b60, C4<1>, C4<1>;
+L_00000000041431c0 .functor NOR 1, L_0000000004142350, L_0000000004143b60, C4<0>, C4<0>;
+L_0000000004142a50 .functor OR 1, L_00000000041431c0, L_0000000004143850, C4<0>, C4<0>;
+L_0000000004143310 .functor BUF 1, L_0000000004142a50, C4<0>, C4<0>, C4<0>;
+v0000000003bbc4e0_0 .net "A1_N", 0 0, L_0000000004142350;  alias, 1 drivers
+v0000000003bbbf40_0 .net "A2_N", 0 0, L_0000000004143b60;  alias, 1 drivers
+v0000000003bba8c0_0 .net "B1", 0 0, L_0000000004142350;  alias, 1 drivers
+v0000000003bbafa0_0 .net "B2", 0 0, L_0000000004143b60;  alias, 1 drivers
+L_0000000004051cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bba5a0_0 .net8 "VGND", 0 0, L_0000000004051cd0;  1 drivers, strength-aware
+L_0000000004053080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbadc0_0 .net8 "VNB", 0 0, L_0000000004053080;  1 drivers, strength-aware
+L_0000000004052980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb4a0_0 .net8 "VPB", 0 0, L_0000000004052980;  1 drivers, strength-aware
+L_0000000004052fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bba640_0 .net8 "VPWR", 0 0, L_0000000004052fa0;  1 drivers, strength-aware
+v0000000003bbb0e0_0 .net "X", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003bba6e0_0 .net "and0_out", 0 0, L_0000000004143850;  1 drivers
+v0000000003bbc580_0 .net "nor0_out", 0 0, L_00000000041431c0;  1 drivers
+v0000000003bba500_0 .net "or0_out_X", 0 0, L_0000000004142a50;  1 drivers
+S_0000000003be4ef0 .scope module, "_0904_" "sky130_fd_sc_hd__or2_2" 3 2708, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bbc080_0 .net "A", 0 0, L_0000000004141a20;  alias, 1 drivers
+v0000000003bbbea0_0 .net "B", 0 0, L_0000000004143310;  alias, 1 drivers
+L_0000000004052f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb400_0 .net8 "VGND", 0 0, L_0000000004052f30;  1 drivers, strength-aware
+L_00000000040528a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb360_0 .net8 "VNB", 0 0, L_00000000040528a0;  1 drivers, strength-aware
+L_00000000040526e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbc800_0 .net8 "VPB", 0 0, L_00000000040526e0;  1 drivers, strength-aware
+L_0000000004052bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bba780_0 .net8 "VPWR", 0 0, L_0000000004052bb0;  1 drivers, strength-aware
+v0000000003bbc8a0_0 .net "X", 0 0, L_0000000004143230;  alias, 1 drivers
+S_0000000003be2df0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be4ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142cf0 .functor OR 1, L_0000000004143310, L_0000000004141a20, C4<0>, C4<0>;
+L_0000000004143230 .functor BUF 1, L_0000000004142cf0, C4<0>, C4<0>, C4<0>;
+v0000000003bbc120_0 .net "A", 0 0, L_0000000004141a20;  alias, 1 drivers
+v0000000003bbba40_0 .net "B", 0 0, L_0000000004143310;  alias, 1 drivers
+L_0000000004052670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbae60_0 .net8 "VGND", 0 0, L_0000000004052670;  1 drivers, strength-aware
+L_0000000004051f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb040_0 .net8 "VNB", 0 0, L_0000000004051f70;  1 drivers, strength-aware
+L_00000000040519c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bba820_0 .net8 "VPB", 0 0, L_00000000040519c0;  1 drivers, strength-aware
+L_0000000004052d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb5e0_0 .net8 "VPWR", 0 0, L_0000000004052d70;  1 drivers, strength-aware
+v0000000003bba1e0_0 .net "X", 0 0, L_0000000004143230;  alias, 1 drivers
+v0000000003bbc6c0_0 .net "or0_out_X", 0 0, L_0000000004142cf0;  1 drivers
+S_0000000003be0e70 .scope module, "_0905_" "sky130_fd_sc_hd__a21boi_2" 3 2713, 4 11576 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003bbc1c0_0 .net "A1", 0 0, L_0000000004141a20;  alias, 1 drivers
+v0000000003bbc3a0_0 .net "A2", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003bba960_0 .net "B1_N", 0 0, L_0000000004143230;  alias, 1 drivers
+L_0000000004051800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbbfe0_0 .net8 "VGND", 0 0, L_0000000004051800;  1 drivers, strength-aware
+L_00000000040529f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbaa00_0 .net8 "VNB", 0 0, L_00000000040529f0;  1 drivers, strength-aware
+L_0000000004051d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbad20_0 .net8 "VPB", 0 0, L_0000000004051d40;  1 drivers, strength-aware
+L_00000000040524b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbc260_0 .net8 "VPWR", 0 0, L_00000000040524b0;  1 drivers, strength-aware
+v0000000003bbc300_0 .net "Y", 0 0, L_00000000041435b0;  alias, 1 drivers
+S_0000000003be0870 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_0000000003be0e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_0000000004142ba0 .functor NOT 1, L_0000000004143230, C4<0>, C4<0>, C4<0>;
+L_00000000041434d0 .functor AND 1, L_0000000004141a20, L_0000000004143310, C4<1>, C4<1>;
+L_0000000004143070 .functor NOR 1, L_0000000004142ba0, L_00000000041434d0, C4<0>, C4<0>;
+L_00000000041435b0 .functor BUF 1, L_0000000004143070, C4<0>, C4<0>, C4<0>;
+v0000000003bbb540_0 .net "A1", 0 0, L_0000000004141a20;  alias, 1 drivers
+v0000000003bbb180_0 .net "A2", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003bba280_0 .net "B1_N", 0 0, L_0000000004143230;  alias, 1 drivers
+L_0000000004052de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbbe00_0 .net8 "VGND", 0 0, L_0000000004052de0;  1 drivers, strength-aware
+L_0000000004052a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbabe0_0 .net8 "VNB", 0 0, L_0000000004052a60;  1 drivers, strength-aware
+L_0000000004052ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bba460_0 .net8 "VPB", 0 0, L_0000000004052ad0;  1 drivers, strength-aware
+L_0000000004052d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb680_0 .net8 "VPWR", 0 0, L_0000000004052d00;  1 drivers, strength-aware
+v0000000003bbbd60_0 .net "Y", 0 0, L_00000000041435b0;  alias, 1 drivers
+v0000000003bbac80_0 .net "and0_out", 0 0, L_00000000041434d0;  1 drivers
+v0000000003bbb220_0 .net "b", 0 0, L_0000000004142ba0;  1 drivers
+v0000000003bba320_0 .net "nor0_out_Y", 0 0, L_0000000004143070;  1 drivers
+S_0000000003be4770 .scope module, "_0906_" "sky130_fd_sc_hd__inv_2" 3 2719, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bbbae0_0 .net "A", 0 0, L_0000000004138d40;  alias, 1 drivers
+L_0000000004052c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe240_0 .net8 "VGND", 0 0, L_0000000004052c20;  1 drivers, strength-aware
+L_0000000004051e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbeba0_0 .net8 "VNB", 0 0, L_0000000004051e90;  1 drivers, strength-aware
+L_0000000004052050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe6a0_0 .net8 "VPB", 0 0, L_0000000004052050;  1 drivers, strength-aware
+L_00000000040522f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe560_0 .net8 "VPWR", 0 0, L_00000000040522f0;  1 drivers, strength-aware
+v0000000003bbcee0_0 .net "Y", 0 0, L_0000000004143e00;  alias, 1 drivers
+S_0000000003be45f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be4770;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004143700 .functor NOT 1, L_0000000004138d40, C4<0>, C4<0>, C4<0>;
+L_0000000004143e00 .functor BUF 1, L_0000000004143700, C4<0>, C4<0>, C4<0>;
+v0000000003bbb7c0_0 .net "A", 0 0, L_0000000004138d40;  alias, 1 drivers
+L_0000000004052910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbaaa0_0 .net8 "VGND", 0 0, L_0000000004052910;  1 drivers, strength-aware
+L_0000000004052ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbab40_0 .net8 "VNB", 0 0, L_0000000004052ec0;  1 drivers, strength-aware
+L_0000000004051aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbaf00_0 .net8 "VPB", 0 0, L_0000000004051aa0;  1 drivers, strength-aware
+L_00000000040520c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbb860_0 .net8 "VPWR", 0 0, L_00000000040520c0;  1 drivers, strength-aware
+v0000000003bbb900_0 .net "Y", 0 0, L_0000000004143e00;  alias, 1 drivers
+v0000000003bbbb80_0 .net "not0_out_Y", 0 0, L_0000000004143700;  1 drivers
+S_0000000003be1bf0 .scope module, "_0907_" "sky130_fd_sc_hd__or2_2" 3 2723, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bbd480_0 .net "A", 0 0, L_0000000004143e00;  alias, 1 drivers
+v0000000003bbe9c0_0 .net "B", 0 0, L_0000000004138950;  alias, 1 drivers
+L_0000000004052750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd160_0 .net8 "VGND", 0 0, L_0000000004052750;  1 drivers, strength-aware
+L_0000000004053010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe740_0 .net8 "VNB", 0 0, L_0000000004053010;  1 drivers, strength-aware
+L_0000000004052c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbee20_0 .net8 "VPB", 0 0, L_0000000004052c90;  1 drivers, strength-aware
+L_0000000004051db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd520_0 .net8 "VPWR", 0 0, L_0000000004051db0;  1 drivers, strength-aware
+v0000000003bbd200_0 .net "X", 0 0, L_0000000004143a80;  alias, 1 drivers
+S_0000000003be3870 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be1bf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041432a0 .functor OR 1, L_0000000004138950, L_0000000004143e00, C4<0>, C4<0>;
+L_0000000004143a80 .functor BUF 1, L_00000000041432a0, C4<0>, C4<0>, C4<0>;
+v0000000003bbed80_0 .net "A", 0 0, L_0000000004143e00;  alias, 1 drivers
+v0000000003bbece0_0 .net "B", 0 0, L_0000000004138950;  alias, 1 drivers
+L_0000000004052b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe7e0_0 .net8 "VGND", 0 0, L_0000000004052b40;  1 drivers, strength-aware
+L_0000000004052360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbc940_0 .net8 "VNB", 0 0, L_0000000004052360;  1 drivers, strength-aware
+L_00000000040527c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd8e0_0 .net8 "VPB", 0 0, L_00000000040527c0;  1 drivers, strength-aware
+L_0000000004052e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe920_0 .net8 "VPWR", 0 0, L_0000000004052e50;  1 drivers, strength-aware
+v0000000003bbd0c0_0 .net "X", 0 0, L_0000000004143a80;  alias, 1 drivers
+v0000000003bbcbc0_0 .net "or0_out_X", 0 0, L_00000000041432a0;  1 drivers
+S_0000000003be12f0 .scope module, "_0908_" "sky130_fd_sc_hd__or2_2" 3 2728, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bbf000_0 .net "A", 0 0, L_00000000041300d0;  alias, 1 drivers
+v0000000003bbdac0_0 .net "B", 0 0, L_0000000004142350;  alias, 1 drivers
+L_00000000040521a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf0a0_0 .net8 "VGND", 0 0, L_00000000040521a0;  1 drivers, strength-aware
+L_0000000004051640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbdb60_0 .net8 "VNB", 0 0, L_0000000004051640;  1 drivers, strength-aware
+L_0000000004051b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbdd40_0 .net8 "VPB", 0 0, L_0000000004051b10;  1 drivers, strength-aware
+L_00000000040516b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbec40_0 .net8 "VPWR", 0 0, L_00000000040516b0;  1 drivers, strength-aware
+v0000000003bbd020_0 .net "X", 0 0, L_00000000041438c0;  alias, 1 drivers
+S_0000000003be0ff0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be12f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004143930 .functor OR 1, L_0000000004142350, L_00000000041300d0, C4<0>, C4<0>;
+L_00000000041438c0 .functor BUF 1, L_0000000004143930, C4<0>, C4<0>, C4<0>;
+v0000000003bbd700_0 .net "A", 0 0, L_00000000041300d0;  alias, 1 drivers
+v0000000003bbdfc0_0 .net "B", 0 0, L_0000000004142350;  alias, 1 drivers
+L_0000000004051e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbcf80_0 .net8 "VGND", 0 0, L_0000000004051e20;  1 drivers, strength-aware
+L_00000000040514f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd840_0 .net8 "VNB", 0 0, L_00000000040514f0;  1 drivers, strength-aware
+L_0000000004052440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbea60_0 .net8 "VPB", 0 0, L_0000000004052440;  1 drivers, strength-aware
+L_00000000040523d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe880_0 .net8 "VPWR", 0 0, L_00000000040523d0;  1 drivers, strength-aware
+v0000000003bbeec0_0 .net "X", 0 0, L_00000000041438c0;  alias, 1 drivers
+v0000000003bbef60_0 .net "or0_out_X", 0 0, L_0000000004143930;  1 drivers
+S_0000000003be4d70 .scope module, "_0909_" "sky130_fd_sc_hd__inv_2" 3 2733, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bbd5c0_0 .net "A", 0 0, L_00000000041438c0;  alias, 1 drivers
+L_0000000004051560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbcd00_0 .net8 "VGND", 0 0, L_0000000004051560;  1 drivers, strength-aware
+L_00000000040515d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd980_0 .net8 "VNB", 0 0, L_00000000040515d0;  1 drivers, strength-aware
+L_0000000004051720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbdc00_0 .net8 "VPB", 0 0, L_0000000004051720;  1 drivers, strength-aware
+L_0000000004051790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbce40_0 .net8 "VPWR", 0 0, L_0000000004051790;  1 drivers, strength-aware
+v0000000003bbc9e0_0 .net "Y", 0 0, L_0000000004142900;  alias, 1 drivers
+S_0000000003be48f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be4d70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004143e70 .functor NOT 1, L_00000000041438c0, C4<0>, C4<0>, C4<0>;
+L_0000000004142900 .functor BUF 1, L_0000000004143e70, C4<0>, C4<0>, C4<0>;
+v0000000003bbeb00_0 .net "A", 0 0, L_00000000041438c0;  alias, 1 drivers
+L_0000000004051870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe420_0 .net8 "VGND", 0 0, L_0000000004051870;  1 drivers, strength-aware
+L_0000000004051a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe2e0_0 .net8 "VNB", 0 0, L_0000000004051a30;  1 drivers, strength-aware
+L_0000000004052280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe380_0 .net8 "VPB", 0 0, L_0000000004052280;  1 drivers, strength-aware
+L_0000000004052830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd7a0_0 .net8 "VPWR", 0 0, L_0000000004052830;  1 drivers, strength-aware
+v0000000003bbcda0_0 .net "Y", 0 0, L_0000000004142900;  alias, 1 drivers
+v0000000003bbcc60_0 .net "not0_out_Y", 0 0, L_0000000004143e70;  1 drivers
+S_0000000003be4470 .scope module, "_0910_" "sky130_fd_sc_hd__o21ai_2" 3 2737, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bbde80_0 .net "A1", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003bbdf20_0 .net "A2", 0 0, L_0000000004140d00;  alias, 1 drivers
+v0000000003bbe060_0 .net "B1", 0 0, L_0000000004142900;  alias, 1 drivers
+L_00000000040518e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe100_0 .net8 "VGND", 0 0, L_00000000040518e0;  1 drivers, strength-aware
+L_0000000004051950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe1a0_0 .net8 "VNB", 0 0, L_0000000004051950;  1 drivers, strength-aware
+L_0000000004051f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbe4c0_0 .net8 "VPB", 0 0, L_0000000004051f00;  1 drivers, strength-aware
+L_0000000004051b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf820_0 .net8 "VPWR", 0 0, L_0000000004051b80;  1 drivers, strength-aware
+v0000000003bc1260_0 .net "Y", 0 0, L_0000000004142e40;  alias, 1 drivers
+S_0000000003bdf670 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be4470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004143380 .functor OR 1, L_0000000004140d00, L_0000000004131790, C4<0>, C4<0>;
+L_00000000041433f0 .functor NAND 1, L_0000000004142900, L_0000000004143380, C4<1>, C4<1>;
+L_0000000004142e40 .functor BUF 1, L_00000000041433f0, C4<0>, C4<0>, C4<0>;
+v0000000003bbca80_0 .net "A1", 0 0, L_0000000004131790;  alias, 1 drivers
+v0000000003bbda20_0 .net "A2", 0 0, L_0000000004140d00;  alias, 1 drivers
+v0000000003bbdca0_0 .net "B1", 0 0, L_0000000004142900;  alias, 1 drivers
+L_0000000004051fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbdde0_0 .net8 "VGND", 0 0, L_0000000004051fe0;  1 drivers, strength-aware
+L_0000000004052520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd660_0 .net8 "VNB", 0 0, L_0000000004052520;  1 drivers, strength-aware
+L_0000000004052210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbcb20_0 .net8 "VPB", 0 0, L_0000000004052210;  1 drivers, strength-aware
+L_0000000004052590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbd2a0_0 .net8 "VPWR", 0 0, L_0000000004052590;  1 drivers, strength-aware
+v0000000003bbd340_0 .net "Y", 0 0, L_0000000004142e40;  alias, 1 drivers
+v0000000003bbd3e0_0 .net "nand0_out_Y", 0 0, L_00000000041433f0;  1 drivers
+v0000000003bbe600_0 .net "or0_out", 0 0, L_0000000004143380;  1 drivers
+S_0000000003be3570 .scope module, "_0911_" "sky130_fd_sc_hd__o21ai_2" 3 2743, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bc0cc0_0 .net "A1", 0 0, L_000000000412cbe0;  alias, 1 drivers
+v0000000003bc0b80_0 .net "A2", 0 0, L_0000000004141f60;  alias, 1 drivers
+v0000000003bc1580_0 .net "B1", 0 0, L_000000000412c940;  alias, 1 drivers
+L_0000000004051bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbfd20_0 .net8 "VGND", 0 0, L_0000000004051bf0;  1 drivers, strength-aware
+L_0000000004051c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0ea0_0 .net8 "VNB", 0 0, L_0000000004051c60;  1 drivers, strength-aware
+L_0000000004054270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0d60_0 .net8 "VPB", 0 0, L_0000000004054270;  1 drivers, strength-aware
+L_0000000004054040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf6e0_0 .net8 "VPWR", 0 0, L_0000000004054040;  1 drivers, strength-aware
+v0000000003bc05e0_0 .net "Y", 0 0, L_0000000004143770;  alias, 1 drivers
+S_0000000003be2c70 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be3570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004143540 .functor OR 1, L_0000000004141f60, L_000000000412cbe0, C4<0>, C4<0>;
+L_0000000004142c10 .functor NAND 1, L_000000000412c940, L_0000000004143540, C4<1>, C4<1>;
+L_0000000004143770 .functor BUF 1, L_0000000004142c10, C4<0>, C4<0>, C4<0>;
+v0000000003bc0ae0_0 .net "A1", 0 0, L_000000000412cbe0;  alias, 1 drivers
+v0000000003bc14e0_0 .net "A2", 0 0, L_0000000004141f60;  alias, 1 drivers
+v0000000003bbf5a0_0 .net "B1", 0 0, L_000000000412c940;  alias, 1 drivers
+L_00000000040546d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbffa0_0 .net8 "VGND", 0 0, L_00000000040546d0;  1 drivers, strength-aware
+L_0000000004054510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0a40_0 .net8 "VNB", 0 0, L_0000000004054510;  1 drivers, strength-aware
+L_0000000004054350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1300_0 .net8 "VPB", 0 0, L_0000000004054350;  1 drivers, strength-aware
+L_0000000004054740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1080_0 .net8 "VPWR", 0 0, L_0000000004054740;  1 drivers, strength-aware
+v0000000003bbfaa0_0 .net "Y", 0 0, L_0000000004143770;  alias, 1 drivers
+v0000000003bbf8c0_0 .net "nand0_out_Y", 0 0, L_0000000004142c10;  1 drivers
+v0000000003bbf1e0_0 .net "or0_out", 0 0, L_0000000004143540;  1 drivers
+S_0000000003be39f0 .scope module, "_0912_" "sky130_fd_sc_hd__nand2_2" 3 2749, 4 8552 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bc13a0_0 .net "A", 0 0, L_0000000004142e40;  alias, 1 drivers
+v0000000003bc1120_0 .net "B", 0 0, L_0000000004143770;  alias, 1 drivers
+L_0000000004054580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbfb40_0 .net8 "VGND", 0 0, L_0000000004054580;  1 drivers, strength-aware
+L_00000000040543c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0e00_0 .net8 "VNB", 0 0, L_00000000040543c0;  1 drivers, strength-aware
+L_0000000004054ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf280_0 .net8 "VPB", 0 0, L_0000000004054ba0;  1 drivers, strength-aware
+L_0000000004054b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf500_0 .net8 "VPWR", 0 0, L_0000000004054b30;  1 drivers, strength-aware
+v0000000003bc09a0_0 .net "Y", 0 0, L_0000000004143620;  alias, 1 drivers
+S_0000000003bdf970 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003be39f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142d60 .functor NAND 1, L_0000000004143770, L_0000000004142e40, C4<1>, C4<1>;
+L_0000000004143620 .functor BUF 1, L_0000000004142d60, C4<0>, C4<0>, C4<0>;
+v0000000003bbf320_0 .net "A", 0 0, L_0000000004142e40;  alias, 1 drivers
+v0000000003bbf640_0 .net "B", 0 0, L_0000000004143770;  alias, 1 drivers
+L_00000000040544a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0040_0 .net8 "VGND", 0 0, L_00000000040544a0;  1 drivers, strength-aware
+L_00000000040542e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0540_0 .net8 "VNB", 0 0, L_00000000040542e0;  1 drivers, strength-aware
+L_00000000040547b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0c20_0 .net8 "VPB", 0 0, L_00000000040547b0;  1 drivers, strength-aware
+L_0000000004054200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1620_0 .net8 "VPWR", 0 0, L_0000000004054200;  1 drivers, strength-aware
+v0000000003bbf780_0 .net "Y", 0 0, L_0000000004143620;  alias, 1 drivers
+v0000000003bc0220_0 .net "nand0_out_Y", 0 0, L_0000000004142d60;  1 drivers
+S_0000000003be4a70 .scope module, "_0913_" "sky130_fd_sc_hd__nand2_2" 3 2754, 4 8552 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bc00e0_0 .net "A", 0 0, L_000000000413f950;  alias, 1 drivers
+v0000000003bc1440_0 .net "B", 0 0, L_0000000004143620;  alias, 1 drivers
+L_0000000004053b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1760_0 .net8 "VGND", 0 0, L_0000000004053b70;  1 drivers, strength-aware
+L_00000000040535c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbfbe0_0 .net8 "VNB", 0 0, L_00000000040535c0;  1 drivers, strength-aware
+L_0000000004054970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1800_0 .net8 "VPB", 0 0, L_0000000004054970;  1 drivers, strength-aware
+L_0000000004053400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc18a0_0 .net8 "VPWR", 0 0, L_0000000004053400;  1 drivers, strength-aware
+v0000000003bbfc80_0 .net "Y", 0 0, L_0000000004142eb0;  alias, 1 drivers
+S_0000000003be36f0 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003be4a70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004142dd0 .functor NAND 1, L_0000000004143620, L_000000000413f950, C4<1>, C4<1>;
+L_0000000004142eb0 .functor BUF 1, L_0000000004142dd0, C4<0>, C4<0>, C4<0>;
+v0000000003bbf960_0 .net "A", 0 0, L_000000000413f950;  alias, 1 drivers
+v0000000003bc11c0_0 .net "B", 0 0, L_0000000004143620;  alias, 1 drivers
+L_00000000040545f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0fe0_0 .net8 "VGND", 0 0, L_00000000040545f0;  1 drivers, strength-aware
+L_00000000040538d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0f40_0 .net8 "VNB", 0 0, L_00000000040538d0;  1 drivers, strength-aware
+L_00000000040540b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbff00_0 .net8 "VPB", 0 0, L_00000000040540b0;  1 drivers, strength-aware
+L_00000000040549e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc16c0_0 .net8 "VPWR", 0 0, L_00000000040549e0;  1 drivers, strength-aware
+v0000000003bbfa00_0 .net "Y", 0 0, L_0000000004142eb0;  alias, 1 drivers
+v0000000003bbf3c0_0 .net "nand0_out_Y", 0 0, L_0000000004142dd0;  1 drivers
+S_0000000003be0270 .scope module, "_0914_" "sky130_fd_sc_hd__o21a_2" 3 2759, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bc0720_0 .net "A1", 0 0, L_0000000004141c50;  alias, 1 drivers
+v0000000003bc07c0_0 .net "A2", 0 0, L_00000000041438c0;  alias, 1 drivers
+v0000000003bc0860_0 .net "B1", 0 0, L_0000000004143770;  alias, 1 drivers
+L_0000000004054660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0900_0 .net8 "VGND", 0 0, L_0000000004054660;  1 drivers, strength-aware
+L_0000000004054820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2f20_0 .net8 "VNB", 0 0, L_0000000004054820;  1 drivers, strength-aware
+L_0000000004054900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc40a0_0 .net8 "VPB", 0 0, L_0000000004054900;  1 drivers, strength-aware
+L_0000000004054890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc27a0_0 .net8 "VPWR", 0 0, L_0000000004054890;  1 drivers, strength-aware
+v0000000003bc4000_0 .net "X", 0 0, L_0000000004143690;  alias, 1 drivers
+S_0000000003bdf4f0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003be0270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004143000 .functor OR 1, L_00000000041438c0, L_0000000004141c50, C4<0>, C4<0>;
+L_0000000004142c80 .functor AND 1, L_0000000004143000, L_0000000004143770, C4<1>, C4<1>;
+L_0000000004143690 .functor BUF 1, L_0000000004142c80, C4<0>, C4<0>, C4<0>;
+v0000000003bc02c0_0 .net "A1", 0 0, L_0000000004141c50;  alias, 1 drivers
+v0000000003bc0180_0 .net "A2", 0 0, L_00000000041438c0;  alias, 1 drivers
+v0000000003bbf460_0 .net "B1", 0 0, L_0000000004143770;  alias, 1 drivers
+L_0000000004053a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbf140_0 .net8 "VGND", 0 0, L_0000000004053a90;  1 drivers, strength-aware
+L_0000000004053c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bbfdc0_0 .net8 "VNB", 0 0, L_0000000004053c50;  1 drivers, strength-aware
+L_0000000004053ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bbfe60_0 .net8 "VPB", 0 0, L_0000000004053ef0;  1 drivers, strength-aware
+L_0000000004054a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc0360_0 .net8 "VPWR", 0 0, L_0000000004054a50;  1 drivers, strength-aware
+v0000000003bc0400_0 .net "X", 0 0, L_0000000004143690;  alias, 1 drivers
+v0000000003bc04a0_0 .net "and0_out_X", 0 0, L_0000000004142c80;  1 drivers
+v0000000003bc0680_0 .net "or0_out", 0 0, L_0000000004143000;  1 drivers
+S_0000000003be1170 .scope module, "_0915_" "sky130_fd_sc_hd__o221a_2" 3 2765, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003bc25c0_0 .net "A1", 0 0, L_000000000413fe20;  alias, 1 drivers
+v0000000003bc3e20_0 .net "A2", 0 0, L_0000000004142e40;  alias, 1 drivers
+v0000000003bc2340_0 .net "B1", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003bc3060_0 .net "B2", 0 0, L_0000000004142eb0;  alias, 1 drivers
+v0000000003bc31a0_0 .net "C1", 0 0, L_0000000004143690;  alias, 1 drivers
+L_0000000004054ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2ca0_0 .net8 "VGND", 0 0, L_0000000004054ac0;  1 drivers, strength-aware
+L_00000000040536a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc28e0_0 .net8 "VNB", 0 0, L_00000000040536a0;  1 drivers, strength-aware
+L_0000000004053cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2480_0 .net8 "VPB", 0 0, L_0000000004053cc0;  1 drivers, strength-aware
+L_0000000004054430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1f80_0 .net8 "VPWR", 0 0, L_0000000004054430;  1 drivers, strength-aware
+v0000000003bc3740_0 .net "X", 0 0, L_0000000004143d90;  alias, 1 drivers
+S_0000000003bdfaf0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003be1170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004143a10 .functor OR 1, L_0000000004142eb0, L_000000000413ca10, C4<0>, C4<0>;
+L_0000000004143af0 .functor OR 1, L_0000000004142e40, L_000000000413fe20, C4<0>, C4<0>;
+L_0000000004143ee0 .functor AND 1, L_0000000004143a10, L_0000000004143af0, L_0000000004143690, C4<1>;
+L_0000000004143d90 .functor BUF 1, L_0000000004143ee0, C4<0>, C4<0>, C4<0>;
+v0000000003bc2660_0 .net "A1", 0 0, L_000000000413fe20;  alias, 1 drivers
+v0000000003bc2840_0 .net "A2", 0 0, L_0000000004142e40;  alias, 1 drivers
+v0000000003bc2e80_0 .net "B1", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003bc2de0_0 .net "B2", 0 0, L_0000000004142eb0;  alias, 1 drivers
+v0000000003bc1940_0 .net "C1", 0 0, L_0000000004143690;  alias, 1 drivers
+L_0000000004054c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1d00_0 .net8 "VGND", 0 0, L_0000000004054c10;  1 drivers, strength-aware
+L_0000000004054c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2160_0 .net8 "VNB", 0 0, L_0000000004054c80;  1 drivers, strength-aware
+L_0000000004053940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2fc0_0 .net8 "VPB", 0 0, L_0000000004053940;  1 drivers, strength-aware
+L_00000000040530f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2980_0 .net8 "VPWR", 0 0, L_00000000040530f0;  1 drivers, strength-aware
+v0000000003bc1da0_0 .net "X", 0 0, L_0000000004143d90;  alias, 1 drivers
+v0000000003bc39c0_0 .net "and0_out_X", 0 0, L_0000000004143ee0;  1 drivers
+v0000000003bc2d40_0 .net "or0_out", 0 0, L_0000000004143a10;  1 drivers
+v0000000003bc1b20_0 .net "or1_out", 0 0, L_0000000004143af0;  1 drivers
+S_0000000003be1ef0 .scope module, "_0916_" "sky130_fd_sc_hd__a2bb2oi_2" 3 2773, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bc3920_0 .net "A1_N", 0 0, L_0000000004143a80;  alias, 1 drivers
+v0000000003bc2c00_0 .net "A2_N", 0 0, L_0000000004143d90;  alias, 1 drivers
+v0000000003bc3600_0 .net "B1", 0 0, L_0000000004143a80;  alias, 1 drivers
+v0000000003bc32e0_0 .net "B2", 0 0, L_0000000004143d90;  alias, 1 drivers
+L_0000000004053f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc3380_0 .net8 "VGND", 0 0, L_0000000004053f60;  1 drivers, strength-aware
+L_0000000004053160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2520_0 .net8 "VNB", 0 0, L_0000000004053160;  1 drivers, strength-aware
+L_00000000040531d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc36a0_0 .net8 "VPB", 0 0, L_00000000040531d0;  1 drivers, strength-aware
+L_0000000004053da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc37e0_0 .net8 "VPWR", 0 0, L_0000000004053da0;  1 drivers, strength-aware
+v0000000003bc2700_0 .net "Y", 0 0, L_0000000004143cb0;  alias, 1 drivers
+S_0000000003be15f0 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003be1ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004142970 .functor AND 1, L_0000000004143a80, L_0000000004143d90, C4<1>, C4<1>;
+L_0000000004143bd0 .functor NOR 1, L_0000000004143a80, L_0000000004143d90, C4<0>, C4<0>;
+L_0000000004143f50 .functor NOR 1, L_0000000004143bd0, L_0000000004142970, C4<0>, C4<0>;
+L_0000000004143cb0 .functor BUF 1, L_0000000004143f50, C4<0>, C4<0>, C4<0>;
+v0000000003bc23e0_0 .net "A1_N", 0 0, L_0000000004143a80;  alias, 1 drivers
+v0000000003bc22a0_0 .net "A2_N", 0 0, L_0000000004143d90;  alias, 1 drivers
+v0000000003bc3ba0_0 .net "B1", 0 0, L_0000000004143a80;  alias, 1 drivers
+v0000000003bc3ec0_0 .net "B2", 0 0, L_0000000004143d90;  alias, 1 drivers
+L_0000000004053240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2020_0 .net8 "VGND", 0 0, L_0000000004053240;  1 drivers, strength-aware
+L_0000000004053710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc19e0_0 .net8 "VNB", 0 0, L_0000000004053710;  1 drivers, strength-aware
+L_00000000040532b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1a80_0 .net8 "VPB", 0 0, L_00000000040532b0;  1 drivers, strength-aware
+L_00000000040539b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc3560_0 .net8 "VPWR", 0 0, L_00000000040539b0;  1 drivers, strength-aware
+v0000000003bc34c0_0 .net "Y", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003bc3100_0 .net "and0_out", 0 0, L_0000000004142970;  1 drivers
+v0000000003bc3240_0 .net "nor0_out", 0 0, L_0000000004143bd0;  1 drivers
+v0000000003bc3f60_0 .net "nor1_out_Y", 0 0, L_0000000004143f50;  1 drivers
+S_0000000003bdf7f0 .scope module, "_0917_" "sky130_fd_sc_hd__nor2_2" 3 2780, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bc3c40_0 .net "A", 0 0, L_0000000004143230;  alias, 1 drivers
+v0000000003bc2a20_0 .net "B", 0 0, L_0000000004143cb0;  alias, 1 drivers
+L_0000000004053320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1e40_0 .net8 "VGND", 0 0, L_0000000004053320;  1 drivers, strength-aware
+L_0000000004054120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1c60_0 .net8 "VNB", 0 0, L_0000000004054120;  1 drivers, strength-aware
+L_0000000004053fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2ac0_0 .net8 "VPB", 0 0, L_0000000004053fd0;  1 drivers, strength-aware
+L_0000000004053390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc2b60_0 .net8 "VPWR", 0 0, L_0000000004053390;  1 drivers, strength-aware
+v0000000003bc1ee0_0 .net "Y", 0 0, L_00000000041429e0;  alias, 1 drivers
+S_0000000003be2f70 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003bdf7f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004143c40 .functor NOR 1, L_0000000004143230, L_0000000004143cb0, C4<0>, C4<0>;
+L_00000000041429e0 .functor BUF 1, L_0000000004143c40, C4<0>, C4<0>, C4<0>;
+v0000000003bc3ce0_0 .net "A", 0 0, L_0000000004143230;  alias, 1 drivers
+v0000000003bc3880_0 .net "B", 0 0, L_0000000004143cb0;  alias, 1 drivers
+L_0000000004053470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc1bc0_0 .net8 "VGND", 0 0, L_0000000004053470;  1 drivers, strength-aware
+L_00000000040534e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc3420_0 .net8 "VNB", 0 0, L_00000000040534e0;  1 drivers, strength-aware
+L_0000000004053550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc3a60_0 .net8 "VPB", 0 0, L_0000000004053550;  1 drivers, strength-aware
+L_0000000004053630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc20c0_0 .net8 "VPWR", 0 0, L_0000000004053630;  1 drivers, strength-aware
+v0000000003bc3b00_0 .net "Y", 0 0, L_00000000041429e0;  alias, 1 drivers
+v0000000003bc3d80_0 .net "nor0_out_Y", 0 0, L_0000000004143c40;  1 drivers
+S_0000000003bdf070 .scope module, "_0918_" "sky130_fd_sc_hd__a21oi_2" 3 2785, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bc6620_0 .net "A1", 0 0, L_0000000004143230;  alias, 1 drivers
+v0000000003bc64e0_0 .net "A2", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003bc4f00_0 .net "B1", 0 0, L_00000000041429e0;  alias, 1 drivers
+L_0000000004053780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc41e0_0 .net8 "VGND", 0 0, L_0000000004053780;  1 drivers, strength-aware
+L_0000000004053e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6120_0 .net8 "VNB", 0 0, L_0000000004053e80;  1 drivers, strength-aware
+L_00000000040537f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5a40_0 .net8 "VPB", 0 0, L_00000000040537f0;  1 drivers, strength-aware
+L_0000000004053860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5ae0_0 .net8 "VPWR", 0 0, L_0000000004053860;  1 drivers, strength-aware
+v0000000003bc5040_0 .net "Y", 0 0, L_0000000004124910;  alias, 1 drivers
+S_0000000003bdf1f0 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003bdf070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004143d20 .functor AND 1, L_0000000004143230, L_0000000004143cb0, C4<1>, C4<1>;
+L_0000000004142f20 .functor NOR 1, L_00000000041429e0, L_0000000004143d20, C4<0>, C4<0>;
+L_0000000004124910 .functor BUF 1, L_0000000004142f20, C4<0>, C4<0>, C4<0>;
+v0000000003bc2200_0 .net "A1", 0 0, L_0000000004143230;  alias, 1 drivers
+v0000000003bc4500_0 .net "A2", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003bc68a0_0 .net "B1", 0 0, L_00000000041429e0;  alias, 1 drivers
+L_0000000004053a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6080_0 .net8 "VGND", 0 0, L_0000000004053a20;  1 drivers, strength-aware
+L_0000000004053b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4140_0 .net8 "VNB", 0 0, L_0000000004053b00;  1 drivers, strength-aware
+L_0000000004053be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc59a0_0 .net8 "VPB", 0 0, L_0000000004053be0;  1 drivers, strength-aware
+L_0000000004053d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5c20_0 .net8 "VPWR", 0 0, L_0000000004053d30;  1 drivers, strength-aware
+v0000000003bc5cc0_0 .net "Y", 0 0, L_0000000004124910;  alias, 1 drivers
+v0000000003bc6440_0 .net "and0_out", 0 0, L_0000000004143d20;  1 drivers
+v0000000003bc6800_0 .net "nor0_out_Y", 0 0, L_0000000004142f20;  1 drivers
+S_0000000003be21f0 .scope module, "_0919_" "sky130_fd_sc_hd__or2b_2" 3 2791, 4 56400 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+v0000000003bc57c0_0 .net "A", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000003bc50e0_0 .net "B_N", 0 0, L_000000000412cef0;  alias, 1 drivers
+L_0000000004054190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4320_0 .net8 "VGND", 0 0, L_0000000004054190;  1 drivers, strength-aware
+L_0000000004053e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4c80_0 .net8 "VNB", 0 0, L_0000000004053e10;  1 drivers, strength-aware
+L_0000000004055620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4780_0 .net8 "VPB", 0 0, L_0000000004055620;  1 drivers, strength-aware
+L_0000000004055930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5fe0_0 .net8 "VPWR", 0 0, L_0000000004055930;  1 drivers, strength-aware
+v0000000003bc43c0_0 .net "X", 0 0, L_0000000004124590;  alias, 1 drivers
+S_0000000003bdf370 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56416, 4 56915 1, S_0000000003be21f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004123870 .functor NOT 1, L_000000000412cef0, C4<0>, C4<0>, C4<0>;
+L_00000000041234f0 .functor OR 1, L_0000000004123870, L_000000000412e150, C4<0>, C4<0>;
+L_0000000004124590 .functor BUF 1, L_00000000041234f0, C4<0>, C4<0>, C4<0>;
+v0000000003bc5680_0 .net "A", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000003bc4820_0 .net "B_N", 0 0, L_000000000412cef0;  alias, 1 drivers
+L_0000000004054f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc45a0_0 .net8 "VGND", 0 0, L_0000000004054f90;  1 drivers, strength-aware
+L_0000000004055e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6580_0 .net8 "VNB", 0 0, L_0000000004055e70;  1 drivers, strength-aware
+L_0000000004055c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5720_0 .net8 "VPB", 0 0, L_0000000004055c40;  1 drivers, strength-aware
+L_00000000040566c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5860_0 .net8 "VPWR", 0 0, L_00000000040566c0;  1 drivers, strength-aware
+v0000000003bc5b80_0 .net "X", 0 0, L_0000000004124590;  alias, 1 drivers
+v0000000003bc4280_0 .net "not0_out", 0 0, L_0000000004123870;  1 drivers
+v0000000003bc5f40_0 .net "or0_out_X", 0 0, L_00000000041234f0;  1 drivers
+S_0000000003be30f0 .scope module, "_0920_" "sky130_fd_sc_hd__or2_2" 3 2796, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bc5e00_0 .net "A", 0 0, L_00000000041381e0;  alias, 1 drivers
+v0000000003bc6300_0 .net "B", 0 0, L_0000000004131090;  alias, 1 drivers
+L_0000000004054cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc66c0_0 .net8 "VGND", 0 0, L_0000000004054cf0;  1 drivers, strength-aware
+L_0000000004055000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5ea0_0 .net8 "VNB", 0 0, L_0000000004055000;  1 drivers, strength-aware
+L_0000000004056730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6760_0 .net8 "VPB", 0 0, L_0000000004056730;  1 drivers, strength-aware
+L_00000000040551c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5220_0 .net8 "VPWR", 0 0, L_00000000040551c0;  1 drivers, strength-aware
+v0000000003bc46e0_0 .net "X", 0 0, L_0000000004123170;  alias, 1 drivers
+S_0000000003be03f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be30f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004123950 .functor OR 1, L_0000000004131090, L_00000000041381e0, C4<0>, C4<0>;
+L_0000000004123170 .functor BUF 1, L_0000000004123950, C4<0>, C4<0>, C4<0>;
+v0000000003bc5180_0 .net "A", 0 0, L_00000000041381e0;  alias, 1 drivers
+v0000000003bc61c0_0 .net "B", 0 0, L_0000000004131090;  alias, 1 drivers
+L_00000000040553f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6260_0 .net8 "VGND", 0 0, L_00000000040553f0;  1 drivers, strength-aware
+L_00000000040567a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5900_0 .net8 "VNB", 0 0, L_00000000040567a0;  1 drivers, strength-aware
+L_00000000040562d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc48c0_0 .net8 "VPB", 0 0, L_00000000040562d0;  1 drivers, strength-aware
+L_0000000004055310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4460_0 .net8 "VPWR", 0 0, L_0000000004055310;  1 drivers, strength-aware
+v0000000003bc4640_0 .net "X", 0 0, L_0000000004123170;  alias, 1 drivers
+v0000000003bc5d60_0 .net "or0_out_X", 0 0, L_0000000004123950;  1 drivers
+S_0000000003be3cf0 .scope module, "_0921_" "sky130_fd_sc_hd__o21a_2" 3 2801, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bc4fa0_0 .net "A1", 0 0, L_00000000041381e0;  alias, 1 drivers
+v0000000003bc5360_0 .net "A2", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003bc5540_0 .net "B1", 0 0, L_000000000412e460;  alias, 1 drivers
+L_0000000004056260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc5400_0 .net8 "VGND", 0 0, L_0000000004056260;  1 drivers, strength-aware
+L_0000000004055cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc54a0_0 .net8 "VNB", 0 0, L_0000000004055cb0;  1 drivers, strength-aware
+L_0000000004056810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc55e0_0 .net8 "VPB", 0 0, L_0000000004056810;  1 drivers, strength-aware
+L_0000000004056110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8600_0 .net8 "VPWR", 0 0, L_0000000004056110;  1 drivers, strength-aware
+v0000000003bc8ce0_0 .net "X", 0 0, L_00000000041238e0;  alias, 1 drivers
+S_0000000003be3e70 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003be3cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041249f0 .functor OR 1, L_0000000004131250, L_00000000041381e0, C4<0>, C4<0>;
+L_0000000004124670 .functor AND 1, L_00000000041249f0, L_000000000412e460, C4<1>, C4<1>;
+L_00000000041238e0 .functor BUF 1, L_0000000004124670, C4<0>, C4<0>, C4<0>;
+v0000000003bc4d20_0 .net "A1", 0 0, L_00000000041381e0;  alias, 1 drivers
+v0000000003bc63a0_0 .net "A2", 0 0, L_0000000004131250;  alias, 1 drivers
+v0000000003bc4be0_0 .net "B1", 0 0, L_000000000412e460;  alias, 1 drivers
+L_0000000004055070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc52c0_0 .net8 "VGND", 0 0, L_0000000004055070;  1 drivers, strength-aware
+L_00000000040550e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4960_0 .net8 "VNB", 0 0, L_00000000040550e0;  1 drivers, strength-aware
+L_0000000004055a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4dc0_0 .net8 "VPB", 0 0, L_0000000004055a80;  1 drivers, strength-aware
+L_00000000040563b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc4a00_0 .net8 "VPWR", 0 0, L_00000000040563b0;  1 drivers, strength-aware
+v0000000003bc4aa0_0 .net "X", 0 0, L_00000000041238e0;  alias, 1 drivers
+v0000000003bc4b40_0 .net "and0_out_X", 0 0, L_0000000004124670;  1 drivers
+v0000000003bc4e60_0 .net "or0_out", 0 0, L_00000000041249f0;  1 drivers
+S_0000000003be42f0 .scope module, "_0922_" "sky130_fd_sc_hd__and2_2" 3 2807, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bc84c0_0 .net "A", 0 0, L_000000000412e460;  alias, 1 drivers
+v0000000003bc89c0_0 .net "B", 0 0, L_0000000004123170;  alias, 1 drivers
+L_0000000004056030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7b60_0 .net8 "VGND", 0 0, L_0000000004056030;  1 drivers, strength-aware
+L_0000000004056880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6c60_0 .net8 "VNB", 0 0, L_0000000004056880;  1 drivers, strength-aware
+L_0000000004056180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8560_0 .net8 "VPB", 0 0, L_0000000004056180;  1 drivers, strength-aware
+L_0000000004055a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6da0_0 .net8 "VPWR", 0 0, L_0000000004055a10;  1 drivers, strength-aware
+v0000000003bc7480_0 .net "X", 0 0, L_0000000004123d40;  alias, 1 drivers
+S_0000000003be3ff0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003be42f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004123640 .functor AND 1, L_000000000412e460, L_0000000004123170, C4<1>, C4<1>;
+L_0000000004123d40 .functor BUF 1, L_0000000004123640, C4<0>, C4<0>, C4<0>;
+v0000000003bc8420_0 .net "A", 0 0, L_000000000412e460;  alias, 1 drivers
+v0000000003bc69e0_0 .net "B", 0 0, L_0000000004123170;  alias, 1 drivers
+L_00000000040554d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6d00_0 .net8 "VGND", 0 0, L_00000000040554d0;  1 drivers, strength-aware
+L_0000000004055460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7ca0_0 .net8 "VNB", 0 0, L_0000000004055460;  1 drivers, strength-aware
+L_0000000004054dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc87e0_0 .net8 "VPB", 0 0, L_0000000004054dd0;  1 drivers, strength-aware
+L_0000000004055690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8d80_0 .net8 "VPWR", 0 0, L_0000000004055690;  1 drivers, strength-aware
+v0000000003bc7520_0 .net "X", 0 0, L_0000000004123d40;  alias, 1 drivers
+v0000000003bc86a0_0 .net "and0_out_X", 0 0, L_0000000004123640;  1 drivers
+S_0000000003bdfc70 .scope module, "_0923_" "sky130_fd_sc_hd__or3_2" 3 2812, 4 49901 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003bc7fc0_0 .net "A", 0 0, L_0000000004140910;  alias, 1 drivers
+v0000000003bc6f80_0 .net "B", 0 0, L_0000000004123d40;  alias, 1 drivers
+v0000000003bc8e20_0 .net "C", 0 0, L_000000000413e1b0;  alias, 1 drivers
+L_0000000004055380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7020_0 .net8 "VGND", 0 0, L_0000000004055380;  1 drivers, strength-aware
+L_0000000004056420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8ec0_0 .net8 "VNB", 0 0, L_0000000004056420;  1 drivers, strength-aware
+L_0000000004055f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7160_0 .net8 "VPB", 0 0, L_0000000004055f50;  1 drivers, strength-aware
+L_0000000004055770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8240_0 .net8 "VPWR", 0 0, L_0000000004055770;  1 drivers, strength-aware
+v0000000003bc72a0_0 .net "X", 0 0, L_0000000004123e20;  alias, 1 drivers
+S_0000000003be1770 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_0000000003bdfc70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004123db0 .functor OR 1, L_0000000004123d40, L_0000000004140910, L_000000000413e1b0, C4<0>;
+L_0000000004123e20 .functor BUF 1, L_0000000004123db0, C4<0>, C4<0>, C4<0>;
+v0000000003bc70c0_0 .net "A", 0 0, L_0000000004140910;  alias, 1 drivers
+v0000000003bc8740_0 .net "B", 0 0, L_0000000004123d40;  alias, 1 drivers
+v0000000003bc9000_0 .net "C", 0 0, L_000000000413e1b0;  alias, 1 drivers
+L_0000000004056340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc75c0_0 .net8 "VGND", 0 0, L_0000000004056340;  1 drivers, strength-aware
+L_00000000040557e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7200_0 .net8 "VNB", 0 0, L_00000000040557e0;  1 drivers, strength-aware
+L_0000000004055e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7a20_0 .net8 "VPB", 0 0, L_0000000004055e00;  1 drivers, strength-aware
+L_0000000004055540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc6e40_0 .net8 "VPWR", 0 0, L_0000000004055540;  1 drivers, strength-aware
+v0000000003bc6ee0_0 .net "X", 0 0, L_0000000004123e20;  alias, 1 drivers
+v0000000003bc8880_0 .net "or0_out_X", 0 0, L_0000000004123db0;  1 drivers
+S_0000000003be1a70 .scope module, "_0924_" "sky130_fd_sc_hd__o211ai_2" 3 2818, 4 78520 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003bc7de0_0 .net "A1", 0 0, L_0000000004123170;  alias, 1 drivers
+v0000000003bc6940_0 .net "A2", 0 0, L_00000000041425f0;  alias, 1 drivers
+v0000000003bc6a80_0 .net "B1", 0 0, L_00000000041238e0;  alias, 1 drivers
+v0000000003bc7980_0 .net "C1", 0 0, L_0000000004123e20;  alias, 1 drivers
+L_0000000004055230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7ac0_0 .net8 "VGND", 0 0, L_0000000004055230;  1 drivers, strength-aware
+L_00000000040555b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8920_0 .net8 "VNB", 0 0, L_00000000040555b0;  1 drivers, strength-aware
+L_0000000004055150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7c00_0 .net8 "VPB", 0 0, L_0000000004055150;  1 drivers, strength-aware
+L_0000000004055700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7d40_0 .net8 "VPWR", 0 0, L_0000000004055700;  1 drivers, strength-aware
+v0000000003bc8b00_0 .net "Y", 0 0, L_0000000004123f70;  alias, 1 drivers
+S_0000000003be4170 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 78540, 4 78275 1, S_0000000003be1a70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004124a60 .functor OR 1, L_00000000041425f0, L_0000000004123170, C4<0>, C4<0>;
+L_0000000004123fe0 .functor NAND 1, L_0000000004123e20, L_0000000004124a60, L_00000000041238e0, C4<1>;
+L_0000000004123f70 .functor BUF 1, L_0000000004123fe0, C4<0>, C4<0>, C4<0>;
+v0000000003bc7340_0 .net "A1", 0 0, L_0000000004123170;  alias, 1 drivers
+v0000000003bc73e0_0 .net "A2", 0 0, L_00000000041425f0;  alias, 1 drivers
+v0000000003bc7660_0 .net "B1", 0 0, L_00000000041238e0;  alias, 1 drivers
+v0000000003bc90a0_0 .net "C1", 0 0, L_0000000004123e20;  alias, 1 drivers
+L_0000000004055ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8f60_0 .net8 "VGND", 0 0, L_0000000004055ee0;  1 drivers, strength-aware
+L_0000000004054f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc82e0_0 .net8 "VNB", 0 0, L_0000000004054f20;  1 drivers, strength-aware
+L_0000000004055850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7700_0 .net8 "VPB", 0 0, L_0000000004055850;  1 drivers, strength-aware
+L_00000000040552a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8a60_0 .net8 "VPWR", 0 0, L_00000000040552a0;  1 drivers, strength-aware
+v0000000003bc77a0_0 .net "Y", 0 0, L_0000000004123f70;  alias, 1 drivers
+v0000000003bc7840_0 .net "nand0_out_Y", 0 0, L_0000000004123fe0;  1 drivers
+v0000000003bc78e0_0 .net "or0_out", 0 0, L_0000000004124a60;  1 drivers
+S_0000000003bdfdf0 .scope module, "_0925_" "sky130_fd_sc_hd__a2bb2o_2" 3 2825, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bcb4e0_0 .net "A1_N", 0 0, L_0000000004124590;  alias, 1 drivers
+v0000000003bc95a0_0 .net "A2_N", 0 0, L_0000000004123f70;  alias, 1 drivers
+v0000000003bcb800_0 .net "B1", 0 0, L_0000000004124590;  alias, 1 drivers
+v0000000003bcb3a0_0 .net "B2", 0 0, L_0000000004123f70;  alias, 1 drivers
+L_00000000040565e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bca9a0_0 .net8 "VGND", 0 0, L_00000000040565e0;  1 drivers, strength-aware
+L_0000000004054d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcb080_0 .net8 "VNB", 0 0, L_0000000004054d60;  1 drivers, strength-aware
+L_00000000040559a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9aa0_0 .net8 "VPB", 0 0, L_00000000040559a0;  1 drivers, strength-aware
+L_00000000040561f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9820_0 .net8 "VPWR", 0 0, L_00000000040561f0;  1 drivers, strength-aware
+v0000000003bc9fa0_0 .net "X", 0 0, L_0000000004124520;  alias, 1 drivers
+S_0000000003bdff70 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003bdfdf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041231e0 .functor AND 1, L_0000000004124590, L_0000000004123f70, C4<1>, C4<1>;
+L_0000000004124440 .functor NOR 1, L_0000000004124590, L_0000000004123f70, C4<0>, C4<0>;
+L_00000000041244b0 .functor OR 1, L_0000000004124440, L_00000000041231e0, C4<0>, C4<0>;
+L_0000000004124520 .functor BUF 1, L_00000000041244b0, C4<0>, C4<0>, C4<0>;
+v0000000003bc7e80_0 .net "A1_N", 0 0, L_0000000004124590;  alias, 1 drivers
+v0000000003bc81a0_0 .net "A2_N", 0 0, L_0000000004123f70;  alias, 1 drivers
+v0000000003bc6b20_0 .net "B1", 0 0, L_0000000004124590;  alias, 1 drivers
+v0000000003bc6bc0_0 .net "B2", 0 0, L_0000000004123f70;  alias, 1 drivers
+L_0000000004054eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc7f20_0 .net8 "VGND", 0 0, L_0000000004054eb0;  1 drivers, strength-aware
+L_0000000004055af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8060_0 .net8 "VNB", 0 0, L_0000000004055af0;  1 drivers, strength-aware
+L_0000000004055b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8ba0_0 .net8 "VPB", 0 0, L_0000000004055b60;  1 drivers, strength-aware
+L_00000000040558c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc8100_0 .net8 "VPWR", 0 0, L_00000000040558c0;  1 drivers, strength-aware
+v0000000003bc8380_0 .net "X", 0 0, L_0000000004124520;  alias, 1 drivers
+v0000000003bc8c40_0 .net "and0_out", 0 0, L_00000000041231e0;  1 drivers
+v0000000003bca540_0 .net "nor0_out", 0 0, L_0000000004124440;  1 drivers
+v0000000003bcaa40_0 .net "or0_out_X", 0 0, L_00000000041244b0;  1 drivers
+S_0000000003be00f0 .scope module, "_0926_" "sky130_fd_sc_hd__a2bb2o_2" 3 2832, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bc98c0_0 .net "A1_N", 0 0, L_00000000041429e0;  alias, 1 drivers
+v0000000003bc93c0_0 .net "A2_N", 0 0, L_0000000004124520;  alias, 1 drivers
+v0000000003bcb580_0 .net "B1", 0 0, L_00000000041429e0;  alias, 1 drivers
+v0000000003bcac20_0 .net "B2", 0 0, L_0000000004124520;  alias, 1 drivers
+L_0000000004055bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9d20_0 .net8 "VGND", 0 0, L_0000000004055bd0;  1 drivers, strength-aware
+L_0000000004055fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcb260_0 .net8 "VNB", 0 0, L_0000000004055fc0;  1 drivers, strength-aware
+L_0000000004055d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bca220_0 .net8 "VPB", 0 0, L_0000000004055d20;  1 drivers, strength-aware
+L_0000000004054e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9640_0 .net8 "VPWR", 0 0, L_0000000004054e40;  1 drivers, strength-aware
+v0000000003bc9780_0 .net "X", 0 0, L_00000000041242f0;  alias, 1 drivers
+S_0000000003be0570 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003be00f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004123f00 .functor AND 1, L_00000000041429e0, L_0000000004124520, C4<1>, C4<1>;
+L_00000000041246e0 .functor NOR 1, L_00000000041429e0, L_0000000004124520, C4<0>, C4<0>;
+L_0000000004124b40 .functor OR 1, L_00000000041246e0, L_0000000004123f00, C4<0>, C4<0>;
+L_00000000041242f0 .functor BUF 1, L_0000000004124b40, C4<0>, C4<0>, C4<0>;
+v0000000003bcad60_0 .net "A1_N", 0 0, L_00000000041429e0;  alias, 1 drivers
+v0000000003bc96e0_0 .net "A2_N", 0 0, L_0000000004124520;  alias, 1 drivers
+v0000000003bcb1c0_0 .net "B1", 0 0, L_00000000041429e0;  alias, 1 drivers
+v0000000003bca360_0 .net "B2", 0 0, L_0000000004124520;  alias, 1 drivers
+L_0000000004055d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcafe0_0 .net8 "VGND", 0 0, L_0000000004055d90;  1 drivers, strength-aware
+L_0000000004056490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcaf40_0 .net8 "VNB", 0 0, L_0000000004056490;  1 drivers, strength-aware
+L_0000000004056500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9f00_0 .net8 "VPB", 0 0, L_0000000004056500;  1 drivers, strength-aware
+L_00000000040560a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9500_0 .net8 "VPWR", 0 0, L_00000000040560a0;  1 drivers, strength-aware
+v0000000003bc9c80_0 .net "X", 0 0, L_00000000041242f0;  alias, 1 drivers
+v0000000003bc9320_0 .net "and0_out", 0 0, L_0000000004123f00;  1 drivers
+v0000000003bcb120_0 .net "nor0_out", 0 0, L_00000000041246e0;  1 drivers
+v0000000003bca4a0_0 .net "or0_out_X", 0 0, L_0000000004124b40;  1 drivers
+S_0000000003be18f0 .scope module, "_0927_" "sky130_fd_sc_hd__o21ai_2" 3 2839, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bc9140_0 .net "A1", 0 0, L_000000000412b590;  alias, 1 drivers
+v0000000003bca040_0 .net "A2", 0 0, L_000000000412b210;  alias, 1 drivers
+v0000000003bc91e0_0 .net "B1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+L_0000000004056570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9280_0 .net8 "VGND", 0 0, L_0000000004056570;  1 drivers, strength-aware
+L_0000000004056650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9460_0 .net8 "VNB", 0 0, L_0000000004056650;  1 drivers, strength-aware
+L_00000000040571b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9e60_0 .net8 "VPB", 0 0, L_00000000040571b0;  1 drivers, strength-aware
+L_0000000004057ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcb440_0 .net8 "VPWR", 0 0, L_0000000004057ca0;  1 drivers, strength-aware
+v0000000003bc9a00_0 .net "Y", 0 0, L_00000000041232c0;  alias, 1 drivers
+S_0000000003be06f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be18f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004124600 .functor OR 1, L_000000000412b210, L_000000000412b590, C4<0>, C4<0>;
+L_0000000004124050 .functor NAND 1, L_000000000412d7b0, L_0000000004124600, C4<1>, C4<1>;
+L_00000000041232c0 .functor BUF 1, L_0000000004124050, C4<0>, C4<0>, C4<0>;
+v0000000003bcb620_0 .net "A1", 0 0, L_000000000412b590;  alias, 1 drivers
+v0000000003bcb300_0 .net "A2", 0 0, L_000000000412b210;  alias, 1 drivers
+v0000000003bcb6c0_0 .net "B1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+L_0000000004057300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9960_0 .net8 "VGND", 0 0, L_0000000004057300;  1 drivers, strength-aware
+L_00000000040574c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bca720_0 .net8 "VNB", 0 0, L_00000000040574c0;  1 drivers, strength-aware
+L_0000000004057fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcb760_0 .net8 "VPB", 0 0, L_0000000004057fb0;  1 drivers, strength-aware
+L_00000000040569d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bca2c0_0 .net8 "VPWR", 0 0, L_00000000040569d0;  1 drivers, strength-aware
+v0000000003bcb8a0_0 .net "Y", 0 0, L_00000000041232c0;  alias, 1 drivers
+v0000000003bcaae0_0 .net "nand0_out_Y", 0 0, L_0000000004124050;  1 drivers
+v0000000003bca5e0_0 .net "or0_out", 0 0, L_0000000004124600;  1 drivers
+S_0000000003be0cf0 .scope module, "_0928_" "sky130_fd_sc_hd__o21ai_2" 3 2845, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bcae00_0 .net "A1", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000003bca900_0 .net "A2", 0 0, L_00000000041385d0;  alias, 1 drivers
+v0000000003bcacc0_0 .net "B1", 0 0, L_000000000412cef0;  alias, 1 drivers
+L_0000000004057c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcaea0_0 .net8 "VGND", 0 0, L_0000000004057c30;  1 drivers, strength-aware
+L_0000000004057a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bccca0_0 .net8 "VNB", 0 0, L_0000000004057a70;  1 drivers, strength-aware
+L_0000000004058250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcb940_0 .net8 "VPB", 0 0, L_0000000004058250;  1 drivers, strength-aware
+L_00000000040581e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bce0a0_0 .net8 "VPWR", 0 0, L_00000000040581e0;  1 drivers, strength-aware
+v0000000003bcb9e0_0 .net "Y", 0 0, L_0000000004124ad0;  alias, 1 drivers
+S_0000000003be2370 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be0cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004123e90 .functor OR 1, L_00000000041385d0, L_000000000412e150, C4<0>, C4<0>;
+L_0000000004123330 .functor NAND 1, L_000000000412cef0, L_0000000004123e90, C4<1>, C4<1>;
+L_0000000004124ad0 .functor BUF 1, L_0000000004123330, C4<0>, C4<0>, C4<0>;
+v0000000003bcab80_0 .net "A1", 0 0, L_000000000412e150;  alias, 1 drivers
+v0000000003bc9b40_0 .net "A2", 0 0, L_00000000041385d0;  alias, 1 drivers
+v0000000003bc9be0_0 .net "B1", 0 0, L_000000000412cef0;  alias, 1 drivers
+L_0000000004057ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bc9dc0_0 .net8 "VGND", 0 0, L_0000000004057ae0;  1 drivers, strength-aware
+L_0000000004057df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bca0e0_0 .net8 "VNB", 0 0, L_0000000004057df0;  1 drivers, strength-aware
+L_00000000040576f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bca180_0 .net8 "VPB", 0 0, L_00000000040576f0;  1 drivers, strength-aware
+L_0000000004057760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bca400_0 .net8 "VPWR", 0 0, L_0000000004057760;  1 drivers, strength-aware
+v0000000003bca680_0 .net "Y", 0 0, L_0000000004124ad0;  alias, 1 drivers
+v0000000003bca7c0_0 .net "nand0_out_Y", 0 0, L_0000000004123330;  1 drivers
+v0000000003bca860_0 .net "or0_out", 0 0, L_0000000004123e90;  1 drivers
+S_0000000003be1470 .scope module, "_0929_" "sky130_fd_sc_hd__o21bai_2" 3 2851, 4 60892 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+v0000000003bcd2e0_0 .net "A1", 0 0, L_000000000412c2b0;  alias, 1 drivers
+v0000000003bcc660_0 .net "A2", 0 0, L_0000000004142900;  alias, 1 drivers
+v0000000003bcda60_0 .net "B1_N", 0 0, L_0000000004124ad0;  alias, 1 drivers
+L_0000000004057370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcbda0_0 .net8 "VGND", 0 0, L_0000000004057370;  1 drivers, strength-aware
+L_00000000040570d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd1a0_0 .net8 "VNB", 0 0, L_00000000040570d0;  1 drivers, strength-aware
+L_0000000004057b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcc700_0 .net8 "VPB", 0 0, L_0000000004057b50;  1 drivers, strength-aware
+L_0000000004056b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd380_0 .net8 "VPWR", 0 0, L_0000000004056b20;  1 drivers, strength-aware
+v0000000003bcc840_0 .net "Y", 0 0, L_0000000004123100;  alias, 1 drivers
+S_0000000003be2070 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 60910, 4 61340 1, S_0000000003be1470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_0000000004124bb0 .functor NOT 1, L_0000000004124ad0, C4<0>, C4<0>, C4<0>;
+L_0000000004123800 .functor OR 1, L_0000000004142900, L_000000000412c2b0, C4<0>, C4<0>;
+L_00000000041241a0 .functor NAND 1, L_0000000004124bb0, L_0000000004123800, C4<1>, C4<1>;
+L_0000000004123100 .functor BUF 1, L_00000000041241a0, C4<0>, C4<0>, C4<0>;
+v0000000003bcc480_0 .net "A1", 0 0, L_000000000412c2b0;  alias, 1 drivers
+v0000000003bcde20_0 .net "A2", 0 0, L_0000000004142900;  alias, 1 drivers
+v0000000003bcbee0_0 .net "B1_N", 0 0, L_0000000004124ad0;  alias, 1 drivers
+L_00000000040582c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd9c0_0 .net8 "VGND", 0 0, L_00000000040582c0;  1 drivers, strength-aware
+L_0000000004058330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcdba0_0 .net8 "VNB", 0 0, L_0000000004058330;  1 drivers, strength-aware
+L_0000000004057d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bccac0_0 .net8 "VPB", 0 0, L_0000000004057d10;  1 drivers, strength-aware
+L_0000000004056f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bccd40_0 .net8 "VPWR", 0 0, L_0000000004056f10;  1 drivers, strength-aware
+v0000000003bcc200_0 .net "Y", 0 0, L_0000000004123100;  alias, 1 drivers
+v0000000003bccf20_0 .net "b", 0 0, L_0000000004124bb0;  1 drivers
+v0000000003bcba80_0 .net "nand0_out_Y", 0 0, L_00000000041241a0;  1 drivers
+v0000000003bcc7a0_0 .net "or0_out", 0 0, L_0000000004123800;  1 drivers
+S_0000000003be24f0 .scope module, "_0930_" "sky130_fd_sc_hd__o21ai_2" 3 2857, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bcc8e0_0 .net "A1", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000003bcc520_0 .net "A2", 0 0, L_0000000004143e00;  alias, 1 drivers
+v0000000003bcbf80_0 .net "B1", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000004056f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd600_0 .net8 "VGND", 0 0, L_0000000004056f80;  1 drivers, strength-aware
+L_00000000040577d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcc3e0_0 .net8 "VNB", 0 0, L_00000000040577d0;  1 drivers, strength-aware
+L_0000000004056c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcbbc0_0 .net8 "VPB", 0 0, L_0000000004056c70;  1 drivers, strength-aware
+L_00000000040573e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bccde0_0 .net8 "VPWR", 0 0, L_00000000040573e0;  1 drivers, strength-aware
+v0000000003bcd4c0_0 .net "Y", 0 0, L_0000000004123250;  alias, 1 drivers
+S_0000000003be2670 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be24f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004123b80 .functor OR 1, L_0000000004143e00, L_000000000412bec0, C4<0>, C4<0>;
+L_00000000041233a0 .functor NAND 1, L_000000000412c010, L_0000000004123b80, C4<1>, C4<1>;
+L_0000000004123250 .functor BUF 1, L_00000000041233a0, C4<0>, C4<0>, C4<0>;
+v0000000003bcc020_0 .net "A1", 0 0, L_000000000412bec0;  alias, 1 drivers
+v0000000003bcbd00_0 .net "A2", 0 0, L_0000000004143e00;  alias, 1 drivers
+v0000000003bcdce0_0 .net "B1", 0 0, L_000000000412c010;  alias, 1 drivers
+L_0000000004056ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bccfc0_0 .net8 "VGND", 0 0, L_0000000004056ce0;  1 drivers, strength-aware
+L_0000000004056d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcbe40_0 .net8 "VNB", 0 0, L_0000000004056d50;  1 drivers, strength-aware
+L_0000000004057bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd420_0 .net8 "VPB", 0 0, L_0000000004057bc0;  1 drivers, strength-aware
+L_0000000004057e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcbb20_0 .net8 "VPWR", 0 0, L_0000000004057e60;  1 drivers, strength-aware
+v0000000003bcd740_0 .net "Y", 0 0, L_0000000004123250;  alias, 1 drivers
+v0000000003bcd560_0 .net "nand0_out_Y", 0 0, L_00000000041233a0;  1 drivers
+v0000000003bcc340_0 .net "or0_out", 0 0, L_0000000004123b80;  1 drivers
+S_0000000003be27f0 .scope module, "_0931_" "sky130_fd_sc_hd__o21a_2" 3 2863, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bcc980_0 .net "A1", 0 0, L_0000000004143770;  alias, 1 drivers
+v0000000003bcd240_0 .net "A2", 0 0, L_0000000004124ad0;  alias, 1 drivers
+v0000000003bcd880_0 .net "B1", 0 0, L_0000000004123250;  alias, 1 drivers
+L_0000000004057450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcc0c0_0 .net8 "VGND", 0 0, L_0000000004057450;  1 drivers, strength-aware
+L_0000000004057530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd100_0 .net8 "VNB", 0 0, L_0000000004057530;  1 drivers, strength-aware
+L_0000000004058410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcc160_0 .net8 "VPB", 0 0, L_0000000004058410;  1 drivers, strength-aware
+L_00000000040575a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcca20_0 .net8 "VPWR", 0 0, L_00000000040575a0;  1 drivers, strength-aware
+v0000000003bcd920_0 .net "X", 0 0, L_00000000041239c0;  alias, 1 drivers
+S_0000000003be2970 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003be27f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004124280 .functor OR 1, L_0000000004124ad0, L_0000000004143770, C4<0>, C4<0>;
+L_0000000004123bf0 .functor AND 1, L_0000000004124280, L_0000000004123250, C4<1>, C4<1>;
+L_00000000041239c0 .functor BUF 1, L_0000000004123bf0, C4<0>, C4<0>, C4<0>;
+v0000000003bcdc40_0 .net "A1", 0 0, L_0000000004143770;  alias, 1 drivers
+v0000000003bcdec0_0 .net "A2", 0 0, L_0000000004124ad0;  alias, 1 drivers
+v0000000003bcdb00_0 .net "B1", 0 0, L_0000000004123250;  alias, 1 drivers
+L_0000000004056e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcbc60_0 .net8 "VGND", 0 0, L_0000000004056e30;  1 drivers, strength-aware
+L_0000000004057840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd6a0_0 .net8 "VNB", 0 0, L_0000000004057840;  1 drivers, strength-aware
+L_00000000040583a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd7e0_0 .net8 "VPB", 0 0, L_00000000040583a0;  1 drivers, strength-aware
+L_0000000004057220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcd060_0 .net8 "VPWR", 0 0, L_0000000004057220;  1 drivers, strength-aware
+v0000000003bcce80_0 .net "X", 0 0, L_00000000041239c0;  alias, 1 drivers
+v0000000003bcdf60_0 .net "and0_out_X", 0 0, L_0000000004123bf0;  1 drivers
+v0000000003bccb60_0 .net "or0_out", 0 0, L_0000000004124280;  1 drivers
+S_0000000003be8070 .scope module, "_0932_" "sky130_fd_sc_hd__and2_2" 3 2869, 4 52012 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bce640_0 .net "A", 0 0, L_0000000004123100;  alias, 1 drivers
+v0000000003bce140_0 .net "B", 0 0, L_0000000004123250;  alias, 1 drivers
+L_0000000004058480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf0e0_0 .net8 "VGND", 0 0, L_0000000004058480;  1 drivers, strength-aware
+L_00000000040568f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0120_0 .net8 "VNB", 0 0, L_00000000040568f0;  1 drivers, strength-aware
+L_0000000004057290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bce8c0_0 .net8 "VPB", 0 0, L_0000000004057290;  1 drivers, strength-aware
+L_0000000004057610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcfea0_0 .net8 "VPWR", 0 0, L_0000000004057610;  1 drivers, strength-aware
+v0000000003bd0580_0 .net "X", 0 0, L_0000000004123c60;  alias, 1 drivers
+S_0000000003be8670 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000003be8070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004123560 .functor AND 1, L_0000000004123100, L_0000000004123250, C4<1>, C4<1>;
+L_0000000004123c60 .functor BUF 1, L_0000000004123560, C4<0>, C4<0>, C4<0>;
+v0000000003bcdd80_0 .net "A", 0 0, L_0000000004123100;  alias, 1 drivers
+v0000000003bcc2a0_0 .net "B", 0 0, L_0000000004123250;  alias, 1 drivers
+L_0000000004057680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bce000_0 .net8 "VGND", 0 0, L_0000000004057680;  1 drivers, strength-aware
+L_0000000004057d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcc5c0_0 .net8 "VNB", 0 0, L_0000000004057d80;  1 drivers, strength-aware
+L_0000000004056960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bccc00_0 .net8 "VPB", 0 0, L_0000000004056960;  1 drivers, strength-aware
+L_0000000004056a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcef00_0 .net8 "VPWR", 0 0, L_0000000004056a40;  1 drivers, strength-aware
+v0000000003bce500_0 .net "X", 0 0, L_0000000004123c60;  alias, 1 drivers
+v0000000003bcec80_0 .net "and0_out_X", 0 0, L_0000000004123560;  1 drivers
+S_0000000003be7ef0 .scope module, "_0933_" "sky130_fd_sc_hd__nor2_2" 3 2874, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bcf720_0 .net "A", 0 0, L_0000000004141b70;  alias, 1 drivers
+v0000000003bd04e0_0 .net "B", 0 0, L_0000000004123c60;  alias, 1 drivers
+L_0000000004057ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0080_0 .net8 "VGND", 0 0, L_0000000004057ed0;  1 drivers, strength-aware
+L_00000000040578b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0800_0 .net8 "VNB", 0 0, L_00000000040578b0;  1 drivers, strength-aware
+L_0000000004058100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bce780_0 .net8 "VPB", 0 0, L_0000000004058100;  1 drivers, strength-aware
+L_0000000004057060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bce320_0 .net8 "VPWR", 0 0, L_0000000004057060;  1 drivers, strength-aware
+v0000000003bcee60_0 .net "Y", 0 0, L_0000000004124c20;  alias, 1 drivers
+S_0000000003be5670 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003be7ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004124750 .functor NOR 1, L_0000000004141b70, L_0000000004123c60, C4<0>, C4<0>;
+L_0000000004124c20 .functor BUF 1, L_0000000004124750, C4<0>, C4<0>, C4<0>;
+v0000000003bcedc0_0 .net "A", 0 0, L_0000000004141b70;  alias, 1 drivers
+v0000000003bcf220_0 .net "B", 0 0, L_0000000004123c60;  alias, 1 drivers
+L_0000000004056dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf180_0 .net8 "VGND", 0 0, L_0000000004056dc0;  1 drivers, strength-aware
+L_0000000004056ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bce6e0_0 .net8 "VNB", 0 0, L_0000000004056ab0;  1 drivers, strength-aware
+L_0000000004057990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0620_0 .net8 "VPB", 0 0, L_0000000004057990;  1 drivers, strength-aware
+L_0000000004056b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0260_0 .net8 "VPWR", 0 0, L_0000000004056b90;  1 drivers, strength-aware
+v0000000003bced20_0 .net "Y", 0 0, L_0000000004124c20;  alias, 1 drivers
+v0000000003bce5a0_0 .net "nor0_out_Y", 0 0, L_0000000004124750;  1 drivers
+S_0000000003be6870 .scope module, "_0934_" "sky130_fd_sc_hd__o221ai_2" 3 2879, 4 23614 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003bcefa0_0 .net "A1", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003bce3c0_0 .net "A2", 0 0, L_000000000413f090;  alias, 1 drivers
+v0000000003bd01c0_0 .net "B1", 0 0, L_000000000413ebc0;  alias, 1 drivers
+v0000000003bcfcc0_0 .net "B2", 0 0, L_000000000413d500;  alias, 1 drivers
+v0000000003bcfa40_0 .net "C1", 0 0, L_0000000004124c20;  alias, 1 drivers
+L_0000000004056ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcfae0_0 .net8 "VGND", 0 0, L_0000000004056ea0;  1 drivers, strength-aware
+L_0000000004057920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf040_0 .net8 "VNB", 0 0, L_0000000004057920;  1 drivers, strength-aware
+L_0000000004056c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf360_0 .net8 "VPB", 0 0, L_0000000004056c00;  1 drivers, strength-aware
+L_0000000004056ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bceaa0_0 .net8 "VPWR", 0 0, L_0000000004056ff0;  1 drivers, strength-aware
+v0000000003bcf5e0_0 .net "Y", 0 0, L_0000000004124c90;  alias, 1 drivers
+S_0000000003be54f0 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23636, 4 23482 1, S_0000000003be6870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041240c0 .functor OR 1, L_000000000413d500, L_000000000413ebc0, C4<0>, C4<0>;
+L_0000000004123a30 .functor OR 1, L_000000000413f090, L_0000000004128110, C4<0>, C4<0>;
+L_0000000004123410 .functor NAND 1, L_0000000004123a30, L_00000000041240c0, L_0000000004124c20, C4<1>;
+L_0000000004124c90 .functor BUF 1, L_0000000004123410, C4<0>, C4<0>, C4<0>;
+v0000000003bd06c0_0 .net "A1", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003bce820_0 .net "A2", 0 0, L_000000000413f090;  alias, 1 drivers
+v0000000003bd0760_0 .net "B1", 0 0, L_000000000413ebc0;  alias, 1 drivers
+v0000000003bcf7c0_0 .net "B2", 0 0, L_000000000413d500;  alias, 1 drivers
+v0000000003bd08a0_0 .net "C1", 0 0, L_0000000004124c20;  alias, 1 drivers
+L_0000000004057a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf2c0_0 .net8 "VGND", 0 0, L_0000000004057a00;  1 drivers, strength-aware
+L_0000000004057f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bce1e0_0 .net8 "VNB", 0 0, L_0000000004057f40;  1 drivers, strength-aware
+L_0000000004058020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf9a0_0 .net8 "VPB", 0 0, L_0000000004058020;  1 drivers, strength-aware
+L_0000000004058090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcfc20_0 .net8 "VPWR", 0 0, L_0000000004058090;  1 drivers, strength-aware
+v0000000003bcea00_0 .net "Y", 0 0, L_0000000004124c90;  alias, 1 drivers
+v0000000003bcf860_0 .net "nand0_out_Y", 0 0, L_0000000004123410;  1 drivers
+v0000000003bce280_0 .net "or0_out", 0 0, L_00000000041240c0;  1 drivers
+v0000000003bce960_0 .net "or1_out", 0 0, L_0000000004123a30;  1 drivers
+S_0000000003be7170 .scope module, "_0935_" "sky130_fd_sc_hd__o211a_2" 3 2887, 4 77704 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003bcfd60_0 .net "A1", 0 0, L_0000000004140e50;  alias, 1 drivers
+v0000000003bcfe00_0 .net "A2", 0 0, L_0000000004123100;  alias, 1 drivers
+v0000000003bcffe0_0 .net "B1", 0 0, L_00000000041239c0;  alias, 1 drivers
+v0000000003bd0300_0 .net "C1", 0 0, L_0000000004124c90;  alias, 1 drivers
+L_0000000004057140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd03a0_0 .net8 "VGND", 0 0, L_0000000004057140;  1 drivers, strength-aware
+L_0000000004058170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd18e0_0 .net8 "VNB", 0 0, L_0000000004058170;  1 drivers, strength-aware
+L_0000000004059910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd09e0_0 .net8 "VPB", 0 0, L_0000000004059910;  1 drivers, strength-aware
+L_0000000004058870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1840_0 .net8 "VPWR", 0 0, L_0000000004058870;  1 drivers, strength-aware
+v0000000003bd0ee0_0 .net "X", 0 0, L_00000000041235d0;  alias, 1 drivers
+S_0000000003be69f0 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_0000000003be7170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004123480 .functor OR 1, L_0000000004123100, L_0000000004140e50, C4<0>, C4<0>;
+L_0000000004123cd0 .functor AND 1, L_0000000004123480, L_00000000041239c0, L_0000000004124c90, C4<1>;
+L_00000000041235d0 .functor BUF 1, L_0000000004123cd0, C4<0>, C4<0>, C4<0>;
+v0000000003bce460_0 .net "A1", 0 0, L_0000000004140e50;  alias, 1 drivers
+v0000000003bceb40_0 .net "A2", 0 0, L_0000000004123100;  alias, 1 drivers
+v0000000003bd0440_0 .net "B1", 0 0, L_00000000041239c0;  alias, 1 drivers
+v0000000003bcebe0_0 .net "C1", 0 0, L_0000000004124c90;  alias, 1 drivers
+L_0000000004058950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcff40_0 .net8 "VGND", 0 0, L_0000000004058950;  1 drivers, strength-aware
+L_0000000004059830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf400_0 .net8 "VNB", 0 0, L_0000000004059830;  1 drivers, strength-aware
+L_00000000040598a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf4a0_0 .net8 "VPB", 0 0, L_00000000040598a0;  1 drivers, strength-aware
+L_0000000004059050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bcf900_0 .net8 "VPWR", 0 0, L_0000000004059050;  1 drivers, strength-aware
+v0000000003bcf540_0 .net "X", 0 0, L_00000000041235d0;  alias, 1 drivers
+v0000000003bcf680_0 .net "and0_out_X", 0 0, L_0000000004123cd0;  1 drivers
+v0000000003bcfb80_0 .net "or0_out", 0 0, L_0000000004123480;  1 drivers
+S_0000000003be7a70 .scope module, "_0936_" "sky130_fd_sc_hd__a2bb2oi_2" 3 2894, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bd0d00_0 .net "A1_N", 0 0, L_00000000041232c0;  alias, 1 drivers
+v0000000003bd1ca0_0 .net "A2_N", 0 0, L_00000000041235d0;  alias, 1 drivers
+v0000000003bd2420_0 .net "B1", 0 0, L_00000000041232c0;  alias, 1 drivers
+v0000000003bd2d80_0 .net "B2", 0 0, L_00000000041235d0;  alias, 1 drivers
+L_0000000004059c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2ba0_0 .net8 "VGND", 0 0, L_0000000004059c90;  1 drivers, strength-aware
+L_0000000004058d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd26a0_0 .net8 "VNB", 0 0, L_0000000004058d40;  1 drivers, strength-aware
+L_0000000004058f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2600_0 .net8 "VPB", 0 0, L_0000000004058f00;  1 drivers, strength-aware
+L_0000000004059600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1520_0 .net8 "VPWR", 0 0, L_0000000004059600;  1 drivers, strength-aware
+v0000000003bd24c0_0 .net "Y", 0 0, L_0000000004123aa0;  alias, 1 drivers
+S_0000000003be51f0 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003be7a70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041236b0 .functor AND 1, L_00000000041232c0, L_00000000041235d0, C4<1>, C4<1>;
+L_0000000004123720 .functor NOR 1, L_00000000041232c0, L_00000000041235d0, C4<0>, C4<0>;
+L_0000000004123790 .functor NOR 1, L_0000000004123720, L_00000000041236b0, C4<0>, C4<0>;
+L_0000000004123aa0 .functor BUF 1, L_0000000004123790, C4<0>, C4<0>, C4<0>;
+v0000000003bd2560_0 .net "A1_N", 0 0, L_00000000041232c0;  alias, 1 drivers
+v0000000003bd2240_0 .net "A2_N", 0 0, L_00000000041235d0;  alias, 1 drivers
+v0000000003bd2f60_0 .net "B1", 0 0, L_00000000041232c0;  alias, 1 drivers
+v0000000003bd22e0_0 .net "B2", 0 0, L_00000000041235d0;  alias, 1 drivers
+L_00000000040589c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1ac0_0 .net8 "VGND", 0 0, L_00000000040589c0;  1 drivers, strength-aware
+L_000000000405a010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2ce0_0 .net8 "VNB", 0 0, L_000000000405a010;  1 drivers, strength-aware
+L_0000000004058720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0da0_0 .net8 "VPB", 0 0, L_0000000004058720;  1 drivers, strength-aware
+L_000000000405a080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd17a0_0 .net8 "VPWR", 0 0, L_000000000405a080;  1 drivers, strength-aware
+v0000000003bd2380_0 .net "Y", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd2a60_0 .net "and0_out", 0 0, L_00000000041236b0;  1 drivers
+v0000000003bd2880_0 .net "nor0_out", 0 0, L_0000000004123720;  1 drivers
+v0000000003bd12a0_0 .net "nor1_out_Y", 0 0, L_0000000004123790;  1 drivers
+S_0000000003be7bf0 .scope module, "_0937_" "sky130_fd_sc_hd__or2_2" 3 2901, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bd29c0_0 .net "A", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003bd1a20_0 .net "B", 0 0, L_0000000004124520;  alias, 1 drivers
+L_0000000004059980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2b00_0 .net8 "VGND", 0 0, L_0000000004059980;  1 drivers, strength-aware
+L_00000000040592f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1480_0 .net8 "VNB", 0 0, L_00000000040592f0;  1 drivers, strength-aware
+L_0000000004059ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2ec0_0 .net8 "VPB", 0 0, L_0000000004059ad0;  1 drivers, strength-aware
+L_0000000004059130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2c40_0 .net8 "VPWR", 0 0, L_0000000004059130;  1 drivers, strength-aware
+v0000000003bd1d40_0 .net "X", 0 0, L_0000000004123b10;  alias, 1 drivers
+S_0000000003be8970 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be7bf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041247c0 .functor OR 1, L_0000000004124520, L_0000000004143310, C4<0>, C4<0>;
+L_0000000004123b10 .functor BUF 1, L_00000000041247c0, C4<0>, C4<0>, C4<0>;
+v0000000003bd2100_0 .net "A", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003bd0e40_0 .net "B", 0 0, L_0000000004124520;  alias, 1 drivers
+L_00000000040588e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0940_0 .net8 "VGND", 0 0, L_00000000040588e0;  1 drivers, strength-aware
+L_0000000004058a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2740_0 .net8 "VNB", 0 0, L_0000000004058a30;  1 drivers, strength-aware
+L_0000000004058aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2920_0 .net8 "VPB", 0 0, L_0000000004058aa0;  1 drivers, strength-aware
+L_0000000004058800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1020_0 .net8 "VPWR", 0 0, L_0000000004058800;  1 drivers, strength-aware
+v0000000003bd27e0_0 .net "X", 0 0, L_0000000004123b10;  alias, 1 drivers
+v0000000003bd2e20_0 .net "or0_out_X", 0 0, L_00000000041247c0;  1 drivers
+S_0000000003be81f0 .scope module, "_0938_" "sky130_fd_sc_hd__or4_2" 3 2906, 4 87422 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+v0000000003bd30a0_0 .net "A", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bd0a80_0 .net "B", 0 0, L_0000000004123b10;  alias, 1 drivers
+v0000000003bd0bc0_0 .net "C", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003bd0c60_0 .net "D", 0 0, L_00000000041420b0;  alias, 1 drivers
+L_0000000004058f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd13e0_0 .net8 "VGND", 0 0, L_0000000004058f70;  1 drivers, strength-aware
+L_0000000004059ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1660_0 .net8 "VNB", 0 0, L_0000000004059ec0;  1 drivers, strength-aware
+L_0000000004059e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1700_0 .net8 "VPB", 0 0, L_0000000004059e50;  1 drivers, strength-aware
+L_0000000004059f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1b60_0 .net8 "VPWR", 0 0, L_0000000004059f30;  1 drivers, strength-aware
+v0000000003bd1980_0 .net "X", 0 0, L_0000000004124130;  alias, 1 drivers
+S_0000000003be5370 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87442, 4 87301 1, S_0000000003be81f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004124830 .functor OR 1, L_00000000041420b0, L_0000000004143cb0, L_0000000004123b10, L_0000000004141cc0;
+L_0000000004124130 .functor BUF 1, L_0000000004124830, C4<0>, C4<0>, C4<0>;
+v0000000003bd3000_0 .net "A", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003bd10c0_0 .net "B", 0 0, L_0000000004123b10;  alias, 1 drivers
+v0000000003bd0f80_0 .net "C", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003bd1160_0 .net "D", 0 0, L_00000000041420b0;  alias, 1 drivers
+L_0000000004059fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1200_0 .net8 "VGND", 0 0, L_0000000004059fa0;  1 drivers, strength-aware
+L_0000000004058fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd0b20_0 .net8 "VNB", 0 0, L_0000000004058fe0;  1 drivers, strength-aware
+L_0000000004058e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd15c0_0 .net8 "VPB", 0 0, L_0000000004058e20;  1 drivers, strength-aware
+L_00000000040599f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1de0_0 .net8 "VPWR", 0 0, L_00000000040599f0;  1 drivers, strength-aware
+v0000000003bd1340_0 .net "X", 0 0, L_0000000004124130;  alias, 1 drivers
+v0000000003bd1fc0_0 .net "or0_out_X", 0 0, L_0000000004124830;  1 drivers
+S_0000000003be72f0 .scope module, "_0939_" "sky130_fd_sc_hd__nor2_2" 3 2913, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003bd3140_0 .net "A", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd56c0_0 .net "B", 0 0, L_0000000004124130;  alias, 1 drivers
+L_0000000004058bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3d20_0 .net8 "VGND", 0 0, L_0000000004058bf0;  1 drivers, strength-aware
+L_00000000040586b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4680_0 .net8 "VNB", 0 0, L_00000000040586b0;  1 drivers, strength-aware
+L_0000000004059a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4180_0 .net8 "VPB", 0 0, L_0000000004059a60;  1 drivers, strength-aware
+L_00000000040584f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4040_0 .net8 "VPWR", 0 0, L_00000000040584f0;  1 drivers, strength-aware
+v0000000003bd4e00_0 .net "Y", 0 0, L_00000000041248a0;  alias, 1 drivers
+S_0000000003be5af0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003be72f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004124210 .functor NOR 1, L_0000000004123aa0, L_0000000004124130, C4<0>, C4<0>;
+L_00000000041248a0 .functor BUF 1, L_0000000004124210, C4<0>, C4<0>, C4<0>;
+v0000000003bd1c00_0 .net "A", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd1e80_0 .net "B", 0 0, L_0000000004124130;  alias, 1 drivers
+L_0000000004059360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd1f20_0 .net8 "VGND", 0 0, L_0000000004059360;  1 drivers, strength-aware
+L_0000000004058b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd2060_0 .net8 "VNB", 0 0, L_0000000004058b10;  1 drivers, strength-aware
+L_0000000004059440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd21a0_0 .net8 "VPB", 0 0, L_0000000004059440;  1 drivers, strength-aware
+L_0000000004058b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3e60_0 .net8 "VPWR", 0 0, L_0000000004058b80;  1 drivers, strength-aware
+v0000000003bd4b80_0 .net "Y", 0 0, L_00000000041248a0;  alias, 1 drivers
+v0000000003bd3fa0_0 .net "nor0_out_Y", 0 0, L_0000000004124210;  1 drivers
+S_0000000003be57f0 .scope module, "_0940_" "sky130_fd_sc_hd__a21oi_2" 3 2918, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bd40e0_0 .net "A1", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd3280_0 .net "A2", 0 0, L_0000000004124130;  alias, 1 drivers
+v0000000003bd4220_0 .net "B1", 0 0, L_00000000041248a0;  alias, 1 drivers
+L_00000000040590c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd36e0_0 .net8 "VGND", 0 0, L_00000000040590c0;  1 drivers, strength-aware
+L_0000000004058790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3aa0_0 .net8 "VNB", 0 0, L_0000000004058790;  1 drivers, strength-aware
+L_00000000040593d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd53a0_0 .net8 "VPB", 0 0, L_00000000040593d0;  1 drivers, strength-aware
+L_0000000004058e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5760_0 .net8 "VPWR", 0 0, L_0000000004058e90;  1 drivers, strength-aware
+v0000000003bd4cc0_0 .net "Y", 0 0, L_0000000004124980;  alias, 1 drivers
+S_0000000003be7470 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003be57f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004124360 .functor AND 1, L_0000000004123aa0, L_0000000004124130, C4<1>, C4<1>;
+L_00000000041243d0 .functor NOR 1, L_00000000041248a0, L_0000000004124360, C4<0>, C4<0>;
+L_0000000004124980 .functor BUF 1, L_00000000041243d0, C4<0>, C4<0>, C4<0>;
+v0000000003bd4d60_0 .net "A1", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd3b40_0 .net "A2", 0 0, L_0000000004124130;  alias, 1 drivers
+v0000000003bd49a0_0 .net "B1", 0 0, L_00000000041248a0;  alias, 1 drivers
+L_0000000004059b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5800_0 .net8 "VGND", 0 0, L_0000000004059b40;  1 drivers, strength-aware
+L_00000000040594b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd31e0_0 .net8 "VNB", 0 0, L_00000000040594b0;  1 drivers, strength-aware
+L_00000000040591a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3780_0 .net8 "VPB", 0 0, L_00000000040591a0;  1 drivers, strength-aware
+L_0000000004058560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4ea0_0 .net8 "VPWR", 0 0, L_0000000004058560;  1 drivers, strength-aware
+v0000000003bd3be0_0 .net "Y", 0 0, L_0000000004124980;  alias, 1 drivers
+v0000000003bd3c80_0 .net "and0_out", 0 0, L_0000000004124360;  1 drivers
+v0000000003bd4540_0 .net "nor0_out_Y", 0 0, L_00000000041243d0;  1 drivers
+S_0000000003be8370 .scope module, "_0941_" "sky130_fd_sc_hd__or2b_2" 3 2924, 4 56400 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+v0000000003bd4400_0 .net "A", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000003bd44a0_0 .net "B_N", 0 0, L_00000000041399f0;  alias, 1 drivers
+L_00000000040585d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4fe0_0 .net8 "VGND", 0 0, L_00000000040585d0;  1 drivers, strength-aware
+L_0000000004059210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5620_0 .net8 "VNB", 0 0, L_0000000004059210;  1 drivers, strength-aware
+L_0000000004059670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3960_0 .net8 "VPB", 0 0, L_0000000004059670;  1 drivers, strength-aware
+L_0000000004058cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5120_0 .net8 "VPWR", 0 0, L_0000000004058cd0;  1 drivers, strength-aware
+v0000000003bd3f00_0 .net "X", 0 0, L_0000000004157fb0;  alias, 1 drivers
+S_0000000003be75f0 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56416, 4 56915 1, S_0000000003be8370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004158090 .functor NOT 1, L_00000000041399f0, C4<0>, C4<0>, C4<0>;
+L_0000000004157b50 .functor OR 1, L_0000000004158090, L_000000000412f420, C4<0>, C4<0>;
+L_0000000004157fb0 .functor BUF 1, L_0000000004157b50, C4<0>, C4<0>, C4<0>;
+v0000000003bd5580_0 .net "A", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000003bd4f40_0 .net "B_N", 0 0, L_00000000041399f0;  alias, 1 drivers
+L_0000000004058640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3820_0 .net8 "VGND", 0 0, L_0000000004058640;  1 drivers, strength-aware
+L_0000000004059bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd42c0_0 .net8 "VNB", 0 0, L_0000000004059bb0;  1 drivers, strength-aware
+L_0000000004059c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4a40_0 .net8 "VPB", 0 0, L_0000000004059c20;  1 drivers, strength-aware
+L_0000000004059280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5260_0 .net8 "VPWR", 0 0, L_0000000004059280;  1 drivers, strength-aware
+v0000000003bd5080_0 .net "X", 0 0, L_0000000004157fb0;  alias, 1 drivers
+v0000000003bd3dc0_0 .net "not0_out", 0 0, L_0000000004158090;  1 drivers
+v0000000003bd38c0_0 .net "or0_out_X", 0 0, L_0000000004157b50;  1 drivers
+S_0000000003be6cf0 .scope module, "_0942_" "sky130_fd_sc_hd__o21ai_2" 3 2929, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bd54e0_0 .net "A1", 0 0, L_0000000004139590;  alias, 1 drivers
+v0000000003bd47c0_0 .net "A2", 0 0, L_0000000004143460;  alias, 1 drivers
+v0000000003bd4860_0 .net "B1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+L_0000000004059d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd58a0_0 .net8 "VGND", 0 0, L_0000000004059d00;  1 drivers, strength-aware
+L_0000000004058db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3320_0 .net8 "VNB", 0 0, L_0000000004058db0;  1 drivers, strength-aware
+L_0000000004059750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd3a00_0 .net8 "VPB", 0 0, L_0000000004059750;  1 drivers, strength-aware
+L_00000000040597c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd33c0_0 .net8 "VPWR", 0 0, L_00000000040597c0;  1 drivers, strength-aware
+v0000000003bd35a0_0 .net "Y", 0 0, L_00000000041585d0;  alias, 1 drivers
+S_0000000003be84f0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be6cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004157e60 .functor OR 1, L_0000000004143460, L_0000000004139590, C4<0>, C4<0>;
+L_0000000004157920 .functor NAND 1, L_000000000412d9e0, L_0000000004157e60, C4<1>, C4<1>;
+L_00000000041585d0 .functor BUF 1, L_0000000004157920, C4<0>, C4<0>, C4<0>;
+v0000000003bd4360_0 .net "A1", 0 0, L_0000000004139590;  alias, 1 drivers
+v0000000003bd4ae0_0 .net "A2", 0 0, L_0000000004143460;  alias, 1 drivers
+v0000000003bd51c0_0 .net "B1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+L_0000000004059520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd45e0_0 .net8 "VGND", 0 0, L_0000000004059520;  1 drivers, strength-aware
+L_0000000004059590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5300_0 .net8 "VNB", 0 0, L_0000000004059590;  1 drivers, strength-aware
+L_0000000004059d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd4720_0 .net8 "VPB", 0 0, L_0000000004059d70;  1 drivers, strength-aware
+L_0000000004059de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5440_0 .net8 "VPWR", 0 0, L_0000000004059de0;  1 drivers, strength-aware
+v0000000003bd3460_0 .net "Y", 0 0, L_00000000041585d0;  alias, 1 drivers
+v0000000003bd4c20_0 .net "nand0_out_Y", 0 0, L_0000000004157920;  1 drivers
+v0000000003bd3500_0 .net "or0_out", 0 0, L_0000000004157e60;  1 drivers
+S_0000000003be5970 .scope module, "_0943_" "sky130_fd_sc_hd__a21o_2" 3 2935, 4 46093 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003bd7ec0_0 .net "A1", 0 0, L_00000000041389c0;  alias, 1 drivers
+v0000000003bd7100_0 .net "A2", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003bd7380_0 .net "B1", 0 0, L_00000000041585d0;  alias, 1 drivers
+L_0000000004058c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7420_0 .net8 "VGND", 0 0, L_0000000004058c60;  1 drivers, strength-aware
+L_00000000040596e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7b00_0 .net8 "VNB", 0 0, L_00000000040596e0;  1 drivers, strength-aware
+L_000000000405b7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7f60_0 .net8 "VPB", 0 0, L_000000000405b7b0;  1 drivers, strength-aware
+L_000000000405a9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6020_0 .net8 "VPWR", 0 0, L_000000000405a9b0;  1 drivers, strength-aware
+v0000000003bd68e0_0 .net "X", 0 0, L_0000000004158560;  alias, 1 drivers
+S_0000000003be66f0 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46111, 4 46415 1, S_0000000003be5970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004158020 .functor AND 1, L_00000000041389c0, L_00000000041382c0, C4<1>, C4<1>;
+L_0000000004157c30 .functor OR 1, L_0000000004158020, L_00000000041585d0, C4<0>, C4<0>;
+L_0000000004158560 .functor BUF 1, L_0000000004157c30, C4<0>, C4<0>, C4<0>;
+v0000000003bd4900_0 .net "A1", 0 0, L_00000000041389c0;  alias, 1 drivers
+v0000000003bd3640_0 .net "A2", 0 0, L_00000000041382c0;  alias, 1 drivers
+v0000000003bd6f20_0 .net "B1", 0 0, L_00000000041585d0;  alias, 1 drivers
+L_000000000405a7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5bc0_0 .net8 "VGND", 0 0, L_000000000405a7f0;  1 drivers, strength-aware
+L_000000000405b6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd67a0_0 .net8 "VNB", 0 0, L_000000000405b6d0;  1 drivers, strength-aware
+L_000000000405a320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7ba0_0 .net8 "VPB", 0 0, L_000000000405a320;  1 drivers, strength-aware
+L_000000000405bc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7740_0 .net8 "VPWR", 0 0, L_000000000405bc80;  1 drivers, strength-aware
+v0000000003bd7d80_0 .net "X", 0 0, L_0000000004158560;  alias, 1 drivers
+v0000000003bd7e20_0 .net "and0_out", 0 0, L_0000000004158020;  1 drivers
+v0000000003bd6de0_0 .net "or0_out_X", 0 0, L_0000000004157c30;  1 drivers
+S_0000000003be6570 .scope module, "_0944_" "sky130_fd_sc_hd__a2bb2o_2" 3 2941, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003bd7c40_0 .net "A1_N", 0 0, L_0000000004157fb0;  alias, 1 drivers
+v0000000003bd5940_0 .net "A2_N", 0 0, L_0000000004158560;  alias, 1 drivers
+v0000000003bd65c0_0 .net "B1", 0 0, L_0000000004157fb0;  alias, 1 drivers
+v0000000003bd59e0_0 .net "B2", 0 0, L_0000000004158560;  alias, 1 drivers
+L_000000000405b040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7ce0_0 .net8 "VGND", 0 0, L_000000000405b040;  1 drivers, strength-aware
+L_000000000405aef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6fc0_0 .net8 "VNB", 0 0, L_000000000405aef0;  1 drivers, strength-aware
+L_000000000405a0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6980_0 .net8 "VPB", 0 0, L_000000000405a0f0;  1 drivers, strength-aware
+L_000000000405b890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5a80_0 .net8 "VPWR", 0 0, L_000000000405b890;  1 drivers, strength-aware
+v0000000003bd5b20_0 .net "X", 0 0, L_0000000004157ed0;  alias, 1 drivers
+S_0000000003be87f0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003be6570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004157610 .functor AND 1, L_0000000004157fb0, L_0000000004158560, C4<1>, C4<1>;
+L_0000000004157bc0 .functor NOR 1, L_0000000004157fb0, L_0000000004158560, C4<0>, C4<0>;
+L_0000000004158790 .functor OR 1, L_0000000004157bc0, L_0000000004157610, C4<0>, C4<0>;
+L_0000000004157ed0 .functor BUF 1, L_0000000004158790, C4<0>, C4<0>, C4<0>;
+v0000000003bd71a0_0 .net "A1_N", 0 0, L_0000000004157fb0;  alias, 1 drivers
+v0000000003bd72e0_0 .net "A2_N", 0 0, L_0000000004158560;  alias, 1 drivers
+v0000000003bd60c0_0 .net "B1", 0 0, L_0000000004157fb0;  alias, 1 drivers
+v0000000003bd5da0_0 .net "B2", 0 0, L_0000000004158560;  alias, 1 drivers
+L_000000000405a160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6ca0_0 .net8 "VGND", 0 0, L_000000000405a160;  1 drivers, strength-aware
+L_000000000405a1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7240_0 .net8 "VNB", 0 0, L_000000000405a1d0;  1 drivers, strength-aware
+L_000000000405b510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5c60_0 .net8 "VPB", 0 0, L_000000000405b510;  1 drivers, strength-aware
+L_000000000405a5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6160_0 .net8 "VPWR", 0 0, L_000000000405a5c0;  1 drivers, strength-aware
+v0000000003bd6d40_0 .net "X", 0 0, L_0000000004157ed0;  alias, 1 drivers
+v0000000003bd6200_0 .net "and0_out", 0 0, L_0000000004157610;  1 drivers
+v0000000003bd6840_0 .net "nor0_out", 0 0, L_0000000004157bc0;  1 drivers
+v0000000003bd74c0_0 .net "or0_out_X", 0 0, L_0000000004158790;  1 drivers
+S_0000000003be6270 .scope module, "_0945_" "sky130_fd_sc_hd__inv_2" 3 2948, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003bd6b60_0 .net "A", 0 0, L_0000000004157ed0;  alias, 1 drivers
+L_000000000405ae80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5f80_0 .net8 "VGND", 0 0, L_000000000405ae80;  1 drivers, strength-aware
+L_000000000405b270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd7600_0 .net8 "VNB", 0 0, L_000000000405b270;  1 drivers, strength-aware
+L_000000000405b3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd76a0_0 .net8 "VPB", 0 0, L_000000000405b3c0;  1 drivers, strength-aware
+L_000000000405a240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd62a0_0 .net8 "VPWR", 0 0, L_000000000405a240;  1 drivers, strength-aware
+v0000000003bd7560_0 .net "Y", 0 0, L_00000000041573e0;  alias, 1 drivers
+S_0000000003be7d70 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be6270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004157990 .functor NOT 1, L_0000000004157ed0, C4<0>, C4<0>, C4<0>;
+L_00000000041573e0 .functor BUF 1, L_0000000004157990, C4<0>, C4<0>, C4<0>;
+v0000000003bd6480_0 .net "A", 0 0, L_0000000004157ed0;  alias, 1 drivers
+L_000000000405a8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5d00_0 .net8 "VGND", 0 0, L_000000000405a8d0;  1 drivers, strength-aware
+L_000000000405a390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6a20_0 .net8 "VNB", 0 0, L_000000000405a390;  1 drivers, strength-aware
+L_000000000405aa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6ac0_0 .net8 "VPB", 0 0, L_000000000405aa20;  1 drivers, strength-aware
+L_000000000405b0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd5ee0_0 .net8 "VPWR", 0 0, L_000000000405b0b0;  1 drivers, strength-aware
+v0000000003bd5e40_0 .net "Y", 0 0, L_00000000041573e0;  alias, 1 drivers
+v0000000003bd79c0_0 .net "not0_out_Y", 0 0, L_0000000004157990;  1 drivers
+S_0000000003be5c70 .scope module, "_0946_" "sky130_fd_sc_hd__or3_2" 3 2952, 4 49901 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003bd7880_0 .net "A", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd7920_0 .net "B", 0 0, L_0000000004157ed0;  alias, 1 drivers
+v0000000003bd7a60_0 .net "C", 0 0, L_0000000004124130;  alias, 1 drivers
+L_000000000405ae10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b99800_0 .net8 "VGND", 0 0, L_000000000405ae10;  1 drivers, strength-aware
+L_000000000405aa90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97c80_0 .net8 "VNB", 0 0, L_000000000405aa90;  1 drivers, strength-aware
+L_000000000405ad30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98f40_0 .net8 "VPB", 0 0, L_000000000405ad30;  1 drivers, strength-aware
+L_000000000405a400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98220_0 .net8 "VPWR", 0 0, L_000000000405a400;  1 drivers, strength-aware
+v0000000003b975a0_0 .net "X", 0 0, L_0000000004158100;  alias, 1 drivers
+S_0000000003be7770 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_0000000003be5c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004157a00 .functor OR 1, L_0000000004157ed0, L_0000000004123aa0, L_0000000004124130, C4<0>;
+L_0000000004158100 .functor BUF 1, L_0000000004157a00, C4<0>, C4<0>, C4<0>;
+v0000000003bd6340_0 .net "A", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003bd6e80_0 .net "B", 0 0, L_0000000004157ed0;  alias, 1 drivers
+v0000000003bd63e0_0 .net "C", 0 0, L_0000000004124130;  alias, 1 drivers
+L_000000000405b2e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6520_0 .net8 "VGND", 0 0, L_000000000405b2e0;  1 drivers, strength-aware
+L_000000000405b120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6660_0 .net8 "VNB", 0 0, L_000000000405b120;  1 drivers, strength-aware
+L_000000000405b740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6700_0 .net8 "VPB", 0 0, L_000000000405b740;  1 drivers, strength-aware
+L_000000000405b580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003bd6c00_0 .net8 "VPWR", 0 0, L_000000000405b580;  1 drivers, strength-aware
+v0000000003bd7060_0 .net "X", 0 0, L_0000000004158100;  alias, 1 drivers
+v0000000003bd77e0_0 .net "or0_out_X", 0 0, L_0000000004157a00;  1 drivers
+S_0000000003be6e70 .scope module, "_0947_" "sky130_fd_sc_hd__o21a_2" 3 2958, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b976e0_0 .net "A1", 0 0, L_00000000041248a0;  alias, 1 drivers
+v0000000003b971e0_0 .net "A2", 0 0, L_00000000041573e0;  alias, 1 drivers
+v0000000003b97fa0_0 .net "B1", 0 0, L_0000000004158100;  alias, 1 drivers
+L_000000000405b350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97280_0 .net8 "VGND", 0 0, L_000000000405b350;  1 drivers, strength-aware
+L_000000000405bba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b996c0_0 .net8 "VNB", 0 0, L_000000000405bba0;  1 drivers, strength-aware
+L_000000000405bb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98ae0_0 .net8 "VPB", 0 0, L_000000000405bb30;  1 drivers, strength-aware
+L_000000000405b4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b97e60_0 .net8 "VPWR", 0 0, L_000000000405b4a0;  1 drivers, strength-aware
+v0000000003b991c0_0 .net "X", 0 0, L_0000000004158170;  alias, 1 drivers
+S_0000000003be6b70 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003be6e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004157f40 .functor OR 1, L_00000000041573e0, L_00000000041248a0, C4<0>, C4<0>;
+L_0000000004157a70 .functor AND 1, L_0000000004157f40, L_0000000004158100, C4<1>, C4<1>;
+L_0000000004158170 .functor BUF 1, L_0000000004157a70, C4<0>, C4<0>, C4<0>;
+v0000000003b99580_0 .net "A1", 0 0, L_00000000041248a0;  alias, 1 drivers
+v0000000003b99260_0 .net "A2", 0 0, L_00000000041573e0;  alias, 1 drivers
+v0000000003b99080_0 .net "B1", 0 0, L_0000000004158100;  alias, 1 drivers
+L_000000000405b430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b98a40_0 .net8 "VGND", 0 0, L_000000000405b430;  1 drivers, strength-aware
+L_000000000405b820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97500_0 .net8 "VNB", 0 0, L_000000000405b820;  1 drivers, strength-aware
+L_000000000405b200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b998a0_0 .net8 "VPB", 0 0, L_000000000405b200;  1 drivers, strength-aware
+L_000000000405ab70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b99620_0 .net8 "VPWR", 0 0, L_000000000405ab70;  1 drivers, strength-aware
+v0000000003b982c0_0 .net "X", 0 0, L_0000000004158170;  alias, 1 drivers
+v0000000003b97140_0 .net "and0_out_X", 0 0, L_0000000004157a70;  1 drivers
+v0000000003b98360_0 .net "or0_out", 0 0, L_0000000004157f40;  1 drivers
+S_0000000003be63f0 .scope module, "_0948_" "sky130_fd_sc_hd__inv_2" 3 2964, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003b97780_0 .net "A", 0 0, L_0000000004138b10;  alias, 1 drivers
+L_000000000405a630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b99440_0 .net8 "VGND", 0 0, L_000000000405a630;  1 drivers, strength-aware
+L_000000000405b970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97320_0 .net8 "VNB", 0 0, L_000000000405b970;  1 drivers, strength-aware
+L_000000000405a470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b97dc0_0 .net8 "VPB", 0 0, L_000000000405a470;  1 drivers, strength-aware
+L_000000000405b5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b973c0_0 .net8 "VPWR", 0 0, L_000000000405b5f0;  1 drivers, strength-aware
+v0000000003b98040_0 .net "Y", 0 0, L_0000000004158bf0;  alias, 1 drivers
+S_0000000003be6ff0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be63f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004157ae0 .functor NOT 1, L_0000000004138b10, C4<0>, C4<0>, C4<0>;
+L_0000000004158bf0 .functor BUF 1, L_0000000004157ae0, C4<0>, C4<0>, C4<0>;
+v0000000003b97460_0 .net "A", 0 0, L_0000000004138b10;  alias, 1 drivers
+L_000000000405a940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b99760_0 .net8 "VGND", 0 0, L_000000000405a940;  1 drivers, strength-aware
+L_000000000405b190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97960_0 .net8 "VNB", 0 0, L_000000000405b190;  1 drivers, strength-aware
+L_000000000405b9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b99120_0 .net8 "VPB", 0 0, L_000000000405b9e0;  1 drivers, strength-aware
+L_000000000405b660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b97820_0 .net8 "VPWR", 0 0, L_000000000405b660;  1 drivers, strength-aware
+v0000000003b97640_0 .net "Y", 0 0, L_0000000004158bf0;  alias, 1 drivers
+v0000000003b99300_0 .net "not0_out_Y", 0 0, L_0000000004157ae0;  1 drivers
+S_0000000003be8df0 .scope module, "_0949_" "sky130_fd_sc_hd__or2_2" 3 2968, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003b98900_0 .net "A", 0 0, L_0000000004158bf0;  alias, 1 drivers
+v0000000003b97f00_0 .net "B", 0 0, L_0000000004138aa0;  alias, 1 drivers
+L_000000000405b900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b993a0_0 .net8 "VGND", 0 0, L_000000000405b900;  1 drivers, strength-aware
+L_000000000405ba50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b98180_0 .net8 "VNB", 0 0, L_000000000405ba50;  1 drivers, strength-aware
+L_000000000405bac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98e00_0 .net8 "VPB", 0 0, L_000000000405bac0;  1 drivers, strength-aware
+L_000000000405ab00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98ea0_0 .net8 "VPWR", 0 0, L_000000000405ab00;  1 drivers, strength-aware
+v0000000003b98720_0 .net "X", 0 0, L_0000000004157140;  alias, 1 drivers
+S_0000000003be5070 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003be8df0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004158cd0 .functor OR 1, L_0000000004138aa0, L_0000000004158bf0, C4<0>, C4<0>;
+L_0000000004157140 .functor BUF 1, L_0000000004158cd0, C4<0>, C4<0>, C4<0>;
+v0000000003b97be0_0 .net "A", 0 0, L_0000000004158bf0;  alias, 1 drivers
+v0000000003b978c0_0 .net "B", 0 0, L_0000000004138aa0;  alias, 1 drivers
+L_000000000405ac50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b98d60_0 .net8 "VGND", 0 0, L_000000000405ac50;  1 drivers, strength-aware
+L_000000000405af60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b97d20_0 .net8 "VNB", 0 0, L_000000000405af60;  1 drivers, strength-aware
+L_000000000405bc10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b97a00_0 .net8 "VPB", 0 0, L_000000000405bc10;  1 drivers, strength-aware
+L_000000000405a2b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b97aa0_0 .net8 "VPWR", 0 0, L_000000000405a2b0;  1 drivers, strength-aware
+v0000000003b980e0_0 .net "X", 0 0, L_0000000004157140;  alias, 1 drivers
+v0000000003b97b40_0 .net "or0_out_X", 0 0, L_0000000004158cd0;  1 drivers
+S_0000000003be8af0 .scope module, "_0950_" "sky130_fd_sc_hd__o21ai_2" 3 2973, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003b98860_0 .net "A1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+v0000000003b98fe0_0 .net "A2", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000003b989a0_0 .net "B1", 0 0, L_00000000041399f0;  alias, 1 drivers
+L_000000000405a6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c042b0_0 .net8 "VGND", 0 0, L_000000000405a6a0;  1 drivers, strength-aware
+L_000000000405acc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03f90_0 .net8 "VNB", 0 0, L_000000000405acc0;  1 drivers, strength-aware
+L_000000000405a4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c04fd0_0 .net8 "VPB", 0 0, L_000000000405a4e0;  1 drivers, strength-aware
+L_000000000405a550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03450_0 .net8 "VPWR", 0 0, L_000000000405a550;  1 drivers, strength-aware
+v0000000003c04c10_0 .net "Y", 0 0, L_0000000004158c60;  alias, 1 drivers
+S_0000000003be5df0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003be8af0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004157d80 .functor OR 1, L_000000000412f420, L_000000000412d7b0, C4<0>, C4<0>;
+L_0000000004158640 .functor NAND 1, L_00000000041399f0, L_0000000004157d80, C4<1>, C4<1>;
+L_0000000004158c60 .functor BUF 1, L_0000000004158640, C4<0>, C4<0>, C4<0>;
+v0000000003b98400_0 .net "A1", 0 0, L_000000000412d7b0;  alias, 1 drivers
+v0000000003b994e0_0 .net "A2", 0 0, L_000000000412f420;  alias, 1 drivers
+v0000000003b984a0_0 .net "B1", 0 0, L_00000000041399f0;  alias, 1 drivers
+L_000000000405a710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b98540_0 .net8 "VGND", 0 0, L_000000000405a710;  1 drivers, strength-aware
+L_000000000405abe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003b985e0_0 .net8 "VNB", 0 0, L_000000000405abe0;  1 drivers, strength-aware
+L_000000000405a780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98c20_0 .net8 "VPB", 0 0, L_000000000405a780;  1 drivers, strength-aware
+L_000000000405afd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003b98680_0 .net8 "VPWR", 0 0, L_000000000405afd0;  1 drivers, strength-aware
+v0000000003b98b80_0 .net "Y", 0 0, L_0000000004158c60;  alias, 1 drivers
+v0000000003b987c0_0 .net "nand0_out_Y", 0 0, L_0000000004158640;  1 drivers
+v0000000003b98cc0_0 .net "or0_out", 0 0, L_0000000004157d80;  1 drivers
+S_0000000003be5f70 .scope module, "_0951_" "sky130_fd_sc_hd__inv_2" 3 2979, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c05250_0 .net "A", 0 0, L_000000000413f950;  alias, 1 drivers
+L_000000000405a860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c05070_0 .net8 "VGND", 0 0, L_000000000405a860;  1 drivers, strength-aware
+L_000000000405ada0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03810_0 .net8 "VNB", 0 0, L_000000000405ada0;  1 drivers, strength-aware
+L_000000000405c9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c040d0_0 .net8 "VPB", 0 0, L_000000000405c9a0;  1 drivers, strength-aware
+L_000000000405be40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c05110_0 .net8 "VPWR", 0 0, L_000000000405be40;  1 drivers, strength-aware
+v0000000003c043f0_0 .net "Y", 0 0, L_0000000004157ca0;  alias, 1 drivers
+S_0000000003be78f0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003be5f70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004158410 .functor NOT 1, L_000000000413f950, C4<0>, C4<0>, C4<0>;
+L_0000000004157ca0 .functor BUF 1, L_0000000004158410, C4<0>, C4<0>, C4<0>;
+v0000000003c04530_0 .net "A", 0 0, L_000000000413f950;  alias, 1 drivers
+L_000000000405c310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c04a30_0 .net8 "VGND", 0 0, L_000000000405c310;  1 drivers, strength-aware
+L_000000000405beb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c05750_0 .net8 "VNB", 0 0, L_000000000405beb0;  1 drivers, strength-aware
+L_000000000405c5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c04350_0 .net8 "VPB", 0 0, L_000000000405c5b0;  1 drivers, strength-aware
+L_000000000405d880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c054d0_0 .net8 "VPWR", 0 0, L_000000000405d880;  1 drivers, strength-aware
+v0000000003c03590_0 .net "Y", 0 0, L_0000000004157ca0;  alias, 1 drivers
+v0000000003c04030_0 .net "not0_out_Y", 0 0, L_0000000004158410;  1 drivers
+S_0000000003be8c70 .scope module, "_0952_" "sky130_fd_sc_hd__o211a_2" 3 2983, 4 77704 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003c038b0_0 .net "A1", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003c033b0_0 .net "A2", 0 0, L_0000000004157ca0;  alias, 1 drivers
+v0000000003c036d0_0 .net "B1", 0 0, L_000000000413fe20;  alias, 1 drivers
+v0000000003c057f0_0 .net "C1", 0 0, L_0000000004143690;  alias, 1 drivers
+L_000000000405d180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c04cb0_0 .net8 "VGND", 0 0, L_000000000405d180;  1 drivers, strength-aware
+L_000000000405d110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c039f0_0 .net8 "VNB", 0 0, L_000000000405d110;  1 drivers, strength-aware
+L_000000000405c690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03770_0 .net8 "VPB", 0 0, L_000000000405c690;  1 drivers, strength-aware
+L_000000000405d340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03950_0 .net8 "VPWR", 0 0, L_000000000405d340;  1 drivers, strength-aware
+v0000000003c04170_0 .net "X", 0 0, L_0000000004157530;  alias, 1 drivers
+S_0000000003be60f0 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_0000000003be8c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004158950 .functor OR 1, L_0000000004157ca0, L_000000000413ca10, C4<0>, C4<0>;
+L_00000000041578b0 .functor AND 1, L_0000000004158950, L_000000000413fe20, L_0000000004143690, C4<1>;
+L_0000000004157530 .functor BUF 1, L_00000000041578b0, C4<0>, C4<0>, C4<0>;
+v0000000003c04df0_0 .net "A1", 0 0, L_000000000413ca10;  alias, 1 drivers
+v0000000003c04490_0 .net "A2", 0 0, L_0000000004157ca0;  alias, 1 drivers
+v0000000003c045d0_0 .net "B1", 0 0, L_000000000413fe20;  alias, 1 drivers
+v0000000003c051b0_0 .net "C1", 0 0, L_0000000004143690;  alias, 1 drivers
+L_000000000405c540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c034f0_0 .net8 "VGND", 0 0, L_000000000405c540;  1 drivers, strength-aware
+L_000000000405cf50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03ef0_0 .net8 "VNB", 0 0, L_000000000405cf50;  1 drivers, strength-aware
+L_000000000405cfc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03630_0 .net8 "VPB", 0 0, L_000000000405cfc0;  1 drivers, strength-aware
+L_000000000405c620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03c70_0 .net8 "VPWR", 0 0, L_000000000405c620;  1 drivers, strength-aware
+v0000000003c05570_0 .net "X", 0 0, L_0000000004157530;  alias, 1 drivers
+v0000000003c052f0_0 .net "and0_out_X", 0 0, L_00000000041578b0;  1 drivers
+v0000000003c04670_0 .net "or0_out", 0 0, L_0000000004158950;  1 drivers
+S_0000000003c48800 .scope module, "_0953_" "sky130_fd_sc_hd__o21ai_2" 3 2990, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c03b30_0 .net "A1", 0 0, L_000000000412a800;  alias, 1 drivers
+v0000000003c04210_0 .net "A2", 0 0, L_000000000412b6e0;  alias, 1 drivers
+v0000000003c03270_0 .net "B1", 0 0, L_000000000412ed20;  alias, 1 drivers
+L_000000000405c4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c056b0_0 .net8 "VGND", 0 0, L_000000000405c4d0;  1 drivers, strength-aware
+L_000000000405d260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c04ad0_0 .net8 "VNB", 0 0, L_000000000405d260;  1 drivers, strength-aware
+L_000000000405d490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c03310_0 .net8 "VPB", 0 0, L_000000000405d490;  1 drivers, strength-aware
+L_000000000405bcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c05430_0 .net8 "VPWR", 0 0, L_000000000405bcf0;  1 drivers, strength-aware
+v0000000003c04f30_0 .net "Y", 0 0, L_00000000041589c0;  alias, 1 drivers
+S_0000000003c46b80 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c48800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004157840 .functor OR 1, L_000000000412b6e0, L_000000000412a800, C4<0>, C4<0>;
+L_0000000004157d10 .functor NAND 1, L_000000000412ed20, L_0000000004157840, C4<1>, C4<1>;
+L_00000000041589c0 .functor BUF 1, L_0000000004157d10, C4<0>, C4<0>, C4<0>;
+v0000000003c05610_0 .net "A1", 0 0, L_000000000412a800;  alias, 1 drivers
+v0000000003c03a90_0 .net "A2", 0 0, L_000000000412b6e0;  alias, 1 drivers
+v0000000003c05890_0 .net "B1", 0 0, L_000000000412ed20;  alias, 1 drivers
+L_000000000405ce00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03e50_0 .net8 "VGND", 0 0, L_000000000405ce00;  1 drivers, strength-aware
+L_000000000405d3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03130_0 .net8 "VNB", 0 0, L_000000000405d3b0;  1 drivers, strength-aware
+L_000000000405c700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c05390_0 .net8 "VPB", 0 0, L_000000000405c700;  1 drivers, strength-aware
+L_000000000405c3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c031d0_0 .net8 "VPWR", 0 0, L_000000000405c3f0;  1 drivers, strength-aware
+v0000000003c04e90_0 .net "Y", 0 0, L_00000000041589c0;  alias, 1 drivers
+v0000000003c04710_0 .net "nand0_out_Y", 0 0, L_0000000004157d10;  1 drivers
+v0000000003c04d50_0 .net "or0_out", 0 0, L_0000000004157840;  1 drivers
+S_0000000003c47480 .scope module, "_0954_" "sky130_fd_sc_hd__inv_2" 3 2996, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c04b70_0 .net "A", 0 0, L_00000000041589c0;  alias, 1 drivers
+L_000000000405d2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c05930_0 .net8 "VGND", 0 0, L_000000000405d2d0;  1 drivers, strength-aware
+L_000000000405bf20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c065b0_0 .net8 "VNB", 0 0, L_000000000405bf20;  1 drivers, strength-aware
+L_000000000405c850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c07b90_0 .net8 "VPB", 0 0, L_000000000405c850;  1 drivers, strength-aware
+L_000000000405d500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06790_0 .net8 "VPWR", 0 0, L_000000000405d500;  1 drivers, strength-aware
+v0000000003c068d0_0 .net "Y", 0 0, L_0000000004158800;  alias, 1 drivers
+S_0000000003c45b00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c47480;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004158250 .functor NOT 1, L_00000000041589c0, C4<0>, C4<0>, C4<0>;
+L_0000000004158800 .functor BUF 1, L_0000000004158250, C4<0>, C4<0>, C4<0>;
+v0000000003c03bd0_0 .net "A", 0 0, L_00000000041589c0;  alias, 1 drivers
+L_000000000405c770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03d10_0 .net8 "VGND", 0 0, L_000000000405c770;  1 drivers, strength-aware
+L_000000000405c7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c03db0_0 .net8 "VNB", 0 0, L_000000000405c7e0;  1 drivers, strength-aware
+L_000000000405ce70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c047b0_0 .net8 "VPB", 0 0, L_000000000405ce70;  1 drivers, strength-aware
+L_000000000405c1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c04850_0 .net8 "VPWR", 0 0, L_000000000405c1c0;  1 drivers, strength-aware
+v0000000003c048f0_0 .net "Y", 0 0, L_0000000004158800;  alias, 1 drivers
+v0000000003c04990_0 .net "not0_out_Y", 0 0, L_0000000004158250;  1 drivers
+S_0000000003c46d00 .scope module, "_0955_" "sky130_fd_sc_hd__nor2_2" 3 3000, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c06010_0 .net "A", 0 0, L_0000000004124ad0;  alias, 1 drivers
+v0000000003c07a50_0 .net "B", 0 0, L_0000000004158c60;  alias, 1 drivers
+L_000000000405d810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c05b10_0 .net8 "VGND", 0 0, L_000000000405d810;  1 drivers, strength-aware
+L_000000000405bf90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c07c30_0 .net8 "VNB", 0 0, L_000000000405bf90;  1 drivers, strength-aware
+L_000000000405bd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c070f0_0 .net8 "VPB", 0 0, L_000000000405bd60;  1 drivers, strength-aware
+L_000000000405d0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c07730_0 .net8 "VPWR", 0 0, L_000000000405d0a0;  1 drivers, strength-aware
+v0000000003c07550_0 .net "Y", 0 0, L_0000000004157680;  alias, 1 drivers
+S_0000000003c49580 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c46d00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004157df0 .functor NOR 1, L_0000000004124ad0, L_0000000004158c60, C4<0>, C4<0>;
+L_0000000004157680 .functor BUF 1, L_0000000004157df0, C4<0>, C4<0>, C4<0>;
+v0000000003c05bb0_0 .net "A", 0 0, L_0000000004124ad0;  alias, 1 drivers
+v0000000003c06d30_0 .net "B", 0 0, L_0000000004158c60;  alias, 1 drivers
+L_000000000405caf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c06bf0_0 .net8 "VGND", 0 0, L_000000000405caf0;  1 drivers, strength-aware
+L_000000000405d420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c06150_0 .net8 "VNB", 0 0, L_000000000405d420;  1 drivers, strength-aware
+L_000000000405c930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06470_0 .net8 "VPB", 0 0, L_000000000405c930;  1 drivers, strength-aware
+L_000000000405c0e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06830_0 .net8 "VPWR", 0 0, L_000000000405c0e0;  1 drivers, strength-aware
+v0000000003c05ed0_0 .net "Y", 0 0, L_0000000004157680;  alias, 1 drivers
+v0000000003c06290_0 .net "nor0_out_Y", 0 0, L_0000000004157df0;  1 drivers
+S_0000000003c48b00 .scope module, "_0956_" "sky130_fd_sc_hd__o21ai_2" 3 3005, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c074b0_0 .net "A1", 0 0, L_0000000004158800;  alias, 1 drivers
+v0000000003c08090_0 .net "A2", 0 0, L_0000000004157680;  alias, 1 drivers
+v0000000003c05a70_0 .net "B1", 0 0, L_0000000004143620;  alias, 1 drivers
+L_000000000405c070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c07690_0 .net8 "VGND", 0 0, L_000000000405c070;  1 drivers, strength-aware
+L_000000000405c230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c077d0_0 .net8 "VNB", 0 0, L_000000000405c230;  1 drivers, strength-aware
+L_000000000405c000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06f10_0 .net8 "VPB", 0 0, L_000000000405c000;  1 drivers, strength-aware
+L_000000000405c8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06dd0_0 .net8 "VPWR", 0 0, L_000000000405c8c0;  1 drivers, strength-aware
+v0000000003c07f50_0 .net "Y", 0 0, L_0000000004158b10;  alias, 1 drivers
+S_0000000003c47600 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c48b00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041571b0 .functor OR 1, L_0000000004157680, L_0000000004158800, C4<0>, C4<0>;
+L_0000000004157220 .functor NAND 1, L_0000000004143620, L_00000000041571b0, C4<1>, C4<1>;
+L_0000000004158b10 .functor BUF 1, L_0000000004157220, C4<0>, C4<0>, C4<0>;
+v0000000003c059d0_0 .net "A1", 0 0, L_0000000004158800;  alias, 1 drivers
+v0000000003c063d0_0 .net "A2", 0 0, L_0000000004157680;  alias, 1 drivers
+v0000000003c05c50_0 .net "B1", 0 0, L_0000000004143620;  alias, 1 drivers
+L_000000000405d6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c075f0_0 .net8 "VGND", 0 0, L_000000000405d6c0;  1 drivers, strength-aware
+L_000000000405d650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c06c90_0 .net8 "VNB", 0 0, L_000000000405d650;  1 drivers, strength-aware
+L_000000000405d730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c061f0_0 .net8 "VPB", 0 0, L_000000000405d730;  1 drivers, strength-aware
+L_000000000405d7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06510_0 .net8 "VPWR", 0 0, L_000000000405d7a0;  1 drivers, strength-aware
+v0000000003c07e10_0 .net "Y", 0 0, L_0000000004158b10;  alias, 1 drivers
+v0000000003c06650_0 .net "nand0_out_Y", 0 0, L_0000000004157220;  1 drivers
+v0000000003c06330_0 .net "or0_out", 0 0, L_00000000041571b0;  1 drivers
+S_0000000003c45e00 .scope module, "_0957_" "sky130_fd_sc_hd__o221a_2" 3 3011, 4 75187 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003c07cd0_0 .net "A1", 0 0, L_0000000004123250;  alias, 1 drivers
+v0000000003c06970_0 .net "A2", 0 0, L_0000000004158c60;  alias, 1 drivers
+v0000000003c06a10_0 .net "B1", 0 0, L_0000000004157530;  alias, 1 drivers
+v0000000003c06ab0_0 .net "B2", 0 0, L_0000000004158b10;  alias, 1 drivers
+v0000000003c06b50_0 .net "C1", 0 0, L_00000000041589c0;  alias, 1 drivers
+L_000000000405ca10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c06e70_0 .net8 "VGND", 0 0, L_000000000405ca10;  1 drivers, strength-aware
+L_000000000405ca80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c07d70_0 .net8 "VNB", 0 0, L_000000000405ca80;  1 drivers, strength-aware
+L_000000000405d1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c06fb0_0 .net8 "VPB", 0 0, L_000000000405d1f0;  1 drivers, strength-aware
+L_000000000405c460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c07230_0 .net8 "VPWR", 0 0, L_000000000405c460;  1 drivers, strength-aware
+v0000000003c072d0_0 .net "X", 0 0, L_00000000041574c0;  alias, 1 drivers
+S_0000000003c4ad80 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_0000000003c45e00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004157290 .functor OR 1, L_0000000004158b10, L_0000000004157530, C4<0>, C4<0>;
+L_0000000004157450 .functor OR 1, L_0000000004158c60, L_0000000004123250, C4<0>, C4<0>;
+L_0000000004158b80 .functor AND 1, L_0000000004157290, L_0000000004157450, L_00000000041589c0, C4<1>;
+L_00000000041574c0 .functor BUF 1, L_0000000004158b80, C4<0>, C4<0>, C4<0>;
+v0000000003c05cf0_0 .net "A1", 0 0, L_0000000004123250;  alias, 1 drivers
+v0000000003c07050_0 .net "A2", 0 0, L_0000000004158c60;  alias, 1 drivers
+v0000000003c060b0_0 .net "B1", 0 0, L_0000000004157530;  alias, 1 drivers
+v0000000003c05d90_0 .net "B2", 0 0, L_0000000004158b10;  alias, 1 drivers
+v0000000003c07370_0 .net "C1", 0 0, L_00000000041589c0;  alias, 1 drivers
+L_000000000405c150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c07190_0 .net8 "VGND", 0 0, L_000000000405c150;  1 drivers, strength-aware
+L_000000000405d570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c07870_0 .net8 "VNB", 0 0, L_000000000405d570;  1 drivers, strength-aware
+L_000000000405bdd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c05e30_0 .net8 "VPB", 0 0, L_000000000405bdd0;  1 drivers, strength-aware
+L_000000000405cb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c05f70_0 .net8 "VPWR", 0 0, L_000000000405cb60;  1 drivers, strength-aware
+v0000000003c066f0_0 .net "X", 0 0, L_00000000041574c0;  alias, 1 drivers
+v0000000003c07910_0 .net "and0_out_X", 0 0, L_0000000004158b80;  1 drivers
+v0000000003c079b0_0 .net "or0_out", 0 0, L_0000000004157290;  1 drivers
+v0000000003c07af0_0 .net "or1_out", 0 0, L_0000000004157450;  1 drivers
+S_0000000003c4af00 .scope module, "_0958_" "sky130_fd_sc_hd__a2bb2oi_2" 3 3019, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c0a070_0 .net "A1_N", 0 0, L_0000000004157140;  alias, 1 drivers
+v0000000003c0a7f0_0 .net "A2_N", 0 0, L_00000000041574c0;  alias, 1 drivers
+v0000000003c092b0_0 .net "B1", 0 0, L_0000000004157140;  alias, 1 drivers
+v0000000003c09530_0 .net "B2", 0 0, L_00000000041574c0;  alias, 1 drivers
+L_000000000405c2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09cb0_0 .net8 "VGND", 0 0, L_000000000405c2a0;  1 drivers, strength-aware
+L_000000000405cc40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09710_0 .net8 "VNB", 0 0, L_000000000405cc40;  1 drivers, strength-aware
+L_000000000405c380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a890_0 .net8 "VPB", 0 0, L_000000000405c380;  1 drivers, strength-aware
+L_000000000405cbd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c08810_0 .net8 "VPWR", 0 0, L_000000000405cbd0;  1 drivers, strength-aware
+v0000000003c09170_0 .net "Y", 0 0, L_00000000041584f0;  alias, 1 drivers
+S_0000000003c46580 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003c4af00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041582c0 .functor AND 1, L_0000000004157140, L_00000000041574c0, C4<1>, C4<1>;
+L_0000000004158720 .functor NOR 1, L_0000000004157140, L_00000000041574c0, C4<0>, C4<0>;
+L_0000000004157760 .functor NOR 1, L_0000000004158720, L_00000000041582c0, C4<0>, C4<0>;
+L_00000000041584f0 .functor BUF 1, L_0000000004157760, C4<0>, C4<0>, C4<0>;
+v0000000003c07410_0 .net "A1_N", 0 0, L_0000000004157140;  alias, 1 drivers
+v0000000003c07eb0_0 .net "A2_N", 0 0, L_00000000041574c0;  alias, 1 drivers
+v0000000003c07ff0_0 .net "B1", 0 0, L_0000000004157140;  alias, 1 drivers
+v0000000003c08310_0 .net "B2", 0 0, L_00000000041574c0;  alias, 1 drivers
+L_000000000405ccb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a390_0 .net8 "VGND", 0 0, L_000000000405ccb0;  1 drivers, strength-aware
+L_000000000405cd20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c090d0_0 .net8 "VNB", 0 0, L_000000000405cd20;  1 drivers, strength-aware
+L_000000000405cd90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c08e50_0 .net8 "VPB", 0 0, L_000000000405cd90;  1 drivers, strength-aware
+L_000000000405d5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a570_0 .net8 "VPWR", 0 0, L_000000000405d5e0;  1 drivers, strength-aware
+v0000000003c084f0_0 .net "Y", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c08d10_0 .net "and0_out", 0 0, L_00000000041582c0;  1 drivers
+v0000000003c08590_0 .net "nor0_out", 0 0, L_0000000004158720;  1 drivers
+v0000000003c09a30_0 .net "nor1_out_Y", 0 0, L_0000000004157760;  1 drivers
+S_0000000003c45080 .scope module, "_0959_" "sky130_fd_sc_hd__nor2_2" 3 3026, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c089f0_0 .net "A", 0 0, L_0000000004158100;  alias, 1 drivers
+v0000000003c09fd0_0 .net "B", 0 0, L_00000000041584f0;  alias, 1 drivers
+L_000000000405cee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09490_0 .net8 "VGND", 0 0, L_000000000405cee0;  1 drivers, strength-aware
+L_000000000405d030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09350_0 .net8 "VNB", 0 0, L_000000000405d030;  1 drivers, strength-aware
+L_000000000405f3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c095d0_0 .net8 "VPB", 0 0, L_000000000405f3a0;  1 drivers, strength-aware
+L_000000000405f480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c088b0_0 .net8 "VPWR", 0 0, L_000000000405f480;  1 drivers, strength-aware
+v0000000003c083b0_0 .net "Y", 0 0, L_0000000004158870;  alias, 1 drivers
+S_0000000003c49100 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c45080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041581e0 .functor NOR 1, L_0000000004158100, L_00000000041584f0, C4<0>, C4<0>;
+L_0000000004158870 .functor BUF 1, L_00000000041581e0, C4<0>, C4<0>, C4<0>;
+v0000000003c09030_0 .net "A", 0 0, L_0000000004158100;  alias, 1 drivers
+v0000000003c08f90_0 .net "B", 0 0, L_00000000041584f0;  alias, 1 drivers
+L_000000000405e530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c08630_0 .net8 "VGND", 0 0, L_000000000405e530;  1 drivers, strength-aware
+L_000000000405ea00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c08130_0 .net8 "VNB", 0 0, L_000000000405ea00;  1 drivers, strength-aware
+L_000000000405e0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a6b0_0 .net8 "VPB", 0 0, L_000000000405e0d0;  1 drivers, strength-aware
+L_000000000405e290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c08950_0 .net8 "VPWR", 0 0, L_000000000405e290;  1 drivers, strength-aware
+v0000000003c09670_0 .net "Y", 0 0, L_0000000004158870;  alias, 1 drivers
+v0000000003c09210_0 .net "nor0_out_Y", 0 0, L_00000000041581e0;  1 drivers
+S_0000000003c46e80 .scope module, "_0960_" "sky130_fd_sc_hd__a21oi_2" 3 3031, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c0a4d0_0 .net "A1", 0 0, L_0000000004158100;  alias, 1 drivers
+v0000000003c0a110_0 .net "A2", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c081d0_0 .net "B1", 0 0, L_0000000004158870;  alias, 1 drivers
+L_000000000405e450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09df0_0 .net8 "VGND", 0 0, L_000000000405e450;  1 drivers, strength-aware
+L_000000000405e6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c098f0_0 .net8 "VNB", 0 0, L_000000000405e6f0;  1 drivers, strength-aware
+L_000000000405eca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c09d50_0 .net8 "VPB", 0 0, L_000000000405eca0;  1 drivers, strength-aware
+L_000000000405f2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a430_0 .net8 "VPWR", 0 0, L_000000000405f2c0;  1 drivers, strength-aware
+v0000000003c08a90_0 .net "Y", 0 0, L_00000000041583a0;  alias, 1 drivers
+S_0000000003c45980 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003c46e80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041575a0 .functor AND 1, L_0000000004158100, L_00000000041584f0, C4<1>, C4<1>;
+L_0000000004158330 .functor NOR 1, L_0000000004158870, L_00000000041575a0, C4<0>, C4<0>;
+L_00000000041583a0 .functor BUF 1, L_0000000004158330, C4<0>, C4<0>, C4<0>;
+v0000000003c086d0_0 .net "A1", 0 0, L_0000000004158100;  alias, 1 drivers
+v0000000003c09e90_0 .net "A2", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c097b0_0 .net "B1", 0 0, L_0000000004158870;  alias, 1 drivers
+L_000000000405dea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c08770_0 .net8 "VGND", 0 0, L_000000000405dea0;  1 drivers, strength-aware
+L_000000000405e4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c093f0_0 .net8 "VNB", 0 0, L_000000000405e4c0;  1 drivers, strength-aware
+L_000000000405ea70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c08c70_0 .net8 "VPB", 0 0, L_000000000405ea70;  1 drivers, strength-aware
+L_000000000405f330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c09850_0 .net8 "VPWR", 0 0, L_000000000405f330;  1 drivers, strength-aware
+v0000000003c0a250_0 .net "Y", 0 0, L_00000000041583a0;  alias, 1 drivers
+v0000000003c08db0_0 .net "and0_out", 0 0, L_00000000041575a0;  1 drivers
+v0000000003c0a750_0 .net "nor0_out_Y", 0 0, L_0000000004158330;  1 drivers
+S_0000000003c45200 .scope module, "_0961_" "sky130_fd_sc_hd__or2_2" 3 3037, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c0a2f0_0 .net "A", 0 0, L_000000000412b360;  alias, 1 drivers
+v0000000003c08bd0_0 .net "B", 0 0, L_000000000412e770;  alias, 1 drivers
+L_000000000405f020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09c10_0 .net8 "VGND", 0 0, L_000000000405f020;  1 drivers, strength-aware
+L_000000000405e140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0a610_0 .net8 "VNB", 0 0, L_000000000405e140;  1 drivers, strength-aware
+L_000000000405ed10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c09f30_0 .net8 "VPB", 0 0, L_000000000405ed10;  1 drivers, strength-aware
+L_000000000405e760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ad90_0 .net8 "VPWR", 0 0, L_000000000405e760;  1 drivers, strength-aware
+v0000000003c0cc30_0 .net "X", 0 0, L_0000000004157300;  alias, 1 drivers
+S_0000000003c48e00 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c45200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041576f0 .functor OR 1, L_000000000412e770, L_000000000412b360, C4<0>, C4<0>;
+L_0000000004157300 .functor BUF 1, L_00000000041576f0, C4<0>, C4<0>, C4<0>;
+v0000000003c0a1b0_0 .net "A", 0 0, L_000000000412b360;  alias, 1 drivers
+v0000000003c09990_0 .net "B", 0 0, L_000000000412e770;  alias, 1 drivers
+L_000000000405eae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c08ef0_0 .net8 "VGND", 0 0, L_000000000405eae0;  1 drivers, strength-aware
+L_000000000405f1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c09ad0_0 .net8 "VNB", 0 0, L_000000000405f1e0;  1 drivers, strength-aware
+L_000000000405e5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c08b30_0 .net8 "VPB", 0 0, L_000000000405e5a0;  1 drivers, strength-aware
+L_000000000405da40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c09b70_0 .net8 "VPWR", 0 0, L_000000000405da40;  1 drivers, strength-aware
+v0000000003c08270_0 .net "X", 0 0, L_0000000004157300;  alias, 1 drivers
+v0000000003c08450_0 .net "or0_out_X", 0 0, L_00000000041576f0;  1 drivers
+S_0000000003c47000 .scope module, "_0962_" "sky130_fd_sc_hd__o21ai_2" 3 3042, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c0b1f0_0 .net "A1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003c0af70_0 .net "A2", 0 0, L_000000000413e6f0;  alias, 1 drivers
+v0000000003c0ab10_0 .net "B1", 0 0, L_0000000004141940;  alias, 1 drivers
+L_000000000405df10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0bbf0_0 .net8 "VGND", 0 0, L_000000000405df10;  1 drivers, strength-aware
+L_000000000405dab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c4b0_0 .net8 "VNB", 0 0, L_000000000405dab0;  1 drivers, strength-aware
+L_000000000405e1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b290_0 .net8 "VPB", 0 0, L_000000000405e1b0;  1 drivers, strength-aware
+L_000000000405d8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b510_0 .net8 "VPWR", 0 0, L_000000000405d8f0;  1 drivers, strength-aware
+v0000000003c0c7d0_0 .net "Y", 0 0, L_0000000004157370;  alias, 1 drivers
+S_0000000003c46880 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c47000;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041577d0 .functor OR 1, L_000000000413e6f0, L_000000000413a390, C4<0>, C4<0>;
+L_0000000004158480 .functor NAND 1, L_0000000004141940, L_00000000041577d0, C4<1>, C4<1>;
+L_0000000004157370 .functor BUF 1, L_0000000004158480, C4<0>, C4<0>, C4<0>;
+v0000000003c0bc90_0 .net "A1", 0 0, L_000000000413a390;  alias, 1 drivers
+v0000000003c0b8d0_0 .net "A2", 0 0, L_000000000413e6f0;  alias, 1 drivers
+v0000000003c0d090_0 .net "B1", 0 0, L_0000000004141940;  alias, 1 drivers
+L_000000000405e840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c5f0_0 .net8 "VGND", 0 0, L_000000000405e840;  1 drivers, strength-aware
+L_000000000405e7d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b3d0_0 .net8 "VNB", 0 0, L_000000000405e7d0;  1 drivers, strength-aware
+L_000000000405d960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0abb0_0 .net8 "VPB", 0 0, L_000000000405d960;  1 drivers, strength-aware
+L_000000000405f090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0bd30_0 .net8 "VPWR", 0 0, L_000000000405f090;  1 drivers, strength-aware
+v0000000003c0c410_0 .net "Y", 0 0, L_0000000004157370;  alias, 1 drivers
+v0000000003c0b470_0 .net "nand0_out_Y", 0 0, L_0000000004158480;  1 drivers
+v0000000003c0b970_0 .net "or0_out", 0 0, L_00000000041577d0;  1 drivers
+S_0000000003c49b80 .scope module, "_0963_" "sky130_fd_sc_hd__or3_2" 3 3048, 4 49901 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003c0a930_0 .net "A", 0 0, L_00000000041397c0;  alias, 1 drivers
+v0000000003c0c2d0_0 .net "B", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000003c0b330_0 .net "C", 0 0, L_0000000004123d40;  alias, 1 drivers
+L_000000000405d9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c9b0_0 .net8 "VGND", 0 0, L_000000000405d9d0;  1 drivers, strength-aware
+L_000000000405db20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b0b0_0 .net8 "VNB", 0 0, L_000000000405db20;  1 drivers, strength-aware
+L_000000000405ed80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ba10_0 .net8 "VPB", 0 0, L_000000000405ed80;  1 drivers, strength-aware
+L_000000000405ddc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c550_0 .net8 "VPWR", 0 0, L_000000000405ddc0;  1 drivers, strength-aware
+v0000000003c0c870_0 .net "X", 0 0, L_00000000041588e0;  alias, 1 drivers
+S_0000000003c47a80 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_0000000003c49b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_00000000041586b0 .functor OR 1, L_000000000412bd00, L_00000000041397c0, L_0000000004123d40, C4<0>;
+L_00000000041588e0 .functor BUF 1, L_00000000041586b0, C4<0>, C4<0>, C4<0>;
+v0000000003c0ae30_0 .net "A", 0 0, L_00000000041397c0;  alias, 1 drivers
+v0000000003c0cff0_0 .net "B", 0 0, L_000000000412bd00;  alias, 1 drivers
+v0000000003c0cb90_0 .net "C", 0 0, L_0000000004123d40;  alias, 1 drivers
+L_000000000405e680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0acf0_0 .net8 "VGND", 0 0, L_000000000405e680;  1 drivers, strength-aware
+L_000000000405eb50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c050_0 .net8 "VNB", 0 0, L_000000000405eb50;  1 drivers, strength-aware
+L_000000000405ebc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b010_0 .net8 "VPB", 0 0, L_000000000405ebc0;  1 drivers, strength-aware
+L_000000000405db90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b790_0 .net8 "VPWR", 0 0, L_000000000405db90;  1 drivers, strength-aware
+v0000000003c0c910_0 .net "X", 0 0, L_00000000041588e0;  alias, 1 drivers
+v0000000003c0aed0_0 .net "or0_out_X", 0 0, L_00000000041586b0;  1 drivers
+S_0000000003c45c80 .scope module, "_0964_" "sky130_fd_sc_hd__a31o_2" 3 3054, 4 42118 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+v0000000003c0c690_0 .net "A1", 0 0, L_00000000041425f0;  alias, 1 drivers
+v0000000003c0b6f0_0 .net "A2", 0 0, L_00000000041238e0;  alias, 1 drivers
+v0000000003c0b830_0 .net "A3", 0 0, L_0000000004157370;  alias, 1 drivers
+v0000000003c0bab0_0 .net "B1", 0 0, L_00000000041588e0;  alias, 1 drivers
+L_000000000405e220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0be70_0 .net8 "VGND", 0 0, L_000000000405e220;  1 drivers, strength-aware
+L_000000000405dc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0bfb0_0 .net8 "VNB", 0 0, L_000000000405dc00;  1 drivers, strength-aware
+L_000000000405e300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0bb50_0 .net8 "VPB", 0 0, L_000000000405e300;  1 drivers, strength-aware
+L_000000000405e8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c230_0 .net8 "VPWR", 0 0, L_000000000405e8b0;  1 drivers, strength-aware
+v0000000003c0a9d0_0 .net "X", 0 0, L_000000000415a160;  alias, 1 drivers
+S_0000000003c4a600 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 42138, 4 41993 1, S_0000000003c45c80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004158a30 .functor AND 1, L_0000000004157370, L_00000000041425f0, L_00000000041238e0, C4<1>;
+L_0000000004158aa0 .functor OR 1, L_0000000004158a30, L_00000000041588e0, C4<0>, C4<0>;
+L_000000000415a160 .functor BUF 1, L_0000000004158aa0, C4<0>, C4<0>, C4<0>;
+v0000000003c0b150_0 .net "A1", 0 0, L_00000000041425f0;  alias, 1 drivers
+v0000000003c0ca50_0 .net "A2", 0 0, L_00000000041238e0;  alias, 1 drivers
+v0000000003c0bf10_0 .net "A3", 0 0, L_0000000004157370;  alias, 1 drivers
+v0000000003c0c0f0_0 .net "B1", 0 0, L_00000000041588e0;  alias, 1 drivers
+L_000000000405e610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0c370_0 .net8 "VGND", 0 0, L_000000000405e610;  1 drivers, strength-aware
+L_000000000405e370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ac50_0 .net8 "VNB", 0 0, L_000000000405e370;  1 drivers, strength-aware
+L_000000000405e920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0b5b0_0 .net8 "VPB", 0 0, L_000000000405e920;  1 drivers, strength-aware
+L_000000000405dc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ce10_0 .net8 "VPWR", 0 0, L_000000000405dc70;  1 drivers, strength-aware
+v0000000003c0b650_0 .net "X", 0 0, L_000000000415a160;  alias, 1 drivers
+v0000000003c0c190_0 .net "and0_out", 0 0, L_0000000004158a30;  1 drivers
+v0000000003c0bdd0_0 .net "or0_out_X", 0 0, L_0000000004158aa0;  1 drivers
+S_0000000003c45500 .scope module, "_0965_" "sky130_fd_sc_hd__o211ai_2" 3 3061, 4 78520 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003c0d810_0 .net "A1", 0 0, L_00000000041397c0;  alias, 1 drivers
+v0000000003c0df90_0 .net "A2", 0 0, L_000000000412e000;  alias, 1 drivers
+v0000000003c0f110_0 .net "B1", 0 0, L_000000000412deb0;  alias, 1 drivers
+v0000000003c0d4f0_0 .net "C1", 0 0, L_000000000415a160;  alias, 1 drivers
+L_000000000405ec30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e3f0_0 .net8 "VGND", 0 0, L_000000000405ec30;  1 drivers, strength-aware
+L_000000000405e990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ecb0_0 .net8 "VNB", 0 0, L_000000000405e990;  1 drivers, strength-aware
+L_000000000405eed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0d310_0 .net8 "VPB", 0 0, L_000000000405eed0;  1 drivers, strength-aware
+L_000000000405edf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f890_0 .net8 "VPWR", 0 0, L_000000000405edf0;  1 drivers, strength-aware
+v0000000003c0ead0_0 .net "Y", 0 0, L_0000000004159b40;  alias, 1 drivers
+S_0000000003c49280 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 78540, 4 78275 1, S_0000000003c45500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004159210 .functor OR 1, L_000000000412e000, L_00000000041397c0, C4<0>, C4<0>;
+L_0000000004159ad0 .functor NAND 1, L_000000000415a160, L_0000000004159210, L_000000000412deb0, C4<1>;
+L_0000000004159b40 .functor BUF 1, L_0000000004159ad0, C4<0>, C4<0>, C4<0>;
+v0000000003c0c730_0 .net "A1", 0 0, L_00000000041397c0;  alias, 1 drivers
+v0000000003c0caf0_0 .net "A2", 0 0, L_000000000412e000;  alias, 1 drivers
+v0000000003c0ccd0_0 .net "B1", 0 0, L_000000000412deb0;  alias, 1 drivers
+v0000000003c0cd70_0 .net "C1", 0 0, L_000000000415a160;  alias, 1 drivers
+L_000000000405ee60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ceb0_0 .net8 "VGND", 0 0, L_000000000405ee60;  1 drivers, strength-aware
+L_000000000405f410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0cf50_0 .net8 "VNB", 0 0, L_000000000405f410;  1 drivers, strength-aware
+L_000000000405dce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0aa70_0 .net8 "VPB", 0 0, L_000000000405dce0;  1 drivers, strength-aware
+L_000000000405ef40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f4d0_0 .net8 "VPWR", 0 0, L_000000000405ef40;  1 drivers, strength-aware
+v0000000003c0d590_0 .net "Y", 0 0, L_0000000004159b40;  alias, 1 drivers
+v0000000003c0f7f0_0 .net "nand0_out_Y", 0 0, L_0000000004159ad0;  1 drivers
+v0000000003c0f390_0 .net "or0_out", 0 0, L_0000000004159210;  1 drivers
+S_0000000003c47900 .scope module, "_0966_" "sky130_fd_sc_hd__a2bb2o_2" 3 3068, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c0d8b0_0 .net "A1_N", 0 0, L_0000000004157300;  alias, 1 drivers
+v0000000003c0d6d0_0 .net "A2_N", 0 0, L_0000000004159b40;  alias, 1 drivers
+v0000000003c0ddb0_0 .net "B1", 0 0, L_0000000004157300;  alias, 1 drivers
+v0000000003c0e490_0 .net "B2", 0 0, L_0000000004159b40;  alias, 1 drivers
+L_000000000405efb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0d450_0 .net8 "VGND", 0 0, L_000000000405efb0;  1 drivers, strength-aware
+L_000000000405f100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e850_0 .net8 "VNB", 0 0, L_000000000405f100;  1 drivers, strength-aware
+L_000000000405f170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ed50_0 .net8 "VPB", 0 0, L_000000000405f170;  1 drivers, strength-aware
+L_000000000405e3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0dc70_0 .net8 "VPWR", 0 0, L_000000000405e3e0;  1 drivers, strength-aware
+v0000000003c0e030_0 .net "X", 0 0, L_0000000004158fe0;  alias, 1 drivers
+S_0000000003c49a00 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003c47900;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004158f70 .functor AND 1, L_0000000004157300, L_0000000004159b40, C4<1>, C4<1>;
+L_000000000415a010 .functor NOR 1, L_0000000004157300, L_0000000004159b40, C4<0>, C4<0>;
+L_000000000415a240 .functor OR 1, L_000000000415a010, L_0000000004158f70, C4<0>, C4<0>;
+L_0000000004158fe0 .functor BUF 1, L_000000000415a240, C4<0>, C4<0>, C4<0>;
+v0000000003c0def0_0 .net "A1_N", 0 0, L_0000000004157300;  alias, 1 drivers
+v0000000003c0f570_0 .net "A2_N", 0 0, L_0000000004159b40;  alias, 1 drivers
+v0000000003c0f610_0 .net "B1", 0 0, L_0000000004157300;  alias, 1 drivers
+v0000000003c0e8f0_0 .net "B2", 0 0, L_0000000004159b40;  alias, 1 drivers
+L_000000000405de30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0efd0_0 .net8 "VGND", 0 0, L_000000000405de30;  1 drivers, strength-aware
+L_000000000405f250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0d130_0 .net8 "VNB", 0 0, L_000000000405f250;  1 drivers, strength-aware
+L_000000000405dd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e0d0_0 .net8 "VPB", 0 0, L_000000000405dd50;  1 drivers, strength-aware
+L_000000000405df80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e530_0 .net8 "VPWR", 0 0, L_000000000405df80;  1 drivers, strength-aware
+v0000000003c0f070_0 .net "X", 0 0, L_0000000004158fe0;  alias, 1 drivers
+v0000000003c0d3b0_0 .net "and0_out", 0 0, L_0000000004158f70;  1 drivers
+v0000000003c0d630_0 .net "nor0_out", 0 0, L_000000000415a010;  1 drivers
+v0000000003c0d1d0_0 .net "or0_out_X", 0 0, L_000000000415a240;  1 drivers
+S_0000000003c4ac00 .scope module, "_0967_" "sky130_fd_sc_hd__inv_2" 3 3075, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c0f6b0_0 .net "A", 0 0, L_0000000004158fe0;  alias, 1 drivers
+L_000000000405dff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e210_0 .net8 "VGND", 0 0, L_000000000405dff0;  1 drivers, strength-aware
+L_000000000405e060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f1b0_0 .net8 "VNB", 0 0, L_000000000405e060;  1 drivers, strength-aware
+L_0000000004060de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ec10_0 .net8 "VPB", 0 0, L_0000000004060de0;  1 drivers, strength-aware
+L_0000000004060a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0dd10_0 .net8 "VPWR", 0 0, L_0000000004060a60;  1 drivers, strength-aware
+v0000000003c0e2b0_0 .net "Y", 0 0, L_0000000004159670;  alias, 1 drivers
+S_0000000003c45380 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4ac00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004159bb0 .functor NOT 1, L_0000000004158fe0, C4<0>, C4<0>, C4<0>;
+L_0000000004159670 .functor BUF 1, L_0000000004159bb0, C4<0>, C4<0>, C4<0>;
+v0000000003c0d270_0 .net "A", 0 0, L_0000000004158fe0;  alias, 1 drivers
+L_00000000040609f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e990_0 .net8 "VGND", 0 0, L_00000000040609f0;  1 drivers, strength-aware
+L_0000000004060d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e5d0_0 .net8 "VNB", 0 0, L_0000000004060d00;  1 drivers, strength-aware
+L_0000000004060c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f430_0 .net8 "VPB", 0 0, L_0000000004060c20;  1 drivers, strength-aware
+L_0000000004060c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0d770_0 .net8 "VPWR", 0 0, L_0000000004060c90;  1 drivers, strength-aware
+v0000000003c0d950_0 .net "Y", 0 0, L_0000000004159670;  alias, 1 drivers
+v0000000003c0e170_0 .net "not0_out_Y", 0 0, L_0000000004159bb0;  1 drivers
+S_0000000003c48380 .scope module, "_0968_" "sky130_fd_sc_hd__or3_2" 3 3079, 4 49901 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003c0e350_0 .net "A", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c0ea30_0 .net "B", 0 0, L_0000000004158fe0;  alias, 1 drivers
+v0000000003c0ef30_0 .net "C", 0 0, L_0000000004158100;  alias, 1 drivers
+L_000000000405fe90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0db30_0 .net8 "VGND", 0 0, L_000000000405fe90;  1 drivers, strength-aware
+L_0000000004060050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f250_0 .net8 "VNB", 0 0, L_0000000004060050;  1 drivers, strength-aware
+L_00000000040602f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0dbd0_0 .net8 "VPB", 0 0, L_00000000040602f0;  1 drivers, strength-aware
+L_00000000040608a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f2f0_0 .net8 "VPWR", 0 0, L_00000000040608a0;  1 drivers, strength-aware
+v0000000003c0de50_0 .net "X", 0 0, L_0000000004159c90;  alias, 1 drivers
+S_0000000003c45680 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_0000000003c48380;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000415a1d0 .functor OR 1, L_0000000004158fe0, L_00000000041584f0, L_0000000004158100, C4<0>;
+L_0000000004159c90 .functor BUF 1, L_000000000415a1d0, C4<0>, C4<0>, C4<0>;
+v0000000003c0d9f0_0 .net "A", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c0e670_0 .net "B", 0 0, L_0000000004158fe0;  alias, 1 drivers
+v0000000003c0da90_0 .net "C", 0 0, L_0000000004158100;  alias, 1 drivers
+L_0000000004060ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0edf0_0 .net8 "VGND", 0 0, L_0000000004060ec0;  1 drivers, strength-aware
+L_000000000405faa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0ee90_0 .net8 "VNB", 0 0, L_000000000405faa0;  1 drivers, strength-aware
+L_00000000040600c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e710_0 .net8 "VPB", 0 0, L_00000000040600c0;  1 drivers, strength-aware
+L_0000000004060600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0e7b0_0 .net8 "VPWR", 0 0, L_0000000004060600;  1 drivers, strength-aware
+v0000000003c0f750_0 .net "X", 0 0, L_0000000004159c90;  alias, 1 drivers
+v0000000003c0eb70_0 .net "or0_out_X", 0 0, L_000000000415a1d0;  1 drivers
+S_0000000003c49d00 .scope module, "_0969_" "sky130_fd_sc_hd__o21a_2" 3 3085, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c10d30_0 .net "A1", 0 0, L_0000000004158870;  alias, 1 drivers
+v0000000003c11910_0 .net "A2", 0 0, L_0000000004159670;  alias, 1 drivers
+v0000000003c10010_0 .net "B1", 0 0, L_0000000004159c90;  alias, 1 drivers
+L_0000000004060f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11690_0 .net8 "VGND", 0 0, L_0000000004060f30;  1 drivers, strength-aware
+L_0000000004060d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11d70_0 .net8 "VNB", 0 0, L_0000000004060d70;  1 drivers, strength-aware
+L_000000000405fcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10510_0 .net8 "VPB", 0 0, L_000000000405fcd0;  1 drivers, strength-aware
+L_0000000004060910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c101f0_0 .net8 "VPWR", 0 0, L_0000000004060910;  1 drivers, strength-aware
+v0000000003c0fd90_0 .net "X", 0 0, L_000000000415a630;  alias, 1 drivers
+S_0000000003c4a300 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003c49d00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004159590 .functor OR 1, L_0000000004159670, L_0000000004158870, C4<0>, C4<0>;
+L_000000000415a7f0 .functor AND 1, L_0000000004159590, L_0000000004159c90, C4<1>, C4<1>;
+L_000000000415a630 .functor BUF 1, L_000000000415a7f0, C4<0>, C4<0>, C4<0>;
+v0000000003c119b0_0 .net "A1", 0 0, L_0000000004158870;  alias, 1 drivers
+v0000000003c106f0_0 .net "A2", 0 0, L_0000000004159670;  alias, 1 drivers
+v0000000003c11370_0 .net "B1", 0 0, L_0000000004159c90;  alias, 1 drivers
+L_0000000004060360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c117d0_0 .net8 "VGND", 0 0, L_0000000004060360;  1 drivers, strength-aware
+L_00000000040606e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0fc50_0 .net8 "VNB", 0 0, L_00000000040606e0;  1 drivers, strength-aware
+L_0000000004060e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10790_0 .net8 "VPB", 0 0, L_0000000004060e50;  1 drivers, strength-aware
+L_00000000040601a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0fcf0_0 .net8 "VPWR", 0 0, L_00000000040601a0;  1 drivers, strength-aware
+v0000000003c10470_0 .net "X", 0 0, L_000000000415a630;  alias, 1 drivers
+v0000000003c11cd0_0 .net "and0_out_X", 0 0, L_000000000415a7f0;  1 drivers
+v0000000003c11870_0 .net "or0_out", 0 0, L_0000000004159590;  1 drivers
+S_0000000003c49700 .scope module, "_0970_" "sky130_fd_sc_hd__inv_2" 3 3091, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c10ab0_0 .net "A", 0 0, L_000000000412ee00;  alias, 1 drivers
+L_000000000405f640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11ff0_0 .net8 "VGND", 0 0, L_000000000405f640;  1 drivers, strength-aware
+L_000000000405fb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c10b50_0 .net8 "VNB", 0 0, L_000000000405fb10;  1 drivers, strength-aware
+L_000000000405f6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c11550_0 .net8 "VPB", 0 0, L_000000000405f6b0;  1 drivers, strength-aware
+L_000000000405fdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c11c30_0 .net8 "VPWR", 0 0, L_000000000405fdb0;  1 drivers, strength-aware
+v0000000003c12090_0 .net "Y", 0 0, L_0000000004159980;  alias, 1 drivers
+S_0000000003c45800 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c49700;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004158d40 .functor NOT 1, L_000000000412ee00, C4<0>, C4<0>, C4<0>;
+L_0000000004159980 .functor BUF 1, L_0000000004158d40, C4<0>, C4<0>, C4<0>;
+v0000000003c114b0_0 .net "A", 0 0, L_000000000412ee00;  alias, 1 drivers
+L_0000000004061080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11e10_0 .net8 "VGND", 0 0, L_0000000004061080;  1 drivers, strength-aware
+L_0000000004060440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11a50_0 .net8 "VNB", 0 0, L_0000000004060440;  1 drivers, strength-aware
+L_00000000040603d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c11af0_0 .net8 "VPB", 0 0, L_00000000040603d0;  1 drivers, strength-aware
+L_000000000405f4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c11eb0_0 .net8 "VPWR", 0 0, L_000000000405f4f0;  1 drivers, strength-aware
+v0000000003c0fe30_0 .net "Y", 0 0, L_0000000004159980;  alias, 1 drivers
+v0000000003c10f10_0 .net "not0_out_Y", 0 0, L_0000000004158d40;  1 drivers
+S_0000000003c45f80 .scope module, "_0971_" "sky130_fd_sc_hd__or2_2" 3 3095, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c10e70_0 .net "A", 0 0, L_0000000004159980;  alias, 1 drivers
+v0000000003c10970_0 .net "B", 0 0, L_000000000412ea80;  alias, 1 drivers
+L_0000000004060fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c108d0_0 .net8 "VGND", 0 0, L_0000000004060fa0;  1 drivers, strength-aware
+L_000000000405f560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11730_0 .net8 "VNB", 0 0, L_000000000405f560;  1 drivers, strength-aware
+L_000000000405f5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c11f50_0 .net8 "VPB", 0 0, L_000000000405f5d0;  1 drivers, strength-aware
+L_0000000004060980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0fb10_0 .net8 "VPWR", 0 0, L_0000000004060980;  1 drivers, strength-aware
+v0000000003c11050_0 .net "X", 0 0, L_000000000415a080;  alias, 1 drivers
+S_0000000003c4a780 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c45f80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415a2b0 .functor OR 1, L_000000000412ea80, L_0000000004159980, C4<0>, C4<0>;
+L_000000000415a080 .functor BUF 1, L_000000000415a2b0, C4<0>, C4<0>, C4<0>;
+v0000000003c11b90_0 .net "A", 0 0, L_0000000004159980;  alias, 1 drivers
+v0000000003c11410_0 .net "B", 0 0, L_000000000412ea80;  alias, 1 drivers
+L_000000000405f9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c11230_0 .net8 "VGND", 0 0, L_000000000405f9c0;  1 drivers, strength-aware
+L_0000000004060280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c115f0_0 .net8 "VNB", 0 0, L_0000000004060280;  1 drivers, strength-aware
+L_0000000004060670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10830_0 .net8 "VPB", 0 0, L_0000000004060670;  1 drivers, strength-aware
+L_00000000040607c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c0fed0_0 .net8 "VPWR", 0 0, L_00000000040607c0;  1 drivers, strength-aware
+v0000000003c0ff70_0 .net "X", 0 0, L_000000000415a080;  alias, 1 drivers
+v0000000003c112d0_0 .net "or0_out_X", 0 0, L_000000000415a2b0;  1 drivers
+S_0000000003c49880 .scope module, "_0972_" "sky130_fd_sc_hd__o21a_2" 3 3100, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c100b0_0 .net "A1", 0 0, L_000000000412e770;  alias, 1 drivers
+v0000000003c10290_0 .net "A2", 0 0, L_0000000004158bf0;  alias, 1 drivers
+v0000000003c10330_0 .net "B1", 0 0, L_000000000412a2c0;  alias, 1 drivers
+L_000000000405f720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c103d0_0 .net8 "VGND", 0 0, L_000000000405f720;  1 drivers, strength-aware
+L_000000000405fd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c10dd0_0 .net8 "VNB", 0 0, L_000000000405fd40;  1 drivers, strength-aware
+L_000000000405f790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10fb0_0 .net8 "VPB", 0 0, L_000000000405f790;  1 drivers, strength-aware
+L_000000000405fe20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c110f0_0 .net8 "VPWR", 0 0, L_000000000405fe20;  1 drivers, strength-aware
+v0000000003c11190_0 .net "X", 0 0, L_0000000004158db0;  alias, 1 drivers
+S_0000000003c4a480 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003c49880;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041599f0 .functor OR 1, L_0000000004158bf0, L_000000000412e770, C4<0>, C4<0>;
+L_000000000415a4e0 .functor AND 1, L_00000000041599f0, L_000000000412a2c0, C4<1>, C4<1>;
+L_0000000004158db0 .functor BUF 1, L_000000000415a4e0, C4<0>, C4<0>, C4<0>;
+v0000000003c10a10_0 .net "A1", 0 0, L_000000000412e770;  alias, 1 drivers
+v0000000003c0f930_0 .net "A2", 0 0, L_0000000004158bf0;  alias, 1 drivers
+v0000000003c105b0_0 .net "B1", 0 0, L_000000000412a2c0;  alias, 1 drivers
+L_00000000040604b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0f9d0_0 .net8 "VGND", 0 0, L_00000000040604b0;  1 drivers, strength-aware
+L_0000000004060210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c0fa70_0 .net8 "VNB", 0 0, L_0000000004060210;  1 drivers, strength-aware
+L_000000000405ff00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10650_0 .net8 "VPB", 0 0, L_000000000405ff00;  1 drivers, strength-aware
+L_0000000004060130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c10bf0_0 .net8 "VPWR", 0 0, L_0000000004060130;  1 drivers, strength-aware
+v0000000003c0fbb0_0 .net "X", 0 0, L_0000000004158db0;  alias, 1 drivers
+v0000000003c10c90_0 .net "and0_out_X", 0 0, L_000000000415a4e0;  1 drivers
+v0000000003c10150_0 .net "or0_out", 0 0, L_00000000041599f0;  1 drivers
+S_0000000003c46100 .scope module, "_0973_" "sky130_fd_sc_hd__or2_2" 3 3106, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c124f0_0 .net "A", 0 0, L_0000000004158c60;  alias, 1 drivers
+v0000000003c14070_0 .net "B", 0 0, L_0000000004158db0;  alias, 1 drivers
+L_000000000405f800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12810_0 .net8 "VGND", 0 0, L_000000000405f800;  1 drivers, strength-aware
+L_0000000004060750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12630_0 .net8 "VNB", 0 0, L_0000000004060750;  1 drivers, strength-aware
+L_0000000004060520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c14250_0 .net8 "VPB", 0 0, L_0000000004060520;  1 drivers, strength-aware
+L_0000000004060ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c13710_0 .net8 "VPWR", 0 0, L_0000000004060ad0;  1 drivers, strength-aware
+v0000000003c126d0_0 .net "X", 0 0, L_000000000415a5c0;  alias, 1 drivers
+S_0000000003c4a900 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c46100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041597c0 .functor OR 1, L_0000000004158db0, L_0000000004158c60, C4<0>, C4<0>;
+L_000000000415a5c0 .functor BUF 1, L_00000000041597c0, C4<0>, C4<0>, C4<0>;
+v0000000003c141b0_0 .net "A", 0 0, L_0000000004158c60;  alias, 1 drivers
+v0000000003c12590_0 .net "B", 0 0, L_0000000004158db0;  alias, 1 drivers
+L_0000000004060b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12d10_0 .net8 "VGND", 0 0, L_0000000004060b40;  1 drivers, strength-aware
+L_0000000004060830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c13030_0 .net8 "VNB", 0 0, L_0000000004060830;  1 drivers, strength-aware
+L_0000000004061010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c130d0_0 .net8 "VPB", 0 0, L_0000000004061010;  1 drivers, strength-aware
+L_000000000405f870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c13670_0 .net8 "VPWR", 0 0, L_000000000405f870;  1 drivers, strength-aware
+v0000000003c135d0_0 .net "X", 0 0, L_000000000415a5c0;  alias, 1 drivers
+v0000000003c12130_0 .net "or0_out_X", 0 0, L_00000000041597c0;  1 drivers
+S_0000000003c46280 .scope module, "_0974_" "sky130_fd_sc_hd__nor2_2" 3 3111, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c123b0_0 .net "A", 0 0, L_000000000413bac0;  alias, 1 drivers
+v0000000003c13210_0 .net "B", 0 0, L_000000000413ebc0;  alias, 1 drivers
+L_0000000004060bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12270_0 .net8 "VGND", 0 0, L_0000000004060bb0;  1 drivers, strength-aware
+L_000000000405f8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12e50_0 .net8 "VNB", 0 0, L_000000000405f8e0;  1 drivers, strength-aware
+L_000000000405f950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c129f0_0 .net8 "VPB", 0 0, L_000000000405f950;  1 drivers, strength-aware
+L_000000000405fa30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c14390_0 .net8 "VPWR", 0 0, L_000000000405fa30;  1 drivers, strength-aware
+v0000000003c13b70_0 .net "Y", 0 0, L_0000000004159ec0;  alias, 1 drivers
+S_0000000003c4aa80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c46280;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004158e20 .functor NOR 1, L_000000000413bac0, L_000000000413ebc0, C4<0>, C4<0>;
+L_0000000004159ec0 .functor BUF 1, L_0000000004158e20, C4<0>, C4<0>, C4<0>;
+v0000000003c13990_0 .net "A", 0 0, L_000000000413bac0;  alias, 1 drivers
+v0000000003c13490_0 .net "B", 0 0, L_000000000413ebc0;  alias, 1 drivers
+L_000000000405ff70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c13170_0 .net8 "VGND", 0 0, L_000000000405ff70;  1 drivers, strength-aware
+L_000000000405fb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14890_0 .net8 "VNB", 0 0, L_000000000405fb80;  1 drivers, strength-aware
+L_000000000405fbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c121d0_0 .net8 "VPB", 0 0, L_000000000405fbf0;  1 drivers, strength-aware
+L_000000000405fc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c12bd0_0 .net8 "VPWR", 0 0, L_000000000405fc60;  1 drivers, strength-aware
+v0000000003c12c70_0 .net "Y", 0 0, L_0000000004159ec0;  alias, 1 drivers
+v0000000003c12db0_0 .net "nor0_out_Y", 0 0, L_0000000004158e20;  1 drivers
+S_0000000003c46700 .scope module, "_0975_" "sky130_fd_sc_hd__o211a_2" 3 3116, 4 77704 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003c13cb0_0 .net "A1", 0 0, L_00000000041417f0;  alias, 1 drivers
+v0000000003c13d50_0 .net "A2", 0 0, L_0000000004159ec0;  alias, 1 drivers
+v0000000003c12310_0 .net "B1", 0 0, L_0000000004140e50;  alias, 1 drivers
+v0000000003c12450_0 .net "C1", 0 0, L_00000000041239c0;  alias, 1 drivers
+L_000000000405ffe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14430_0 .net8 "VGND", 0 0, L_000000000405ffe0;  1 drivers, strength-aware
+L_0000000004060590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12b30_0 .net8 "VNB", 0 0, L_0000000004060590;  1 drivers, strength-aware
+L_00000000040620b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c142f0_0 .net8 "VPB", 0 0, L_00000000040620b0;  1 drivers, strength-aware
+L_00000000040629e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c12ef0_0 .net8 "VPWR", 0 0, L_00000000040629e0;  1 drivers, strength-aware
+v0000000003c13df0_0 .net "X", 0 0, L_00000000041592f0;  alias, 1 drivers
+S_0000000003c49e80 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_0000000003c46700;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004159830 .functor OR 1, L_0000000004159ec0, L_00000000041417f0, C4<0>, C4<0>;
+L_0000000004158e90 .functor AND 1, L_0000000004159830, L_0000000004140e50, L_00000000041239c0, C4<1>;
+L_00000000041592f0 .functor BUF 1, L_0000000004158e90, C4<0>, C4<0>, C4<0>;
+v0000000003c13a30_0 .net "A1", 0 0, L_00000000041417f0;  alias, 1 drivers
+v0000000003c14750_0 .net "A2", 0 0, L_0000000004159ec0;  alias, 1 drivers
+v0000000003c132b0_0 .net "B1", 0 0, L_0000000004140e50;  alias, 1 drivers
+v0000000003c144d0_0 .net "C1", 0 0, L_00000000041239c0;  alias, 1 drivers
+L_0000000004062660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12770_0 .net8 "VGND", 0 0, L_0000000004062660;  1 drivers, strength-aware
+L_00000000040625f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c12f90_0 .net8 "VNB", 0 0, L_00000000040625f0;  1 drivers, strength-aware
+L_0000000004062900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c13ad0_0 .net8 "VPB", 0 0, L_0000000004062900;  1 drivers, strength-aware
+L_0000000004062a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c13c10_0 .net8 "VPWR", 0 0, L_0000000004062a50;  1 drivers, strength-aware
+v0000000003c128b0_0 .net "X", 0 0, L_00000000041592f0;  alias, 1 drivers
+v0000000003c12a90_0 .net "and0_out_X", 0 0, L_0000000004158e90;  1 drivers
+v0000000003c12950_0 .net "or0_out", 0 0, L_0000000004159830;  1 drivers
+S_0000000003c49400 .scope module, "_0976_" "sky130_fd_sc_hd__or2_2" 3 3123, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c13e90_0 .net "A", 0 0, L_00000000041589c0;  alias, 1 drivers
+v0000000003c13f30_0 .net "B", 0 0, L_0000000004158db0;  alias, 1 drivers
+L_0000000004062ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14110_0 .net8 "VGND", 0 0, L_0000000004062ac0;  1 drivers, strength-aware
+L_0000000004062b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14570_0 .net8 "VNB", 0 0, L_0000000004062b30;  1 drivers, strength-aware
+L_0000000004061be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c14610_0 .net8 "VPB", 0 0, L_0000000004061be0;  1 drivers, strength-aware
+L_0000000004061a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c146b0_0 .net8 "VPWR", 0 0, L_0000000004061a20;  1 drivers, strength-aware
+v0000000003c16050_0 .net "X", 0 0, L_000000000415a400;  alias, 1 drivers
+S_0000000003c46400 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c49400;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415a470 .functor OR 1, L_0000000004158db0, L_00000000041589c0, C4<0>, C4<0>;
+L_000000000415a400 .functor BUF 1, L_000000000415a470, C4<0>, C4<0>, C4<0>;
+v0000000003c138f0_0 .net "A", 0 0, L_00000000041589c0;  alias, 1 drivers
+v0000000003c13350_0 .net "B", 0 0, L_0000000004158db0;  alias, 1 drivers
+L_0000000004062510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c133f0_0 .net8 "VGND", 0 0, L_0000000004062510;  1 drivers, strength-aware
+L_00000000040617f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c13530_0 .net8 "VNB", 0 0, L_00000000040617f0;  1 drivers, strength-aware
+L_00000000040612b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c13fd0_0 .net8 "VPB", 0 0, L_00000000040612b0;  1 drivers, strength-aware
+L_00000000040626d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c137b0_0 .net8 "VPWR", 0 0, L_00000000040626d0;  1 drivers, strength-aware
+v0000000003c13850_0 .net "X", 0 0, L_000000000415a400;  alias, 1 drivers
+v0000000003c147f0_0 .net "or0_out_X", 0 0, L_000000000415a470;  1 drivers
+S_0000000003c47780 .scope module, "_0977_" "sky130_fd_sc_hd__o21ai_2" 3 3128, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c14cf0_0 .net "A1", 0 0, L_000000000412ab10;  alias, 1 drivers
+v0000000003c15fb0_0 .net "A2", 0 0, L_0000000004138aa0;  alias, 1 drivers
+v0000000003c16e10_0 .net "B1", 0 0, L_000000000412a720;  alias, 1 drivers
+L_00000000040610f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c16910_0 .net8 "VGND", 0 0, L_00000000040610f0;  1 drivers, strength-aware
+L_0000000004061ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c149d0_0 .net8 "VNB", 0 0, L_0000000004061ef0;  1 drivers, strength-aware
+L_00000000040616a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16230_0 .net8 "VPB", 0 0, L_00000000040616a0;  1 drivers, strength-aware
+L_0000000004062040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16550_0 .net8 "VPWR", 0 0, L_0000000004062040;  1 drivers, strength-aware
+v0000000003c165f0_0 .net "Y", 0 0, L_000000000415a320;  alias, 1 drivers
+S_0000000003c47180 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c47780;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004159c20 .functor OR 1, L_0000000004138aa0, L_000000000412ab10, C4<0>, C4<0>;
+L_0000000004159360 .functor NAND 1, L_000000000412a720, L_0000000004159c20, C4<1>, C4<1>;
+L_000000000415a320 .functor BUF 1, L_0000000004159360, C4<0>, C4<0>, C4<0>;
+v0000000003c16f50_0 .net "A1", 0 0, L_000000000412ab10;  alias, 1 drivers
+v0000000003c15f10_0 .net "A2", 0 0, L_0000000004138aa0;  alias, 1 drivers
+v0000000003c16cd0_0 .net "B1", 0 0, L_000000000412a720;  alias, 1 drivers
+L_00000000040615c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c16870_0 .net8 "VGND", 0 0, L_00000000040615c0;  1 drivers, strength-aware
+L_0000000004061cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14930_0 .net8 "VNB", 0 0, L_0000000004061cc0;  1 drivers, strength-aware
+L_0000000004061390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16190_0 .net8 "VPB", 0 0, L_0000000004061390;  1 drivers, strength-aware
+L_0000000004061f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16410_0 .net8 "VPWR", 0 0, L_0000000004061f60;  1 drivers, strength-aware
+v0000000003c164b0_0 .net "Y", 0 0, L_000000000415a320;  alias, 1 drivers
+v0000000003c15830_0 .net "nand0_out_Y", 0 0, L_0000000004159360;  1 drivers
+v0000000003c16d70_0 .net "or0_out", 0 0, L_0000000004159c20;  1 drivers
+S_0000000003c46a00 .scope module, "_0978_" "sky130_fd_sc_hd__o311a_2" 3 3134, 4 48371 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003c16eb0_0 .net "A1", 0 0, L_0000000004123c60;  alias, 1 drivers
+v0000000003c16370_0 .net "A2", 0 0, L_000000000415a5c0;  alias, 1 drivers
+v0000000003c14e30_0 .net "A3", 0 0, L_00000000041592f0;  alias, 1 drivers
+v0000000003c16c30_0 .net "B1", 0 0, L_000000000415a400;  alias, 1 drivers
+v0000000003c16730_0 .net "C1", 0 0, L_000000000415a320;  alias, 1 drivers
+L_0000000004061a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14b10_0 .net8 "VGND", 0 0, L_0000000004061a90;  1 drivers, strength-aware
+L_0000000004062580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c167d0_0 .net8 "VNB", 0 0, L_0000000004062580;  1 drivers, strength-aware
+L_0000000004062120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16a50_0 .net8 "VPB", 0 0, L_0000000004062120;  1 drivers, strength-aware
+L_0000000004061c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c16b90_0 .net8 "VPWR", 0 0, L_0000000004061c50;  1 drivers, strength-aware
+v0000000003c16af0_0 .net "X", 0 0, L_00000000041590c0;  alias, 1 drivers
+S_0000000003c47300 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48393, 4 48837 1, S_0000000003c46a00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004159600 .functor OR 1, L_000000000415a5c0, L_0000000004123c60, L_00000000041592f0, C4<0>;
+L_0000000004159280 .functor AND 1, L_0000000004159600, L_000000000415a400, L_000000000415a320, C4<1>;
+L_00000000041590c0 .functor BUF 1, L_0000000004159280, C4<0>, C4<0>, C4<0>;
+v0000000003c156f0_0 .net "A1", 0 0, L_0000000004123c60;  alias, 1 drivers
+v0000000003c169b0_0 .net "A2", 0 0, L_000000000415a5c0;  alias, 1 drivers
+v0000000003c16690_0 .net "A3", 0 0, L_00000000041592f0;  alias, 1 drivers
+v0000000003c162d0_0 .net "B1", 0 0, L_000000000415a400;  alias, 1 drivers
+v0000000003c158d0_0 .net "C1", 0 0, L_000000000415a320;  alias, 1 drivers
+L_0000000004062ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c15790_0 .net8 "VGND", 0 0, L_0000000004062ba0;  1 drivers, strength-aware
+L_0000000004062c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c15e70_0 .net8 "VNB", 0 0, L_0000000004062c80;  1 drivers, strength-aware
+L_0000000004061d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c15dd0_0 .net8 "VPB", 0 0, L_0000000004061d30;  1 drivers, strength-aware
+L_0000000004062200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c14a70_0 .net8 "VPWR", 0 0, L_0000000004062200;  1 drivers, strength-aware
+v0000000003c14d90_0 .net "X", 0 0, L_00000000041590c0;  alias, 1 drivers
+v0000000003c15150_0 .net "and0_out_X", 0 0, L_0000000004159280;  1 drivers
+v0000000003c160f0_0 .net "or0_out", 0 0, L_0000000004159600;  1 drivers
+S_0000000003c47c00 .scope module, "_0979_" "sky130_fd_sc_hd__a2bb2oi_2" 3 3142, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c17090_0 .net "A1_N", 0 0, L_000000000415a080;  alias, 1 drivers
+v0000000003c14ed0_0 .net "A2_N", 0 0, L_00000000041590c0;  alias, 1 drivers
+v0000000003c15010_0 .net "B1", 0 0, L_000000000415a080;  alias, 1 drivers
+v0000000003c150b0_0 .net "B2", 0 0, L_00000000041590c0;  alias, 1 drivers
+L_00000000040618d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c155b0_0 .net8 "VGND", 0 0, L_00000000040618d0;  1 drivers, strength-aware
+L_0000000004061160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c15650_0 .net8 "VNB", 0 0, L_0000000004061160;  1 drivers, strength-aware
+L_0000000004062740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c15970_0 .net8 "VPB", 0 0, L_0000000004062740;  1 drivers, strength-aware
+L_00000000040627b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c15a10_0 .net8 "VPWR", 0 0, L_00000000040627b0;  1 drivers, strength-aware
+v0000000003c15ab0_0 .net "Y", 0 0, L_00000000041593d0;  alias, 1 drivers
+S_0000000003c47d80 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003c47c00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041598a0 .functor AND 1, L_000000000415a080, L_00000000041590c0, C4<1>, C4<1>;
+L_0000000004158f00 .functor NOR 1, L_000000000415a080, L_00000000041590c0, C4<0>, C4<0>;
+L_0000000004159050 .functor NOR 1, L_0000000004158f00, L_00000000041598a0, C4<0>, C4<0>;
+L_00000000041593d0 .functor BUF 1, L_0000000004159050, C4<0>, C4<0>, C4<0>;
+v0000000003c15d30_0 .net "A1_N", 0 0, L_000000000415a080;  alias, 1 drivers
+v0000000003c15bf0_0 .net "A2_N", 0 0, L_00000000041590c0;  alias, 1 drivers
+v0000000003c151f0_0 .net "B1", 0 0, L_000000000415a080;  alias, 1 drivers
+v0000000003c15470_0 .net "B2", 0 0, L_00000000041590c0;  alias, 1 drivers
+L_0000000004061b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c14bb0_0 .net8 "VGND", 0 0, L_0000000004061b00;  1 drivers, strength-aware
+L_0000000004062820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c153d0_0 .net8 "VNB", 0 0, L_0000000004062820;  1 drivers, strength-aware
+L_0000000004061940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c15290_0 .net8 "VPB", 0 0, L_0000000004061940;  1 drivers, strength-aware
+L_0000000004062350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c14f70_0 .net8 "VPWR", 0 0, L_0000000004062350;  1 drivers, strength-aware
+v0000000003c14c50_0 .net "Y", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c15510_0 .net "and0_out", 0 0, L_00000000041598a0;  1 drivers
+v0000000003c16ff0_0 .net "nor0_out", 0 0, L_0000000004158f00;  1 drivers
+v0000000003c15330_0 .net "nor1_out_Y", 0 0, L_0000000004159050;  1 drivers
+S_0000000003c47f00 .scope module, "_0980_" "sky130_fd_sc_hd__nor2_2" 3 3149, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c18b70_0 .net "A", 0 0, L_0000000004159c90;  alias, 1 drivers
+v0000000003c19570_0 .net "B", 0 0, L_00000000041593d0;  alias, 1 drivers
+L_00000000040623c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c174f0_0 .net8 "VGND", 0 0, L_00000000040623c0;  1 drivers, strength-aware
+L_0000000004061b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c188f0_0 .net8 "VNB", 0 0, L_0000000004061b70;  1 drivers, strength-aware
+L_00000000040619b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c17630_0 .net8 "VPB", 0 0, L_00000000040619b0;  1 drivers, strength-aware
+L_0000000004062890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18030_0 .net8 "VPWR", 0 0, L_0000000004062890;  1 drivers, strength-aware
+v0000000003c18a30_0 .net "Y", 0 0, L_0000000004159e50;  alias, 1 drivers
+S_0000000003c48080 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c47f00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004159130 .functor NOR 1, L_0000000004159c90, L_00000000041593d0, C4<0>, C4<0>;
+L_0000000004159e50 .functor BUF 1, L_0000000004159130, C4<0>, C4<0>, C4<0>;
+v0000000003c15b50_0 .net "A", 0 0, L_0000000004159c90;  alias, 1 drivers
+v0000000003c15c90_0 .net "B", 0 0, L_00000000041593d0;  alias, 1 drivers
+L_0000000004062970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c17770_0 .net8 "VGND", 0 0, L_0000000004062970;  1 drivers, strength-aware
+L_00000000040611d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c191b0_0 .net8 "VNB", 0 0, L_00000000040611d0;  1 drivers, strength-aware
+L_0000000004062270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c176d0_0 .net8 "VPB", 0 0, L_0000000004062270;  1 drivers, strength-aware
+L_0000000004062c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18210_0 .net8 "VPWR", 0 0, L_0000000004062c10;  1 drivers, strength-aware
+v0000000003c18d50_0 .net "Y", 0 0, L_0000000004159e50;  alias, 1 drivers
+v0000000003c18fd0_0 .net "nor0_out_Y", 0 0, L_0000000004159130;  1 drivers
+S_0000000003c48200 .scope module, "_0981_" "sky130_fd_sc_hd__a21oi_2" 3 3154, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c18490_0 .net "A1", 0 0, L_0000000004159c90;  alias, 1 drivers
+v0000000003c19430_0 .net "A2", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c18990_0 .net "B1", 0 0, L_0000000004159e50;  alias, 1 drivers
+L_0000000004061da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c18df0_0 .net8 "VGND", 0 0, L_0000000004061da0;  1 drivers, strength-aware
+L_0000000004061860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c17d10_0 .net8 "VNB", 0 0, L_0000000004061860;  1 drivers, strength-aware
+L_0000000004061240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c17810_0 .net8 "VPB", 0 0, L_0000000004061240;  1 drivers, strength-aware
+L_0000000004061320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c194d0_0 .net8 "VPWR", 0 0, L_0000000004061320;  1 drivers, strength-aware
+v0000000003c19070_0 .net "Y", 0 0, L_000000000415a390;  alias, 1 drivers
+S_0000000003c48500 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003c48200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415a710 .functor AND 1, L_0000000004159c90, L_00000000041593d0, C4<1>, C4<1>;
+L_000000000415a550 .functor NOR 1, L_0000000004159e50, L_000000000415a710, C4<0>, C4<0>;
+L_000000000415a390 .functor BUF 1, L_000000000415a550, C4<0>, C4<0>, C4<0>;
+v0000000003c18f30_0 .net "A1", 0 0, L_0000000004159c90;  alias, 1 drivers
+v0000000003c182b0_0 .net "A2", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c17f90_0 .net "B1", 0 0, L_0000000004159e50;  alias, 1 drivers
+L_0000000004061e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c18e90_0 .net8 "VGND", 0 0, L_0000000004061e10;  1 drivers, strength-aware
+L_0000000004061400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c18350_0 .net8 "VNB", 0 0, L_0000000004061400;  1 drivers, strength-aware
+L_0000000004061e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c19390_0 .net8 "VPB", 0 0, L_0000000004061e80;  1 drivers, strength-aware
+L_0000000004061fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18850_0 .net8 "VPWR", 0 0, L_0000000004061fd0;  1 drivers, strength-aware
+v0000000003c18cb0_0 .net "Y", 0 0, L_000000000415a390;  alias, 1 drivers
+v0000000003c17c70_0 .net "and0_out", 0 0, L_000000000415a710;  1 drivers
+v0000000003c17590_0 .net "nor0_out_Y", 0 0, L_000000000415a550;  1 drivers
+S_0000000003c48680 .scope module, "_0982_" "sky130_fd_sc_hd__nor2_2" 3 3160, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c19110_0 .net "A", 0 0, L_0000000004139750;  alias, 1 drivers
+v0000000003c18c10_0 .net "B", 0 0, L_00000000041295a0;  alias, 1 drivers
+L_00000000040622e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c17db0_0 .net8 "VGND", 0 0, L_00000000040622e0;  1 drivers, strength-aware
+L_0000000004061630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c180d0_0 .net8 "VNB", 0 0, L_0000000004061630;  1 drivers, strength-aware
+L_0000000004061470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18170_0 .net8 "VPB", 0 0, L_0000000004061470;  1 drivers, strength-aware
+L_00000000040614e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18670_0 .net8 "VPWR", 0 0, L_00000000040614e0;  1 drivers, strength-aware
+v0000000003c185d0_0 .net "Y", 0 0, L_000000000415a860;  alias, 1 drivers
+S_0000000003c4a000 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c48680;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004159d00 .functor NOR 1, L_0000000004139750, L_00000000041295a0, C4<0>, C4<0>;
+L_000000000415a860 .functor BUF 1, L_0000000004159d00, C4<0>, C4<0>, C4<0>;
+v0000000003c18ad0_0 .net "A", 0 0, L_0000000004139750;  alias, 1 drivers
+v0000000003c18530_0 .net "B", 0 0, L_00000000041295a0;  alias, 1 drivers
+L_0000000004061550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c19610_0 .net8 "VGND", 0 0, L_0000000004061550;  1 drivers, strength-aware
+L_00000000040624a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c197f0_0 .net8 "VNB", 0 0, L_00000000040624a0;  1 drivers, strength-aware
+L_0000000004062190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c178b0_0 .net8 "VPB", 0 0, L_0000000004062190;  1 drivers, strength-aware
+L_0000000004061710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c19890_0 .net8 "VPWR", 0 0, L_0000000004061710;  1 drivers, strength-aware
+v0000000003c196b0_0 .net "Y", 0 0, L_000000000415a860;  alias, 1 drivers
+v0000000003c19750_0 .net "nor0_out_Y", 0 0, L_0000000004159d00;  1 drivers
+S_0000000003c48980 .scope module, "_0983_" "sky130_fd_sc_hd__nor2_2" 3 3165, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c17270_0 .net "A", 0 0, L_0000000004137d10;  alias, 1 drivers
+v0000000003c173b0_0 .net "B", 0 0, L_0000000004137840;  alias, 1 drivers
+L_0000000004062430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c17450_0 .net8 "VGND", 0 0, L_0000000004062430;  1 drivers, strength-aware
+L_0000000004061780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c183f0_0 .net8 "VNB", 0 0, L_0000000004061780;  1 drivers, strength-aware
+L_0000000004063070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c192f0_0 .net8 "VPB", 0 0, L_0000000004063070;  1 drivers, strength-aware
+L_00000000040631c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c18710_0 .net8 "VPWR", 0 0, L_00000000040631c0;  1 drivers, strength-aware
+v0000000003c179f0_0 .net "Y", 0 0, L_00000000041591a0;  alias, 1 drivers
+S_0000000003c4a180 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c48980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415a6a0 .functor NOR 1, L_0000000004137d10, L_0000000004137840, C4<0>, C4<0>;
+L_00000000041591a0 .functor BUF 1, L_000000000415a6a0, C4<0>, C4<0>, C4<0>;
+v0000000003c17950_0 .net "A", 0 0, L_0000000004137d10;  alias, 1 drivers
+v0000000003c17130_0 .net "B", 0 0, L_0000000004137840;  alias, 1 drivers
+L_0000000004063000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c17310_0 .net8 "VGND", 0 0, L_0000000004063000;  1 drivers, strength-aware
+L_0000000004063700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c19250_0 .net8 "VNB", 0 0, L_0000000004063700;  1 drivers, strength-aware
+L_00000000040646c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c17e50_0 .net8 "VPB", 0 0, L_00000000040646c0;  1 drivers, strength-aware
+L_00000000040647a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c17ef0_0 .net8 "VPWR", 0 0, L_00000000040647a0;  1 drivers, strength-aware
+v0000000003c171d0_0 .net "Y", 0 0, L_00000000041591a0;  alias, 1 drivers
+v0000000003c17b30_0 .net "nor0_out_Y", 0 0, L_000000000415a6a0;  1 drivers
+S_0000000003c48c80 .scope module, "_0984_" "sky130_fd_sc_hd__o211a_2" 3 3170, 4 77704 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+v0000000003c1bff0_0 .net "A1", 0 0, L_00000000041437e0;  alias, 1 drivers
+v0000000003c1bb90_0 .net "A2", 0 0, L_00000000041591a0;  alias, 1 drivers
+v0000000003c1ba50_0 .net "B1", 0 0, L_0000000004143460;  alias, 1 drivers
+v0000000003c1b870_0 .net "C1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+L_00000000040632a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1b050_0 .net8 "VGND", 0 0, L_00000000040632a0;  1 drivers, strength-aware
+L_0000000004063b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a010_0 .net8 "VNB", 0 0, L_0000000004063b60;  1 drivers, strength-aware
+L_0000000004062eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a790_0 .net8 "VPB", 0 0, L_0000000004062eb0;  1 drivers, strength-aware
+L_0000000004064730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1b910_0 .net8 "VPWR", 0 0, L_0000000004064730;  1 drivers, strength-aware
+v0000000003c19cf0_0 .net "X", 0 0, L_0000000004159de0;  alias, 1 drivers
+S_0000000003c48f80 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_0000000003c48c80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004159440 .functor OR 1, L_00000000041591a0, L_00000000041437e0, C4<0>, C4<0>;
+L_0000000004159d70 .functor AND 1, L_0000000004159440, L_0000000004143460, L_000000000412d9e0, C4<1>;
+L_0000000004159de0 .functor BUF 1, L_0000000004159d70, C4<0>, C4<0>, C4<0>;
+v0000000003c17a90_0 .net "A1", 0 0, L_00000000041437e0;  alias, 1 drivers
+v0000000003c187b0_0 .net "A2", 0 0, L_00000000041591a0;  alias, 1 drivers
+v0000000003c17bd0_0 .net "B1", 0 0, L_0000000004143460;  alias, 1 drivers
+v0000000003c1a1f0_0 .net "C1", 0 0, L_000000000412d9e0;  alias, 1 drivers
+L_0000000004063690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c19a70_0 .net8 "VGND", 0 0, L_0000000004063690;  1 drivers, strength-aware
+L_0000000004063bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1b7d0_0 .net8 "VNB", 0 0, L_0000000004063bd0;  1 drivers, strength-aware
+L_0000000004064420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1b550_0 .net8 "VPB", 0 0, L_0000000004064420;  1 drivers, strength-aware
+L_0000000004063a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1af10_0 .net8 "VPWR", 0 0, L_0000000004063a10;  1 drivers, strength-aware
+v0000000003c1ad30_0 .net "X", 0 0, L_0000000004159de0;  alias, 1 drivers
+v0000000003c1bd70_0 .net "and0_out_X", 0 0, L_0000000004159d70;  1 drivers
+v0000000003c1aab0_0 .net "or0_out", 0 0, L_0000000004159440;  1 drivers
+S_0000000003c50300 .scope module, "_0985_" "sky130_fd_sc_hd__o311a_2" 3 3177, 4 48371 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+v0000000003c1b4b0_0 .net "A1", 0 0, L_00000000041386b0;  alias, 1 drivers
+v0000000003c1a0b0_0 .net "A2", 0 0, L_0000000004138fe0;  alias, 1 drivers
+v0000000003c1b730_0 .net "A3", 0 0, L_0000000004159de0;  alias, 1 drivers
+v0000000003c1be10_0 .net "B1", 0 0, L_000000000412b7c0;  alias, 1 drivers
+v0000000003c1b690_0 .net "C1", 0 0, L_000000000412f2d0;  alias, 1 drivers
+L_00000000040645e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1baf0_0 .net8 "VGND", 0 0, L_00000000040645e0;  1 drivers, strength-aware
+L_0000000004063c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1beb0_0 .net8 "VNB", 0 0, L_0000000004063c40;  1 drivers, strength-aware
+L_0000000004064110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c19d90_0 .net8 "VPB", 0 0, L_0000000004064110;  1 drivers, strength-aware
+L_00000000040630e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a8d0_0 .net8 "VPWR", 0 0, L_00000000040630e0;  1 drivers, strength-aware
+v0000000003c1bc30_0 .net "X", 0 0, L_0000000004159f30;  alias, 1 drivers
+S_0000000003c4f700 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48393, 4 48837 1, S_0000000003c50300;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041594b0 .functor OR 1, L_0000000004138fe0, L_00000000041386b0, L_0000000004159de0, C4<0>;
+L_0000000004159910 .functor AND 1, L_00000000041594b0, L_000000000412b7c0, L_000000000412f2d0, C4<1>;
+L_0000000004159f30 .functor BUF 1, L_0000000004159910, C4<0>, C4<0>, C4<0>;
+v0000000003c1b2d0_0 .net "A1", 0 0, L_00000000041386b0;  alias, 1 drivers
+v0000000003c1b5f0_0 .net "A2", 0 0, L_0000000004138fe0;  alias, 1 drivers
+v0000000003c1b190_0 .net "A3", 0 0, L_0000000004159de0;  alias, 1 drivers
+v0000000003c1b410_0 .net "B1", 0 0, L_000000000412b7c0;  alias, 1 drivers
+v0000000003c1b370_0 .net "C1", 0 0, L_000000000412f2d0;  alias, 1 drivers
+L_0000000004063150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a470_0 .net8 "VGND", 0 0, L_0000000004063150;  1 drivers, strength-aware
+L_0000000004064030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1bcd0_0 .net8 "VNB", 0 0, L_0000000004064030;  1 drivers, strength-aware
+L_00000000040640a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1b0f0_0 .net8 "VPB", 0 0, L_00000000040640a0;  1 drivers, strength-aware
+L_0000000004062dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c19e30_0 .net8 "VPWR", 0 0, L_0000000004062dd0;  1 drivers, strength-aware
+v0000000003c1a830_0 .net "X", 0 0, L_0000000004159f30;  alias, 1 drivers
+v0000000003c1b230_0 .net "and0_out_X", 0 0, L_0000000004159910;  1 drivers
+v0000000003c1b9b0_0 .net "or0_out", 0 0, L_00000000041594b0;  1 drivers
+S_0000000003c4f100 .scope module, "_0986_" "sky130_fd_sc_hd__o2bb2a_2" 3 3185, 4 85742 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c1a150_0 .net "A1_N", 0 0, L_000000000415a860;  alias, 1 drivers
+v0000000003c1a330_0 .net "A2_N", 0 0, L_0000000004159f30;  alias, 1 drivers
+v0000000003c1a3d0_0 .net "B1", 0 0, L_000000000415a860;  alias, 1 drivers
+v0000000003c1a510_0 .net "B2", 0 0, L_0000000004159f30;  alias, 1 drivers
+L_0000000004064180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a5b0_0 .net8 "VGND", 0 0, L_0000000004064180;  1 drivers, strength-aware
+L_0000000004063e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a650_0 .net8 "VNB", 0 0, L_0000000004063e70;  1 drivers, strength-aware
+L_0000000004064650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1a970_0 .net8 "VPB", 0 0, L_0000000004064650;  1 drivers, strength-aware
+L_0000000004064810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1aa10_0 .net8 "VPWR", 0 0, L_0000000004064810;  1 drivers, strength-aware
+v0000000003c1abf0_0 .net "X", 0 0, L_0000000004159750;  alias, 1 drivers
+S_0000000003c4ef80 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85762, 4 86199 1, S_0000000003c4f100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004159fa0 .functor NAND 1, L_0000000004159f30, L_000000000415a860, C4<1>, C4<1>;
+L_00000000041596e0 .functor OR 1, L_0000000004159f30, L_000000000415a860, C4<0>, C4<0>;
+L_000000000415a780 .functor AND 1, L_0000000004159fa0, L_00000000041596e0, C4<1>, C4<1>;
+L_0000000004159750 .functor BUF 1, L_000000000415a780, C4<0>, C4<0>, C4<0>;
+v0000000003c1bf50_0 .net "A1_N", 0 0, L_000000000415a860;  alias, 1 drivers
+v0000000003c1a6f0_0 .net "A2_N", 0 0, L_0000000004159f30;  alias, 1 drivers
+v0000000003c1c090_0 .net "B1", 0 0, L_000000000415a860;  alias, 1 drivers
+v0000000003c1a290_0 .net "B2", 0 0, L_0000000004159f30;  alias, 1 drivers
+L_0000000004063ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c19930_0 .net8 "VGND", 0 0, L_0000000004063ee0;  1 drivers, strength-aware
+L_00000000040641f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c19ed0_0 .net8 "VNB", 0 0, L_00000000040641f0;  1 drivers, strength-aware
+L_0000000004063af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c199d0_0 .net8 "VPB", 0 0, L_0000000004063af0;  1 drivers, strength-aware
+L_0000000004063cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c19b10_0 .net8 "VPWR", 0 0, L_0000000004063cb0;  1 drivers, strength-aware
+v0000000003c1ab50_0 .net "X", 0 0, L_0000000004159750;  alias, 1 drivers
+v0000000003c19c50_0 .net "and0_out_X", 0 0, L_000000000415a780;  1 drivers
+v0000000003c19bb0_0 .net "nand0_out", 0 0, L_0000000004159fa0;  1 drivers
+v0000000003c19f70_0 .net "or0_out", 0 0, L_00000000041596e0;  1 drivers
+S_0000000003c4bb00 .scope module, "_0987_" "sky130_fd_sc_hd__inv_2" 3 3192, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c1e610_0 .net "A", 0 0, L_0000000004159750;  alias, 1 drivers
+L_0000000004063770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d2b0_0 .net8 "VGND", 0 0, L_0000000004063770;  1 drivers, strength-aware
+L_00000000040634d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ddf0_0 .net8 "VNB", 0 0, L_00000000040634d0;  1 drivers, strength-aware
+L_0000000004063f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1dc10_0 .net8 "VPB", 0 0, L_0000000004063f50;  1 drivers, strength-aware
+L_0000000004062f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1dcb0_0 .net8 "VPWR", 0 0, L_0000000004062f20;  1 drivers, strength-aware
+v0000000003c1d710_0 .net "Y", 0 0, L_0000000004159520;  alias, 1 drivers
+S_0000000003c4da80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4bb00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415a8d0 .functor NOT 1, L_0000000004159750, C4<0>, C4<0>, C4<0>;
+L_0000000004159520 .functor BUF 1, L_000000000415a8d0, C4<0>, C4<0>, C4<0>;
+v0000000003c1ac90_0 .net "A", 0 0, L_0000000004159750;  alias, 1 drivers
+L_0000000004064880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1add0_0 .net8 "VGND", 0 0, L_0000000004064880;  1 drivers, strength-aware
+L_0000000004062cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ae70_0 .net8 "VNB", 0 0, L_0000000004062cf0;  1 drivers, strength-aware
+L_0000000004064260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1afb0_0 .net8 "VPB", 0 0, L_0000000004064260;  1 drivers, strength-aware
+L_0000000004063310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e070_0 .net8 "VPWR", 0 0, L_0000000004063310;  1 drivers, strength-aware
+v0000000003c1da30_0 .net "Y", 0 0, L_0000000004159520;  alias, 1 drivers
+v0000000003c1c4f0_0 .net "not0_out_Y", 0 0, L_000000000415a8d0;  1 drivers
+S_0000000003c4d300 .scope module, "_0988_" "sky130_fd_sc_hd__or3_2" 3 3196, 4 49901 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+v0000000003c1e110_0 .net "A", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c1c810_0 .net "B", 0 0, L_0000000004159520;  alias, 1 drivers
+v0000000003c1d0d0_0 .net "C", 0 0, L_0000000004159c90;  alias, 1 drivers
+L_0000000004063380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1de90_0 .net8 "VGND", 0 0, L_0000000004063380;  1 drivers, strength-aware
+L_0000000004063d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e4d0_0 .net8 "VNB", 0 0, L_0000000004063d20;  1 drivers, strength-aware
+L_0000000004063230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e570_0 .net8 "VPB", 0 0, L_0000000004063230;  1 drivers, strength-aware
+L_00000000040637e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d7b0_0 .net8 "VPWR", 0 0, L_00000000040637e0;  1 drivers, strength-aware
+v0000000003c1dfd0_0 .net "X", 0 0, L_000000000415a0f0;  alias, 1 drivers
+S_0000000003c50900 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_0000000003c4d300;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004159a60 .functor OR 1, L_0000000004159520, L_00000000041593d0, L_0000000004159c90, C4<0>;
+L_000000000415a0f0 .functor BUF 1, L_0000000004159a60, C4<0>, C4<0>, C4<0>;
+v0000000003c1ce50_0 .net "A", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c1e1b0_0 .net "B", 0 0, L_0000000004159520;  alias, 1 drivers
+v0000000003c1dd50_0 .net "C", 0 0, L_0000000004159c90;  alias, 1 drivers
+L_00000000040633f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1dad0_0 .net8 "VGND", 0 0, L_00000000040633f0;  1 drivers, strength-aware
+L_0000000004063460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d030_0 .net8 "VNB", 0 0, L_0000000004063460;  1 drivers, strength-aware
+L_0000000004063fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1cf90_0 .net8 "VPB", 0 0, L_0000000004063fc0;  1 drivers, strength-aware
+L_00000000040642d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d670_0 .net8 "VPWR", 0 0, L_00000000040642d0;  1 drivers, strength-aware
+v0000000003c1d5d0_0 .net "X", 0 0, L_000000000415a0f0;  alias, 1 drivers
+v0000000003c1c130_0 .net "or0_out_X", 0 0, L_0000000004159a60;  1 drivers
+S_0000000003c50a80 .scope module, "_0989_" "sky130_fd_sc_hd__o21a_2" 3 3202, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c1e390_0 .net "A1", 0 0, L_0000000004159e50;  alias, 1 drivers
+v0000000003c1db70_0 .net "A2", 0 0, L_0000000004159750;  alias, 1 drivers
+v0000000003c1cc70_0 .net "B1", 0 0, L_000000000415a0f0;  alias, 1 drivers
+L_0000000004063850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e430_0 .net8 "VGND", 0 0, L_0000000004063850;  1 drivers, strength-aware
+L_00000000040638c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1c9f0_0 .net8 "VNB", 0 0, L_00000000040638c0;  1 drivers, strength-aware
+L_0000000004062d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1df30_0 .net8 "VPB", 0 0, L_0000000004062d60;  1 drivers, strength-aware
+L_0000000004063930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1c270_0 .net8 "VPWR", 0 0, L_0000000004063930;  1 drivers, strength-aware
+v0000000003c1d530_0 .net "X", 0 0, L_000000000415be40;  alias, 1 drivers
+S_0000000003c4e500 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003c50a80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415aa90 .functor OR 1, L_0000000004159750, L_0000000004159e50, C4<0>, C4<0>;
+L_000000000415ad30 .functor AND 1, L_000000000415aa90, L_000000000415a0f0, C4<1>, C4<1>;
+L_000000000415be40 .functor BUF 1, L_000000000415ad30, C4<0>, C4<0>, C4<0>;
+v0000000003c1d170_0 .net "A1", 0 0, L_0000000004159e50;  alias, 1 drivers
+v0000000003c1e250_0 .net "A2", 0 0, L_0000000004159750;  alias, 1 drivers
+v0000000003c1e6b0_0 .net "B1", 0 0, L_000000000415a0f0;  alias, 1 drivers
+L_0000000004063540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e2f0_0 .net8 "VGND", 0 0, L_0000000004063540;  1 drivers, strength-aware
+L_0000000004063d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e750_0 .net8 "VNB", 0 0, L_0000000004063d90;  1 drivers, strength-aware
+L_0000000004062e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1c590_0 .net8 "VPB", 0 0, L_0000000004062e40;  1 drivers, strength-aware
+L_0000000004063620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e7f0_0 .net8 "VPWR", 0 0, L_0000000004063620;  1 drivers, strength-aware
+v0000000003c1e890_0 .net "X", 0 0, L_000000000415be40;  alias, 1 drivers
+v0000000003c1d210_0 .net "and0_out_X", 0 0, L_000000000415ad30;  1 drivers
+v0000000003c1c1d0_0 .net "or0_out", 0 0, L_000000000415aa90;  1 drivers
+S_0000000003c4f400 .scope module, "_0990_" "sky130_fd_sc_hd__nor2_2" 3 3208, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c1c3b0_0 .net "A", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003c1c950_0 .net "B", 0 0, L_00000000041394b0;  alias, 1 drivers
+L_0000000004062f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1c450_0 .net8 "VGND", 0 0, L_0000000004062f90;  1 drivers, strength-aware
+L_00000000040635b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ca90_0 .net8 "VNB", 0 0, L_00000000040635b0;  1 drivers, strength-aware
+L_00000000040639a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d3f0_0 .net8 "VPB", 0 0, L_00000000040639a0;  1 drivers, strength-aware
+L_0000000004063a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1c770_0 .net8 "VPWR", 0 0, L_0000000004063a80;  1 drivers, strength-aware
+v0000000003c1d990_0 .net "Y", 0 0, L_000000000415b430;  alias, 1 drivers
+S_0000000003c4b800 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c4f400;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415b3c0 .functor NOR 1, L_0000000004138870, L_00000000041394b0, C4<0>, C4<0>;
+L_000000000415b430 .functor BUF 1, L_000000000415b3c0, C4<0>, C4<0>, C4<0>;
+v0000000003c1c630_0 .net "A", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003c1c6d0_0 .net "B", 0 0, L_00000000041394b0;  alias, 1 drivers
+L_0000000004063e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d8f0_0 .net8 "VGND", 0 0, L_0000000004063e00;  1 drivers, strength-aware
+L_0000000004064340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d490_0 .net8 "VNB", 0 0, L_0000000004064340;  1 drivers, strength-aware
+L_00000000040643b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d350_0 .net8 "VPB", 0 0, L_00000000040643b0;  1 drivers, strength-aware
+L_0000000004064490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1d850_0 .net8 "VPWR", 0 0, L_0000000004064490;  1 drivers, strength-aware
+v0000000003c1c310_0 .net "Y", 0 0, L_000000000415b430;  alias, 1 drivers
+v0000000003c1c8b0_0 .net "nor0_out_Y", 0 0, L_000000000415b3c0;  1 drivers
+S_0000000003c4d600 .scope module, "_0991_" "sky130_fd_sc_hd__inv_2" 3 3213, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c204b0_0 .net "A", 0 0, L_000000000415a320;  alias, 1 drivers
+L_0000000004064500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c20c30_0 .net8 "VGND", 0 0, L_0000000004064500;  1 drivers, strength-aware
+L_0000000004064570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c20ff0_0 .net8 "VNB", 0 0, L_0000000004064570;  1 drivers, strength-aware
+L_0000000004064ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f790_0 .net8 "VPB", 0 0, L_0000000004064ea0;  1 drivers, strength-aware
+L_0000000004064ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21090_0 .net8 "VPWR", 0 0, L_0000000004064ab0;  1 drivers, strength-aware
+v0000000003c20d70_0 .net "Y", 0 0, L_000000000415b4a0;  alias, 1 drivers
+S_0000000003c50780 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4d600;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415c460 .functor NOT 1, L_000000000415a320, C4<0>, C4<0>, C4<0>;
+L_000000000415b4a0 .functor BUF 1, L_000000000415c460, C4<0>, C4<0>, C4<0>;
+v0000000003c1cd10_0 .net "A", 0 0, L_000000000415a320;  alias, 1 drivers
+L_00000000040649d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1cb30_0 .net8 "VGND", 0 0, L_00000000040649d0;  1 drivers, strength-aware
+L_0000000004064f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1cbd0_0 .net8 "VNB", 0 0, L_0000000004064f80;  1 drivers, strength-aware
+L_0000000004064ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1cdb0_0 .net8 "VPB", 0 0, L_0000000004064ce0;  1 drivers, strength-aware
+L_0000000004064f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1cef0_0 .net8 "VPWR", 0 0, L_0000000004064f10;  1 drivers, strength-aware
+v0000000003c1e930_0 .net "Y", 0 0, L_000000000415b4a0;  alias, 1 drivers
+v0000000003c205f0_0 .net "not0_out_Y", 0 0, L_000000000415c460;  1 drivers
+S_0000000003c4b080 .scope module, "_0992_" "sky130_fd_sc_hd__o21a_2" 3 3217, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c20190_0 .net "A1", 0 0, L_0000000004128a40;  alias, 1 drivers
+v0000000003c1fdd0_0 .net "A2", 0 0, L_0000000004159980;  alias, 1 drivers
+v0000000003c209b0_0 .net "B1", 0 0, L_0000000004128810;  alias, 1 drivers
+L_0000000004064c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ebb0_0 .net8 "VGND", 0 0, L_0000000004064c00;  1 drivers, strength-aware
+L_00000000040648f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f5b0_0 .net8 "VNB", 0 0, L_00000000040648f0;  1 drivers, strength-aware
+L_0000000004064b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c20b90_0 .net8 "VPB", 0 0, L_0000000004064b20;  1 drivers, strength-aware
+L_0000000004064a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f970_0 .net8 "VPWR", 0 0, L_0000000004064a40;  1 drivers, strength-aware
+v0000000003c202d0_0 .net "X", 0 0, L_000000000415bb30;  alias, 1 drivers
+S_0000000003c4f280 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003c4b080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415b900 .functor OR 1, L_0000000004159980, L_0000000004128a40, C4<0>, C4<0>;
+L_000000000415bac0 .functor AND 1, L_000000000415b900, L_0000000004128810, C4<1>, C4<1>;
+L_000000000415bb30 .functor BUF 1, L_000000000415bac0, C4<0>, C4<0>, C4<0>;
+v0000000003c1f830_0 .net "A1", 0 0, L_0000000004128a40;  alias, 1 drivers
+v0000000003c1f8d0_0 .net "A2", 0 0, L_0000000004159980;  alias, 1 drivers
+v0000000003c1ed90_0 .net "B1", 0 0, L_0000000004128810;  alias, 1 drivers
+L_0000000004064b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ec50_0 .net8 "VGND", 0 0, L_0000000004064b90;  1 drivers, strength-aware
+L_0000000004064960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c20230_0 .net8 "VNB", 0 0, L_0000000004064960;  1 drivers, strength-aware
+L_0000000004064c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f510_0 .net8 "VPB", 0 0, L_0000000004064c70;  1 drivers, strength-aware
+L_0000000004064d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ecf0_0 .net8 "VPWR", 0 0, L_0000000004064d50;  1 drivers, strength-aware
+v0000000003c20870_0 .net "X", 0 0, L_000000000415bb30;  alias, 1 drivers
+v0000000003c1f010_0 .net "and0_out_X", 0 0, L_000000000415bac0;  1 drivers
+v0000000003c1ee30_0 .net "or0_out", 0 0, L_000000000415b900;  1 drivers
+S_0000000003c50000 .scope module, "_0993_" "sky130_fd_sc_hd__o21ai_2" 3 3223, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c207d0_0 .net "A1", 0 0, L_000000000413f330;  alias, 1 drivers
+v0000000003c20730_0 .net "A2", 0 0, L_0000000004142890;  alias, 1 drivers
+v0000000003c1ff10_0 .net "B1", 0 0, L_0000000004124c20;  alias, 1 drivers
+L_0000000004064dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1fd30_0 .net8 "VGND", 0 0, L_0000000004064dc0;  1 drivers, strength-aware
+L_0000000004064e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c20f50_0 .net8 "VNB", 0 0, L_0000000004064e30;  1 drivers, strength-aware
+L_00000000040450f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1fab0_0 .net8 "VPB", 0 0, L_00000000040450f0;  1 drivers, strength-aware
+L_0000000004045160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1e9d0_0 .net8 "VPWR", 0 0, L_0000000004045160;  1 drivers, strength-aware
+v0000000003c1ef70_0 .net "Y", 0 0, L_000000000415ba50;  alias, 1 drivers
+S_0000000003c4dd80 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c50000;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415b890 .functor OR 1, L_0000000004142890, L_000000000413f330, C4<0>, C4<0>;
+L_000000000415bf20 .functor NAND 1, L_0000000004124c20, L_000000000415b890, C4<1>, C4<1>;
+L_000000000415ba50 .functor BUF 1, L_000000000415bf20, C4<0>, C4<0>, C4<0>;
+v0000000003c20550_0 .net "A1", 0 0, L_000000000413f330;  alias, 1 drivers
+v0000000003c1fe70_0 .net "A2", 0 0, L_0000000004142890;  alias, 1 drivers
+v0000000003c20e10_0 .net "B1", 0 0, L_0000000004124c20;  alias, 1 drivers
+L_0000000004046510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f470_0 .net8 "VGND", 0 0, L_0000000004046510;  1 drivers, strength-aware
+L_00000000040455c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c20eb0_0 .net8 "VNB", 0 0, L_00000000040455c0;  1 drivers, strength-aware
+L_0000000004045e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1eed0_0 .net8 "VPB", 0 0, L_0000000004045e80;  1 drivers, strength-aware
+L_0000000004046270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c20a50_0 .net8 "VPWR", 0 0, L_0000000004046270;  1 drivers, strength-aware
+v0000000003c20cd0_0 .net "Y", 0 0, L_000000000415ba50;  alias, 1 drivers
+v0000000003c20370_0 .net "nand0_out_Y", 0 0, L_000000000415bf20;  1 drivers
+v0000000003c20690_0 .net "or0_out", 0 0, L_000000000415b890;  1 drivers
+S_0000000003c4eb00 .scope module, "_0994_" "sky130_fd_sc_hd__a31oi_2" 3 3229, 4 72663 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+v0000000003c1f290_0 .net "A1", 0 0, L_00000000041239c0;  alias, 1 drivers
+v0000000003c1fb50_0 .net "A2", 0 0, L_000000000415a400;  alias, 1 drivers
+v0000000003c1fc90_0 .net "A3", 0 0, L_000000000415ba50;  alias, 1 drivers
+v0000000003c1f330_0 .net "B1", 0 0, L_000000000415a5c0;  alias, 1 drivers
+L_00000000040463c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ffb0_0 .net8 "VGND", 0 0, L_00000000040463c0;  1 drivers, strength-aware
+L_0000000004045240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f3d0_0 .net8 "VNB", 0 0, L_0000000004045240;  1 drivers, strength-aware
+L_00000000040458d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f6f0_0 .net8 "VPB", 0 0, L_00000000040458d0;  1 drivers, strength-aware
+L_0000000004045390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c20050_0 .net8 "VPWR", 0 0, L_0000000004045390;  1 drivers, strength-aware
+v0000000003c200f0_0 .net "Y", 0 0, L_000000000415af60;  alias, 1 drivers
+S_0000000003c4e800 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72683, 4 72538 1, S_0000000003c4eb00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_000000000415b120 .functor AND 1, L_000000000415ba50, L_00000000041239c0, L_000000000415a400, C4<1>;
+L_000000000415c4d0 .functor NOR 1, L_000000000415a5c0, L_000000000415b120, C4<0>, C4<0>;
+L_000000000415af60 .functor BUF 1, L_000000000415c4d0, C4<0>, C4<0>, C4<0>;
+v0000000003c1fa10_0 .net "A1", 0 0, L_00000000041239c0;  alias, 1 drivers
+v0000000003c20910_0 .net "A2", 0 0, L_000000000415a400;  alias, 1 drivers
+v0000000003c1fbf0_0 .net "A3", 0 0, L_000000000415ba50;  alias, 1 drivers
+v0000000003c20af0_0 .net "B1", 0 0, L_000000000415a5c0;  alias, 1 drivers
+L_00000000040459b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1eb10_0 .net8 "VGND", 0 0, L_00000000040459b0;  1 drivers, strength-aware
+L_0000000004046040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c1ea70_0 .net8 "VNB", 0 0, L_0000000004046040;  1 drivers, strength-aware
+L_0000000004045e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f0b0_0 .net8 "VPB", 0 0, L_0000000004045e10;  1 drivers, strength-aware
+L_0000000004045a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c1f150_0 .net8 "VPWR", 0 0, L_0000000004045a20;  1 drivers, strength-aware
+v0000000003c1f1f0_0 .net "Y", 0 0, L_000000000415af60;  alias, 1 drivers
+v0000000003c20410_0 .net "and0_out", 0 0, L_000000000415b120;  1 drivers
+v0000000003c1f650_0 .net "nor0_out_Y", 0 0, L_000000000415c4d0;  1 drivers
+S_0000000003c4f580 .scope module, "_0995_" "sky130_fd_sc_hd__nor2_2" 3 3236, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c236b0_0 .net "A", 0 0, L_0000000004139750;  alias, 1 drivers
+v0000000003c22530_0 .net "B", 0 0, L_000000000412ea80;  alias, 1 drivers
+L_0000000004045d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c21130_0 .net8 "VGND", 0 0, L_0000000004045d30;  1 drivers, strength-aware
+L_0000000004045400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c21d10_0 .net8 "VNB", 0 0, L_0000000004045400;  1 drivers, strength-aware
+L_00000000040462e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c22670_0 .net8 "VPB", 0 0, L_00000000040462e0;  1 drivers, strength-aware
+L_00000000040460b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c23750_0 .net8 "VPWR", 0 0, L_00000000040460b0;  1 drivers, strength-aware
+v0000000003c22170_0 .net "Y", 0 0, L_000000000415bba0;  alias, 1 drivers
+S_0000000003c4c400 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c4f580;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415acc0 .functor NOR 1, L_0000000004139750, L_000000000412ea80, C4<0>, C4<0>;
+L_000000000415bba0 .functor BUF 1, L_000000000415acc0, C4<0>, C4<0>, C4<0>;
+v0000000003c22fd0_0 .net "A", 0 0, L_0000000004139750;  alias, 1 drivers
+v0000000003c21db0_0 .net "B", 0 0, L_000000000412ea80;  alias, 1 drivers
+L_00000000040466d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c22f30_0 .net8 "VGND", 0 0, L_00000000040466d0;  1 drivers, strength-aware
+L_0000000004046580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23610_0 .net8 "VNB", 0 0, L_0000000004046580;  1 drivers, strength-aware
+L_0000000004046350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21b30_0 .net8 "VPB", 0 0, L_0000000004046350;  1 drivers, strength-aware
+L_0000000004046ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c22990_0 .net8 "VPWR", 0 0, L_0000000004046ba0;  1 drivers, strength-aware
+v0000000003c22490_0 .net "Y", 0 0, L_000000000415bba0;  alias, 1 drivers
+v0000000003c220d0_0 .net "nor0_out_Y", 0 0, L_000000000415acc0;  1 drivers
+S_0000000003c4be00 .scope module, "_0996_" "sky130_fd_sc_hd__o32a_2" 3 3241, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003c22c10_0 .net "A1", 0 0, L_000000000415b4a0;  alias, 1 drivers
+v0000000003c211d0_0 .net "A2", 0 0, L_000000000415bb30;  alias, 1 drivers
+v0000000003c22b70_0 .net "A3", 0 0, L_000000000415af60;  alias, 1 drivers
+v0000000003c223f0_0 .net "B1", 0 0, L_00000000041295a0;  alias, 1 drivers
+v0000000003c22a30_0 .net "B2", 0 0, L_000000000415bba0;  alias, 1 drivers
+L_0000000004046b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23070_0 .net8 "VGND", 0 0, L_0000000004046b30;  1 drivers, strength-aware
+L_00000000040464a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c21310_0 .net8 "VNB", 0 0, L_00000000040464a0;  1 drivers, strength-aware
+L_0000000004046430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21270_0 .net8 "VPB", 0 0, L_0000000004046430;  1 drivers, strength-aware
+L_00000000040467b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c23110_0 .net8 "VPWR", 0 0, L_00000000040467b0;  1 drivers, strength-aware
+v0000000003c231b0_0 .net "X", 0 0, L_000000000415b970;  alias, 1 drivers
+S_0000000003c50480 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003c4be00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_000000000415c310 .functor OR 1, L_000000000415bb30, L_000000000415b4a0, L_000000000415af60, C4<0>;
+L_000000000415c070 .functor OR 1, L_000000000415bba0, L_00000000041295a0, C4<0>, C4<0>;
+L_000000000415b190 .functor AND 1, L_000000000415c310, L_000000000415c070, C4<1>, C4<1>;
+L_000000000415b970 .functor BUF 1, L_000000000415b190, C4<0>, C4<0>, C4<0>;
+v0000000003c22cb0_0 .net "A1", 0 0, L_000000000415b4a0;  alias, 1 drivers
+v0000000003c219f0_0 .net "A2", 0 0, L_000000000415bb30;  alias, 1 drivers
+v0000000003c22d50_0 .net "A3", 0 0, L_000000000415af60;  alias, 1 drivers
+v0000000003c22df0_0 .net "B1", 0 0, L_00000000041295a0;  alias, 1 drivers
+v0000000003c225d0_0 .net "B2", 0 0, L_000000000415bba0;  alias, 1 drivers
+L_0000000004046200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c22710_0 .net8 "VGND", 0 0, L_0000000004046200;  1 drivers, strength-aware
+L_0000000004045b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c237f0_0 .net8 "VNB", 0 0, L_0000000004045b70;  1 drivers, strength-aware
+L_0000000004045630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c22ad0_0 .net8 "VPB", 0 0, L_0000000004045630;  1 drivers, strength-aware
+L_0000000004046970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c22e90_0 .net8 "VPWR", 0 0, L_0000000004046970;  1 drivers, strength-aware
+v0000000003c216d0_0 .net "X", 0 0, L_000000000415b970;  alias, 1 drivers
+v0000000003c22210_0 .net "and0_out_X", 0 0, L_000000000415b190;  1 drivers
+v0000000003c23890_0 .net "or0_out", 0 0, L_000000000415c310;  1 drivers
+v0000000003c23390_0 .net "or1_out", 0 0, L_000000000415c070;  1 drivers
+S_0000000003c4dc00 .scope module, "_0997_" "sky130_fd_sc_hd__inv_2" 3 3249, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c21450_0 .net "A", 0 0, L_000000000415b970;  alias, 1 drivers
+L_0000000004045470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23430_0 .net8 "VGND", 0 0, L_0000000004045470;  1 drivers, strength-aware
+L_00000000040465f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c21a90_0 .net8 "VNB", 0 0, L_00000000040465f0;  1 drivers, strength-aware
+L_0000000004045940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c22350_0 .net8 "VPB", 0 0, L_0000000004045940;  1 drivers, strength-aware
+L_0000000004046120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21590_0 .net8 "VPWR", 0 0, L_0000000004046120;  1 drivers, strength-aware
+v0000000003c214f0_0 .net "Y", 0 0, L_000000000415b7b0;  alias, 1 drivers
+S_0000000003c4f880 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4dc00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415c3f0 .functor NOT 1, L_000000000415b970, C4<0>, C4<0>, C4<0>;
+L_000000000415b7b0 .functor BUF 1, L_000000000415c3f0, C4<0>, C4<0>, C4<0>;
+v0000000003c23570_0 .net "A", 0 0, L_000000000415b970;  alias, 1 drivers
+L_00000000040469e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c234d0_0 .net8 "VGND", 0 0, L_00000000040469e0;  1 drivers, strength-aware
+L_0000000004046660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23250_0 .net8 "VNB", 0 0, L_0000000004046660;  1 drivers, strength-aware
+L_0000000004046740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c213b0_0 .net8 "VPB", 0 0, L_0000000004046740;  1 drivers, strength-aware
+L_0000000004046900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c222b0_0 .net8 "VPWR", 0 0, L_0000000004046900;  1 drivers, strength-aware
+v0000000003c232f0_0 .net "Y", 0 0, L_000000000415b7b0;  alias, 1 drivers
+v0000000003c218b0_0 .net "not0_out_Y", 0 0, L_000000000415c3f0;  1 drivers
+S_0000000003c4b500 .scope module, "_0998_" "sky130_fd_sc_hd__a2bb2o_2" 3 3253, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c228f0_0 .net "A1_N", 0 0, L_000000000415b430;  alias, 1 drivers
+v0000000003c26090_0 .net "A2_N", 0 0, L_000000000415b7b0;  alias, 1 drivers
+v0000000003c25cd0_0 .net "B1", 0 0, L_000000000415b430;  alias, 1 drivers
+v0000000003c246f0_0 .net "B2", 0 0, L_000000000415b7b0;  alias, 1 drivers
+L_0000000004046820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23930_0 .net8 "VGND", 0 0, L_0000000004046820;  1 drivers, strength-aware
+L_0000000004045a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24470_0 .net8 "VNB", 0 0, L_0000000004045a90;  1 drivers, strength-aware
+L_0000000004045c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c257d0_0 .net8 "VPB", 0 0, L_0000000004045c50;  1 drivers, strength-aware
+L_0000000004045ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25550_0 .net8 "VPWR", 0 0, L_0000000004045ef0;  1 drivers, strength-aware
+v0000000003c24f10_0 .net "X", 0 0, L_000000000415b040;  alias, 1 drivers
+S_0000000003c4d780 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003c4b500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000415bc10 .functor AND 1, L_000000000415b430, L_000000000415b7b0, C4<1>, C4<1>;
+L_000000000415ae10 .functor NOR 1, L_000000000415b430, L_000000000415b7b0, C4<0>, C4<0>;
+L_000000000415ab00 .functor OR 1, L_000000000415ae10, L_000000000415bc10, C4<0>, C4<0>;
+L_000000000415b040 .functor BUF 1, L_000000000415ab00, C4<0>, C4<0>, C4<0>;
+v0000000003c22030_0 .net "A1_N", 0 0, L_000000000415b430;  alias, 1 drivers
+v0000000003c21630_0 .net "A2_N", 0 0, L_000000000415b7b0;  alias, 1 drivers
+v0000000003c21770_0 .net "B1", 0 0, L_000000000415b430;  alias, 1 drivers
+v0000000003c21810_0 .net "B2", 0 0, L_000000000415b7b0;  alias, 1 drivers
+L_0000000004046890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c21950_0 .net8 "VGND", 0 0, L_0000000004046890;  1 drivers, strength-aware
+L_0000000004046ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c227b0_0 .net8 "VNB", 0 0, L_0000000004046ac0;  1 drivers, strength-aware
+L_00000000040456a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21bd0_0 .net8 "VPB", 0 0, L_00000000040456a0;  1 drivers, strength-aware
+L_0000000004045cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c21c70_0 .net8 "VPWR", 0 0, L_0000000004045cc0;  1 drivers, strength-aware
+v0000000003c21e50_0 .net "X", 0 0, L_000000000415b040;  alias, 1 drivers
+v0000000003c21ef0_0 .net "and0_out", 0 0, L_000000000415bc10;  1 drivers
+v0000000003c21f90_0 .net "nor0_out", 0 0, L_000000000415ae10;  1 drivers
+v0000000003c22850_0 .net "or0_out_X", 0 0, L_000000000415ab00;  1 drivers
+S_0000000003c50600 .scope module, "_0999_" "sky130_fd_sc_hd__or2_2" 3 3260, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c23f70_0 .net "A", 0 0, L_000000000415a0f0;  alias, 1 drivers
+v0000000003c25690_0 .net "B", 0 0, L_000000000415b040;  alias, 1 drivers
+L_0000000004046a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25d70_0 .net8 "VGND", 0 0, L_0000000004046a50;  1 drivers, strength-aware
+L_0000000004046c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c252d0_0 .net8 "VNB", 0 0, L_0000000004046c10;  1 drivers, strength-aware
+L_0000000004046c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25370_0 .net8 "VPB", 0 0, L_0000000004046c80;  1 drivers, strength-aware
+L_0000000004045b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25a50_0 .net8 "VPWR", 0 0, L_0000000004045b00;  1 drivers, strength-aware
+v0000000003c23c50_0 .net "X", 0 0, L_000000000415bc80;  alias, 1 drivers
+S_0000000003c4d900 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c50600;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415b510 .functor OR 1, L_000000000415b040, L_000000000415a0f0, C4<0>, C4<0>;
+L_000000000415bc80 .functor BUF 1, L_000000000415b510, C4<0>, C4<0>, C4<0>;
+v0000000003c25190_0 .net "A", 0 0, L_000000000415a0f0;  alias, 1 drivers
+v0000000003c25870_0 .net "B", 0 0, L_000000000415b040;  alias, 1 drivers
+L_00000000040451d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24010_0 .net8 "VGND", 0 0, L_00000000040451d0;  1 drivers, strength-aware
+L_0000000004045f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24790_0 .net8 "VNB", 0 0, L_0000000004045f60;  1 drivers, strength-aware
+L_00000000040452b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25910_0 .net8 "VPB", 0 0, L_00000000040452b0;  1 drivers, strength-aware
+L_0000000004045fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24bf0_0 .net8 "VPWR", 0 0, L_0000000004045fd0;  1 drivers, strength-aware
+v0000000003c24c90_0 .net "X", 0 0, L_000000000415bc80;  alias, 1 drivers
+v0000000003c259b0_0 .net "or0_out_X", 0 0, L_000000000415b510;  1 drivers
+S_0000000003c50c00 .scope module, "_1000_" "sky130_fd_sc_hd__inv_2" 3 3265, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c24150_0 .net "A", 0 0, L_000000000415bc80;  alias, 1 drivers
+L_0000000004045be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24830_0 .net8 "VGND", 0 0, L_0000000004045be0;  1 drivers, strength-aware
+L_0000000004045da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25730_0 .net8 "VNB", 0 0, L_0000000004045da0;  1 drivers, strength-aware
+L_00000000040454e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24d30_0 .net8 "VPB", 0 0, L_00000000040454e0;  1 drivers, strength-aware
+L_0000000004045320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25b90_0 .net8 "VPWR", 0 0, L_0000000004045320;  1 drivers, strength-aware
+v0000000003c248d0_0 .net "Y", 0 0, L_000000000415ae80;  alias, 1 drivers
+S_0000000003c4b680 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c50c00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415ab70 .functor NOT 1, L_000000000415bc80, C4<0>, C4<0>, C4<0>;
+L_000000000415ae80 .functor BUF 1, L_000000000415ab70, C4<0>, C4<0>, C4<0>;
+v0000000003c239d0_0 .net "A", 0 0, L_000000000415bc80;  alias, 1 drivers
+L_0000000004046190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25230_0 .net8 "VGND", 0 0, L_0000000004046190;  1 drivers, strength-aware
+L_0000000004045550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25af0_0 .net8 "VNB", 0 0, L_0000000004045550;  1 drivers, strength-aware
+L_0000000004045710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c23bb0_0 .net8 "VPB", 0 0, L_0000000004045710;  1 drivers, strength-aware
+L_0000000004045780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c23cf0_0 .net8 "VPWR", 0 0, L_0000000004045780;  1 drivers, strength-aware
+v0000000003c25410_0 .net "Y", 0 0, L_000000000415ae80;  alias, 1 drivers
+v0000000003c240b0_0 .net "not0_out_Y", 0 0, L_000000000415ab70;  1 drivers
+S_0000000003c4d480 .scope module, "_1001_" "sky130_fd_sc_hd__a21oi_2" 3 3269, 4 51903 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c25eb0_0 .net "A1", 0 0, L_000000000415a0f0;  alias, 1 drivers
+v0000000003c254b0_0 .net "A2", 0 0, L_000000000415b040;  alias, 1 drivers
+v0000000003c24970_0 .net "B1", 0 0, L_000000000415ae80;  alias, 1 drivers
+L_00000000040457f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25c30_0 .net8 "VGND", 0 0, L_00000000040457f0;  1 drivers, strength-aware
+L_0000000004045860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23d90_0 .net8 "VNB", 0 0, L_0000000004045860;  1 drivers, strength-aware
+L_0000000004079770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24510_0 .net8 "VPB", 0 0, L_0000000004079770;  1 drivers, strength-aware
+L_0000000004079690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24a10_0 .net8 "VPWR", 0 0, L_0000000004079690;  1 drivers, strength-aware
+v0000000003c255f0_0 .net "Y", 0 0, L_000000000415ac50;  alias, 1 drivers
+S_0000000003c4cd00 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_0000000003c4d480;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415b200 .functor AND 1, L_000000000415a0f0, L_000000000415b040, C4<1>, C4<1>;
+L_000000000415abe0 .functor NOR 1, L_000000000415ae80, L_000000000415b200, C4<0>, C4<0>;
+L_000000000415ac50 .functor BUF 1, L_000000000415abe0, C4<0>, C4<0>, C4<0>;
+v0000000003c25f50_0 .net "A1", 0 0, L_000000000415a0f0;  alias, 1 drivers
+v0000000003c24650_0 .net "A2", 0 0, L_000000000415b040;  alias, 1 drivers
+v0000000003c25e10_0 .net "B1", 0 0, L_000000000415ae80;  alias, 1 drivers
+L_000000000407a340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24ab0_0 .net8 "VGND", 0 0, L_000000000407a340;  1 drivers, strength-aware
+L_0000000004079540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c25ff0_0 .net8 "VNB", 0 0, L_0000000004079540;  1 drivers, strength-aware
+L_0000000004079f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24b50_0 .net8 "VPB", 0 0, L_0000000004079f50;  1 drivers, strength-aware
+L_0000000004079fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c24dd0_0 .net8 "VPWR", 0 0, L_0000000004079fc0;  1 drivers, strength-aware
+v0000000003c241f0_0 .net "Y", 0 0, L_000000000415ac50;  alias, 1 drivers
+v0000000003c24fb0_0 .net "and0_out", 0 0, L_000000000415b200;  1 drivers
+v0000000003c23a70_0 .net "nor0_out_Y", 0 0, L_000000000415abe0;  1 drivers
+S_0000000003c4b980 .scope module, "_1002_" "sky130_fd_sc_hd__inv_2" 3 3275, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c24330_0 .net "A", 0 0, L_0000000004139520;  alias, 1 drivers
+L_0000000004079620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c243d0_0 .net8 "VGND", 0 0, L_0000000004079620;  1 drivers, strength-aware
+L_00000000040794d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c245b0_0 .net8 "VNB", 0 0, L_00000000040794d0;  1 drivers, strength-aware
+L_000000000407a260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c27490_0 .net8 "VPB", 0 0, L_000000000407a260;  1 drivers, strength-aware
+L_000000000407a490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c270d0_0 .net8 "VPWR", 0 0, L_000000000407a490;  1 drivers, strength-aware
+v0000000003c28250_0 .net "Y", 0 0, L_000000000415bcf0;  alias, 1 drivers
+S_0000000003c4bc80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4b980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415c000 .functor NOT 1, L_0000000004139520, C4<0>, C4<0>, C4<0>;
+L_000000000415bcf0 .functor BUF 1, L_000000000415c000, C4<0>, C4<0>, C4<0>;
+v0000000003c23b10_0 .net "A", 0 0, L_0000000004139520;  alias, 1 drivers
+L_000000000407a880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c24e70_0 .net8 "VGND", 0 0, L_000000000407a880;  1 drivers, strength-aware
+L_0000000004079e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c23e30_0 .net8 "VNB", 0 0, L_0000000004079e00;  1 drivers, strength-aware
+L_000000000407a3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c25050_0 .net8 "VPB", 0 0, L_000000000407a3b0;  1 drivers, strength-aware
+L_00000000040795b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c23ed0_0 .net8 "VPWR", 0 0, L_00000000040795b0;  1 drivers, strength-aware
+v0000000003c250f0_0 .net "Y", 0 0, L_000000000415bcf0;  alias, 1 drivers
+v0000000003c24290_0 .net "not0_out_Y", 0 0, L_000000000415c000;  1 drivers
+S_0000000003c4e080 .scope module, "_1003_" "sky130_fd_sc_hd__inv_2" 3 3279, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c26590_0 .net "A", 0 0, L_0000000004139280;  alias, 1 drivers
+L_00000000040793f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27e90_0 .net8 "VGND", 0 0, L_00000000040793f0;  1 drivers, strength-aware
+L_000000000407a2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27530_0 .net8 "VNB", 0 0, L_000000000407a2d0;  1 drivers, strength-aware
+L_0000000004078f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c26630_0 .net8 "VPB", 0 0, L_0000000004078f20;  1 drivers, strength-aware
+L_0000000004079850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c27210_0 .net8 "VPWR", 0 0, L_0000000004079850;  1 drivers, strength-aware
+v0000000003c26c70_0 .net "Y", 0 0, L_000000000415bf90;  alias, 1 drivers
+S_0000000003c4fa00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4e080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415b580 .functor NOT 1, L_0000000004139280, C4<0>, C4<0>, C4<0>;
+L_000000000415bf90 .functor BUF 1, L_000000000415b580, C4<0>, C4<0>, C4<0>;
+v0000000003c26f90_0 .net "A", 0 0, L_0000000004139280;  alias, 1 drivers
+L_000000000407a500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27170_0 .net8 "VGND", 0 0, L_000000000407a500;  1 drivers, strength-aware
+L_0000000004079700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c28610_0 .net8 "VNB", 0 0, L_0000000004079700;  1 drivers, strength-aware
+L_00000000040797e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c266d0_0 .net8 "VPB", 0 0, L_00000000040797e0;  1 drivers, strength-aware
+L_0000000004079e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c281b0_0 .net8 "VPWR", 0 0, L_0000000004079e70;  1 drivers, strength-aware
+v0000000003c26310_0 .net "Y", 0 0, L_000000000415bf90;  alias, 1 drivers
+v0000000003c273f0_0 .net "not0_out_Y", 0 0, L_000000000415b580;  1 drivers
+S_0000000003c50d80 .scope module, "_1004_" "sky130_fd_sc_hd__nor2_2" 3 3283, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c28890_0 .net "A", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c28570_0 .net "B", 0 0, L_000000000415bcf0;  alias, 1 drivers
+L_00000000040791c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27ad0_0 .net8 "VGND", 0 0, L_00000000040791c0;  1 drivers, strength-aware
+L_000000000407a810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c261d0_0 .net8 "VNB", 0 0, L_000000000407a810;  1 drivers, strength-aware
+L_0000000004078f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28110_0 .net8 "VPB", 0 0, L_0000000004078f90;  1 drivers, strength-aware
+L_0000000004078cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c27a30_0 .net8 "VPWR", 0 0, L_0000000004078cf0;  1 drivers, strength-aware
+v0000000003c27b70_0 .net "Y", 0 0, L_000000000415aef0;  alias, 1 drivers
+S_0000000003c50f00 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c50d80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415ada0 .functor NOR 1, L_00000000041298b0, L_000000000415bcf0, C4<0>, C4<0>;
+L_000000000415aef0 .functor BUF 1, L_000000000415ada0, C4<0>, C4<0>, C4<0>;
+v0000000003c27710_0 .net "A", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c286b0_0 .net "B", 0 0, L_000000000415bcf0;  alias, 1 drivers
+L_000000000407a0a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c26130_0 .net8 "VGND", 0 0, L_000000000407a0a0;  1 drivers, strength-aware
+L_0000000004079af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27990_0 .net8 "VNB", 0 0, L_0000000004079af0;  1 drivers, strength-aware
+L_000000000407a420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c27c10_0 .net8 "VPB", 0 0, L_000000000407a420;  1 drivers, strength-aware
+L_0000000004079930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c269f0_0 .net8 "VPWR", 0 0, L_0000000004079930;  1 drivers, strength-aware
+v0000000003c277b0_0 .net "Y", 0 0, L_000000000415aef0;  alias, 1 drivers
+v0000000003c287f0_0 .net "nor0_out_Y", 0 0, L_000000000415ada0;  1 drivers
+S_0000000003c4c100 .scope module, "_1005_" "sky130_fd_sc_hd__o32a_2" 3 3288, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003c26270_0 .net "A1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c282f0_0 .net "A2", 0 0, L_000000000415bcf0;  alias, 1 drivers
+v0000000003c27670_0 .net "A3", 0 0, L_0000000004139280;  alias, 1 drivers
+v0000000003c27850_0 .net "B1", 0 0, L_000000000415bf90;  alias, 1 drivers
+v0000000003c278f0_0 .net "B2", 0 0, L_000000000415aef0;  alias, 1 drivers
+L_00000000040790e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c263b0_0 .net8 "VGND", 0 0, L_00000000040790e0;  1 drivers, strength-aware
+L_0000000004079070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27df0_0 .net8 "VNB", 0 0, L_0000000004079070;  1 drivers, strength-aware
+L_0000000004079230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c26810_0 .net8 "VPB", 0 0, L_0000000004079230;  1 drivers, strength-aware
+L_0000000004079000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28750_0 .net8 "VPWR", 0 0, L_0000000004079000;  1 drivers, strength-aware
+v0000000003c26a90_0 .net "X", 0 0, L_000000000415b270;  alias, 1 drivers
+S_0000000003c4bf80 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003c4c100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_000000000415afd0 .functor OR 1, L_000000000415bcf0, L_00000000041298b0, L_0000000004139280, C4<0>;
+L_000000000415b5f0 .functor OR 1, L_000000000415aef0, L_000000000415bf90, C4<0>, C4<0>;
+L_000000000415b660 .functor AND 1, L_000000000415afd0, L_000000000415b5f0, C4<1>, C4<1>;
+L_000000000415b270 .functor BUF 1, L_000000000415b660, C4<0>, C4<0>, C4<0>;
+v0000000003c26d10_0 .net "A1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c264f0_0 .net "A2", 0 0, L_000000000415bcf0;  alias, 1 drivers
+v0000000003c272b0_0 .net "A3", 0 0, L_0000000004139280;  alias, 1 drivers
+v0000000003c27350_0 .net "B1", 0 0, L_000000000415bf90;  alias, 1 drivers
+v0000000003c26770_0 .net "B2", 0 0, L_000000000415aef0;  alias, 1 drivers
+L_00000000040798c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c284d0_0 .net8 "VGND", 0 0, L_00000000040798c0;  1 drivers, strength-aware
+L_000000000407a6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c26950_0 .net8 "VNB", 0 0, L_000000000407a6c0;  1 drivers, strength-aware
+L_000000000407a650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c27cb0_0 .net8 "VPB", 0 0, L_000000000407a650;  1 drivers, strength-aware
+L_000000000407a730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c275d0_0 .net8 "VPWR", 0 0, L_000000000407a730;  1 drivers, strength-aware
+v0000000003c26db0_0 .net "X", 0 0, L_000000000415b270;  alias, 1 drivers
+v0000000003c27f30_0 .net "and0_out_X", 0 0, L_000000000415b660;  1 drivers
+v0000000003c27d50_0 .net "or0_out", 0 0, L_000000000415afd0;  1 drivers
+v0000000003c28390_0 .net "or1_out", 0 0, L_000000000415b5f0;  1 drivers
+S_0000000003c4fe80 .scope module, "_1006_" "sky130_fd_sc_hd__inv_2" 3 3296, 4 54053 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003c26bd0_0 .net "A", 0 0, L_000000000415b270;  alias, 1 drivers
+L_000000000407a7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27030_0 .net8 "VGND", 0 0, L_000000000407a7a0;  1 drivers, strength-aware
+L_00000000040799a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c26ef0_0 .net8 "VNB", 0 0, L_00000000040799a0;  1 drivers, strength-aware
+L_0000000004079a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28cf0_0 .net8 "VPB", 0 0, L_0000000004079a10;  1 drivers, strength-aware
+L_000000000407a110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a050_0 .net8 "VPWR", 0 0, L_000000000407a110;  1 drivers, strength-aware
+v0000000003c29010_0 .net "Y", 0 0, L_000000000415b6d0;  alias, 1 drivers
+S_0000000003c4fb80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003c4fe80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000415bdd0 .functor NOT 1, L_000000000415b270, C4<0>, C4<0>, C4<0>;
+L_000000000415b6d0 .functor BUF 1, L_000000000415bdd0, C4<0>, C4<0>, C4<0>;
+v0000000003c26450_0 .net "A", 0 0, L_000000000415b270;  alias, 1 drivers
+L_0000000004079460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c26e50_0 .net8 "VGND", 0 0, L_0000000004079460;  1 drivers, strength-aware
+L_0000000004078eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c27fd0_0 .net8 "VNB", 0 0, L_0000000004078eb0;  1 drivers, strength-aware
+L_000000000407a570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28070_0 .net8 "VPB", 0 0, L_000000000407a570;  1 drivers, strength-aware
+L_0000000004078d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28430_0 .net8 "VPWR", 0 0, L_0000000004078d60;  1 drivers, strength-aware
+v0000000003c268b0_0 .net "Y", 0 0, L_000000000415b6d0;  alias, 1 drivers
+v0000000003c26b30_0 .net "not0_out_Y", 0 0, L_000000000415bdd0;  1 drivers
+S_0000000003c4fd00 .scope module, "_1007_" "sky130_fd_sc_hd__or2_2" 3 3300, 4 33031 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c29470_0 .net "A", 0 0, L_000000000415bc80;  alias, 1 drivers
+v0000000003c2acd0_0 .net "B", 0 0, L_000000000415b6d0;  alias, 1 drivers
+L_0000000004079b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a0f0_0 .net8 "VGND", 0 0, L_0000000004079b60;  1 drivers, strength-aware
+L_00000000040792a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c29c90_0 .net8 "VNB", 0 0, L_00000000040792a0;  1 drivers, strength-aware
+L_0000000004079c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29830_0 .net8 "VPB", 0 0, L_0000000004079c40;  1 drivers, strength-aware
+L_0000000004079310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29d30_0 .net8 "VPWR", 0 0, L_0000000004079310;  1 drivers, strength-aware
+v0000000003c2a7d0_0 .net "X", 0 0, L_000000000415b2e0;  alias, 1 drivers
+S_0000000003c4df00 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_0000000003c4fd00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415a940 .functor OR 1, L_000000000415b6d0, L_000000000415bc80, C4<0>, C4<0>;
+L_000000000415b2e0 .functor BUF 1, L_000000000415a940, C4<0>, C4<0>, C4<0>;
+v0000000003c2b090_0 .net "A", 0 0, L_000000000415bc80;  alias, 1 drivers
+v0000000003c28f70_0 .net "B", 0 0, L_000000000415b6d0;  alias, 1 drivers
+L_0000000004079a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a9b0_0 .net8 "VGND", 0 0, L_0000000004079a80;  1 drivers, strength-aware
+L_0000000004079150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c296f0_0 .net8 "VNB", 0 0, L_0000000004079150;  1 drivers, strength-aware
+L_0000000004079bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29a10_0 .net8 "VPB", 0 0, L_0000000004079bd0;  1 drivers, strength-aware
+L_000000000407a5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29b50_0 .net8 "VPWR", 0 0, L_000000000407a5e0;  1 drivers, strength-aware
+v0000000003c2a190_0 .net "X", 0 0, L_000000000415b2e0;  alias, 1 drivers
+v0000000003c2a730_0 .net "or0_out_X", 0 0, L_000000000415a940;  1 drivers
+S_0000000003c4b200 .scope module, "_1008_" "sky130_fd_sc_hd__o21a_2" 3 3305, 4 65618 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c29dd0_0 .net "A1", 0 0, L_000000000415ae80;  alias, 1 drivers
+v0000000003c2ab90_0 .net "A2", 0 0, L_000000000415b270;  alias, 1 drivers
+v0000000003c2a230_0 .net "B1", 0 0, L_000000000415b2e0;  alias, 1 drivers
+L_0000000004078dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a4b0_0 .net8 "VGND", 0 0, L_0000000004078dd0;  1 drivers, strength-aware
+L_0000000004078e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c295b0_0 .net8 "VNB", 0 0, L_0000000004078e40;  1 drivers, strength-aware
+L_0000000004079380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28ed0_0 .net8 "VPB", 0 0, L_0000000004079380;  1 drivers, strength-aware
+L_0000000004079cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ad70_0 .net8 "VPWR", 0 0, L_0000000004079cb0;  1 drivers, strength-aware
+v0000000003c2a870_0 .net "X", 0 0, L_000000000415bd60;  alias, 1 drivers
+S_0000000003c4c280 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_0000000003c4b200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415c380 .functor OR 1, L_000000000415b270, L_000000000415ae80, C4<0>, C4<0>;
+L_000000000415a9b0 .functor AND 1, L_000000000415c380, L_000000000415b2e0, C4<1>, C4<1>;
+L_000000000415bd60 .functor BUF 1, L_000000000415a9b0, C4<0>, C4<0>, C4<0>;
+v0000000003c290b0_0 .net "A1", 0 0, L_000000000415ae80;  alias, 1 drivers
+v0000000003c298d0_0 .net "A2", 0 0, L_000000000415b270;  alias, 1 drivers
+v0000000003c2a910_0 .net "B1", 0 0, L_000000000415b2e0;  alias, 1 drivers
+L_0000000004079d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c29150_0 .net8 "VGND", 0 0, L_0000000004079d20;  1 drivers, strength-aware
+L_0000000004079d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a690_0 .net8 "VNB", 0 0, L_0000000004079d90;  1 drivers, strength-aware
+L_0000000004079ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2aff0_0 .net8 "VPB", 0 0, L_0000000004079ee0;  1 drivers, strength-aware
+L_000000000407a030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29510_0 .net8 "VPWR", 0 0, L_000000000407a030;  1 drivers, strength-aware
+v0000000003c291f0_0 .net "X", 0 0, L_000000000415bd60;  alias, 1 drivers
+v0000000003c28d90_0 .net "and0_out_X", 0 0, L_000000000415a9b0;  1 drivers
+v0000000003c28e30_0 .net "or0_out", 0 0, L_000000000415c380;  1 drivers
+S_0000000003c4e680 .scope module, "_1009_" "sky130_fd_sc_hd__o21ai_2" 3 3311, 4 89631 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+v0000000003c2a410_0 .net "A1", 0 0, L_0000000004127700;  alias, 1 drivers
+v0000000003c29ab0_0 .net "A2", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003c29bf0_0 .net "B1", 0 0, L_0000000004126e40;  alias, 1 drivers
+L_000000000407a180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c293d0_0 .net8 "VGND", 0 0, L_000000000407a180;  1 drivers, strength-aware
+L_000000000407a1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c29650_0 .net8 "VNB", 0 0, L_000000000407a1f0;  1 drivers, strength-aware
+L_000000000407b840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c28b10_0 .net8 "VPB", 0 0, L_000000000407b840;  1 drivers, strength-aware
+L_000000000407c3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2aeb0_0 .net8 "VPWR", 0 0, L_000000000407c3a0;  1 drivers, strength-aware
+v0000000003c29790_0 .net "Y", 0 0, L_000000000415b740;  alias, 1 drivers
+S_0000000003c50180 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_0000000003c4e680;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415aa20 .functor OR 1, L_0000000004128110, L_0000000004127700, C4<0>, C4<0>;
+L_000000000415b350 .functor NAND 1, L_0000000004126e40, L_000000000415aa20, C4<1>, C4<1>;
+L_000000000415b740 .functor BUF 1, L_000000000415b350, C4<0>, C4<0>, C4<0>;
+v0000000003c2a2d0_0 .net "A1", 0 0, L_0000000004127700;  alias, 1 drivers
+v0000000003c29e70_0 .net "A2", 0 0, L_0000000004128110;  alias, 1 drivers
+v0000000003c29290_0 .net "B1", 0 0, L_0000000004126e40;  alias, 1 drivers
+L_000000000407bd10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c29330_0 .net8 "VGND", 0 0, L_000000000407bd10;  1 drivers, strength-aware
+L_000000000407ac00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c28930_0 .net8 "VNB", 0 0, L_000000000407ac00;  1 drivers, strength-aware
+L_000000000407ac70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29970_0 .net8 "VPB", 0 0, L_000000000407ac70;  1 drivers, strength-aware
+L_000000000407b680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c289d0_0 .net8 "VPWR", 0 0, L_000000000407b680;  1 drivers, strength-aware
+v0000000003c2ae10_0 .net "Y", 0 0, L_000000000415b740;  alias, 1 drivers
+v0000000003c2a370_0 .net "nand0_out_Y", 0 0, L_000000000415b350;  1 drivers
+v0000000003c28a70_0 .net "or0_out", 0 0, L_000000000415aa20;  1 drivers
+S_0000000003c4e200 .scope module, "_1010_" "sky130_fd_sc_hd__nor2_2" 3 3317, 4 30285 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003c28bb0_0 .net "A", 0 0, L_00000000041394b0;  alias, 1 drivers
+v0000000003c28c50_0 .net "B", 0 0, L_000000000415bcf0;  alias, 1 drivers
+L_000000000407bfb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c3f0_0 .net8 "VGND", 0 0, L_000000000407bfb0;  1 drivers, strength-aware
+L_000000000407bc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b130_0 .net8 "VNB", 0 0, L_000000000407bc30;  1 drivers, strength-aware
+L_000000000407c410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2cd50_0 .net8 "VPB", 0 0, L_000000000407c410;  1 drivers, strength-aware
+L_000000000407bd80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c670_0 .net8 "VPWR", 0 0, L_000000000407bd80;  1 drivers, strength-aware
+v0000000003c2bf90_0 .net "Y", 0 0, L_000000000415b820;  alias, 1 drivers
+S_0000000003c4b380 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003c4e200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000415b0b0 .functor NOR 1, L_00000000041394b0, L_000000000415bcf0, C4<0>, C4<0>;
+L_000000000415b820 .functor BUF 1, L_000000000415b0b0, C4<0>, C4<0>, C4<0>;
+v0000000003c2a550_0 .net "A", 0 0, L_00000000041394b0;  alias, 1 drivers
+v0000000003c29f10_0 .net "B", 0 0, L_000000000415bcf0;  alias, 1 drivers
+L_000000000407b610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2aa50_0 .net8 "VGND", 0 0, L_000000000407b610;  1 drivers, strength-aware
+L_000000000407b0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2aaf0_0 .net8 "VNB", 0 0, L_000000000407b0d0;  1 drivers, strength-aware
+L_000000000407aff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2a5f0_0 .net8 "VPB", 0 0, L_000000000407aff0;  1 drivers, strength-aware
+L_000000000407a9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c29fb0_0 .net8 "VPWR", 0 0, L_000000000407a9d0;  1 drivers, strength-aware
+v0000000003c2ac30_0 .net "Y", 0 0, L_000000000415b820;  alias, 1 drivers
+v0000000003c2af50_0 .net "nor0_out_Y", 0 0, L_000000000415b0b0;  1 drivers
+S_0000000003c4c580 .scope module, "_1011_" "sky130_fd_sc_hd__o32a_2" 3 3322, 4 45973 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+v0000000003c2c850_0 .net "A1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c2b810_0 .net "A2", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003c2cc10_0 .net "A3", 0 0, L_000000000415b970;  alias, 1 drivers
+v0000000003c2b1d0_0 .net "B1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c2d110_0 .net "B2", 0 0, L_000000000415b820;  alias, 1 drivers
+L_000000000407b220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b4f0_0 .net8 "VGND", 0 0, L_000000000407b220;  1 drivers, strength-aware
+L_000000000407af80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c990_0 .net8 "VNB", 0 0, L_000000000407af80;  1 drivers, strength-aware
+L_000000000407c020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2cf30_0 .net8 "VPB", 0 0, L_000000000407c020;  1 drivers, strength-aware
+L_000000000407bb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b310_0 .net8 "VPWR", 0 0, L_000000000407bb50;  1 drivers, strength-aware
+v0000000003c2d390_0 .net "X", 0 0, L_000000000415c150;  alias, 1 drivers
+S_0000000003c4c700 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_0000000003c4c580;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_000000000415b9e0 .functor OR 1, L_0000000004138870, L_00000000041298b0, L_000000000415b970, C4<0>;
+L_000000000415beb0 .functor OR 1, L_000000000415b820, L_00000000041298b0, C4<0>, C4<0>;
+L_000000000415c0e0 .functor AND 1, L_000000000415b9e0, L_000000000415beb0, C4<1>, C4<1>;
+L_000000000415c150 .functor BUF 1, L_000000000415c0e0, C4<0>, C4<0>, C4<0>;
+v0000000003c2cb70_0 .net "A1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c2ccb0_0 .net "A2", 0 0, L_0000000004138870;  alias, 1 drivers
+v0000000003c2d890_0 .net "A3", 0 0, L_000000000415b970;  alias, 1 drivers
+v0000000003c2bc70_0 .net "B1", 0 0, L_00000000041298b0;  alias, 1 drivers
+v0000000003c2cdf0_0 .net "B2", 0 0, L_000000000415b820;  alias, 1 drivers
+L_000000000407b370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ce90_0 .net8 "VGND", 0 0, L_000000000407b370;  1 drivers, strength-aware
+L_000000000407bf40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c710_0 .net8 "VNB", 0 0, L_000000000407bf40;  1 drivers, strength-aware
+L_000000000407b3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c530_0 .net8 "VPB", 0 0, L_000000000407b3e0;  1 drivers, strength-aware
+L_000000000407ba00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2d750_0 .net8 "VPWR", 0 0, L_000000000407ba00;  1 drivers, strength-aware
+v0000000003c2c2b0_0 .net "X", 0 0, L_000000000415c150;  alias, 1 drivers
+v0000000003c2d4d0_0 .net "and0_out_X", 0 0, L_000000000415c0e0;  1 drivers
+v0000000003c2b6d0_0 .net "or0_out", 0 0, L_000000000415b9e0;  1 drivers
+v0000000003c2c210_0 .net "or1_out", 0 0, L_000000000415beb0;  1 drivers
+S_0000000003c4ee00 .scope module, "_1012_" "sky130_fd_sc_hd__a2bb2o_2" 3 3330, 4 62293 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c2c350_0 .net "A1_N", 0 0, L_000000000415b740;  alias, 1 drivers
+v0000000003c2d570_0 .net "A2_N", 0 0, L_000000000415c150;  alias, 1 drivers
+v0000000003c2c7b0_0 .net "B1", 0 0, L_000000000415b740;  alias, 1 drivers
+v0000000003c2d7f0_0 .net "B2", 0 0, L_000000000415c150;  alias, 1 drivers
+L_000000000407af10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ca30_0 .net8 "VGND", 0 0, L_000000000407af10;  1 drivers, strength-aware
+L_000000000407ae30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2d2f0_0 .net8 "VNB", 0 0, L_000000000407ae30;  1 drivers, strength-aware
+L_000000000407b140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2d430_0 .net8 "VPB", 0 0, L_000000000407b140;  1 drivers, strength-aware
+L_000000000407ace0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ba90_0 .net8 "VPWR", 0 0, L_000000000407ace0;  1 drivers, strength-aware
+v0000000003c2b8b0_0 .net "X", 0 0, L_000000000415d3b0;  alias, 1 drivers
+S_0000000003c4e380 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000003c4ee00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000415c1c0 .functor AND 1, L_000000000415b740, L_000000000415c150, C4<1>, C4<1>;
+L_000000000415c230 .functor NOR 1, L_000000000415b740, L_000000000415c150, C4<0>, C4<0>;
+L_000000000415c2a0 .functor OR 1, L_000000000415c230, L_000000000415c1c0, C4<0>, C4<0>;
+L_000000000415d3b0 .functor BUF 1, L_000000000415c2a0, C4<0>, C4<0>, C4<0>;
+v0000000003c2cfd0_0 .net "A1_N", 0 0, L_000000000415b740;  alias, 1 drivers
+v0000000003c2b590_0 .net "A2_N", 0 0, L_000000000415c150;  alias, 1 drivers
+v0000000003c2b630_0 .net "B1", 0 0, L_000000000415b740;  alias, 1 drivers
+v0000000003c2b3b0_0 .net "B2", 0 0, L_000000000415c150;  alias, 1 drivers
+L_000000000407b290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c8f0_0 .net8 "VGND", 0 0, L_000000000407b290;  1 drivers, strength-aware
+L_000000000407bae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2c490_0 .net8 "VNB", 0 0, L_000000000407bae0;  1 drivers, strength-aware
+L_000000000407ab20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2bd10_0 .net8 "VPB", 0 0, L_000000000407ab20;  1 drivers, strength-aware
+L_000000000407b1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2d250_0 .net8 "VPWR", 0 0, L_000000000407b1b0;  1 drivers, strength-aware
+v0000000003c2b9f0_0 .net "X", 0 0, L_000000000415d3b0;  alias, 1 drivers
+v0000000003c2d070_0 .net "and0_out", 0 0, L_000000000415c1c0;  1 drivers
+v0000000003c2d1b0_0 .net "nor0_out", 0 0, L_000000000415c230;  1 drivers
+v0000000003c2c5d0_0 .net "or0_out_X", 0 0, L_000000000415c2a0;  1 drivers
+S_0000000003c4e980 .scope module, "_1013_" "sky130_fd_sc_hd__a2bb2oi_2" 3 3337, 4 61581 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+v0000000003c2c030_0 .net "A1_N", 0 0, L_000000000415b2e0;  alias, 1 drivers
+v0000000003c2c0d0_0 .net "A2_N", 0 0, L_000000000415d3b0;  alias, 1 drivers
+v0000000003c2c170_0 .net "B1", 0 0, L_000000000415b2e0;  alias, 1 drivers
+v0000000003c2fd70_0 .net "B2", 0 0, L_000000000415d3b0;  alias, 1 drivers
+L_000000000407ab90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2fff0_0 .net8 "VGND", 0 0, L_000000000407ab90;  1 drivers, strength-aware
+L_000000000407c1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e010_0 .net8 "VNB", 0 0, L_000000000407c1e0;  1 drivers, strength-aware
+L_000000000407a8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f730_0 .net8 "VPB", 0 0, L_000000000407a8f0;  1 drivers, strength-aware
+L_000000000407b530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ea10_0 .net8 "VPWR", 0 0, L_000000000407b530;  1 drivers, strength-aware
+v0000000003c2dd90_0 .net "Y", 0 0, L_000000000415c620;  alias, 1 drivers
+S_0000000003c4d180 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000003c4e980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000415c770 .functor AND 1, L_000000000415b2e0, L_000000000415d3b0, C4<1>, C4<1>;
+L_000000000415c690 .functor NOR 1, L_000000000415b2e0, L_000000000415d3b0, C4<0>, C4<0>;
+L_000000000415c5b0 .functor NOR 1, L_000000000415c690, L_000000000415c770, C4<0>, C4<0>;
+L_000000000415c620 .functor BUF 1, L_000000000415c5b0, C4<0>, C4<0>, C4<0>;
+v0000000003c2bb30_0 .net "A1_N", 0 0, L_000000000415b2e0;  alias, 1 drivers
+v0000000003c2d610_0 .net "A2_N", 0 0, L_000000000415d3b0;  alias, 1 drivers
+v0000000003c2cad0_0 .net "B1", 0 0, L_000000000415b2e0;  alias, 1 drivers
+v0000000003c2d6b0_0 .net "B2", 0 0, L_000000000415d3b0;  alias, 1 drivers
+L_000000000407bdf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b270_0 .net8 "VGND", 0 0, L_000000000407bdf0;  1 drivers, strength-aware
+L_000000000407aab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b450_0 .net8 "VNB", 0 0, L_000000000407aab0;  1 drivers, strength-aware
+L_000000000407c090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2b770_0 .net8 "VPB", 0 0, L_000000000407c090;  1 drivers, strength-aware
+L_000000000407be60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2bef0_0 .net8 "VPWR", 0 0, L_000000000407be60;  1 drivers, strength-aware
+v0000000003c2b950_0 .net "Y", 0 0, L_000000000415c620;  alias, 1 drivers
+v0000000003c2bbd0_0 .net "and0_out", 0 0, L_000000000415c770;  1 drivers
+v0000000003c2bdb0_0 .net "nor0_out", 0 0, L_000000000415c690;  1 drivers
+v0000000003c2be50_0 .net "nor1_out_Y", 0 0, L_000000000415c5b0;  1 drivers
+S_0000000003c4c880 .scope module, "_1014_" "sky130_fd_sc_hd__mux2_1" 3 3344, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c2ef10_0 .net "A0", 0 0, L_000000000413a7f0;  alias, 1 drivers
+v0000000003c30090_0 .net "A1", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003c2e0b0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407b300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e970_0 .net8 "VGND", 0 0, L_000000000407b300;  1 drivers, strength-aware
+L_000000000407ad50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2d9d0_0 .net8 "VNB", 0 0, L_000000000407ad50;  1 drivers, strength-aware
+L_000000000407ba70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2fe10_0 .net8 "VPB", 0 0, L_000000000407ba70;  1 drivers, strength-aware
+L_000000000407b450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e6f0_0 .net8 "VPWR", 0 0, L_000000000407b450;  1 drivers, strength-aware
+v0000000003c2da70_0 .net "X", 0 0, L_000000000415cd90;  1 drivers
+S_0000000003c4ca00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c4c880;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+UDP_sky130_fd_sc_hd__udp_mux_2to1 .udp/comb "sky130_fd_sc_hd__udp_mux_2to1", 3
+ ,"00?0"
+ ,"11?1"
+ ,"0?00"
+ ,"1?01"
+ ,"?010"
+ ,"?111";
+L_000000000415d0a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413a7f0, L_000000000413b820, L_000000000413b0b0;
+L_000000000415cd90 .functor BUF 1, L_000000000415d0a0, C4<0>, C4<0>, C4<0>;
+v0000000003c2dcf0_0 .net "A0", 0 0, L_000000000413a7f0;  alias, 1 drivers
+v0000000003c2e510_0 .net "A1", 0 0, L_000000000413b820;  alias, 1 drivers
+v0000000003c2de30_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407a960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ff50_0 .net8 "VGND", 0 0, L_000000000407a960;  1 drivers, strength-aware
+L_000000000407adc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e650_0 .net8 "VNB", 0 0, L_000000000407adc0;  1 drivers, strength-aware
+L_000000000407bed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2fcd0_0 .net8 "VPB", 0 0, L_000000000407bed0;  1 drivers, strength-aware
+L_000000000407c100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f870_0 .net8 "VPWR", 0 0, L_000000000407c100;  1 drivers, strength-aware
+v0000000003c2d930_0 .net "X", 0 0, L_000000000415cd90;  alias, 1 drivers
+v0000000003c2f5f0_0 .net "mux_2to10_out_X", 0 0, L_000000000415d0a0;  1 drivers
+S_0000000003c4ec80 .scope module, "_1015_" "sky130_fd_sc_hd__mux2_1" 3 3350, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c2e5b0_0 .net "A0", 0 0, L_000000000413af60;  alias, 1 drivers
+v0000000003c2f7d0_0 .net "A1", 0 0, L_0000000004139ec0;  alias, 1 drivers
+v0000000003c2f550_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407aea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2fb90_0 .net8 "VGND", 0 0, L_000000000407aea0;  1 drivers, strength-aware
+L_000000000407bbc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e790_0 .net8 "VNB", 0 0, L_000000000407bbc0;  1 drivers, strength-aware
+L_000000000407b760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2eab0_0 .net8 "VPB", 0 0, L_000000000407b760;  1 drivers, strength-aware
+L_000000000407b4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2db10_0 .net8 "VPWR", 0 0, L_000000000407b4c0;  1 drivers, strength-aware
+v0000000003c2dbb0_0 .net "X", 0 0, L_000000000415d340;  1 drivers
+S_0000000003c4cb80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c4ec80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d110 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413af60, L_0000000004139ec0, L_000000000413b0b0;
+L_000000000415d340 .functor BUF 1, L_000000000415d110, C4<0>, C4<0>, C4<0>;
+v0000000003c2edd0_0 .net "A0", 0 0, L_000000000413af60;  alias, 1 drivers
+v0000000003c2f230_0 .net "A1", 0 0, L_0000000004139ec0;  alias, 1 drivers
+v0000000003c2ded0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407bca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2df70_0 .net8 "VGND", 0 0, L_000000000407bca0;  1 drivers, strength-aware
+L_000000000407b5a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f910_0 .net8 "VNB", 0 0, L_000000000407b5a0;  1 drivers, strength-aware
+L_000000000407b6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e8d0_0 .net8 "VPB", 0 0, L_000000000407b6f0;  1 drivers, strength-aware
+L_000000000407b060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e150_0 .net8 "VPWR", 0 0, L_000000000407b060;  1 drivers, strength-aware
+v0000000003c2f9b0_0 .net "X", 0 0, L_000000000415d340;  alias, 1 drivers
+v0000000003c2ed30_0 .net "mux_2to10_out_X", 0 0, L_000000000415d110;  1 drivers
+S_0000000003c4ce80 .scope module, "_1016_" "sky130_fd_sc_hd__mux2_1" 3 3356, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c2fa50_0 .net "A0", 0 0, L_000000000413a470;  alias, 1 drivers
+v0000000003c2ee70_0 .net "A1", 0 0, L_000000000413b510;  alias, 1 drivers
+v0000000003c2e3d0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407b7d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f2d0_0 .net8 "VGND", 0 0, L_000000000407b7d0;  1 drivers, strength-aware
+L_000000000407b8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e470_0 .net8 "VNB", 0 0, L_000000000407b8b0;  1 drivers, strength-aware
+L_000000000407b920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2efb0_0 .net8 "VPB", 0 0, L_000000000407b920;  1 drivers, strength-aware
+L_000000000407b990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2feb0_0 .net8 "VPWR", 0 0, L_000000000407b990;  1 drivers, strength-aware
+v0000000003c2f0f0_0 .net "X", 0 0, L_000000000415cf50;  1 drivers
+S_0000000003c4d000 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c4ce80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415ce00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413a470, L_000000000413b510, L_000000000413b0b0;
+L_000000000415cf50 .functor BUF 1, L_000000000415ce00, C4<0>, C4<0>, C4<0>;
+v0000000003c2e830_0 .net "A0", 0 0, L_000000000413a470;  alias, 1 drivers
+v0000000003c2eb50_0 .net "A1", 0 0, L_000000000413b510;  alias, 1 drivers
+v0000000003c2dc50_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407c170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2ebf0_0 .net8 "VGND", 0 0, L_000000000407c170;  1 drivers, strength-aware
+L_000000000407c250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e1f0_0 .net8 "VNB", 0 0, L_000000000407c250;  1 drivers, strength-aware
+L_000000000407c2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e290_0 .net8 "VPB", 0 0, L_000000000407c2c0;  1 drivers, strength-aware
+L_000000000407c330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2e330_0 .net8 "VPWR", 0 0, L_000000000407c330;  1 drivers, strength-aware
+v0000000003c2ec90_0 .net "X", 0 0, L_000000000415cf50;  alias, 1 drivers
+v0000000003c2f050_0 .net "mux_2to10_out_X", 0 0, L_000000000415ce00;  1 drivers
+S_0000000003c53000 .scope module, "_1017_" "sky130_fd_sc_hd__mux2_1" 3 3362, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c30450_0 .net "A0", 0 0, L_000000000413b900;  alias, 1 drivers
+v0000000003c31ad0_0 .net "A1", 0 0, L_000000000413cee0;  alias, 1 drivers
+v0000000003c304f0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407c480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c30950_0 .net8 "VGND", 0 0, L_000000000407c480;  1 drivers, strength-aware
+L_000000000407aa40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c31670_0 .net8 "VNB", 0 0, L_000000000407aa40;  1 drivers, strength-aware
+L_000000000407d750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c30810_0 .net8 "VPB", 0 0, L_000000000407d750;  1 drivers, strength-aware
+L_000000000407dfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c310d0_0 .net8 "VPWR", 0 0, L_000000000407dfa0;  1 drivers, strength-aware
+v0000000003c31df0_0 .net "X", 0 0, L_000000000415d880;  1 drivers
+S_0000000003c53180 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c53000;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d490 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413b900, L_000000000413cee0, L_000000000413b0b0;
+L_000000000415d880 .functor BUF 1, L_000000000415d490, C4<0>, C4<0>, C4<0>;
+v0000000003c2f190_0 .net "A0", 0 0, L_000000000413b900;  alias, 1 drivers
+v0000000003c2f370_0 .net "A1", 0 0, L_000000000413cee0;  alias, 1 drivers
+v0000000003c2f410_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407cf00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f4b0_0 .net8 "VGND", 0 0, L_000000000407cf00;  1 drivers, strength-aware
+L_000000000407cdb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c2f690_0 .net8 "VNB", 0 0, L_000000000407cdb0;  1 drivers, strength-aware
+L_000000000407d6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2faf0_0 .net8 "VPB", 0 0, L_000000000407d6e0;  1 drivers, strength-aware
+L_000000000407dbb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c2fc30_0 .net8 "VPWR", 0 0, L_000000000407dbb0;  1 drivers, strength-aware
+v0000000003c31a30_0 .net "X", 0 0, L_000000000415d880;  alias, 1 drivers
+v0000000003c31030_0 .net "mux_2to10_out_X", 0 0, L_000000000415d490;  1 drivers
+S_0000000003c53300 .scope module, "_1018_" "sky130_fd_sc_hd__mux2_1" 3 3368, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c312b0_0 .net "A0", 0 0, L_000000000413c7e0;  alias, 1 drivers
+v0000000003c309f0_0 .net "A1", 0 0, L_000000000413d260;  alias, 1 drivers
+v0000000003c30c70_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c326b0_0 .net8 "VGND", 0 0, L_000000000407d600;  1 drivers, strength-aware
+L_000000000407cf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c30bd0_0 .net8 "VNB", 0 0, L_000000000407cf70;  1 drivers, strength-aware
+L_000000000407c9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c321b0_0 .net8 "VPB", 0 0, L_000000000407c9c0;  1 drivers, strength-aware
+L_000000000407dd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32390_0 .net8 "VPWR", 0 0, L_000000000407dd70;  1 drivers, strength-aware
+v0000000003c31b70_0 .net "X", 0 0, L_000000000415d960;  1 drivers
+S_0000000003c52400 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c53300;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d8f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413c7e0, L_000000000413d260, L_000000000413b0b0;
+L_000000000415d960 .functor BUF 1, L_000000000415d8f0, C4<0>, C4<0>, C4<0>;
+v0000000003c32610_0 .net "A0", 0 0, L_000000000413c7e0;  alias, 1 drivers
+v0000000003c30f90_0 .net "A1", 0 0, L_000000000413d260;  alias, 1 drivers
+v0000000003c31990_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407c800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c31490_0 .net8 "VGND", 0 0, L_000000000407c800;  1 drivers, strength-aware
+L_000000000407d980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c31170_0 .net8 "VNB", 0 0, L_000000000407d980;  1 drivers, strength-aware
+L_000000000407ccd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32250_0 .net8 "VPB", 0 0, L_000000000407ccd0;  1 drivers, strength-aware
+L_000000000407d4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c31210_0 .net8 "VPWR", 0 0, L_000000000407d4b0;  1 drivers, strength-aware
+v0000000003c313f0_0 .net "X", 0 0, L_000000000415d960;  alias, 1 drivers
+v0000000003c322f0_0 .net "mux_2to10_out_X", 0 0, L_000000000415d8f0;  1 drivers
+S_0000000003c51200 .scope module, "_1019_" "sky130_fd_sc_hd__mux2_1" 3 3374, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c301d0_0 .net "A0", 0 0, L_000000000413da40;  alias, 1 drivers
+v0000000003c31d50_0 .net "A1", 0 0, L_000000000413db20;  alias, 1 drivers
+v0000000003c31710_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407dde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c317b0_0 .net8 "VGND", 0 0, L_000000000407dde0;  1 drivers, strength-aware
+L_000000000407da60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c31fd0_0 .net8 "VNB", 0 0, L_000000000407da60;  1 drivers, strength-aware
+L_000000000407d9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32890_0 .net8 "VPB", 0 0, L_000000000407d9f0;  1 drivers, strength-aware
+L_000000000407dd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c31e90_0 .net8 "VPWR", 0 0, L_000000000407dd00;  1 drivers, strength-aware
+v0000000003c30a90_0 .net "X", 0 0, L_000000000415d9d0;  1 drivers
+S_0000000003c53a80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415cd20 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413da40, L_000000000413db20, L_000000000413b0b0;
+L_000000000415d9d0 .functor BUF 1, L_000000000415cd20, C4<0>, C4<0>, C4<0>;
+v0000000003c31530_0 .net "A0", 0 0, L_000000000413da40;  alias, 1 drivers
+v0000000003c32570_0 .net "A1", 0 0, L_000000000413db20;  alias, 1 drivers
+v0000000003c31350_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407dc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c324d0_0 .net8 "VGND", 0 0, L_000000000407dc20;  1 drivers, strength-aware
+L_000000000407ce90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c306d0_0 .net8 "VNB", 0 0, L_000000000407ce90;  1 drivers, strength-aware
+L_000000000407d050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c315d0_0 .net8 "VPB", 0 0, L_000000000407d050;  1 drivers, strength-aware
+L_000000000407d2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c31c10_0 .net8 "VPWR", 0 0, L_000000000407d2f0;  1 drivers, strength-aware
+v0000000003c31cb0_0 .net "X", 0 0, L_000000000415d9d0;  alias, 1 drivers
+v0000000003c30590_0 .net "mux_2to10_out_X", 0 0, L_000000000415cd20;  1 drivers
+S_0000000003c52a00 .scope module, "_1020_" "sky130_fd_sc_hd__mux2_1" 3 3380, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c31f30_0 .net "A0", 0 0, L_000000000413e4c0;  alias, 1 drivers
+v0000000003c308b0_0 .net "A1", 0 0, L_000000000413e610;  alias, 1 drivers
+v0000000003c32430_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c327f0_0 .net8 "VGND", 0 0, L_000000000407d8a0;  1 drivers, strength-aware
+L_000000000407dec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c30770_0 .net8 "VNB", 0 0, L_000000000407dec0;  1 drivers, strength-aware
+L_000000000407caa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c303b0_0 .net8 "VPB", 0 0, L_000000000407caa0;  1 drivers, strength-aware
+L_000000000407d0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c30db0_0 .net8 "VPWR", 0 0, L_000000000407d0c0;  1 drivers, strength-aware
+v0000000003c30270_0 .net "X", 0 0, L_000000000415df80;  1 drivers
+S_0000000003c54080 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c52a00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415db20 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413e4c0, L_000000000413e610, L_000000000413b0b0;
+L_000000000415df80 .functor BUF 1, L_000000000415db20, C4<0>, C4<0>, C4<0>;
+v0000000003c30ef0_0 .net "A0", 0 0, L_000000000413e4c0;  alias, 1 drivers
+v0000000003c32750_0 .net "A1", 0 0, L_000000000413e610;  alias, 1 drivers
+v0000000003c30630_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c30310_0 .net8 "VGND", 0 0, L_000000000407d670;  1 drivers, strength-aware
+L_000000000407df30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c32070_0 .net8 "VNB", 0 0, L_000000000407df30;  1 drivers, strength-aware
+L_000000000407dc90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c30130_0 .net8 "VPB", 0 0, L_000000000407dc90;  1 drivers, strength-aware
+L_000000000407cd40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c31850_0 .net8 "VPWR", 0 0, L_000000000407cd40;  1 drivers, strength-aware
+v0000000003c318f0_0 .net "X", 0 0, L_000000000415df80;  alias, 1 drivers
+v0000000003c32110_0 .net "mux_2to10_out_X", 0 0, L_000000000415db20;  1 drivers
+S_0000000003c53f00 .scope module, "_1021_" "sky130_fd_sc_hd__mux2_1" 3 3386, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c34870_0 .net "A0", 0 0, L_0000000004140bb0;  alias, 1 drivers
+v0000000003c32930_0 .net "A1", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003c345f0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33ab0_0 .net8 "VGND", 0 0, L_000000000407d910;  1 drivers, strength-aware
+L_000000000407d360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33d30_0 .net8 "VNB", 0 0, L_000000000407d360;  1 drivers, strength-aware
+L_000000000407d7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c34c30_0 .net8 "VPB", 0 0, L_000000000407d7c0;  1 drivers, strength-aware
+L_000000000407de50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32ed0_0 .net8 "VPWR", 0 0, L_000000000407de50;  1 drivers, strength-aware
+v0000000003c35090_0 .net "X", 0 0, L_000000000415c850;  1 drivers
+S_0000000003c51680 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c53f00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415c700 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004140bb0, L_0000000004140ad0, L_000000000413b0b0;
+L_000000000415c850 .functor BUF 1, L_000000000415c700, C4<0>, C4<0>, C4<0>;
+v0000000003c30e50_0 .net "A0", 0 0, L_0000000004140bb0;  alias, 1 drivers
+v0000000003c30b30_0 .net "A1", 0 0, L_0000000004140ad0;  alias, 1 drivers
+v0000000003c30d10_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33650_0 .net8 "VGND", 0 0, L_000000000407d1a0;  1 drivers, strength-aware
+L_000000000407c640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c34d70_0 .net8 "VNB", 0 0, L_000000000407c640;  1 drivers, strength-aware
+L_000000000407cb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c34a50_0 .net8 "VPB", 0 0, L_000000000407cb10;  1 drivers, strength-aware
+L_000000000407c6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c33510_0 .net8 "VPWR", 0 0, L_000000000407c6b0;  1 drivers, strength-aware
+v0000000003c32d90_0 .net "X", 0 0, L_000000000415c850;  alias, 1 drivers
+v0000000003c34230_0 .net "mux_2to10_out_X", 0 0, L_000000000415c700;  1 drivers
+S_0000000003c54980 .scope module, "_1022_" "sky130_fd_sc_hd__mux2_1" 3 3392, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c32e30_0 .net "A0", 0 0, L_00000000041400c0;  alias, 1 drivers
+v0000000003c349b0_0 .net "A1", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003c33dd0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407ce20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c34cd0_0 .net8 "VGND", 0 0, L_000000000407ce20;  1 drivers, strength-aware
+L_000000000407e080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33f10_0 .net8 "VNB", 0 0, L_000000000407e080;  1 drivers, strength-aware
+L_000000000407d440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c34af0_0 .net8 "VPB", 0 0, L_000000000407d440;  1 drivers, strength-aware
+L_000000000407d3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32bb0_0 .net8 "VPWR", 0 0, L_000000000407d3d0;  1 drivers, strength-aware
+v0000000003c335b0_0 .net "X", 0 0, L_000000000415d500;  1 drivers
+S_0000000003c52580 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415c8c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000041400c0, L_000000000413f1e0, L_000000000413b0b0;
+L_000000000415d500 .functor BUF 1, L_000000000415c8c0, C4<0>, C4<0>, C4<0>;
+v0000000003c34410_0 .net "A0", 0 0, L_00000000041400c0;  alias, 1 drivers
+v0000000003c342d0_0 .net "A1", 0 0, L_000000000413f1e0;  alias, 1 drivers
+v0000000003c34370_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407c4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33790_0 .net8 "VGND", 0 0, L_000000000407c4f0;  1 drivers, strength-aware
+L_000000000407e010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33e70_0 .net8 "VNB", 0 0, L_000000000407e010;  1 drivers, strength-aware
+L_000000000407c560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c32c50_0 .net8 "VPB", 0 0, L_000000000407c560;  1 drivers, strength-aware
+L_000000000407c5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c344b0_0 .net8 "VPWR", 0 0, L_000000000407c5d0;  1 drivers, strength-aware
+v0000000003c32cf0_0 .net "X", 0 0, L_000000000415d500;  alias, 1 drivers
+v0000000003c33150_0 .net "mux_2to10_out_X", 0 0, L_000000000415c8c0;  1 drivers
+S_0000000003c53600 .scope module, "_1023_" "sky130_fd_sc_hd__mux2_1" 3 3398, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c34550_0 .net "A0", 0 0, L_000000000413fdb0;  alias, 1 drivers
+v0000000003c33470_0 .net "A1", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003c34b90_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407dad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c331f0_0 .net8 "VGND", 0 0, L_000000000407dad0;  1 drivers, strength-aware
+L_000000000407ca30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33a10_0 .net8 "VNB", 0 0, L_000000000407ca30;  1 drivers, strength-aware
+L_000000000407d280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c34690_0 .net8 "VPB", 0 0, L_000000000407d280;  1 drivers, strength-aware
+L_000000000407d830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c340f0_0 .net8 "VPWR", 0 0, L_000000000407d830;  1 drivers, strength-aware
+v0000000003c34730_0 .net "X", 0 0, L_000000000415c7e0;  1 drivers
+S_0000000003c52880 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c53600;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d2d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000413fdb0, L_0000000004140600, L_000000000413b0b0;
+L_000000000415c7e0 .functor BUF 1, L_000000000415d2d0, C4<0>, C4<0>, C4<0>;
+v0000000003c33970_0 .net "A0", 0 0, L_000000000413fdb0;  alias, 1 drivers
+v0000000003c33fb0_0 .net "A1", 0 0, L_0000000004140600;  alias, 1 drivers
+v0000000003c34e10_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407db40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c336f0_0 .net8 "VGND", 0 0, L_000000000407db40;  1 drivers, strength-aware
+L_000000000407c720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c34050_0 .net8 "VNB", 0 0, L_000000000407c720;  1 drivers, strength-aware
+L_000000000407cfe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c34eb0_0 .net8 "VPB", 0 0, L_000000000407cfe0;  1 drivers, strength-aware
+L_000000000407c790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c338d0_0 .net8 "VPWR", 0 0, L_000000000407c790;  1 drivers, strength-aware
+v0000000003c329d0_0 .net "X", 0 0, L_000000000415c7e0;  alias, 1 drivers
+v0000000003c33830_0 .net "mux_2to10_out_X", 0 0, L_000000000415d2d0;  1 drivers
+S_0000000003c53d80 .scope module, "_1024_" "sky130_fd_sc_hd__mux2_1" 3 3404, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c34ff0_0 .net "A0", 0 0, L_0000000004141400;  alias, 1 drivers
+v0000000003c32a70_0 .net "A1", 0 0, L_0000000004142580;  alias, 1 drivers
+v0000000003c34190_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c32b10_0 .net8 "VGND", 0 0, L_000000000407d130;  1 drivers, strength-aware
+L_000000000407d210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c330b0_0 .net8 "VNB", 0 0, L_000000000407d210;  1 drivers, strength-aware
+L_000000000407c870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c33330_0 .net8 "VPB", 0 0, L_000000000407c870;  1 drivers, strength-aware
+L_000000000407cb80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c333d0_0 .net8 "VPWR", 0 0, L_000000000407cb80;  1 drivers, strength-aware
+v0000000003c35ef0_0 .net "X", 0 0, L_000000000415dff0;  1 drivers
+S_0000000003c51800 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c53d80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415df10 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004141400, L_0000000004142580, L_000000000413b0b0;
+L_000000000415dff0 .functor BUF 1, L_000000000415df10, C4<0>, C4<0>, C4<0>;
+v0000000003c34f50_0 .net "A0", 0 0, L_0000000004141400;  alias, 1 drivers
+v0000000003c32f70_0 .net "A1", 0 0, L_0000000004142580;  alias, 1 drivers
+v0000000003c33290_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407c8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33010_0 .net8 "VGND", 0 0, L_000000000407c8e0;  1 drivers, strength-aware
+L_000000000407c950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c33b50_0 .net8 "VNB", 0 0, L_000000000407c950;  1 drivers, strength-aware
+L_000000000407cbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c347d0_0 .net8 "VPB", 0 0, L_000000000407cbf0;  1 drivers, strength-aware
+L_000000000407cc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c33bf0_0 .net8 "VPWR", 0 0, L_000000000407cc60;  1 drivers, strength-aware
+v0000000003c33c90_0 .net "X", 0 0, L_000000000415dff0;  alias, 1 drivers
+v0000000003c34910_0 .net "mux_2to10_out_X", 0 0, L_000000000415df10;  1 drivers
+S_0000000003c51380 .scope module, "_1025_" "sky130_fd_sc_hd__mux2_1" 3 3410, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c362b0_0 .net "A0", 0 0, L_0000000004141d30;  alias, 1 drivers
+v0000000003c365d0_0 .net "A1", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003c359f0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407d520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c367b0_0 .net8 "VGND", 0 0, L_000000000407d520;  1 drivers, strength-aware
+L_000000000407d590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c377f0_0 .net8 "VNB", 0 0, L_000000000407d590;  1 drivers, strength-aware
+L_000000000407ed30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c35f90_0 .net8 "VPB", 0 0, L_000000000407ed30;  1 drivers, strength-aware
+L_000000000407e4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c37890_0 .net8 "VPWR", 0 0, L_000000000407e4e0;  1 drivers, strength-aware
+v0000000003c37610_0 .net "X", 0 0, L_000000000415dc00;  1 drivers
+S_0000000003c52e80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51380;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415cee0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004141d30, L_0000000004141cc0, L_000000000413b0b0;
+L_000000000415dc00 .functor BUF 1, L_000000000415cee0, C4<0>, C4<0>, C4<0>;
+v0000000003c36530_0 .net "A0", 0 0, L_0000000004141d30;  alias, 1 drivers
+v0000000003c358b0_0 .net "A1", 0 0, L_0000000004141cc0;  alias, 1 drivers
+v0000000003c36e90_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c37570_0 .net8 "VGND", 0 0, L_000000000407e470;  1 drivers, strength-aware
+L_000000000407e5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c37070_0 .net8 "VNB", 0 0, L_000000000407e5c0;  1 drivers, strength-aware
+L_000000000407e400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c36a30_0 .net8 "VPB", 0 0, L_000000000407e400;  1 drivers, strength-aware
+L_000000000407eb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c354f0_0 .net8 "VPWR", 0 0, L_000000000407eb00;  1 drivers, strength-aware
+v0000000003c36710_0 .net "X", 0 0, L_000000000415dc00;  alias, 1 drivers
+v0000000003c374d0_0 .net "mux_2to10_out_X", 0 0, L_000000000415cee0;  1 drivers
+S_0000000003c54380 .scope module, "_1026_" "sky130_fd_sc_hd__mux2_1" 3 3416, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c37750_0 .net "A0", 0 0, L_00000000041435b0;  alias, 1 drivers
+v0000000003c368f0_0 .net "A1", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003c36fd0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407fac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c35db0_0 .net8 "VGND", 0 0, L_000000000407fac0;  1 drivers, strength-aware
+L_000000000407fa50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c36f30_0 .net8 "VNB", 0 0, L_000000000407fa50;  1 drivers, strength-aware
+L_000000000407fb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c351d0_0 .net8 "VPB", 0 0, L_000000000407fb30;  1 drivers, strength-aware
+L_000000000407fba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c35b30_0 .net8 "VPWR", 0 0, L_000000000407fba0;  1 drivers, strength-aware
+v0000000003c36990_0 .net "X", 0 0, L_000000000415cb60;  1 drivers
+S_0000000003c53780 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54380;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d030 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000041435b0, L_0000000004143310, L_000000000413b0b0;
+L_000000000415cb60 .functor BUF 1, L_000000000415d030, C4<0>, C4<0>, C4<0>;
+v0000000003c36b70_0 .net "A0", 0 0, L_00000000041435b0;  alias, 1 drivers
+v0000000003c35810_0 .net "A1", 0 0, L_0000000004143310;  alias, 1 drivers
+v0000000003c36670_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407ebe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c35130_0 .net8 "VGND", 0 0, L_000000000407ebe0;  1 drivers, strength-aware
+L_000000000407ea20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c376b0_0 .net8 "VNB", 0 0, L_000000000407ea20;  1 drivers, strength-aware
+L_000000000407f510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c35950_0 .net8 "VPB", 0 0, L_000000000407f510;  1 drivers, strength-aware
+L_000000000407e7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c36850_0 .net8 "VPWR", 0 0, L_000000000407e7f0;  1 drivers, strength-aware
+v0000000003c36170_0 .net "X", 0 0, L_000000000415cb60;  alias, 1 drivers
+v0000000003c360d0_0 .net "mux_2to10_out_X", 0 0, L_000000000415d030;  1 drivers
+S_0000000003c52100 .scope module, "_1027_" "sky130_fd_sc_hd__mux2_1" 3 3422, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c35bd0_0 .net "A0", 0 0, L_0000000004124910;  alias, 1 drivers
+v0000000003c35d10_0 .net "A1", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003c37110_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c36d50_0 .net8 "VGND", 0 0, L_000000000407e2b0;  1 drivers, strength-aware
+L_000000000407f660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c36ad0_0 .net8 "VNB", 0 0, L_000000000407f660;  1 drivers, strength-aware
+L_000000000407e0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c37250_0 .net8 "VPB", 0 0, L_000000000407e0f0;  1 drivers, strength-aware
+L_000000000407eef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c35310_0 .net8 "VPWR", 0 0, L_000000000407eef0;  1 drivers, strength-aware
+v0000000003c36350_0 .net "X", 0 0, L_000000000415d420;  1 drivers
+S_0000000003c54b00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c52100;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415ca10 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004124910, L_0000000004143cb0, L_000000000413b0b0;
+L_000000000415d420 .functor BUF 1, L_000000000415ca10, C4<0>, C4<0>, C4<0>;
+v0000000003c35270_0 .net "A0", 0 0, L_0000000004124910;  alias, 1 drivers
+v0000000003c35590_0 .net "A1", 0 0, L_0000000004143cb0;  alias, 1 drivers
+v0000000003c36030_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c35a90_0 .net8 "VGND", 0 0, L_000000000407e6a0;  1 drivers, strength-aware
+L_000000000407f040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c35c70_0 .net8 "VNB", 0 0, L_000000000407f040;  1 drivers, strength-aware
+L_000000000407e630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c36210_0 .net8 "VPB", 0 0, L_000000000407e630;  1 drivers, strength-aware
+L_000000000407ecc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c356d0_0 .net8 "VPWR", 0 0, L_000000000407ecc0;  1 drivers, strength-aware
+v0000000003c371b0_0 .net "X", 0 0, L_000000000415d420;  alias, 1 drivers
+v0000000003c37390_0 .net "mux_2to10_out_X", 0 0, L_000000000415ca10;  1 drivers
+S_0000000003c52700 .scope module, "_1028_" "sky130_fd_sc_hd__mux2_1" 3 3428, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c36490_0 .net "A0", 0 0, L_00000000041242f0;  alias, 1 drivers
+v0000000003c36df0_0 .net "A1", 0 0, L_0000000004124520;  alias, 1 drivers
+v0000000003c35450_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c37c50_0 .net8 "VGND", 0 0, L_000000000407e390;  1 drivers, strength-aware
+L_000000000407ef60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c39410_0 .net8 "VNB", 0 0, L_000000000407ef60;  1 drivers, strength-aware
+L_000000000407ea90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c37cf0_0 .net8 "VPB", 0 0, L_000000000407ea90;  1 drivers, strength-aware
+L_000000000407f580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c38470_0 .net8 "VPWR", 0 0, L_000000000407f580;  1 drivers, strength-aware
+v0000000003c39cd0_0 .net "X", 0 0, L_000000000415c930;  1 drivers
+S_0000000003c53900 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c52700;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d570 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000041242f0, L_0000000004124520, L_000000000413b0b0;
+L_000000000415c930 .functor BUF 1, L_000000000415d570, C4<0>, C4<0>, C4<0>;
+v0000000003c35e50_0 .net "A0", 0 0, L_00000000041242f0;  alias, 1 drivers
+v0000000003c36c10_0 .net "A1", 0 0, L_0000000004124520;  alias, 1 drivers
+v0000000003c372f0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407f0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c35630_0 .net8 "VGND", 0 0, L_000000000407f0b0;  1 drivers, strength-aware
+L_000000000407ec50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c36cb0_0 .net8 "VNB", 0 0, L_000000000407ec50;  1 drivers, strength-aware
+L_000000000407fc10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c37430_0 .net8 "VPB", 0 0, L_000000000407fc10;  1 drivers, strength-aware
+L_000000000407fc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c363f0_0 .net8 "VPWR", 0 0, L_000000000407fc80;  1 drivers, strength-aware
+v0000000003c353b0_0 .net "X", 0 0, L_000000000415c930;  alias, 1 drivers
+v0000000003c35770_0 .net "mux_2to10_out_X", 0 0, L_000000000415d570;  1 drivers
+S_0000000003c52b80 .scope module, "_1029_" "sky130_fd_sc_hd__mux2_1" 3 3434, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c38510_0 .net "A0", 0 0, L_0000000004124980;  alias, 1 drivers
+v0000000003c38830_0 .net "A1", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003c39a50_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407eda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c38650_0 .net8 "VGND", 0 0, L_000000000407eda0;  1 drivers, strength-aware
+L_000000000407f200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c397d0_0 .net8 "VNB", 0 0, L_000000000407f200;  1 drivers, strength-aware
+L_000000000407e8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c39870_0 .net8 "VPB", 0 0, L_000000000407e8d0;  1 drivers, strength-aware
+L_000000000407e160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c386f0_0 .net8 "VPWR", 0 0, L_000000000407e160;  1 drivers, strength-aware
+v0000000003c37d90_0 .net "X", 0 0, L_000000000415cbd0;  1 drivers
+S_0000000003c54200 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c52b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415c9a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004124980, L_0000000004123aa0, L_000000000413b0b0;
+L_000000000415cbd0 .functor BUF 1, L_000000000415c9a0, C4<0>, C4<0>, C4<0>;
+v0000000003c39690_0 .net "A0", 0 0, L_0000000004124980;  alias, 1 drivers
+v0000000003c39ff0_0 .net "A1", 0 0, L_0000000004123aa0;  alias, 1 drivers
+v0000000003c38010_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c39730_0 .net8 "VGND", 0 0, L_000000000407e1d0;  1 drivers, strength-aware
+L_000000000407eb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c38a10_0 .net8 "VNB", 0 0, L_000000000407eb70;  1 drivers, strength-aware
+L_000000000407ee10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c38790_0 .net8 "VPB", 0 0, L_000000000407ee10;  1 drivers, strength-aware
+L_000000000407f740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c37b10_0 .net8 "VPWR", 0 0, L_000000000407f740;  1 drivers, strength-aware
+v0000000003c385b0_0 .net "X", 0 0, L_000000000415cbd0;  alias, 1 drivers
+v0000000003c38c90_0 .net "mux_2to10_out_X", 0 0, L_000000000415c9a0;  1 drivers
+S_0000000003c54500 .scope module, "_1030_" "sky130_fd_sc_hd__mux2_1" 3 3440, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c380b0_0 .net "A0", 0 0, L_0000000004158170;  alias, 1 drivers
+v0000000003c38970_0 .net "A1", 0 0, L_0000000004157ed0;  alias, 1 drivers
+v0000000003c38b50_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c39d70_0 .net8 "VGND", 0 0, L_000000000407e940;  1 drivers, strength-aware
+L_000000000407f350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c38150_0 .net8 "VNB", 0 0, L_000000000407f350;  1 drivers, strength-aware
+L_000000000407f3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c38bf0_0 .net8 "VPB", 0 0, L_000000000407f3c0;  1 drivers, strength-aware
+L_000000000407ee80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c381f0_0 .net8 "VPWR", 0 0, L_000000000407ee80;  1 drivers, strength-aware
+v0000000003c39230_0 .net "X", 0 0, L_000000000415d180;  1 drivers
+S_0000000003c52d00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415cfc0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000004158170, L_0000000004157ed0, L_000000000413b0b0;
+L_000000000415d180 .functor BUF 1, L_000000000415cfc0, C4<0>, C4<0>, C4<0>;
+v0000000003c39910_0 .net "A0", 0 0, L_0000000004158170;  alias, 1 drivers
+v0000000003c37bb0_0 .net "A1", 0 0, L_0000000004157ed0;  alias, 1 drivers
+v0000000003c37e30_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a090_0 .net8 "VGND", 0 0, L_000000000407e9b0;  1 drivers, strength-aware
+L_000000000407f6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c388d0_0 .net8 "VNB", 0 0, L_000000000407f6d0;  1 drivers, strength-aware
+L_000000000407f890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c399b0_0 .net8 "VPB", 0 0, L_000000000407f890;  1 drivers, strength-aware
+L_000000000407e240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c38ab0_0 .net8 "VPWR", 0 0, L_000000000407e240;  1 drivers, strength-aware
+v0000000003c37ed0_0 .net "X", 0 0, L_000000000415d180;  alias, 1 drivers
+v0000000003c37f70_0 .net "mux_2to10_out_X", 0 0, L_000000000415cfc0;  1 drivers
+S_0000000003c54c80 .scope module, "_1031_" "sky130_fd_sc_hd__mux2_1" 3 3446, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c38f10_0 .net "A0", 0 0, L_00000000041583a0;  alias, 1 drivers
+v0000000003c38fb0_0 .net "A1", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c38290_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407efd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c38330_0 .net8 "VGND", 0 0, L_000000000407efd0;  1 drivers, strength-aware
+L_000000000407f120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c383d0_0 .net8 "VNB", 0 0, L_000000000407f120;  1 drivers, strength-aware
+L_000000000407f4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c39eb0_0 .net8 "VPB", 0 0, L_000000000407f4a0;  1 drivers, strength-aware
+L_000000000407f190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c39050_0 .net8 "VPWR", 0 0, L_000000000407f190;  1 drivers, strength-aware
+v0000000003c390f0_0 .net "X", 0 0, L_000000000415ce70;  1 drivers
+S_0000000003c54e00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54c80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d260 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000041583a0, L_00000000041584f0, L_000000000413b0b0;
+L_000000000415ce70 .functor BUF 1, L_000000000415d260, C4<0>, C4<0>, C4<0>;
+v0000000003c38d30_0 .net "A0", 0 0, L_00000000041583a0;  alias, 1 drivers
+v0000000003c39c30_0 .net "A1", 0 0, L_00000000041584f0;  alias, 1 drivers
+v0000000003c37930_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407f270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c38dd0_0 .net8 "VGND", 0 0, L_000000000407f270;  1 drivers, strength-aware
+L_000000000407f7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c379d0_0 .net8 "VNB", 0 0, L_000000000407f7b0;  1 drivers, strength-aware
+L_000000000407e320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c39e10_0 .net8 "VPB", 0 0, L_000000000407e320;  1 drivers, strength-aware
+L_000000000407f2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c392d0_0 .net8 "VPWR", 0 0, L_000000000407f2e0;  1 drivers, strength-aware
+v0000000003c38e70_0 .net "X", 0 0, L_000000000415ce70;  alias, 1 drivers
+v0000000003c39af0_0 .net "mux_2to10_out_X", 0 0, L_000000000415d260;  1 drivers
+S_0000000003c51500 .scope module, "_1032_" "sky130_fd_sc_hd__mux2_1" 3 3452, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3c2f0_0 .net "A0", 0 0, L_000000000415a630;  alias, 1 drivers
+v0000000003c3c4d0_0 .net "A1", 0 0, L_0000000004158fe0;  alias, 1 drivers
+v0000000003c3ad10_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407e710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b670_0 .net8 "VGND", 0 0, L_000000000407e710;  1 drivers, strength-aware
+L_000000000407e780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3af90_0 .net8 "VNB", 0 0, L_000000000407e780;  1 drivers, strength-aware
+L_000000000407f430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b0d0_0 .net8 "VPB", 0 0, L_000000000407f430;  1 drivers, strength-aware
+L_000000000407e550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a1d0_0 .net8 "VPWR", 0 0, L_000000000407e550;  1 drivers, strength-aware
+v0000000003c3b030_0 .net "X", 0 0, L_000000000415d1f0;  1 drivers
+S_0000000003c53480 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d5e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415a630, L_0000000004158fe0, L_000000000413b0b0;
+L_000000000415d1f0 .functor BUF 1, L_000000000415d5e0, C4<0>, C4<0>, C4<0>;
+v0000000003c39190_0 .net "A0", 0 0, L_000000000415a630;  alias, 1 drivers
+v0000000003c39370_0 .net "A1", 0 0, L_0000000004158fe0;  alias, 1 drivers
+v0000000003c39b90_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407f5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c39550_0 .net8 "VGND", 0 0, L_000000000407f5f0;  1 drivers, strength-aware
+L_000000000407f820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c39f50_0 .net8 "VNB", 0 0, L_000000000407f820;  1 drivers, strength-aware
+L_000000000407e860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c394b0_0 .net8 "VPB", 0 0, L_000000000407e860;  1 drivers, strength-aware
+L_000000000407f900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c395f0_0 .net8 "VPWR", 0 0, L_000000000407f900;  1 drivers, strength-aware
+v0000000003c37a70_0 .net "X", 0 0, L_000000000415d1f0;  alias, 1 drivers
+v0000000003c3a130_0 .net "mux_2to10_out_X", 0 0, L_000000000415d5e0;  1 drivers
+S_0000000003c51980 .scope module, "_1033_" "sky130_fd_sc_hd__mux2_1" 3 3458, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3c070_0 .net "A0", 0 0, L_000000000415a390;  alias, 1 drivers
+v0000000003c3aa90_0 .net "A1", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c3a810_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407f970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b170_0 .net8 "VGND", 0 0, L_000000000407f970;  1 drivers, strength-aware
+L_000000000407f9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c110_0 .net8 "VNB", 0 0, L_000000000407f9e0;  1 drivers, strength-aware
+L_000000000407fcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b3f0_0 .net8 "VPB", 0 0, L_000000000407fcf0;  1 drivers, strength-aware
+L_0000000004080930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b490_0 .net8 "VPWR", 0 0, L_0000000004080930;  1 drivers, strength-aware
+v0000000003c3bfd0_0 .net "X", 0 0, L_000000000415de30;  1 drivers
+S_0000000003c53c00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415ca80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415a390, L_00000000041593d0, L_000000000413b0b0;
+L_000000000415de30 .functor BUF 1, L_000000000415ca80, C4<0>, C4<0>, C4<0>;
+v0000000003c3ac70_0 .net "A0", 0 0, L_000000000415a390;  alias, 1 drivers
+v0000000003c3bcb0_0 .net "A1", 0 0, L_00000000041593d0;  alias, 1 drivers
+v0000000003c3b710_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004081180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b530_0 .net8 "VGND", 0 0, L_0000000004081180;  1 drivers, strength-aware
+L_000000000407feb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c750_0 .net8 "VNB", 0 0, L_000000000407feb0;  1 drivers, strength-aware
+L_0000000004081490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b2b0_0 .net8 "VPB", 0 0, L_0000000004081490;  1 drivers, strength-aware
+L_0000000004081110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c570_0 .net8 "VPWR", 0 0, L_0000000004081110;  1 drivers, strength-aware
+v0000000003c3a6d0_0 .net "X", 0 0, L_000000000415de30;  alias, 1 drivers
+v0000000003c3b210_0 .net "mux_2to10_out_X", 0 0, L_000000000415ca80;  1 drivers
+S_0000000003c51e00 .scope module, "_1034_" "sky130_fd_sc_hd__mux2_1" 3 3464, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3b7b0_0 .net "A0", 0 0, L_000000000415be40;  alias, 1 drivers
+v0000000003c3a310_0 .net "A1", 0 0, L_0000000004159520;  alias, 1 drivers
+v0000000003c3a630_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004080620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b850_0 .net8 "VGND", 0 0, L_0000000004080620;  1 drivers, strength-aware
+L_0000000004080000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3ae50_0 .net8 "VNB", 0 0, L_0000000004080000;  1 drivers, strength-aware
+L_0000000004080e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3b8f0_0 .net8 "VPB", 0 0, L_0000000004080e70;  1 drivers, strength-aware
+L_0000000004080770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c250_0 .net8 "VPWR", 0 0, L_0000000004080770;  1 drivers, strength-aware
+v0000000003c3adb0_0 .net "X", 0 0, L_000000000415d650;  1 drivers
+S_0000000003c51b00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51e00;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415e060 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415be40, L_0000000004159520, L_000000000413b0b0;
+L_000000000415d650 .functor BUF 1, L_000000000415e060, C4<0>, C4<0>, C4<0>;
+v0000000003c3bd50_0 .net "A0", 0 0, L_000000000415be40;  alias, 1 drivers
+v0000000003c3b5d0_0 .net "A1", 0 0, L_0000000004159520;  alias, 1 drivers
+v0000000003c3a8b0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_000000000407fd60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a3b0_0 .net8 "VGND", 0 0, L_000000000407fd60;  1 drivers, strength-aware
+L_00000000040801c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a4f0_0 .net8 "VNB", 0 0, L_00000000040801c0;  1 drivers, strength-aware
+L_00000000040812d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3bc10_0 .net8 "VPB", 0 0, L_00000000040812d0;  1 drivers, strength-aware
+L_00000000040813b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a950_0 .net8 "VPWR", 0 0, L_00000000040813b0;  1 drivers, strength-aware
+v0000000003c3bf30_0 .net "X", 0 0, L_000000000415d650;  alias, 1 drivers
+v0000000003c3b350_0 .net "mux_2to10_out_X", 0 0, L_000000000415e060;  1 drivers
+S_0000000003c54680 .scope module, "_1035_" "sky130_fd_sc_hd__mux2_1" 3 3470, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3a590_0 .net "A0", 0 0, L_000000000415ac50;  alias, 1 drivers
+v0000000003c3be90_0 .net "A1", 0 0, L_000000000415b040;  alias, 1 drivers
+v0000000003c3c1b0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004080c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c390_0 .net8 "VGND", 0 0, L_0000000004080c40;  1 drivers, strength-aware
+L_00000000040816c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c430_0 .net8 "VNB", 0 0, L_00000000040816c0;  1 drivers, strength-aware
+L_0000000004080b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c6b0_0 .net8 "VPB", 0 0, L_0000000004080b60;  1 drivers, strength-aware
+L_00000000040805b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c7f0_0 .net8 "VPWR", 0 0, L_00000000040805b0;  1 drivers, strength-aware
+v0000000003c3a270_0 .net "X", 0 0, L_000000000415d6c0;  1 drivers
+S_0000000003c51080 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54680;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415e0d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415ac50, L_000000000415b040, L_000000000413b0b0;
+L_000000000415d6c0 .functor BUF 1, L_000000000415e0d0, C4<0>, C4<0>, C4<0>;
+v0000000003c3bdf0_0 .net "A0", 0 0, L_000000000415ac50;  alias, 1 drivers
+v0000000003c3b990_0 .net "A1", 0 0, L_000000000415b040;  alias, 1 drivers
+v0000000003c3aef0_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_00000000040810a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3ba30_0 .net8 "VGND", 0 0, L_00000000040810a0;  1 drivers, strength-aware
+L_0000000004080700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3bad0_0 .net8 "VNB", 0 0, L_0000000004080700;  1 drivers, strength-aware
+L_00000000040808c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3a9f0_0 .net8 "VPB", 0 0, L_00000000040808c0;  1 drivers, strength-aware
+L_0000000004081420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3bb70_0 .net8 "VPWR", 0 0, L_0000000004081420;  1 drivers, strength-aware
+v0000000003c3c890_0 .net "X", 0 0, L_000000000415d6c0;  alias, 1 drivers
+v0000000003c3c610_0 .net "mux_2to10_out_X", 0 0, L_000000000415e0d0;  1 drivers
+S_0000000003c54800 .scope module, "_1036_" "sky130_fd_sc_hd__mux2_1" 3 3476, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3d970_0 .net "A0", 0 0, L_000000000415bd60;  alias, 1 drivers
+v0000000003c3ee10_0 .net "A1", 0 0, L_000000000415b6d0;  alias, 1 drivers
+v0000000003c3dd30_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004081730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c930_0 .net8 "VGND", 0 0, L_0000000004081730;  1 drivers, strength-aware
+L_000000000407fdd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e5f0_0 .net8 "VNB", 0 0, L_000000000407fdd0;  1 drivers, strength-aware
+L_0000000004080070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3de70_0 .net8 "VPB", 0 0, L_0000000004080070;  1 drivers, strength-aware
+L_00000000040817a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3d830_0 .net8 "VPWR", 0 0, L_00000000040817a0;  1 drivers, strength-aware
+v0000000003c3d150_0 .net "X", 0 0, L_000000000415caf0;  1 drivers
+S_0000000003c51c80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c54800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415d730 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415bd60, L_000000000415b6d0, L_000000000413b0b0;
+L_000000000415caf0 .functor BUF 1, L_000000000415d730, C4<0>, C4<0>, C4<0>;
+v0000000003c3a450_0 .net "A0", 0 0, L_000000000415bd60;  alias, 1 drivers
+v0000000003c3a770_0 .net "A1", 0 0, L_000000000415b6d0;  alias, 1 drivers
+v0000000003c3ab30_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004080230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3abd0_0 .net8 "VGND", 0 0, L_0000000004080230;  1 drivers, strength-aware
+L_00000000040803f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3cbb0_0 .net8 "VNB", 0 0, L_00000000040803f0;  1 drivers, strength-aware
+L_0000000004081810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e550_0 .net8 "VPB", 0 0, L_0000000004081810;  1 drivers, strength-aware
+L_0000000004081340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3eb90_0 .net8 "VPWR", 0 0, L_0000000004081340;  1 drivers, strength-aware
+v0000000003c3d790_0 .net "X", 0 0, L_000000000415caf0;  alias, 1 drivers
+v0000000003c3e190_0 .net "mux_2to10_out_X", 0 0, L_000000000415d730;  1 drivers
+S_0000000003c51f80 .scope module, "_1037_" "sky130_fd_sc_hd__mux2_1" 3 3482, 4 29526 1, S_00000000028e54a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+v0000000003c3eff0_0 .net "A0", 0 0, L_000000000415c620;  alias, 1 drivers
+v0000000003c3ec30_0 .net "A1", 0 0, L_000000000415d3b0;  alias, 1 drivers
+v0000000003c3ea50_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_0000000004080310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e910_0 .net8 "VGND", 0 0, L_0000000004080310;  1 drivers, strength-aware
+L_0000000004081260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3d290_0 .net8 "VNB", 0 0, L_0000000004081260;  1 drivers, strength-aware
+L_0000000004080cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e410_0 .net8 "VPB", 0 0, L_0000000004080cb0;  1 drivers, strength-aware
+L_0000000004081880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3c9d0_0 .net8 "VPWR", 0 0, L_0000000004081880;  1 drivers, strength-aware
+v0000000003c3e370_0 .net "X", 0 0, L_000000000415d7a0;  1 drivers
+S_0000000003c52280 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_0000000003c51f80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_000000000415cc40 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000415c620, L_000000000415d3b0, L_000000000413b0b0;
+L_000000000415d7a0 .functor BUF 1, L_000000000415cc40, C4<0>, C4<0>, C4<0>;
+v0000000003c3e4b0_0 .net "A0", 0 0, L_000000000415c620;  alias, 1 drivers
+v0000000003c3d1f0_0 .net "A1", 0 0, L_000000000415d3b0;  alias, 1 drivers
+v0000000003c3d470_0 .net "S", 0 0, L_000000000413b0b0;  alias, 1 drivers
+L_00000000040811f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e7d0_0 .net8 "VGND", 0 0, L_00000000040811f0;  1 drivers, strength-aware
+L_00000000040800e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e690_0 .net8 "VNB", 0 0, L_00000000040800e0;  1 drivers, strength-aware
+L_0000000004080150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e230_0 .net8 "VPB", 0 0, L_0000000004080150;  1 drivers, strength-aware
+L_0000000004080a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003c3e870_0 .net8 "VPWR", 0 0, L_0000000004080a80;  1 drivers, strength-aware
+v0000000003c3ed70_0 .net "X", 0 0, L_000000000415d7a0;  alias, 1 drivers
+v0000000003c3dab0_0 .net "mux_2to10_out_X", 0 0, L_000000000415cc40;  1 drivers
+S_0000000002722720 .scope module, "sky130_fd_sc_hd__a2111o_1" "sky130_fd_sc_hd__a2111o_1" 4 39193;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c65e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cc8790_0 .net "A1", 0 0, o0000000003c65e98;  0 drivers
+o0000000003c65ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cc9370_0 .net "A2", 0 0, o0000000003c65ec8;  0 drivers
+o0000000003c65ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cc9410_0 .net "B1", 0 0, o0000000003c65ef8;  0 drivers
+o0000000003c65f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cc79d0_0 .net "C1", 0 0, o0000000003c65f28;  0 drivers
+o0000000003c65f58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cc8b50_0 .net "D1", 0 0, o0000000003c65f58;  0 drivers
+L_0000000004081500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cc7a70_0 .net8 "VGND", 0 0, L_0000000004081500;  1 drivers, strength-aware
+L_0000000004081030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cc8290_0 .net8 "VNB", 0 0, L_0000000004081030;  1 drivers, strength-aware
+L_000000000407fe40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cc7bb0_0 .net8 "VPB", 0 0, L_000000000407fe40;  1 drivers, strength-aware
+L_0000000004081570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cc7ed0_0 .net8 "VPWR", 0 0, L_0000000004081570;  1 drivers, strength-aware
+v0000000003cc8fb0_0 .net "X", 0 0, L_000000000415ccb0;  1 drivers
+S_0000000003d094b0 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39215, 4 38937 1, S_0000000002722720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415d810 .functor AND 1, o0000000003c65e98, o0000000003c65ec8, C4<1>, C4<1>;
+L_000000000415da40 .functor OR 1, o0000000003c65f28, o0000000003c65ef8, L_000000000415d810, o0000000003c65f58;
+L_000000000415ccb0 .functor BUF 1, L_000000000415da40, C4<0>, C4<0>, C4<0>;
+v0000000003cc7cf0_0 .net "A1", 0 0, o0000000003c65e98;  alias, 0 drivers
+v0000000003cc9230_0 .net "A2", 0 0, o0000000003c65ec8;  alias, 0 drivers
+v0000000003cc8650_0 .net "B1", 0 0, o0000000003c65ef8;  alias, 0 drivers
+v0000000003cc9cd0_0 .net "C1", 0 0, o0000000003c65f28;  alias, 0 drivers
+v0000000003cc9e10_0 .net "D1", 0 0, o0000000003c65f58;  alias, 0 drivers
+L_0000000004080a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cc9ff0_0 .net8 "VGND", 0 0, L_0000000004080a10;  1 drivers, strength-aware
+L_00000000040804d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cc9190_0 .net8 "VNB", 0 0, L_00000000040804d0;  1 drivers, strength-aware
+L_0000000004080460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cc8e70_0 .net8 "VPB", 0 0, L_0000000004080460;  1 drivers, strength-aware
+L_000000000407ff20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cc85b0_0 .net8 "VPWR", 0 0, L_000000000407ff20;  1 drivers, strength-aware
+v0000000003cc9eb0_0 .net "X", 0 0, L_000000000415ccb0;  alias, 1 drivers
+v0000000003cc9f50_0 .net "and0_out", 0 0, L_000000000415d810;  1 drivers
+v0000000003cc7930_0 .net "or0_out_X", 0 0, L_000000000415da40;  1 drivers
+S_00000000027228a0 .scope module, "sky130_fd_sc_hd__a2111o_2" "sky130_fd_sc_hd__a2111o_2" 4 39067;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c663d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccb490_0 .net "A1", 0 0, o0000000003c663d8;  0 drivers
+o0000000003c66408 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cca630_0 .net "A2", 0 0, o0000000003c66408;  0 drivers
+o0000000003c66438 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccbcb0_0 .net "B1", 0 0, o0000000003c66438;  0 drivers
+o0000000003c66468 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccb530_0 .net "C1", 0 0, o0000000003c66468;  0 drivers
+o0000000003c66498 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cca950_0 .net "D1", 0 0, o0000000003c66498;  0 drivers
+L_0000000004080690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccaef0_0 .net8 "VGND", 0 0, L_0000000004080690;  1 drivers, strength-aware
+L_0000000004080380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccb030_0 .net8 "VNB", 0 0, L_0000000004080380;  1 drivers, strength-aware
+L_00000000040815e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccba30_0 .net8 "VPB", 0 0, L_00000000040815e0;  1 drivers, strength-aware
+L_0000000004080f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cca590_0 .net8 "VPWR", 0 0, L_0000000004080f50;  1 drivers, strength-aware
+v0000000003ccc890_0 .net "X", 0 0, L_000000000415dce0;  1 drivers
+S_0000000003d07830 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39089, 4 38937 1, S_00000000027228a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415dab0 .functor AND 1, o0000000003c663d8, o0000000003c66408, C4<1>, C4<1>;
+L_000000000415db90 .functor OR 1, o0000000003c66468, o0000000003c66438, L_000000000415dab0, o0000000003c66498;
+L_000000000415dce0 .functor BUF 1, L_000000000415db90, C4<0>, C4<0>, C4<0>;
+v0000000003cc8150_0 .net "A1", 0 0, o0000000003c663d8;  alias, 0 drivers
+v0000000003cc8330_0 .net "A2", 0 0, o0000000003c66408;  alias, 0 drivers
+v0000000003cc9050_0 .net "B1", 0 0, o0000000003c66438;  alias, 0 drivers
+v0000000003cc83d0_0 .net "C1", 0 0, o0000000003c66468;  alias, 0 drivers
+v0000000003cc8470_0 .net "D1", 0 0, o0000000003c66498;  alias, 0 drivers
+L_00000000040807e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cc8510_0 .net8 "VGND", 0 0, L_00000000040807e0;  1 drivers, strength-aware
+L_0000000004081650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cca3b0_0 .net8 "VNB", 0 0, L_0000000004081650;  1 drivers, strength-aware
+L_0000000004080850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cca4f0_0 .net8 "VPB", 0 0, L_0000000004080850;  1 drivers, strength-aware
+L_0000000004080fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccc7f0_0 .net8 "VPWR", 0 0, L_0000000004080fc0;  1 drivers, strength-aware
+v0000000003cca810_0 .net "X", 0 0, L_000000000415dce0;  alias, 1 drivers
+v0000000003ccbf30_0 .net "and0_out", 0 0, L_000000000415dab0;  1 drivers
+v0000000003ccb210_0 .net "or0_out_X", 0 0, L_000000000415db90;  1 drivers
+S_0000000002cf95e0 .scope module, "sky130_fd_sc_hd__a2111o_4" "sky130_fd_sc_hd__a2111o_4" 4 39319;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c66918 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccc6b0_0 .net "A1", 0 0, o0000000003c66918;  0 drivers
+o0000000003c66948 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cca9f0_0 .net "A2", 0 0, o0000000003c66948;  0 drivers
+o0000000003c66978 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccc070_0 .net "B1", 0 0, o0000000003c66978;  0 drivers
+o0000000003c669a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccb350_0 .net "C1", 0 0, o0000000003c669a8;  0 drivers
+o0000000003c669d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cca450_0 .net "D1", 0 0, o0000000003c669d8;  0 drivers
+L_00000000040809a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccb670_0 .net8 "VGND", 0 0, L_00000000040809a0;  1 drivers, strength-aware
+L_000000000407ff90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccaa90_0 .net8 "VNB", 0 0, L_000000000407ff90;  1 drivers, strength-aware
+L_0000000004080540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccb990_0 .net8 "VPB", 0 0, L_0000000004080540;  1 drivers, strength-aware
+L_00000000040802a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccb5d0_0 .net8 "VPWR", 0 0, L_00000000040802a0;  1 drivers, strength-aware
+v0000000003ccadb0_0 .net "X", 0 0, L_000000000415ddc0;  1 drivers
+S_0000000003d09ab0 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39341, 4 38937 1, S_0000000002cf95e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415dd50 .functor AND 1, o0000000003c66918, o0000000003c66948, C4<1>, C4<1>;
+L_000000000415dc70 .functor OR 1, o0000000003c669a8, o0000000003c66978, L_000000000415dd50, o0000000003c669d8;
+L_000000000415ddc0 .functor BUF 1, L_000000000415dc70, C4<0>, C4<0>, C4<0>;
+v0000000003ccb8f0_0 .net "A1", 0 0, o0000000003c66918;  alias, 0 drivers
+v0000000003ccc570_0 .net "A2", 0 0, o0000000003c66948;  alias, 0 drivers
+v0000000003ccbe90_0 .net "B1", 0 0, o0000000003c66978;  alias, 0 drivers
+v0000000003ccbd50_0 .net "C1", 0 0, o0000000003c669a8;  alias, 0 drivers
+v0000000003ccb2b0_0 .net "D1", 0 0, o0000000003c669d8;  alias, 0 drivers
+L_0000000004080af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccaf90_0 .net8 "VGND", 0 0, L_0000000004080af0;  1 drivers, strength-aware
+L_0000000004080bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cca130_0 .net8 "VNB", 0 0, L_0000000004080bd0;  1 drivers, strength-aware
+L_0000000004080d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccc110_0 .net8 "VPB", 0 0, L_0000000004080d20;  1 drivers, strength-aware
+L_0000000004080d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccbc10_0 .net8 "VPWR", 0 0, L_0000000004080d90;  1 drivers, strength-aware
+v0000000003ccbad0_0 .net "X", 0 0, L_000000000415ddc0;  alias, 1 drivers
+v0000000003ccb0d0_0 .net "and0_out", 0 0, L_000000000415dd50;  1 drivers
+v0000000003ccb170_0 .net "or0_out_X", 0 0, L_000000000415dc70;  1 drivers
+S_0000000002cf9760 .scope module, "sky130_fd_sc_hd__a2111oi_0" "sky130_fd_sc_hd__a2111oi_0" 4 35958;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c66e58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccc390_0 .net "A1", 0 0, o0000000003c66e58;  0 drivers
+o0000000003c66e88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cca270_0 .net "A2", 0 0, o0000000003c66e88;  0 drivers
+o0000000003c66eb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccbfd0_0 .net "B1", 0 0, o0000000003c66eb8;  0 drivers
+o0000000003c66ee8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccb850_0 .net "C1", 0 0, o0000000003c66ee8;  0 drivers
+o0000000003c66f18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccbb70_0 .net "D1", 0 0, o0000000003c66f18;  0 drivers
+L_0000000004080e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cca310_0 .net8 "VGND", 0 0, L_0000000004080e00;  1 drivers, strength-aware
+L_0000000004080ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccbdf0_0 .net8 "VNB", 0 0, L_0000000004080ee0;  1 drivers, strength-aware
+L_00000000040832c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccc1b0_0 .net8 "VPB", 0 0, L_00000000040832c0;  1 drivers, strength-aware
+L_0000000004082290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cca8b0_0 .net8 "VPWR", 0 0, L_0000000004082290;  1 drivers, strength-aware
+v0000000003ccc430_0 .net "Y", 0 0, L_000000000415e990;  1 drivers
+S_0000000003d0a530 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 35980, 4 35828 1, S_0000000002cf9760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415dea0 .functor AND 1, o0000000003c66e58, o0000000003c66e88, C4<1>, C4<1>;
+L_000000000415c540 .functor NOR 1, o0000000003c66eb8, o0000000003c66ee8, o0000000003c66f18, L_000000000415dea0;
+L_000000000415e990 .functor BUF 1, L_000000000415c540, C4<0>, C4<0>, C4<0>;
+v0000000003ccb3f0_0 .net "A1", 0 0, o0000000003c66e58;  alias, 0 drivers
+v0000000003ccc250_0 .net "A2", 0 0, o0000000003c66e88;  alias, 0 drivers
+v0000000003ccc610_0 .net "B1", 0 0, o0000000003c66eb8;  alias, 0 drivers
+v0000000003ccc2f0_0 .net "C1", 0 0, o0000000003c66ee8;  alias, 0 drivers
+v0000000003ccc4d0_0 .net "D1", 0 0, o0000000003c66f18;  alias, 0 drivers
+L_00000000040827d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cca6d0_0 .net8 "VGND", 0 0, L_00000000040827d0;  1 drivers, strength-aware
+L_0000000004083020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccc750_0 .net8 "VNB", 0 0, L_0000000004083020;  1 drivers, strength-aware
+L_0000000004082610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cca1d0_0 .net8 "VPB", 0 0, L_0000000004082610;  1 drivers, strength-aware
+L_00000000040831e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccb710_0 .net8 "VPWR", 0 0, L_00000000040831e0;  1 drivers, strength-aware
+v0000000003cca770_0 .net "Y", 0 0, L_000000000415e990;  alias, 1 drivers
+v0000000003ccb7b0_0 .net "and0_out", 0 0, L_000000000415dea0;  1 drivers
+v0000000003ccab30_0 .net "nor0_out_Y", 0 0, L_000000000415c540;  1 drivers
+S_0000000002cf98e0 .scope module, "sky130_fd_sc_hd__a2111oi_1" "sky130_fd_sc_hd__a2111oi_1" 4 36084;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c67398 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccecd0_0 .net "A1", 0 0, o0000000003c67398;  0 drivers
+o0000000003c673c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccda10_0 .net "A2", 0 0, o0000000003c673c8;  0 drivers
+o0000000003c673f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cce2d0_0 .net "B1", 0 0, o0000000003c673f8;  0 drivers
+o0000000003c67428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cceaf0_0 .net "C1", 0 0, o0000000003c67428;  0 drivers
+o0000000003c67458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cce870_0 .net "D1", 0 0, o0000000003c67458;  0 drivers
+L_0000000004082840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd010_0 .net8 "VGND", 0 0, L_0000000004082840;  1 drivers, strength-aware
+L_0000000004082d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cce410_0 .net8 "VNB", 0 0, L_0000000004082d10;  1 drivers, strength-aware
+L_0000000004081c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccc9d0_0 .net8 "VPB", 0 0, L_0000000004081c70;  1 drivers, strength-aware
+L_0000000004081d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cce370_0 .net8 "VPWR", 0 0, L_0000000004081d50;  1 drivers, strength-aware
+v0000000003cce190_0 .net "Y", 0 0, L_000000000415e290;  1 drivers
+S_0000000003d0a3b0 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36106, 4 35828 1, S_0000000002cf98e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415f9c0 .functor AND 1, o0000000003c67398, o0000000003c673c8, C4<1>, C4<1>;
+L_000000000415efb0 .functor NOR 1, o0000000003c673f8, o0000000003c67428, o0000000003c67458, L_000000000415f9c0;
+L_000000000415e290 .functor BUF 1, L_000000000415efb0, C4<0>, C4<0>, C4<0>;
+v0000000003ccabd0_0 .net "A1", 0 0, o0000000003c67398;  alias, 0 drivers
+v0000000003ccac70_0 .net "A2", 0 0, o0000000003c673c8;  alias, 0 drivers
+v0000000003ccae50_0 .net "B1", 0 0, o0000000003c673f8;  alias, 0 drivers
+v0000000003ccad10_0 .net "C1", 0 0, o0000000003c67428;  alias, 0 drivers
+v0000000003cccb10_0 .net "D1", 0 0, o0000000003c67458;  alias, 0 drivers
+L_0000000004082c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd470_0 .net8 "VGND", 0 0, L_0000000004082c30;  1 drivers, strength-aware
+L_0000000004082ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccea50_0 .net8 "VNB", 0 0, L_0000000004082ca0;  1 drivers, strength-aware
+L_00000000040819d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd1f0_0 .net8 "VPB", 0 0, L_00000000040819d0;  1 drivers, strength-aware
+L_0000000004082d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd510_0 .net8 "VPWR", 0 0, L_0000000004082d80;  1 drivers, strength-aware
+v0000000003cce4b0_0 .net "Y", 0 0, L_000000000415e290;  alias, 1 drivers
+v0000000003ccdd30_0 .net "and0_out", 0 0, L_000000000415f9c0;  1 drivers
+v0000000003cce230_0 .net "nor0_out_Y", 0 0, L_000000000415efb0;  1 drivers
+S_0000000002cf9a60 .scope module, "sky130_fd_sc_hd__a2111oi_2" "sky130_fd_sc_hd__a2111oi_2" 4 36336;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c678d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cced70_0 .net "A1", 0 0, o0000000003c678d8;  0 drivers
+o0000000003c67908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccd5b0_0 .net "A2", 0 0, o0000000003c67908;  0 drivers
+o0000000003c67938 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cce730_0 .net "B1", 0 0, o0000000003c67938;  0 drivers
+o0000000003c67968 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccd0b0_0 .net "C1", 0 0, o0000000003c67968;  0 drivers
+o0000000003c67998 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccd790_0 .net "D1", 0 0, o0000000003c67998;  0 drivers
+L_0000000004082a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cce690_0 .net8 "VGND", 0 0, L_0000000004082a70;  1 drivers, strength-aware
+L_0000000004083250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccdb50_0 .net8 "VNB", 0 0, L_0000000004083250;  1 drivers, strength-aware
+L_0000000004083330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cccc50_0 .net8 "VPB", 0 0, L_0000000004083330;  1 drivers, strength-aware
+L_0000000004082ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccce30_0 .net8 "VPWR", 0 0, L_0000000004082ae0;  1 drivers, strength-aware
+v0000000003cce5f0_0 .net "Y", 0 0, L_000000000415e140;  1 drivers
+S_0000000003d07fb0 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36358, 4 35828 1, S_0000000002cf9a60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415e6f0 .functor AND 1, o0000000003c678d8, o0000000003c67908, C4<1>, C4<1>;
+L_000000000415ed80 .functor NOR 1, o0000000003c67938, o0000000003c67968, o0000000003c67998, L_000000000415e6f0;
+L_000000000415e140 .functor BUF 1, L_000000000415ed80, C4<0>, C4<0>, C4<0>;
+v0000000003ccced0_0 .net "A1", 0 0, o0000000003c678d8;  alias, 0 drivers
+v0000000003ccdab0_0 .net "A2", 0 0, o0000000003c67908;  alias, 0 drivers
+v0000000003cceb90_0 .net "B1", 0 0, o0000000003c67938;  alias, 0 drivers
+v0000000003ccdbf0_0 .net "C1", 0 0, o0000000003c67968;  alias, 0 drivers
+v0000000003ccd8d0_0 .net "D1", 0 0, o0000000003c67998;  alias, 0 drivers
+L_0000000004082df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd290_0 .net8 "VGND", 0 0, L_0000000004082df0;  1 drivers, strength-aware
+L_00000000040826f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cccbb0_0 .net8 "VNB", 0 0, L_00000000040826f0;  1 drivers, strength-aware
+L_0000000004082760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccddd0_0 .net8 "VPB", 0 0, L_0000000004082760;  1 drivers, strength-aware
+L_0000000004082370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cce7d0_0 .net8 "VPWR", 0 0, L_0000000004082370;  1 drivers, strength-aware
+v0000000003ccdc90_0 .net "Y", 0 0, L_000000000415e140;  alias, 1 drivers
+v0000000003ccd830_0 .net "and0_out", 0 0, L_000000000415e6f0;  1 drivers
+v0000000003cce550_0 .net "nor0_out_Y", 0 0, L_000000000415ed80;  1 drivers
+S_0000000002cf9be0 .scope module, "sky130_fd_sc_hd__a2111oi_4" "sky130_fd_sc_hd__a2111oi_4" 4 36210;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003c67e18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cccd90_0 .net "A1", 0 0, o0000000003c67e18;  0 drivers
+o0000000003c67e48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccd650_0 .net "A2", 0 0, o0000000003c67e48;  0 drivers
+o0000000003c67e78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccd970_0 .net "B1", 0 0, o0000000003c67e78;  0 drivers
+o0000000003c67ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccdf10_0 .net "C1", 0 0, o0000000003c67ea8;  0 drivers
+o0000000003c67ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccdfb0_0 .net "D1", 0 0, o0000000003c67ed8;  0 drivers
+L_00000000040820d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cccf70_0 .net8 "VGND", 0 0, L_00000000040820d0;  1 drivers, strength-aware
+L_0000000004082b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd150_0 .net8 "VNB", 0 0, L_0000000004082b50;  1 drivers, strength-aware
+L_0000000004081b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd330_0 .net8 "VPB", 0 0, L_0000000004081b20;  1 drivers, strength-aware
+L_00000000040833a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccd3d0_0 .net8 "VPWR", 0 0, L_00000000040833a0;  1 drivers, strength-aware
+v0000000003ccd6f0_0 .net "Y", 0 0, L_000000000415fc60;  1 drivers
+S_0000000003d079b0 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36232, 4 35828 1, S_0000000002cf9be0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_000000000415f020 .functor AND 1, o0000000003c67e18, o0000000003c67e48, C4<1>, C4<1>;
+L_000000000415f090 .functor NOR 1, o0000000003c67e78, o0000000003c67ea8, o0000000003c67ed8, L_000000000415f020;
+L_000000000415fc60 .functor BUF 1, L_000000000415f090, C4<0>, C4<0>, C4<0>;
+v0000000003ccccf0_0 .net "A1", 0 0, o0000000003c67e18;  alias, 0 drivers
+v0000000003ccf090_0 .net "A2", 0 0, o0000000003c67e48;  alias, 0 drivers
+v0000000003cce910_0 .net "B1", 0 0, o0000000003c67e78;  alias, 0 drivers
+v0000000003cceff0_0 .net "C1", 0 0, o0000000003c67ea8;  alias, 0 drivers
+v0000000003cce9b0_0 .net "D1", 0 0, o0000000003c67ed8;  alias, 0 drivers
+L_0000000004083410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccec30_0 .net8 "VGND", 0 0, L_0000000004083410;  1 drivers, strength-aware
+L_0000000004082e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccde70_0 .net8 "VNB", 0 0, L_0000000004082e60;  1 drivers, strength-aware
+L_0000000004081f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccee10_0 .net8 "VPB", 0 0, L_0000000004081f10;  1 drivers, strength-aware
+L_0000000004081f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cceeb0_0 .net8 "VPWR", 0 0, L_0000000004081f80;  1 drivers, strength-aware
+v0000000003ccef50_0 .net "Y", 0 0, L_000000000415fc60;  alias, 1 drivers
+v0000000003ccc930_0 .net "and0_out", 0 0, L_000000000415f020;  1 drivers
+v0000000003ccca70_0 .net "nor0_out_Y", 0 0, L_000000000415f090;  1 drivers
+S_0000000002cf9d60 .scope module, "sky130_fd_sc_hd__a211o_1" "sky130_fd_sc_hd__a211o_1" 4 1907;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c68358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd16b0_0 .net "A1", 0 0, o0000000003c68358;  0 drivers
+o0000000003c68388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd1750_0 .net "A2", 0 0, o0000000003c68388;  0 drivers
+o0000000003c683b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd0490_0 .net "B1", 0 0, o0000000003c683b8;  0 drivers
+o0000000003c683e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd02b0_0 .net "C1", 0 0, o0000000003c683e8;  0 drivers
+L_00000000040828b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf9f0_0 .net8 "VGND", 0 0, L_00000000040828b0;  1 drivers, strength-aware
+L_0000000004081ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1430_0 .net8 "VNB", 0 0, L_0000000004081ce0;  1 drivers, strength-aware
+L_00000000040823e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0b70_0 .net8 "VPB", 0 0, L_00000000040823e0;  1 drivers, strength-aware
+L_0000000004081dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccfc70_0 .net8 "VPWR", 0 0, L_0000000004081dc0;  1 drivers, strength-aware
+v0000000003cd12f0_0 .net "X", 0 0, L_000000000415f2c0;  1 drivers
+S_0000000003d073b0 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 1927, 4 2358 1, S_0000000002cf9d60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415f720 .functor AND 1, o0000000003c68358, o0000000003c68388, C4<1>, C4<1>;
+L_000000000415e920 .functor OR 1, L_000000000415f720, o0000000003c683e8, o0000000003c683b8, C4<0>;
+L_000000000415f2c0 .functor BUF 1, L_000000000415e920, C4<0>, C4<0>, C4<0>;
+v0000000003cce050_0 .net "A1", 0 0, o0000000003c68358;  alias, 0 drivers
+v0000000003cce0f0_0 .net "A2", 0 0, o0000000003c68388;  alias, 0 drivers
+v0000000003ccfdb0_0 .net "B1", 0 0, o0000000003c683b8;  alias, 0 drivers
+v0000000003cd1390_0 .net "C1", 0 0, o0000000003c683e8;  alias, 0 drivers
+L_0000000004081e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccff90_0 .net8 "VGND", 0 0, L_0000000004081e30;  1 drivers, strength-aware
+L_0000000004082bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd00d0_0 .net8 "VNB", 0 0, L_0000000004082bc0;  1 drivers, strength-aware
+L_0000000004082ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd17f0_0 .net8 "VPB", 0 0, L_0000000004082ed0;  1 drivers, strength-aware
+L_0000000004082450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf130_0 .net8 "VPWR", 0 0, L_0000000004082450;  1 drivers, strength-aware
+v0000000003cd1250_0 .net "X", 0 0, L_000000000415f2c0;  alias, 1 drivers
+v0000000003cd1610_0 .net "and0_out", 0 0, L_000000000415f720;  1 drivers
+v0000000003cd0530_0 .net "or0_out_X", 0 0, L_000000000415e920;  1 drivers
+S_0000000002cf9ee0 .scope module, "sky130_fd_sc_hd__a211o_2" "sky130_fd_sc_hd__a211o_2" 4 2027;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c68808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccf310_0 .net "A1", 0 0, o0000000003c68808;  0 drivers
+o0000000003c68838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd1570_0 .net "A2", 0 0, o0000000003c68838;  0 drivers
+o0000000003c68868 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccfa90_0 .net "B1", 0 0, o0000000003c68868;  0 drivers
+o0000000003c68898 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccf270_0 .net "C1", 0 0, o0000000003c68898;  0 drivers
+L_00000000040824c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccfef0_0 .net8 "VGND", 0 0, L_00000000040824c0;  1 drivers, strength-aware
+L_0000000004083480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0c10_0 .net8 "VNB", 0 0, L_0000000004083480;  1 drivers, strength-aware
+L_0000000004082530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf3b0_0 .net8 "VPB", 0 0, L_0000000004082530;  1 drivers, strength-aware
+L_0000000004081ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf8b0_0 .net8 "VPWR", 0 0, L_0000000004081ea0;  1 drivers, strength-aware
+v0000000003cd0cb0_0 .net "X", 0 0, L_000000000415e610;  1 drivers
+S_0000000003d0a0b0 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 2047, 4 2358 1, S_0000000002cf9ee0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415f790 .functor AND 1, o0000000003c68808, o0000000003c68838, C4<1>, C4<1>;
+L_000000000415e1b0 .functor OR 1, L_000000000415f790, o0000000003c68898, o0000000003c68868, C4<0>;
+L_000000000415e610 .functor BUF 1, L_000000000415e1b0, C4<0>, C4<0>, C4<0>;
+v0000000003cd1890_0 .net "A1", 0 0, o0000000003c68808;  alias, 0 drivers
+v0000000003cd0350_0 .net "A2", 0 0, o0000000003c68838;  alias, 0 drivers
+v0000000003cd14d0_0 .net "B1", 0 0, o0000000003c68868;  alias, 0 drivers
+v0000000003cd0210_0 .net "C1", 0 0, o0000000003c68898;  alias, 0 drivers
+L_0000000004082920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf1d0_0 .net8 "VGND", 0 0, L_0000000004082920;  1 drivers, strength-aware
+L_00000000040818f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0990_0 .net8 "VNB", 0 0, L_00000000040818f0;  1 drivers, strength-aware
+L_0000000004082220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf4f0_0 .net8 "VPB", 0 0, L_0000000004082220;  1 drivers, strength-aware
+L_0000000004081960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0850_0 .net8 "VPWR", 0 0, L_0000000004081960;  1 drivers, strength-aware
+v0000000003ccf810_0 .net "X", 0 0, L_000000000415e610;  alias, 1 drivers
+v0000000003cd0030_0 .net "and0_out", 0 0, L_000000000415f790;  1 drivers
+v0000000003cd1110_0 .net "or0_out_X", 0 0, L_000000000415e1b0;  1 drivers
+S_0000000002843080 .scope module, "sky130_fd_sc_hd__a211o_4" "sky130_fd_sc_hd__a211o_4" 4 1787;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c68cb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd08f0_0 .net "A1", 0 0, o0000000003c68cb8;  0 drivers
+o0000000003c68ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ccfe50_0 .net "A2", 0 0, o0000000003c68ce8;  0 drivers
+o0000000003c68d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd05d0_0 .net "B1", 0 0, o0000000003c68d18;  0 drivers
+o0000000003c68d48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd0ad0_0 .net "C1", 0 0, o0000000003c68d48;  0 drivers
+L_0000000004081a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf770_0 .net8 "VGND", 0 0, L_0000000004081a40;  1 drivers, strength-aware
+L_00000000040821b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0df0_0 .net8 "VNB", 0 0, L_00000000040821b0;  1 drivers, strength-aware
+L_0000000004082300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccfb30_0 .net8 "VPB", 0 0, L_0000000004082300;  1 drivers, strength-aware
+L_0000000004082f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0710_0 .net8 "VPWR", 0 0, L_0000000004082f40;  1 drivers, strength-aware
+v0000000003ccfbd0_0 .net "X", 0 0, L_000000000415f3a0;  1 drivers
+S_0000000003d08130 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 1807, 4 2358 1, S_0000000002843080;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415e4c0 .functor AND 1, o0000000003c68cb8, o0000000003c68ce8, C4<1>, C4<1>;
+L_000000000415eed0 .functor OR 1, L_000000000415e4c0, o0000000003c68d48, o0000000003c68d18, C4<0>;
+L_000000000415f3a0 .functor BUF 1, L_000000000415eed0, C4<0>, C4<0>, C4<0>;
+v0000000003ccf450_0 .net "A1", 0 0, o0000000003c68cb8;  alias, 0 drivers
+v0000000003cd0a30_0 .net "A2", 0 0, o0000000003c68ce8;  alias, 0 drivers
+v0000000003cd0fd0_0 .net "B1", 0 0, o0000000003c68d18;  alias, 0 drivers
+v0000000003ccf590_0 .net "C1", 0 0, o0000000003c68d48;  alias, 0 drivers
+L_00000000040825a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf630_0 .net8 "VGND", 0 0, L_00000000040825a0;  1 drivers, strength-aware
+L_0000000004081ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0d50_0 .net8 "VNB", 0 0, L_0000000004081ab0;  1 drivers, strength-aware
+L_0000000004081b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ccf950_0 .net8 "VPB", 0 0, L_0000000004081b90;  1 drivers, strength-aware
+L_0000000004082fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd0f30_0 .net8 "VPWR", 0 0, L_0000000004082fb0;  1 drivers, strength-aware
+v0000000003cd03f0_0 .net "X", 0 0, L_000000000415f3a0;  alias, 1 drivers
+v0000000003cd0170_0 .net "and0_out", 0 0, L_000000000415e4c0;  1 drivers
+v0000000003ccf6d0_0 .net "or0_out_X", 0 0, L_000000000415eed0;  1 drivers
+S_0000000002843200 .scope module, "sky130_fd_sc_hd__a211oi_1" "sky130_fd_sc_hd__a211oi_1" 4 13183;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c69168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd1930_0 .net "A1", 0 0, o0000000003c69168;  0 drivers
+o0000000003c69198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd1cf0_0 .net "A2", 0 0, o0000000003c69198;  0 drivers
+o0000000003c691c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd1e30_0 .net "B1", 0 0, o0000000003c691c8;  0 drivers
+o0000000003c691f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd2970_0 .net "C1", 0 0, o0000000003c691f8;  0 drivers
+L_0000000004082a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd28d0_0 .net8 "VGND", 0 0, L_0000000004082a00;  1 drivers, strength-aware
+L_0000000004082680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2510_0 .net8 "VNB", 0 0, L_0000000004082680;  1 drivers, strength-aware
+L_0000000004081ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2e70_0 .net8 "VPB", 0 0, L_0000000004081ff0;  1 drivers, strength-aware
+L_0000000004083170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2150_0 .net8 "VPWR", 0 0, L_0000000004083170;  1 drivers, strength-aware
+v0000000003cd3230_0 .net "Y", 0 0, L_000000000415ec30;  1 drivers
+S_0000000003d09f30 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13203, 4 13634 1, S_0000000002843200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415ef40 .functor AND 1, o0000000003c69168, o0000000003c69198, C4<1>, C4<1>;
+L_000000000415eae0 .functor NOR 1, L_000000000415ef40, o0000000003c691c8, o0000000003c691f8, C4<0>;
+L_000000000415ec30 .functor BUF 1, L_000000000415eae0, C4<0>, C4<0>, C4<0>;
+v0000000003ccfd10_0 .net "A1", 0 0, o0000000003c69168;  alias, 0 drivers
+v0000000003cd0670_0 .net "A2", 0 0, o0000000003c69198;  alias, 0 drivers
+v0000000003cd07b0_0 .net "B1", 0 0, o0000000003c691c8;  alias, 0 drivers
+v0000000003cd0e90_0 .net "C1", 0 0, o0000000003c691f8;  alias, 0 drivers
+L_0000000004081c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1070_0 .net8 "VGND", 0 0, L_0000000004081c00;  1 drivers, strength-aware
+L_0000000004083090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd11b0_0 .net8 "VNB", 0 0, L_0000000004083090;  1 drivers, strength-aware
+L_0000000004082140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd39b0_0 .net8 "VPB", 0 0, L_0000000004082140;  1 drivers, strength-aware
+L_0000000004082060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1d90_0 .net8 "VPWR", 0 0, L_0000000004082060;  1 drivers, strength-aware
+v0000000003cd3190_0 .net "Y", 0 0, L_000000000415ec30;  alias, 1 drivers
+v0000000003cd2650_0 .net "and0_out", 0 0, L_000000000415ef40;  1 drivers
+v0000000003cd3370_0 .net "nor0_out_Y", 0 0, L_000000000415eae0;  1 drivers
+S_0000000002843380 .scope module, "sky130_fd_sc_hd__a211oi_2" "sky130_fd_sc_hd__a211oi_2" 4 13303;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c69618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd2ab0_0 .net "A1", 0 0, o0000000003c69618;  0 drivers
+o0000000003c69648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd3c30_0 .net "A2", 0 0, o0000000003c69648;  0 drivers
+o0000000003c69678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd3eb0_0 .net "B1", 0 0, o0000000003c69678;  0 drivers
+o0000000003c696a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd3d70_0 .net "C1", 0 0, o0000000003c696a8;  0 drivers
+L_0000000004082990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3f50_0 .net8 "VGND", 0 0, L_0000000004082990;  1 drivers, strength-aware
+L_0000000004083100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1ed0_0 .net8 "VNB", 0 0, L_0000000004083100;  1 drivers, strength-aware
+L_00000000040849f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3ff0_0 .net8 "VPB", 0 0, L_00000000040849f0;  1 drivers, strength-aware
+L_0000000004084d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4090_0 .net8 "VPWR", 0 0, L_0000000004084d00;  1 drivers, strength-aware
+v0000000003cd2b50_0 .net "Y", 0 0, L_000000000415eca0;  1 drivers
+S_0000000003d0b430 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13323, 4 13634 1, S_0000000002843380;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415e370 .functor AND 1, o0000000003c69618, o0000000003c69648, C4<1>, C4<1>;
+L_000000000415e680 .functor NOR 1, L_000000000415e370, o0000000003c69678, o0000000003c696a8, C4<0>;
+L_000000000415eca0 .functor BUF 1, L_000000000415e680, C4<0>, C4<0>, C4<0>;
+v0000000003cd2f10_0 .net "A1", 0 0, o0000000003c69618;  alias, 0 drivers
+v0000000003cd2c90_0 .net "A2", 0 0, o0000000003c69648;  alias, 0 drivers
+v0000000003cd19d0_0 .net "B1", 0 0, o0000000003c69678;  alias, 0 drivers
+v0000000003cd2a10_0 .net "C1", 0 0, o0000000003c696a8;  alias, 0 drivers
+L_0000000004084c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3e10_0 .net8 "VGND", 0 0, L_0000000004084c20;  1 drivers, strength-aware
+L_0000000004083e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3af0_0 .net8 "VNB", 0 0, L_0000000004083e90;  1 drivers, strength-aware
+L_0000000004084050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3cd0_0 .net8 "VPB", 0 0, L_0000000004084050;  1 drivers, strength-aware
+L_00000000040842f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3a50_0 .net8 "VPWR", 0 0, L_00000000040842f0;  1 drivers, strength-aware
+v0000000003cd1bb0_0 .net "Y", 0 0, L_000000000415eca0;  alias, 1 drivers
+v0000000003cd3550_0 .net "and0_out", 0 0, L_000000000415e370;  1 drivers
+v0000000003cd3b90_0 .net "nor0_out_Y", 0 0, L_000000000415e680;  1 drivers
+S_0000000002843500 .scope module, "sky130_fd_sc_hd__a211oi_4" "sky130_fd_sc_hd__a211oi_4" 4 13063;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003c69ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd3870_0 .net "A1", 0 0, o0000000003c69ac8;  0 drivers
+o0000000003c69af8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd2010_0 .net "A2", 0 0, o0000000003c69af8;  0 drivers
+o0000000003c69b28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd2790_0 .net "B1", 0 0, o0000000003c69b28;  0 drivers
+o0000000003c69b58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd3410_0 .net "C1", 0 0, o0000000003c69b58;  0 drivers
+L_00000000040848a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2fb0_0 .net8 "VGND", 0 0, L_00000000040848a0;  1 drivers, strength-aware
+L_0000000004084ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd3690_0 .net8 "VNB", 0 0, L_0000000004084ec0;  1 drivers, strength-aware
+L_0000000004083aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1c50_0 .net8 "VPB", 0 0, L_0000000004083aa0;  1 drivers, strength-aware
+L_00000000040840c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd20b0_0 .net8 "VPWR", 0 0, L_00000000040840c0;  1 drivers, strength-aware
+v0000000003cd3730_0 .net "Y", 0 0, L_000000000415ed10;  1 drivers
+S_0000000003d082b0 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13083, 4 13634 1, S_0000000002843500;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_000000000415e760 .functor AND 1, o0000000003c69ac8, o0000000003c69af8, C4<1>, C4<1>;
+L_000000000415e530 .functor NOR 1, L_000000000415e760, o0000000003c69b28, o0000000003c69b58, C4<0>;
+L_000000000415ed10 .functor BUF 1, L_000000000415e530, C4<0>, C4<0>, C4<0>;
+v0000000003cd2470_0 .net "A1", 0 0, o0000000003c69ac8;  alias, 0 drivers
+v0000000003cd1a70_0 .net "A2", 0 0, o0000000003c69af8;  alias, 0 drivers
+v0000000003cd25b0_0 .net "B1", 0 0, o0000000003c69b28;  alias, 0 drivers
+v0000000003cd34b0_0 .net "C1", 0 0, o0000000003c69b58;  alias, 0 drivers
+L_0000000004084600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2d30_0 .net8 "VGND", 0 0, L_0000000004084600;  1 drivers, strength-aware
+L_0000000004084f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2dd0_0 .net8 "VNB", 0 0, L_0000000004084f30;  1 drivers, strength-aware
+L_0000000004084c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd1b10_0 .net8 "VPB", 0 0, L_0000000004084c90;  1 drivers, strength-aware
+L_0000000004083cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd32d0_0 .net8 "VPWR", 0 0, L_0000000004083cd0;  1 drivers, strength-aware
+v0000000003cd35f0_0 .net "Y", 0 0, L_000000000415ed10;  alias, 1 drivers
+v0000000003cd1f70_0 .net "and0_out", 0 0, L_000000000415e760;  1 drivers
+v0000000003cd2bf0_0 .net "nor0_out_Y", 0 0, L_000000000415e530;  1 drivers
+S_0000000002843680 .scope module, "sky130_fd_sc_hd__a21bo_1" "sky130_fd_sc_hd__a21bo_1" 4 90993;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003c69f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5c10_0 .net "A1", 0 0, o0000000003c69f78;  0 drivers
+o0000000003c69fa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd49f0_0 .net "A2", 0 0, o0000000003c69fa8;  0 drivers
+o0000000003c69fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5210_0 .net "B1_N", 0 0, o0000000003c69fd8;  0 drivers
+L_0000000004084910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4f90_0 .net8 "VGND", 0 0, L_0000000004084910;  1 drivers, strength-aware
+L_0000000004084360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4310_0 .net8 "VNB", 0 0, L_0000000004084360;  1 drivers, strength-aware
+L_00000000040846e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd52b0_0 .net8 "VPB", 0 0, L_00000000040846e0;  1 drivers, strength-aware
+L_0000000004084de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd43b0_0 .net8 "VPWR", 0 0, L_0000000004084de0;  1 drivers, strength-aware
+v0000000003cd4630_0 .net "X", 0 0, L_000000000415f330;  1 drivers
+S_0000000003d09930 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91011, 4 91435 1, S_0000000002843680;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000415ea00 .functor NAND 1, o0000000003c69fa8, o0000000003c69f78, C4<1>, C4<1>;
+L_000000000415ee60 .functor NAND 1, o0000000003c69fd8, L_000000000415ea00, C4<1>, C4<1>;
+L_000000000415f330 .functor BUF 1, L_000000000415ee60, C4<0>, C4<0>, C4<0>;
+v0000000003cd21f0_0 .net "A1", 0 0, o0000000003c69f78;  alias, 0 drivers
+v0000000003cd3050_0 .net "A2", 0 0, o0000000003c69fa8;  alias, 0 drivers
+v0000000003cd2290_0 .net "B1_N", 0 0, o0000000003c69fd8;  alias, 0 drivers
+L_00000000040841a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2330_0 .net8 "VGND", 0 0, L_00000000040841a0;  1 drivers, strength-aware
+L_0000000004083640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd23d0_0 .net8 "VNB", 0 0, L_0000000004083640;  1 drivers, strength-aware
+L_0000000004083b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd26f0_0 .net8 "VPB", 0 0, L_0000000004083b10;  1 drivers, strength-aware
+L_00000000040836b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd2830_0 .net8 "VPWR", 0 0, L_00000000040836b0;  1 drivers, strength-aware
+v0000000003cd30f0_0 .net "X", 0 0, L_000000000415f330;  alias, 1 drivers
+v0000000003cd37d0_0 .net "nand0_out", 0 0, L_000000000415ea00;  1 drivers
+v0000000003cd3910_0 .net "nand1_out_X", 0 0, L_000000000415ee60;  1 drivers
+S_0000000002843800 .scope module, "sky130_fd_sc_hd__a21bo_4" "sky130_fd_sc_hd__a21bo_4" 4 91556;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003c6a398 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5cb0_0 .net "A1", 0 0, o0000000003c6a398;  0 drivers
+o0000000003c6a3c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5350_0 .net "A2", 0 0, o0000000003c6a3c8;  0 drivers
+o0000000003c6a3f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd4ef0_0 .net "B1_N", 0 0, o0000000003c6a3f8;  0 drivers
+L_0000000004083db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd61b0_0 .net8 "VGND", 0 0, L_0000000004083db0;  1 drivers, strength-aware
+L_0000000004085080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4590_0 .net8 "VNB", 0 0, L_0000000004085080;  1 drivers, strength-aware
+L_0000000004084440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4d10_0 .net8 "VPB", 0 0, L_0000000004084440;  1 drivers, strength-aware
+L_00000000040843d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5030_0 .net8 "VPWR", 0 0, L_00000000040843d0;  1 drivers, strength-aware
+v0000000003cd5b70_0 .net "X", 0 0, L_000000000415fb10;  1 drivers
+S_0000000003d09630 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91574, 4 91435 1, S_0000000002843800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000415f410 .functor NAND 1, o0000000003c6a3c8, o0000000003c6a398, C4<1>, C4<1>;
+L_000000000415fbf0 .functor NAND 1, o0000000003c6a3f8, L_000000000415f410, C4<1>, C4<1>;
+L_000000000415fb10 .functor BUF 1, L_000000000415fbf0, C4<0>, C4<0>, C4<0>;
+v0000000003cd44f0_0 .net "A1", 0 0, o0000000003c6a398;  alias, 0 drivers
+v0000000003cd5a30_0 .net "A2", 0 0, o0000000003c6a3c8;  alias, 0 drivers
+v0000000003cd4e50_0 .net "B1_N", 0 0, o0000000003c6a3f8;  alias, 0 drivers
+L_00000000040834f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd64d0_0 .net8 "VGND", 0 0, L_00000000040834f0;  1 drivers, strength-aware
+L_0000000004084d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6070_0 .net8 "VNB", 0 0, L_0000000004084d70;  1 drivers, strength-aware
+L_0000000004083560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd67f0_0 .net8 "VPB", 0 0, L_0000000004083560;  1 drivers, strength-aware
+L_00000000040835d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5990_0 .net8 "VPWR", 0 0, L_00000000040835d0;  1 drivers, strength-aware
+v0000000003cd5490_0 .net "X", 0 0, L_000000000415fb10;  alias, 1 drivers
+v0000000003cd4db0_0 .net "nand0_out", 0 0, L_000000000415f410;  1 drivers
+v0000000003cd62f0_0 .net "nand1_out_X", 0 0, L_000000000415fbf0;  1 drivers
+S_0000000002843980 .scope module, "sky130_fd_sc_hd__a21boi_0" "sky130_fd_sc_hd__a21boi_0" 4 12147;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003c6a7b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd53f0_0 .net "A1", 0 0, o0000000003c6a7b8;  0 drivers
+o0000000003c6a7e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5df0_0 .net "A2", 0 0, o0000000003c6a7e8;  0 drivers
+o0000000003c6a818 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd58f0_0 .net "B1_N", 0 0, o0000000003c6a818;  0 drivers
+L_0000000004084980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5e90_0 .net8 "VGND", 0 0, L_0000000004084980;  1 drivers, strength-aware
+L_00000000040839c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd46d0_0 .net8 "VNB", 0 0, L_00000000040839c0;  1 drivers, strength-aware
+L_0000000004084280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5f30_0 .net8 "VPB", 0 0, L_0000000004084280;  1 drivers, strength-aware
+L_0000000004084670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6250_0 .net8 "VPWR", 0 0, L_0000000004084670;  1 drivers, strength-aware
+v0000000003cd4810_0 .net "Y", 0 0, L_000000000415e300;  1 drivers
+S_0000000003d07b30 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 12165, 4 12024 1, S_0000000002843980;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000415f560 .functor NOT 1, o0000000003c6a818, C4<0>, C4<0>, C4<0>;
+L_000000000415ea70 .functor AND 1, o0000000003c6a7b8, o0000000003c6a7e8, C4<1>, C4<1>;
+L_000000000415f640 .functor NOR 1, L_000000000415f560, L_000000000415ea70, C4<0>, C4<0>;
+L_000000000415e300 .functor BUF 1, L_000000000415f640, C4<0>, C4<0>, C4<0>;
+v0000000003cd50d0_0 .net "A1", 0 0, o0000000003c6a7b8;  alias, 0 drivers
+v0000000003cd5670_0 .net "A2", 0 0, o0000000003c6a7e8;  alias, 0 drivers
+v0000000003cd5170_0 .net "B1_N", 0 0, o0000000003c6a818;  alias, 0 drivers
+L_00000000040847c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4450_0 .net8 "VGND", 0 0, L_00000000040847c0;  1 drivers, strength-aware
+L_0000000004083720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5530_0 .net8 "VNB", 0 0, L_0000000004083720;  1 drivers, strength-aware
+L_0000000004083d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4950_0 .net8 "VPB", 0 0, L_0000000004083d40;  1 drivers, strength-aware
+L_0000000004083790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5ad0_0 .net8 "VPWR", 0 0, L_0000000004083790;  1 drivers, strength-aware
+v0000000003cd55d0_0 .net "Y", 0 0, L_000000000415e300;  alias, 1 drivers
+v0000000003cd5fd0_0 .net "and0_out", 0 0, L_000000000415ea70;  1 drivers
+v0000000003cd6890_0 .net "b", 0 0, L_000000000415f560;  1 drivers
+v0000000003cd5d50_0 .net "nor0_out_Y", 0 0, L_000000000415f640;  1 drivers
+S_0000000002756d50 .scope module, "sky130_fd_sc_hd__a21boi_1" "sky130_fd_sc_hd__a21boi_1" 4 12262;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003c6ac08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd5850_0 .net "A1", 0 0, o0000000003c6ac08;  0 drivers
+o0000000003c6ac38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd6430_0 .net "A2", 0 0, o0000000003c6ac38;  0 drivers
+o0000000003c6ac68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd6570_0 .net "B1_N", 0 0, o0000000003c6ac68;  0 drivers
+L_0000000004083e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6750_0 .net8 "VGND", 0 0, L_0000000004083e20;  1 drivers, strength-aware
+L_00000000040844b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6610_0 .net8 "VNB", 0 0, L_00000000040844b0;  1 drivers, strength-aware
+L_0000000004084210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd66b0_0 .net8 "VPB", 0 0, L_0000000004084210;  1 drivers, strength-aware
+L_0000000004083f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd41d0_0 .net8 "VPWR", 0 0, L_0000000004083f00;  1 drivers, strength-aware
+v0000000003cd4270_0 .net "Y", 0 0, L_000000000415f100;  1 drivers
+S_0000000003d097b0 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 12280, 4 12024 1, S_0000000002756d50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000415fb80 .functor NOT 1, o0000000003c6ac68, C4<0>, C4<0>, C4<0>;
+L_000000000415edf0 .functor AND 1, o0000000003c6ac08, o0000000003c6ac38, C4<1>, C4<1>;
+L_000000000415fcd0 .functor NOR 1, L_000000000415fb80, L_000000000415edf0, C4<0>, C4<0>;
+L_000000000415f100 .functor BUF 1, L_000000000415fcd0, C4<0>, C4<0>, C4<0>;
+v0000000003cd48b0_0 .net "A1", 0 0, o0000000003c6ac08;  alias, 0 drivers
+v0000000003cd6110_0 .net "A2", 0 0, o0000000003c6ac38;  alias, 0 drivers
+v0000000003cd4130_0 .net "B1_N", 0 0, o0000000003c6ac68;  alias, 0 drivers
+L_0000000004084130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4a90_0 .net8 "VGND", 0 0, L_0000000004084130;  1 drivers, strength-aware
+L_0000000004083800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6390_0 .net8 "VNB", 0 0, L_0000000004083800;  1 drivers, strength-aware
+L_0000000004084750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd4b30_0 .net8 "VPB", 0 0, L_0000000004084750;  1 drivers, strength-aware
+L_0000000004084520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd5710_0 .net8 "VPWR", 0 0, L_0000000004084520;  1 drivers, strength-aware
+v0000000003cd4770_0 .net "Y", 0 0, L_000000000415f100;  alias, 1 drivers
+v0000000003cd57b0_0 .net "and0_out", 0 0, L_000000000415edf0;  1 drivers
+v0000000003cd4bd0_0 .net "b", 0 0, L_000000000415fb80;  1 drivers
+v0000000003cd4c70_0 .net "nor0_out_Y", 0 0, L_000000000415fcd0;  1 drivers
+S_00000000027577d0 .scope module, "sky130_fd_sc_hd__a21boi_4" "sky130_fd_sc_hd__a21boi_4" 4 11691;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003c6b058 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd82d0_0 .net "A1", 0 0, o0000000003c6b058;  0 drivers
+o0000000003c6b088 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd7510_0 .net "A2", 0 0, o0000000003c6b088;  0 drivers
+o0000000003c6b0b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd7e70_0 .net "B1_N", 0 0, o0000000003c6b0b8;  0 drivers
+L_0000000004084ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd78d0_0 .net8 "VGND", 0 0, L_0000000004084ad0;  1 drivers, strength-aware
+L_0000000004084a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd70b0_0 .net8 "VNB", 0 0, L_0000000004084a60;  1 drivers, strength-aware
+L_0000000004084830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7c90_0 .net8 "VPB", 0 0, L_0000000004084830;  1 drivers, strength-aware
+L_0000000004084fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6a70_0 .net8 "VPWR", 0 0, L_0000000004084fa0;  1 drivers, strength-aware
+v0000000003cd8e10_0 .net "Y", 0 0, L_000000000415f6b0;  1 drivers
+S_0000000003d08eb0 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11709, 4 12024 1, S_00000000027577d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_000000000415eb50 .functor NOT 1, o0000000003c6b0b8, C4<0>, C4<0>, C4<0>;
+L_000000000415f170 .functor AND 1, o0000000003c6b058, o0000000003c6b088, C4<1>, C4<1>;
+L_000000000415e7d0 .functor NOR 1, L_000000000415eb50, L_000000000415f170, C4<0>, C4<0>;
+L_000000000415f6b0 .functor BUF 1, L_000000000415e7d0, C4<0>, C4<0>, C4<0>;
+v0000000003cd8d70_0 .net "A1", 0 0, o0000000003c6b058;  alias, 0 drivers
+v0000000003cd8690_0 .net "A2", 0 0, o0000000003c6b088;  alias, 0 drivers
+v0000000003cd8550_0 .net "B1_N", 0 0, o0000000003c6b0b8;  alias, 0 drivers
+L_0000000004083f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8cd0_0 .net8 "VGND", 0 0, L_0000000004083f70;  1 drivers, strength-aware
+L_0000000004083fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd76f0_0 .net8 "VNB", 0 0, L_0000000004083fe0;  1 drivers, strength-aware
+L_0000000004084b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd89b0_0 .net8 "VPB", 0 0, L_0000000004084b40;  1 drivers, strength-aware
+L_0000000004084bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6d90_0 .net8 "VPWR", 0 0, L_0000000004084bb0;  1 drivers, strength-aware
+v0000000003cd8190_0 .net "Y", 0 0, L_000000000415f6b0;  alias, 1 drivers
+v0000000003cd8230_0 .net "and0_out", 0 0, L_000000000415f170;  1 drivers
+v0000000003cd8370_0 .net "b", 0 0, L_000000000415eb50;  1 drivers
+v0000000003cd7790_0 .net "nor0_out_Y", 0 0, L_000000000415e7d0;  1 drivers
+S_0000000002757ad0 .scope module, "sky130_fd_sc_hd__a21o_1" "sky130_fd_sc_hd__a21o_1" 4 46535;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003c6b4a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd8050_0 .net "A1", 0 0, o0000000003c6b4a8;  0 drivers
+o0000000003c6b4d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd7ab0_0 .net "A2", 0 0, o0000000003c6b4d8;  0 drivers
+o0000000003c6b508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd8af0_0 .net "B1", 0 0, o0000000003c6b508;  0 drivers
+L_0000000004084590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6b10_0 .net8 "VGND", 0 0, L_0000000004084590;  1 drivers, strength-aware
+L_0000000004085010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7bf0_0 .net8 "VNB", 0 0, L_0000000004085010;  1 drivers, strength-aware
+L_0000000004084e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8c30_0 .net8 "VPB", 0 0, L_0000000004084e50;  1 drivers, strength-aware
+L_0000000004083870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd71f0_0 .net8 "VPWR", 0 0, L_0000000004083870;  1 drivers, strength-aware
+v0000000003cd7470_0 .net "X", 0 0, L_000000000415e5a0;  1 drivers
+S_0000000003d076b0 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46553, 4 46415 1, S_0000000002757ad0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415ebc0 .functor AND 1, o0000000003c6b4a8, o0000000003c6b4d8, C4<1>, C4<1>;
+L_000000000415e840 .functor OR 1, L_000000000415ebc0, o0000000003c6b508, C4<0>, C4<0>;
+L_000000000415e5a0 .functor BUF 1, L_000000000415e840, C4<0>, C4<0>, C4<0>;
+v0000000003cd8b90_0 .net "A1", 0 0, o0000000003c6b4a8;  alias, 0 drivers
+v0000000003cd7f10_0 .net "A2", 0 0, o0000000003c6b4d8;  alias, 0 drivers
+v0000000003cd7d30_0 .net "B1", 0 0, o0000000003c6b508;  alias, 0 drivers
+L_00000000040838e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6930_0 .net8 "VGND", 0 0, L_00000000040838e0;  1 drivers, strength-aware
+L_0000000004083950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8a50_0 .net8 "VNB", 0 0, L_0000000004083950;  1 drivers, strength-aware
+L_0000000004083a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8eb0_0 .net8 "VPB", 0 0, L_0000000004083a30;  1 drivers, strength-aware
+L_0000000004083b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7dd0_0 .net8 "VPWR", 0 0, L_0000000004083b80;  1 drivers, strength-aware
+v0000000003cd69d0_0 .net "X", 0 0, L_000000000415e5a0;  alias, 1 drivers
+v0000000003cd85f0_0 .net "and0_out", 0 0, L_000000000415ebc0;  1 drivers
+v0000000003cd7fb0_0 .net "or0_out_X", 0 0, L_000000000415e840;  1 drivers
+S_0000000002757050 .scope module, "sky130_fd_sc_hd__a21o_4" "sky130_fd_sc_hd__a21o_4" 4 46649;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003c6b8c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd7830_0 .net "A1", 0 0, o0000000003c6b8c8;  0 drivers
+o0000000003c6b8f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd7970_0 .net "A2", 0 0, o0000000003c6b8f8;  0 drivers
+o0000000003c6b928 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd6ed0_0 .net "B1", 0 0, o0000000003c6b928;  0 drivers
+L_0000000004083bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6bb0_0 .net8 "VGND", 0 0, L_0000000004083bf0;  1 drivers, strength-aware
+L_0000000004083c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6c50_0 .net8 "VNB", 0 0, L_0000000004083c60;  1 drivers, strength-aware
+L_0000000004085e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7150_0 .net8 "VPB", 0 0, L_0000000004085e10;  1 drivers, strength-aware
+L_00000000040858d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8730_0 .net8 "VPWR", 0 0, L_00000000040858d0;  1 drivers, strength-aware
+v0000000003cd7a10_0 .net "X", 0 0, L_000000000415e220;  1 drivers
+S_0000000003d0acb0 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46667, 4 46415 1, S_0000000002757050;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415f800 .functor AND 1, o0000000003c6b8c8, o0000000003c6b8f8, C4<1>, C4<1>;
+L_000000000415e3e0 .functor OR 1, L_000000000415f800, o0000000003c6b928, C4<0>, C4<0>;
+L_000000000415e220 .functor BUF 1, L_000000000415e3e0, C4<0>, C4<0>, C4<0>;
+v0000000003cd8410_0 .net "A1", 0 0, o0000000003c6b8c8;  alias, 0 drivers
+v0000000003cd8f50_0 .net "A2", 0 0, o0000000003c6b8f8;  alias, 0 drivers
+v0000000003cd6e30_0 .net "B1", 0 0, o0000000003c6b928;  alias, 0 drivers
+L_00000000040857f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd8ff0_0 .net8 "VGND", 0 0, L_00000000040857f0;  1 drivers, strength-aware
+L_00000000040851d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9090_0 .net8 "VNB", 0 0, L_00000000040851d0;  1 drivers, strength-aware
+L_0000000004085a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd6cf0_0 .net8 "VPB", 0 0, L_0000000004085a20;  1 drivers, strength-aware
+L_0000000004085780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd80f0_0 .net8 "VPWR", 0 0, L_0000000004085780;  1 drivers, strength-aware
+v0000000003cd7010_0 .net "X", 0 0, L_000000000415e220;  alias, 1 drivers
+v0000000003cd84b0_0 .net "and0_out", 0 0, L_000000000415f800;  1 drivers
+v0000000003cd8910_0 .net "or0_out_X", 0 0, L_000000000415e3e0;  1 drivers
+S_0000000002756ed0 .scope module, "sky130_fd_sc_hd__a21oi_1" "sky130_fd_sc_hd__a21oi_1" 4 51675;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003c6bce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdad50_0 .net "A1", 0 0, o0000000003c6bce8;  0 drivers
+o0000000003c6bd18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cda670_0 .net "A2", 0 0, o0000000003c6bd18;  0 drivers
+o0000000003c6bd48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdb610_0 .net "B1", 0 0, o0000000003c6bd48;  0 drivers
+L_00000000040867b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd99f0_0 .net8 "VGND", 0 0, L_00000000040867b0;  1 drivers, strength-aware
+L_0000000004086350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd93b0_0 .net8 "VNB", 0 0, L_0000000004086350;  1 drivers, strength-aware
+L_0000000004085b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9db0_0 .net8 "VPB", 0 0, L_0000000004085b70;  1 drivers, strength-aware
+L_0000000004086740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdb1b0_0 .net8 "VPWR", 0 0, L_0000000004086740;  1 drivers, strength-aware
+v0000000003cdb390_0 .net "Y", 0 0, L_000000000415f480;  1 drivers
+S_0000000003d0a6b0 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51693, 4 51555 1, S_0000000002756ed0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415f1e0 .functor AND 1, o0000000003c6bce8, o0000000003c6bd18, C4<1>, C4<1>;
+L_000000000415f250 .functor NOR 1, o0000000003c6bd48, L_000000000415f1e0, C4<0>, C4<0>;
+L_000000000415f480 .functor BUF 1, L_000000000415f250, C4<0>, C4<0>, C4<0>;
+v0000000003cd87d0_0 .net "A1", 0 0, o0000000003c6bce8;  alias, 0 drivers
+v0000000003cd6f70_0 .net "A2", 0 0, o0000000003c6bd18;  alias, 0 drivers
+v0000000003cd8870_0 .net "B1", 0 0, o0000000003c6bd48;  alias, 0 drivers
+L_0000000004085be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7290_0 .net8 "VGND", 0 0, L_0000000004085be0;  1 drivers, strength-aware
+L_0000000004086200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd7330_0 .net8 "VNB", 0 0, L_0000000004086200;  1 drivers, strength-aware
+L_0000000004085710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd73d0_0 .net8 "VPB", 0 0, L_0000000004085710;  1 drivers, strength-aware
+L_0000000004085630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd75b0_0 .net8 "VPWR", 0 0, L_0000000004085630;  1 drivers, strength-aware
+v0000000003cd7b50_0 .net "Y", 0 0, L_000000000415f480;  alias, 1 drivers
+v0000000003cd7650_0 .net "and0_out", 0 0, L_000000000415f1e0;  1 drivers
+v0000000003cda170_0 .net "nor0_out_Y", 0 0, L_000000000415f250;  1 drivers
+S_0000000002757950 .scope module, "sky130_fd_sc_hd__a21oi_4" "sky130_fd_sc_hd__a21oi_4" 4 51789;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003c6c108 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdac10_0 .net "A1", 0 0, o0000000003c6c108;  0 drivers
+o0000000003c6c138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdb110_0 .net "A2", 0 0, o0000000003c6c138;  0 drivers
+o0000000003c6c168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cda3f0_0 .net "B1", 0 0, o0000000003c6c168;  0 drivers
+L_0000000004085940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdacb0_0 .net8 "VGND", 0 0, L_0000000004085940;  1 drivers, strength-aware
+L_0000000004085400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9310_0 .net8 "VNB", 0 0, L_0000000004085400;  1 drivers, strength-aware
+L_0000000004085a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdb430_0 .net8 "VPB", 0 0, L_0000000004085a90;  1 drivers, strength-aware
+L_00000000040862e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9770_0 .net8 "VPWR", 0 0, L_00000000040862e0;  1 drivers, strength-aware
+v0000000003cdae90_0 .net "Y", 0 0, L_000000000415f4f0;  1 drivers
+S_0000000003d0cf30 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51807, 4 51555 1, S_0000000002757950;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_000000000415e450 .functor AND 1, o0000000003c6c108, o0000000003c6c138, C4<1>, C4<1>;
+L_000000000415e8b0 .functor NOR 1, o0000000003c6c168, L_000000000415e450, C4<0>, C4<0>;
+L_000000000415f4f0 .functor BUF 1, L_000000000415e8b0, C4<0>, C4<0>, C4<0>;
+v0000000003cdafd0_0 .net "A1", 0 0, o0000000003c6c108;  alias, 0 drivers
+v0000000003cda530_0 .net "A2", 0 0, o0000000003c6c138;  alias, 0 drivers
+v0000000003cda5d0_0 .net "B1", 0 0, o0000000003c6c168;  alias, 0 drivers
+L_0000000004085320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdb570_0 .net8 "VGND", 0 0, L_0000000004085320;  1 drivers, strength-aware
+L_00000000040859b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cda2b0_0 .net8 "VNB", 0 0, L_00000000040859b0;  1 drivers, strength-aware
+L_0000000004085390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdb4d0_0 .net8 "VPB", 0 0, L_0000000004085390;  1 drivers, strength-aware
+L_00000000040869e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9590_0 .net8 "VPWR", 0 0, L_00000000040869e0;  1 drivers, strength-aware
+v0000000003cd9f90_0 .net "Y", 0 0, L_000000000415f4f0;  alias, 1 drivers
+v0000000003cdaa30_0 .net "and0_out", 0 0, L_000000000415e450;  1 drivers
+v0000000003cdb250_0 .net "nor0_out_Y", 0 0, L_000000000415e8b0;  1 drivers
+S_00000000027571d0 .scope module, "sky130_fd_sc_hd__a221o_1" "sky130_fd_sc_hd__a221o_1" 4 98119;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c6c528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cda0d0_0 .net "A1", 0 0, o0000000003c6c528;  0 drivers
+o0000000003c6c558 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdb7f0_0 .net "A2", 0 0, o0000000003c6c558;  0 drivers
+o0000000003c6c588 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cda850_0 .net "B1", 0 0, o0000000003c6c588;  0 drivers
+o0000000003c6c5b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd9630_0 .net "B2", 0 0, o0000000003c6c5b8;  0 drivers
+o0000000003c6c5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cda210_0 .net "C1", 0 0, o0000000003c6c5e8;  0 drivers
+L_00000000040850f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9c70_0 .net8 "VGND", 0 0, L_00000000040850f0;  1 drivers, strength-aware
+L_0000000004085d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cda350_0 .net8 "VNB", 0 0, L_0000000004085d30;  1 drivers, strength-aware
+L_0000000004086580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9a90_0 .net8 "VPB", 0 0, L_0000000004086580;  1 drivers, strength-aware
+L_00000000040852b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9ef0_0 .net8 "VPWR", 0 0, L_00000000040852b0;  1 drivers, strength-aware
+v0000000003cdb890_0 .net "X", 0 0, L_000000000415f8e0;  1 drivers
+S_0000000003d0afb0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98141, 4 97861 1, S_00000000027571d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000415f5d0 .functor AND 1, o0000000003c6c588, o0000000003c6c5b8, C4<1>, C4<1>;
+L_000000000415f870 .functor AND 1, o0000000003c6c528, o0000000003c6c558, C4<1>, C4<1>;
+L_000000000415fa30 .functor OR 1, L_000000000415f870, L_000000000415f5d0, o0000000003c6c5e8, C4<0>;
+L_000000000415f8e0 .functor BUF 1, L_000000000415fa30, C4<0>, C4<0>, C4<0>;
+v0000000003cda490_0 .net "A1", 0 0, o0000000003c6c528;  alias, 0 drivers
+v0000000003cd9450_0 .net "A2", 0 0, o0000000003c6c558;  alias, 0 drivers
+v0000000003cdadf0_0 .net "B1", 0 0, o0000000003c6c588;  alias, 0 drivers
+v0000000003cda710_0 .net "B2", 0 0, o0000000003c6c5b8;  alias, 0 drivers
+v0000000003cdb070_0 .net "C1", 0 0, o0000000003c6c5e8;  alias, 0 drivers
+L_0000000004086890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cda7b0_0 .net8 "VGND", 0 0, L_0000000004086890;  1 drivers, strength-aware
+L_0000000004086510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cda030_0 .net8 "VNB", 0 0, L_0000000004086510;  1 drivers, strength-aware
+L_0000000004085b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdaad0_0 .net8 "VPB", 0 0, L_0000000004085b00;  1 drivers, strength-aware
+L_0000000004085470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdb2f0_0 .net8 "VPWR", 0 0, L_0000000004085470;  1 drivers, strength-aware
+v0000000003cd9810_0 .net "X", 0 0, L_000000000415f8e0;  alias, 1 drivers
+v0000000003cdaf30_0 .net "and0_out", 0 0, L_000000000415f5d0;  1 drivers
+v0000000003cdb6b0_0 .net "and1_out", 0 0, L_000000000415f870;  1 drivers
+v0000000003cdb750_0 .net "or0_out_X", 0 0, L_000000000415fa30;  1 drivers
+S_00000000027574d0 .scope module, "sky130_fd_sc_hd__a221o_4" "sky130_fd_sc_hd__a221o_4" 4 97993;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c6ca98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cd9e50_0 .net "A1", 0 0, o0000000003c6ca98;  0 drivers
+o0000000003c6cac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdd550_0 .net "A2", 0 0, o0000000003c6cac8;  0 drivers
+o0000000003c6caf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdd5f0_0 .net "B1", 0 0, o0000000003c6caf8;  0 drivers
+o0000000003c6cb28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdd230_0 .net "B2", 0 0, o0000000003c6cb28;  0 drivers
+o0000000003c6cb58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdd870_0 .net "C1", 0 0, o0000000003c6cb58;  0 drivers
+L_0000000004086270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdd2d0_0 .net8 "VGND", 0 0, L_0000000004086270;  1 drivers, strength-aware
+L_0000000004085c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdd690_0 .net8 "VNB", 0 0, L_0000000004085c50;  1 drivers, strength-aware
+L_0000000004085160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cddcd0_0 .net8 "VPB", 0 0, L_0000000004085160;  1 drivers, strength-aware
+L_00000000040855c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdbd90_0 .net8 "VPWR", 0 0, L_00000000040855c0;  1 drivers, strength-aware
+v0000000003cddff0_0 .net "X", 0 0, L_00000000041612b0;  1 drivers
+S_0000000003d0bbb0 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98015, 4 97861 1, S_00000000027574d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_000000000415f950 .functor AND 1, o0000000003c6caf8, o0000000003c6cb28, C4<1>, C4<1>;
+L_000000000415faa0 .functor AND 1, o0000000003c6ca98, o0000000003c6cac8, C4<1>, C4<1>;
+L_00000000041606e0 .functor OR 1, L_000000000415faa0, L_000000000415f950, o0000000003c6cb58, C4<0>;
+L_00000000041612b0 .functor BUF 1, L_00000000041606e0, C4<0>, C4<0>, C4<0>;
+v0000000003cda990_0 .net "A1", 0 0, o0000000003c6ca98;  alias, 0 drivers
+v0000000003cdab70_0 .net "A2", 0 0, o0000000003c6cac8;  alias, 0 drivers
+v0000000003cda8f0_0 .net "B1", 0 0, o0000000003c6caf8;  alias, 0 drivers
+v0000000003cd9130_0 .net "B2", 0 0, o0000000003c6cb28;  alias, 0 drivers
+v0000000003cd91d0_0 .net "C1", 0 0, o0000000003c6cb58;  alias, 0 drivers
+L_00000000040866d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd9270_0 .net8 "VGND", 0 0, L_00000000040866d0;  1 drivers, strength-aware
+L_0000000004086820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cd94f0_0 .net8 "VNB", 0 0, L_0000000004086820;  1 drivers, strength-aware
+L_0000000004086040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd96d0_0 .net8 "VPB", 0 0, L_0000000004086040;  1 drivers, strength-aware
+L_0000000004086ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cd98b0_0 .net8 "VPWR", 0 0, L_0000000004086ac0;  1 drivers, strength-aware
+v0000000003cd9950_0 .net "X", 0 0, L_00000000041612b0;  alias, 1 drivers
+v0000000003cd9b30_0 .net "and0_out", 0 0, L_000000000415f950;  1 drivers
+v0000000003cd9bd0_0 .net "and1_out", 0 0, L_000000000415faa0;  1 drivers
+v0000000003cd9d10_0 .net "or0_out_X", 0 0, L_00000000041606e0;  1 drivers
+S_0000000002757350 .scope module, "sky130_fd_sc_hd__a221oi_1" "sky130_fd_sc_hd__a221oi_1" 4 2612;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c6d008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdd7d0_0 .net "A1", 0 0, o0000000003c6d008;  0 drivers
+o0000000003c6d038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdcd30_0 .net "A2", 0 0, o0000000003c6d038;  0 drivers
+o0000000003c6d068 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdc970_0 .net "B1", 0 0, o0000000003c6d068;  0 drivers
+o0000000003c6d098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdda50_0 .net "B2", 0 0, o0000000003c6d098;  0 drivers
+o0000000003c6d0c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdc0b0_0 .net "C1", 0 0, o0000000003c6d0c8;  0 drivers
+L_0000000004085f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cddaf0_0 .net8 "VGND", 0 0, L_0000000004085f60;  1 drivers, strength-aware
+L_0000000004085cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cddd70_0 .net8 "VNB", 0 0, L_0000000004085cc0;  1 drivers, strength-aware
+L_00000000040864a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdd410_0 .net8 "VPB", 0 0, L_00000000040864a0;  1 drivers, strength-aware
+L_0000000004085da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc010_0 .net8 "VPWR", 0 0, L_0000000004085da0;  1 drivers, strength-aware
+v0000000003cdbcf0_0 .net "Y", 0 0, L_00000000041618d0;  1 drivers
+S_0000000003d08430 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2634, 4 3084 1, S_0000000002757350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004161710 .functor AND 1, o0000000003c6d068, o0000000003c6d098, C4<1>, C4<1>;
+L_0000000004161320 .functor AND 1, o0000000003c6d008, o0000000003c6d038, C4<1>, C4<1>;
+L_000000000415fe20 .functor NOR 1, L_0000000004161710, o0000000003c6d0c8, L_0000000004161320, C4<0>;
+L_00000000041618d0 .functor BUF 1, L_000000000415fe20, C4<0>, C4<0>, C4<0>;
+v0000000003cdd910_0 .net "A1", 0 0, o0000000003c6d008;  alias, 0 drivers
+v0000000003cdcbf0_0 .net "A2", 0 0, o0000000003c6d038;  alias, 0 drivers
+v0000000003cdd4b0_0 .net "B1", 0 0, o0000000003c6d068;  alias, 0 drivers
+v0000000003cdc6f0_0 .net "B2", 0 0, o0000000003c6d098;  alias, 0 drivers
+v0000000003cddb90_0 .net "C1", 0 0, o0000000003c6d0c8;  alias, 0 drivers
+L_0000000004085e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc1f0_0 .net8 "VGND", 0 0, L_0000000004085e80;  1 drivers, strength-aware
+L_0000000004086900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdd9b0_0 .net8 "VNB", 0 0, L_0000000004086900;  1 drivers, strength-aware
+L_0000000004086b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdbed0_0 .net8 "VPB", 0 0, L_0000000004086b30;  1 drivers, strength-aware
+L_0000000004085240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdd370_0 .net8 "VPWR", 0 0, L_0000000004085240;  1 drivers, strength-aware
+v0000000003cdd730_0 .net "Y", 0 0, L_00000000041618d0;  alias, 1 drivers
+v0000000003cdd0f0_0 .net "and0_out", 0 0, L_0000000004161710;  1 drivers
+v0000000003cdcc90_0 .net "and1_out", 0 0, L_0000000004161320;  1 drivers
+v0000000003cdc8d0_0 .net "nor0_out_Y", 0 0, L_000000000415fe20;  1 drivers
+S_0000000002757650 .scope module, "sky130_fd_sc_hd__a221oi_4" "sky130_fd_sc_hd__a221oi_4" 4 2738;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c6d578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cddf50_0 .net "A1", 0 0, o0000000003c6d578;  0 drivers
+o0000000003c6d5a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdb930_0 .net "A2", 0 0, o0000000003c6d5a8;  0 drivers
+o0000000003c6d5d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdcb50_0 .net "B1", 0 0, o0000000003c6d5d8;  0 drivers
+o0000000003c6d608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdc790_0 .net "B2", 0 0, o0000000003c6d608;  0 drivers
+o0000000003c6d638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdb9d0_0 .net "C1", 0 0, o0000000003c6d638;  0 drivers
+L_00000000040854e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc150_0 .net8 "VGND", 0 0, L_00000000040854e0;  1 drivers, strength-aware
+L_0000000004086ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdba70_0 .net8 "VNB", 0 0, L_0000000004086ba0;  1 drivers, strength-aware
+L_00000000040856a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdbb10_0 .net8 "VPB", 0 0, L_00000000040856a0;  1 drivers, strength-aware
+L_0000000004085860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdca10_0 .net8 "VPWR", 0 0, L_0000000004085860;  1 drivers, strength-aware
+v0000000003cdce70_0 .net "Y", 0 0, L_0000000004160bb0;  1 drivers
+S_0000000003d09c30 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2760, 4 3084 1, S_0000000002757650;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004160980 .functor AND 1, o0000000003c6d5d8, o0000000003c6d608, C4<1>, C4<1>;
+L_0000000004160b40 .functor AND 1, o0000000003c6d578, o0000000003c6d5a8, C4<1>, C4<1>;
+L_0000000004160050 .functor NOR 1, L_0000000004160980, o0000000003c6d638, L_0000000004160b40, C4<0>;
+L_0000000004160bb0 .functor BUF 1, L_0000000004160050, C4<0>, C4<0>, C4<0>;
+v0000000003cdd050_0 .net "A1", 0 0, o0000000003c6d578;  alias, 0 drivers
+v0000000003cdc650_0 .net "A2", 0 0, o0000000003c6d5a8;  alias, 0 drivers
+v0000000003cdc830_0 .net "B1", 0 0, o0000000003c6d5d8;  alias, 0 drivers
+v0000000003cdd190_0 .net "B2", 0 0, o0000000003c6d608;  alias, 0 drivers
+v0000000003cdbe30_0 .net "C1", 0 0, o0000000003c6d638;  alias, 0 drivers
+L_0000000004086c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cddc30_0 .net8 "VGND", 0 0, L_0000000004086c10;  1 drivers, strength-aware
+L_0000000004086970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdbf70_0 .net8 "VNB", 0 0, L_0000000004086970;  1 drivers, strength-aware
+L_0000000004085ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdcf10_0 .net8 "VPB", 0 0, L_0000000004085ef0;  1 drivers, strength-aware
+L_0000000004086a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdde10_0 .net8 "VPWR", 0 0, L_0000000004086a50;  1 drivers, strength-aware
+v0000000003cdcab0_0 .net "Y", 0 0, L_0000000004160bb0;  alias, 1 drivers
+v0000000003cde090_0 .net "and0_out", 0 0, L_0000000004160980;  1 drivers
+v0000000003cddeb0_0 .net "and1_out", 0 0, L_0000000004160b40;  1 drivers
+v0000000003cdcdd0_0 .net "nor0_out_Y", 0 0, L_0000000004160050;  1 drivers
+S_00000000029eb8d0 .scope module, "sky130_fd_sc_hd__a222oi_1" "sky130_fd_sc_hd__a222oi_1" 4 68369;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+    .port_info 6 /INPUT 1 "C2"
+o0000000003c6dae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdfd50_0 .net "A1", 0 0, o0000000003c6dae8;  0 drivers
+o0000000003c6db18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdf670_0 .net "A2", 0 0, o0000000003c6db18;  0 drivers
+o0000000003c6db48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce0610_0 .net "B1", 0 0, o0000000003c6db48;  0 drivers
+o0000000003c6db78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cde9f0_0 .net "B2", 0 0, o0000000003c6db78;  0 drivers
+o0000000003c6dba8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cde3b0_0 .net "C1", 0 0, o0000000003c6dba8;  0 drivers
+o0000000003c6dbd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdedb0_0 .net "C2", 0 0, o0000000003c6dbd8;  0 drivers
+L_0000000004085550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce01b0_0 .net8 "VGND", 0 0, L_0000000004085550;  1 drivers, strength-aware
+L_0000000004085fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdf5d0_0 .net8 "VNB", 0 0, L_0000000004085fd0;  1 drivers, strength-aware
+L_00000000040865f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdffd0_0 .net8 "VPB", 0 0, L_00000000040865f0;  1 drivers, strength-aware
+L_00000000040860b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cde450_0 .net8 "VPWR", 0 0, L_00000000040860b0;  1 drivers, strength-aware
+v0000000003cdee50_0 .net "Y", 0 0, L_000000000415fe90;  1 drivers
+S_0000000003d07cb0 .scope module, "base" "sky130_fd_sc_hd__a222oi" 4 68393, 4 68230 1, S_00000000029eb8d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+    .port_info 6 /INPUT 1 "C2"
+L_0000000004161080 .functor NAND 1, o0000000003c6db18, o0000000003c6dae8, C4<1>, C4<1>;
+L_0000000004161780 .functor NAND 1, o0000000003c6db78, o0000000003c6db48, C4<1>, C4<1>;
+L_0000000004160360 .functor NAND 1, o0000000003c6dbd8, o0000000003c6dba8, C4<1>, C4<1>;
+L_00000000041610f0 .functor AND 1, L_0000000004161080, L_0000000004161780, L_0000000004160360, C4<1>;
+L_000000000415fe90 .functor BUF 1, L_00000000041610f0, C4<0>, C4<0>, C4<0>;
+v0000000003cdbbb0_0 .net "A1", 0 0, o0000000003c6dae8;  alias, 0 drivers
+v0000000003cdcfb0_0 .net "A2", 0 0, o0000000003c6db18;  alias, 0 drivers
+v0000000003cdc510_0 .net "B1", 0 0, o0000000003c6db48;  alias, 0 drivers
+v0000000003cdbc50_0 .net "B2", 0 0, o0000000003c6db78;  alias, 0 drivers
+v0000000003cdc290_0 .net "C1", 0 0, o0000000003c6dba8;  alias, 0 drivers
+v0000000003cdc330_0 .net "C2", 0 0, o0000000003c6dbd8;  alias, 0 drivers
+L_0000000004086120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc3d0_0 .net8 "VGND", 0 0, L_0000000004086120;  1 drivers, strength-aware
+L_00000000040863c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc470_0 .net8 "VNB", 0 0, L_00000000040863c0;  1 drivers, strength-aware
+L_0000000004086430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdc5b0_0 .net8 "VPB", 0 0, L_0000000004086430;  1 drivers, strength-aware
+L_0000000004086190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0390_0 .net8 "VPWR", 0 0, L_0000000004086190;  1 drivers, strength-aware
+v0000000003cdef90_0 .net "Y", 0 0, L_000000000415fe90;  alias, 1 drivers
+v0000000003cdf990_0 .net "and0_out_Y", 0 0, L_00000000041610f0;  1 drivers
+v0000000003cdf490_0 .net "nand0_out", 0 0, L_0000000004161080;  1 drivers
+v0000000003cdf0d0_0 .net "nand1_out", 0 0, L_0000000004161780;  1 drivers
+v0000000003cdec70_0 .net "nand2_out", 0 0, L_0000000004160360;  1 drivers
+S_00000000029eb5d0 .scope module, "sky130_fd_sc_hd__a22o_1" "sky130_fd_sc_hd__a22o_1" 4 92137;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6e118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cde270_0 .net "A1", 0 0, o0000000003c6e118;  0 drivers
+o0000000003c6e148 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce0070_0 .net "A2", 0 0, o0000000003c6e148;  0 drivers
+o0000000003c6e178 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdf7b0_0 .net "B1", 0 0, o0000000003c6e178;  0 drivers
+o0000000003c6e1a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdf850_0 .net "B2", 0 0, o0000000003c6e1a8;  0 drivers
+L_0000000004086660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0750_0 .net8 "VGND", 0 0, L_0000000004086660;  1 drivers, strength-aware
+L_0000000004086c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdf350_0 .net8 "VNB", 0 0, L_0000000004086c80;  1 drivers, strength-aware
+L_00000000040875b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce04d0_0 .net8 "VPB", 0 0, L_00000000040875b0;  1 drivers, strength-aware
+L_0000000004087c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cde6d0_0 .net8 "VPWR", 0 0, L_0000000004087c40;  1 drivers, strength-aware
+v0000000003cdf210_0 .net "X", 0 0, L_00000000041615c0;  1 drivers
+S_0000000003d0cdb0 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92157, 4 91890 1, S_00000000029eb5d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041601a0 .functor AND 1, o0000000003c6e178, o0000000003c6e1a8, C4<1>, C4<1>;
+L_0000000004160c20 .functor AND 1, o0000000003c6e118, o0000000003c6e148, C4<1>, C4<1>;
+L_000000000415ff00 .functor OR 1, L_0000000004160c20, L_00000000041601a0, C4<0>, C4<0>;
+L_00000000041615c0 .functor BUF 1, L_000000000415ff00, C4<0>, C4<0>, C4<0>;
+v0000000003cdf170_0 .net "A1", 0 0, o0000000003c6e118;  alias, 0 drivers
+v0000000003cdf3f0_0 .net "A2", 0 0, o0000000003c6e148;  alias, 0 drivers
+v0000000003cde130_0 .net "B1", 0 0, o0000000003c6e178;  alias, 0 drivers
+v0000000003cded10_0 .net "B2", 0 0, o0000000003c6e1a8;  alias, 0 drivers
+L_0000000004087a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdf710_0 .net8 "VGND", 0 0, L_0000000004087a10;  1 drivers, strength-aware
+L_0000000004087620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce06b0_0 .net8 "VNB", 0 0, L_0000000004087620;  1 drivers, strength-aware
+L_0000000004087930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdf2b0_0 .net8 "VPB", 0 0, L_0000000004087930;  1 drivers, strength-aware
+L_0000000004086f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdf530_0 .net8 "VPWR", 0 0, L_0000000004086f90;  1 drivers, strength-aware
+v0000000003cdeef0_0 .net "X", 0 0, L_00000000041615c0;  alias, 1 drivers
+v0000000003cdea90_0 .net "and0_out", 0 0, L_00000000041601a0;  1 drivers
+v0000000003cde770_0 .net "and1_out", 0 0, L_0000000004160c20;  1 drivers
+v0000000003cde310_0 .net "or0_out_X", 0 0, L_000000000415ff00;  1 drivers
+S_00000000029eba50 .scope module, "sky130_fd_sc_hd__a22o_4" "sky130_fd_sc_hd__a22o_4" 4 92257;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6e5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cde630_0 .net "A1", 0 0, o0000000003c6e5f8;  0 drivers
+o0000000003c6e628 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cde950_0 .net "A2", 0 0, o0000000003c6e628;  0 drivers
+o0000000003c6e658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdeb30_0 .net "B1", 0 0, o0000000003c6e658;  0 drivers
+o0000000003c6e688 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cdfa30_0 .net "B2", 0 0, o0000000003c6e688;  0 drivers
+L_0000000004087e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cdfad0_0 .net8 "VGND", 0 0, L_0000000004087e70;  1 drivers, strength-aware
+L_0000000004087cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0110_0 .net8 "VNB", 0 0, L_0000000004087cb0;  1 drivers, strength-aware
+L_00000000040882d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdebd0_0 .net8 "VPB", 0 0, L_00000000040882d0;  1 drivers, strength-aware
+L_0000000004088110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdff30_0 .net8 "VPWR", 0 0, L_0000000004088110;  1 drivers, strength-aware
+v0000000003ce07f0_0 .net "X", 0 0, L_000000000415ff70;  1 drivers
+S_0000000003d08730 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92277, 4 91890 1, S_00000000029eba50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041600c0 .functor AND 1, o0000000003c6e658, o0000000003c6e688, C4<1>, C4<1>;
+L_0000000004161630 .functor AND 1, o0000000003c6e5f8, o0000000003c6e628, C4<1>, C4<1>;
+L_00000000041617f0 .functor OR 1, L_0000000004161630, L_00000000041600c0, C4<0>, C4<0>;
+L_000000000415ff70 .functor BUF 1, L_00000000041617f0, C4<0>, C4<0>, C4<0>;
+v0000000003cde1d0_0 .net "A1", 0 0, o0000000003c6e5f8;  alias, 0 drivers
+v0000000003cde4f0_0 .net "A2", 0 0, o0000000003c6e628;  alias, 0 drivers
+v0000000003cdf8f0_0 .net "B1", 0 0, o0000000003c6e658;  alias, 0 drivers
+v0000000003cde590_0 .net "B2", 0 0, o0000000003c6e688;  alias, 0 drivers
+L_0000000004087f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0890_0 .net8 "VGND", 0 0, L_0000000004087f50;  1 drivers, strength-aware
+L_00000000040887a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cde810_0 .net8 "VNB", 0 0, L_00000000040887a0;  1 drivers, strength-aware
+L_0000000004087700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cdfe90_0 .net8 "VPB", 0 0, L_0000000004087700;  1 drivers, strength-aware
+L_0000000004087690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0570_0 .net8 "VPWR", 0 0, L_0000000004087690;  1 drivers, strength-aware
+v0000000003cdf030_0 .net "X", 0 0, L_000000000415ff70;  alias, 1 drivers
+v0000000003cdfb70_0 .net "and0_out", 0 0, L_00000000041600c0;  1 drivers
+v0000000003ce0250_0 .net "and1_out", 0 0, L_0000000004161630;  1 drivers
+v0000000003cde8b0_0 .net "or0_out_X", 0 0, L_00000000041617f0;  1 drivers
+S_00000000029ea9d0 .scope module, "sky130_fd_sc_hd__a22oi_1" "sky130_fd_sc_hd__a22oi_1" 4 64190;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6ead8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce1ab0_0 .net "A1", 0 0, o0000000003c6ead8;  0 drivers
+o0000000003c6eb08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce15b0_0 .net "A2", 0 0, o0000000003c6eb08;  0 drivers
+o0000000003c6eb38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce2af0_0 .net "B1", 0 0, o0000000003c6eb38;  0 drivers
+o0000000003c6eb68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce1650_0 .net "B2", 0 0, o0000000003c6eb68;  0 drivers
+L_0000000004087ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2690_0 .net8 "VGND", 0 0, L_0000000004087ee0;  1 drivers, strength-aware
+L_00000000040883b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2550_0 .net8 "VNB", 0 0, L_00000000040883b0;  1 drivers, strength-aware
+L_0000000004087e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1b50_0 .net8 "VPB", 0 0, L_0000000004087e00;  1 drivers, strength-aware
+L_0000000004087770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce22d0_0 .net8 "VPWR", 0 0, L_0000000004087770;  1 drivers, strength-aware
+v0000000003ce16f0_0 .net "Y", 0 0, L_0000000004160830;  1 drivers
+S_0000000003d085b0 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 64210, 4 64063 1, S_00000000029ea9d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004161860 .functor NAND 1, o0000000003c6eb08, o0000000003c6ead8, C4<1>, C4<1>;
+L_0000000004160c90 .functor NAND 1, o0000000003c6eb68, o0000000003c6eb38, C4<1>, C4<1>;
+L_0000000004160de0 .functor AND 1, L_0000000004161860, L_0000000004160c90, C4<1>, C4<1>;
+L_0000000004160830 .functor BUF 1, L_0000000004160de0, C4<0>, C4<0>, C4<0>;
+v0000000003ce02f0_0 .net "A1", 0 0, o0000000003c6ead8;  alias, 0 drivers
+v0000000003cdfc10_0 .net "A2", 0 0, o0000000003c6eb08;  alias, 0 drivers
+v0000000003cdfcb0_0 .net "B1", 0 0, o0000000003c6eb38;  alias, 0 drivers
+v0000000003cdfdf0_0 .net "B2", 0 0, o0000000003c6eb68;  alias, 0 drivers
+L_00000000040871c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0430_0 .net8 "VGND", 0 0, L_00000000040871c0;  1 drivers, strength-aware
+L_0000000004088570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1150_0 .net8 "VNB", 0 0, L_0000000004088570;  1 drivers, strength-aware
+L_0000000004087000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce20f0_0 .net8 "VPB", 0 0, L_0000000004087000;  1 drivers, strength-aware
+L_0000000004088180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0cf0_0 .net8 "VPWR", 0 0, L_0000000004088180;  1 drivers, strength-aware
+v0000000003ce2eb0_0 .net "Y", 0 0, L_0000000004160830;  alias, 1 drivers
+v0000000003ce0d90_0 .net "and0_out_Y", 0 0, L_0000000004160de0;  1 drivers
+v0000000003ce1f10_0 .net "nand0_out", 0 0, L_0000000004161860;  1 drivers
+v0000000003ce2cd0_0 .net "nand1_out", 0 0, L_0000000004160c90;  1 drivers
+S_00000000029ec050 .scope module, "sky130_fd_sc_hd__a22oi_2" "sky130_fd_sc_hd__a22oi_2" 4 64310;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6efb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce1790_0 .net "A1", 0 0, o0000000003c6efb8;  0 drivers
+o0000000003c6efe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce2f50_0 .net "A2", 0 0, o0000000003c6efe8;  0 drivers
+o0000000003c6f018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce0ed0_0 .net "B1", 0 0, o0000000003c6f018;  0 drivers
+o0000000003c6f048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce3090_0 .net "B2", 0 0, o0000000003c6f048;  0 drivers
+L_0000000004087540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2e10_0 .net8 "VGND", 0 0, L_0000000004087540;  1 drivers, strength-aware
+L_0000000004086d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0930_0 .net8 "VNB", 0 0, L_0000000004086d60;  1 drivers, strength-aware
+L_00000000040885e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce25f0_0 .net8 "VPB", 0 0, L_00000000040885e0;  1 drivers, strength-aware
+L_0000000004088260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1bf0_0 .net8 "VPWR", 0 0, L_0000000004088260;  1 drivers, strength-aware
+v0000000003ce2370_0 .net "Y", 0 0, L_000000000415ffe0;  1 drivers
+S_0000000003d09030 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 64330, 4 64063 1, S_00000000029ec050;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004161160 .functor NAND 1, o0000000003c6efe8, o0000000003c6efb8, C4<1>, C4<1>;
+L_0000000004160fa0 .functor NAND 1, o0000000003c6f048, o0000000003c6f018, C4<1>, C4<1>;
+L_0000000004160ec0 .functor AND 1, L_0000000004161160, L_0000000004160fa0, C4<1>, C4<1>;
+L_000000000415ffe0 .functor BUF 1, L_0000000004160ec0, C4<0>, C4<0>, C4<0>;
+v0000000003ce1010_0 .net "A1", 0 0, o0000000003c6efb8;  alias, 0 drivers
+v0000000003ce1dd0_0 .net "A2", 0 0, o0000000003c6efe8;  alias, 0 drivers
+v0000000003ce2230_0 .net "B1", 0 0, o0000000003c6f018;  alias, 0 drivers
+v0000000003ce1510_0 .net "B2", 0 0, o0000000003c6f048;  alias, 0 drivers
+L_00000000040881f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0e30_0 .net8 "VGND", 0 0, L_00000000040881f0;  1 drivers, strength-aware
+L_0000000004088500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1970_0 .net8 "VNB", 0 0, L_0000000004088500;  1 drivers, strength-aware
+L_0000000004088420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce18d0_0 .net8 "VPB", 0 0, L_0000000004088420;  1 drivers, strength-aware
+L_00000000040877e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0c50_0 .net8 "VPWR", 0 0, L_00000000040877e0;  1 drivers, strength-aware
+v0000000003ce1c90_0 .net "Y", 0 0, L_000000000415ffe0;  alias, 1 drivers
+v0000000003ce11f0_0 .net "and0_out_Y", 0 0, L_0000000004160ec0;  1 drivers
+v0000000003ce2190_0 .net "nand0_out", 0 0, L_0000000004161160;  1 drivers
+v0000000003ce24b0_0 .net "nand1_out", 0 0, L_0000000004160fa0;  1 drivers
+S_00000000029ec1d0 .scope module, "sky130_fd_sc_hd__a22oi_4" "sky130_fd_sc_hd__a22oi_4" 4 63726;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6f498 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce1290_0 .net "A1", 0 0, o0000000003c6f498;  0 drivers
+o0000000003c6f4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce2730_0 .net "A2", 0 0, o0000000003c6f4c8;  0 drivers
+o0000000003c6f4f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce1330_0 .net "B1", 0 0, o0000000003c6f4f8;  0 drivers
+o0000000003c6f528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce27d0_0 .net "B2", 0 0, o0000000003c6f528;  0 drivers
+L_0000000004087850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2870_0 .net8 "VGND", 0 0, L_0000000004087850;  1 drivers, strength-aware
+L_0000000004087af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0bb0_0 .net8 "VNB", 0 0, L_0000000004087af0;  1 drivers, strength-aware
+L_00000000040880a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2910_0 .net8 "VPB", 0 0, L_00000000040880a0;  1 drivers, strength-aware
+L_00000000040886c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce0a70_0 .net8 "VPWR", 0 0, L_00000000040886c0;  1 drivers, strength-aware
+v0000000003ce13d0_0 .net "Y", 0 0, L_0000000004160670;  1 drivers
+S_0000000003d0b730 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 63746, 4 64063 1, S_00000000029ec1d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004161010 .functor NAND 1, o0000000003c6f4c8, o0000000003c6f498, C4<1>, C4<1>;
+L_0000000004160910 .functor NAND 1, o0000000003c6f528, o0000000003c6f4f8, C4<1>, C4<1>;
+L_00000000041607c0 .functor AND 1, L_0000000004161010, L_0000000004160910, C4<1>, C4<1>;
+L_0000000004160670 .functor BUF 1, L_00000000041607c0, C4<0>, C4<0>, C4<0>;
+v0000000003ce1d30_0 .net "A1", 0 0, o0000000003c6f498;  alias, 0 drivers
+v0000000003ce1830_0 .net "A2", 0 0, o0000000003c6f4c8;  alias, 0 drivers
+v0000000003ce29b0_0 .net "B1", 0 0, o0000000003c6f4f8;  alias, 0 drivers
+v0000000003ce2410_0 .net "B2", 0 0, o0000000003c6f528;  alias, 0 drivers
+L_00000000040872a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1a10_0 .net8 "VGND", 0 0, L_00000000040872a0;  1 drivers, strength-aware
+L_00000000040878c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1e70_0 .net8 "VNB", 0 0, L_00000000040878c0;  1 drivers, strength-aware
+L_0000000004087fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce1fb0_0 .net8 "VPB", 0 0, L_0000000004087fc0;  1 drivers, strength-aware
+L_0000000004088730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce10b0_0 .net8 "VPWR", 0 0, L_0000000004088730;  1 drivers, strength-aware
+v0000000003ce0f70_0 .net "Y", 0 0, L_0000000004160670;  alias, 1 drivers
+v0000000003ce09d0_0 .net "and0_out_Y", 0 0, L_00000000041607c0;  1 drivers
+v0000000003ce2ff0_0 .net "nand0_out", 0 0, L_0000000004161010;  1 drivers
+v0000000003ce2050_0 .net "nand1_out", 0 0, L_0000000004160910;  1 drivers
+S_00000000029ebbd0 .scope module, "sky130_fd_sc_hd__a2bb2o_1" "sky130_fd_sc_hd__a2bb2o_1" 4 62763;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6f978 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4df0_0 .net "A1_N", 0 0, o0000000003c6f978;  0 drivers
+o0000000003c6f9a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4710_0 .net "A2_N", 0 0, o0000000003c6f9a8;  0 drivers
+o0000000003c6f9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce5070_0 .net "B1", 0 0, o0000000003c6f9d8;  0 drivers
+o0000000003c6fa08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4ad0_0 .net "B2", 0 0, o0000000003c6fa08;  0 drivers
+L_0000000004088490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4e90_0 .net8 "VGND", 0 0, L_0000000004088490;  1 drivers, strength-aware
+L_00000000040874d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce36d0_0 .net8 "VNB", 0 0, L_00000000040874d0;  1 drivers, strength-aware
+L_0000000004088340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3770_0 .net8 "VPB", 0 0, L_0000000004088340;  1 drivers, strength-aware
+L_0000000004087b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce34f0_0 .net8 "VPWR", 0 0, L_0000000004087b60;  1 drivers, strength-aware
+v0000000003ce4b70_0 .net "X", 0 0, L_0000000004161390;  1 drivers
+S_0000000003d08bb0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62783, 4 62635 1, S_00000000029ebbd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004160f30 .functor AND 1, o0000000003c6f9d8, o0000000003c6fa08, C4<1>, C4<1>;
+L_00000000041609f0 .functor NOR 1, o0000000003c6f978, o0000000003c6f9a8, C4<0>, C4<0>;
+L_0000000004160130 .functor OR 1, L_00000000041609f0, L_0000000004160f30, C4<0>, C4<0>;
+L_0000000004161390 .functor BUF 1, L_0000000004160130, C4<0>, C4<0>, C4<0>;
+v0000000003ce2a50_0 .net "A1_N", 0 0, o0000000003c6f978;  alias, 0 drivers
+v0000000003ce0b10_0 .net "A2_N", 0 0, o0000000003c6f9a8;  alias, 0 drivers
+v0000000003ce2b90_0 .net "B1", 0 0, o0000000003c6f9d8;  alias, 0 drivers
+v0000000003ce1470_0 .net "B2", 0 0, o0000000003c6fa08;  alias, 0 drivers
+L_0000000004088030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2c30_0 .net8 "VGND", 0 0, L_0000000004088030;  1 drivers, strength-aware
+L_0000000004088650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce2d70_0 .net8 "VNB", 0 0, L_0000000004088650;  1 drivers, strength-aware
+L_00000000040879a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce33b0_0 .net8 "VPB", 0 0, L_00000000040879a0;  1 drivers, strength-aware
+L_0000000004086e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce42b0_0 .net8 "VPWR", 0 0, L_0000000004086e40;  1 drivers, strength-aware
+v0000000003ce4990_0 .net "X", 0 0, L_0000000004161390;  alias, 1 drivers
+v0000000003ce4cb0_0 .net "and0_out", 0 0, L_0000000004160f30;  1 drivers
+v0000000003ce3450_0 .net "nor0_out", 0 0, L_00000000041609f0;  1 drivers
+v0000000003ce4d50_0 .net "or0_out_X", 0 0, L_0000000004160130;  1 drivers
+S_00000000029eacd0 .scope module, "sky130_fd_sc_hd__a2bb2o_4" "sky130_fd_sc_hd__a2bb2o_4" 4 62884;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c6fe58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce3950_0 .net "A1_N", 0 0, o0000000003c6fe58;  0 drivers
+o0000000003c6fe88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce3630_0 .net "A2_N", 0 0, o0000000003c6fe88;  0 drivers
+o0000000003c6feb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4030_0 .net "B1", 0 0, o0000000003c6feb8;  0 drivers
+o0000000003c6fee8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4530_0 .net "B2", 0 0, o0000000003c6fee8;  0 drivers
+L_0000000004087310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4fd0_0 .net8 "VGND", 0 0, L_0000000004087310;  1 drivers, strength-aware
+L_0000000004086eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce39f0_0 .net8 "VNB", 0 0, L_0000000004086eb0;  1 drivers, strength-aware
+L_0000000004087a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3a90_0 .net8 "VPB", 0 0, L_0000000004087a80;  1 drivers, strength-aware
+L_0000000004088880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce57f0_0 .net8 "VPWR", 0 0, L_0000000004088880;  1 drivers, strength-aware
+v0000000003ce3c70_0 .net "X", 0 0, L_00000000041614e0;  1 drivers
+S_0000000003d0b130 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62904, 4 62635 1, S_00000000029eacd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004160e50 .functor AND 1, o0000000003c6feb8, o0000000003c6fee8, C4<1>, C4<1>;
+L_0000000004160750 .functor NOR 1, o0000000003c6fe58, o0000000003c6fe88, C4<0>, C4<0>;
+L_000000000415fd40 .functor OR 1, L_0000000004160750, L_0000000004160e50, C4<0>, C4<0>;
+L_00000000041614e0 .functor BUF 1, L_000000000415fd40, C4<0>, C4<0>, C4<0>;
+v0000000003ce3590_0 .net "A1_N", 0 0, o0000000003c6fe58;  alias, 0 drivers
+v0000000003ce4490_0 .net "A2_N", 0 0, o0000000003c6fe88;  alias, 0 drivers
+v0000000003ce3310_0 .net "B1", 0 0, o0000000003c6feb8;  alias, 0 drivers
+v0000000003ce5390_0 .net "B2", 0 0, o0000000003c6fee8;  alias, 0 drivers
+L_0000000004087d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3810_0 .net8 "VGND", 0 0, L_0000000004087d20;  1 drivers, strength-aware
+L_0000000004087bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce51b0_0 .net8 "VNB", 0 0, L_0000000004087bd0;  1 drivers, strength-aware
+L_0000000004086cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce38b0_0 .net8 "VPB", 0 0, L_0000000004086cf0;  1 drivers, strength-aware
+L_00000000040873f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4c10_0 .net8 "VPWR", 0 0, L_00000000040873f0;  1 drivers, strength-aware
+v0000000003ce4f30_0 .net "X", 0 0, L_00000000041614e0;  alias, 1 drivers
+v0000000003ce48f0_0 .net "and0_out", 0 0, L_0000000004160e50;  1 drivers
+v0000000003ce43f0_0 .net "nor0_out", 0 0, L_0000000004160750;  1 drivers
+v0000000003ce40d0_0 .net "or0_out_X", 0 0, L_000000000415fd40;  1 drivers
+S_00000000029eb2d0 .scope module, "sky130_fd_sc_hd__a2bb2oi_1" "sky130_fd_sc_hd__a2bb2oi_1" 4 61702;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c70338 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce54d0_0 .net "A1_N", 0 0, o0000000003c70338;  0 drivers
+o0000000003c70368 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce3e50_0 .net "A2_N", 0 0, o0000000003c70368;  0 drivers
+o0000000003c70398 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4170_0 .net "B1", 0 0, o0000000003c70398;  0 drivers
+o0000000003c703c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce4850_0 .net "B2", 0 0, o0000000003c703c8;  0 drivers
+L_0000000004088810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5570_0 .net8 "VGND", 0 0, L_0000000004088810;  1 drivers, strength-aware
+L_0000000004086dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5610_0 .net8 "VNB", 0 0, L_0000000004086dd0;  1 drivers, strength-aware
+L_0000000004087380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3bd0_0 .net8 "VPB", 0 0, L_0000000004087380;  1 drivers, strength-aware
+L_0000000004086f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3d10_0 .net8 "VPWR", 0 0, L_0000000004086f20;  1 drivers, strength-aware
+v0000000003ce56b0_0 .net "Y", 0 0, L_0000000004160280;  1 drivers
+S_0000000003d07e30 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61722, 4 62165 1, S_00000000029eb2d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_000000000415fdb0 .functor AND 1, o0000000003c70398, o0000000003c703c8, C4<1>, C4<1>;
+L_00000000041611d0 .functor NOR 1, o0000000003c70338, o0000000003c70368, C4<0>, C4<0>;
+L_0000000004160210 .functor NOR 1, L_00000000041611d0, L_000000000415fdb0, C4<0>, C4<0>;
+L_0000000004160280 .functor BUF 1, L_0000000004160210, C4<0>, C4<0>, C4<0>;
+v0000000003ce45d0_0 .net "A1_N", 0 0, o0000000003c70338;  alias, 0 drivers
+v0000000003ce3b30_0 .net "A2_N", 0 0, o0000000003c70368;  alias, 0 drivers
+v0000000003ce5890_0 .net "B1", 0 0, o0000000003c70398;  alias, 0 drivers
+v0000000003ce4350_0 .net "B2", 0 0, o0000000003c703c8;  alias, 0 drivers
+L_0000000004087d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5110_0 .net8 "VGND", 0 0, L_0000000004087d90;  1 drivers, strength-aware
+L_0000000004087070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4a30_0 .net8 "VNB", 0 0, L_0000000004087070;  1 drivers, strength-aware
+L_00000000040870e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4670_0 .net8 "VPB", 0 0, L_00000000040870e0;  1 drivers, strength-aware
+L_0000000004087150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3db0_0 .net8 "VPWR", 0 0, L_0000000004087150;  1 drivers, strength-aware
+v0000000003ce5250_0 .net "Y", 0 0, L_0000000004160280;  alias, 1 drivers
+v0000000003ce52f0_0 .net "and0_out", 0 0, L_000000000415fdb0;  1 drivers
+v0000000003ce47b0_0 .net "nor0_out", 0 0, L_00000000041611d0;  1 drivers
+v0000000003ce5430_0 .net "nor1_out_Y", 0 0, L_0000000004160210;  1 drivers
+S_00000000029ec650 .scope module, "sky130_fd_sc_hd__a2bb2oi_4" "sky130_fd_sc_hd__a2bb2oi_4" 4 61823;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003c70818 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce6790_0 .net "A1_N", 0 0, o0000000003c70818;  0 drivers
+o0000000003c70848 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce6ab0_0 .net "A2_N", 0 0, o0000000003c70848;  0 drivers
+o0000000003c70878 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce5bb0_0 .net "B1", 0 0, o0000000003c70878;  0 drivers
+o0000000003c708a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce65b0_0 .net "B2", 0 0, o0000000003c708a8;  0 drivers
+L_0000000004087230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7190_0 .net8 "VGND", 0 0, L_0000000004087230;  1 drivers, strength-aware
+L_0000000004087460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce74b0_0 .net8 "VNB", 0 0, L_0000000004087460;  1 drivers, strength-aware
+L_0000000004089fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5c50_0 .net8 "VPB", 0 0, L_0000000004089fb0;  1 drivers, strength-aware
+L_0000000004089c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7550_0 .net8 "VPWR", 0 0, L_0000000004089c30;  1 drivers, strength-aware
+v0000000003ce8090_0 .net "Y", 0 0, L_0000000004161550;  1 drivers
+S_0000000003d0a830 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61843, 4 62165 1, S_00000000029ec650;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004161470 .functor AND 1, o0000000003c70878, o0000000003c708a8, C4<1>, C4<1>;
+L_0000000004161400 .functor NOR 1, o0000000003c70818, o0000000003c70848, C4<0>, C4<0>;
+L_00000000041602f0 .functor NOR 1, L_0000000004161400, L_0000000004161470, C4<0>, C4<0>;
+L_0000000004161550 .functor BUF 1, L_00000000041602f0, C4<0>, C4<0>, C4<0>;
+v0000000003ce5750_0 .net "A1_N", 0 0, o0000000003c70818;  alias, 0 drivers
+v0000000003ce3130_0 .net "A2_N", 0 0, o0000000003c70848;  alias, 0 drivers
+v0000000003ce31d0_0 .net "B1", 0 0, o0000000003c70878;  alias, 0 drivers
+v0000000003ce3270_0 .net "B2", 0 0, o0000000003c708a8;  alias, 0 drivers
+L_000000000408a410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3ef0_0 .net8 "VGND", 0 0, L_000000000408a410;  1 drivers, strength-aware
+L_0000000004089d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce3f90_0 .net8 "VNB", 0 0, L_0000000004089d10;  1 drivers, strength-aware
+L_0000000004089610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce4210_0 .net8 "VPB", 0 0, L_0000000004089610;  1 drivers, strength-aware
+L_00000000040890d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce68d0_0 .net8 "VPWR", 0 0, L_00000000040890d0;  1 drivers, strength-aware
+v0000000003ce6470_0 .net "Y", 0 0, L_0000000004161550;  alias, 1 drivers
+v0000000003ce6970_0 .net "and0_out", 0 0, L_0000000004161470;  1 drivers
+v0000000003ce6bf0_0 .net "nor0_out", 0 0, L_0000000004161400;  1 drivers
+v0000000003ce7af0_0 .net "nor1_out_Y", 0 0, L_00000000041602f0;  1 drivers
+S_00000000029ec350 .scope module, "sky130_fd_sc_hd__a311o_1" "sky130_fd_sc_hd__a311o_1" 4 35018;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c70cf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce72d0_0 .net "A1", 0 0, o0000000003c70cf8;  0 drivers
+o0000000003c70d28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce7690_0 .net "A2", 0 0, o0000000003c70d28;  0 drivers
+o0000000003c70d58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce5f70_0 .net "A3", 0 0, o0000000003c70d58;  0 drivers
+o0000000003c70d88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce6a10_0 .net "B1", 0 0, o0000000003c70d88;  0 drivers
+o0000000003c70db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce7730_0 .net "C1", 0 0, o0000000003c70db8;  0 drivers
+L_0000000004088ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce60b0_0 .net8 "VGND", 0 0, L_0000000004088ff0;  1 drivers, strength-aware
+L_00000000040889d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce77d0_0 .net8 "VNB", 0 0, L_00000000040889d0;  1 drivers, strength-aware
+L_0000000004089220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5cf0_0 .net8 "VPB", 0 0, L_0000000004089220;  1 drivers, strength-aware
+L_0000000004088f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce61f0_0 .net8 "VPWR", 0 0, L_0000000004088f80;  1 drivers, strength-aware
+v0000000003ce79b0_0 .net "X", 0 0, L_00000000041608a0;  1 drivers
+S_0000000003d0a9b0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 35040, 4 35484 1, S_00000000029ec350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041603d0 .functor AND 1, o0000000003c70d58, o0000000003c70cf8, o0000000003c70d28, C4<1>;
+L_0000000004160440 .functor OR 1, L_00000000041603d0, o0000000003c70db8, o0000000003c70d88, C4<0>;
+L_00000000041608a0 .functor BUF 1, L_0000000004160440, C4<0>, C4<0>, C4<0>;
+v0000000003ce7d70_0 .net "A1", 0 0, o0000000003c70cf8;  alias, 0 drivers
+v0000000003ce75f0_0 .net "A2", 0 0, o0000000003c70d28;  alias, 0 drivers
+v0000000003ce5ed0_0 .net "A3", 0 0, o0000000003c70d58;  alias, 0 drivers
+v0000000003ce7f50_0 .net "B1", 0 0, o0000000003c70d88;  alias, 0 drivers
+v0000000003ce5e30_0 .net "C1", 0 0, o0000000003c70db8;  alias, 0 drivers
+L_000000000408a020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6510_0 .net8 "VGND", 0 0, L_000000000408a020;  1 drivers, strength-aware
+L_0000000004089b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7870_0 .net8 "VNB", 0 0, L_0000000004089b50;  1 drivers, strength-aware
+L_0000000004089370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6290_0 .net8 "VPB", 0 0, L_0000000004089370;  1 drivers, strength-aware
+L_0000000004089f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6010_0 .net8 "VPWR", 0 0, L_0000000004089f40;  1 drivers, strength-aware
+v0000000003ce59d0_0 .net "X", 0 0, L_00000000041608a0;  alias, 1 drivers
+v0000000003ce7370_0 .net "and0_out", 0 0, L_00000000041603d0;  1 drivers
+v0000000003ce6c90_0 .net "or0_out_X", 0 0, L_0000000004160440;  1 drivers
+S_00000000029ec7d0 .scope module, "sky130_fd_sc_hd__a311o_2" "sky130_fd_sc_hd__a311o_2" 4 34892;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c71238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce6d30_0 .net "A1", 0 0, o0000000003c71238;  0 drivers
+o0000000003c71268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce7eb0_0 .net "A2", 0 0, o0000000003c71268;  0 drivers
+o0000000003c71298 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce6dd0_0 .net "A3", 0 0, o0000000003c71298;  0 drivers
+o0000000003c712c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce5930_0 .net "B1", 0 0, o0000000003c712c8;  0 drivers
+o0000000003c712f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce7e10_0 .net "C1", 0 0, o0000000003c712f8;  0 drivers
+L_00000000040893e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6e70_0 .net8 "VGND", 0 0, L_00000000040893e0;  1 drivers, strength-aware
+L_0000000004089a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5a70_0 .net8 "VNB", 0 0, L_0000000004089a00;  1 drivers, strength-aware
+L_0000000004088f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7410_0 .net8 "VPB", 0 0, L_0000000004088f10;  1 drivers, strength-aware
+L_0000000004088e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7b90_0 .net8 "VPWR", 0 0, L_0000000004088e30;  1 drivers, strength-aware
+v0000000003ce6f10_0 .net "X", 0 0, L_0000000004160520;  1 drivers
+S_0000000003d09db0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 34914, 4 35484 1, S_00000000029ec7d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041616a0 .functor AND 1, o0000000003c71298, o0000000003c71238, o0000000003c71268, C4<1>;
+L_00000000041604b0 .functor OR 1, L_00000000041616a0, o0000000003c712f8, o0000000003c712c8, C4<0>;
+L_0000000004160520 .functor BUF 1, L_00000000041604b0, C4<0>, C4<0>, C4<0>;
+v0000000003ce6150_0 .net "A1", 0 0, o0000000003c71238;  alias, 0 drivers
+v0000000003ce7910_0 .net "A2", 0 0, o0000000003c71268;  alias, 0 drivers
+v0000000003ce7ff0_0 .net "A3", 0 0, o0000000003c71298;  alias, 0 drivers
+v0000000003ce6330_0 .net "B1", 0 0, o0000000003c712c8;  alias, 0 drivers
+v0000000003ce7a50_0 .net "C1", 0 0, o0000000003c712f8;  alias, 0 drivers
+L_0000000004089140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce63d0_0 .net8 "VGND", 0 0, L_0000000004089140;  1 drivers, strength-aware
+L_0000000004088c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6830_0 .net8 "VNB", 0 0, L_0000000004088c00;  1 drivers, strength-aware
+L_0000000004089290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce5b10_0 .net8 "VPB", 0 0, L_0000000004089290;  1 drivers, strength-aware
+L_0000000004089ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce6650_0 .net8 "VPWR", 0 0, L_0000000004089ae0;  1 drivers, strength-aware
+v0000000003ce5d90_0 .net "X", 0 0, L_0000000004160520;  alias, 1 drivers
+v0000000003ce66f0_0 .net "and0_out", 0 0, L_00000000041616a0;  1 drivers
+v0000000003ce6b50_0 .net "or0_out_X", 0 0, L_00000000041604b0;  1 drivers
+S_00000000029eab50 .scope module, "sky130_fd_sc_hd__a311o_4" "sky130_fd_sc_hd__a311o_4" 4 35144;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c71778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce8a90_0 .net "A1", 0 0, o0000000003c71778;  0 drivers
+o0000000003c717a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea250_0 .net "A2", 0 0, o0000000003c717a8;  0 drivers
+o0000000003c717d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9fd0_0 .net "A3", 0 0, o0000000003c717d8;  0 drivers
+o0000000003c71808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9490_0 .net "B1", 0 0, o0000000003c71808;  0 drivers
+o0000000003c71838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9030_0 .net "C1", 0 0, o0000000003c71838;  0 drivers
+L_0000000004088b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9530_0 .net8 "VGND", 0 0, L_0000000004088b20;  1 drivers, strength-aware
+L_00000000040891b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cea070_0 .net8 "VNB", 0 0, L_00000000040891b0;  1 drivers, strength-aware
+L_0000000004088b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8810_0 .net8 "VPB", 0 0, L_0000000004088b90;  1 drivers, strength-aware
+L_000000000408a1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9e90_0 .net8 "VPWR", 0 0, L_000000000408a1e0;  1 drivers, strength-aware
+v0000000003cea7f0_0 .net "X", 0 0, L_0000000004160600;  1 drivers
+S_0000000003d091b0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 35166, 4 35484 1, S_00000000029eab50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004161240 .functor AND 1, o0000000003c717d8, o0000000003c71778, o0000000003c717a8, C4<1>;
+L_0000000004160590 .functor OR 1, L_0000000004161240, o0000000003c71838, o0000000003c71808, C4<0>;
+L_0000000004160600 .functor BUF 1, L_0000000004160590, C4<0>, C4<0>, C4<0>;
+v0000000003ce6fb0_0 .net "A1", 0 0, o0000000003c71778;  alias, 0 drivers
+v0000000003ce7050_0 .net "A2", 0 0, o0000000003c717a8;  alias, 0 drivers
+v0000000003ce70f0_0 .net "A3", 0 0, o0000000003c717d8;  alias, 0 drivers
+v0000000003ce7230_0 .net "B1", 0 0, o0000000003c71808;  alias, 0 drivers
+v0000000003ce7c30_0 .net "C1", 0 0, o0000000003c71838;  alias, 0 drivers
+L_00000000040888f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce7cd0_0 .net8 "VGND", 0 0, L_00000000040888f0;  1 drivers, strength-aware
+L_0000000004089530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9ad0_0 .net8 "VNB", 0 0, L_0000000004089530;  1 drivers, strength-aware
+L_0000000004089d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce89f0_0 .net8 "VPB", 0 0, L_0000000004089d80;  1 drivers, strength-aware
+L_0000000004088ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cea1b0_0 .net8 "VPWR", 0 0, L_0000000004088ab0;  1 drivers, strength-aware
+v0000000003ce8ef0_0 .net "X", 0 0, L_0000000004160600;  alias, 1 drivers
+v0000000003ce9210_0 .net "and0_out", 0 0, L_0000000004161240;  1 drivers
+v0000000003ce9d50_0 .net "or0_out_X", 0 0, L_0000000004160590;  1 drivers
+S_00000000029ec4d0 .scope module, "sky130_fd_sc_hd__a311oi_1" "sky130_fd_sc_hd__a311oi_1" 4 98967;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c71cb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9b70_0 .net "A1", 0 0, o0000000003c71cb8;  0 drivers
+o0000000003c71ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce98f0_0 .net "A2", 0 0, o0000000003c71ce8;  0 drivers
+o0000000003c71d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea570_0 .net "A3", 0 0, o0000000003c71d18;  0 drivers
+o0000000003c71d48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9f30_0 .net "B1", 0 0, o0000000003c71d48;  0 drivers
+o0000000003c71d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce9cb0_0 .net "C1", 0 0, o0000000003c71d78;  0 drivers
+L_000000000408a090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce92b0_0 .net8 "VGND", 0 0, L_000000000408a090;  1 drivers, strength-aware
+L_0000000004089df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9c10_0 .net8 "VNB", 0 0, L_0000000004089df0;  1 drivers, strength-aware
+L_0000000004089300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9350_0 .net8 "VPB", 0 0, L_0000000004089300;  1 drivers, strength-aware
+L_0000000004088c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cea2f0_0 .net8 "VPWR", 0 0, L_0000000004088c70;  1 drivers, strength-aware
+v0000000003ce9df0_0 .net "Y", 0 0, L_0000000004160d00;  1 drivers
+S_0000000003d088b0 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98989, 4 98585 1, S_00000000029ec4d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004160a60 .functor AND 1, o0000000003c71d18, o0000000003c71cb8, o0000000003c71ce8, C4<1>;
+L_0000000004160ad0 .functor NOR 1, L_0000000004160a60, o0000000003c71d48, o0000000003c71d78, C4<0>;
+L_0000000004160d00 .functor BUF 1, L_0000000004160ad0, C4<0>, C4<0>, C4<0>;
+v0000000003ce8db0_0 .net "A1", 0 0, o0000000003c71cb8;  alias, 0 drivers
+v0000000003ce8310_0 .net "A2", 0 0, o0000000003c71ce8;  alias, 0 drivers
+v0000000003ce9850_0 .net "A3", 0 0, o0000000003c71d18;  alias, 0 drivers
+v0000000003ce8e50_0 .net "B1", 0 0, o0000000003c71d48;  alias, 0 drivers
+v0000000003ce95d0_0 .net "C1", 0 0, o0000000003c71d78;  alias, 0 drivers
+L_0000000004089a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8b30_0 .net8 "VGND", 0 0, L_0000000004089a70;  1 drivers, strength-aware
+L_0000000004089450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8f90_0 .net8 "VNB", 0 0, L_0000000004089450;  1 drivers, strength-aware
+L_0000000004088960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce90d0_0 .net8 "VPB", 0 0, L_0000000004088960;  1 drivers, strength-aware
+L_0000000004088dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9a30_0 .net8 "VPWR", 0 0, L_0000000004088dc0;  1 drivers, strength-aware
+v0000000003ce9170_0 .net "Y", 0 0, L_0000000004160d00;  alias, 1 drivers
+v0000000003cea890_0 .net "and0_out", 0 0, L_0000000004160a60;  1 drivers
+v0000000003cea610_0 .net "nor0_out_Y", 0 0, L_0000000004160ad0;  1 drivers
+S_00000000029eb450 .scope module, "sky130_fd_sc_hd__a311oi_2" "sky130_fd_sc_hd__a311oi_2" 4 98715;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c721f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea430_0 .net "A1", 0 0, o0000000003c721f8;  0 drivers
+o0000000003c72228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea4d0_0 .net "A2", 0 0, o0000000003c72228;  0 drivers
+o0000000003c72258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea6b0_0 .net "A3", 0 0, o0000000003c72258;  0 drivers
+o0000000003c72288 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cea750_0 .net "B1", 0 0, o0000000003c72288;  0 drivers
+o0000000003c722b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ce81d0_0 .net "C1", 0 0, o0000000003c722b8;  0 drivers
+L_0000000004089ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8270_0 .net8 "VGND", 0 0, L_0000000004089ed0;  1 drivers, strength-aware
+L_000000000408a100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce83b0_0 .net8 "VNB", 0 0, L_000000000408a100;  1 drivers, strength-aware
+L_0000000004089840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8450_0 .net8 "VPB", 0 0, L_0000000004089840;  1 drivers, strength-aware
+L_000000000408a2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8630_0 .net8 "VPWR", 0 0, L_000000000408a2c0;  1 drivers, strength-aware
+v0000000003ce86d0_0 .net "Y", 0 0, L_0000000004162430;  1 drivers
+S_0000000003d08a30 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98737, 4 98585 1, S_00000000029eb450;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004160d70 .functor AND 1, o0000000003c72258, o0000000003c721f8, o0000000003c72228, C4<1>;
+L_0000000004162200 .functor NOR 1, L_0000000004160d70, o0000000003c72288, o0000000003c722b8, C4<0>;
+L_0000000004162430 .functor BUF 1, L_0000000004162200, C4<0>, C4<0>, C4<0>;
+v0000000003ce8130_0 .net "A1", 0 0, o0000000003c721f8;  alias, 0 drivers
+v0000000003ce84f0_0 .net "A2", 0 0, o0000000003c72228;  alias, 0 drivers
+v0000000003ce8590_0 .net "A3", 0 0, o0000000003c72258;  alias, 0 drivers
+v0000000003ce93f0_0 .net "B1", 0 0, o0000000003c72288;  alias, 0 drivers
+v0000000003ce9670_0 .net "C1", 0 0, o0000000003c722b8;  alias, 0 drivers
+L_0000000004089760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8d10_0 .net8 "VGND", 0 0, L_0000000004089760;  1 drivers, strength-aware
+L_00000000040894c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9710_0 .net8 "VNB", 0 0, L_00000000040894c0;  1 drivers, strength-aware
+L_0000000004089ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce8950_0 .net8 "VPB", 0 0, L_0000000004089ca0;  1 drivers, strength-aware
+L_00000000040895a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ce9990_0 .net8 "VPWR", 0 0, L_00000000040895a0;  1 drivers, strength-aware
+v0000000003cea110_0 .net "Y", 0 0, L_0000000004162430;  alias, 1 drivers
+v0000000003ce97b0_0 .net "and0_out", 0 0, L_0000000004160d70;  1 drivers
+v0000000003cea390_0 .net "nor0_out_Y", 0 0, L_0000000004162200;  1 drivers
+S_00000000029eae50 .scope module, "sky130_fd_sc_hd__a311oi_4" "sky130_fd_sc_hd__a311oi_4" 4 98841;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003c72738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceccd0_0 .net "A1", 0 0, o0000000003c72738;  0 drivers
+o0000000003c72768 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceb650_0 .net "A2", 0 0, o0000000003c72768;  0 drivers
+o0000000003c72798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cec910_0 .net "A3", 0 0, o0000000003c72798;  0 drivers
+o0000000003c727c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cec230_0 .net "B1", 0 0, o0000000003c727c8;  0 drivers
+o0000000003c727f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cec2d0_0 .net "C1", 0 0, o0000000003c727f8;  0 drivers
+L_0000000004089680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cec370_0 .net8 "VGND", 0 0, L_0000000004089680;  1 drivers, strength-aware
+L_000000000408a170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb790_0 .net8 "VNB", 0 0, L_000000000408a170;  1 drivers, strength-aware
+L_000000000408a330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cebe70_0 .net8 "VPB", 0 0, L_000000000408a330;  1 drivers, strength-aware
+L_0000000004088a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cebf10_0 .net8 "VPWR", 0 0, L_0000000004088a40;  1 drivers, strength-aware
+v0000000003cec410_0 .net "Y", 0 0, L_0000000004162f90;  1 drivers
+S_0000000003d070b0 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98863, 4 98585 1, S_00000000029eae50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004162d60 .functor AND 1, o0000000003c72798, o0000000003c72738, o0000000003c72768, C4<1>;
+L_0000000004161cc0 .functor NOR 1, L_0000000004162d60, o0000000003c727c8, o0000000003c727f8, C4<0>;
+L_0000000004162f90 .functor BUF 1, L_0000000004161cc0, C4<0>, C4<0>, C4<0>;
+v0000000003ce8770_0 .net "A1", 0 0, o0000000003c72738;  alias, 0 drivers
+v0000000003ce88b0_0 .net "A2", 0 0, o0000000003c72768;  alias, 0 drivers
+v0000000003ce8c70_0 .net "A3", 0 0, o0000000003c72798;  alias, 0 drivers
+v0000000003ce8bd0_0 .net "B1", 0 0, o0000000003c727c8;  alias, 0 drivers
+v0000000003cebd30_0 .net "C1", 0 0, o0000000003c727f8;  alias, 0 drivers
+L_0000000004088ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cebab0_0 .net8 "VGND", 0 0, L_0000000004088ce0;  1 drivers, strength-aware
+L_000000000408a3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cecff0_0 .net8 "VNB", 0 0, L_000000000408a3a0;  1 drivers, strength-aware
+L_0000000004088ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cec190_0 .net8 "VPB", 0 0, L_0000000004088ea0;  1 drivers, strength-aware
+L_000000000408a480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cebc90_0 .net8 "VPWR", 0 0, L_000000000408a480;  1 drivers, strength-aware
+v0000000003cebdd0_0 .net "Y", 0 0, L_0000000004162f90;  alias, 1 drivers
+v0000000003cecaf0_0 .net "and0_out", 0 0, L_0000000004162d60;  1 drivers
+v0000000003cecd70_0 .net "nor0_out_Y", 0 0, L_0000000004161cc0;  1 drivers
+S_00000000029eafd0 .scope module, "sky130_fd_sc_hd__a31o_1" "sky130_fd_sc_hd__a31o_1" 4 41662;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003c72c78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cecc30_0 .net "A1", 0 0, o0000000003c72c78;  0 drivers
+o0000000003c72ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cec5f0_0 .net "A2", 0 0, o0000000003c72ca8;  0 drivers
+o0000000003c72cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cec0f0_0 .net "A3", 0 0, o0000000003c72cd8;  0 drivers
+o0000000003c72d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cece10_0 .net "B1", 0 0, o0000000003c72d08;  0 drivers
+L_0000000004089e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cebb50_0 .net8 "VGND", 0 0, L_0000000004089e60;  1 drivers, strength-aware
+L_00000000040896f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceac50_0 .net8 "VNB", 0 0, L_00000000040896f0;  1 drivers, strength-aware
+L_000000000408a250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cebbf0_0 .net8 "VPB", 0 0, L_000000000408a250;  1 drivers, strength-aware
+L_00000000040897d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceaf70_0 .net8 "VPWR", 0 0, L_00000000040897d0;  1 drivers, strength-aware
+v0000000003cea9d0_0 .net "X", 0 0, L_0000000004162270;  1 drivers
+S_0000000003d0a230 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 41682, 4 41993 1, S_00000000029eafd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_00000000041626d0 .functor AND 1, o0000000003c72cd8, o0000000003c72c78, o0000000003c72ca8, C4<1>;
+L_0000000004161f60 .functor OR 1, L_00000000041626d0, o0000000003c72d08, C4<0>, C4<0>;
+L_0000000004162270 .functor BUF 1, L_0000000004161f60, C4<0>, C4<0>, C4<0>;
+v0000000003cebfb0_0 .net "A1", 0 0, o0000000003c72c78;  alias, 0 drivers
+v0000000003ceb150_0 .net "A2", 0 0, o0000000003c72ca8;  alias, 0 drivers
+v0000000003cec050_0 .net "A3", 0 0, o0000000003c72cd8;  alias, 0 drivers
+v0000000003cec9b0_0 .net "B1", 0 0, o0000000003c72d08;  alias, 0 drivers
+L_0000000004088d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceabb0_0 .net8 "VGND", 0 0, L_0000000004088d50;  1 drivers, strength-aware
+L_0000000004089060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cec550_0 .net8 "VNB", 0 0, L_0000000004089060;  1 drivers, strength-aware
+L_00000000040898b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cecb90_0 .net8 "VPB", 0 0, L_00000000040898b0;  1 drivers, strength-aware
+L_0000000004089920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb830_0 .net8 "VPWR", 0 0, L_0000000004089920;  1 drivers, strength-aware
+v0000000003cec4b0_0 .net "X", 0 0, L_0000000004162270;  alias, 1 drivers
+v0000000003ced090_0 .net "and0_out", 0 0, L_00000000041626d0;  1 drivers
+v0000000003cea930_0 .net "or0_out_X", 0 0, L_0000000004161f60;  1 drivers
+S_00000000029ebed0 .scope module, "sky130_fd_sc_hd__a31o_4" "sky130_fd_sc_hd__a31o_4" 4 42238;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003c73128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceaa70_0 .net "A1", 0 0, o0000000003c73128;  0 drivers
+o0000000003c73158 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceab10_0 .net "A2", 0 0, o0000000003c73158;  0 drivers
+o0000000003c73188 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cead90_0 .net "A3", 0 0, o0000000003c73188;  0 drivers
+o0000000003c731b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceae30_0 .net "B1", 0 0, o0000000003c731b8;  0 drivers
+L_0000000004089990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb0b0_0 .net8 "VGND", 0 0, L_0000000004089990;  1 drivers, strength-aware
+L_0000000004089bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb1f0_0 .net8 "VNB", 0 0, L_0000000004089bc0;  1 drivers, strength-aware
+L_000000000408be50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb290_0 .net8 "VPB", 0 0, L_000000000408be50;  1 drivers, strength-aware
+L_000000000408bec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb6f0_0 .net8 "VPWR", 0 0, L_000000000408bec0;  1 drivers, strength-aware
+v0000000003ceba10_0 .net "X", 0 0, L_00000000041624a0;  1 drivers
+S_0000000003d08d30 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 42258, 4 41993 1, S_00000000029ebed0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004162740 .functor AND 1, o0000000003c73188, o0000000003c73128, o0000000003c73158, C4<1>;
+L_00000000041622e0 .functor OR 1, L_0000000004162740, o0000000003c731b8, C4<0>, C4<0>;
+L_00000000041624a0 .functor BUF 1, L_00000000041622e0, C4<0>, C4<0>, C4<0>;
+v0000000003cec690_0 .net "A1", 0 0, o0000000003c73128;  alias, 0 drivers
+v0000000003cec730_0 .net "A2", 0 0, o0000000003c73158;  alias, 0 drivers
+v0000000003cec870_0 .net "A3", 0 0, o0000000003c73188;  alias, 0 drivers
+v0000000003cec7d0_0 .net "B1", 0 0, o0000000003c731b8;  alias, 0 drivers
+L_000000000408bf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceca50_0 .net8 "VGND", 0 0, L_000000000408bf30;  1 drivers, strength-aware
+L_000000000408afe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceaed0_0 .net8 "VNB", 0 0, L_000000000408afe0;  1 drivers, strength-aware
+L_000000000408ae20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb010_0 .net8 "VPB", 0 0, L_000000000408ae20;  1 drivers, strength-aware
+L_000000000408b910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ceacf0_0 .net8 "VPWR", 0 0, L_000000000408b910;  1 drivers, strength-aware
+v0000000003ceceb0_0 .net "X", 0 0, L_00000000041624a0;  alias, 1 drivers
+v0000000003ceb5b0_0 .net "and0_out", 0 0, L_0000000004162740;  1 drivers
+v0000000003cecf50_0 .net "or0_out_X", 0 0, L_00000000041622e0;  1 drivers
+S_00000000029eb150 .scope module, "sky130_fd_sc_hd__a31oi_1" "sky130_fd_sc_hd__a31oi_1" 4 72207;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003c735d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceee90_0 .net "A1", 0 0, o0000000003c735d8;  0 drivers
+o0000000003c73608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cee490_0 .net "A2", 0 0, o0000000003c73608;  0 drivers
+o0000000003c73638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ced630_0 .net "A3", 0 0, o0000000003c73638;  0 drivers
+o0000000003c73668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceecb0_0 .net "B1", 0 0, o0000000003c73668;  0 drivers
+L_000000000408abf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cedc70_0 .net8 "VGND", 0 0, L_000000000408abf0;  1 drivers, strength-aware
+L_000000000408a6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ced950_0 .net8 "VNB", 0 0, L_000000000408a6b0;  1 drivers, strength-aware
+L_000000000408ba60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cee8f0_0 .net8 "VPB", 0 0, L_000000000408ba60;  1 drivers, strength-aware
+L_000000000408a4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ced590_0 .net8 "VPWR", 0 0, L_000000000408a4f0;  1 drivers, strength-aware
+v0000000003cef6b0_0 .net "Y", 0 0, L_0000000004162dd0;  1 drivers
+S_0000000003d09330 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72227, 4 72538 1, S_00000000029eb150;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004163380 .functor AND 1, o0000000003c73638, o0000000003c735d8, o0000000003c73608, C4<1>;
+L_0000000004163230 .functor NOR 1, o0000000003c73668, L_0000000004163380, C4<0>, C4<0>;
+L_0000000004162dd0 .functor BUF 1, L_0000000004163230, C4<0>, C4<0>, C4<0>;
+v0000000003ceb330_0 .net "A1", 0 0, o0000000003c735d8;  alias, 0 drivers
+v0000000003ceb3d0_0 .net "A2", 0 0, o0000000003c73608;  alias, 0 drivers
+v0000000003ceb470_0 .net "A3", 0 0, o0000000003c73638;  alias, 0 drivers
+v0000000003ceb8d0_0 .net "B1", 0 0, o0000000003c73668;  alias, 0 drivers
+L_000000000408b2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb510_0 .net8 "VGND", 0 0, L_000000000408b2f0;  1 drivers, strength-aware
+L_000000000408aaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceb970_0 .net8 "VNB", 0 0, L_000000000408aaa0;  1 drivers, strength-aware
+L_000000000408b440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ced3b0_0 .net8 "VPB", 0 0, L_000000000408b440;  1 drivers, strength-aware
+L_000000000408a9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ced4f0_0 .net8 "VPWR", 0 0, L_000000000408a9c0;  1 drivers, strength-aware
+v0000000003cef7f0_0 .net "Y", 0 0, L_0000000004162dd0;  alias, 1 drivers
+v0000000003ced810_0 .net "and0_out", 0 0, L_0000000004163380;  1 drivers
+v0000000003ceef30_0 .net "nor0_out_Y", 0 0, L_0000000004163230;  1 drivers
+S_00000000029eb750 .scope module, "sky130_fd_sc_hd__a31oi_4" "sky130_fd_sc_hd__a31oi_4" 4 72087;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003c73a88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cee990_0 .net "A1", 0 0, o0000000003c73a88;  0 drivers
+o0000000003c73ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceedf0_0 .net "A2", 0 0, o0000000003c73ab8;  0 drivers
+o0000000003c73ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cee710_0 .net "A3", 0 0, o0000000003c73ae8;  0 drivers
+o0000000003c73b18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ced450_0 .net "B1", 0 0, o0000000003c73b18;  0 drivers
+L_000000000408b0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cee5d0_0 .net8 "VGND", 0 0, L_000000000408b0c0;  1 drivers, strength-aware
+L_000000000408a790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceec10_0 .net8 "VNB", 0 0, L_000000000408a790;  1 drivers, strength-aware
+L_000000000408b360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cee530_0 .net8 "VPB", 0 0, L_000000000408b360;  1 drivers, strength-aware
+L_000000000408ae90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cee030_0 .net8 "VPWR", 0 0, L_000000000408ae90;  1 drivers, strength-aware
+v0000000003ceea30_0 .net "Y", 0 0, L_0000000004162e40;  1 drivers
+S_0000000003d0bd30 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72107, 4 72538 1, S_00000000029eb750;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004162120 .functor AND 1, o0000000003c73ae8, o0000000003c73a88, o0000000003c73ab8, C4<1>;
+L_0000000004162350 .functor NOR 1, o0000000003c73b18, L_0000000004162120, C4<0>, C4<0>;
+L_0000000004162e40 .functor BUF 1, L_0000000004162350, C4<0>, C4<0>, C4<0>;
+v0000000003cef070_0 .net "A1", 0 0, o0000000003c73a88;  alias, 0 drivers
+v0000000003ced8b0_0 .net "A2", 0 0, o0000000003c73ab8;  alias, 0 drivers
+v0000000003cedf90_0 .net "A3", 0 0, o0000000003c73ae8;  alias, 0 drivers
+v0000000003ceeb70_0 .net "B1", 0 0, o0000000003c73b18;  alias, 0 drivers
+L_000000000408b980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cee3f0_0 .net8 "VGND", 0 0, L_000000000408b980;  1 drivers, strength-aware
+L_000000000408b4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ceed50_0 .net8 "VNB", 0 0, L_000000000408b4b0;  1 drivers, strength-aware
+L_000000000408b050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ced310_0 .net8 "VPB", 0 0, L_000000000408b050;  1 drivers, strength-aware
+L_000000000408bfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cef890_0 .net8 "VPWR", 0 0, L_000000000408bfa0;  1 drivers, strength-aware
+v0000000003ceead0_0 .net "Y", 0 0, L_0000000004162e40;  alias, 1 drivers
+v0000000003ceefd0_0 .net "and0_out", 0 0, L_0000000004162120;  1 drivers
+v0000000003cef570_0 .net "nor0_out_Y", 0 0, L_0000000004162350;  1 drivers
+S_00000000029ebd50 .scope module, "sky130_fd_sc_hd__a32o_1" "sky130_fd_sc_hd__a32o_1" 4 96611;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c73f38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cef2f0_0 .net "A1", 0 0, o0000000003c73f38;  0 drivers
+o0000000003c73f68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ced130_0 .net "A2", 0 0, o0000000003c73f68;  0 drivers
+o0000000003c73f98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cee350_0 .net "A3", 0 0, o0000000003c73f98;  0 drivers
+o0000000003c73fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ceddb0_0 .net "B1", 0 0, o0000000003c73fc8;  0 drivers
+o0000000003c73ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cef430_0 .net "B2", 0 0, o0000000003c73ff8;  0 drivers
+L_000000000408c080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cef610_0 .net8 "VGND", 0 0, L_000000000408c080;  1 drivers, strength-aware
+L_000000000408b130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ced1d0_0 .net8 "VNB", 0 0, L_000000000408b130;  1 drivers, strength-aware
+L_000000000408b600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cee670_0 .net8 "VPB", 0 0, L_000000000408b600;  1 drivers, strength-aware
+L_000000000408acd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cef4d0_0 .net8 "VPWR", 0 0, L_000000000408acd0;  1 drivers, strength-aware
+v0000000003ced270_0 .net "X", 0 0, L_0000000004161e80;  1 drivers
+S_0000000003d0c7b0 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96633, 4 97089 1, S_00000000029ebd50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004163460 .functor AND 1, o0000000003c73f98, o0000000003c73f38, o0000000003c73f68, C4<1>;
+L_0000000004162ac0 .functor AND 1, o0000000003c73fc8, o0000000003c73ff8, C4<1>, C4<1>;
+L_0000000004161e10 .functor OR 1, L_0000000004162ac0, L_0000000004163460, C4<0>, C4<0>;
+L_0000000004161e80 .functor BUF 1, L_0000000004161e10, C4<0>, C4<0>, C4<0>;
+v0000000003ced9f0_0 .net "A1", 0 0, o0000000003c73f38;  alias, 0 drivers
+v0000000003cee210_0 .net "A2", 0 0, o0000000003c73f68;  alias, 0 drivers
+v0000000003cee0d0_0 .net "A3", 0 0, o0000000003c73f98;  alias, 0 drivers
+v0000000003cef110_0 .net "B1", 0 0, o0000000003c73fc8;  alias, 0 drivers
+v0000000003cee2b0_0 .net "B2", 0 0, o0000000003c73ff8;  alias, 0 drivers
+L_000000000408a560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cef390_0 .net8 "VGND", 0 0, L_000000000408a560;  1 drivers, strength-aware
+L_000000000408a5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cee850_0 .net8 "VNB", 0 0, L_000000000408a5d0;  1 drivers, strength-aware
+L_000000000408af70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cef1b0_0 .net8 "VPB", 0 0, L_000000000408af70;  1 drivers, strength-aware
+L_000000000408af00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cedd10_0 .net8 "VPWR", 0 0, L_000000000408af00;  1 drivers, strength-aware
+v0000000003ceda90_0 .net "X", 0 0, L_0000000004161e80;  alias, 1 drivers
+v0000000003cef250_0 .net "and0_out", 0 0, L_0000000004163460;  1 drivers
+v0000000003ced6d0_0 .net "and1_out", 0 0, L_0000000004162ac0;  1 drivers
+v0000000003cef750_0 .net "or0_out_X", 0 0, L_0000000004161e10;  1 drivers
+S_00000000029ed760 .scope module, "sky130_fd_sc_hd__a32o_2" "sky130_fd_sc_hd__a32o_2" 4 96484;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c744a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf1e10_0 .net "A1", 0 0, o0000000003c744a8;  0 drivers
+o0000000003c744d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0790_0 .net "A2", 0 0, o0000000003c744d8;  0 drivers
+o0000000003c74508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0970_0 .net "A3", 0 0, o0000000003c74508;  0 drivers
+o0000000003c74538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0a10_0 .net "B1", 0 0, o0000000003c74538;  0 drivers
+o0000000003c74568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0470_0 .net "B2", 0 0, o0000000003c74568;  0 drivers
+L_000000000408bb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0ab0_0 .net8 "VGND", 0 0, L_000000000408bb40;  1 drivers, strength-aware
+L_000000000408ad40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0bf0_0 .net8 "VNB", 0 0, L_000000000408ad40;  1 drivers, strength-aware
+L_000000000408b750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1af0_0 .net8 "VPB", 0 0, L_000000000408b750;  1 drivers, strength-aware
+L_000000000408b7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1d70_0 .net8 "VPWR", 0 0, L_000000000408b7c0;  1 drivers, strength-aware
+v0000000003cefd90_0 .net "X", 0 0, L_00000000041623c0;  1 drivers
+S_0000000003d0ab30 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96506, 4 97089 1, S_00000000029ed760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004163070 .functor AND 1, o0000000003c74508, o0000000003c744a8, o0000000003c744d8, C4<1>;
+L_0000000004162890 .functor AND 1, o0000000003c74538, o0000000003c74568, C4<1>, C4<1>;
+L_00000000041632a0 .functor OR 1, L_0000000004162890, L_0000000004163070, C4<0>, C4<0>;
+L_00000000041623c0 .functor BUF 1, L_00000000041632a0, C4<0>, C4<0>, C4<0>;
+v0000000003ced770_0 .net "A1", 0 0, o0000000003c744a8;  alias, 0 drivers
+v0000000003cedb30_0 .net "A2", 0 0, o0000000003c744d8;  alias, 0 drivers
+v0000000003cee7b0_0 .net "A3", 0 0, o0000000003c74508;  alias, 0 drivers
+v0000000003cedbd0_0 .net "B1", 0 0, o0000000003c74538;  alias, 0 drivers
+v0000000003cede50_0 .net "B2", 0 0, o0000000003c74568;  alias, 0 drivers
+L_000000000408b1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cedef0_0 .net8 "VGND", 0 0, L_000000000408b1a0;  1 drivers, strength-aware
+L_000000000408adb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cee170_0 .net8 "VNB", 0 0, L_000000000408adb0;  1 drivers, strength-aware
+L_000000000408bad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf08d0_0 .net8 "VPB", 0 0, L_000000000408bad0;  1 drivers, strength-aware
+L_000000000408bbb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf00b0_0 .net8 "VPWR", 0 0, L_000000000408bbb0;  1 drivers, strength-aware
+v0000000003cf0c90_0 .net "X", 0 0, L_00000000041623c0;  alias, 1 drivers
+v0000000003cefa70_0 .net "and0_out", 0 0, L_0000000004163070;  1 drivers
+v0000000003cf1cd0_0 .net "and1_out", 0 0, L_0000000004162890;  1 drivers
+v0000000003cf0dd0_0 .net "or0_out_X", 0 0, L_00000000041632a0;  1 drivers
+S_00000000029ecce0 .scope module, "sky130_fd_sc_hd__a32o_4" "sky130_fd_sc_hd__a32o_4" 4 96738;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c74a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf1ff0_0 .net "A1", 0 0, o0000000003c74a18;  0 drivers
+o0000000003c74a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0e70_0 .net "A2", 0 0, o0000000003c74a48;  0 drivers
+o0000000003c74a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0fb0_0 .net "A3", 0 0, o0000000003c74a78;  0 drivers
+o0000000003c74aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf1230_0 .net "B1", 0 0, o0000000003c74aa8;  0 drivers
+o0000000003c74ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cef930_0 .net "B2", 0 0, o0000000003c74ad8;  0 drivers
+L_000000000408bd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cefc50_0 .net8 "VGND", 0 0, L_000000000408bd70;  1 drivers, strength-aware
+L_000000000408b670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf15f0_0 .net8 "VNB", 0 0, L_000000000408b670;  1 drivers, strength-aware
+L_000000000408bc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cef9d0_0 .net8 "VPB", 0 0, L_000000000408bc20;  1 drivers, strength-aware
+L_000000000408b210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cefbb0_0 .net8 "VPWR", 0 0, L_000000000408b210;  1 drivers, strength-aware
+v0000000003cf1910_0 .net "X", 0 0, L_0000000004161940;  1 drivers
+S_0000000003d0ae30 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96760, 4 97089 1, S_00000000029ecce0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004161a90 .functor AND 1, o0000000003c74a78, o0000000003c74a18, o0000000003c74a48, C4<1>;
+L_0000000004162580 .functor AND 1, o0000000003c74aa8, o0000000003c74ad8, C4<1>, C4<1>;
+L_0000000004162510 .functor OR 1, L_0000000004162580, L_0000000004161a90, C4<0>, C4<0>;
+L_0000000004161940 .functor BUF 1, L_0000000004162510, C4<0>, C4<0>, C4<0>;
+v0000000003cf1190_0 .net "A1", 0 0, o0000000003c74a18;  alias, 0 drivers
+v0000000003cf14b0_0 .net "A2", 0 0, o0000000003c74a48;  alias, 0 drivers
+v0000000003cf1870_0 .net "A3", 0 0, o0000000003c74a78;  alias, 0 drivers
+v0000000003cf2090_0 .net "B1", 0 0, o0000000003c74aa8;  alias, 0 drivers
+v0000000003cefb10_0 .net "B2", 0 0, o0000000003c74ad8;  alias, 0 drivers
+L_000000000408ac60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf17d0_0 .net8 "VGND", 0 0, L_000000000408ac60;  1 drivers, strength-aware
+L_000000000408bc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1550_0 .net8 "VNB", 0 0, L_000000000408bc90;  1 drivers, strength-aware
+L_000000000408a720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0f10_0 .net8 "VPB", 0 0, L_000000000408a720;  1 drivers, strength-aware
+L_000000000408b280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0d30_0 .net8 "VPWR", 0 0, L_000000000408b280;  1 drivers, strength-aware
+v0000000003cf1eb0_0 .net "X", 0 0, L_0000000004161940;  alias, 1 drivers
+v0000000003cf0b50_0 .net "and0_out", 0 0, L_0000000004161a90;  1 drivers
+v0000000003cf1f50_0 .net "and1_out", 0 0, L_0000000004162580;  1 drivers
+v0000000003cefed0_0 .net "or0_out_X", 0 0, L_0000000004162510;  1 drivers
+S_00000000029eda60 .scope module, "sky130_fd_sc_hd__a32oi_1" "sky130_fd_sc_hd__a32oi_1" 4 101708;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c74f88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf06f0_0 .net "A1", 0 0, o0000000003c74f88;  0 drivers
+o0000000003c74fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf1730_0 .net "A2", 0 0, o0000000003c74fb8;  0 drivers
+o0000000003c74fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf10f0_0 .net "A3", 0 0, o0000000003c74fe8;  0 drivers
+o0000000003c75018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf1a50_0 .net "B1", 0 0, o0000000003c75018;  0 drivers
+o0000000003c75048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf0330_0 .net "B2", 0 0, o0000000003c75048;  0 drivers
+L_000000000408bd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1b90_0 .net8 "VGND", 0 0, L_000000000408bd00;  1 drivers, strength-aware
+L_000000000408b3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1c30_0 .net8 "VNB", 0 0, L_000000000408b3d0;  1 drivers, strength-aware
+L_000000000408b520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf03d0_0 .net8 "VPB", 0 0, L_000000000408b520;  1 drivers, strength-aware
+L_000000000408b6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf05b0_0 .net8 "VPWR", 0 0, L_000000000408b6e0;  1 drivers, strength-aware
+v0000000003cf0650_0 .net "Y", 0 0, L_0000000004162f20;  1 drivers
+S_0000000003d0c930 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101730, 4 101575 1, S_00000000029eda60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004162820 .functor NAND 1, o0000000003c74fb8, o0000000003c74f88, o0000000003c74fe8, C4<1>;
+L_0000000004162900 .functor NAND 1, o0000000003c75048, o0000000003c75018, C4<1>, C4<1>;
+L_0000000004162a50 .functor AND 1, L_0000000004162820, L_0000000004162900, C4<1>, C4<1>;
+L_0000000004162f20 .functor BUF 1, L_0000000004162a50, C4<0>, C4<0>, C4<0>;
+v0000000003cefcf0_0 .net "A1", 0 0, o0000000003c74f88;  alias, 0 drivers
+v0000000003ceff70_0 .net "A2", 0 0, o0000000003c74fb8;  alias, 0 drivers
+v0000000003cefe30_0 .net "A3", 0 0, o0000000003c74fe8;  alias, 0 drivers
+v0000000003cf0510_0 .net "B1", 0 0, o0000000003c75018;  alias, 0 drivers
+v0000000003cf19b0_0 .net "B2", 0 0, o0000000003c75048;  alias, 0 drivers
+L_000000000408aa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0010_0 .net8 "VGND", 0 0, L_000000000408aa30;  1 drivers, strength-aware
+L_000000000408c010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1410_0 .net8 "VNB", 0 0, L_000000000408c010;  1 drivers, strength-aware
+L_000000000408a800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf0150_0 .net8 "VPB", 0 0, L_000000000408a800;  1 drivers, strength-aware
+L_000000000408b590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf1370_0 .net8 "VPWR", 0 0, L_000000000408b590;  1 drivers, strength-aware
+v0000000003cf12d0_0 .net "Y", 0 0, L_0000000004162f20;  alias, 1 drivers
+v0000000003cf1690_0 .net "and0_out_Y", 0 0, L_0000000004162a50;  1 drivers
+v0000000003cf01f0_0 .net "nand0_out", 0 0, L_0000000004162820;  1 drivers
+v0000000003cf0290_0 .net "nand1_out", 0 0, L_0000000004162900;  1 drivers
+S_00000000029ecb60 .scope module, "sky130_fd_sc_hd__a32oi_2" "sky130_fd_sc_hd__a32oi_2" 4 101224;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c754f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf4890_0 .net "A1", 0 0, o0000000003c754f8;  0 drivers
+o0000000003c75528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf4070_0 .net "A2", 0 0, o0000000003c75528;  0 drivers
+o0000000003c75558 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf47f0_0 .net "A3", 0 0, o0000000003c75558;  0 drivers
+o0000000003c75588 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf3350_0 .net "B1", 0 0, o0000000003c75588;  0 drivers
+o0000000003c755b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf3ad0_0 .net "B2", 0 0, o0000000003c755b8;  0 drivers
+L_000000000408b830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf38f0_0 .net8 "VGND", 0 0, L_000000000408b830;  1 drivers, strength-aware
+L_000000000408a640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf35d0_0 .net8 "VNB", 0 0, L_000000000408a640;  1 drivers, strength-aware
+L_000000000408b8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf2db0_0 .net8 "VPB", 0 0, L_000000000408b8a0;  1 drivers, strength-aware
+L_000000000408ab10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3e90_0 .net8 "VPWR", 0 0, L_000000000408ab10;  1 drivers, strength-aware
+v0000000003cf3d50_0 .net "Y", 0 0, L_00000000041619b0;  1 drivers
+S_0000000003d0b2b0 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101246, 4 101575 1, S_00000000029ecb60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004161a20 .functor NAND 1, o0000000003c75528, o0000000003c754f8, o0000000003c75558, C4<1>;
+L_0000000004162970 .functor NAND 1, o0000000003c755b8, o0000000003c75588, C4<1>, C4<1>;
+L_0000000004163000 .functor AND 1, L_0000000004161a20, L_0000000004162970, C4<1>, C4<1>;
+L_00000000041619b0 .functor BUF 1, L_0000000004163000, C4<0>, C4<0>, C4<0>;
+v0000000003cf0830_0 .net "A1", 0 0, o0000000003c754f8;  alias, 0 drivers
+v0000000003cf1050_0 .net "A2", 0 0, o0000000003c75528;  alias, 0 drivers
+v0000000003cf3210_0 .net "A3", 0 0, o0000000003c75558;  alias, 0 drivers
+v0000000003cf2f90_0 .net "B1", 0 0, o0000000003c75588;  alias, 0 drivers
+v0000000003cf2310_0 .net "B2", 0 0, o0000000003c755b8;  alias, 0 drivers
+L_000000000408b9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf32b0_0 .net8 "VGND", 0 0, L_000000000408b9f0;  1 drivers, strength-aware
+L_000000000408a870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf23b0_0 .net8 "VNB", 0 0, L_000000000408a870;  1 drivers, strength-aware
+L_000000000408bde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf2630_0 .net8 "VPB", 0 0, L_000000000408bde0;  1 drivers, strength-aware
+L_000000000408a8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf30d0_0 .net8 "VPWR", 0 0, L_000000000408a8e0;  1 drivers, strength-aware
+v0000000003cf2c70_0 .net "Y", 0 0, L_00000000041619b0;  alias, 1 drivers
+v0000000003cf3030_0 .net "and0_out_Y", 0 0, L_0000000004163000;  1 drivers
+v0000000003cf2a90_0 .net "nand0_out", 0 0, L_0000000004161a20;  1 drivers
+v0000000003cf2ef0_0 .net "nand1_out", 0 0, L_0000000004162970;  1 drivers
+S_00000000029ec9e0 .scope module, "sky130_fd_sc_hd__a32oi_4" "sky130_fd_sc_hd__a32oi_4" 4 101097;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003c75a68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf3f30_0 .net "A1", 0 0, o0000000003c75a68;  0 drivers
+o0000000003c75a98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf4610_0 .net "A2", 0 0, o0000000003c75a98;  0 drivers
+o0000000003c75ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf33f0_0 .net "A3", 0 0, o0000000003c75ac8;  0 drivers
+o0000000003c75af8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf3490_0 .net "B1", 0 0, o0000000003c75af8;  0 drivers
+o0000000003c75b28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf21d0_0 .net "B2", 0 0, o0000000003c75b28;  0 drivers
+L_000000000408a950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf2e50_0 .net8 "VGND", 0 0, L_000000000408a950;  1 drivers, strength-aware
+L_000000000408ab80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3530_0 .net8 "VNB", 0 0, L_000000000408ab80;  1 drivers, strength-aware
+L_000000000408ca90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf46b0_0 .net8 "VPB", 0 0, L_000000000408ca90;  1 drivers, strength-aware
+L_000000000408d430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3850_0 .net8 "VPWR", 0 0, L_000000000408d430;  1 drivers, strength-aware
+v0000000003cf44d0_0 .net "Y", 0 0, L_00000000041631c0;  1 drivers
+S_0000000003d0beb0 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101119, 4 101575 1, S_00000000029ec9e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004162eb0 .functor NAND 1, o0000000003c75a98, o0000000003c75a68, o0000000003c75ac8, C4<1>;
+L_00000000041630e0 .functor NAND 1, o0000000003c75b28, o0000000003c75af8, C4<1>, C4<1>;
+L_0000000004163150 .functor AND 1, L_0000000004162eb0, L_00000000041630e0, C4<1>, C4<1>;
+L_00000000041631c0 .functor BUF 1, L_0000000004163150, C4<0>, C4<0>, C4<0>;
+v0000000003cf3a30_0 .net "A1", 0 0, o0000000003c75a68;  alias, 0 drivers
+v0000000003cf3b70_0 .net "A2", 0 0, o0000000003c75a98;  alias, 0 drivers
+v0000000003cf2810_0 .net "A3", 0 0, o0000000003c75ac8;  alias, 0 drivers
+v0000000003cf3670_0 .net "B1", 0 0, o0000000003c75af8;  alias, 0 drivers
+v0000000003cf2130_0 .net "B2", 0 0, o0000000003c75b28;  alias, 0 drivers
+L_000000000408cda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf24f0_0 .net8 "VGND", 0 0, L_000000000408cda0;  1 drivers, strength-aware
+L_000000000408d9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf2950_0 .net8 "VNB", 0 0, L_000000000408d9e0;  1 drivers, strength-aware
+L_000000000408c0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3710_0 .net8 "VPB", 0 0, L_000000000408c0f0;  1 drivers, strength-aware
+L_000000000408d3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3170_0 .net8 "VPWR", 0 0, L_000000000408d3c0;  1 drivers, strength-aware
+v0000000003cf28b0_0 .net "Y", 0 0, L_00000000041631c0;  alias, 1 drivers
+v0000000003cf2d10_0 .net "and0_out_Y", 0 0, L_0000000004163150;  1 drivers
+v0000000003cf37b0_0 .net "nand0_out", 0 0, L_0000000004162eb0;  1 drivers
+v0000000003cf29f0_0 .net "nand1_out", 0 0, L_00000000041630e0;  1 drivers
+S_00000000029ee060 .scope module, "sky130_fd_sc_hd__a41o_1" "sky130_fd_sc_hd__a41o_1" 4 17450;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c75fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf4250_0 .net "A1", 0 0, o0000000003c75fd8;  0 drivers
+o0000000003c76008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf26d0_0 .net "A2", 0 0, o0000000003c76008;  0 drivers
+o0000000003c76038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf2770_0 .net "A3", 0 0, o0000000003c76038;  0 drivers
+o0000000003c76068 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf42f0_0 .net "A4", 0 0, o0000000003c76068;  0 drivers
+o0000000003c76098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf2bd0_0 .net "B1", 0 0, o0000000003c76098;  0 drivers
+L_000000000408ca20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4390_0 .net8 "VGND", 0 0, L_000000000408ca20;  1 drivers, strength-aware
+L_000000000408d900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4430_0 .net8 "VNB", 0 0, L_000000000408d900;  1 drivers, strength-aware
+L_000000000408c860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4570_0 .net8 "VPB", 0 0, L_000000000408c860;  1 drivers, strength-aware
+L_000000000408c4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5f10_0 .net8 "VPWR", 0 0, L_000000000408c4e0;  1 drivers, strength-aware
+v0000000003cf6870_0 .net "X", 0 0, L_00000000041634d0;  1 drivers
+S_0000000003d0c030 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17472, 4 17068 1, S_00000000029ee060;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004163310 .functor AND 1, o0000000003c75fd8, o0000000003c76008, o0000000003c76038, o0000000003c76068;
+L_0000000004161b00 .functor OR 1, L_0000000004163310, o0000000003c76098, C4<0>, C4<0>;
+L_00000000041634d0 .functor BUF 1, L_0000000004161b00, C4<0>, C4<0>, C4<0>;
+v0000000003cf3df0_0 .net "A1", 0 0, o0000000003c75fd8;  alias, 0 drivers
+v0000000003cf2b30_0 .net "A2", 0 0, o0000000003c76008;  alias, 0 drivers
+v0000000003cf3990_0 .net "A3", 0 0, o0000000003c76038;  alias, 0 drivers
+v0000000003cf2270_0 .net "A4", 0 0, o0000000003c76068;  alias, 0 drivers
+v0000000003cf2450_0 .net "B1", 0 0, o0000000003c76098;  alias, 0 drivers
+L_000000000408dc80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3c10_0 .net8 "VGND", 0 0, L_000000000408dc80;  1 drivers, strength-aware
+L_000000000408d7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4750_0 .net8 "VNB", 0 0, L_000000000408d7b0;  1 drivers, strength-aware
+L_000000000408cef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf3cb0_0 .net8 "VPB", 0 0, L_000000000408cef0;  1 drivers, strength-aware
+L_000000000408c6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf2590_0 .net8 "VPWR", 0 0, L_000000000408c6a0;  1 drivers, strength-aware
+v0000000003cf3fd0_0 .net "X", 0 0, L_00000000041634d0;  alias, 1 drivers
+v0000000003cf4110_0 .net "and0_out", 0 0, L_0000000004163310;  1 drivers
+v0000000003cf41b0_0 .net "or0_out_X", 0 0, L_0000000004161b00;  1 drivers
+S_00000000029ee1e0 .scope module, "sky130_fd_sc_hd__a41o_2" "sky130_fd_sc_hd__a41o_2" 4 17324;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c76518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf6a50_0 .net "A1", 0 0, o0000000003c76518;  0 drivers
+o0000000003c76548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5bf0_0 .net "A2", 0 0, o0000000003c76548;  0 drivers
+o0000000003c76578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf4c50_0 .net "A3", 0 0, o0000000003c76578;  0 drivers
+o0000000003c765a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf65f0_0 .net "A4", 0 0, o0000000003c765a8;  0 drivers
+o0000000003c765d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf69b0_0 .net "B1", 0 0, o0000000003c765d8;  0 drivers
+L_000000000408cf60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf67d0_0 .net8 "VGND", 0 0, L_000000000408cf60;  1 drivers, strength-aware
+L_000000000408c2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4e30_0 .net8 "VNB", 0 0, L_000000000408c2b0;  1 drivers, strength-aware
+L_000000000408dac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4930_0 .net8 "VPB", 0 0, L_000000000408dac0;  1 drivers, strength-aware
+L_000000000408cb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf58d0_0 .net8 "VPWR", 0 0, L_000000000408cb00;  1 drivers, strength-aware
+v0000000003cf6910_0 .net "X", 0 0, L_00000000041633f0;  1 drivers
+S_0000000003d0b5b0 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17346, 4 17068 1, S_00000000029ee1e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_00000000041625f0 .functor AND 1, o0000000003c76518, o0000000003c76548, o0000000003c76578, o0000000003c765a8;
+L_0000000004161b70 .functor OR 1, L_00000000041625f0, o0000000003c765d8, C4<0>, C4<0>;
+L_00000000041633f0 .functor BUF 1, L_0000000004161b70, C4<0>, C4<0>, C4<0>;
+v0000000003cf6370_0 .net "A1", 0 0, o0000000003c76518;  alias, 0 drivers
+v0000000003cf55b0_0 .net "A2", 0 0, o0000000003c76548;  alias, 0 drivers
+v0000000003cf5290_0 .net "A3", 0 0, o0000000003c76578;  alias, 0 drivers
+v0000000003cf6410_0 .net "A4", 0 0, o0000000003c765a8;  alias, 0 drivers
+v0000000003cf49d0_0 .net "B1", 0 0, o0000000003c765d8;  alias, 0 drivers
+L_000000000408cfd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4cf0_0 .net8 "VGND", 0 0, L_000000000408cfd0;  1 drivers, strength-aware
+L_000000000408d820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6190_0 .net8 "VNB", 0 0, L_000000000408d820;  1 drivers, strength-aware
+L_000000000408ce10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf64b0_0 .net8 "VPB", 0 0, L_000000000408ce10;  1 drivers, strength-aware
+L_000000000408da50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf4b10_0 .net8 "VPWR", 0 0, L_000000000408da50;  1 drivers, strength-aware
+v0000000003cf6b90_0 .net "X", 0 0, L_00000000041633f0;  alias, 1 drivers
+v0000000003cf4f70_0 .net "and0_out", 0 0, L_00000000041625f0;  1 drivers
+v0000000003cf6690_0 .net "or0_out_X", 0 0, L_0000000004161b70;  1 drivers
+S_00000000029edee0 .scope module, "sky130_fd_sc_hd__a41o_4" "sky130_fd_sc_hd__a41o_4" 4 17198;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c76a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf6af0_0 .net "A1", 0 0, o0000000003c76a58;  0 drivers
+o0000000003c76a88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf6ff0_0 .net "A2", 0 0, o0000000003c76a88;  0 drivers
+o0000000003c76ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5b50_0 .net "A3", 0 0, o0000000003c76ab8;  0 drivers
+o0000000003c76ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5650_0 .net "A4", 0 0, o0000000003c76ae8;  0 drivers
+o0000000003c76b18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf6230_0 .net "B1", 0 0, o0000000003c76b18;  0 drivers
+L_000000000408d040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6d70_0 .net8 "VGND", 0 0, L_000000000408d040;  1 drivers, strength-aware
+L_000000000408d510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6f50_0 .net8 "VNB", 0 0, L_000000000408d510;  1 drivers, strength-aware
+L_000000000408c470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5c90_0 .net8 "VPB", 0 0, L_000000000408c470;  1 drivers, strength-aware
+L_000000000408c550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6730_0 .net8 "VPWR", 0 0, L_000000000408c550;  1 drivers, strength-aware
+v0000000003cf6cd0_0 .net "X", 0 0, L_0000000004162c80;  1 drivers
+S_0000000003d0b8b0 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17220, 4 17068 1, S_00000000029edee0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_00000000041627b0 .functor AND 1, o0000000003c76a58, o0000000003c76a88, o0000000003c76ab8, o0000000003c76ae8;
+L_0000000004161be0 .functor OR 1, L_00000000041627b0, o0000000003c76b18, C4<0>, C4<0>;
+L_0000000004162c80 .functor BUF 1, L_0000000004161be0, C4<0>, C4<0>, C4<0>;
+v0000000003cf4d90_0 .net "A1", 0 0, o0000000003c76a58;  alias, 0 drivers
+v0000000003cf4ed0_0 .net "A2", 0 0, o0000000003c76a88;  alias, 0 drivers
+v0000000003cf4bb0_0 .net "A3", 0 0, o0000000003c76ab8;  alias, 0 drivers
+v0000000003cf5ab0_0 .net "A4", 0 0, o0000000003c76ae8;  alias, 0 drivers
+v0000000003cf5010_0 .net "B1", 0 0, o0000000003c76b18;  alias, 0 drivers
+L_000000000408d4a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6050_0 .net8 "VGND", 0 0, L_000000000408d4a0;  1 drivers, strength-aware
+L_000000000408d580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6550_0 .net8 "VNB", 0 0, L_000000000408d580;  1 drivers, strength-aware
+L_000000000408c1d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5470_0 .net8 "VPB", 0 0, L_000000000408c1d0;  1 drivers, strength-aware
+L_000000000408d5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5830_0 .net8 "VPWR", 0 0, L_000000000408d5f0;  1 drivers, strength-aware
+v0000000003cf60f0_0 .net "X", 0 0, L_0000000004162c80;  alias, 1 drivers
+v0000000003cf50b0_0 .net "and0_out", 0 0, L_00000000041627b0;  1 drivers
+v0000000003cf6eb0_0 .net "or0_out_X", 0 0, L_0000000004161be0;  1 drivers
+S_00000000029ece60 .scope module, "sky130_fd_sc_hd__a41oi_1" "sky130_fd_sc_hd__a41oi_1" 4 31700;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c76f98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5510_0 .net "A1", 0 0, o0000000003c76f98;  0 drivers
+o0000000003c76fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf56f0_0 .net "A2", 0 0, o0000000003c76fc8;  0 drivers
+o0000000003c76ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5790_0 .net "A3", 0 0, o0000000003c76ff8;  0 drivers
+o0000000003c77028 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5a10_0 .net "A4", 0 0, o0000000003c77028;  0 drivers
+o0000000003c77058 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf5e70_0 .net "B1", 0 0, o0000000003c77058;  0 drivers
+L_000000000408d270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5fb0_0 .net8 "VGND", 0 0, L_000000000408d270;  1 drivers, strength-aware
+L_000000000408db30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9250_0 .net8 "VNB", 0 0, L_000000000408db30;  1 drivers, strength-aware
+L_000000000408dba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8170_0 .net8 "VPB", 0 0, L_000000000408dba0;  1 drivers, strength-aware
+L_000000000408d2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf83f0_0 .net8 "VPWR", 0 0, L_000000000408d2e0;  1 drivers, strength-aware
+v0000000003cf7130_0 .net "Y", 0 0, L_0000000004161c50;  1 drivers
+S_0000000003d0ba30 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31722, 4 32292 1, S_00000000029ece60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004162190 .functor AND 1, o0000000003c76f98, o0000000003c76fc8, o0000000003c76ff8, o0000000003c77028;
+L_00000000041629e0 .functor NOR 1, o0000000003c77058, L_0000000004162190, C4<0>, C4<0>;
+L_0000000004161c50 .functor BUF 1, L_00000000041629e0, C4<0>, C4<0>, C4<0>;
+v0000000003cf6c30_0 .net "A1", 0 0, o0000000003c76f98;  alias, 0 drivers
+v0000000003cf5150_0 .net "A2", 0 0, o0000000003c76fc8;  alias, 0 drivers
+v0000000003cf5dd0_0 .net "A3", 0 0, o0000000003c76ff8;  alias, 0 drivers
+v0000000003cf62d0_0 .net "A4", 0 0, o0000000003c77028;  alias, 0 drivers
+v0000000003cf51f0_0 .net "B1", 0 0, o0000000003c77058;  alias, 0 drivers
+L_000000000408d660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5330_0 .net8 "VGND", 0 0, L_000000000408d660;  1 drivers, strength-aware
+L_000000000408d0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf6e10_0 .net8 "VNB", 0 0, L_000000000408d0b0;  1 drivers, strength-aware
+L_000000000408d120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf5970_0 .net8 "VPB", 0 0, L_000000000408d120;  1 drivers, strength-aware
+L_000000000408cb70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf53d0_0 .net8 "VPWR", 0 0, L_000000000408cb70;  1 drivers, strength-aware
+v0000000003cf5d30_0 .net "Y", 0 0, L_0000000004161c50;  alias, 1 drivers
+v0000000003cf4a70_0 .net "and0_out", 0 0, L_0000000004162190;  1 drivers
+v0000000003cf7090_0 .net "nor0_out_Y", 0 0, L_00000000041629e0;  1 drivers
+S_00000000029ee7e0 .scope module, "sky130_fd_sc_hd__a41oi_2" "sky130_fd_sc_hd__a41oi_2" 4 31952;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c774d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf97f0_0 .net "A1", 0 0, o0000000003c774d8;  0 drivers
+o0000000003c77508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf8b70_0 .net "A2", 0 0, o0000000003c77508;  0 drivers
+o0000000003c77538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7db0_0 .net "A3", 0 0, o0000000003c77538;  0 drivers
+o0000000003c77568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7a90_0 .net "A4", 0 0, o0000000003c77568;  0 drivers
+o0000000003c77598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7810_0 .net "B1", 0 0, o0000000003c77598;  0 drivers
+L_000000000408c8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf71d0_0 .net8 "VGND", 0 0, L_000000000408c8d0;  1 drivers, strength-aware
+L_000000000408d350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8c10_0 .net8 "VNB", 0 0, L_000000000408d350;  1 drivers, strength-aware
+L_000000000408c320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8490_0 .net8 "VPB", 0 0, L_000000000408c320;  1 drivers, strength-aware
+L_000000000408dc10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8530_0 .net8 "VPWR", 0 0, L_000000000408dc10;  1 drivers, strength-aware
+v0000000003cf7310_0 .net "Y", 0 0, L_0000000004162ba0;  1 drivers
+S_0000000003d0cab0 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31974, 4 32292 1, S_00000000029ee7e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004162b30 .functor AND 1, o0000000003c774d8, o0000000003c77508, o0000000003c77538, o0000000003c77568;
+L_0000000004161d30 .functor NOR 1, o0000000003c77598, L_0000000004162b30, C4<0>, C4<0>;
+L_0000000004162ba0 .functor BUF 1, L_0000000004161d30, C4<0>, C4<0>, C4<0>;
+v0000000003cf7ef0_0 .net "A1", 0 0, o0000000003c774d8;  alias, 0 drivers
+v0000000003cf7770_0 .net "A2", 0 0, o0000000003c77508;  alias, 0 drivers
+v0000000003cf9750_0 .net "A3", 0 0, o0000000003c77538;  alias, 0 drivers
+v0000000003cf7450_0 .net "A4", 0 0, o0000000003c77568;  alias, 0 drivers
+v0000000003cf8cb0_0 .net "B1", 0 0, o0000000003c77598;  alias, 0 drivers
+L_000000000408c160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf79f0_0 .net8 "VGND", 0 0, L_000000000408c160;  1 drivers, strength-aware
+L_000000000408d6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7c70_0 .net8 "VNB", 0 0, L_000000000408d6d0;  1 drivers, strength-aware
+L_000000000408c710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8fd0_0 .net8 "VPB", 0 0, L_000000000408c710;  1 drivers, strength-aware
+L_000000000408c780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8d50_0 .net8 "VPWR", 0 0, L_000000000408c780;  1 drivers, strength-aware
+v0000000003cf8a30_0 .net "Y", 0 0, L_0000000004162ba0;  alias, 1 drivers
+v0000000003cf9070_0 .net "and0_out", 0 0, L_0000000004162b30;  1 drivers
+v0000000003cf9570_0 .net "nor0_out_Y", 0 0, L_0000000004161d30;  1 drivers
+S_00000000029ecfe0 .scope module, "sky130_fd_sc_hd__a41oi_4" "sky130_fd_sc_hd__a41oi_4" 4 31826;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003c77a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7950_0 .net "A1", 0 0, o0000000003c77a18;  0 drivers
+o0000000003c77a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf74f0_0 .net "A2", 0 0, o0000000003c77a48;  0 drivers
+o0000000003c77a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7590_0 .net "A3", 0 0, o0000000003c77a78;  0 drivers
+o0000000003c77aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf73b0_0 .net "A4", 0 0, o0000000003c77aa8;  0 drivers
+o0000000003c77ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf7e50_0 .net "B1", 0 0, o0000000003c77ad8;  0 drivers
+L_000000000408d190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf76d0_0 .net8 "VGND", 0 0, L_000000000408d190;  1 drivers, strength-aware
+L_000000000408c5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7b30_0 .net8 "VNB", 0 0, L_000000000408c5c0;  1 drivers, strength-aware
+L_000000000408cbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf80d0_0 .net8 "VPB", 0 0, L_000000000408cbe0;  1 drivers, strength-aware
+L_000000000408c630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7f90_0 .net8 "VPWR", 0 0, L_000000000408c630;  1 drivers, strength-aware
+v0000000003cf8030_0 .net "Y", 0 0, L_0000000004161fd0;  1 drivers
+S_0000000003d0cc30 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31848, 4 32292 1, S_00000000029ecfe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004161ef0 .functor AND 1, o0000000003c77a18, o0000000003c77a48, o0000000003c77a78, o0000000003c77aa8;
+L_0000000004162660 .functor NOR 1, o0000000003c77ad8, L_0000000004161ef0, C4<0>, C4<0>;
+L_0000000004161fd0 .functor BUF 1, L_0000000004162660, C4<0>, C4<0>, C4<0>;
+v0000000003cf8df0_0 .net "A1", 0 0, o0000000003c77a18;  alias, 0 drivers
+v0000000003cf88f0_0 .net "A2", 0 0, o0000000003c77a48;  alias, 0 drivers
+v0000000003cf8e90_0 .net "A3", 0 0, o0000000003c77a78;  alias, 0 drivers
+v0000000003cf8710_0 .net "A4", 0 0, o0000000003c77aa8;  alias, 0 drivers
+v0000000003cf8f30_0 .net "B1", 0 0, o0000000003c77ad8;  alias, 0 drivers
+L_000000000408c7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf85d0_0 .net8 "VGND", 0 0, L_000000000408c7f0;  1 drivers, strength-aware
+L_000000000408d740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9110_0 .net8 "VNB", 0 0, L_000000000408d740;  1 drivers, strength-aware
+L_000000000408d890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7630_0 .net8 "VPB", 0 0, L_000000000408d890;  1 drivers, strength-aware
+L_000000000408cc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7270_0 .net8 "VPWR", 0 0, L_000000000408cc50;  1 drivers, strength-aware
+v0000000003cf8ad0_0 .net "Y", 0 0, L_0000000004161fd0;  alias, 1 drivers
+v0000000003cf91b0_0 .net "and0_out", 0 0, L_0000000004161ef0;  1 drivers
+v0000000003cf78b0_0 .net "nor0_out_Y", 0 0, L_0000000004162660;  1 drivers
+S_00000000029ee360 .scope module, "sky130_fd_sc_hd__and2_0" "sky130_fd_sc_hd__and2_0" 4 52526;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003c77f58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf8350_0 .net "A", 0 0, o0000000003c77f58;  0 drivers
+o0000000003c77f88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf87b0_0 .net "B", 0 0, o0000000003c77f88;  0 drivers
+L_000000000408c940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9430_0 .net8 "VGND", 0 0, L_000000000408c940;  1 drivers, strength-aware
+L_000000000408cd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9890_0 .net8 "VNB", 0 0, L_000000000408cd30;  1 drivers, strength-aware
+L_000000000408d970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf7d10_0 .net8 "VPB", 0 0, L_000000000408d970;  1 drivers, strength-aware
+L_000000000408d200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8850_0 .net8 "VPWR", 0 0, L_000000000408d200;  1 drivers, strength-aware
+v0000000003cf8990_0 .net "X", 0 0, L_0000000004162cf0;  1 drivers
+S_0000000003d07230 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52542, 4 52415 1, S_00000000029ee360;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004162c10 .functor AND 1, o0000000003c77f58, o0000000003c77f88, C4<1>, C4<1>;
+L_0000000004162cf0 .functor BUF 1, L_0000000004162c10, C4<0>, C4<0>, C4<0>;
+v0000000003cf94d0_0 .net "A", 0 0, o0000000003c77f58;  alias, 0 drivers
+v0000000003cf82b0_0 .net "B", 0 0, o0000000003c77f88;  alias, 0 drivers
+L_000000000408c240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf92f0_0 .net8 "VGND", 0 0, L_000000000408c240;  1 drivers, strength-aware
+L_000000000408c390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8670_0 .net8 "VNB", 0 0, L_000000000408c390;  1 drivers, strength-aware
+L_000000000408c400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf8210_0 .net8 "VPB", 0 0, L_000000000408c400;  1 drivers, strength-aware
+L_000000000408c9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9390_0 .net8 "VPWR", 0 0, L_000000000408c9b0;  1 drivers, strength-aware
+v0000000003cf9610_0 .net "X", 0 0, L_0000000004162cf0;  alias, 1 drivers
+v0000000003cf96b0_0 .net "and0_out_X", 0 0, L_0000000004162c10;  1 drivers
+S_00000000029ee660 .scope module, "sky130_fd_sc_hd__and2_1" "sky130_fd_sc_hd__and2_1" 4 52632;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003c782b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfa470_0 .net "A", 0 0, o0000000003c782b8;  0 drivers
+o0000000003c782e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfae70_0 .net "B", 0 0, o0000000003c782e8;  0 drivers
+L_000000000408ccc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa8d0_0 .net8 "VGND", 0 0, L_000000000408ccc0;  1 drivers, strength-aware
+L_000000000408ce80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9cf0_0 .net8 "VNB", 0 0, L_000000000408ce80;  1 drivers, strength-aware
+L_000000000408eee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfaf10_0 .net8 "VPB", 0 0, L_000000000408eee0;  1 drivers, strength-aware
+L_000000000408f3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa0b0_0 .net8 "VPWR", 0 0, L_000000000408f3b0;  1 drivers, strength-aware
+v0000000003cfb050_0 .net "X", 0 0, L_0000000004162040;  1 drivers
+S_0000000003d0c1b0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52648, 4 52415 1, S_00000000029ee660;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004161da0 .functor AND 1, o0000000003c782b8, o0000000003c782e8, C4<1>, C4<1>;
+L_0000000004162040 .functor BUF 1, L_0000000004161da0, C4<0>, C4<0>, C4<0>;
+v0000000003cf7bd0_0 .net "A", 0 0, o0000000003c782b8;  alias, 0 drivers
+v0000000003cfad30_0 .net "B", 0 0, o0000000003c782e8;  alias, 0 drivers
+L_000000000408ee00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa830_0 .net8 "VGND", 0 0, L_000000000408ee00;  1 drivers, strength-aware
+L_000000000408e770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9c50_0 .net8 "VNB", 0 0, L_000000000408e770;  1 drivers, strength-aware
+L_000000000408e1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfabf0_0 .net8 "VPB", 0 0, L_000000000408e1c0;  1 drivers, strength-aware
+L_000000000408f570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa6f0_0 .net8 "VPWR", 0 0, L_000000000408f570;  1 drivers, strength-aware
+v0000000003cfadd0_0 .net "X", 0 0, L_0000000004162040;  alias, 1 drivers
+v0000000003cfac90_0 .net "and0_out_X", 0 0, L_0000000004161da0;  1 drivers
+S_00000000029ee4e0 .scope module, "sky130_fd_sc_hd__and2_4" "sky130_fd_sc_hd__and2_4" 4 52118;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003c78618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfbe10_0 .net "A", 0 0, o0000000003c78618;  0 drivers
+o0000000003c78648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfbeb0_0 .net "B", 0 0, o0000000003c78648;  0 drivers
+L_000000000408e000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb230_0 .net8 "VGND", 0 0, L_000000000408e000;  1 drivers, strength-aware
+L_000000000408f180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfab50_0 .net8 "VNB", 0 0, L_000000000408f180;  1 drivers, strength-aware
+L_000000000408e540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa010_0 .net8 "VPB", 0 0, L_000000000408e540;  1 drivers, strength-aware
+L_000000000408dd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfbf50_0 .net8 "VPWR", 0 0, L_000000000408dd60;  1 drivers, strength-aware
+v0000000003cf9a70_0 .net "X", 0 0, L_0000000004163770;  1 drivers
+S_0000000003d0c330 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52134, 4 52415 1, S_00000000029ee4e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041620b0 .functor AND 1, o0000000003c78618, o0000000003c78648, C4<1>, C4<1>;
+L_0000000004163770 .functor BUF 1, L_00000000041620b0, C4<0>, C4<0>, C4<0>;
+v0000000003cfba50_0 .net "A", 0 0, o0000000003c78618;  alias, 0 drivers
+v0000000003cfafb0_0 .net "B", 0 0, o0000000003c78648;  alias, 0 drivers
+L_000000000408f5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb0f0_0 .net8 "VGND", 0 0, L_000000000408f5e0;  1 drivers, strength-aware
+L_000000000408f260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9930_0 .net8 "VNB", 0 0, L_000000000408f260;  1 drivers, strength-aware
+L_000000000408f1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb9b0_0 .net8 "VPB", 0 0, L_000000000408f1f0;  1 drivers, strength-aware
+L_000000000408f500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfbd70_0 .net8 "VPWR", 0 0, L_000000000408f500;  1 drivers, strength-aware
+v0000000003cfb190_0 .net "X", 0 0, L_0000000004163770;  alias, 1 drivers
+v0000000003cf99d0_0 .net "and0_out_X", 0 0, L_00000000041620b0;  1 drivers
+S_00000000029ed460 .scope module, "sky130_fd_sc_hd__and2b_1" "sky130_fd_sc_hd__and2b_1" 4 34775;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+o0000000003c78978 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfa290_0 .net "A_N", 0 0, o0000000003c78978;  0 drivers
+o0000000003c789a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfa970_0 .net "B", 0 0, o0000000003c789a8;  0 drivers
+L_000000000408f420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb5f0_0 .net8 "VGND", 0 0, L_000000000408f420;  1 drivers, strength-aware
+L_000000000408e690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb410_0 .net8 "VNB", 0 0, L_000000000408e690;  1 drivers, strength-aware
+L_000000000408e850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb730_0 .net8 "VPB", 0 0, L_000000000408e850;  1 drivers, strength-aware
+L_000000000408eaf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfaa10_0 .net8 "VPWR", 0 0, L_000000000408eaf0;  1 drivers, strength-aware
+v0000000003cfbc30_0 .net "X", 0 0, L_00000000041637e0;  1 drivers
+S_0000000003d0c4b0 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34791, 4 34662 1, S_00000000029ed460;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004163930 .functor NOT 1, o0000000003c78978, C4<0>, C4<0>, C4<0>;
+L_0000000004164a40 .functor AND 1, L_0000000004163930, o0000000003c789a8, C4<1>, C4<1>;
+L_00000000041637e0 .functor BUF 1, L_0000000004164a40, C4<0>, C4<0>, C4<0>;
+v0000000003cfb550_0 .net "A_N", 0 0, o0000000003c78978;  alias, 0 drivers
+v0000000003cfb2d0_0 .net "B", 0 0, o0000000003c789a8;  alias, 0 drivers
+L_000000000408f0a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb910_0 .net8 "VGND", 0 0, L_000000000408f0a0;  1 drivers, strength-aware
+L_000000000408f6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb370_0 .net8 "VNB", 0 0, L_000000000408f6c0;  1 drivers, strength-aware
+L_000000000408e2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfb690_0 .net8 "VPB", 0 0, L_000000000408e2a0;  1 drivers, strength-aware
+L_000000000408e8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa150_0 .net8 "VPWR", 0 0, L_000000000408e8c0;  1 drivers, strength-aware
+v0000000003cfa1f0_0 .net "X", 0 0, L_00000000041637e0;  alias, 1 drivers
+v0000000003cf9d90_0 .net "and0_out_X", 0 0, L_0000000004164a40;  1 drivers
+v0000000003cfb4b0_0 .net "not0_out", 0 0, L_0000000004163930;  1 drivers
+S_00000000029ed8e0 .scope module, "sky130_fd_sc_hd__and2b_4" "sky130_fd_sc_hd__and2b_4" 4 34359;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+o0000000003c78d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cfa5b0_0 .net "A_N", 0 0, o0000000003c78d08;  0 drivers
+o0000000003c78d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003cf9ed0_0 .net "B", 0 0, o0000000003c78d38;  0 drivers
+L_000000000408ee70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9f70_0 .net8 "VGND", 0 0, L_000000000408ee70;  1 drivers, strength-aware
+L_000000000408f730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfaab0_0 .net8 "VNB", 0 0, L_000000000408f730;  1 drivers, strength-aware
+L_000000000408f490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa3d0_0 .net8 "VPB", 0 0, L_000000000408f490;  1 drivers, strength-aware
+L_000000000408e4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfa510_0 .net8 "VPWR", 0 0, L_000000000408e4d0;  1 drivers, strength-aware
+v0000000003cfa650_0 .net "X", 0 0, L_0000000004164490;  1 drivers
+S_0000000003d07530 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34375, 4 34662 1, S_00000000029ed8e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004163850 .functor NOT 1, o0000000003c78d08, C4<0>, C4<0>, C4<0>;
+L_0000000004163fc0 .functor AND 1, L_0000000004163850, o0000000003c78d38, C4<1>, C4<1>;
+L_0000000004164490 .functor BUF 1, L_0000000004163fc0, C4<0>, C4<0>, C4<0>;
+v0000000003cfb7d0_0 .net "A_N", 0 0, o0000000003c78d08;  alias, 0 drivers
+v0000000003cfb870_0 .net "B", 0 0, o0000000003c78d38;  alias, 0 drivers
+L_000000000408f110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfbaf0_0 .net8 "VGND", 0 0, L_000000000408f110;  1 drivers, strength-aware
+L_000000000408eb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003cfbb90_0 .net8 "VNB", 0 0, L_000000000408eb60;  1 drivers, strength-aware
+L_000000000408ef50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cfbcd0_0 .net8 "VPB", 0 0, L_000000000408ef50;  1 drivers, strength-aware
+L_000000000408f650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003cf9b10_0 .net8 "VPWR", 0 0, L_000000000408f650;  1 drivers, strength-aware
+v0000000003cf9bb0_0 .net "X", 0 0, L_0000000004164490;  alias, 1 drivers
+v0000000003cfa330_0 .net "and0_out_X", 0 0, L_0000000004163fc0;  1 drivers
+v0000000003cf9e30_0 .net "not0_out", 0 0, L_0000000004163850;  1 drivers
+S_00000000029ed160 .scope module, "sky130_fd_sc_hd__and3_1" "sky130_fd_sc_hd__and3_1" 4 9901;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c79098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3cad0_0 .net "A", 0 0, o0000000003c79098;  0 drivers
+o0000000003c790c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3c8f0_0 .net "B", 0 0, o0000000003c790c8;  0 drivers
+o0000000003c790f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3d570_0 .net "C", 0 0, o0000000003c790f8;  0 drivers
+L_000000000408e9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ce90_0 .net8 "VGND", 0 0, L_000000000408e9a0;  1 drivers, strength-aware
+L_000000000408de40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ccb0_0 .net8 "VNB", 0 0, L_000000000408de40;  1 drivers, strength-aware
+L_000000000408e310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c2b0_0 .net8 "VPB", 0 0, L_000000000408e310;  1 drivers, strength-aware
+L_000000000408deb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3cb70_0 .net8 "VPWR", 0 0, L_000000000408deb0;  1 drivers, strength-aware
+v0000000003d3be50_0 .net "X", 0 0, L_00000000041650d0;  1 drivers
+S_0000000003d0c630 .scope module, "base" "sky130_fd_sc_hd__and3" 4 9919, 4 10319 1, S_00000000029ed160;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004165060 .functor AND 1, o0000000003c790f8, o0000000003c79098, o0000000003c790c8, C4<1>;
+L_00000000041650d0 .functor BUF 1, L_0000000004165060, C4<0>, C4<0>, C4<0>;
+v0000000003cfa790_0 .net "A", 0 0, o0000000003c79098;  alias, 0 drivers
+v0000000003d3c850_0 .net "B", 0 0, o0000000003c790c8;  alias, 0 drivers
+v0000000003d3bef0_0 .net "C", 0 0, o0000000003c790f8;  alias, 0 drivers
+L_000000000408e5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c3f0_0 .net8 "VGND", 0 0, L_000000000408e5b0;  1 drivers, strength-aware
+L_000000000408f880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d6b0_0 .net8 "VNB", 0 0, L_000000000408f880;  1 drivers, strength-aware
+L_000000000408ec40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b4f0_0 .net8 "VPB", 0 0, L_000000000408ec40;  1 drivers, strength-aware
+L_000000000408ebd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c710_0 .net8 "VPWR", 0 0, L_000000000408ebd0;  1 drivers, strength-aware
+v0000000003d3d4d0_0 .net "X", 0 0, L_00000000041650d0;  alias, 1 drivers
+v0000000003d3d070_0 .net "and0_out_X", 0 0, L_0000000004165060;  1 drivers
+S_00000000029ed2e0 .scope module, "sky130_fd_sc_hd__and3_2" "sky130_fd_sc_hd__and3_2" 4 10013;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c79488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3bc70_0 .net "A", 0 0, o0000000003c79488;  0 drivers
+o0000000003c794b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3cd50_0 .net "B", 0 0, o0000000003c794b8;  0 drivers
+o0000000003c794e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3c7b0_0 .net "C", 0 0, o0000000003c794e8;  0 drivers
+L_000000000408dcf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d110_0 .net8 "VGND", 0 0, L_000000000408dcf0;  1 drivers, strength-aware
+L_000000000408f7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d890_0 .net8 "VNB", 0 0, L_000000000408f7a0;  1 drivers, strength-aware
+L_000000000408ddd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3cdf0_0 .net8 "VPB", 0 0, L_000000000408ddd0;  1 drivers, strength-aware
+L_000000000408df20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b130_0 .net8 "VPWR", 0 0, L_000000000408df20;  1 drivers, strength-aware
+v0000000003d3b590_0 .net "X", 0 0, L_0000000004163d20;  1 drivers
+S_0000000003d0ed30 .scope module, "base" "sky130_fd_sc_hd__and3" 4 10031, 4 10319 1, S_00000000029ed2e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004163540 .functor AND 1, o0000000003c794e8, o0000000003c79488, o0000000003c794b8, C4<1>;
+L_0000000004163d20 .functor BUF 1, L_0000000004163540, C4<0>, C4<0>, C4<0>;
+v0000000003d3c030_0 .net "A", 0 0, o0000000003c79488;  alias, 0 drivers
+v0000000003d3c670_0 .net "B", 0 0, o0000000003c794b8;  alias, 0 drivers
+v0000000003d3d610_0 .net "C", 0 0, o0000000003c794e8;  alias, 0 drivers
+L_000000000408f2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b9f0_0 .net8 "VGND", 0 0, L_000000000408f2d0;  1 drivers, strength-aware
+L_000000000408e230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b3b0_0 .net8 "VNB", 0 0, L_000000000408e230;  1 drivers, strength-aware
+L_000000000408ea80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3bdb0_0 .net8 "VPB", 0 0, L_000000000408ea80;  1 drivers, strength-aware
+L_000000000408efc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c990_0 .net8 "VPWR", 0 0, L_000000000408efc0;  1 drivers, strength-aware
+v0000000003d3d750_0 .net "X", 0 0, L_0000000004163d20;  alias, 1 drivers
+v0000000003d3d7f0_0 .net "and0_out_X", 0 0, L_0000000004163540;  1 drivers
+S_00000000029ed5e0 .scope module, "sky130_fd_sc_hd__and3_4" "sky130_fd_sc_hd__and3_4" 4 9789;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c79878 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3d1b0_0 .net "A", 0 0, o0000000003c79878;  0 drivers
+o0000000003c798a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3b8b0_0 .net "B", 0 0, o0000000003c798a8;  0 drivers
+o0000000003c798d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3c170_0 .net "C", 0 0, o0000000003c798d8;  0 drivers
+L_000000000408f030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ba90_0 .net8 "VGND", 0 0, L_000000000408f030;  1 drivers, strength-aware
+L_000000000408df90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b450_0 .net8 "VNB", 0 0, L_000000000408df90;  1 drivers, strength-aware
+L_000000000408e620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b950_0 .net8 "VPB", 0 0, L_000000000408e620;  1 drivers, strength-aware
+L_000000000408e070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d250_0 .net8 "VPWR", 0 0, L_000000000408e070;  1 drivers, strength-aware
+v0000000003d3c490_0 .net "X", 0 0, L_0000000004164030;  1 drivers
+S_0000000003d0ebb0 .scope module, "base" "sky130_fd_sc_hd__and3" 4 9807, 4 10319 1, S_00000000029ed5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004163700 .functor AND 1, o0000000003c798d8, o0000000003c79878, o0000000003c798a8, C4<1>;
+L_0000000004164030 .functor BUF 1, L_0000000004163700, C4<0>, C4<0>, C4<0>;
+v0000000003d3b810_0 .net "A", 0 0, o0000000003c79878;  alias, 0 drivers
+v0000000003d3bf90_0 .net "B", 0 0, o0000000003c798a8;  alias, 0 drivers
+v0000000003d3cc10_0 .net "C", 0 0, o0000000003c798d8;  alias, 0 drivers
+L_000000000408e700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ca30_0 .net8 "VGND", 0 0, L_000000000408e700;  1 drivers, strength-aware
+L_000000000408ecb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3cf30_0 .net8 "VNB", 0 0, L_000000000408ecb0;  1 drivers, strength-aware
+L_000000000408ea10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c0d0_0 .net8 "VPB", 0 0, L_000000000408ea10;  1 drivers, strength-aware
+L_000000000408ed20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d390_0 .net8 "VPWR", 0 0, L_000000000408ed20;  1 drivers, strength-aware
+v0000000003d3b770_0 .net "X", 0 0, L_0000000004164030;  alias, 1 drivers
+v0000000003d3cfd0_0 .net "and0_out_X", 0 0, L_0000000004163700;  1 drivers
+S_00000000029edbe0 .scope module, "sky130_fd_sc_hd__and3b_1" "sky130_fd_sc_hd__and3b_1" 4 40615;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c79c68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3b1d0_0 .net "A_N", 0 0, o0000000003c79c68;  0 drivers
+o0000000003c79c98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3b270_0 .net "B", 0 0, o0000000003c79c98;  0 drivers
+o0000000003c79cc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3bbd0_0 .net "C", 0 0, o0000000003c79cc8;  0 drivers
+L_000000000408f340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3bd10_0 .net8 "VGND", 0 0, L_000000000408f340;  1 drivers, strength-aware
+L_000000000408e930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d40090_0 .net8 "VNB", 0 0, L_000000000408e930;  1 drivers, strength-aware
+L_000000000408e0e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f870_0 .net8 "VPB", 0 0, L_000000000408e0e0;  1 drivers, strength-aware
+L_000000000408e150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d930_0 .net8 "VPWR", 0 0, L_000000000408e150;  1 drivers, strength-aware
+v0000000003d3f5f0_0 .net "X", 0 0, L_00000000041640a0;  1 drivers
+S_0000000003d11a30 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40633, 4 40385 1, S_00000000029edbe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004164dc0 .functor NOT 1, o0000000003c79c68, C4<0>, C4<0>, C4<0>;
+L_0000000004164810 .functor AND 1, o0000000003c79cc8, L_0000000004164dc0, o0000000003c79c98, C4<1>;
+L_00000000041640a0 .functor BUF 1, L_0000000004164810, C4<0>, C4<0>, C4<0>;
+v0000000003d3b630_0 .net "A_N", 0 0, o0000000003c79c68;  alias, 0 drivers
+v0000000003d3d2f0_0 .net "B", 0 0, o0000000003c79c98;  alias, 0 drivers
+v0000000003d3bb30_0 .net "C", 0 0, o0000000003c79cc8;  alias, 0 drivers
+L_000000000408e380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c210_0 .net8 "VGND", 0 0, L_000000000408e380;  1 drivers, strength-aware
+L_000000000408e3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b6d0_0 .net8 "VNB", 0 0, L_000000000408e3f0;  1 drivers, strength-aware
+L_000000000408e7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3b310_0 .net8 "VPB", 0 0, L_000000000408e7e0;  1 drivers, strength-aware
+L_000000000408f810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3c350_0 .net8 "VPWR", 0 0, L_000000000408f810;  1 drivers, strength-aware
+v0000000003d3c530_0 .net "X", 0 0, L_00000000041640a0;  alias, 1 drivers
+v0000000003d3d430_0 .net "and0_out_X", 0 0, L_0000000004164810;  1 drivers
+v0000000003d3c5d0_0 .net "not0_out", 0 0, L_0000000004164dc0;  1 drivers
+S_00000000029edd60 .scope module, "sky130_fd_sc_hd__and3b_2" "sky130_fd_sc_hd__and3b_2" 4 40073;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c7a088 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3f2d0_0 .net "A_N", 0 0, o0000000003c7a088;  0 drivers
+o0000000003c7a0b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3e510_0 .net "B", 0 0, o0000000003c7a0b8;  0 drivers
+o0000000003c7a0e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3ee70_0 .net "C", 0 0, o0000000003c7a0e8;  0 drivers
+L_000000000408e460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e8d0_0 .net8 "VGND", 0 0, L_000000000408e460;  1 drivers, strength-aware
+L_000000000408ed90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e0b0_0 .net8 "VNB", 0 0, L_000000000408ed90;  1 drivers, strength-aware
+L_0000000004091330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ec90_0 .net8 "VPB", 0 0, L_0000000004091330;  1 drivers, strength-aware
+L_00000000040903e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3da70_0 .net8 "VPWR", 0 0, L_00000000040903e0;  1 drivers, strength-aware
+v0000000003d3fcd0_0 .net "X", 0 0, L_00000000041638c0;  1 drivers
+S_0000000003d109b0 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40091, 4 40385 1, S_00000000029edd60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004163cb0 .functor NOT 1, o0000000003c7a088, C4<0>, C4<0>, C4<0>;
+L_00000000041641f0 .functor AND 1, o0000000003c7a0e8, L_0000000004163cb0, o0000000003c7a0b8, C4<1>;
+L_00000000041638c0 .functor BUF 1, L_00000000041641f0, C4<0>, C4<0>, C4<0>;
+v0000000003d3feb0_0 .net "A_N", 0 0, o0000000003c7a088;  alias, 0 drivers
+v0000000003d3f4b0_0 .net "B", 0 0, o0000000003c7a0b8;  alias, 0 drivers
+v0000000003d3eab0_0 .net "C", 0 0, o0000000003c7a0e8;  alias, 0 drivers
+L_0000000004090220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e6f0_0 .net8 "VGND", 0 0, L_0000000004090220;  1 drivers, strength-aware
+L_0000000004090d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3d9d0_0 .net8 "VNB", 0 0, L_0000000004090d10;  1 drivers, strength-aware
+L_000000000408fff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3dd90_0 .net8 "VPB", 0 0, L_000000000408fff0;  1 drivers, strength-aware
+L_000000000408fab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f190_0 .net8 "VPWR", 0 0, L_000000000408fab0;  1 drivers, strength-aware
+v0000000003d3f230_0 .net "X", 0 0, L_00000000041638c0;  alias, 1 drivers
+v0000000003d3e830_0 .net "and0_out_X", 0 0, L_00000000041641f0;  1 drivers
+v0000000003d3e790_0 .net "not0_out", 0 0, L_0000000004163cb0;  1 drivers
+S_00000000030e4870 .scope module, "sky130_fd_sc_hd__and3b_4" "sky130_fd_sc_hd__and3b_4" 4 40503;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003c7a4a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3dc50_0 .net "A_N", 0 0, o0000000003c7a4a8;  0 drivers
+o0000000003c7a4d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3f690_0 .net "B", 0 0, o0000000003c7a4d8;  0 drivers
+o0000000003c7a508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3e330_0 .net "C", 0 0, o0000000003c7a508;  0 drivers
+L_0000000004090e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f370_0 .net8 "VGND", 0 0, L_0000000004090e60;  1 drivers, strength-aware
+L_000000000408f8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3efb0_0 .net8 "VNB", 0 0, L_000000000408f8f0;  1 drivers, strength-aware
+L_00000000040906f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3dcf0_0 .net8 "VPB", 0 0, L_00000000040906f0;  1 drivers, strength-aware
+L_000000000408fea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3faf0_0 .net8 "VPWR", 0 0, L_000000000408fea0;  1 drivers, strength-aware
+v0000000003d3e970_0 .net "X", 0 0, L_00000000041649d0;  1 drivers
+S_0000000003d0d6b0 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40521, 4 40385 1, S_00000000030e4870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_00000000041639a0 .functor NOT 1, o0000000003c7a4a8, C4<0>, C4<0>, C4<0>;
+L_0000000004163a10 .functor AND 1, o0000000003c7a508, L_00000000041639a0, o0000000003c7a4d8, C4<1>;
+L_00000000041649d0 .functor BUF 1, L_0000000004163a10, C4<0>, C4<0>, C4<0>;
+v0000000003d3fb90_0 .net "A_N", 0 0, o0000000003c7a4a8;  alias, 0 drivers
+v0000000003d3ef10_0 .net "B", 0 0, o0000000003c7a4d8;  alias, 0 drivers
+v0000000003d3ed30_0 .net "C", 0 0, o0000000003c7a508;  alias, 0 drivers
+L_0000000004090840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3db10_0 .net8 "VGND", 0 0, L_0000000004090840;  1 drivers, strength-aware
+L_000000000408fdc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3fa50_0 .net8 "VNB", 0 0, L_000000000408fdc0;  1 drivers, strength-aware
+L_00000000040904c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3fe10_0 .net8 "VPB", 0 0, L_00000000040904c0;  1 drivers, strength-aware
+L_000000000408fb90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3edd0_0 .net8 "VPWR", 0 0, L_000000000408fb90;  1 drivers, strength-aware
+v0000000003d3dbb0_0 .net "X", 0 0, L_00000000041649d0;  alias, 1 drivers
+v0000000003d3f550_0 .net "and0_out_X", 0 0, L_0000000004163a10;  1 drivers
+v0000000003d3fd70_0 .net "not0_out", 0 0, L_00000000041639a0;  1 drivers
+S_00000000030e34f0 .scope module, "sky130_fd_sc_hd__and4_1" "sky130_fd_sc_hd__and4_1" 4 83588;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7a8c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3f050_0 .net "A", 0 0, o0000000003c7a8c8;  0 drivers
+o0000000003c7a8f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3ff50_0 .net "B", 0 0, o0000000003c7a8f8;  0 drivers
+o0000000003c7a928 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3f910_0 .net "C", 0 0, o0000000003c7a928;  0 drivers
+o0000000003c7a958 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d3e010_0 .net "D", 0 0, o0000000003c7a958;  0 drivers
+L_0000000004090760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e150_0 .net8 "VGND", 0 0, L_0000000004090760;  1 drivers, strength-aware
+L_0000000004090290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e1f0_0 .net8 "VNB", 0 0, L_0000000004090290;  1 drivers, strength-aware
+L_0000000004090d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ebf0_0 .net8 "VPB", 0 0, L_0000000004090d80;  1 drivers, strength-aware
+L_00000000040908b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3e650_0 .net8 "VPWR", 0 0, L_00000000040908b0;  1 drivers, strength-aware
+v0000000003d3f0f0_0 .net "X", 0 0, L_0000000004163a80;  1 drivers
+S_0000000003d11430 .scope module, "base" "sky130_fd_sc_hd__and4" 4 83608, 4 83903 1, S_00000000030e34f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004164110 .functor AND 1, o0000000003c7a8c8, o0000000003c7a8f8, o0000000003c7a928, o0000000003c7a958;
+L_0000000004163a80 .functor BUF 1, L_0000000004164110, C4<0>, C4<0>, C4<0>;
+v0000000003d3ea10_0 .net "A", 0 0, o0000000003c7a8c8;  alias, 0 drivers
+v0000000003d3eb50_0 .net "B", 0 0, o0000000003c7a8f8;  alias, 0 drivers
+v0000000003d3de30_0 .net "C", 0 0, o0000000003c7a928;  alias, 0 drivers
+v0000000003d3e5b0_0 .net "D", 0 0, o0000000003c7a958;  alias, 0 drivers
+L_0000000004090140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f410_0 .net8 "VGND", 0 0, L_0000000004090140;  1 drivers, strength-aware
+L_00000000040913a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f730_0 .net8 "VNB", 0 0, L_00000000040913a0;  1 drivers, strength-aware
+L_0000000004091480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3ded0_0 .net8 "VPB", 0 0, L_0000000004091480;  1 drivers, strength-aware
+L_0000000004090530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d3f7d0_0 .net8 "VPWR", 0 0, L_0000000004090530;  1 drivers, strength-aware
+v0000000003d3df70_0 .net "X", 0 0, L_0000000004163a80;  alias, 1 drivers
+v0000000003d3e470_0 .net "and0_out_X", 0 0, L_0000000004164110;  1 drivers
+S_00000000030e3f70 .scope module, "sky130_fd_sc_hd__and4_2" "sky130_fd_sc_hd__and4_2" 4 83470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7ad48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d41fd0_0 .net "A", 0 0, o0000000003c7ad48;  0 drivers
+o0000000003c7ad78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d41490_0 .net "B", 0 0, o0000000003c7ad78;  0 drivers
+o0000000003c7ada8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d410d0_0 .net "C", 0 0, o0000000003c7ada8;  0 drivers
+o0000000003c7add8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42110_0 .net "D", 0 0, o0000000003c7add8;  0 drivers
+L_0000000004090a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d408b0_0 .net8 "VGND", 0 0, L_0000000004090a00;  1 drivers, strength-aware
+L_00000000040900d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41e90_0 .net8 "VNB", 0 0, L_00000000040900d0;  1 drivers, strength-aware
+L_000000000408f960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d42570_0 .net8 "VPB", 0 0, L_000000000408f960;  1 drivers, strength-aware
+L_000000000408f9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d41c10_0 .net8 "VPWR", 0 0, L_000000000408f9d0;  1 drivers, strength-aware
+v0000000003d40810_0 .net "X", 0 0, L_0000000004163e00;  1 drivers
+S_0000000003d0d9b0 .scope module, "base" "sky130_fd_sc_hd__and4" 4 83490, 4 83903 1, S_00000000030e3f70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004164f10 .functor AND 1, o0000000003c7ad48, o0000000003c7ad78, o0000000003c7ada8, o0000000003c7add8;
+L_0000000004163e00 .functor BUF 1, L_0000000004164f10, C4<0>, C4<0>, C4<0>;
+v0000000003d3f9b0_0 .net "A", 0 0, o0000000003c7ad48;  alias, 0 drivers
+v0000000003d3e290_0 .net "B", 0 0, o0000000003c7ad78;  alias, 0 drivers
+v0000000003d3e3d0_0 .net "C", 0 0, o0000000003c7ada8;  alias, 0 drivers
+v0000000003d3fc30_0 .net "D", 0 0, o0000000003c7add8;  alias, 0 drivers
+L_0000000004090370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d3fff0_0 .net8 "VGND", 0 0, L_0000000004090370;  1 drivers, strength-aware
+L_0000000004090300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41210_0 .net8 "VNB", 0 0, L_0000000004090300;  1 drivers, strength-aware
+L_0000000004090f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d41d50_0 .net8 "VPB", 0 0, L_0000000004090f40;  1 drivers, strength-aware
+L_00000000040901b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d418f0_0 .net8 "VPWR", 0 0, L_00000000040901b0;  1 drivers, strength-aware
+v0000000003d413f0_0 .net "X", 0 0, L_0000000004163e00;  alias, 1 drivers
+v0000000003d40450_0 .net "and0_out_X", 0 0, L_0000000004164f10;  1 drivers
+S_00000000030e4570 .scope module, "sky130_fd_sc_hd__and4_4" "sky130_fd_sc_hd__and4_4" 4 84024;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7b1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d412b0_0 .net "A", 0 0, o0000000003c7b1c8;  0 drivers
+o0000000003c7b1f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d40db0_0 .net "B", 0 0, o0000000003c7b1f8;  0 drivers
+o0000000003c7b228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d422f0_0 .net "C", 0 0, o0000000003c7b228;  0 drivers
+o0000000003c7b258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d41030_0 .net "D", 0 0, o0000000003c7b258;  0 drivers
+L_0000000004090b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41f30_0 .net8 "VGND", 0 0, L_0000000004090b50;  1 drivers, strength-aware
+L_0000000004090bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41df0_0 .net8 "VNB", 0 0, L_0000000004090bc0;  1 drivers, strength-aware
+L_0000000004090450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d41350_0 .net8 "VPB", 0 0, L_0000000004090450;  1 drivers, strength-aware
+L_00000000040905a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d41ad0_0 .net8 "VPWR", 0 0, L_00000000040905a0;  1 drivers, strength-aware
+v0000000003d41170_0 .net "X", 0 0, L_0000000004163e70;  1 drivers
+S_0000000003d0d530 .scope module, "base" "sky130_fd_sc_hd__and4" 4 84044, 4 83903 1, S_00000000030e4570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004164ff0 .functor AND 1, o0000000003c7b1c8, o0000000003c7b1f8, o0000000003c7b228, o0000000003c7b258;
+L_0000000004163e70 .functor BUF 1, L_0000000004164ff0, C4<0>, C4<0>, C4<0>;
+v0000000003d40310_0 .net "A", 0 0, o0000000003c7b1c8;  alias, 0 drivers
+v0000000003d41850_0 .net "B", 0 0, o0000000003c7b1f8;  alias, 0 drivers
+v0000000003d40e50_0 .net "C", 0 0, o0000000003c7b228;  alias, 0 drivers
+v0000000003d41990_0 .net "D", 0 0, o0000000003c7b258;  alias, 0 drivers
+L_0000000004090ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d40ef0_0 .net8 "VGND", 0 0, L_0000000004090ed0;  1 drivers, strength-aware
+L_0000000004090fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41530_0 .net8 "VNB", 0 0, L_0000000004090fb0;  1 drivers, strength-aware
+L_0000000004091170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d426b0_0 .net8 "VPB", 0 0, L_0000000004091170;  1 drivers, strength-aware
+L_0000000004090a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d42750_0 .net8 "VPWR", 0 0, L_0000000004090a70;  1 drivers, strength-aware
+v0000000003d40f90_0 .net "X", 0 0, L_0000000004163e70;  alias, 1 drivers
+v0000000003d424d0_0 .net "and0_out_X", 0 0, L_0000000004164ff0;  1 drivers
+S_00000000030e3970 .scope module, "sky130_fd_sc_hd__and4b_1" "sky130_fd_sc_hd__and4b_1" 4 73181;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7b648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42070_0 .net "A_N", 0 0, o0000000003c7b648;  0 drivers
+o0000000003c7b678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d421b0_0 .net "B", 0 0, o0000000003c7b678;  0 drivers
+o0000000003c7b6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42250_0 .net "C", 0 0, o0000000003c7b6a8;  0 drivers
+o0000000003c7b6d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42390_0 .net "D", 0 0, o0000000003c7b6d8;  0 drivers
+L_0000000004091020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d42430_0 .net8 "VGND", 0 0, L_0000000004091020;  1 drivers, strength-aware
+L_0000000004090610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d40270_0 .net8 "VNB", 0 0, L_0000000004090610;  1 drivers, strength-aware
+L_0000000004090060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d42610_0 .net8 "VPB", 0 0, L_0000000004090060;  1 drivers, strength-aware
+L_0000000004091090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d427f0_0 .net8 "VPWR", 0 0, L_0000000004091090;  1 drivers, strength-aware
+v0000000003d42890_0 .net "X", 0 0, L_0000000004164180;  1 drivers
+S_0000000003d0f030 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73201, 4 73502 1, S_00000000030e3970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004163af0 .functor NOT 1, o0000000003c7b648, C4<0>, C4<0>, C4<0>;
+L_0000000004163620 .functor AND 1, L_0000000004163af0, o0000000003c7b678, o0000000003c7b6a8, o0000000003c7b6d8;
+L_0000000004164180 .functor BUF 1, L_0000000004163620, C4<0>, C4<0>, C4<0>;
+v0000000003d40950_0 .net "A_N", 0 0, o0000000003c7b648;  alias, 0 drivers
+v0000000003d415d0_0 .net "B", 0 0, o0000000003c7b678;  alias, 0 drivers
+v0000000003d41a30_0 .net "C", 0 0, o0000000003c7b6a8;  alias, 0 drivers
+v0000000003d40d10_0 .net "D", 0 0, o0000000003c7b6d8;  alias, 0 drivers
+L_000000000408fb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d404f0_0 .net8 "VGND", 0 0, L_000000000408fb20;  1 drivers, strength-aware
+L_0000000004090680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d41670_0 .net8 "VNB", 0 0, L_0000000004090680;  1 drivers, strength-aware
+L_0000000004091100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d41710_0 .net8 "VPB", 0 0, L_0000000004091100;  1 drivers, strength-aware
+L_00000000040907d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d40590_0 .net8 "VPWR", 0 0, L_00000000040907d0;  1 drivers, strength-aware
+v0000000003d417b0_0 .net "X", 0 0, L_0000000004164180;  alias, 1 drivers
+v0000000003d41b70_0 .net "and0_out_X", 0 0, L_0000000004163620;  1 drivers
+v0000000003d41cb0_0 .net "not0_out", 0 0, L_0000000004163af0;  1 drivers
+S_00000000030e4cf0 .scope module, "sky130_fd_sc_hd__and4b_2" "sky130_fd_sc_hd__and4b_2" 4 73625;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7baf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d44d70_0 .net "A_N", 0 0, o0000000003c7baf8;  0 drivers
+o0000000003c7bb28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d442d0_0 .net "B", 0 0, o0000000003c7bb28;  0 drivers
+o0000000003c7bb58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d44550_0 .net "C", 0 0, o0000000003c7bb58;  0 drivers
+o0000000003c7bb88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43010_0 .net "D", 0 0, o0000000003c7bb88;  0 drivers
+L_0000000004090920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d444b0_0 .net8 "VGND", 0 0, L_0000000004090920;  1 drivers, strength-aware
+L_0000000004090ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43f10_0 .net8 "VNB", 0 0, L_0000000004090ae0;  1 drivers, strength-aware
+L_000000000408fe30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d445f0_0 .net8 "VPB", 0 0, L_000000000408fe30;  1 drivers, strength-aware
+L_0000000004091410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d449b0_0 .net8 "VPWR", 0 0, L_0000000004091410;  1 drivers, strength-aware
+v0000000003d430b0_0 .net "X", 0 0, L_0000000004163ee0;  1 drivers
+S_0000000003d115b0 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73645, 4 73502 1, S_00000000030e4cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004163d90 .functor NOT 1, o0000000003c7baf8, C4<0>, C4<0>, C4<0>;
+L_0000000004163b60 .functor AND 1, L_0000000004163d90, o0000000003c7bb28, o0000000003c7bb58, o0000000003c7bb88;
+L_0000000004163ee0 .functor BUF 1, L_0000000004163b60, C4<0>, C4<0>, C4<0>;
+v0000000003d406d0_0 .net "A_N", 0 0, o0000000003c7baf8;  alias, 0 drivers
+v0000000003d40630_0 .net "B", 0 0, o0000000003c7bb28;  alias, 0 drivers
+v0000000003d40c70_0 .net "C", 0 0, o0000000003c7bb58;  alias, 0 drivers
+v0000000003d40130_0 .net "D", 0 0, o0000000003c7bb88;  alias, 0 drivers
+L_000000000408fc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d409f0_0 .net8 "VGND", 0 0, L_000000000408fc00;  1 drivers, strength-aware
+L_000000000408fa40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d401d0_0 .net8 "VNB", 0 0, L_000000000408fa40;  1 drivers, strength-aware
+L_0000000004090ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d403b0_0 .net8 "VPB", 0 0, L_0000000004090ca0;  1 drivers, strength-aware
+L_0000000004090c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d40770_0 .net8 "VPWR", 0 0, L_0000000004090c30;  1 drivers, strength-aware
+v0000000003d40a90_0 .net "X", 0 0, L_0000000004163ee0;  alias, 1 drivers
+v0000000003d40b30_0 .net "and0_out_X", 0 0, L_0000000004163b60;  1 drivers
+v0000000003d40bd0_0 .net "not0_out", 0 0, L_0000000004163d90;  1 drivers
+S_00000000030e46f0 .scope module, "sky130_fd_sc_hd__and4b_4" "sky130_fd_sc_hd__and4b_4" 4 73743;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7bfa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d44370_0 .net "A_N", 0 0, o0000000003c7bfa8;  0 drivers
+o0000000003c7bfd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d44870_0 .net "B", 0 0, o0000000003c7bfd8;  0 drivers
+o0000000003c7c008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d44f50_0 .net "C", 0 0, o0000000003c7c008;  0 drivers
+o0000000003c7c038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43fb0_0 .net "D", 0 0, o0000000003c7c038;  0 drivers
+L_000000000408fc70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d44cd0_0 .net8 "VGND", 0 0, L_000000000408fc70;  1 drivers, strength-aware
+L_0000000004090990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43ab0_0 .net8 "VNB", 0 0, L_0000000004090990;  1 drivers, strength-aware
+L_000000000408fce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d44ff0_0 .net8 "VPB", 0 0, L_000000000408fce0;  1 drivers, strength-aware
+L_0000000004090df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d44190_0 .net8 "VPWR", 0 0, L_0000000004090df0;  1 drivers, strength-aware
+v0000000003d43d30_0 .net "X", 0 0, L_0000000004163690;  1 drivers
+S_0000000003d100b0 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73763, 4 73502 1, S_00000000030e46f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004164e30 .functor NOT 1, o0000000003c7bfa8, C4<0>, C4<0>, C4<0>;
+L_0000000004164880 .functor AND 1, L_0000000004164e30, o0000000003c7bfd8, o0000000003c7c008, o0000000003c7c038;
+L_0000000004163690 .functor BUF 1, L_0000000004164880, C4<0>, C4<0>, C4<0>;
+v0000000003d42bb0_0 .net "A_N", 0 0, o0000000003c7bfa8;  alias, 0 drivers
+v0000000003d44e10_0 .net "B", 0 0, o0000000003c7bfd8;  alias, 0 drivers
+v0000000003d43470_0 .net "C", 0 0, o0000000003c7c008;  alias, 0 drivers
+v0000000003d44730_0 .net "D", 0 0, o0000000003c7c038;  alias, 0 drivers
+L_00000000040911e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43a10_0 .net8 "VGND", 0 0, L_00000000040911e0;  1 drivers, strength-aware
+L_0000000004091250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43790_0 .net8 "VNB", 0 0, L_0000000004091250;  1 drivers, strength-aware
+L_00000000040912c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d42b10_0 .net8 "VPB", 0 0, L_00000000040912c0;  1 drivers, strength-aware
+L_000000000408fd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d435b0_0 .net8 "VPWR", 0 0, L_000000000408fd50;  1 drivers, strength-aware
+v0000000003d43c90_0 .net "X", 0 0, L_0000000004163690;  alias, 1 drivers
+v0000000003d42e30_0 .net "and0_out_X", 0 0, L_0000000004164880;  1 drivers
+v0000000003d438d0_0 .net "not0_out", 0 0, L_0000000004164e30;  1 drivers
+S_00000000030e31f0 .scope module, "sky130_fd_sc_hd__and4bb_1" "sky130_fd_sc_hd__and4bb_1" 4 42800;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7c458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43970_0 .net "A_N", 0 0, o0000000003c7c458;  0 drivers
+o0000000003c7c488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43150_0 .net "B_N", 0 0, o0000000003c7c488;  0 drivers
+o0000000003c7c4b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43dd0_0 .net "C", 0 0, o0000000003c7c4b8;  0 drivers
+o0000000003c7c4e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d431f0_0 .net "D", 0 0, o0000000003c7c4e8;  0 drivers
+L_000000000408ff10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d44a50_0 .net8 "VGND", 0 0, L_000000000408ff10;  1 drivers, strength-aware
+L_000000000408ff80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d44af0_0 .net8 "VNB", 0 0, L_000000000408ff80;  1 drivers, strength-aware
+L_0000000004092440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d436f0_0 .net8 "VPB", 0 0, L_0000000004092440;  1 drivers, strength-aware
+L_0000000004092ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d44b90_0 .net8 "VPWR", 0 0, L_0000000004092ad0;  1 drivers, strength-aware
+v0000000003d44c30_0 .net "X", 0 0, L_0000000004164340;  1 drivers
+S_0000000003d12ab0 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42820, 4 42559 1, S_00000000030e31f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_00000000041635b0 .functor NOR 1, o0000000003c7c458, o0000000003c7c488, C4<0>, C4<0>;
+L_0000000004163bd0 .functor AND 1, L_00000000041635b0, o0000000003c7c4b8, o0000000003c7c4e8, C4<1>;
+L_0000000004164340 .functor BUF 1, L_0000000004163bd0, C4<0>, C4<0>, C4<0>;
+v0000000003d44690_0 .net "A_N", 0 0, o0000000003c7c458;  alias, 0 drivers
+v0000000003d44410_0 .net "B_N", 0 0, o0000000003c7c488;  alias, 0 drivers
+v0000000003d42930_0 .net "C", 0 0, o0000000003c7c4b8;  alias, 0 drivers
+v0000000003d42d90_0 .net "D", 0 0, o0000000003c7c4e8;  alias, 0 drivers
+L_0000000004092910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d44230_0 .net8 "VGND", 0 0, L_0000000004092910;  1 drivers, strength-aware
+L_0000000004092750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43650_0 .net8 "VNB", 0 0, L_0000000004092750;  1 drivers, strength-aware
+L_0000000004092fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d447d0_0 .net8 "VPB", 0 0, L_0000000004092fa0;  1 drivers, strength-aware
+L_0000000004091f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d43830_0 .net8 "VPWR", 0 0, L_0000000004091f00;  1 drivers, strength-aware
+v0000000003d43e70_0 .net "X", 0 0, L_0000000004164340;  alias, 1 drivers
+v0000000003d42c50_0 .net "and0_out_X", 0 0, L_0000000004163bd0;  1 drivers
+v0000000003d44910_0 .net "nor0_out", 0 0, L_00000000041635b0;  1 drivers
+S_00000000030e3370 .scope module, "sky130_fd_sc_hd__and4bb_2" "sky130_fd_sc_hd__and4bb_2" 4 42918;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7c908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42ed0_0 .net "A_N", 0 0, o0000000003c7c908;  0 drivers
+o0000000003c7c938 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d42f70_0 .net "B_N", 0 0, o0000000003c7c938;  0 drivers
+o0000000003c7c968 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d43330_0 .net "C", 0 0, o0000000003c7c968;  0 drivers
+o0000000003c7c998 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d433d0_0 .net "D", 0 0, o0000000003c7c998;  0 drivers
+L_0000000004091db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d47610_0 .net8 "VGND", 0 0, L_0000000004091db0;  1 drivers, strength-aware
+L_00000000040926e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d472f0_0 .net8 "VNB", 0 0, L_00000000040926e0;  1 drivers, strength-aware
+L_0000000004092bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d474d0_0 .net8 "VPB", 0 0, L_0000000004092bb0;  1 drivers, strength-aware
+L_0000000004092600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d45d10_0 .net8 "VPWR", 0 0, L_0000000004092600;  1 drivers, strength-aware
+v0000000003d46670_0 .net "X", 0 0, L_00000000041648f0;  1 drivers
+S_0000000003d12db0 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42938, 4 42559 1, S_00000000030e3370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004163f50 .functor NOR 1, o0000000003c7c908, o0000000003c7c938, C4<0>, C4<0>;
+L_0000000004164ea0 .functor AND 1, L_0000000004163f50, o0000000003c7c968, o0000000003c7c998, C4<1>;
+L_00000000041648f0 .functor BUF 1, L_0000000004164ea0, C4<0>, C4<0>, C4<0>;
+v0000000003d43b50_0 .net "A_N", 0 0, o0000000003c7c908;  alias, 0 drivers
+v0000000003d43bf0_0 .net "B_N", 0 0, o0000000003c7c938;  alias, 0 drivers
+v0000000003d429d0_0 .net "C", 0 0, o0000000003c7c968;  alias, 0 drivers
+v0000000003d43510_0 .net "D", 0 0, o0000000003c7c998;  alias, 0 drivers
+L_0000000004091f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d43290_0 .net8 "VGND", 0 0, L_0000000004091f70;  1 drivers, strength-aware
+L_00000000040919c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d44050_0 .net8 "VNB", 0 0, L_00000000040919c0;  1 drivers, strength-aware
+L_0000000004092d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d42a70_0 .net8 "VPB", 0 0, L_0000000004092d70;  1 drivers, strength-aware
+L_0000000004091800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d44eb0_0 .net8 "VPWR", 0 0, L_0000000004091800;  1 drivers, strength-aware
+v0000000003d440f0_0 .net "X", 0 0, L_00000000041648f0;  alias, 1 drivers
+v0000000003d45090_0 .net "and0_out_X", 0 0, L_0000000004164ea0;  1 drivers
+v0000000003d42cf0_0 .net "nor0_out", 0 0, L_0000000004163f50;  1 drivers
+S_00000000030e3af0 .scope module, "sky130_fd_sc_hd__and4bb_4" "sky130_fd_sc_hd__and4bb_4" 4 42682;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003c7cdb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d45630_0 .net "A_N", 0 0, o0000000003c7cdb8;  0 drivers
+o0000000003c7cde8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d45db0_0 .net "B_N", 0 0, o0000000003c7cde8;  0 drivers
+o0000000003c7ce18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d46850_0 .net "C", 0 0, o0000000003c7ce18;  0 drivers
+o0000000003c7ce48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d45810_0 .net "D", 0 0, o0000000003c7ce48;  0 drivers
+L_0000000004092980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45f90_0 .net8 "VGND", 0 0, L_0000000004092980;  1 drivers, strength-aware
+L_0000000004091d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d46b70_0 .net8 "VNB", 0 0, L_0000000004091d40;  1 drivers, strength-aware
+L_0000000004091560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d463f0_0 .net8 "VPB", 0 0, L_0000000004091560;  1 drivers, strength-aware
+L_0000000004092de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d46490_0 .net8 "VPWR", 0 0, L_0000000004092de0;  1 drivers, strength-aware
+v0000000003d46fd0_0 .net "X", 0 0, L_0000000004164ab0;  1 drivers
+S_0000000003d0f1b0 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42702, 4 42559 1, S_00000000030e3af0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004164960 .functor NOR 1, o0000000003c7cdb8, o0000000003c7cde8, C4<0>, C4<0>;
+L_0000000004163c40 .functor AND 1, L_0000000004164960, o0000000003c7ce18, o0000000003c7ce48, C4<1>;
+L_0000000004164ab0 .functor BUF 1, L_0000000004163c40, C4<0>, C4<0>, C4<0>;
+v0000000003d477f0_0 .net "A_N", 0 0, o0000000003c7cdb8;  alias, 0 drivers
+v0000000003d476b0_0 .net "B_N", 0 0, o0000000003c7cde8;  alias, 0 drivers
+v0000000003d46cb0_0 .net "C", 0 0, o0000000003c7ce18;  alias, 0 drivers
+v0000000003d459f0_0 .net "D", 0 0, o0000000003c7ce48;  alias, 0 drivers
+L_0000000004092a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45c70_0 .net8 "VGND", 0 0, L_0000000004092a60;  1 drivers, strength-aware
+L_00000000040929f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d46d50_0 .net8 "VNB", 0 0, L_00000000040929f0;  1 drivers, strength-aware
+L_0000000004092d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d46530_0 .net8 "VPB", 0 0, L_0000000004092d00;  1 drivers, strength-aware
+L_0000000004092c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d46a30_0 .net8 "VPWR", 0 0, L_0000000004092c20;  1 drivers, strength-aware
+v0000000003d47070_0 .net "X", 0 0, L_0000000004164ab0;  alias, 1 drivers
+v0000000003d46ad0_0 .net "and0_out_X", 0 0, L_0000000004163c40;  1 drivers
+v0000000003d46df0_0 .net "nor0_out", 0 0, L_0000000004164960;  1 drivers
+S_00000000030e3c70 .scope module, "sky130_fd_sc_hd__buf_12" "sky130_fd_sc_hd__buf_12" 4 80560;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7d268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d45130_0 .net "A", 0 0, o0000000003c7d268;  0 drivers
+L_0000000004091e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d46c10_0 .net8 "VGND", 0 0, L_0000000004091e90;  1 drivers, strength-aware
+L_0000000004092050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d47110_0 .net8 "VNB", 0 0, L_0000000004092050;  1 drivers, strength-aware
+L_00000000040922f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d453b0_0 .net8 "VPB", 0 0, L_00000000040922f0;  1 drivers, strength-aware
+L_00000000040928a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d454f0_0 .net8 "VPWR", 0 0, L_00000000040928a0;  1 drivers, strength-aware
+v0000000003d46e90_0 .net "X", 0 0, L_0000000004164b90;  1 drivers
+S_0000000003d11eb0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 80574, 4 80948 1, S_00000000030e3c70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004164b20 .functor BUF 1, o0000000003c7d268, C4<0>, C4<0>, C4<0>;
+L_0000000004164b90 .functor BUF 1, L_0000000004164b20, C4<0>, C4<0>, C4<0>;
+v0000000003d46210_0 .net "A", 0 0, o0000000003c7d268;  alias, 0 drivers
+L_0000000004092ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d47250_0 .net8 "VGND", 0 0, L_0000000004092ec0;  1 drivers, strength-aware
+L_0000000004091aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d465d0_0 .net8 "VNB", 0 0, L_0000000004091aa0;  1 drivers, strength-aware
+L_00000000040920c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d45450_0 .net8 "VPB", 0 0, L_00000000040920c0;  1 drivers, strength-aware
+L_0000000004092670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d45a90_0 .net8 "VPWR", 0 0, L_0000000004092670;  1 drivers, strength-aware
+v0000000003d471b0_0 .net "X", 0 0, L_0000000004164b90;  alias, 1 drivers
+v0000000003d458b0_0 .net "buf0_out_X", 0 0, L_0000000004164b20;  1 drivers
+S_00000000030e49f0 .scope module, "sky130_fd_sc_hd__buf_16" "sky130_fd_sc_hd__buf_16" 4 80660;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7d538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d47390_0 .net "A", 0 0, o0000000003c7d538;  0 drivers
+L_0000000004092f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d47750_0 .net8 "VGND", 0 0, L_0000000004092f30;  1 drivers, strength-aware
+L_0000000004092c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d467b0_0 .net8 "VNB", 0 0, L_0000000004092c90;  1 drivers, strength-aware
+L_0000000004091cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d47890_0 .net8 "VPB", 0 0, L_0000000004091cd0;  1 drivers, strength-aware
+L_0000000004092b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d462b0_0 .net8 "VPWR", 0 0, L_0000000004092b40;  1 drivers, strength-aware
+v0000000003d47430_0 .net "X", 0 0, L_0000000004164260;  1 drivers
+S_0000000003d0db30 .scope module, "base" "sky130_fd_sc_hd__buf" 4 80674, 4 80948 1, S_00000000030e49f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004164730 .functor BUF 1, o0000000003c7d538, C4<0>, C4<0>, C4<0>;
+L_0000000004164260 .functor BUF 1, L_0000000004164730, C4<0>, C4<0>, C4<0>;
+v0000000003d45590_0 .net "A", 0 0, o0000000003c7d538;  alias, 0 drivers
+L_0000000004092360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45e50_0 .net8 "VGND", 0 0, L_0000000004092360;  1 drivers, strength-aware
+L_00000000040927c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45310_0 .net8 "VNB", 0 0, L_00000000040927c0;  1 drivers, strength-aware
+L_0000000004092e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d468f0_0 .net8 "VPB", 0 0, L_0000000004092e50;  1 drivers, strength-aware
+L_00000000040921a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d46f30_0 .net8 "VPWR", 0 0, L_00000000040921a0;  1 drivers, strength-aware
+v0000000003d46990_0 .net "X", 0 0, L_0000000004164260;  alias, 1 drivers
+v0000000003d46710_0 .net "buf0_out_X", 0 0, L_0000000004164730;  1 drivers
+S_00000000030e3df0 .scope module, "sky130_fd_sc_hd__buf_2" "sky130_fd_sc_hd__buf_2" 4 81354;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7d808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d46030_0 .net "A", 0 0, o0000000003c7d808;  0 drivers
+L_0000000004091640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d460d0_0 .net8 "VGND", 0 0, L_0000000004091640;  1 drivers, strength-aware
+L_0000000004091b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45b30_0 .net8 "VNB", 0 0, L_0000000004091b10;  1 drivers, strength-aware
+L_00000000040916b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d45bd0_0 .net8 "VPB", 0 0, L_00000000040916b0;  1 drivers, strength-aware
+L_0000000004091e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d46170_0 .net8 "VPWR", 0 0, L_0000000004091e20;  1 drivers, strength-aware
+v0000000003d46350_0 .net "X", 0 0, L_0000000004164f80;  1 drivers
+S_0000000003d0eeb0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81368, 4 80948 1, S_00000000030e3df0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041642d0 .functor BUF 1, o0000000003c7d808, C4<0>, C4<0>, C4<0>;
+L_0000000004164f80 .functor BUF 1, L_00000000041642d0, C4<0>, C4<0>, C4<0>;
+v0000000003d47570_0 .net "A", 0 0, o0000000003c7d808;  alias, 0 drivers
+L_0000000004093080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d451d0_0 .net8 "VGND", 0 0, L_0000000004093080;  1 drivers, strength-aware
+L_00000000040924b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d45270_0 .net8 "VNB", 0 0, L_00000000040924b0;  1 drivers, strength-aware
+L_00000000040923d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d456d0_0 .net8 "VPB", 0 0, L_00000000040923d0;  1 drivers, strength-aware
+L_00000000040914f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d45ef0_0 .net8 "VPWR", 0 0, L_00000000040914f0;  1 drivers, strength-aware
+v0000000003d45770_0 .net "X", 0 0, L_0000000004164f80;  alias, 1 drivers
+v0000000003d45950_0 .net "buf0_out_X", 0 0, L_00000000041642d0;  1 drivers
+S_00000000030e4b70 .scope module, "sky130_fd_sc_hd__buf_4" "sky130_fd_sc_hd__buf_4" 4 81054;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7dad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d486f0_0 .net "A", 0 0, o0000000003c7dad8;  0 drivers
+L_0000000004093010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48bf0_0 .net8 "VGND", 0 0, L_0000000004093010;  1 drivers, strength-aware
+L_00000000040915d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49230_0 .net8 "VNB", 0 0, L_00000000040915d0;  1 drivers, strength-aware
+L_0000000004091720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48830_0 .net8 "VPB", 0 0, L_0000000004091720;  1 drivers, strength-aware
+L_0000000004091790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a090_0 .net8 "VPWR", 0 0, L_0000000004091790;  1 drivers, strength-aware
+v0000000003d49870_0 .net "X", 0 0, L_0000000004164500;  1 drivers
+S_0000000003d0f7b0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81068, 4 80948 1, S_00000000030e4b70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041643b0 .functor BUF 1, o0000000003c7dad8, C4<0>, C4<0>, C4<0>;
+L_0000000004164500 .functor BUF 1, L_00000000041643b0, C4<0>, C4<0>, C4<0>;
+v0000000003d48a10_0 .net "A", 0 0, o0000000003c7dad8;  alias, 0 drivers
+L_0000000004091a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48790_0 .net8 "VGND", 0 0, L_0000000004091a30;  1 drivers, strength-aware
+L_0000000004092280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49690_0 .net8 "VNB", 0 0, L_0000000004092280;  1 drivers, strength-aware
+L_0000000004092830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48c90_0 .net8 "VPB", 0 0, L_0000000004092830;  1 drivers, strength-aware
+L_0000000004091fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d49b90_0 .net8 "VPWR", 0 0, L_0000000004091fe0;  1 drivers, strength-aware
+v0000000003d488d0_0 .net "X", 0 0, L_0000000004164500;  alias, 1 drivers
+v0000000003d48650_0 .net "buf0_out_X", 0 0, L_00000000041643b0;  1 drivers
+S_00000000030e40f0 .scope module, "sky130_fd_sc_hd__buf_6" "sky130_fd_sc_hd__buf_6" 4 81254;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7dda8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d49410_0 .net "A", 0 0, o0000000003c7dda8;  0 drivers
+L_0000000004091870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49370_0 .net8 "VGND", 0 0, L_0000000004091870;  1 drivers, strength-aware
+L_0000000004092520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49550_0 .net8 "VNB", 0 0, L_0000000004092520;  1 drivers, strength-aware
+L_00000000040918e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48010_0 .net8 "VPB", 0 0, L_00000000040918e0;  1 drivers, strength-aware
+L_0000000004091950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d47d90_0 .net8 "VPWR", 0 0, L_0000000004091950;  1 drivers, strength-aware
+v0000000003d47930_0 .net "X", 0 0, L_0000000004164570;  1 drivers
+S_0000000003d10b30 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81268, 4 80948 1, S_00000000030e40f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004164420 .functor BUF 1, o0000000003c7dda8, C4<0>, C4<0>, C4<0>;
+L_0000000004164570 .functor BUF 1, L_0000000004164420, C4<0>, C4<0>, C4<0>;
+v0000000003d48d30_0 .net "A", 0 0, o0000000003c7dda8;  alias, 0 drivers
+L_0000000004092210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48dd0_0 .net8 "VGND", 0 0, L_0000000004092210;  1 drivers, strength-aware
+L_0000000004091b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49eb0_0 .net8 "VNB", 0 0, L_0000000004091b80;  1 drivers, strength-aware
+L_0000000004091bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d494b0_0 .net8 "VPB", 0 0, L_0000000004091bf0;  1 drivers, strength-aware
+L_0000000004091c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d495f0_0 .net8 "VPWR", 0 0, L_0000000004091c60;  1 drivers, strength-aware
+v0000000003d492d0_0 .net "X", 0 0, L_0000000004164570;  alias, 1 drivers
+v0000000003d48970_0 .net "buf0_out_X", 0 0, L_0000000004164420;  1 drivers
+S_00000000030e4e70 .scope module, "sky130_fd_sc_hd__buf_8" "sky130_fd_sc_hd__buf_8" 4 81454;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7e078 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d49c30_0 .net "A", 0 0, o0000000003c7e078;  0 drivers
+L_0000000004092130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48fb0_0 .net8 "VGND", 0 0, L_0000000004092130;  1 drivers, strength-aware
+L_0000000004092590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49050_0 .net8 "VNB", 0 0, L_0000000004092590;  1 drivers, strength-aware
+L_0000000004094040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d479d0_0 .net8 "VPB", 0 0, L_0000000004094040;  1 drivers, strength-aware
+L_0000000004093ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d49a50_0 .net8 "VPWR", 0 0, L_0000000004093ef0;  1 drivers, strength-aware
+v0000000003d49e10_0 .net "X", 0 0, L_0000000004164650;  1 drivers
+S_0000000003d0e430 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81468, 4 80948 1, S_00000000030e4e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041645e0 .functor BUF 1, o0000000003c7e078, C4<0>, C4<0>, C4<0>;
+L_0000000004164650 .functor BUF 1, L_00000000041645e0, C4<0>, C4<0>, C4<0>;
+v0000000003d48ab0_0 .net "A", 0 0, o0000000003c7e078;  alias, 0 drivers
+L_00000000040930f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d47c50_0 .net8 "VGND", 0 0, L_00000000040930f0;  1 drivers, strength-aware
+L_0000000004094890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48e70_0 .net8 "VNB", 0 0, L_0000000004094890;  1 drivers, strength-aware
+L_0000000004093160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d49cd0_0 .net8 "VPB", 0 0, L_0000000004093160;  1 drivers, strength-aware
+L_00000000040931d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48f10_0 .net8 "VPWR", 0 0, L_00000000040931d0;  1 drivers, strength-aware
+v0000000003d499b0_0 .net "X", 0 0, L_0000000004164650;  alias, 1 drivers
+v0000000003d47bb0_0 .net "buf0_out_X", 0 0, L_00000000041645e0;  1 drivers
+S_00000000030e4270 .scope module, "sky130_fd_sc_hd__bufbuf_16" "sky130_fd_sc_hd__bufbuf_16" 4 70555;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7e348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d47cf0_0 .net "A", 0 0, o0000000003c7e348;  0 drivers
+L_0000000004094510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48470_0 .net8 "VGND", 0 0, L_0000000004094510;  1 drivers, strength-aware
+L_00000000040935c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49730_0 .net8 "VNB", 0 0, L_00000000040935c0;  1 drivers, strength-aware
+L_0000000004093e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d49190_0 .net8 "VPB", 0 0, L_0000000004093e80;  1 drivers, strength-aware
+L_0000000004094270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d497d0_0 .net8 "VPWR", 0 0, L_0000000004094270;  1 drivers, strength-aware
+v0000000003d49d70_0 .net "X", 0 0, L_00000000041647a0;  1 drivers
+S_0000000003d12630 .scope module, "base" "sky130_fd_sc_hd__bufbuf" 4 70569, 4 70449 1, S_00000000030e4270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041646c0 .functor BUF 1, o0000000003c7e348, C4<0>, C4<0>, C4<0>;
+L_00000000041647a0 .functor BUF 1, L_00000000041646c0, C4<0>, C4<0>, C4<0>;
+v0000000003d49f50_0 .net "A", 0 0, o0000000003c7e348;  alias, 0 drivers
+L_00000000040943c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49ff0_0 .net8 "VGND", 0 0, L_00000000040943c0;  1 drivers, strength-aware
+L_0000000004093240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d490f0_0 .net8 "VNB", 0 0, L_0000000004093240;  1 drivers, strength-aware
+L_00000000040938d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48b50_0 .net8 "VPB", 0 0, L_00000000040938d0;  1 drivers, strength-aware
+L_0000000004093390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d47f70_0 .net8 "VPWR", 0 0, L_0000000004093390;  1 drivers, strength-aware
+v0000000003d47a70_0 .net "X", 0 0, L_00000000041647a0;  alias, 1 drivers
+v0000000003d47b10_0 .net "buf0_out_X", 0 0, L_00000000041646c0;  1 drivers
+S_00000000030e3070 .scope module, "sky130_fd_sc_hd__bufbuf_8" "sky130_fd_sc_hd__bufbuf_8" 4 70161;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7e618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d48290_0 .net "A", 0 0, o0000000003c7e618;  0 drivers
+L_00000000040939b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d48330_0 .net8 "VGND", 0 0, L_00000000040939b0;  1 drivers, strength-aware
+L_00000000040940b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d483d0_0 .net8 "VNB", 0 0, L_00000000040940b0;  1 drivers, strength-aware
+L_0000000004093e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d48510_0 .net8 "VPB", 0 0, L_0000000004093e10;  1 drivers, strength-aware
+L_0000000004093a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d485b0_0 .net8 "VPWR", 0 0, L_0000000004093a20;  1 drivers, strength-aware
+v0000000003d4b210_0 .net "X", 0 0, L_0000000004164c70;  1 drivers
+S_0000000003d127b0 .scope module, "base" "sky130_fd_sc_hd__bufbuf" 4 70175, 4 70449 1, S_00000000030e3070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004164c00 .functor BUF 1, o0000000003c7e618, C4<0>, C4<0>, C4<0>;
+L_0000000004164c70 .functor BUF 1, L_0000000004164c00, C4<0>, C4<0>, C4<0>;
+v0000000003d47e30_0 .net "A", 0 0, o0000000003c7e618;  alias, 0 drivers
+L_0000000004094120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49910_0 .net8 "VGND", 0 0, L_0000000004094120;  1 drivers, strength-aware
+L_0000000004093d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d49af0_0 .net8 "VNB", 0 0, L_0000000004093d30;  1 drivers, strength-aware
+L_00000000040942e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d480b0_0 .net8 "VPB", 0 0, L_00000000040942e0;  1 drivers, strength-aware
+L_0000000004094190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d47ed0_0 .net8 "VPWR", 0 0, L_0000000004094190;  1 drivers, strength-aware
+v0000000003d48150_0 .net "X", 0 0, L_0000000004164c70;  alias, 1 drivers
+v0000000003d481f0_0 .net "buf0_out_X", 0 0, L_0000000004164c00;  1 drivers
+S_00000000030e3670 .scope module, "sky130_fd_sc_hd__bufinv_16" "sky130_fd_sc_hd__bufinv_16" 4 37202;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7e8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4be90_0 .net "A", 0 0, o0000000003c7e8e8;  0 drivers
+L_00000000040946d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c7f0_0 .net8 "VGND", 0 0, L_00000000040946d0;  1 drivers, strength-aware
+L_0000000004094580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a8b0_0 .net8 "VNB", 0 0, L_0000000004094580;  1 drivers, strength-aware
+L_0000000004094350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ad10_0 .net8 "VPB", 0 0, L_0000000004094350;  1 drivers, strength-aware
+L_0000000004094ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a4f0_0 .net8 "VPWR", 0 0, L_0000000004094ba0;  1 drivers, strength-aware
+v0000000003d4b170_0 .net "Y", 0 0, L_0000000004164d50;  1 drivers
+S_0000000003d0e130 .scope module, "base" "sky130_fd_sc_hd__bufinv" 4 37216, 4 37490 1, S_00000000030e3670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004164ce0 .functor NOT 1, o0000000003c7e8e8, C4<0>, C4<0>, C4<0>;
+L_0000000004164d50 .functor BUF 1, L_0000000004164ce0, C4<0>, C4<0>, C4<0>;
+v0000000003d4b710_0 .net "A", 0 0, o0000000003c7e8e8;  alias, 0 drivers
+L_0000000004093b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a3b0_0 .net8 "VGND", 0 0, L_0000000004093b00;  1 drivers, strength-aware
+L_0000000004093a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a810_0 .net8 "VNB", 0 0, L_0000000004093a90;  1 drivers, strength-aware
+L_0000000004094430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a630_0 .net8 "VPB", 0 0, L_0000000004094430;  1 drivers, strength-aware
+L_00000000040947b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a130_0 .net8 "VPWR", 0 0, L_00000000040947b0;  1 drivers, strength-aware
+v0000000003d4ba30_0 .net "Y", 0 0, L_0000000004164d50;  alias, 1 drivers
+v0000000003d4c110_0 .net "not0_out_Y", 0 0, L_0000000004164ce0;  1 drivers
+S_00000000030e43f0 .scope module, "sky130_fd_sc_hd__bufinv_8" "sky130_fd_sc_hd__bufinv_8" 4 37102;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7ebb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4a1d0_0 .net "A", 0 0, o0000000003c7ebb8;  0 drivers
+L_0000000004094200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b2b0_0 .net8 "VGND", 0 0, L_0000000004094200;  1 drivers, strength-aware
+L_0000000004093b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b3f0_0 .net8 "VNB", 0 0, L_0000000004093b70;  1 drivers, strength-aware
+L_0000000004093630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a270_0 .net8 "VPB", 0 0, L_0000000004093630;  1 drivers, strength-aware
+L_0000000004094970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bd50_0 .net8 "VPWR", 0 0, L_0000000004094970;  1 drivers, strength-aware
+v0000000003d4b670_0 .net "Y", 0 0, L_0000000004165450;  1 drivers
+S_0000000003d0f330 .scope module, "base" "sky130_fd_sc_hd__bufinv" 4 37116, 4 37490 1, S_00000000030e43f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041653e0 .functor NOT 1, o0000000003c7ebb8, C4<0>, C4<0>, C4<0>;
+L_0000000004165450 .functor BUF 1, L_00000000041653e0, C4<0>, C4<0>, C4<0>;
+v0000000003d4c4d0_0 .net "A", 0 0, o0000000003c7ebb8;  alias, 0 drivers
+L_0000000004093400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b5d0_0 .net8 "VGND", 0 0, L_0000000004093400;  1 drivers, strength-aware
+L_00000000040945f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4adb0_0 .net8 "VNB", 0 0, L_00000000040945f0;  1 drivers, strength-aware
+L_0000000004093940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ae50_0 .net8 "VPB", 0 0, L_0000000004093940;  1 drivers, strength-aware
+L_00000000040932b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c610_0 .net8 "VPWR", 0 0, L_00000000040932b0;  1 drivers, strength-aware
+v0000000003d4af90_0 .net "Y", 0 0, L_0000000004165450;  alias, 1 drivers
+v0000000003d4b990_0 .net "not0_out_Y", 0 0, L_00000000041653e0;  1 drivers
+S_00000000030e37f0 .scope module, "sky130_fd_sc_hd__clkbuf_1" "sky130_fd_sc_hd__clkbuf_1" 4 94876;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7ee88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4b7b0_0 .net "A", 0 0, o0000000003c7ee88;  0 drivers
+L_00000000040949e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c1b0_0 .net8 "VGND", 0 0, L_00000000040949e0;  1 drivers, strength-aware
+L_0000000004094660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bb70_0 .net8 "VNB", 0 0, L_0000000004094660;  1 drivers, strength-aware
+L_0000000004094740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c570_0 .net8 "VPB", 0 0, L_0000000004094740;  1 drivers, strength-aware
+L_0000000004094900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a6d0_0 .net8 "VPWR", 0 0, L_0000000004094900;  1 drivers, strength-aware
+v0000000003d4c750_0 .net "X", 0 0, L_0000000004166170;  1 drivers
+S_0000000003d0fab0 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94890, 4 95264 1, S_00000000030e37f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165bc0 .functor BUF 1, o0000000003c7ee88, C4<0>, C4<0>, C4<0>;
+L_0000000004166170 .functor BUF 1, L_0000000004165bc0, C4<0>, C4<0>, C4<0>;
+v0000000003d4b350_0 .net "A", 0 0, o0000000003c7ee88;  alias, 0 drivers
+L_0000000004094820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bad0_0 .net8 "VGND", 0 0, L_0000000004094820;  1 drivers, strength-aware
+L_0000000004093be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bcb0_0 .net8 "VNB", 0 0, L_0000000004093be0;  1 drivers, strength-aware
+L_0000000004093c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c070_0 .net8 "VPB", 0 0, L_0000000004093c50;  1 drivers, strength-aware
+L_0000000004093f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c250_0 .net8 "VPWR", 0 0, L_0000000004093f60;  1 drivers, strength-aware
+v0000000003d4a310_0 .net "X", 0 0, L_0000000004166170;  alias, 1 drivers
+v0000000003d4bdf0_0 .net "buf0_out_X", 0 0, L_0000000004165bc0;  1 drivers
+S_00000000029ee9f0 .scope module, "sky130_fd_sc_hd__clkbuf_16" "sky130_fd_sc_hd__clkbuf_16" 4 94776;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7f158 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4c2f0_0 .net "A", 0 0, o0000000003c7f158;  0 drivers
+L_00000000040944a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b0d0_0 .net8 "VGND", 0 0, L_00000000040944a0;  1 drivers, strength-aware
+L_0000000004094ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4c430_0 .net8 "VNB", 0 0, L_0000000004094ac0;  1 drivers, strength-aware
+L_00000000040936a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b8f0_0 .net8 "VPB", 0 0, L_00000000040936a0;  1 drivers, strength-aware
+L_0000000004093cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b490_0 .net8 "VPWR", 0 0, L_0000000004093cc0;  1 drivers, strength-aware
+v0000000003d4a450_0 .net "X", 0 0, L_00000000041654c0;  1 drivers
+S_0000000003d0f4b0 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94790, 4 95264 1, S_00000000029ee9f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165990 .functor BUF 1, o0000000003c7f158, C4<0>, C4<0>, C4<0>;
+L_00000000041654c0 .functor BUF 1, L_0000000004165990, C4<0>, C4<0>, C4<0>;
+v0000000003d4a950_0 .net "A", 0 0, o0000000003c7f158;  alias, 0 drivers
+L_0000000004094a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b030_0 .net8 "VGND", 0 0, L_0000000004094a50;  1 drivers, strength-aware
+L_0000000004094b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bc10_0 .net8 "VNB", 0 0, L_0000000004094b30;  1 drivers, strength-aware
+L_0000000004094c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bf30_0 .net8 "VPB", 0 0, L_0000000004094c10;  1 drivers, strength-aware
+L_0000000004094c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4bfd0_0 .net8 "VPWR", 0 0, L_0000000004094c80;  1 drivers, strength-aware
+v0000000003d4aef0_0 .net "X", 0 0, L_00000000041654c0;  alias, 1 drivers
+v0000000003d4c390_0 .net "buf0_out_X", 0 0, L_0000000004165990;  1 drivers
+S_00000000029eeb70 .scope module, "sky130_fd_sc_hd__clkbuf_2" "sky130_fd_sc_hd__clkbuf_2" 4 95370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7f428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4aa90_0 .net "A", 0 0, o0000000003c7f428;  0 drivers
+L_0000000004093da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ab30_0 .net8 "VGND", 0 0, L_0000000004093da0;  1 drivers, strength-aware
+L_0000000004093fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4abd0_0 .net8 "VNB", 0 0, L_0000000004093fd0;  1 drivers, strength-aware
+L_0000000004093320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ac70_0 .net8 "VPB", 0 0, L_0000000004093320;  1 drivers, strength-aware
+L_00000000040937f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4cb10_0 .net8 "VPWR", 0 0, L_00000000040937f0;  1 drivers, strength-aware
+v0000000003d4e050_0 .net "X", 0 0, L_0000000004166560;  1 drivers
+S_0000000003d12030 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 95384, 4 95264 1, S_00000000029eeb70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166b10 .functor BUF 1, o0000000003c7f428, C4<0>, C4<0>, C4<0>;
+L_0000000004166560 .functor BUF 1, L_0000000004166b10, C4<0>, C4<0>, C4<0>;
+v0000000003d4a770_0 .net "A", 0 0, o0000000003c7f428;  alias, 0 drivers
+L_0000000004093470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b530_0 .net8 "VGND", 0 0, L_0000000004093470;  1 drivers, strength-aware
+L_00000000040934e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4b850_0 .net8 "VNB", 0 0, L_00000000040934e0;  1 drivers, strength-aware
+L_0000000004093550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a9f0_0 .net8 "VPB", 0 0, L_0000000004093550;  1 drivers, strength-aware
+L_0000000004093710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4a590_0 .net8 "VPWR", 0 0, L_0000000004093710;  1 drivers, strength-aware
+v0000000003d4c6b0_0 .net "X", 0 0, L_0000000004166560;  alias, 1 drivers
+v0000000003d4c890_0 .net "buf0_out_X", 0 0, L_0000000004166b10;  1 drivers
+S_00000000029eee70 .scope module, "sky130_fd_sc_hd__clkbuf_4" "sky130_fd_sc_hd__clkbuf_4" 4 94976;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7f6f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4d5b0_0 .net "A", 0 0, o0000000003c7f6f8;  0 drivers
+L_0000000004093780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4eaf0_0 .net8 "VGND", 0 0, L_0000000004093780;  1 drivers, strength-aware
+L_0000000004093860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d650_0 .net8 "VNB", 0 0, L_0000000004093860;  1 drivers, strength-aware
+L_00000000040951c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4dc90_0 .net8 "VPB", 0 0, L_00000000040951c0;  1 drivers, strength-aware
+L_00000000040958c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e550_0 .net8 "VPWR", 0 0, L_00000000040958c0;  1 drivers, strength-aware
+v0000000003d4ecd0_0 .net "X", 0 0, L_0000000004165300;  1 drivers
+S_0000000003d10830 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94990, 4 95264 1, S_00000000029eee70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165920 .functor BUF 1, o0000000003c7f6f8, C4<0>, C4<0>, C4<0>;
+L_0000000004165300 .functor BUF 1, L_0000000004165920, C4<0>, C4<0>, C4<0>;
+v0000000003d4c9d0_0 .net "A", 0 0, o0000000003c7f6f8;  alias, 0 drivers
+L_0000000004094f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4eeb0_0 .net8 "VGND", 0 0, L_0000000004094f90;  1 drivers, strength-aware
+L_0000000004095af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ccf0_0 .net8 "VNB", 0 0, L_0000000004095af0;  1 drivers, strength-aware
+L_0000000004095620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f090_0 .net8 "VPB", 0 0, L_0000000004095620;  1 drivers, strength-aware
+L_0000000004096180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ee10_0 .net8 "VPWR", 0 0, L_0000000004096180;  1 drivers, strength-aware
+v0000000003d4c930_0 .net "X", 0 0, L_0000000004165300;  alias, 1 drivers
+v0000000003d4e5f0_0 .net "buf0_out_X", 0 0, L_0000000004165920;  1 drivers
+S_00000000029f01f0 .scope module, "sky130_fd_sc_hd__clkbuf_8" "sky130_fd_sc_hd__clkbuf_8" 4 95470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7f9c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4d1f0_0 .net "A", 0 0, o0000000003c7f9c8;  0 drivers
+L_0000000004095c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4da10_0 .net8 "VGND", 0 0, L_0000000004095c40;  1 drivers, strength-aware
+L_0000000004095540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d8d0_0 .net8 "VNB", 0 0, L_0000000004095540;  1 drivers, strength-aware
+L_00000000040967a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e730_0 .net8 "VPB", 0 0, L_00000000040967a0;  1 drivers, strength-aware
+L_0000000004096880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4dab0_0 .net8 "VPWR", 0 0, L_0000000004096880;  1 drivers, strength-aware
+v0000000003d4eb90_0 .net "X", 0 0, L_0000000004166aa0;  1 drivers
+S_0000000003d121b0 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 95484, 4 95264 1, S_00000000029f01f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165df0 .functor BUF 1, o0000000003c7f9c8, C4<0>, C4<0>, C4<0>;
+L_0000000004166aa0 .functor BUF 1, L_0000000004165df0, C4<0>, C4<0>, C4<0>;
+v0000000003d4d510_0 .net "A", 0 0, o0000000003c7f9c8;  alias, 0 drivers
+L_0000000004095930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d830_0 .net8 "VGND", 0 0, L_0000000004095930;  1 drivers, strength-aware
+L_0000000004095e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d790_0 .net8 "VNB", 0 0, L_0000000004095e00;  1 drivers, strength-aware
+L_00000000040954d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4cd90_0 .net8 "VPB", 0 0, L_00000000040954d0;  1 drivers, strength-aware
+L_0000000004094cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4cc50_0 .net8 "VPWR", 0 0, L_0000000004094cf0;  1 drivers, strength-aware
+v0000000003d4e690_0 .net "X", 0 0, L_0000000004166aa0;  alias, 1 drivers
+v0000000003d4ed70_0 .net "buf0_out_X", 0 0, L_0000000004165df0;  1 drivers
+S_00000000029ef470 .scope module, "sky130_fd_sc_hd__clkdlybuf4s15_1" "sky130_fd_sc_hd__clkdlybuf4s15_1" 4 81656;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7fc98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4dd30_0 .net "A", 0 0, o0000000003c7fc98;  0 drivers
+L_0000000004094d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ddd0_0 .net8 "VGND", 0 0, L_0000000004094d60;  1 drivers, strength-aware
+L_0000000004095770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4de70_0 .net8 "VNB", 0 0, L_0000000004095770;  1 drivers, strength-aware
+L_0000000004095690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ef50_0 .net8 "VPB", 0 0, L_0000000004095690;  1 drivers, strength-aware
+L_0000000004096340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4df10_0 .net8 "VPWR", 0 0, L_0000000004096340;  1 drivers, strength-aware
+v0000000003d4e7d0_0 .net "X", 0 0, L_00000000041662c0;  1 drivers
+S_0000000003d0f630 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s15" 4 81670, 4 81949 1, S_00000000029ef470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165f40 .functor BUF 1, o0000000003c7fc98, C4<0>, C4<0>, C4<0>;
+L_00000000041662c0 .functor BUF 1, L_0000000004165f40, C4<0>, C4<0>, C4<0>;
+v0000000003d4d6f0_0 .net "A", 0 0, o0000000003c7fc98;  alias, 0 drivers
+L_00000000040955b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4dbf0_0 .net8 "VGND", 0 0, L_00000000040955b0;  1 drivers, strength-aware
+L_0000000004095f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e230_0 .net8 "VNB", 0 0, L_0000000004095f50;  1 drivers, strength-aware
+L_0000000004095fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d970_0 .net8 "VPB", 0 0, L_0000000004095fc0;  1 drivers, strength-aware
+L_0000000004095700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ca70_0 .net8 "VPWR", 0 0, L_0000000004095700;  1 drivers, strength-aware
+v0000000003d4e870_0 .net "X", 0 0, L_00000000041662c0;  alias, 1 drivers
+v0000000003d4cbb0_0 .net "buf0_out_X", 0 0, L_0000000004165f40;  1 drivers
+S_00000000029f0370 .scope module, "sky130_fd_sc_hd__clkdlybuf4s15_2" "sky130_fd_sc_hd__clkdlybuf4s15_2" 4 81555;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c7ff68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4dfb0_0 .net "A", 0 0, o0000000003c7ff68;  0 drivers
+L_00000000040957e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4db50_0 .net8 "VGND", 0 0, L_00000000040957e0;  1 drivers, strength-aware
+L_0000000004096260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4cf70_0 .net8 "VNB", 0 0, L_0000000004096260;  1 drivers, strength-aware
+L_00000000040962d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e0f0_0 .net8 "VPB", 0 0, L_00000000040962d0;  1 drivers, strength-aware
+L_0000000004096570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d150_0 .net8 "VPWR", 0 0, L_0000000004096570;  1 drivers, strength-aware
+v0000000003d4e190_0 .net "X", 0 0, L_00000000041669c0;  1 drivers
+S_0000000003d0f930 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s15" 4 81569, 4 81949 1, S_00000000029f0370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166950 .functor BUF 1, o0000000003c7ff68, C4<0>, C4<0>, C4<0>;
+L_00000000041669c0 .functor BUF 1, L_0000000004166950, C4<0>, C4<0>, C4<0>;
+v0000000003d4e410_0 .net "A", 0 0, o0000000003c7ff68;  alias, 0 drivers
+L_0000000004095e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e2d0_0 .net8 "VGND", 0 0, L_0000000004095e70;  1 drivers, strength-aware
+L_00000000040963b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e370_0 .net8 "VNB", 0 0, L_00000000040963b0;  1 drivers, strength-aware
+L_0000000004095850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d010_0 .net8 "VPB", 0 0, L_0000000004095850;  1 drivers, strength-aware
+L_00000000040953f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ce30_0 .net8 "VPWR", 0 0, L_00000000040953f0;  1 drivers, strength-aware
+v0000000003d4ced0_0 .net "X", 0 0, L_00000000041669c0;  alias, 1 drivers
+v0000000003d4eff0_0 .net "buf0_out_X", 0 0, L_0000000004166950;  1 drivers
+S_00000000029efbf0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s18_1" "sky130_fd_sc_hd__clkdlybuf4s18_1" 4 21940;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c80238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4d330_0 .net "A", 0 0, o0000000003c80238;  0 drivers
+L_0000000004096420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d3d0_0 .net8 "VGND", 0 0, L_0000000004096420;  1 drivers, strength-aware
+L_0000000004094f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d470_0 .net8 "VNB", 0 0, L_0000000004094f20;  1 drivers, strength-aware
+L_00000000040959a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50490_0 .net8 "VPB", 0 0, L_00000000040959a0;  1 drivers, strength-aware
+L_0000000004096490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fef0_0 .net8 "VPWR", 0 0, L_0000000004096490;  1 drivers, strength-aware
+v0000000003d4f770_0 .net "X", 0 0, L_0000000004166cd0;  1 drivers
+S_0000000003d0d830 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s18" 4 21954, 4 22233 1, S_00000000029efbf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041666b0 .functor BUF 1, o0000000003c80238, C4<0>, C4<0>, C4<0>;
+L_0000000004166cd0 .functor BUF 1, L_00000000041666b0, C4<0>, C4<0>, C4<0>;
+v0000000003d4ec30_0 .net "A", 0 0, o0000000003c80238;  alias, 0 drivers
+L_0000000004095a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e4b0_0 .net8 "VGND", 0 0, L_0000000004095a10;  1 drivers, strength-aware
+L_0000000004095a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4e910_0 .net8 "VNB", 0 0, L_0000000004095a80;  1 drivers, strength-aware
+L_0000000004095ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4d0b0_0 .net8 "VPB", 0 0, L_0000000004095ee0;  1 drivers, strength-aware
+L_0000000004095230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ea50_0 .net8 "VPWR", 0 0, L_0000000004095230;  1 drivers, strength-aware
+v0000000003d4d290_0 .net "X", 0 0, L_0000000004166cd0;  alias, 1 drivers
+v0000000003d4e9b0_0 .net "buf0_out_X", 0 0, L_00000000041666b0;  1 drivers
+S_00000000029ef5f0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s18_2" "sky130_fd_sc_hd__clkdlybuf4s18_2" 4 21839;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c80508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d4f590_0 .net "A", 0 0, o0000000003c80508;  0 drivers
+L_0000000004096810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f450_0 .net8 "VGND", 0 0, L_0000000004096810;  1 drivers, strength-aware
+L_0000000004095000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d500d0_0 .net8 "VNB", 0 0, L_0000000004095000;  1 drivers, strength-aware
+L_0000000004094dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d51070_0 .net8 "VPB", 0 0, L_0000000004094dd0;  1 drivers, strength-aware
+L_00000000040960a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fa90_0 .net8 "VPWR", 0 0, L_00000000040960a0;  1 drivers, strength-aware
+v0000000003d50c10_0 .net "X", 0 0, L_00000000041668e0;  1 drivers
+S_0000000003d12930 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s18" 4 21853, 4 22233 1, S_00000000029ef5f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165fb0 .functor BUF 1, o0000000003c80508, C4<0>, C4<0>, C4<0>;
+L_00000000041668e0 .functor BUF 1, L_0000000004165fb0, C4<0>, C4<0>, C4<0>;
+v0000000003d51890_0 .net "A", 0 0, o0000000003c80508;  alias, 0 drivers
+L_0000000004095b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fc70_0 .net8 "VGND", 0 0, L_0000000004095b60;  1 drivers, strength-aware
+L_0000000004096500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d50cb0_0 .net8 "VNB", 0 0, L_0000000004096500;  1 drivers, strength-aware
+L_0000000004095bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50710_0 .net8 "VPB", 0 0, L_0000000004095bd0;  1 drivers, strength-aware
+L_00000000040950e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50530_0 .net8 "VPWR", 0 0, L_00000000040950e0;  1 drivers, strength-aware
+v0000000003d51570_0 .net "X", 0 0, L_00000000041668e0;  alias, 1 drivers
+v0000000003d502b0_0 .net "buf0_out_X", 0 0, L_0000000004165fb0;  1 drivers
+S_00000000029eecf0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s25_1" "sky130_fd_sc_hd__clkdlybuf4s25_1" 4 38508;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c807d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d50df0_0 .net "A", 0 0, o0000000003c807d8;  0 drivers
+L_0000000004095070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d507b0_0 .net8 "VGND", 0 0, L_0000000004095070;  1 drivers, strength-aware
+L_00000000040952a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f3b0_0 .net8 "VNB", 0 0, L_00000000040952a0;  1 drivers, strength-aware
+L_0000000004095150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f8b0_0 .net8 "VPB", 0 0, L_0000000004095150;  1 drivers, strength-aware
+L_0000000004095cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50b70_0 .net8 "VPWR", 0 0, L_0000000004095cb0;  1 drivers, strength-aware
+v0000000003d4f1d0_0 .net "X", 0 0, L_0000000004165220;  1 drivers
+S_0000000003d0dcb0 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s25" 4 38522, 4 38401 1, S_00000000029eecf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166a30 .functor BUF 1, o0000000003c807d8, C4<0>, C4<0>, C4<0>;
+L_0000000004165220 .functor BUF 1, L_0000000004166a30, C4<0>, C4<0>, C4<0>;
+v0000000003d50fd0_0 .net "A", 0 0, o0000000003c807d8;  alias, 0 drivers
+L_00000000040966c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f130_0 .net8 "VGND", 0 0, L_00000000040966c0;  1 drivers, strength-aware
+L_0000000004096650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f810_0 .net8 "VNB", 0 0, L_0000000004096650;  1 drivers, strength-aware
+L_0000000004096730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d511b0_0 .net8 "VPB", 0 0, L_0000000004096730;  1 drivers, strength-aware
+L_00000000040965e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f6d0_0 .net8 "VPWR", 0 0, L_00000000040965e0;  1 drivers, strength-aware
+v0000000003d50210_0 .net "X", 0 0, L_0000000004165220;  alias, 1 drivers
+v0000000003d50d50_0 .net "buf0_out_X", 0 0, L_0000000004166a30;  1 drivers
+S_00000000029ef770 .scope module, "sky130_fd_sc_hd__clkdlybuf4s25_2" "sky130_fd_sc_hd__clkdlybuf4s25_2" 4 38609;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c80aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d50850_0 .net "A", 0 0, o0000000003c80aa8;  0 drivers
+L_0000000004094e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fdb0_0 .net8 "VGND", 0 0, L_0000000004094e40;  1 drivers, strength-aware
+L_0000000004096030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fe50_0 .net8 "VNB", 0 0, L_0000000004096030;  1 drivers, strength-aware
+L_0000000004095d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d51390_0 .net8 "VPB", 0 0, L_0000000004095d20;  1 drivers, strength-aware
+L_0000000004094eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4ff90_0 .net8 "VPWR", 0 0, L_0000000004094eb0;  1 drivers, strength-aware
+v0000000003d50350_0 .net "X", 0 0, L_0000000004165530;  1 drivers
+S_0000000003d11d30 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s25" 4 38623, 4 38401 1, S_00000000029ef770;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041651b0 .functor BUF 1, o0000000003c80aa8, C4<0>, C4<0>, C4<0>;
+L_0000000004165530 .functor BUF 1, L_00000000041651b0, C4<0>, C4<0>, C4<0>;
+v0000000003d50a30_0 .net "A", 0 0, o0000000003c80aa8;  alias, 0 drivers
+L_0000000004095460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fd10_0 .net8 "VGND", 0 0, L_0000000004095460;  1 drivers, strength-aware
+L_0000000004095310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d50670_0 .net8 "VNB", 0 0, L_0000000004095310;  1 drivers, strength-aware
+L_0000000004095380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50170_0 .net8 "VPB", 0 0, L_0000000004095380;  1 drivers, strength-aware
+L_0000000004095d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f950_0 .net8 "VPWR", 0 0, L_0000000004095d90;  1 drivers, strength-aware
+v0000000003d505d0_0 .net "X", 0 0, L_0000000004165530;  alias, 1 drivers
+v0000000003d4f270_0 .net "buf0_out_X", 0 0, L_00000000041651b0;  1 drivers
+S_00000000029ef8f0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s50_1" "sky130_fd_sc_hd__clkdlybuf4s50_1" 4 90585;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c80d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d50990_0 .net "A", 0 0, o0000000003c80d78;  0 drivers
+L_0000000004096110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d50e90_0 .net8 "VGND", 0 0, L_0000000004096110;  1 drivers, strength-aware
+L_00000000040961f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d51110_0 .net8 "VNB", 0 0, L_00000000040961f0;  1 drivers, strength-aware
+L_0000000004096c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f630_0 .net8 "VPB", 0 0, L_0000000004096c70;  1 drivers, strength-aware
+L_0000000004096960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fb30_0 .net8 "VPWR", 0 0, L_0000000004096960;  1 drivers, strength-aware
+v0000000003d51250_0 .net "X", 0 0, L_0000000004165140;  1 drivers
+S_0000000003d0fc30 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s50" 4 90599, 4 90878 1, S_00000000029ef8f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165ca0 .functor BUF 1, o0000000003c80d78, C4<0>, C4<0>, C4<0>;
+L_0000000004165140 .functor BUF 1, L_0000000004165ca0, C4<0>, C4<0>, C4<0>;
+v0000000003d503f0_0 .net "A", 0 0, o0000000003c80d78;  alias, 0 drivers
+L_0000000004096f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4f310_0 .net8 "VGND", 0 0, L_0000000004096f10;  1 drivers, strength-aware
+L_0000000004096b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d50030_0 .net8 "VNB", 0 0, L_0000000004096b20;  1 drivers, strength-aware
+L_0000000004096ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d51610_0 .net8 "VPB", 0 0, L_0000000004096ce0;  1 drivers, strength-aware
+L_0000000004096ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d516b0_0 .net8 "VPWR", 0 0, L_0000000004096ea0;  1 drivers, strength-aware
+v0000000003d4f9f0_0 .net "X", 0 0, L_0000000004165140;  alias, 1 drivers
+v0000000003d4f4f0_0 .net "buf0_out_X", 0 0, L_0000000004165ca0;  1 drivers
+S_00000000029f0070 .scope module, "sky130_fd_sc_hd__clkdlybuf4s50_2" "sky130_fd_sc_hd__clkdlybuf4s50_2" 4 90484;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c81048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d51750_0 .net "A", 0 0, o0000000003c81048;  0 drivers
+L_0000000004096c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d517f0_0 .net8 "VGND", 0 0, L_0000000004096c00;  1 drivers, strength-aware
+L_0000000004096f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53190_0 .net8 "VNB", 0 0, L_0000000004096f80;  1 drivers, strength-aware
+L_0000000004096d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d537d0_0 .net8 "VPB", 0 0, L_0000000004096d50;  1 drivers, strength-aware
+L_0000000004096dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d526f0_0 .net8 "VPWR", 0 0, L_0000000004096dc0;  1 drivers, strength-aware
+v0000000003d532d0_0 .net "X", 0 0, L_0000000004165760;  1 drivers
+S_0000000003d10cb0 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s50" 4 90498, 4 90878 1, S_00000000029f0070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166020 .functor BUF 1, o0000000003c81048, C4<0>, C4<0>, C4<0>;
+L_0000000004165760 .functor BUF 1, L_0000000004166020, C4<0>, C4<0>, C4<0>;
+v0000000003d50ad0_0 .net "A", 0 0, o0000000003c81048;  alias, 0 drivers
+L_00000000040969d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d514d0_0 .net8 "VGND", 0 0, L_00000000040969d0;  1 drivers, strength-aware
+L_0000000004096a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d4fbd0_0 .net8 "VNB", 0 0, L_0000000004096a40;  1 drivers, strength-aware
+L_0000000004096e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d508f0_0 .net8 "VPB", 0 0, L_0000000004096e30;  1 drivers, strength-aware
+L_00000000040968f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d50f30_0 .net8 "VPWR", 0 0, L_00000000040968f0;  1 drivers, strength-aware
+v0000000003d512f0_0 .net "X", 0 0, L_0000000004165760;  alias, 1 drivers
+v0000000003d51430_0 .net "buf0_out_X", 0 0, L_0000000004166020;  1 drivers
+S_00000000029f07f0 .scope module, "sky130_fd_sc_hd__clkinv_1" "sky130_fd_sc_hd__clkinv_1" 4 18836;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c81318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d52830_0 .net "A", 0 0, o0000000003c81318;  0 drivers
+L_0000000004096ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d52d30_0 .net8 "VGND", 0 0, L_0000000004096ab0;  1 drivers, strength-aware
+L_0000000004096b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d520b0_0 .net8 "VNB", 0 0, L_0000000004096b90;  1 drivers, strength-aware
+L_0000000004078270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d53690_0 .net8 "VPB", 0 0, L_0000000004078270;  1 drivers, strength-aware
+L_0000000004078a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d53d70_0 .net8 "VPWR", 0 0, L_0000000004078a50;  1 drivers, strength-aware
+v0000000003d52470_0 .net "Y", 0 0, L_0000000004166bf0;  1 drivers
+S_0000000003d12c30 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18850, 4 18530 1, S_00000000029f07f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165290 .functor NOT 1, o0000000003c81318, C4<0>, C4<0>, C4<0>;
+L_0000000004166bf0 .functor BUF 1, L_0000000004165290, C4<0>, C4<0>, C4<0>;
+v0000000003d53370_0 .net "A", 0 0, o0000000003c81318;  alias, 0 drivers
+L_00000000040789e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d530f0_0 .net8 "VGND", 0 0, L_00000000040789e0;  1 drivers, strength-aware
+L_00000000040782e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d534b0_0 .net8 "VNB", 0 0, L_00000000040782e0;  1 drivers, strength-aware
+L_00000000040785f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52f10_0 .net8 "VPB", 0 0, L_00000000040785f0;  1 drivers, strength-aware
+L_0000000004077ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d535f0_0 .net8 "VPWR", 0 0, L_0000000004077ef0;  1 drivers, strength-aware
+v0000000003d52dd0_0 .net "Y", 0 0, L_0000000004166bf0;  alias, 1 drivers
+v0000000003d53870_0 .net "not0_out_Y", 0 0, L_0000000004165290;  1 drivers
+S_00000000029f04f0 .scope module, "sky130_fd_sc_hd__clkinv_16" "sky130_fd_sc_hd__clkinv_16" 4 18936;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c815e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d53eb0_0 .net "A", 0 0, o0000000003c815e8;  0 drivers
+L_0000000004077f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d51cf0_0 .net8 "VGND", 0 0, L_0000000004077f60;  1 drivers, strength-aware
+L_0000000004077b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54090_0 .net8 "VNB", 0 0, L_0000000004077b70;  1 drivers, strength-aware
+L_00000000040778d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d53910_0 .net8 "VPB", 0 0, L_00000000040778d0;  1 drivers, strength-aware
+L_0000000004078350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d51930_0 .net8 "VPWR", 0 0, L_0000000004078350;  1 drivers, strength-aware
+v0000000003d53410_0 .net "Y", 0 0, L_0000000004165a00;  1 drivers
+S_0000000003d0fdb0 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18950, 4 18530 1, S_00000000029f04f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166480 .functor NOT 1, o0000000003c815e8, C4<0>, C4<0>, C4<0>;
+L_0000000004165a00 .functor BUF 1, L_0000000004166480, C4<0>, C4<0>, C4<0>;
+v0000000003d51b10_0 .net "A", 0 0, o0000000003c815e8;  alias, 0 drivers
+L_0000000004077320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d52ab0_0 .net8 "VGND", 0 0, L_0000000004077320;  1 drivers, strength-aware
+L_0000000004078ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53b90_0 .net8 "VNB", 0 0, L_0000000004078ac0;  1 drivers, strength-aware
+L_0000000004078b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d528d0_0 .net8 "VPB", 0 0, L_0000000004078b30;  1 drivers, strength-aware
+L_00000000040784a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52650_0 .net8 "VPWR", 0 0, L_00000000040784a0;  1 drivers, strength-aware
+v0000000003d53230_0 .net "Y", 0 0, L_0000000004165a00;  alias, 1 drivers
+v0000000003d52790_0 .net "not0_out_Y", 0 0, L_0000000004166480;  1 drivers
+S_00000000029efa70 .scope module, "sky130_fd_sc_hd__clkinv_2" "sky130_fd_sc_hd__clkinv_2" 4 18242;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c818b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d52a10_0 .net "A", 0 0, o0000000003c818b8;  0 drivers
+L_0000000004077710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d52b50_0 .net8 "VGND", 0 0, L_0000000004077710;  1 drivers, strength-aware
+L_0000000004077780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d51d90_0 .net8 "VNB", 0 0, L_0000000004077780;  1 drivers, strength-aware
+L_0000000004077fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d519d0_0 .net8 "VPB", 0 0, L_0000000004077fd0;  1 drivers, strength-aware
+L_0000000004077470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52bf0_0 .net8 "VPWR", 0 0, L_0000000004077470;  1 drivers, strength-aware
+v0000000003d53af0_0 .net "Y", 0 0, L_0000000004166c60;  1 drivers
+S_0000000003d0ff30 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18256, 4 18530 1, S_00000000029efa70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166090 .functor NOT 1, o0000000003c818b8, C4<0>, C4<0>, C4<0>;
+L_0000000004166c60 .functor BUF 1, L_0000000004166090, C4<0>, C4<0>, C4<0>;
+v0000000003d525b0_0 .net "A", 0 0, o0000000003c818b8;  alias, 0 drivers
+L_0000000004077be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d52c90_0 .net8 "VGND", 0 0, L_0000000004077be0;  1 drivers, strength-aware
+L_00000000040774e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53730_0 .net8 "VNB", 0 0, L_00000000040774e0;  1 drivers, strength-aware
+L_0000000004077550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d53550_0 .net8 "VPB", 0 0, L_0000000004077550;  1 drivers, strength-aware
+L_00000000040783c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52970_0 .net8 "VPWR", 0 0, L_00000000040783c0;  1 drivers, strength-aware
+v0000000003d539b0_0 .net "Y", 0 0, L_0000000004166c60;  alias, 1 drivers
+v0000000003d53a50_0 .net "not0_out_Y", 0 0, L_0000000004166090;  1 drivers
+S_00000000029efd70 .scope module, "sky130_fd_sc_hd__clkinv_4" "sky130_fd_sc_hd__clkinv_4" 4 18636;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c81b88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d51e30_0 .net "A", 0 0, o0000000003c81b88;  0 drivers
+L_0000000004078660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53f50_0 .net8 "VGND", 0 0, L_0000000004078660;  1 drivers, strength-aware
+L_0000000004077c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d52290_0 .net8 "VNB", 0 0, L_0000000004077c50;  1 drivers, strength-aware
+L_0000000004077cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d53ff0_0 .net8 "VPB", 0 0, L_0000000004077cc0;  1 drivers, strength-aware
+L_0000000004078c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d51ed0_0 .net8 "VPWR", 0 0, L_0000000004078c10;  1 drivers, strength-aware
+v0000000003d51bb0_0 .net "Y", 0 0, L_0000000004165e60;  1 drivers
+S_0000000003d10230 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18650, 4 18530 1, S_00000000029efd70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166100 .functor NOT 1, o0000000003c81b88, C4<0>, C4<0>, C4<0>;
+L_0000000004165e60 .functor BUF 1, L_0000000004166100, C4<0>, C4<0>, C4<0>;
+v0000000003d521f0_0 .net "A", 0 0, o0000000003c81b88;  alias, 0 drivers
+L_0000000004077d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53c30_0 .net8 "VGND", 0 0, L_0000000004077d30;  1 drivers, strength-aware
+L_00000000040780b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d53cd0_0 .net8 "VNB", 0 0, L_00000000040780b0;  1 drivers, strength-aware
+L_0000000004078430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52e70_0 .net8 "VPB", 0 0, L_0000000004078430;  1 drivers, strength-aware
+L_0000000004078ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52fb0_0 .net8 "VPWR", 0 0, L_0000000004078ba0;  1 drivers, strength-aware
+v0000000003d53050_0 .net "Y", 0 0, L_0000000004165e60;  alias, 1 drivers
+v0000000003d53e10_0 .net "not0_out_Y", 0 0, L_0000000004166100;  1 drivers
+S_00000000029eeff0 .scope module, "sky130_fd_sc_hd__clkinv_8" "sky130_fd_sc_hd__clkinv_8" 4 18736;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c81e58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d52510_0 .net "A", 0 0, o0000000003c81e58;  0 drivers
+L_0000000004077a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55df0_0 .net8 "VGND", 0 0, L_0000000004077a20;  1 drivers, strength-aware
+L_0000000004078c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55490_0 .net8 "VNB", 0 0, L_0000000004078c80;  1 drivers, strength-aware
+L_00000000040770f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55530_0 .net8 "VPB", 0 0, L_00000000040770f0;  1 drivers, strength-aware
+L_00000000040779b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d562f0_0 .net8 "VPWR", 0 0, L_00000000040779b0;  1 drivers, strength-aware
+v0000000003d54db0_0 .net "Y", 0 0, L_00000000041655a0;  1 drivers
+S_0000000003d0de30 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18750, 4 18530 1, S_00000000029eeff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165610 .functor NOT 1, o0000000003c81e58, C4<0>, C4<0>, C4<0>;
+L_00000000041655a0 .functor BUF 1, L_0000000004165610, C4<0>, C4<0>, C4<0>;
+v0000000003d51a70_0 .net "A", 0 0, o0000000003c81e58;  alias, 0 drivers
+L_0000000004077a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d51c50_0 .net8 "VGND", 0 0, L_0000000004077a90;  1 drivers, strength-aware
+L_0000000004078510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d51f70_0 .net8 "VNB", 0 0, L_0000000004078510;  1 drivers, strength-aware
+L_0000000004077da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52010_0 .net8 "VPB", 0 0, L_0000000004077da0;  1 drivers, strength-aware
+L_0000000004077390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d52150_0 .net8 "VPWR", 0 0, L_0000000004077390;  1 drivers, strength-aware
+v0000000003d52330_0 .net "Y", 0 0, L_00000000041655a0;  alias, 1 drivers
+v0000000003d523d0_0 .net "not0_out_Y", 0 0, L_0000000004165610;  1 drivers
+S_00000000029f0670 .scope module, "sky130_fd_sc_hd__clkinvlp_2" "sky130_fd_sc_hd__clkinvlp_2" 4 87943;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c82128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d55ad0_0 .net "A", 0 0, o0000000003c82128;  0 drivers
+L_0000000004077b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54d10_0 .net8 "VGND", 0 0, L_0000000004077b00;  1 drivers, strength-aware
+L_0000000004078040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55710_0 .net8 "VNB", 0 0, L_0000000004078040;  1 drivers, strength-aware
+L_0000000004077e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d550d0_0 .net8 "VPB", 0 0, L_0000000004077e10;  1 drivers, strength-aware
+L_0000000004077e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d548b0_0 .net8 "VPWR", 0 0, L_0000000004077e80;  1 drivers, strength-aware
+v0000000003d555d0_0 .net "Y", 0 0, L_0000000004165370;  1 drivers
+S_0000000003d11730 .scope module, "base" "sky130_fd_sc_hd__clkinvlp" 4 87957, 4 87837 1, S_00000000029f0670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004165840 .functor NOT 1, o0000000003c82128, C4<0>, C4<0>, C4<0>;
+L_0000000004165370 .functor BUF 1, L_0000000004165840, C4<0>, C4<0>, C4<0>;
+v0000000003d54ef0_0 .net "A", 0 0, o0000000003c82128;  alias, 0 drivers
+L_0000000004078120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d561b0_0 .net8 "VGND", 0 0, L_0000000004078120;  1 drivers, strength-aware
+L_0000000004078190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55c10_0 .net8 "VNB", 0 0, L_0000000004078190;  1 drivers, strength-aware
+L_0000000004078580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55a30_0 .net8 "VPB", 0 0, L_0000000004078580;  1 drivers, strength-aware
+L_0000000004078200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55030_0 .net8 "VPWR", 0 0, L_0000000004078200;  1 drivers, strength-aware
+v0000000003d54f90_0 .net "Y", 0 0, L_0000000004165370;  alias, 1 drivers
+v0000000003d55670_0 .net "not0_out_Y", 0 0, L_0000000004165840;  1 drivers
+S_00000000029ef170 .scope module, "sky130_fd_sc_hd__clkinvlp_4" "sky130_fd_sc_hd__clkinvlp_4" 4 88043;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003c823f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d553f0_0 .net "A", 0 0, o0000000003c823f8;  0 drivers
+L_00000000040786d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54130_0 .net8 "VGND", 0 0, L_00000000040786d0;  1 drivers, strength-aware
+L_0000000004078740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55350_0 .net8 "VNB", 0 0, L_0000000004078740;  1 drivers, strength-aware
+L_00000000040787b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56610_0 .net8 "VPB", 0 0, L_00000000040787b0;  1 drivers, strength-aware
+L_0000000004077160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d566b0_0 .net8 "VPWR", 0 0, L_0000000004077160;  1 drivers, strength-aware
+v0000000003d549f0_0 .net "Y", 0 0, L_0000000004165a70;  1 drivers
+S_0000000003d10e30 .scope module, "base" "sky130_fd_sc_hd__clkinvlp" 4 88057, 4 87837 1, S_00000000029ef170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004166b80 .functor NOT 1, o0000000003c823f8, C4<0>, C4<0>, C4<0>;
+L_0000000004165a70 .functor BUF 1, L_0000000004166b80, C4<0>, C4<0>, C4<0>;
+v0000000003d54e50_0 .net "A", 0 0, o0000000003c823f8;  alias, 0 drivers
+L_0000000004078820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55170_0 .net8 "VGND", 0 0, L_0000000004078820;  1 drivers, strength-aware
+L_0000000004078890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56390_0 .net8 "VNB", 0 0, L_0000000004078890;  1 drivers, strength-aware
+L_0000000004078900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d557b0_0 .net8 "VPB", 0 0, L_0000000004078900;  1 drivers, strength-aware
+L_0000000004078970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55210_0 .net8 "VPWR", 0 0, L_0000000004078970;  1 drivers, strength-aware
+v0000000003d552b0_0 .net "Y", 0 0, L_0000000004165a70;  alias, 1 drivers
+v0000000003d54c70_0 .net "not0_out_Y", 0 0, L_0000000004166b80;  1 drivers
+S_00000000029efef0 .scope module, "sky130_fd_sc_hd__decap_12" "sky130_fd_sc_hd__decap_12" 4 83287;
+ .timescale -9 -12;
+L_00000000040771d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55850_0 .net8 "VGND", 0 0, L_00000000040771d0;  1 drivers, strength-aware
+L_0000000004077240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55d50_0 .net8 "VNB", 0 0, L_0000000004077240;  1 drivers, strength-aware
+L_00000000040775c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d558f0_0 .net8 "VPB", 0 0, L_00000000040775c0;  1 drivers, strength-aware
+L_00000000040772b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56070_0 .net8 "VPWR", 0 0, L_00000000040772b0;  1 drivers, strength-aware
+S_0000000003d103b0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83294, 4 82949 1, S_00000000029efef0;
+ .timescale -9 -12;
+L_0000000004077400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d567f0_0 .net8 "VGND", 0 0, L_0000000004077400;  1 drivers, strength-aware
+L_0000000004077630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56750_0 .net8 "VNB", 0 0, L_0000000004077630;  1 drivers, strength-aware
+L_0000000004077940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55cb0_0 .net8 "VPB", 0 0, L_0000000004077940;  1 drivers, strength-aware
+L_00000000040776a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54a90_0 .net8 "VPWR", 0 0, L_00000000040776a0;  1 drivers, strength-aware
+S_00000000029ef2f0 .scope module, "sky130_fd_sc_hd__decap_3" "sky130_fd_sc_hd__decap_3" 4 83035;
+ .timescale -9 -12;
+L_00000000040777f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55990_0 .net8 "VGND", 0 0, L_00000000040777f0;  1 drivers, strength-aware
+L_0000000004077860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55f30_0 .net8 "VNB", 0 0, L_0000000004077860;  1 drivers, strength-aware
+L_00000000040b65f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54810_0 .net8 "VPB", 0 0, L_00000000040b65f0;  1 drivers, strength-aware
+L_00000000040b6270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d541d0_0 .net8 "VPWR", 0 0, L_00000000040b6270;  1 drivers, strength-aware
+S_0000000003d12f30 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83042, 4 82949 1, S_00000000029ef2f0;
+ .timescale -9 -12;
+L_00000000040b62e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55e90_0 .net8 "VGND", 0 0, L_00000000040b62e0;  1 drivers, strength-aware
+L_00000000040b4f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d546d0_0 .net8 "VNB", 0 0, L_00000000040b4f30;  1 drivers, strength-aware
+L_00000000040b5860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56890_0 .net8 "VPB", 0 0, L_00000000040b5860;  1 drivers, strength-aware
+L_00000000040b64a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d55b70_0 .net8 "VPWR", 0 0, L_00000000040b64a0;  1 drivers, strength-aware
+S_00000000029c1aa0 .scope module, "sky130_fd_sc_hd__decap_4" "sky130_fd_sc_hd__decap_4" 4 83119;
+ .timescale -9 -12;
+L_00000000040b5550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56250_0 .net8 "VGND", 0 0, L_00000000040b5550;  1 drivers, strength-aware
+L_00000000040b5710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56570_0 .net8 "VNB", 0 0, L_00000000040b5710;  1 drivers, strength-aware
+L_00000000040b5e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56430_0 .net8 "VPB", 0 0, L_00000000040b5e10;  1 drivers, strength-aware
+L_00000000040b51d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54950_0 .net8 "VPWR", 0 0, L_00000000040b51d0;  1 drivers, strength-aware
+S_0000000003d10fb0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83126, 4 82949 1, S_00000000029c1aa0;
+ .timescale -9 -12;
+L_00000000040b6820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d55fd0_0 .net8 "VGND", 0 0, L_00000000040b6820;  1 drivers, strength-aware
+L_00000000040b4fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56110_0 .net8 "VNB", 0 0, L_00000000040b4fa0;  1 drivers, strength-aware
+L_00000000040b6890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54270_0 .net8 "VPB", 0 0, L_00000000040b6890;  1 drivers, strength-aware
+L_00000000040b60b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54770_0 .net8 "VPWR", 0 0, L_00000000040b60b0;  1 drivers, strength-aware
+S_00000000029c1da0 .scope module, "sky130_fd_sc_hd__decap_6" "sky130_fd_sc_hd__decap_6" 4 83203;
+ .timescale -9 -12;
+L_00000000040b5b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d543b0_0 .net8 "VGND", 0 0, L_00000000040b5b00;  1 drivers, strength-aware
+L_00000000040b6350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54450_0 .net8 "VNB", 0 0, L_00000000040b6350;  1 drivers, strength-aware
+L_00000000040b5940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d544f0_0 .net8 "VPB", 0 0, L_00000000040b5940;  1 drivers, strength-aware
+L_00000000040b50f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54590_0 .net8 "VPWR", 0 0, L_00000000040b50f0;  1 drivers, strength-aware
+S_0000000003d0dfb0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83210, 4 82949 1, S_00000000029c1da0;
+ .timescale -9 -12;
+L_00000000040b5080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54630_0 .net8 "VGND", 0 0, L_00000000040b5080;  1 drivers, strength-aware
+L_00000000040b5240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d564d0_0 .net8 "VNB", 0 0, L_00000000040b5240;  1 drivers, strength-aware
+L_00000000040b5010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54310_0 .net8 "VPB", 0 0, L_00000000040b5010;  1 drivers, strength-aware
+L_00000000040b5780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d54b30_0 .net8 "VPWR", 0 0, L_00000000040b5780;  1 drivers, strength-aware
+S_00000000029c1f20 .scope module, "sky130_fd_sc_hd__decap_8" "sky130_fd_sc_hd__decap_8" 4 83371;
+ .timescale -9 -12;
+L_00000000040b66d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d58550_0 .net8 "VGND", 0 0, L_00000000040b66d0;  1 drivers, strength-aware
+L_00000000040b6660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d57010_0 .net8 "VNB", 0 0, L_00000000040b6660;  1 drivers, strength-aware
+L_00000000040b6740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d578d0_0 .net8 "VPB", 0 0, L_00000000040b6740;  1 drivers, strength-aware
+L_00000000040b67b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d571f0_0 .net8 "VPWR", 0 0, L_00000000040b67b0;  1 drivers, strength-aware
+S_0000000003d10530 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83378, 4 82949 1, S_00000000029c1f20;
+ .timescale -9 -12;
+L_00000000040b57f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d54bd0_0 .net8 "VGND", 0 0, L_00000000040b57f0;  1 drivers, strength-aware
+L_00000000040b5630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d58690_0 .net8 "VNB", 0 0, L_00000000040b5630;  1 drivers, strength-aware
+L_00000000040b6120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56ed0_0 .net8 "VPB", 0 0, L_00000000040b6120;  1 drivers, strength-aware
+L_00000000040b5400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d57a10_0 .net8 "VPWR", 0 0, L_00000000040b5400;  1 drivers, strength-aware
+S_00000000029c1620 .scope module, "sky130_fd_sc_hd__dfbbn_1" "sky130_fd_sc_hd__dfbbn_1" 4 64432;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK_N"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c82e78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d58d70_0 .net "CLK_N", 0 0, o0000000003c82e78;  0 drivers
+o0000000003c82ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d58870_0 .net "D", 0 0, o0000000003c82ed8;  0 drivers
+v0000000003d585f0_0 .net "Q", 0 0, L_00000000041663a0;  1 drivers
+v0000000003d58cd0_0 .net "Q_N", 0 0, L_0000000004166250;  1 drivers
+o0000000003c82fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d576f0_0 .net "RESET_B", 0 0, o0000000003c82fc8;  0 drivers
+o0000000003c83058 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d589b0_0 .net "SET_B", 0 0, o0000000003c83058;  0 drivers
+L_00000000040b4ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d57150_0 .net8 "VGND", 0 0, L_00000000040b4ec0;  1 drivers, strength-aware
+L_00000000040b63c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d58910_0 .net8 "VNB", 0 0, L_00000000040b63c0;  1 drivers, strength-aware
+L_00000000040b4d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d58a50_0 .net8 "VPB", 0 0, L_00000000040b4d00;  1 drivers, strength-aware
+L_00000000040b5b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d58af0_0 .net8 "VPWR", 0 0, L_00000000040b5b70;  1 drivers, strength-aware
+S_0000000003d0e2b0 .scope module, "base" "sky130_fd_sc_hd__dfbbn" 4 64454, 4 64795 1, S_00000000029c1620;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK_N"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c82ff8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041665d0 .functor NOT 1, o0000000003c82ff8, C4<0>, C4<0>, C4<0>;
+o0000000003c83088 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004165680 .functor NOT 1, o0000000003c83088, C4<0>, C4<0>, C4<0>;
+o0000000003c82ea8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004165ae0 .functor NOT 1, o0000000003c82ea8, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N", 7, 2
+ ,"?01b??100"
+ ,"00*???100"
+ ,"?1?b??101"
+ ,"1*0???101"
+ ,"11?n??101"
+ ,"0?1n??100"
+ ,"1x?n??101"
+ ,"0?xn??100"
+ ,"?0?r0?100"
+ ,"??0r1?101"
+ ,"00?p0?100"
+ ,"1?0p1?101"
+ ,"10?x0?10x"
+ ,"0?0x1?10x"
+ ,"?00n??10-"
+ ,"?00?*?10-"
+ ,"???????*x";
+o0000000003c82f08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b6190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b52b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004166800 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000004165680, L_00000000041665d0, L_0000000004165ae0, o0000000003c82f08, v0000000003d584b0_0, L_00000000040b6190, L_00000000040b52b0;
+L_0000000004166330 .functor AND 1, L_0000000003f93900, L_0000000003f94580, C4<1>, C4<1>;
+L_00000000041661e0 .functor AND 1, L_0000000003f93900, L_0000000003f926e0, C4<1>, C4<1>;
+L_0000000004165b50 .functor AND 1, L_0000000004166330, L_00000000041661e0, C4<1>, C4<1>;
+L_00000000041663a0 .functor BUF 1, L_0000000004166800, C4<0>, C4<0>, C4<0>;
+L_0000000004166250 .functor NOT 1, L_0000000004166800, C4<0>, C4<0>, C4<0>;
+v0000000003d58370_0 .net "CLK", 0 0, L_0000000004165ae0;  1 drivers
+v0000000003d56930_0 .net "CLK_N", 0 0, o0000000003c82e78;  alias, 0 drivers
+v0000000003d58230_0 .net "CLK_N_delayed", 0 0, o0000000003c82ea8;  0 drivers
+v0000000003d587d0_0 .net "D", 0 0, o0000000003c82ed8;  alias, 0 drivers
+v0000000003d570b0_0 .net "D_delayed", 0 0, o0000000003c82f08;  0 drivers
+v0000000003d56cf0_0 .net "Q", 0 0, L_00000000041663a0;  alias, 1 drivers
+v0000000003d58ff0_0 .net "Q_N", 0 0, L_0000000004166250;  alias, 1 drivers
+v0000000003d57470_0 .net "RESET", 0 0, L_00000000041665d0;  1 drivers
+v0000000003d57290_0 .net "RESET_B", 0 0, o0000000003c82fc8;  alias, 0 drivers
+v0000000003d57ab0_0 .net "RESET_B_delayed", 0 0, o0000000003c82ff8;  0 drivers
+v0000000003d56d90_0 .net "SET", 0 0, L_0000000004165680;  1 drivers
+v0000000003d56e30_0 .net "SET_B", 0 0, o0000000003c83058;  alias, 0 drivers
+v0000000003d58730_0 .net "SET_B_delayed", 0 0, o0000000003c83088;  0 drivers
+v0000000003d57b50_0 .net8 "VGND", 0 0, L_00000000040b52b0;  1 drivers, strength-aware
+L_00000000040b5c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d56b10_0 .net8 "VNB", 0 0, L_00000000040b5c50;  1 drivers, strength-aware
+L_00000000040b6040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d56f70_0 .net8 "VPB", 0 0, L_00000000040b6040;  1 drivers, strength-aware
+v0000000003d57970_0 .net8 "VPWR", 0 0, L_00000000040b6190;  1 drivers, strength-aware
+v0000000003d57510_0 .net *"_s10", 0 0, L_0000000003f94580;  1 drivers
+L_0000000004189148 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d58190_0 .net/2u *"_s14", 0 0, L_0000000004189148;  1 drivers
+v0000000003d582d0_0 .net *"_s16", 0 0, L_0000000003f926e0;  1 drivers
+L_00000000041890b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d57bf0_0 .net/2u *"_s4", 0 0, L_00000000041890b8;  1 drivers
+L_0000000004189100 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d58410_0 .net/2u *"_s8", 0 0, L_0000000004189100;  1 drivers
+v0000000003d57650_0 .net "awake", 0 0, L_0000000003f93900;  1 drivers
+v0000000003d59090_0 .net "buf_Q", 0 0, L_0000000004166800;  1 drivers
+v0000000003d58e10_0 .net "cond0", 0 0, L_0000000004166330;  1 drivers
+v0000000003d57c90_0 .net "cond1", 0 0, L_00000000041661e0;  1 drivers
+v0000000003d569d0_0 .net "condb", 0 0, L_0000000004165b50;  1 drivers
+v0000000003d584b0_0 .var "notifier", 0 0;
+L_0000000003f93900 .cmp/eeq 1, L_00000000040b6190, L_00000000041890b8;
+L_0000000003f94580 .cmp/eeq 1, o0000000003c82ff8, L_0000000004189100;
+L_0000000003f926e0 .cmp/eeq 1, o0000000003c83088, L_0000000004189148;
+S_00000000029c0ea0 .scope module, "sky130_fd_sc_hd__dfbbn_2" "sky130_fd_sc_hd__dfbbn_2" 4 64942;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK_N"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c836b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d59270_0 .net "CLK_N", 0 0, o0000000003c836b8;  0 drivers
+o0000000003c83718 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5afd0_0 .net "D", 0 0, o0000000003c83718;  0 drivers
+v0000000003d5a530_0 .net "Q", 0 0, L_0000000004165d80;  1 drivers
+v0000000003d5a5d0_0 .net "Q_N", 0 0, L_0000000004166720;  1 drivers
+o0000000003c83808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5b7f0_0 .net "RESET_B", 0 0, o0000000003c83808;  0 drivers
+o0000000003c83898 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d599f0_0 .net "SET_B", 0 0, o0000000003c83898;  0 drivers
+L_00000000040b4de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d593b0_0 .net8 "VGND", 0 0, L_00000000040b4de0;  1 drivers, strength-aware
+L_00000000040b6200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5a350_0 .net8 "VNB", 0 0, L_00000000040b6200;  1 drivers, strength-aware
+L_00000000040b5e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d59770_0 .net8 "VPB", 0 0, L_00000000040b5e80;  1 drivers, strength-aware
+L_00000000040b4d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5b890_0 .net8 "VPWR", 0 0, L_00000000040b4d70;  1 drivers, strength-aware
+S_0000000003d11130 .scope module, "base" "sky130_fd_sc_hd__dfbbn" 4 64964, 4 64795 1, S_00000000029c0ea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK_N"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c83838 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041656f0 .functor NOT 1, o0000000003c83838, C4<0>, C4<0>, C4<0>;
+o0000000003c838c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041664f0 .functor NOT 1, o0000000003c838c8, C4<0>, C4<0>, C4<0>;
+o0000000003c836e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041657d0 .functor NOT 1, o0000000003c836e8, C4<0>, C4<0>, C4<0>;
+o0000000003c83748 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b5be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b4e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041658b0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_00000000041664f0, L_00000000041656f0, L_00000000041657d0, o0000000003c83748, v0000000003d5b750_0, L_00000000040b5be0, L_00000000040b4e50;
+L_0000000004165ed0 .functor AND 1, L_0000000003f93ae0, L_0000000003f92c80, C4<1>, C4<1>;
+L_0000000004165c30 .functor AND 1, L_0000000003f93ae0, L_0000000003f92780, C4<1>, C4<1>;
+L_0000000004165d10 .functor AND 1, L_0000000004165ed0, L_0000000004165c30, C4<1>, C4<1>;
+L_0000000004165d80 .functor BUF 1, L_00000000041658b0, C4<0>, C4<0>, C4<0>;
+L_0000000004166720 .functor NOT 1, L_00000000041658b0, C4<0>, C4<0>, C4<0>;
+v0000000003d57330_0 .net "CLK", 0 0, L_00000000041657d0;  1 drivers
+v0000000003d57d30_0 .net "CLK_N", 0 0, o0000000003c836b8;  alias, 0 drivers
+v0000000003d573d0_0 .net "CLK_N_delayed", 0 0, o0000000003c836e8;  0 drivers
+v0000000003d57dd0_0 .net "D", 0 0, o0000000003c83718;  alias, 0 drivers
+v0000000003d56a70_0 .net "D_delayed", 0 0, o0000000003c83748;  0 drivers
+v0000000003d58b90_0 .net "Q", 0 0, L_0000000004165d80;  alias, 1 drivers
+v0000000003d57e70_0 .net "Q_N", 0 0, L_0000000004166720;  alias, 1 drivers
+v0000000003d58c30_0 .net "RESET", 0 0, L_00000000041656f0;  1 drivers
+v0000000003d56bb0_0 .net "RESET_B", 0 0, o0000000003c83808;  alias, 0 drivers
+v0000000003d58eb0_0 .net "RESET_B_delayed", 0 0, o0000000003c83838;  0 drivers
+v0000000003d58f50_0 .net "SET", 0 0, L_00000000041664f0;  1 drivers
+v0000000003d57790_0 .net "SET_B", 0 0, o0000000003c83898;  alias, 0 drivers
+v0000000003d56c50_0 .net "SET_B_delayed", 0 0, o0000000003c838c8;  0 drivers
+v0000000003d57f10_0 .net8 "VGND", 0 0, L_00000000040b4e50;  1 drivers, strength-aware
+L_00000000040b5ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d57fb0_0 .net8 "VNB", 0 0, L_00000000040b5ef0;  1 drivers, strength-aware
+L_00000000040b6430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d575b0_0 .net8 "VPB", 0 0, L_00000000040b6430;  1 drivers, strength-aware
+v0000000003d58050_0 .net8 "VPWR", 0 0, L_00000000040b5be0;  1 drivers, strength-aware
+v0000000003d580f0_0 .net *"_s10", 0 0, L_0000000003f92c80;  1 drivers
+L_0000000004189220 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d57830_0 .net/2u *"_s14", 0 0, L_0000000004189220;  1 drivers
+v0000000003d5ad50_0 .net *"_s16", 0 0, L_0000000003f92780;  1 drivers
+L_0000000004189190 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d59590_0 .net/2u *"_s4", 0 0, L_0000000004189190;  1 drivers
+L_00000000041891d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d59f90_0 .net/2u *"_s8", 0 0, L_00000000041891d8;  1 drivers
+v0000000003d5a2b0_0 .net "awake", 0 0, L_0000000003f93ae0;  1 drivers
+v0000000003d5a490_0 .net "buf_Q", 0 0, L_00000000041658b0;  1 drivers
+v0000000003d59ef0_0 .net "cond0", 0 0, L_0000000004165ed0;  1 drivers
+v0000000003d59db0_0 .net "cond1", 0 0, L_0000000004165c30;  1 drivers
+v0000000003d5a990_0 .net "condb", 0 0, L_0000000004165d10;  1 drivers
+v0000000003d5b750_0 .var "notifier", 0 0;
+L_0000000003f93ae0 .cmp/eeq 1, L_00000000040b5be0, L_0000000004189190;
+L_0000000003f92c80 .cmp/eeq 1, o0000000003c83838, L_00000000041891d8;
+L_0000000003f92780 .cmp/eeq 1, o0000000003c838c8, L_0000000004189220;
+S_00000000029c0ba0 .scope module, "sky130_fd_sc_hd__dfbbp_1" "sky130_fd_sc_hd__dfbbp_1" 4 44024;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c83ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5b1b0_0 .net "CLK", 0 0, o0000000003c83ec8;  0 drivers
+o0000000003c83f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d59310_0 .net "D", 0 0, o0000000003c83f28;  0 drivers
+v0000000003d5b2f0_0 .net "Q", 0 0, L_0000000004167670;  1 drivers
+v0000000003d5b390_0 .net "Q_N", 0 0, L_00000000041676e0;  1 drivers
+o0000000003c84018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d59950_0 .net "RESET_B", 0 0, o0000000003c84018;  0 drivers
+o0000000003c840a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d59bd0_0 .net "SET_B", 0 0, o0000000003c840a8;  0 drivers
+L_00000000040b5cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d59c70_0 .net8 "VGND", 0 0, L_00000000040b5cc0;  1 drivers, strength-aware
+L_00000000040b58d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d59d10_0 .net8 "VNB", 0 0, L_00000000040b58d0;  1 drivers, strength-aware
+L_00000000040b54e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d59e50_0 .net8 "VPB", 0 0, L_00000000040b54e0;  1 drivers, strength-aware
+L_00000000040b5f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5a210_0 .net8 "VPWR", 0 0, L_00000000040b5f60;  1 drivers, strength-aware
+S_0000000003d0d3b0 .scope module, "base" "sky130_fd_sc_hd__dfbbp" 4 44046, 4 44381 1, S_00000000029c0ba0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "CLK"
+    .port_info 4 /INPUT 1 "SET_B"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003c84048 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004166640 .functor NOT 1, o0000000003c84048, C4<0>, C4<0>, C4<0>;
+o0000000003c840d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004166870 .functor NOT 1, o0000000003c840d8, C4<0>, C4<0>, C4<0>;
+o0000000003c83ef8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003c83f58 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b6510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b5160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168710 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000004166870, L_0000000004166640, o0000000003c83ef8, o0000000003c83f58, v0000000003d59450_0, L_00000000040b6510, L_00000000040b5160;
+L_0000000004168160 .functor AND 1, L_0000000003f94760, L_0000000003f94800, C4<1>, C4<1>;
+L_0000000004167ec0 .functor AND 1, L_0000000003f94760, L_0000000003f948a0, C4<1>, C4<1>;
+L_0000000004168550 .functor AND 1, L_0000000004168160, L_0000000004167ec0, C4<1>, C4<1>;
+L_0000000004167670 .functor BUF 1, L_0000000004168710, C4<0>, C4<0>, C4<0>;
+L_00000000041676e0 .functor NOT 1, L_0000000004168710, C4<0>, C4<0>, C4<0>;
+v0000000003d5adf0_0 .net "CLK", 0 0, o0000000003c83ec8;  alias, 0 drivers
+v0000000003d5aa30_0 .net "CLK_delayed", 0 0, o0000000003c83ef8;  0 drivers
+v0000000003d59130_0 .net "D", 0 0, o0000000003c83f28;  alias, 0 drivers
+v0000000003d5a3f0_0 .net "D_delayed", 0 0, o0000000003c83f58;  0 drivers
+v0000000003d5b4d0_0 .net "Q", 0 0, L_0000000004167670;  alias, 1 drivers
+v0000000003d59630_0 .net "Q_N", 0 0, L_00000000041676e0;  alias, 1 drivers
+v0000000003d591d0_0 .net "RESET", 0 0, L_0000000004166640;  1 drivers
+v0000000003d596d0_0 .net "RESET_B", 0 0, o0000000003c84018;  alias, 0 drivers
+v0000000003d5a0d0_0 .net "RESET_B_delayed", 0 0, o0000000003c84048;  0 drivers
+v0000000003d5b070_0 .net "SET", 0 0, L_0000000004166870;  1 drivers
+v0000000003d59a90_0 .net "SET_B", 0 0, o0000000003c840a8;  alias, 0 drivers
+v0000000003d59810_0 .net "SET_B_delayed", 0 0, o0000000003c840d8;  0 drivers
+v0000000003d5a030_0 .net8 "VGND", 0 0, L_00000000040b5160;  1 drivers, strength-aware
+L_00000000040b5320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5b110_0 .net8 "VNB", 0 0, L_00000000040b5320;  1 drivers, strength-aware
+L_00000000040b5390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d594f0_0 .net8 "VPB", 0 0, L_00000000040b5390;  1 drivers, strength-aware
+v0000000003d5aad0_0 .net8 "VPWR", 0 0, L_00000000040b6510;  1 drivers, strength-aware
+v0000000003d5acb0_0 .net *"_s10", 0 0, L_0000000003f94800;  1 drivers
+L_00000000041892f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5a170_0 .net/2u *"_s14", 0 0, L_00000000041892f8;  1 drivers
+v0000000003d5ab70_0 .net *"_s16", 0 0, L_0000000003f948a0;  1 drivers
+L_0000000004189268 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d59b30_0 .net/2u *"_s4", 0 0, L_0000000004189268;  1 drivers
+L_00000000041892b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5b570_0 .net/2u *"_s8", 0 0, L_00000000041892b0;  1 drivers
+v0000000003d5ac10_0 .net "awake", 0 0, L_0000000003f94760;  1 drivers
+v0000000003d5ae90_0 .net "buf_Q", 0 0, L_0000000004168710;  1 drivers
+v0000000003d5b250_0 .net "cond0", 0 0, L_0000000004168160;  1 drivers
+v0000000003d598b0_0 .net "cond1", 0 0, L_0000000004167ec0;  1 drivers
+v0000000003d5af30_0 .net "condb", 0 0, L_0000000004168550;  1 drivers
+v0000000003d59450_0 .var "notifier", 0 0;
+L_0000000003f94760 .cmp/eeq 1, L_00000000040b6510, L_0000000004189268;
+L_0000000003f94800 .cmp/eeq 1, o0000000003c84048, L_00000000041892b0;
+L_0000000003f948a0 .cmp/eeq 1, o0000000003c840d8, L_00000000041892f8;
+S_00000000029c1320 .scope module, "sky130_fd_sc_hd__dfrbp_1" "sky130_fd_sc_hd__dfrbp_1" 4 15271;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "RESET_B"
+o0000000003c846d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5d370_0 .net "CLK", 0 0, o0000000003c846d8;  0 drivers
+o0000000003c84738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5c010_0 .net "D", 0 0, o0000000003c84738;  0 drivers
+v0000000003d5ce70_0 .net "Q", 0 0, L_0000000004167590;  1 drivers
+v0000000003d5d230_0 .net "Q_N", 0 0, L_0000000004168780;  1 drivers
+o0000000003c84828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5bcf0_0 .net "RESET_B", 0 0, o0000000003c84828;  0 drivers
+L_00000000040b5470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5bd90_0 .net8 "VGND", 0 0, L_00000000040b5470;  1 drivers, strength-aware
+L_00000000040b55c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5d870_0 .net8 "VNB", 0 0, L_00000000040b55c0;  1 drivers, strength-aware
+L_00000000040b5d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5c8d0_0 .net8 "VPB", 0 0, L_00000000040b5d30;  1 drivers, strength-aware
+L_00000000040b56a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5c0b0_0 .net8 "VPWR", 0 0, L_00000000040b56a0;  1 drivers, strength-aware
+S_0000000003d106b0 .scope module, "base" "sky130_fd_sc_hd__dfrbp" 4 15291, 4 15138 1, S_00000000029c1320;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "RESET_B"
+o0000000003c84858 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041688d0 .functor NOT 1, o0000000003c84858, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$PR_pp$PG$N", 6, 2
+ ,"?*b0?10-"
+ ,"??_0?10-"
+ ,"??b_?10-"
+ ,"???1?100"
+ ,"?0r??100"
+ ,"?1r0?101"
+ ,"00R??100"
+ ,"11R0?101"
+ ,"00x??100"
+ ,"11x0?101"
+ ,"0?b%?100"
+ ,"0?_x?100"
+ ,"??????*x";
+o0000000003c84768 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003c84708 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b5fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b59b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167b40 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003c84768, o0000000003c84708, L_00000000041688d0, v0000000003d5d910_0, L_00000000040b5fd0, L_00000000040b59b0;
+o0000000003c84a08 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004166db0 .functor AND 1, o0000000003c84a08, L_0000000003f94a80, C4<1>, C4<1>;
+L_0000000004167a60 .functor AND 1, o0000000003c84a08, L_0000000003f95ac0, C4<1>, C4<1>;
+L_0000000004167590 .functor BUF 1, L_0000000004167b40, C4<0>, C4<0>, C4<0>;
+L_0000000004168780 .functor NOT 1, L_0000000004167b40, C4<0>, C4<0>, C4<0>;
+v0000000003d5a670_0 .net "CLK", 0 0, o0000000003c846d8;  alias, 0 drivers
+v0000000003d5a710_0 .net "CLK_delayed", 0 0, o0000000003c84708;  0 drivers
+v0000000003d5a7b0_0 .net "D", 0 0, o0000000003c84738;  alias, 0 drivers
+v0000000003d5a850_0 .net "D_delayed", 0 0, o0000000003c84768;  0 drivers
+v0000000003d5b430_0 .net "Q", 0 0, L_0000000004167590;  alias, 1 drivers
+v0000000003d5a8f0_0 .net "Q_N", 0 0, L_0000000004168780;  alias, 1 drivers
+v0000000003d5b610_0 .net "RESET", 0 0, L_00000000041688d0;  1 drivers
+v0000000003d5b6b0_0 .net "RESET_B", 0 0, o0000000003c84828;  alias, 0 drivers
+v0000000003d5de10_0 .net "RESET_B_delayed", 0 0, o0000000003c84858;  0 drivers
+v0000000003d5b930_0 .net8 "VGND", 0 0, L_00000000040b59b0;  1 drivers, strength-aware
+L_00000000040b5a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5d5f0_0 .net8 "VNB", 0 0, L_00000000040b5a20;  1 drivers, strength-aware
+L_00000000040b5a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5cab0_0 .net8 "VPB", 0 0, L_00000000040b5a90;  1 drivers, strength-aware
+v0000000003d5d2d0_0 .net8 "VPWR", 0 0, L_00000000040b5fd0;  1 drivers, strength-aware
+L_0000000004189388 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5cc90_0 .net/2u *"_s10", 0 0, L_0000000004189388;  1 drivers
+v0000000003d5cdd0_0 .net *"_s12", 0 0, L_0000000003f95ac0;  1 drivers
+L_0000000004189340 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5c5b0_0 .net/2u *"_s4", 0 0, L_0000000004189340;  1 drivers
+v0000000003d5cd30_0 .net *"_s6", 0 0, L_0000000003f94a80;  1 drivers
+v0000000003d5d690_0 .net "awake", 0 0, o0000000003c84a08;  0 drivers
+v0000000003d5dcd0_0 .net "buf_Q", 0 0, L_0000000004167b40;  1 drivers
+v0000000003d5c6f0_0 .net "cond0", 0 0, L_0000000004166db0;  1 drivers
+v0000000003d5b9d0_0 .net "cond1", 0 0, L_0000000004167a60;  1 drivers
+v0000000003d5d910_0 .var "notifier", 0 0;
+L_0000000003f94a80 .cmp/eeq 1, o0000000003c84858, L_0000000004189340;
+L_0000000003f95ac0 .cmp/eeq 1, o0000000003c84828, L_0000000004189388;
+S_00000000029c20a0 .scope module, "sky130_fd_sc_hd__dfrbp_2" "sky130_fd_sc_hd__dfrbp_2" 4 15389;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "RESET_B"
+o0000000003c84d98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5bc50_0 .net "CLK", 0 0, o0000000003c84d98;  0 drivers
+o0000000003c84df8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5dd70_0 .net "D", 0 0, o0000000003c84df8;  0 drivers
+v0000000003d5c470_0 .net "Q", 0 0, L_0000000004167de0;  1 drivers
+v0000000003d5d7d0_0 .net "Q_N", 0 0, L_00000000041687f0;  1 drivers
+o0000000003c84ee8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5cb50_0 .net "RESET_B", 0 0, o0000000003c84ee8;  0 drivers
+L_00000000040b6580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5c790_0 .net8 "VGND", 0 0, L_00000000040b6580;  1 drivers, strength-aware
+L_00000000040b5da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5bed0_0 .net8 "VNB", 0 0, L_00000000040b5da0;  1 drivers, strength-aware
+L_00000000040b7380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5d050_0 .net8 "VPB", 0 0, L_00000000040b7380;  1 drivers, strength-aware
+L_00000000040b8420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5d0f0_0 .net8 "VPWR", 0 0, L_00000000040b8420;  1 drivers, strength-aware
+S_0000000003d112b0 .scope module, "base" "sky130_fd_sc_hd__dfrbp" 4 15409, 4 15138 1, S_00000000029c20a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "RESET_B"
+o0000000003c84f18 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167c90 .functor NOT 1, o0000000003c84f18, C4<0>, C4<0>, C4<0>;
+o0000000003c84e28 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003c84dc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b8340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b73f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041671a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003c84e28, o0000000003c84dc8, L_0000000004167c90, v0000000003d5c830_0, L_00000000040b8340, L_00000000040b73f0;
+o0000000003d7d0b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004168080 .functor AND 1, o0000000003d7d0b8, L_0000000003f95200, C4<1>, C4<1>;
+L_0000000004167bb0 .functor AND 1, o0000000003d7d0b8, L_0000000003f95c00, C4<1>, C4<1>;
+L_0000000004167de0 .functor BUF 1, L_00000000041671a0, C4<0>, C4<0>, C4<0>;
+L_00000000041687f0 .functor NOT 1, L_00000000041671a0, C4<0>, C4<0>, C4<0>;
+v0000000003d5bbb0_0 .net "CLK", 0 0, o0000000003c84d98;  alias, 0 drivers
+v0000000003d5d550_0 .net "CLK_delayed", 0 0, o0000000003c84dc8;  0 drivers
+v0000000003d5c330_0 .net "D", 0 0, o0000000003c84df8;  alias, 0 drivers
+v0000000003d5d190_0 .net "D_delayed", 0 0, o0000000003c84e28;  0 drivers
+v0000000003d5cf10_0 .net "Q", 0 0, L_0000000004167de0;  alias, 1 drivers
+v0000000003d5ba70_0 .net "Q_N", 0 0, L_00000000041687f0;  alias, 1 drivers
+v0000000003d5da50_0 .net "RESET", 0 0, L_0000000004167c90;  1 drivers
+v0000000003d5c970_0 .net "RESET_B", 0 0, o0000000003c84ee8;  alias, 0 drivers
+v0000000003d5cbf0_0 .net "RESET_B_delayed", 0 0, o0000000003c84f18;  0 drivers
+v0000000003d5bb10_0 .net8 "VGND", 0 0, L_00000000040b73f0;  1 drivers, strength-aware
+L_00000000040b78c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5d730_0 .net8 "VNB", 0 0, L_00000000040b78c0;  1 drivers, strength-aware
+L_00000000040b7a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5be30_0 .net8 "VPB", 0 0, L_00000000040b7a80;  1 drivers, strength-aware
+v0000000003d5deb0_0 .net8 "VPWR", 0 0, L_00000000040b8340;  1 drivers, strength-aware
+L_0000000004189418 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5df50_0 .net/2u *"_s10", 0 0, L_0000000004189418;  1 drivers
+v0000000003d5c650_0 .net *"_s12", 0 0, L_0000000003f95c00;  1 drivers
+L_00000000041893d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5ca10_0 .net/2u *"_s4", 0 0, L_00000000041893d0;  1 drivers
+v0000000003d5c1f0_0 .net *"_s6", 0 0, L_0000000003f95200;  1 drivers
+v0000000003d5d9b0_0 .net "awake", 0 0, o0000000003d7d0b8;  0 drivers
+v0000000003d5c150_0 .net "buf_Q", 0 0, L_00000000041671a0;  1 drivers
+v0000000003d5d410_0 .net "cond0", 0 0, L_0000000004168080;  1 drivers
+v0000000003d5cfb0_0 .net "cond1", 0 0, L_0000000004167bb0;  1 drivers
+v0000000003d5c830_0 .var "notifier", 0 0;
+L_0000000003f95200 .cmp/eeq 1, o0000000003c84f18, L_00000000041893d0;
+L_0000000003f95c00 .cmp/eeq 1, o0000000003c84ee8, L_0000000004189418;
+S_00000000029c23a0 .scope module, "sky130_fd_sc_hd__dfrtn_1" "sky130_fd_sc_hd__dfrtn_1" 4 94319;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7d448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5e4f0_0 .net "CLK_N", 0 0, o0000000003d7d448;  0 drivers
+o0000000003d7d4a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5e590_0 .net "D", 0 0, o0000000003d7d4a8;  0 drivers
+v0000000003d5f170_0 .net "Q", 0 0, L_0000000004167d00;  1 drivers
+o0000000003d7d568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5e8b0_0 .net "RESET_B", 0 0, o0000000003d7d568;  0 drivers
+L_00000000040b7230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5eef0_0 .net8 "VGND", 0 0, L_00000000040b7230;  1 drivers, strength-aware
+L_00000000040b82d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5e270_0 .net8 "VNB", 0 0, L_00000000040b82d0;  1 drivers, strength-aware
+L_00000000040b8490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d604d0_0 .net8 "VPB", 0 0, L_00000000040b8490;  1 drivers, strength-aware
+L_00000000040b71c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5f5d0_0 .net8 "VPWR", 0 0, L_00000000040b71c0;  1 drivers, strength-aware
+S_0000000003d118b0 .scope module, "base" "sky130_fd_sc_hd__dfrtn" 4 94337, 4 94652 1, S_00000000029c23a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7d598 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004166f70 .functor NOT 1, o0000000003d7d598, C4<0>, C4<0>, C4<0>;
+o0000000003d7d478 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167c20 .functor NOT 1, o0000000003d7d478, C4<0>, C4<0>, C4<0>;
+o0000000003d7d4d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b81f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b72a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167ad0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003d7d4d8, L_0000000004167c20, L_0000000004166f70, v0000000003d5f670_0, L_00000000040b81f0, L_00000000040b72a0;
+L_0000000004167280 .functor AND 1, L_0000000003f95ca0, L_0000000003f95020, C4<1>, C4<1>;
+L_0000000004167750 .functor AND 1, L_0000000003f95ca0, L_0000000003f95d40, C4<1>, C4<1>;
+L_0000000004167d00 .functor BUF 1, L_0000000004167ad0, C4<0>, C4<0>, C4<0>;
+v0000000003d5bf70_0 .net "CLK_N", 0 0, o0000000003d7d448;  alias, 0 drivers
+v0000000003d5dff0_0 .net "CLK_N_delayed", 0 0, o0000000003d7d478;  0 drivers
+v0000000003d5c290_0 .net "D", 0 0, o0000000003d7d4a8;  alias, 0 drivers
+v0000000003d5e090_0 .net "D_delayed", 0 0, o0000000003d7d4d8;  0 drivers
+v0000000003d5c3d0_0 .net "Q", 0 0, L_0000000004167d00;  alias, 1 drivers
+v0000000003d5c510_0 .net "RESET", 0 0, L_0000000004166f70;  1 drivers
+v0000000003d5daf0_0 .net "RESET_B", 0 0, o0000000003d7d568;  alias, 0 drivers
+v0000000003d5d4b0_0 .net "RESET_B_delayed", 0 0, o0000000003d7d598;  0 drivers
+v0000000003d5db90_0 .net8 "VGND", 0 0, L_00000000040b72a0;  1 drivers, strength-aware
+L_00000000040b7c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5dc30_0 .net8 "VNB", 0 0, L_00000000040b7c40;  1 drivers, strength-aware
+L_00000000040b75b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d601b0_0 .net8 "VPB", 0 0, L_00000000040b75b0;  1 drivers, strength-aware
+v0000000003d5edb0_0 .net8 "VPWR", 0 0, L_00000000040b81f0;  1 drivers, strength-aware
+v0000000003d5fe90_0 .net *"_s10", 0 0, L_0000000003f95020;  1 drivers
+L_00000000041894f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5fcb0_0 .net/2u *"_s14", 0 0, L_00000000041894f0;  1 drivers
+v0000000003d5f2b0_0 .net *"_s16", 0 0, L_0000000003f95d40;  1 drivers
+L_0000000004189460 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5fad0_0 .net/2u *"_s4", 0 0, L_0000000004189460;  1 drivers
+L_00000000041894a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5e130_0 .net/2u *"_s8", 0 0, L_00000000041894a8;  1 drivers
+v0000000003d5fc10_0 .net "awake", 0 0, L_0000000003f95ca0;  1 drivers
+v0000000003d5ed10_0 .net "buf_Q", 0 0, L_0000000004167ad0;  1 drivers
+v0000000003d5ee50_0 .net "cond0", 0 0, L_0000000004167280;  1 drivers
+v0000000003d5fb70_0 .net "cond1", 0 0, L_0000000004167750;  1 drivers
+v0000000003d5ef90_0 .net "intclk", 0 0, L_0000000004167c20;  1 drivers
+v0000000003d5f670_0 .var "notifier", 0 0;
+L_0000000003f95ca0 .cmp/eeq 1, L_00000000040b81f0, L_0000000004189460;
+L_0000000003f95020 .cmp/eeq 1, o0000000003d7d598, L_00000000041894a8;
+L_0000000003f95d40 .cmp/eeq 1, o0000000003d7d568, L_00000000041894f0;
+S_00000000029c05a0 .scope module, "sky130_fd_sc_hd__dfrtp_1" "sky130_fd_sc_hd__dfrtp_1" 4 27830;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7dad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5ffd0_0 .net "CLK", 0 0, o0000000003d7dad8;  0 drivers
+o0000000003d7db38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d60570_0 .net "D", 0 0, o0000000003d7db38;  0 drivers
+v0000000003d5e6d0_0 .net "Q", 0 0, L_0000000004168010;  1 drivers
+o0000000003d7dbf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d5e770_0 .net "RESET_B", 0 0, o0000000003d7dbf8;  0 drivers
+L_00000000040b6900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d60070_0 .net8 "VGND", 0 0, L_00000000040b6900;  1 drivers, strength-aware
+L_00000000040b7bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5f7b0_0 .net8 "VNB", 0 0, L_00000000040b7bd0;  1 drivers, strength-aware
+L_00000000040b7310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5f850_0 .net8 "VPB", 0 0, L_00000000040b7310;  1 drivers, strength-aware
+L_00000000040b8110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d5e810_0 .net8 "VPWR", 0 0, L_00000000040b8110;  1 drivers, strength-aware
+S_0000000003d11bb0 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 27848, 4 28152 1, S_00000000029c05a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7dc28 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167980 .functor NOT 1, o0000000003d7dc28, C4<0>, C4<0>, C4<0>;
+o0000000003d7db68 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7db08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b7fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b7070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168860 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003d7db68, o0000000003d7db08, L_0000000004167980, v0000000003d5f710_0, L_00000000040b7fc0, L_00000000040b7070;
+L_0000000004166f00 .functor AND 1, L_0000000003f96600, L_0000000003f95480, C4<1>, C4<1>;
+L_00000000041685c0 .functor AND 1, L_0000000003f96600, L_0000000003f95840, C4<1>, C4<1>;
+L_0000000004168010 .functor BUF 1, L_0000000004168860, C4<0>, C4<0>, C4<0>;
+v0000000003d5f030_0 .net "CLK", 0 0, o0000000003d7dad8;  alias, 0 drivers
+v0000000003d5f0d0_0 .net "CLK_delayed", 0 0, o0000000003d7db08;  0 drivers
+v0000000003d5f210_0 .net "D", 0 0, o0000000003d7db38;  alias, 0 drivers
+v0000000003d60250_0 .net "D_delayed", 0 0, o0000000003d7db68;  0 drivers
+v0000000003d5f350_0 .net "Q", 0 0, L_0000000004168010;  alias, 1 drivers
+v0000000003d5f530_0 .net "RESET", 0 0, L_0000000004167980;  1 drivers
+v0000000003d5e1d0_0 .net "RESET_B", 0 0, o0000000003d7dbf8;  alias, 0 drivers
+v0000000003d5fd50_0 .net "RESET_B_delayed", 0 0, o0000000003d7dc28;  0 drivers
+v0000000003d5e630_0 .net8 "VGND", 0 0, L_00000000040b7070;  1 drivers, strength-aware
+L_00000000040b6cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5f3f0_0 .net8 "VNB", 0 0, L_00000000040b6cf0;  1 drivers, strength-aware
+L_00000000040b6970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d60610_0 .net8 "VPB", 0 0, L_00000000040b6970;  1 drivers, strength-aware
+v0000000003d5e9f0_0 .net8 "VPWR", 0 0, L_00000000040b7fc0;  1 drivers, strength-aware
+v0000000003d5e3b0_0 .net *"_s10", 0 0, L_0000000003f95480;  1 drivers
+L_00000000041895c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5f490_0 .net/2u *"_s14", 0 0, L_00000000041895c8;  1 drivers
+v0000000003d5f990_0 .net *"_s16", 0 0, L_0000000003f95840;  1 drivers
+L_0000000004189538 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d60750_0 .net/2u *"_s4", 0 0, L_0000000004189538;  1 drivers
+L_0000000004189580 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d5e450_0 .net/2u *"_s8", 0 0, L_0000000004189580;  1 drivers
+v0000000003d60890_0 .net "awake", 0 0, L_0000000003f96600;  1 drivers
+v0000000003d5e310_0 .net "buf_Q", 0 0, L_0000000004168860;  1 drivers
+v0000000003d5fdf0_0 .net "cond0", 0 0, L_0000000004166f00;  1 drivers
+v0000000003d5ff30_0 .net "cond1", 0 0, L_00000000041685c0;  1 drivers
+v0000000003d5f710_0 .var "notifier", 0 0;
+L_0000000003f96600 .cmp/eeq 1, L_00000000040b7fc0, L_0000000004189538;
+L_0000000003f95480 .cmp/eeq 1, o0000000003d7dc28, L_0000000004189580;
+L_0000000003f95840 .cmp/eeq 1, o0000000003d7dbf8, L_00000000041895c8;
+S_00000000029c1c20 .scope module, "sky130_fd_sc_hd__dfrtp_2" "sky130_fd_sc_hd__dfrtp_2" 4 28280;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7e138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d624b0_0 .net "CLK", 0 0, o0000000003d7e138;  0 drivers
+o0000000003d7e198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d618d0_0 .net "D", 0 0, o0000000003d7e198;  0 drivers
+v0000000003d61790_0 .net "Q", 0 0, L_0000000004166e90;  1 drivers
+o0000000003d7e258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d61f10_0 .net "RESET_B", 0 0, o0000000003d7e258;  0 drivers
+L_00000000040b7700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d62d70_0 .net8 "VGND", 0 0, L_00000000040b7700;  1 drivers, strength-aware
+L_00000000040b6eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d622d0_0 .net8 "VNB", 0 0, L_00000000040b6eb0;  1 drivers, strength-aware
+L_00000000040b7770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d62370_0 .net8 "VPB", 0 0, L_00000000040b7770;  1 drivers, strength-aware
+L_00000000040b7460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d62a50_0 .net8 "VPWR", 0 0, L_00000000040b7460;  1 drivers, strength-aware
+S_0000000003d0e5b0 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 28298, 4 28152 1, S_00000000029c1c20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7e288 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041677c0 .functor NOT 1, o0000000003d7e288, C4<0>, C4<0>, C4<0>;
+o0000000003d7e1c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7e168 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b8030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b6c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041680f0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003d7e1c8, o0000000003d7e168, L_00000000041677c0, v0000000003d609d0_0, L_00000000040b8030, L_00000000040b6c10;
+L_0000000004166d40 .functor AND 1, L_0000000003f95340, L_0000000003f967e0, C4<1>, C4<1>;
+L_0000000004166e20 .functor AND 1, L_0000000003f95340, L_0000000003f96ba0, C4<1>, C4<1>;
+L_0000000004166e90 .functor BUF 1, L_00000000041680f0, C4<0>, C4<0>, C4<0>;
+v0000000003d60110_0 .net "CLK", 0 0, o0000000003d7e138;  alias, 0 drivers
+v0000000003d602f0_0 .net "CLK_delayed", 0 0, o0000000003d7e168;  0 drivers
+v0000000003d5e950_0 .net "D", 0 0, o0000000003d7e198;  alias, 0 drivers
+v0000000003d60390_0 .net "D_delayed", 0 0, o0000000003d7e1c8;  0 drivers
+v0000000003d5ea90_0 .net "Q", 0 0, L_0000000004166e90;  alias, 1 drivers
+v0000000003d5f8f0_0 .net "RESET", 0 0, L_00000000041677c0;  1 drivers
+v0000000003d5eb30_0 .net "RESET_B", 0 0, o0000000003d7e258;  alias, 0 drivers
+v0000000003d60430_0 .net "RESET_B_delayed", 0 0, o0000000003d7e288;  0 drivers
+v0000000003d606b0_0 .net8 "VGND", 0 0, L_00000000040b6c10;  1 drivers, strength-aware
+L_00000000040b74d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d5fa30_0 .net8 "VNB", 0 0, L_00000000040b74d0;  1 drivers, strength-aware
+L_00000000040b77e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d607f0_0 .net8 "VPB", 0 0, L_00000000040b77e0;  1 drivers, strength-aware
+v0000000003d5ebd0_0 .net8 "VPWR", 0 0, L_00000000040b8030;  1 drivers, strength-aware
+v0000000003d5ec70_0 .net *"_s10", 0 0, L_0000000003f967e0;  1 drivers
+L_00000000041896a0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d625f0_0 .net/2u *"_s14", 0 0, L_00000000041896a0;  1 drivers
+v0000000003d60ed0_0 .net *"_s16", 0 0, L_0000000003f96ba0;  1 drivers
+L_0000000004189610 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d60f70_0 .net/2u *"_s4", 0 0, L_0000000004189610;  1 drivers
+L_0000000004189658 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d60e30_0 .net/2u *"_s8", 0 0, L_0000000004189658;  1 drivers
+v0000000003d615b0_0 .net "awake", 0 0, L_0000000003f95340;  1 drivers
+v0000000003d62050_0 .net "buf_Q", 0 0, L_00000000041680f0;  1 drivers
+v0000000003d61010_0 .net "cond0", 0 0, L_0000000004166d40;  1 drivers
+v0000000003d62410_0 .net "cond1", 0 0, L_0000000004166e20;  1 drivers
+v0000000003d609d0_0 .var "notifier", 0 0;
+L_0000000003f95340 .cmp/eeq 1, L_00000000040b8030, L_0000000004189610;
+L_0000000003f967e0 .cmp/eeq 1, o0000000003d7e288, L_0000000004189658;
+L_0000000003f96ba0 .cmp/eeq 1, o0000000003d7e258, L_00000000041896a0;
+S_00000000029c1920 .scope module, "sky130_fd_sc_hd__dfrtp_4" "sky130_fd_sc_hd__dfrtp_4" 4 28392;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7e798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d63090_0 .net "CLK", 0 0, o0000000003d7e798;  0 drivers
+o0000000003d7e7f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d629b0_0 .net "D", 0 0, o0000000003d7e7f8;  0 drivers
+v0000000003d62ff0_0 .net "Q", 0 0, L_0000000004168240;  1 drivers
+o0000000003d7e8b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d61b50_0 .net "RESET_B", 0 0, o0000000003d7e8b8;  0 drivers
+L_00000000040b7620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d61510_0 .net8 "VGND", 0 0, L_00000000040b7620;  1 drivers, strength-aware
+L_00000000040b8260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d627d0_0 .net8 "VNB", 0 0, L_00000000040b8260;  1 drivers, strength-aware
+L_00000000040b7850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d62af0_0 .net8 "VPB", 0 0, L_00000000040b7850;  1 drivers, strength-aware
+L_00000000040b7d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d61650_0 .net8 "VPWR", 0 0, L_00000000040b7d20;  1 drivers, strength-aware
+S_0000000003d12330 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 28410, 4 28152 1, S_00000000029c1920;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "RESET_B"
+o0000000003d7e8e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041670c0 .functor NOT 1, o0000000003d7e8e8, C4<0>, C4<0>, C4<0>;
+o0000000003d7e828 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7e7c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b6dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b6c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041678a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003d7e828, o0000000003d7e7c8, L_00000000041670c0, v0000000003d62870_0, L_00000000040b6dd0, L_00000000040b6c80;
+L_00000000041681d0 .functor AND 1, L_0000000003f96e20, L_0000000003f95de0, C4<1>, C4<1>;
+L_0000000004167360 .functor AND 1, L_0000000003f96e20, L_0000000003f94c60, C4<1>, C4<1>;
+L_0000000004168240 .functor BUF 1, L_00000000041678a0, C4<0>, C4<0>, C4<0>;
+v0000000003d61dd0_0 .net "CLK", 0 0, o0000000003d7e798;  alias, 0 drivers
+v0000000003d62550_0 .net "CLK_delayed", 0 0, o0000000003d7e7c8;  0 drivers
+v0000000003d60930_0 .net "D", 0 0, o0000000003d7e7f8;  alias, 0 drivers
+v0000000003d62230_0 .net "D_delayed", 0 0, o0000000003d7e828;  0 drivers
+v0000000003d62910_0 .net "Q", 0 0, L_0000000004168240;  alias, 1 drivers
+v0000000003d610b0_0 .net "RESET", 0 0, L_00000000041670c0;  1 drivers
+v0000000003d62690_0 .net "RESET_B", 0 0, o0000000003d7e8b8;  alias, 0 drivers
+v0000000003d62e10_0 .net "RESET_B_delayed", 0 0, o0000000003d7e8e8;  0 drivers
+v0000000003d62730_0 .net8 "VGND", 0 0, L_00000000040b6c80;  1 drivers, strength-aware
+L_00000000040b6d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d611f0_0 .net8 "VNB", 0 0, L_00000000040b6d60;  1 drivers, strength-aware
+L_00000000040b7540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d60cf0_0 .net8 "VPB", 0 0, L_00000000040b7540;  1 drivers, strength-aware
+v0000000003d61150_0 .net8 "VPWR", 0 0, L_00000000040b6dd0;  1 drivers, strength-aware
+v0000000003d61830_0 .net *"_s10", 0 0, L_0000000003f95de0;  1 drivers
+L_0000000004189778 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d60b10_0 .net/2u *"_s14", 0 0, L_0000000004189778;  1 drivers
+v0000000003d61ab0_0 .net *"_s16", 0 0, L_0000000003f94c60;  1 drivers
+L_00000000041896e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d60bb0_0 .net/2u *"_s4", 0 0, L_00000000041896e8;  1 drivers
+L_0000000004189730 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d620f0_0 .net/2u *"_s8", 0 0, L_0000000004189730;  1 drivers
+v0000000003d61470_0 .net "awake", 0 0, L_0000000003f96e20;  1 drivers
+v0000000003d62190_0 .net "buf_Q", 0 0, L_00000000041678a0;  1 drivers
+v0000000003d616f0_0 .net "cond0", 0 0, L_00000000041681d0;  1 drivers
+v0000000003d60a70_0 .net "cond1", 0 0, L_0000000004167360;  1 drivers
+v0000000003d62870_0 .var "notifier", 0 0;
+L_0000000003f96e20 .cmp/eeq 1, L_00000000040b6dd0, L_00000000041896e8;
+L_0000000003f95de0 .cmp/eeq 1, o0000000003d7e8e8, L_0000000004189730;
+L_0000000003f94c60 .cmp/eeq 1, o0000000003d7e8b8, L_0000000004189778;
+S_00000000029c0d20 .scope module, "sky130_fd_sc_hd__dfsbp_1" "sky130_fd_sc_hd__dfsbp_1" 4 21611;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SET_B"
+o0000000003d7edf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d640d0_0 .net "CLK", 0 0, o0000000003d7edf8;  0 drivers
+o0000000003d7ee58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d65250_0 .net "D", 0 0, o0000000003d7ee58;  0 drivers
+v0000000003d65610_0 .net "Q", 0 0, L_0000000004167e50;  1 drivers
+v0000000003d652f0_0 .net "Q_N", 0 0, L_0000000004167f30;  1 drivers
+o0000000003d7ef48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d654d0_0 .net "SET_B", 0 0, o0000000003d7ef48;  0 drivers
+L_00000000040b7af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d63590_0 .net8 "VGND", 0 0, L_00000000040b7af0;  1 drivers, strength-aware
+L_00000000040b7690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d656b0_0 .net8 "VNB", 0 0, L_00000000040b7690;  1 drivers, strength-aware
+L_00000000040b69e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d65750_0 .net8 "VPB", 0 0, L_00000000040b69e0;  1 drivers, strength-aware
+L_00000000040b6e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d642b0_0 .net8 "VPWR", 0 0, L_00000000040b6e40;  1 drivers, strength-aware
+S_0000000003d124b0 .scope module, "base" "sky130_fd_sc_hd__dfsbp" 4 21631, 4 21477 1, S_00000000029c0d20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SET_B"
+o0000000003d7ef78 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167d70 .functor NOT 1, o0000000003d7ef78, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$PS_pp$PG$N", 6, 2
+ ,"?*b0?10-"
+ ,"??_0?10-"
+ ,"??b_?10-"
+ ,"???1?101"
+ ,"?0r0?100"
+ ,"?1r??101"
+ ,"00R0?100"
+ ,"11R??101"
+ ,"00x0?100"
+ ,"11x??101"
+ ,"1?b%?101"
+ ,"1?_x?101"
+ ,"??????*x";
+o0000000003d7ee88 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7ee28 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b83b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b7ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004166fe0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003d7ee88, o0000000003d7ee28, L_0000000004167d70, v0000000003d65390_0, L_00000000040b83b0, L_00000000040b7ee0;
+L_0000000004167e50 .functor BUF 1, L_0000000004166fe0, C4<0>, C4<0>, C4<0>;
+L_0000000004167f30 .functor NOT 1, L_0000000004166fe0, C4<0>, C4<0>, C4<0>;
+v0000000003d60c50_0 .net "CLK", 0 0, o0000000003d7edf8;  alias, 0 drivers
+v0000000003d60d90_0 .net "CLK_delayed", 0 0, o0000000003d7ee28;  0 drivers
+v0000000003d61970_0 .net "D", 0 0, o0000000003d7ee58;  alias, 0 drivers
+v0000000003d61a10_0 .net "D_delayed", 0 0, o0000000003d7ee88;  0 drivers
+v0000000003d61bf0_0 .net "Q", 0 0, L_0000000004167e50;  alias, 1 drivers
+v0000000003d61e70_0 .net "Q_N", 0 0, L_0000000004167f30;  alias, 1 drivers
+v0000000003d61fb0_0 .net "SET", 0 0, L_0000000004167d70;  1 drivers
+v0000000003d61290_0 .net "SET_B", 0 0, o0000000003d7ef48;  alias, 0 drivers
+v0000000003d62eb0_0 .net "SET_B_delayed", 0 0, o0000000003d7ef78;  0 drivers
+v0000000003d61330_0 .net8 "VGND", 0 0, L_00000000040b7ee0;  1 drivers, strength-aware
+L_00000000040b80a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d62b90_0 .net8 "VNB", 0 0, L_00000000040b80a0;  1 drivers, strength-aware
+L_00000000040b7930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d61c90_0 .net8 "VPB", 0 0, L_00000000040b7930;  1 drivers, strength-aware
+v0000000003d61d30_0 .net8 "VPWR", 0 0, L_00000000040b83b0;  1 drivers, strength-aware
+L_0000000004189850 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d613d0_0 .net/2u *"_s12", 0 0, L_0000000004189850;  1 drivers
+L_00000000041897c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d62c30_0 .net/2u *"_s4", 0 0, L_00000000041897c0;  1 drivers
+L_0000000004189808 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d62cd0_0 .net/2u *"_s8", 0 0, L_0000000004189808;  1 drivers
+v0000000003d62f50_0 .net "awake", 0 0, L_0000000003f96ce0;  1 drivers
+v0000000003d63db0_0 .net "buf_Q", 0 0, L_0000000004166fe0;  1 drivers
+v0000000003d64f30_0 .net "cond0", 0 0, L_0000000003f95f20;  1 drivers
+v0000000003d64d50_0 .net "cond1", 0 0, L_0000000003f95980;  1 drivers
+v0000000003d65390_0 .var "notifier", 0 0;
+L_0000000003f96ce0 .cmp/eeq 1, L_00000000040b83b0, L_00000000041897c0;
+L_0000000003f95f20 .cmp/eeq 1, o0000000003d7ef78, L_0000000004189808;
+L_0000000003f95980 .cmp/eeq 1, o0000000003d7ef48, L_0000000004189850;
+S_00000000029c0720 .scope module, "sky130_fd_sc_hd__dfsbp_2" "sky130_fd_sc_hd__dfsbp_2" 4 21729;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SET_B"
+o0000000003d7f488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d63450_0 .net "CLK", 0 0, o0000000003d7f488;  0 drivers
+o0000000003d7f4e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d65430_0 .net "D", 0 0, o0000000003d7f4e8;  0 drivers
+v0000000003d645d0_0 .net "Q", 0 0, L_00000000041682b0;  1 drivers
+v0000000003d64c10_0 .net "Q_N", 0 0, L_0000000004168320;  1 drivers
+o0000000003d7f5d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d64490_0 .net "SET_B", 0 0, o0000000003d7f5d8;  0 drivers
+L_00000000040b79a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d64210_0 .net8 "VGND", 0 0, L_00000000040b79a0;  1 drivers, strength-aware
+L_00000000040b7a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d64530_0 .net8 "VNB", 0 0, L_00000000040b7a10;  1 drivers, strength-aware
+L_00000000040b8180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d65570_0 .net8 "VPB", 0 0, L_00000000040b8180;  1 drivers, strength-aware
+L_00000000040b7cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d639f0_0 .net8 "VPWR", 0 0, L_00000000040b7cb0;  1 drivers, strength-aware
+S_0000000003d0d0b0 .scope module, "base" "sky130_fd_sc_hd__dfsbp" 4 21749, 4 21477 1, S_00000000029c0720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SET_B"
+o0000000003d7f608 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167910 .functor NOT 1, o0000000003d7f608, C4<0>, C4<0>, C4<0>;
+o0000000003d7f518 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7f4b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b6b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b7b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167fa0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003d7f518, o0000000003d7f4b8, L_0000000004167910, v0000000003d64b70_0, L_00000000040b6b30, L_00000000040b7b60;
+L_00000000041682b0 .functor BUF 1, L_0000000004167fa0, C4<0>, C4<0>, C4<0>;
+L_0000000004168320 .functor NOT 1, L_0000000004167fa0, C4<0>, C4<0>, C4<0>;
+v0000000003d65070_0 .net "CLK", 0 0, o0000000003d7f488;  alias, 0 drivers
+v0000000003d65890_0 .net "CLK_delayed", 0 0, o0000000003d7f4b8;  0 drivers
+v0000000003d64df0_0 .net "D", 0 0, o0000000003d7f4e8;  alias, 0 drivers
+v0000000003d636d0_0 .net "D_delayed", 0 0, o0000000003d7f518;  0 drivers
+v0000000003d63770_0 .net "Q", 0 0, L_00000000041682b0;  alias, 1 drivers
+v0000000003d63630_0 .net "Q_N", 0 0, L_0000000004168320;  alias, 1 drivers
+v0000000003d64170_0 .net "SET", 0 0, L_0000000004167910;  1 drivers
+v0000000003d63e50_0 .net "SET_B", 0 0, o0000000003d7f5d8;  alias, 0 drivers
+v0000000003d64850_0 .net "SET_B_delayed", 0 0, o0000000003d7f608;  0 drivers
+v0000000003d63810_0 .net8 "VGND", 0 0, L_00000000040b7b60;  1 drivers, strength-aware
+L_00000000040b6a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d63f90_0 .net8 "VNB", 0 0, L_00000000040b6a50;  1 drivers, strength-aware
+L_00000000040b6ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d65110_0 .net8 "VPB", 0 0, L_00000000040b6ac0;  1 drivers, strength-aware
+v0000000003d634f0_0 .net8 "VPWR", 0 0, L_00000000040b6b30;  1 drivers, strength-aware
+L_0000000004189928 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d64990_0 .net/2u *"_s12", 0 0, L_0000000004189928;  1 drivers
+L_0000000004189898 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d64fd0_0 .net/2u *"_s4", 0 0, L_0000000004189898;  1 drivers
+L_00000000041898e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d64e90_0 .net/2u *"_s8", 0 0, L_00000000041898e0;  1 drivers
+v0000000003d638b0_0 .net "awake", 0 0, L_0000000003f96f60;  1 drivers
+v0000000003d651b0_0 .net "buf_Q", 0 0, L_0000000004167fa0;  1 drivers
+v0000000003d63950_0 .net "cond0", 0 0, L_0000000003f96d80;  1 drivers
+v0000000003d64ad0_0 .net "cond1", 0 0, L_0000000003f961a0;  1 drivers
+v0000000003d64b70_0 .var "notifier", 0 0;
+L_0000000003f96f60 .cmp/eeq 1, L_00000000040b6b30, L_0000000004189898;
+L_0000000003f96d80 .cmp/eeq 1, o0000000003d7f608, L_00000000041898e0;
+L_0000000003f961a0 .cmp/eeq 1, o0000000003d7f5d8, L_0000000004189928;
+S_00000000029c08a0 .scope module, "sky130_fd_sc_hd__dfstp_1" "sky130_fd_sc_hd__dfstp_1" 4 27718;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d7fb18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d647b0_0 .net "CLK", 0 0, o0000000003d7fb18;  0 drivers
+o0000000003d7fb78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d672d0_0 .net "D", 0 0, o0000000003d7fb78;  0 drivers
+v0000000003d65930_0 .net "Q", 0 0, L_0000000004168470;  1 drivers
+o0000000003d7fc38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d65d90_0 .net "SET_B", 0 0, o0000000003d7fc38;  0 drivers
+L_00000000040b6f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d67190_0 .net8 "VGND", 0 0, L_00000000040b6f20;  1 drivers, strength-aware
+L_00000000040b6ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d66650_0 .net8 "VNB", 0 0, L_00000000040b6ba0;  1 drivers, strength-aware
+L_00000000040b6f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d67370_0 .net8 "VPB", 0 0, L_00000000040b6f90;  1 drivers, strength-aware
+L_00000000040b7000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d66790_0 .net8 "VPWR", 0 0, L_00000000040b7000;  1 drivers, strength-aware
+S_0000000003d0e730 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27736, 4 27590 1, S_00000000029c08a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d7fc68 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041679f0 .functor NOT 1, o0000000003d7fc68, C4<0>, C4<0>, C4<0>;
+o0000000003d7fba8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d7fb48 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b7e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b70e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041686a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003d7fba8, o0000000003d7fb48, L_00000000041679f0, v0000000003d643f0_0, L_00000000040b7e70, L_00000000040b70e0;
+L_0000000004168470 .functor BUF 1, L_00000000041686a0, C4<0>, C4<0>, C4<0>;
+v0000000003d63a90_0 .net "CLK", 0 0, o0000000003d7fb18;  alias, 0 drivers
+v0000000003d63310_0 .net "CLK_delayed", 0 0, o0000000003d7fb48;  0 drivers
+v0000000003d64350_0 .net "D", 0 0, o0000000003d7fb78;  alias, 0 drivers
+v0000000003d657f0_0 .net "D_delayed", 0 0, o0000000003d7fba8;  0 drivers
+v0000000003d648f0_0 .net "Q", 0 0, L_0000000004168470;  alias, 1 drivers
+v0000000003d63ef0_0 .net "SET", 0 0, L_00000000041679f0;  1 drivers
+v0000000003d64a30_0 .net "SET_B", 0 0, o0000000003d7fc38;  alias, 0 drivers
+v0000000003d64670_0 .net "SET_B_delayed", 0 0, o0000000003d7fc68;  0 drivers
+v0000000003d64cb0_0 .net8 "VGND", 0 0, L_00000000040b70e0;  1 drivers, strength-aware
+L_00000000040b7f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d63130_0 .net8 "VNB", 0 0, L_00000000040b7f50;  1 drivers, strength-aware
+L_00000000040b7150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d631d0_0 .net8 "VPB", 0 0, L_00000000040b7150;  1 drivers, strength-aware
+v0000000003d63b30_0 .net8 "VPWR", 0 0, L_00000000040b7e70;  1 drivers, strength-aware
+L_0000000004189a00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d64710_0 .net/2u *"_s12", 0 0, L_0000000004189a00;  1 drivers
+L_0000000004189970 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d63270_0 .net/2u *"_s4", 0 0, L_0000000004189970;  1 drivers
+L_00000000041899b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d633b0_0 .net/2u *"_s8", 0 0, L_00000000041899b8;  1 drivers
+v0000000003d63bd0_0 .net "awake", 0 0, L_0000000003f95660;  1 drivers
+v0000000003d64030_0 .net "buf_Q", 0 0, L_00000000041686a0;  1 drivers
+v0000000003d63c70_0 .net "cond0", 0 0, L_0000000003f950c0;  1 drivers
+v0000000003d63d10_0 .net "cond1", 0 0, L_0000000003f95160;  1 drivers
+v0000000003d643f0_0 .var "notifier", 0 0;
+L_0000000003f95660 .cmp/eeq 1, L_00000000040b7e70, L_0000000004189970;
+L_0000000003f950c0 .cmp/eeq 1, o0000000003d7fc68, L_00000000041899b8;
+L_0000000003f95160 .cmp/eeq 1, o0000000003d7fc38, L_0000000004189a00;
+S_00000000029c2220 .scope module, "sky130_fd_sc_hd__dfstp_2" "sky130_fd_sc_hd__dfstp_2" 4 27156;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d80118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d661f0_0 .net "CLK", 0 0, o0000000003d80118;  0 drivers
+o0000000003d80178 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d666f0_0 .net "D", 0 0, o0000000003d80178;  0 drivers
+v0000000003d65f70_0 .net "Q", 0 0, L_0000000004168390;  1 drivers
+o0000000003d80238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d67f50_0 .net "SET_B", 0 0, o0000000003d80238;  0 drivers
+L_00000000040b7d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d67e10_0 .net8 "VGND", 0 0, L_00000000040b7d90;  1 drivers, strength-aware
+L_00000000040b7e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d674b0_0 .net8 "VNB", 0 0, L_00000000040b7e00;  1 drivers, strength-aware
+L_00000000040b9920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d68090_0 .net8 "VPB", 0 0, L_00000000040b9920;  1 drivers, strength-aware
+L_00000000040b8810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d65b10_0 .net8 "VPWR", 0 0, L_00000000040b8810;  1 drivers, strength-aware
+S_0000000003d0d230 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27174, 4 27590 1, S_00000000029c2220;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d80268 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004167600 .functor NOT 1, o0000000003d80268, C4<0>, C4<0>, C4<0>;
+o0000000003d801a8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d80148 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b9840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b8880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168630 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003d801a8, o0000000003d80148, L_0000000004167600, v0000000003d65e30_0, L_00000000040b9840, L_00000000040b8880;
+L_0000000004168390 .functor BUF 1, L_0000000004168630, C4<0>, C4<0>, C4<0>;
+v0000000003d65cf0_0 .net "CLK", 0 0, o0000000003d80118;  alias, 0 drivers
+v0000000003d66970_0 .net "CLK_delayed", 0 0, o0000000003d80148;  0 drivers
+v0000000003d660b0_0 .net "D", 0 0, o0000000003d80178;  alias, 0 drivers
+v0000000003d66c90_0 .net "D_delayed", 0 0, o0000000003d801a8;  0 drivers
+v0000000003d65a70_0 .net "Q", 0 0, L_0000000004168390;  alias, 1 drivers
+v0000000003d67230_0 .net "SET", 0 0, L_0000000004167600;  1 drivers
+v0000000003d66dd0_0 .net "SET_B", 0 0, o0000000003d80238;  alias, 0 drivers
+v0000000003d679b0_0 .net "SET_B_delayed", 0 0, o0000000003d80268;  0 drivers
+v0000000003d65bb0_0 .net8 "VGND", 0 0, L_00000000040b8880;  1 drivers, strength-aware
+L_00000000040b9290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d67550_0 .net8 "VNB", 0 0, L_00000000040b9290;  1 drivers, strength-aware
+L_00000000040b9bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d67b90_0 .net8 "VPB", 0 0, L_00000000040b9bc0;  1 drivers, strength-aware
+v0000000003d66830_0 .net8 "VPWR", 0 0, L_00000000040b9840;  1 drivers, strength-aware
+L_0000000004189ad8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d67410_0 .net/2u *"_s12", 0 0, L_0000000004189ad8;  1 drivers
+L_0000000004189a48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d67ff0_0 .net/2u *"_s4", 0 0, L_0000000004189a48;  1 drivers
+L_0000000004189a90 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d66470_0 .net/2u *"_s8", 0 0, L_0000000004189a90;  1 drivers
+v0000000003d66a10_0 .net "awake", 0 0, L_0000000003f95520;  1 drivers
+v0000000003d66bf0_0 .net "buf_Q", 0 0, L_0000000004168630;  1 drivers
+v0000000003d659d0_0 .net "cond0", 0 0, L_0000000003f952a0;  1 drivers
+v0000000003d675f0_0 .net "cond1", 0 0, L_0000000003f96420;  1 drivers
+v0000000003d65e30_0 .var "notifier", 0 0;
+L_0000000003f95520 .cmp/eeq 1, L_00000000040b9840, L_0000000004189a48;
+L_0000000003f952a0 .cmp/eeq 1, o0000000003d80268, L_0000000004189a90;
+L_0000000003f96420 .cmp/eeq 1, o0000000003d80238, L_0000000004189ad8;
+S_00000000029c17a0 .scope module, "sky130_fd_sc_hd__dfstp_4" "sky130_fd_sc_hd__dfstp_4" 4 27268;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d80718 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d66290_0 .net "CLK", 0 0, o0000000003d80718;  0 drivers
+o0000000003d80778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d66330_0 .net "D", 0 0, o0000000003d80778;  0 drivers
+v0000000003d663d0_0 .net "Q", 0 0, L_0000000004168400;  1 drivers
+o0000000003d80838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d66f10_0 .net "SET_B", 0 0, o0000000003d80838;  0 drivers
+L_00000000040ba020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d66fb0_0 .net8 "VGND", 0 0, L_00000000040ba020;  1 drivers, strength-aware
+L_00000000040b9990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d66510_0 .net8 "VNB", 0 0, L_00000000040b9990;  1 drivers, strength-aware
+L_00000000040b9220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d67050_0 .net8 "VPB", 0 0, L_00000000040b9220;  1 drivers, strength-aware
+L_00000000040b8ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d670f0_0 .net8 "VPWR", 0 0, L_00000000040b8ce0;  1 drivers, strength-aware
+S_0000000003d0e8b0 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27286, 4 27590 1, S_00000000029c17a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SET_B"
+o0000000003d80868 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041684e0 .functor NOT 1, o0000000003d80868, C4<0>, C4<0>, C4<0>;
+o0000000003d807a8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d80748 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b8b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b8c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167050 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003d807a8, o0000000003d80748, L_00000000041684e0, v0000000003d66e70_0, L_00000000040b8b90, L_00000000040b8c00;
+L_0000000004168400 .functor BUF 1, L_0000000004167050, C4<0>, C4<0>, C4<0>;
+v0000000003d67d70_0 .net "CLK", 0 0, o0000000003d80718;  alias, 0 drivers
+v0000000003d65ed0_0 .net "CLK_delayed", 0 0, o0000000003d80748;  0 drivers
+v0000000003d65c50_0 .net "D", 0 0, o0000000003d80778;  alias, 0 drivers
+v0000000003d67870_0 .net "D_delayed", 0 0, o0000000003d807a8;  0 drivers
+v0000000003d66010_0 .net "Q", 0 0, L_0000000004168400;  alias, 1 drivers
+v0000000003d67690_0 .net "SET", 0 0, L_00000000041684e0;  1 drivers
+v0000000003d665b0_0 .net "SET_B", 0 0, o0000000003d80838;  alias, 0 drivers
+v0000000003d66150_0 .net "SET_B_delayed", 0 0, o0000000003d80868;  0 drivers
+v0000000003d67730_0 .net8 "VGND", 0 0, L_00000000040b8c00;  1 drivers, strength-aware
+L_00000000040b85e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d668d0_0 .net8 "VNB", 0 0, L_00000000040b85e0;  1 drivers, strength-aware
+L_00000000040b8e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d67eb0_0 .net8 "VPB", 0 0, L_00000000040b8e30;  1 drivers, strength-aware
+v0000000003d66d30_0 .net8 "VPWR", 0 0, L_00000000040b8b90;  1 drivers, strength-aware
+L_0000000004189bb0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d677d0_0 .net/2u *"_s12", 0 0, L_0000000004189bb0;  1 drivers
+L_0000000004189b20 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d67cd0_0 .net/2u *"_s4", 0 0, L_0000000004189b20;  1 drivers
+L_0000000004189b68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d66ab0_0 .net/2u *"_s8", 0 0, L_0000000004189b68;  1 drivers
+v0000000003d67910_0 .net "awake", 0 0, L_0000000003f94b20;  1 drivers
+v0000000003d67a50_0 .net "buf_Q", 0 0, L_0000000004167050;  1 drivers
+v0000000003d67af0_0 .net "cond0", 0 0, L_0000000003f97000;  1 drivers
+v0000000003d66b50_0 .net "cond1", 0 0, L_0000000003f96a60;  1 drivers
+v0000000003d66e70_0 .var "notifier", 0 0;
+L_0000000003f94b20 .cmp/eeq 1, L_00000000040b8b90, L_0000000004189b20;
+L_0000000003f97000 .cmp/eeq 1, o0000000003d80868, L_0000000004189b68;
+L_0000000003f96a60 .cmp/eeq 1, o0000000003d80838, L_0000000004189bb0;
+S_00000000029c0a20 .scope module, "sky130_fd_sc_hd__dfxbp_1" "sky130_fd_sc_hd__dfxbp_1" 4 43145;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+o0000000003d80d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6a750_0 .net "CLK", 0 0, o0000000003d80d18;  0 drivers
+o0000000003d80d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d68450_0 .net "D", 0 0, o0000000003d80d78;  0 drivers
+v0000000003d6a250_0 .net "Q", 0 0, L_00000000041672f0;  1 drivers
+v0000000003d68270_0 .net "Q_N", 0 0, L_00000000041673d0;  1 drivers
+L_00000000040b9c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d69d50_0 .net8 "VGND", 0 0, L_00000000040b9c30;  1 drivers, strength-aware
+L_00000000040b9760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d69df0_0 .net8 "VNB", 0 0, L_00000000040b9760;  1 drivers, strength-aware
+L_00000000040b8f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d69710_0 .net8 "VPB", 0 0, L_00000000040b8f80;  1 drivers, strength-aware
+L_00000000040b9b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d69530_0 .net8 "VPWR", 0 0, L_00000000040b9b50;  1 drivers, strength-aware
+S_0000000003d0ea30 .scope module, "base" "sky130_fd_sc_hd__dfxbp" 4 43163, 4 43459 1, S_00000000029c0a20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$P_pp$PG$N", 5, 2
+ ,"?1r?101"
+ ,"?0r?100"
+ ,"11R?101"
+ ,"00R?100"
+ ,"11Q?101"
+ ,"00Q?100"
+ ,"00x?100"
+ ,"11x?101"
+ ,"??_?10-"
+ ,"?*b?10-"
+ ,"?????*x";
+o0000000003d80da8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d80d48 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b8a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b8ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167130 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003d80da8, o0000000003d80d48, v0000000003d683b0_0, L_00000000040b8a40, L_00000000040b8ff0;
+L_00000000041672f0 .functor BUF 1, L_0000000004167130, C4<0>, C4<0>, C4<0>;
+L_00000000041673d0 .functor NOT 1, L_0000000004167130, C4<0>, C4<0>, C4<0>;
+v0000000003d67c30_0 .net "CLK", 0 0, o0000000003d80d18;  alias, 0 drivers
+v0000000003d68f90_0 .net "CLK_delayed", 0 0, o0000000003d80d48;  0 drivers
+v0000000003d690d0_0 .net "D", 0 0, o0000000003d80d78;  alias, 0 drivers
+v0000000003d69170_0 .net "D_delayed", 0 0, o0000000003d80da8;  0 drivers
+v0000000003d68c70_0 .net "Q", 0 0, L_00000000041672f0;  alias, 1 drivers
+v0000000003d69210_0 .net "Q_N", 0 0, L_00000000041673d0;  alias, 1 drivers
+v0000000003d693f0_0 .net8 "VGND", 0 0, L_00000000040b8ff0;  1 drivers, strength-aware
+L_00000000040b9610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6a2f0_0 .net8 "VNB", 0 0, L_00000000040b9610;  1 drivers, strength-aware
+L_00000000040b8b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6a4d0_0 .net8 "VPB", 0 0, L_00000000040b8b20;  1 drivers, strength-aware
+v0000000003d68590_0 .net8 "VPWR", 0 0, L_00000000040b8a40;  1 drivers, strength-aware
+L_0000000004189bf8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6a610_0 .net/2u *"_s4", 0 0, L_0000000004189bf8;  1 drivers
+v0000000003d6a6b0_0 .net "awake", 0 0, L_0000000003f95b60;  1 drivers
+v0000000003d689f0_0 .net "buf_Q", 0 0, L_0000000004167130;  1 drivers
+v0000000003d683b0_0 .var "notifier", 0 0;
+L_0000000003f95b60 .cmp/eeq 1, L_00000000040b8a40, L_0000000004189bf8;
+S_00000000029c1020 .scope module, "sky130_fd_sc_hd__dfxbp_2" "sky130_fd_sc_hd__dfxbp_2" 4 43033;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+o0000000003d811f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6a390_0 .net "CLK", 0 0, o0000000003d811f8;  0 drivers
+o0000000003d81258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d69670_0 .net "D", 0 0, o0000000003d81258;  0 drivers
+v0000000003d684f0_0 .net "Q", 0 0, L_00000000041674b0;  1 drivers
+v0000000003d69f30_0 .net "Q_N", 0 0, L_0000000004167520;  1 drivers
+L_00000000040b8d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6a1b0_0 .net8 "VGND", 0 0, L_00000000040b8d50;  1 drivers, strength-aware
+L_00000000040b88f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d69fd0_0 .net8 "VNB", 0 0, L_00000000040b88f0;  1 drivers, strength-aware
+L_00000000040b8ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d686d0_0 .net8 "VPB", 0 0, L_00000000040b8ea0;  1 drivers, strength-aware
+L_00000000040b96f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d68130_0 .net8 "VPWR", 0 0, L_00000000040b96f0;  1 drivers, strength-aware
+S_0000000003d18630 .scope module, "base" "sky130_fd_sc_hd__dfxbp" 4 43051, 4 43459 1, S_00000000029c1020;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+o0000000003d81288 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d81228 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b9df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b9060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004167440 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003d81288, o0000000003d81228, v0000000003d6a570_0, L_00000000040b9df0, L_00000000040b9060;
+L_00000000041674b0 .functor BUF 1, L_0000000004167440, C4<0>, C4<0>, C4<0>;
+L_0000000004167520 .functor NOT 1, L_0000000004167440, C4<0>, C4<0>, C4<0>;
+v0000000003d6a7f0_0 .net "CLK", 0 0, o0000000003d811f8;  alias, 0 drivers
+v0000000003d69b70_0 .net "CLK_delayed", 0 0, o0000000003d81228;  0 drivers
+v0000000003d68db0_0 .net "D", 0 0, o0000000003d81258;  alias, 0 drivers
+v0000000003d68a90_0 .net "D_delayed", 0 0, o0000000003d81288;  0 drivers
+v0000000003d68810_0 .net "Q", 0 0, L_00000000041674b0;  alias, 1 drivers
+v0000000003d681d0_0 .net "Q_N", 0 0, L_0000000004167520;  alias, 1 drivers
+v0000000003d69c10_0 .net8 "VGND", 0 0, L_00000000040b9060;  1 drivers, strength-aware
+L_00000000040ba090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d69490_0 .net8 "VNB", 0 0, L_00000000040ba090;  1 drivers, strength-aware
+L_00000000040b87a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d695d0_0 .net8 "VPB", 0 0, L_00000000040b87a0;  1 drivers, strength-aware
+v0000000003d68b30_0 .net8 "VPWR", 0 0, L_00000000040b9df0;  1 drivers, strength-aware
+L_0000000004189c40 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d69e90_0 .net/2u *"_s4", 0 0, L_0000000004189c40;  1 drivers
+v0000000003d68630_0 .net "awake", 0 0, L_0000000003f96380;  1 drivers
+v0000000003d697b0_0 .net "buf_Q", 0 0, L_0000000004167440;  1 drivers
+v0000000003d6a570_0 .var "notifier", 0 0;
+L_0000000003f96380 .cmp/eeq 1, L_00000000040b9df0, L_0000000004189c40;
+S_00000000029c11a0 .scope module, "sky130_fd_sc_hd__dfxtp_1" "sky130_fd_sc_hd__dfxtp_1" 4 58198;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d816d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6a430_0 .net "CLK", 0 0, o0000000003d816d8;  0 drivers
+o0000000003d81738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d68950_0 .net "D", 0 0, o0000000003d81738;  0 drivers
+v0000000003d68bd0_0 .net "Q", 0 0, L_000000000416a000;  1 drivers
+L_00000000040b8500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d68e50_0 .net8 "VGND", 0 0, L_00000000040b8500;  1 drivers, strength-aware
+L_00000000040b9140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d68ef0_0 .net8 "VNB", 0 0, L_00000000040b9140;  1 drivers, strength-aware
+L_00000000040b9a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d69350_0 .net8 "VPB", 0 0, L_00000000040b9a00;  1 drivers, strength-aware
+L_00000000040b86c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d69990_0 .net8 "VPWR", 0 0, L_00000000040b86c0;  1 drivers, strength-aware
+S_0000000003d142b0 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 58214, 4 58082 1, S_00000000029c11a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d81768 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d81708 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b90d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b9ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169200 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003d81768, o0000000003d81708, v0000000003d69ad0_0, L_00000000040b90d0, L_00000000040b9ca0;
+L_000000000416a000 .functor BUF 1, L_0000000004169200, C4<0>, C4<0>, C4<0>;
+v0000000003d6a890_0 .net "CLK", 0 0, o0000000003d816d8;  alias, 0 drivers
+v0000000003d68d10_0 .net "CLK_delayed", 0 0, o0000000003d81708;  0 drivers
+v0000000003d6a070_0 .net "D", 0 0, o0000000003d81738;  alias, 0 drivers
+v0000000003d688b0_0 .net "D_delayed", 0 0, o0000000003d81768;  0 drivers
+v0000000003d69030_0 .net "Q", 0 0, L_000000000416a000;  alias, 1 drivers
+v0000000003d6a110_0 .net8 "VGND", 0 0, L_00000000040b9ca0;  1 drivers, strength-aware
+L_00000000040b9a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d692b0_0 .net8 "VNB", 0 0, L_00000000040b9a70;  1 drivers, strength-aware
+L_00000000040b8960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d68310_0 .net8 "VPB", 0 0, L_00000000040b8960;  1 drivers, strength-aware
+v0000000003d68770_0 .net8 "VPWR", 0 0, L_00000000040b90d0;  1 drivers, strength-aware
+L_0000000004189c88 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d69cb0_0 .net/2u *"_s4", 0 0, L_0000000004189c88;  1 drivers
+v0000000003d69850_0 .net "awake", 0 0, L_0000000003f94d00;  1 drivers
+v0000000003d698f0_0 .net "buf_Q", 0 0, L_0000000004169200;  1 drivers
+v0000000003d69ad0_0 .var "notifier", 0 0;
+L_0000000003f94d00 .cmp/eeq 1, L_00000000040b90d0, L_0000000004189c88;
+S_00000000029c14a0 .scope module, "sky130_fd_sc_hd__dfxtp_2" "sky130_fd_sc_hd__dfxtp_2" 4 57780;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d81b28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6c9b0_0 .net "CLK", 0 0, o0000000003d81b28;  0 drivers
+o0000000003d81b88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6a930_0 .net "D", 0 0, o0000000003d81b88;  0 drivers
+v0000000003d6c550_0 .net "Q", 0 0, L_00000000041695f0;  1 drivers
+L_00000000040b89d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6bab0_0 .net8 "VGND", 0 0, L_00000000040b89d0;  1 drivers, strength-aware
+L_00000000040b8ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c2d0_0 .net8 "VNB", 0 0, L_00000000040b8ab0;  1 drivers, strength-aware
+L_00000000040b97d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6aa70_0 .net8 "VPB", 0 0, L_00000000040b97d0;  1 drivers, strength-aware
+L_00000000040b9ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c910_0 .net8 "VPWR", 0 0, L_00000000040b9ae0;  1 drivers, strength-aware
+S_0000000003d14eb0 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 57796, 4 58082 1, S_00000000029c14a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d81bb8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d81b58 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b9370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b91b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168cc0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003d81bb8, o0000000003d81b58, v0000000003d6b5b0_0, L_00000000040b9370, L_00000000040b91b0;
+L_00000000041695f0 .functor BUF 1, L_0000000004168cc0, C4<0>, C4<0>, C4<0>;
+v0000000003d69a30_0 .net "CLK", 0 0, o0000000003d81b28;  alias, 0 drivers
+v0000000003d6c4b0_0 .net "CLK_delayed", 0 0, o0000000003d81b58;  0 drivers
+v0000000003d6c050_0 .net "D", 0 0, o0000000003d81b88;  alias, 0 drivers
+v0000000003d6b6f0_0 .net "D_delayed", 0 0, o0000000003d81bb8;  0 drivers
+v0000000003d6a9d0_0 .net "Q", 0 0, L_00000000041695f0;  alias, 1 drivers
+v0000000003d6ceb0_0 .net8 "VGND", 0 0, L_00000000040b91b0;  1 drivers, strength-aware
+L_00000000040b9300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6cf50_0 .net8 "VNB", 0 0, L_00000000040b9300;  1 drivers, strength-aware
+L_00000000040b8570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6b650_0 .net8 "VPB", 0 0, L_00000000040b8570;  1 drivers, strength-aware
+v0000000003d6d090_0 .net8 "VPWR", 0 0, L_00000000040b9370;  1 drivers, strength-aware
+L_0000000004189cd0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c870_0 .net/2u *"_s4", 0 0, L_0000000004189cd0;  1 drivers
+v0000000003d6cff0_0 .net "awake", 0 0, L_0000000003f94da0;  1 drivers
+v0000000003d6c190_0 .net "buf_Q", 0 0, L_0000000004168cc0;  1 drivers
+v0000000003d6b5b0_0 .var "notifier", 0 0;
+L_0000000003f94da0 .cmp/eeq 1, L_00000000040b9370, L_0000000004189cd0;
+S_00000000029c2eb0 .scope module, "sky130_fd_sc_hd__dfxtp_4" "sky130_fd_sc_hd__dfxtp_4" 4 57674;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d81f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6cb90_0 .net "CLK", 0 0, o0000000003d81f78;  0 drivers
+o0000000003d81fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6bf10_0 .net "D", 0 0, o0000000003d81fd8;  0 drivers
+v0000000003d6bd30_0 .net "Q", 0 0, L_000000000416a0e0;  1 drivers
+L_00000000040b94c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ab10_0 .net8 "VGND", 0 0, L_00000000040b94c0;  1 drivers, strength-aware
+L_00000000040b9680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ca50_0 .net8 "VNB", 0 0, L_00000000040b9680;  1 drivers, strength-aware
+L_00000000040b9f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ce10_0 .net8 "VPB", 0 0, L_00000000040b9f40;  1 drivers, strength-aware
+L_00000000040b8f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6bfb0_0 .net8 "VPWR", 0 0, L_00000000040b8f10;  1 drivers, strength-aware
+S_0000000003d15030 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 57690, 4 58082 1, S_00000000029c2eb0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+o0000000003d82008 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d81fa8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040b93e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040b9ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168f60 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003d82008, o0000000003d81fa8, v0000000003d6b790_0, L_00000000040b93e0, L_00000000040b9ed0;
+L_000000000416a0e0 .functor BUF 1, L_0000000004168f60, C4<0>, C4<0>, C4<0>;
+v0000000003d6b010_0 .net "CLK", 0 0, o0000000003d81f78;  alias, 0 drivers
+v0000000003d6bdd0_0 .net "CLK_delayed", 0 0, o0000000003d81fa8;  0 drivers
+v0000000003d6c230_0 .net "D", 0 0, o0000000003d81fd8;  alias, 0 drivers
+v0000000003d6b510_0 .net "D_delayed", 0 0, o0000000003d82008;  0 drivers
+v0000000003d6acf0_0 .net "Q", 0 0, L_000000000416a0e0;  alias, 1 drivers
+v0000000003d6b970_0 .net8 "VGND", 0 0, L_00000000040b9ed0;  1 drivers, strength-aware
+L_00000000040b8650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6b8d0_0 .net8 "VNB", 0 0, L_00000000040b8650;  1 drivers, strength-aware
+L_00000000040b8dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ac50_0 .net8 "VPB", 0 0, L_00000000040b8dc0;  1 drivers, strength-aware
+v0000000003d6bc90_0 .net8 "VPWR", 0 0, L_00000000040b93e0;  1 drivers, strength-aware
+L_0000000004189d18 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6b150_0 .net/2u *"_s4", 0 0, L_0000000004189d18;  1 drivers
+v0000000003d6be70_0 .net "awake", 0 0, L_0000000003f95a20;  1 drivers
+v0000000003d6c7d0_0 .net "buf_Q", 0 0, L_0000000004168f60;  1 drivers
+v0000000003d6b790_0 .var "notifier", 0 0;
+L_0000000003f95a20 .cmp/eeq 1, L_00000000040b93e0, L_0000000004189d18;
+S_00000000029c25b0 .scope module, "sky130_fd_sc_hd__diode_2" "sky130_fd_sc_hd__diode_2" 4 759;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "DIODE"
+o0000000003d823c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6c5f0_0 .net "DIODE", 0 0, o0000000003d823c8;  0 drivers
+L_00000000040b98b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6b1f0_0 .net8 "VGND", 0 0, L_00000000040b98b0;  1 drivers, strength-aware
+L_00000000040b9450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c690_0 .net8 "VNB", 0 0, L_00000000040b9450;  1 drivers, strength-aware
+L_00000000040b9e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c730_0 .net8 "VPB", 0 0, L_00000000040b9e60;  1 drivers, strength-aware
+L_00000000040b8730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c410_0 .net8 "VPWR", 0 0, L_00000000040b8730;  1 drivers, strength-aware
+S_0000000003d13b30 .scope module, "base" "sky130_fd_sc_hd__diode" 4 771, 4 1009 1, S_00000000029c25b0;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "DIODE"
+v0000000003d6abb0_0 .net "DIODE", 0 0, o0000000003d823c8;  alias, 0 drivers
+L_00000000040b9d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c0f0_0 .net8 "VGND", 0 0, L_00000000040b9d10;  1 drivers, strength-aware
+L_00000000040b9530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6bb50_0 .net8 "VNB", 0 0, L_00000000040b9530;  1 drivers, strength-aware
+L_00000000040b9d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6c370_0 .net8 "VPB", 0 0, L_00000000040b9d80;  1 drivers, strength-aware
+L_00000000040b8c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ad90_0 .net8 "VPWR", 0 0, L_00000000040b8c70;  1 drivers, strength-aware
+S_00000000029c3330 .scope module, "sky130_fd_sc_hd__dlclkp_1" "sky130_fd_sc_hd__dlclkp_1" 4 4641;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d825d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6bbf0_0 .net "CLK", 0 0, o0000000003d825d8;  0 drivers
+o0000000003d82638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6eb70_0 .net "GATE", 0 0, o0000000003d82638;  0 drivers
+v0000000003d6e8f0_0 .net "GCLK", 0 0, L_000000000416a310;  1 drivers
+L_00000000040b95a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ecb0_0 .net8 "VGND", 0 0, L_00000000040b95a0;  1 drivers, strength-aware
+L_00000000040b9fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6d450_0 .net8 "VNB", 0 0, L_00000000040b9fb0;  1 drivers, strength-aware
+L_00000000040bb7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6edf0_0 .net8 "VPB", 0 0, L_00000000040bb7c0;  1 drivers, strength-aware
+L_00000000040baf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f1b0_0 .net8 "VPWR", 0 0, L_00000000040baf00;  1 drivers, strength-aware
+S_0000000003d187b0 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4657, 4 4949 1, S_00000000029c3330;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d82608 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004168c50 .functor NOT 1, o0000000003d82608, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N", 5, 2
+ ,"?*0?10-"
+ ,"??_?10-"
+ ,"??M?10-"
+ ,"00Q?100"
+ ,"11Q?101"
+ ,"?0R?100"
+ ,"?1R?101"
+ ,"?_1?100"
+ ,"?+1?101"
+ ,"?0r?100"
+ ,"?1r?101"
+ ,"1+x?101"
+ ,"0_x?100"
+ ,"?11?+01"
+ ,"?01?1_0"
+ ,"?11?1_1";
+o0000000003d82668 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ba410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040ba6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416a2a0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d82668, L_0000000004168c50, v0000000003d6b830_0, L_00000000040ba410, L_00000000040ba6b0;
+L_000000000416a310 .functor AND 1, L_000000000416a2a0, o0000000003d82608, C4<1>, C4<1>;
+v0000000003d6ccd0_0 .net "CLK", 0 0, o0000000003d825d8;  alias, 0 drivers
+v0000000003d6aed0_0 .net "CLK_delayed", 0 0, o0000000003d82608;  0 drivers
+v0000000003d6ae30_0 .net "GATE", 0 0, o0000000003d82638;  alias, 0 drivers
+v0000000003d6b470_0 .net "GATE_delayed", 0 0, o0000000003d82668;  0 drivers
+v0000000003d6caf0_0 .net "GCLK", 0 0, L_000000000416a310;  alias, 1 drivers
+v0000000003d6b0b0_0 .net8 "VGND", 0 0, L_00000000040ba6b0;  1 drivers, strength-aware
+L_00000000040baf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6cc30_0 .net8 "VNB", 0 0, L_00000000040baf70;  1 drivers, strength-aware
+L_00000000040babf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6af70_0 .net8 "VPB", 0 0, L_00000000040babf0;  1 drivers, strength-aware
+v0000000003d6cd70_0 .net8 "VPWR", 0 0, L_00000000040ba410;  1 drivers, strength-aware
+L_0000000004189d60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6b290_0 .net/2u *"_s4", 0 0, L_0000000004189d60;  1 drivers
+v0000000003d6b330_0 .net "awake", 0 0, L_0000000003f94bc0;  1 drivers
+v0000000003d6ba10_0 .net "clkn", 0 0, L_0000000004168c50;  1 drivers
+v0000000003d6b3d0_0 .net "m0", 0 0, L_000000000416a2a0;  1 drivers
+v0000000003d6b830_0 .var "notifier", 0 0;
+L_0000000003f94bc0 .cmp/eeq 1, L_00000000040ba410, L_0000000004189d60;
+S_00000000029c4230 .scope module, "sky130_fd_sc_hd__dlclkp_2" "sky130_fd_sc_hd__dlclkp_2" 4 4535;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d82a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6def0_0 .net "CLK", 0 0, o0000000003d82a58;  0 drivers
+o0000000003d82ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6f2f0_0 .net "GATE", 0 0, o0000000003d82ab8;  0 drivers
+v0000000003d6ec10_0 .net "GCLK", 0 0, L_000000000416a1c0;  1 drivers
+L_00000000040baaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6ea30_0 .net8 "VGND", 0 0, L_00000000040baaa0;  1 drivers, strength-aware
+L_00000000040bafe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6e030_0 .net8 "VNB", 0 0, L_00000000040bafe0;  1 drivers, strength-aware
+L_00000000040bb830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6df90_0 .net8 "VPB", 0 0, L_00000000040bb830;  1 drivers, strength-aware
+L_00000000040bae20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6e670_0 .net8 "VPWR", 0 0, L_00000000040bae20;  1 drivers, strength-aware
+S_0000000003d15f30 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4551, 4 4949 1, S_00000000029c4230;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d82a88 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169c80 .functor NOT 1, o0000000003d82a88, C4<0>, C4<0>, C4<0>;
+o0000000003d82ae8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ba480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bb9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169740 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d82ae8, L_0000000004169c80, v0000000003d6ed50_0, L_00000000040ba480, L_00000000040bb9f0;
+L_000000000416a1c0 .functor AND 1, L_0000000004169740, o0000000003d82a88, C4<1>, C4<1>;
+v0000000003d6e530_0 .net "CLK", 0 0, o0000000003d82a58;  alias, 0 drivers
+v0000000003d6f070_0 .net "CLK_delayed", 0 0, o0000000003d82a88;  0 drivers
+v0000000003d6f750_0 .net "GATE", 0 0, o0000000003d82ab8;  alias, 0 drivers
+v0000000003d6e710_0 .net "GATE_delayed", 0 0, o0000000003d82ae8;  0 drivers
+v0000000003d6f4d0_0 .net "GCLK", 0 0, L_000000000416a1c0;  alias, 1 drivers
+v0000000003d6e2b0_0 .net8 "VGND", 0 0, L_00000000040bb9f0;  1 drivers, strength-aware
+L_00000000040bb050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f7f0_0 .net8 "VNB", 0 0, L_00000000040bb050;  1 drivers, strength-aware
+L_00000000040bb520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6e990_0 .net8 "VPB", 0 0, L_00000000040bb520;  1 drivers, strength-aware
+v0000000003d6ddb0_0 .net8 "VPWR", 0 0, L_00000000040ba480;  1 drivers, strength-aware
+L_0000000004189da8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6d770_0 .net/2u *"_s4", 0 0, L_0000000004189da8;  1 drivers
+v0000000003d6f250_0 .net "awake", 0 0, L_0000000003f94e40;  1 drivers
+v0000000003d6de50_0 .net "clkn", 0 0, L_0000000004169c80;  1 drivers
+v0000000003d6ee90_0 .net "m0", 0 0, L_0000000004169740;  1 drivers
+v0000000003d6ed50_0 .var "notifier", 0 0;
+L_0000000003f94e40 .cmp/eeq 1, L_00000000040ba480, L_0000000004189da8;
+S_00000000029c3c30 .scope module, "sky130_fd_sc_hd__dlclkp_4" "sky130_fd_sc_hd__dlclkp_4" 4 4429;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d82ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6f6b0_0 .net "CLK", 0 0, o0000000003d82ed8;  0 drivers
+o0000000003d82f38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6f390_0 .net "GATE", 0 0, o0000000003d82f38;  0 drivers
+v0000000003d6f110_0 .net "GCLK", 0 0, L_00000000041697b0;  1 drivers
+L_00000000040ba560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f430_0 .net8 "VGND", 0 0, L_00000000040ba560;  1 drivers, strength-aware
+L_00000000040bb440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6e3f0_0 .net8 "VNB", 0 0, L_00000000040bb440;  1 drivers, strength-aware
+L_00000000040bb4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f570_0 .net8 "VPB", 0 0, L_00000000040bb4b0;  1 drivers, strength-aware
+L_00000000040ba1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f890_0 .net8 "VPWR", 0 0, L_00000000040ba1e0;  1 drivers, strength-aware
+S_0000000003d18ab0 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4445, 4 4949 1, S_00000000029c3c30;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "GATE"
+    .port_info 2 /INPUT 1 "CLK"
+o0000000003d82f08 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a230 .functor NOT 1, o0000000003d82f08, C4<0>, C4<0>, C4<0>;
+o0000000003d82f68 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bbad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bb590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169890 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d82f68, L_000000000416a230, v0000000003d6e350_0, L_00000000040bbad0, L_00000000040bb590;
+L_00000000041697b0 .functor AND 1, L_0000000004169890, o0000000003d82f08, C4<1>, C4<1>;
+v0000000003d6e7b0_0 .net "CLK", 0 0, o0000000003d82ed8;  alias, 0 drivers
+v0000000003d6e0d0_0 .net "CLK_delayed", 0 0, o0000000003d82f08;  0 drivers
+v0000000003d6d4f0_0 .net "GATE", 0 0, o0000000003d82f38;  alias, 0 drivers
+v0000000003d6e850_0 .net "GATE_delayed", 0 0, o0000000003d82f68;  0 drivers
+v0000000003d6d950_0 .net "GCLK", 0 0, L_00000000041697b0;  alias, 1 drivers
+v0000000003d6e5d0_0 .net8 "VGND", 0 0, L_00000000040bb590;  1 drivers, strength-aware
+L_00000000040bb280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6efd0_0 .net8 "VNB", 0 0, L_00000000040bb280;  1 drivers, strength-aware
+L_00000000040bba60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6e170_0 .net8 "VPB", 0 0, L_00000000040bba60;  1 drivers, strength-aware
+v0000000003d6ef30_0 .net8 "VPWR", 0 0, L_00000000040bbad0;  1 drivers, strength-aware
+L_0000000004189df0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f610_0 .net/2u *"_s4", 0 0, L_0000000004189df0;  1 drivers
+v0000000003d6e210_0 .net "awake", 0 0, L_0000000003f96ec0;  1 drivers
+v0000000003d6ead0_0 .net "clkn", 0 0, L_000000000416a230;  1 drivers
+v0000000003d6e490_0 .net "m0", 0 0, L_0000000004169890;  1 drivers
+v0000000003d6e350_0 .var "notifier", 0 0;
+L_0000000003f96ec0 .cmp/eeq 1, L_00000000040bbad0, L_0000000004189df0;
+S_00000000029c43b0 .scope module, "sky130_fd_sc_hd__dlrbn_1" "sky130_fd_sc_hd__dlrbn_1" 4 68978;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE_N"
+o0000000003d83358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d70a10_0 .net "D", 0 0, o0000000003d83358;  0 drivers
+o0000000003d833b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d71a50_0 .net "GATE_N", 0 0, o0000000003d833b8;  0 drivers
+v0000000003d70d30_0 .net "Q", 0 0, L_0000000004169820;  1 drivers
+v0000000003d6fc50_0 .net "Q_N", 0 0, L_00000000041692e0;  1 drivers
+o0000000003d834a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d701f0_0 .net "RESET_B", 0 0, o0000000003d834a8;  0 drivers
+L_00000000040bb2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d719b0_0 .net8 "VGND", 0 0, L_00000000040bb2f0;  1 drivers, strength-aware
+L_00000000040bb600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d70150_0 .net8 "VNB", 0 0, L_00000000040bb600;  1 drivers, strength-aware
+L_00000000040bb0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d71370_0 .net8 "VPB", 0 0, L_00000000040bb0c0;  1 drivers, strength-aware
+L_00000000040bb130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d70dd0_0 .net8 "VPWR", 0 0, L_00000000040bb130;  1 drivers, strength-aware
+S_0000000003d16b30 .scope module, "base" "sky130_fd_sc_hd__dlrbn" 4 68998, 4 68840 1, S_00000000029c43b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE_N"
+o0000000003d834d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169040 .functor NOT 1, o0000000003d834d8, C4<0>, C4<0>, C4<0>;
+o0000000003d833e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a070 .functor NOT 1, o0000000003d833e8, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N", 6, 2
+ ,"?*00?10-"
+ ,"???1?100"
+ ,"??_0?10-"
+ ,"??M0?10-"
+ ,"00Q0?100"
+ ,"11Q0?101"
+ ,"?0R0?100"
+ ,"?1R0?101"
+ ,"?_10?100"
+ ,"?+10?101"
+ ,"?0r0?100"
+ ,"?1r0?101"
+ ,"0?0%?100"
+ ,"0*0x?100"
+ ,"?0+x?100"
+ ,"?_1x?100"
+ ,"?01%?100"
+ ,"??0_?10-"
+ ,"?01_?100"
+ ,"?11_?101"
+ ,"1+x0?101"
+ ,"0_x0?100"
+ ,"?110?+01"
+ ,"?010?1_0"
+ ,"?110?1_1";
+o0000000003d83388 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ba330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bab80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169430 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d83388, L_000000000416a070, L_0000000004169040, v0000000003d6fd90_0, L_00000000040ba330, L_00000000040bab80;
+L_00000000041696d0 .functor AND 1, L_0000000003f958e0, L_0000000003f94ee0, C4<1>, C4<1>;
+L_0000000004169270 .functor AND 1, L_0000000003f958e0, L_0000000003f96740, C4<1>, C4<1>;
+L_0000000004169820 .functor BUF 1, L_0000000004169430, C4<0>, C4<0>, C4<0>;
+L_00000000041692e0 .functor NOT 1, L_0000000004169430, C4<0>, C4<0>, C4<0>;
+v0000000003d6d590_0 .net "D", 0 0, o0000000003d83358;  alias, 0 drivers
+v0000000003d6d130_0 .net "D_delayed", 0 0, o0000000003d83388;  0 drivers
+v0000000003d6d270_0 .net "GATE_N", 0 0, o0000000003d833b8;  alias, 0 drivers
+v0000000003d6d1d0_0 .net "GATE_N_delayed", 0 0, o0000000003d833e8;  0 drivers
+v0000000003d6d310_0 .net "Q", 0 0, L_0000000004169820;  alias, 1 drivers
+v0000000003d6d3b0_0 .net "Q_N", 0 0, L_00000000041692e0;  alias, 1 drivers
+v0000000003d6d630_0 .net "RESET", 0 0, L_0000000004169040;  1 drivers
+v0000000003d6d6d0_0 .net "RESET_B", 0 0, o0000000003d834a8;  alias, 0 drivers
+v0000000003d6d810_0 .net "RESET_B_delayed", 0 0, o0000000003d834d8;  0 drivers
+v0000000003d6d8b0_0 .net8 "VGND", 0 0, L_00000000040bab80;  1 drivers, strength-aware
+L_00000000040ba8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d6d9f0_0 .net8 "VNB", 0 0, L_00000000040ba8e0;  1 drivers, strength-aware
+L_00000000040bb360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6da90_0 .net8 "VPB", 0 0, L_00000000040bb360;  1 drivers, strength-aware
+v0000000003d6db30_0 .net8 "VPWR", 0 0, L_00000000040ba330;  1 drivers, strength-aware
+v0000000003d6dbd0_0 .net *"_s10", 0 0, L_0000000003f94ee0;  1 drivers
+L_0000000004189ec8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d6dc70_0 .net/2u *"_s14", 0 0, L_0000000004189ec8;  1 drivers
+v0000000003d6dd10_0 .net *"_s16", 0 0, L_0000000003f96740;  1 drivers
+L_0000000004189e38 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d70010_0 .net/2u *"_s4", 0 0, L_0000000004189e38;  1 drivers
+L_0000000004189e80 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d71910_0 .net/2u *"_s8", 0 0, L_0000000004189e80;  1 drivers
+v0000000003d70bf0_0 .net "awake", 0 0, L_0000000003f958e0;  1 drivers
+v0000000003d70c90_0 .net "buf_Q", 0 0, L_0000000004169430;  1 drivers
+v0000000003d717d0_0 .net "cond0", 0 0, L_00000000041696d0;  1 drivers
+v0000000003d708d0_0 .net "cond1", 0 0, L_0000000004169270;  1 drivers
+v0000000003d700b0_0 .net "intgate", 0 0, L_000000000416a070;  1 drivers
+v0000000003d6fd90_0 .var "notifier", 0 0;
+L_0000000003f958e0 .cmp/eeq 1, L_00000000040ba330, L_0000000004189e38;
+L_0000000003f94ee0 .cmp/eeq 1, o0000000003d834d8, L_0000000004189e80;
+L_0000000003f96740 .cmp/eeq 1, o0000000003d834a8, L_0000000004189ec8;
+S_00000000029c2730 .scope module, "sky130_fd_sc_hd__dlrbn_2" "sky130_fd_sc_hd__dlrbn_2" 4 68494;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE_N"
+o0000000003d83a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d71cd0_0 .net "D", 0 0, o0000000003d83a78;  0 drivers
+o0000000003d83ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d6ff70_0 .net "GATE_N", 0 0, o0000000003d83ad8;  0 drivers
+v0000000003d70330_0 .net "Q", 0 0, L_0000000004168a20;  1 drivers
+v0000000003d70970_0 .net "Q_N", 0 0, L_0000000004169350;  1 drivers
+o0000000003d83bc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d706f0_0 .net "RESET_B", 0 0, o0000000003d83bc8;  0 drivers
+L_00000000040bbb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d703d0_0 .net8 "VGND", 0 0, L_00000000040bbb40;  1 drivers, strength-aware
+L_00000000040bbbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d70470_0 .net8 "VNB", 0 0, L_00000000040bbbb0;  1 drivers, strength-aware
+L_00000000040ba100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d70790_0 .net8 "VPB", 0 0, L_00000000040ba100;  1 drivers, strength-aware
+L_00000000040ba170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d71af0_0 .net8 "VPWR", 0 0, L_00000000040ba170;  1 drivers, strength-aware
+S_0000000003d14130 .scope module, "base" "sky130_fd_sc_hd__dlrbn" 4 68514, 4 68840 1, S_00000000029c2730;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE_N"
+o0000000003d83bf8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169b30 .functor NOT 1, o0000000003d83bf8, C4<0>, C4<0>, C4<0>;
+o0000000003d83b08 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169ac0 .functor NOT 1, o0000000003d83b08, C4<0>, C4<0>, C4<0>;
+o0000000003d83aa8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ba4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bb670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169ba0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d83aa8, L_0000000004169ac0, L_0000000004169b30, v0000000003d71230_0, L_00000000040ba4f0, L_00000000040bb670;
+L_000000000416a4d0 .functor AND 1, L_0000000003f970a0, L_0000000003f964c0, C4<1>, C4<1>;
+L_0000000004168b00 .functor AND 1, L_0000000003f970a0, L_0000000003f955c0, C4<1>, C4<1>;
+L_0000000004168a20 .functor BUF 1, L_0000000004169ba0, C4<0>, C4<0>, C4<0>;
+L_0000000004169350 .functor NOT 1, L_0000000004169ba0, C4<0>, C4<0>, C4<0>;
+v0000000003d71ff0_0 .net "D", 0 0, o0000000003d83a78;  alias, 0 drivers
+v0000000003d70290_0 .net "D_delayed", 0 0, o0000000003d83aa8;  0 drivers
+v0000000003d6fcf0_0 .net "GATE_N", 0 0, o0000000003d83ad8;  alias, 0 drivers
+v0000000003d6fe30_0 .net "GATE_N_delayed", 0 0, o0000000003d83b08;  0 drivers
+v0000000003d6fed0_0 .net "Q", 0 0, L_0000000004168a20;  alias, 1 drivers
+v0000000003d705b0_0 .net "Q_N", 0 0, L_0000000004169350;  alias, 1 drivers
+v0000000003d70e70_0 .net "RESET", 0 0, L_0000000004169b30;  1 drivers
+v0000000003d71b90_0 .net "RESET_B", 0 0, o0000000003d83bc8;  alias, 0 drivers
+v0000000003d71050_0 .net "RESET_B_delayed", 0 0, o0000000003d83bf8;  0 drivers
+v0000000003d70650_0 .net8 "VGND", 0 0, L_00000000040bb670;  1 drivers, strength-aware
+L_00000000040ba5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d710f0_0 .net8 "VNB", 0 0, L_00000000040ba5d0;  1 drivers, strength-aware
+L_00000000040ba950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d70f10_0 .net8 "VPB", 0 0, L_00000000040ba950;  1 drivers, strength-aware
+v0000000003d712d0_0 .net8 "VPWR", 0 0, L_00000000040ba4f0;  1 drivers, strength-aware
+v0000000003d6fbb0_0 .net *"_s10", 0 0, L_0000000003f964c0;  1 drivers
+L_0000000004189fa0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d70ab0_0 .net/2u *"_s14", 0 0, L_0000000004189fa0;  1 drivers
+v0000000003d71190_0 .net *"_s16", 0 0, L_0000000003f955c0;  1 drivers
+L_0000000004189f10 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d71f50_0 .net/2u *"_s4", 0 0, L_0000000004189f10;  1 drivers
+L_0000000004189f58 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d71870_0 .net/2u *"_s8", 0 0, L_0000000004189f58;  1 drivers
+v0000000003d72090_0 .net "awake", 0 0, L_0000000003f970a0;  1 drivers
+v0000000003d6fa70_0 .net "buf_Q", 0 0, L_0000000004169ba0;  1 drivers
+v0000000003d71550_0 .net "cond0", 0 0, L_000000000416a4d0;  1 drivers
+v0000000003d714b0_0 .net "cond1", 0 0, L_0000000004168b00;  1 drivers
+v0000000003d70fb0_0 .net "intgate", 0 0, L_0000000004169ac0;  1 drivers
+v0000000003d71230_0 .var "notifier", 0 0;
+L_0000000003f970a0 .cmp/eeq 1, L_00000000040ba4f0, L_0000000004189f10;
+L_0000000003f964c0 .cmp/eeq 1, o0000000003d83bf8, L_0000000004189f58;
+L_0000000003f955c0 .cmp/eeq 1, o0000000003d83bc8, L_0000000004189fa0;
+S_00000000029c3db0 .scope module, "sky130_fd_sc_hd__dlrbp_1" "sky130_fd_sc_hd__dlrbp_1" 4 59598;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE"
+o0000000003d84198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d73850_0 .net "D", 0 0, o0000000003d84198;  0 drivers
+o0000000003d841f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d72e50_0 .net "GATE", 0 0, o0000000003d841f8;  0 drivers
+v0000000003d73990_0 .net "Q", 0 0, L_0000000004169580;  1 drivers
+v0000000003d73ad0_0 .net "Q_N", 0 0, L_00000000041693c0;  1 drivers
+o0000000003d842e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d733f0_0 .net "RESET_B", 0 0, o0000000003d842e8;  0 drivers
+L_00000000040baa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d73a30_0 .net8 "VGND", 0 0, L_00000000040baa30;  1 drivers, strength-aware
+L_00000000040bb3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d72590_0 .net8 "VNB", 0 0, L_00000000040bb3d0;  1 drivers, strength-aware
+L_00000000040bac60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d73710_0 .net8 "VPB", 0 0, L_00000000040bac60;  1 drivers, strength-aware
+L_00000000040bbc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d744d0_0 .net8 "VPWR", 0 0, L_00000000040bbc20;  1 drivers, strength-aware
+S_0000000003d15630 .scope module, "base" "sky130_fd_sc_hd__dlrbp" 4 59618, 4 59938 1, S_00000000029c3db0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE"
+o0000000003d84318 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a150 .functor NOT 1, o0000000003d84318, C4<0>, C4<0>, C4<0>;
+o0000000003d841c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d84228 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bad40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040ba3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416a380 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d841c8, o0000000003d84228, L_000000000416a150, v0000000003d72310_0, L_00000000040bad40, L_00000000040ba3a0;
+L_0000000004169a50 .functor AND 1, L_0000000003f969c0, L_0000000003f949e0, C4<1>, C4<1>;
+L_0000000004168e80 .functor AND 1, L_0000000003f969c0, L_0000000003f95700, C4<1>, C4<1>;
+L_0000000004169580 .functor BUF 1, L_000000000416a380, C4<0>, C4<0>, C4<0>;
+L_00000000041693c0 .functor NOT 1, L_000000000416a380, C4<0>, C4<0>, C4<0>;
+v0000000003d71410_0 .net "D", 0 0, o0000000003d84198;  alias, 0 drivers
+v0000000003d71d70_0 .net "D_delayed", 0 0, o0000000003d841c8;  0 drivers
+v0000000003d715f0_0 .net "GATE", 0 0, o0000000003d841f8;  alias, 0 drivers
+v0000000003d71690_0 .net "GATE_delayed", 0 0, o0000000003d84228;  0 drivers
+v0000000003d71730_0 .net "Q", 0 0, L_0000000004169580;  alias, 1 drivers
+v0000000003d71c30_0 .net "Q_N", 0 0, L_00000000041693c0;  alias, 1 drivers
+v0000000003d70510_0 .net "RESET", 0 0, L_000000000416a150;  1 drivers
+v0000000003d70830_0 .net "RESET_B", 0 0, o0000000003d842e8;  alias, 0 drivers
+v0000000003d70b50_0 .net "RESET_B_delayed", 0 0, o0000000003d84318;  0 drivers
+v0000000003d71e10_0 .net8 "VGND", 0 0, L_00000000040ba3a0;  1 drivers, strength-aware
+L_00000000040bbc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d71eb0_0 .net8 "VNB", 0 0, L_00000000040bbc90;  1 drivers, strength-aware
+L_00000000040ba250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d6f930_0 .net8 "VPB", 0 0, L_00000000040ba250;  1 drivers, strength-aware
+v0000000003d6f9d0_0 .net8 "VPWR", 0 0, L_00000000040bad40;  1 drivers, strength-aware
+v0000000003d6fb10_0 .net *"_s10", 0 0, L_0000000003f949e0;  1 drivers
+L_000000000418a078 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d74110_0 .net/2u *"_s14", 0 0, L_000000000418a078;  1 drivers
+v0000000003d72810_0 .net *"_s16", 0 0, L_0000000003f95700;  1 drivers
+L_0000000004189fe8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d73e90_0 .net/2u *"_s4", 0 0, L_0000000004189fe8;  1 drivers
+L_000000000418a030 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d73c10_0 .net/2u *"_s8", 0 0, L_000000000418a030;  1 drivers
+v0000000003d729f0_0 .net "awake", 0 0, L_0000000003f969c0;  1 drivers
+v0000000003d724f0_0 .net "buf_Q", 0 0, L_000000000416a380;  1 drivers
+v0000000003d728b0_0 .net "cond0", 0 0, L_0000000004169a50;  1 drivers
+v0000000003d72f90_0 .net "cond1", 0 0, L_0000000004168e80;  1 drivers
+v0000000003d72310_0 .var "notifier", 0 0;
+L_0000000003f969c0 .cmp/eeq 1, L_00000000040bad40, L_0000000004189fe8;
+L_0000000003f949e0 .cmp/eeq 1, o0000000003d84318, L_000000000418a030;
+L_0000000003f95700 .cmp/eeq 1, o0000000003d842e8, L_000000000418a078;
+S_00000000029c2d30 .scope module, "sky130_fd_sc_hd__dlrbp_2" "sky130_fd_sc_hd__dlrbp_2" 4 59479;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE"
+o0000000003d84888 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d73210_0 .net "D", 0 0, o0000000003d84888;  0 drivers
+o0000000003d848e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d74390_0 .net "GATE", 0 0, o0000000003d848e8;  0 drivers
+v0000000003d738f0_0 .net "Q", 0 0, L_0000000004168d30;  1 drivers
+v0000000003d73530_0 .net "Q_N", 0 0, L_0000000004168da0;  1 drivers
+o0000000003d849d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d732b0_0 .net "RESET_B", 0 0, o0000000003d849d8;  0 drivers
+L_00000000040bb6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d74250_0 .net8 "VGND", 0 0, L_00000000040bb6e0;  1 drivers, strength-aware
+L_00000000040ba2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d73350_0 .net8 "VNB", 0 0, L_00000000040ba2c0;  1 drivers, strength-aware
+L_00000000040bb8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d73f30_0 .net8 "VPB", 0 0, L_00000000040bb8a0;  1 drivers, strength-aware
+L_00000000040bb750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d742f0_0 .net8 "VPWR", 0 0, L_00000000040bb750;  1 drivers, strength-aware
+S_0000000003d151b0 .scope module, "base" "sky130_fd_sc_hd__dlrbp" 4 59499, 4 59938 1, S_00000000029c2d30;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "RESET_B"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "GATE"
+o0000000003d84a08 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a3f0 .functor NOT 1, o0000000003d84a08, C4<0>, C4<0>, C4<0>;
+o0000000003d848b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d84918 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bacd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bab10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041694a0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d848b8, o0000000003d84918, L_000000000416a3f0, v0000000003d73d50_0, L_00000000040bacd0, L_00000000040bab10;
+L_0000000004168e10 .functor AND 1, L_0000000003f96560, L_0000000003f95e80, C4<1>, C4<1>;
+L_0000000004168be0 .functor AND 1, L_0000000003f96560, L_0000000003f966a0, C4<1>, C4<1>;
+L_0000000004168d30 .functor BUF 1, L_00000000041694a0, C4<0>, C4<0>, C4<0>;
+L_0000000004168da0 .functor NOT 1, L_00000000041694a0, C4<0>, C4<0>, C4<0>;
+v0000000003d72130_0 .net "D", 0 0, o0000000003d84888;  alias, 0 drivers
+v0000000003d72db0_0 .net "D_delayed", 0 0, o0000000003d848b8;  0 drivers
+v0000000003d73490_0 .net "GATE", 0 0, o0000000003d848e8;  alias, 0 drivers
+v0000000003d73df0_0 .net "GATE_delayed", 0 0, o0000000003d84918;  0 drivers
+v0000000003d74570_0 .net "Q", 0 0, L_0000000004168d30;  alias, 1 drivers
+v0000000003d72ef0_0 .net "Q_N", 0 0, L_0000000004168da0;  alias, 1 drivers
+v0000000003d741b0_0 .net "RESET", 0 0, L_000000000416a3f0;  1 drivers
+v0000000003d72630_0 .net "RESET_B", 0 0, o0000000003d849d8;  alias, 0 drivers
+v0000000003d73b70_0 .net "RESET_B_delayed", 0 0, o0000000003d84a08;  0 drivers
+v0000000003d73030_0 .net8 "VGND", 0 0, L_00000000040bab10;  1 drivers, strength-aware
+L_00000000040ba640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d73cb0_0 .net8 "VNB", 0 0, L_00000000040ba640;  1 drivers, strength-aware
+L_00000000040bb910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d730d0_0 .net8 "VPB", 0 0, L_00000000040bb910;  1 drivers, strength-aware
+v0000000003d73670_0 .net8 "VPWR", 0 0, L_00000000040bacd0;  1 drivers, strength-aware
+v0000000003d735d0_0 .net *"_s10", 0 0, L_0000000003f95e80;  1 drivers
+L_000000000418a150 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d721d0_0 .net/2u *"_s14", 0 0, L_000000000418a150;  1 drivers
+v0000000003d726d0_0 .net *"_s16", 0 0, L_0000000003f966a0;  1 drivers
+L_000000000418a0c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d72950_0 .net/2u *"_s4", 0 0, L_000000000418a0c0;  1 drivers
+L_000000000418a108 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d73170_0 .net/2u *"_s8", 0 0, L_000000000418a108;  1 drivers
+v0000000003d72a90_0 .net "awake", 0 0, L_0000000003f96560;  1 drivers
+v0000000003d72d10_0 .net "buf_Q", 0 0, L_00000000041694a0;  1 drivers
+v0000000003d737b0_0 .net "cond0", 0 0, L_0000000004168e10;  1 drivers
+v0000000003d72b30_0 .net "cond1", 0 0, L_0000000004168be0;  1 drivers
+v0000000003d73d50_0 .var "notifier", 0 0;
+L_0000000003f96560 .cmp/eeq 1, L_00000000040bacd0, L_000000000418a0c0;
+L_0000000003f95e80 .cmp/eeq 1, o0000000003d84a08, L_000000000418a108;
+L_0000000003f966a0 .cmp/eeq 1, o0000000003d849d8, L_000000000418a150;
+S_00000000029c40b0 .scope module, "sky130_fd_sc_hd__dlrtn_1" "sky130_fd_sc_hd__dlrtn_1" 4 12374;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d84f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d74930_0 .net "D", 0 0, o0000000003d84f78;  0 drivers
+o0000000003d84fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d76230_0 .net "GATE_N", 0 0, o0000000003d84fd8;  0 drivers
+v0000000003d767d0_0 .net "Q", 0 0, L_000000000416a460;  1 drivers
+o0000000003d85098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d74bb0_0 .net "RESET_B", 0 0, o0000000003d85098;  0 drivers
+L_00000000040ba720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d74cf0_0 .net8 "VGND", 0 0, L_00000000040ba720;  1 drivers, strength-aware
+L_00000000040ba790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d76410_0 .net8 "VNB", 0 0, L_00000000040ba790;  1 drivers, strength-aware
+L_00000000040bb980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d75010_0 .net8 "VPB", 0 0, L_00000000040bb980;  1 drivers, strength-aware
+L_00000000040ba800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d76730_0 .net8 "VPWR", 0 0, L_00000000040ba800;  1 drivers, strength-aware
+S_0000000003d18930 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12392, 4 12703 1, S_00000000029c40b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d850c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169510 .functor NOT 1, o0000000003d850c8, C4<0>, C4<0>, C4<0>;
+o0000000003d85008 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169900 .functor NOT 1, o0000000003d85008, C4<0>, C4<0>, C4<0>;
+o0000000003d84fa8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ba9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bb1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169660 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d84fa8, L_0000000004169900, L_0000000004169510, v0000000003d76a50_0, L_00000000040ba9c0, L_00000000040bb1a0;
+L_0000000004169120 .functor AND 1, L_0000000003f94940, L_0000000003f96880, C4<1>, C4<1>;
+L_0000000004169970 .functor AND 1, L_0000000003f94940, L_0000000003f957a0, C4<1>, C4<1>;
+L_000000000416a460 .functor BUF 1, L_0000000004169660, C4<0>, C4<0>, C4<0>;
+v0000000003d72770_0 .net "D", 0 0, o0000000003d84f78;  alias, 0 drivers
+v0000000003d74750_0 .net "D_delayed", 0 0, o0000000003d84fa8;  0 drivers
+v0000000003d73fd0_0 .net "GATE_N", 0 0, o0000000003d84fd8;  alias, 0 drivers
+v0000000003d74070_0 .net "GATE_N_delayed", 0 0, o0000000003d85008;  0 drivers
+v0000000003d74430_0 .net "Q", 0 0, L_000000000416a460;  alias, 1 drivers
+v0000000003d72bd0_0 .net "RESET", 0 0, L_0000000004169510;  1 drivers
+v0000000003d74610_0 .net "RESET_B", 0 0, o0000000003d85098;  alias, 0 drivers
+v0000000003d746b0_0 .net "RESET_B_delayed", 0 0, o0000000003d850c8;  0 drivers
+v0000000003d72c70_0 .net8 "VGND", 0 0, L_00000000040bb1a0;  1 drivers, strength-aware
+L_00000000040ba870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d747f0_0 .net8 "VNB", 0 0, L_00000000040ba870;  1 drivers, strength-aware
+L_00000000040bb210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d74890_0 .net8 "VPB", 0 0, L_00000000040bb210;  1 drivers, strength-aware
+v0000000003d72270_0 .net8 "VPWR", 0 0, L_00000000040ba9c0;  1 drivers, strength-aware
+v0000000003d723b0_0 .net *"_s10", 0 0, L_0000000003f96880;  1 drivers
+L_000000000418a228 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d72450_0 .net/2u *"_s14", 0 0, L_000000000418a228;  1 drivers
+v0000000003d769b0_0 .net *"_s16", 0 0, L_0000000003f957a0;  1 drivers
+L_000000000418a198 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d74ed0_0 .net/2u *"_s4", 0 0, L_000000000418a198;  1 drivers
+L_000000000418a1e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d75a10_0 .net/2u *"_s8", 0 0, L_000000000418a1e0;  1 drivers
+v0000000003d760f0_0 .net "awake", 0 0, L_0000000003f94940;  1 drivers
+v0000000003d75bf0_0 .net "buf_Q", 0 0, L_0000000004169660;  1 drivers
+v0000000003d758d0_0 .net "cond0", 0 0, L_0000000004169120;  1 drivers
+v0000000003d75f10_0 .net "cond1", 0 0, L_0000000004169970;  1 drivers
+v0000000003d765f0_0 .net "intgate", 0 0, L_0000000004169900;  1 drivers
+v0000000003d76a50_0 .var "notifier", 0 0;
+L_0000000003f94940 .cmp/eeq 1, L_00000000040ba9c0, L_000000000418a198;
+L_0000000003f96880 .cmp/eeq 1, o0000000003d850c8, L_000000000418a1e0;
+L_0000000003f957a0 .cmp/eeq 1, o0000000003d85098, L_000000000418a228;
+S_00000000029c28b0 .scope module, "sky130_fd_sc_hd__dlrtn_2" "sky130_fd_sc_hd__dlrtn_2" 4 12946;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d85608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d75970_0 .net "D", 0 0, o0000000003d85608;  0 drivers
+o0000000003d85668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d75dd0_0 .net "GATE_N", 0 0, o0000000003d85668;  0 drivers
+v0000000003d75e70_0 .net "Q", 0 0, L_00000000041689b0;  1 drivers
+o0000000003d85728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d74d90_0 .net "RESET_B", 0 0, o0000000003d85728;  0 drivers
+L_00000000040badb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d764b0_0 .net8 "VGND", 0 0, L_00000000040badb0;  1 drivers, strength-aware
+L_00000000040bae90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d75510_0 .net8 "VNB", 0 0, L_00000000040bae90;  1 drivers, strength-aware
+L_00000000040bc8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d74e30_0 .net8 "VPB", 0 0, L_00000000040bc8d0;  1 drivers, strength-aware
+L_00000000040bd3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d76910_0 .net8 "VPWR", 0 0, L_00000000040bd3c0;  1 drivers, strength-aware
+S_0000000003d13530 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12964, 4 12703 1, S_00000000029c28b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d85758 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169c10 .functor NOT 1, o0000000003d85758, C4<0>, C4<0>, C4<0>;
+o0000000003d85698 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041699e0 .functor NOT 1, o0000000003d85698, C4<0>, C4<0>, C4<0>;
+o0000000003d85638 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bd740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bd6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004169cf0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d85638, L_00000000041699e0, L_0000000004169c10, v0000000003d76af0_0, L_00000000040bd740, L_00000000040bd6d0;
+L_0000000004168940 .functor AND 1, L_0000000003f953e0, L_0000000003f96920, C4<1>, C4<1>;
+L_0000000004168a90 .functor AND 1, L_0000000003f953e0, L_0000000003f96c40, C4<1>, C4<1>;
+L_00000000041689b0 .functor BUF 1, L_0000000004169cf0, C4<0>, C4<0>, C4<0>;
+v0000000003d74b10_0 .net "D", 0 0, o0000000003d85608;  alias, 0 drivers
+v0000000003d76050_0 .net "D_delayed", 0 0, o0000000003d85638;  0 drivers
+v0000000003d75650_0 .net "GATE_N", 0 0, o0000000003d85668;  alias, 0 drivers
+v0000000003d76190_0 .net "GATE_N_delayed", 0 0, o0000000003d85698;  0 drivers
+v0000000003d756f0_0 .net "Q", 0 0, L_00000000041689b0;  alias, 1 drivers
+v0000000003d75c90_0 .net "RESET", 0 0, L_0000000004169c10;  1 drivers
+v0000000003d76eb0_0 .net "RESET_B", 0 0, o0000000003d85728;  alias, 0 drivers
+v0000000003d76f50_0 .net "RESET_B_delayed", 0 0, o0000000003d85758;  0 drivers
+v0000000003d75790_0 .net8 "VGND", 0 0, L_00000000040bd6d0;  1 drivers, strength-aware
+L_00000000040bbd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d76cd0_0 .net8 "VNB", 0 0, L_00000000040bbd00;  1 drivers, strength-aware
+L_00000000040bc010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d76870_0 .net8 "VPB", 0 0, L_00000000040bc010;  1 drivers, strength-aware
+v0000000003d749d0_0 .net8 "VPWR", 0 0, L_00000000040bd740;  1 drivers, strength-aware
+v0000000003d76690_0 .net *"_s10", 0 0, L_0000000003f96920;  1 drivers
+L_000000000418a300 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d75ab0_0 .net/2u *"_s14", 0 0, L_000000000418a300;  1 drivers
+v0000000003d74c50_0 .net *"_s16", 0 0, L_0000000003f96c40;  1 drivers
+L_000000000418a270 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d762d0_0 .net/2u *"_s4", 0 0, L_000000000418a270;  1 drivers
+L_000000000418a2b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d755b0_0 .net/2u *"_s8", 0 0, L_000000000418a2b8;  1 drivers
+v0000000003d75d30_0 .net "awake", 0 0, L_0000000003f953e0;  1 drivers
+v0000000003d76550_0 .net "buf_Q", 0 0, L_0000000004169cf0;  1 drivers
+v0000000003d75b50_0 .net "cond0", 0 0, L_0000000004168940;  1 drivers
+v0000000003d76370_0 .net "cond1", 0 0, L_0000000004168a90;  1 drivers
+v0000000003d75830_0 .net "intgate", 0 0, L_00000000041699e0;  1 drivers
+v0000000003d76af0_0 .var "notifier", 0 0;
+L_0000000003f953e0 .cmp/eeq 1, L_00000000040bd740, L_000000000418a270;
+L_0000000003f96920 .cmp/eeq 1, o0000000003d85758, L_000000000418a2b8;
+L_0000000003f96c40 .cmp/eeq 1, o0000000003d85728, L_000000000418a300;
+S_00000000029c37b0 .scope module, "sky130_fd_sc_hd__dlrtn_4" "sky130_fd_sc_hd__dlrtn_4" 4 12834;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d85c98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d78d50_0 .net "D", 0 0, o0000000003d85c98;  0 drivers
+o0000000003d85cf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d78df0_0 .net "GATE_N", 0 0, o0000000003d85cf8;  0 drivers
+v0000000003d78a30_0 .net "Q", 0 0, L_0000000004169eb0;  1 drivers
+o0000000003d85db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d797f0_0 .net "RESET_B", 0 0, o0000000003d85db8;  0 drivers
+L_00000000040bc1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d78ad0_0 .net8 "VGND", 0 0, L_00000000040bc1d0;  1 drivers, strength-aware
+L_00000000040bc400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d794d0_0 .net8 "VNB", 0 0, L_00000000040bc400;  1 drivers, strength-aware
+L_00000000040bd7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d78fd0_0 .net8 "VPB", 0 0, L_00000000040bd7b0;  1 drivers, strength-aware
+L_00000000040bd2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d77630_0 .net8 "VPWR", 0 0, L_00000000040bd2e0;  1 drivers, strength-aware
+S_0000000003d160b0 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12852, 4 12703 1, S_00000000029c37b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d85de8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004168ef0 .functor NOT 1, o0000000003d85de8, C4<0>, C4<0>, C4<0>;
+o0000000003d85d28 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004169d60 .functor NOT 1, o0000000003d85d28, C4<0>, C4<0>, C4<0>;
+o0000000003d85cc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bd820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bc320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004168b70 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d85cc8, L_0000000004169d60, L_0000000004168ef0, v0000000003d79070_0, L_00000000040bd820, L_00000000040bc320;
+L_0000000004169dd0 .functor AND 1, L_0000000003f95fc0, L_0000000003f96b00, C4<1>, C4<1>;
+L_0000000004169e40 .functor AND 1, L_0000000003f95fc0, L_0000000003f96060, C4<1>, C4<1>;
+L_0000000004169eb0 .functor BUF 1, L_0000000004168b70, C4<0>, C4<0>, C4<0>;
+v0000000003d76b90_0 .net "D", 0 0, o0000000003d85c98;  alias, 0 drivers
+v0000000003d76c30_0 .net "D_delayed", 0 0, o0000000003d85cc8;  0 drivers
+v0000000003d74f70_0 .net "GATE_N", 0 0, o0000000003d85cf8;  alias, 0 drivers
+v0000000003d76d70_0 .net "GATE_N_delayed", 0 0, o0000000003d85d28;  0 drivers
+v0000000003d76e10_0 .net "Q", 0 0, L_0000000004169eb0;  alias, 1 drivers
+v0000000003d75fb0_0 .net "RESET", 0 0, L_0000000004168ef0;  1 drivers
+v0000000003d76ff0_0 .net "RESET_B", 0 0, o0000000003d85db8;  alias, 0 drivers
+v0000000003d77090_0 .net "RESET_B_delayed", 0 0, o0000000003d85de8;  0 drivers
+v0000000003d74a70_0 .net8 "VGND", 0 0, L_00000000040bc320;  1 drivers, strength-aware
+L_00000000040bd270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d750b0_0 .net8 "VNB", 0 0, L_00000000040bd270;  1 drivers, strength-aware
+L_00000000040bcc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d75150_0 .net8 "VPB", 0 0, L_00000000040bcc50;  1 drivers, strength-aware
+v0000000003d751f0_0 .net8 "VPWR", 0 0, L_00000000040bd820;  1 drivers, strength-aware
+v0000000003d75290_0 .net *"_s10", 0 0, L_0000000003f96b00;  1 drivers
+L_000000000418a3d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d75330_0 .net/2u *"_s14", 0 0, L_000000000418a3d8;  1 drivers
+v0000000003d753d0_0 .net *"_s16", 0 0, L_0000000003f96060;  1 drivers
+L_000000000418a348 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d75470_0 .net/2u *"_s4", 0 0, L_000000000418a348;  1 drivers
+L_000000000418a390 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d782b0_0 .net/2u *"_s8", 0 0, L_000000000418a390;  1 drivers
+v0000000003d77ef0_0 .net "awake", 0 0, L_0000000003f95fc0;  1 drivers
+v0000000003d77db0_0 .net "buf_Q", 0 0, L_0000000004168b70;  1 drivers
+v0000000003d78990_0 .net "cond0", 0 0, L_0000000004169dd0;  1 drivers
+v0000000003d79750_0 .net "cond1", 0 0, L_0000000004169e40;  1 drivers
+v0000000003d79610_0 .net "intgate", 0 0, L_0000000004169d60;  1 drivers
+v0000000003d79070_0 .var "notifier", 0 0;
+L_0000000003f95fc0 .cmp/eeq 1, L_00000000040bd820, L_000000000418a348;
+L_0000000003f96b00 .cmp/eeq 1, o0000000003d85de8, L_000000000418a390;
+L_0000000003f96060 .cmp/eeq 1, o0000000003d85db8, L_000000000418a3d8;
+S_00000000029c2a30 .scope module, "sky130_fd_sc_hd__dlrtp_1" "sky130_fd_sc_hd__dlrtp_1" 4 58879;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d86328 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d79250_0 .net "D", 0 0, o0000000003d86328;  0 drivers
+o0000000003d86388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d771d0_0 .net "GATE", 0 0, o0000000003d86388;  0 drivers
+v0000000003d792f0_0 .net "Q", 0 0, L_0000000004169190;  1 drivers
+o0000000003d86448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d78530_0 .net "RESET_B", 0 0, o0000000003d86448;  0 drivers
+L_00000000040bd120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d78c10_0 .net8 "VGND", 0 0, L_00000000040bd120;  1 drivers, strength-aware
+L_00000000040bc080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d77270_0 .net8 "VNB", 0 0, L_00000000040bc080;  1 drivers, strength-aware
+L_00000000040bc0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d79390_0 .net8 "VPB", 0 0, L_00000000040bc0f0;  1 drivers, strength-aware
+L_00000000040bca90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d79430_0 .net8 "VPWR", 0 0, L_00000000040bca90;  1 drivers, strength-aware
+S_0000000003d17d30 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58897, 4 58749 1, S_00000000029c2a30;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d86478 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004168fd0 .functor NOT 1, o0000000003d86478, C4<0>, C4<0>, C4<0>;
+o0000000003d86358 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d863b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bd190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bd430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000041690b0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d86358, o0000000003d863b8, L_0000000004168fd0, v0000000003d78490_0, L_00000000040bd190, L_00000000040bd430;
+L_0000000004169f20 .functor AND 1, L_0000000003f94f80, L_0000000003f96100, C4<1>, C4<1>;
+L_0000000004169f90 .functor AND 1, L_0000000003f94f80, L_0000000003f96240, C4<1>, C4<1>;
+L_0000000004169190 .functor BUF 1, L_00000000041690b0, C4<0>, C4<0>, C4<0>;
+v0000000003d78e90_0 .net "D", 0 0, o0000000003d86328;  alias, 0 drivers
+v0000000003d79890_0 .net "D_delayed", 0 0, o0000000003d86358;  0 drivers
+v0000000003d77810_0 .net "GATE", 0 0, o0000000003d86388;  alias, 0 drivers
+v0000000003d774f0_0 .net "GATE_delayed", 0 0, o0000000003d863b8;  0 drivers
+v0000000003d778b0_0 .net "Q", 0 0, L_0000000004169190;  alias, 1 drivers
+v0000000003d77590_0 .net "RESET", 0 0, L_0000000004168fd0;  1 drivers
+v0000000003d78f30_0 .net "RESET_B", 0 0, o0000000003d86448;  alias, 0 drivers
+v0000000003d78350_0 .net "RESET_B_delayed", 0 0, o0000000003d86478;  0 drivers
+v0000000003d77310_0 .net8 "VGND", 0 0, L_00000000040bd430;  1 drivers, strength-aware
+L_00000000040bd040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d78850_0 .net8 "VNB", 0 0, L_00000000040bd040;  1 drivers, strength-aware
+L_00000000040bd890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d78cb0_0 .net8 "VPB", 0 0, L_00000000040bd890;  1 drivers, strength-aware
+v0000000003d77c70_0 .net8 "VPWR", 0 0, L_00000000040bd190;  1 drivers, strength-aware
+v0000000003d78b70_0 .net *"_s10", 0 0, L_0000000003f96100;  1 drivers
+L_000000000418a4b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d77f90_0 .net/2u *"_s14", 0 0, L_000000000418a4b0;  1 drivers
+v0000000003d783f0_0 .net *"_s16", 0 0, L_0000000003f96240;  1 drivers
+L_000000000418a420 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d796b0_0 .net/2u *"_s4", 0 0, L_000000000418a420;  1 drivers
+L_000000000418a468 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d776d0_0 .net/2u *"_s8", 0 0, L_000000000418a468;  1 drivers
+v0000000003d79570_0 .net "awake", 0 0, L_0000000003f94f80;  1 drivers
+v0000000003d79110_0 .net "buf_Q", 0 0, L_00000000041690b0;  1 drivers
+v0000000003d77130_0 .net "cond0", 0 0, L_0000000004169f20;  1 drivers
+v0000000003d791b0_0 .net "cond1", 0 0, L_0000000004169f90;  1 drivers
+v0000000003d78490_0 .var "notifier", 0 0;
+L_0000000003f94f80 .cmp/eeq 1, L_00000000040bd190, L_000000000418a420;
+L_0000000003f96100 .cmp/eeq 1, o0000000003d86478, L_000000000418a468;
+L_0000000003f96240 .cmp/eeq 1, o0000000003d86448, L_000000000418a4b0;
+S_00000000029c3f30 .scope module, "sky130_fd_sc_hd__dlrtp_2" "sky130_fd_sc_hd__dlrtp_2" 4 58308;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d86988 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d7bcd0_0 .net "D", 0 0, o0000000003d86988;  0 drivers
+o0000000003d869e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d7a150_0 .net "GATE", 0 0, o0000000003d869e8;  0 drivers
+v0000000003d7a650_0 .net "Q", 0 0, L_000000000416ad90;  1 drivers
+o0000000003d86aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d79ed0_0 .net "RESET_B", 0 0, o0000000003d86aa8;  0 drivers
+L_00000000040bca20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7beb0_0 .net8 "VGND", 0 0, L_00000000040bca20;  1 drivers, strength-aware
+L_00000000040bc4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7bd70_0 .net8 "VNB", 0 0, L_00000000040bc4e0;  1 drivers, strength-aware
+L_00000000040bc6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d7b730_0 .net8 "VPB", 0 0, L_00000000040bc6a0;  1 drivers, strength-aware
+L_00000000040bd4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d7b910_0 .net8 "VPWR", 0 0, L_00000000040bd4a0;  1 drivers, strength-aware
+S_0000000003d154b0 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58326, 4 58749 1, S_00000000029c3f30;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d86ad8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a8c0 .functor NOT 1, o0000000003d86ad8, C4<0>, C4<0>, C4<0>;
+o0000000003d869b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d86a18 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bcf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bc630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416b2d0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d869b8, o0000000003d86a18, L_000000000416a8c0, v0000000003d7bb90_0, L_00000000040bcf60, L_00000000040bc630;
+L_000000000416a770 .functor AND 1, L_0000000003f962e0, L_0000000003f985e0, C4<1>, C4<1>;
+L_000000000416b3b0 .functor AND 1, L_0000000003f962e0, L_0000000003f97f00, C4<1>, C4<1>;
+L_000000000416ad90 .functor BUF 1, L_000000000416b2d0, C4<0>, C4<0>, C4<0>;
+v0000000003d785d0_0 .net "D", 0 0, o0000000003d86988;  alias, 0 drivers
+v0000000003d773b0_0 .net "D_delayed", 0 0, o0000000003d869b8;  0 drivers
+v0000000003d77d10_0 .net "GATE", 0 0, o0000000003d869e8;  alias, 0 drivers
+v0000000003d78670_0 .net "GATE_delayed", 0 0, o0000000003d86a18;  0 drivers
+v0000000003d78170_0 .net "Q", 0 0, L_000000000416ad90;  alias, 1 drivers
+v0000000003d77950_0 .net "RESET", 0 0, L_000000000416a8c0;  1 drivers
+v0000000003d77e50_0 .net "RESET_B", 0 0, o0000000003d86aa8;  alias, 0 drivers
+v0000000003d78710_0 .net "RESET_B_delayed", 0 0, o0000000003d86ad8;  0 drivers
+v0000000003d779f0_0 .net8 "VGND", 0 0, L_00000000040bc630;  1 drivers, strength-aware
+L_00000000040bc390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d787b0_0 .net8 "VNB", 0 0, L_00000000040bc390;  1 drivers, strength-aware
+L_00000000040bd510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d77450_0 .net8 "VPB", 0 0, L_00000000040bd510;  1 drivers, strength-aware
+v0000000003d78030_0 .net8 "VPWR", 0 0, L_00000000040bcf60;  1 drivers, strength-aware
+v0000000003d77770_0 .net *"_s10", 0 0, L_0000000003f985e0;  1 drivers
+L_000000000418a588 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d77a90_0 .net/2u *"_s14", 0 0, L_000000000418a588;  1 drivers
+v0000000003d77b30_0 .net *"_s16", 0 0, L_0000000003f97f00;  1 drivers
+L_000000000418a4f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d788f0_0 .net/2u *"_s4", 0 0, L_000000000418a4f8;  1 drivers
+L_000000000418a540 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d77bd0_0 .net/2u *"_s8", 0 0, L_000000000418a540;  1 drivers
+v0000000003d780d0_0 .net "awake", 0 0, L_0000000003f962e0;  1 drivers
+v0000000003d78210_0 .net "buf_Q", 0 0, L_000000000416b2d0;  1 drivers
+v0000000003d7ab50_0 .net "cond0", 0 0, L_000000000416a770;  1 drivers
+v0000000003d7b9b0_0 .net "cond1", 0 0, L_000000000416b3b0;  1 drivers
+v0000000003d7bb90_0 .var "notifier", 0 0;
+L_0000000003f962e0 .cmp/eeq 1, L_00000000040bcf60, L_000000000418a4f8;
+L_0000000003f985e0 .cmp/eeq 1, o0000000003d86ad8, L_000000000418a540;
+L_0000000003f97f00 .cmp/eeq 1, o0000000003d86aa8, L_000000000418a588;
+S_00000000029c34b0 .scope module, "sky130_fd_sc_hd__dlrtp_4" "sky130_fd_sc_hd__dlrtp_4" 4 58421;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d86fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d7ae70_0 .net "D", 0 0, o0000000003d86fe8;  0 drivers
+o0000000003d87048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d79b10_0 .net "GATE", 0 0, o0000000003d87048;  0 drivers
+v0000000003d7a290_0 .net "Q", 0 0, L_000000000416ae70;  1 drivers
+o0000000003d87108 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d7a970_0 .net "RESET_B", 0 0, o0000000003d87108;  0 drivers
+L_00000000040bc780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7baf0_0 .net8 "VGND", 0 0, L_00000000040bc780;  1 drivers, strength-aware
+L_00000000040bd350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7abf0_0 .net8 "VNB", 0 0, L_00000000040bd350;  1 drivers, strength-aware
+L_00000000040bc7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d7ad30_0 .net8 "VPB", 0 0, L_00000000040bc7f0;  1 drivers, strength-aware
+L_00000000040bce10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d7be10_0 .net8 "VPWR", 0 0, L_00000000040bce10;  1 drivers, strength-aware
+S_0000000003d172b0 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58439, 4 58749 1, S_00000000029c34b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "RESET_B"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d87138 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416a700 .functor NOT 1, o0000000003d87138, C4<0>, C4<0>, C4<0>;
+o0000000003d87018 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d87078 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bc710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bc470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416b7a0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o0000000003d87018, o0000000003d87078, L_000000000416a700, v0000000003d7ba50_0, L_00000000040bc710, L_00000000040bc470;
+L_000000000416ba40 .functor AND 1, L_0000000003f97460, L_0000000003f976e0, C4<1>, C4<1>;
+L_000000000416c060 .functor AND 1, L_0000000003f97460, L_0000000003f97d20, C4<1>, C4<1>;
+L_000000000416ae70 .functor BUF 1, L_000000000416b7a0, C4<0>, C4<0>, C4<0>;
+v0000000003d7ac90_0 .net "D", 0 0, o0000000003d86fe8;  alias, 0 drivers
+v0000000003d7bc30_0 .net "D_delayed", 0 0, o0000000003d87018;  0 drivers
+v0000000003d7b4b0_0 .net "GATE", 0 0, o0000000003d87048;  alias, 0 drivers
+v0000000003d79e30_0 .net "GATE_delayed", 0 0, o0000000003d87078;  0 drivers
+v0000000003d79f70_0 .net "Q", 0 0, L_000000000416ae70;  alias, 1 drivers
+v0000000003d7a010_0 .net "RESET", 0 0, L_000000000416a700;  1 drivers
+v0000000003d7a830_0 .net "RESET_B", 0 0, o0000000003d87108;  alias, 0 drivers
+v0000000003d7a510_0 .net "RESET_B_delayed", 0 0, o0000000003d87138;  0 drivers
+v0000000003d7af10_0 .net8 "VGND", 0 0, L_00000000040bc470;  1 drivers, strength-aware
+L_00000000040bc240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7a0b0_0 .net8 "VNB", 0 0, L_00000000040bc240;  1 drivers, strength-aware
+L_00000000040bc160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d7a6f0_0 .net8 "VPB", 0 0, L_00000000040bc160;  1 drivers, strength-aware
+v0000000003d7b7d0_0 .net8 "VPWR", 0 0, L_00000000040bc710;  1 drivers, strength-aware
+v0000000003d79cf0_0 .net *"_s10", 0 0, L_0000000003f976e0;  1 drivers
+L_000000000418a660 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d7b0f0_0 .net/2u *"_s14", 0 0, L_000000000418a660;  1 drivers
+v0000000003d7b690_0 .net *"_s16", 0 0, L_0000000003f97d20;  1 drivers
+L_000000000418a5d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d7a8d0_0 .net/2u *"_s4", 0 0, L_000000000418a5d0;  1 drivers
+L_000000000418a618 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003d7a790_0 .net/2u *"_s8", 0 0, L_000000000418a618;  1 drivers
+v0000000003d7b870_0 .net "awake", 0 0, L_0000000003f97460;  1 drivers
+v0000000003d7a1f0_0 .net "buf_Q", 0 0, L_000000000416b7a0;  1 drivers
+v0000000003d7b230_0 .net "cond0", 0 0, L_000000000416ba40;  1 drivers
+v0000000003d7b2d0_0 .net "cond1", 0 0, L_000000000416c060;  1 drivers
+v0000000003d7ba50_0 .var "notifier", 0 0;
+L_0000000003f97460 .cmp/eeq 1, L_00000000040bc710, L_000000000418a5d0;
+L_0000000003f976e0 .cmp/eeq 1, o0000000003d87138, L_000000000418a618;
+L_0000000003f97d20 .cmp/eeq 1, o0000000003d87108, L_000000000418a660;
+S_00000000029c31b0 .scope module, "sky130_fd_sc_hd__dlxbn_1" "sky130_fd_sc_hd__dlxbn_1" 4 67766;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d87648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d79d90_0 .net "D", 0 0, o0000000003d87648;  0 drivers
+o0000000003d876d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003d7b190_0 .net "GATE_N", 0 0, o0000000003d876d8;  0 drivers
+v0000000003d79bb0_0 .net "Q", 0 0, L_000000000416a540;  1 drivers
+v0000000003d7a5b0_0 .net "Q_N", 0 0, L_000000000416bce0;  1 drivers
+L_00000000040bcef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd3a10_0 .net8 "VGND", 0 0, L_00000000040bcef0;  1 drivers, strength-aware
+L_00000000040bc860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd45f0_0 .net8 "VNB", 0 0, L_00000000040bc860;  1 drivers, strength-aware
+L_00000000040bbd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4af0_0 .net8 "VPB", 0 0, L_00000000040bbd70;  1 drivers, strength-aware
+L_00000000040bbfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4410_0 .net8 "VPWR", 0 0, L_00000000040bbfa0;  1 drivers, strength-aware
+S_0000000003d169b0 .scope module, "base" "sky130_fd_sc_hd__dlxbn" 4 67784, 4 67641 1, S_00000000029c31b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d87708 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416b490 .functor NOT 1, o0000000003d87708, C4<0>, C4<0>, C4<0>;
+o0000000003d87678 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bd200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bd5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416c0d0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d87678, L_000000000416b490, v0000000003d7a470_0, L_00000000040bd200, L_00000000040bd5f0;
+L_000000000416a540 .functor BUF 1, L_000000000416c0d0, C4<0>, C4<0>, C4<0>;
+L_000000000416bce0 .functor NOT 1, L_000000000416c0d0, C4<0>, C4<0>, C4<0>;
+v0000000003d7aa10_0 .net "D", 0 0, o0000000003d87648;  alias, 0 drivers
+v0000000003d7b370_0 .net "D_delayed", 0 0, o0000000003d87678;  0 drivers
+v0000000003d7afb0_0 .net "GATE", 0 0, L_000000000416b490;  1 drivers
+v0000000003d7b410_0 .net "GATE_N", 0 0, o0000000003d876d8;  alias, 0 drivers
+v0000000003d79c50_0 .net "GATE_N_delayed", 0 0, o0000000003d87708;  0 drivers
+v0000000003d7b550_0 .net "Q", 0 0, L_000000000416a540;  alias, 1 drivers
+v0000000003d7bf50_0 .net "Q_N", 0 0, L_000000000416bce0;  alias, 1 drivers
+v0000000003d7a330_0 .net8 "VGND", 0 0, L_00000000040bd5f0;  1 drivers, strength-aware
+L_00000000040bbde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003d7b5f0_0 .net8 "VNB", 0 0, L_00000000040bbde0;  1 drivers, strength-aware
+L_00000000040bc940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003d79930_0 .net8 "VPB", 0 0, L_00000000040bc940;  1 drivers, strength-aware
+v0000000003d7aab0_0 .net8 "VPWR", 0 0, L_00000000040bd200;  1 drivers, strength-aware
+v0000000003d7add0_0 .net *"_s4", 31 0, L_0000000003f99620;  1 drivers
+L_000000000418a6a8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000000003d7a3d0_0 .net *"_s7", 30 0, L_000000000418a6a8;  1 drivers
+L_000000000418a6f0 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000000003d799d0_0 .net/2u *"_s8", 31 0, L_000000000418a6f0;  1 drivers
+v0000000003d79a70_0 .net "awake", 0 0, L_0000000003f98b80;  1 drivers
+v0000000003d7b050_0 .net "buf_Q", 0 0, L_000000000416c0d0;  1 drivers
+v0000000003d7a470_0 .var "notifier", 0 0;
+L_0000000003f99620 .concat [ 1 31 0 0], L_00000000040bd200, L_000000000418a6a8;
+L_0000000003f98b80 .cmp/eeq 32, L_0000000003f99620, L_000000000418a6f0;
+S_00000000029c3930 .scope module, "sky130_fd_sc_hd__dlxbn_2" "sky130_fd_sc_hd__dlxbn_2" 4 67878;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d87bb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd3d30_0 .net "D", 0 0, o0000000003d87bb8;  0 drivers
+o0000000003d87c48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd4730_0 .net "GATE_N", 0 0, o0000000003d87c48;  0 drivers
+v0000000003dd40f0_0 .net "Q", 0 0, L_000000000416a930;  1 drivers
+v0000000003dd3470_0 .net "Q_N", 0 0, L_000000000416b030;  1 drivers
+L_00000000040bbec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd44b0_0 .net8 "VGND", 0 0, L_00000000040bbec0;  1 drivers, strength-aware
+L_00000000040bd580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd3970_0 .net8 "VNB", 0 0, L_00000000040bd580;  1 drivers, strength-aware
+L_00000000040bd660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd49b0_0 .net8 "VPB", 0 0, L_00000000040bd660;  1 drivers, strength-aware
+L_00000000040bc9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd47d0_0 .net8 "VPWR", 0 0, L_00000000040bc9b0;  1 drivers, strength-aware
+S_0000000003d16530 .scope module, "base" "sky130_fd_sc_hd__dlxbn" 4 67896, 4 67641 1, S_00000000029c3930;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE_N"
+o0000000003d87c78 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416b960 .functor NOT 1, o0000000003d87c78, C4<0>, C4<0>, C4<0>;
+o0000000003d87be8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bbe50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bc2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416a5b0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d87be8, L_000000000416b960, v0000000003dd4690_0, L_00000000040bbe50, L_00000000040bc2b0;
+L_000000000416a930 .functor BUF 1, L_000000000416a5b0, C4<0>, C4<0>, C4<0>;
+L_000000000416b030 .functor NOT 1, L_000000000416a5b0, C4<0>, C4<0>, C4<0>;
+v0000000003dd42d0_0 .net "D", 0 0, o0000000003d87bb8;  alias, 0 drivers
+v0000000003dd4e10_0 .net "D_delayed", 0 0, o0000000003d87be8;  0 drivers
+v0000000003dd3dd0_0 .net "GATE", 0 0, L_000000000416b960;  1 drivers
+v0000000003dd3790_0 .net "GATE_N", 0 0, o0000000003d87c48;  alias, 0 drivers
+v0000000003dd3150_0 .net "GATE_N_delayed", 0 0, o0000000003d87c78;  0 drivers
+v0000000003dd3e70_0 .net "Q", 0 0, L_000000000416a930;  alias, 1 drivers
+v0000000003dd4eb0_0 .net "Q_N", 0 0, L_000000000416b030;  alias, 1 drivers
+v0000000003dd4cd0_0 .net8 "VGND", 0 0, L_00000000040bc2b0;  1 drivers, strength-aware
+L_00000000040bce80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4f50_0 .net8 "VNB", 0 0, L_00000000040bce80;  1 drivers, strength-aware
+L_00000000040bcb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4b90_0 .net8 "VPB", 0 0, L_00000000040bcb00;  1 drivers, strength-aware
+v0000000003dd3f10_0 .net8 "VPWR", 0 0, L_00000000040bbe50;  1 drivers, strength-aware
+v0000000003dd51d0_0 .net *"_s4", 31 0, L_0000000003f98040;  1 drivers
+L_000000000418a738 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4c30_0 .net *"_s7", 30 0, L_000000000418a738;  1 drivers
+L_000000000418a780 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4a50_0 .net/2u *"_s8", 31 0, L_000000000418a780;  1 drivers
+v0000000003dd4d70_0 .net "awake", 0 0, L_0000000003f97be0;  1 drivers
+v0000000003dd3fb0_0 .net "buf_Q", 0 0, L_000000000416a5b0;  1 drivers
+v0000000003dd4690_0 .var "notifier", 0 0;
+L_0000000003f98040 .concat [ 1 31 0 0], L_00000000040bbe50, L_000000000418a738;
+L_0000000003f97be0 .cmp/eeq 32, L_0000000003f98040, L_000000000418a780;
+S_00000000029c3ab0 .scope module, "sky130_fd_sc_hd__dlxbp_1" "sky130_fd_sc_hd__dlxbp_1" 4 43581;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d88128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd5130_0 .net "D", 0 0, o0000000003d88128;  0 drivers
+o0000000003d88188 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd58b0_0 .net "GATE", 0 0, o0000000003d88188;  0 drivers
+v0000000003dd3c90_0 .net "Q", 0 0, L_000000000416b810;  1 drivers
+v0000000003dd5270_0 .net "Q_N", 0 0, L_000000000416a7e0;  1 drivers
+L_00000000040bc550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4910_0 .net8 "VGND", 0 0, L_00000000040bc550;  1 drivers, strength-aware
+L_00000000040bbf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd53b0_0 .net8 "VNB", 0 0, L_00000000040bbf30;  1 drivers, strength-aware
+L_00000000040bc5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd5770_0 .net8 "VPB", 0 0, L_00000000040bc5c0;  1 drivers, strength-aware
+L_00000000040bccc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd5450_0 .net8 "VPWR", 0 0, L_00000000040bccc0;  1 drivers, strength-aware
+S_0000000003d17430 .scope module, "base" "sky130_fd_sc_hd__dlxbp" 4 43599, 4 43895 1, S_00000000029c3ab0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "GATE"
+o0000000003d88158 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d881b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bcda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bcb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416bab0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d88158, o0000000003d881b8, v0000000003dd3830_0, L_00000000040bcda0, L_00000000040bcb70;
+L_000000000416b810 .functor BUF 1, L_000000000416bab0, C4<0>, C4<0>, C4<0>;
+L_000000000416a7e0 .functor NOT 1, L_000000000416bab0, C4<0>, C4<0>, C4<0>;
+v0000000003dd4ff0_0 .net "D", 0 0, o0000000003d88128;  alias, 0 drivers
+v0000000003dd4050_0 .net "D_delayed", 0 0, o0000000003d88158;  0 drivers
+v0000000003dd5090_0 .net "GATE", 0 0, o0000000003d88188;  alias, 0 drivers
+v0000000003dd4190_0 .net "GATE_delayed", 0 0, o0000000003d881b8;  0 drivers
+v0000000003dd5630_0 .net "Q", 0 0, L_000000000416b810;  alias, 1 drivers
+v0000000003dd5310_0 .net "Q_N", 0 0, L_000000000416a7e0;  alias, 1 drivers
+v0000000003dd54f0_0 .net8 "VGND", 0 0, L_00000000040bcb70;  1 drivers, strength-aware
+L_00000000040bcbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4230_0 .net8 "VNB", 0 0, L_00000000040bcbe0;  1 drivers, strength-aware
+L_00000000040bcd30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4870_0 .net8 "VPB", 0 0, L_00000000040bcd30;  1 drivers, strength-aware
+v0000000003dd56d0_0 .net8 "VPWR", 0 0, L_00000000040bcda0;  1 drivers, strength-aware
+L_000000000418a7c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dd4370_0 .net/2u *"_s4", 0 0, L_000000000418a7c8;  1 drivers
+v0000000003dd33d0_0 .net "awake", 0 0, L_0000000003f97140;  1 drivers
+v0000000003dd4550_0 .net "buf_Q", 0 0, L_000000000416bab0;  1 drivers
+v0000000003dd3830_0 .var "notifier", 0 0;
+L_0000000003f97140 .cmp/eeq 1, L_00000000040bcda0, L_000000000418a7c8;
+S_00000000029c3030 .scope module, "sky130_fd_sc_hd__dlxtn_1" "sky130_fd_sc_hd__dlxtn_1" 4 26941;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d88608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd80b0_0 .net "D", 0 0, o0000000003d88608;  0 drivers
+o0000000003d88698 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd6490_0 .net "GATE_N", 0 0, o0000000003d88698;  0 drivers
+v0000000003dd7570_0 .net "Q", 0 0, L_000000000416a690;  1 drivers
+L_00000000040bd0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6f30_0 .net8 "VGND", 0 0, L_00000000040bd0b0;  1 drivers, strength-aware
+L_00000000040bcfd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6d50_0 .net8 "VNB", 0 0, L_00000000040bcfd0;  1 drivers, strength-aware
+L_00000000040befc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7d90_0 .net8 "VPB", 0 0, L_00000000040befc0;  1 drivers, strength-aware
+L_00000000040bf2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6ad0_0 .net8 "VPWR", 0 0, L_00000000040bf2d0;  1 drivers, strength-aware
+S_0000000003d13e30 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 26957, 4 26717 1, S_00000000029c3030;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d886c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416aaf0 .functor NOT 1, o0000000003d886c8, C4<0>, C4<0>, C4<0>;
+o0000000003d88638 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bddd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bd900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416a620 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d88638, L_000000000416aaf0, v0000000003dd74d0_0, L_00000000040bddd0, L_00000000040bd900;
+L_000000000416a690 .functor BUF 1, L_000000000416a620, C4<0>, C4<0>, C4<0>;
+v0000000003dd5590_0 .net "D", 0 0, o0000000003d88608;  alias, 0 drivers
+v0000000003dd3ab0_0 .net "D_delayed", 0 0, o0000000003d88638;  0 drivers
+v0000000003dd5810_0 .net "GATE", 0 0, L_000000000416aaf0;  1 drivers
+v0000000003dd31f0_0 .net "GATE_N", 0 0, o0000000003d88698;  alias, 0 drivers
+v0000000003dd3290_0 .net "GATE_N_delayed", 0 0, o0000000003d886c8;  0 drivers
+v0000000003dd3330_0 .net "Q", 0 0, L_000000000416a690;  alias, 1 drivers
+v0000000003dd3510_0 .net8 "VGND", 0 0, L_00000000040bd900;  1 drivers, strength-aware
+L_00000000040bdc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd35b0_0 .net8 "VNB", 0 0, L_00000000040bdc10;  1 drivers, strength-aware
+L_00000000040bf340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd3650_0 .net8 "VPB", 0 0, L_00000000040bf340;  1 drivers, strength-aware
+v0000000003dd36f0_0 .net8 "VPWR", 0 0, L_00000000040bddd0;  1 drivers, strength-aware
+L_000000000418a810 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dd38d0_0 .net/2u *"_s4", 0 0, L_000000000418a810;  1 drivers
+v0000000003dd3b50_0 .net "awake", 0 0, L_0000000003f996c0;  1 drivers
+v0000000003dd3bf0_0 .net "buf_Q", 0 0, L_000000000416a620;  1 drivers
+v0000000003dd74d0_0 .var "notifier", 0 0;
+L_0000000003f996c0 .cmp/eeq 1, L_00000000040bddd0, L_000000000418a810;
+S_00000000029c2bb0 .scope module, "sky130_fd_sc_hd__dlxtn_2" "sky130_fd_sc_hd__dlxtn_2" 4 26835;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d88a88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd6e90_0 .net "D", 0 0, o0000000003d88a88;  0 drivers
+o0000000003d88b18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd5c70_0 .net "GATE_N", 0 0, o0000000003d88b18;  0 drivers
+v0000000003dd7610_0 .net "Q", 0 0, L_000000000416bb20;  1 drivers
+L_00000000040be000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6fd0_0 .net8 "VGND", 0 0, L_00000000040be000;  1 drivers, strength-aware
+L_00000000040bf3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7890_0 .net8 "VNB", 0 0, L_00000000040bf3b0;  1 drivers, strength-aware
+L_00000000040beee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7070_0 .net8 "VPB", 0 0, L_00000000040beee0;  1 drivers, strength-aware
+L_00000000040bdf20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6b70_0 .net8 "VPWR", 0 0, L_00000000040bdf20;  1 drivers, strength-aware
+S_0000000003d13fb0 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 26851, 4 26717 1, S_00000000029c2bb0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d88b48 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416ab60 .functor NOT 1, o0000000003d88b48, C4<0>, C4<0>, C4<0>;
+o0000000003d88ab8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040bed20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bee70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416a850 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d88ab8, L_000000000416ab60, v0000000003dd6a30_0, L_00000000040bed20, L_00000000040bee70;
+L_000000000416bb20 .functor BUF 1, L_000000000416a850, C4<0>, C4<0>, C4<0>;
+v0000000003dd68f0_0 .net "D", 0 0, o0000000003d88a88;  alias, 0 drivers
+v0000000003dd6df0_0 .net "D_delayed", 0 0, o0000000003d88ab8;  0 drivers
+v0000000003dd79d0_0 .net "GATE", 0 0, L_000000000416ab60;  1 drivers
+v0000000003dd67b0_0 .net "GATE_N", 0 0, o0000000003d88b18;  alias, 0 drivers
+v0000000003dd7930_0 .net "GATE_N_delayed", 0 0, o0000000003d88b48;  0 drivers
+v0000000003dd6c10_0 .net "Q", 0 0, L_000000000416bb20;  alias, 1 drivers
+v0000000003dd6cb0_0 .net8 "VGND", 0 0, L_00000000040bee70;  1 drivers, strength-aware
+L_00000000040be850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd77f0_0 .net8 "VNB", 0 0, L_00000000040be850;  1 drivers, strength-aware
+L_00000000040bf420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6990_0 .net8 "VPB", 0 0, L_00000000040bf420;  1 drivers, strength-aware
+v0000000003dd6850_0 .net8 "VPWR", 0 0, L_00000000040bed20;  1 drivers, strength-aware
+L_000000000418a858 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7110_0 .net/2u *"_s4", 0 0, L_000000000418a858;  1 drivers
+v0000000003dd7e30_0 .net "awake", 0 0, L_0000000003f97c80;  1 drivers
+v0000000003dd6710_0 .net "buf_Q", 0 0, L_000000000416a850;  1 drivers
+v0000000003dd6a30_0 .var "notifier", 0 0;
+L_0000000003f97c80 .cmp/eeq 1, L_00000000040bed20, L_000000000418a858;
+S_00000000029c3630 .scope module, "sky130_fd_sc_hd__dlxtn_4" "sky130_fd_sc_hd__dlxtn_4" 4 27047;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d88f08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd6670_0 .net "D", 0 0, o0000000003d88f08;  0 drivers
+o0000000003d88f98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd7cf0_0 .net "GATE_N", 0 0, o0000000003d88f98;  0 drivers
+v0000000003dd7b10_0 .net "Q", 0 0, L_000000000416b9d0;  1 drivers
+L_00000000040bdc80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7bb0_0 .net8 "VGND", 0 0, L_00000000040bdc80;  1 drivers, strength-aware
+L_00000000040bdcf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7c50_0 .net8 "VNB", 0 0, L_00000000040bdcf0;  1 drivers, strength-aware
+L_00000000040be690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd5b30_0 .net8 "VPB", 0 0, L_00000000040be690;  1 drivers, strength-aware
+L_00000000040bf030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd7f70_0 .net8 "VPWR", 0 0, L_00000000040bf030;  1 drivers, strength-aware
+S_0000000003d14430 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 27063, 4 26717 1, S_00000000029c3630;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE_N"
+o0000000003d88fc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416b8f0 .functor NOT 1, o0000000003d88fc8, C4<0>, C4<0>, C4<0>;
+o0000000003d88f38 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040be620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bec40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416bb90 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d88f38, L_000000000416b8f0, v0000000003dd7a70_0, L_00000000040be620, L_00000000040bec40;
+L_000000000416b9d0 .functor BUF 1, L_000000000416bb90, C4<0>, C4<0>, C4<0>;
+v0000000003dd7ed0_0 .net "D", 0 0, o0000000003d88f08;  alias, 0 drivers
+v0000000003dd6530_0 .net "D_delayed", 0 0, o0000000003d88f38;  0 drivers
+v0000000003dd7750_0 .net "GATE", 0 0, L_000000000416b8f0;  1 drivers
+v0000000003dd60d0_0 .net "GATE_N", 0 0, o0000000003d88f98;  alias, 0 drivers
+v0000000003dd71b0_0 .net "GATE_N_delayed", 0 0, o0000000003d88fc8;  0 drivers
+v0000000003dd76b0_0 .net "Q", 0 0, L_000000000416b9d0;  alias, 1 drivers
+v0000000003dd7250_0 .net8 "VGND", 0 0, L_00000000040bec40;  1 drivers, strength-aware
+L_00000000040bf490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd62b0_0 .net8 "VNB", 0 0, L_00000000040bf490;  1 drivers, strength-aware
+L_00000000040bed90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6170_0 .net8 "VPB", 0 0, L_00000000040bed90;  1 drivers, strength-aware
+v0000000003dd72f0_0 .net8 "VPWR", 0 0, L_00000000040be620;  1 drivers, strength-aware
+L_000000000418a8a0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6210_0 .net/2u *"_s4", 0 0, L_000000000418a8a0;  1 drivers
+v0000000003dd7390_0 .net "awake", 0 0, L_0000000003f97fa0;  1 drivers
+v0000000003dd7430_0 .net "buf_Q", 0 0, L_000000000416bb90;  1 drivers
+v0000000003dd7a70_0 .var "notifier", 0 0;
+L_0000000003f97fa0 .cmp/eeq 1, L_00000000040be620, L_000000000418a8a0;
+S_00000000029c4d40 .scope module, "sky130_fd_sc_hd__dlxtp_1" "sky130_fd_sc_hd__dlxtp_1" 4 92369;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE"
+o0000000003d89388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd63f0_0 .net "D", 0 0, o0000000003d89388;  0 drivers
+o0000000003d893e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd9690_0 .net "GATE", 0 0, o0000000003d893e8;  0 drivers
+v0000000003dda4f0_0 .net "Q", 0 0, L_000000000416b340;  1 drivers
+L_00000000040be0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd95f0_0 .net8 "VGND", 0 0, L_00000000040be0e0;  1 drivers, strength-aware
+L_00000000040be2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dda1d0_0 .net8 "VNB", 0 0, L_00000000040be2a0;  1 drivers, strength-aware
+L_00000000040bf0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9f50_0 .net8 "VPB", 0 0, L_00000000040bf0a0;  1 drivers, strength-aware
+L_00000000040be230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9d70_0 .net8 "VPWR", 0 0, L_00000000040be230;  1 drivers, strength-aware
+S_0000000003d17730 .scope module, "base" "sky130_fd_sc_hd__dlxtp" 4 92385, 4 92671 1, S_00000000029c4d40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "GATE"
+o0000000003d893b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d89418 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040be380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040bdf90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416ae00 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003d893b8, o0000000003d89418, v0000000003dd5f90_0, L_00000000040be380, L_00000000040bdf90;
+L_000000000416b340 .functor BUF 1, L_000000000416ae00, C4<0>, C4<0>, C4<0>;
+v0000000003dd8010_0 .net "D", 0 0, o0000000003d89388;  alias, 0 drivers
+v0000000003dd5950_0 .net "D_delayed", 0 0, o0000000003d893b8;  0 drivers
+v0000000003dd59f0_0 .net "GATE", 0 0, o0000000003d893e8;  alias, 0 drivers
+v0000000003dd5a90_0 .net "GATE_delayed", 0 0, o0000000003d89418;  0 drivers
+v0000000003dd65d0_0 .net "Q", 0 0, L_000000000416b340;  alias, 1 drivers
+v0000000003dd5bd0_0 .net8 "VGND", 0 0, L_00000000040bdf90;  1 drivers, strength-aware
+L_00000000040bf110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd5d10_0 .net8 "VNB", 0 0, L_00000000040bf110;  1 drivers, strength-aware
+L_00000000040beb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd6030_0 .net8 "VPB", 0 0, L_00000000040beb60;  1 drivers, strength-aware
+v0000000003dd5db0_0 .net8 "VPWR", 0 0, L_00000000040be380;  1 drivers, strength-aware
+L_000000000418a8e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dd5e50_0 .net/2u *"_s4", 0 0, L_000000000418a8e8;  1 drivers
+v0000000003dd5ef0_0 .net "awake", 0 0, L_0000000003f97e60;  1 drivers
+v0000000003dd6350_0 .net "buf_Q", 0 0, L_000000000416ae00;  1 drivers
+v0000000003dd5f90_0 .var "notifier", 0 0;
+L_0000000003f97e60 .cmp/eeq 1, L_00000000040be380, L_000000000418a8e8;
+S_00000000029c60c0 .scope module, "sky130_fd_sc_hd__dlygate4sd1_1" "sky130_fd_sc_hd__dlygate4sd1_1" 4 88901;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d897d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd9e10_0 .net "A", 0 0, o0000000003d897d8;  0 drivers
+L_00000000040bef50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd85b0_0 .net8 "VGND", 0 0, L_00000000040bef50;  1 drivers, strength-aware
+L_00000000040be3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dda310_0 .net8 "VNB", 0 0, L_00000000040be3f0;  1 drivers, strength-aware
+L_00000000040bea10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8f10_0 .net8 "VPB", 0 0, L_00000000040bea10;  1 drivers, strength-aware
+L_00000000040be070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9230_0 .net8 "VPWR", 0 0, L_00000000040be070;  1 drivers, strength-aware
+v0000000003dda3b0_0 .net "X", 0 0, L_000000000416bdc0;  1 drivers
+S_0000000003d14bb0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd1" 4 88915, 4 89189 1, S_00000000029c60c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416bd50 .functor BUF 1, o0000000003d897d8, C4<0>, C4<0>, C4<0>;
+L_000000000416bdc0 .functor BUF 1, L_000000000416bd50, C4<0>, C4<0>, C4<0>;
+v0000000003dd9cd0_0 .net "A", 0 0, o0000000003d897d8;  alias, 0 drivers
+L_00000000040bde40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9550_0 .net8 "VGND", 0 0, L_00000000040bde40;  1 drivers, strength-aware
+L_00000000040be150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dda270_0 .net8 "VNB", 0 0, L_00000000040be150;  1 drivers, strength-aware
+L_00000000040bd970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8fb0_0 .net8 "VPB", 0 0, L_00000000040bd970;  1 drivers, strength-aware
+L_00000000040bd9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda130_0 .net8 "VPWR", 0 0, L_00000000040bd9e0;  1 drivers, strength-aware
+v0000000003dd9410_0 .net "X", 0 0, L_000000000416bdc0;  alias, 1 drivers
+v0000000003dd94b0_0 .net "buf0_out_X", 0 0, L_000000000416bd50;  1 drivers
+S_00000000029c57c0 .scope module, "sky130_fd_sc_hd__dlygate4sd2_1" "sky130_fd_sc_hd__dlygate4sd2_1" 4 33428;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d89aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dda810_0 .net "A", 0 0, o0000000003d89aa8;  0 drivers
+L_00000000040be540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8970_0 .net8 "VGND", 0 0, L_00000000040be540;  1 drivers, strength-aware
+L_00000000040bea80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8510_0 .net8 "VNB", 0 0, L_00000000040bea80;  1 drivers, strength-aware
+L_00000000040be1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd86f0_0 .net8 "VPB", 0 0, L_00000000040be1c0;  1 drivers, strength-aware
+L_00000000040bda50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8790_0 .net8 "VPWR", 0 0, L_00000000040bda50;  1 drivers, strength-aware
+v0000000003dd8dd0_0 .net "X", 0 0, L_000000000416a9a0;  1 drivers
+S_0000000003d157b0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd2" 4 33442, 4 33322 1, S_00000000029c57c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416bc00 .functor BUF 1, o0000000003d89aa8, C4<0>, C4<0>, C4<0>;
+L_000000000416a9a0 .functor BUF 1, L_000000000416bc00, C4<0>, C4<0>, C4<0>;
+v0000000003dd83d0_0 .net "A", 0 0, o0000000003d89aa8;  alias, 0 drivers
+L_00000000040bdac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8830_0 .net8 "VGND", 0 0, L_00000000040bdac0;  1 drivers, strength-aware
+L_00000000040be460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8650_0 .net8 "VNB", 0 0, L_00000000040be460;  1 drivers, strength-aware
+L_00000000040be310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9050_0 .net8 "VPB", 0 0, L_00000000040be310;  1 drivers, strength-aware
+L_00000000040bf180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9a50_0 .net8 "VPWR", 0 0, L_00000000040bf180;  1 drivers, strength-aware
+v0000000003dd9ff0_0 .net "X", 0 0, L_000000000416a9a0;  alias, 1 drivers
+v0000000003dd88d0_0 .net "buf0_out_X", 0 0, L_000000000416bc00;  1 drivers
+S_00000000029c5dc0 .scope module, "sky130_fd_sc_hd__dlygate4sd3_1" "sky130_fd_sc_hd__dlygate4sd3_1" 4 56297;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d89d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dda8b0_0 .net "A", 0 0, o0000000003d89d78;  0 drivers
+L_00000000040be4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd92d0_0 .net8 "VGND", 0 0, L_00000000040be4d0;  1 drivers, strength-aware
+L_00000000040bebd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8330_0 .net8 "VNB", 0 0, L_00000000040bebd0;  1 drivers, strength-aware
+L_00000000040becb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8150_0 .net8 "VPB", 0 0, L_00000000040becb0;  1 drivers, strength-aware
+L_00000000040be5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8e70_0 .net8 "VPWR", 0 0, L_00000000040be5b0;  1 drivers, strength-aware
+v0000000003dd9eb0_0 .net "X", 0 0, L_000000000416be30;  1 drivers
+S_0000000003d145b0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd3" 4 56311, 4 56191 1, S_00000000029c5dc0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416b420 .functor BUF 1, o0000000003d89d78, C4<0>, C4<0>, C4<0>;
+L_000000000416be30 .functor BUF 1, L_000000000416b420, C4<0>, C4<0>, C4<0>;
+v0000000003dd8a10_0 .net "A", 0 0, o0000000003d89d78;  alias, 0 drivers
+L_00000000040be700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9730_0 .net8 "VGND", 0 0, L_00000000040be700;  1 drivers, strength-aware
+L_00000000040bf1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd81f0_0 .net8 "VNB", 0 0, L_00000000040bf1f0;  1 drivers, strength-aware
+L_00000000040bf260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda6d0_0 .net8 "VPB", 0 0, L_00000000040bf260;  1 drivers, strength-aware
+L_00000000040bdb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda770_0 .net8 "VPWR", 0 0, L_00000000040bdb30;  1 drivers, strength-aware
+v0000000003dd97d0_0 .net "X", 0 0, L_000000000416be30;  alias, 1 drivers
+v0000000003dda590_0 .net "buf0_out_X", 0 0, L_000000000416b420;  1 drivers
+S_00000000029c63c0 .scope module, "sky130_fd_sc_hd__dlymetal6s2s_1" "sky130_fd_sc_hd__dlymetal6s2s_1" 4 84134;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d8a048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dd8b50_0 .net "A", 0 0, o0000000003d8a048;  0 drivers
+L_00000000040beaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8bf0_0 .net8 "VGND", 0 0, L_00000000040beaf0;  1 drivers, strength-aware
+L_00000000040bdba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9370_0 .net8 "VNB", 0 0, L_00000000040bdba0;  1 drivers, strength-aware
+L_00000000040bdd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8c90_0 .net8 "VPB", 0 0, L_00000000040bdd60;  1 drivers, strength-aware
+L_00000000040bdeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd99b0_0 .net8 "VPWR", 0 0, L_00000000040bdeb0;  1 drivers, strength-aware
+v0000000003dd8470_0 .net "X", 0 0, L_000000000416aa10;  1 drivers
+S_0000000003d15ab0 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s2s" 4 84148, 4 84427 1, S_00000000029c63c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416bea0 .functor BUF 1, o0000000003d8a048, C4<0>, C4<0>, C4<0>;
+L_000000000416aa10 .functor BUF 1, L_000000000416bea0, C4<0>, C4<0>, C4<0>;
+v0000000003dd8290_0 .net "A", 0 0, o0000000003d8a048;  alias, 0 drivers
+L_00000000040be770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8ab0_0 .net8 "VGND", 0 0, L_00000000040be770;  1 drivers, strength-aware
+L_00000000040be7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd8d30_0 .net8 "VNB", 0 0, L_00000000040be7e0;  1 drivers, strength-aware
+L_00000000040be8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd90f0_0 .net8 "VPB", 0 0, L_00000000040be8c0;  1 drivers, strength-aware
+L_00000000040be930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9190_0 .net8 "VPWR", 0 0, L_00000000040be930;  1 drivers, strength-aware
+v0000000003dd9870_0 .net "X", 0 0, L_000000000416aa10;  alias, 1 drivers
+v0000000003dd9910_0 .net "buf0_out_X", 0 0, L_000000000416bea0;  1 drivers
+S_00000000029c5340 .scope module, "sky130_fd_sc_hd__dlymetal6s4s_1" "sky130_fd_sc_hd__dlymetal6s4s_1" 4 9683;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d8a318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddcb10_0 .net "A", 0 0, o0000000003d8a318;  0 drivers
+L_00000000040be9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc570_0 .net8 "VGND", 0 0, L_00000000040be9a0;  1 drivers, strength-aware
+L_00000000040bee00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddbe90_0 .net8 "VNB", 0 0, L_00000000040bee00;  1 drivers, strength-aware
+L_00000000040c0610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddce30_0 .net8 "VPB", 0 0, L_00000000040c0610;  1 drivers, strength-aware
+L_00000000040bf9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddbad0_0 .net8 "VPWR", 0 0, L_00000000040bf9d0;  1 drivers, strength-aware
+v0000000003ddabd0_0 .net "X", 0 0, L_000000000416abd0;  1 drivers
+S_0000000003d16230 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s4s" 4 9697, 4 9576 1, S_00000000029c5340;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416aa80 .functor BUF 1, o0000000003d8a318, C4<0>, C4<0>, C4<0>;
+L_000000000416abd0 .functor BUF 1, L_000000000416aa80, C4<0>, C4<0>, C4<0>;
+v0000000003dda090_0 .net "A", 0 0, o0000000003d8a318;  alias, 0 drivers
+L_00000000040c1020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dda630_0 .net8 "VGND", 0 0, L_00000000040c1020;  1 drivers, strength-aware
+L_00000000040bf730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9af0_0 .net8 "VNB", 0 0, L_00000000040bf730;  1 drivers, strength-aware
+L_00000000040c1090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dd9b90_0 .net8 "VPB", 0 0, L_00000000040c1090;  1 drivers, strength-aware
+L_00000000040c08b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda450_0 .net8 "VPWR", 0 0, L_00000000040c08b0;  1 drivers, strength-aware
+v0000000003dd9c30_0 .net "X", 0 0, L_000000000416abd0;  alias, 1 drivers
+v0000000003ddb990_0 .net "buf0_out_X", 0 0, L_000000000416aa80;  1 drivers
+S_00000000029c5ac0 .scope module, "sky130_fd_sc_hd__dlymetal6s6s_1" "sky130_fd_sc_hd__dlymetal6s6s_1" 4 73072;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d8a5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddc6b0_0 .net "A", 0 0, o0000000003d8a5e8;  0 drivers
+L_00000000040c0300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddaef0_0 .net8 "VGND", 0 0, L_00000000040c0300;  1 drivers, strength-aware
+L_00000000040c0ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddcf70_0 .net8 "VNB", 0 0, L_00000000040c0ae0;  1 drivers, strength-aware
+L_00000000040c0140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc390_0 .net8 "VPB", 0 0, L_00000000040c0140;  1 drivers, strength-aware
+L_00000000040bf8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb490_0 .net8 "VPWR", 0 0, L_00000000040bf8f0;  1 drivers, strength-aware
+v0000000003ddc750_0 .net "X", 0 0, L_000000000416ac40;  1 drivers
+S_0000000003d16cb0 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s6s" 4 73086, 4 72965 1, S_00000000029c5ac0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416b0a0 .functor BUF 1, o0000000003d8a5e8, C4<0>, C4<0>, C4<0>;
+L_000000000416ac40 .functor BUF 1, L_000000000416b0a0, C4<0>, C4<0>, C4<0>;
+v0000000003ddac70_0 .net "A", 0 0, o0000000003d8a5e8;  alias, 0 drivers
+L_00000000040bf880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddca70_0 .net8 "VGND", 0 0, L_00000000040bf880;  1 drivers, strength-aware
+L_00000000040bfa40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddaa90_0 .net8 "VNB", 0 0, L_00000000040bfa40;  1 drivers, strength-aware
+L_00000000040bf810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc7f0_0 .net8 "VPB", 0 0, L_00000000040bf810;  1 drivers, strength-aware
+L_00000000040bff10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc610_0 .net8 "VPWR", 0 0, L_00000000040bff10;  1 drivers, strength-aware
+v0000000003ddc250_0 .net "X", 0 0, L_000000000416ac40;  alias, 1 drivers
+v0000000003ddc890_0 .net "buf0_out_X", 0 0, L_000000000416b0a0;  1 drivers
+S_00000000029c5640 .scope module, "sky130_fd_sc_hd__ebufn_1" "sky130_fd_sc_hd__ebufn_1" 4 48128;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8a8b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddbcb0_0 .net "A", 0 0, o0000000003d8a8b8;  0 drivers
+o0000000003d8a8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddbb70_0 .net "TE_B", 0 0, o0000000003d8a8e8;  0 drivers
+L_00000000040c0ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc1b0_0 .net8 "VGND", 0 0, L_00000000040c0ed0;  1 drivers, strength-aware
+L_00000000040c0e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc4d0_0 .net8 "VNB", 0 0, L_00000000040c0e60;  1 drivers, strength-aware
+L_00000000040c0f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddad10_0 .net8 "VPB", 0 0, L_00000000040c0f40;  1 drivers, strength-aware
+L_00000000040c0fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddcd90_0 .net8 "VPWR", 0 0, L_00000000040c0fb0;  1 drivers, strength-aware
+v0000000003ddb210_0 .net8 "Z", 0 0, L_000000000416b500;  1 drivers, strength-aware
+S_0000000003d16fb0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 48144, 4 48021 1, S_00000000029c5640;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b500 .functor BUFIF0 1, o0000000003d8a8b8, o0000000003d8a8e8, C4<0>, C4<0>;
+v0000000003ddae50_0 .net "A", 0 0, o0000000003d8a8b8;  alias, 0 drivers
+v0000000003ddcbb0_0 .net "TE_B", 0 0, o0000000003d8a8e8;  alias, 0 drivers
+L_00000000040bfc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddced0_0 .net8 "VGND", 0 0, L_00000000040bfc00;  1 drivers, strength-aware
+L_00000000040c05a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddcc50_0 .net8 "VNB", 0 0, L_00000000040c05a0;  1 drivers, strength-aware
+L_00000000040c0920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddccf0_0 .net8 "VPB", 0 0, L_00000000040c0920;  1 drivers, strength-aware
+L_00000000040bfc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddadb0_0 .net8 "VPWR", 0 0, L_00000000040bfc70;  1 drivers, strength-aware
+v0000000003ddd010_0 .net8 "Z", 0 0, L_000000000416b500;  alias, 1 drivers, strength-aware
+S_00000000029c48c0 .scope module, "sky130_fd_sc_hd__ebufn_2" "sky130_fd_sc_hd__ebufn_2" 4 47728;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8abe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddbd50_0 .net "A", 0 0, o0000000003d8abe8;  0 drivers
+o0000000003d8ac18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddc9d0_0 .net "TE_B", 0 0, o0000000003d8ac18;  0 drivers
+L_00000000040bf6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb030_0 .net8 "VGND", 0 0, L_00000000040bf6c0;  1 drivers, strength-aware
+L_00000000040c0a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddbdf0_0 .net8 "VNB", 0 0, L_00000000040c0a70;  1 drivers, strength-aware
+L_00000000040bf500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda9f0_0 .net8 "VPB", 0 0, L_00000000040bf500;  1 drivers, strength-aware
+L_00000000040c0370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddab30_0 .net8 "VPWR", 0 0, L_00000000040c0370;  1 drivers, strength-aware
+v0000000003ddb7b0_0 .net8 "Z", 0 0, L_000000000416b570;  1 drivers, strength-aware
+S_0000000003d175b0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47744, 4 48021 1, S_00000000029c48c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b570 .functor BUFIF0 1, o0000000003d8abe8, o0000000003d8ac18, C4<0>, C4<0>;
+v0000000003ddc930_0 .net "A", 0 0, o0000000003d8abe8;  alias, 0 drivers
+v0000000003ddc2f0_0 .net "TE_B", 0 0, o0000000003d8ac18;  alias, 0 drivers
+L_00000000040bfab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddd0b0_0 .net8 "VGND", 0 0, L_00000000040bfab0;  1 drivers, strength-aware
+L_00000000040c0450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddaf90_0 .net8 "VNB", 0 0, L_00000000040c0450;  1 drivers, strength-aware
+L_00000000040bfb20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dda950_0 .net8 "VPB", 0 0, L_00000000040bfb20;  1 drivers, strength-aware
+L_00000000040c00d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddc430_0 .net8 "VPWR", 0 0, L_00000000040c00d0;  1 drivers, strength-aware
+v0000000003ddb530_0 .net8 "Z", 0 0, L_000000000416b570;  alias, 1 drivers, strength-aware
+S_00000000029c4bc0 .scope module, "sky130_fd_sc_hd__ebufn_4" "sky130_fd_sc_hd__ebufn_4" 4 47622;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8af18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddb670_0 .net "A", 0 0, o0000000003d8af18;  0 drivers
+o0000000003d8af48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddb710_0 .net "TE_B", 0 0, o0000000003d8af48;  0 drivers
+L_00000000040bf7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb850_0 .net8 "VGND", 0 0, L_00000000040bf7a0;  1 drivers, strength-aware
+L_00000000040c03e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddba30_0 .net8 "VNB", 0 0, L_00000000040c03e0;  1 drivers, strength-aware
+L_00000000040bfe30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddbc10_0 .net8 "VPB", 0 0, L_00000000040bfe30;  1 drivers, strength-aware
+L_00000000040c0990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddbf30_0 .net8 "VPWR", 0 0, L_00000000040c0990;  1 drivers, strength-aware
+v0000000003ddbfd0_0 .net8 "Z", 0 0, L_000000000416acb0;  1 drivers, strength-aware
+S_0000000003d14730 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47638, 4 48021 1, S_00000000029c4bc0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416acb0 .functor BUFIF0 1, o0000000003d8af18, o0000000003d8af48, C4<0>, C4<0>;
+v0000000003ddb0d0_0 .net "A", 0 0, o0000000003d8af18;  alias, 0 drivers
+v0000000003ddb170_0 .net "TE_B", 0 0, o0000000003d8af48;  alias, 0 drivers
+L_00000000040c04c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb8f0_0 .net8 "VGND", 0 0, L_00000000040c04c0;  1 drivers, strength-aware
+L_00000000040bfd50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb2b0_0 .net8 "VNB", 0 0, L_00000000040bfd50;  1 drivers, strength-aware
+L_00000000040bf650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb350_0 .net8 "VPB", 0 0, L_00000000040bf650;  1 drivers, strength-aware
+L_00000000040c0c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddb3f0_0 .net8 "VPWR", 0 0, L_00000000040c0c30;  1 drivers, strength-aware
+v0000000003ddb5d0_0 .net8 "Z", 0 0, L_000000000416acb0;  alias, 1 drivers, strength-aware
+S_00000000029c5c40 .scope module, "sky130_fd_sc_hd__ebufn_8" "sky130_fd_sc_hd__ebufn_8" 4 47516;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8b248 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddf8b0_0 .net "A", 0 0, o0000000003d8b248;  0 drivers
+o0000000003d8b278 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddf090_0 .net "TE_B", 0 0, o0000000003d8b278;  0 drivers
+L_00000000040bfea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddf810_0 .net8 "VGND", 0 0, L_00000000040bfea0;  1 drivers, strength-aware
+L_00000000040c0060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dde2d0_0 .net8 "VNB", 0 0, L_00000000040c0060;  1 drivers, strength-aware
+L_00000000040c0530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dddd30_0 .net8 "VPB", 0 0, L_00000000040c0530;  1 drivers, strength-aware
+L_00000000040c0a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddea50_0 .net8 "VPWR", 0 0, L_00000000040c0a00;  1 drivers, strength-aware
+v0000000003ddf1d0_0 .net8 "Z", 0 0, L_000000000416ad20;  1 drivers, strength-aware
+S_0000000003d136b0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47532, 4 48021 1, S_00000000029c5c40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416ad20 .functor BUFIF0 1, o0000000003d8b248, o0000000003d8b278, C4<0>, C4<0>;
+v0000000003ddc070_0 .net "A", 0 0, o0000000003d8b248;  alias, 0 drivers
+v0000000003ddc110_0 .net "TE_B", 0 0, o0000000003d8b278;  alias, 0 drivers
+L_00000000040bf570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddd970_0 .net8 "VGND", 0 0, L_00000000040bf570;  1 drivers, strength-aware
+L_00000000040bfb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dde9b0_0 .net8 "VNB", 0 0, L_00000000040bfb90;  1 drivers, strength-aware
+L_00000000040c01b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dddf10_0 .net8 "VPB", 0 0, L_00000000040c01b0;  1 drivers, strength-aware
+L_00000000040c0680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dde410_0 .net8 "VPWR", 0 0, L_00000000040c0680;  1 drivers, strength-aware
+v0000000003ddf6d0_0 .net8 "Z", 0 0, L_000000000416ad20;  alias, 1 drivers, strength-aware
+S_00000000029c5940 .scope module, "sky130_fd_sc_hd__edfxbp_1" "sky130_fd_sc_hd__edfxbp_1" 4 19397;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+o0000000003d8b578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dde230_0 .net "CLK", 0 0, o0000000003d8b578;  0 drivers
+o0000000003d8b5d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dde370_0 .net "D", 0 0, o0000000003d8b5d8;  0 drivers
+o0000000003d8b608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddeeb0_0 .net "DE", 0 0, o0000000003d8b608;  0 drivers
+v0000000003dde4b0_0 .net "Q", 0 0, L_000000000416b6c0;  1 drivers
+v0000000003ddf270_0 .net "Q_N", 0 0, L_000000000416b730;  1 drivers
+L_00000000040bf5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddeb90_0 .net8 "VGND", 0 0, L_00000000040bf5e0;  1 drivers, strength-aware
+L_00000000040c0ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dddab0_0 .net8 "VNB", 0 0, L_00000000040c0ca0;  1 drivers, strength-aware
+L_00000000040bfce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dde870_0 .net8 "VPB", 0 0, L_00000000040bfce0;  1 drivers, strength-aware
+L_00000000040c0b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dde730_0 .net8 "VPWR", 0 0, L_00000000040c0b50;  1 drivers, strength-aware
+S_0000000003d178b0 .scope module, "base" "sky130_fd_sc_hd__edfxbp" 4 19417, 4 19264 1, S_00000000029c5940;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+o0000000003d8b668 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d8b638 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416aee0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000416b5e0, o0000000003d8b668, o0000000003d8b638;
+o0000000003d8b5a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040c0220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040c06f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416b5e0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000416aee0, o0000000003d8b5a8, v0000000003dde190_0, L_00000000040c0220, L_00000000040c06f0;
+L_000000000416b650 .functor AND 1, L_0000000003f97780, L_0000000003f97640, C4<1>, C4<1>;
+L_000000000416b6c0 .functor BUF 1, L_000000000416b5e0, C4<0>, C4<0>, C4<0>;
+L_000000000416b730 .functor NOT 1, L_000000000416b5e0, C4<0>, C4<0>, C4<0>;
+v0000000003ddeaf0_0 .net "CLK", 0 0, o0000000003d8b578;  alias, 0 drivers
+v0000000003ddd150_0 .net "CLK_delayed", 0 0, o0000000003d8b5a8;  0 drivers
+v0000000003ddd5b0_0 .net "D", 0 0, o0000000003d8b5d8;  alias, 0 drivers
+v0000000003ddddd0_0 .net "DE", 0 0, o0000000003d8b608;  alias, 0 drivers
+v0000000003ddde70_0 .net "DE_delayed", 0 0, o0000000003d8b638;  0 drivers
+v0000000003dde050_0 .net "D_delayed", 0 0, o0000000003d8b668;  0 drivers
+v0000000003ddd830_0 .net "Q", 0 0, L_000000000416b6c0;  alias, 1 drivers
+v0000000003ddd650_0 .net "Q_N", 0 0, L_000000000416b730;  alias, 1 drivers
+v0000000003ddd470_0 .net8 "VGND", 0 0, L_00000000040c06f0;  1 drivers, strength-aware
+L_00000000040c0760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddf770_0 .net8 "VNB", 0 0, L_00000000040c0760;  1 drivers, strength-aware
+L_00000000040c0df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dddfb0_0 .net8 "VPB", 0 0, L_00000000040c0df0;  1 drivers, strength-aware
+v0000000003ddd510_0 .net8 "VPWR", 0 0, L_00000000040c0220;  1 drivers, strength-aware
+v0000000003ddf130_0 .net *"_s10", 0 0, L_0000000003f97640;  1 drivers
+L_000000000418a930 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003dde0f0_0 .net/2u *"_s4", 0 0, L_000000000418a930;  1 drivers
+L_000000000418a978 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003ddd6f0_0 .net/2u *"_s8", 0 0, L_000000000418a978;  1 drivers
+v0000000003dde690_0 .net "awake", 0 0, L_0000000003f97780;  1 drivers
+v0000000003ddda10_0 .net "buf_Q", 0 0, L_000000000416b5e0;  1 drivers
+v0000000003dde5f0_0 .net "cond0", 0 0, L_000000000416b650;  1 drivers
+v0000000003ddeff0_0 .net "mux_out", 0 0, L_000000000416aee0;  1 drivers
+v0000000003dde190_0 .var "notifier", 0 0;
+L_0000000003f97780 .cmp/eeq 1, L_00000000040c0220, L_000000000418a930;
+L_0000000003f97640 .cmp/eeq 1, o0000000003d8b638, L_000000000418a978;
+S_00000000029c45c0 .scope module, "sky130_fd_sc_hd__edfxtp_1" "sky130_fd_sc_hd__edfxtp_1" 4 96363;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+o0000000003d8bbd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dddb50_0 .net "CLK", 0 0, o0000000003d8bbd8;  0 drivers
+o0000000003d8bc38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddd8d0_0 .net "D", 0 0, o0000000003d8bc38;  0 drivers
+o0000000003d8bc68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dddbf0_0 .net "DE", 0 0, o0000000003d8bc68;  0 drivers
+v0000000003dddc90_0 .net "Q", 0 0, L_000000000416bf10;  1 drivers
+L_00000000040bf960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0e90_0 .net8 "VGND", 0 0, L_00000000040bf960;  1 drivers, strength-aware
+L_00000000040bfdc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1cf0_0 .net8 "VNB", 0 0, L_00000000040bfdc0;  1 drivers, strength-aware
+L_00000000040bff80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de0df0_0 .net8 "VPB", 0 0, L_00000000040bff80;  1 drivers, strength-aware
+L_00000000040bfff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de17f0_0 .net8 "VPWR", 0 0, L_00000000040bfff0;  1 drivers, strength-aware
+S_0000000003d139b0 .scope module, "base" "sky130_fd_sc_hd__edfxtp" 4 96381, 4 96236 1, S_00000000029c45c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+o0000000003d8bcc8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d8bc98 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000416af50 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000416b880, o0000000003d8bcc8, o0000000003d8bc98;
+o0000000003d8bc08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040c0bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040c0290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416b880 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000416af50, o0000000003d8bc08, v0000000003ddd3d0_0, L_00000000040c0bc0, L_00000000040c0290;
+L_000000000416bc70 .functor AND 1, L_0000000003f991c0, L_0000000003f980e0, C4<1>, C4<1>;
+L_000000000416bf10 .functor BUF 1, L_000000000416b880, C4<0>, C4<0>, C4<0>;
+v0000000003ddf630_0 .net "CLK", 0 0, o0000000003d8bbd8;  alias, 0 drivers
+v0000000003ddd1f0_0 .net "CLK_delayed", 0 0, o0000000003d8bc08;  0 drivers
+v0000000003ddec30_0 .net "D", 0 0, o0000000003d8bc38;  alias, 0 drivers
+v0000000003dde550_0 .net "DE", 0 0, o0000000003d8bc68;  alias, 0 drivers
+v0000000003ddd790_0 .net "DE_delayed", 0 0, o0000000003d8bc98;  0 drivers
+v0000000003ddf310_0 .net "D_delayed", 0 0, o0000000003d8bcc8;  0 drivers
+v0000000003dde7d0_0 .net "Q", 0 0, L_000000000416bf10;  alias, 1 drivers
+v0000000003ddef50_0 .net8 "VGND", 0 0, L_00000000040c0290;  1 drivers, strength-aware
+L_00000000040c07d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddecd0_0 .net8 "VNB", 0 0, L_00000000040c07d0;  1 drivers, strength-aware
+L_00000000040c0840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dde910_0 .net8 "VPB", 0 0, L_00000000040c0840;  1 drivers, strength-aware
+v0000000003dded70_0 .net8 "VPWR", 0 0, L_00000000040c0bc0;  1 drivers, strength-aware
+v0000000003ddee10_0 .net *"_s10", 0 0, L_0000000003f980e0;  1 drivers
+L_000000000418a9c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003ddf3b0_0 .net/2u *"_s4", 0 0, L_000000000418a9c0;  1 drivers
+L_000000000418aa08 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003ddf450_0 .net/2u *"_s8", 0 0, L_000000000418aa08;  1 drivers
+v0000000003ddf4f0_0 .net "awake", 0 0, L_0000000003f991c0;  1 drivers
+v0000000003ddf590_0 .net "buf_Q", 0 0, L_000000000416b880;  1 drivers
+v0000000003ddd290_0 .net "cond0", 0 0, L_000000000416bc70;  1 drivers
+v0000000003ddd330_0 .net "mux_out", 0 0, L_000000000416af50;  1 drivers
+v0000000003ddd3d0_0 .var "notifier", 0 0;
+L_0000000003f991c0 .cmp/eeq 1, L_00000000040c0bc0, L_000000000418a9c0;
+L_0000000003f980e0 .cmp/eeq 1, o0000000003d8bc98, L_000000000418aa08;
+S_00000000029c4a40 .scope module, "sky130_fd_sc_hd__einvn_0" "sky130_fd_sc_hd__einvn_0" 4 52738;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8c1a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de1e30_0 .net "A", 0 0, o0000000003d8c1a8;  0 drivers
+o0000000003d8c1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de0210_0 .net "TE_B", 0 0, o0000000003d8c1d8;  0 drivers
+L_00000000040c0d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0710_0 .net8 "VGND", 0 0, L_00000000040c0d10;  1 drivers, strength-aware
+L_00000000040c0d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddff90_0 .net8 "VNB", 0 0, L_00000000040c0d80;  1 drivers, strength-aware
+L_00000000040c1100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2010_0 .net8 "VPB", 0 0, L_00000000040c1100;  1 drivers, strength-aware
+L_00000000040c2520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de1ed0_0 .net8 "VPWR", 0 0, L_00000000040c2520;  1 drivers, strength-aware
+v0000000003de1890_0 .net "Z", 0 0, L_000000000416afc0;  1 drivers
+S_0000000003d18c30 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52754, 4 53243 1, S_00000000029c4a40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416afc0 .functor NOTIF0 1, o0000000003d8c1a8, o0000000003d8c1d8, C4<0>, C4<0>;
+v0000000003de0490_0 .net "A", 0 0, o0000000003d8c1a8;  alias, 0 drivers
+v0000000003de1b10_0 .net "TE_B", 0 0, o0000000003d8c1d8;  alias, 0 drivers
+L_00000000040c15d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de02b0_0 .net8 "VGND", 0 0, L_00000000040c15d0;  1 drivers, strength-aware
+L_00000000040c1e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0990_0 .net8 "VNB", 0 0, L_00000000040c1e90;  1 drivers, strength-aware
+L_00000000040c2280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de0c10_0 .net8 "VPB", 0 0, L_00000000040c2280;  1 drivers, strength-aware
+L_00000000040c23d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddf950_0 .net8 "VPWR", 0 0, L_00000000040c23d0;  1 drivers, strength-aware
+v0000000003de1570_0 .net "Z", 0 0, L_000000000416afc0;  alias, 1 drivers
+S_00000000029c4ec0 .scope module, "sky130_fd_sc_hd__einvn_1" "sky130_fd_sc_hd__einvn_1" 4 52950;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8c4d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de0fd0_0 .net "A", 0 0, o0000000003d8c4d8;  0 drivers
+o0000000003d8c508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de19d0_0 .net "TE_B", 0 0, o0000000003d8c508;  0 drivers
+L_00000000040c1250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de07b0_0 .net8 "VGND", 0 0, L_00000000040c1250;  1 drivers, strength-aware
+L_00000000040c18e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1390_0 .net8 "VNB", 0 0, L_00000000040c18e0;  1 drivers, strength-aware
+L_00000000040c13a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de0cb0_0 .net8 "VPB", 0 0, L_00000000040c13a0;  1 drivers, strength-aware
+L_00000000040c19c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de14d0_0 .net8 "VPWR", 0 0, L_00000000040c19c0;  1 drivers, strength-aware
+v0000000003de0350_0 .net "Z", 0 0, L_000000000416b110;  1 drivers
+S_0000000003d14d30 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52966, 4 53243 1, S_00000000029c4ec0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b110 .functor NOTIF0 1, o0000000003d8c4d8, o0000000003d8c508, C4<0>, C4<0>;
+v0000000003de0d50_0 .net "A", 0 0, o0000000003d8c4d8;  alias, 0 drivers
+v0000000003de0f30_0 .net "TE_B", 0 0, o0000000003d8c508;  alias, 0 drivers
+L_00000000040c2050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1d90_0 .net8 "VGND", 0 0, L_00000000040c2050;  1 drivers, strength-aware
+L_00000000040c1e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1610_0 .net8 "VNB", 0 0, L_00000000040c1e20;  1 drivers, strength-aware
+L_00000000040c1a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de1f70_0 .net8 "VPB", 0 0, L_00000000040c1a30;  1 drivers, strength-aware
+L_00000000040c2130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddfef0_0 .net8 "VPWR", 0 0, L_00000000040c2130;  1 drivers, strength-aware
+v0000000003ddfc70_0 .net "Z", 0 0, L_000000000416b110;  alias, 1 drivers
+S_00000000029c51c0 .scope module, "sky130_fd_sc_hd__einvn_2" "sky130_fd_sc_hd__einvn_2" 4 53350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8c808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de1070_0 .net "A", 0 0, o0000000003d8c808;  0 drivers
+o0000000003d8c838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de08f0_0 .net "TE_B", 0 0, o0000000003d8c838;  0 drivers
+L_00000000040c1d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1930_0 .net8 "VGND", 0 0, L_00000000040c1d40;  1 drivers, strength-aware
+L_00000000040c22f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0030_0 .net8 "VNB", 0 0, L_00000000040c22f0;  1 drivers, strength-aware
+L_00000000040c20c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de1bb0_0 .net8 "VPB", 0 0, L_00000000040c20c0;  1 drivers, strength-aware
+L_00000000040c26e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de20b0_0 .net8 "VPWR", 0 0, L_00000000040c26e0;  1 drivers, strength-aware
+v0000000003de11b0_0 .net "Z", 0 0, L_000000000416b180;  1 drivers
+S_0000000003d16e30 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 53366, 4 53243 1, S_00000000029c51c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b180 .functor NOTIF0 1, o0000000003d8c808, o0000000003d8c838, C4<0>, C4<0>;
+v0000000003de0850_0 .net "A", 0 0, o0000000003d8c808;  alias, 0 drivers
+v0000000003de1430_0 .net "TE_B", 0 0, o0000000003d8c838;  alias, 0 drivers
+L_00000000040c2590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de1110_0 .net8 "VGND", 0 0, L_00000000040c2590;  1 drivers, strength-aware
+L_00000000040c2360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de16b0_0 .net8 "VNB", 0 0, L_00000000040c2360;  1 drivers, strength-aware
+L_00000000040c2bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ddfd10_0 .net8 "VPB", 0 0, L_00000000040c2bb0;  1 drivers, strength-aware
+L_00000000040c1b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de1750_0 .net8 "VPWR", 0 0, L_00000000040c1b10;  1 drivers, strength-aware
+v0000000003de1a70_0 .net "Z", 0 0, L_000000000416b180;  alias, 1 drivers
+S_00000000029c5040 .scope module, "sky130_fd_sc_hd__einvn_4" "sky130_fd_sc_hd__einvn_4" 4 52844;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8cb38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de1c50_0 .net "A", 0 0, o0000000003d8cb38;  0 drivers
+o0000000003d8cb68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ddfbd0_0 .net "TE_B", 0 0, o0000000003d8cb68;  0 drivers
+L_00000000040c1aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddfdb0_0 .net8 "VGND", 0 0, L_00000000040c1aa0;  1 drivers, strength-aware
+L_00000000040c2440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddfe50_0 .net8 "VNB", 0 0, L_00000000040c2440;  1 drivers, strength-aware
+L_00000000040c27c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de0170_0 .net8 "VPB", 0 0, L_00000000040c27c0;  1 drivers, strength-aware
+L_00000000040c2210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de03f0_0 .net8 "VPWR", 0 0, L_00000000040c2210;  1 drivers, strength-aware
+v0000000003de0530_0 .net "Z", 0 0, L_000000000416b1f0;  1 drivers
+S_0000000003d18db0 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52860, 4 53243 1, S_00000000029c5040;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b1f0 .functor NOTIF0 1, o0000000003d8cb38, o0000000003d8cb68, C4<0>, C4<0>;
+v0000000003de1250_0 .net "A", 0 0, o0000000003d8cb38;  alias, 0 drivers
+v0000000003ddf9f0_0 .net "TE_B", 0 0, o0000000003d8cb68;  alias, 0 drivers
+L_00000000040c1b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ddfa90_0 .net8 "VGND", 0 0, L_00000000040c1b80;  1 drivers, strength-aware
+L_00000000040c1640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de12f0_0 .net8 "VNB", 0 0, L_00000000040c1640;  1 drivers, strength-aware
+L_00000000040c2980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de05d0_0 .net8 "VPB", 0 0, L_00000000040c2980;  1 drivers, strength-aware
+L_00000000040c1410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de00d0_0 .net8 "VPWR", 0 0, L_00000000040c1410;  1 drivers, strength-aware
+v0000000003ddfb30_0 .net "Z", 0 0, L_000000000416b1f0;  alias, 1 drivers
+S_00000000029c5f40 .scope module, "sky130_fd_sc_hd__einvn_8" "sky130_fd_sc_hd__einvn_8" 4 53456;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+o0000000003d8ce68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de35f0_0 .net "A", 0 0, o0000000003d8ce68;  0 drivers
+o0000000003d8ce98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de2dd0_0 .net "TE_B", 0 0, o0000000003d8ce98;  0 drivers
+L_00000000040c2600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2e70_0 .net8 "VGND", 0 0, L_00000000040c2600;  1 drivers, strength-aware
+L_00000000040c1950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de43b0_0 .net8 "VNB", 0 0, L_00000000040c1950;  1 drivers, strength-aware
+L_00000000040c1170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2fb0_0 .net8 "VPB", 0 0, L_00000000040c1170;  1 drivers, strength-aware
+L_00000000040c29f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3af0_0 .net8 "VPWR", 0 0, L_00000000040c29f0;  1 drivers, strength-aware
+v0000000003de4310_0 .net "Z", 0 0, L_000000000416b260;  1 drivers
+S_0000000003d148b0 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 53472, 4 53243 1, S_00000000029c5f40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE_B"
+L_000000000416b260 .functor NOTIF0 1, o0000000003d8ce68, o0000000003d8ce98, C4<0>, C4<0>;
+v0000000003de0670_0 .net "A", 0 0, o0000000003d8ce68;  alias, 0 drivers
+v0000000003de0a30_0 .net "TE_B", 0 0, o0000000003d8ce98;  alias, 0 drivers
+L_00000000040c2670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0ad0_0 .net8 "VGND", 0 0, L_00000000040c2670;  1 drivers, strength-aware
+L_00000000040c1db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de0b70_0 .net8 "VNB", 0 0, L_00000000040c1db0;  1 drivers, strength-aware
+L_00000000040c24b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de30f0_0 .net8 "VPB", 0 0, L_00000000040c24b0;  1 drivers, strength-aware
+L_00000000040c1f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2d30_0 .net8 "VPWR", 0 0, L_00000000040c1f00;  1 drivers, strength-aware
+v0000000003de3690_0 .net "Z", 0 0, L_000000000416b260;  alias, 1 drivers
+S_00000000029c6240 .scope module, "sky130_fd_sc_hd__einvp_1" "sky130_fd_sc_hd__einvp_1" 4 100473;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+o0000000003d8d198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de4770_0 .net "A", 0 0, o0000000003d8d198;  0 drivers
+o0000000003d8d1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de3cd0_0 .net "TE", 0 0, o0000000003d8d1c8;  0 drivers
+L_00000000040c2750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2ab0_0 .net8 "VGND", 0 0, L_00000000040c2750;  1 drivers, strength-aware
+L_00000000040c2a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de3d70_0 .net8 "VNB", 0 0, L_00000000040c2a60;  1 drivers, strength-aware
+L_00000000040c1f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3e10_0 .net8 "VPB", 0 0, L_00000000040c1f70;  1 drivers, strength-aware
+L_00000000040c12c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3730_0 .net8 "VPWR", 0 0, L_00000000040c12c0;  1 drivers, strength-aware
+v0000000003de3550_0 .net "Z", 0 0, L_000000000416bf80;  1 drivers
+S_0000000003d15930 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100489, 4 100978 1, S_00000000029c6240;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+L_000000000416bf80 .functor NOTIF1 1, o0000000003d8d198, o0000000003d8d1c8, C4<0>, C4<0>;
+v0000000003de2150_0 .net "A", 0 0, o0000000003d8d198;  alias, 0 drivers
+v0000000003de2f10_0 .net "TE", 0 0, o0000000003d8d1c8;  alias, 0 drivers
+L_00000000040c1720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de4630_0 .net8 "VGND", 0 0, L_00000000040c1720;  1 drivers, strength-aware
+L_00000000040c1330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de46d0_0 .net8 "VNB", 0 0, L_00000000040c1330;  1 drivers, strength-aware
+L_00000000040c1bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2a10_0 .net8 "VPB", 0 0, L_00000000040c1bf0;  1 drivers, strength-aware
+L_00000000040c2c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3050_0 .net8 "VPWR", 0 0, L_00000000040c2c90;  1 drivers, strength-aware
+v0000000003de3190_0 .net "Z", 0 0, L_000000000416bf80;  alias, 1 drivers
+S_00000000029c4740 .scope module, "sky130_fd_sc_hd__einvp_2" "sky130_fd_sc_hd__einvp_2" 4 100579;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+o0000000003d8d4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de3eb0_0 .net "A", 0 0, o0000000003d8d4c8;  0 drivers
+o0000000003d8d4f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de32d0_0 .net "TE", 0 0, o0000000003d8d4f8;  0 drivers
+L_00000000040c21a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de3370_0 .net8 "VGND", 0 0, L_00000000040c21a0;  1 drivers, strength-aware
+L_00000000040c1fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de37d0_0 .net8 "VNB", 0 0, L_00000000040c1fe0;  1 drivers, strength-aware
+L_00000000040c16b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de4590_0 .net8 "VPB", 0 0, L_00000000040c16b0;  1 drivers, strength-aware
+L_00000000040c1c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3b90_0 .net8 "VPWR", 0 0, L_00000000040c1c60;  1 drivers, strength-aware
+v0000000003de3c30_0 .net "Z", 0 0, L_000000000416bff0;  1 drivers
+S_0000000003d17a30 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100595, 4 100978 1, S_00000000029c4740;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+L_000000000416bff0 .functor NOTIF1 1, o0000000003d8d4c8, o0000000003d8d4f8, C4<0>, C4<0>;
+v0000000003de26f0_0 .net "A", 0 0, o0000000003d8d4c8;  alias, 0 drivers
+v0000000003de2650_0 .net "TE", 0 0, o0000000003d8d4f8;  alias, 0 drivers
+L_00000000040c11e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2c90_0 .net8 "VGND", 0 0, L_00000000040c11e0;  1 drivers, strength-aware
+L_00000000040c1480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2b50_0 .net8 "VNB", 0 0, L_00000000040c1480;  1 drivers, strength-aware
+L_00000000040c2830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de41d0_0 .net8 "VPB", 0 0, L_00000000040c2830;  1 drivers, strength-aware
+L_00000000040c1790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3230_0 .net8 "VPWR", 0 0, L_00000000040c1790;  1 drivers, strength-aware
+v0000000003de4130_0 .net "Z", 0 0, L_000000000416bff0;  alias, 1 drivers
+S_00000000029c54c0 .scope module, "sky130_fd_sc_hd__einvp_4" "sky130_fd_sc_hd__einvp_4" 4 100367;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+o0000000003d8d7f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de4810_0 .net "A", 0 0, o0000000003d8d7f8;  0 drivers
+o0000000003d8d828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de2830_0 .net "TE", 0 0, o0000000003d8d828;  0 drivers
+L_00000000040c28a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2510_0 .net8 "VGND", 0 0, L_00000000040c28a0;  1 drivers, strength-aware
+L_00000000040c2910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de25b0_0 .net8 "VNB", 0 0, L_00000000040c2910;  1 drivers, strength-aware
+L_00000000040c2ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2790_0 .net8 "VPB", 0 0, L_00000000040c2ad0;  1 drivers, strength-aware
+L_00000000040c14f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de34b0_0 .net8 "VPWR", 0 0, L_00000000040c14f0;  1 drivers, strength-aware
+v0000000003de3910_0 .net "Z", 0 0, L_000000000416cd80;  1 drivers
+S_0000000003d17bb0 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100383, 4 100978 1, S_00000000029c54c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+L_000000000416cd80 .functor NOTIF1 1, o0000000003d8d7f8, o0000000003d8d828, C4<0>, C4<0>;
+v0000000003de3f50_0 .net "A", 0 0, o0000000003d8d7f8;  alias, 0 drivers
+v0000000003de3870_0 .net "TE", 0 0, o0000000003d8d828;  alias, 0 drivers
+L_00000000040c1cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de3ff0_0 .net8 "VGND", 0 0, L_00000000040c1cd0;  1 drivers, strength-aware
+L_00000000040c1560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de21f0_0 .net8 "VNB", 0 0, L_00000000040c1560;  1 drivers, strength-aware
+L_00000000040c2b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de3410_0 .net8 "VPB", 0 0, L_00000000040c2b40;  1 drivers, strength-aware
+L_00000000040c2c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de4270_0 .net8 "VPWR", 0 0, L_00000000040c2c20;  1 drivers, strength-aware
+v0000000003de28d0_0 .net "Z", 0 0, L_000000000416cd80;  alias, 1 drivers
+S_00000000029177c0 .scope module, "sky130_fd_sc_hd__einvp_8" "sky130_fd_sc_hd__einvp_8" 4 100685;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+o0000000003d8db28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de48b0_0 .net "A", 0 0, o0000000003d8db28;  0 drivers
+o0000000003d8db58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de23d0_0 .net "TE", 0 0, o0000000003d8db58;  0 drivers
+L_00000000040c1800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2330_0 .net8 "VGND", 0 0, L_00000000040c1800;  1 drivers, strength-aware
+L_00000000040c1870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de2bf0_0 .net8 "VNB", 0 0, L_00000000040c1870;  1 drivers, strength-aware
+L_00000000040c3d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2470_0 .net8 "VPB", 0 0, L_00000000040c3d30;  1 drivers, strength-aware
+L_00000000040c3940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de5670_0 .net8 "VPWR", 0 0, L_00000000040c3940;  1 drivers, strength-aware
+v0000000003de4e50_0 .net "Z", 0 0, L_000000000416c3e0;  1 drivers
+S_0000000003d163b0 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100701, 4 100978 1, S_00000000029177c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Z"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "TE"
+L_000000000416c3e0 .functor NOTIF1 1, o0000000003d8db28, o0000000003d8db58, C4<0>, C4<0>;
+v0000000003de3a50_0 .net "A", 0 0, o0000000003d8db28;  alias, 0 drivers
+v0000000003de39b0_0 .net "TE", 0 0, o0000000003d8db58;  alias, 0 drivers
+L_00000000040c3e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de4090_0 .net8 "VGND", 0 0, L_00000000040c3e80;  1 drivers, strength-aware
+L_00000000040c3c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de4450_0 .net8 "VNB", 0 0, L_00000000040c3c50;  1 drivers, strength-aware
+L_00000000040c42e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de2970_0 .net8 "VPB", 0 0, L_00000000040c42e0;  1 drivers, strength-aware
+L_00000000040c4120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de44f0_0 .net8 "VPWR", 0 0, L_00000000040c4120;  1 drivers, strength-aware
+v0000000003de2290_0 .net "Z", 0 0, L_000000000416c3e0;  alias, 1 drivers
+S_00000000029171c0 .scope module, "sky130_fd_sc_hd__fa_1" "sky130_fd_sc_hd__fa_1" 4 55192;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+o0000000003d8de58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de4ef0_0 .net "A", 0 0, o0000000003d8de58;  0 drivers
+o0000000003d8de88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de6f70_0 .net "B", 0 0, o0000000003d8de88;  0 drivers
+o0000000003d8deb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de6390_0 .net "CIN", 0 0, o0000000003d8deb8;  0 drivers
+v0000000003de55d0_0 .net "COUT", 0 0, L_000000000416d170;  1 drivers
+v0000000003de52b0_0 .net "SUM", 0 0, L_000000000416cb50;  1 drivers
+L_00000000040c3f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de5df0_0 .net8 "VGND", 0 0, L_00000000040c3f60;  1 drivers, strength-aware
+L_00000000040c47b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de5850_0 .net8 "VNB", 0 0, L_00000000040c47b0;  1 drivers, strength-aware
+L_00000000040c3710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de6930_0 .net8 "VPB", 0 0, L_00000000040c3710;  1 drivers, strength-aware
+L_00000000040c35c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de4d10_0 .net8 "VPWR", 0 0, L_00000000040c35c0;  1 drivers, strength-aware
+S_0000000003d18f30 .scope module, "base" "sky130_fd_sc_hd__fa" 4 55212, 4 55556 1, S_00000000029171c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+L_000000000416d720 .functor OR 1, o0000000003d8deb8, o0000000003d8de88, C4<0>, C4<0>;
+L_000000000416ca00 .functor AND 1, L_000000000416d720, o0000000003d8de58, C4<1>, C4<1>;
+L_000000000416c450 .functor AND 1, o0000000003d8de88, o0000000003d8deb8, C4<1>, C4<1>;
+L_000000000416ca70 .functor OR 1, L_000000000416c450, L_000000000416ca00, C4<0>, C4<0>;
+L_000000000416d170 .functor BUF 1, L_000000000416ca70, C4<0>, C4<0>, C4<0>;
+L_000000000416c990 .functor AND 1, o0000000003d8deb8, o0000000003d8de58, o0000000003d8de88, C4<1>;
+L_000000000416cae0 .functor NOR 1, o0000000003d8de58, L_000000000416d720, C4<0>, C4<0>;
+L_000000000416d790 .functor NOR 1, L_000000000416cae0, L_000000000416d170, C4<0>, C4<0>;
+L_000000000416d250 .functor OR 1, L_000000000416d790, L_000000000416c990, C4<0>, C4<0>;
+L_000000000416cb50 .functor BUF 1, L_000000000416d250, C4<0>, C4<0>, C4<0>;
+v0000000003de6cf0_0 .net "A", 0 0, o0000000003d8de58;  alias, 0 drivers
+v0000000003de4db0_0 .net "B", 0 0, o0000000003d8de88;  alias, 0 drivers
+v0000000003de57b0_0 .net "CIN", 0 0, o0000000003d8deb8;  alias, 0 drivers
+v0000000003de5ad0_0 .net "COUT", 0 0, L_000000000416d170;  alias, 1 drivers
+v0000000003de5cb0_0 .net "SUM", 0 0, L_000000000416cb50;  alias, 1 drivers
+L_00000000040c3ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de5b70_0 .net8 "VGND", 0 0, L_00000000040c3ef0;  1 drivers, strength-aware
+L_00000000040c43c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de4f90_0 .net8 "VNB", 0 0, L_00000000040c43c0;  1 drivers, strength-aware
+L_00000000040c3e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de7010_0 .net8 "VPB", 0 0, L_00000000040c3e10;  1 drivers, strength-aware
+L_00000000040c3780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de64d0_0 .net8 "VPWR", 0 0, L_00000000040c3780;  1 drivers, strength-aware
+v0000000003de6890_0 .net "and0_out", 0 0, L_000000000416ca00;  1 drivers
+v0000000003de6a70_0 .net "and1_out", 0 0, L_000000000416c450;  1 drivers
+v0000000003de5210_0 .net "and2_out", 0 0, L_000000000416c990;  1 drivers
+v0000000003de5490_0 .net "nor0_out", 0 0, L_000000000416cae0;  1 drivers
+v0000000003de67f0_0 .net "nor1_out", 0 0, L_000000000416d790;  1 drivers
+v0000000003de6570_0 .net "or0_out", 0 0, L_000000000416d720;  1 drivers
+v0000000003de5f30_0 .net "or1_out_COUT", 0 0, L_000000000416ca70;  1 drivers
+v0000000003de5d50_0 .net "or2_out_SUM", 0 0, L_000000000416d250;  1 drivers
+S_0000000002916d40 .scope module, "sky130_fd_sc_hd__fa_2" "sky130_fd_sc_hd__fa_2" 4 54956;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+o0000000003d8e428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de5a30_0 .net "A", 0 0, o0000000003d8e428;  0 drivers
+o0000000003d8e458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de5990_0 .net "B", 0 0, o0000000003d8e458;  0 drivers
+o0000000003d8e488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de66b0_0 .net "CIN", 0 0, o0000000003d8e488;  0 drivers
+v0000000003de6070_0 .net "COUT", 0 0, L_000000000416cc30;  1 drivers
+v0000000003de6bb0_0 .net "SUM", 0 0, L_000000000416d330;  1 drivers
+L_00000000040c31d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de62f0_0 .net8 "VGND", 0 0, L_00000000040c31d0;  1 drivers, strength-aware
+L_00000000040c4580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de53f0_0 .net8 "VNB", 0 0, L_00000000040c4580;  1 drivers, strength-aware
+L_00000000040c3010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de61b0_0 .net8 "VPB", 0 0, L_00000000040c3010;  1 drivers, strength-aware
+L_00000000040c4190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de6750_0 .net8 "VPWR", 0 0, L_00000000040c4190;  1 drivers, strength-aware
+S_0000000003d14a30 .scope module, "base" "sky130_fd_sc_hd__fa" 4 54976, 4 55556 1, S_0000000002916d40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+L_000000000416cbc0 .functor OR 1, o0000000003d8e488, o0000000003d8e458, C4<0>, C4<0>;
+L_000000000416d560 .functor AND 1, L_000000000416cbc0, o0000000003d8e428, C4<1>, C4<1>;
+L_000000000416c1b0 .functor AND 1, o0000000003d8e458, o0000000003d8e488, C4<1>, C4<1>;
+L_000000000416d2c0 .functor OR 1, L_000000000416c1b0, L_000000000416d560, C4<0>, C4<0>;
+L_000000000416cc30 .functor BUF 1, L_000000000416d2c0, C4<0>, C4<0>, C4<0>;
+L_000000000416c8b0 .functor AND 1, o0000000003d8e488, o0000000003d8e428, o0000000003d8e458, C4<1>;
+L_000000000416d6b0 .functor NOR 1, o0000000003d8e428, L_000000000416cbc0, C4<0>, C4<0>;
+L_000000000416dcd0 .functor NOR 1, L_000000000416d6b0, L_000000000416cc30, C4<0>, C4<0>;
+L_000000000416cf40 .functor OR 1, L_000000000416dcd0, L_000000000416c8b0, C4<0>, C4<0>;
+L_000000000416d330 .functor BUF 1, L_000000000416cf40, C4<0>, C4<0>, C4<0>;
+v0000000003de69d0_0 .net "A", 0 0, o0000000003d8e428;  alias, 0 drivers
+v0000000003de5710_0 .net "B", 0 0, o0000000003d8e458;  alias, 0 drivers
+v0000000003de6430_0 .net "CIN", 0 0, o0000000003d8e488;  alias, 0 drivers
+v0000000003de6110_0 .net "COUT", 0 0, L_000000000416cc30;  alias, 1 drivers
+v0000000003de5c10_0 .net "SUM", 0 0, L_000000000416d330;  alias, 1 drivers
+L_00000000040c3550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de4c70_0 .net8 "VGND", 0 0, L_00000000040c3550;  1 drivers, strength-aware
+L_00000000040c2d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de5350_0 .net8 "VNB", 0 0, L_00000000040c2d70;  1 drivers, strength-aware
+L_00000000040c45f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de4bd0_0 .net8 "VPB", 0 0, L_00000000040c45f0;  1 drivers, strength-aware
+L_00000000040c4270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de5e90_0 .net8 "VPWR", 0 0, L_00000000040c4270;  1 drivers, strength-aware
+v0000000003de6610_0 .net "and0_out", 0 0, L_000000000416d560;  1 drivers
+v0000000003de5fd0_0 .net "and1_out", 0 0, L_000000000416c1b0;  1 drivers
+v0000000003de58f0_0 .net "and2_out", 0 0, L_000000000416c8b0;  1 drivers
+v0000000003de6250_0 .net "nor0_out", 0 0, L_000000000416d6b0;  1 drivers
+v0000000003de6b10_0 .net "nor1_out", 0 0, L_000000000416dcd0;  1 drivers
+v0000000003de50d0_0 .net "or0_out", 0 0, L_000000000416cbc0;  1 drivers
+v0000000003de5030_0 .net "or1_out_COUT", 0 0, L_000000000416d2c0;  1 drivers
+v0000000003de5170_0 .net "or2_out_SUM", 0 0, L_000000000416cf40;  1 drivers
+S_0000000002916740 .scope module, "sky130_fd_sc_hd__fa_4" "sky130_fd_sc_hd__fa_4" 4 55074;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+o0000000003d8e9f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de7150_0 .net "A", 0 0, o0000000003d8e9f8;  0 drivers
+o0000000003d8ea28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de9270_0 .net "B", 0 0, o0000000003d8ea28;  0 drivers
+o0000000003d8ea58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de7970_0 .net "CIN", 0 0, o0000000003d8ea58;  0 drivers
+v0000000003de8b90_0 .net "COUT", 0 0, L_000000000416cfb0;  1 drivers
+v0000000003de7f10_0 .net "SUM", 0 0, L_000000000416d480;  1 drivers
+L_00000000040c39b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de8410_0 .net8 "VGND", 0 0, L_00000000040c39b0;  1 drivers, strength-aware
+L_00000000040c2e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de96d0_0 .net8 "VNB", 0 0, L_00000000040c2e50;  1 drivers, strength-aware
+L_00000000040c4430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de9770_0 .net8 "VPB", 0 0, L_00000000040c4430;  1 drivers, strength-aware
+L_00000000040c36a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de7fb0_0 .net8 "VPWR", 0 0, L_00000000040c36a0;  1 drivers, strength-aware
+S_0000000003d13cb0 .scope module, "base" "sky130_fd_sc_hd__fa" 4 55094, 4 55556 1, S_0000000002916740;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+L_000000000416cca0 .functor OR 1, o0000000003d8ea58, o0000000003d8ea28, C4<0>, C4<0>;
+L_000000000416c140 .functor AND 1, L_000000000416cca0, o0000000003d8e9f8, C4<1>, C4<1>;
+L_000000000416cdf0 .functor AND 1, o0000000003d8ea28, o0000000003d8ea58, C4<1>, C4<1>;
+L_000000000416ce60 .functor OR 1, L_000000000416cdf0, L_000000000416c140, C4<0>, C4<0>;
+L_000000000416cfb0 .functor BUF 1, L_000000000416ce60, C4<0>, C4<0>, C4<0>;
+L_000000000416cd10 .functor AND 1, o0000000003d8ea58, o0000000003d8e9f8, o0000000003d8ea28, C4<1>;
+L_000000000416daa0 .functor NOR 1, o0000000003d8e9f8, L_000000000416cca0, C4<0>, C4<0>;
+L_000000000416c4c0 .functor NOR 1, L_000000000416daa0, L_000000000416cfb0, C4<0>, C4<0>;
+L_000000000416dc60 .functor OR 1, L_000000000416c4c0, L_000000000416cd10, C4<0>, C4<0>;
+L_000000000416d480 .functor BUF 1, L_000000000416dc60, C4<0>, C4<0>, C4<0>;
+v0000000003de6e30_0 .net "A", 0 0, o0000000003d8e9f8;  alias, 0 drivers
+v0000000003de4950_0 .net "B", 0 0, o0000000003d8ea28;  alias, 0 drivers
+v0000000003de6c50_0 .net "CIN", 0 0, o0000000003d8ea58;  alias, 0 drivers
+v0000000003de5530_0 .net "COUT", 0 0, L_000000000416cfb0;  alias, 1 drivers
+v0000000003de6d90_0 .net "SUM", 0 0, L_000000000416d480;  alias, 1 drivers
+L_00000000040c3860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de6ed0_0 .net8 "VGND", 0 0, L_00000000040c3860;  1 drivers, strength-aware
+L_00000000040c3b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de70b0_0 .net8 "VNB", 0 0, L_00000000040c3b00;  1 drivers, strength-aware
+L_00000000040c40b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de49f0_0 .net8 "VPB", 0 0, L_00000000040c40b0;  1 drivers, strength-aware
+L_00000000040c46d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de4a90_0 .net8 "VPWR", 0 0, L_00000000040c46d0;  1 drivers, strength-aware
+v0000000003de4b30_0 .net "and0_out", 0 0, L_000000000416c140;  1 drivers
+v0000000003de8af0_0 .net "and1_out", 0 0, L_000000000416cdf0;  1 drivers
+v0000000003de7e70_0 .net "and2_out", 0 0, L_000000000416cd10;  1 drivers
+v0000000003de91d0_0 .net "nor0_out", 0 0, L_000000000416daa0;  1 drivers
+v0000000003de75b0_0 .net "nor1_out", 0 0, L_000000000416c4c0;  1 drivers
+v0000000003de89b0_0 .net "or0_out", 0 0, L_000000000416cca0;  1 drivers
+v0000000003de8a50_0 .net "or1_out_COUT", 0 0, L_000000000416ce60;  1 drivers
+v0000000003de8050_0 .net "or2_out_SUM", 0 0, L_000000000416dc60;  1 drivers
+S_0000000002916ec0 .scope module, "sky130_fd_sc_hd__fah_1" "sky130_fd_sc_hd__fah_1" 4 13757;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CI"
+o0000000003d8efc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de7510_0 .net "A", 0 0, o0000000003d8efc8;  0 drivers
+o0000000003d8eff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de7650_0 .net "B", 0 0, o0000000003d8eff8;  0 drivers
+o0000000003d8f028 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de82d0_0 .net "CI", 0 0, o0000000003d8f028;  0 drivers
+v0000000003de78d0_0 .net "COUT", 0 0, L_000000000416db10;  1 drivers
+v0000000003de7d30_0 .net "SUM", 0 0, L_000000000416d3a0;  1 drivers
+L_00000000040c32b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de73d0_0 .net8 "VGND", 0 0, L_00000000040c32b0;  1 drivers, strength-aware
+L_00000000040c38d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9590_0 .net8 "VNB", 0 0, L_00000000040c38d0;  1 drivers, strength-aware
+L_00000000040c3fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de85f0_0 .net8 "VPB", 0 0, L_00000000040c3fd0;  1 drivers, strength-aware
+L_00000000040c4740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de8ff0_0 .net8 "VPWR", 0 0, L_00000000040c4740;  1 drivers, strength-aware
+S_0000000003d17eb0 .scope module, "base" "sky130_fd_sc_hd__fah" 4 13777, 4 14103 1, S_0000000002916ec0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CI"
+L_000000000416c920 .functor XOR 1, o0000000003d8efc8, o0000000003d8eff8, o0000000003d8f028, C4<0>;
+L_000000000416d3a0 .functor BUF 1, L_000000000416c920, C4<0>, C4<0>, C4<0>;
+L_000000000416d800 .functor AND 1, o0000000003d8efc8, o0000000003d8eff8, C4<1>, C4<1>;
+L_000000000416c5a0 .functor AND 1, o0000000003d8efc8, o0000000003d8f028, C4<1>, C4<1>;
+L_000000000416c530 .functor AND 1, o0000000003d8eff8, o0000000003d8f028, C4<1>, C4<1>;
+L_000000000416c610 .functor OR 1, L_000000000416d800, L_000000000416c5a0, L_000000000416c530, C4<0>;
+L_000000000416db10 .functor BUF 1, L_000000000416c610, C4<0>, C4<0>, C4<0>;
+v0000000003de7330_0 .net "A", 0 0, o0000000003d8efc8;  alias, 0 drivers
+v0000000003de71f0_0 .net "B", 0 0, o0000000003d8eff8;  alias, 0 drivers
+v0000000003de7dd0_0 .net "CI", 0 0, o0000000003d8f028;  alias, 0 drivers
+v0000000003de84b0_0 .net "COUT", 0 0, L_000000000416db10;  alias, 1 drivers
+v0000000003de8d70_0 .net "SUM", 0 0, L_000000000416d3a0;  alias, 1 drivers
+L_00000000040c44a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de94f0_0 .net8 "VGND", 0 0, L_00000000040c44a0;  1 drivers, strength-aware
+L_00000000040c34e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de80f0_0 .net8 "VNB", 0 0, L_00000000040c34e0;  1 drivers, strength-aware
+L_00000000040c3630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de7290_0 .net8 "VPB", 0 0, L_00000000040c3630;  1 drivers, strength-aware
+L_00000000040c37f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de9130_0 .net8 "VPWR", 0 0, L_00000000040c37f0;  1 drivers, strength-aware
+v0000000003de8c30_0 .net "a_b", 0 0, L_000000000416d800;  1 drivers
+v0000000003de8cd0_0 .net "a_ci", 0 0, L_000000000416c5a0;  1 drivers
+v0000000003de8190_0 .net "b_ci", 0 0, L_000000000416c530;  1 drivers
+v0000000003de8230_0 .net "or0_out_COUT", 0 0, L_000000000416c610;  1 drivers
+v0000000003de7830_0 .net "xor0_out_SUM", 0 0, L_000000000416c920;  1 drivers
+S_00000000029168c0 .scope module, "sky130_fd_sc_hd__fahcin_1" "sky130_fd_sc_hd__fahcin_1" 4 59360;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+o0000000003d8f508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de7ab0_0 .net "A", 0 0, o0000000003d8f508;  0 drivers
+o0000000003d8f538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de9090_0 .net "B", 0 0, o0000000003d8f538;  0 drivers
+o0000000003d8f568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de87d0_0 .net "CIN", 0 0, o0000000003d8f568;  0 drivers
+v0000000003de8870_0 .net "COUT", 0 0, L_000000000416d4f0;  1 drivers
+v0000000003de7b50_0 .net "SUM", 0 0, L_000000000416d020;  1 drivers
+L_00000000040c4350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de8910_0 .net8 "VGND", 0 0, L_00000000040c4350;  1 drivers, strength-aware
+L_00000000040c4510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de7bf0_0 .net8 "VNB", 0 0, L_00000000040c4510;  1 drivers, strength-aware
+L_00000000040c4660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de7c90_0 .net8 "VPB", 0 0, L_00000000040c4660;  1 drivers, strength-aware
+L_00000000040c4040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de93b0_0 .net8 "VPWR", 0 0, L_00000000040c4040;  1 drivers, strength-aware
+S_0000000003d15330 .scope module, "base" "sky130_fd_sc_hd__fahcin" 4 59380, 4 59228 1, S_00000000029168c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CIN"
+L_000000000416ced0 .functor NOT 1, o0000000003d8f568, C4<0>, C4<0>, C4<0>;
+L_000000000416d090 .functor XOR 1, o0000000003d8f508, o0000000003d8f538, L_000000000416ced0, C4<0>;
+L_000000000416d020 .functor BUF 1, L_000000000416d090, C4<0>, C4<0>, C4<0>;
+L_000000000416d100 .functor AND 1, o0000000003d8f508, o0000000003d8f538, C4<1>, C4<1>;
+L_000000000416c370 .functor AND 1, o0000000003d8f508, L_000000000416ced0, C4<1>, C4<1>;
+L_000000000416d1e0 .functor AND 1, o0000000003d8f538, L_000000000416ced0, C4<1>, C4<1>;
+L_000000000416d410 .functor OR 1, L_000000000416d100, L_000000000416c370, L_000000000416d1e0, C4<0>;
+L_000000000416d4f0 .functor BUF 1, L_000000000416d410, C4<0>, C4<0>, C4<0>;
+v0000000003de8370_0 .net "A", 0 0, o0000000003d8f508;  alias, 0 drivers
+v0000000003de8e10_0 .net "B", 0 0, o0000000003d8f538;  alias, 0 drivers
+v0000000003de8550_0 .net "CIN", 0 0, o0000000003d8f568;  alias, 0 drivers
+v0000000003de8690_0 .net "COUT", 0 0, L_000000000416d4f0;  alias, 1 drivers
+v0000000003de9310_0 .net "SUM", 0 0, L_000000000416d020;  alias, 1 drivers
+L_00000000040c4820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de8eb0_0 .net8 "VGND", 0 0, L_00000000040c4820;  1 drivers, strength-aware
+L_00000000040c4890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de76f0_0 .net8 "VNB", 0 0, L_00000000040c4890;  1 drivers, strength-aware
+L_00000000040c2d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de9630_0 .net8 "VPB", 0 0, L_00000000040c2d00;  1 drivers, strength-aware
+L_00000000040c2de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de9810_0 .net8 "VPWR", 0 0, L_00000000040c2de0;  1 drivers, strength-aware
+v0000000003de7a10_0 .net "a_b", 0 0, L_000000000416d100;  1 drivers
+v0000000003de7470_0 .net "a_ci", 0 0, L_000000000416c370;  1 drivers
+v0000000003de8730_0 .net "b_ci", 0 0, L_000000000416d1e0;  1 drivers
+v0000000003de7790_0 .net "ci", 0 0, L_000000000416ced0;  1 drivers
+v0000000003de98b0_0 .net "or0_out_COUT", 0 0, L_000000000416d410;  1 drivers
+v0000000003de8f50_0 .net "xor0_out_SUM", 0 0, L_000000000416d090;  1 drivers
+S_0000000002915e40 .scope module, "sky130_fd_sc_hd__fahcon_1" "sky130_fd_sc_hd__fahcon_1" 4 11458;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT_N"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CI"
+o0000000003d8fa78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dea030_0 .net "A", 0 0, o0000000003d8fa78;  0 drivers
+o0000000003d8faa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003de9e50_0 .net "B", 0 0, o0000000003d8faa8;  0 drivers
+o0000000003d8fad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dea850_0 .net "CI", 0 0, o0000000003d8fad8;  0 drivers
+v0000000003dead50_0 .net "COUT_N", 0 0, L_000000000416d8e0;  1 drivers
+v0000000003deb890_0 .net "SUM", 0 0, L_000000000416c680;  1 drivers
+L_00000000040c2f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9bd0_0 .net8 "VGND", 0 0, L_00000000040c2f30;  1 drivers, strength-aware
+L_00000000040c3a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9d10_0 .net8 "VNB", 0 0, L_00000000040c3a20;  1 drivers, strength-aware
+L_00000000040c2ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dec010_0 .net8 "VPB", 0 0, L_00000000040c2ec0;  1 drivers, strength-aware
+L_00000000040c3a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dea490_0 .net8 "VPWR", 0 0, L_00000000040c3a90;  1 drivers, strength-aware
+S_0000000003d15c30 .scope module, "base" "sky130_fd_sc_hd__fahcon" 4 11478, 4 11328 1, S_0000000002915e40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT_N"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+    .port_info 4 /INPUT 1 "CI"
+L_000000000416c300 .functor XOR 1, o0000000003d8fa78, o0000000003d8faa8, o0000000003d8fad8, C4<0>;
+L_000000000416c680 .functor BUF 1, L_000000000416c300, C4<0>, C4<0>, C4<0>;
+L_000000000416d640 .functor NOR 1, o0000000003d8fa78, o0000000003d8faa8, C4<0>, C4<0>;
+L_000000000416d5d0 .functor NOR 1, o0000000003d8fa78, o0000000003d8fad8, C4<0>, C4<0>;
+L_000000000416c220 .functor NOR 1, o0000000003d8faa8, o0000000003d8fad8, C4<0>, C4<0>;
+L_000000000416c290 .functor OR 1, L_000000000416d640, L_000000000416d5d0, L_000000000416c220, C4<0>;
+L_000000000416d8e0 .functor BUF 1, L_000000000416c290, C4<0>, C4<0>, C4<0>;
+v0000000003de9450_0 .net "A", 0 0, o0000000003d8fa78;  alias, 0 drivers
+v0000000003deb390_0 .net "B", 0 0, o0000000003d8faa8;  alias, 0 drivers
+v0000000003deb1b0_0 .net "CI", 0 0, o0000000003d8fad8;  alias, 0 drivers
+v0000000003deb7f0_0 .net "COUT_N", 0 0, L_000000000416d8e0;  alias, 1 drivers
+v0000000003dea8f0_0 .net "SUM", 0 0, L_000000000416c680;  alias, 1 drivers
+L_00000000040c3b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea7b0_0 .net8 "VGND", 0 0, L_00000000040c3b70;  1 drivers, strength-aware
+L_00000000040c4200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deb110_0 .net8 "VNB", 0 0, L_00000000040c4200;  1 drivers, strength-aware
+L_00000000040c3240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb9d0_0 .net8 "VPB", 0 0, L_00000000040c3240;  1 drivers, strength-aware
+L_00000000040c2fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de9ef0_0 .net8 "VPWR", 0 0, L_00000000040c2fa0;  1 drivers, strength-aware
+v0000000003deaa30_0 .net "a_b", 0 0, L_000000000416d640;  1 drivers
+v0000000003deb570_0 .net "a_ci", 0 0, L_000000000416d5d0;  1 drivers
+v0000000003deb250_0 .net "b_ci", 0 0, L_000000000416c220;  1 drivers
+v0000000003deac10_0 .net "or0_out_coutn", 0 0, L_000000000416c290;  1 drivers
+v0000000003dea990_0 .net "xor0_out_SUM", 0 0, L_000000000416c300;  1 drivers
+S_0000000002916bc0 .scope module, "sky130_fd_sc_hd__fill_1" "sky130_fd_sc_hd__fill_1" 4 3690;
+ .timescale -9 -12;
+L_00000000040c3080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9b30_0 .net8 "VGND", 0 0, L_00000000040c3080;  1 drivers, strength-aware
+L_00000000040c30f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9950_0 .net8 "VNB", 0 0, L_00000000040c30f0;  1 drivers, strength-aware
+L_00000000040c3160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dea710_0 .net8 "VPB", 0 0, L_00000000040c3160;  1 drivers, strength-aware
+L_00000000040c3be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deacb0_0 .net8 "VPWR", 0 0, L_00000000040c3be0;  1 drivers, strength-aware
+S_0000000003d15db0 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3697, 4 3352 1, S_0000000002916bc0;
+ .timescale -9 -12;
+L_00000000040c3320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea5d0_0 .net8 "VGND", 0 0, L_00000000040c3320;  1 drivers, strength-aware
+L_00000000040c3cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea2b0_0 .net8 "VNB", 0 0, L_00000000040c3cc0;  1 drivers, strength-aware
+L_00000000040c3390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb610_0 .net8 "VPB", 0 0, L_00000000040c3390;  1 drivers, strength-aware
+L_00000000040c3400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dea670_0 .net8 "VPWR", 0 0, L_00000000040c3400;  1 drivers, strength-aware
+S_00000000029162c0 .scope module, "sky130_fd_sc_hd__fill_2" "sky130_fd_sc_hd__fill_2" 4 3606;
+ .timescale -9 -12;
+L_00000000040c3470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deb430_0 .net8 "VGND", 0 0, L_00000000040c3470;  1 drivers, strength-aware
+L_00000000040c3da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deb4d0_0 .net8 "VNB", 0 0, L_00000000040c3da0;  1 drivers, strength-aware
+L_00000000040c5310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dea0d0_0 .net8 "VPB", 0 0, L_00000000040c5310;  1 drivers, strength-aware
+L_00000000040c62d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deadf0_0 .net8 "VPWR", 0 0, L_00000000040c62d0;  1 drivers, strength-aware
+S_0000000003d18030 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3613, 4 3352 1, S_00000000029162c0;
+ .timescale -9 -12;
+L_00000000040c6260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003debcf0_0 .net8 "VGND", 0 0, L_00000000040c6260;  1 drivers, strength-aware
+L_00000000040c6340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deaad0_0 .net8 "VNB", 0 0, L_00000000040c6340;  1 drivers, strength-aware
+L_00000000040c63b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb930_0 .net8 "VPB", 0 0, L_00000000040c63b0;  1 drivers, strength-aware
+L_00000000040c5000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb2f0_0 .net8 "VPWR", 0 0, L_00000000040c5000;  1 drivers, strength-aware
+S_0000000002917c40 .scope module, "sky130_fd_sc_hd__fill_4" "sky130_fd_sc_hd__fill_4" 4 3438;
+ .timescale -9 -12;
+L_00000000040c59a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea530_0 .net8 "VGND", 0 0, L_00000000040c59a0;  1 drivers, strength-aware
+L_00000000040c5d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9a90_0 .net8 "VNB", 0 0, L_00000000040c5d20;  1 drivers, strength-aware
+L_00000000040c5070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb6b0_0 .net8 "VPB", 0 0, L_00000000040c5070;  1 drivers, strength-aware
+L_00000000040c4ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deba70_0 .net8 "VPWR", 0 0, L_00000000040c4ac0;  1 drivers, strength-aware
+S_0000000003d130b0 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3445, 4 3352 1, S_0000000002917c40;
+ .timescale -9 -12;
+L_00000000040c5e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9db0_0 .net8 "VGND", 0 0, L_00000000040c5e70;  1 drivers, strength-aware
+L_00000000040c4900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003de9f90_0 .net8 "VNB", 0 0, L_00000000040c4900;  1 drivers, strength-aware
+L_00000000040c5700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deab70_0 .net8 "VPB", 0 0, L_00000000040c5700;  1 drivers, strength-aware
+L_00000000040c4eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dea170_0 .net8 "VPWR", 0 0, L_00000000040c4eb0;  1 drivers, strength-aware
+S_0000000002917ac0 .scope module, "sky130_fd_sc_hd__fill_8" "sky130_fd_sc_hd__fill_8" 4 3522;
+ .timescale -9 -12;
+L_00000000040c5850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea210_0 .net8 "VGND", 0 0, L_00000000040c5850;  1 drivers, strength-aware
+L_00000000040c4dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003debb10_0 .net8 "VNB", 0 0, L_00000000040c4dd0;  1 drivers, strength-aware
+L_00000000040c54d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003debe30_0 .net8 "VPB", 0 0, L_00000000040c54d0;  1 drivers, strength-aware
+L_00000000040c4ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003debc50_0 .net8 "VPWR", 0 0, L_00000000040c4ba0;  1 drivers, strength-aware
+S_0000000003d166b0 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3529, 4 3352 1, S_0000000002917ac0;
+ .timescale -9 -12;
+L_00000000040c5770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deae90_0 .net8 "VGND", 0 0, L_00000000040c5770;  1 drivers, strength-aware
+L_00000000040c5230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003debbb0_0 .net8 "VNB", 0 0, L_00000000040c5230;  1 drivers, strength-aware
+L_00000000040c5d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deb750_0 .net8 "VPB", 0 0, L_00000000040c5d90;  1 drivers, strength-aware
+L_00000000040c58c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deaf30_0 .net8 "VPWR", 0 0, L_00000000040c58c0;  1 drivers, strength-aware
+S_00000000029165c0 .scope module, "sky130_fd_sc_hd__ha_1" "sky130_fd_sc_hd__ha_1" 4 10435;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+o0000000003d905b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ded730_0 .net "A", 0 0, o0000000003d905b8;  0 drivers
+o0000000003d905e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dee090_0 .net "B", 0 0, o0000000003d905e8;  0 drivers
+v0000000003dedaf0_0 .net "COUT", 0 0, L_000000000416d9c0;  1 drivers
+v0000000003dee4f0_0 .net "SUM", 0 0, L_000000000416da30;  1 drivers
+L_00000000040c5150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dec6f0_0 .net8 "VGND", 0 0, L_00000000040c5150;  1 drivers, strength-aware
+L_00000000040c6420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dee770_0 .net8 "VNB", 0 0, L_00000000040c6420;  1 drivers, strength-aware
+L_00000000040c6490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dec650_0 .net8 "VPB", 0 0, L_00000000040c6490;  1 drivers, strength-aware
+L_00000000040c5540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ded0f0_0 .net8 "VPWR", 0 0, L_00000000040c5540;  1 drivers, strength-aware
+S_0000000003d13230 .scope module, "base" "sky130_fd_sc_hd__ha" 4 10453, 4 10866 1, S_00000000029165c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+L_000000000416d950 .functor AND 1, o0000000003d905b8, o0000000003d905e8, C4<1>, C4<1>;
+L_000000000416d9c0 .functor BUF 1, L_000000000416d950, C4<0>, C4<0>, C4<0>;
+L_000000000416c6f0 .functor XOR 1, o0000000003d905e8, o0000000003d905b8, C4<0>, C4<0>;
+L_000000000416da30 .functor BUF 1, L_000000000416c6f0, C4<0>, C4<0>, C4<0>;
+v0000000003debed0_0 .net "A", 0 0, o0000000003d905b8;  alias, 0 drivers
+v0000000003debf70_0 .net "B", 0 0, o0000000003d905e8;  alias, 0 drivers
+v0000000003deafd0_0 .net "COUT", 0 0, L_000000000416d9c0;  alias, 1 drivers
+v0000000003deb070_0 .net "SUM", 0 0, L_000000000416da30;  alias, 1 drivers
+L_00000000040c5a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dea350_0 .net8 "VGND", 0 0, L_00000000040c5a10;  1 drivers, strength-aware
+L_00000000040c50e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dec0b0_0 .net8 "VNB", 0 0, L_00000000040c50e0;  1 drivers, strength-aware
+L_00000000040c4970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003de99f0_0 .net8 "VPB", 0 0, L_00000000040c4970;  1 drivers, strength-aware
+L_00000000040c49e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003debd90_0 .net8 "VPWR", 0 0, L_00000000040c49e0;  1 drivers, strength-aware
+v0000000003de9c70_0 .net "and0_out_COUT", 0 0, L_000000000416d950;  1 drivers
+v0000000003dea3f0_0 .net "xor0_out_SUM", 0 0, L_000000000416c6f0;  1 drivers
+S_0000000002917640 .scope module, "sky130_fd_sc_hd__ha_2" "sky130_fd_sc_hd__ha_2" 4 10985;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+o0000000003d909d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ded870_0 .net "A", 0 0, o0000000003d909d8;  0 drivers
+o0000000003d90a08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dec3d0_0 .net "B", 0 0, o0000000003d90a08;  0 drivers
+v0000000003dec830_0 .net "COUT", 0 0, L_000000000416dbf0;  1 drivers
+v0000000003dec790_0 .net "SUM", 0 0, L_000000000416c7d0;  1 drivers
+L_00000000040c5380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dec150_0 .net8 "VGND", 0 0, L_00000000040c5380;  1 drivers, strength-aware
+L_00000000040c52a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deda50_0 .net8 "VNB", 0 0, L_00000000040c52a0;  1 drivers, strength-aware
+L_00000000040c5f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dee130_0 .net8 "VPB", 0 0, L_00000000040c5f50;  1 drivers, strength-aware
+L_00000000040c51c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dec8d0_0 .net8 "VPWR", 0 0, L_00000000040c51c0;  1 drivers, strength-aware
+S_0000000003d16830 .scope module, "base" "sky130_fd_sc_hd__ha" 4 11003, 4 10866 1, S_0000000002917640;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+L_000000000416db80 .functor AND 1, o0000000003d909d8, o0000000003d90a08, C4<1>, C4<1>;
+L_000000000416dbf0 .functor BUF 1, L_000000000416db80, C4<0>, C4<0>, C4<0>;
+L_000000000416c760 .functor XOR 1, o0000000003d90a08, o0000000003d909d8, C4<0>, C4<0>;
+L_000000000416c7d0 .functor BUF 1, L_000000000416c760, C4<0>, C4<0>, C4<0>;
+v0000000003dedb90_0 .net "A", 0 0, o0000000003d909d8;  alias, 0 drivers
+v0000000003ded9b0_0 .net "B", 0 0, o0000000003d90a08;  alias, 0 drivers
+v0000000003dedff0_0 .net "COUT", 0 0, L_000000000416dbf0;  alias, 1 drivers
+v0000000003dede10_0 .net "SUM", 0 0, L_000000000416c7d0;  alias, 1 drivers
+L_00000000040c5b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003decfb0_0 .net8 "VGND", 0 0, L_00000000040c5b60;  1 drivers, strength-aware
+L_00000000040c5bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ded7d0_0 .net8 "VNB", 0 0, L_00000000040c5bd0;  1 drivers, strength-aware
+L_00000000040c5ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dee590_0 .net8 "VPB", 0 0, L_00000000040c5ee0;  1 drivers, strength-aware
+L_00000000040c5fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003decf10_0 .net8 "VPWR", 0 0, L_00000000040c5fc0;  1 drivers, strength-aware
+v0000000003ded230_0 .net "and0_out_COUT", 0 0, L_000000000416db80;  1 drivers
+v0000000003dee270_0 .net "xor0_out_SUM", 0 0, L_000000000416c760;  1 drivers
+S_0000000002916440 .scope module, "sky130_fd_sc_hd__ha_4" "sky130_fd_sc_hd__ha_4" 4 10547;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+o0000000003d90df8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dec970_0 .net "A", 0 0, o0000000003d90df8;  0 drivers
+o0000000003d90e28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dee8b0_0 .net "B", 0 0, o0000000003d90e28;  0 drivers
+v0000000003dee310_0 .net "COUT", 0 0, L_000000000416f390;  1 drivers
+v0000000003dedd70_0 .net "SUM", 0 0, L_000000000416f010;  1 drivers
+L_00000000040c4b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dedeb0_0 .net8 "VGND", 0 0, L_00000000040c4b30;  1 drivers, strength-aware
+L_00000000040c5460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dedf50_0 .net8 "VNB", 0 0, L_00000000040c5460;  1 drivers, strength-aware
+L_00000000040c60a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dee3b0_0 .net8 "VPB", 0 0, L_00000000040c60a0;  1 drivers, strength-aware
+L_00000000040c53f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003decb50_0 .net8 "VPWR", 0 0, L_00000000040c53f0;  1 drivers, strength-aware
+S_0000000003d17130 .scope module, "base" "sky130_fd_sc_hd__ha" 4 10565, 4 10866 1, S_0000000002916440;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "COUT"
+    .port_info 1 /OUTPUT 1 "SUM"
+    .port_info 2 /INPUT 1 "A"
+    .port_info 3 /INPUT 1 "B"
+L_000000000416c840 .functor AND 1, o0000000003d90df8, o0000000003d90e28, C4<1>, C4<1>;
+L_000000000416f390 .functor BUF 1, L_000000000416c840, C4<0>, C4<0>, C4<0>;
+L_000000000416ead0 .functor XOR 1, o0000000003d90e28, o0000000003d90df8, C4<0>, C4<0>;
+L_000000000416f010 .functor BUF 1, L_000000000416ead0, C4<0>, C4<0>, C4<0>;
+v0000000003dec510_0 .net "A", 0 0, o0000000003d90df8;  alias, 0 drivers
+v0000000003dec5b0_0 .net "B", 0 0, o0000000003d90e28;  alias, 0 drivers
+v0000000003dec330_0 .net "COUT", 0 0, L_000000000416f390;  alias, 1 drivers
+v0000000003ded2d0_0 .net "SUM", 0 0, L_000000000416f010;  alias, 1 drivers
+L_00000000040c55b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003decab0_0 .net8 "VGND", 0 0, L_00000000040c55b0;  1 drivers, strength-aware
+L_00000000040c5a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dee1d0_0 .net8 "VNB", 0 0, L_00000000040c5a80;  1 drivers, strength-aware
+L_00000000040c4e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ded690_0 .net8 "VPB", 0 0, L_00000000040c4e40;  1 drivers, strength-aware
+L_00000000040c4a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deca10_0 .net8 "VPWR", 0 0, L_00000000040c4a50;  1 drivers, strength-aware
+v0000000003dedc30_0 .net "and0_out_COUT", 0 0, L_000000000416c840;  1 drivers
+v0000000003dedcd0_0 .net "xor0_out_SUM", 0 0, L_000000000416ead0;  1 drivers
+S_0000000002917040 .scope module, "sky130_fd_sc_hd__inv_1" "sky130_fd_sc_hd__inv_1" 4 53953;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d91218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003ded4b0_0 .net "A", 0 0, o0000000003d91218;  0 drivers
+L_00000000040c4c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ded370_0 .net8 "VGND", 0 0, L_00000000040c4c10;  1 drivers, strength-aware
+L_00000000040c4c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dee6d0_0 .net8 "VNB", 0 0, L_00000000040c4c80;  1 drivers, strength-aware
+L_00000000040c5cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003decc90_0 .net8 "VPB", 0 0, L_00000000040c5cb0;  1 drivers, strength-aware
+L_00000000040c57e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dee810_0 .net8 "VPWR", 0 0, L_00000000040c57e0;  1 drivers, strength-aware
+v0000000003dec1f0_0 .net "Y", 0 0, L_000000000416e050;  1 drivers
+S_0000000003d181b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 53967, 4 54841 1, S_0000000002917040;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416dfe0 .functor NOT 1, o0000000003d91218, C4<0>, C4<0>, C4<0>;
+L_000000000416e050 .functor BUF 1, L_000000000416dfe0, C4<0>, C4<0>, C4<0>;
+v0000000003dee450_0 .net "A", 0 0, o0000000003d91218;  alias, 0 drivers
+L_00000000040c6030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dee630_0 .net8 "VGND", 0 0, L_00000000040c6030;  1 drivers, strength-aware
+L_00000000040c5620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003decbf0_0 .net8 "VNB", 0 0, L_00000000040c5620;  1 drivers, strength-aware
+L_00000000040c4cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ded190_0 .net8 "VPB", 0 0, L_00000000040c4cf0;  1 drivers, strength-aware
+L_00000000040c4d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003ded910_0 .net8 "VPWR", 0 0, L_00000000040c4d60;  1 drivers, strength-aware
+v0000000003dec470_0 .net "Y", 0 0, L_000000000416e050;  alias, 1 drivers
+v0000000003ded5f0_0 .net "not0_out_Y", 0 0, L_000000000416dfe0;  1 drivers
+S_0000000002917340 .scope module, "sky130_fd_sc_hd__inv_12" "sky130_fd_sc_hd__inv_12" 4 54553;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d914e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003defc10_0 .net "A", 0 0, o0000000003d914e8;  0 drivers
+L_00000000040c4f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df0250_0 .net8 "VGND", 0 0, L_00000000040c4f20;  1 drivers, strength-aware
+L_00000000040c4f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def670_0 .net8 "VNB", 0 0, L_00000000040c4f90;  1 drivers, strength-aware
+L_00000000040c5690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0cf0_0 .net8 "VPB", 0 0, L_00000000040c5690;  1 drivers, strength-aware
+L_00000000040c5930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0890_0 .net8 "VPWR", 0 0, L_00000000040c5930;  1 drivers, strength-aware
+v0000000003df1010_0 .net "Y", 0 0, L_000000000416e7c0;  1 drivers
+S_0000000003d18330 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54567, 4 54841 1, S_0000000002917340;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416e0c0 .functor NOT 1, o0000000003d914e8, C4<0>, C4<0>, C4<0>;
+L_000000000416e7c0 .functor BUF 1, L_000000000416e0c0, C4<0>, C4<0>, C4<0>;
+v0000000003ded050_0 .net "A", 0 0, o0000000003d914e8;  alias, 0 drivers
+L_00000000040c5af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dec290_0 .net8 "VGND", 0 0, L_00000000040c5af0;  1 drivers, strength-aware
+L_00000000040c5c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003ded550_0 .net8 "VNB", 0 0, L_00000000040c5c40;  1 drivers, strength-aware
+L_00000000040c5e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003decd30_0 .net8 "VPB", 0 0, L_00000000040c5e00;  1 drivers, strength-aware
+L_00000000040c6110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003decdd0_0 .net8 "VPWR", 0 0, L_00000000040c6110;  1 drivers, strength-aware
+v0000000003dece70_0 .net "Y", 0 0, L_000000000416e7c0;  alias, 1 drivers
+v0000000003ded410_0 .net "not0_out_Y", 0 0, L_000000000416e0c0;  1 drivers
+S_0000000002915fc0 .scope module, "sky130_fd_sc_hd__inv_16" "sky130_fd_sc_hd__inv_16" 4 54253;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d917b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df0390_0 .net "A", 0 0, o0000000003d917b8;  0 drivers
+L_00000000040c6180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df0430_0 .net8 "VGND", 0 0, L_00000000040c6180;  1 drivers, strength-aware
+L_00000000040c61f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def030_0 .net8 "VNB", 0 0, L_00000000040c61f0;  1 drivers, strength-aware
+L_00000000040c6c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003defdf0_0 .net8 "VPB", 0 0, L_00000000040c6c00;  1 drivers, strength-aware
+L_00000000040c66c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dee9f0_0 .net8 "VPWR", 0 0, L_00000000040c66c0;  1 drivers, strength-aware
+v0000000003deed10_0 .net "Y", 0 0, L_000000000416e590;  1 drivers
+S_0000000003d184b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54267, 4 54841 1, S_0000000002915fc0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416ed70 .functor NOT 1, o0000000003d917b8, C4<0>, C4<0>, C4<0>;
+L_000000000416e590 .functor BUF 1, L_000000000416ed70, C4<0>, C4<0>, C4<0>;
+v0000000003df09d0_0 .net "A", 0 0, o0000000003d917b8;  alias, 0 drivers
+L_00000000040c7a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df0ed0_0 .net8 "VGND", 0 0, L_00000000040c7a70;  1 drivers, strength-aware
+L_00000000040c6500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df04d0_0 .net8 "VNB", 0 0, L_00000000040c6500;  1 drivers, strength-aware
+L_00000000040c7300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003defad0_0 .net8 "VPB", 0 0, L_00000000040c7300;  1 drivers, strength-aware
+L_00000000040c6ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df02f0_0 .net8 "VPWR", 0 0, L_00000000040c6ab0;  1 drivers, strength-aware
+v0000000003dee950_0 .net "Y", 0 0, L_000000000416e590;  alias, 1 drivers
+v0000000003df0930_0 .net "not0_out_Y", 0 0, L_000000000416ed70;  1 drivers
+S_0000000002916a40 .scope module, "sky130_fd_sc_hd__inv_4" "sky130_fd_sc_hd__inv_4" 4 54353;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d91a88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df0610_0 .net "A", 0 0, o0000000003d91a88;  0 drivers
+L_00000000040c7450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def710_0 .net8 "VGND", 0 0, L_00000000040c7450;  1 drivers, strength-aware
+L_00000000040c69d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df06b0_0 .net8 "VNB", 0 0, L_00000000040c69d0;  1 drivers, strength-aware
+L_00000000040c70d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003def990_0 .net8 "VPB", 0 0, L_00000000040c70d0;  1 drivers, strength-aware
+L_00000000040c67a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0e30_0 .net8 "VPWR", 0 0, L_00000000040c67a0;  1 drivers, strength-aware
+v0000000003df0b10_0 .net "Y", 0 0, L_000000000416f710;  1 drivers
+S_0000000003d133b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54367, 4 54841 1, S_0000000002916a40;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416e130 .functor NOT 1, o0000000003d91a88, C4<0>, C4<0>, C4<0>;
+L_000000000416f710 .functor BUF 1, L_000000000416e130, C4<0>, C4<0>, C4<0>;
+v0000000003deec70_0 .net "A", 0 0, o0000000003d91a88;  alias, 0 drivers
+L_00000000040c7370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003defe90_0 .net8 "VGND", 0 0, L_00000000040c7370;  1 drivers, strength-aware
+L_00000000040c6e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df0d90_0 .net8 "VNB", 0 0, L_00000000040c6e30;  1 drivers, strength-aware
+L_00000000040c7990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deff30_0 .net8 "VPB", 0 0, L_00000000040c7990;  1 drivers, strength-aware
+L_00000000040c74c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0a70_0 .net8 "VPWR", 0 0, L_00000000040c74c0;  1 drivers, strength-aware
+v0000000003df0750_0 .net "Y", 0 0, L_000000000416f710;  alias, 1 drivers
+v0000000003df0570_0 .net "not0_out_Y", 0 0, L_000000000416e130;  1 drivers
+S_00000000029174c0 .scope module, "sky130_fd_sc_hd__inv_6" "sky130_fd_sc_hd__inv_6" 4 54153;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d91d58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003def490_0 .net "A", 0 0, o0000000003d91d58;  0 drivers
+L_00000000040c6d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df0bb0_0 .net8 "VGND", 0 0, L_00000000040c6d50;  1 drivers, strength-aware
+L_00000000040c7fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deffd0_0 .net8 "VNB", 0 0, L_00000000040c7fb0;  1 drivers, strength-aware
+L_00000000040c8090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0c50_0 .net8 "VPB", 0 0, L_00000000040c8090;  1 drivers, strength-aware
+L_00000000040c7140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deea90_0 .net8 "VPWR", 0 0, L_00000000040c7140;  1 drivers, strength-aware
+v0000000003deeb30_0 .net "Y", 0 0, L_000000000416e520;  1 drivers
+S_0000000003d13830 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54167, 4 54841 1, S_00000000029174c0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f160 .functor NOT 1, o0000000003d91d58, C4<0>, C4<0>, C4<0>;
+L_000000000416e520 .functor BUF 1, L_000000000416f160, C4<0>, C4<0>, C4<0>;
+v0000000003df0f70_0 .net "A", 0 0, o0000000003d91d58;  alias, 0 drivers
+L_00000000040c7610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003defcb0_0 .net8 "VGND", 0 0, L_00000000040c7610;  1 drivers, strength-aware
+L_00000000040c6ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003defb70_0 .net8 "VNB", 0 0, L_00000000040c6ce0;  1 drivers, strength-aware
+L_00000000040c6570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df01b0_0 .net8 "VPB", 0 0, L_00000000040c6570;  1 drivers, strength-aware
+L_00000000040c65e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df10b0_0 .net8 "VPWR", 0 0, L_00000000040c65e0;  1 drivers, strength-aware
+v0000000003deedb0_0 .net "Y", 0 0, L_000000000416e520;  alias, 1 drivers
+v0000000003df07f0_0 .net "not0_out_Y", 0 0, L_000000000416f160;  1 drivers
+S_0000000002917940 .scope module, "sky130_fd_sc_hd__inv_8" "sky130_fd_sc_hd__inv_8" 4 54453;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d92028 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003deef90_0 .net "A", 0 0, o0000000003d92028;  0 drivers
+L_00000000040c6f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def0d0_0 .net8 "VGND", 0 0, L_00000000040c6f80;  1 drivers, strength-aware
+L_00000000040c6ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def170_0 .net8 "VNB", 0 0, L_00000000040c6ea0;  1 drivers, strength-aware
+L_00000000040c7b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003def210_0 .net8 "VPB", 0 0, L_00000000040c7b50;  1 drivers, strength-aware
+L_00000000040c6dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003def530_0 .net8 "VPWR", 0 0, L_00000000040c6dc0;  1 drivers, strength-aware
+v0000000003def2b0_0 .net "Y", 0 0, L_000000000416e9f0;  1 drivers
+S_0000000003d19e30 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54467, 4 54841 1, S_0000000002917940;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416df00 .functor NOT 1, o0000000003d92028, C4<0>, C4<0>, C4<0>;
+L_000000000416e9f0 .functor BUF 1, L_000000000416df00, C4<0>, C4<0>, C4<0>;
+v0000000003def8f0_0 .net "A", 0 0, o0000000003d92028;  alias, 0 drivers
+L_00000000040c7760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003defd50_0 .net8 "VGND", 0 0, L_00000000040c7760;  1 drivers, strength-aware
+L_00000000040c77d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003deebd0_0 .net8 "VNB", 0 0, L_00000000040c77d0;  1 drivers, strength-aware
+L_00000000040c6f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003deee50_0 .net8 "VPB", 0 0, L_00000000040c6f10;  1 drivers, strength-aware
+L_00000000040c6ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df0070_0 .net8 "VPWR", 0 0, L_00000000040c6ff0;  1 drivers, strength-aware
+v0000000003deeef0_0 .net "Y", 0 0, L_000000000416e9f0;  alias, 1 drivers
+v0000000003df0110_0 .net "not0_out_Y", 0 0, L_000000000416df00;  1 drivers
+S_0000000002916140 .scope module, "sky130_fd_sc_hd__lpflow_bleeder_1" "sky130_fd_sc_hd__lpflow_bleeder_1" 4 74255;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "SHORT"
+o0000000003d922f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003def3f0_0 .net "SHORT", 0 0, o0000000003d922f8;  0 drivers
+L_00000000040c7ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def5d0_0 .net8 "VGND", 0 0, L_00000000040c7ae0;  1 drivers, strength-aware
+L_00000000040c7bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003def7b0_0 .net8 "VNB", 0 0, L_00000000040c7bc0;  1 drivers, strength-aware
+L_00000000040c7d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003def850_0 .net8 "VPB", 0 0, L_00000000040c7d80;  1 drivers, strength-aware
+S_0000000003d1b330 .scope module, "base" "sky130_fd_sc_hd__lpflow_bleeder" 4 74267, 4 74479 1, S_0000000002916140;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "SHORT"
+v0000000003def350_0 .net "SHORT", 0 0, o0000000003d922f8;  alias, 0 drivers
+S_000000000284b060 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_1" "sky130_fd_sc_hd__lpflow_clkbufkapwr_1" 4 7217;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d92418 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df2cd0_0 .net "A", 0 0, o0000000003d92418;  0 drivers
+L_00000000040c7680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df22d0_0 .net8 "KAPWR", 0 0, L_00000000040c7680;  1 drivers, strength-aware
+L_00000000040c7c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1f10_0 .net8 "VGND", 0 0, L_00000000040c7c30;  1 drivers, strength-aware
+L_00000000040c7df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df31d0_0 .net8 "VNB", 0 0, L_00000000040c7df0;  1 drivers, strength-aware
+L_00000000040c7ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df15b0_0 .net8 "VPB", 0 0, L_00000000040c7ca0;  1 drivers, strength-aware
+L_00000000040c7060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1d30_0 .net8 "VPWR", 0 0, L_00000000040c7060;  1 drivers, strength-aware
+v0000000003df1fb0_0 .net "X", 0 0, L_000000000416eb40;  1 drivers
+S_0000000003d1eab0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7232, 4 7510 1, S_000000000284b060;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f6a0 .functor BUF 1, o0000000003d92418, C4<0>, C4<0>, C4<0>;
+L_000000000416eb40 .functor BUF 1, L_000000000416f6a0, C4<0>, C4<0>, C4<0>;
+v0000000003defa30_0 .net "A", 0 0, o0000000003d92418;  alias, 0 drivers
+L_00000000040c6b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3630_0 .net8 "KAPWR", 0 0, L_00000000040c6b90;  1 drivers, strength-aware
+L_00000000040c7d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1150_0 .net8 "VGND", 0 0, L_00000000040c7d10;  1 drivers, strength-aware
+L_00000000040c7840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df29b0_0 .net8 "VNB", 0 0, L_00000000040c7840;  1 drivers, strength-aware
+L_00000000040c71b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1dd0_0 .net8 "VPB", 0 0, L_00000000040c71b0;  1 drivers, strength-aware
+L_00000000040c7e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1790_0 .net8 "VPWR", 0 0, L_00000000040c7e60;  1 drivers, strength-aware
+v0000000003df11f0_0 .net "X", 0 0, L_000000000416eb40;  alias, 1 drivers
+v0000000003df1e70_0 .net "buf0_out_X", 0 0, L_000000000416f6a0;  1 drivers
+S_000000000284a760 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_16" "sky130_fd_sc_hd__lpflow_clkbufkapwr_16" 4 7113;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d92748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df2ff0_0 .net "A", 0 0, o0000000003d92748;  0 drivers
+L_00000000040c7220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df13d0_0 .net8 "KAPWR", 0 0, L_00000000040c7220;  1 drivers, strength-aware
+L_00000000040c76f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df2d70_0 .net8 "VGND", 0 0, L_00000000040c76f0;  1 drivers, strength-aware
+L_00000000040c6b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1b50_0 .net8 "VNB", 0 0, L_00000000040c6b20;  1 drivers, strength-aware
+L_00000000040c6a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2b90_0 .net8 "VPB", 0 0, L_00000000040c6a40;  1 drivers, strength-aware
+L_00000000040c7290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2230_0 .net8 "VPWR", 0 0, L_00000000040c7290;  1 drivers, strength-aware
+v0000000003df16f0_0 .net "X", 0 0, L_000000000416f550;  1 drivers
+S_0000000003d1a130 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7128, 4 7510 1, S_000000000284a760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416eec0 .functor BUF 1, o0000000003d92748, C4<0>, C4<0>, C4<0>;
+L_000000000416f550 .functor BUF 1, L_000000000416eec0, C4<0>, C4<0>, C4<0>;
+v0000000003df1290_0 .net "A", 0 0, o0000000003d92748;  alias, 0 drivers
+L_00000000040c6810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1510_0 .net8 "KAPWR", 0 0, L_00000000040c6810;  1 drivers, strength-aware
+L_00000000040c73e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1650_0 .net8 "VGND", 0 0, L_00000000040c73e0;  1 drivers, strength-aware
+L_00000000040c78b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df2190_0 .net8 "VNB", 0 0, L_00000000040c78b0;  1 drivers, strength-aware
+L_00000000040c7530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df20f0_0 .net8 "VPB", 0 0, L_00000000040c7530;  1 drivers, strength-aware
+L_00000000040c8020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2050_0 .net8 "VPWR", 0 0, L_00000000040c8020;  1 drivers, strength-aware
+v0000000003df2690_0 .net "X", 0 0, L_000000000416f550;  alias, 1 drivers
+v0000000003df1970_0 .net "buf0_out_X", 0 0, L_000000000416eec0;  1 drivers
+S_000000000284d8e0 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_2" "sky130_fd_sc_hd__lpflow_clkbufkapwr_2" 4 7724;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d92a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df1470_0 .net "A", 0 0, o0000000003d92a78;  0 drivers
+L_00000000040c6880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3270_0 .net8 "KAPWR", 0 0, L_00000000040c6880;  1 drivers, strength-aware
+L_00000000040c7ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1830_0 .net8 "VGND", 0 0, L_00000000040c7ed0;  1 drivers, strength-aware
+L_00000000040c6650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3090_0 .net8 "VNB", 0 0, L_00000000040c6650;  1 drivers, strength-aware
+L_00000000040c75a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2e10_0 .net8 "VPB", 0 0, L_00000000040c75a0;  1 drivers, strength-aware
+L_00000000040c7a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2af0_0 .net8 "VPWR", 0 0, L_00000000040c7a00;  1 drivers, strength-aware
+v0000000003df3130_0 .net "X", 0 0, L_000000000416f2b0;  1 drivers
+S_0000000003d1b7b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7739, 4 7510 1, S_000000000284d8e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f5c0 .functor BUF 1, o0000000003d92a78, C4<0>, C4<0>, C4<0>;
+L_000000000416f2b0 .functor BUF 1, L_000000000416f5c0, C4<0>, C4<0>, C4<0>;
+v0000000003df1330_0 .net "A", 0 0, o0000000003d92a78;  alias, 0 drivers
+L_00000000040c6730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2370_0 .net8 "KAPWR", 0 0, L_00000000040c6730;  1 drivers, strength-aware
+L_00000000040c7f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df36d0_0 .net8 "VGND", 0 0, L_00000000040c7f40;  1 drivers, strength-aware
+L_00000000040c7920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3770_0 .net8 "VNB", 0 0, L_00000000040c7920;  1 drivers, strength-aware
+L_00000000040c68f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1a10_0 .net8 "VPB", 0 0, L_00000000040c68f0;  1 drivers, strength-aware
+L_00000000040c6960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2410_0 .net8 "VPWR", 0 0, L_00000000040c6960;  1 drivers, strength-aware
+v0000000003df24b0_0 .net "X", 0 0, L_000000000416f2b0;  alias, 1 drivers
+v0000000003df2a50_0 .net "buf0_out_X", 0 0, L_000000000416f5c0;  1 drivers
+S_000000000284b1e0 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_4" "sky130_fd_sc_hd__lpflow_clkbufkapwr_4" 4 7828;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d92da8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df3450_0 .net "A", 0 0, o0000000003d92da8;  0 drivers
+L_00000000040c6c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2eb0_0 .net8 "KAPWR", 0 0, L_00000000040c6c70;  1 drivers, strength-aware
+L_00000000040c8b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df2730_0 .net8 "VGND", 0 0, L_00000000040c8b80;  1 drivers, strength-aware
+L_00000000040c8170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df34f0_0 .net8 "VNB", 0 0, L_00000000040c8170;  1 drivers, strength-aware
+L_00000000040c85d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df27d0_0 .net8 "VPB", 0 0, L_00000000040c85d0;  1 drivers, strength-aware
+L_00000000040c96e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2870_0 .net8 "VPWR", 0 0, L_00000000040c96e0;  1 drivers, strength-aware
+v0000000003df2f50_0 .net "X", 0 0, L_000000000416ebb0;  1 drivers
+S_0000000003d1d5b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7843, 4 7510 1, S_000000000284b1e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f8d0 .functor BUF 1, o0000000003d92da8, C4<0>, C4<0>, C4<0>;
+L_000000000416ebb0 .functor BUF 1, L_000000000416f8d0, C4<0>, C4<0>, C4<0>;
+v0000000003df18d0_0 .net "A", 0 0, o0000000003d92da8;  alias, 0 drivers
+L_00000000040c97c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df1ab0_0 .net8 "KAPWR", 0 0, L_00000000040c97c0;  1 drivers, strength-aware
+L_00000000040c9050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1c90_0 .net8 "VGND", 0 0, L_00000000040c9050;  1 drivers, strength-aware
+L_00000000040c9ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df1bf0_0 .net8 "VNB", 0 0, L_00000000040c9ad0;  1 drivers, strength-aware
+L_00000000040c8f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3310_0 .net8 "VPB", 0 0, L_00000000040c8f70;  1 drivers, strength-aware
+L_00000000040c89c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2550_0 .net8 "VPWR", 0 0, L_00000000040c89c0;  1 drivers, strength-aware
+v0000000003df33b0_0 .net "X", 0 0, L_000000000416ebb0;  alias, 1 drivers
+v0000000003df25f0_0 .net "buf0_out_X", 0 0, L_000000000416f8d0;  1 drivers
+S_0000000002849fe0 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_8" "sky130_fd_sc_hd__lpflow_clkbufkapwr_8" 4 7620;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d930d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df4f30_0 .net "A", 0 0, o0000000003d930d8;  0 drivers
+L_00000000040c9910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5cf0_0 .net8 "KAPWR", 0 0, L_00000000040c9910;  1 drivers, strength-aware
+L_00000000040c9440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df4df0_0 .net8 "VGND", 0 0, L_00000000040c9440;  1 drivers, strength-aware
+L_00000000040c8cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df45d0_0 .net8 "VNB", 0 0, L_00000000040c8cd0;  1 drivers, strength-aware
+L_00000000040c9830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5750_0 .net8 "VPB", 0 0, L_00000000040c9830;  1 drivers, strength-aware
+L_00000000040c9b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5e30_0 .net8 "VPWR", 0 0, L_00000000040c9b40;  1 drivers, strength-aware
+v0000000003df4350_0 .net "X", 0 0, L_000000000416f630;  1 drivers
+S_0000000003d1d2b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7635, 4 7510 1, S_0000000002849fe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f4e0 .functor BUF 1, o0000000003d930d8, C4<0>, C4<0>, C4<0>;
+L_000000000416f630 .functor BUF 1, L_000000000416f4e0, C4<0>, C4<0>, C4<0>;
+v0000000003df3590_0 .net "A", 0 0, o0000000003d930d8;  alias, 0 drivers
+L_00000000040c8100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df2910_0 .net8 "KAPWR", 0 0, L_00000000040c8100;  1 drivers, strength-aware
+L_00000000040c8410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df2c30_0 .net8 "VGND", 0 0, L_00000000040c8410;  1 drivers, strength-aware
+L_00000000040c9bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3810_0 .net8 "VNB", 0 0, L_00000000040c9bb0;  1 drivers, strength-aware
+L_00000000040c8640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df38b0_0 .net8 "VPB", 0 0, L_00000000040c8640;  1 drivers, strength-aware
+L_00000000040c8800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4e90_0 .net8 "VPWR", 0 0, L_00000000040c8800;  1 drivers, strength-aware
+v0000000003df4990_0 .net "X", 0 0, L_000000000416f630;  alias, 1 drivers
+v0000000003df48f0_0 .net "buf0_out_X", 0 0, L_000000000416f4e0;  1 drivers
+S_000000000284b660 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_1" "sky130_fd_sc_hd__lpflow_clkinvkapwr_1" 4 60782;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d93408 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df4670_0 .net "A", 0 0, o0000000003d93408;  0 drivers
+L_00000000040c9c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6010_0 .net8 "KAPWR", 0 0, L_00000000040c9c20;  1 drivers, strength-aware
+L_00000000040c9750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df60b0_0 .net8 "VGND", 0 0, L_00000000040c9750;  1 drivers, strength-aware
+L_00000000040c8720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df54d0_0 .net8 "VNB", 0 0, L_00000000040c8720;  1 drivers, strength-aware
+L_00000000040c9670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3950_0 .net8 "VPB", 0 0, L_00000000040c9670;  1 drivers, strength-aware
+L_00000000040c90c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4490_0 .net8 "VPWR", 0 0, L_00000000040c90c0;  1 drivers, strength-aware
+v0000000003df57f0_0 .net "Y", 0 0, L_000000000416ddb0;  1 drivers
+S_0000000003d1b030 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60797, 4 60360 1, S_000000000284b660;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416de20 .functor NOT 1, o0000000003d93408, C4<0>, C4<0>, C4<0>;
+L_000000000416ddb0 .functor BUF 1, L_000000000416de20, C4<0>, C4<0>, C4<0>;
+v0000000003df5a70_0 .net "A", 0 0, o0000000003d93408;  alias, 0 drivers
+L_00000000040c9c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5ed0_0 .net8 "KAPWR", 0 0, L_00000000040c9c90;  1 drivers, strength-aware
+L_00000000040c9520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df5b10_0 .net8 "VGND", 0 0, L_00000000040c9520;  1 drivers, strength-aware
+L_00000000040c8480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df5570_0 .net8 "VNB", 0 0, L_00000000040c8480;  1 drivers, strength-aware
+L_00000000040c84f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3db0_0 .net8 "VPB", 0 0, L_00000000040c84f0;  1 drivers, strength-aware
+L_00000000040c8e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df47b0_0 .net8 "VPWR", 0 0, L_00000000040c8e90;  1 drivers, strength-aware
+v0000000003df5f70_0 .net "Y", 0 0, L_000000000416ddb0;  alias, 1 drivers
+v0000000003df4210_0 .net "not0_out_Y", 0 0, L_000000000416de20;  1 drivers
+S_000000000284d760 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_16" "sky130_fd_sc_hd__lpflow_clkinvkapwr_16" 4 60678;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d93738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df5930_0 .net "A", 0 0, o0000000003d93738;  0 drivers
+L_00000000040c98a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4c10_0 .net8 "KAPWR", 0 0, L_00000000040c98a0;  1 drivers, strength-aware
+L_00000000040c94b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df5610_0 .net8 "VGND", 0 0, L_00000000040c94b0;  1 drivers, strength-aware
+L_00000000040c81e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df4a30_0 .net8 "VNB", 0 0, L_00000000040c81e0;  1 drivers, strength-aware
+L_00000000040c9590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df40d0_0 .net8 "VPB", 0 0, L_00000000040c9590;  1 drivers, strength-aware
+L_00000000040c8e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5110_0 .net8 "VPWR", 0 0, L_00000000040c8e20;  1 drivers, strength-aware
+v0000000003df5bb0_0 .net "Y", 0 0, L_000000000416e8a0;  1 drivers
+S_0000000003d1ccb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60693, 4 60360 1, S_000000000284d760;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416e1a0 .functor NOT 1, o0000000003d93738, C4<0>, C4<0>, C4<0>;
+L_000000000416e8a0 .functor BUF 1, L_000000000416e1a0, C4<0>, C4<0>, C4<0>;
+v0000000003df52f0_0 .net "A", 0 0, o0000000003d93738;  alias, 0 drivers
+L_00000000040c88e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5d90_0 .net8 "KAPWR", 0 0, L_00000000040c88e0;  1 drivers, strength-aware
+L_00000000040c8aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3e50_0 .net8 "VGND", 0 0, L_00000000040c8aa0;  1 drivers, strength-aware
+L_00000000040c8250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3c70_0 .net8 "VNB", 0 0, L_00000000040c8250;  1 drivers, strength-aware
+L_00000000040c86b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5390_0 .net8 "VPB", 0 0, L_00000000040c86b0;  1 drivers, strength-aware
+L_00000000040c9980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4710_0 .net8 "VPWR", 0 0, L_00000000040c9980;  1 drivers, strength-aware
+v0000000003df42b0_0 .net "Y", 0 0, L_000000000416e8a0;  alias, 1 drivers
+v0000000003df59d0_0 .net "not0_out_Y", 0 0, L_000000000416e1a0;  1 drivers
+S_000000000284aee0 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_2" "sky130_fd_sc_hd__lpflow_clkinvkapwr_2" 4 60067;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d93a68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df4530_0 .net "A", 0 0, o0000000003d93a68;  0 drivers
+L_00000000040c99f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df56b0_0 .net8 "KAPWR", 0 0, L_00000000040c99f0;  1 drivers, strength-aware
+L_00000000040c9130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df3a90_0 .net8 "VGND", 0 0, L_00000000040c9130;  1 drivers, strength-aware
+L_00000000040c82c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df4850_0 .net8 "VNB", 0 0, L_00000000040c82c0;  1 drivers, strength-aware
+L_00000000040c8fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5890_0 .net8 "VPB", 0 0, L_00000000040c8fe0;  1 drivers, strength-aware
+L_00000000040c8a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4cb0_0 .net8 "VPWR", 0 0, L_00000000040c8a30;  1 drivers, strength-aware
+v0000000003df4d50_0 .net "Y", 0 0, L_000000000416ec20;  1 drivers
+S_0000000003d1b930 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60082, 4 60360 1, S_000000000284aee0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416dd40 .functor NOT 1, o0000000003d93a68, C4<0>, C4<0>, C4<0>;
+L_000000000416ec20 .functor BUF 1, L_000000000416dd40, C4<0>, C4<0>, C4<0>;
+v0000000003df4030_0 .net "A", 0 0, o0000000003d93a68;  alias, 0 drivers
+L_00000000040c9a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4ad0_0 .net8 "KAPWR", 0 0, L_00000000040c9a60;  1 drivers, strength-aware
+L_00000000040c9600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df43f0_0 .net8 "VGND", 0 0, L_00000000040c9600;  1 drivers, strength-aware
+L_00000000040c8d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df5c50_0 .net8 "VNB", 0 0, L_00000000040c8d40;  1 drivers, strength-aware
+L_00000000040c8330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4170_0 .net8 "VPB", 0 0, L_00000000040c8330;  1 drivers, strength-aware
+L_00000000040c83a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df3ef0_0 .net8 "VPWR", 0 0, L_00000000040c83a0;  1 drivers, strength-aware
+v0000000003df39f0_0 .net "Y", 0 0, L_000000000416ec20;  alias, 1 drivers
+v0000000003df4b70_0 .net "not0_out_Y", 0 0, L_000000000416dd40;  1 drivers
+S_000000000284b360 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_4" "sky130_fd_sc_hd__lpflow_clkinvkapwr_4" 4 60470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d93d98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df3f90_0 .net "A", 0 0, o0000000003d93d98;  0 drivers
+L_00000000040c8560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7e10_0 .net8 "KAPWR", 0 0, L_00000000040c8560;  1 drivers, strength-aware
+L_00000000040c8790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6dd0_0 .net8 "VGND", 0 0, L_00000000040c8790;  1 drivers, strength-aware
+L_00000000040c8870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6790_0 .net8 "VNB", 0 0, L_00000000040c8870;  1 drivers, strength-aware
+L_00000000040c8950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6150_0 .net8 "VPB", 0 0, L_00000000040c8950;  1 drivers, strength-aware
+L_00000000040c8b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6e70_0 .net8 "VPWR", 0 0, L_00000000040c8b10;  1 drivers, strength-aware
+v0000000003df7eb0_0 .net "Y", 0 0, L_000000000416de90;  1 drivers
+S_0000000003d1bab0 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60485, 4 60360 1, S_000000000284b360;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416e360 .functor NOT 1, o0000000003d93d98, C4<0>, C4<0>, C4<0>;
+L_000000000416de90 .functor BUF 1, L_000000000416e360, C4<0>, C4<0>, C4<0>;
+v0000000003df3b30_0 .net "A", 0 0, o0000000003d93d98;  alias, 0 drivers
+L_00000000040c8bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df4fd0_0 .net8 "KAPWR", 0 0, L_00000000040c8bf0;  1 drivers, strength-aware
+L_00000000040c8c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df51b0_0 .net8 "VGND", 0 0, L_00000000040c8c60;  1 drivers, strength-aware
+L_00000000040c8db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df5430_0 .net8 "VNB", 0 0, L_00000000040c8db0;  1 drivers, strength-aware
+L_00000000040c8f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5070_0 .net8 "VPB", 0 0, L_00000000040c8f00;  1 drivers, strength-aware
+L_00000000040c91a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df5250_0 .net8 "VPWR", 0 0, L_00000000040c91a0;  1 drivers, strength-aware
+v0000000003df3d10_0 .net "Y", 0 0, L_000000000416de90;  alias, 1 drivers
+v0000000003df3bd0_0 .net "not0_out_Y", 0 0, L_000000000416e360;  1 drivers
+S_000000000284a2e0 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_8" "sky130_fd_sc_hd__lpflow_clkinvkapwr_8" 4 60574;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d940c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df8090_0 .net "A", 0 0, o0000000003d940c8;  0 drivers
+L_00000000040c9210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8770_0 .net8 "KAPWR", 0 0, L_00000000040c9210;  1 drivers, strength-aware
+L_00000000040c9280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7730_0 .net8 "VGND", 0 0, L_00000000040c9280;  1 drivers, strength-aware
+L_00000000040c92f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8630_0 .net8 "VNB", 0 0, L_00000000040c92f0;  1 drivers, strength-aware
+L_00000000040c9360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df72d0_0 .net8 "VPB", 0 0, L_00000000040c9360;  1 drivers, strength-aware
+L_00000000040c93d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7f50_0 .net8 "VPWR", 0 0, L_00000000040c93d0;  1 drivers, strength-aware
+v0000000003df7370_0 .net "Y", 0 0, L_000000000416f080;  1 drivers
+S_0000000003d1bc30 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60589, 4 60360 1, S_000000000284a2e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f7f0 .functor NOT 1, o0000000003d940c8, C4<0>, C4<0>, C4<0>;
+L_000000000416f080 .functor BUF 1, L_000000000416f7f0, C4<0>, C4<0>, C4<0>;
+v0000000003df61f0_0 .net "A", 0 0, o0000000003d940c8;  alias, 0 drivers
+L_00000000040cb3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df65b0_0 .net8 "KAPWR", 0 0, L_00000000040cb3c0;  1 drivers, strength-aware
+L_00000000040cb040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6d30_0 .net8 "VGND", 0 0, L_00000000040cb040;  1 drivers, strength-aware
+L_00000000040cb820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7050_0 .net8 "VNB", 0 0, L_00000000040cb820;  1 drivers, strength-aware
+L_00000000040cb120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df70f0_0 .net8 "VPB", 0 0, L_00000000040cb120;  1 drivers, strength-aware
+L_00000000040caa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6970_0 .net8 "VPWR", 0 0, L_00000000040caa20;  1 drivers, strength-aware
+v0000000003df7870_0 .net "Y", 0 0, L_000000000416f080;  alias, 1 drivers
+v0000000003df75f0_0 .net "not0_out_Y", 0 0, L_000000000416f7f0;  1 drivers
+S_000000000284cce0 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_12" "sky130_fd_sc_hd__lpflow_decapkapwr_12" 4 157;
+ .timescale -9 -12;
+L_00000000040ca4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df81d0_0 .net8 "KAPWR", 0 0, L_00000000040ca4e0;  1 drivers, strength-aware
+L_00000000040ca6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7c30_0 .net8 "VGND", 0 0, L_00000000040ca6a0;  1 drivers, strength-aware
+L_00000000040cb430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7a50_0 .net8 "VNB", 0 0, L_00000000040cb430;  1 drivers, strength-aware
+L_00000000040ca630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7b90_0 .net8 "VPB", 0 0, L_00000000040ca630;  1 drivers, strength-aware
+L_00000000040ca390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7190_0 .net8 "VPWR", 0 0, L_00000000040ca390;  1 drivers, strength-aware
+S_0000000003d1cb30 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 165, 4 580 1, S_000000000284cce0;
+ .timescale -9 -12;
+L_00000000040cb4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6f10_0 .net8 "KAPWR", 0 0, L_00000000040cb4a0;  1 drivers, strength-aware
+L_00000000040caf60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7ff0_0 .net8 "VGND", 0 0, L_00000000040caf60;  1 drivers, strength-aware
+L_00000000040ca780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7d70_0 .net8 "VNB", 0 0, L_00000000040ca780;  1 drivers, strength-aware
+L_00000000040cb350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df84f0_0 .net8 "VPB", 0 0, L_00000000040cb350;  1 drivers, strength-aware
+L_00000000040ca7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6fb0_0 .net8 "VPWR", 0 0, L_00000000040ca7f0;  1 drivers, strength-aware
+S_000000000284da60 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_3" "sky130_fd_sc_hd__lpflow_decapkapwr_3" 4 247;
+ .timescale -9 -12;
+L_00000000040cae10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df74b0_0 .net8 "KAPWR", 0 0, L_00000000040cae10;  1 drivers, strength-aware
+L_00000000040ca320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6330_0 .net8 "VGND", 0 0, L_00000000040ca320;  1 drivers, strength-aware
+L_00000000040ca240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df79b0_0 .net8 "VNB", 0 0, L_00000000040ca240;  1 drivers, strength-aware
+L_00000000040ca550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8130_0 .net8 "VPB", 0 0, L_00000000040ca550;  1 drivers, strength-aware
+L_00000000040ca010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7550_0 .net8 "VPWR", 0 0, L_00000000040ca010;  1 drivers, strength-aware
+S_0000000003d19b30 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 255, 4 580 1, S_000000000284da60;
+ .timescale -9 -12;
+L_00000000040ca710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6290_0 .net8 "KAPWR", 0 0, L_00000000040ca710;  1 drivers, strength-aware
+L_00000000040caef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6510_0 .net8 "VGND", 0 0, L_00000000040caef0;  1 drivers, strength-aware
+L_00000000040ca860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6650_0 .net8 "VNB", 0 0, L_00000000040ca860;  1 drivers, strength-aware
+L_00000000040cb890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7230_0 .net8 "VPB", 0 0, L_00000000040cb890;  1 drivers, strength-aware
+L_00000000040c9fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7410_0 .net8 "VPWR", 0 0, L_00000000040c9fa0;  1 drivers, strength-aware
+S_000000000284ce60 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_4" "sky130_fd_sc_hd__lpflow_decapkapwr_4" 4 336;
+ .timescale -9 -12;
+L_00000000040cb5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df86d0_0 .net8 "KAPWR", 0 0, L_00000000040cb5f0;  1 drivers, strength-aware
+L_00000000040c9d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8450_0 .net8 "VGND", 0 0, L_00000000040c9d00;  1 drivers, strength-aware
+L_00000000040ca940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8590_0 .net8 "VNB", 0 0, L_00000000040ca940;  1 drivers, strength-aware
+L_00000000040cb190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df77d0_0 .net8 "VPB", 0 0, L_00000000040cb190;  1 drivers, strength-aware
+L_00000000040c9ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df7910_0 .net8 "VPWR", 0 0, L_00000000040c9ec0;  1 drivers, strength-aware
+S_0000000003d1aeb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 344, 4 580 1, S_000000000284ce60;
+ .timescale -9 -12;
+L_00000000040cb510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df83b0_0 .net8 "KAPWR", 0 0, L_00000000040cb510;  1 drivers, strength-aware
+L_00000000040cb200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7cd0_0 .net8 "VGND", 0 0, L_00000000040cb200;  1 drivers, strength-aware
+L_00000000040ca8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7690_0 .net8 "VNB", 0 0, L_00000000040ca8d0;  1 drivers, strength-aware
+L_00000000040ca080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8270_0 .net8 "VPB", 0 0, L_00000000040ca080;  1 drivers, strength-aware
+L_00000000040cae80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8310_0 .net8 "VPWR", 0 0, L_00000000040cae80;  1 drivers, strength-aware
+S_000000000284b7e0 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_6" "sky130_fd_sc_hd__lpflow_decapkapwr_6" 4 68;
+ .timescale -9 -12;
+L_00000000040ca9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df66f0_0 .net8 "KAPWR", 0 0, L_00000000040ca9b0;  1 drivers, strength-aware
+L_00000000040cafd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6c90_0 .net8 "VGND", 0 0, L_00000000040cafd0;  1 drivers, strength-aware
+L_00000000040ca1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6830_0 .net8 "VNB", 0 0, L_00000000040ca1d0;  1 drivers, strength-aware
+L_00000000040c9d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df68d0_0 .net8 "VPB", 0 0, L_00000000040c9d70;  1 drivers, strength-aware
+L_00000000040c9f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6a10_0 .net8 "VPWR", 0 0, L_00000000040c9f30;  1 drivers, strength-aware
+S_0000000003d1bdb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 76, 4 580 1, S_000000000284b7e0;
+ .timescale -9 -12;
+L_00000000040c9de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df63d0_0 .net8 "KAPWR", 0 0, L_00000000040c9de0;  1 drivers, strength-aware
+L_00000000040cb0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df7af0_0 .net8 "VGND", 0 0, L_00000000040cb0b0;  1 drivers, strength-aware
+L_00000000040cab00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8810_0 .net8 "VNB", 0 0, L_00000000040cab00;  1 drivers, strength-aware
+L_00000000040cb2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df88b0_0 .net8 "VPB", 0 0, L_00000000040cb2e0;  1 drivers, strength-aware
+L_00000000040caa90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6470_0 .net8 "VPWR", 0 0, L_00000000040caa90;  1 drivers, strength-aware
+S_0000000002849ce0 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_8" "sky130_fd_sc_hd__lpflow_decapkapwr_8" 4 671;
+ .timescale -9 -12;
+L_00000000040ca0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9210_0 .net8 "KAPWR", 0 0, L_00000000040ca0f0;  1 drivers, strength-aware
+L_00000000040ca160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9d50_0 .net8 "VGND", 0 0, L_00000000040ca160;  1 drivers, strength-aware
+L_00000000040ca2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa4d0_0 .net8 "VNB", 0 0, L_00000000040ca2b0;  1 drivers, strength-aware
+L_00000000040ca400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8d10_0 .net8 "VPB", 0 0, L_00000000040ca400;  1 drivers, strength-aware
+L_00000000040cab70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa1b0_0 .net8 "VPWR", 0 0, L_00000000040cab70;  1 drivers, strength-aware
+S_0000000003d1e7b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 679, 4 580 1, S_0000000002849ce0;
+ .timescale -9 -12;
+L_00000000040cb6d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df6ab0_0 .net8 "KAPWR", 0 0, L_00000000040cb6d0;  1 drivers, strength-aware
+L_00000000040cb660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6b50_0 .net8 "VGND", 0 0, L_00000000040cb660;  1 drivers, strength-aware
+L_00000000040cb740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df6bf0_0 .net8 "VNB", 0 0, L_00000000040cb740;  1 drivers, strength-aware
+L_00000000040cb7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa390_0 .net8 "VPB", 0 0, L_00000000040cb7b0;  1 drivers, strength-aware
+L_00000000040ca470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9490_0 .net8 "VPWR", 0 0, L_00000000040ca470;  1 drivers, strength-aware
+S_0000000002849e60 .scope module, "sky130_fd_sc_hd__lpflow_inputiso0n_1" "sky130_fd_sc_hd__lpflow_inputiso0n_1" 4 85208;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003d94d58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df8bd0_0 .net "A", 0 0, o0000000003d94d58;  0 drivers
+o0000000003d94d88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df90d0_0 .net "SLEEP_B", 0 0, o0000000003d94d88;  0 drivers
+L_00000000040cada0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8e50_0 .net8 "VGND", 0 0, L_00000000040cada0;  1 drivers, strength-aware
+L_00000000040cb270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9850_0 .net8 "VNB", 0 0, L_00000000040cb270;  1 drivers, strength-aware
+L_00000000040ca5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa250_0 .net8 "VPB", 0 0, L_00000000040ca5c0;  1 drivers, strength-aware
+L_00000000040cabe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa7f0_0 .net8 "VPWR", 0 0, L_00000000040cabe0;  1 drivers, strength-aware
+v0000000003df9170_0 .net "X", 0 0, L_000000000416e600;  1 drivers
+S_0000000003d1da30 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso0n" 4 85224, 4 85507 1, S_0000000002849e60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+L_000000000416e600 .functor AND 1, o0000000003d94d58, o0000000003d94d88, C4<1>, C4<1>;
+v0000000003df97b0_0 .net "A", 0 0, o0000000003d94d58;  alias, 0 drivers
+v0000000003df9f30_0 .net "SLEEP_B", 0 0, o0000000003d94d88;  alias, 0 drivers
+L_00000000040cb580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8ef0_0 .net8 "VGND", 0 0, L_00000000040cb580;  1 drivers, strength-aware
+L_00000000040c9e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9a30_0 .net8 "VNB", 0 0, L_00000000040c9e50;  1 drivers, strength-aware
+L_00000000040cac50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa570_0 .net8 "VPB", 0 0, L_00000000040cac50;  1 drivers, strength-aware
+L_00000000040cacc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9030_0 .net8 "VPWR", 0 0, L_00000000040cacc0;  1 drivers, strength-aware
+v0000000003dfa610_0 .net "X", 0 0, L_000000000416e600;  alias, 1 drivers
+S_000000000284bc60 .scope module, "sky130_fd_sc_hd__lpflow_inputiso0p_1" "sky130_fd_sc_hd__lpflow_inputiso0p_1" 4 70058;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP"
+o0000000003d95088 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfa430_0 .net "A", 0 0, o0000000003d95088;  0 drivers
+o0000000003d950b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfa2f0_0 .net "SLEEP", 0 0, o0000000003d950b8;  0 drivers
+L_00000000040cad30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa890_0 .net8 "VGND", 0 0, L_00000000040cad30;  1 drivers, strength-aware
+L_00000000040cbdd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa6b0_0 .net8 "VNB", 0 0, L_00000000040cbdd0;  1 drivers, strength-aware
+L_00000000040cc4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df98f0_0 .net8 "VPB", 0 0, L_00000000040cc4d0;  1 drivers, strength-aware
+L_00000000040cbba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9fd0_0 .net8 "VPWR", 0 0, L_00000000040cbba0;  1 drivers, strength-aware
+v0000000003dfad90_0 .net "X", 0 0, L_000000000416df70;  1 drivers
+S_0000000003d1d130 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso0p" 4 70074, 4 69945 1, S_000000000284bc60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP"
+L_000000000416ec90 .functor NOT 1, o0000000003d950b8, C4<0>, C4<0>, C4<0>;
+L_000000000416df70 .functor AND 1, o0000000003d95088, L_000000000416ec90, C4<1>, C4<1>;
+v0000000003df8db0_0 .net "A", 0 0, o0000000003d95088;  alias, 0 drivers
+v0000000003df8f90_0 .net "SLEEP", 0 0, o0000000003d950b8;  alias, 0 drivers
+L_00000000040cc700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df8b30_0 .net8 "VGND", 0 0, L_00000000040cc700;  1 drivers, strength-aware
+L_00000000040cc230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9ad0_0 .net8 "VNB", 0 0, L_00000000040cc230;  1 drivers, strength-aware
+L_00000000040ccd90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df92b0_0 .net8 "VPB", 0 0, L_00000000040ccd90;  1 drivers, strength-aware
+L_00000000040cc850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa9d0_0 .net8 "VPWR", 0 0, L_00000000040cc850;  1 drivers, strength-aware
+v0000000003df9350_0 .net "X", 0 0, L_000000000416df70;  alias, 1 drivers
+v0000000003dfaa70_0 .net "sleepn", 0 0, L_000000000416ec90;  1 drivers
+S_000000000284cfe0 .scope module, "sky130_fd_sc_hd__lpflow_inputiso1n_1" "sky130_fd_sc_hd__lpflow_inputiso1n_1" 4 97212;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003d953e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfab10_0 .net "A", 0 0, o0000000003d953e8;  0 drivers
+o0000000003d95448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfb010_0 .net "SLEEP_B", 0 0, o0000000003d95448;  0 drivers
+L_00000000040cc150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9530_0 .net8 "VGND", 0 0, L_00000000040cc150;  1 drivers, strength-aware
+L_00000000040cd3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df95d0_0 .net8 "VNB", 0 0, L_00000000040cd3b0;  1 drivers, strength-aware
+L_00000000040cd490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9670_0 .net8 "VPB", 0 0, L_00000000040cd490;  1 drivers, strength-aware
+L_00000000040cc540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9710_0 .net8 "VPWR", 0 0, L_00000000040cc540;  1 drivers, strength-aware
+v0000000003dfabb0_0 .net "X", 0 0, L_000000000416f320;  1 drivers
+S_0000000003d1d430 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso1n" 4 97228, 4 97519 1, S_000000000284cfe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+L_000000000416ef30 .functor NOT 1, o0000000003d95448, C4<0>, C4<0>, C4<0>;
+L_000000000416f320 .functor OR 1, o0000000003d953e8, L_000000000416ef30, C4<0>, C4<0>;
+v0000000003dfa750_0 .net "A", 0 0, o0000000003d953e8;  alias, 0 drivers
+v0000000003dfa070_0 .net "SLEEP", 0 0, L_000000000416ef30;  1 drivers
+v0000000003df8c70_0 .net "SLEEP_B", 0 0, o0000000003d95448;  alias, 0 drivers
+L_00000000040cca10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df93f0_0 .net8 "VGND", 0 0, L_00000000040cca10;  1 drivers, strength-aware
+L_00000000040cc0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa930_0 .net8 "VNB", 0 0, L_00000000040cc0e0;  1 drivers, strength-aware
+L_00000000040cb900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8950_0 .net8 "VPB", 0 0, L_00000000040cb900;  1 drivers, strength-aware
+L_00000000040cb970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df9990_0 .net8 "VPWR", 0 0, L_00000000040cb970;  1 drivers, strength-aware
+v0000000003df9df0_0 .net "X", 0 0, L_000000000416f320;  alias, 1 drivers
+S_000000000284c260 .scope module, "sky130_fd_sc_hd__lpflow_inputiso1p_1" "sky130_fd_sc_hd__lpflow_inputiso1p_1" 4 49258;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP"
+o0000000003d95748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfac50_0 .net "A", 0 0, o0000000003d95748;  0 drivers
+o0000000003d95778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003df9c10_0 .net "SLEEP", 0 0, o0000000003d95778;  0 drivers
+L_00000000040cc380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df9cb0_0 .net8 "VGND", 0 0, L_00000000040cc380;  1 drivers, strength-aware
+L_00000000040cc2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfae30_0 .net8 "VNB", 0 0, L_00000000040cc2a0;  1 drivers, strength-aware
+L_00000000040ccf50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb0b0_0 .net8 "VPB", 0 0, L_00000000040ccf50;  1 drivers, strength-aware
+L_00000000040cc1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003df8a90_0 .net8 "VPWR", 0 0, L_00000000040cc1c0;  1 drivers, strength-aware
+v0000000003dfcd70_0 .net "X", 0 0, L_000000000416e210;  1 drivers
+S_0000000003d1a2b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso1p" 4 49274, 4 49149 1, S_000000000284c260;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "SLEEP"
+L_000000000416e210 .functor OR 1, o0000000003d95748, o0000000003d95778, C4<0>, C4<0>;
+v0000000003df9b70_0 .net "A", 0 0, o0000000003d95748;  alias, 0 drivers
+v0000000003df9e90_0 .net "SLEEP", 0 0, o0000000003d95778;  alias, 0 drivers
+L_00000000040ccb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003df89f0_0 .net8 "VGND", 0 0, L_00000000040ccb60;  1 drivers, strength-aware
+L_00000000040ccbd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfaed0_0 .net8 "VNB", 0 0, L_00000000040ccbd0;  1 drivers, strength-aware
+L_00000000040cc310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfaf70_0 .net8 "VPB", 0 0, L_00000000040cc310;  1 drivers, strength-aware
+L_00000000040cc3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfa110_0 .net8 "VPWR", 0 0, L_00000000040cc3f0;  1 drivers, strength-aware
+v0000000003dfacf0_0 .net "X", 0 0, L_000000000416e210;  alias, 1 drivers
+S_000000000284a8e0 .scope module, "sky130_fd_sc_hd__lpflow_inputisolatch_1" "sky130_fd_sc_hd__lpflow_inputisolatch_1" 4 78940;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003d95a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfb290_0 .net "D", 0 0, o0000000003d95a78;  0 drivers
+v0000000003dfc9b0_0 .net "Q", 0 0, L_000000000416e750;  1 drivers
+o0000000003d95b08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfcff0_0 .net "SLEEP_B", 0 0, o0000000003d95b08;  0 drivers
+L_00000000040cce70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb3d0_0 .net8 "VGND", 0 0, L_00000000040cce70;  1 drivers, strength-aware
+L_00000000040ccee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbdd0_0 .net8 "VNB", 0 0, L_00000000040ccee0;  1 drivers, strength-aware
+L_00000000040cd180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd3b0_0 .net8 "VPB", 0 0, L_00000000040cd180;  1 drivers, strength-aware
+L_00000000040cca80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbfb0_0 .net8 "VPWR", 0 0, L_00000000040cca80;  1 drivers, strength-aware
+S_0000000003d1b1b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputisolatch" 4 78956, 4 78826 1, S_000000000284a8e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "D"
+    .port_info 2 /INPUT 1 "SLEEP_B"
+UDP_sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N", 5, 2
+ ,"?*0?10-"
+ ,"??_?10-"
+ ,"??M?10-"
+ ,"00Q?100"
+ ,"11Q?101"
+ ,"?0R?100"
+ ,"?1R?101"
+ ,"?_1?100"
+ ,"?+1?101"
+ ,"?0r?100"
+ ,"?1r?101"
+ ,"1+x?101"
+ ,"0_x?100"
+ ,"?????*x";
+o0000000003d95aa8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003d95b38 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040cd0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040ccfc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000416e280 .udp UDP_sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N, o0000000003d95aa8, o0000000003d95b38, v0000000003dfc0f0_0, L_00000000040cd0a0, L_00000000040ccfc0;
+L_000000000416e750 .functor BUF 1, L_000000000416e280, C4<0>, C4<0>, C4<0>;
+v0000000003dfcc30_0 .net "D", 0 0, o0000000003d95a78;  alias, 0 drivers
+v0000000003dfca50_0 .net "D_delayed", 0 0, o0000000003d95aa8;  0 drivers
+v0000000003dfcb90_0 .net "Q", 0 0, L_000000000416e750;  alias, 1 drivers
+v0000000003dfb830_0 .net "SLEEP_B", 0 0, o0000000003d95b08;  alias, 0 drivers
+v0000000003dfb5b0_0 .net "SLEEP_B_delayed", 0 0, o0000000003d95b38;  0 drivers
+v0000000003dfb150_0 .net8 "VGND", 0 0, L_00000000040ccfc0;  1 drivers, strength-aware
+L_00000000040cd1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd6d0_0 .net8 "VNB", 0 0, L_00000000040cd1f0;  1 drivers, strength-aware
+L_00000000040cd030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbd30_0 .net8 "VPB", 0 0, L_00000000040cd030;  1 drivers, strength-aware
+v0000000003dfb510_0 .net8 "VPWR", 0 0, L_00000000040cd0a0;  1 drivers, strength-aware
+v0000000003dfc190_0 .net "buf_Q", 0 0, L_000000000416e280;  1 drivers
+v0000000003dfc0f0_0 .var "notifier", 0 0;
+S_000000000284b4e0 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_1" "sky130_fd_sc_hd__lpflow_isobufsrc_1" 4 79705;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d95e68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfd810_0 .net "A", 0 0, o0000000003d95e68;  0 drivers
+o0000000003d95e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfccd0_0 .net "SLEEP", 0 0, o0000000003d95e98;  0 drivers
+L_00000000040cbb30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbab0_0 .net8 "VGND", 0 0, L_00000000040cbb30;  1 drivers, strength-aware
+L_00000000040cc460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfce10_0 .net8 "VNB", 0 0, L_00000000040cc460;  1 drivers, strength-aware
+L_00000000040cd110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfceb0_0 .net8 "VPB", 0 0, L_00000000040cd110;  1 drivers, strength-aware
+L_00000000040cc5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfc730_0 .net8 "VPWR", 0 0, L_00000000040cc5b0;  1 drivers, strength-aware
+v0000000003dfc5f0_0 .net "X", 0 0, L_000000000416e440;  1 drivers
+S_0000000003d19cb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79721, 4 80234 1, S_000000000284b4e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416ed00 .functor NOT 1, o0000000003d95e98, C4<0>, C4<0>, C4<0>;
+L_000000000416e2f0 .functor AND 1, L_000000000416ed00, o0000000003d95e68, C4<1>, C4<1>;
+L_000000000416e440 .functor BUF 1, L_000000000416e2f0, C4<0>, C4<0>, C4<0>;
+v0000000003dfc230_0 .net "A", 0 0, o0000000003d95e68;  alias, 0 drivers
+v0000000003dfc550_0 .net "SLEEP", 0 0, o0000000003d95e98;  alias, 0 drivers
+L_00000000040cc620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd4f0_0 .net8 "VGND", 0 0, L_00000000040cc620;  1 drivers, strength-aware
+L_00000000040cbe40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb650_0 .net8 "VNB", 0 0, L_00000000040cbe40;  1 drivers, strength-aware
+L_00000000040cd420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd630_0 .net8 "VPB", 0 0, L_00000000040cd420;  1 drivers, strength-aware
+L_00000000040cbc10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd770_0 .net8 "VPWR", 0 0, L_00000000040cbc10;  1 drivers, strength-aware
+v0000000003dfba10_0 .net "X", 0 0, L_000000000416e440;  alias, 1 drivers
+v0000000003dfb470_0 .net "and0_out_X", 0 0, L_000000000416e2f0;  1 drivers
+v0000000003dfc2d0_0 .net "not0_out", 0 0, L_000000000416ed00;  1 drivers
+S_000000000284d160 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_16" "sky130_fd_sc_hd__lpflow_isobufsrc_16" 4 79921;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d961f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfc050_0 .net "A", 0 0, o0000000003d961f8;  0 drivers
+o0000000003d96228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfd1d0_0 .net "SLEEP", 0 0, o0000000003d96228;  0 drivers
+L_00000000040cb9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfcf50_0 .net8 "VGND", 0 0, L_00000000040cb9e0;  1 drivers, strength-aware
+L_00000000040cccb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfcaf0_0 .net8 "VNB", 0 0, L_00000000040cccb0;  1 drivers, strength-aware
+L_00000000040cc770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfc370_0 .net8 "VPB", 0 0, L_00000000040cc770;  1 drivers, strength-aware
+L_00000000040cd260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfc410_0 .net8 "VPWR", 0 0, L_00000000040cd260;  1 drivers, strength-aware
+v0000000003dfc690_0 .net "X", 0 0, L_000000000416e3d0;  1 drivers
+S_0000000003d1d730 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79937, 4 80234 1, S_000000000284d160;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416f400 .functor NOT 1, o0000000003d96228, C4<0>, C4<0>, C4<0>;
+L_000000000416e830 .functor AND 1, L_000000000416f400, o0000000003d961f8, C4<1>, C4<1>;
+L_000000000416e3d0 .functor BUF 1, L_000000000416e830, C4<0>, C4<0>, C4<0>;
+v0000000003dfb6f0_0 .net "A", 0 0, o0000000003d961f8;  alias, 0 drivers
+v0000000003dfb790_0 .net "SLEEP", 0 0, o0000000003d96228;  alias, 0 drivers
+L_00000000040cc690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbc90_0 .net8 "VGND", 0 0, L_00000000040cc690;  1 drivers, strength-aware
+L_00000000040cbcf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbe70_0 .net8 "VNB", 0 0, L_00000000040cbcf0;  1 drivers, strength-aware
+L_00000000040cbc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb330_0 .net8 "VPB", 0 0, L_00000000040cbc80;  1 drivers, strength-aware
+L_00000000040cbeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb1f0_0 .net8 "VPWR", 0 0, L_00000000040cbeb0;  1 drivers, strength-aware
+v0000000003dfbf10_0 .net "X", 0 0, L_000000000416e3d0;  alias, 1 drivers
+v0000000003dfd8b0_0 .net "and0_out_X", 0 0, L_000000000416e830;  1 drivers
+v0000000003dfc4b0_0 .net "not0_out", 0 0, L_000000000416f400;  1 drivers
+S_000000000284c860 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_2" "sky130_fd_sc_hd__lpflow_isobufsrc_2" 4 79813;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d96588 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfd450_0 .net "A", 0 0, o0000000003d96588;  0 drivers
+o0000000003d965b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfd590_0 .net "SLEEP", 0 0, o0000000003d965b8;  0 drivers
+L_00000000040cbd60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbb50_0 .net8 "VGND", 0 0, L_00000000040cbd60;  1 drivers, strength-aware
+L_00000000040cc7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfbbf0_0 .net8 "VNB", 0 0, L_00000000040cc7e0;  1 drivers, strength-aware
+L_00000000040cd2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dffe30_0 .net8 "VPB", 0 0, L_00000000040cd2d0;  1 drivers, strength-aware
+L_00000000040cd340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dffb10_0 .net8 "VPWR", 0 0, L_00000000040cd340;  1 drivers, strength-aware
+v0000000003dffcf0_0 .net "X", 0 0, L_000000000416e4b0;  1 drivers
+S_0000000003d1ec30 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79829, 4 80234 1, S_000000000284c860;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416efa0 .functor NOT 1, o0000000003d965b8, C4<0>, C4<0>, C4<0>;
+L_000000000416e910 .functor AND 1, L_000000000416efa0, o0000000003d96588, C4<1>, C4<1>;
+L_000000000416e4b0 .functor BUF 1, L_000000000416e910, C4<0>, C4<0>, C4<0>;
+v0000000003dfc7d0_0 .net "A", 0 0, o0000000003d96588;  alias, 0 drivers
+v0000000003dfc870_0 .net "SLEEP", 0 0, o0000000003d965b8;  alias, 0 drivers
+L_00000000040cba50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb8d0_0 .net8 "VGND", 0 0, L_00000000040cba50;  1 drivers, strength-aware
+L_00000000040cbac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfc910_0 .net8 "VNB", 0 0, L_00000000040cbac0;  1 drivers, strength-aware
+L_00000000040cc000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfb970_0 .net8 "VPB", 0 0, L_00000000040cc000;  1 drivers, strength-aware
+L_00000000040cc9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd090_0 .net8 "VPWR", 0 0, L_00000000040cc9a0;  1 drivers, strength-aware
+v0000000003dfd130_0 .net "X", 0 0, L_000000000416e4b0;  alias, 1 drivers
+v0000000003dfd270_0 .net "and0_out_X", 0 0, L_000000000416e910;  1 drivers
+v0000000003dfd310_0 .net "not0_out", 0 0, L_000000000416efa0;  1 drivers
+S_000000000284a160 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_4" "sky130_fd_sc_hd__lpflow_isobufsrc_4" 4 80457;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d96918 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dff890_0 .net "A", 0 0, o0000000003d96918;  0 drivers
+o0000000003d96948 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dff2f0_0 .net "SLEEP", 0 0, o0000000003d96948;  0 drivers
+L_00000000040ccd20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dffd90_0 .net8 "VGND", 0 0, L_00000000040ccd20;  1 drivers, strength-aware
+L_00000000040cc070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfddb0_0 .net8 "VNB", 0 0, L_00000000040cc070;  1 drivers, strength-aware
+L_00000000040cbf20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfff70_0 .net8 "VPB", 0 0, L_00000000040cbf20;  1 drivers, strength-aware
+L_00000000040cbf90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dff390_0 .net8 "VPWR", 0 0, L_00000000040cbf90;  1 drivers, strength-aware
+v0000000003dfe530_0 .net "X", 0 0, L_000000000416e6e0;  1 drivers
+S_0000000003d1b4b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 80473, 4 80234 1, S_000000000284a160;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416e670 .functor NOT 1, o0000000003d96948, C4<0>, C4<0>, C4<0>;
+L_000000000416f240 .functor AND 1, L_000000000416e670, o0000000003d96918, C4<1>, C4<1>;
+L_000000000416e6e0 .functor BUF 1, L_000000000416f240, C4<0>, C4<0>, C4<0>;
+v0000000003dfecb0_0 .net "A", 0 0, o0000000003d96918;  alias, 0 drivers
+v0000000003dfead0_0 .net "SLEEP", 0 0, o0000000003d96948;  alias, 0 drivers
+L_00000000040cc8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dff1b0_0 .net8 "VGND", 0 0, L_00000000040cc8c0;  1 drivers, strength-aware
+L_00000000040cc930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dff4d0_0 .net8 "VNB", 0 0, L_00000000040cc930;  1 drivers, strength-aware
+L_00000000040ccaf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfdc70_0 .net8 "VPB", 0 0, L_00000000040ccaf0;  1 drivers, strength-aware
+L_00000000040ccc40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dffa70_0 .net8 "VPWR", 0 0, L_00000000040ccc40;  1 drivers, strength-aware
+v0000000003dfe210_0 .net "X", 0 0, L_000000000416e6e0;  alias, 1 drivers
+v0000000003dfe490_0 .net "and0_out_X", 0 0, L_000000000416f240;  1 drivers
+v0000000003dff7f0_0 .net "not0_out", 0 0, L_000000000416e670;  1 drivers
+S_000000000284aa60 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_8" "sky130_fd_sc_hd__lpflow_isobufsrc_8" 4 80349;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d96ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dff570_0 .net "A", 0 0, o0000000003d96ca8;  0 drivers
+o0000000003d96cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfefd0_0 .net "SLEEP", 0 0, o0000000003d96cd8;  0 drivers
+L_00000000040cce00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfdbd0_0 .net8 "VGND", 0 0, L_00000000040cce00;  1 drivers, strength-aware
+L_00000000040ce0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe030_0 .net8 "VNB", 0 0, L_00000000040ce0d0;  1 drivers, strength-aware
+L_00000000040cd7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dff6b0_0 .net8 "VPB", 0 0, L_00000000040cd7a0;  1 drivers, strength-aware
+L_00000000040ce300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd950_0 .net8 "VPWR", 0 0, L_00000000040ce300;  1 drivers, strength-aware
+v0000000003dfe8f0_0 .net "X", 0 0, L_000000000416ede0;  1 drivers
+S_0000000003d1c0b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 80365, 4 80234 1, S_000000000284aa60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416e980 .functor NOT 1, o0000000003d96cd8, C4<0>, C4<0>, C4<0>;
+L_000000000416ea60 .functor AND 1, L_000000000416e980, o0000000003d96ca8, C4<1>, C4<1>;
+L_000000000416ede0 .functor BUF 1, L_000000000416ea60, C4<0>, C4<0>, C4<0>;
+v0000000003dff430_0 .net "A", 0 0, o0000000003d96ca8;  alias, 0 drivers
+v0000000003dff250_0 .net "SLEEP", 0 0, o0000000003d96cd8;  alias, 0 drivers
+L_00000000040cde30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dff930_0 .net8 "VGND", 0 0, L_00000000040cde30;  1 drivers, strength-aware
+L_00000000040ce990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dff610_0 .net8 "VNB", 0 0, L_00000000040ce990;  1 drivers, strength-aware
+L_00000000040ce450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe7b0_0 .net8 "VPB", 0 0, L_00000000040ce450;  1 drivers, strength-aware
+L_00000000040cdd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfef30_0 .net8 "VPWR", 0 0, L_00000000040cdd50;  1 drivers, strength-aware
+v0000000003dffed0_0 .net "X", 0 0, L_000000000416ede0;  alias, 1 drivers
+v0000000003dfe710_0 .net "and0_out_X", 0 0, L_000000000416ea60;  1 drivers
+v0000000003dfea30_0 .net "not0_out", 0 0, L_000000000416e980;  1 drivers
+S_000000000284b960 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrckapwr_16" "sky130_fd_sc_hd__lpflow_isobufsrckapwr_16" 4 95579;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+o0000000003d97038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dff750_0 .net "A", 0 0, o0000000003d97038;  0 drivers
+L_00000000040cefb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dffc50_0 .net8 "KAPWR", 0 0, L_00000000040cefb0;  1 drivers, strength-aware
+o0000000003d97098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e000b0_0 .net "SLEEP", 0 0, o0000000003d97098;  0 drivers
+L_00000000040cf090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dff070_0 .net8 "VGND", 0 0, L_00000000040cf090;  1 drivers, strength-aware
+L_00000000040ce140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfd9f0_0 .net8 "VNB", 0 0, L_00000000040ce140;  1 drivers, strength-aware
+L_00000000040ce610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfeb70_0 .net8 "VPB", 0 0, L_00000000040ce610;  1 drivers, strength-aware
+L_00000000040cdce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfda90_0 .net8 "VPWR", 0 0, L_00000000040cdce0;  1 drivers, strength-aware
+v0000000003dfdb30_0 .net "X", 0 0, L_000000000416f0f0;  1 drivers
+S_0000000003d1a430 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrckapwr" 4 95596, 4 95906 1, S_000000000284b960;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "SLEEP"
+    .port_info 2 /INPUT 1 "A"
+L_000000000416f860 .functor NOT 1, o0000000003d97098, C4<0>, C4<0>, C4<0>;
+L_000000000416ee50 .functor AND 1, L_000000000416f860, o0000000003d97038, C4<1>, C4<1>;
+L_000000000416f0f0 .functor BUF 1, L_000000000416ee50, C4<0>, C4<0>, C4<0>;
+v0000000003e00010_0 .net "A", 0 0, o0000000003d97038;  alias, 0 drivers
+L_00000000040cd500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe0d0_0 .net8 "KAPWR", 0 0, L_00000000040cd500;  1 drivers, strength-aware
+v0000000003dfdd10_0 .net "SLEEP", 0 0, o0000000003d97098;  alias, 0 drivers
+L_00000000040cd570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfde50_0 .net8 "VGND", 0 0, L_00000000040cd570;  1 drivers, strength-aware
+L_00000000040cdf80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfdef0_0 .net8 "VNB", 0 0, L_00000000040cdf80;  1 drivers, strength-aware
+L_00000000040cdea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe5d0_0 .net8 "VPB", 0 0, L_00000000040cdea0;  1 drivers, strength-aware
+L_00000000040ceb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfed50_0 .net8 "VPWR", 0 0, L_00000000040ceb50;  1 drivers, strength-aware
+v0000000003dff9d0_0 .net "X", 0 0, L_000000000416f0f0;  alias, 1 drivers
+v0000000003dffbb0_0 .net "and0_out_X", 0 0, L_000000000416ee50;  1 drivers
+v0000000003dfe170_0 .net "not0_out", 0 0, L_000000000416f860;  1 drivers
+S_000000000284bae0 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1" 4 38004;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d97428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003dfec10_0 .net "A", 0 0, o0000000003d97428;  0 drivers
+L_00000000040cddc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe670_0 .net8 "VGND", 0 0, L_00000000040cddc0;  1 drivers, strength-aware
+L_00000000040ce760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe850_0 .net8 "VPB", 0 0, L_00000000040ce760;  1 drivers, strength-aware
+L_00000000040ce7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe990_0 .net8 "VPWR", 0 0, L_00000000040ce7d0;  1 drivers, strength-aware
+v0000000003dfee90_0 .net "X", 0 0, L_000000000416f1d0;  1 drivers
+S_0000000003d1d8b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 38018, 4 37899 1, S_000000000284bae0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f1d0 .functor BUF 1, o0000000003d97428, C4<0>, C4<0>, C4<0>;
+v0000000003dfdf90_0 .net "A", 0 0, o0000000003d97428;  alias, 0 drivers
+L_00000000040cdf10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe2b0_0 .net8 "VGND", 0 0, L_00000000040cdf10;  1 drivers, strength-aware
+L_00000000040cdff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfe350_0 .net8 "VPB", 0 0, L_00000000040cdff0;  1 drivers, strength-aware
+L_00000000040cea70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003dfedf0_0 .net8 "VPWR", 0 0, L_00000000040cea70;  1 drivers, strength-aware
+v0000000003dfe3f0_0 .net "X", 0 0, L_000000000416f1d0;  alias, 1 drivers
+S_000000000284bde0 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2" 4 37600;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d97668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e02590_0 .net "A", 0 0, o0000000003d97668;  0 drivers
+L_00000000040ceae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e01af0_0 .net8 "VGND", 0 0, L_00000000040ceae0;  1 drivers, strength-aware
+L_00000000040ced80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01d70_0 .net8 "VPB", 0 0, L_00000000040ced80;  1 drivers, strength-aware
+L_00000000040ce680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00830_0 .net8 "VPWR", 0 0, L_00000000040ce680;  1 drivers, strength-aware
+v0000000003e01e10_0 .net "X", 0 0, L_000000000416f470;  1 drivers
+S_0000000003d1deb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 37614, 4 37899 1, S_000000000284bde0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f470 .functor BUF 1, o0000000003d97668, C4<0>, C4<0>, C4<0>;
+v0000000003dff110_0 .net "A", 0 0, o0000000003d97668;  alias, 0 drivers
+L_00000000040cebc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e01410_0 .net8 "VGND", 0 0, L_00000000040cebc0;  1 drivers, strength-aware
+L_00000000040cedf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01cd0_0 .net8 "VPB", 0 0, L_00000000040cedf0;  1 drivers, strength-aware
+L_00000000040cec30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e010f0_0 .net8 "VPWR", 0 0, L_00000000040cec30;  1 drivers, strength-aware
+v0000000003e008d0_0 .net "X", 0 0, L_000000000416f470;  alias, 1 drivers
+S_000000000284d2e0 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4" 4 38108;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d978a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e01c30_0 .net "A", 0 0, o0000000003d978a8;  0 drivers
+L_00000000040ceca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e00a10_0 .net8 "VGND", 0 0, L_00000000040ceca0;  1 drivers, strength-aware
+L_00000000040cd730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01230_0 .net8 "VPB", 0 0, L_00000000040cd730;  1 drivers, strength-aware
+L_00000000040ce060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00fb0_0 .net8 "VPWR", 0 0, L_00000000040ce060;  1 drivers, strength-aware
+v0000000003e00330_0 .net "X", 0 0, L_000000000416f780;  1 drivers
+S_0000000003d196b0 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 38122, 4 37899 1, S_000000000284d2e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_000000000416f780 .functor BUF 1, o0000000003d978a8, C4<0>, C4<0>, C4<0>;
+v0000000003e01b90_0 .net "A", 0 0, o0000000003d978a8;  alias, 0 drivers
+L_00000000040ced10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e00150_0 .net8 "VGND", 0 0, L_00000000040ced10;  1 drivers, strength-aware
+L_00000000040ce1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01a50_0 .net8 "VPB", 0 0, L_00000000040ce1b0;  1 drivers, strength-aware
+L_00000000040ce220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01ff0_0 .net8 "VPWR", 0 0, L_00000000040ce220;  1 drivers, strength-aware
+v0000000003e00970_0 .net "X", 0 0, L_000000000416f780;  alias, 1 drivers
+S_000000000284a460 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4" 4 74157;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d97ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e02130_0 .net "A", 0 0, o0000000003d97ae8;  0 drivers
+L_00000000040ce6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e02810_0 .net8 "VGND", 0 0, L_00000000040ce6f0;  1 drivers, strength-aware
+L_00000000040ce290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e012d0_0 .net8 "VNB", 0 0, L_00000000040ce290;  1 drivers, strength-aware
+L_00000000040ce840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e003d0_0 .net8 "VPB", 0 0, L_00000000040ce840;  1 drivers, strength-aware
+L_00000000040ceed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e021d0_0 .net8 "VPWR", 0 0, L_00000000040ceed0;  1 drivers, strength-aware
+v0000000003e00dd0_0 .net "X", 0 0, L_00000000041703c0;  1 drivers
+S_0000000003d1dbb0 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell" 4 74172, 4 74050 1, S_000000000284a460;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041703c0 .functor BUF 1, o0000000003d97ae8, C4<0>, C4<0>, C4<0>;
+v0000000003e00ab0_0 .net "A", 0 0, o0000000003d97ae8;  alias, 0 drivers
+L_00000000040cee60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e019b0_0 .net8 "VGND", 0 0, L_00000000040cee60;  1 drivers, strength-aware
+L_00000000040ce370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e01eb0_0 .net8 "VNB", 0 0, L_00000000040ce370;  1 drivers, strength-aware
+L_00000000040ce8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e02090_0 .net8 "VPB", 0 0, L_00000000040ce8b0;  1 drivers, strength-aware
+L_00000000040ce3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01f50_0 .net8 "VPWR", 0 0, L_00000000040ce3e0;  1 drivers, strength-aware
+v0000000003e00e70_0 .net "X", 0 0, L_00000000041703c0;  alias, 1 drivers
+S_000000000284d460 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1" 4 41019;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d97d88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e01690_0 .net "A", 0 0, o0000000003d97d88;  0 drivers
+L_00000000040ce920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e00470_0 .net8 "VGND", 0 0, L_00000000040ce920;  1 drivers, strength-aware
+L_00000000040cef40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e026d0_0 .net8 "VPB", 0 0, L_00000000040cef40;  1 drivers, strength-aware
+L_00000000040ce4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00b50_0 .net8 "VPWR", 0 0, L_00000000040ce4c0;  1 drivers, strength-aware
+v0000000003e01730_0 .net "X", 0 0, L_00000000041711c0;  1 drivers
+S_0000000003d1dd30 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41033, 4 40915 1, S_000000000284d460;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_00000000041711c0 .functor BUF 1, o0000000003d97d88, C4<0>, C4<0>, C4<0>;
+v0000000003e02270_0 .net "A", 0 0, o0000000003d97d88;  alias, 0 drivers
+L_00000000040cd650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e001f0_0 .net8 "VGND", 0 0, L_00000000040cd650;  1 drivers, strength-aware
+L_00000000040cdb20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e005b0_0 .net8 "VPB", 0 0, L_00000000040cdb20;  1 drivers, strength-aware
+L_00000000040cd6c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00d30_0 .net8 "VPWR", 0 0, L_00000000040cd6c0;  1 drivers, strength-aware
+v0000000003e00f10_0 .net "X", 0 0, L_00000000041711c0;  alias, 1 drivers
+S_000000000284cb60 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2" 4 41225;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d97fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e00c90_0 .net "A", 0 0, o0000000003d97fc8;  0 drivers
+L_00000000040ce530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e024f0_0 .net8 "VGND", 0 0, L_00000000040ce530;  1 drivers, strength-aware
+L_00000000040cd5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01050_0 .net8 "VPB", 0 0, L_00000000040cd5e0;  1 drivers, strength-aware
+L_00000000040ce5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01190_0 .net8 "VPWR", 0 0, L_00000000040ce5a0;  1 drivers, strength-aware
+v0000000003e014b0_0 .net "X", 0 0, L_0000000004170c10;  1 drivers
+S_0000000003d19830 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41239, 4 40915 1, S_000000000284cb60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004170c10 .functor BUF 1, o0000000003d97fc8, C4<0>, C4<0>, C4<0>;
+v0000000003e00bf0_0 .net "A", 0 0, o0000000003d97fc8;  alias, 0 drivers
+L_00000000040cea00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e015f0_0 .net8 "VGND", 0 0, L_00000000040cea00;  1 drivers, strength-aware
+L_00000000040cd9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e02310_0 .net8 "VPB", 0 0, L_00000000040cd9d0;  1 drivers, strength-aware
+L_00000000040cf020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e023b0_0 .net8 "VPWR", 0 0, L_00000000040cf020;  1 drivers, strength-aware
+v0000000003e02450_0 .net "X", 0 0, L_0000000004170c10;  alias, 1 drivers
+S_000000000284c3e0 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4" 4 41122;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003d98208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e02770_0 .net "A", 0 0, o0000000003d98208;  0 drivers
+L_00000000040cd810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e01870_0 .net8 "VGND", 0 0, L_00000000040cd810;  1 drivers, strength-aware
+L_00000000040cd880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e028b0_0 .net8 "VPB", 0 0, L_00000000040cd880;  1 drivers, strength-aware
+L_00000000040cd8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00290_0 .net8 "VPWR", 0 0, L_00000000040cd8f0;  1 drivers, strength-aware
+v0000000003e01910_0 .net "X", 0 0, L_0000000004170430;  1 drivers
+S_0000000003d1ad30 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41136, 4 40915 1, S_000000000284c3e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004170430 .functor BUF 1, o0000000003d98208, C4<0>, C4<0>, C4<0>;
+v0000000003e02630_0 .net "A", 0 0, o0000000003d98208;  alias, 0 drivers
+L_00000000040cda40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e01370_0 .net8 "VGND", 0 0, L_00000000040cda40;  1 drivers, strength-aware
+L_00000000040cd960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e01550_0 .net8 "VPB", 0 0, L_00000000040cd960;  1 drivers, strength-aware
+L_00000000040cdab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e00510_0 .net8 "VPWR", 0 0, L_00000000040cdab0;  1 drivers, strength-aware
+v0000000003e017d0_0 .net "X", 0 0, L_0000000004170430;  alias, 1 drivers
+S_000000000284d5e0 .scope module, "sky130_fd_sc_hd__macro_sparecell" "sky130_fd_sc_hd__macro_sparecell" 4 29409;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "LO"
+L_000000000416f940 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+L_0000000004170190 .functor BUF 1, L_000000000416f940, C4<0>, C4<0>, C4<0>;
+v0000000003e05330_0 .net "LO", 0 0, L_0000000004170190;  1 drivers
+v0000000003e05290_0 .net "invleft", 0 0, L_0000000004170270;  1 drivers
+v0000000003e05dd0_0 .net "invright", 0 0, L_00000000041704a0;  1 drivers
+v0000000003e065f0_0 .net "nd2left", 0 0, L_0000000004171070;  1 drivers
+v0000000003e06d70_0 .net "nd2right", 0 0, L_000000000416f9b0;  1 drivers
+L_0000000004170660 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v0000000003e06f50_0 .net8 "net7", 0 0, L_0000000004170660;  1 drivers, strength-aware
+v0000000003e074f0_0 .net "nor2left", 0 0, L_0000000004171310;  1 drivers
+v0000000003e05fb0_0 .net "nor2right", 0 0, L_000000000416fb70;  1 drivers
+v0000000003e05470_0 .net8 "tielo", 0 0, L_000000000416f940;  1 drivers, strength-aware
+S_0000000003d1b630 .scope module, "conb0" "sky130_fd_sc_hd__conb_1" 4 29433, 4 20862 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "HI"
+    .port_info 1 /OUTPUT 1 "LO"
+v0000000003e042f0_0 .net8 "HI", 0 0, L_0000000004170660;  alias, 1 drivers, strength-aware
+v0000000003e02950_0 .net8 "LO", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040d0600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e02db0_0 .net8 "VGND", 0 0, L_00000000040d0600;  1 drivers, strength-aware
+L_00000000040cf480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03530_0 .net8 "VNB", 0 0, L_00000000040cf480;  1 drivers, strength-aware
+L_00000000040cf4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e03670_0 .net8 "VPB", 0 0, L_00000000040cf4f0;  1 drivers, strength-aware
+L_00000000040cfe90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e03850_0 .net8 "VPWR", 0 0, L_00000000040cfe90;  1 drivers, strength-aware
+S_0000000003d1e030 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_0000000003d1b630;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "HI"
+    .port_info 1 /OUTPUT 1 "LO"
+v0000000003e00650_0 .net8 "HI", 0 0, L_0000000004170660;  alias, 1 drivers, strength-aware
+v0000000003e006f0_0 .net8 "LO", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040d0910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e00790_0 .net8 "VGND", 0 0, L_00000000040d0910;  1 drivers, strength-aware
+L_00000000040d0440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e035d0_0 .net8 "VNB", 0 0, L_00000000040d0440;  1 drivers, strength-aware
+L_00000000040cf100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04ed0_0 .net8 "VPB", 0 0, L_00000000040cf100;  1 drivers, strength-aware
+L_00000000040d0a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e044d0_0 .net8 "VPWR", 0 0, L_00000000040d0a60;  1 drivers, strength-aware
+S_0000000003d1c230 .scope module, "inv0" "sky130_fd_sc_hd__inv_2" 4 29427, 4 54053 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003e04570_0 .net "A", 0 0, L_0000000004171310;  alias, 1 drivers
+L_00000000040cdb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03350_0 .net8 "VGND", 0 0, L_00000000040cdb90;  1 drivers, strength-aware
+L_00000000040cdc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03490_0 .net8 "VNB", 0 0, L_00000000040cdc00;  1 drivers, strength-aware
+L_00000000040cdc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04b10_0 .net8 "VPB", 0 0, L_00000000040cdc70;  1 drivers, strength-aware
+L_00000000040cf3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04610_0 .net8 "VPWR", 0 0, L_00000000040cf3a0;  1 drivers, strength-aware
+v0000000003e03990_0 .net "Y", 0 0, L_0000000004170270;  alias, 1 drivers
+S_0000000003d199b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003d1c230;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004170c80 .functor NOT 1, L_0000000004171310, C4<0>, C4<0>, C4<0>;
+L_0000000004170270 .functor BUF 1, L_0000000004170c80, C4<0>, C4<0>, C4<0>;
+v0000000003e04890_0 .net "A", 0 0, L_0000000004171310;  alias, 1 drivers
+L_00000000040cf9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e038f0_0 .net8 "VGND", 0 0, L_00000000040cf9c0;  1 drivers, strength-aware
+L_00000000040d0050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03710_0 .net8 "VNB", 0 0, L_00000000040d0050;  1 drivers, strength-aware
+L_00000000040cfe20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e02a90_0 .net8 "VPB", 0 0, L_00000000040cfe20;  1 drivers, strength-aware
+L_00000000040cfa30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04cf0_0 .net8 "VPWR", 0 0, L_00000000040cfa30;  1 drivers, strength-aware
+v0000000003e03df0_0 .net "Y", 0 0, L_0000000004170270;  alias, 1 drivers
+v0000000003e049d0_0 .net "not0_out_Y", 0 0, L_0000000004170c80;  1 drivers
+S_0000000003d1e1b0 .scope module, "inv1" "sky130_fd_sc_hd__inv_2" 4 29428, 4 54053 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+v0000000003e037b0_0 .net "A", 0 0, L_000000000416fb70;  alias, 1 drivers
+L_00000000040d0130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e04750_0 .net8 "VGND", 0 0, L_00000000040d0130;  1 drivers, strength-aware
+L_00000000040cfd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03f30_0 .net8 "VNB", 0 0, L_00000000040cfd40;  1 drivers, strength-aware
+L_00000000040d0280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04930_0 .net8 "VPB", 0 0, L_00000000040d0280;  1 drivers, strength-aware
+L_00000000040d00c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04d90_0 .net8 "VPWR", 0 0, L_00000000040d00c0;  1 drivers, strength-aware
+v0000000003e047f0_0 .net "Y", 0 0, L_00000000041704a0;  alias, 1 drivers
+S_0000000003d19fb0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_0000000003d1e1b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004170eb0 .functor NOT 1, L_000000000416fb70, C4<0>, C4<0>, C4<0>;
+L_00000000041704a0 .functor BUF 1, L_0000000004170eb0, C4<0>, C4<0>, C4<0>;
+v0000000003e04e30_0 .net "A", 0 0, L_000000000416fb70;  alias, 1 drivers
+L_00000000040d06e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03cb0_0 .net8 "VGND", 0 0, L_00000000040d06e0;  1 drivers, strength-aware
+L_00000000040d0520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03ad0_0 .net8 "VNB", 0 0, L_00000000040d0520;  1 drivers, strength-aware
+L_00000000040d0360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e041b0_0 .net8 "VPB", 0 0, L_00000000040d0360;  1 drivers, strength-aware
+L_00000000040d0bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04f70_0 .net8 "VPWR", 0 0, L_00000000040d0bb0;  1 drivers, strength-aware
+v0000000003e02c70_0 .net "Y", 0 0, L_00000000041704a0;  alias, 1 drivers
+v0000000003e046b0_0 .net "not0_out_Y", 0 0, L_0000000004170eb0;  1 drivers
+S_0000000003d1a5b0 .scope module, "nand20" "sky130_fd_sc_hd__nand2_2" 4 29431, 4 8552 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003e04c50_0 .net8 "A", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+v0000000003e03b70_0 .net8 "B", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040d0830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03e90_0 .net8 "VGND", 0 0, L_00000000040d0830;  1 drivers, strength-aware
+L_00000000040cfbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e05010_0 .net8 "VNB", 0 0, L_00000000040cfbf0;  1 drivers, strength-aware
+L_00000000040cfc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e03030_0 .net8 "VPB", 0 0, L_00000000040cfc60;  1 drivers, strength-aware
+L_00000000040cff00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e03fd0_0 .net8 "VPWR", 0 0, L_00000000040cff00;  1 drivers, strength-aware
+v0000000003e04070_0 .net "Y", 0 0, L_000000000416f9b0;  alias, 1 drivers
+S_0000000003d1cfb0 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003d1a5b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000416fa90 .functor NAND 1, L_000000000416f940, L_000000000416f940, C4<1>, C4<1>;
+L_000000000416f9b0 .functor BUF 1, L_000000000416fa90, C4<0>, C4<0>, C4<0>;
+v0000000003e03210_0 .net8 "A", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+v0000000003e03d50_0 .net8 "B", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040d04b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e03a30_0 .net8 "VGND", 0 0, L_00000000040d04b0;  1 drivers, strength-aware
+L_00000000040d0ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e04390_0 .net8 "VNB", 0 0, L_00000000040d0ad0;  1 drivers, strength-aware
+L_00000000040cf6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e03c10_0 .net8 "VPB", 0 0, L_00000000040cf6b0;  1 drivers, strength-aware
+L_00000000040d0b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04a70_0 .net8 "VPWR", 0 0, L_00000000040d0b40;  1 drivers, strength-aware
+v0000000003e033f0_0 .net "Y", 0 0, L_000000000416f9b0;  alias, 1 drivers
+v0000000003e04bb0_0 .net "nand0_out_Y", 0 0, L_000000000416fa90;  1 drivers
+S_0000000003d1a730 .scope module, "nand21" "sky130_fd_sc_hd__nand2_2" 4 29432, 4 8552 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003e02b30_0 .net8 "A", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+v0000000003e02ef0_0 .net8 "B", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040cf640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e02e50_0 .net8 "VGND", 0 0, L_00000000040cf640;  1 drivers, strength-aware
+L_00000000040cf800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e04110_0 .net8 "VNB", 0 0, L_00000000040cf800;  1 drivers, strength-aware
+L_00000000040d0c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04250_0 .net8 "VPB", 0 0, L_00000000040d0c20;  1 drivers, strength-aware
+L_00000000040d0750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e02f90_0 .net8 "VPWR", 0 0, L_00000000040d0750;  1 drivers, strength-aware
+v0000000003e06550_0 .net "Y", 0 0, L_0000000004171070;  alias, 1 drivers
+S_0000000003d190b0 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_0000000003d1a730;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170d60 .functor NAND 1, L_000000000416f940, L_000000000416f940, C4<1>, C4<1>;
+L_0000000004171070 .functor BUF 1, L_0000000004170d60, C4<0>, C4<0>, C4<0>;
+v0000000003e050b0_0 .net8 "A", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+v0000000003e030d0_0 .net8 "B", 0 0, L_000000000416f940;  alias, 1 drivers, strength-aware
+L_00000000040cf720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e02bd0_0 .net8 "VGND", 0 0, L_00000000040cf720;  1 drivers, strength-aware
+L_00000000040d08a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e029f0_0 .net8 "VNB", 0 0, L_00000000040d08a0;  1 drivers, strength-aware
+L_00000000040d01a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e04430_0 .net8 "VPB", 0 0, L_00000000040d01a0;  1 drivers, strength-aware
+L_00000000040d0c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e032b0_0 .net8 "VPWR", 0 0, L_00000000040d0c90;  1 drivers, strength-aware
+v0000000003e02d10_0 .net "Y", 0 0, L_0000000004171070;  alias, 1 drivers
+v0000000003e03170_0 .net "nand0_out_Y", 0 0, L_0000000004170d60;  1 drivers
+S_0000000003d1a8b0 .scope module, "nor20" "sky130_fd_sc_hd__nor2_2" 4 29429, 4 30285 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003e053d0_0 .net "A", 0 0, L_0000000004171070;  alias, 1 drivers
+v0000000003e05970_0 .net "B", 0 0, L_0000000004171070;  alias, 1 drivers
+L_00000000040cfb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e06b90_0 .net8 "VGND", 0 0, L_00000000040cfb10;  1 drivers, strength-aware
+L_00000000040cfaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e05150_0 .net8 "VNB", 0 0, L_00000000040cfaa0;  1 drivers, strength-aware
+L_00000000040d02f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e060f0_0 .net8 "VPB", 0 0, L_00000000040d02f0;  1 drivers, strength-aware
+L_00000000040d07c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e07130_0 .net8 "VPWR", 0 0, L_00000000040d07c0;  1 drivers, strength-aware
+v0000000003e05a10_0 .net "Y", 0 0, L_0000000004171310;  alias, 1 drivers
+S_0000000003d1e330 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003d1a8b0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170f20 .functor NOR 1, L_0000000004171070, L_0000000004171070, C4<0>, C4<0>;
+L_0000000004171310 .functor BUF 1, L_0000000004170f20, C4<0>, C4<0>, C4<0>;
+v0000000003e058d0_0 .net "A", 0 0, L_0000000004171070;  alias, 1 drivers
+v0000000003e06910_0 .net "B", 0 0, L_0000000004171070;  alias, 1 drivers
+L_00000000040d0210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e071d0_0 .net8 "VGND", 0 0, L_00000000040d0210;  1 drivers, strength-aware
+L_00000000040cfb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e05f10_0 .net8 "VNB", 0 0, L_00000000040cfb80;  1 drivers, strength-aware
+L_00000000040cf5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e06230_0 .net8 "VPB", 0 0, L_00000000040cf5d0;  1 drivers, strength-aware
+L_00000000040d0980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e07270_0 .net8 "VPWR", 0 0, L_00000000040d0980;  1 drivers, strength-aware
+v0000000003e05830_0 .net "Y", 0 0, L_0000000004171310;  alias, 1 drivers
+v0000000003e06cd0_0 .net "nor0_out_Y", 0 0, L_0000000004170f20;  1 drivers
+S_0000000003d1e930 .scope module, "nor21" "sky130_fd_sc_hd__nor2_2" 4 29430, 4 30285 1, S_000000000284d5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+v0000000003e06410_0 .net "A", 0 0, L_000000000416f9b0;  alias, 1 drivers
+v0000000003e06a50_0 .net "B", 0 0, L_000000000416f9b0;  alias, 1 drivers
+L_00000000040cf410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e05510_0 .net8 "VGND", 0 0, L_00000000040cf410;  1 drivers, strength-aware
+L_00000000040d0590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e078b0_0 .net8 "VNB", 0 0, L_00000000040d0590;  1 drivers, strength-aware
+L_00000000040cf950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e07630_0 .net8 "VPB", 0 0, L_00000000040cf950;  1 drivers, strength-aware
+L_00000000040cf170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e051f0_0 .net8 "VPWR", 0 0, L_00000000040cf170;  1 drivers, strength-aware
+v0000000003e06e10_0 .net "Y", 0 0, L_000000000416fb70;  alias, 1 drivers
+S_0000000003d1aa30 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_0000000003d1e930;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170cf0 .functor NOR 1, L_000000000416f9b0, L_000000000416f9b0, C4<0>, C4<0>;
+L_000000000416fb70 .functor BUF 1, L_0000000004170cf0, C4<0>, C4<0>, C4<0>;
+v0000000003e05ab0_0 .net "A", 0 0, L_000000000416f9b0;  alias, 1 drivers
+v0000000003e055b0_0 .net "B", 0 0, L_000000000416f9b0;  alias, 1 drivers
+L_00000000040d09f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e06eb0_0 .net8 "VGND", 0 0, L_00000000040d09f0;  1 drivers, strength-aware
+L_00000000040d0670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e064b0_0 .net8 "VNB", 0 0, L_00000000040d0670;  1 drivers, strength-aware
+L_00000000040cfdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e06ff0_0 .net8 "VPB", 0 0, L_00000000040cfdb0;  1 drivers, strength-aware
+L_00000000040cf250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e06af0_0 .net8 "VPWR", 0 0, L_00000000040cf250;  1 drivers, strength-aware
+v0000000003e05b50_0 .net "Y", 0 0, L_000000000416fb70;  alias, 1 drivers
+v0000000003e06870_0 .net "nor0_out_Y", 0 0, L_0000000004170cf0;  1 drivers
+S_000000000284abe0 .scope module, "sky130_fd_sc_hd__maj3_1" "sky130_fd_sc_hd__maj3_1" 4 84985;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d99888 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e05e70_0 .net "A", 0 0, o0000000003d99888;  0 drivers
+o0000000003d998b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e067d0_0 .net "B", 0 0, o0000000003d998b8;  0 drivers
+o0000000003d998e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e073b0_0 .net "C", 0 0, o0000000003d998e8;  0 drivers
+L_00000000040cff70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e06c30_0 .net8 "VGND", 0 0, L_00000000040cff70;  1 drivers, strength-aware
+L_00000000040cf8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e07090_0 .net8 "VNB", 0 0, L_00000000040cf8e0;  1 drivers, strength-aware
+L_00000000040cfcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e05790_0 .net8 "VPB", 0 0, L_00000000040cfcd0;  1 drivers, strength-aware
+L_00000000040cf1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e069b0_0 .net8 "VPWR", 0 0, L_00000000040cf1e0;  1 drivers, strength-aware
+v0000000003e07310_0 .net "X", 0 0, L_0000000004170120;  1 drivers
+S_0000000003d1e4b0 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 85003, 4 84751 1, S_000000000284abe0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004171380 .functor OR 1, o0000000003d998b8, o0000000003d99888, C4<0>, C4<0>;
+L_000000000416fcc0 .functor AND 1, L_0000000004171380, o0000000003d998e8, C4<1>, C4<1>;
+L_00000000041713f0 .functor AND 1, o0000000003d99888, o0000000003d998b8, C4<1>, C4<1>;
+L_0000000004170f90 .functor OR 1, L_00000000041713f0, L_000000000416fcc0, C4<0>, C4<0>;
+L_0000000004170120 .functor BUF 1, L_0000000004170f90, C4<0>, C4<0>, C4<0>;
+v0000000003e06050_0 .net "A", 0 0, o0000000003d99888;  alias, 0 drivers
+v0000000003e06190_0 .net "B", 0 0, o0000000003d998b8;  alias, 0 drivers
+v0000000003e05650_0 .net "C", 0 0, o0000000003d998e8;  alias, 0 drivers
+L_00000000040cffe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e056f0_0 .net8 "VGND", 0 0, L_00000000040cffe0;  1 drivers, strength-aware
+L_00000000040cf790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e076d0_0 .net8 "VNB", 0 0, L_00000000040cf790;  1 drivers, strength-aware
+L_00000000040cf2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e05bf0_0 .net8 "VPB", 0 0, L_00000000040cf2c0;  1 drivers, strength-aware
+L_00000000040d03d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e06690_0 .net8 "VPWR", 0 0, L_00000000040d03d0;  1 drivers, strength-aware
+v0000000003e062d0_0 .net "X", 0 0, L_0000000004170120;  alias, 1 drivers
+v0000000003e06370_0 .net "and0_out", 0 0, L_000000000416fcc0;  1 drivers
+v0000000003e05d30_0 .net "and1_out", 0 0, L_00000000041713f0;  1 drivers
+v0000000003e06730_0 .net "or0_out", 0 0, L_0000000004171380;  1 drivers
+v0000000003e05c90_0 .net "or1_out_X", 0 0, L_0000000004170f90;  1 drivers
+S_000000000284a5e0 .scope module, "sky130_fd_sc_hd__maj3_2" "sky130_fd_sc_hd__maj3_2" 4 85097;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d99d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0a010_0 .net "A", 0 0, o0000000003d99d08;  0 drivers
+o0000000003d99d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e08530_0 .net "B", 0 0, o0000000003d99d38;  0 drivers
+o0000000003d99d68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e08850_0 .net "C", 0 0, o0000000003d99d68;  0 drivers
+L_00000000040cf330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e087b0_0 .net8 "VGND", 0 0, L_00000000040cf330;  1 drivers, strength-aware
+L_00000000040cf560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e08e90_0 .net8 "VNB", 0 0, L_00000000040cf560;  1 drivers, strength-aware
+L_00000000040cf870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e07c70_0 .net8 "VPB", 0 0, L_00000000040cf870;  1 drivers, strength-aware
+L_00000000040d1e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09250_0 .net8 "VPWR", 0 0, L_00000000040d1e10;  1 drivers, strength-aware
+v0000000003e07d10_0 .net "X", 0 0, L_000000000416ff60;  1 drivers
+S_0000000003d1e630 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 85115, 4 84751 1, S_000000000284a5e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004171460 .functor OR 1, o0000000003d99d38, o0000000003d99d08, C4<0>, C4<0>;
+L_0000000004170740 .functor AND 1, L_0000000004171460, o0000000003d99d68, C4<1>, C4<1>;
+L_00000000041709e0 .functor AND 1, o0000000003d99d08, o0000000003d99d38, C4<1>, C4<1>;
+L_0000000004170510 .functor OR 1, L_00000000041709e0, L_0000000004170740, C4<0>, C4<0>;
+L_000000000416ff60 .functor BUF 1, L_0000000004170510, C4<0>, C4<0>, C4<0>;
+v0000000003e07770_0 .net "A", 0 0, o0000000003d99d08;  alias, 0 drivers
+v0000000003e07810_0 .net "B", 0 0, o0000000003d99d38;  alias, 0 drivers
+v0000000003e07450_0 .net "C", 0 0, o0000000003d99d68;  alias, 0 drivers
+L_00000000040d1320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e07590_0 .net8 "VGND", 0 0, L_00000000040d1320;  1 drivers, strength-aware
+L_00000000040d1240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e07f90_0 .net8 "VNB", 0 0, L_00000000040d1240;  1 drivers, strength-aware
+L_00000000040d1550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09f70_0 .net8 "VPB", 0 0, L_00000000040d1550;  1 drivers, strength-aware
+L_00000000040d1010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09e30_0 .net8 "VPWR", 0 0, L_00000000040d1010;  1 drivers, strength-aware
+v0000000003e09890_0 .net "X", 0 0, L_000000000416ff60;  alias, 1 drivers
+v0000000003e09a70_0 .net "and0_out", 0 0, L_0000000004170740;  1 drivers
+v0000000003e07a90_0 .net "and1_out", 0 0, L_00000000041709e0;  1 drivers
+v0000000003e09570_0 .net "or0_out", 0 0, L_0000000004171460;  1 drivers
+v0000000003e094d0_0 .net "or1_out_X", 0 0, L_0000000004170510;  1 drivers
+S_000000000284ad60 .scope module, "sky130_fd_sc_hd__maj3_4" "sky130_fd_sc_hd__maj3_4" 4 84873;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9a188 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e07950_0 .net "A", 0 0, o0000000003d9a188;  0 drivers
+o0000000003d9a1b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e085d0_0 .net "B", 0 0, o0000000003d9a1b8;  0 drivers
+o0000000003d9a1e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e09ed0_0 .net "C", 0 0, o0000000003d9a1e8;  0 drivers
+L_00000000040d1630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a0b0_0 .net8 "VGND", 0 0, L_00000000040d1630;  1 drivers, strength-aware
+L_00000000040d1ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e08210_0 .net8 "VNB", 0 0, L_00000000040d1ef0;  1 drivers, strength-aware
+L_00000000040d1860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e08710_0 .net8 "VPB", 0 0, L_00000000040d1860;  1 drivers, strength-aware
+L_00000000040d2820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e08670_0 .net8 "VPWR", 0 0, L_00000000040d2820;  1 drivers, strength-aware
+v0000000003e091b0_0 .net "X", 0 0, L_000000000416ffd0;  1 drivers
+S_0000000003d1bf30 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 84891, 4 84751 1, S_000000000284ad60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000416fe10 .functor OR 1, o0000000003d9a1b8, o0000000003d9a188, C4<0>, C4<0>;
+L_0000000004170580 .functor AND 1, L_000000000416fe10, o0000000003d9a1e8, C4<1>, C4<1>;
+L_000000000416fe80 .functor AND 1, o0000000003d9a188, o0000000003d9a1b8, C4<1>, C4<1>;
+L_00000000041706d0 .functor OR 1, L_000000000416fe80, L_0000000004170580, C4<0>, C4<0>;
+L_000000000416ffd0 .functor BUF 1, L_00000000041706d0, C4<0>, C4<0>, C4<0>;
+v0000000003e08cb0_0 .net "A", 0 0, o0000000003d9a188;  alias, 0 drivers
+v0000000003e08170_0 .net "B", 0 0, o0000000003d9a1b8;  alias, 0 drivers
+v0000000003e08df0_0 .net "C", 0 0, o0000000003d9a1e8;  alias, 0 drivers
+L_00000000040d0fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e099d0_0 .net8 "VGND", 0 0, L_00000000040d0fa0;  1 drivers, strength-aware
+L_00000000040d25f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e07bd0_0 .net8 "VNB", 0 0, L_00000000040d25f0;  1 drivers, strength-aware
+L_00000000040d0d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09610_0 .net8 "VPB", 0 0, L_00000000040d0d00;  1 drivers, strength-aware
+L_00000000040d1940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09bb0_0 .net8 "VPWR", 0 0, L_00000000040d1940;  1 drivers, strength-aware
+v0000000003e088f0_0 .net "X", 0 0, L_000000000416ffd0;  alias, 1 drivers
+v0000000003e08490_0 .net "and0_out", 0 0, L_0000000004170580;  1 drivers
+v0000000003e09b10_0 .net "and1_out", 0 0, L_000000000416fe80;  1 drivers
+v0000000003e096b0_0 .net "or0_out", 0 0, L_000000000416fe10;  1 drivers
+v0000000003e09c50_0 .net "or1_out_X", 0 0, L_00000000041706d0;  1 drivers
+S_000000000284c9e0 .scope module, "sky130_fd_sc_hd__mux2_2" "sky130_fd_sc_hd__mux2_2" 4 29952;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9a608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e082b0_0 .net "A0", 0 0, o0000000003d9a608;  0 drivers
+o0000000003d9a638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e08d50_0 .net "A1", 0 0, o0000000003d9a638;  0 drivers
+o0000000003d9a668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e07b30_0 .net "S", 0 0, o0000000003d9a668;  0 drivers
+L_00000000040d2190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e07e50_0 .net8 "VGND", 0 0, L_00000000040d2190;  1 drivers, strength-aware
+L_00000000040d0ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e092f0_0 .net8 "VNB", 0 0, L_00000000040d0ec0;  1 drivers, strength-aware
+L_00000000040d24a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e07ef0_0 .net8 "VPB", 0 0, L_00000000040d24a0;  1 drivers, strength-aware
+L_00000000040d2120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e08a30_0 .net8 "VPWR", 0 0, L_00000000040d2120;  1 drivers, strength-aware
+v0000000003e080d0_0 .net "X", 0 0, L_000000000416fc50;  1 drivers
+S_0000000003d1edb0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29970, 4 29836 1, S_000000000284c9e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_00000000041705f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003d9a608, o0000000003d9a638, o0000000003d9a668;
+L_000000000416fc50 .functor BUF 1, L_00000000041705f0, C4<0>, C4<0>, C4<0>;
+v0000000003e08990_0 .net "A0", 0 0, o0000000003d9a608;  alias, 0 drivers
+v0000000003e09750_0 .net "A1", 0 0, o0000000003d9a638;  alias, 0 drivers
+v0000000003e08f30_0 .net "S", 0 0, o0000000003d9a668;  alias, 0 drivers
+L_00000000040d16a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e09930_0 .net8 "VGND", 0 0, L_00000000040d16a0;  1 drivers, strength-aware
+L_00000000040d1080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e09d90_0 .net8 "VNB", 0 0, L_00000000040d1080;  1 drivers, strength-aware
+L_00000000040d1e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e097f0_0 .net8 "VPB", 0 0, L_00000000040d1e80;  1 drivers, strength-aware
+L_00000000040d1780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09cf0_0 .net8 "VPWR", 0 0, L_00000000040d1780;  1 drivers, strength-aware
+v0000000003e07db0_0 .net "X", 0 0, L_000000000416fc50;  alias, 1 drivers
+v0000000003e079f0_0 .net "mux_2to10_out_X", 0 0, L_00000000041705f0;  1 drivers
+S_000000000284bf60 .scope module, "sky130_fd_sc_hd__mux2_4" "sky130_fd_sc_hd__mux2_4" 4 30176;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9a9f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e09110_0 .net "A0", 0 0, o0000000003d9a9f8;  0 drivers
+o0000000003d9aa28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e09430_0 .net "A1", 0 0, o0000000003d9aa28;  0 drivers
+o0000000003d9aa58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0ac90_0 .net "S", 0 0, o0000000003d9aa58;  0 drivers
+L_00000000040d0d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0bf50_0 .net8 "VGND", 0 0, L_00000000040d0d70;  1 drivers, strength-aware
+L_00000000040d11d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b230_0 .net8 "VNB", 0 0, L_00000000040d11d0;  1 drivers, strength-aware
+L_00000000040d22e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0afb0_0 .net8 "VPB", 0 0, L_00000000040d22e0;  1 drivers, strength-aware
+L_00000000040d23c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a330_0 .net8 "VPWR", 0 0, L_00000000040d23c0;  1 drivers, strength-aware
+v0000000003e0add0_0 .net "X", 0 0, L_0000000004170820;  1 drivers
+S_0000000003d1abb0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 30194, 4 29836 1, S_000000000284bf60;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_00000000041707b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003d9a9f8, o0000000003d9aa28, o0000000003d9aa58;
+L_0000000004170820 .functor BUF 1, L_00000000041707b0, C4<0>, C4<0>, C4<0>;
+v0000000003e08030_0 .net "A0", 0 0, o0000000003d9a9f8;  alias, 0 drivers
+v0000000003e08350_0 .net "A1", 0 0, o0000000003d9aa28;  alias, 0 drivers
+v0000000003e08ad0_0 .net "S", 0 0, o0000000003d9aa58;  alias, 0 drivers
+L_00000000040d1c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e083f0_0 .net8 "VGND", 0 0, L_00000000040d1c50;  1 drivers, strength-aware
+L_00000000040d26d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e08b70_0 .net8 "VNB", 0 0, L_00000000040d26d0;  1 drivers, strength-aware
+L_00000000040d1b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e08c10_0 .net8 "VPB", 0 0, L_00000000040d1b70;  1 drivers, strength-aware
+L_00000000040d15c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e09390_0 .net8 "VPWR", 0 0, L_00000000040d15c0;  1 drivers, strength-aware
+v0000000003e08fd0_0 .net "X", 0 0, L_0000000004170820;  alias, 1 drivers
+v0000000003e09070_0 .net "mux_2to10_out_X", 0 0, L_00000000041707b0;  1 drivers
+S_000000000284c0e0 .scope module, "sky130_fd_sc_hd__mux2_8" "sky130_fd_sc_hd__mux2_8" 4 30064;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9ade8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0a1f0_0 .net "A0", 0 0, o0000000003d9ade8;  0 drivers
+o0000000003d9ae18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0af10_0 .net "A1", 0 0, o0000000003d9ae18;  0 drivers
+o0000000003d9ae48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0b4b0_0 .net "S", 0 0, o0000000003d9ae48;  0 drivers
+L_00000000040d2510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0beb0_0 .net8 "VGND", 0 0, L_00000000040d2510;  1 drivers, strength-aware
+L_00000000040d2040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c590_0 .net8 "VNB", 0 0, L_00000000040d2040;  1 drivers, strength-aware
+L_00000000040d18d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b050_0 .net8 "VPB", 0 0, L_00000000040d18d0;  1 drivers, strength-aware
+L_00000000040d2430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c1d0_0 .net8 "VPWR", 0 0, L_00000000040d2430;  1 drivers, strength-aware
+v0000000003e0a5b0_0 .net "X", 0 0, L_0000000004171230;  1 drivers
+S_0000000003d1ce30 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 30082, 4 29836 1, S_000000000284c0e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_00000000041714d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003d9ade8, o0000000003d9ae18, o0000000003d9ae48;
+L_0000000004171230 .functor BUF 1, L_00000000041714d0, C4<0>, C4<0>, C4<0>;
+v0000000003e0b9b0_0 .net "A0", 0 0, o0000000003d9ade8;  alias, 0 drivers
+v0000000003e0baf0_0 .net "A1", 0 0, o0000000003d9ae18;  alias, 0 drivers
+v0000000003e0c090_0 .net "S", 0 0, o0000000003d9ae48;  alias, 0 drivers
+L_00000000040d2740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c770_0 .net8 "VGND", 0 0, L_00000000040d2740;  1 drivers, strength-aware
+L_00000000040d0de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ae70_0 .net8 "VNB", 0 0, L_00000000040d0de0;  1 drivers, strength-aware
+L_00000000040d10f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c4f0_0 .net8 "VPB", 0 0, L_00000000040d10f0;  1 drivers, strength-aware
+L_00000000040d2350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c130_0 .net8 "VPWR", 0 0, L_00000000040d2350;  1 drivers, strength-aware
+v0000000003e0a150_0 .net "X", 0 0, L_0000000004171230;  alias, 1 drivers
+v0000000003e0be10_0 .net "mux_2to10_out_X", 0 0, L_00000000041714d0;  1 drivers
+S_000000000284c560 .scope module, "sky130_fd_sc_hd__mux2i_1" "sky130_fd_sc_hd__mux2i_1" 4 20050;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9b1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0b370_0 .net "A0", 0 0, o0000000003d9b1d8;  0 drivers
+o0000000003d9b208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0c630_0 .net "A1", 0 0, o0000000003d9b208;  0 drivers
+o0000000003d9b238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0a6f0_0 .net "S", 0 0, o0000000003d9b238;  0 drivers
+L_00000000040d19b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a650_0 .net8 "VGND", 0 0, L_00000000040d19b0;  1 drivers, strength-aware
+L_00000000040d1160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b0f0_0 .net8 "VNB", 0 0, L_00000000040d1160;  1 drivers, strength-aware
+L_00000000040d12b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b5f0_0 .net8 "VPB", 0 0, L_00000000040d12b0;  1 drivers, strength-aware
+L_00000000040d1390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a790_0 .net8 "VPWR", 0 0, L_00000000040d1390;  1 drivers, strength-aware
+v0000000003e0b690_0 .net "Y", 0 0, L_000000000416fb00;  1 drivers
+S_0000000003d1c3b0 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 20068, 4 19934 1, S_000000000284c560;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+UDP_sky130_fd_sc_hd__udp_mux_2to1_N .udp/comb "sky130_fd_sc_hd__udp_mux_2to1_N", 3
+ ,"0?01"
+ ,"1?00"
+ ,"?011"
+ ,"?110"
+ ,"00?1"
+ ,"11?0";
+L_000000000416fa20 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o0000000003d9b1d8, o0000000003d9b208, o0000000003d9b238;
+L_000000000416fb00 .functor BUF 1, L_000000000416fa20, C4<0>, C4<0>, C4<0>;
+v0000000003e0b2d0_0 .net "A0", 0 0, o0000000003d9b1d8;  alias, 0 drivers
+v0000000003e0ba50_0 .net "A1", 0 0, o0000000003d9b208;  alias, 0 drivers
+v0000000003e0bcd0_0 .net "S", 0 0, o0000000003d9b238;  alias, 0 drivers
+L_00000000040d1400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c270_0 .net8 "VGND", 0 0, L_00000000040d1400;  1 drivers, strength-aware
+L_00000000040d1710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c310_0 .net8 "VNB", 0 0, L_00000000040d1710;  1 drivers, strength-aware
+L_00000000040d27b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a290_0 .net8 "VPB", 0 0, L_00000000040d27b0;  1 drivers, strength-aware
+L_00000000040d2660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0bd70_0 .net8 "VPWR", 0 0, L_00000000040d2660;  1 drivers, strength-aware
+v0000000003e0bff0_0 .net "Y", 0 0, L_000000000416fb00;  alias, 1 drivers
+v0000000003e0b550_0 .net "mux_2to1_n0_out_Y", 0 0, L_000000000416fa20;  1 drivers
+S_000000000284c6e0 .scope module, "sky130_fd_sc_hd__mux2i_2" "sky130_fd_sc_hd__mux2i_2" 4 19512;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9b5c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0b730_0 .net "A0", 0 0, o0000000003d9b5c8;  0 drivers
+o0000000003d9b5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0bc30_0 .net "A1", 0 0, o0000000003d9b5f8;  0 drivers
+o0000000003d9b628 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0a3d0_0 .net "S", 0 0, o0000000003d9b628;  0 drivers
+L_00000000040d2890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c810_0 .net8 "VGND", 0 0, L_00000000040d2890;  1 drivers, strength-aware
+L_00000000040d0e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c8b0_0 .net8 "VNB", 0 0, L_00000000040d0e50;  1 drivers, strength-aware
+L_00000000040d1470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a970_0 .net8 "VPB", 0 0, L_00000000040d1470;  1 drivers, strength-aware
+L_00000000040d1da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0a470_0 .net8 "VPWR", 0 0, L_00000000040d1da0;  1 drivers, strength-aware
+v0000000003e0a510_0 .net "Y", 0 0, L_00000000041712a0;  1 drivers
+S_0000000003d1c530 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 19530, 4 19934 1, S_000000000284c6e0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_0000000004170890 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o0000000003d9b5c8, o0000000003d9b5f8, o0000000003d9b628;
+L_00000000041712a0 .functor BUF 1, L_0000000004170890, C4<0>, C4<0>, C4<0>;
+v0000000003e0ab50_0 .net "A0", 0 0, o0000000003d9b5c8;  alias, 0 drivers
+v0000000003e0a8d0_0 .net "A1", 0 0, o0000000003d9b5f8;  alias, 0 drivers
+v0000000003e0b910_0 .net "S", 0 0, o0000000003d9b628;  alias, 0 drivers
+L_00000000040d2200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c6d0_0 .net8 "VGND", 0 0, L_00000000040d2200;  1 drivers, strength-aware
+L_00000000040d14e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b190_0 .net8 "VNB", 0 0, L_00000000040d14e0;  1 drivers, strength-aware
+L_00000000040d0f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0bb90_0 .net8 "VPB", 0 0, L_00000000040d0f30;  1 drivers, strength-aware
+L_00000000040d2270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c3b0_0 .net8 "VPWR", 0 0, L_00000000040d2270;  1 drivers, strength-aware
+v0000000003e0a830_0 .net "Y", 0 0, L_00000000041712a0;  alias, 1 drivers
+v0000000003e0c450_0 .net "mux_2to1_n0_out_Y", 0 0, L_0000000004170890;  1 drivers
+S_000000000291ba50 .scope module, "sky130_fd_sc_hd__mux2i_4" "sky130_fd_sc_hd__mux2i_4" 4 19624;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+o0000000003d9b9b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0f0b0_0 .net "A0", 0 0, o0000000003d9b9b8;  0 drivers
+o0000000003d9b9e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0e890_0 .net "A1", 0 0, o0000000003d9b9e8;  0 drivers
+o0000000003d9ba18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0f010_0 .net "S", 0 0, o0000000003d9ba18;  0 drivers
+L_00000000040d17f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0dad0_0 .net8 "VGND", 0 0, L_00000000040d17f0;  1 drivers, strength-aware
+L_00000000040d1b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0d530_0 .net8 "VNB", 0 0, L_00000000040d1b00;  1 drivers, strength-aware
+L_00000000040d1a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e1b0_0 .net8 "VPB", 0 0, L_00000000040d1a20;  1 drivers, strength-aware
+L_00000000040d1cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e9d0_0 .net8 "VPWR", 0 0, L_00000000040d1cc0;  1 drivers, strength-aware
+v0000000003e0d5d0_0 .net "Y", 0 0, L_0000000004170900;  1 drivers
+S_0000000003d1c6b0 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 19642, 4 19934 1, S_000000000291ba50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "S"
+L_0000000004170dd0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o0000000003d9b9b8, o0000000003d9b9e8, o0000000003d9ba18;
+L_0000000004170900 .functor BUF 1, L_0000000004170dd0, C4<0>, C4<0>, C4<0>;
+v0000000003e0aa10_0 .net "A0", 0 0, o0000000003d9b9b8;  alias, 0 drivers
+v0000000003e0b410_0 .net "A1", 0 0, o0000000003d9b9e8;  alias, 0 drivers
+v0000000003e0aab0_0 .net "S", 0 0, o0000000003d9ba18;  alias, 0 drivers
+L_00000000040d1a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0abf0_0 .net8 "VGND", 0 0, L_00000000040d1a90;  1 drivers, strength-aware
+L_00000000040d1be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b7d0_0 .net8 "VNB", 0 0, L_00000000040d1be0;  1 drivers, strength-aware
+L_00000000040d1d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0b870_0 .net8 "VPB", 0 0, L_00000000040d1d30;  1 drivers, strength-aware
+L_00000000040d1f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ad30_0 .net8 "VPWR", 0 0, L_00000000040d1f60;  1 drivers, strength-aware
+v0000000003e0e2f0_0 .net "Y", 0 0, L_0000000004170900;  alias, 1 drivers
+v0000000003e0dc10_0 .net "mux_2to1_n0_out_Y", 0 0, L_0000000004170dd0;  1 drivers
+S_0000000002918750 .scope module, "sky130_fd_sc_hd__mux4_1" "sky130_fd_sc_hd__mux4_1" 4 9008;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+o0000000003d9bda8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0ecf0_0 .net "A0", 0 0, o0000000003d9bda8;  0 drivers
+o0000000003d9bdd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0dfd0_0 .net "A1", 0 0, o0000000003d9bdd8;  0 drivers
+o0000000003d9be08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0d710_0 .net "A2", 0 0, o0000000003d9be08;  0 drivers
+o0000000003d9be38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0d7b0_0 .net "A3", 0 0, o0000000003d9be38;  0 drivers
+o0000000003d9be68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0ee30_0 .net "S0", 0 0, o0000000003d9be68;  0 drivers
+o0000000003d9be98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0da30_0 .net "S1", 0 0, o0000000003d9be98;  0 drivers
+L_00000000040d1fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0d490_0 .net8 "VGND", 0 0, L_00000000040d1fd0;  1 drivers, strength-aware
+L_00000000040d2580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0db70_0 .net8 "VNB", 0 0, L_00000000040d2580;  1 drivers, strength-aware
+L_00000000040d20b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ce50_0 .net8 "VPB", 0 0, L_00000000040d20b0;  1 drivers, strength-aware
+L_00000000040d2ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ea70_0 .net8 "VPWR", 0 0, L_00000000040d2ac0;  1 drivers, strength-aware
+v0000000003e0dcb0_0 .net "X", 0 0, L_0000000004171000;  1 drivers
+S_0000000003d1c830 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9032, 4 8877 1, S_0000000002918750;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+UDP_sky130_fd_sc_hd__udp_mux_4to2 .udp/comb "sky130_fd_sc_hd__udp_mux_4to2", 6
+ ,"0???000"
+ ,"1???001"
+ ,"?0??100"
+ ,"?1??101"
+ ,"??0?010"
+ ,"??1?011"
+ ,"???0110"
+ ,"???1111"
+ ,"0000??0"
+ ,"1111??1"
+ ,"00???00"
+ ,"11???01"
+ ,"??00?10"
+ ,"??11?11"
+ ,"0?0?0?0"
+ ,"1?1?0?1"
+ ,"?0?01?0"
+ ,"?1?11?1";
+L_00000000041700b0 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, o0000000003d9bda8, o0000000003d9bdd8, o0000000003d9be08, o0000000003d9be38, o0000000003d9be68, o0000000003d9be98;
+L_0000000004171000 .functor BUF 1, L_00000000041700b0, C4<0>, C4<0>, C4<0>;
+v0000000003e0c950_0 .net "A0", 0 0, o0000000003d9bda8;  alias, 0 drivers
+v0000000003e0cdb0_0 .net "A1", 0 0, o0000000003d9bdd8;  alias, 0 drivers
+v0000000003e0d670_0 .net "A2", 0 0, o0000000003d9be08;  alias, 0 drivers
+v0000000003e0d850_0 .net "A3", 0 0, o0000000003d9be38;  alias, 0 drivers
+v0000000003e0d8f0_0 .net "S0", 0 0, o0000000003d9be68;  alias, 0 drivers
+v0000000003e0de90_0 .net "S1", 0 0, o0000000003d9be98;  alias, 0 drivers
+L_00000000040d2f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ddf0_0 .net8 "VGND", 0 0, L_00000000040d2f90;  1 drivers, strength-aware
+L_00000000040d2900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0c9f0_0 .net8 "VNB", 0 0, L_00000000040d2900;  1 drivers, strength-aware
+L_00000000040d2c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0eed0_0 .net8 "VPB", 0 0, L_00000000040d2c80;  1 drivers, strength-aware
+L_00000000040d2d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0d170_0 .net8 "VPWR", 0 0, L_00000000040d2d60;  1 drivers, strength-aware
+v0000000003e0df30_0 .net "X", 0 0, L_0000000004171000;  alias, 1 drivers
+v0000000003e0d990_0 .net "mux_4to20_out_X", 0 0, L_00000000041700b0;  1 drivers
+S_000000000291acd0 .scope module, "sky130_fd_sc_hd__mux4_2" "sky130_fd_sc_hd__mux4_2" 4 9268;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+o0000000003d9c348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0e570_0 .net "A0", 0 0, o0000000003d9c348;  0 drivers
+o0000000003d9c378 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0d030_0 .net "A1", 0 0, o0000000003d9c378;  0 drivers
+o0000000003d9c3a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0e390_0 .net "A2", 0 0, o0000000003d9c3a8;  0 drivers
+o0000000003d9c3d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0d210_0 .net "A3", 0 0, o0000000003d9c3d8;  0 drivers
+o0000000003d9c408 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0cf90_0 .net "S0", 0 0, o0000000003d9c408;  0 drivers
+o0000000003d9c438 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0d2b0_0 .net "S1", 0 0, o0000000003d9c438;  0 drivers
+L_00000000040d2b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e430_0 .net8 "VGND", 0 0, L_00000000040d2b30;  1 drivers, strength-aware
+L_00000000040d2970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e610_0 .net8 "VNB", 0 0, L_00000000040d2970;  1 drivers, strength-aware
+L_00000000040d29e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e6b0_0 .net8 "VPB", 0 0, L_00000000040d29e0;  1 drivers, strength-aware
+L_00000000040d2cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e750_0 .net8 "VPWR", 0 0, L_00000000040d2cf0;  1 drivers, strength-aware
+v0000000003e0e7f0_0 .net "X", 0 0, L_0000000004170200;  1 drivers
+S_0000000003d1c9b0 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9292, 4 8877 1, S_000000000291acd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+L_000000000416fbe0 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, o0000000003d9c348, o0000000003d9c378, o0000000003d9c3a8, o0000000003d9c3d8, o0000000003d9c408, o0000000003d9c438;
+L_0000000004170200 .functor BUF 1, L_000000000416fbe0, C4<0>, C4<0>, C4<0>;
+v0000000003e0cc70_0 .net "A0", 0 0, o0000000003d9c348;  alias, 0 drivers
+v0000000003e0dd50_0 .net "A1", 0 0, o0000000003d9c378;  alias, 0 drivers
+v0000000003e0e070_0 .net "A2", 0 0, o0000000003d9c3a8;  alias, 0 drivers
+v0000000003e0eb10_0 .net "A3", 0 0, o0000000003d9c3d8;  alias, 0 drivers
+v0000000003e0cbd0_0 .net "S0", 0 0, o0000000003d9c408;  alias, 0 drivers
+v0000000003e0e930_0 .net "S1", 0 0, o0000000003d9c438;  alias, 0 drivers
+L_00000000040d2dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0cd10_0 .net8 "VGND", 0 0, L_00000000040d2dd0;  1 drivers, strength-aware
+L_00000000040d2a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e250_0 .net8 "VNB", 0 0, L_00000000040d2a50;  1 drivers, strength-aware
+L_00000000040d2e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e4d0_0 .net8 "VPB", 0 0, L_00000000040d2e40;  1 drivers, strength-aware
+L_00000000040d2ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0e110_0 .net8 "VPWR", 0 0, L_00000000040d2ba0;  1 drivers, strength-aware
+v0000000003e0d0d0_0 .net "X", 0 0, L_0000000004170200;  alias, 1 drivers
+v0000000003e0cef0_0 .net "mux_4to20_out_X", 0 0, L_000000000416fbe0;  1 drivers
+S_0000000002919050 .scope module, "sky130_fd_sc_hd__mux4_4" "sky130_fd_sc_hd__mux4_4" 4 9138;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+o0000000003d9c8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e11810_0 .net "A0", 0 0, o0000000003d9c8e8;  0 drivers
+o0000000003d9c918 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e102d0_0 .net "A1", 0 0, o0000000003d9c918;  0 drivers
+o0000000003d9c948 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0f330_0 .net "A2", 0 0, o0000000003d9c948;  0 drivers
+o0000000003d9c978 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0f150_0 .net "A3", 0 0, o0000000003d9c978;  0 drivers
+o0000000003d9c9a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0fdd0_0 .net "S0", 0 0, o0000000003d9c9a8;  0 drivers
+o0000000003d9c9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e10eb0_0 .net "S1", 0 0, o0000000003d9c9d8;  0 drivers
+L_00000000040d2c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e10cd0_0 .net8 "VGND", 0 0, L_00000000040d2c10;  1 drivers, strength-aware
+L_00000000040d2eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e10e10_0 .net8 "VNB", 0 0, L_00000000040d2eb0;  1 drivers, strength-aware
+L_00000000040d2f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e114f0_0 .net8 "VPB", 0 0, L_00000000040d2f20;  1 drivers, strength-aware
+L_00000000040b4670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fe70_0 .net8 "VPWR", 0 0, L_00000000040b4670;  1 drivers, strength-aware
+v0000000003e111d0_0 .net "X", 0 0, L_00000000041710e0;  1 drivers
+S_0000000003d1ef30 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9162, 4 8877 1, S_0000000002919050;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A0"
+    .port_info 2 /INPUT 1 "A1"
+    .port_info 3 /INPUT 1 "A2"
+    .port_info 4 /INPUT 1 "A3"
+    .port_info 5 /INPUT 1 "S0"
+    .port_info 6 /INPUT 1 "S1"
+L_000000000416fef0 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, o0000000003d9c8e8, o0000000003d9c918, o0000000003d9c948, o0000000003d9c978, o0000000003d9c9a8, o0000000003d9c9d8;
+L_00000000041710e0 .functor BUF 1, L_000000000416fef0, C4<0>, C4<0>, C4<0>;
+v0000000003e0d350_0 .net "A0", 0 0, o0000000003d9c8e8;  alias, 0 drivers
+v0000000003e0d3f0_0 .net "A1", 0 0, o0000000003d9c918;  alias, 0 drivers
+v0000000003e0ebb0_0 .net "A2", 0 0, o0000000003d9c948;  alias, 0 drivers
+v0000000003e0ec50_0 .net "A3", 0 0, o0000000003d9c978;  alias, 0 drivers
+v0000000003e0ed90_0 .net "S0", 0 0, o0000000003d9c9a8;  alias, 0 drivers
+v0000000003e0ef70_0 .net "S1", 0 0, o0000000003d9c9d8;  alias, 0 drivers
+L_00000000040b46e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ca90_0 .net8 "VGND", 0 0, L_00000000040b46e0;  1 drivers, strength-aware
+L_00000000040b4980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0cb30_0 .net8 "VNB", 0 0, L_00000000040b4980;  1 drivers, strength-aware
+L_00000000040b4210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0ff10_0 .net8 "VPB", 0 0, L_00000000040b4210;  1 drivers, strength-aware
+L_00000000040b47c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10410_0 .net8 "VPWR", 0 0, L_00000000040b47c0;  1 drivers, strength-aware
+v0000000003e116d0_0 .net "X", 0 0, L_00000000041710e0;  alias, 1 drivers
+v0000000003e11770_0 .net "mux_4to20_out_X", 0 0, L_000000000416fef0;  1 drivers
+S_000000000291a6d0 .scope module, "sky130_fd_sc_hd__nand2_1" "sky130_fd_sc_hd__nand2_1" 4 8144;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9ce88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e107d0_0 .net "A", 0 0, o0000000003d9ce88;  0 drivers
+o0000000003d9ceb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e10050_0 .net "B", 0 0, o0000000003d9ceb8;  0 drivers
+L_00000000040b49f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e100f0_0 .net8 "VGND", 0 0, L_00000000040b49f0;  1 drivers, strength-aware
+L_00000000040b4750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e113b0_0 .net8 "VNB", 0 0, L_00000000040b4750;  1 drivers, strength-aware
+L_00000000040b4830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10230_0 .net8 "VPB", 0 0, L_00000000040b4830;  1 drivers, strength-aware
+L_00000000040b3330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10af0_0 .net8 "VPWR", 0 0, L_00000000040b3330;  1 drivers, strength-aware
+v0000000003e11310_0 .net "Y", 0 0, L_000000000416fd30;  1 drivers
+S_0000000003d19230 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8160, 4 8441 1, S_000000000291a6d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170970 .functor NAND 1, o0000000003d9ceb8, o0000000003d9ce88, C4<1>, C4<1>;
+L_000000000416fd30 .functor BUF 1, L_0000000004170970, C4<0>, C4<0>, C4<0>;
+v0000000003e105f0_0 .net "A", 0 0, o0000000003d9ce88;  alias, 0 drivers
+v0000000003e10a50_0 .net "B", 0 0, o0000000003d9ceb8;  alias, 0 drivers
+L_00000000040b3c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fd30_0 .net8 "VGND", 0 0, L_00000000040b3c60;  1 drivers, strength-aware
+L_00000000040b48a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e10690_0 .net8 "VNB", 0 0, L_00000000040b48a0;  1 drivers, strength-aware
+L_00000000040b3950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10190_0 .net8 "VPB", 0 0, L_00000000040b3950;  1 drivers, strength-aware
+L_00000000040b3b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f8d0_0 .net8 "VPWR", 0 0, L_00000000040b3b10;  1 drivers, strength-aware
+v0000000003e0ffb0_0 .net "Y", 0 0, L_000000000416fd30;  alias, 1 drivers
+v0000000003e10730_0 .net "nand0_out_Y", 0 0, L_0000000004170970;  1 drivers
+S_0000000002919f50 .scope module, "sky130_fd_sc_hd__nand2_4" "sky130_fd_sc_hd__nand2_4" 4 7932;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9d1e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e11090_0 .net "A", 0 0, o0000000003d9d1e8;  0 drivers
+o0000000003d9d218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e0f290_0 .net "B", 0 0, o0000000003d9d218;  0 drivers
+L_00000000040b4280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fc90_0 .net8 "VGND", 0 0, L_00000000040b4280;  1 drivers, strength-aware
+L_00000000040b35d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e10d70_0 .net8 "VNB", 0 0, L_00000000040b35d0;  1 drivers, strength-aware
+L_00000000040b4c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10870_0 .net8 "VPB", 0 0, L_00000000040b4c20;  1 drivers, strength-aware
+L_00000000040b33a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e10910_0 .net8 "VPWR", 0 0, L_00000000040b33a0;  1 drivers, strength-aware
+v0000000003e0f3d0_0 .net "Y", 0 0, L_0000000004170040;  1 drivers
+S_0000000003d193b0 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 7948, 4 8441 1, S_0000000002919f50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000416fda0 .functor NAND 1, o0000000003d9d218, o0000000003d9d1e8, C4<1>, C4<1>;
+L_0000000004170040 .functor BUF 1, L_000000000416fda0, C4<0>, C4<0>, C4<0>;
+v0000000003e0f1f0_0 .net "A", 0 0, o0000000003d9d1e8;  alias, 0 drivers
+v0000000003e10370_0 .net "B", 0 0, o0000000003d9d218;  alias, 0 drivers
+L_00000000040b4c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e11630_0 .net8 "VGND", 0 0, L_00000000040b4c90;  1 drivers, strength-aware
+L_00000000040b44b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e118b0_0 .net8 "VNB", 0 0, L_00000000040b44b0;  1 drivers, strength-aware
+L_00000000040b3f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fa10_0 .net8 "VPB", 0 0, L_00000000040b3f00;  1 drivers, strength-aware
+L_00000000040b3100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e104b0_0 .net8 "VPWR", 0 0, L_00000000040b3100;  1 drivers, strength-aware
+v0000000003e10550_0 .net "Y", 0 0, L_0000000004170040;  alias, 1 drivers
+v0000000003e109b0_0 .net "nand0_out_Y", 0 0, L_000000000416fda0;  1 drivers
+S_000000000291b450 .scope module, "sky130_fd_sc_hd__nand2_8" "sky130_fd_sc_hd__nand2_8" 4 8038;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9d548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e11270_0 .net "A", 0 0, o0000000003d9d548;  0 drivers
+o0000000003d9d578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e10ff0_0 .net "B", 0 0, o0000000003d9d578;  0 drivers
+L_00000000040b3170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e11450_0 .net8 "VGND", 0 0, L_00000000040b3170;  1 drivers, strength-aware
+L_00000000040b3b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f510_0 .net8 "VNB", 0 0, L_00000000040b3b80;  1 drivers, strength-aware
+L_00000000040b3aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f5b0_0 .net8 "VPB", 0 0, L_00000000040b3aa0;  1 drivers, strength-aware
+L_00000000040b4910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f790_0 .net8 "VPWR", 0 0, L_00000000040b4910;  1 drivers, strength-aware
+v0000000003e0f970_0 .net "Y", 0 0, L_0000000004171150;  1 drivers
+S_0000000003d19530 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8054, 4 8441 1, S_000000000291b450;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041702e0 .functor NAND 1, o0000000003d9d578, o0000000003d9d548, C4<1>, C4<1>;
+L_0000000004171150 .functor BUF 1, L_00000000041702e0, C4<0>, C4<0>, C4<0>;
+v0000000003e10b90_0 .net "A", 0 0, o0000000003d9d548;  alias, 0 drivers
+v0000000003e11130_0 .net "B", 0 0, o0000000003d9d578;  alias, 0 drivers
+L_00000000040b39c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e10c30_0 .net8 "VGND", 0 0, L_00000000040b39c0;  1 drivers, strength-aware
+L_00000000040b4360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e11590_0 .net8 "VNB", 0 0, L_00000000040b4360;  1 drivers, strength-aware
+L_00000000040b43d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f6f0_0 .net8 "VPB", 0 0, L_00000000040b43d0;  1 drivers, strength-aware
+L_00000000040b3a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e0f470_0 .net8 "VPWR", 0 0, L_00000000040b3a30;  1 drivers, strength-aware
+v0000000003e0f650_0 .net "Y", 0 0, L_0000000004171150;  alias, 1 drivers
+v0000000003e10f50_0 .net "nand0_out_Y", 0 0, L_00000000041702e0;  1 drivers
+S_0000000002919350 .scope module, "sky130_fd_sc_hd__nand2b_1" "sky130_fd_sc_hd__nand2b_1" 4 50222;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9d8a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e120d0_0 .net "A_N", 0 0, o0000000003d9d8a8;  0 drivers
+o0000000003d9d8d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e13570_0 .net "B", 0 0, o0000000003d9d8d8;  0 drivers
+L_00000000040b38e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e13ed0_0 .net8 "VGND", 0 0, L_00000000040b38e0;  1 drivers, strength-aware
+L_00000000040b4a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12030_0 .net8 "VNB", 0 0, L_00000000040b4a60;  1 drivers, strength-aware
+L_00000000040b4ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e136b0_0 .net8 "VPB", 0 0, L_00000000040b4ad0;  1 drivers, strength-aware
+L_00000000040b4b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e12170_0 .net8 "VPWR", 0 0, L_00000000040b4b40;  1 drivers, strength-aware
+v0000000003e127b0_0 .net "Y", 0 0, L_0000000004170350;  1 drivers
+S_0000000003d20d30 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50238, 4 50525 1, S_0000000002919350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170e40 .functor NOT 1, o0000000003d9d8d8, C4<0>, C4<0>, C4<0>;
+L_0000000004170a50 .functor OR 1, L_0000000004170e40, o0000000003d9d8a8, C4<0>, C4<0>;
+L_0000000004170350 .functor BUF 1, L_0000000004170a50, C4<0>, C4<0>, C4<0>;
+v0000000003e0f830_0 .net "A_N", 0 0, o0000000003d9d8a8;  alias, 0 drivers
+v0000000003e0fab0_0 .net "B", 0 0, o0000000003d9d8d8;  alias, 0 drivers
+L_00000000040b42f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fb50_0 .net8 "VGND", 0 0, L_00000000040b42f0;  1 drivers, strength-aware
+L_00000000040b4bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e0fbf0_0 .net8 "VNB", 0 0, L_00000000040b4bb0;  1 drivers, strength-aware
+L_00000000040b31e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e134d0_0 .net8 "VPB", 0 0, L_00000000040b31e0;  1 drivers, strength-aware
+L_00000000040b3250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e12cb0_0 .net8 "VPWR", 0 0, L_00000000040b3250;  1 drivers, strength-aware
+v0000000003e13610_0 .net "Y", 0 0, L_0000000004170350;  alias, 1 drivers
+v0000000003e11e50_0 .net "not0_out", 0 0, L_0000000004170e40;  1 drivers
+v0000000003e11950_0 .net "or0_out_Y", 0 0, L_0000000004170a50;  1 drivers
+S_00000000029191d0 .scope module, "sky130_fd_sc_hd__nand2b_2" "sky130_fd_sc_hd__nand2b_2" 4 50010;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9dc38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e12c10_0 .net "A_N", 0 0, o0000000003d9dc38;  0 drivers
+o0000000003d9dc68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e11db0_0 .net "B", 0 0, o0000000003d9dc68;  0 drivers
+L_00000000040b32c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e11bd0_0 .net8 "VGND", 0 0, L_00000000040b32c0;  1 drivers, strength-aware
+L_00000000040b3410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12850_0 .net8 "VNB", 0 0, L_00000000040b3410;  1 drivers, strength-aware
+L_00000000040b3cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13890_0 .net8 "VPB", 0 0, L_00000000040b3cd0;  1 drivers, strength-aware
+L_00000000040b3480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e137f0_0 .net8 "VPWR", 0 0, L_00000000040b3480;  1 drivers, strength-aware
+v0000000003e12df0_0 .net "Y", 0 0, L_0000000004170ba0;  1 drivers
+S_0000000003d1ffb0 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50026, 4 50525 1, S_00000000029191d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004170ac0 .functor NOT 1, o0000000003d9dc68, C4<0>, C4<0>, C4<0>;
+L_0000000004170b30 .functor OR 1, L_0000000004170ac0, o0000000003d9dc38, C4<0>, C4<0>;
+L_0000000004170ba0 .functor BUF 1, L_0000000004170b30, C4<0>, C4<0>, C4<0>;
+v0000000003e13250_0 .net "A_N", 0 0, o0000000003d9dc38;  alias, 0 drivers
+v0000000003e12210_0 .net "B", 0 0, o0000000003d9dc68;  alias, 0 drivers
+L_00000000040b3bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12d50_0 .net8 "VGND", 0 0, L_00000000040b3bf0;  1 drivers, strength-aware
+L_00000000040b3d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e11a90_0 .net8 "VNB", 0 0, L_00000000040b3d40;  1 drivers, strength-aware
+L_00000000040b4440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13750_0 .net8 "VPB", 0 0, L_00000000040b4440;  1 drivers, strength-aware
+L_00000000040b3640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13e30_0 .net8 "VPWR", 0 0, L_00000000040b3640;  1 drivers, strength-aware
+v0000000003e12670_0 .net "Y", 0 0, L_0000000004170ba0;  alias, 1 drivers
+v0000000003e119f0_0 .net "not0_out", 0 0, L_0000000004170ac0;  1 drivers
+v0000000003e11b30_0 .net "or0_out_Y", 0 0, L_0000000004170b30;  1 drivers
+S_0000000002918d50 .scope module, "sky130_fd_sc_hd__nand2b_4" "sky130_fd_sc_hd__nand2b_4" 4 50116;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+o0000000003d9dfc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e12fd0_0 .net "A_N", 0 0, o0000000003d9dfc8;  0 drivers
+o0000000003d9dff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e12490_0 .net "B", 0 0, o0000000003d9dff8;  0 drivers
+L_00000000040b34f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e13070_0 .net8 "VGND", 0 0, L_00000000040b34f0;  1 drivers, strength-aware
+L_00000000040b3560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e13bb0_0 .net8 "VNB", 0 0, L_00000000040b3560;  1 drivers, strength-aware
+L_00000000040b36b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e11f90_0 .net8 "VPB", 0 0, L_00000000040b36b0;  1 drivers, strength-aware
+L_00000000040b4520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13930_0 .net8 "VPWR", 0 0, L_00000000040b4520;  1 drivers, strength-aware
+v0000000003e13d90_0 .net "Y", 0 0, L_0000000004172110;  1 drivers
+S_0000000003d20a30 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50132, 4 50525 1, S_0000000002918d50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004172490 .functor NOT 1, o0000000003d9dff8, C4<0>, C4<0>, C4<0>;
+L_0000000004171af0 .functor OR 1, L_0000000004172490, o0000000003d9dfc8, C4<0>, C4<0>;
+L_0000000004172110 .functor BUF 1, L_0000000004171af0, C4<0>, C4<0>, C4<0>;
+v0000000003e128f0_0 .net "A_N", 0 0, o0000000003d9dfc8;  alias, 0 drivers
+v0000000003e12ad0_0 .net "B", 0 0, o0000000003d9dff8;  alias, 0 drivers
+L_00000000040b3f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12990_0 .net8 "VGND", 0 0, L_00000000040b3f70;  1 drivers, strength-aware
+L_00000000040b3720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e122b0_0 .net8 "VNB", 0 0, L_00000000040b3720;  1 drivers, strength-aware
+L_00000000040b3db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e11ef0_0 .net8 "VPB", 0 0, L_00000000040b3db0;  1 drivers, strength-aware
+L_00000000040b3790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e11c70_0 .net8 "VPWR", 0 0, L_00000000040b3790;  1 drivers, strength-aware
+v0000000003e12a30_0 .net "Y", 0 0, L_0000000004172110;  alias, 1 drivers
+v0000000003e12350_0 .net "not0_out", 0 0, L_0000000004172490;  1 drivers
+v0000000003e13a70_0 .net "or0_out_Y", 0 0, L_0000000004171af0;  1 drivers
+S_000000000291b5d0 .scope module, "sky130_fd_sc_hd__nand3_1" "sky130_fd_sc_hd__nand3_1" 4 4208;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9e358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e12710_0 .net "A", 0 0, o0000000003d9e358;  0 drivers
+o0000000003d9e388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e13110_0 .net "B", 0 0, o0000000003d9e388;  0 drivers
+o0000000003d9e3b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e131b0_0 .net "C", 0 0, o0000000003d9e3b8;  0 drivers
+L_00000000040b3800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e132f0_0 .net8 "VGND", 0 0, L_00000000040b3800;  1 drivers, strength-aware
+L_00000000040b3870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e13430_0 .net8 "VNB", 0 0, L_00000000040b3870;  1 drivers, strength-aware
+L_00000000040b3e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e139d0_0 .net8 "VPB", 0 0, L_00000000040b3e20;  1 drivers, strength-aware
+L_00000000040b3e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13b10_0 .net8 "VPWR", 0 0, L_00000000040b3e90;  1 drivers, strength-aware
+v0000000003e13cf0_0 .net "Y", 0 0, L_0000000004171e70;  1 drivers
+S_0000000003d1fb30 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4226, 4 3980 1, S_000000000291b5d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004171d90 .functor NAND 1, o0000000003d9e388, o0000000003d9e358, o0000000003d9e3b8, C4<1>;
+L_0000000004171e70 .functor BUF 1, L_0000000004171d90, C4<0>, C4<0>, C4<0>;
+v0000000003e13c50_0 .net "A", 0 0, o0000000003d9e358;  alias, 0 drivers
+v0000000003e11d10_0 .net "B", 0 0, o0000000003d9e388;  alias, 0 drivers
+v0000000003e123f0_0 .net "C", 0 0, o0000000003d9e3b8;  alias, 0 drivers
+L_00000000040b3fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12530_0 .net8 "VGND", 0 0, L_00000000040b3fe0;  1 drivers, strength-aware
+L_00000000040b4050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e12b70_0 .net8 "VNB", 0 0, L_00000000040b4050;  1 drivers, strength-aware
+L_00000000040b40c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e13390_0 .net8 "VPB", 0 0, L_00000000040b40c0;  1 drivers, strength-aware
+L_00000000040b4130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e125d0_0 .net8 "VPWR", 0 0, L_00000000040b4130;  1 drivers, strength-aware
+v0000000003e12f30_0 .net "Y", 0 0, L_0000000004171e70;  alias, 1 drivers
+v0000000003e12e90_0 .net "nand0_out_Y", 0 0, L_0000000004171d90;  1 drivers
+S_00000000029188d0 .scope module, "sky130_fd_sc_hd__nand3_2" "sky130_fd_sc_hd__nand3_2" 4 4096;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9e748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e28c20_0 .net "A", 0 0, o0000000003d9e748;  0 drivers
+o0000000003d9e778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e27a00_0 .net "B", 0 0, o0000000003d9e778;  0 drivers
+o0000000003d9e7a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e28220_0 .net "C", 0 0, o0000000003d9e7a8;  0 drivers
+L_00000000040b41a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e27fa0_0 .net8 "VGND", 0 0, L_00000000040b41a0;  1 drivers, strength-aware
+L_00000000040b4590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e27320_0 .net8 "VNB", 0 0, L_00000000040b4590;  1 drivers, strength-aware
+L_00000000040b4600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e282c0_0 .net8 "VPB", 0 0, L_00000000040b4600;  1 drivers, strength-aware
+L_00000000040e5320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e27aa0_0 .net8 "VPWR", 0 0, L_00000000040e5320;  1 drivers, strength-aware
+v0000000003e278c0_0 .net "Y", 0 0, L_0000000004171e00;  1 drivers
+S_0000000003d20430 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4114, 4 3980 1, S_00000000029188d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004172730 .functor NAND 1, o0000000003d9e778, o0000000003d9e748, o0000000003d9e7a8, C4<1>;
+L_0000000004171e00 .functor BUF 1, L_0000000004172730, C4<0>, C4<0>, C4<0>;
+v0000000003e28040_0 .net "A", 0 0, o0000000003d9e748;  alias, 0 drivers
+v0000000003e27e60_0 .net "B", 0 0, o0000000003d9e778;  alias, 0 drivers
+v0000000003e273c0_0 .net "C", 0 0, o0000000003d9e7a8;  alias, 0 drivers
+L_00000000040e67b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e27820_0 .net8 "VGND", 0 0, L_00000000040e67b0;  1 drivers, strength-aware
+L_00000000040e6350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e28b80_0 .net8 "VNB", 0 0, L_00000000040e6350;  1 drivers, strength-aware
+L_00000000040e5b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e27140_0 .net8 "VPB", 0 0, L_00000000040e5b70;  1 drivers, strength-aware
+L_00000000040e6740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e280e0_0 .net8 "VPWR", 0 0, L_00000000040e6740;  1 drivers, strength-aware
+v0000000003e28540_0 .net "Y", 0 0, L_0000000004171e00;  alias, 1 drivers
+v0000000003e28fe0_0 .net "nand0_out_Y", 0 0, L_0000000004172730;  1 drivers
+S_000000000291bbd0 .scope module, "sky130_fd_sc_hd__nand3_4" "sky130_fd_sc_hd__nand3_4" 4 4320;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9eb38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e28ea0_0 .net "A", 0 0, o0000000003d9eb38;  0 drivers
+o0000000003d9eb68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e28d60_0 .net "B", 0 0, o0000000003d9eb68;  0 drivers
+o0000000003d9eb98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e29580_0 .net "C", 0 0, o0000000003d9eb98;  0 drivers
+L_00000000040e5be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e28180_0 .net8 "VGND", 0 0, L_00000000040e5be0;  1 drivers, strength-aware
+L_00000000040e6200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e291c0_0 .net8 "VNB", 0 0, L_00000000040e6200;  1 drivers, strength-aware
+L_00000000040e5710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e28cc0_0 .net8 "VPB", 0 0, L_00000000040e5710;  1 drivers, strength-aware
+L_00000000040e5630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e27d20_0 .net8 "VPWR", 0 0, L_00000000040e5630;  1 drivers, strength-aware
+v0000000003e28360_0 .net "Y", 0 0, L_0000000004172180;  1 drivers
+S_0000000003d202b0 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4338, 4 3980 1, S_000000000291bbd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_00000000041717e0 .functor NAND 1, o0000000003d9eb68, o0000000003d9eb38, o0000000003d9eb98, C4<1>;
+L_0000000004172180 .functor BUF 1, L_00000000041717e0, C4<0>, C4<0>, C4<0>;
+v0000000003e28400_0 .net "A", 0 0, o0000000003d9eb38;  alias, 0 drivers
+v0000000003e28a40_0 .net "B", 0 0, o0000000003d9eb68;  alias, 0 drivers
+v0000000003e27f00_0 .net "C", 0 0, o0000000003d9eb98;  alias, 0 drivers
+L_00000000040e5940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e294e0_0 .net8 "VGND", 0 0, L_00000000040e5940;  1 drivers, strength-aware
+L_00000000040e5400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29080_0 .net8 "VNB", 0 0, L_00000000040e5400;  1 drivers, strength-aware
+L_00000000040e5a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e29800_0 .net8 "VPB", 0 0, L_00000000040e5a20;  1 drivers, strength-aware
+L_00000000040e62e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e289a0_0 .net8 "VPWR", 0 0, L_00000000040e62e0;  1 drivers, strength-aware
+v0000000003e27dc0_0 .net "Y", 0 0, L_0000000004172180;  alias, 1 drivers
+v0000000003e27460_0 .net "nand0_out_Y", 0 0, L_00000000041717e0;  1 drivers
+S_0000000002918ed0 .scope module, "sky130_fd_sc_hd__nand3b_1" "sky130_fd_sc_hd__nand3b_1" 4 69205;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9ef28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e27be0_0 .net "A_N", 0 0, o0000000003d9ef28;  0 drivers
+o0000000003d9ef58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e27c80_0 .net "B", 0 0, o0000000003d9ef58;  0 drivers
+o0000000003d9ef88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e29300_0 .net "C", 0 0, o0000000003d9ef88;  0 drivers
+L_00000000040e5c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e287c0_0 .net8 "VGND", 0 0, L_00000000040e5c50;  1 drivers, strength-aware
+L_00000000040e6c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e28860_0 .net8 "VNB", 0 0, L_00000000040e6c10;  1 drivers, strength-aware
+L_00000000040e5390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e28900_0 .net8 "VPB", 0 0, L_00000000040e5390;  1 drivers, strength-aware
+L_00000000040e69e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e293a0_0 .net8 "VPWR", 0 0, L_00000000040e69e0;  1 drivers, strength-aware
+v0000000003e29620_0 .net "Y", 0 0, L_0000000004172ce0;  1 drivers
+S_0000000003d1f3b0 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69223, 4 69517 1, S_0000000002918ed0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_00000000041721f0 .functor NOT 1, o0000000003d9ef28, C4<0>, C4<0>, C4<0>;
+L_0000000004171ee0 .functor NAND 1, o0000000003d9ef58, L_00000000041721f0, o0000000003d9ef88, C4<1>;
+L_0000000004172ce0 .functor BUF 1, L_0000000004171ee0, C4<0>, C4<0>, C4<0>;
+v0000000003e296c0_0 .net "A_N", 0 0, o0000000003d9ef28;  alias, 0 drivers
+v0000000003e27960_0 .net "B", 0 0, o0000000003d9ef58;  alias, 0 drivers
+v0000000003e29120_0 .net "C", 0 0, o0000000003d9ef88;  alias, 0 drivers
+L_00000000040e50f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e284a0_0 .net8 "VGND", 0 0, L_00000000040e50f0;  1 drivers, strength-aware
+L_00000000040e5d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e27500_0 .net8 "VNB", 0 0, L_00000000040e5d30;  1 drivers, strength-aware
+L_00000000040e6580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e28680_0 .net8 "VPB", 0 0, L_00000000040e6580;  1 drivers, strength-aware
+L_00000000040e6510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e27b40_0 .net8 "VPWR", 0 0, L_00000000040e6510;  1 drivers, strength-aware
+v0000000003e28ae0_0 .net "Y", 0 0, L_0000000004172ce0;  alias, 1 drivers
+v0000000003e285e0_0 .net "nand0_out_Y", 0 0, L_0000000004171ee0;  1 drivers
+v0000000003e28720_0 .net "not0_out", 0 0, L_00000000041721f0;  1 drivers
+S_000000000291b150 .scope module, "sky130_fd_sc_hd__nand3b_2" "sky130_fd_sc_hd__nand3b_2" 4 69635;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9f348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e276e0_0 .net "A_N", 0 0, o0000000003d9f348;  0 drivers
+o0000000003d9f378 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e27780_0 .net "B", 0 0, o0000000003d9f378;  0 drivers
+o0000000003d9f3a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e29ee0_0 .net "C", 0 0, o0000000003d9f3a8;  0 drivers
+L_00000000040e5470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29e40_0 .net8 "VGND", 0 0, L_00000000040e5470;  1 drivers, strength-aware
+L_00000000040e54e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a8e0_0 .net8 "VNB", 0 0, L_00000000040e54e0;  1 drivers, strength-aware
+L_00000000040e5e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2ad40_0 .net8 "VPB", 0 0, L_00000000040e5e80;  1 drivers, strength-aware
+L_00000000040e6820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e29da0_0 .net8 "VPWR", 0 0, L_00000000040e6820;  1 drivers, strength-aware
+v0000000003e2ade0_0 .net "Y", 0 0, L_0000000004171f50;  1 drivers
+S_0000000003d20eb0 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69653, 4 69517 1, S_000000000291b150;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004172d50 .functor NOT 1, o0000000003d9f348, C4<0>, C4<0>, C4<0>;
+L_00000000041715b0 .functor NAND 1, o0000000003d9f378, L_0000000004172d50, o0000000003d9f3a8, C4<1>;
+L_0000000004171f50 .functor BUF 1, L_00000000041715b0, C4<0>, C4<0>, C4<0>;
+v0000000003e275a0_0 .net "A_N", 0 0, o0000000003d9f348;  alias, 0 drivers
+v0000000003e28e00_0 .net "B", 0 0, o0000000003d9f378;  alias, 0 drivers
+v0000000003e298a0_0 .net "C", 0 0, o0000000003d9f3a8;  alias, 0 drivers
+L_00000000040e6430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29760_0 .net8 "VGND", 0 0, L_00000000040e6430;  1 drivers, strength-aware
+L_00000000040e6c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29260_0 .net8 "VNB", 0 0, L_00000000040e6c80;  1 drivers, strength-aware
+L_00000000040e65f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e271e0_0 .net8 "VPB", 0 0, L_00000000040e65f0;  1 drivers, strength-aware
+L_00000000040e5e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e27280_0 .net8 "VPWR", 0 0, L_00000000040e5e10;  1 drivers, strength-aware
+v0000000003e28f40_0 .net "Y", 0 0, L_0000000004171f50;  alias, 1 drivers
+v0000000003e29440_0 .net "nand0_out_Y", 0 0, L_00000000041715b0;  1 drivers
+v0000000003e27640_0 .net "not0_out", 0 0, L_0000000004172d50;  1 drivers
+S_000000000291afd0 .scope module, "sky130_fd_sc_hd__nand3b_4" "sky130_fd_sc_hd__nand3b_4" 4 69093;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003d9f768 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2a5c0_0 .net "A_N", 0 0, o0000000003d9f768;  0 drivers
+o0000000003d9f798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e29f80_0 .net "B", 0 0, o0000000003d9f798;  0 drivers
+o0000000003d9f7c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2b9c0_0 .net "C", 0 0, o0000000003d9f7c8;  0 drivers
+L_00000000040e58d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c000_0 .net8 "VGND", 0 0, L_00000000040e58d0;  1 drivers, strength-aware
+L_00000000040e5a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2aca0_0 .net8 "VNB", 0 0, L_00000000040e5a90;  1 drivers, strength-aware
+L_00000000040e6890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b600_0 .net8 "VPB", 0 0, L_00000000040e6890;  1 drivers, strength-aware
+L_00000000040e6b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2bce0_0 .net8 "VPWR", 0 0, L_00000000040e6b30;  1 drivers, strength-aware
+v0000000003e2a7a0_0 .net "Y", 0 0, L_0000000004171c40;  1 drivers
+S_0000000003d1fe30 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69111, 4 69517 1, S_000000000291afd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004171a10 .functor NOT 1, o0000000003d9f768, C4<0>, C4<0>, C4<0>;
+L_0000000004171fc0 .functor NAND 1, o0000000003d9f798, L_0000000004171a10, o0000000003d9f7c8, C4<1>;
+L_0000000004171c40 .functor BUF 1, L_0000000004171fc0, C4<0>, C4<0>, C4<0>;
+v0000000003e2a0c0_0 .net "A_N", 0 0, o0000000003d9f768;  alias, 0 drivers
+v0000000003e2ae80_0 .net "B", 0 0, o0000000003d9f798;  alias, 0 drivers
+v0000000003e2b060_0 .net "C", 0 0, o0000000003d9f7c8;  alias, 0 drivers
+L_00000000040e5550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a700_0 .net8 "VGND", 0 0, L_00000000040e5550;  1 drivers, strength-aware
+L_00000000040e6900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e299e0_0 .net8 "VNB", 0 0, L_00000000040e6900;  1 drivers, strength-aware
+L_00000000040e63c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2bec0_0 .net8 "VPB", 0 0, L_00000000040e63c0;  1 drivers, strength-aware
+L_00000000040e5cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2bf60_0 .net8 "VPWR", 0 0, L_00000000040e5cc0;  1 drivers, strength-aware
+v0000000003e2a660_0 .net "Y", 0 0, L_0000000004171c40;  alias, 1 drivers
+v0000000003e2c0a0_0 .net "nand0_out_Y", 0 0, L_0000000004171fc0;  1 drivers
+v0000000003e2b880_0 .net "not0_out", 0 0, L_0000000004171a10;  1 drivers
+S_00000000029182d0 .scope module, "sky130_fd_sc_hd__nand4_1" "sky130_fd_sc_hd__nand4_1" 4 25605;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003d9fb88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2b7e0_0 .net "A", 0 0, o0000000003d9fb88;  0 drivers
+o0000000003d9fbb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e29bc0_0 .net "B", 0 0, o0000000003d9fbb8;  0 drivers
+o0000000003d9fbe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2b560_0 .net "C", 0 0, o0000000003d9fbe8;  0 drivers
+o0000000003d9fc18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2a340_0 .net "D", 0 0, o0000000003d9fc18;  0 drivers
+L_00000000040e6970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b420_0 .net8 "VGND", 0 0, L_00000000040e6970;  1 drivers, strength-aware
+L_00000000040e5da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a840_0 .net8 "VNB", 0 0, L_00000000040e5da0;  1 drivers, strength-aware
+L_00000000040e6270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a2a0_0 .net8 "VPB", 0 0, L_00000000040e6270;  1 drivers, strength-aware
+L_00000000040e5780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a3e0_0 .net8 "VPWR", 0 0, L_00000000040e5780;  1 drivers, strength-aware
+v0000000003e2aa20_0 .net "Y", 0 0, L_0000000004172650;  1 drivers
+S_0000000003d205b0 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25625, 4 25484 1, S_00000000029182d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172ab0 .functor NAND 1, o0000000003d9fc18, o0000000003d9fbe8, o0000000003d9fbb8, o0000000003d9fb88;
+L_0000000004172650 .functor BUF 1, L_0000000004172ab0, C4<0>, C4<0>, C4<0>;
+v0000000003e2b380_0 .net "A", 0 0, o0000000003d9fb88;  alias, 0 drivers
+v0000000003e2a020_0 .net "B", 0 0, o0000000003d9fbb8;  alias, 0 drivers
+v0000000003e2af20_0 .net "C", 0 0, o0000000003d9fbe8;  alias, 0 drivers
+v0000000003e2b240_0 .net "D", 0 0, o0000000003d9fc18;  alias, 0 drivers
+L_00000000040e56a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29d00_0 .net8 "VGND", 0 0, L_00000000040e56a0;  1 drivers, strength-aware
+L_00000000040e59b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a160_0 .net8 "VNB", 0 0, L_00000000040e59b0;  1 drivers, strength-aware
+L_00000000040e55c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b920_0 .net8 "VPB", 0 0, L_00000000040e55c0;  1 drivers, strength-aware
+L_00000000040e5b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2a980_0 .net8 "VPWR", 0 0, L_00000000040e5b00;  1 drivers, strength-aware
+v0000000003e2a200_0 .net "Y", 0 0, L_0000000004172650;  alias, 1 drivers
+v0000000003e2afc0_0 .net "nand0_out_Y", 0 0, L_0000000004172ab0;  1 drivers
+S_000000000291a550 .scope module, "sky130_fd_sc_hd__nand4_2" "sky130_fd_sc_hd__nand4_2" 4 25169;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da0008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2bba0_0 .net "A", 0 0, o0000000003da0008;  0 drivers
+o0000000003da0038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2b2e0_0 .net "B", 0 0, o0000000003da0038;  0 drivers
+o0000000003da0068 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2bd80_0 .net "C", 0 0, o0000000003da0068;  0 drivers
+o0000000003da0098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2ac00_0 .net "D", 0 0, o0000000003da0098;  0 drivers
+L_00000000040e64a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29b20_0 .net8 "VGND", 0 0, L_00000000040e64a0;  1 drivers, strength-aware
+L_00000000040e5ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b4c0_0 .net8 "VNB", 0 0, L_00000000040e5ef0;  1 drivers, strength-aware
+L_00000000040e5160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b100_0 .net8 "VPB", 0 0, L_00000000040e5160;  1 drivers, strength-aware
+L_00000000040e57f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2b1a0_0 .net8 "VPWR", 0 0, L_00000000040e57f0;  1 drivers, strength-aware
+v0000000003e2b740_0 .net "Y", 0 0, L_00000000041727a0;  1 drivers
+S_0000000003d1f9b0 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25189, 4 25484 1, S_000000000291a550;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172030 .functor NAND 1, o0000000003da0098, o0000000003da0068, o0000000003da0038, o0000000003da0008;
+L_00000000041727a0 .functor BUF 1, L_0000000004172030, C4<0>, C4<0>, C4<0>;
+v0000000003e2be20_0 .net "A", 0 0, o0000000003da0008;  alias, 0 drivers
+v0000000003e2a480_0 .net "B", 0 0, o0000000003da0038;  alias, 0 drivers
+v0000000003e2aac0_0 .net "C", 0 0, o0000000003da0068;  alias, 0 drivers
+v0000000003e2a520_0 .net "D", 0 0, o0000000003da0098;  alias, 0 drivers
+L_00000000040e6a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29940_0 .net8 "VGND", 0 0, L_00000000040e6a50;  1 drivers, strength-aware
+L_00000000040e51d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e29a80_0 .net8 "VNB", 0 0, L_00000000040e51d0;  1 drivers, strength-aware
+L_00000000040e5f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2ba60_0 .net8 "VPB", 0 0, L_00000000040e5f60;  1 drivers, strength-aware
+L_00000000040e6660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2bb00_0 .net8 "VPWR", 0 0, L_00000000040e6660;  1 drivers, strength-aware
+v0000000003e2ab60_0 .net "Y", 0 0, L_00000000041727a0;  alias, 1 drivers
+v0000000003e2b6a0_0 .net "nand0_out_Y", 0 0, L_0000000004172030;  1 drivers
+S_000000000291b750 .scope module, "sky130_fd_sc_hd__nand4_4" "sky130_fd_sc_hd__nand4_4" 4 25723;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da0488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2dc20_0 .net "A", 0 0, o0000000003da0488;  0 drivers
+o0000000003da04b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2c140_0 .net "B", 0 0, o0000000003da04b8;  0 drivers
+o0000000003da04e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2da40_0 .net "C", 0 0, o0000000003da04e8;  0 drivers
+o0000000003da0518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2dfe0_0 .net "D", 0 0, o0000000003da0518;  0 drivers
+L_00000000040e52b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c820_0 .net8 "VGND", 0 0, L_00000000040e52b0;  1 drivers, strength-aware
+L_00000000040e6ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c500_0 .net8 "VNB", 0 0, L_00000000040e6ac0;  1 drivers, strength-aware
+L_00000000040e66d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2e800_0 .net8 "VPB", 0 0, L_00000000040e66d0;  1 drivers, strength-aware
+L_00000000040e5fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2cc80_0 .net8 "VPWR", 0 0, L_00000000040e5fd0;  1 drivers, strength-aware
+v0000000003e2ca00_0 .net "Y", 0 0, L_0000000004172260;  1 drivers
+S_0000000003d20130 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25743, 4 25484 1, S_000000000291b750;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172810 .functor NAND 1, o0000000003da0518, o0000000003da04e8, o0000000003da04b8, o0000000003da0488;
+L_0000000004172260 .functor BUF 1, L_0000000004172810, C4<0>, C4<0>, C4<0>;
+v0000000003e2bc40_0 .net "A", 0 0, o0000000003da0488;  alias, 0 drivers
+v0000000003e29c60_0 .net "B", 0 0, o0000000003da04b8;  alias, 0 drivers
+v0000000003e2d900_0 .net "C", 0 0, o0000000003da04e8;  alias, 0 drivers
+v0000000003e2e580_0 .net "D", 0 0, o0000000003da0518;  alias, 0 drivers
+L_00000000040e5860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2cf00_0 .net8 "VGND", 0 0, L_00000000040e5860;  1 drivers, strength-aware
+L_00000000040e6ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2db80_0 .net8 "VNB", 0 0, L_00000000040e6ba0;  1 drivers, strength-aware
+L_00000000040e6040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2cbe0_0 .net8 "VPB", 0 0, L_00000000040e6040;  1 drivers, strength-aware
+L_00000000040e5240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d2c0_0 .net8 "VPWR", 0 0, L_00000000040e5240;  1 drivers, strength-aware
+v0000000003e2d040_0 .net "Y", 0 0, L_0000000004172260;  alias, 1 drivers
+v0000000003e2ce60_0 .net "nand0_out_Y", 0 0, L_0000000004172810;  1 drivers
+S_0000000002918450 .scope module, "sky130_fd_sc_hd__nand4b_1" "sky130_fd_sc_hd__nand4b_1" 4 6883;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da0908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2dcc0_0 .net "A_N", 0 0, o0000000003da0908;  0 drivers
+o0000000003da0938 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2d0e0_0 .net "B", 0 0, o0000000003da0938;  0 drivers
+o0000000003da0968 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2e4e0_0 .net "C", 0 0, o0000000003da0968;  0 drivers
+o0000000003da0998 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2d400_0 .net "D", 0 0, o0000000003da0998;  0 drivers
+L_00000000040e60b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2e8a0_0 .net8 "VGND", 0 0, L_00000000040e60b0;  1 drivers, strength-aware
+L_00000000040e6120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d4a0_0 .net8 "VNB", 0 0, L_00000000040e6120;  1 drivers, strength-aware
+L_00000000040e6190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2cdc0_0 .net8 "VPB", 0 0, L_00000000040e6190;  1 drivers, strength-aware
+L_00000000040e7c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c780_0 .net8 "VPWR", 0 0, L_00000000040e7c40;  1 drivers, strength-aware
+v0000000003e2c1e0_0 .net "Y", 0 0, L_0000000004171620;  1 drivers
+S_0000000003d20730 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 6903, 4 6642 1, S_0000000002918450;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_00000000041728f0 .functor NOT 1, o0000000003da0908, C4<0>, C4<0>, C4<0>;
+L_00000000041720a0 .functor NAND 1, o0000000003da0998, o0000000003da0968, o0000000003da0938, L_00000000041728f0;
+L_0000000004171620 .functor BUF 1, L_00000000041720a0, C4<0>, C4<0>, C4<0>;
+v0000000003e2e080_0 .net "A_N", 0 0, o0000000003da0908;  alias, 0 drivers
+v0000000003e2caa0_0 .net "B", 0 0, o0000000003da0938;  alias, 0 drivers
+v0000000003e2d220_0 .net "C", 0 0, o0000000003da0968;  alias, 0 drivers
+v0000000003e2cfa0_0 .net "D", 0 0, o0000000003da0998;  alias, 0 drivers
+L_00000000040e86c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c320_0 .net8 "VGND", 0 0, L_00000000040e86c0;  1 drivers, strength-aware
+L_00000000040e7b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d360_0 .net8 "VNB", 0 0, L_00000000040e7b60;  1 drivers, strength-aware
+L_00000000040e75b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2cb40_0 .net8 "VPB", 0 0, L_00000000040e75b0;  1 drivers, strength-aware
+L_00000000040e8500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c8c0_0 .net8 "VPWR", 0 0, L_00000000040e8500;  1 drivers, strength-aware
+v0000000003e2dae0_0 .net "Y", 0 0, L_0000000004171620;  alias, 1 drivers
+v0000000003e2cd20_0 .net "nand0_out_Y", 0 0, L_00000000041720a0;  1 drivers
+v0000000003e2d9a0_0 .net "not0_out", 0 0, L_00000000041728f0;  1 drivers
+S_000000000291b2d0 .scope module, "sky130_fd_sc_hd__nand4b_2" "sky130_fd_sc_hd__nand4b_2" 4 7001;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da0db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2d680_0 .net "A_N", 0 0, o0000000003da0db8;  0 drivers
+o0000000003da0de8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2c280_0 .net "B", 0 0, o0000000003da0de8;  0 drivers
+o0000000003da0e18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2df40_0 .net "C", 0 0, o0000000003da0e18;  0 drivers
+o0000000003da0e48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2e1c0_0 .net "D", 0 0, o0000000003da0e48;  0 drivers
+L_00000000040e8030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d720_0 .net8 "VGND", 0 0, L_00000000040e8030;  1 drivers, strength-aware
+L_00000000040e78c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d7c0_0 .net8 "VNB", 0 0, L_00000000040e78c0;  1 drivers, strength-aware
+L_00000000040e83b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2e620_0 .net8 "VPB", 0 0, L_00000000040e83b0;  1 drivers, strength-aware
+L_00000000040e8730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2d860_0 .net8 "VPWR", 0 0, L_00000000040e8730;  1 drivers, strength-aware
+v0000000003e2e260_0 .net "Y", 0 0, L_0000000004172960;  1 drivers
+S_0000000003d208b0 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 7021, 4 6642 1, S_000000000291b2d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172ff0 .functor NOT 1, o0000000003da0db8, C4<0>, C4<0>, C4<0>;
+L_0000000004172880 .functor NAND 1, o0000000003da0e48, o0000000003da0e18, o0000000003da0de8, L_0000000004172ff0;
+L_0000000004172960 .functor BUF 1, L_0000000004172880, C4<0>, C4<0>, C4<0>;
+v0000000003e2d180_0 .net "A_N", 0 0, o0000000003da0db8;  alias, 0 drivers
+v0000000003e2e120_0 .net "B", 0 0, o0000000003da0de8;  alias, 0 drivers
+v0000000003e2dd60_0 .net "C", 0 0, o0000000003da0e18;  alias, 0 drivers
+v0000000003e2d540_0 .net "D", 0 0, o0000000003da0e48;  alias, 0 drivers
+L_00000000040e6cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2de00_0 .net8 "VGND", 0 0, L_00000000040e6cf0;  1 drivers, strength-aware
+L_00000000040e7000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c960_0 .net8 "VNB", 0 0, L_00000000040e7000;  1 drivers, strength-aware
+L_00000000040e87a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c5a0_0 .net8 "VPB", 0 0, L_00000000040e87a0;  1 drivers, strength-aware
+L_00000000040e71c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c460_0 .net8 "VPWR", 0 0, L_00000000040e71c0;  1 drivers, strength-aware
+v0000000003e2dea0_0 .net "Y", 0 0, L_0000000004172960;  alias, 1 drivers
+v0000000003e2d5e0_0 .net "nand0_out_Y", 0 0, L_0000000004172880;  1 drivers
+v0000000003e2c640_0 .net "not0_out", 0 0, L_0000000004172ff0;  1 drivers
+S_000000000291a0d0 .scope module, "sky130_fd_sc_hd__nand4b_4" "sky130_fd_sc_hd__nand4b_4" 4 6765;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da1268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e307e0_0 .net "A_N", 0 0, o0000000003da1268;  0 drivers
+o0000000003da1298 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2fd40_0 .net "B", 0 0, o0000000003da1298;  0 drivers
+o0000000003da12c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2fde0_0 .net "C", 0 0, o0000000003da12c8;  0 drivers
+o0000000003da12f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e30d80_0 .net "D", 0 0, o0000000003da12f8;  0 drivers
+L_00000000040e73f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2fac0_0 .net8 "VGND", 0 0, L_00000000040e73f0;  1 drivers, strength-aware
+L_00000000040e8810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e30ce0_0 .net8 "VNB", 0 0, L_00000000040e8810;  1 drivers, strength-aware
+L_00000000040e82d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2eda0_0 .net8 "VPB", 0 0, L_00000000040e82d0;  1 drivers, strength-aware
+L_00000000040e7310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e30f60_0 .net8 "VPWR", 0 0, L_00000000040e7310;  1 drivers, strength-aware
+v0000000003e2ee40_0 .net "Y", 0 0, L_00000000041718c0;  1 drivers
+S_0000000003d1fcb0 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 6785, 4 6642 1, S_000000000291a0d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172340 .functor NOT 1, o0000000003da1268, C4<0>, C4<0>, C4<0>;
+L_0000000004172f80 .functor NAND 1, o0000000003da12f8, o0000000003da12c8, o0000000003da1298, L_0000000004172340;
+L_00000000041718c0 .functor BUF 1, L_0000000004172f80, C4<0>, C4<0>, C4<0>;
+v0000000003e2e300_0 .net "A_N", 0 0, o0000000003da1268;  alias, 0 drivers
+v0000000003e2e3a0_0 .net "B", 0 0, o0000000003da1298;  alias, 0 drivers
+v0000000003e2e440_0 .net "C", 0 0, o0000000003da12c8;  alias, 0 drivers
+v0000000003e2e6c0_0 .net "D", 0 0, o0000000003da12f8;  alias, 0 drivers
+L_00000000040e8260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2e760_0 .net8 "VGND", 0 0, L_00000000040e8260;  1 drivers, strength-aware
+L_00000000040e7cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c3c0_0 .net8 "VNB", 0 0, L_00000000040e7cb0;  1 drivers, strength-aware
+L_00000000040e8880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2c6e0_0 .net8 "VPB", 0 0, L_00000000040e8880;  1 drivers, strength-aware
+L_00000000040e6d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2ef80_0 .net8 "VPWR", 0 0, L_00000000040e6d60;  1 drivers, strength-aware
+v0000000003e31000_0 .net "Y", 0 0, L_00000000041718c0;  alias, 1 drivers
+v0000000003e30e20_0 .net "nand0_out_Y", 0 0, L_0000000004172f80;  1 drivers
+v0000000003e30880_0 .net "not0_out", 0 0, L_0000000004172340;  1 drivers
+S_000000000291ae50 .scope module, "sky130_fd_sc_hd__nand4bb_1" "sky130_fd_sc_hd__nand4bb_1" 4 28507;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da1718 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2ebc0_0 .net "A_N", 0 0, o0000000003da1718;  0 drivers
+o0000000003da1748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2f020_0 .net "B_N", 0 0, o0000000003da1748;  0 drivers
+o0000000003da1778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2eee0_0 .net "C", 0 0, o0000000003da1778;  0 drivers
+o0000000003da17a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2f840_0 .net "D", 0 0, o0000000003da17a8;  0 drivers
+L_00000000040e6dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e30240_0 .net8 "VGND", 0 0, L_00000000040e6dd0;  1 drivers, strength-aware
+L_00000000040e7070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e309c0_0 .net8 "VNB", 0 0, L_00000000040e7070;  1 drivers, strength-aware
+L_00000000040e6e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f0c0_0 .net8 "VPB", 0 0, L_00000000040e6e40;  1 drivers, strength-aware
+L_00000000040e7230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e306a0_0 .net8 "VPWR", 0 0, L_00000000040e7230;  1 drivers, strength-aware
+v0000000003e310a0_0 .net "Y", 0 0, L_00000000041723b0;  1 drivers
+S_0000000003d20bb0 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 28527, 4 28828 1, S_000000000291ae50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_00000000041722d0 .functor NAND 1, o0000000003da17a8, o0000000003da1778, C4<1>, C4<1>;
+L_0000000004172500 .functor OR 1, o0000000003da1748, o0000000003da1718, L_00000000041722d0, C4<0>;
+L_00000000041723b0 .functor BUF 1, L_0000000004172500, C4<0>, C4<0>, C4<0>;
+v0000000003e30380_0 .net "A_N", 0 0, o0000000003da1718;  alias, 0 drivers
+v0000000003e301a0_0 .net "B_N", 0 0, o0000000003da1748;  alias, 0 drivers
+v0000000003e30920_0 .net "C", 0 0, o0000000003da1778;  alias, 0 drivers
+v0000000003e30600_0 .net "D", 0 0, o0000000003da17a8;  alias, 0 drivers
+L_00000000040e7460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f7a0_0 .net8 "VGND", 0 0, L_00000000040e7460;  1 drivers, strength-aware
+L_00000000040e6eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2ff20_0 .net8 "VNB", 0 0, L_00000000040e6eb0;  1 drivers, strength-aware
+L_00000000040e8340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e30ec0_0 .net8 "VPB", 0 0, L_00000000040e8340;  1 drivers, strength-aware
+L_00000000040e7380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f700_0 .net8 "VPWR", 0 0, L_00000000040e7380;  1 drivers, strength-aware
+v0000000003e2fa20_0 .net "Y", 0 0, L_00000000041723b0;  alias, 1 drivers
+v0000000003e2f3e0_0 .net "nand0_out", 0 0, L_00000000041722d0;  1 drivers
+v0000000003e2fb60_0 .net "or0_out_Y", 0 0, L_0000000004172500;  1 drivers
+S_0000000002918a50 .scope module, "sky130_fd_sc_hd__nand4bb_2" "sky130_fd_sc_hd__nand4bb_2" 4 28951;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da1bc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e30ba0_0 .net "A_N", 0 0, o0000000003da1bc8;  0 drivers
+o0000000003da1bf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2ffc0_0 .net "B_N", 0 0, o0000000003da1bf8;  0 drivers
+o0000000003da1c28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2e940_0 .net "C", 0 0, o0000000003da1c28;  0 drivers
+o0000000003da1c58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e2f200_0 .net "D", 0 0, o0000000003da1c58;  0 drivers
+L_00000000040e8420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2ec60_0 .net8 "VGND", 0 0, L_00000000040e8420;  1 drivers, strength-aware
+L_00000000040e7d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f5c0_0 .net8 "VNB", 0 0, L_00000000040e7d20;  1 drivers, strength-aware
+L_00000000040e6f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e304c0_0 .net8 "VPB", 0 0, L_00000000040e6f20;  1 drivers, strength-aware
+L_00000000040e8110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2e9e0_0 .net8 "VPWR", 0 0, L_00000000040e8110;  1 drivers, strength-aware
+v0000000003e2ea80_0 .net "Y", 0 0, L_00000000041725e0;  1 drivers
+S_0000000003d1f230 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 28971, 4 28828 1, S_0000000002918a50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004172570 .functor NAND 1, o0000000003da1c58, o0000000003da1c28, C4<1>, C4<1>;
+L_0000000004171d20 .functor OR 1, o0000000003da1bf8, o0000000003da1bc8, L_0000000004172570, C4<0>;
+L_00000000041725e0 .functor BUF 1, L_0000000004171d20, C4<0>, C4<0>, C4<0>;
+v0000000003e2f160_0 .net "A_N", 0 0, o0000000003da1bc8;  alias, 0 drivers
+v0000000003e2fe80_0 .net "B_N", 0 0, o0000000003da1bf8;  alias, 0 drivers
+v0000000003e30a60_0 .net "C", 0 0, o0000000003da1c28;  alias, 0 drivers
+v0000000003e30740_0 .net "D", 0 0, o0000000003da1c58;  alias, 0 drivers
+L_00000000040e70e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e30560_0 .net8 "VGND", 0 0, L_00000000040e70e0;  1 drivers, strength-aware
+L_00000000040e7150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f340_0 .net8 "VNB", 0 0, L_00000000040e7150;  1 drivers, strength-aware
+L_00000000040e7a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e30420_0 .net8 "VPB", 0 0, L_00000000040e7a80;  1 drivers, strength-aware
+L_00000000040e8490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e302e0_0 .net8 "VPWR", 0 0, L_00000000040e8490;  1 drivers, strength-aware
+v0000000003e30b00_0 .net "Y", 0 0, L_00000000041725e0;  alias, 1 drivers
+v0000000003e2f2a0_0 .net "nand0_out", 0 0, L_0000000004172570;  1 drivers
+v0000000003e2f980_0 .net "or0_out_Y", 0 0, L_0000000004171d20;  1 drivers
+S_00000000029194d0 .scope module, "sky130_fd_sc_hd__nand4bb_4" "sky130_fd_sc_hd__nand4bb_4" 4 29069;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da2078 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e329a0_0 .net "A_N", 0 0, o0000000003da2078;  0 drivers
+o0000000003da20a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e32fe0_0 .net "B_N", 0 0, o0000000003da20a8;  0 drivers
+o0000000003da20d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e32e00_0 .net "C", 0 0, o0000000003da20d8;  0 drivers
+o0000000003da2108 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e315a0_0 .net "D", 0 0, o0000000003da2108;  0 drivers
+L_00000000040e80a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32720_0 .net8 "VGND", 0 0, L_00000000040e80a0;  1 drivers, strength-aware
+L_00000000040e6f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e316e0_0 .net8 "VNB", 0 0, L_00000000040e6f90;  1 drivers, strength-aware
+L_00000000040e8180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e32ae0_0 .net8 "VPB", 0 0, L_00000000040e8180;  1 drivers, strength-aware
+L_00000000040e7a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e32b80_0 .net8 "VPWR", 0 0, L_00000000040e7a10;  1 drivers, strength-aware
+v0000000003e31be0_0 .net "Y", 0 0, L_0000000004171930;  1 drivers
+S_0000000003d1f0b0 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 29089, 4 28828 1, S_00000000029194d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A_N"
+    .port_info 2 /INPUT 1 "B_N"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004173060 .functor NAND 1, o0000000003da2108, o0000000003da20d8, C4<1>, C4<1>;
+L_00000000041729d0 .functor OR 1, o0000000003da20a8, o0000000003da2078, L_0000000004173060, C4<0>;
+L_0000000004171930 .functor BUF 1, L_00000000041729d0, C4<0>, C4<0>, C4<0>;
+v0000000003e30060_0 .net "A_N", 0 0, o0000000003da2078;  alias, 0 drivers
+v0000000003e30c40_0 .net "B_N", 0 0, o0000000003da20a8;  alias, 0 drivers
+v0000000003e2eb20_0 .net "C", 0 0, o0000000003da20d8;  alias, 0 drivers
+v0000000003e2ed00_0 .net "D", 0 0, o0000000003da2108;  alias, 0 drivers
+L_00000000040e74d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f480_0 .net8 "VGND", 0 0, L_00000000040e74d0;  1 drivers, strength-aware
+L_00000000040e7690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f520_0 .net8 "VNB", 0 0, L_00000000040e7690;  1 drivers, strength-aware
+L_00000000040e8570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f660_0 .net8 "VPB", 0 0, L_00000000040e8570;  1 drivers, strength-aware
+L_00000000040e72a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e2f8e0_0 .net8 "VPWR", 0 0, L_00000000040e72a0;  1 drivers, strength-aware
+v0000000003e2fc00_0 .net "Y", 0 0, L_0000000004171930;  alias, 1 drivers
+v0000000003e2fca0_0 .net "nand0_out", 0 0, L_0000000004173060;  1 drivers
+v0000000003e30100_0 .net "or0_out_Y", 0 0, L_00000000041729d0;  1 drivers
+S_000000000291b8d0 .scope module, "sky130_fd_sc_hd__nor2_1" "sky130_fd_sc_hd__nor2_1" 4 30391;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003da2528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e32220_0 .net "A", 0 0, o0000000003da2528;  0 drivers
+o0000000003da2558 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e31fa0_0 .net "B", 0 0, o0000000003da2558;  0 drivers
+L_00000000040e7540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32f40_0 .net8 "VGND", 0 0, L_00000000040e7540;  1 drivers, strength-aware
+L_00000000040e85e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32540_0 .net8 "VNB", 0 0, L_00000000040e85e0;  1 drivers, strength-aware
+L_00000000040e7f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e331c0_0 .net8 "VPB", 0 0, L_00000000040e7f50;  1 drivers, strength-aware
+L_00000000040e7770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e32cc0_0 .net8 "VPWR", 0 0, L_00000000040e7770;  1 drivers, strength-aware
+v0000000003e31960_0 .net "Y", 0 0, L_0000000004171690;  1 drivers
+S_0000000003d1f530 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30407, 4 30688 1, S_000000000291b8d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000041726c0 .functor NOR 1, o0000000003da2528, o0000000003da2558, C4<0>, C4<0>;
+L_0000000004171690 .functor BUF 1, L_00000000041726c0, C4<0>, C4<0>, C4<0>;
+v0000000003e33080_0 .net "A", 0 0, o0000000003da2528;  alias, 0 drivers
+v0000000003e324a0_0 .net "B", 0 0, o0000000003da2558;  alias, 0 drivers
+L_00000000040e8650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e320e0_0 .net8 "VGND", 0 0, L_00000000040e8650;  1 drivers, strength-aware
+L_00000000040e77e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e33120_0 .net8 "VNB", 0 0, L_00000000040e77e0;  1 drivers, strength-aware
+L_00000000040e7e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e318c0_0 .net8 "VPB", 0 0, L_00000000040e7e00;  1 drivers, strength-aware
+L_00000000040e7620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e32ea0_0 .net8 "VPWR", 0 0, L_00000000040e7620;  1 drivers, strength-aware
+v0000000003e33580_0 .net "Y", 0 0, L_0000000004171690;  alias, 1 drivers
+v0000000003e32c20_0 .net "nor0_out_Y", 0 0, L_00000000041726c0;  1 drivers
+S_0000000002917e50 .scope module, "sky130_fd_sc_hd__nor2_4" "sky130_fd_sc_hd__nor2_4" 4 30799;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003da2888 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e336c0_0 .net "A", 0 0, o0000000003da2888;  0 drivers
+o0000000003da28b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e32d60_0 .net "B", 0 0, o0000000003da28b8;  0 drivers
+L_00000000040e7700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32400_0 .net8 "VGND", 0 0, L_00000000040e7700;  1 drivers, strength-aware
+L_00000000040e7850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e31f00_0 .net8 "VNB", 0 0, L_00000000040e7850;  1 drivers, strength-aware
+L_00000000040e7930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e31140_0 .net8 "VPB", 0 0, L_00000000040e7930;  1 drivers, strength-aware
+L_00000000040e79a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e31640_0 .net8 "VPWR", 0 0, L_00000000040e79a0;  1 drivers, strength-aware
+v0000000003e33260_0 .net "Y", 0 0, L_0000000004171cb0;  1 drivers
+S_0000000003d1f6b0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30815, 4 30688 1, S_0000000002917e50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004172a40 .functor NOR 1, o0000000003da2888, o0000000003da28b8, C4<0>, C4<0>;
+L_0000000004171cb0 .functor BUF 1, L_0000000004172a40, C4<0>, C4<0>, C4<0>;
+v0000000003e32a40_0 .net "A", 0 0, o0000000003da2888;  alias, 0 drivers
+v0000000003e31e60_0 .net "B", 0 0, o0000000003da28b8;  alias, 0 drivers
+L_00000000040e7ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e334e0_0 .net8 "VGND", 0 0, L_00000000040e7ee0;  1 drivers, strength-aware
+L_00000000040e7af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e322c0_0 .net8 "VNB", 0 0, L_00000000040e7af0;  1 drivers, strength-aware
+L_00000000040e7bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33800_0 .net8 "VPB", 0 0, L_00000000040e7bd0;  1 drivers, strength-aware
+L_00000000040e7d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e32360_0 .net8 "VPWR", 0 0, L_00000000040e7d90;  1 drivers, strength-aware
+v0000000003e31d20_0 .net "Y", 0 0, L_0000000004171cb0;  alias, 1 drivers
+v0000000003e31780_0 .net "nor0_out_Y", 0 0, L_0000000004172a40;  1 drivers
+S_0000000002918150 .scope module, "sky130_fd_sc_hd__nor2_8" "sky130_fd_sc_hd__nor2_8" 4 30905;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003da2be8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e33760_0 .net "A", 0 0, o0000000003da2be8;  0 drivers
+o0000000003da2c18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e32180_0 .net "B", 0 0, o0000000003da2c18;  0 drivers
+L_00000000040e7e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32680_0 .net8 "VGND", 0 0, L_00000000040e7e70;  1 drivers, strength-aware
+L_00000000040e7fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e311e0_0 .net8 "VNB", 0 0, L_00000000040e7fc0;  1 drivers, strength-aware
+L_00000000040e81f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e338a0_0 .net8 "VPB", 0 0, L_00000000040e81f0;  1 drivers, strength-aware
+L_00000000040e9d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e327c0_0 .net8 "VPWR", 0 0, L_00000000040e9d80;  1 drivers, strength-aware
+v0000000003e32860_0 .net "Y", 0 0, L_0000000004172420;  1 drivers
+S_0000000003d1f830 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30921, 4 30688 1, S_0000000002918150;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004171770 .functor NOR 1, o0000000003da2be8, o0000000003da2c18, C4<0>, C4<0>;
+L_0000000004172420 .functor BUF 1, L_0000000004171770, C4<0>, C4<0>, C4<0>;
+v0000000003e325e0_0 .net "A", 0 0, o0000000003da2be8;  alias, 0 drivers
+v0000000003e33300_0 .net "B", 0 0, o0000000003da2c18;  alias, 0 drivers
+L_00000000040e8ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e31dc0_0 .net8 "VGND", 0 0, L_00000000040e8ab0;  1 drivers, strength-aware
+L_00000000040ea090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e32040_0 .net8 "VNB", 0 0, L_00000000040ea090;  1 drivers, strength-aware
+L_00000000040e9d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e333a0_0 .net8 "VPB", 0 0, L_00000000040e9d10;  1 drivers, strength-aware
+L_00000000040e9220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33620_0 .net8 "VPWR", 0 0, L_00000000040e9220;  1 drivers, strength-aware
+v0000000003e31b40_0 .net "Y", 0 0, L_0000000004172420;  alias, 1 drivers
+v0000000003e33440_0 .net "nor0_out_Y", 0 0, L_0000000004171770;  1 drivers
+S_0000000002917fd0 .scope module, "sky130_fd_sc_hd__nor2b_1" "sky130_fd_sc_hd__nor2b_1" 4 5605;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+o0000000003da2f48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e31c80_0 .net "A", 0 0, o0000000003da2f48;  0 drivers
+o0000000003da2f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e33da0_0 .net "B_N", 0 0, o0000000003da2f78;  0 drivers
+L_00000000040e8c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e33c60_0 .net8 "VGND", 0 0, L_00000000040e8c00;  1 drivers, strength-aware
+L_00000000040e9a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e348e0_0 .net8 "VNB", 0 0, L_00000000040e9a70;  1 drivers, strength-aware
+L_00000000040e9370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e345c0_0 .net8 "VPB", 0 0, L_00000000040e9370;  1 drivers, strength-aware
+L_00000000040e8960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33e40_0 .net8 "VPWR", 0 0, L_00000000040e8960;  1 drivers, strength-aware
+v0000000003e34d40_0 .net "Y", 0 0, L_00000000041730d0;  1 drivers
+S_0000000003d016b0 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5621, 4 5274 1, S_0000000002917fd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004172b20 .functor NOT 1, o0000000003da2f48, C4<0>, C4<0>, C4<0>;
+L_0000000004172b90 .functor AND 1, L_0000000004172b20, o0000000003da2f78, C4<1>, C4<1>;
+L_00000000041730d0 .functor BUF 1, L_0000000004172b90, C4<0>, C4<0>, C4<0>;
+v0000000003e31280_0 .net "A", 0 0, o0000000003da2f48;  alias, 0 drivers
+v0000000003e31320_0 .net "B_N", 0 0, o0000000003da2f78;  alias, 0 drivers
+L_00000000040e8dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e313c0_0 .net8 "VGND", 0 0, L_00000000040e8dc0;  1 drivers, strength-aware
+L_00000000040e9ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e31460_0 .net8 "VNB", 0 0, L_00000000040e9ed0;  1 drivers, strength-aware
+L_00000000040e9fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e31500_0 .net8 "VPB", 0 0, L_00000000040e9fb0;  1 drivers, strength-aware
+L_00000000040e9840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e31820_0 .net8 "VPWR", 0 0, L_00000000040e9840;  1 drivers, strength-aware
+v0000000003e31a00_0 .net "Y", 0 0, L_00000000041730d0;  alias, 1 drivers
+v0000000003e32900_0 .net "and0_out_Y", 0 0, L_0000000004172b90;  1 drivers
+v0000000003e31aa0_0 .net "not0_out", 0 0, L_0000000004172b20;  1 drivers
+S_00000000029185d0 .scope module, "sky130_fd_sc_hd__nor2b_2" "sky130_fd_sc_hd__nor2b_2" 4 5389;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+o0000000003da32d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e33bc0_0 .net "A", 0 0, o0000000003da32d8;  0 drivers
+o0000000003da3308 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e34020_0 .net "B_N", 0 0, o0000000003da3308;  0 drivers
+L_00000000040ea2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e340c0_0 .net8 "VGND", 0 0, L_00000000040ea2c0;  1 drivers, strength-aware
+L_00000000040e9760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e34840_0 .net8 "VNB", 0 0, L_00000000040e9760;  1 drivers, strength-aware
+L_00000000040e91b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35240_0 .net8 "VPB", 0 0, L_00000000040e91b0;  1 drivers, strength-aware
+L_00000000040ea100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35880_0 .net8 "VPWR", 0 0, L_00000000040ea100;  1 drivers, strength-aware
+v0000000003e34160_0 .net "Y", 0 0, L_0000000004172c00;  1 drivers
+S_0000000003d019b0 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5405, 4 5274 1, S_00000000029185d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004171b60 .functor NOT 1, o0000000003da32d8, C4<0>, C4<0>, C4<0>;
+L_0000000004171a80 .functor AND 1, L_0000000004171b60, o0000000003da3308, C4<1>, C4<1>;
+L_0000000004172c00 .functor BUF 1, L_0000000004171a80, C4<0>, C4<0>, C4<0>;
+v0000000003e357e0_0 .net "A", 0 0, o0000000003da32d8;  alias, 0 drivers
+v0000000003e35600_0 .net "B_N", 0 0, o0000000003da3308;  alias, 0 drivers
+L_00000000040e9c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e33ee0_0 .net8 "VGND", 0 0, L_00000000040e9c30;  1 drivers, strength-aware
+L_00000000040e94c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e359c0_0 .net8 "VNB", 0 0, L_00000000040e94c0;  1 drivers, strength-aware
+L_00000000040ea020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33f80_0 .net8 "VPB", 0 0, L_00000000040ea020;  1 drivers, strength-aware
+L_00000000040e90d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e34a20_0 .net8 "VPWR", 0 0, L_00000000040e90d0;  1 drivers, strength-aware
+v0000000003e35560_0 .net "Y", 0 0, L_0000000004172c00;  alias, 1 drivers
+v0000000003e342a0_0 .net "and0_out_Y", 0 0, L_0000000004171a80;  1 drivers
+v0000000003e34660_0 .net "not0_out", 0 0, L_0000000004171b60;  1 drivers
+S_0000000002919650 .scope module, "sky130_fd_sc_hd__nor2b_4" "sky130_fd_sc_hd__nor2b_4" 4 5497;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+o0000000003da3668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e35ec0_0 .net "A", 0 0, o0000000003da3668;  0 drivers
+o0000000003da3698 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e34480_0 .net "B_N", 0 0, o0000000003da3698;  0 drivers
+L_00000000040ea480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e360a0_0 .net8 "VGND", 0 0, L_00000000040ea480;  1 drivers, strength-aware
+L_00000000040e88f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e35920_0 .net8 "VNB", 0 0, L_00000000040e88f0;  1 drivers, strength-aware
+L_00000000040e93e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33940_0 .net8 "VPB", 0 0, L_00000000040e93e0;  1 drivers, strength-aware
+L_00000000040e9290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e352e0_0 .net8 "VPWR", 0 0, L_00000000040e9290;  1 drivers, strength-aware
+v0000000003e34700_0 .net "Y", 0 0, L_0000000004171bd0;  1 drivers
+S_0000000003d05130 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5513, 4 5274 1, S_0000000002919650;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004171700 .functor NOT 1, o0000000003da3668, C4<0>, C4<0>, C4<0>;
+L_0000000004172c70 .functor AND 1, L_0000000004171700, o0000000003da3698, C4<1>, C4<1>;
+L_0000000004171bd0 .functor BUF 1, L_0000000004172c70, C4<0>, C4<0>, C4<0>;
+v0000000003e33d00_0 .net "A", 0 0, o0000000003da3668;  alias, 0 drivers
+v0000000003e34200_0 .net "B_N", 0 0, o0000000003da3698;  alias, 0 drivers
+L_00000000040e9f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e33b20_0 .net8 "VGND", 0 0, L_00000000040e9f40;  1 drivers, strength-aware
+L_00000000040e9140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e34ac0_0 .net8 "VNB", 0 0, L_00000000040e9140;  1 drivers, strength-aware
+L_00000000040e9b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e34340_0 .net8 "VPB", 0 0, L_00000000040e9b50;  1 drivers, strength-aware
+L_00000000040e9bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35a60_0 .net8 "VPWR", 0 0, L_00000000040e9bc0;  1 drivers, strength-aware
+v0000000003e34e80_0 .net "Y", 0 0, L_0000000004171bd0;  alias, 1 drivers
+v0000000003e343e0_0 .net "and0_out_Y", 0 0, L_0000000004172c70;  1 drivers
+v0000000003e351a0_0 .net "not0_out", 0 0, L_0000000004171700;  1 drivers
+S_0000000002918bd0 .scope module, "sky130_fd_sc_hd__nor3_1" "sky130_fd_sc_hd__nor3_1" 4 16734;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003da39f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e35740_0 .net "A", 0 0, o0000000003da39f8;  0 drivers
+o0000000003da3a28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e34520_0 .net "B", 0 0, o0000000003da3a28;  0 drivers
+o0000000003da3a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e34f20_0 .net "C", 0 0, o0000000003da3a58;  0 drivers
+L_00000000040e9300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e34c00_0 .net8 "VGND", 0 0, L_00000000040e9300;  1 drivers, strength-aware
+L_00000000040e9450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e347a0_0 .net8 "VNB", 0 0, L_00000000040e9450;  1 drivers, strength-aware
+L_00000000040e9e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e34de0_0 .net8 "VPB", 0 0, L_00000000040e9e60;  1 drivers, strength-aware
+L_00000000040ea170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e33a80_0 .net8 "VPWR", 0 0, L_00000000040ea170;  1 drivers, strength-aware
+v0000000003e35ce0_0 .net "Y", 0 0, L_0000000004171850;  1 drivers
+S_0000000003d05eb0 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16752, 4 16616 1, S_0000000002918bd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004172dc0 .functor NOR 1, o0000000003da3a58, o0000000003da39f8, o0000000003da3a28, C4<0>;
+L_0000000004171850 .functor BUF 1, L_0000000004172dc0, C4<0>, C4<0>, C4<0>;
+v0000000003e34ca0_0 .net "A", 0 0, o0000000003da39f8;  alias, 0 drivers
+v0000000003e356a0_0 .net "B", 0 0, o0000000003da3a28;  alias, 0 drivers
+v0000000003e35380_0 .net "C", 0 0, o0000000003da3a58;  alias, 0 drivers
+L_00000000040ea1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e339e0_0 .net8 "VGND", 0 0, L_00000000040ea1e0;  1 drivers, strength-aware
+L_00000000040e9a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e35b00_0 .net8 "VNB", 0 0, L_00000000040e9a00;  1 drivers, strength-aware
+L_00000000040ea250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35420_0 .net8 "VPB", 0 0, L_00000000040ea250;  1 drivers, strength-aware
+L_00000000040ea330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e354c0_0 .net8 "VPWR", 0 0, L_00000000040ea330;  1 drivers, strength-aware
+v0000000003e34980_0 .net "Y", 0 0, L_0000000004171850;  alias, 1 drivers
+v0000000003e34b60_0 .net "nor0_out_Y", 0 0, L_0000000004172dc0;  1 drivers
+S_000000000291a9d0 .scope module, "sky130_fd_sc_hd__nor3_4" "sky130_fd_sc_hd__nor3_4" 4 16186;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003da3de8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e36fa0_0 .net "A", 0 0, o0000000003da3de8;  0 drivers
+o0000000003da3e18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e365a0_0 .net "B", 0 0, o0000000003da3e18;  0 drivers
+o0000000003da3e48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e36140_0 .net "C", 0 0, o0000000003da3e48;  0 drivers
+L_00000000040ea3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36500_0 .net8 "VGND", 0 0, L_00000000040ea3a0;  1 drivers, strength-aware
+L_00000000040ea410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36960_0 .net8 "VNB", 0 0, L_00000000040ea410;  1 drivers, strength-aware
+L_00000000040e8b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38080_0 .net8 "VPB", 0 0, L_00000000040e8b20;  1 drivers, strength-aware
+L_00000000040e9530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e370e0_0 .net8 "VPWR", 0 0, L_00000000040e9530;  1 drivers, strength-aware
+v0000000003e368c0_0 .net "Y", 0 0, L_0000000004172ea0;  1 drivers
+S_0000000003d03ab0 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16204, 4 16616 1, S_000000000291a9d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004172e30 .functor NOR 1, o0000000003da3e48, o0000000003da3de8, o0000000003da3e18, C4<0>;
+L_0000000004172ea0 .functor BUF 1, L_0000000004172e30, C4<0>, C4<0>, C4<0>;
+v0000000003e35ba0_0 .net "A", 0 0, o0000000003da3de8;  alias, 0 drivers
+v0000000003e34fc0_0 .net "B", 0 0, o0000000003da3e18;  alias, 0 drivers
+v0000000003e35c40_0 .net "C", 0 0, o0000000003da3e48;  alias, 0 drivers
+L_00000000040e89d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e35d80_0 .net8 "VGND", 0 0, L_00000000040e89d0;  1 drivers, strength-aware
+L_00000000040e95a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e35060_0 .net8 "VNB", 0 0, L_00000000040e95a0;  1 drivers, strength-aware
+L_00000000040e9610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35100_0 .net8 "VPB", 0 0, L_00000000040e9610;  1 drivers, strength-aware
+L_00000000040e9ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e35e20_0 .net8 "VPWR", 0 0, L_00000000040e9ae0;  1 drivers, strength-aware
+v0000000003e35f60_0 .net "Y", 0 0, L_0000000004172ea0;  alias, 1 drivers
+v0000000003e36000_0 .net "nor0_out_Y", 0 0, L_0000000004172e30;  1 drivers
+S_000000000291a850 .scope module, "sky130_fd_sc_hd__nor3b_1" "sky130_fd_sc_hd__nor3b_1" 4 1442;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003da41d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e37680_0 .net "A", 0 0, o0000000003da41d8;  0 drivers
+o0000000003da4208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e386c0_0 .net "B", 0 0, o0000000003da4208;  0 drivers
+o0000000003da4238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e36a00_0 .net "C_N", 0 0, o0000000003da4238;  0 drivers
+L_00000000040e8e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36f00_0 .net8 "VGND", 0 0, L_00000000040e8e30;  1 drivers, strength-aware
+L_00000000040e8a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36dc0_0 .net8 "VNB", 0 0, L_00000000040e8a40;  1 drivers, strength-aware
+L_00000000040e8b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38800_0 .net8 "VPB", 0 0, L_00000000040e8b90;  1 drivers, strength-aware
+L_00000000040e8c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e37d60_0 .net8 "VPWR", 0 0, L_00000000040e8c70;  1 drivers, strength-aware
+v0000000003e36460_0 .net "Y", 0 0, L_0000000004172f10;  1 drivers
+S_0000000003d06630 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1460, 4 1322 1, S_000000000291a850;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_0000000004171540 .functor NOR 1, o0000000003da41d8, o0000000003da4208, C4<0>, C4<0>;
+L_00000000041719a0 .functor AND 1, o0000000003da4238, L_0000000004171540, C4<1>, C4<1>;
+L_0000000004172f10 .functor BUF 1, L_00000000041719a0, C4<0>, C4<0>, C4<0>;
+v0000000003e381c0_0 .net "A", 0 0, o0000000003da41d8;  alias, 0 drivers
+v0000000003e37f40_0 .net "B", 0 0, o0000000003da4208;  alias, 0 drivers
+v0000000003e38620_0 .net "C_N", 0 0, o0000000003da4238;  alias, 0 drivers
+L_00000000040e9ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e37040_0 .net8 "VGND", 0 0, L_00000000040e9ca0;  1 drivers, strength-aware
+L_00000000040e96f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36c80_0 .net8 "VNB", 0 0, L_00000000040e96f0;  1 drivers, strength-aware
+L_00000000040e8ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38300_0 .net8 "VPB", 0 0, L_00000000040e8ce0;  1 drivers, strength-aware
+L_00000000040e9680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e37cc0_0 .net8 "VPWR", 0 0, L_00000000040e9680;  1 drivers, strength-aware
+v0000000003e38260_0 .net "Y", 0 0, L_0000000004172f10;  alias, 1 drivers
+v0000000003e37180_0 .net "and0_out_Y", 0 0, L_00000000041719a0;  1 drivers
+v0000000003e37540_0 .net "nor0_out", 0 0, L_0000000004171540;  1 drivers
+S_00000000029197d0 .scope module, "sky130_fd_sc_hd__nor3b_2" "sky130_fd_sc_hd__nor3b_2" 4 1556;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003da45f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e38120_0 .net "A", 0 0, o0000000003da45f8;  0 drivers
+o0000000003da4628 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e37400_0 .net "B", 0 0, o0000000003da4628;  0 drivers
+o0000000003da4658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e37ea0_0 .net "C_N", 0 0, o0000000003da4658;  0 drivers
+L_00000000040e8d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e37220_0 .net8 "VGND", 0 0, L_00000000040e8d50;  1 drivers, strength-aware
+L_00000000040e8ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e36b40_0 .net8 "VNB", 0 0, L_00000000040e8ea0;  1 drivers, strength-aware
+L_00000000040e8f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e37900_0 .net8 "VPB", 0 0, L_00000000040e8f10;  1 drivers, strength-aware
+L_00000000040e8f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e383a0_0 .net8 "VPWR", 0 0, L_00000000040e8f80;  1 drivers, strength-aware
+v0000000003e36780_0 .net "Y", 0 0, L_0000000004173a00;  1 drivers
+S_0000000003d02bb0 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1574, 4 1322 1, S_00000000029197d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_00000000041743a0 .functor NOR 1, o0000000003da45f8, o0000000003da4628, C4<0>, C4<0>;
+L_0000000004173300 .functor AND 1, o0000000003da4658, L_00000000041743a0, C4<1>, C4<1>;
+L_0000000004173a00 .functor BUF 1, L_0000000004173300, C4<0>, C4<0>, C4<0>;
+v0000000003e375e0_0 .net "A", 0 0, o0000000003da45f8;  alias, 0 drivers
+v0000000003e37720_0 .net "B", 0 0, o0000000003da4628;  alias, 0 drivers
+v0000000003e38580_0 .net "C_N", 0 0, o0000000003da4658;  alias, 0 drivers
+L_00000000040e97d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e37e00_0 .net8 "VGND", 0 0, L_00000000040e97d0;  1 drivers, strength-aware
+L_00000000040e8ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e384e0_0 .net8 "VNB", 0 0, L_00000000040e8ff0;  1 drivers, strength-aware
+L_00000000040e9060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e366e0_0 .net8 "VPB", 0 0, L_00000000040e9060;  1 drivers, strength-aware
+L_00000000040e98b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e36640_0 .net8 "VPWR", 0 0, L_00000000040e98b0;  1 drivers, strength-aware
+v0000000003e37b80_0 .net "Y", 0 0, L_0000000004173a00;  alias, 1 drivers
+v0000000003e36d20_0 .net "and0_out_Y", 0 0, L_0000000004173300;  1 drivers
+v0000000003e36aa0_0 .net "nor0_out", 0 0, L_00000000041743a0;  1 drivers
+S_0000000002919950 .scope module, "sky130_fd_sc_hd__nor3b_4" "sky130_fd_sc_hd__nor3b_4" 4 1670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003da4a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e38760_0 .net "A", 0 0, o0000000003da4a18;  0 drivers
+o0000000003da4a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e36e60_0 .net "B", 0 0, o0000000003da4a48;  0 drivers
+o0000000003da4a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e37360_0 .net "C_N", 0 0, o0000000003da4a78;  0 drivers
+L_00000000040e9920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e379a0_0 .net8 "VGND", 0 0, L_00000000040e9920;  1 drivers, strength-aware
+L_00000000040e9990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e37a40_0 .net8 "VNB", 0 0, L_00000000040e9990;  1 drivers, strength-aware
+L_00000000040e9df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e37ae0_0 .net8 "VPB", 0 0, L_00000000040e9df0;  1 drivers, strength-aware
+L_00000000040eafe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e388a0_0 .net8 "VPWR", 0 0, L_00000000040eafe0;  1 drivers, strength-aware
+v0000000003e36280_0 .net "Y", 0 0, L_0000000004174480;  1 drivers
+S_0000000003d02730 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1688, 4 1322 1, S_0000000002919950;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_0000000004173370 .functor NOR 1, o0000000003da4a18, o0000000003da4a48, C4<0>, C4<0>;
+L_0000000004174410 .functor AND 1, o0000000003da4a78, L_0000000004173370, C4<1>, C4<1>;
+L_0000000004174480 .functor BUF 1, L_0000000004174410, C4<0>, C4<0>, C4<0>;
+v0000000003e361e0_0 .net "A", 0 0, o0000000003da4a18;  alias, 0 drivers
+v0000000003e37fe0_0 .net "B", 0 0, o0000000003da4a48;  alias, 0 drivers
+v0000000003e377c0_0 .net "C_N", 0 0, o0000000003da4a78;  alias, 0 drivers
+L_00000000040eae20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e37c20_0 .net8 "VGND", 0 0, L_00000000040eae20;  1 drivers, strength-aware
+L_00000000040ea6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e374a0_0 .net8 "VNB", 0 0, L_00000000040ea6b0;  1 drivers, strength-aware
+L_00000000040eba60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e372c0_0 .net8 "VPB", 0 0, L_00000000040eba60;  1 drivers, strength-aware
+L_00000000040ea4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e37860_0 .net8 "VPWR", 0 0, L_00000000040ea4f0;  1 drivers, strength-aware
+v0000000003e38440_0 .net "Y", 0 0, L_0000000004174480;  alias, 1 drivers
+v0000000003e36820_0 .net "and0_out_Y", 0 0, L_0000000004174410;  1 drivers
+v0000000003e36be0_0 .net "nor0_out", 0 0, L_0000000004173370;  1 drivers
+S_000000000291a250 .scope module, "sky130_fd_sc_hd__nor4_1" "sky130_fd_sc_hd__nor4_1" 4 75984;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da4e38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e39f20_0 .net "A", 0 0, o0000000003da4e38;  0 drivers
+o0000000003da4e68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e38ee0_0 .net "B", 0 0, o0000000003da4e68;  0 drivers
+o0000000003da4e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e39a20_0 .net "C", 0 0, o0000000003da4e98;  0 drivers
+o0000000003da4ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e393e0_0 .net "D", 0 0, o0000000003da4ec8;  0 drivers
+L_00000000040eb2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e39ac0_0 .net8 "VGND", 0 0, L_00000000040eb2f0;  1 drivers, strength-aware
+L_00000000040eaaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e39700_0 .net8 "VNB", 0 0, L_00000000040eaaa0;  1 drivers, strength-aware
+L_00000000040eb440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e39660_0 .net8 "VPB", 0 0, L_00000000040eb440;  1 drivers, strength-aware
+L_00000000040ea9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a6a0_0 .net8 "VPWR", 0 0, L_00000000040ea9c0;  1 drivers, strength-aware
+v0000000003e3a9c0_0 .net "Y", 0 0, L_0000000004173ae0;  1 drivers
+S_0000000003d01230 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 76004, 4 76309 1, S_000000000291a250;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_00000000041731b0 .functor NOR 1, o0000000003da4e38, o0000000003da4e68, o0000000003da4e98, o0000000003da4ec8;
+L_0000000004173ae0 .functor BUF 1, L_00000000041731b0, C4<0>, C4<0>, C4<0>;
+v0000000003e36320_0 .net "A", 0 0, o0000000003da4e38;  alias, 0 drivers
+v0000000003e363c0_0 .net "B", 0 0, o0000000003da4e68;  alias, 0 drivers
+v0000000003e3ae20_0 .net "C", 0 0, o0000000003da4e98;  alias, 0 drivers
+v0000000003e38940_0 .net "D", 0 0, o0000000003da4ec8;  alias, 0 drivers
+L_00000000040eb0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a600_0 .net8 "VGND", 0 0, L_00000000040eb0c0;  1 drivers, strength-aware
+L_00000000040ea790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e397a0_0 .net8 "VNB", 0 0, L_00000000040ea790;  1 drivers, strength-aware
+L_00000000040eb360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a920_0 .net8 "VPB", 0 0, L_00000000040eb360;  1 drivers, strength-aware
+L_00000000040eae90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38d00_0 .net8 "VPWR", 0 0, L_00000000040eae90;  1 drivers, strength-aware
+v0000000003e3a1a0_0 .net "Y", 0 0, L_0000000004173ae0;  alias, 1 drivers
+v0000000003e3a7e0_0 .net "nor0_out_Y", 0 0, L_00000000041731b0;  1 drivers
+S_0000000002919ad0 .scope module, "sky130_fd_sc_hd__nor4_2" "sky130_fd_sc_hd__nor4_2" 4 76432;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da52b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3a240_0 .net "A", 0 0, o0000000003da52b8;  0 drivers
+o0000000003da52e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3a2e0_0 .net "B", 0 0, o0000000003da52e8;  0 drivers
+o0000000003da5318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3aa60_0 .net "C", 0 0, o0000000003da5318;  0 drivers
+o0000000003da5348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3af60_0 .net "D", 0 0, o0000000003da5348;  0 drivers
+L_00000000040eb980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e398e0_0 .net8 "VGND", 0 0, L_00000000040eb980;  1 drivers, strength-aware
+L_00000000040eb4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ace0_0 .net8 "VNB", 0 0, L_00000000040eb4b0;  1 drivers, strength-aware
+L_00000000040ead40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ab00_0 .net8 "VPB", 0 0, L_00000000040ead40;  1 drivers, strength-aware
+L_00000000040ebfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e389e0_0 .net8 "VPWR", 0 0, L_00000000040ebfa0;  1 drivers, strength-aware
+v0000000003e3aba0_0 .net "Y", 0 0, L_0000000004174170;  1 drivers
+S_0000000003d03630 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 76452, 4 76309 1, S_0000000002919ad0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004174800 .functor NOR 1, o0000000003da52b8, o0000000003da52e8, o0000000003da5318, o0000000003da5348;
+L_0000000004174170 .functor BUF 1, L_0000000004174800, C4<0>, C4<0>, C4<0>;
+v0000000003e390c0_0 .net "A", 0 0, o0000000003da52b8;  alias, 0 drivers
+v0000000003e3a740_0 .net "B", 0 0, o0000000003da52e8;  alias, 0 drivers
+v0000000003e3b000_0 .net "C", 0 0, o0000000003da5318;  alias, 0 drivers
+v0000000003e39020_0 .net "D", 0 0, o0000000003da5348;  alias, 0 drivers
+L_00000000040ec080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a880_0 .net8 "VGND", 0 0, L_00000000040ec080;  1 drivers, strength-aware
+L_00000000040eb130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e39160_0 .net8 "VNB", 0 0, L_00000000040eb130;  1 drivers, strength-aware
+L_00000000040eb600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e39840_0 .net8 "VPB", 0 0, L_00000000040eb600;  1 drivers, strength-aware
+L_00000000040ea870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38b20_0 .net8 "VPWR", 0 0, L_00000000040ea870;  1 drivers, strength-aware
+v0000000003e395c0_0 .net "Y", 0 0, L_0000000004174170;  alias, 1 drivers
+v0000000003e392a0_0 .net "nor0_out_Y", 0 0, L_0000000004174800;  1 drivers
+S_0000000002919c50 .scope module, "sky130_fd_sc_hd__nor4_4" "sky130_fd_sc_hd__nor4_4" 4 75864;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003da5738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e39520_0 .net "A", 0 0, o0000000003da5738;  0 drivers
+o0000000003da5768 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e39fc0_0 .net "B", 0 0, o0000000003da5768;  0 drivers
+o0000000003da5798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e39c00_0 .net "C", 0 0, o0000000003da5798;  0 drivers
+o0000000003da57c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e38c60_0 .net "D", 0 0, o0000000003da57c8;  0 drivers
+L_00000000040ea950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e39d40_0 .net8 "VGND", 0 0, L_00000000040ea950;  1 drivers, strength-aware
+L_00000000040eb830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e39200_0 .net8 "VNB", 0 0, L_00000000040eb830;  1 drivers, strength-aware
+L_00000000040eb8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a560_0 .net8 "VPB", 0 0, L_00000000040eb8a0;  1 drivers, strength-aware
+L_00000000040ea5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e39de0_0 .net8 "VPWR", 0 0, L_00000000040ea5d0;  1 drivers, strength-aware
+v0000000003e3aec0_0 .net "Y", 0 0, L_0000000004173140;  1 drivers
+S_0000000003d06030 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 75884, 4 76309 1, S_0000000002919c50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004173ca0 .functor NOR 1, o0000000003da5738, o0000000003da5768, o0000000003da5798, o0000000003da57c8;
+L_0000000004173140 .functor BUF 1, L_0000000004173ca0, C4<0>, C4<0>, C4<0>;
+v0000000003e39ca0_0 .net "A", 0 0, o0000000003da5738;  alias, 0 drivers
+v0000000003e3ac40_0 .net "B", 0 0, o0000000003da5768;  alias, 0 drivers
+v0000000003e3a380_0 .net "C", 0 0, o0000000003da5798;  alias, 0 drivers
+v0000000003e38a80_0 .net "D", 0 0, o0000000003da57c8;  alias, 0 drivers
+L_00000000040eb910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ad80_0 .net8 "VGND", 0 0, L_00000000040eb910;  1 drivers, strength-aware
+L_00000000040eb670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a420_0 .net8 "VNB", 0 0, L_00000000040eb670;  1 drivers, strength-aware
+L_00000000040ebe50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3a4c0_0 .net8 "VPB", 0 0, L_00000000040ebe50;  1 drivers, strength-aware
+L_00000000040ebde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e39980_0 .net8 "VPWR", 0 0, L_00000000040ebde0;  1 drivers, strength-aware
+v0000000003e39b60_0 .net "Y", 0 0, L_0000000004173140;  alias, 1 drivers
+v0000000003e39e80_0 .net "nor0_out_Y", 0 0, L_0000000004173ca0;  1 drivers
+S_0000000002919dd0 .scope module, "sky130_fd_sc_hd__nor4b_1" "sky130_fd_sc_hd__nor4b_1" 4 92793;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da5bb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3d620_0 .net "A", 0 0, o0000000003da5bb8;  0 drivers
+o0000000003da5be8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3ccc0_0 .net "B", 0 0, o0000000003da5be8;  0 drivers
+o0000000003da5c18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3ba00_0 .net "C", 0 0, o0000000003da5c18;  0 drivers
+o0000000003da5c48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3cd60_0 .net "D_N", 0 0, o0000000003da5c48;  0 drivers
+L_00000000040eb6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ce00_0 .net8 "VGND", 0 0, L_00000000040eb6e0;  1 drivers, strength-aware
+L_00000000040eb9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3c720_0 .net8 "VNB", 0 0, L_00000000040eb9f0;  1 drivers, strength-aware
+L_00000000040eb3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3c540_0 .net8 "VPB", 0 0, L_00000000040eb3d0;  1 drivers, strength-aware
+L_00000000040eb520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d760_0 .net8 "VPWR", 0 0, L_00000000040eb520;  1 drivers, strength-aware
+v0000000003e3cae0_0 .net "Y", 0 0, L_0000000004173220;  1 drivers
+S_0000000003d03330 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 92813, 4 93114 1, S_0000000002919dd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004174cd0 .functor NOT 1, o0000000003da5c48, C4<0>, C4<0>, C4<0>;
+L_0000000004173d80 .functor NOR 1, o0000000003da5bb8, o0000000003da5be8, o0000000003da5c18, L_0000000004174cd0;
+L_0000000004173220 .functor BUF 1, L_0000000004173d80, C4<0>, C4<0>, C4<0>;
+v0000000003e3b0a0_0 .net "A", 0 0, o0000000003da5bb8;  alias, 0 drivers
+v0000000003e39340_0 .net "B", 0 0, o0000000003da5be8;  alias, 0 drivers
+v0000000003e3a060_0 .net "C", 0 0, o0000000003da5c18;  alias, 0 drivers
+v0000000003e3a100_0 .net "D_N", 0 0, o0000000003da5c48;  alias, 0 drivers
+L_00000000040eb280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e38bc0_0 .net8 "VGND", 0 0, L_00000000040eb280;  1 drivers, strength-aware
+L_00000000040ea720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e38da0_0 .net8 "VNB", 0 0, L_00000000040ea720;  1 drivers, strength-aware
+L_00000000040eb590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38e40_0 .net8 "VPB", 0 0, L_00000000040eb590;  1 drivers, strength-aware
+L_00000000040eb750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e38f80_0 .net8 "VPWR", 0 0, L_00000000040eb750;  1 drivers, strength-aware
+v0000000003e39480_0 .net "Y", 0 0, L_0000000004173220;  alias, 1 drivers
+v0000000003e3c4a0_0 .net "nor0_out_Y", 0 0, L_0000000004173d80;  1 drivers
+v0000000003e3bf00_0 .net "not0_out", 0 0, L_0000000004174cd0;  1 drivers
+S_000000000291a3d0 .scope module, "sky130_fd_sc_hd__nor4b_2" "sky130_fd_sc_hd__nor4b_2" 4 93355;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da6068 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3b140_0 .net "A", 0 0, o0000000003da6068;  0 drivers
+o0000000003da6098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3ca40_0 .net "B", 0 0, o0000000003da6098;  0 drivers
+o0000000003da60c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3cfe0_0 .net "C", 0 0, o0000000003da60c8;  0 drivers
+o0000000003da60f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3b460_0 .net "D_N", 0 0, o0000000003da60f8;  0 drivers
+L_00000000040eaa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3b500_0 .net8 "VGND", 0 0, L_00000000040eaa30;  1 drivers, strength-aware
+L_00000000040eadb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3cc20_0 .net8 "VNB", 0 0, L_00000000040eadb0;  1 drivers, strength-aware
+L_00000000040ea800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3b820_0 .net8 "VPB", 0 0, L_00000000040ea800;  1 drivers, strength-aware
+L_00000000040eaf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3cf40_0 .net8 "VPWR", 0 0, L_00000000040eaf00;  1 drivers, strength-aware
+v0000000003e3c220_0 .net "Y", 0 0, L_0000000004174250;  1 drivers
+S_0000000003d01830 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 93375, 4 93114 1, S_000000000291a3d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004174020 .functor NOT 1, o0000000003da60f8, C4<0>, C4<0>, C4<0>;
+L_0000000004173760 .functor NOR 1, o0000000003da6068, o0000000003da6098, o0000000003da60c8, L_0000000004174020;
+L_0000000004174250 .functor BUF 1, L_0000000004173760, C4<0>, C4<0>, C4<0>;
+v0000000003e3bdc0_0 .net "A", 0 0, o0000000003da6068;  alias, 0 drivers
+v0000000003e3b5a0_0 .net "B", 0 0, o0000000003da6098;  alias, 0 drivers
+v0000000003e3c7c0_0 .net "C", 0 0, o0000000003da60c8;  alias, 0 drivers
+v0000000003e3b6e0_0 .net "D_N", 0 0, o0000000003da60f8;  alias, 0 drivers
+L_00000000040ebad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3cb80_0 .net8 "VGND", 0 0, L_00000000040ebad0;  1 drivers, strength-aware
+L_00000000040eab10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3cea0_0 .net8 "VNB", 0 0, L_00000000040eab10;  1 drivers, strength-aware
+L_00000000040eb7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3baa0_0 .net8 "VPB", 0 0, L_00000000040eb7c0;  1 drivers, strength-aware
+L_00000000040ebb40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3be60_0 .net8 "VPWR", 0 0, L_00000000040ebb40;  1 drivers, strength-aware
+v0000000003e3bfa0_0 .net "Y", 0 0, L_0000000004174250;  alias, 1 drivers
+v0000000003e3bb40_0 .net "nor0_out_Y", 0 0, L_0000000004173760;  1 drivers
+v0000000003e3b3c0_0 .net "not0_out", 0 0, L_0000000004174020;  1 drivers
+S_000000000291ab50 .scope module, "sky130_fd_sc_hd__nor4b_4" "sky130_fd_sc_hd__nor4b_4" 4 93237;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da6518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3b640_0 .net "A", 0 0, o0000000003da6518;  0 drivers
+o0000000003da6548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3c0e0_0 .net "B", 0 0, o0000000003da6548;  0 drivers
+o0000000003da6578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3c680_0 .net "C", 0 0, o0000000003da6578;  0 drivers
+o0000000003da65a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3d1c0_0 .net "D_N", 0 0, o0000000003da65a8;  0 drivers
+L_00000000040ebbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d4e0_0 .net8 "VGND", 0 0, L_00000000040ebbb0;  1 drivers, strength-aware
+L_00000000040ea640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3c180_0 .net8 "VNB", 0 0, L_00000000040ea640;  1 drivers, strength-aware
+L_00000000040eacd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d300_0 .net8 "VPB", 0 0, L_00000000040eacd0;  1 drivers, strength-aware
+L_00000000040ea8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3b780_0 .net8 "VPWR", 0 0, L_00000000040ea8e0;  1 drivers, strength-aware
+v0000000003e3c9a0_0 .net "Y", 0 0, L_0000000004174090;  1 drivers
+S_0000000003d03f30 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 93257, 4 93114 1, S_000000000291ab50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_00000000041733e0 .functor NOT 1, o0000000003da65a8, C4<0>, C4<0>, C4<0>;
+L_00000000041737d0 .functor NOR 1, o0000000003da6518, o0000000003da6548, o0000000003da6578, L_00000000041733e0;
+L_0000000004174090 .functor BUF 1, L_00000000041737d0, C4<0>, C4<0>, C4<0>;
+v0000000003e3d260_0 .net "A", 0 0, o0000000003da6518;  alias, 0 drivers
+v0000000003e3d6c0_0 .net "B", 0 0, o0000000003da6548;  alias, 0 drivers
+v0000000003e3c5e0_0 .net "C", 0 0, o0000000003da6578;  alias, 0 drivers
+v0000000003e3b1e0_0 .net "D_N", 0 0, o0000000003da65a8;  alias, 0 drivers
+L_00000000040eaf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d080_0 .net8 "VGND", 0 0, L_00000000040eaf70;  1 drivers, strength-aware
+L_00000000040ebc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d800_0 .net8 "VNB", 0 0, L_00000000040ebc20;  1 drivers, strength-aware
+L_00000000040eb210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3c040_0 .net8 "VPB", 0 0, L_00000000040eb210;  1 drivers, strength-aware
+L_00000000040eb050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d8a0_0 .net8 "VPWR", 0 0, L_00000000040eb050;  1 drivers, strength-aware
+v0000000003e3b280_0 .net "Y", 0 0, L_0000000004174090;  alias, 1 drivers
+v0000000003e3b320_0 .net "nor0_out_Y", 0 0, L_00000000041737d0;  1 drivers
+v0000000003e3d120_0 .net "not0_out", 0 0, L_00000000041733e0;  1 drivers
+S_000000000289a650 .scope module, "sky130_fd_sc_hd__nor4bb_1" "sky130_fd_sc_hd__nor4bb_1" 4 26077;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da69c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3c360_0 .net "A", 0 0, o0000000003da69c8;  0 drivers
+o0000000003da69f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3c400_0 .net "B", 0 0, o0000000003da69f8;  0 drivers
+o0000000003da6a28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3f4c0_0 .net "C_N", 0 0, o0000000003da6a28;  0 drivers
+o0000000003da6a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e980_0 .net "D_N", 0 0, o0000000003da6a58;  0 drivers
+L_00000000040ebc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3fe20_0 .net8 "VGND", 0 0, L_00000000040ebc90;  1 drivers, strength-aware
+L_00000000040eb1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3fb00_0 .net8 "VNB", 0 0, L_00000000040eb1a0;  1 drivers, strength-aware
+L_00000000040ebd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3fce0_0 .net8 "VPB", 0 0, L_00000000040ebd00;  1 drivers, strength-aware
+L_00000000040ebd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3e520_0 .net8 "VPWR", 0 0, L_00000000040ebd70;  1 drivers, strength-aware
+v0000000003e3ee80_0 .net "Y", 0 0, L_0000000004173450;  1 drivers
+S_0000000003d043b0 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 26097, 4 26398 1, S_000000000289a650;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004173290 .functor NOR 1, o0000000003da69c8, o0000000003da69f8, C4<0>, C4<0>;
+L_00000000041749c0 .functor AND 1, L_0000000004173290, o0000000003da6a28, o0000000003da6a58, C4<1>;
+L_0000000004173450 .functor BUF 1, L_00000000041749c0, C4<0>, C4<0>, C4<0>;
+v0000000003e3d3a0_0 .net "A", 0 0, o0000000003da69c8;  alias, 0 drivers
+v0000000003e3bd20_0 .net "B", 0 0, o0000000003da69f8;  alias, 0 drivers
+v0000000003e3c860_0 .net "C_N", 0 0, o0000000003da6a28;  alias, 0 drivers
+v0000000003e3c2c0_0 .net "D_N", 0 0, o0000000003da6a58;  alias, 0 drivers
+L_00000000040ebec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3b8c0_0 .net8 "VGND", 0 0, L_00000000040ebec0;  1 drivers, strength-aware
+L_00000000040ebf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3c900_0 .net8 "VNB", 0 0, L_00000000040ebf30;  1 drivers, strength-aware
+L_00000000040ec010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3b960_0 .net8 "VPB", 0 0, L_00000000040ec010;  1 drivers, strength-aware
+L_00000000040ea560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3d580_0 .net8 "VPWR", 0 0, L_00000000040ea560;  1 drivers, strength-aware
+v0000000003e3d440_0 .net "Y", 0 0, L_0000000004173450;  alias, 1 drivers
+v0000000003e3bbe0_0 .net "and0_out_Y", 0 0, L_00000000041749c0;  1 drivers
+v0000000003e3bc80_0 .net "nor0_out", 0 0, L_0000000004173290;  1 drivers
+S_000000000289a350 .scope module, "sky130_fd_sc_hd__nor4bb_2" "sky130_fd_sc_hd__nor4bb_2" 4 25841;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da6e78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3de40_0 .net "A", 0 0, o0000000003da6e78;  0 drivers
+o0000000003da6ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e5c0_0 .net "B", 0 0, o0000000003da6ea8;  0 drivers
+o0000000003da6ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e2a0_0 .net "C_N", 0 0, o0000000003da6ed8;  0 drivers
+o0000000003da6f08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3ede0_0 .net "D_N", 0 0, o0000000003da6f08;  0 drivers
+L_00000000040eab80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3e7a0_0 .net8 "VGND", 0 0, L_00000000040eab80;  1 drivers, strength-aware
+L_00000000040eabf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f380_0 .net8 "VNB", 0 0, L_00000000040eabf0;  1 drivers, strength-aware
+L_00000000040eac60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ec00_0 .net8 "VPB", 0 0, L_00000000040eac60;  1 drivers, strength-aware
+L_00000000040ed7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3eca0_0 .net8 "VPWR", 0 0, L_00000000040ed7b0;  1 drivers, strength-aware
+v0000000003e3f7e0_0 .net "Y", 0 0, L_0000000004173b50;  1 drivers
+S_0000000003d031b0 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 25861, 4 26398 1, S_000000000289a350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_00000000041734c0 .functor NOR 1, o0000000003da6e78, o0000000003da6ea8, C4<0>, C4<0>;
+L_0000000004173920 .functor AND 1, L_00000000041734c0, o0000000003da6ed8, o0000000003da6f08, C4<1>;
+L_0000000004173b50 .functor BUF 1, L_0000000004173920, C4<0>, C4<0>, C4<0>;
+v0000000003e40000_0 .net "A", 0 0, o0000000003da6e78;  alias, 0 drivers
+v0000000003e3fec0_0 .net "B", 0 0, o0000000003da6ea8;  alias, 0 drivers
+v0000000003e3f560_0 .net "C_N", 0 0, o0000000003da6ed8;  alias, 0 drivers
+v0000000003e3e200_0 .net "D_N", 0 0, o0000000003da6f08;  alias, 0 drivers
+L_00000000040ed200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3e480_0 .net8 "VGND", 0 0, L_00000000040ed200;  1 drivers, strength-aware
+L_00000000040ecb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f600_0 .net8 "VNB", 0 0, L_00000000040ecb70;  1 drivers, strength-aware
+L_00000000040ec5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ed40_0 .net8 "VPB", 0 0, L_00000000040ec5c0;  1 drivers, strength-aware
+L_00000000040ed970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f240_0 .net8 "VPWR", 0 0, L_00000000040ed970;  1 drivers, strength-aware
+v0000000003e3f880_0 .net "Y", 0 0, L_0000000004173b50;  alias, 1 drivers
+v0000000003e3f2e0_0 .net "and0_out_Y", 0 0, L_0000000004173920;  1 drivers
+v0000000003e3f6a0_0 .net "nor0_out", 0 0, L_00000000041734c0;  1 drivers
+S_000000000289b850 .scope module, "sky130_fd_sc_hd__nor4bb_4" "sky130_fd_sc_hd__nor4bb_4" 4 25959;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003da7328 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3dbc0_0 .net "A", 0 0, o0000000003da7328;  0 drivers
+o0000000003da7358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e840_0 .net "B", 0 0, o0000000003da7358;  0 drivers
+o0000000003da7388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e400a0_0 .net "C_N", 0 0, o0000000003da7388;  0 drivers
+o0000000003da73b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3d9e0_0 .net "D_N", 0 0, o0000000003da73b8;  0 drivers
+L_00000000040ec400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f9c0_0 .net8 "VGND", 0 0, L_00000000040ec400;  1 drivers, strength-aware
+L_00000000040ed580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3da80_0 .net8 "VNB", 0 0, L_00000000040ed580;  1 drivers, strength-aware
+L_00000000040ec940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3db20_0 .net8 "VPB", 0 0, L_00000000040ec940;  1 drivers, strength-aware
+L_00000000040ec160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3fa60_0 .net8 "VPWR", 0 0, L_00000000040ec160;  1 drivers, strength-aware
+v0000000003e3fc40_0 .net "Y", 0 0, L_00000000041742c0;  1 drivers
+S_0000000003d061b0 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 25979, 4 26398 1, S_000000000289b850;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004173bc0 .functor NOR 1, o0000000003da7328, o0000000003da7358, C4<0>, C4<0>;
+L_0000000004174c60 .functor AND 1, L_0000000004173bc0, o0000000003da7388, o0000000003da73b8, C4<1>;
+L_00000000041742c0 .functor BUF 1, L_0000000004174c60, C4<0>, C4<0>, C4<0>;
+v0000000003e3f740_0 .net "A", 0 0, o0000000003da7328;  alias, 0 drivers
+v0000000003e3e340_0 .net "B", 0 0, o0000000003da7358;  alias, 0 drivers
+v0000000003e3e660_0 .net "C_N", 0 0, o0000000003da7388;  alias, 0 drivers
+v0000000003e3fba0_0 .net "D_N", 0 0, o0000000003da73b8;  alias, 0 drivers
+L_00000000040ed9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f920_0 .net8 "VGND", 0 0, L_00000000040ed9e0;  1 drivers, strength-aware
+L_00000000040ed660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ea20_0 .net8 "VNB", 0 0, L_00000000040ed660;  1 drivers, strength-aware
+L_00000000040ecda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ff60_0 .net8 "VPB", 0 0, L_00000000040ecda0;  1 drivers, strength-aware
+L_00000000040ec240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3ef20_0 .net8 "VPWR", 0 0, L_00000000040ec240;  1 drivers, strength-aware
+v0000000003e3d940_0 .net "Y", 0 0, L_00000000041742c0;  alias, 1 drivers
+v0000000003e3e700_0 .net "and0_out_Y", 0 0, L_0000000004174c60;  1 drivers
+v0000000003e3efc0_0 .net "nor0_out", 0 0, L_0000000004173bc0;  1 drivers
+S_0000000002899ed0 .scope module, "sky130_fd_sc_hd__o2111a_1" "sky130_fd_sc_hd__o2111a_1" 4 5848;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da77d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3df80_0 .net "A1", 0 0, o0000000003da77d8;  0 drivers
+o0000000003da7808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3f1a0_0 .net "A2", 0 0, o0000000003da7808;  0 drivers
+o0000000003da7838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e020_0 .net "B1", 0 0, o0000000003da7838;  0 drivers
+o0000000003da7868 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e0c0_0 .net "C1", 0 0, o0000000003da7868;  0 drivers
+o0000000003da7898 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e3e160_0 .net "D1", 0 0, o0000000003da7898;  0 drivers
+L_00000000040ed820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e40a00_0 .net8 "VGND", 0 0, L_00000000040ed820;  1 drivers, strength-aware
+L_00000000040eca90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e403c0_0 .net8 "VNB", 0 0, L_00000000040eca90;  1 drivers, strength-aware
+L_00000000040ecc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e415e0_0 .net8 "VPB", 0 0, L_00000000040ecc50;  1 drivers, strength-aware
+L_00000000040ecef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e41fe0_0 .net8 "VPWR", 0 0, L_00000000040ecef0;  1 drivers, strength-aware
+v0000000003e414a0_0 .net "X", 0 0, L_0000000004173c30;  1 drivers
+S_0000000003d04e30 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 5870, 4 6188 1, S_0000000002899ed0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004174950 .functor OR 1, o0000000003da7808, o0000000003da77d8, C4<0>, C4<0>;
+L_0000000004173a70 .functor AND 1, o0000000003da7838, o0000000003da7868, L_0000000004174950, o0000000003da7898;
+L_0000000004173c30 .functor BUF 1, L_0000000004173a70, C4<0>, C4<0>, C4<0>;
+v0000000003e3dee0_0 .net "A1", 0 0, o0000000003da77d8;  alias, 0 drivers
+v0000000003e3dc60_0 .net "A2", 0 0, o0000000003da7808;  alias, 0 drivers
+v0000000003e3f420_0 .net "B1", 0 0, o0000000003da7838;  alias, 0 drivers
+v0000000003e3e8e0_0 .net "C1", 0 0, o0000000003da7868;  alias, 0 drivers
+v0000000003e3e3e0_0 .net "D1", 0 0, o0000000003da7898;  alias, 0 drivers
+L_00000000040ed4a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3f060_0 .net8 "VGND", 0 0, L_00000000040ed4a0;  1 drivers, strength-aware
+L_00000000040edac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e3eac0_0 .net8 "VNB", 0 0, L_00000000040edac0;  1 drivers, strength-aware
+L_00000000040ec6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3fd80_0 .net8 "VPB", 0 0, L_00000000040ec6a0;  1 drivers, strength-aware
+L_00000000040ecbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e3dd00_0 .net8 "VPWR", 0 0, L_00000000040ecbe0;  1 drivers, strength-aware
+v0000000003e3f100_0 .net "X", 0 0, L_0000000004173c30;  alias, 1 drivers
+v0000000003e3dda0_0 .net "and0_out_X", 0 0, L_0000000004173a70;  1 drivers
+v0000000003e3eb60_0 .net "or0_out", 0 0, L_0000000004174950;  1 drivers
+S_0000000002899bd0 .scope module, "sky130_fd_sc_hd__o2111a_2" "sky130_fd_sc_hd__o2111a_2" 4 5722;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da7d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e406e0_0 .net "A1", 0 0, o0000000003da7d18;  0 drivers
+o0000000003da7d48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e428a0_0 .net "A2", 0 0, o0000000003da7d48;  0 drivers
+o0000000003da7d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e42080_0 .net "B1", 0 0, o0000000003da7d78;  0 drivers
+o0000000003da7da8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e40140_0 .net "C1", 0 0, o0000000003da7da8;  0 drivers
+o0000000003da7dd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e419a0_0 .net "D1", 0 0, o0000000003da7dd8;  0 drivers
+L_00000000040ed270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e40d20_0 .net8 "VGND", 0 0, L_00000000040ed270;  1 drivers, strength-aware
+L_00000000040ec710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e40780_0 .net8 "VNB", 0 0, L_00000000040ec710;  1 drivers, strength-aware
+L_00000000040ec630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e401e0_0 .net8 "VPB", 0 0, L_00000000040ec630;  1 drivers, strength-aware
+L_00000000040ec9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e40e60_0 .net8 "VPWR", 0 0, L_00000000040ec9b0;  1 drivers, strength-aware
+v0000000003e41ea0_0 .net "X", 0 0, L_0000000004173990;  1 drivers
+S_0000000003d02130 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 5744, 4 6188 1, S_0000000002899bd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004174100 .functor OR 1, o0000000003da7d48, o0000000003da7d18, C4<0>, C4<0>;
+L_00000000041748e0 .functor AND 1, o0000000003da7d78, o0000000003da7da8, L_0000000004174100, o0000000003da7dd8;
+L_0000000004173990 .functor BUF 1, L_00000000041748e0, C4<0>, C4<0>, C4<0>;
+v0000000003e42800_0 .net "A1", 0 0, o0000000003da7d18;  alias, 0 drivers
+v0000000003e40820_0 .net "A2", 0 0, o0000000003da7d48;  alias, 0 drivers
+v0000000003e40500_0 .net "B1", 0 0, o0000000003da7d78;  alias, 0 drivers
+v0000000003e405a0_0 .net "C1", 0 0, o0000000003da7da8;  alias, 0 drivers
+v0000000003e40640_0 .net "D1", 0 0, o0000000003da7dd8;  alias, 0 drivers
+L_00000000040ec470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e40dc0_0 .net8 "VGND", 0 0, L_00000000040ec470;  1 drivers, strength-aware
+L_00000000040eca20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e41540_0 .net8 "VNB", 0 0, L_00000000040eca20;  1 drivers, strength-aware
+L_00000000040ed2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e41360_0 .net8 "VPB", 0 0, L_00000000040ed2e0;  1 drivers, strength-aware
+L_00000000040eccc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e408c0_0 .net8 "VPWR", 0 0, L_00000000040eccc0;  1 drivers, strength-aware
+v0000000003e42760_0 .net "X", 0 0, L_0000000004173990;  alias, 1 drivers
+v0000000003e41860_0 .net "and0_out_X", 0 0, L_00000000041748e0;  1 drivers
+v0000000003e41680_0 .net "or0_out", 0 0, L_0000000004174100;  1 drivers
+S_000000000289a950 .scope module, "sky130_fd_sc_hd__o2111a_4" "sky130_fd_sc_hd__o2111a_4" 4 6318;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da8258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e41ae0_0 .net "A1", 0 0, o0000000003da8258;  0 drivers
+o0000000003da8288 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e40fa0_0 .net "A2", 0 0, o0000000003da8288;  0 drivers
+o0000000003da82b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e41cc0_0 .net "B1", 0 0, o0000000003da82b8;  0 drivers
+o0000000003da82e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e41040_0 .net "C1", 0 0, o0000000003da82e8;  0 drivers
+o0000000003da8318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e40320_0 .net "D1", 0 0, o0000000003da8318;  0 drivers
+L_00000000040edc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e41d60_0 .net8 "VGND", 0 0, L_00000000040edc10;  1 drivers, strength-aware
+L_00000000040ec390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e41e00_0 .net8 "VNB", 0 0, L_00000000040ec390;  1 drivers, strength-aware
+L_00000000040eda50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e424e0_0 .net8 "VPB", 0 0, L_00000000040eda50;  1 drivers, strength-aware
+L_00000000040ec0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e41220_0 .net8 "VPWR", 0 0, L_00000000040ec0f0;  1 drivers, strength-aware
+v0000000003e421c0_0 .net "X", 0 0, L_0000000004173e60;  1 drivers
+S_0000000003d03030 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 6340, 4 6188 1, S_000000000289a950;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004173680 .functor OR 1, o0000000003da8288, o0000000003da8258, C4<0>, C4<0>;
+L_00000000041744f0 .functor AND 1, o0000000003da82b8, o0000000003da82e8, L_0000000004173680, o0000000003da8318;
+L_0000000004173e60 .functor BUF 1, L_00000000041744f0, C4<0>, C4<0>, C4<0>;
+v0000000003e41c20_0 .net "A1", 0 0, o0000000003da8258;  alias, 0 drivers
+v0000000003e41a40_0 .net "A2", 0 0, o0000000003da8288;  alias, 0 drivers
+v0000000003e41b80_0 .net "B1", 0 0, o0000000003da82b8;  alias, 0 drivers
+v0000000003e40960_0 .net "C1", 0 0, o0000000003da82e8;  alias, 0 drivers
+v0000000003e40aa0_0 .net "D1", 0 0, o0000000003da8318;  alias, 0 drivers
+L_00000000040ecd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e40280_0 .net8 "VGND", 0 0, L_00000000040ecd30;  1 drivers, strength-aware
+L_00000000040ed5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e426c0_0 .net8 "VNB", 0 0, L_00000000040ed5f0;  1 drivers, strength-aware
+L_00000000040ec2b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e40f00_0 .net8 "VPB", 0 0, L_00000000040ec2b0;  1 drivers, strength-aware
+L_00000000040ed890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e40b40_0 .net8 "VPWR", 0 0, L_00000000040ed890;  1 drivers, strength-aware
+v0000000003e41180_0 .net "X", 0 0, L_0000000004173e60;  alias, 1 drivers
+v0000000003e410e0_0 .net "and0_out_X", 0 0, L_00000000041744f0;  1 drivers
+v0000000003e40460_0 .net "or0_out", 0 0, L_0000000004173680;  1 drivers
+S_0000000002898550 .scope module, "sky130_fd_sc_hd__o2111ai_1" "sky130_fd_sc_hd__o2111ai_1" 4 63007;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da8798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e42440_0 .net "A1", 0 0, o0000000003da8798;  0 drivers
+o0000000003da87c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e42580_0 .net "A2", 0 0, o0000000003da87c8;  0 drivers
+o0000000003da87f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e42620_0 .net "B1", 0 0, o0000000003da87f8;  0 drivers
+o0000000003da8828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e44a60_0 .net "C1", 0 0, o0000000003da8828;  0 drivers
+o0000000003da8858 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43980_0 .net "D1", 0 0, o0000000003da8858;  0 drivers
+L_00000000040ed510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e43d40_0 .net8 "VGND", 0 0, L_00000000040ed510;  1 drivers, strength-aware
+L_00000000040ecb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e42940_0 .net8 "VNB", 0 0, L_00000000040ecb00;  1 drivers, strength-aware
+L_00000000040ec4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44560_0 .net8 "VPB", 0 0, L_00000000040ec4e0;  1 drivers, strength-aware
+L_00000000040ed350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e42da0_0 .net8 "VPWR", 0 0, L_00000000040ed350;  1 drivers, strength-aware
+v0000000003e437a0_0 .net "Y", 0 0, L_00000000041745d0;  1 drivers
+S_0000000003d04fb0 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63029, 4 63599 1, S_0000000002898550;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004174560 .functor OR 1, o0000000003da87c8, o0000000003da8798, C4<0>, C4<0>;
+L_0000000004174b10 .functor NAND 1, o0000000003da8828, o0000000003da87f8, o0000000003da8858, L_0000000004174560;
+L_00000000041745d0 .functor BUF 1, L_0000000004174b10, C4<0>, C4<0>, C4<0>;
+v0000000003e40be0_0 .net "A1", 0 0, o0000000003da8798;  alias, 0 drivers
+v0000000003e40c80_0 .net "A2", 0 0, o0000000003da87c8;  alias, 0 drivers
+v0000000003e412c0_0 .net "B1", 0 0, o0000000003da87f8;  alias, 0 drivers
+v0000000003e41400_0 .net "C1", 0 0, o0000000003da8828;  alias, 0 drivers
+v0000000003e42120_0 .net "D1", 0 0, o0000000003da8858;  alias, 0 drivers
+L_00000000040ece10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e41720_0 .net8 "VGND", 0 0, L_00000000040ece10;  1 drivers, strength-aware
+L_00000000040ec1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e417c0_0 .net8 "VNB", 0 0, L_00000000040ec1d0;  1 drivers, strength-aware
+L_00000000040ec780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e41900_0 .net8 "VPB", 0 0, L_00000000040ec780;  1 drivers, strength-aware
+L_00000000040ed6d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e41f40_0 .net8 "VPWR", 0 0, L_00000000040ed6d0;  1 drivers, strength-aware
+v0000000003e42260_0 .net "Y", 0 0, L_00000000041745d0;  alias, 1 drivers
+v0000000003e42300_0 .net "nand0_out_Y", 0 0, L_0000000004174b10;  1 drivers
+v0000000003e423a0_0 .net "or0_out", 0 0, L_0000000004174560;  1 drivers
+S_000000000289b0d0 .scope module, "sky130_fd_sc_hd__o2111ai_2" "sky130_fd_sc_hd__o2111ai_2" 4 63133;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da8cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43e80_0 .net "A1", 0 0, o0000000003da8cd8;  0 drivers
+o0000000003da8d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e449c0_0 .net "A2", 0 0, o0000000003da8d08;  0 drivers
+o0000000003da8d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43840_0 .net "B1", 0 0, o0000000003da8d38;  0 drivers
+o0000000003da8d68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e44380_0 .net "C1", 0 0, o0000000003da8d68;  0 drivers
+o0000000003da8d98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43c00_0 .net "D1", 0 0, o0000000003da8d98;  0 drivers
+L_00000000040ed900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e446a0_0 .net8 "VGND", 0 0, L_00000000040ed900;  1 drivers, strength-aware
+L_00000000040ed040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e43340_0 .net8 "VNB", 0 0, L_00000000040ed040;  1 drivers, strength-aware
+L_00000000040edb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44740_0 .net8 "VPB", 0 0, L_00000000040edb30;  1 drivers, strength-aware
+L_00000000040ecf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e438e0_0 .net8 "VPWR", 0 0, L_00000000040ecf60;  1 drivers, strength-aware
+v0000000003e43f20_0 .net "Y", 0 0, L_0000000004173f40;  1 drivers
+S_0000000003d02eb0 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63155, 4 63599 1, S_000000000289b0d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004174640 .functor OR 1, o0000000003da8d08, o0000000003da8cd8, C4<0>, C4<0>;
+L_0000000004173530 .functor NAND 1, o0000000003da8d68, o0000000003da8d38, o0000000003da8d98, L_0000000004174640;
+L_0000000004173f40 .functor BUF 1, L_0000000004173530, C4<0>, C4<0>, C4<0>;
+v0000000003e444c0_0 .net "A1", 0 0, o0000000003da8cd8;  alias, 0 drivers
+v0000000003e44880_0 .net "A2", 0 0, o0000000003da8d08;  alias, 0 drivers
+v0000000003e450a0_0 .net "B1", 0 0, o0000000003da8d38;  alias, 0 drivers
+v0000000003e43480_0 .net "C1", 0 0, o0000000003da8d68;  alias, 0 drivers
+v0000000003e447e0_0 .net "D1", 0 0, o0000000003da8d98;  alias, 0 drivers
+L_00000000040ece80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e43de0_0 .net8 "VGND", 0 0, L_00000000040ece80;  1 drivers, strength-aware
+L_00000000040edba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e44240_0 .net8 "VNB", 0 0, L_00000000040edba0;  1 drivers, strength-aware
+L_00000000040ed430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44920_0 .net8 "VPB", 0 0, L_00000000040ed430;  1 drivers, strength-aware
+L_00000000040ecfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44d80_0 .net8 "VPWR", 0 0, L_00000000040ecfd0;  1 drivers, strength-aware
+v0000000003e44600_0 .net "Y", 0 0, L_0000000004173f40;  alias, 1 drivers
+v0000000003e44ce0_0 .net "nand0_out_Y", 0 0, L_0000000004173530;  1 drivers
+v0000000003e42e40_0 .net "or0_out", 0 0, L_0000000004174640;  1 drivers
+S_000000000289bb50 .scope module, "sky130_fd_sc_hd__o2111ai_4" "sky130_fd_sc_hd__o2111ai_4" 4 63259;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+o0000000003da9218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43ac0_0 .net "A1", 0 0, o0000000003da9218;  0 drivers
+o0000000003da9248 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e44f60_0 .net "A2", 0 0, o0000000003da9248;  0 drivers
+o0000000003da9278 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43ca0_0 .net "B1", 0 0, o0000000003da9278;  0 drivers
+o0000000003da92a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e435c0_0 .net "C1", 0 0, o0000000003da92a8;  0 drivers
+o0000000003da92d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e45000_0 .net "D1", 0 0, o0000000003da92d8;  0 drivers
+L_00000000040edc80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e429e0_0 .net8 "VGND", 0 0, L_00000000040edc80;  1 drivers, strength-aware
+L_00000000040ec320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e441a0_0 .net8 "VNB", 0 0, L_00000000040ec320;  1 drivers, strength-aware
+L_00000000040ec550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e43b60_0 .net8 "VPB", 0 0, L_00000000040ec550;  1 drivers, strength-aware
+L_00000000040ec7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e42a80_0 .net8 "VPWR", 0 0, L_00000000040ec7f0;  1 drivers, strength-aware
+v0000000003e42b20_0 .net "Y", 0 0, L_0000000004173610;  1 drivers
+S_0000000003d02a30 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63281, 4 63599 1, S_000000000289bb50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+    .port_info 5 /INPUT 1 "D1"
+L_0000000004174bf0 .functor OR 1, o0000000003da9248, o0000000003da9218, C4<0>, C4<0>;
+L_00000000041735a0 .functor NAND 1, o0000000003da92a8, o0000000003da9278, o0000000003da92d8, L_0000000004174bf0;
+L_0000000004173610 .functor BUF 1, L_00000000041735a0, C4<0>, C4<0>, C4<0>;
+v0000000003e43700_0 .net "A1", 0 0, o0000000003da9218;  alias, 0 drivers
+v0000000003e43200_0 .net "A2", 0 0, o0000000003da9248;  alias, 0 drivers
+v0000000003e44b00_0 .net "B1", 0 0, o0000000003da9278;  alias, 0 drivers
+v0000000003e44ba0_0 .net "C1", 0 0, o0000000003da92a8;  alias, 0 drivers
+v0000000003e42ee0_0 .net "D1", 0 0, o0000000003da92d8;  alias, 0 drivers
+L_00000000040ec860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e43a20_0 .net8 "VGND", 0 0, L_00000000040ec860;  1 drivers, strength-aware
+L_00000000040ec8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e442e0_0 .net8 "VNB", 0 0, L_00000000040ec8d0;  1 drivers, strength-aware
+L_00000000040ed0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44c40_0 .net8 "VPB", 0 0, L_00000000040ed0b0;  1 drivers, strength-aware
+L_00000000040ed120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e430c0_0 .net8 "VPWR", 0 0, L_00000000040ed120;  1 drivers, strength-aware
+v0000000003e44e20_0 .net "Y", 0 0, L_0000000004173610;  alias, 1 drivers
+v0000000003e44ec0_0 .net "nand0_out_Y", 0 0, L_00000000041735a0;  1 drivers
+v0000000003e44420_0 .net "or0_out", 0 0, L_0000000004174bf0;  1 drivers
+S_00000000028980d0 .scope module, "sky130_fd_sc_hd__o211a_1" "sky130_fd_sc_hd__o211a_1" 4 77584;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003da9758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e433e0_0 .net "A1", 0 0, o0000000003da9758;  0 drivers
+o0000000003da9788 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e43520_0 .net "A2", 0 0, o0000000003da9788;  0 drivers
+o0000000003da97b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e469a0_0 .net "B1", 0 0, o0000000003da97b8;  0 drivers
+o0000000003da97e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e46cc0_0 .net "C1", 0 0, o0000000003da97e8;  0 drivers
+L_00000000040ed740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e45460_0 .net8 "VGND", 0 0, L_00000000040ed740;  1 drivers, strength-aware
+L_00000000040ed190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e47260_0 .net8 "VNB", 0 0, L_00000000040ed190;  1 drivers, strength-aware
+L_00000000040ed3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45a00_0 .net8 "VPB", 0 0, L_00000000040ed3c0;  1 drivers, strength-aware
+L_00000000040eec40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45c80_0 .net8 "VPWR", 0 0, L_00000000040eec40;  1 drivers, strength-aware
+v0000000003e46fe0_0 .net "X", 0 0, L_0000000004173fb0;  1 drivers
+S_0000000003d05bb0 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77604, 4 77459 1, S_00000000028980d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_00000000041736f0 .functor OR 1, o0000000003da9788, o0000000003da9758, C4<0>, C4<0>;
+L_0000000004173840 .functor AND 1, L_00000000041736f0, o0000000003da97b8, o0000000003da97e8, C4<1>;
+L_0000000004173fb0 .functor BUF 1, L_0000000004173840, C4<0>, C4<0>, C4<0>;
+v0000000003e43660_0 .net "A1", 0 0, o0000000003da9758;  alias, 0 drivers
+v0000000003e42bc0_0 .net "A2", 0 0, o0000000003da9788;  alias, 0 drivers
+v0000000003e42c60_0 .net "B1", 0 0, o0000000003da97b8;  alias, 0 drivers
+v0000000003e43fc0_0 .net "C1", 0 0, o0000000003da97e8;  alias, 0 drivers
+L_00000000040ef7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e42f80_0 .net8 "VGND", 0 0, L_00000000040ef7a0;  1 drivers, strength-aware
+L_00000000040ef110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e42d00_0 .net8 "VNB", 0 0, L_00000000040ef110;  1 drivers, strength-aware
+L_00000000040ee000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44060_0 .net8 "VPB", 0 0, L_00000000040ee000;  1 drivers, strength-aware
+L_00000000040ee070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e44100_0 .net8 "VPWR", 0 0, L_00000000040ee070;  1 drivers, strength-aware
+v0000000003e43020_0 .net "X", 0 0, L_0000000004173fb0;  alias, 1 drivers
+v0000000003e43160_0 .net "and0_out_X", 0 0, L_0000000004173840;  1 drivers
+v0000000003e432a0_0 .net "or0_out", 0 0, L_00000000041736f0;  1 drivers
+S_00000000028983d0 .scope module, "sky130_fd_sc_hd__o211a_4" "sky130_fd_sc_hd__o211a_4" 4 77824;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003da9c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e46900_0 .net "A1", 0 0, o0000000003da9c08;  0 drivers
+o0000000003da9c38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47580_0 .net "A2", 0 0, o0000000003da9c38;  0 drivers
+o0000000003da9c68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e46ae0_0 .net "B1", 0 0, o0000000003da9c68;  0 drivers
+o0000000003da9c98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e46ea0_0 .net "C1", 0 0, o0000000003da9c98;  0 drivers
+L_00000000040eea80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e45aa0_0 .net8 "VGND", 0 0, L_00000000040eea80;  1 drivers, strength-aware
+L_00000000040ef3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e46040_0 .net8 "VNB", 0 0, L_00000000040ef3b0;  1 drivers, strength-aware
+L_00000000040ef030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45140_0 .net8 "VPB", 0 0, L_00000000040ef030;  1 drivers, strength-aware
+L_00000000040ee2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45b40_0 .net8 "VPWR", 0 0, L_00000000040ee2a0;  1 drivers, strength-aware
+v0000000003e45500_0 .net "X", 0 0, L_0000000004173df0;  1 drivers
+S_0000000003d067b0 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77844, 4 77459 1, S_00000000028983d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_00000000041738b0 .functor OR 1, o0000000003da9c38, o0000000003da9c08, C4<0>, C4<0>;
+L_0000000004173d10 .functor AND 1, L_00000000041738b0, o0000000003da9c68, o0000000003da9c98, C4<1>;
+L_0000000004173df0 .functor BUF 1, L_0000000004173d10, C4<0>, C4<0>, C4<0>;
+v0000000003e474e0_0 .net "A1", 0 0, o0000000003da9c08;  alias, 0 drivers
+v0000000003e456e0_0 .net "A2", 0 0, o0000000003da9c38;  alias, 0 drivers
+v0000000003e45640_0 .net "B1", 0 0, o0000000003da9c68;  alias, 0 drivers
+v0000000003e45d20_0 .net "C1", 0 0, o0000000003da9c98;  alias, 0 drivers
+L_00000000040eeb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e46540_0 .net8 "VGND", 0 0, L_00000000040eeb60;  1 drivers, strength-aware
+L_00000000040eea10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e471c0_0 .net8 "VNB", 0 0, L_00000000040eea10;  1 drivers, strength-aware
+L_00000000040ee4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e453c0_0 .net8 "VPB", 0 0, L_00000000040ee4d0;  1 drivers, strength-aware
+L_00000000040ee690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e46d60_0 .net8 "VPWR", 0 0, L_00000000040ee690;  1 drivers, strength-aware
+v0000000003e46b80_0 .net "X", 0 0, L_0000000004173df0;  alias, 1 drivers
+v0000000003e46a40_0 .net "and0_out_X", 0 0, L_0000000004173d10;  1 drivers
+v0000000003e46e00_0 .net "or0_out", 0 0, L_00000000041738b0;  1 drivers
+S_0000000002898b50 .scope module, "sky130_fd_sc_hd__o211ai_1" "sky130_fd_sc_hd__o211ai_1" 4 77944;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003daa0b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e46c20_0 .net "A1", 0 0, o0000000003daa0b8;  0 drivers
+o0000000003daa0e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47120_0 .net "A2", 0 0, o0000000003daa0e8;  0 drivers
+o0000000003daa118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47300_0 .net "B1", 0 0, o0000000003daa118;  0 drivers
+o0000000003daa148 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47760_0 .net "C1", 0 0, o0000000003daa148;  0 drivers
+L_00000000040ef420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e45e60_0 .net8 "VGND", 0 0, L_00000000040ef420;  1 drivers, strength-aware
+L_00000000040ef730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e476c0_0 .net8 "VNB", 0 0, L_00000000040ef730;  1 drivers, strength-aware
+L_00000000040edf20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e473a0_0 .net8 "VPB", 0 0, L_00000000040edf20;  1 drivers, strength-aware
+L_00000000040ef490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e451e0_0 .net8 "VPWR", 0 0, L_00000000040ef490;  1 drivers, strength-aware
+v0000000003e47440_0 .net "Y", 0 0, L_0000000004174330;  1 drivers
+S_0000000003d034b0 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 77964, 4 78275 1, S_0000000002898b50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_0000000004173ed0 .functor OR 1, o0000000003daa0e8, o0000000003daa0b8, C4<0>, C4<0>;
+L_00000000041741e0 .functor NAND 1, o0000000003daa148, L_0000000004173ed0, o0000000003daa118, C4<1>;
+L_0000000004174330 .functor BUF 1, L_00000000041741e0, C4<0>, C4<0>, C4<0>;
+v0000000003e47080_0 .net "A1", 0 0, o0000000003daa0b8;  alias, 0 drivers
+v0000000003e455a0_0 .net "A2", 0 0, o0000000003daa0e8;  alias, 0 drivers
+v0000000003e47620_0 .net "B1", 0 0, o0000000003daa118;  alias, 0 drivers
+v0000000003e45dc0_0 .net "C1", 0 0, o0000000003daa148;  alias, 0 drivers
+L_00000000040eef50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e45be0_0 .net8 "VGND", 0 0, L_00000000040eef50;  1 drivers, strength-aware
+L_00000000040ee770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e46220_0 .net8 "VNB", 0 0, L_00000000040ee770;  1 drivers, strength-aware
+L_00000000040ef340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45780_0 .net8 "VPB", 0 0, L_00000000040ef340;  1 drivers, strength-aware
+L_00000000040ee850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45820_0 .net8 "VPWR", 0 0, L_00000000040ee850;  1 drivers, strength-aware
+v0000000003e46f40_0 .net "Y", 0 0, L_0000000004174330;  alias, 1 drivers
+v0000000003e464a0_0 .net "nand0_out_Y", 0 0, L_00000000041741e0;  1 drivers
+v0000000003e46360_0 .net "or0_out", 0 0, L_0000000004173ed0;  1 drivers
+S_000000000289ac50 .scope module, "sky130_fd_sc_hd__o211ai_4" "sky130_fd_sc_hd__o211ai_4" 4 78400;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+o0000000003daa568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e45f00_0 .net "A1", 0 0, o0000000003daa568;  0 drivers
+o0000000003daa598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e462c0_0 .net "A2", 0 0, o0000000003daa598;  0 drivers
+o0000000003daa5c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e45fa0_0 .net "B1", 0 0, o0000000003daa5c8;  0 drivers
+o0000000003daa5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e467c0_0 .net "C1", 0 0, o0000000003daa5f8;  0 drivers
+L_00000000040eee00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e46400_0 .net8 "VGND", 0 0, L_00000000040eee00;  1 drivers, strength-aware
+L_00000000040ef6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e46860_0 .net8 "VNB", 0 0, L_00000000040ef6c0;  1 drivers, strength-aware
+L_00000000040ef500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48de0_0 .net8 "VPB", 0 0, L_00000000040ef500;  1 drivers, strength-aware
+L_00000000040ee540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e499c0_0 .net8 "VPWR", 0 0, L_00000000040ee540;  1 drivers, strength-aware
+v0000000003e47bc0_0 .net "Y", 0 0, L_0000000004174790;  1 drivers
+S_0000000003d06330 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 78420, 4 78275 1, S_000000000289ac50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "C1"
+L_00000000041746b0 .functor OR 1, o0000000003daa598, o0000000003daa568, C4<0>, C4<0>;
+L_0000000004174720 .functor NAND 1, o0000000003daa5f8, L_00000000041746b0, o0000000003daa5c8, C4<1>;
+L_0000000004174790 .functor BUF 1, L_0000000004174720, C4<0>, C4<0>, C4<0>;
+v0000000003e465e0_0 .net "A1", 0 0, o0000000003daa568;  alias, 0 drivers
+v0000000003e47800_0 .net "A2", 0 0, o0000000003daa598;  alias, 0 drivers
+v0000000003e478a0_0 .net "B1", 0 0, o0000000003daa5c8;  alias, 0 drivers
+v0000000003e45280_0 .net "C1", 0 0, o0000000003daa5f8;  alias, 0 drivers
+L_00000000040ef0a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e45320_0 .net8 "VGND", 0 0, L_00000000040ef0a0;  1 drivers, strength-aware
+L_00000000040eeaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e458c0_0 .net8 "VNB", 0 0, L_00000000040eeaf0;  1 drivers, strength-aware
+L_00000000040eeee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e45960_0 .net8 "VPB", 0 0, L_00000000040eeee0;  1 drivers, strength-aware
+L_00000000040ef5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e460e0_0 .net8 "VPWR", 0 0, L_00000000040ef5e0;  1 drivers, strength-aware
+v0000000003e46180_0 .net "Y", 0 0, L_0000000004174790;  alias, 1 drivers
+v0000000003e46680_0 .net "nand0_out_Y", 0 0, L_0000000004174720;  1 drivers
+v0000000003e46720_0 .net "or0_out", 0 0, L_00000000041746b0;  1 drivers
+S_00000000028986d0 .scope module, "sky130_fd_sc_hd__o21a_1" "sky130_fd_sc_hd__o21a_1" 4 65062;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003daaa18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e49920_0 .net "A1", 0 0, o0000000003daaa18;  0 drivers
+o0000000003daaa48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e480c0_0 .net "A2", 0 0, o0000000003daaa48;  0 drivers
+o0000000003daaa78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47d00_0 .net "B1", 0 0, o0000000003daaa78;  0 drivers
+L_00000000040ee9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e49420_0 .net8 "VGND", 0 0, L_00000000040ee9a0;  1 drivers, strength-aware
+L_00000000040ede40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48160_0 .net8 "VNB", 0 0, L_00000000040ede40;  1 drivers, strength-aware
+L_00000000040ee310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e47da0_0 .net8 "VPB", 0 0, L_00000000040ee310;  1 drivers, strength-aware
+L_00000000040edeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48200_0 .net8 "VPWR", 0 0, L_00000000040edeb0;  1 drivers, strength-aware
+v0000000003e487a0_0 .net "X", 0 0, L_0000000004174aa0;  1 drivers
+S_0000000003d037b0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65080, 4 65384 1, S_00000000028986d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004174870 .functor OR 1, o0000000003daaa48, o0000000003daaa18, C4<0>, C4<0>;
+L_0000000004174a30 .functor AND 1, L_0000000004174870, o0000000003daaa78, C4<1>, C4<1>;
+L_0000000004174aa0 .functor BUF 1, L_0000000004174a30, C4<0>, C4<0>, C4<0>;
+v0000000003e49d80_0 .net "A1", 0 0, o0000000003daaa18;  alias, 0 drivers
+v0000000003e492e0_0 .net "A2", 0 0, o0000000003daaa48;  alias, 0 drivers
+v0000000003e49560_0 .net "B1", 0 0, o0000000003daaa78;  alias, 0 drivers
+L_00000000040eebd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48ac0_0 .net8 "VGND", 0 0, L_00000000040eebd0;  1 drivers, strength-aware
+L_00000000040edf90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48840_0 .net8 "VNB", 0 0, L_00000000040edf90;  1 drivers, strength-aware
+L_00000000040eecb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48660_0 .net8 "VPB", 0 0, L_00000000040eecb0;  1 drivers, strength-aware
+L_00000000040eed20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e49600_0 .net8 "VPWR", 0 0, L_00000000040eed20;  1 drivers, strength-aware
+v0000000003e49a60_0 .net "X", 0 0, L_0000000004174aa0;  alias, 1 drivers
+v0000000003e48020_0 .net "and0_out_X", 0 0, L_0000000004174a30;  1 drivers
+v0000000003e47e40_0 .net "or0_out", 0 0, L_0000000004174870;  1 drivers
+S_00000000028995d0 .scope module, "sky130_fd_sc_hd__o21a_4" "sky130_fd_sc_hd__o21a_4" 4 65504;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003daae38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e47f80_0 .net "A1", 0 0, o0000000003daae38;  0 drivers
+o0000000003daae68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e49ba0_0 .net "A2", 0 0, o0000000003daae68;  0 drivers
+o0000000003daae98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e49f60_0 .net "B1", 0 0, o0000000003daae98;  0 drivers
+L_00000000040ee1c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e494c0_0 .net8 "VGND", 0 0, L_00000000040ee1c0;  1 drivers, strength-aware
+L_00000000040ee5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e496a0_0 .net8 "VNB", 0 0, L_00000000040ee5b0;  1 drivers, strength-aware
+L_00000000040ee0e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e49380_0 .net8 "VPB", 0 0, L_00000000040ee0e0;  1 drivers, strength-aware
+L_00000000040ee620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e488e0_0 .net8 "VPWR", 0 0, L_00000000040ee620;  1 drivers, strength-aware
+v0000000003e49c40_0 .net "X", 0 0, L_0000000004176630;  1 drivers
+S_0000000003d022b0 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65522, 4 65384 1, S_00000000028995d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004174b80 .functor OR 1, o0000000003daae68, o0000000003daae38, C4<0>, C4<0>;
+L_0000000004175ec0 .functor AND 1, L_0000000004174b80, o0000000003daae98, C4<1>, C4<1>;
+L_0000000004176630 .functor BUF 1, L_0000000004175ec0, C4<0>, C4<0>, C4<0>;
+v0000000003e49b00_0 .net "A1", 0 0, o0000000003daae38;  alias, 0 drivers
+v0000000003e49060_0 .net "A2", 0 0, o0000000003daae68;  alias, 0 drivers
+v0000000003e48700_0 .net "B1", 0 0, o0000000003daae98;  alias, 0 drivers
+L_00000000040ef180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48c00_0 .net8 "VGND", 0 0, L_00000000040ef180;  1 drivers, strength-aware
+L_00000000040ee230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e49ec0_0 .net8 "VNB", 0 0, L_00000000040ee230;  1 drivers, strength-aware
+L_00000000040eed90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e47ee0_0 .net8 "VPB", 0 0, L_00000000040eed90;  1 drivers, strength-aware
+L_00000000040eee70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48f20_0 .net8 "VPWR", 0 0, L_00000000040eee70;  1 drivers, strength-aware
+v0000000003e49ce0_0 .net "X", 0 0, L_0000000004176630;  alias, 1 drivers
+v0000000003e49880_0 .net "and0_out_X", 0 0, L_0000000004175ec0;  1 drivers
+v0000000003e4a000_0 .net "or0_out", 0 0, L_0000000004174b80;  1 drivers
+S_0000000002899d50 .scope module, "sky130_fd_sc_hd__o21ai_0" "sky130_fd_sc_hd__o21ai_0" 4 89973;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003dab258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e483e0_0 .net "A1", 0 0, o0000000003dab258;  0 drivers
+o0000000003dab288 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e49740_0 .net "A2", 0 0, o0000000003dab288;  0 drivers
+o0000000003dab2b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e48480_0 .net "B1", 0 0, o0000000003dab2b8;  0 drivers
+L_00000000040eefc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e485c0_0 .net8 "VGND", 0 0, L_00000000040eefc0;  1 drivers, strength-aware
+L_00000000040ee150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48b60_0 .net8 "VNB", 0 0, L_00000000040ee150;  1 drivers, strength-aware
+L_00000000040ee700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e497e0_0 .net8 "VPB", 0 0, L_00000000040ee700;  1 drivers, strength-aware
+L_00000000040ee380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a0a0_0 .net8 "VPWR", 0 0, L_00000000040ee380;  1 drivers, strength-aware
+v0000000003e48d40_0 .net "Y", 0 0, L_0000000004176780;  1 drivers
+S_0000000003d03930 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89991, 4 89511 1, S_0000000002899d50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004176860 .functor OR 1, o0000000003dab288, o0000000003dab258, C4<0>, C4<0>;
+L_0000000004175c90 .functor NAND 1, o0000000003dab2b8, L_0000000004176860, C4<1>, C4<1>;
+L_0000000004176780 .functor BUF 1, L_0000000004175c90, C4<0>, C4<0>, C4<0>;
+v0000000003e482a0_0 .net "A1", 0 0, o0000000003dab258;  alias, 0 drivers
+v0000000003e48e80_0 .net "A2", 0 0, o0000000003dab288;  alias, 0 drivers
+v0000000003e49240_0 .net "B1", 0 0, o0000000003dab2b8;  alias, 0 drivers
+L_00000000040ee7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48520_0 .net8 "VGND", 0 0, L_00000000040ee7e0;  1 drivers, strength-aware
+L_00000000040ef1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e48340_0 .net8 "VNB", 0 0, L_00000000040ef1f0;  1 drivers, strength-aware
+L_00000000040ef260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48980_0 .net8 "VPB", 0 0, L_00000000040ef260;  1 drivers, strength-aware
+L_00000000040ee8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e48a20_0 .net8 "VPWR", 0 0, L_00000000040ee8c0;  1 drivers, strength-aware
+v0000000003e47c60_0 .net "Y", 0 0, L_0000000004176780;  alias, 1 drivers
+v0000000003e48ca0_0 .net "nand0_out_Y", 0 0, L_0000000004175c90;  1 drivers
+v0000000003e49e20_0 .net "or0_out", 0 0, L_0000000004176860;  1 drivers
+S_000000000289b3d0 .scope module, "sky130_fd_sc_hd__o21ai_1" "sky130_fd_sc_hd__o21ai_1" 4 89745;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003dab678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ba40_0 .net "A1", 0 0, o0000000003dab678;  0 drivers
+o0000000003dab6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4c760_0 .net "A2", 0 0, o0000000003dab6a8;  0 drivers
+o0000000003dab6d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4b2c0_0 .net "B1", 0 0, o0000000003dab6d8;  0 drivers
+L_00000000040ef2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c4e0_0 .net8 "VGND", 0 0, L_00000000040ef2d0;  1 drivers, strength-aware
+L_00000000040ee930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a5a0_0 .net8 "VNB", 0 0, L_00000000040ee930;  1 drivers, strength-aware
+L_00000000040ef570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a460_0 .net8 "VPB", 0 0, L_00000000040ef570;  1 drivers, strength-aware
+L_00000000040ef650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4bb80_0 .net8 "VPWR", 0 0, L_00000000040ef650;  1 drivers, strength-aware
+v0000000003e4ad20_0 .net "Y", 0 0, L_0000000004175fa0;  1 drivers
+S_0000000003d05430 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89763, 4 89511 1, S_000000000289b3d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_0000000004175d00 .functor OR 1, o0000000003dab6a8, o0000000003dab678, C4<0>, C4<0>;
+L_0000000004174d40 .functor NAND 1, o0000000003dab6d8, L_0000000004175d00, C4<1>, C4<1>;
+L_0000000004175fa0 .functor BUF 1, L_0000000004174d40, C4<0>, C4<0>, C4<0>;
+v0000000003e48fc0_0 .net "A1", 0 0, o0000000003dab678;  alias, 0 drivers
+v0000000003e49100_0 .net "A2", 0 0, o0000000003dab6a8;  alias, 0 drivers
+v0000000003e491a0_0 .net "B1", 0 0, o0000000003dab6d8;  alias, 0 drivers
+L_00000000040ef810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e47940_0 .net8 "VGND", 0 0, L_00000000040ef810;  1 drivers, strength-aware
+L_00000000040ef880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e479e0_0 .net8 "VNB", 0 0, L_00000000040ef880;  1 drivers, strength-aware
+L_00000000040edcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e47a80_0 .net8 "VPB", 0 0, L_00000000040edcf0;  1 drivers, strength-aware
+L_00000000040edd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e47b20_0 .net8 "VPWR", 0 0, L_00000000040edd60;  1 drivers, strength-aware
+v0000000003e4bcc0_0 .net "Y", 0 0, L_0000000004175fa0;  alias, 1 drivers
+v0000000003e4c8a0_0 .net "nand0_out_Y", 0 0, L_0000000004174d40;  1 drivers
+v0000000003e4ac80_0 .net "or0_out", 0 0, L_0000000004175d00;  1 drivers
+S_0000000002898250 .scope module, "sky130_fd_sc_hd__o21ai_4" "sky130_fd_sc_hd__o21ai_4" 4 89859;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+o0000000003daba98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4bc20_0 .net "A1", 0 0, o0000000003daba98;  0 drivers
+o0000000003dabac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4b9a0_0 .net "A2", 0 0, o0000000003dabac8;  0 drivers
+o0000000003dabaf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4bfe0_0 .net "B1", 0 0, o0000000003dabaf8;  0 drivers
+L_00000000040eddd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4be00_0 .net8 "VGND", 0 0, L_00000000040eddd0;  1 drivers, strength-aware
+L_00000000040ee3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4afa0_0 .net8 "VNB", 0 0, L_00000000040ee3f0;  1 drivers, strength-aware
+L_00000000040ee460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b720_0 .net8 "VPB", 0 0, L_00000000040ee460;  1 drivers, strength-aware
+L_00000000040f0fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c620_0 .net8 "VPWR", 0 0, L_00000000040f0fb0;  1 drivers, strength-aware
+v0000000003e4af00_0 .net "Y", 0 0, L_0000000004174f00;  1 drivers
+S_0000000003d01b30 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89877, 4 89511 1, S_0000000002898250;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+L_00000000041768d0 .functor OR 1, o0000000003dabac8, o0000000003daba98, C4<0>, C4<0>;
+L_00000000041759f0 .functor NAND 1, o0000000003dabaf8, L_00000000041768d0, C4<1>, C4<1>;
+L_0000000004174f00 .functor BUF 1, L_00000000041759f0, C4<0>, C4<0>, C4<0>;
+v0000000003e4a500_0 .net "A1", 0 0, o0000000003daba98;  alias, 0 drivers
+v0000000003e4c080_0 .net "A2", 0 0, o0000000003dabac8;  alias, 0 drivers
+v0000000003e4bae0_0 .net "B1", 0 0, o0000000003dabaf8;  alias, 0 drivers
+L_00000000040f0a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c580_0 .net8 "VGND", 0 0, L_00000000040f0a00;  1 drivers, strength-aware
+L_00000000040f0370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a6e0_0 .net8 "VNB", 0 0, L_00000000040f0370;  1 drivers, strength-aware
+L_00000000040efdc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c800_0 .net8 "VPB", 0 0, L_00000000040efdc0;  1 drivers, strength-aware
+L_00000000040f1170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a640_0 .net8 "VPWR", 0 0, L_00000000040f1170;  1 drivers, strength-aware
+v0000000003e4b0e0_0 .net "Y", 0 0, L_0000000004174f00;  alias, 1 drivers
+v0000000003e4adc0_0 .net "nand0_out_Y", 0 0, L_00000000041759f0;  1 drivers
+v0000000003e4a780_0 .net "or0_out", 0 0, L_00000000041768d0;  1 drivers
+S_0000000002898cd0 .scope module, "sky130_fd_sc_hd__o21ba_1" "sky130_fd_sc_hd__o21ba_1" 4 31350;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003dabeb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4aaa0_0 .net "A1", 0 0, o0000000003dabeb8;  0 drivers
+o0000000003dabee8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ab40_0 .net "A2", 0 0, o0000000003dabee8;  0 drivers
+o0000000003dabf18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4a320_0 .net "B1_N", 0 0, o0000000003dabf18;  0 drivers
+L_00000000040efc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b360_0 .net8 "VGND", 0 0, L_00000000040efc00;  1 drivers, strength-aware
+L_00000000040f0d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4abe0_0 .net8 "VNB", 0 0, L_00000000040f0d80;  1 drivers, strength-aware
+L_00000000040f0140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b040_0 .net8 "VPB", 0 0, L_00000000040f0140;  1 drivers, strength-aware
+L_00000000040ef960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c300_0 .net8 "VPWR", 0 0, L_00000000040ef960;  1 drivers, strength-aware
+v0000000003e4a1e0_0 .net "X", 0 0, L_0000000004174db0;  1 drivers
+S_0000000003d03c30 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31368, 4 31229 1, S_0000000002898cd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_0000000004174e20 .functor NOR 1, o0000000003dabeb8, o0000000003dabee8, C4<0>, C4<0>;
+L_00000000041757c0 .functor NOR 1, o0000000003dabf18, L_0000000004174e20, C4<0>, C4<0>;
+L_0000000004174db0 .functor BUF 1, L_00000000041757c0, C4<0>, C4<0>, C4<0>;
+v0000000003e4ae60_0 .net "A1", 0 0, o0000000003dabeb8;  alias, 0 drivers
+v0000000003e4a3c0_0 .net "A2", 0 0, o0000000003dabee8;  alias, 0 drivers
+v0000000003e4a820_0 .net "B1_N", 0 0, o0000000003dabf18;  alias, 0 drivers
+L_00000000040f11e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a8c0_0 .net8 "VGND", 0 0, L_00000000040f11e0;  1 drivers, strength-aware
+L_00000000040f0e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4a140_0 .net8 "VNB", 0 0, L_00000000040f0e60;  1 drivers, strength-aware
+L_00000000040f05a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4bd60_0 .net8 "VPB", 0 0, L_00000000040f05a0;  1 drivers, strength-aware
+L_00000000040efa40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c120_0 .net8 "VPWR", 0 0, L_00000000040efa40;  1 drivers, strength-aware
+v0000000003e4a960_0 .net "X", 0 0, L_0000000004174db0;  alias, 1 drivers
+v0000000003e4aa00_0 .net "nor0_out", 0 0, L_0000000004174e20;  1 drivers
+v0000000003e4c6c0_0 .net "nor1_out_X", 0 0, L_00000000041757c0;  1 drivers
+S_0000000002898850 .scope module, "sky130_fd_sc_hd__o21ba_2" "sky130_fd_sc_hd__o21ba_2" 4 31465;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003dac2d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4c260_0 .net "A1", 0 0, o0000000003dac2d8;  0 drivers
+o0000000003dac308 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4b680_0 .net "A2", 0 0, o0000000003dac308;  0 drivers
+o0000000003dac338 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4b7c0_0 .net "B1_N", 0 0, o0000000003dac338;  0 drivers
+L_00000000040f1020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b860_0 .net8 "VGND", 0 0, L_00000000040f1020;  1 drivers, strength-aware
+L_00000000040f0290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b900_0 .net8 "VNB", 0 0, L_00000000040f0290;  1 drivers, strength-aware
+L_00000000040f0450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c3a0_0 .net8 "VPB", 0 0, L_00000000040f0450;  1 drivers, strength-aware
+L_00000000040f06f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4c440_0 .net8 "VPWR", 0 0, L_00000000040f06f0;  1 drivers, strength-aware
+v0000000003e4cda0_0 .net "X", 0 0, L_0000000004175b40;  1 drivers
+S_0000000003d03db0 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31483, 4 31229 1, S_0000000002898850;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_00000000041752f0 .functor NOR 1, o0000000003dac2d8, o0000000003dac308, C4<0>, C4<0>;
+L_0000000004175830 .functor NOR 1, o0000000003dac338, L_00000000041752f0, C4<0>, C4<0>;
+L_0000000004175b40 .functor BUF 1, L_0000000004175830, C4<0>, C4<0>, C4<0>;
+v0000000003e4b180_0 .net "A1", 0 0, o0000000003dac2d8;  alias, 0 drivers
+v0000000003e4a280_0 .net "A2", 0 0, o0000000003dac308;  alias, 0 drivers
+v0000000003e4c1c0_0 .net "B1_N", 0 0, o0000000003dac338;  alias, 0 drivers
+L_00000000040f0ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b220_0 .net8 "VGND", 0 0, L_00000000040f0ca0;  1 drivers, strength-aware
+L_00000000040f12c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4bea0_0 .net8 "VNB", 0 0, L_00000000040f12c0;  1 drivers, strength-aware
+L_00000000040efea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b400_0 .net8 "VPB", 0 0, L_00000000040efea0;  1 drivers, strength-aware
+L_00000000040f0840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4b4a0_0 .net8 "VPWR", 0 0, L_00000000040f0840;  1 drivers, strength-aware
+v0000000003e4b540_0 .net "X", 0 0, L_0000000004175b40;  alias, 1 drivers
+v0000000003e4b5e0_0 .net "nor0_out", 0 0, L_00000000041752f0;  1 drivers
+v0000000003e4bf40_0 .net "nor1_out_X", 0 0, L_0000000004175830;  1 drivers
+S_00000000028989d0 .scope module, "sky130_fd_sc_hd__o21ba_4" "sky130_fd_sc_hd__o21ba_4" 4 31580;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003dac6f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ce40_0 .net "A1", 0 0, o0000000003dac6f8;  0 drivers
+o0000000003dac728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ea60_0 .net "A2", 0 0, o0000000003dac728;  0 drivers
+o0000000003dac758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ee20_0 .net "B1_N", 0 0, o0000000003dac758;  0 drivers
+L_00000000040f01b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4eb00_0 .net8 "VGND", 0 0, L_00000000040f01b0;  1 drivers, strength-aware
+L_00000000040f13a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4ece0_0 .net8 "VNB", 0 0, L_00000000040f13a0;  1 drivers, strength-aware
+L_00000000040f1480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4cee0_0 .net8 "VPB", 0 0, L_00000000040f1480;  1 drivers, strength-aware
+L_00000000040f0530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4eec0_0 .net8 "VPWR", 0 0, L_00000000040f0530;  1 drivers, strength-aware
+v0000000003e4ef60_0 .net "X", 0 0, L_0000000004174e90;  1 drivers
+S_0000000003d02d30 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31598, 4 31229 1, S_00000000028989d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_00000000041764e0 .functor NOR 1, o0000000003dac6f8, o0000000003dac728, C4<0>, C4<0>;
+L_00000000041758a0 .functor NOR 1, o0000000003dac758, L_00000000041764e0, C4<0>, C4<0>;
+L_0000000004174e90 .functor BUF 1, L_00000000041758a0, C4<0>, C4<0>, C4<0>;
+v0000000003e4d980_0 .net "A1", 0 0, o0000000003dac6f8;  alias, 0 drivers
+v0000000003e4d3e0_0 .net "A2", 0 0, o0000000003dac728;  alias, 0 drivers
+v0000000003e4d840_0 .net "B1_N", 0 0, o0000000003dac758;  alias, 0 drivers
+L_00000000040f0a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4d160_0 .net8 "VGND", 0 0, L_00000000040f0a70;  1 drivers, strength-aware
+L_00000000040f00d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e1a0_0 .net8 "VNB", 0 0, L_00000000040f00d0;  1 drivers, strength-aware
+L_00000000040ef8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e7e0_0 .net8 "VPB", 0 0, L_00000000040ef8f0;  1 drivers, strength-aware
+L_00000000040ef9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4d5c0_0 .net8 "VPWR", 0 0, L_00000000040ef9d0;  1 drivers, strength-aware
+v0000000003e4e740_0 .net "X", 0 0, L_0000000004174e90;  alias, 1 drivers
+v0000000003e4e560_0 .net "nor0_out", 0 0, L_00000000041764e0;  1 drivers
+v0000000003e4d340_0 .net "nor1_out_X", 0 0, L_00000000041758a0;  1 drivers
+S_0000000002898e50 .scope module, "sky130_fd_sc_hd__o21bai_1" "sky130_fd_sc_hd__o21bai_1" 4 61463;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003dacb18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4c940_0 .net "A1", 0 0, o0000000003dacb18;  0 drivers
+o0000000003dacb48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4cf80_0 .net "A2", 0 0, o0000000003dacb48;  0 drivers
+o0000000003dacb78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4d520_0 .net "B1_N", 0 0, o0000000003dacb78;  0 drivers
+L_00000000040f03e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4d8e0_0 .net8 "VGND", 0 0, L_00000000040f03e0;  1 drivers, strength-aware
+L_00000000040f0300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4da20_0 .net8 "VNB", 0 0, L_00000000040f0300;  1 drivers, strength-aware
+L_00000000040f0f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4de80_0 .net8 "VPB", 0 0, L_00000000040f0f40;  1 drivers, strength-aware
+L_00000000040f0220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4dde0_0 .net8 "VPWR", 0 0, L_00000000040f0220;  1 drivers, strength-aware
+v0000000003e4c9e0_0 .net "Y", 0 0, L_0000000004175050;  1 drivers
+S_0000000003d040b0 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 61481, 4 61340 1, S_0000000002898e50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_0000000004174f70 .functor NOT 1, o0000000003dacb78, C4<0>, C4<0>, C4<0>;
+L_0000000004175980 .functor OR 1, o0000000003dacb48, o0000000003dacb18, C4<0>, C4<0>;
+L_0000000004175bb0 .functor NAND 1, L_0000000004174f70, L_0000000004175980, C4<1>, C4<1>;
+L_0000000004175050 .functor BUF 1, L_0000000004175bb0, C4<0>, C4<0>, C4<0>;
+v0000000003e4f000_0 .net "A1", 0 0, o0000000003dacb18;  alias, 0 drivers
+v0000000003e4cc60_0 .net "A2", 0 0, o0000000003dacb48;  alias, 0 drivers
+v0000000003e4eba0_0 .net "B1_N", 0 0, o0000000003dacb78;  alias, 0 drivers
+L_00000000040f0b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4ca80_0 .net8 "VGND", 0 0, L_00000000040f0b50;  1 drivers, strength-aware
+L_00000000040f0bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e600_0 .net8 "VNB", 0 0, L_00000000040f0bc0;  1 drivers, strength-aware
+L_00000000040f04c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e6a0_0 .net8 "VPB", 0 0, L_00000000040f04c0;  1 drivers, strength-aware
+L_00000000040f0610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4df20_0 .net8 "VPWR", 0 0, L_00000000040f0610;  1 drivers, strength-aware
+v0000000003e4dd40_0 .net "Y", 0 0, L_0000000004175050;  alias, 1 drivers
+v0000000003e4d660_0 .net "b", 0 0, L_0000000004174f70;  1 drivers
+v0000000003e4dca0_0 .net "nand0_out_Y", 0 0, L_0000000004175bb0;  1 drivers
+v0000000003e4e880_0 .net "or0_out", 0 0, L_0000000004175980;  1 drivers
+S_0000000002898fd0 .scope module, "sky130_fd_sc_hd__o21bai_4" "sky130_fd_sc_hd__o21bai_4" 4 61007;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+o0000000003dacf68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4d020_0 .net "A1", 0 0, o0000000003dacf68;  0 drivers
+o0000000003dacf98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4ed80_0 .net "A2", 0 0, o0000000003dacf98;  0 drivers
+o0000000003dacfc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4d700_0 .net "B1_N", 0 0, o0000000003dacfc8;  0 drivers
+L_00000000040f0ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e420_0 .net8 "VGND", 0 0, L_00000000040f0ed0;  1 drivers, strength-aware
+L_00000000040f1090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4f0a0_0 .net8 "VNB", 0 0, L_00000000040f1090;  1 drivers, strength-aware
+L_00000000040f1250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4d7a0_0 .net8 "VPB", 0 0, L_00000000040f1250;  1 drivers, strength-aware
+L_00000000040f0ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4cb20_0 .net8 "VPWR", 0 0, L_00000000040f0ae0;  1 drivers, strength-aware
+v0000000003e4d2a0_0 .net "Y", 0 0, L_0000000004176470;  1 drivers
+S_0000000003d04530 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 61025, 4 61340 1, S_0000000002898fd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1_N"
+L_00000000041766a0 .functor NOT 1, o0000000003dacfc8, C4<0>, C4<0>, C4<0>;
+L_00000000041750c0 .functor OR 1, o0000000003dacf98, o0000000003dacf68, C4<0>, C4<0>;
+L_00000000041767f0 .functor NAND 1, L_00000000041766a0, L_00000000041750c0, C4<1>, C4<1>;
+L_0000000004176470 .functor BUF 1, L_00000000041767f0, C4<0>, C4<0>, C4<0>;
+v0000000003e4d480_0 .net "A1", 0 0, o0000000003dacf68;  alias, 0 drivers
+v0000000003e4dac0_0 .net "A2", 0 0, o0000000003dacf98;  alias, 0 drivers
+v0000000003e4d200_0 .net "B1_N", 0 0, o0000000003dacfc8;  alias, 0 drivers
+L_00000000040f1100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4dfc0_0 .net8 "VGND", 0 0, L_00000000040f1100;  1 drivers, strength-aware
+L_00000000040f1330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e920_0 .net8 "VNB", 0 0, L_00000000040f1330;  1 drivers, strength-aware
+L_00000000040f1410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e9c0_0 .net8 "VPB", 0 0, L_00000000040f1410;  1 drivers, strength-aware
+L_00000000040efab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4cbc0_0 .net8 "VPWR", 0 0, L_00000000040efab0;  1 drivers, strength-aware
+v0000000003e4e4c0_0 .net "Y", 0 0, L_0000000004176470;  alias, 1 drivers
+v0000000003e4e380_0 .net "b", 0 0, L_00000000041766a0;  1 drivers
+v0000000003e4e240_0 .net "nand0_out_Y", 0 0, L_00000000041767f0;  1 drivers
+v0000000003e4ec40_0 .net "or0_out", 0 0, L_00000000041750c0;  1 drivers
+S_0000000002899150 .scope module, "sky130_fd_sc_hd__o221a_1" "sky130_fd_sc_hd__o221a_1" 4 74583;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e833c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e509a0_0 .net "A1", 0 0, o0000000003e833c8;  0 drivers
+o0000000003e833f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e50ae0_0 .net "A2", 0 0, o0000000003e833f8;  0 drivers
+o0000000003e83428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e51080_0 .net "B1", 0 0, o0000000003e83428;  0 drivers
+o0000000003e83458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e51760_0 .net "B2", 0 0, o0000000003e83458;  0 drivers
+o0000000003e83488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4fe60_0 .net "C1", 0 0, o0000000003e83488;  0 drivers
+L_00000000040efb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e514e0_0 .net8 "VGND", 0 0, L_00000000040efb20;  1 drivers, strength-aware
+L_00000000040f0680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51120_0 .net8 "VNB", 0 0, L_00000000040f0680;  1 drivers, strength-aware
+L_00000000040efb90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4f140_0 .net8 "VPB", 0 0, L_00000000040efb90;  1 drivers, strength-aware
+L_00000000040f0760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e50e00_0 .net8 "VPWR", 0 0, L_00000000040f0760;  1 drivers, strength-aware
+v0000000003e4fdc0_0 .net "X", 0 0, L_0000000004175a60;  1 drivers
+S_0000000003d05a30 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 74605, 4 74929 1, S_0000000002899150;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041760f0 .functor OR 1, o0000000003e83458, o0000000003e83428, C4<0>, C4<0>;
+L_0000000004175f30 .functor OR 1, o0000000003e833f8, o0000000003e833c8, C4<0>, C4<0>;
+L_0000000004174fe0 .functor AND 1, L_00000000041760f0, L_0000000004175f30, o0000000003e83488, C4<1>;
+L_0000000004175a60 .functor BUF 1, L_0000000004174fe0, C4<0>, C4<0>, C4<0>;
+v0000000003e4db60_0 .net "A1", 0 0, o0000000003e833c8;  alias, 0 drivers
+v0000000003e4e060_0 .net "A2", 0 0, o0000000003e833f8;  alias, 0 drivers
+v0000000003e4d0c0_0 .net "B1", 0 0, o0000000003e83428;  alias, 0 drivers
+v0000000003e4cd00_0 .net "B2", 0 0, o0000000003e83458;  alias, 0 drivers
+v0000000003e4dc00_0 .net "C1", 0 0, o0000000003e83488;  alias, 0 drivers
+L_00000000040f07d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e100_0 .net8 "VGND", 0 0, L_00000000040f07d0;  1 drivers, strength-aware
+L_00000000040f0c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4e2e0_0 .net8 "VNB", 0 0, L_00000000040f0c30;  1 drivers, strength-aware
+L_00000000040efe30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4f500_0 .net8 "VPB", 0 0, L_00000000040efe30;  1 drivers, strength-aware
+L_00000000040efc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4f8c0_0 .net8 "VPWR", 0 0, L_00000000040efc70;  1 drivers, strength-aware
+v0000000003e4f5a0_0 .net "X", 0 0, L_0000000004175a60;  alias, 1 drivers
+v0000000003e50ea0_0 .net "and0_out_X", 0 0, L_0000000004174fe0;  1 drivers
+v0000000003e502c0_0 .net "or0_out", 0 0, L_00000000041760f0;  1 drivers
+v0000000003e4f820_0 .net "or1_out", 0 0, L_0000000004175f30;  1 drivers
+S_00000000028992d0 .scope module, "sky130_fd_sc_hd__o221a_4" "sky130_fd_sc_hd__o221a_4" 4 75061;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e83938 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4f320_0 .net "A1", 0 0, o0000000003e83938;  0 drivers
+o0000000003e83968 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4f780_0 .net "A2", 0 0, o0000000003e83968;  0 drivers
+o0000000003e83998 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e50d60_0 .net "B1", 0 0, o0000000003e83998;  0 drivers
+o0000000003e839c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e50fe0_0 .net "B2", 0 0, o0000000003e839c8;  0 drivers
+o0000000003e839f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e50040_0 .net "C1", 0 0, o0000000003e839f8;  0 drivers
+L_00000000040efce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e500e0_0 .net8 "VGND", 0 0, L_00000000040efce0;  1 drivers, strength-aware
+L_00000000040efd50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51620_0 .net8 "VNB", 0 0, L_00000000040efd50;  1 drivers, strength-aware
+L_00000000040f0d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4fb40_0 .net8 "VPB", 0 0, L_00000000040f0d10;  1 drivers, strength-aware
+L_00000000040f08b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e511c0_0 .net8 "VPWR", 0 0, L_00000000040f08b0;  1 drivers, strength-aware
+v0000000003e50180_0 .net "X", 0 0, L_0000000004175de0;  1 drivers
+S_0000000003d06ab0 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75083, 4 74929 1, S_00000000028992d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004175210 .functor OR 1, o0000000003e839c8, o0000000003e83998, C4<0>, C4<0>;
+L_0000000004175d70 .functor OR 1, o0000000003e83968, o0000000003e83938, C4<0>, C4<0>;
+L_0000000004175750 .functor AND 1, L_0000000004175210, L_0000000004175d70, o0000000003e839f8, C4<1>;
+L_0000000004175de0 .functor BUF 1, L_0000000004175750, C4<0>, C4<0>, C4<0>;
+v0000000003e50f40_0 .net "A1", 0 0, o0000000003e83938;  alias, 0 drivers
+v0000000003e50b80_0 .net "A2", 0 0, o0000000003e83968;  alias, 0 drivers
+v0000000003e4f1e0_0 .net "B1", 0 0, o0000000003e83998;  alias, 0 drivers
+v0000000003e4f640_0 .net "B2", 0 0, o0000000003e839c8;  alias, 0 drivers
+v0000000003e50a40_0 .net "C1", 0 0, o0000000003e839f8;  alias, 0 drivers
+L_00000000040eff10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e4ff00_0 .net8 "VGND", 0 0, L_00000000040eff10;  1 drivers, strength-aware
+L_00000000040f0920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e50c20_0 .net8 "VNB", 0 0, L_00000000040f0920;  1 drivers, strength-aware
+L_00000000040eff80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e4ffa0_0 .net8 "VPB", 0 0, L_00000000040eff80;  1 drivers, strength-aware
+L_00000000040efff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e50680_0 .net8 "VPWR", 0 0, L_00000000040efff0;  1 drivers, strength-aware
+v0000000003e4f460_0 .net "X", 0 0, L_0000000004175de0;  alias, 1 drivers
+v0000000003e50cc0_0 .net "and0_out_X", 0 0, L_0000000004175750;  1 drivers
+v0000000003e4f6e0_0 .net "or0_out", 0 0, L_0000000004175210;  1 drivers
+v0000000003e4f960_0 .net "or1_out", 0 0, L_0000000004175d70;  1 drivers
+S_000000000289a050 .scope module, "sky130_fd_sc_hd__o221ai_1" "sky130_fd_sc_hd__o221ai_1" 4 23010;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e83ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e50540_0 .net "A1", 0 0, o0000000003e83ea8;  0 drivers
+o0000000003e83ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4f3c0_0 .net "A2", 0 0, o0000000003e83ed8;  0 drivers
+o0000000003e83f08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4fc80_0 .net "B1", 0 0, o0000000003e83f08;  0 drivers
+o0000000003e83f38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e504a0_0 .net "B2", 0 0, o0000000003e83f38;  0 drivers
+o0000000003e83f68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e4fd20_0 .net "C1", 0 0, o0000000003e83f68;  0 drivers
+L_00000000040f0060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e50220_0 .net8 "VGND", 0 0, L_00000000040f0060;  1 drivers, strength-aware
+L_00000000040f0990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e50400_0 .net8 "VNB", 0 0, L_00000000040f0990;  1 drivers, strength-aware
+L_00000000040f0df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e50720_0 .net8 "VPB", 0 0, L_00000000040f0df0;  1 drivers, strength-aware
+L_00000000040f1f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e505e0_0 .net8 "VPWR", 0 0, L_00000000040f1f00;  1 drivers, strength-aware
+v0000000003e507c0_0 .net "Y", 0 0, L_0000000004176160;  1 drivers
+S_0000000003d04230 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23032, 4 23482 1, S_000000000289a050;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004175130 .functor OR 1, o0000000003e83f38, o0000000003e83f08, C4<0>, C4<0>;
+L_00000000041761d0 .functor OR 1, o0000000003e83ed8, o0000000003e83ea8, C4<0>, C4<0>;
+L_0000000004175910 .functor NAND 1, L_00000000041761d0, L_0000000004175130, o0000000003e83f68, C4<1>;
+L_0000000004176160 .functor BUF 1, L_0000000004175910, C4<0>, C4<0>, C4<0>;
+v0000000003e4fa00_0 .net "A1", 0 0, o0000000003e83ea8;  alias, 0 drivers
+v0000000003e51260_0 .net "A2", 0 0, o0000000003e83ed8;  alias, 0 drivers
+v0000000003e4f280_0 .net "B1", 0 0, o0000000003e83f08;  alias, 0 drivers
+v0000000003e51300_0 .net "B2", 0 0, o0000000003e83f38;  alias, 0 drivers
+v0000000003e513a0_0 .net "C1", 0 0, o0000000003e83f68;  alias, 0 drivers
+L_00000000040f1f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51440_0 .net8 "VGND", 0 0, L_00000000040f1f70;  1 drivers, strength-aware
+L_00000000040f2ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51580_0 .net8 "VNB", 0 0, L_00000000040f2ec0;  1 drivers, strength-aware
+L_00000000040f2f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e516c0_0 .net8 "VPB", 0 0, L_00000000040f2f30;  1 drivers, strength-aware
+L_00000000040f1bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e50360_0 .net8 "VPWR", 0 0, L_00000000040f1bf0;  1 drivers, strength-aware
+v0000000003e51800_0 .net "Y", 0 0, L_0000000004176160;  alias, 1 drivers
+v0000000003e4faa0_0 .net "nand0_out_Y", 0 0, L_0000000004175910;  1 drivers
+v0000000003e518a0_0 .net "or0_out", 0 0, L_0000000004175130;  1 drivers
+v0000000003e4fbe0_0 .net "or1_out", 0 0, L_00000000041761d0;  1 drivers
+S_0000000002899450 .scope module, "sky130_fd_sc_hd__o221ai_4" "sky130_fd_sc_hd__o221ai_4" 4 23136;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e84418 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e52160_0 .net "A1", 0 0, o0000000003e84418;  0 drivers
+o0000000003e84448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e522a0_0 .net "A2", 0 0, o0000000003e84448;  0 drivers
+o0000000003e84478 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e53f60_0 .net "B1", 0 0, o0000000003e84478;  0 drivers
+o0000000003e844a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e531a0_0 .net "B2", 0 0, o0000000003e844a8;  0 drivers
+o0000000003e844d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e52700_0 .net "C1", 0 0, o0000000003e844d8;  0 drivers
+L_00000000040f2590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e52c00_0 .net8 "VGND", 0 0, L_00000000040f2590;  1 drivers, strength-aware
+L_00000000040f1fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e53ec0_0 .net8 "VNB", 0 0, L_00000000040f1fe0;  1 drivers, strength-aware
+L_00000000040f1e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54000_0 .net8 "VPB", 0 0, L_00000000040f1e20;  1 drivers, strength-aware
+L_00000000040f16b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e52660_0 .net8 "VPWR", 0 0, L_00000000040f16b0;  1 drivers, strength-aware
+v0000000003e53ce0_0 .net "Y", 0 0, L_0000000004175520;  1 drivers
+S_0000000003d010b0 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23158, 4 23482 1, S_0000000002899450;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041762b0 .functor OR 1, o0000000003e844a8, o0000000003e84478, C4<0>, C4<0>;
+L_0000000004175ad0 .functor OR 1, o0000000003e84448, o0000000003e84418, C4<0>, C4<0>;
+L_00000000041751a0 .functor NAND 1, L_0000000004175ad0, L_00000000041762b0, o0000000003e844d8, C4<1>;
+L_0000000004175520 .functor BUF 1, L_00000000041751a0, C4<0>, C4<0>, C4<0>;
+v0000000003e50860_0 .net "A1", 0 0, o0000000003e84418;  alias, 0 drivers
+v0000000003e50900_0 .net "A2", 0 0, o0000000003e84448;  alias, 0 drivers
+v0000000003e51e40_0 .net "B1", 0 0, o0000000003e84478;  alias, 0 drivers
+v0000000003e52840_0 .net "B2", 0 0, o0000000003e844a8;  alias, 0 drivers
+v0000000003e53240_0 .net "C1", 0 0, o0000000003e844d8;  alias, 0 drivers
+L_00000000040f2a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e537e0_0 .net8 "VGND", 0 0, L_00000000040f2a60;  1 drivers, strength-aware
+L_00000000040f14f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e52020_0 .net8 "VNB", 0 0, L_00000000040f14f0;  1 drivers, strength-aware
+L_00000000040f22f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e536a0_0 .net8 "VPB", 0 0, L_00000000040f22f0;  1 drivers, strength-aware
+L_00000000040f1aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e53d80_0 .net8 "VPWR", 0 0, L_00000000040f1aa0;  1 drivers, strength-aware
+v0000000003e52480_0 .net "Y", 0 0, L_0000000004175520;  alias, 1 drivers
+v0000000003e52200_0 .net "nand0_out_Y", 0 0, L_00000000041751a0;  1 drivers
+v0000000003e51d00_0 .net "or0_out", 0 0, L_00000000041762b0;  1 drivers
+v0000000003e520c0_0 .net "or1_out", 0 0, L_0000000004175ad0;  1 drivers
+S_0000000002897f50 .scope module, "sky130_fd_sc_hd__o22a_1" "sky130_fd_sc_hd__o22a_1" 4 50886;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e84988 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e51940_0 .net "A1", 0 0, o0000000003e84988;  0 drivers
+o0000000003e849b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e52340_0 .net "A2", 0 0, o0000000003e849b8;  0 drivers
+o0000000003e849e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e53880_0 .net "B1", 0 0, o0000000003e849e8;  0 drivers
+o0000000003e84a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e519e0_0 .net "B2", 0 0, o0000000003e84a18;  0 drivers
+L_00000000040f2440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51a80_0 .net8 "VGND", 0 0, L_00000000040f2440;  1 drivers, strength-aware
+L_00000000040f19c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51b20_0 .net8 "VNB", 0 0, L_00000000040f19c0;  1 drivers, strength-aware
+L_00000000040f20c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e523e0_0 .net8 "VPB", 0 0, L_00000000040f20c0;  1 drivers, strength-aware
+L_00000000040f1790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e53420_0 .net8 "VPWR", 0 0, L_00000000040f1790;  1 drivers, strength-aware
+v0000000003e52de0_0 .net "X", 0 0, L_0000000004176010;  1 drivers
+S_0000000003d046b0 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50906, 4 51223 1, S_0000000002897f50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004175c20 .functor OR 1, o0000000003e849b8, o0000000003e84988, C4<0>, C4<0>;
+L_0000000004175e50 .functor OR 1, o0000000003e84a18, o0000000003e849e8, C4<0>, C4<0>;
+L_0000000004175670 .functor AND 1, L_0000000004175c20, L_0000000004175e50, C4<1>, C4<1>;
+L_0000000004176010 .functor BUF 1, L_0000000004175670, C4<0>, C4<0>, C4<0>;
+v0000000003e540a0_0 .net "A1", 0 0, o0000000003e84988;  alias, 0 drivers
+v0000000003e525c0_0 .net "A2", 0 0, o0000000003e849b8;  alias, 0 drivers
+v0000000003e52ca0_0 .net "B1", 0 0, o0000000003e849e8;  alias, 0 drivers
+v0000000003e53600_0 .net "B2", 0 0, o0000000003e84a18;  alias, 0 drivers
+L_00000000040f2360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e53e20_0 .net8 "VGND", 0 0, L_00000000040f2360;  1 drivers, strength-aware
+L_00000000040f1e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e527a0_0 .net8 "VNB", 0 0, L_00000000040f1e90;  1 drivers, strength-aware
+L_00000000040f2980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e539c0_0 .net8 "VPB", 0 0, L_00000000040f2980;  1 drivers, strength-aware
+L_00000000040f24b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e51da0_0 .net8 "VPWR", 0 0, L_00000000040f24b0;  1 drivers, strength-aware
+v0000000003e532e0_0 .net "X", 0 0, L_0000000004176010;  alias, 1 drivers
+v0000000003e528e0_0 .net "and0_out_X", 0 0, L_0000000004175670;  1 drivers
+v0000000003e53380_0 .net "or0_out", 0 0, L_0000000004175c20;  1 drivers
+v0000000003e52980_0 .net "or1_out", 0 0, L_0000000004175e50;  1 drivers
+S_000000000289a1d0 .scope module, "sky130_fd_sc_hd__o22a_4" "sky130_fd_sc_hd__o22a_4" 4 50646;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e84e68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e52fc0_0 .net "A1", 0 0, o0000000003e84e68;  0 drivers
+o0000000003e84e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e53060_0 .net "A2", 0 0, o0000000003e84e98;  0 drivers
+o0000000003e84ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e53b00_0 .net "B1", 0 0, o0000000003e84ec8;  0 drivers
+o0000000003e84ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e53740_0 .net "B2", 0 0, o0000000003e84ef8;  0 drivers
+L_00000000040f2ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e53560_0 .net8 "VGND", 0 0, L_00000000040f2ad0;  1 drivers, strength-aware
+L_00000000040f2910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e53100_0 .net8 "VNB", 0 0, L_00000000040f2910;  1 drivers, strength-aware
+L_00000000040f2750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e53920_0 .net8 "VPB", 0 0, L_00000000040f2750;  1 drivers, strength-aware
+L_00000000040f2fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e53ba0_0 .net8 "VPWR", 0 0, L_00000000040f2fa0;  1 drivers, strength-aware
+v0000000003e53c40_0 .net "X", 0 0, L_0000000004175360;  1 drivers
+S_0000000003d064b0 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50666, 4 51223 1, S_000000000289a1d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004176080 .functor OR 1, o0000000003e84e98, o0000000003e84e68, C4<0>, C4<0>;
+L_00000000041756e0 .functor OR 1, o0000000003e84ef8, o0000000003e84ec8, C4<0>, C4<0>;
+L_0000000004175280 .functor AND 1, L_0000000004176080, L_00000000041756e0, C4<1>, C4<1>;
+L_0000000004175360 .functor BUF 1, L_0000000004175280, C4<0>, C4<0>, C4<0>;
+v0000000003e534c0_0 .net "A1", 0 0, o0000000003e84e68;  alias, 0 drivers
+v0000000003e51ee0_0 .net "A2", 0 0, o0000000003e84e98;  alias, 0 drivers
+v0000000003e53a60_0 .net "B1", 0 0, o0000000003e84ec8;  alias, 0 drivers
+v0000000003e51bc0_0 .net "B2", 0 0, o0000000003e84ef8;  alias, 0 drivers
+L_00000000040f2050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e52d40_0 .net8 "VGND", 0 0, L_00000000040f2050;  1 drivers, strength-aware
+L_00000000040f1db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e51c60_0 .net8 "VNB", 0 0, L_00000000040f1db0;  1 drivers, strength-aware
+L_00000000040f26e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e52520_0 .net8 "VPB", 0 0, L_00000000040f26e0;  1 drivers, strength-aware
+L_00000000040f2bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e52e80_0 .net8 "VPWR", 0 0, L_00000000040f2bb0;  1 drivers, strength-aware
+v0000000003e52a20_0 .net "X", 0 0, L_0000000004175360;  alias, 1 drivers
+v0000000003e52ac0_0 .net "and0_out_X", 0 0, L_0000000004175280;  1 drivers
+v0000000003e52f20_0 .net "or0_out", 0 0, L_0000000004176080;  1 drivers
+v0000000003e52b60_0 .net "or1_out", 0 0, L_00000000041756e0;  1 drivers
+S_0000000002899750 .scope module, "sky130_fd_sc_hd__o22ai_1" "sky130_fd_sc_hd__o22ai_1" 4 24201;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e85348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55540_0 .net "A1", 0 0, o0000000003e85348;  0 drivers
+o0000000003e85378 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e56580_0 .net "A2", 0 0, o0000000003e85378;  0 drivers
+o0000000003e853a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55e00_0 .net "B1", 0 0, o0000000003e853a8;  0 drivers
+o0000000003e853d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e546e0_0 .net "B2", 0 0, o0000000003e853d8;  0 drivers
+L_00000000040f2600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e54820_0 .net8 "VGND", 0 0, L_00000000040f2600;  1 drivers, strength-aware
+L_00000000040f2130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e54640_0 .net8 "VNB", 0 0, L_00000000040f2130;  1 drivers, strength-aware
+L_00000000040f1a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e550e0_0 .net8 "VPB", 0 0, L_00000000040f1a30;  1 drivers, strength-aware
+L_00000000040f2d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54dc0_0 .net8 "VPWR", 0 0, L_00000000040f2d70;  1 drivers, strength-aware
+v0000000003e54aa0_0 .net "Y", 0 0, L_0000000004176320;  1 drivers
+S_0000000003d04830 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 24221, 4 24074 1, S_0000000002899750;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004176240 .functor NOR 1, o0000000003e853a8, o0000000003e853d8, C4<0>, C4<0>;
+L_00000000041753d0 .functor NOR 1, o0000000003e85348, o0000000003e85378, C4<0>, C4<0>;
+L_0000000004175440 .functor OR 1, L_00000000041753d0, L_0000000004176240, C4<0>, C4<0>;
+L_0000000004176320 .functor BUF 1, L_0000000004175440, C4<0>, C4<0>, C4<0>;
+v0000000003e51f80_0 .net "A1", 0 0, o0000000003e85348;  alias, 0 drivers
+v0000000003e56620_0 .net "A2", 0 0, o0000000003e85378;  alias, 0 drivers
+v0000000003e566c0_0 .net "B1", 0 0, o0000000003e853a8;  alias, 0 drivers
+v0000000003e554a0_0 .net "B2", 0 0, o0000000003e853d8;  alias, 0 drivers
+L_00000000040f1800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e54f00_0 .net8 "VGND", 0 0, L_00000000040f1800;  1 drivers, strength-aware
+L_00000000040f29f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e54780_0 .net8 "VNB", 0 0, L_00000000040f29f0;  1 drivers, strength-aware
+L_00000000040f1d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e56800_0 .net8 "VPB", 0 0, L_00000000040f1d40;  1 drivers, strength-aware
+L_00000000040f1560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e55cc0_0 .net8 "VPWR", 0 0, L_00000000040f1560;  1 drivers, strength-aware
+v0000000003e54460_0 .net "Y", 0 0, L_0000000004176320;  alias, 1 drivers
+v0000000003e56260_0 .net "nor0_out", 0 0, L_0000000004176240;  1 drivers
+v0000000003e54a00_0 .net "nor1_out", 0 0, L_00000000041753d0;  1 drivers
+v0000000003e54c80_0 .net "or0_out_Y", 0 0, L_0000000004175440;  1 drivers
+S_000000000289b550 .scope module, "sky130_fd_sc_hd__o22ai_2" "sky130_fd_sc_hd__o22ai_2" 4 24321;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e85828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e541e0_0 .net "A1", 0 0, o0000000003e85828;  0 drivers
+o0000000003e85858 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55a40_0 .net "A2", 0 0, o0000000003e85858;  0 drivers
+o0000000003e85888 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55fe0_0 .net "B1", 0 0, o0000000003e85888;  0 drivers
+o0000000003e858b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e54500_0 .net "B2", 0 0, o0000000003e858b8;  0 drivers
+L_00000000040f2de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e54960_0 .net8 "VGND", 0 0, L_00000000040f2de0;  1 drivers, strength-aware
+L_00000000040f2b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e55c20_0 .net8 "VNB", 0 0, L_00000000040f2b40;  1 drivers, strength-aware
+L_00000000040f21a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54d20_0 .net8 "VPB", 0 0, L_00000000040f21a0;  1 drivers, strength-aware
+L_00000000040f1640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e56080_0 .net8 "VPWR", 0 0, L_00000000040f1640;  1 drivers, strength-aware
+v0000000003e552c0_0 .net "Y", 0 0, L_0000000004176390;  1 drivers
+S_0000000003d06930 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 24341, 4 24074 1, S_000000000289b550;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_00000000041754b0 .functor NOR 1, o0000000003e85888, o0000000003e858b8, C4<0>, C4<0>;
+L_0000000004175600 .functor NOR 1, o0000000003e85828, o0000000003e85858, C4<0>, C4<0>;
+L_0000000004175590 .functor OR 1, L_0000000004175600, L_00000000041754b0, C4<0>, C4<0>;
+L_0000000004176390 .functor BUF 1, L_0000000004175590, C4<0>, C4<0>, C4<0>;
+v0000000003e55ea0_0 .net "A1", 0 0, o0000000003e85828;  alias, 0 drivers
+v0000000003e55f40_0 .net "A2", 0 0, o0000000003e85858;  alias, 0 drivers
+v0000000003e545a0_0 .net "B1", 0 0, o0000000003e85888;  alias, 0 drivers
+v0000000003e561c0_0 .net "B2", 0 0, o0000000003e858b8;  alias, 0 drivers
+L_00000000040f2c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e548c0_0 .net8 "VGND", 0 0, L_00000000040f2c20;  1 drivers, strength-aware
+L_00000000040f2210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e55220_0 .net8 "VNB", 0 0, L_00000000040f2210;  1 drivers, strength-aware
+L_00000000040f2280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e55d60_0 .net8 "VPB", 0 0, L_00000000040f2280;  1 drivers, strength-aware
+L_00000000040f23d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54140_0 .net8 "VPWR", 0 0, L_00000000040f23d0;  1 drivers, strength-aware
+v0000000003e54e60_0 .net "Y", 0 0, L_0000000004176390;  alias, 1 drivers
+v0000000003e54b40_0 .net "nor0_out", 0 0, L_00000000041754b0;  1 drivers
+v0000000003e54be0_0 .net "nor1_out", 0 0, L_0000000004175600;  1 drivers
+v0000000003e543c0_0 .net "or0_out_Y", 0 0, L_0000000004175590;  1 drivers
+S_000000000289a4d0 .scope module, "sky130_fd_sc_hd__o22ai_4" "sky130_fd_sc_hd__o22ai_4" 4 23737;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e85d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55400_0 .net "A1", 0 0, o0000000003e85d08;  0 drivers
+o0000000003e85d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e56440_0 .net "A2", 0 0, o0000000003e85d38;  0 drivers
+o0000000003e85d68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e564e0_0 .net "B1", 0 0, o0000000003e85d68;  0 drivers
+o0000000003e85d98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e55680_0 .net "B2", 0 0, o0000000003e85d98;  0 drivers
+L_00000000040f28a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e55720_0 .net8 "VGND", 0 0, L_00000000040f28a0;  1 drivers, strength-aware
+L_00000000040f3010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e557c0_0 .net8 "VNB", 0 0, L_00000000040f3010;  1 drivers, strength-aware
+L_00000000040f1b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e55860_0 .net8 "VPB", 0 0, L_00000000040f1b10;  1 drivers, strength-aware
+L_00000000040f2520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e559a0_0 .net8 "VPWR", 0 0, L_00000000040f2520;  1 drivers, strength-aware
+v0000000003e55ae0_0 .net "Y", 0 0, L_0000000004176710;  1 drivers
+S_0000000003d049b0 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 23757, 4 24074 1, S_000000000289a4d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004176400 .functor NOR 1, o0000000003e85d68, o0000000003e85d98, C4<0>, C4<0>;
+L_0000000004176550 .functor NOR 1, o0000000003e85d08, o0000000003e85d38, C4<0>, C4<0>;
+L_00000000041765c0 .functor OR 1, L_0000000004176550, L_0000000004176400, C4<0>, C4<0>;
+L_0000000004176710 .functor BUF 1, L_00000000041765c0, C4<0>, C4<0>, C4<0>;
+v0000000003e56300_0 .net "A1", 0 0, o0000000003e85d08;  alias, 0 drivers
+v0000000003e56760_0 .net "A2", 0 0, o0000000003e85d38;  alias, 0 drivers
+v0000000003e555e0_0 .net "B1", 0 0, o0000000003e85d68;  alias, 0 drivers
+v0000000003e54280_0 .net "B2", 0 0, o0000000003e85d98;  alias, 0 drivers
+L_00000000040f2670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e56120_0 .net8 "VGND", 0 0, L_00000000040f2670;  1 drivers, strength-aware
+L_00000000040f3080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e568a0_0 .net8 "VNB", 0 0, L_00000000040f3080;  1 drivers, strength-aware
+L_00000000040f2c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54fa0_0 .net8 "VPB", 0 0, L_00000000040f2c90;  1 drivers, strength-aware
+L_00000000040f1cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e54320_0 .net8 "VPWR", 0 0, L_00000000040f1cd0;  1 drivers, strength-aware
+v0000000003e55040_0 .net "Y", 0 0, L_0000000004176710;  alias, 1 drivers
+v0000000003e55180_0 .net "nor0_out", 0 0, L_0000000004176400;  1 drivers
+v0000000003e563a0_0 .net "nor1_out", 0 0, L_0000000004176550;  1 drivers
+v0000000003e55360_0 .net "or0_out_Y", 0 0, L_00000000041765c0;  1 drivers
+S_000000000289add0 .scope module, "sky130_fd_sc_hd__o2bb2a_1" "sky130_fd_sc_hd__o2bb2a_1" 4 85622;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e861e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e57840_0 .net "A1_N", 0 0, o0000000003e861e8;  0 drivers
+o0000000003e86218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e59000_0 .net "A2_N", 0 0, o0000000003e86218;  0 drivers
+o0000000003e86248 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e58d80_0 .net "B1", 0 0, o0000000003e86248;  0 drivers
+o0000000003e86278 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e578e0_0 .net "B2", 0 0, o0000000003e86278;  0 drivers
+L_00000000040f2d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e570c0_0 .net8 "VGND", 0 0, L_00000000040f2d00;  1 drivers, strength-aware
+L_00000000040f27c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e58100_0 .net8 "VNB", 0 0, L_00000000040f27c0;  1 drivers, strength-aware
+L_00000000040f2830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e589c0_0 .net8 "VPB", 0 0, L_00000000040f2830;  1 drivers, strength-aware
+L_00000000040f2e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e56f80_0 .net8 "VPWR", 0 0, L_00000000040f2e50;  1 drivers, strength-aware
+v0000000003e582e0_0 .net "X", 0 0, L_0000000004177cf0;  1 drivers
+S_0000000003d04b30 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85642, 4 86199 1, S_000000000289add0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004177820 .functor NAND 1, o0000000003e86218, o0000000003e861e8, C4<1>, C4<1>;
+L_0000000004176a90 .functor OR 1, o0000000003e86278, o0000000003e86248, C4<0>, C4<0>;
+L_0000000004177040 .functor AND 1, L_0000000004177820, L_0000000004176a90, C4<1>, C4<1>;
+L_0000000004177cf0 .functor BUF 1, L_0000000004177040, C4<0>, C4<0>, C4<0>;
+v0000000003e55900_0 .net "A1_N", 0 0, o0000000003e861e8;  alias, 0 drivers
+v0000000003e55b80_0 .net "A2_N", 0 0, o0000000003e86218;  alias, 0 drivers
+v0000000003e57980_0 .net "B1", 0 0, o0000000003e86248;  alias, 0 drivers
+v0000000003e573e0_0 .net "B2", 0 0, o0000000003e86278;  alias, 0 drivers
+L_00000000040f15d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e56b20_0 .net8 "VGND", 0 0, L_00000000040f15d0;  1 drivers, strength-aware
+L_00000000040f1720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e56ee0_0 .net8 "VNB", 0 0, L_00000000040f1720;  1 drivers, strength-aware
+L_00000000040f1b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e58ce0_0 .net8 "VPB", 0 0, L_00000000040f1b80;  1 drivers, strength-aware
+L_00000000040f1870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e56da0_0 .net8 "VPWR", 0 0, L_00000000040f1870;  1 drivers, strength-aware
+v0000000003e58f60_0 .net "X", 0 0, L_0000000004177cf0;  alias, 1 drivers
+v0000000003e58380_0 .net "and0_out_X", 0 0, L_0000000004177040;  1 drivers
+v0000000003e57480_0 .net "nand0_out", 0 0, L_0000000004177820;  1 drivers
+v0000000003e57d40_0 .net "or0_out", 0 0, L_0000000004176a90;  1 drivers
+S_0000000002897dd0 .scope module, "sky130_fd_sc_hd__o2bb2a_4" "sky130_fd_sc_hd__o2bb2a_4" 4 85862;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e866c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e575c0_0 .net "A1_N", 0 0, o0000000003e866c8;  0 drivers
+o0000000003e866f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e572a0_0 .net "A2_N", 0 0, o0000000003e866f8;  0 drivers
+o0000000003e86728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e57340_0 .net "B1", 0 0, o0000000003e86728;  0 drivers
+o0000000003e86758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e590a0_0 .net "B2", 0 0, o0000000003e86758;  0 drivers
+L_00000000040f18e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e58060_0 .net8 "VGND", 0 0, L_00000000040f18e0;  1 drivers, strength-aware
+L_00000000040f1950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e57700_0 .net8 "VNB", 0 0, L_00000000040f1950;  1 drivers, strength-aware
+L_00000000040f1c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e569e0_0 .net8 "VPB", 0 0, L_00000000040f1c60;  1 drivers, strength-aware
+L_00000000040f3ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e58880_0 .net8 "VPWR", 0 0, L_00000000040f3ef0;  1 drivers, strength-aware
+v0000000003e58420_0 .net "X", 0 0, L_0000000004177a50;  1 drivers
+S_0000000003d013b0 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85882, 4 86199 1, S_0000000002897dd0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004177890 .functor NAND 1, o0000000003e866f8, o0000000003e866c8, C4<1>, C4<1>;
+L_0000000004177900 .functor OR 1, o0000000003e86758, o0000000003e86728, C4<0>, C4<0>;
+L_0000000004176ef0 .functor AND 1, L_0000000004177890, L_0000000004177900, C4<1>, C4<1>;
+L_0000000004177a50 .functor BUF 1, L_0000000004176ef0, C4<0>, C4<0>, C4<0>;
+v0000000003e56bc0_0 .net "A1_N", 0 0, o0000000003e866c8;  alias, 0 drivers
+v0000000003e57020_0 .net "A2_N", 0 0, o0000000003e866f8;  alias, 0 drivers
+v0000000003e56e40_0 .net "B1", 0 0, o0000000003e86728;  alias, 0 drivers
+v0000000003e57a20_0 .net "B2", 0 0, o0000000003e86758;  alias, 0 drivers
+L_00000000040f35c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e58240_0 .net8 "VGND", 0 0, L_00000000040f35c0;  1 drivers, strength-aware
+L_00000000040f39b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e587e0_0 .net8 "VNB", 0 0, L_00000000040f39b0;  1 drivers, strength-aware
+L_00000000040f3320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e57160_0 .net8 "VPB", 0 0, L_00000000040f3320;  1 drivers, strength-aware
+L_00000000040f3940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e586a0_0 .net8 "VPWR", 0 0, L_00000000040f3940;  1 drivers, strength-aware
+v0000000003e58e20_0 .net "X", 0 0, L_0000000004177a50;  alias, 1 drivers
+v0000000003e57520_0 .net "and0_out_X", 0 0, L_0000000004176ef0;  1 drivers
+v0000000003e57200_0 .net "nand0_out", 0 0, L_0000000004177890;  1 drivers
+v0000000003e56d00_0 .net "or0_out", 0 0, L_0000000004177900;  1 drivers
+S_000000000289b6d0 .scope module, "sky130_fd_sc_hd__o2bb2ai_1" "sky130_fd_sc_hd__o2bb2ai_1" 4 101951;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e86ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e57e80_0 .net "A1_N", 0 0, o0000000003e86ba8;  0 drivers
+o0000000003e86bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e56c60_0 .net "A2_N", 0 0, o0000000003e86bd8;  0 drivers
+o0000000003e86c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e58ec0_0 .net "B1", 0 0, o0000000003e86c08;  0 drivers
+o0000000003e86c38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e57de0_0 .net "B2", 0 0, o0000000003e86c38;  0 drivers
+L_00000000040f4510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e57f20_0 .net8 "VGND", 0 0, L_00000000040f4510;  1 drivers, strength-aware
+L_00000000040f3630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e57fc0_0 .net8 "VNB", 0 0, L_00000000040f3630;  1 drivers, strength-aware
+L_00000000040f3e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e581a0_0 .net8 "VPB", 0 0, L_00000000040f3e80;  1 drivers, strength-aware
+L_00000000040f4270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e58a60_0 .net8 "VPWR", 0 0, L_00000000040f4270;  1 drivers, strength-aware
+v0000000003e56a80_0 .net "Y", 0 0, L_00000000041770b0;  1 drivers
+S_0000000003d04cb0 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 101971, 4 102408 1, S_000000000289b6d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004177f90 .functor NAND 1, o0000000003e86bd8, o0000000003e86ba8, C4<1>, C4<1>;
+L_0000000004176940 .functor OR 1, o0000000003e86c38, o0000000003e86c08, C4<0>, C4<0>;
+L_0000000004177970 .functor NAND 1, L_0000000004177f90, L_0000000004176940, C4<1>, C4<1>;
+L_00000000041770b0 .functor BUF 1, L_0000000004177970, C4<0>, C4<0>, C4<0>;
+v0000000003e57ac0_0 .net "A1_N", 0 0, o0000000003e86ba8;  alias, 0 drivers
+v0000000003e57660_0 .net "A2_N", 0 0, o0000000003e86bd8;  alias, 0 drivers
+v0000000003e56940_0 .net "B1", 0 0, o0000000003e86c08;  alias, 0 drivers
+v0000000003e577a0_0 .net "B2", 0 0, o0000000003e86c38;  alias, 0 drivers
+L_00000000040f43c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e58740_0 .net8 "VGND", 0 0, L_00000000040f43c0;  1 drivers, strength-aware
+L_00000000040f3240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e58560_0 .net8 "VNB", 0 0, L_00000000040f3240;  1 drivers, strength-aware
+L_00000000040f38d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e57b60_0 .net8 "VPB", 0 0, L_00000000040f38d0;  1 drivers, strength-aware
+L_00000000040f3390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e584c0_0 .net8 "VPWR", 0 0, L_00000000040f3390;  1 drivers, strength-aware
+v0000000003e57c00_0 .net "Y", 0 0, L_00000000041770b0;  alias, 1 drivers
+v0000000003e58920_0 .net "nand0_out", 0 0, L_0000000004177f90;  1 drivers
+v0000000003e58600_0 .net "nand1_out_Y", 0 0, L_0000000004177970;  1 drivers
+v0000000003e57ca0_0 .net "or0_out", 0 0, L_0000000004176940;  1 drivers
+S_00000000028998d0 .scope module, "sky130_fd_sc_hd__o2bb2ai_2" "sky130_fd_sc_hd__o2bb2ai_2" 4 101831;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e87088 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e59dc0_0 .net "A1_N", 0 0, o0000000003e87088;  0 drivers
+o0000000003e870b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5b800_0 .net "A2_N", 0 0, o0000000003e870b8;  0 drivers
+o0000000003e870e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5b760_0 .net "B1", 0 0, o0000000003e870e8;  0 drivers
+o0000000003e87118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5acc0_0 .net "B2", 0 0, o0000000003e87118;  0 drivers
+L_00000000040f3a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5b8a0_0 .net8 "VGND", 0 0, L_00000000040f3a20;  1 drivers, strength-aware
+L_00000000040f4040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e59c80_0 .net8 "VNB", 0 0, L_00000000040f4040;  1 drivers, strength-aware
+L_00000000040f3e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5afe0_0 .net8 "VPB", 0 0, L_00000000040f3e10;  1 drivers, strength-aware
+L_00000000040f3a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ad60_0 .net8 "VPWR", 0 0, L_00000000040f3a90;  1 drivers, strength-aware
+v0000000003e5a720_0 .net "Y", 0 0, L_0000000004177dd0;  1 drivers
+S_0000000003d052b0 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 101851, 4 102408 1, S_00000000028998d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004176e10 .functor NAND 1, o0000000003e870b8, o0000000003e87088, C4<1>, C4<1>;
+L_00000000041779e0 .functor OR 1, o0000000003e87118, o0000000003e870e8, C4<0>, C4<0>;
+L_00000000041772e0 .functor NAND 1, L_0000000004176e10, L_00000000041779e0, C4<1>, C4<1>;
+L_0000000004177dd0 .functor BUF 1, L_00000000041772e0, C4<0>, C4<0>, C4<0>;
+v0000000003e58b00_0 .net "A1_N", 0 0, o0000000003e87088;  alias, 0 drivers
+v0000000003e58ba0_0 .net "A2_N", 0 0, o0000000003e870b8;  alias, 0 drivers
+v0000000003e58c40_0 .net "B1", 0 0, o0000000003e870e8;  alias, 0 drivers
+v0000000003e59640_0 .net "B2", 0 0, o0000000003e87118;  alias, 0 drivers
+L_00000000040f4120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e59aa0_0 .net8 "VGND", 0 0, L_00000000040f4120;  1 drivers, strength-aware
+L_00000000040f3d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5a180_0 .net8 "VNB", 0 0, L_00000000040f3d30;  1 drivers, strength-aware
+L_00000000040f42e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5a400_0 .net8 "VPB", 0 0, L_00000000040f42e0;  1 drivers, strength-aware
+L_00000000040f3400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5b300_0 .net8 "VPWR", 0 0, L_00000000040f3400;  1 drivers, strength-aware
+v0000000003e5b4e0_0 .net "Y", 0 0, L_0000000004177dd0;  alias, 1 drivers
+v0000000003e595a0_0 .net "nand0_out", 0 0, L_0000000004176e10;  1 drivers
+v0000000003e5b620_0 .net "nand1_out_Y", 0 0, L_00000000041772e0;  1 drivers
+v0000000003e5b6c0_0 .net "or0_out", 0 0, L_00000000041779e0;  1 drivers
+S_0000000002899a50 .scope module, "sky130_fd_sc_hd__o2bb2ai_4" "sky130_fd_sc_hd__o2bb2ai_4" 4 102071;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+o0000000003e87568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5a7c0_0 .net "A1_N", 0 0, o0000000003e87568;  0 drivers
+o0000000003e87598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e59280_0 .net "A2_N", 0 0, o0000000003e87598;  0 drivers
+o0000000003e875c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e593c0_0 .net "B1", 0 0, o0000000003e875c8;  0 drivers
+o0000000003e875f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5aa40_0 .net "B2", 0 0, o0000000003e875f8;  0 drivers
+L_00000000040f3b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5a040_0 .net8 "VGND", 0 0, L_00000000040f3b00;  1 drivers, strength-aware
+L_00000000040f3b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5aea0_0 .net8 "VNB", 0 0, L_00000000040f3b70;  1 drivers, strength-aware
+L_00000000040f3be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e59460_0 .net8 "VPB", 0 0, L_00000000040f3be0;  1 drivers, strength-aware
+L_00000000040f4ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e59780_0 .net8 "VPWR", 0 0, L_00000000040f4ac0;  1 drivers, strength-aware
+v0000000003e59960_0 .net "Y", 0 0, L_0000000004177ba0;  1 drivers
+S_0000000003d01cb0 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 102091, 4 102408 1, S_0000000002899a50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1_N"
+    .port_info 2 /INPUT 1 "A2_N"
+    .port_info 3 /INPUT 1 "B1"
+    .port_info 4 /INPUT 1 "B2"
+L_0000000004177eb0 .functor NAND 1, o0000000003e87598, o0000000003e87568, C4<1>, C4<1>;
+L_00000000041775f0 .functor OR 1, o0000000003e875f8, o0000000003e875c8, C4<0>, C4<0>;
+L_00000000041777b0 .functor NAND 1, L_0000000004177eb0, L_00000000041775f0, C4<1>, C4<1>;
+L_0000000004177ba0 .functor BUF 1, L_00000000041777b0, C4<0>, C4<0>, C4<0>;
+v0000000003e59820_0 .net "A1_N", 0 0, o0000000003e87568;  alias, 0 drivers
+v0000000003e59500_0 .net "A2_N", 0 0, o0000000003e87598;  alias, 0 drivers
+v0000000003e596e0_0 .net "B1", 0 0, o0000000003e875c8;  alias, 0 drivers
+v0000000003e59320_0 .net "B2", 0 0, o0000000003e875f8;  alias, 0 drivers
+L_00000000040f4b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e59e60_0 .net8 "VGND", 0 0, L_00000000040f4b30;  1 drivers, strength-aware
+L_00000000040f37f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e598c0_0 .net8 "VNB", 0 0, L_00000000040f37f0;  1 drivers, strength-aware
+L_00000000040f4190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e59f00_0 .net8 "VPB", 0 0, L_00000000040f4190;  1 drivers, strength-aware
+L_00000000040f3c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5b260_0 .net8 "VPWR", 0 0, L_00000000040f3c50;  1 drivers, strength-aware
+v0000000003e59140_0 .net "Y", 0 0, L_0000000004177ba0;  alias, 1 drivers
+v0000000003e5a9a0_0 .net "nand0_out", 0 0, L_0000000004177eb0;  1 drivers
+v0000000003e59fa0_0 .net "nand1_out_Y", 0 0, L_00000000041777b0;  1 drivers
+v0000000003e591e0_0 .net "or0_out", 0 0, L_00000000041775f0;  1 drivers
+S_000000000289af50 .scope module, "sky130_fd_sc_hd__o311a_1" "sky130_fd_sc_hd__o311a_1" 4 48497;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e87a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5a5e0_0 .net "A1", 0 0, o0000000003e87a48;  0 drivers
+o0000000003e87a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5b1c0_0 .net "A2", 0 0, o0000000003e87a78;  0 drivers
+o0000000003e87aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5af40_0 .net "A3", 0 0, o0000000003e87aa8;  0 drivers
+o0000000003e87ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5a4a0_0 .net "B1", 0 0, o0000000003e87ad8;  0 drivers
+o0000000003e87b08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5a540_0 .net "C1", 0 0, o0000000003e87b08;  0 drivers
+L_00000000040f3cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5a900_0 .net8 "VGND", 0 0, L_00000000040f3cc0;  1 drivers, strength-aware
+L_00000000040f32b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ab80_0 .net8 "VNB", 0 0, L_00000000040f32b0;  1 drivers, strength-aware
+L_00000000040f4660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ac20_0 .net8 "VPB", 0 0, L_00000000040f4660;  1 drivers, strength-aware
+L_00000000040f30f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ae00_0 .net8 "VPWR", 0 0, L_00000000040f30f0;  1 drivers, strength-aware
+v0000000003e5b120_0 .net "X", 0 0, L_0000000004177f20;  1 drivers
+S_0000000003d055b0 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48519, 4 48837 1, S_000000000289af50;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004176b00 .functor OR 1, o0000000003e87a78, o0000000003e87a48, o0000000003e87aa8, C4<0>;
+L_0000000004177660 .functor AND 1, L_0000000004176b00, o0000000003e87ad8, o0000000003e87b08, C4<1>;
+L_0000000004177f20 .functor BUF 1, L_0000000004177660, C4<0>, C4<0>, C4<0>;
+v0000000003e59a00_0 .net "A1", 0 0, o0000000003e87a48;  alias, 0 drivers
+v0000000003e59d20_0 .net "A2", 0 0, o0000000003e87a78;  alias, 0 drivers
+v0000000003e5a0e0_0 .net "A3", 0 0, o0000000003e87aa8;  alias, 0 drivers
+v0000000003e5a220_0 .net "B1", 0 0, o0000000003e87ad8;  alias, 0 drivers
+v0000000003e5a680_0 .net "C1", 0 0, o0000000003e87b08;  alias, 0 drivers
+L_00000000040f3f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e59b40_0 .net8 "VGND", 0 0, L_00000000040f3f60;  1 drivers, strength-aware
+L_00000000040f36a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5aae0_0 .net8 "VNB", 0 0, L_00000000040f36a0;  1 drivers, strength-aware
+L_00000000040f40b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e59be0_0 .net8 "VPB", 0 0, L_00000000040f40b0;  1 drivers, strength-aware
+L_00000000040f3710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5a2c0_0 .net8 "VPWR", 0 0, L_00000000040f3710;  1 drivers, strength-aware
+v0000000003e5b080_0 .net "X", 0 0, L_0000000004177f20;  alias, 1 drivers
+v0000000003e5a860_0 .net "and0_out_X", 0 0, L_0000000004177660;  1 drivers
+v0000000003e5a360_0 .net "or0_out", 0 0, L_0000000004176b00;  1 drivers
+S_000000000289b9d0 .scope module, "sky130_fd_sc_hd__o311a_4" "sky130_fd_sc_hd__o311a_4" 4 48245;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e87f88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5dce0_0 .net "A1", 0 0, o0000000003e87f88;  0 drivers
+o0000000003e87fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5bda0_0 .net "A2", 0 0, o0000000003e87fb8;  0 drivers
+o0000000003e87fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5bd00_0 .net "A3", 0 0, o0000000003e87fe8;  0 drivers
+o0000000003e88018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5c8e0_0 .net "B1", 0 0, o0000000003e88018;  0 drivers
+o0000000003e88048 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5c5c0_0 .net "C1", 0 0, o0000000003e88048;  0 drivers
+L_00000000040f3da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5be40_0 .net8 "VGND", 0 0, L_00000000040f3da0;  1 drivers, strength-aware
+L_00000000040f3470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cd40_0 .net8 "VNB", 0 0, L_00000000040f3470;  1 drivers, strength-aware
+L_00000000040f3fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5c7a0_0 .net8 "VPB", 0 0, L_00000000040f3fd0;  1 drivers, strength-aware
+L_00000000040f4200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5c840_0 .net8 "VPWR", 0 0, L_00000000040f4200;  1 drivers, strength-aware
+v0000000003e5e000_0 .net "X", 0 0, L_00000000041776d0;  1 drivers
+S_0000000003d01e30 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48267, 4 48837 1, S_000000000289b9d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_00000000041769b0 .functor OR 1, o0000000003e87fb8, o0000000003e87f88, o0000000003e87fe8, C4<0>;
+L_0000000004176da0 .functor AND 1, L_00000000041769b0, o0000000003e88018, o0000000003e88048, C4<1>;
+L_00000000041776d0 .functor BUF 1, L_0000000004176da0, C4<0>, C4<0>, C4<0>;
+v0000000003e5b3a0_0 .net "A1", 0 0, o0000000003e87f88;  alias, 0 drivers
+v0000000003e5b440_0 .net "A2", 0 0, o0000000003e87fb8;  alias, 0 drivers
+v0000000003e5b580_0 .net "A3", 0 0, o0000000003e87fe8;  alias, 0 drivers
+v0000000003e5d1a0_0 .net "B1", 0 0, o0000000003e88018;  alias, 0 drivers
+v0000000003e5df60_0 .net "C1", 0 0, o0000000003e88048;  alias, 0 drivers
+L_00000000040f4580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5bc60_0 .net8 "VGND", 0 0, L_00000000040f4580;  1 drivers, strength-aware
+L_00000000040f4350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5d4c0_0 .net8 "VNB", 0 0, L_00000000040f4350;  1 drivers, strength-aware
+L_00000000040f4430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5e0a0_0 .net8 "VPB", 0 0, L_00000000040f4430;  1 drivers, strength-aware
+L_00000000040f4ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ba80_0 .net8 "VPWR", 0 0, L_00000000040f4ba0;  1 drivers, strength-aware
+v0000000003e5d7e0_0 .net "X", 0 0, L_00000000041776d0;  alias, 1 drivers
+v0000000003e5d560_0 .net "and0_out_X", 0 0, L_0000000004176da0;  1 drivers
+v0000000003e5cf20_0 .net "or0_out", 0 0, L_00000000041769b0;  1 drivers
+S_000000000289a7d0 .scope module, "sky130_fd_sc_hd__o311ai_0" "sky130_fd_sc_hd__o311ai_0" 4 93948;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e884c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5d880_0 .net "A1", 0 0, o0000000003e884c8;  0 drivers
+o0000000003e884f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5ca20_0 .net "A2", 0 0, o0000000003e884f8;  0 drivers
+o0000000003e88528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5cc00_0 .net "A3", 0 0, o0000000003e88528;  0 drivers
+o0000000003e88558 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5b9e0_0 .net "B1", 0 0, o0000000003e88558;  0 drivers
+o0000000003e88588 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5d920_0 .net "C1", 0 0, o0000000003e88588;  0 drivers
+L_00000000040f4c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ce80_0 .net8 "VGND", 0 0, L_00000000040f4c80;  1 drivers, strength-aware
+L_00000000040f44a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cac0_0 .net8 "VNB", 0 0, L_00000000040f44a0;  1 drivers, strength-aware
+L_00000000040f45f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5de20_0 .net8 "VPB", 0 0, L_00000000040f45f0;  1 drivers, strength-aware
+L_00000000040f46d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5c340_0 .net8 "VPWR", 0 0, L_00000000040f46d0;  1 drivers, strength-aware
+v0000000003e5c700_0 .net "Y", 0 0, L_0000000004176a20;  1 drivers
+S_0000000003d05730 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 93970, 4 93818 1, S_000000000289a7d0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004177200 .functor OR 1, o0000000003e884f8, o0000000003e884c8, o0000000003e88528, C4<0>;
+L_0000000004177740 .functor NAND 1, o0000000003e88588, L_0000000004177200, o0000000003e88558, C4<1>;
+L_0000000004176a20 .functor BUF 1, L_0000000004177740, C4<0>, C4<0>, C4<0>;
+v0000000003e5dd80_0 .net "A1", 0 0, o0000000003e884c8;  alias, 0 drivers
+v0000000003e5d2e0_0 .net "A2", 0 0, o0000000003e884f8;  alias, 0 drivers
+v0000000003e5d600_0 .net "A3", 0 0, o0000000003e88528;  alias, 0 drivers
+v0000000003e5d6a0_0 .net "B1", 0 0, o0000000003e88558;  alias, 0 drivers
+v0000000003e5c200_0 .net "C1", 0 0, o0000000003e88588;  alias, 0 drivers
+L_00000000040f3160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5c2a0_0 .net8 "VGND", 0 0, L_00000000040f3160;  1 drivers, strength-aware
+L_00000000040f31d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5d740_0 .net8 "VNB", 0 0, L_00000000040f31d0;  1 drivers, strength-aware
+L_00000000040f4740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5d9c0_0 .net8 "VPB", 0 0, L_00000000040f4740;  1 drivers, strength-aware
+L_00000000040f47b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5c020_0 .net8 "VPWR", 0 0, L_00000000040f47b0;  1 drivers, strength-aware
+v0000000003e5bee0_0 .net "Y", 0 0, L_0000000004176a20;  alias, 1 drivers
+v0000000003e5b940_0 .net "nand0_out_Y", 0 0, L_0000000004177740;  1 drivers
+v0000000003e5c980_0 .net "or0_out", 0 0, L_0000000004177200;  1 drivers
+S_000000000289aad0 .scope module, "sky130_fd_sc_hd__o311ai_1" "sky130_fd_sc_hd__o311ai_1" 4 94074;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e88a08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5bb20_0 .net "A1", 0 0, o0000000003e88a08;  0 drivers
+o0000000003e88a38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5bbc0_0 .net "A2", 0 0, o0000000003e88a38;  0 drivers
+o0000000003e88a68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5c160_0 .net "A3", 0 0, o0000000003e88a68;  0 drivers
+o0000000003e88a98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5c520_0 .net "B1", 0 0, o0000000003e88a98;  0 drivers
+o0000000003e88ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5c660_0 .net "C1", 0 0, o0000000003e88ac8;  0 drivers
+L_00000000040f4820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cb60_0 .net8 "VGND", 0 0, L_00000000040f4820;  1 drivers, strength-aware
+L_00000000040f4890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cfc0_0 .net8 "VNB", 0 0, L_00000000040f4890;  1 drivers, strength-aware
+L_00000000040f4900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cca0_0 .net8 "VPB", 0 0, L_00000000040f4900;  1 drivers, strength-aware
+L_00000000040f4970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5cde0_0 .net8 "VPWR", 0 0, L_00000000040f4970;  1 drivers, strength-aware
+v0000000003e5d060_0 .net "Y", 0 0, L_0000000004176b70;  1 drivers
+S_0000000003d01fb0 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 94096, 4 93818 1, S_000000000289aad0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004177ac0 .functor OR 1, o0000000003e88a38, o0000000003e88a08, o0000000003e88a68, C4<0>;
+L_0000000004177270 .functor NAND 1, o0000000003e88ac8, L_0000000004177ac0, o0000000003e88a98, C4<1>;
+L_0000000004176b70 .functor BUF 1, L_0000000004177270, C4<0>, C4<0>, C4<0>;
+v0000000003e5c3e0_0 .net "A1", 0 0, o0000000003e88a08;  alias, 0 drivers
+v0000000003e5da60_0 .net "A2", 0 0, o0000000003e88a38;  alias, 0 drivers
+v0000000003e5db00_0 .net "A3", 0 0, o0000000003e88a68;  alias, 0 drivers
+v0000000003e5d240_0 .net "B1", 0 0, o0000000003e88a98;  alias, 0 drivers
+v0000000003e5dba0_0 .net "C1", 0 0, o0000000003e88ac8;  alias, 0 drivers
+L_00000000040f49e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5d380_0 .net8 "VGND", 0 0, L_00000000040f49e0;  1 drivers, strength-aware
+L_00000000040f4a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5dc40_0 .net8 "VNB", 0 0, L_00000000040f4a50;  1 drivers, strength-aware
+L_00000000040f4c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5dec0_0 .net8 "VPB", 0 0, L_00000000040f4c10;  1 drivers, strength-aware
+L_00000000040f34e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5bf80_0 .net8 "VPWR", 0 0, L_00000000040f34e0;  1 drivers, strength-aware
+v0000000003e5c0c0_0 .net "Y", 0 0, L_0000000004176b70;  alias, 1 drivers
+v0000000003e5d420_0 .net "nand0_out_Y", 0 0, L_0000000004177270;  1 drivers
+v0000000003e5c480_0 .net "or0_out", 0 0, L_0000000004177ac0;  1 drivers
+S_000000000289b250 .scope module, "sky130_fd_sc_hd__o311ai_2" "sky130_fd_sc_hd__o311ai_2" 4 94200;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e88f48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5e960_0 .net "A1", 0 0, o0000000003e88f48;  0 drivers
+o0000000003e88f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5eaa0_0 .net "A2", 0 0, o0000000003e88f78;  0 drivers
+o0000000003e88fa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e60760_0 .net "A3", 0 0, o0000000003e88fa8;  0 drivers
+o0000000003e88fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f9a0_0 .net "B1", 0 0, o0000000003e88fd8;  0 drivers
+o0000000003e89008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5ef00_0 .net "C1", 0 0, o0000000003e89008;  0 drivers
+L_00000000040f3550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5f400_0 .net8 "VGND", 0 0, L_00000000040f3550;  1 drivers, strength-aware
+L_00000000040f3780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e606c0_0 .net8 "VNB", 0 0, L_00000000040f3780;  1 drivers, strength-aware
+L_00000000040f3860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e60800_0 .net8 "VPB", 0 0, L_00000000040f3860;  1 drivers, strength-aware
+L_00000000040f65e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ee60_0 .net8 "VPWR", 0 0, L_00000000040f65e0;  1 drivers, strength-aware
+v0000000003e604e0_0 .net "Y", 0 0, L_0000000004176f60;  1 drivers
+S_0000000003d028b0 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 94222, 4 93818 1, S_000000000289b250;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004176e80 .functor OR 1, o0000000003e88f78, o0000000003e88f48, o0000000003e88fa8, C4<0>;
+L_0000000004177b30 .functor NAND 1, o0000000003e89008, L_0000000004176e80, o0000000003e88fd8, C4<1>;
+L_0000000004176f60 .functor BUF 1, L_0000000004177b30, C4<0>, C4<0>, C4<0>;
+v0000000003e5d100_0 .net "A1", 0 0, o0000000003e88f48;  alias, 0 drivers
+v0000000003e5fb80_0 .net "A2", 0 0, o0000000003e88f78;  alias, 0 drivers
+v0000000003e5e140_0 .net "A3", 0 0, o0000000003e88fa8;  alias, 0 drivers
+v0000000003e5fa40_0 .net "B1", 0 0, o0000000003e88fd8;  alias, 0 drivers
+v0000000003e60120_0 .net "C1", 0 0, o0000000003e89008;  alias, 0 drivers
+L_00000000040f6260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5e820_0 .net8 "VGND", 0 0, L_00000000040f6260;  1 drivers, strength-aware
+L_00000000040f62d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5fea0_0 .net8 "VNB", 0 0, L_00000000040f62d0;  1 drivers, strength-aware
+L_00000000040f4f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e60580_0 .net8 "VPB", 0 0, L_00000000040f4f20;  1 drivers, strength-aware
+L_00000000040f5850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5fc20_0 .net8 "VPWR", 0 0, L_00000000040f5850;  1 drivers, strength-aware
+v0000000003e5ea00_0 .net "Y", 0 0, L_0000000004176f60;  alias, 1 drivers
+v0000000003e5e500_0 .net "nand0_out_Y", 0 0, L_0000000004177b30;  1 drivers
+v0000000003e5e8c0_0 .net "or0_out", 0 0, L_0000000004176e80;  1 drivers
+S_000000000298af70 .scope module, "sky130_fd_sc_hd__o311ai_4" "sky130_fd_sc_hd__o311ai_4" 4 93478;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+o0000000003e89488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5e640_0 .net "A1", 0 0, o0000000003e89488;  0 drivers
+o0000000003e894b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5e6e0_0 .net "A2", 0 0, o0000000003e894b8;  0 drivers
+o0000000003e894e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f180_0 .net "A3", 0 0, o0000000003e894e8;  0 drivers
+o0000000003e89518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5ebe0_0 .net "B1", 0 0, o0000000003e89518;  0 drivers
+o0000000003e89548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5e320_0 .net "C1", 0 0, o0000000003e89548;  0 drivers
+L_00000000040f6490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5e780_0 .net8 "VGND", 0 0, L_00000000040f6490;  1 drivers, strength-aware
+L_00000000040f5540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5e1e0_0 .net8 "VNB", 0 0, L_00000000040f5540;  1 drivers, strength-aware
+L_00000000040f5700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5f5e0_0 .net8 "VPB", 0 0, L_00000000040f5700;  1 drivers, strength-aware
+L_00000000040f5e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ffe0_0 .net8 "VPWR", 0 0, L_00000000040f5e00;  1 drivers, strength-aware
+v0000000003e5e3c0_0 .net "Y", 0 0, L_0000000004176fd0;  1 drivers
+S_0000000003d058b0 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 93500, 4 93818 1, S_000000000298af70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "C1"
+L_0000000004176be0 .functor OR 1, o0000000003e894b8, o0000000003e89488, o0000000003e894e8, C4<0>;
+L_0000000004177c10 .functor NAND 1, o0000000003e89548, L_0000000004176be0, o0000000003e89518, C4<1>;
+L_0000000004176fd0 .functor BUF 1, L_0000000004177c10, C4<0>, C4<0>, C4<0>;
+v0000000003e608a0_0 .net "A1", 0 0, o0000000003e89488;  alias, 0 drivers
+v0000000003e5edc0_0 .net "A2", 0 0, o0000000003e894b8;  alias, 0 drivers
+v0000000003e5f4a0_0 .net "A3", 0 0, o0000000003e894e8;  alias, 0 drivers
+v0000000003e5fe00_0 .net "B1", 0 0, o0000000003e89518;  alias, 0 drivers
+v0000000003e60620_0 .net "C1", 0 0, o0000000003e89548;  alias, 0 drivers
+L_00000000040f51c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5efa0_0 .net8 "VGND", 0 0, L_00000000040f51c0;  1 drivers, strength-aware
+L_00000000040f6810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e601c0_0 .net8 "VNB", 0 0, L_00000000040f6810;  1 drivers, strength-aware
+L_00000000040f4f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5e5a0_0 .net8 "VPB", 0 0, L_00000000040f4f90;  1 drivers, strength-aware
+L_00000000040f6880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5fae0_0 .net8 "VPWR", 0 0, L_00000000040f6880;  1 drivers, strength-aware
+v0000000003e5f040_0 .net "Y", 0 0, L_0000000004176fd0;  alias, 1 drivers
+v0000000003e5fcc0_0 .net "nand0_out_Y", 0 0, L_0000000004177c10;  1 drivers
+v0000000003e5f0e0_0 .net "or0_out", 0 0, L_0000000004176be0;  1 drivers
+S_000000000298ac70 .scope module, "sky130_fd_sc_hd__o31a_1" "sky130_fd_sc_hd__o31a_1" 4 76792;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e899c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f2c0_0 .net "A1", 0 0, o0000000003e899c8;  0 drivers
+o0000000003e899f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f360_0 .net "A2", 0 0, o0000000003e899f8;  0 drivers
+o0000000003e89a28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f680_0 .net "A3", 0 0, o0000000003e89a28;  0 drivers
+o0000000003e89a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e5f7c0_0 .net "B1", 0 0, o0000000003e89a58;  0 drivers
+L_00000000040f60a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5f860_0 .net8 "VGND", 0 0, L_00000000040f60a0;  1 drivers, strength-aware
+L_00000000040f5af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e60260_0 .net8 "VNB", 0 0, L_00000000040f5af0;  1 drivers, strength-aware
+L_00000000040f6340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5f900_0 .net8 "VPB", 0 0, L_00000000040f6340;  1 drivers, strength-aware
+L_00000000040f5930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e60300_0 .net8 "VPWR", 0 0, L_00000000040f5930;  1 drivers, strength-aware
+v0000000003e603a0_0 .net "X", 0 0, L_0000000004176cc0;  1 drivers
+S_0000000003d05d30 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76812, 4 77123 1, S_000000000298ac70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004177120 .functor OR 1, o0000000003e899f8, o0000000003e899c8, o0000000003e89a28, C4<0>;
+L_0000000004177c80 .functor AND 1, L_0000000004177120, o0000000003e89a58, C4<1>, C4<1>;
+L_0000000004176cc0 .functor BUF 1, L_0000000004177c80, C4<0>, C4<0>, C4<0>;
+v0000000003e5e460_0 .net "A1", 0 0, o0000000003e899c8;  alias, 0 drivers
+v0000000003e5f220_0 .net "A2", 0 0, o0000000003e899f8;  alias, 0 drivers
+v0000000003e5e280_0 .net "A3", 0 0, o0000000003e89a28;  alias, 0 drivers
+v0000000003e5eb40_0 .net "B1", 0 0, o0000000003e89a58;  alias, 0 drivers
+L_00000000040f50e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e60080_0 .net8 "VGND", 0 0, L_00000000040f50e0;  1 drivers, strength-aware
+L_00000000040f5070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ec80_0 .net8 "VNB", 0 0, L_00000000040f5070;  1 drivers, strength-aware
+L_00000000040f5230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5ed20_0 .net8 "VPB", 0 0, L_00000000040f5230;  1 drivers, strength-aware
+L_00000000040f63b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e5fd60_0 .net8 "VPWR", 0 0, L_00000000040f63b0;  1 drivers, strength-aware
+v0000000003e5ff40_0 .net "X", 0 0, L_0000000004176cc0;  alias, 1 drivers
+v0000000003e5f720_0 .net "and0_out_X", 0 0, L_0000000004177c80;  1 drivers
+v0000000003e5f540_0 .net "or0_out", 0 0, L_0000000004177120;  1 drivers
+S_000000000298adf0 .scope module, "sky130_fd_sc_hd__o31a_2" "sky130_fd_sc_hd__o31a_2" 4 76672;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e89e78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e62880_0 .net "A1", 0 0, o0000000003e89e78;  0 drivers
+o0000000003e89ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e60bc0_0 .net "A2", 0 0, o0000000003e89ea8;  0 drivers
+o0000000003e89ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e62d80_0 .net "A3", 0 0, o0000000003e89ed8;  0 drivers
+o0000000003e89f08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e61480_0 .net "B1", 0 0, o0000000003e89f08;  0 drivers
+L_00000000040f6030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e61200_0 .net8 "VGND", 0 0, L_00000000040f6030;  1 drivers, strength-aware
+L_00000000040f52a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e61ac0_0 .net8 "VNB", 0 0, L_00000000040f52a0;  1 drivers, strength-aware
+L_00000000040f5b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e60da0_0 .net8 "VPB", 0 0, L_00000000040f5b60;  1 drivers, strength-aware
+L_00000000040f5a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e60f80_0 .net8 "VPWR", 0 0, L_00000000040f5a10;  1 drivers, strength-aware
+v0000000003e62740_0 .net "X", 0 0, L_0000000004177350;  1 drivers
+S_0000000003d06c30 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76692, 4 77123 1, S_000000000298adf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004177190 .functor OR 1, o0000000003e89ea8, o0000000003e89e78, o0000000003e89ed8, C4<0>;
+L_0000000004177d60 .functor AND 1, L_0000000004177190, o0000000003e89f08, C4<1>, C4<1>;
+L_0000000004177350 .functor BUF 1, L_0000000004177d60, C4<0>, C4<0>, C4<0>;
+v0000000003e60440_0 .net "A1", 0 0, o0000000003e89e78;  alias, 0 drivers
+v0000000003e60ee0_0 .net "A2", 0 0, o0000000003e89ea8;  alias, 0 drivers
+v0000000003e61a20_0 .net "A3", 0 0, o0000000003e89ed8;  alias, 0 drivers
+v0000000003e62560_0 .net "B1", 0 0, o0000000003e89f08;  alias, 0 drivers
+L_00000000040f54d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62600_0 .net8 "VGND", 0 0, L_00000000040f54d0;  1 drivers, strength-aware
+L_00000000040f5690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e60940_0 .net8 "VNB", 0 0, L_00000000040f5690;  1 drivers, strength-aware
+L_00000000040f6420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e612a0_0 .net8 "VPB", 0 0, L_00000000040f6420;  1 drivers, strength-aware
+L_00000000040f6730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e626a0_0 .net8 "VPWR", 0 0, L_00000000040f6730;  1 drivers, strength-aware
+v0000000003e629c0_0 .net "X", 0 0, L_0000000004177350;  alias, 1 drivers
+v0000000003e627e0_0 .net "and0_out_X", 0 0, L_0000000004177d60;  1 drivers
+v0000000003e60e40_0 .net "or0_out", 0 0, L_0000000004177190;  1 drivers
+S_0000000002988e70 .scope module, "sky130_fd_sc_hd__o31a_4" "sky130_fd_sc_hd__o31a_4" 4 76552;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e8a328 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e61ca0_0 .net "A1", 0 0, o0000000003e8a328;  0 drivers
+o0000000003e8a358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e62a60_0 .net "A2", 0 0, o0000000003e8a358;  0 drivers
+o0000000003e8a388 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e622e0_0 .net "A3", 0 0, o0000000003e8a388;  0 drivers
+o0000000003e8a3b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e60a80_0 .net "B1", 0 0, o0000000003e8a3b8;  0 drivers
+L_00000000040f5000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62b00_0 .net8 "VGND", 0 0, L_00000000040f5000;  1 drivers, strength-aware
+L_00000000040f6500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62240_0 .net8 "VNB", 0 0, L_00000000040f6500;  1 drivers, strength-aware
+L_00000000040f5f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e62420_0 .net8 "VPB", 0 0, L_00000000040f5f50;  1 drivers, strength-aware
+L_00000000040f5770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e61840_0 .net8 "VPWR", 0 0, L_00000000040f5770;  1 drivers, strength-aware
+v0000000003e618e0_0 .net "X", 0 0, L_00000000041773c0;  1 drivers
+S_0000000003d06db0 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76572, 4 77123 1, S_0000000002988e70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004176c50 .functor OR 1, o0000000003e8a358, o0000000003e8a328, o0000000003e8a388, C4<0>;
+L_0000000004177580 .functor AND 1, L_0000000004176c50, o0000000003e8a3b8, C4<1>, C4<1>;
+L_00000000041773c0 .functor BUF 1, L_0000000004177580, C4<0>, C4<0>, C4<0>;
+v0000000003e61de0_0 .net "A1", 0 0, o0000000003e8a328;  alias, 0 drivers
+v0000000003e609e0_0 .net "A2", 0 0, o0000000003e8a358;  alias, 0 drivers
+v0000000003e62ec0_0 .net "A3", 0 0, o0000000003e8a388;  alias, 0 drivers
+v0000000003e60d00_0 .net "B1", 0 0, o0000000003e8a3b8;  alias, 0 drivers
+L_00000000040f6570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e61f20_0 .net8 "VGND", 0 0, L_00000000040f6570;  1 drivers, strength-aware
+L_00000000040f57e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62e20_0 .net8 "VNB", 0 0, L_00000000040f57e0;  1 drivers, strength-aware
+L_00000000040f5e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e61b60_0 .net8 "VPB", 0 0, L_00000000040f5e70;  1 drivers, strength-aware
+L_00000000040f5310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e63000_0 .net8 "VPWR", 0 0, L_00000000040f5310;  1 drivers, strength-aware
+v0000000003e621a0_0 .net "X", 0 0, L_00000000041773c0;  alias, 1 drivers
+v0000000003e62380_0 .net "and0_out_X", 0 0, L_0000000004177580;  1 drivers
+v0000000003e62920_0 .net "or0_out", 0 0, L_0000000004176c50;  1 drivers
+S_000000000298a370 .scope module, "sky130_fd_sc_hd__o31ai_1" "sky130_fd_sc_hd__o31ai_1" 4 67077;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e8a7d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e624c0_0 .net "A1", 0 0, o0000000003e8a7d8;  0 drivers
+o0000000003e8a808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e61980_0 .net "A2", 0 0, o0000000003e8a808;  0 drivers
+o0000000003e8a838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e61c00_0 .net "A3", 0 0, o0000000003e8a838;  0 drivers
+o0000000003e8a868 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e60c60_0 .net "B1", 0 0, o0000000003e8a868;  0 drivers
+L_00000000040f5380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e630a0_0 .net8 "VGND", 0 0, L_00000000040f5380;  1 drivers, strength-aware
+L_00000000040f55b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62100_0 .net8 "VNB", 0 0, L_00000000040f55b0;  1 drivers, strength-aware
+L_00000000040f5150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e617a0_0 .net8 "VPB", 0 0, L_00000000040f5150;  1 drivers, strength-aware
+L_00000000040f5620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e61020_0 .net8 "VPWR", 0 0, L_00000000040f5620;  1 drivers, strength-aware
+v0000000003e613e0_0 .net "Y", 0 0, L_00000000041774a0;  1 drivers
+S_0000000003d06f30 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67097, 4 66952 1, S_000000000298a370;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004177430 .functor OR 1, o0000000003e8a808, o0000000003e8a7d8, o0000000003e8a838, C4<0>;
+L_0000000004177e40 .functor NAND 1, o0000000003e8a868, L_0000000004177430, C4<1>, C4<1>;
+L_00000000041774a0 .functor BUF 1, L_0000000004177e40, C4<0>, C4<0>, C4<0>;
+v0000000003e61e80_0 .net "A1", 0 0, o0000000003e8a7d8;  alias, 0 drivers
+v0000000003e61fc0_0 .net "A2", 0 0, o0000000003e8a808;  alias, 0 drivers
+v0000000003e60b20_0 .net "A3", 0 0, o0000000003e8a838;  alias, 0 drivers
+v0000000003e62ce0_0 .net "B1", 0 0, o0000000003e8a868;  alias, 0 drivers
+L_00000000040f5ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e61160_0 .net8 "VGND", 0 0, L_00000000040f5ee0;  1 drivers, strength-aware
+L_00000000040f58c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e62060_0 .net8 "VNB", 0 0, L_00000000040f58c0;  1 drivers, strength-aware
+L_00000000040f4cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e62ba0_0 .net8 "VPB", 0 0, L_00000000040f4cf0;  1 drivers, strength-aware
+L_00000000040f53f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e615c0_0 .net8 "VPWR", 0 0, L_00000000040f53f0;  1 drivers, strength-aware
+v0000000003e62c40_0 .net "Y", 0 0, L_00000000041774a0;  alias, 1 drivers
+v0000000003e62f60_0 .net "nand0_out_Y", 0 0, L_0000000004177e40;  1 drivers
+v0000000003e61340_0 .net "or0_out", 0 0, L_0000000004177430;  1 drivers
+S_000000000298b0f0 .scope module, "sky130_fd_sc_hd__o31ai_2" "sky130_fd_sc_hd__o31ai_2" 4 67197;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e8ac88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e65580_0 .net "A1", 0 0, o0000000003e8ac88;  0 drivers
+o0000000003e8acb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e64180_0 .net "A2", 0 0, o0000000003e8acb8;  0 drivers
+o0000000003e8ace8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e64040_0 .net "A3", 0 0, o0000000003e8ace8;  0 drivers
+o0000000003e8ad18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e64720_0 .net "B1", 0 0, o0000000003e8ad18;  0 drivers
+L_00000000040f6650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e65620_0 .net8 "VGND", 0 0, L_00000000040f6650;  1 drivers, strength-aware
+L_00000000040f4d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e64ae0_0 .net8 "VNB", 0 0, L_00000000040f4d60;  1 drivers, strength-aware
+L_00000000040f59a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e64b80_0 .net8 "VPB", 0 0, L_00000000040f59a0;  1 drivers, strength-aware
+L_00000000040f6180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e64d60_0 .net8 "VPWR", 0 0, L_00000000040f6180;  1 drivers, strength-aware
+v0000000003e64e00_0 .net "Y", 0 0, L_00000000042040c0;  1 drivers
+S_0000000003d01530 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67217, 4 66952 1, S_000000000298b0f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004176d30 .functor OR 1, o0000000003e8acb8, o0000000003e8ac88, o0000000003e8ace8, C4<0>;
+L_0000000004177510 .functor NAND 1, o0000000003e8ad18, L_0000000004176d30, C4<1>, C4<1>;
+L_00000000042040c0 .functor BUF 1, L_0000000004177510, C4<0>, C4<0>, C4<0>;
+v0000000003e61d40_0 .net "A1", 0 0, o0000000003e8ac88;  alias, 0 drivers
+v0000000003e610c0_0 .net "A2", 0 0, o0000000003e8acb8;  alias, 0 drivers
+v0000000003e61520_0 .net "A3", 0 0, o0000000003e8ace8;  alias, 0 drivers
+v0000000003e61660_0 .net "B1", 0 0, o0000000003e8ad18;  alias, 0 drivers
+L_00000000040f4eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e61700_0 .net8 "VGND", 0 0, L_00000000040f4eb0;  1 drivers, strength-aware
+L_00000000040f66c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e63640_0 .net8 "VNB", 0 0, L_00000000040f66c0;  1 drivers, strength-aware
+L_00000000040f6110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e640e0_0 .net8 "VPB", 0 0, L_00000000040f6110;  1 drivers, strength-aware
+L_00000000040f5a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e63dc0_0 .net8 "VPWR", 0 0, L_00000000040f5a80;  1 drivers, strength-aware
+v0000000003e63a00_0 .net "Y", 0 0, L_00000000042040c0;  alias, 1 drivers
+v0000000003e64540_0 .net "nand0_out_Y", 0 0, L_0000000004177510;  1 drivers
+v0000000003e63fa0_0 .net "or0_out", 0 0, L_0000000004176d30;  1 drivers
+S_0000000002989770 .scope module, "sky130_fd_sc_hd__o31ai_4" "sky130_fd_sc_hd__o31ai_4" 4 67317;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+o0000000003e8b138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e64360_0 .net "A1", 0 0, o0000000003e8b138;  0 drivers
+o0000000003e8b168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e65260_0 .net "A2", 0 0, o0000000003e8b168;  0 drivers
+o0000000003e8b198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e65760_0 .net "A3", 0 0, o0000000003e8b198;  0 drivers
+o0000000003e8b1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e64680_0 .net "B1", 0 0, o0000000003e8b1c8;  0 drivers
+L_00000000040f5460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e64cc0_0 .net8 "VGND", 0 0, L_00000000040f5460;  1 drivers, strength-aware
+L_00000000040f5fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e65080_0 .net8 "VNB", 0 0, L_00000000040f5fc0;  1 drivers, strength-aware
+L_00000000040f5bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e64a40_0 .net8 "VPB", 0 0, L_00000000040f5bd0;  1 drivers, strength-aware
+L_00000000040f4dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e63500_0 .net8 "VPWR", 0 0, L_00000000040f4dd0;  1 drivers, strength-aware
+v0000000003e647c0_0 .net "Y", 0 0, L_0000000004203950;  1 drivers
+S_0000000003d02430 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67337, 4 66952 1, S_0000000002989770;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+L_0000000004204670 .functor OR 1, o0000000003e8b168, o0000000003e8b138, o0000000003e8b198, C4<0>;
+L_00000000042033a0 .functor NAND 1, o0000000003e8b1c8, L_0000000004204670, C4<1>, C4<1>;
+L_0000000004203950 .functor BUF 1, L_00000000042033a0, C4<0>, C4<0>, C4<0>;
+v0000000003e636e0_0 .net "A1", 0 0, o0000000003e8b138;  alias, 0 drivers
+v0000000003e64220_0 .net "A2", 0 0, o0000000003e8b168;  alias, 0 drivers
+v0000000003e645e0_0 .net "A3", 0 0, o0000000003e8b198;  alias, 0 drivers
+v0000000003e638c0_0 .net "B1", 0 0, o0000000003e8b1c8;  alias, 0 drivers
+L_00000000040f5c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e633c0_0 .net8 "VGND", 0 0, L_00000000040f5c40;  1 drivers, strength-aware
+L_00000000040f67a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e656c0_0 .net8 "VNB", 0 0, L_00000000040f67a0;  1 drivers, strength-aware
+L_00000000040f4e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e64c20_0 .net8 "VPB", 0 0, L_00000000040f4e40;  1 drivers, strength-aware
+L_00000000040f5cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e63820_0 .net8 "VPWR", 0 0, L_00000000040f5cb0;  1 drivers, strength-aware
+v0000000003e64f40_0 .net "Y", 0 0, L_0000000004203950;  alias, 1 drivers
+v0000000003e63960_0 .net "nand0_out_Y", 0 0, L_00000000042033a0;  1 drivers
+v0000000003e642c0_0 .net "or0_out", 0 0, L_0000000004204670;  1 drivers
+S_000000000298be70 .scope module, "sky130_fd_sc_hd__o32a_1" "sky130_fd_sc_hd__o32a_1" 4 45369;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003e8b5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e63780_0 .net "A1", 0 0, o0000000003e8b5e8;  0 drivers
+o0000000003e8b618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e63aa0_0 .net "A2", 0 0, o0000000003e8b618;  0 drivers
+o0000000003e8b648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e644a0_0 .net "A3", 0 0, o0000000003e8b648;  0 drivers
+o0000000003e8b678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e63be0_0 .net "B1", 0 0, o0000000003e8b678;  0 drivers
+o0000000003e8b6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e63320_0 .net "B2", 0 0, o0000000003e8b6a8;  0 drivers
+L_00000000040f5d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e63b40_0 .net8 "VGND", 0 0, L_00000000040f5d20;  1 drivers, strength-aware
+L_00000000040f5d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e654e0_0 .net8 "VNB", 0 0, L_00000000040f5d90;  1 drivers, strength-aware
+L_00000000040f61f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e64860_0 .net8 "VPB", 0 0, L_00000000040f61f0;  1 drivers, strength-aware
+L_00000000040f8100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e65440_0 .net8 "VPWR", 0 0, L_00000000040f8100;  1 drivers, strength-aware
+v0000000003e63460_0 .net "X", 0 0, L_0000000004203410;  1 drivers
+S_0000000003d025b0 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45391, 4 45841 1, S_000000000298be70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004204c20 .functor OR 1, o0000000003e8b618, o0000000003e8b5e8, o0000000003e8b648, C4<0>;
+L_00000000042042f0 .functor OR 1, o0000000003e8b6a8, o0000000003e8b678, C4<0>, C4<0>;
+L_0000000004203d40 .functor AND 1, L_0000000004204c20, L_00000000042042f0, C4<1>, C4<1>;
+L_0000000004203410 .functor BUF 1, L_0000000004203d40, C4<0>, C4<0>, C4<0>;
+v0000000003e64ea0_0 .net "A1", 0 0, o0000000003e8b5e8;  alias, 0 drivers
+v0000000003e658a0_0 .net "A2", 0 0, o0000000003e8b618;  alias, 0 drivers
+v0000000003e65800_0 .net "A3", 0 0, o0000000003e8b648;  alias, 0 drivers
+v0000000003e64fe0_0 .net "B1", 0 0, o0000000003e8b678;  alias, 0 drivers
+v0000000003e65120_0 .net "B2", 0 0, o0000000003e8b6a8;  alias, 0 drivers
+L_00000000040f7c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e651c0_0 .net8 "VGND", 0 0, L_00000000040f7c30;  1 drivers, strength-aware
+L_00000000040f74c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e63e60_0 .net8 "VNB", 0 0, L_00000000040f74c0;  1 drivers, strength-aware
+L_00000000040f7fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e65300_0 .net8 "VPB", 0 0, L_00000000040f7fb0;  1 drivers, strength-aware
+L_00000000040f82c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e635a0_0 .net8 "VPWR", 0 0, L_00000000040f82c0;  1 drivers, strength-aware
+v0000000003e63d20_0 .net "X", 0 0, L_0000000004203410;  alias, 1 drivers
+v0000000003e63f00_0 .net "and0_out_X", 0 0, L_0000000004203d40;  1 drivers
+v0000000003e653a0_0 .net "or0_out", 0 0, L_0000000004204c20;  1 drivers
+v0000000003e64400_0 .net "or1_out", 0 0, L_00000000042042f0;  1 drivers
+S_000000000298b270 .scope module, "sky130_fd_sc_hd__o32a_4" "sky130_fd_sc_hd__o32a_4" 4 45495;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003e8bb58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67100_0 .net "A1", 0 0, o0000000003e8bb58;  0 drivers
+o0000000003e8bb88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e672e0_0 .net "A2", 0 0, o0000000003e8bb88;  0 drivers
+o0000000003e8bbb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e66020_0 .net "A3", 0 0, o0000000003e8bbb8;  0 drivers
+o0000000003e8bbe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e66ca0_0 .net "B1", 0 0, o0000000003e8bbe8;  0 drivers
+o0000000003e8bc18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e65940_0 .net "B2", 0 0, o0000000003e8bc18;  0 drivers
+L_00000000040f68f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e65d00_0 .net8 "VGND", 0 0, L_00000000040f68f0;  1 drivers, strength-aware
+L_00000000040f6c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e66160_0 .net8 "VNB", 0 0, L_00000000040f6c00;  1 drivers, strength-aware
+L_00000000040f8330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66de0_0 .net8 "VPB", 0 0, L_00000000040f8330;  1 drivers, strength-aware
+L_00000000040f6dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66980_0 .net8 "VPWR", 0 0, L_00000000040f6dc0;  1 drivers, strength-aware
+v0000000003e663e0_0 .net "X", 0 0, L_00000000042048a0;  1 drivers
+S_0000000003ee9e00 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45517, 4 45841 1, S_000000000298b270;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004204ad0 .functor OR 1, o0000000003e8bb88, o0000000003e8bb58, o0000000003e8bbb8, C4<0>;
+L_0000000004203db0 .functor OR 1, o0000000003e8bc18, o0000000003e8bbe8, C4<0>, C4<0>;
+L_0000000004204bb0 .functor AND 1, L_0000000004204ad0, L_0000000004203db0, C4<1>, C4<1>;
+L_00000000042048a0 .functor BUF 1, L_0000000004204bb0, C4<0>, C4<0>, C4<0>;
+v0000000003e63140_0 .net "A1", 0 0, o0000000003e8bb58;  alias, 0 drivers
+v0000000003e64900_0 .net "A2", 0 0, o0000000003e8bb88;  alias, 0 drivers
+v0000000003e649a0_0 .net "A3", 0 0, o0000000003e8bbb8;  alias, 0 drivers
+v0000000003e631e0_0 .net "B1", 0 0, o0000000003e8bbe8;  alias, 0 drivers
+v0000000003e63280_0 .net "B2", 0 0, o0000000003e8bc18;  alias, 0 drivers
+L_00000000040f6ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e63c80_0 .net8 "VGND", 0 0, L_00000000040f6ff0;  1 drivers, strength-aware
+L_00000000040f83a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e67ce0_0 .net8 "VNB", 0 0, L_00000000040f83a0;  1 drivers, strength-aware
+L_00000000040f7ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66a20_0 .net8 "VPB", 0 0, L_00000000040f7ed0;  1 drivers, strength-aware
+L_00000000040f6f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66c00_0 .net8 "VPWR", 0 0, L_00000000040f6f10;  1 drivers, strength-aware
+v0000000003e66ac0_0 .net "X", 0 0, L_00000000042048a0;  alias, 1 drivers
+v0000000003e65ee0_0 .net "and0_out_X", 0 0, L_0000000004204bb0;  1 drivers
+v0000000003e67ec0_0 .net "or0_out", 0 0, L_0000000004204ad0;  1 drivers
+v0000000003e67380_0 .net "or1_out", 0 0, L_0000000004203db0;  1 drivers
+S_0000000002988870 .scope module, "sky130_fd_sc_hd__o32ai_1" "sky130_fd_sc_hd__o32ai_1" 4 25048;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003e8c0c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e66e80_0 .net "A1", 0 0, o0000000003e8c0c8;  0 drivers
+o0000000003e8c0f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67240_0 .net "A2", 0 0, o0000000003e8c0f8;  0 drivers
+o0000000003e8c128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e674c0_0 .net "A3", 0 0, o0000000003e8c128;  0 drivers
+o0000000003e8c158 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67880_0 .net "B1", 0 0, o0000000003e8c158;  0 drivers
+o0000000003e8c188 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67a60_0 .net "B2", 0 0, o0000000003e8c188;  0 drivers
+L_00000000040f7e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e65bc0_0 .net8 "VGND", 0 0, L_00000000040f7e60;  1 drivers, strength-aware
+L_00000000040f7840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e676a0_0 .net8 "VNB", 0 0, L_00000000040f7840;  1 drivers, strength-aware
+L_00000000040f8410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e67740_0 .net8 "VPB", 0 0, L_00000000040f8410;  1 drivers, strength-aware
+L_00000000040f7d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66f20_0 .net8 "VPWR", 0 0, L_00000000040f7d10;  1 drivers, strength-aware
+v0000000003e66fc0_0 .net "Y", 0 0, L_0000000004203170;  1 drivers
+S_0000000003eec200 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 25070, 4 24916 1, S_0000000002988870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004204910 .functor NOR 1, o0000000003e8c128, o0000000003e8c0c8, o0000000003e8c0f8, C4<0>;
+L_00000000042031e0 .functor NOR 1, o0000000003e8c158, o0000000003e8c188, C4<0>, C4<0>;
+L_0000000004203b80 .functor OR 1, L_00000000042031e0, L_0000000004204910, C4<0>, C4<0>;
+L_0000000004203170 .functor BUF 1, L_0000000004203b80, C4<0>, C4<0>, C4<0>;
+v0000000003e65c60_0 .net "A1", 0 0, o0000000003e8c0c8;  alias, 0 drivers
+v0000000003e67560_0 .net "A2", 0 0, o0000000003e8c0f8;  alias, 0 drivers
+v0000000003e66340_0 .net "A3", 0 0, o0000000003e8c128;  alias, 0 drivers
+v0000000003e677e0_0 .net "B1", 0 0, o0000000003e8c158;  alias, 0 drivers
+v0000000003e66520_0 .net "B2", 0 0, o0000000003e8c188;  alias, 0 drivers
+L_00000000040f6c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e67420_0 .net8 "VGND", 0 0, L_00000000040f6c70;  1 drivers, strength-aware
+L_00000000040f6ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e679c0_0 .net8 "VNB", 0 0, L_00000000040f6ce0;  1 drivers, strength-aware
+L_00000000040f7680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66b60_0 .net8 "VPB", 0 0, L_00000000040f7680;  1 drivers, strength-aware
+L_00000000040f6d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66d40_0 .net8 "VPWR", 0 0, L_00000000040f6d50;  1 drivers, strength-aware
+v0000000003e659e0_0 .net "Y", 0 0, L_0000000004203170;  alias, 1 drivers
+v0000000003e67600_0 .net "nor0_out", 0 0, L_0000000004204910;  1 drivers
+v0000000003e65e40_0 .net "nor1_out", 0 0, L_00000000042031e0;  1 drivers
+v0000000003e67e20_0 .net "or0_out_Y", 0 0, L_0000000004203b80;  1 drivers
+S_00000000029889f0 .scope module, "sky130_fd_sc_hd__o32ai_2" "sky130_fd_sc_hd__o32ai_2" 4 24570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003e8c638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e65da0_0 .net "A1", 0 0, o0000000003e8c638;  0 drivers
+o0000000003e8c668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e668e0_0 .net "A2", 0 0, o0000000003e8c668;  0 drivers
+o0000000003e8c698 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67c40_0 .net "A3", 0 0, o0000000003e8c698;  0 drivers
+o0000000003e8c6c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e662a0_0 .net "B1", 0 0, o0000000003e8c6c8;  0 drivers
+o0000000003e8c6f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003e67f60_0 .net "B2", 0 0, o0000000003e8c6f8;  0 drivers
+L_00000000040f7ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e660c0_0 .net8 "VGND", 0 0, L_00000000040f7ca0;  1 drivers, strength-aware
+L_00000000040f7d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e66200_0 .net8 "VNB", 0 0, L_00000000040f7d80;  1 drivers, strength-aware
+L_00000000040f69d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e66700_0 .net8 "VPB", 0 0, L_00000000040f69d0;  1 drivers, strength-aware
+L_00000000040f7df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e667a0_0 .net8 "VPWR", 0 0, L_00000000040f7df0;  1 drivers, strength-aware
+v0000000003f0ca20_0 .net "Y", 0 0, L_00000000042034f0;  1 drivers
+S_0000000003ee9f80 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 24592, 4 24916 1, S_00000000029889f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_00000000042036b0 .functor NOR 1, o0000000003e8c698, o0000000003e8c638, o0000000003e8c668, C4<0>;
+L_0000000004203f70 .functor NOR 1, o0000000003e8c6c8, o0000000003e8c6f8, C4<0>, C4<0>;
+L_0000000004203480 .functor OR 1, L_0000000004203f70, L_00000000042036b0, C4<0>, C4<0>;
+L_00000000042034f0 .functor BUF 1, L_0000000004203480, C4<0>, C4<0>, C4<0>;
+v0000000003e65f80_0 .net "A1", 0 0, o0000000003e8c638;  alias, 0 drivers
+v0000000003e665c0_0 .net "A2", 0 0, o0000000003e8c668;  alias, 0 drivers
+v0000000003e66480_0 .net "A3", 0 0, o0000000003e8c698;  alias, 0 drivers
+v0000000003e67060_0 .net "B1", 0 0, o0000000003e8c6c8;  alias, 0 drivers
+v0000000003e66840_0 .net "B2", 0 0, o0000000003e8c6f8;  alias, 0 drivers
+L_00000000040f7a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e66660_0 .net8 "VGND", 0 0, L_00000000040f7a70;  1 drivers, strength-aware
+L_00000000040f8250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003e65a80_0 .net8 "VNB", 0 0, L_00000000040f8250;  1 drivers, strength-aware
+L_00000000040f81e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e65b20_0 .net8 "VPB", 0 0, L_00000000040f81e0;  1 drivers, strength-aware
+L_00000000040f7ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003e67920_0 .net8 "VPWR", 0 0, L_00000000040f7ae0;  1 drivers, strength-aware
+v0000000003e67b00_0 .net "Y", 0 0, L_00000000042034f0;  alias, 1 drivers
+v0000000003e671a0_0 .net "nor0_out", 0 0, L_00000000042036b0;  1 drivers
+v0000000003e67ba0_0 .net "nor1_out", 0 0, L_0000000004203f70;  1 drivers
+v0000000003e67d80_0 .net "or0_out_Y", 0 0, L_0000000004203480;  1 drivers
+S_00000000029895f0 .scope module, "sky130_fd_sc_hd__o32ai_4" "sky130_fd_sc_hd__o32ai_4" 4 24444;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+o0000000003e8cba8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0d600_0 .net "A1", 0 0, o0000000003e8cba8;  0 drivers
+o0000000003e8cbd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0c840_0 .net "A2", 0 0, o0000000003e8cbd8;  0 drivers
+o0000000003e8cc08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0d6a0_0 .net "A3", 0 0, o0000000003e8cc08;  0 drivers
+o0000000003e8cc38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0e0a0_0 .net "B1", 0 0, o0000000003e8cc38;  0 drivers
+o0000000003e8cc68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0c8e0_0 .net "B2", 0 0, o0000000003e8cc68;  0 drivers
+L_00000000040f7f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0cca0_0 .net8 "VGND", 0 0, L_00000000040f7f40;  1 drivers, strength-aware
+L_00000000040f76f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d560_0 .net8 "VNB", 0 0, L_00000000040f76f0;  1 drivers, strength-aware
+L_00000000040f7760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0cac0_0 .net8 "VPB", 0 0, L_00000000040f7760;  1 drivers, strength-aware
+L_00000000040f7060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d2e0_0 .net8 "VPWR", 0 0, L_00000000040f7060;  1 drivers, strength-aware
+v0000000003f0b940_0 .net "Y", 0 0, L_0000000004203f00;  1 drivers
+S_0000000003eea100 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 24466, 4 24916 1, S_00000000029895f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "B1"
+    .port_info 5 /INPUT 1 "B2"
+L_0000000004204130 .functor NOR 1, o0000000003e8cc08, o0000000003e8cba8, o0000000003e8cbd8, C4<0>;
+L_0000000004203c60 .functor NOR 1, o0000000003e8cc38, o0000000003e8cc68, C4<0>, C4<0>;
+L_0000000004204b40 .functor OR 1, L_0000000004203c60, L_0000000004204130, C4<0>, C4<0>;
+L_0000000004203f00 .functor BUF 1, L_0000000004204b40, C4<0>, C4<0>, C4<0>;
+v0000000003f0c0c0_0 .net "A1", 0 0, o0000000003e8cba8;  alias, 0 drivers
+v0000000003f0bda0_0 .net "A2", 0 0, o0000000003e8cbd8;  alias, 0 drivers
+v0000000003f0c5c0_0 .net "A3", 0 0, o0000000003e8cc08;  alias, 0 drivers
+v0000000003f0c020_0 .net "B1", 0 0, o0000000003e8cc38;  alias, 0 drivers
+v0000000003f0c660_0 .net "B2", 0 0, o0000000003e8cc68;  alias, 0 drivers
+L_00000000040f7450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0db00_0 .net8 "VGND", 0 0, L_00000000040f7450;  1 drivers, strength-aware
+L_00000000040f7b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0dec0_0 .net8 "VNB", 0 0, L_00000000040f7b50;  1 drivers, strength-aware
+L_00000000040f6b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d1a0_0 .net8 "VPB", 0 0, L_00000000040f6b20;  1 drivers, strength-aware
+L_00000000040f77d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0c700_0 .net8 "VPWR", 0 0, L_00000000040f77d0;  1 drivers, strength-aware
+v0000000003f0cc00_0 .net "Y", 0 0, L_0000000004203f00;  alias, 1 drivers
+v0000000003f0df60_0 .net "nor0_out", 0 0, L_0000000004204130;  1 drivers
+v0000000003f0e000_0 .net "nor1_out", 0 0, L_0000000004203c60;  1 drivers
+v0000000003f0c7a0_0 .net "or0_out_Y", 0 0, L_0000000004204b40;  1 drivers
+S_000000000298b3f0 .scope module, "sky130_fd_sc_hd__o41a_1" "sky130_fd_sc_hd__o41a_1" 4 71368;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8d118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0cb60_0 .net "A1", 0 0, o0000000003e8d118;  0 drivers
+o0000000003e8d148 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0cd40_0 .net "A2", 0 0, o0000000003e8d148;  0 drivers
+o0000000003e8d178 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0ba80_0 .net "A3", 0 0, o0000000003e8d178;  0 drivers
+o0000000003e8d1a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0c520_0 .net "A4", 0 0, o0000000003e8d1a8;  0 drivers
+o0000000003e8d1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0cfc0_0 .net "B1", 0 0, o0000000003e8d1d8;  0 drivers
+L_00000000040f8020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0bb20_0 .net8 "VGND", 0 0, L_00000000040f8020;  1 drivers, strength-aware
+L_00000000040f78b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d060_0 .net8 "VNB", 0 0, L_00000000040f78b0;  1 drivers, strength-aware
+L_00000000040f73e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d100_0 .net8 "VPB", 0 0, L_00000000040f73e0;  1 drivers, strength-aware
+L_00000000040f6f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d240_0 .net8 "VPWR", 0 0, L_00000000040f6f80;  1 drivers, strength-aware
+v0000000003f0bf80_0 .net "X", 0 0, L_0000000004203fe0;  1 drivers
+S_0000000003eeea80 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71390, 4 71708 1, S_000000000298b3f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_00000000042039c0 .functor OR 1, o0000000003e8d1a8, o0000000003e8d178, o0000000003e8d148, o0000000003e8d118;
+L_0000000004203100 .functor AND 1, L_00000000042039c0, o0000000003e8d1d8, C4<1>, C4<1>;
+L_0000000004203fe0 .functor BUF 1, L_0000000004203100, C4<0>, C4<0>, C4<0>;
+v0000000003f0ce80_0 .net "A1", 0 0, o0000000003e8d118;  alias, 0 drivers
+v0000000003f0cf20_0 .net "A2", 0 0, o0000000003e8d148;  alias, 0 drivers
+v0000000003f0b9e0_0 .net "A3", 0 0, o0000000003e8d178;  alias, 0 drivers
+v0000000003f0dce0_0 .net "A4", 0 0, o0000000003e8d1a8;  alias, 0 drivers
+v0000000003f0c160_0 .net "B1", 0 0, o0000000003e8d1d8;  alias, 0 drivers
+L_00000000040f7920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0cde0_0 .net8 "VGND", 0 0, L_00000000040f7920;  1 drivers, strength-aware
+L_00000000040f6e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d7e0_0 .net8 "VNB", 0 0, L_00000000040f6e30;  1 drivers, strength-aware
+L_00000000040f7530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0c980_0 .net8 "VPB", 0 0, L_00000000040f7530;  1 drivers, strength-aware
+L_00000000040f6ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0d740_0 .net8 "VPWR", 0 0, L_00000000040f6ea0;  1 drivers, strength-aware
+v0000000003f0de20_0 .net "X", 0 0, L_0000000004203fe0;  alias, 1 drivers
+v0000000003f0c340_0 .net "and0_out_X", 0 0, L_0000000004203100;  1 drivers
+v0000000003f0c200_0 .net "or0_out", 0 0, L_00000000042039c0;  1 drivers
+S_0000000002988b70 .scope module, "sky130_fd_sc_hd__o41a_2" "sky130_fd_sc_hd__o41a_2" 4 71838;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8d658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0bd00_0 .net "A1", 0 0, o0000000003e8d658;  0 drivers
+o0000000003e8d688 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0be40_0 .net "A2", 0 0, o0000000003e8d688;  0 drivers
+o0000000003e8d6b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0c480_0 .net "A3", 0 0, o0000000003e8d6b8;  0 drivers
+o0000000003e8d6e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0da60_0 .net "A4", 0 0, o0000000003e8d6e8;  0 drivers
+o0000000003e8d718 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0dba0_0 .net "B1", 0 0, o0000000003e8d718;  0 drivers
+L_00000000040f70d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0dc40_0 .net8 "VGND", 0 0, L_00000000040f70d0;  1 drivers, strength-aware
+L_00000000040f7bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0e6e0_0 .net8 "VNB", 0 0, L_00000000040f7bc0;  1 drivers, strength-aware
+L_00000000040f8090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0fae0_0 .net8 "VPB", 0 0, L_00000000040f8090;  1 drivers, strength-aware
+L_00000000040f7370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0fb80_0 .net8 "VPWR", 0 0, L_00000000040f7370;  1 drivers, strength-aware
+v0000000003f0e140_0 .net "X", 0 0, L_0000000004203a30;  1 drivers
+S_0000000003eee000 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71860, 4 71708 1, S_0000000002988b70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004203e90 .functor OR 1, o0000000003e8d6e8, o0000000003e8d6b8, o0000000003e8d688, o0000000003e8d658;
+L_00000000042041a0 .functor AND 1, L_0000000004203e90, o0000000003e8d718, C4<1>, C4<1>;
+L_0000000004203a30 .functor BUF 1, L_00000000042041a0, C4<0>, C4<0>, C4<0>;
+v0000000003f0d880_0 .net "A1", 0 0, o0000000003e8d658;  alias, 0 drivers
+v0000000003f0d920_0 .net "A2", 0 0, o0000000003e8d688;  alias, 0 drivers
+v0000000003f0d380_0 .net "A3", 0 0, o0000000003e8d6b8;  alias, 0 drivers
+v0000000003f0bbc0_0 .net "A4", 0 0, o0000000003e8d6e8;  alias, 0 drivers
+v0000000003f0d420_0 .net "B1", 0 0, o0000000003e8d718;  alias, 0 drivers
+L_00000000040f75a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0dd80_0 .net8 "VGND", 0 0, L_00000000040f75a0;  1 drivers, strength-aware
+L_00000000040f8480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0bee0_0 .net8 "VNB", 0 0, L_00000000040f8480;  1 drivers, strength-aware
+L_00000000040f7610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0c2a0_0 .net8 "VPB", 0 0, L_00000000040f7610;  1 drivers, strength-aware
+L_00000000040f7990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0bc60_0 .net8 "VPWR", 0 0, L_00000000040f7990;  1 drivers, strength-aware
+v0000000003f0d4c0_0 .net "X", 0 0, L_0000000004203a30;  alias, 1 drivers
+v0000000003f0d9c0_0 .net "and0_out_X", 0 0, L_00000000042041a0;  1 drivers
+v0000000003f0c3e0_0 .net "or0_out", 0 0, L_0000000004203e90;  1 drivers
+S_00000000029898f0 .scope module, "sky130_fd_sc_hd__o41a_4" "sky130_fd_sc_hd__o41a_4" 4 71964;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8db98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0e8c0_0 .net "A1", 0 0, o0000000003e8db98;  0 drivers
+o0000000003e8dbc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f10760_0 .net "A2", 0 0, o0000000003e8dbc8;  0 drivers
+o0000000003e8dbf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f9a0_0 .net "A3", 0 0, o0000000003e8dbf8;  0 drivers
+o0000000003e8dc28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0fcc0_0 .net "A4", 0 0, o0000000003e8dc28;  0 drivers
+o0000000003e8dc58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f4a0_0 .net "B1", 0 0, o0000000003e8dc58;  0 drivers
+L_00000000040f8170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0fd60_0 .net8 "VGND", 0 0, L_00000000040f8170;  1 drivers, strength-aware
+L_00000000040f6960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0e500_0 .net8 "VNB", 0 0, L_00000000040f6960;  1 drivers, strength-aware
+L_00000000040f7220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0f7c0_0 .net8 "VPB", 0 0, L_00000000040f7220;  1 drivers, strength-aware
+L_00000000040f6a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f104e0_0 .net8 "VPWR", 0 0, L_00000000040f6a40;  1 drivers, strength-aware
+v0000000003f0f2c0_0 .net "X", 0 0, L_0000000004203aa0;  1 drivers
+S_0000000003ee9680 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71986, 4 71708 1, S_00000000029898f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004204600 .functor OR 1, o0000000003e8dc28, o0000000003e8dbf8, o0000000003e8dbc8, o0000000003e8db98;
+L_0000000004203bf0 .functor AND 1, L_0000000004204600, o0000000003e8dc58, C4<1>, C4<1>;
+L_0000000004203aa0 .functor BUF 1, L_0000000004203bf0, C4<0>, C4<0>, C4<0>;
+v0000000003f0fc20_0 .net "A1", 0 0, o0000000003e8db98;  alias, 0 drivers
+v0000000003f0e1e0_0 .net "A2", 0 0, o0000000003e8dbc8;  alias, 0 drivers
+v0000000003f0fa40_0 .net "A3", 0 0, o0000000003e8dbf8;  alias, 0 drivers
+v0000000003f0f400_0 .net "A4", 0 0, o0000000003e8dc28;  alias, 0 drivers
+v0000000003f0f720_0 .net "B1", 0 0, o0000000003e8dc58;  alias, 0 drivers
+L_00000000040f6ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ffe0_0 .net8 "VGND", 0 0, L_00000000040f6ab0;  1 drivers, strength-aware
+L_00000000040f71b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ea00_0 .net8 "VNB", 0 0, L_00000000040f71b0;  1 drivers, strength-aware
+L_00000000040f7290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ec80_0 .net8 "VPB", 0 0, L_00000000040f7290;  1 drivers, strength-aware
+L_00000000040f6b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0eaa0_0 .net8 "VPWR", 0 0, L_00000000040f6b90;  1 drivers, strength-aware
+v0000000003f0f220_0 .net "X", 0 0, L_0000000004203aa0;  alias, 1 drivers
+v0000000003f0e5a0_0 .net "and0_out_X", 0 0, L_0000000004203bf0;  1 drivers
+v0000000003f0e640_0 .net "or0_out", 0 0, L_0000000004204600;  1 drivers
+S_000000000298bb70 .scope module, "sky130_fd_sc_hd__o41ai_1" "sky130_fd_sc_hd__o41ai_1" 4 34012;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8e0d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f10080_0 .net "A1", 0 0, o0000000003e8e0d8;  0 drivers
+o0000000003e8e108 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f5e0_0 .net "A2", 0 0, o0000000003e8e108;  0 drivers
+o0000000003e8e138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f0e0_0 .net "A3", 0 0, o0000000003e8e138;  0 drivers
+o0000000003e8e168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f101c0_0 .net "A4", 0 0, o0000000003e8e168;  0 drivers
+o0000000003e8e198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f360_0 .net "B1", 0 0, o0000000003e8e198;  0 drivers
+L_00000000040f7a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10260_0 .net8 "VGND", 0 0, L_00000000040f7a00;  1 drivers, strength-aware
+L_00000000040f7140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10300_0 .net8 "VNB", 0 0, L_00000000040f7140;  1 drivers, strength-aware
+L_00000000040f7300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f103a0_0 .net8 "VPB", 0 0, L_00000000040f7300;  1 drivers, strength-aware
+L_00000000040f9600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0e960_0 .net8 "VPWR", 0 0, L_00000000040f9600;  1 drivers, strength-aware
+v0000000003f0e780_0 .net "Y", 0 0, L_0000000004204050;  1 drivers
+S_0000000003eed700 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 34034, 4 33756 1, S_000000000298bb70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004204360 .functor OR 1, o0000000003e8e168, o0000000003e8e138, o0000000003e8e108, o0000000003e8e0d8;
+L_0000000004204c90 .functor NAND 1, o0000000003e8e198, L_0000000004204360, C4<1>, C4<1>;
+L_0000000004204050 .functor BUF 1, L_0000000004204c90, C4<0>, C4<0>, C4<0>;
+v0000000003f0edc0_0 .net "A1", 0 0, o0000000003e8e0d8;  alias, 0 drivers
+v0000000003f0f540_0 .net "A2", 0 0, o0000000003e8e108;  alias, 0 drivers
+v0000000003f0fe00_0 .net "A3", 0 0, o0000000003e8e138;  alias, 0 drivers
+v0000000003f0fea0_0 .net "A4", 0 0, o0000000003e8e168;  alias, 0 drivers
+v0000000003f0ee60_0 .net "B1", 0 0, o0000000003e8e198;  alias, 0 drivers
+L_00000000040f8f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10120_0 .net8 "VGND", 0 0, L_00000000040f8f70;  1 drivers, strength-aware
+L_00000000040f89c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ff40_0 .net8 "VNB", 0 0, L_00000000040f89c0;  1 drivers, strength-aware
+L_00000000040f9d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ed20_0 .net8 "VPB", 0 0, L_00000000040f9d70;  1 drivers, strength-aware
+L_00000000040f8800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ef00_0 .net8 "VPWR", 0 0, L_00000000040f8800;  1 drivers, strength-aware
+v0000000003f0f040_0 .net "Y", 0 0, L_0000000004204050;  alias, 1 drivers
+v0000000003f0e820_0 .net "nand0_out_Y", 0 0, L_0000000004204c90;  1 drivers
+v0000000003f0e280_0 .net "or0_out", 0 0, L_0000000004204360;  1 drivers
+S_000000000298b570 .scope module, "sky130_fd_sc_hd__o41ai_2" "sky130_fd_sc_hd__o41ai_2" 4 33886;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8e618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0e3c0_0 .net "A1", 0 0, o0000000003e8e618;  0 drivers
+o0000000003e8e648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0e460_0 .net "A2", 0 0, o0000000003e8e648;  0 drivers
+o0000000003e8e678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0efa0_0 .net "A3", 0 0, o0000000003e8e678;  0 drivers
+o0000000003e8e6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0f180_0 .net "A4", 0 0, o0000000003e8e6a8;  0 drivers
+o0000000003e8e6d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f11700_0 .net "B1", 0 0, o0000000003e8e6d8;  0 drivers
+L_00000000040f9980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f129c0_0 .net8 "VGND", 0 0, L_00000000040f9980;  1 drivers, strength-aware
+L_00000000040f8d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10da0_0 .net8 "VNB", 0 0, L_00000000040f8d40;  1 drivers, strength-aware
+L_00000000040f8560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f121a0_0 .net8 "VPB", 0 0, L_00000000040f8560;  1 drivers, strength-aware
+L_00000000040f9de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f12240_0 .net8 "VPWR", 0 0, L_00000000040f9de0;  1 drivers, strength-aware
+v0000000003f12380_0 .net "Y", 0 0, L_0000000004204440;  1 drivers
+S_0000000003eeba80 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 33908, 4 33756 1, S_000000000298b570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004203e20 .functor OR 1, o0000000003e8e6a8, o0000000003e8e678, o0000000003e8e648, o0000000003e8e618;
+L_00000000042038e0 .functor NAND 1, o0000000003e8e6d8, L_0000000004203e20, C4<1>, C4<1>;
+L_0000000004204440 .functor BUF 1, L_00000000042038e0, C4<0>, C4<0>, C4<0>;
+v0000000003f0eb40_0 .net "A1", 0 0, o0000000003e8e618;  alias, 0 drivers
+v0000000003f10800_0 .net "A2", 0 0, o0000000003e8e648;  alias, 0 drivers
+v0000000003f10440_0 .net "A3", 0 0, o0000000003e8e678;  alias, 0 drivers
+v0000000003f10580_0 .net "A4", 0 0, o0000000003e8e6a8;  alias, 0 drivers
+v0000000003f0f680_0 .net "B1", 0 0, o0000000003e8e6d8;  alias, 0 drivers
+L_00000000040f9a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10620_0 .net8 "VGND", 0 0, L_00000000040f9a60;  1 drivers, strength-aware
+L_00000000040f91a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ebe0_0 .net8 "VNB", 0 0, L_00000000040f91a0;  1 drivers, strength-aware
+L_00000000040f8640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0f860_0 .net8 "VPB", 0 0, L_00000000040f8640;  1 drivers, strength-aware
+L_00000000040f9c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f106c0_0 .net8 "VPWR", 0 0, L_00000000040f9c20;  1 drivers, strength-aware
+v0000000003f0f900_0 .net "Y", 0 0, L_0000000004204440;  alias, 1 drivers
+v0000000003f108a0_0 .net "nand0_out_Y", 0 0, L_00000000042038e0;  1 drivers
+v0000000003f0e320_0 .net "or0_out", 0 0, L_0000000004203e20;  1 drivers
+S_0000000002989170 .scope module, "sky130_fd_sc_hd__o41ai_4" "sky130_fd_sc_hd__o41ai_4" 4 34138;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+o0000000003e8eb58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f12b00_0 .net "A1", 0 0, o0000000003e8eb58;  0 drivers
+o0000000003e8eb88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f12e20_0 .net "A2", 0 0, o0000000003e8eb88;  0 drivers
+o0000000003e8ebb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f12c40_0 .net "A3", 0 0, o0000000003e8ebb8;  0 drivers
+o0000000003e8ebe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f12600_0 .net "A4", 0 0, o0000000003e8ebe8;  0 drivers
+o0000000003e8ec18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f10e40_0 .net "B1", 0 0, o0000000003e8ec18;  0 drivers
+L_00000000040f8e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f118e0_0 .net8 "VGND", 0 0, L_00000000040f8e90;  1 drivers, strength-aware
+L_00000000040f9050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12ec0_0 .net8 "VNB", 0 0, L_00000000040f9050;  1 drivers, strength-aware
+L_00000000040f92f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11200_0 .net8 "VPB", 0 0, L_00000000040f92f0;  1 drivers, strength-aware
+L_00000000040f98a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f10c60_0 .net8 "VPWR", 0 0, L_00000000040f98a0;  1 drivers, strength-aware
+v0000000003f115c0_0 .net "Y", 0 0, L_0000000004204280;  1 drivers
+S_0000000003eecc80 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 34160, 4 33756 1, S_0000000002989170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A1"
+    .port_info 2 /INPUT 1 "A2"
+    .port_info 3 /INPUT 1 "A3"
+    .port_info 4 /INPUT 1 "A4"
+    .port_info 5 /INPUT 1 "B1"
+L_0000000004203b10 .functor OR 1, o0000000003e8ebe8, o0000000003e8ebb8, o0000000003e8eb88, o0000000003e8eb58;
+L_0000000004203250 .functor NAND 1, o0000000003e8ec18, L_0000000004203b10, C4<1>, C4<1>;
+L_0000000004204280 .functor BUF 1, L_0000000004203250, C4<0>, C4<0>, C4<0>;
+v0000000003f10d00_0 .net "A1", 0 0, o0000000003e8eb58;  alias, 0 drivers
+v0000000003f11980_0 .net "A2", 0 0, o0000000003e8eb88;  alias, 0 drivers
+v0000000003f113e0_0 .net "A3", 0 0, o0000000003e8ebb8;  alias, 0 drivers
+v0000000003f11840_0 .net "A4", 0 0, o0000000003e8ebe8;  alias, 0 drivers
+v0000000003f10ee0_0 .net "B1", 0 0, o0000000003e8ec18;  alias, 0 drivers
+L_00000000040f9ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f122e0_0 .net8 "VGND", 0 0, L_00000000040f9ec0;  1 drivers, strength-aware
+L_00000000040f8aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f11de0_0 .net8 "VNB", 0 0, L_00000000040f8aa0;  1 drivers, strength-aware
+L_00000000040f93d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f12a60_0 .net8 "VPB", 0 0, L_00000000040f93d0;  1 drivers, strength-aware
+L_00000000040f9910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f10bc0_0 .net8 "VPWR", 0 0, L_00000000040f9910;  1 drivers, strength-aware
+v0000000003f12560_0 .net "Y", 0 0, L_0000000004204280;  alias, 1 drivers
+v0000000003f12ba0_0 .net "nand0_out_Y", 0 0, L_0000000004203250;  1 drivers
+v0000000003f117a0_0 .net "or0_out", 0 0, L_0000000004203b10;  1 drivers
+S_000000000298c170 .scope module, "sky130_fd_sc_hd__or2_0" "sky130_fd_sc_hd__or2_0" 4 32925;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003e8f098 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f11a20_0 .net "A", 0 0, o0000000003e8f098;  0 drivers
+o0000000003e8f0c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f11d40_0 .net "B", 0 0, o0000000003e8f0c8;  0 drivers
+L_00000000040f8870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12f60_0 .net8 "VGND", 0 0, L_00000000040f8870;  1 drivers, strength-aware
+L_00000000040f8950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f11ac0_0 .net8 "VNB", 0 0, L_00000000040f8950;  1 drivers, strength-aware
+L_00000000040f9830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11b60_0 .net8 "VPB", 0 0, L_00000000040f9830;  1 drivers, strength-aware
+L_00000000040f99f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f13000_0 .net8 "VPWR", 0 0, L_00000000040f99f0;  1 drivers, strength-aware
+v0000000003f130a0_0 .net "X", 0 0, L_0000000004203cd0;  1 drivers
+S_0000000003eed280 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32941, 4 32814 1, S_000000000298c170;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004204980 .functor OR 1, o0000000003e8f0c8, o0000000003e8f098, C4<0>, C4<0>;
+L_0000000004203cd0 .functor BUF 1, L_0000000004204980, C4<0>, C4<0>, C4<0>;
+v0000000003f11480_0 .net "A", 0 0, o0000000003e8f098;  alias, 0 drivers
+v0000000003f124c0_0 .net "B", 0 0, o0000000003e8f0c8;  alias, 0 drivers
+L_00000000040f85d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f11f20_0 .net8 "VGND", 0 0, L_00000000040f85d0;  1 drivers, strength-aware
+L_00000000040f9ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12880_0 .net8 "VNB", 0 0, L_00000000040f9ad0;  1 drivers, strength-aware
+L_00000000040f9670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f12d80_0 .net8 "VPB", 0 0, L_00000000040f9670;  1 drivers, strength-aware
+L_00000000040f9e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f126a0_0 .net8 "VPWR", 0 0, L_00000000040f9e50;  1 drivers, strength-aware
+v0000000003f12ce0_0 .net "X", 0 0, L_0000000004203cd0;  alias, 1 drivers
+v0000000003f10f80_0 .net "or0_out_X", 0 0, L_0000000004204980;  1 drivers
+S_0000000002988ff0 .scope module, "sky130_fd_sc_hd__or2_1" "sky130_fd_sc_hd__or2_1" 4 32411;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003e8f3f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f127e0_0 .net "A", 0 0, o0000000003e8f3f8;  0 drivers
+o0000000003e8f428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f11020_0 .net "B", 0 0, o0000000003e8f428;  0 drivers
+L_00000000040f9f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f10a80_0 .net8 "VGND", 0 0, L_00000000040f9f30;  1 drivers, strength-aware
+L_00000000040f96e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12920_0 .net8 "VNB", 0 0, L_00000000040f96e0;  1 drivers, strength-aware
+L_00000000040f9b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11520_0 .net8 "VPB", 0 0, L_00000000040f9b40;  1 drivers, strength-aware
+L_00000000040f9360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f112a0_0 .net8 "VPWR", 0 0, L_00000000040f9360;  1 drivers, strength-aware
+v0000000003f10b20_0 .net "X", 0 0, L_00000000042043d0;  1 drivers
+S_0000000003eea280 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32427, 4 32814 1, S_0000000002988ff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_0000000004204210 .functor OR 1, o0000000003e8f428, o0000000003e8f3f8, C4<0>, C4<0>;
+L_00000000042043d0 .functor BUF 1, L_0000000004204210, C4<0>, C4<0>, C4<0>;
+v0000000003f10940_0 .net "A", 0 0, o0000000003e8f3f8;  alias, 0 drivers
+v0000000003f11c00_0 .net "B", 0 0, o0000000003e8f428;  alias, 0 drivers
+L_00000000040f9440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12420_0 .net8 "VGND", 0 0, L_00000000040f9440;  1 drivers, strength-aware
+L_00000000040f8bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f109e0_0 .net8 "VNB", 0 0, L_00000000040f8bf0;  1 drivers, strength-aware
+L_00000000040f90c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11660_0 .net8 "VPB", 0 0, L_00000000040f90c0;  1 drivers, strength-aware
+L_00000000040f9750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f12740_0 .net8 "VPWR", 0 0, L_00000000040f9750;  1 drivers, strength-aware
+v0000000003f11fc0_0 .net "X", 0 0, L_00000000042043d0;  alias, 1 drivers
+v0000000003f11e80_0 .net "or0_out_X", 0 0, L_0000000004204210;  1 drivers
+S_000000000298b6f0 .scope module, "sky130_fd_sc_hd__or2_4" "sky130_fd_sc_hd__or2_4" 4 32517;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003e8f758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f13b40_0 .net "A", 0 0, o0000000003e8f758;  0 drivers
+o0000000003e8f788 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f14e00_0 .net "B", 0 0, o0000000003e8f788;  0 drivers
+L_00000000040f8720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f145e0_0 .net8 "VGND", 0 0, L_00000000040f8720;  1 drivers, strength-aware
+L_00000000040f94b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f14c20_0 .net8 "VNB", 0 0, L_00000000040f94b0;  1 drivers, strength-aware
+L_00000000040f9bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f144a0_0 .net8 "VPB", 0 0, L_00000000040f9bb0;  1 drivers, strength-aware
+L_00000000040f9520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f140e0_0 .net8 "VPWR", 0 0, L_00000000040f9520;  1 drivers, strength-aware
+v0000000003f14540_0 .net "X", 0 0, L_0000000004204a60;  1 drivers
+S_0000000003eeae80 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32533, 4 32814 1, S_000000000298b6f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_00000000042049f0 .functor OR 1, o0000000003e8f788, o0000000003e8f758, C4<0>, C4<0>;
+L_0000000004204a60 .functor BUF 1, L_00000000042049f0, C4<0>, C4<0>, C4<0>;
+v0000000003f110c0_0 .net "A", 0 0, o0000000003e8f758;  alias, 0 drivers
+v0000000003f11ca0_0 .net "B", 0 0, o0000000003e8f788;  alias, 0 drivers
+L_00000000040f8fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12060_0 .net8 "VGND", 0 0, L_00000000040f8fe0;  1 drivers, strength-aware
+L_00000000040f8b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f12100_0 .net8 "VNB", 0 0, L_00000000040f8b10;  1 drivers, strength-aware
+L_00000000040f9590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11160_0 .net8 "VPB", 0 0, L_00000000040f9590;  1 drivers, strength-aware
+L_00000000040f88e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f11340_0 .net8 "VPWR", 0 0, L_00000000040f88e0;  1 drivers, strength-aware
+v0000000003f14b80_0 .net "X", 0 0, L_0000000004204a60;  alias, 1 drivers
+v0000000003f14d60_0 .net "or0_out_X", 0 0, L_00000000042049f0;  1 drivers
+S_0000000002989a70 .scope module, "sky130_fd_sc_hd__or2b_1" "sky130_fd_sc_hd__or2b_1" 4 56612;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+o0000000003e8fab8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f14ae0_0 .net "A", 0 0, o0000000003e8fab8;  0 drivers
+o0000000003e8fae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15080_0 .net "B_N", 0 0, o0000000003e8fae8;  0 drivers
+L_00000000040f9130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f15760_0 .net8 "VGND", 0 0, L_00000000040f9130;  1 drivers, strength-aware
+L_00000000040f8a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f14720_0 .net8 "VNB", 0 0, L_00000000040f8a30;  1 drivers, strength-aware
+L_00000000040f8b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f154e0_0 .net8 "VPB", 0 0, L_00000000040f8b80;  1 drivers, strength-aware
+L_00000000040f97c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f142c0_0 .net8 "VPWR", 0 0, L_00000000040f97c0;  1 drivers, strength-aware
+v0000000003f15800_0 .net "X", 0 0, L_0000000004204520;  1 drivers
+S_0000000003eecf80 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56628, 4 56915 1, S_0000000002989a70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_00000000042044b0 .functor NOT 1, o0000000003e8fae8, C4<0>, C4<0>, C4<0>;
+L_0000000004203640 .functor OR 1, L_00000000042044b0, o0000000003e8fab8, C4<0>, C4<0>;
+L_0000000004204520 .functor BUF 1, L_0000000004203640, C4<0>, C4<0>, C4<0>;
+v0000000003f13c80_0 .net "A", 0 0, o0000000003e8fab8;  alias, 0 drivers
+v0000000003f14f40_0 .net "B_N", 0 0, o0000000003e8fae8;  alias, 0 drivers
+L_00000000040f9c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f138c0_0 .net8 "VGND", 0 0, L_00000000040f9c90;  1 drivers, strength-aware
+L_00000000040f9210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f135a0_0 .net8 "VNB", 0 0, L_00000000040f9210;  1 drivers, strength-aware
+L_00000000040f9280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14ea0_0 .net8 "VPB", 0 0, L_00000000040f9280;  1 drivers, strength-aware
+L_00000000040fa010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14680_0 .net8 "VPWR", 0 0, L_00000000040fa010;  1 drivers, strength-aware
+v0000000003f14360_0 .net "X", 0 0, L_0000000004204520;  alias, 1 drivers
+v0000000003f13960_0 .net "not0_out", 0 0, L_00000000042044b0;  1 drivers
+v0000000003f15300_0 .net "or0_out_X", 0 0, L_0000000004203640;  1 drivers
+S_000000000298b870 .scope module, "sky130_fd_sc_hd__or2b_4" "sky130_fd_sc_hd__or2b_4" 4 56506;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+o0000000003e8fe48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f147c0_0 .net "A", 0 0, o0000000003e8fe48;  0 drivers
+o0000000003e8fe78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f13460_0 .net "B_N", 0 0, o0000000003e8fe78;  0 drivers
+L_00000000040f9d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f156c0_0 .net8 "VGND", 0 0, L_00000000040f9d00;  1 drivers, strength-aware
+L_00000000040f9fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f13a00_0 .net8 "VNB", 0 0, L_00000000040f9fa0;  1 drivers, strength-aware
+L_00000000040fa080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14860_0 .net8 "VPB", 0 0, L_00000000040fa080;  1 drivers, strength-aware
+L_00000000040f84f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14900_0 .net8 "VPWR", 0 0, L_00000000040f84f0;  1 drivers, strength-aware
+v0000000003f13be0_0 .net "X", 0 0, L_00000000042046e0;  1 drivers
+S_0000000003eeab80 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56522, 4 56915 1, S_000000000298b870;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B_N"
+L_0000000004204590 .functor NOT 1, o0000000003e8fe78, C4<0>, C4<0>, C4<0>;
+L_00000000042032c0 .functor OR 1, L_0000000004204590, o0000000003e8fe48, C4<0>, C4<0>;
+L_00000000042046e0 .functor BUF 1, L_00000000042032c0, C4<0>, C4<0>, C4<0>;
+v0000000003f133c0_0 .net "A", 0 0, o0000000003e8fe48;  alias, 0 drivers
+v0000000003f14fe0_0 .net "B_N", 0 0, o0000000003e8fe78;  alias, 0 drivers
+L_00000000040f8e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f15120_0 .net8 "VGND", 0 0, L_00000000040f8e20;  1 drivers, strength-aware
+L_00000000040f86b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f15580_0 .net8 "VNB", 0 0, L_00000000040f86b0;  1 drivers, strength-aware
+L_00000000040f8790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f13f00_0 .net8 "VPB", 0 0, L_00000000040f8790;  1 drivers, strength-aware
+L_00000000040f8db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f151c0_0 .net8 "VPWR", 0 0, L_00000000040f8db0;  1 drivers, strength-aware
+v0000000003f13640_0 .net "X", 0 0, L_00000000042046e0;  alias, 1 drivers
+v0000000003f149a0_0 .net "not0_out", 0 0, L_0000000004204590;  1 drivers
+v0000000003f14a40_0 .net "or0_out_X", 0 0, L_00000000042032c0;  1 drivers
+S_000000000298a670 .scope module, "sky130_fd_sc_hd__or3_1" "sky130_fd_sc_hd__or3_1" 4 49789;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003e901d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15440_0 .net "A", 0 0, o0000000003e901d8;  0 drivers
+o0000000003e90208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15620_0 .net "B", 0 0, o0000000003e90208;  0 drivers
+o0000000003e90238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f158a0_0 .net "C", 0 0, o0000000003e90238;  0 drivers
+L_00000000040f8f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f13fa0_0 .net8 "VGND", 0 0, L_00000000040f8f00;  1 drivers, strength-aware
+L_00000000040f8c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f136e0_0 .net8 "VNB", 0 0, L_00000000040f8c60;  1 drivers, strength-aware
+L_00000000040f8cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14040_0 .net8 "VPB", 0 0, L_00000000040f8cd0;  1 drivers, strength-aware
+L_00000000040fb890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f13140_0 .net8 "VPWR", 0 0, L_00000000040fb890;  1 drivers, strength-aware
+v0000000003f131e0_0 .net "X", 0 0, L_0000000004203560;  1 drivers
+S_0000000003eea400 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49807, 4 49673 1, S_000000000298a670;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004203720 .functor OR 1, o0000000003e90208, o0000000003e901d8, o0000000003e90238, C4<0>;
+L_0000000004203560 .functor BUF 1, L_0000000004203720, C4<0>, C4<0>, C4<0>;
+v0000000003f15260_0 .net "A", 0 0, o0000000003e901d8;  alias, 0 drivers
+v0000000003f13500_0 .net "B", 0 0, o0000000003e90208;  alias, 0 drivers
+v0000000003f153a0_0 .net "C", 0 0, o0000000003e90238;  alias, 0 drivers
+L_00000000040fbc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f13d20_0 .net8 "VGND", 0 0, L_00000000040fbc10;  1 drivers, strength-aware
+L_00000000040fb3c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f13aa0_0 .net8 "VNB", 0 0, L_00000000040fb3c0;  1 drivers, strength-aware
+L_00000000040faa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f13dc0_0 .net8 "VPB", 0 0, L_00000000040faa20;  1 drivers, strength-aware
+L_00000000040fb900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f13e60_0 .net8 "VPWR", 0 0, L_00000000040fb900;  1 drivers, strength-aware
+v0000000003f14cc0_0 .net "X", 0 0, L_0000000004203560;  alias, 1 drivers
+v0000000003f14180_0 .net "or0_out_X", 0 0, L_0000000004203720;  1 drivers
+S_000000000298bcf0 .scope module, "sky130_fd_sc_hd__or3_4" "sky130_fd_sc_hd__or3_4" 4 49367;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003e905c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f174c0_0 .net "A", 0 0, o0000000003e905c8;  0 drivers
+o0000000003e905f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f16ac0_0 .net "B", 0 0, o0000000003e905f8;  0 drivers
+o0000000003e90628 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f167a0_0 .net "C", 0 0, o0000000003e90628;  0 drivers
+L_00000000040fa860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f179c0_0 .net8 "VGND", 0 0, L_00000000040fa860;  1 drivers, strength-aware
+L_00000000040fa4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f15da0_0 .net8 "VNB", 0 0, L_00000000040fa4e0;  1 drivers, strength-aware
+L_00000000040fbc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f16520_0 .net8 "VPB", 0 0, L_00000000040fbc80;  1 drivers, strength-aware
+L_00000000040fb7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f16660_0 .net8 "VPWR", 0 0, L_00000000040fb7b0;  1 drivers, strength-aware
+v0000000003f17380_0 .net "X", 0 0, L_00000000042035d0;  1 drivers
+S_0000000003eeef00 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49385, 4 49673 1, S_000000000298bcf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_0000000004203330 .functor OR 1, o0000000003e905f8, o0000000003e905c8, o0000000003e90628, C4<0>;
+L_00000000042035d0 .functor BUF 1, L_0000000004203330, C4<0>, C4<0>, C4<0>;
+v0000000003f13280_0 .net "A", 0 0, o0000000003e905c8;  alias, 0 drivers
+v0000000003f13780_0 .net "B", 0 0, o0000000003e905f8;  alias, 0 drivers
+v0000000003f13320_0 .net "C", 0 0, o0000000003e90628;  alias, 0 drivers
+L_00000000040faef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f13820_0 .net8 "VGND", 0 0, L_00000000040faef0;  1 drivers, strength-aware
+L_00000000040fa6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f14220_0 .net8 "VNB", 0 0, L_00000000040fa6a0;  1 drivers, strength-aware
+L_00000000040faf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f14400_0 .net8 "VPB", 0 0, L_00000000040faf60;  1 drivers, strength-aware
+L_00000000040fabe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f165c0_0 .net8 "VPWR", 0 0, L_00000000040fabe0;  1 drivers, strength-aware
+v0000000003f16480_0 .net "X", 0 0, L_00000000042035d0;  alias, 1 drivers
+v0000000003f16700_0 .net "or0_out_X", 0 0, L_0000000004203330;  1 drivers
+S_0000000002989bf0 .scope module, "sky130_fd_sc_hd__or3b_1" "sky130_fd_sc_hd__or3b_1" 4 36996;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003e909b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f16200_0 .net "A", 0 0, o0000000003e909b8;  0 drivers
+o0000000003e909e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f16980_0 .net "B", 0 0, o0000000003e909e8;  0 drivers
+o0000000003e90a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f17560_0 .net "C_N", 0 0, o0000000003e90a18;  0 drivers
+L_00000000040fa400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f16a20_0 .net8 "VGND", 0 0, L_00000000040fa400;  1 drivers, strength-aware
+L_00000000040faa90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17e20_0 .net8 "VNB", 0 0, L_00000000040faa90;  1 drivers, strength-aware
+L_00000000040fafd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f17b00_0 .net8 "VPB", 0 0, L_00000000040fafd0;  1 drivers, strength-aware
+L_00000000040fb820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f17ce0_0 .net8 "VPWR", 0 0, L_00000000040fb820;  1 drivers, strength-aware
+v0000000003f16b60_0 .net "X", 0 0, L_0000000004204830;  1 drivers
+S_0000000003ee9800 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 37014, 4 36878 1, S_0000000002989bf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_0000000004204750 .functor NOT 1, o0000000003e90a18, C4<0>, C4<0>, C4<0>;
+L_00000000042047c0 .functor OR 1, o0000000003e909e8, o0000000003e909b8, L_0000000004204750, C4<0>;
+L_0000000004204830 .functor BUF 1, L_00000000042047c0, C4<0>, C4<0>, C4<0>;
+v0000000003f16840_0 .net "A", 0 0, o0000000003e909b8;  alias, 0 drivers
+v0000000003f16e80_0 .net "B", 0 0, o0000000003e909e8;  alias, 0 drivers
+v0000000003f16f20_0 .net "C_N", 0 0, o0000000003e90a18;  alias, 0 drivers
+L_00000000040fae10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f15940_0 .net8 "VGND", 0 0, L_00000000040fae10;  1 drivers, strength-aware
+L_00000000040fb9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f168e0_0 .net8 "VNB", 0 0, L_00000000040fb9e0;  1 drivers, strength-aware
+L_00000000040fb430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f16160_0 .net8 "VPB", 0 0, L_00000000040fb430;  1 drivers, strength-aware
+L_00000000040fb4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f171a0_0 .net8 "VPWR", 0 0, L_00000000040fb4a0;  1 drivers, strength-aware
+v0000000003f16de0_0 .net "X", 0 0, L_0000000004204830;  alias, 1 drivers
+v0000000003f17a60_0 .net "not0_out", 0 0, L_0000000004204750;  1 drivers
+v0000000003f17740_0 .net "or0_out_X", 0 0, L_00000000042047c0;  1 drivers
+S_000000000298a070 .scope module, "sky130_fd_sc_hd__or3b_2" "sky130_fd_sc_hd__or3b_2" 4 36566;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003e90dd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f17d80_0 .net "A", 0 0, o0000000003e90dd8;  0 drivers
+o0000000003e90e08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15e40_0 .net "B", 0 0, o0000000003e90e08;  0 drivers
+o0000000003e90e38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15c60_0 .net "C_N", 0 0, o0000000003e90e38;  0 drivers
+L_00000000040fa1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f16ca0_0 .net8 "VGND", 0 0, L_00000000040fa1d0;  1 drivers, strength-aware
+L_00000000040fb510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17060_0 .net8 "VNB", 0 0, L_00000000040fb510;  1 drivers, strength-aware
+L_00000000040fb270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f15ee0_0 .net8 "VPB", 0 0, L_00000000040fb270;  1 drivers, strength-aware
+L_00000000040fba50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f17100_0 .net8 "VPWR", 0 0, L_00000000040fba50;  1 drivers, strength-aware
+v0000000003f172e0_0 .net "X", 0 0, L_0000000004203870;  1 drivers
+S_0000000003eebc00 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 36584, 4 36878 1, S_000000000298a070;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_0000000004203790 .functor NOT 1, o0000000003e90e38, C4<0>, C4<0>, C4<0>;
+L_0000000004203800 .functor OR 1, o0000000003e90e08, o0000000003e90dd8, L_0000000004203790, C4<0>;
+L_0000000004203870 .functor BUF 1, L_0000000004203800, C4<0>, C4<0>, C4<0>;
+v0000000003f16c00_0 .net "A", 0 0, o0000000003e90dd8;  alias, 0 drivers
+v0000000003f17240_0 .net "B", 0 0, o0000000003e90e08;  alias, 0 drivers
+v0000000003f17600_0 .net "C_N", 0 0, o0000000003e90e38;  alias, 0 drivers
+L_00000000040fbac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17880_0 .net8 "VGND", 0 0, L_00000000040fbac0;  1 drivers, strength-aware
+L_00000000040fb2e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17ba0_0 .net8 "VNB", 0 0, L_00000000040fb2e0;  1 drivers, strength-aware
+L_00000000040fb5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f15a80_0 .net8 "VPB", 0 0, L_00000000040fb5f0;  1 drivers, strength-aware
+L_00000000040fb040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f176a0_0 .net8 "VPWR", 0 0, L_00000000040fb040;  1 drivers, strength-aware
+v0000000003f177e0_0 .net "X", 0 0, L_0000000004203870;  alias, 1 drivers
+v0000000003f16d40_0 .net "not0_out", 0 0, L_0000000004203790;  1 drivers
+v0000000003f16fc0_0 .net "or0_out_X", 0 0, L_0000000004203800;  1 drivers
+S_000000000298bff0 .scope module, "sky130_fd_sc_hd__or3b_4" "sky130_fd_sc_hd__or3b_4" 4 36454;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+o0000000003e911f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f180a0_0 .net "A", 0 0, o0000000003e911f8;  0 drivers
+o0000000003e91228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15d00_0 .net "B", 0 0, o0000000003e91228;  0 drivers
+o0000000003e91258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f15f80_0 .net "C_N", 0 0, o0000000003e91258;  0 drivers
+L_00000000040fb0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f16020_0 .net8 "VGND", 0 0, L_00000000040fb0b0;  1 drivers, strength-aware
+L_00000000040fa7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f160c0_0 .net8 "VNB", 0 0, L_00000000040fa7f0;  1 drivers, strength-aware
+L_00000000040fac50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f16340_0 .net8 "VPB", 0 0, L_00000000040fac50;  1 drivers, strength-aware
+L_00000000040fb350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f163e0_0 .net8 "VPWR", 0 0, L_00000000040fb350;  1 drivers, strength-aware
+v0000000003f18a00_0 .net "X", 0 0, L_0000000004205860;  1 drivers
+S_0000000003ee9080 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 36472, 4 36878 1, S_000000000298bff0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+L_0000000004205240 .functor NOT 1, o0000000003e91258, C4<0>, C4<0>, C4<0>;
+L_0000000004205940 .functor OR 1, o0000000003e91228, o0000000003e911f8, L_0000000004205240, C4<0>;
+L_0000000004205860 .functor BUF 1, L_0000000004205940, C4<0>, C4<0>, C4<0>;
+v0000000003f17420_0 .net "A", 0 0, o0000000003e911f8;  alias, 0 drivers
+v0000000003f17ec0_0 .net "B", 0 0, o0000000003e91228;  alias, 0 drivers
+v0000000003f17f60_0 .net "C_N", 0 0, o0000000003e91258;  alias, 0 drivers
+L_00000000040fa320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17920_0 .net8 "VGND", 0 0, L_00000000040fa320;  1 drivers, strength-aware
+L_00000000040fb120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f17c40_0 .net8 "VNB", 0 0, L_00000000040fb120;  1 drivers, strength-aware
+L_00000000040fb580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f159e0_0 .net8 "VPB", 0 0, L_00000000040fb580;  1 drivers, strength-aware
+L_00000000040fb190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f18000_0 .net8 "VPWR", 0 0, L_00000000040fb190;  1 drivers, strength-aware
+v0000000003f15b20_0 .net "X", 0 0, L_0000000004205860;  alias, 1 drivers
+v0000000003f162a0_0 .net "not0_out", 0 0, L_0000000004205240;  1 drivers
+v0000000003f15bc0_0 .net "or0_out_X", 0 0, L_0000000004205940;  1 drivers
+S_000000000298c2f0 .scope module, "sky130_fd_sc_hd__or4_1" "sky130_fd_sc_hd__or4_1" 4 87540;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003e91618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f19fe0_0 .net "A", 0 0, o0000000003e91618;  0 drivers
+o0000000003e91648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f19540_0 .net "B", 0 0, o0000000003e91648;  0 drivers
+o0000000003e91678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f19680_0 .net "C", 0 0, o0000000003e91678;  0 drivers
+o0000000003e916a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1a580_0 .net "D", 0 0, o0000000003e916a8;  0 drivers
+L_00000000040facc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f192c0_0 .net8 "VGND", 0 0, L_00000000040facc0;  1 drivers, strength-aware
+L_00000000040fa710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a4e0_0 .net8 "VNB", 0 0, L_00000000040fa710;  1 drivers, strength-aware
+L_00000000040fb200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f185a0_0 .net8 "VPB", 0 0, L_00000000040fb200;  1 drivers, strength-aware
+L_00000000040fa470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a760_0 .net8 "VPWR", 0 0, L_00000000040fa470;  1 drivers, strength-aware
+v0000000003f18640_0 .net "X", 0 0, L_00000000042066d0;  1 drivers
+S_0000000003ee9b00 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87560, 4 87301 1, S_000000000298c2f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004204d00 .functor OR 1, o0000000003e916a8, o0000000003e91678, o0000000003e91648, o0000000003e91618;
+L_00000000042066d0 .functor BUF 1, L_0000000004204d00, C4<0>, C4<0>, C4<0>;
+v0000000003f194a0_0 .net "A", 0 0, o0000000003e91618;  alias, 0 drivers
+v0000000003f18dc0_0 .net "B", 0 0, o0000000003e91648;  alias, 0 drivers
+v0000000003f1a300_0 .net "C", 0 0, o0000000003e91678;  alias, 0 drivers
+v0000000003f19860_0 .net "D", 0 0, o0000000003e916a8;  alias, 0 drivers
+L_00000000040fad30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f195e0_0 .net8 "VGND", 0 0, L_00000000040fad30;  1 drivers, strength-aware
+L_00000000040fa550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f181e0_0 .net8 "VNB", 0 0, L_00000000040fa550;  1 drivers, strength-aware
+L_00000000040fa5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a080_0 .net8 "VPB", 0 0, L_00000000040fa5c0;  1 drivers, strength-aware
+L_00000000040fb660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a800_0 .net8 "VPWR", 0 0, L_00000000040fb660;  1 drivers, strength-aware
+v0000000003f19cc0_0 .net "X", 0 0, L_00000000042066d0;  alias, 1 drivers
+v0000000003f1a120_0 .net "or0_out_X", 0 0, L_0000000004204d00;  1 drivers
+S_0000000002988570 .scope module, "sky130_fd_sc_hd__or4_4" "sky130_fd_sc_hd__or4_4" 4 86986;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+o0000000003e91a98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f18aa0_0 .net "A", 0 0, o0000000003e91a98;  0 drivers
+o0000000003e91ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1a1c0_0 .net "B", 0 0, o0000000003e91ac8;  0 drivers
+o0000000003e91af8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1a260_0 .net "C", 0 0, o0000000003e91af8;  0 drivers
+o0000000003e91b28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f19720_0 .net "D", 0 0, o0000000003e91b28;  0 drivers
+L_00000000040fb6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f19040_0 .net8 "VGND", 0 0, L_00000000040fb6d0;  1 drivers, strength-aware
+L_00000000040fab70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f197c0_0 .net8 "VNB", 0 0, L_00000000040fab70;  1 drivers, strength-aware
+L_00000000040fada0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f19400_0 .net8 "VPB", 0 0, L_00000000040fada0;  1 drivers, strength-aware
+L_00000000040fa0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f19900_0 .net8 "VPWR", 0 0, L_00000000040fa0f0;  1 drivers, strength-aware
+v0000000003f19b80_0 .net "X", 0 0, L_0000000004206040;  1 drivers
+S_0000000003eec080 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87006, 4 87301 1, S_0000000002988570;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D"
+L_0000000004206820 .functor OR 1, o0000000003e91b28, o0000000003e91af8, o0000000003e91ac8, o0000000003e91a98;
+L_0000000004206040 .functor BUF 1, L_0000000004206820, C4<0>, C4<0>, C4<0>;
+v0000000003f18e60_0 .net "A", 0 0, o0000000003e91a98;  alias, 0 drivers
+v0000000003f18c80_0 .net "B", 0 0, o0000000003e91ac8;  alias, 0 drivers
+v0000000003f19e00_0 .net "C", 0 0, o0000000003e91af8;  alias, 0 drivers
+v0000000003f1a620_0 .net "D", 0 0, o0000000003e91b28;  alias, 0 drivers
+L_00000000040fae80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f18460_0 .net8 "VGND", 0 0, L_00000000040fae80;  1 drivers, strength-aware
+L_00000000040fb740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f18d20_0 .net8 "VNB", 0 0, L_00000000040fb740;  1 drivers, strength-aware
+L_00000000040fb970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a6c0_0 .net8 "VPB", 0 0, L_00000000040fb970;  1 drivers, strength-aware
+L_00000000040fbb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f18f00_0 .net8 "VPWR", 0 0, L_00000000040fbb30;  1 drivers, strength-aware
+v0000000003f19220_0 .net "X", 0 0, L_0000000004206040;  alias, 1 drivers
+v0000000003f19d60_0 .net "or0_out_X", 0 0, L_0000000004206820;  1 drivers
+S_000000000298b9f0 .scope module, "sky130_fd_sc_hd__or4b_1" "sky130_fd_sc_hd__or4b_1" 4 18133;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e91f18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f18140_0 .net "A", 0 0, o0000000003e91f18;  0 drivers
+o0000000003e91f48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f19f40_0 .net "B", 0 0, o0000000003e91f48;  0 drivers
+o0000000003e91f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1a440_0 .net "C", 0 0, o0000000003e91f78;  0 drivers
+o0000000003e91fa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f190e0_0 .net "D_N", 0 0, o0000000003e91fa8;  0 drivers
+L_00000000040fab00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a8a0_0 .net8 "VGND", 0 0, L_00000000040fab00;  1 drivers, strength-aware
+L_00000000040fbba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f18280_0 .net8 "VNB", 0 0, L_00000000040fbba0;  1 drivers, strength-aware
+L_00000000040fa160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f18320_0 .net8 "VPB", 0 0, L_00000000040fa160;  1 drivers, strength-aware
+L_00000000040fa9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f183c0_0 .net8 "VPWR", 0 0, L_00000000040fa9b0;  1 drivers, strength-aware
+v0000000003f19360_0 .net "X", 0 0, L_00000000042062e0;  1 drivers
+S_0000000003ee9980 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 18153, 4 17892 1, S_000000000298b9f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004206430 .functor NOT 1, o0000000003e91fa8, C4<0>, C4<0>, C4<0>;
+L_00000000042060b0 .functor OR 1, L_0000000004206430, o0000000003e91f78, o0000000003e91f48, o0000000003e91f18;
+L_00000000042062e0 .functor BUF 1, L_00000000042060b0, C4<0>, C4<0>, C4<0>;
+v0000000003f186e0_0 .net "A", 0 0, o0000000003e91f18;  alias, 0 drivers
+v0000000003f18fa0_0 .net "B", 0 0, o0000000003e91f48;  alias, 0 drivers
+v0000000003f18820_0 .net "C", 0 0, o0000000003e91f78;  alias, 0 drivers
+v0000000003f188c0_0 .net "D_N", 0 0, o0000000003e91fa8;  alias, 0 drivers
+L_00000000040fa240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a3a0_0 .net8 "VGND", 0 0, L_00000000040fa240;  1 drivers, strength-aware
+L_00000000040fa2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f199a0_0 .net8 "VNB", 0 0, L_00000000040fa2b0;  1 drivers, strength-aware
+L_00000000040fa390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f19a40_0 .net8 "VPB", 0 0, L_00000000040fa390;  1 drivers, strength-aware
+L_00000000040fa630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f19ae0_0 .net8 "VPWR", 0 0, L_00000000040fa630;  1 drivers, strength-aware
+v0000000003f19c20_0 .net "X", 0 0, L_00000000042062e0;  alias, 1 drivers
+v0000000003f19ea0_0 .net "not0_out", 0 0, L_0000000004206430;  1 drivers
+v0000000003f18500_0 .net "or0_out_X", 0 0, L_00000000042060b0;  1 drivers
+S_000000000298aaf0 .scope module, "sky130_fd_sc_hd__or4b_2" "sky130_fd_sc_hd__or4b_2" 4 18015;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e923c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1c9c0_0 .net "A", 0 0, o0000000003e923c8;  0 drivers
+o0000000003e923f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1c740_0 .net "B", 0 0, o0000000003e923f8;  0 drivers
+o0000000003e92428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1ce20_0 .net "C", 0 0, o0000000003e92428;  0 drivers
+o0000000003e92458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1b7a0_0 .net "D_N", 0 0, o0000000003e92458;  0 drivers
+L_00000000040fa780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c880_0 .net8 "VGND", 0 0, L_00000000040fa780;  1 drivers, strength-aware
+L_00000000040fa8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1aee0_0 .net8 "VNB", 0 0, L_00000000040fa8d0;  1 drivers, strength-aware
+L_00000000040fa940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c4c0_0 .net8 "VPB", 0 0, L_00000000040fa940;  1 drivers, strength-aware
+L_00000000040fd500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1ca60_0 .net8 "VPWR", 0 0, L_00000000040fd500;  1 drivers, strength-aware
+v0000000003f1ba20_0 .net "X", 0 0, L_0000000004205080;  1 drivers
+S_0000000003eed100 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 18035, 4 17892 1, S_000000000298aaf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004206350 .functor NOT 1, o0000000003e92458, C4<0>, C4<0>, C4<0>;
+L_0000000004205ef0 .functor OR 1, L_0000000004206350, o0000000003e92428, o0000000003e923f8, o0000000003e923c8;
+L_0000000004205080 .functor BUF 1, L_0000000004205ef0, C4<0>, C4<0>, C4<0>;
+v0000000003f19180_0 .net "A", 0 0, o0000000003e923c8;  alias, 0 drivers
+v0000000003f18780_0 .net "B", 0 0, o0000000003e923f8;  alias, 0 drivers
+v0000000003f18960_0 .net "C", 0 0, o0000000003e92428;  alias, 0 drivers
+v0000000003f18b40_0 .net "D_N", 0 0, o0000000003e92458;  alias, 0 drivers
+L_00000000040fc460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f18be0_0 .net8 "VGND", 0 0, L_00000000040fc460;  1 drivers, strength-aware
+L_00000000040fc0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b160_0 .net8 "VNB", 0 0, L_00000000040fc0e0;  1 drivers, strength-aware
+L_00000000040fd880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1be80_0 .net8 "VPB", 0 0, L_00000000040fd880;  1 drivers, strength-aware
+L_00000000040fd3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b980_0 .net8 "VPWR", 0 0, L_00000000040fd3b0;  1 drivers, strength-aware
+v0000000003f1cd80_0 .net "X", 0 0, L_0000000004205080;  alias, 1 drivers
+v0000000003f1ab20_0 .net "not0_out", 0 0, L_0000000004206350;  1 drivers
+v0000000003f1cce0_0 .net "or0_out_X", 0 0, L_0000000004205ef0;  1 drivers
+S_00000000029892f0 .scope module, "sky130_fd_sc_hd__or4b_4" "sky130_fd_sc_hd__or4b_4" 4 17571;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e92878 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1abc0_0 .net "A", 0 0, o0000000003e92878;  0 drivers
+o0000000003e928a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1bb60_0 .net "B", 0 0, o0000000003e928a8;  0 drivers
+o0000000003e928d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1bd40_0 .net "C", 0 0, o0000000003e928d8;  0 drivers
+o0000000003e92908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1cb00_0 .net "D_N", 0 0, o0000000003e92908;  0 drivers
+L_00000000040fcaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1cf60_0 .net8 "VGND", 0 0, L_00000000040fcaf0;  1 drivers, strength-aware
+L_00000000040fc2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c1a0_0 .net8 "VNB", 0 0, L_00000000040fc2a0;  1 drivers, strength-aware
+L_00000000040fcb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b700_0 .net8 "VPB", 0 0, L_00000000040fcb60;  1 drivers, strength-aware
+L_00000000040fc7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1a9e0_0 .net8 "VPWR", 0 0, L_00000000040fc7e0;  1 drivers, strength-aware
+v0000000003f1c920_0 .net "X", 0 0, L_0000000004206740;  1 drivers
+S_0000000003ee9c80 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 17591, 4 17892 1, S_00000000029892f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004205cc0 .functor NOT 1, o0000000003e92908, C4<0>, C4<0>, C4<0>;
+L_0000000004205710 .functor OR 1, L_0000000004205cc0, o0000000003e928d8, o0000000003e928a8, o0000000003e92878;
+L_0000000004206740 .functor BUF 1, L_0000000004205710, C4<0>, C4<0>, C4<0>;
+v0000000003f1cec0_0 .net "A", 0 0, o0000000003e92878;  alias, 0 drivers
+v0000000003f1bca0_0 .net "B", 0 0, o0000000003e928a8;  alias, 0 drivers
+v0000000003f1bac0_0 .net "C", 0 0, o0000000003e928d8;  alias, 0 drivers
+v0000000003f1b840_0 .net "D_N", 0 0, o0000000003e92908;  alias, 0 drivers
+L_00000000040fc000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c240_0 .net8 "VGND", 0 0, L_00000000040fc000;  1 drivers, strength-aware
+L_00000000040fc690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1bc00_0 .net8 "VNB", 0 0, L_00000000040fc690;  1 drivers, strength-aware
+L_00000000040fcbd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1bf20_0 .net8 "VPB", 0 0, L_00000000040fcbd0;  1 drivers, strength-aware
+L_00000000040fd420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c380_0 .net8 "VPWR", 0 0, L_00000000040fd420;  1 drivers, strength-aware
+v0000000003f1c420_0 .net "X", 0 0, L_0000000004206740;  alias, 1 drivers
+v0000000003f1b480_0 .net "not0_out", 0 0, L_0000000004205cc0;  1 drivers
+v0000000003f1b200_0 .net "or0_out_X", 0 0, L_0000000004205710;  1 drivers
+S_00000000029886f0 .scope module, "sky130_fd_sc_hd__or4bb_1" "sky130_fd_sc_hd__or4bb_1" 4 15625;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e92d28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1c7e0_0 .net "A", 0 0, o0000000003e92d28;  0 drivers
+o0000000003e92d58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1b020_0 .net "B", 0 0, o0000000003e92d58;  0 drivers
+o0000000003e92d88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1c060_0 .net "C_N", 0 0, o0000000003e92d88;  0 drivers
+o0000000003e92db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1cc40_0 .net "D_N", 0 0, o0000000003e92db8;  0 drivers
+L_00000000040fca10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1ad00_0 .net8 "VGND", 0 0, L_00000000040fca10;  1 drivers, strength-aware
+L_00000000040fd5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1ada0_0 .net8 "VNB", 0 0, L_00000000040fd5e0;  1 drivers, strength-aware
+L_00000000040fcc40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d000_0 .net8 "VPB", 0 0, L_00000000040fcc40;  1 drivers, strength-aware
+L_00000000040fd110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c100_0 .net8 "VPWR", 0 0, L_00000000040fd110;  1 drivers, strength-aware
+v0000000003f1b3e0_0 .net "X", 0 0, L_0000000004205390;  1 drivers
+S_0000000003eee900 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 15645, 4 15946 1, S_00000000029886f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_00000000042054e0 .functor NAND 1, o0000000003e92db8, o0000000003e92d88, C4<1>, C4<1>;
+L_00000000042055c0 .functor OR 1, o0000000003e92d58, o0000000003e92d28, L_00000000042054e0, C4<0>;
+L_0000000004205390 .functor BUF 1, L_00000000042055c0, C4<0>, C4<0>, C4<0>;
+v0000000003f1c600_0 .net "A", 0 0, o0000000003e92d28;  alias, 0 drivers
+v0000000003f1b5c0_0 .net "B", 0 0, o0000000003e92d58;  alias, 0 drivers
+v0000000003f1c6a0_0 .net "C_N", 0 0, o0000000003e92d88;  alias, 0 drivers
+v0000000003f1d0a0_0 .net "D_N", 0 0, o0000000003e92db8;  alias, 0 drivers
+L_00000000040fc070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b660_0 .net8 "VGND", 0 0, L_00000000040fc070;  1 drivers, strength-aware
+L_00000000040fc150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1bde0_0 .net8 "VNB", 0 0, L_00000000040fc150;  1 drivers, strength-aware
+L_00000000040fd0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1c560_0 .net8 "VPB", 0 0, L_00000000040fd0a0;  1 drivers, strength-aware
+L_00000000040fccb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1bfc0_0 .net8 "VPWR", 0 0, L_00000000040fccb0;  1 drivers, strength-aware
+v0000000003f1c2e0_0 .net "X", 0 0, L_0000000004205390;  alias, 1 drivers
+v0000000003f1a940_0 .net "nand0_out", 0 0, L_00000000042054e0;  1 drivers
+v0000000003f1cba0_0 .net "or0_out_X", 0 0, L_00000000042055c0;  1 drivers
+S_000000000298a4f0 .scope module, "sky130_fd_sc_hd__or4bb_2" "sky130_fd_sc_hd__or4bb_2" 4 16069;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e931d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1e2c0_0 .net "A", 0 0, o0000000003e931d8;  0 drivers
+o0000000003e93208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1d3c0_0 .net "B", 0 0, o0000000003e93208;  0 drivers
+o0000000003e93238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1ddc0_0 .net "C_N", 0 0, o0000000003e93238;  0 drivers
+o0000000003e93268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1f800_0 .net "D_N", 0 0, o0000000003e93268;  0 drivers
+L_00000000040fd2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1ecc0_0 .net8 "VGND", 0 0, L_00000000040fd2d0;  1 drivers, strength-aware
+L_00000000040fc930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1f080_0 .net8 "VNB", 0 0, L_00000000040fc930;  1 drivers, strength-aware
+L_00000000040fc1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1f260_0 .net8 "VPB", 0 0, L_00000000040fc1c0;  1 drivers, strength-aware
+L_00000000040fc230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1da00_0 .net8 "VPWR", 0 0, L_00000000040fc230;  1 drivers, strength-aware
+v0000000003f1dc80_0 .net "X", 0 0, L_0000000004205b00;  1 drivers
+S_0000000003eec380 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 16089, 4 15946 1, S_000000000298a4f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004206120 .functor NAND 1, o0000000003e93268, o0000000003e93238, C4<1>, C4<1>;
+L_0000000004205f60 .functor OR 1, o0000000003e93208, o0000000003e931d8, L_0000000004206120, C4<0>;
+L_0000000004205b00 .functor BUF 1, L_0000000004205f60, C4<0>, C4<0>, C4<0>;
+v0000000003f1ac60_0 .net "A", 0 0, o0000000003e931d8;  alias, 0 drivers
+v0000000003f1aa80_0 .net "B", 0 0, o0000000003e93208;  alias, 0 drivers
+v0000000003f1b340_0 .net "C_N", 0 0, o0000000003e93238;  alias, 0 drivers
+v0000000003f1ae40_0 .net "D_N", 0 0, o0000000003e93268;  alias, 0 drivers
+L_00000000040fc310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b520_0 .net8 "VGND", 0 0, L_00000000040fc310;  1 drivers, strength-aware
+L_00000000040fc380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1af80_0 .net8 "VNB", 0 0, L_00000000040fc380;  1 drivers, strength-aware
+L_00000000040fc700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b0c0_0 .net8 "VPB", 0 0, L_00000000040fc700;  1 drivers, strength-aware
+L_00000000040fc770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1b2a0_0 .net8 "VPWR", 0 0, L_00000000040fc770;  1 drivers, strength-aware
+v0000000003f1b8e0_0 .net "X", 0 0, L_0000000004205b00;  alias, 1 drivers
+v0000000003f1d140_0 .net "nand0_out", 0 0, L_0000000004206120;  1 drivers
+v0000000003f1ed60_0 .net "or0_out_X", 0 0, L_0000000004205f60;  1 drivers
+S_0000000002989470 .scope module, "sky130_fd_sc_hd__or4bb_4" "sky130_fd_sc_hd__or4bb_4" 4 15507;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+o0000000003e93688 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1d500_0 .net "A", 0 0, o0000000003e93688;  0 drivers
+o0000000003e936b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1df00_0 .net "B", 0 0, o0000000003e936b8;  0 drivers
+o0000000003e936e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1d780_0 .net "C_N", 0 0, o0000000003e936e8;  0 drivers
+o0000000003e93718 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1e220_0 .net "D_N", 0 0, o0000000003e93718;  0 drivers
+L_00000000040fc850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1ef40_0 .net8 "VGND", 0 0, L_00000000040fc850;  1 drivers, strength-aware
+L_00000000040fd6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1efe0_0 .net8 "VNB", 0 0, L_00000000040fd6c0;  1 drivers, strength-aware
+L_00000000040fd730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1db40_0 .net8 "VPB", 0 0, L_00000000040fd730;  1 drivers, strength-aware
+L_00000000040fc3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1dbe0_0 .net8 "VPWR", 0 0, L_00000000040fc3f0;  1 drivers, strength-aware
+v0000000003f1dfa0_0 .net "X", 0 0, L_0000000004205780;  1 drivers
+S_0000000003eedb80 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 15527, 4 15946 1, S_0000000002989470;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C_N"
+    .port_info 4 /INPUT 1 "D_N"
+L_0000000004205400 .functor NAND 1, o0000000003e93718, o0000000003e936e8, C4<1>, C4<1>;
+L_0000000004205550 .functor OR 1, o0000000003e936b8, o0000000003e93688, L_0000000004205400, C4<0>;
+L_0000000004205780 .functor BUF 1, L_0000000004205550, C4<0>, C4<0>, C4<0>;
+v0000000003f1ee00_0 .net "A", 0 0, o0000000003e93688;  alias, 0 drivers
+v0000000003f1d6e0_0 .net "B", 0 0, o0000000003e936b8;  alias, 0 drivers
+v0000000003f1f760_0 .net "C_N", 0 0, o0000000003e936e8;  alias, 0 drivers
+v0000000003f1eb80_0 .net "D_N", 0 0, o0000000003e93718;  alias, 0 drivers
+L_00000000040fcd90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1dd20_0 .net8 "VGND", 0 0, L_00000000040fcd90;  1 drivers, strength-aware
+L_00000000040fc8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1daa0_0 .net8 "VNB", 0 0, L_00000000040fc8c0;  1 drivers, strength-aware
+L_00000000040fc620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1f1c0_0 .net8 "VPB", 0 0, L_00000000040fc620;  1 drivers, strength-aware
+L_00000000040fbeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d460_0 .net8 "VPWR", 0 0, L_00000000040fbeb0;  1 drivers, strength-aware
+v0000000003f1eea0_0 .net "X", 0 0, L_0000000004205780;  alias, 1 drivers
+v0000000003f1f620_0 .net "nand0_out", 0 0, L_0000000004205400;  1 drivers
+v0000000003f1de60_0 .net "or0_out_X", 0 0, L_0000000004205550;  1 drivers
+S_0000000002989ef0 .scope module, "sky130_fd_sc_hd__probe_p_8" "sky130_fd_sc_hd__probe_p_8" 4 53853;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003e93b38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1d320_0 .net "A", 0 0, o0000000003e93b38;  0 drivers
+L_00000000040fd260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e360_0 .net8 "VGND", 0 0, L_00000000040fd260;  1 drivers, strength-aware
+L_00000000040fbcf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e040_0 .net8 "VNB", 0 0, L_00000000040fbcf0;  1 drivers, strength-aware
+L_00000000040fcd20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d5a0_0 .net8 "VPB", 0 0, L_00000000040fcd20;  1 drivers, strength-aware
+L_00000000040fc4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d640_0 .net8 "VPWR", 0 0, L_00000000040fc4d0;  1 drivers, strength-aware
+v0000000003f1f120_0 .net "X", 0 0, L_0000000004205630;  1 drivers
+S_0000000003eebf00 .scope module, "base" "sky130_fd_sc_hd__probe_p" 4 53867, 4 53747 1, S_0000000002989ef0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004205c50 .functor BUF 1, o0000000003e93b38, C4<0>, C4<0>, C4<0>;
+L_0000000004205630 .functor BUF 1, L_0000000004205c50, C4<0>, C4<0>, C4<0>;
+v0000000003f1f6c0_0 .net "A", 0 0, o0000000003e93b38;  alias, 0 drivers
+L_00000000040fce00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e5e0_0 .net8 "VGND", 0 0, L_00000000040fce00;  1 drivers, strength-aware
+L_00000000040fc540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d1e0_0 .net8 "VNB", 0 0, L_00000000040fc540;  1 drivers, strength-aware
+L_00000000040fc9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1f8a0_0 .net8 "VPB", 0 0, L_00000000040fc9a0;  1 drivers, strength-aware
+L_00000000040fbf90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d280_0 .net8 "VPWR", 0 0, L_00000000040fbf90;  1 drivers, strength-aware
+v0000000003f1e720_0 .net "X", 0 0, L_0000000004205630;  alias, 1 drivers
+v0000000003f1f4e0_0 .net "buf0_out_X", 0 0, L_0000000004205c50;  1 drivers
+S_0000000002989d70 .scope module, "sky130_fd_sc_hd__probec_p_8" "sky130_fd_sc_hd__probec_p_8" 4 66336;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+o0000000003e93e08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1d960_0 .net "A", 0 0, o0000000003e93e08;  0 drivers
+L_00000000040fce70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e4a0_0 .net8 "VGND", 0 0, L_00000000040fce70;  1 drivers, strength-aware
+L_00000000040fca80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e540_0 .net8 "VNB", 0 0, L_00000000040fca80;  1 drivers, strength-aware
+L_00000000040fd180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e860_0 .net8 "VPB", 0 0, L_00000000040fd180;  1 drivers, strength-aware
+L_00000000040fcee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e900_0 .net8 "VPWR", 0 0, L_00000000040fcee0;  1 drivers, strength-aware
+v0000000003f1e9a0_0 .net "X", 0 0, L_0000000004205e80;  1 drivers
+S_0000000003eebd80 .scope module, "base" "sky130_fd_sc_hd__probec_p" 4 66350, 4 66624 1, S_0000000002989d70;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+L_0000000004205fd0 .functor BUF 1, o0000000003e93e08, C4<0>, C4<0>, C4<0>;
+L_0000000004205e80 .functor BUF 1, L_0000000004205fd0, C4<0>, C4<0>, C4<0>;
+v0000000003f1d820_0 .net "A", 0 0, o0000000003e93e08;  alias, 0 drivers
+L_00000000040fc5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1d8c0_0 .net8 "VGND", 0 0, L_00000000040fc5b0;  1 drivers, strength-aware
+L_00000000040fd7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e0e0_0 .net8 "VNB", 0 0, L_00000000040fd7a0;  1 drivers, strength-aware
+L_00000000040fbd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e180_0 .net8 "VPB", 0 0, L_00000000040fbd60;  1 drivers, strength-aware
+L_00000000040fcf50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f1e400_0 .net8 "VPWR", 0 0, L_00000000040fcf50;  1 drivers, strength-aware
+v0000000003f1e680_0 .net "X", 0 0, L_0000000004205e80;  alias, 1 drivers
+v0000000003f1e7c0_0 .net "buf0_out_X", 0 0, L_0000000004205fd0;  1 drivers
+S_000000000298a1f0 .scope module, "sky130_fd_sc_hd__sdfbbn_1" "sky130_fd_sc_hd__sdfbbn_1" 4 70811;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK_N"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e94108 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f21b00_0 .net "CLK_N", 0 0, o0000000003e94108;  0 drivers
+o0000000003e94168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f20700_0 .net "D", 0 0, o0000000003e94168;  0 drivers
+v0000000003f21420_0 .net "Q", 0 0, L_0000000004204de0;  1 drivers
+v0000000003f1fa80_0 .net "Q_N", 0 0, L_00000000042064a0;  1 drivers
+o0000000003e94258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f20840_0 .net "RESET_B", 0 0, o0000000003e94258;  0 drivers
+o0000000003e942b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f203e0_0 .net "SCD", 0 0, o0000000003e942b8;  0 drivers
+o0000000003e94318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f20480_0 .net "SCE", 0 0, o0000000003e94318;  0 drivers
+o0000000003e943a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f1fe40_0 .net "SET_B", 0 0, o0000000003e943a8;  0 drivers
+L_00000000040fcfc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f20fc0_0 .net8 "VGND", 0 0, L_00000000040fcfc0;  1 drivers, strength-aware
+L_00000000040fd030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f216a0_0 .net8 "VNB", 0 0, L_00000000040fd030;  1 drivers, strength-aware
+L_00000000040fbdd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f20ca0_0 .net8 "VPB", 0 0, L_00000000040fbdd0;  1 drivers, strength-aware
+L_00000000040fbe40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f208e0_0 .net8 "VPWR", 0 0, L_00000000040fbe40;  1 drivers, strength-aware
+S_0000000003eec500 .scope module, "base" "sky130_fd_sc_hd__sdfbbn" 4 70837, 4 71206 1, S_000000000298a1f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK_N"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e94288 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206190 .functor NOT 1, o0000000003e94288, C4<0>, C4<0>, C4<0>;
+o0000000003e943d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206890 .functor NOT 1, o0000000003e943d8, C4<0>, C4<0>, C4<0>;
+o0000000003e94138 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004204d70 .functor NOT 1, o0000000003e94138, C4<0>, C4<0>, C4<0>;
+o0000000003e94198 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e942e8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e94348 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042056a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e94198, o0000000003e942e8, o0000000003e94348;
+L_00000000040fd490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fd1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004204ec0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000004206890, L_0000000004206190, L_0000000004204d70, L_00000000042056a0, v0000000003f1f9e0_0, L_00000000040fd490, L_00000000040fd1f0;
+L_00000000042057f0 .functor AND 1, L_0000000003f99440, L_0000000003f98c20, C4<1>, C4<1>;
+L_00000000042050f0 .functor AND 1, L_0000000003f99440, L_0000000003f97dc0, C4<1>, C4<1>;
+L_00000000042058d0 .functor AND 1, L_00000000042057f0, L_00000000042050f0, C4<1>, C4<1>;
+L_0000000004206200 .functor AND 1, L_0000000003f98cc0, L_00000000042058d0, C4<1>, C4<1>;
+L_0000000004206270 .functor AND 1, L_0000000003f97a00, L_00000000042058d0, C4<1>, C4<1>;
+L_00000000042063c0 .functor AND 1, L_0000000003f98a40, L_00000000042058d0, C4<1>, C4<1>;
+L_0000000004204de0 .functor BUF 1, L_0000000004204ec0, C4<0>, C4<0>, C4<0>;
+L_00000000042064a0 .functor NOT 1, L_0000000004204ec0, C4<0>, C4<0>, C4<0>;
+v0000000003f1f300_0 .net "CLK", 0 0, L_0000000004204d70;  1 drivers
+v0000000003f1ea40_0 .net "CLK_N", 0 0, o0000000003e94108;  alias, 0 drivers
+v0000000003f1eae0_0 .net "CLK_N_delayed", 0 0, o0000000003e94138;  0 drivers
+v0000000003f1ec20_0 .net "D", 0 0, o0000000003e94168;  alias, 0 drivers
+v0000000003f1f3a0_0 .net "D_delayed", 0 0, o0000000003e94198;  0 drivers
+v0000000003f1f440_0 .net "Q", 0 0, L_0000000004204de0;  alias, 1 drivers
+v0000000003f1f580_0 .net "Q_N", 0 0, L_00000000042064a0;  alias, 1 drivers
+v0000000003f21e20_0 .net "RESET", 0 0, L_0000000004206190;  1 drivers
+v0000000003f20d40_0 .net "RESET_B", 0 0, o0000000003e94258;  alias, 0 drivers
+v0000000003f21ce0_0 .net "RESET_B_delayed", 0 0, o0000000003e94288;  0 drivers
+v0000000003f20520_0 .net "SCD", 0 0, o0000000003e942b8;  alias, 0 drivers
+v0000000003f20e80_0 .net "SCD_delayed", 0 0, o0000000003e942e8;  0 drivers
+v0000000003f207a0_0 .net "SCE", 0 0, o0000000003e94318;  alias, 0 drivers
+v0000000003f21ec0_0 .net "SCE_delayed", 0 0, o0000000003e94348;  0 drivers
+v0000000003f20200_0 .net "SET", 0 0, L_0000000004206890;  1 drivers
+v0000000003f1fbc0_0 .net "SET_B", 0 0, o0000000003e943a8;  alias, 0 drivers
+v0000000003f20ac0_0 .net "SET_B_delayed", 0 0, o0000000003e943d8;  0 drivers
+v0000000003f211a0_0 .net8 "VGND", 0 0, L_00000000040fd1f0;  1 drivers, strength-aware
+L_00000000040fbf20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f21f60_0 .net8 "VNB", 0 0, L_00000000040fbf20;  1 drivers, strength-aware
+L_00000000040fd340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f22000_0 .net8 "VPB", 0 0, L_00000000040fd340;  1 drivers, strength-aware
+v0000000003f21880_0 .net8 "VPWR", 0 0, L_00000000040fd490;  1 drivers, strength-aware
+v0000000003f21a60_0 .net *"_s10", 0 0, L_0000000003f98c20;  1 drivers
+L_000000000418aae0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f202a0_0 .net/2u *"_s14", 0 0, L_000000000418aae0;  1 drivers
+v0000000003f21560_0 .net *"_s16", 0 0, L_0000000003f97dc0;  1 drivers
+L_000000000418ab28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f214c0_0 .net/2u *"_s22", 0 0, L_000000000418ab28;  1 drivers
+v0000000003f20f20_0 .net *"_s24", 0 0, L_0000000003f98cc0;  1 drivers
+L_000000000418ab70 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f20de0_0 .net/2u *"_s28", 0 0, L_000000000418ab70;  1 drivers
+v0000000003f21d80_0 .net *"_s30", 0 0, L_0000000003f97a00;  1 drivers
+v0000000003f20b60_0 .net *"_s34", 0 0, L_0000000003f98a40;  1 drivers
+L_000000000418aa50 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f220a0_0 .net/2u *"_s4", 0 0, L_000000000418aa50;  1 drivers
+L_000000000418aa98 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f1fda0_0 .net/2u *"_s8", 0 0, L_000000000418aa98;  1 drivers
+v0000000003f1fc60_0 .net "awake", 0 0, L_0000000003f99440;  1 drivers
+v0000000003f21380_0 .net "buf_Q", 0 0, L_0000000004204ec0;  1 drivers
+v0000000003f205c0_0 .net "cond0", 0 0, L_00000000042057f0;  1 drivers
+v0000000003f20340_0 .net "cond1", 0 0, L_00000000042050f0;  1 drivers
+v0000000003f219c0_0 .net "cond_D", 0 0, L_0000000004206200;  1 drivers
+v0000000003f1fd00_0 .net "cond_SCD", 0 0, L_0000000004206270;  1 drivers
+v0000000003f21600_0 .net "cond_SCE", 0 0, L_00000000042063c0;  1 drivers
+v0000000003f20660_0 .net "condb", 0 0, L_00000000042058d0;  1 drivers
+v0000000003f1f940_0 .net "mux_out", 0 0, L_00000000042056a0;  1 drivers
+v0000000003f1f9e0_0 .var "notifier", 0 0;
+L_0000000003f99440 .cmp/eeq 1, L_00000000040fd490, L_000000000418aa50;
+L_0000000003f98c20 .cmp/eeq 1, o0000000003e94288, L_000000000418aa98;
+L_0000000003f97dc0 .cmp/eeq 1, o0000000003e943d8, L_000000000418aae0;
+L_0000000003f98cc0 .cmp/eeq 1, o0000000003e94348, L_000000000418ab28;
+L_0000000003f97a00 .cmp/eeq 1, o0000000003e94348, L_000000000418ab70;
+L_0000000003f98a40 .cmp/nee 1, o0000000003e94198, o0000000003e942e8;
+S_0000000002988cf0 .scope module, "sky130_fd_sc_hd__sdfbbn_2" "sky130_fd_sc_hd__sdfbbn_2" 4 70674;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK_N"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e94c78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f234a0_0 .net "CLK_N", 0 0, o0000000003e94c78;  0 drivers
+o0000000003e94cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f230e0_0 .net "D", 0 0, o0000000003e94cd8;  0 drivers
+v0000000003f24120_0 .net "Q", 0 0, L_0000000004206580;  1 drivers
+v0000000003f23720_0 .net "Q_N", 0 0, L_00000000042065f0;  1 drivers
+o0000000003e94dc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f23ea0_0 .net "RESET_B", 0 0, o0000000003e94dc8;  0 drivers
+o0000000003e94e28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f22be0_0 .net "SCD", 0 0, o0000000003e94e28;  0 drivers
+o0000000003e94e88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f22c80_0 .net "SCE", 0 0, o0000000003e94e88;  0 drivers
+o0000000003e94f18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f22d20_0 .net "SET_B", 0 0, o0000000003e94f18;  0 drivers
+L_00000000040fd570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f22500_0 .net8 "VGND", 0 0, L_00000000040fd570;  1 drivers, strength-aware
+L_00000000040fd650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f225a0_0 .net8 "VNB", 0 0, L_00000000040fd650;  1 drivers, strength-aware
+L_00000000040fd810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f22640_0 .net8 "VPB", 0 0, L_00000000040fd810;  1 drivers, strength-aware
+L_00000000040fe0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f23f40_0 .net8 "VPWR", 0 0, L_00000000040fe0d0;  1 drivers, strength-aware
+S_0000000003eed400 .scope module, "base" "sky130_fd_sc_hd__sdfbbn" 4 70700, 4 71206 1, S_0000000002988cf0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK_N"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e94df8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004205160 .functor NOT 1, o0000000003e94df8, C4<0>, C4<0>, C4<0>;
+o0000000003e94f48 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004205d30 .functor NOT 1, o0000000003e94f48, C4<0>, C4<0>, C4<0>;
+o0000000003e94ca8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042059b0 .functor NOT 1, o0000000003e94ca8, C4<0>, C4<0>, C4<0>;
+o0000000003e94d08 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e94e58 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e94eb8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004205b70 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e94d08, o0000000003e94e58, o0000000003e94eb8;
+L_00000000040fea00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fee60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000042067b0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000004205d30, L_0000000004205160, L_00000000042059b0, L_0000000004205b70, v0000000003f22b40_0, L_00000000040fea00, L_00000000040fee60;
+L_0000000004205be0 .functor AND 1, L_0000000003f98220, L_0000000003f982c0, C4<1>, C4<1>;
+L_0000000004205a20 .functor AND 1, L_0000000003f98220, L_0000000003f98360, C4<1>, C4<1>;
+L_0000000004205a90 .functor AND 1, L_0000000004205be0, L_0000000004205a20, C4<1>, C4<1>;
+L_0000000004205da0 .functor AND 1, L_0000000003f98f40, L_0000000004205a90, C4<1>, C4<1>;
+L_0000000004206510 .functor AND 1, L_0000000003f99800, L_0000000004205a90, C4<1>, C4<1>;
+L_0000000004205e10 .functor AND 1, L_0000000003f98860, L_0000000004205a90, C4<1>, C4<1>;
+L_0000000004206580 .functor BUF 1, L_00000000042067b0, C4<0>, C4<0>, C4<0>;
+L_00000000042065f0 .functor NOT 1, L_00000000042067b0, C4<0>, C4<0>, C4<0>;
+v0000000003f20980_0 .net "CLK", 0 0, L_00000000042059b0;  1 drivers
+v0000000003f20a20_0 .net "CLK_N", 0 0, o0000000003e94c78;  alias, 0 drivers
+v0000000003f20c00_0 .net "CLK_N_delayed", 0 0, o0000000003e94ca8;  0 drivers
+v0000000003f21740_0 .net "D", 0 0, o0000000003e94cd8;  alias, 0 drivers
+v0000000003f21060_0 .net "D_delayed", 0 0, o0000000003e94d08;  0 drivers
+v0000000003f21100_0 .net "Q", 0 0, L_0000000004206580;  alias, 1 drivers
+v0000000003f200c0_0 .net "Q_N", 0 0, L_00000000042065f0;  alias, 1 drivers
+v0000000003f217e0_0 .net "RESET", 0 0, L_0000000004205160;  1 drivers
+v0000000003f1fee0_0 .net "RESET_B", 0 0, o0000000003e94dc8;  alias, 0 drivers
+v0000000003f21ba0_0 .net "RESET_B_delayed", 0 0, o0000000003e94df8;  0 drivers
+v0000000003f21240_0 .net "SCD", 0 0, o0000000003e94e28;  alias, 0 drivers
+v0000000003f212e0_0 .net "SCD_delayed", 0 0, o0000000003e94e58;  0 drivers
+v0000000003f21920_0 .net "SCE", 0 0, o0000000003e94e88;  alias, 0 drivers
+v0000000003f21c40_0 .net "SCE_delayed", 0 0, o0000000003e94eb8;  0 drivers
+v0000000003f1fb20_0 .net "SET", 0 0, L_0000000004205d30;  1 drivers
+v0000000003f1ff80_0 .net "SET_B", 0 0, o0000000003e94f18;  alias, 0 drivers
+v0000000003f20020_0 .net "SET_B_delayed", 0 0, o0000000003e94f48;  0 drivers
+v0000000003f20160_0 .net8 "VGND", 0 0, L_00000000040fee60;  1 drivers, strength-aware
+L_00000000040feed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f244e0_0 .net8 "VNB", 0 0, L_00000000040feed0;  1 drivers, strength-aware
+L_00000000040ff170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f226e0_0 .net8 "VPB", 0 0, L_00000000040ff170;  1 drivers, strength-aware
+v0000000003f22780_0 .net8 "VPWR", 0 0, L_00000000040fea00;  1 drivers, strength-aware
+v0000000003f22460_0 .net *"_s10", 0 0, L_0000000003f982c0;  1 drivers
+L_000000000418ac48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f23b80_0 .net/2u *"_s14", 0 0, L_000000000418ac48;  1 drivers
+v0000000003f22dc0_0 .net *"_s16", 0 0, L_0000000003f98360;  1 drivers
+L_000000000418ac90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f22a00_0 .net/2u *"_s22", 0 0, L_000000000418ac90;  1 drivers
+v0000000003f23540_0 .net *"_s24", 0 0, L_0000000003f98f40;  1 drivers
+L_000000000418acd8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f22fa0_0 .net/2u *"_s28", 0 0, L_000000000418acd8;  1 drivers
+v0000000003f22e60_0 .net *"_s30", 0 0, L_0000000003f99800;  1 drivers
+v0000000003f24800_0 .net *"_s34", 0 0, L_0000000003f98860;  1 drivers
+L_000000000418abb8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f248a0_0 .net/2u *"_s4", 0 0, L_000000000418abb8;  1 drivers
+L_000000000418ac00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f23c20_0 .net/2u *"_s8", 0 0, L_000000000418ac00;  1 drivers
+v0000000003f23400_0 .net "awake", 0 0, L_0000000003f98220;  1 drivers
+v0000000003f235e0_0 .net "buf_Q", 0 0, L_00000000042067b0;  1 drivers
+v0000000003f241c0_0 .net "cond0", 0 0, L_0000000004205be0;  1 drivers
+v0000000003f22820_0 .net "cond1", 0 0, L_0000000004205a20;  1 drivers
+v0000000003f23ae0_0 .net "cond_D", 0 0, L_0000000004205da0;  1 drivers
+v0000000003f23cc0_0 .net "cond_SCD", 0 0, L_0000000004206510;  1 drivers
+v0000000003f23d60_0 .net "cond_SCE", 0 0, L_0000000004205e10;  1 drivers
+v0000000003f23e00_0 .net "condb", 0 0, L_0000000004205a90;  1 drivers
+v0000000003f22aa0_0 .net "mux_out", 0 0, L_0000000004205b70;  1 drivers
+v0000000003f22b40_0 .var "notifier", 0 0;
+L_0000000003f98220 .cmp/eeq 1, L_00000000040fea00, L_000000000418abb8;
+L_0000000003f982c0 .cmp/eeq 1, o0000000003e94df8, L_000000000418ac00;
+L_0000000003f98360 .cmp/eeq 1, o0000000003e94f48, L_000000000418ac48;
+L_0000000003f98f40 .cmp/eeq 1, o0000000003e94eb8, L_000000000418ac90;
+L_0000000003f99800 .cmp/eeq 1, o0000000003e94eb8, L_000000000418acd8;
+L_0000000003f98860 .cmp/nee 1, o0000000003e94d08, o0000000003e94e58;
+S_000000000298a7f0 .scope module, "sky130_fd_sc_hd__sdfbbp_1" "sky130_fd_sc_hd__sdfbbp_1" 4 75318;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e957b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25980_0 .net "CLK", 0 0, o0000000003e957b8;  0 drivers
+o0000000003e95818 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25c00_0 .net "D", 0 0, o0000000003e95818;  0 drivers
+v0000000003f249e0_0 .net "Q", 0 0, L_00000000042077e0;  1 drivers
+v0000000003f25520_0 .net "Q_N", 0 0, L_0000000004208490;  1 drivers
+o0000000003e95908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25e80_0 .net "RESET_B", 0 0, o0000000003e95908;  0 drivers
+o0000000003e95968 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f26ec0_0 .net "SCD", 0 0, o0000000003e95968;  0 drivers
+o0000000003e959c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25ac0_0 .net "SCE", 0 0, o0000000003e959c8;  0 drivers
+o0000000003e95a58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25ca0_0 .net "SET_B", 0 0, o0000000003e95a58;  0 drivers
+L_00000000040fefb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f25700_0 .net8 "VGND", 0 0, L_00000000040fefb0;  1 drivers, strength-aware
+L_00000000040ff1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f24f80_0 .net8 "VNB", 0 0, L_00000000040ff1e0;  1 drivers, strength-aware
+L_00000000040fef40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f27000_0 .net8 "VPB", 0 0, L_00000000040fef40;  1 drivers, strength-aware
+L_00000000040ff020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f26b00_0 .net8 "VPWR", 0 0, L_00000000040ff020;  1 drivers, strength-aware
+S_0000000003eeec00 .scope module, "base" "sky130_fd_sc_hd__sdfbbp" 4 75344, 4 75707 1, S_000000000298a7f0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "CLK"
+    .port_info 6 /INPUT 1 "SET_B"
+    .port_info 7 /INPUT 1 "RESET_B"
+o0000000003e95938 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206660 .functor NOT 1, o0000000003e95938, C4<0>, C4<0>, C4<0>;
+o0000000003e95a88 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004204e50 .functor NOT 1, o0000000003e95a88, C4<0>, C4<0>, C4<0>;
+o0000000003e95848 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e95998 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e959f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004204f30 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e95848, o0000000003e95998, o0000000003e959f8;
+o0000000003e957e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040fe140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fdb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004204fa0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000004204e50, L_0000000004206660, o0000000003e957e8, L_0000000004204f30, v0000000003f25340_0, L_00000000040fe140, L_00000000040fdb20;
+L_0000000004205470 .functor AND 1, L_0000000003f98400, L_0000000003f984a0, C4<1>, C4<1>;
+L_0000000004205010 .functor AND 1, L_0000000003f98400, L_0000000003f98540, C4<1>, C4<1>;
+L_00000000042051d0 .functor AND 1, L_0000000004205470, L_0000000004205010, C4<1>, C4<1>;
+L_00000000042052b0 .functor AND 1, L_0000000003f994e0, L_00000000042051d0, C4<1>, C4<1>;
+L_0000000004207bd0 .functor AND 1, L_0000000003f971e0, L_00000000042051d0, C4<1>, C4<1>;
+L_0000000004205320 .functor AND 1, L_0000000003f98680, L_00000000042051d0, C4<1>, C4<1>;
+L_00000000042077e0 .functor BUF 1, L_0000000004204fa0, C4<0>, C4<0>, C4<0>;
+L_0000000004208490 .functor NOT 1, L_0000000004204fa0, C4<0>, C4<0>, C4<0>;
+v0000000003f23fe0_0 .net "CLK", 0 0, o0000000003e957b8;  alias, 0 drivers
+v0000000003f24080_0 .net "CLK_delayed", 0 0, o0000000003e957e8;  0 drivers
+v0000000003f24760_0 .net "D", 0 0, o0000000003e95818;  alias, 0 drivers
+v0000000003f237c0_0 .net "D_delayed", 0 0, o0000000003e95848;  0 drivers
+v0000000003f24580_0 .net "Q", 0 0, L_00000000042077e0;  alias, 1 drivers
+v0000000003f232c0_0 .net "Q_N", 0 0, L_0000000004208490;  alias, 1 drivers
+v0000000003f22140_0 .net "RESET", 0 0, L_0000000004206660;  1 drivers
+v0000000003f239a0_0 .net "RESET_B", 0 0, o0000000003e95908;  alias, 0 drivers
+v0000000003f22f00_0 .net "RESET_B_delayed", 0 0, o0000000003e95938;  0 drivers
+v0000000003f24260_0 .net "SCD", 0 0, o0000000003e95968;  alias, 0 drivers
+v0000000003f221e0_0 .net "SCD_delayed", 0 0, o0000000003e95998;  0 drivers
+v0000000003f223c0_0 .net "SCE", 0 0, o0000000003e959c8;  alias, 0 drivers
+v0000000003f246c0_0 .net "SCE_delayed", 0 0, o0000000003e959f8;  0 drivers
+v0000000003f23680_0 .net "SET", 0 0, L_0000000004204e50;  1 drivers
+v0000000003f24300_0 .net "SET_B", 0 0, o0000000003e95a58;  alias, 0 drivers
+v0000000003f23360_0 .net "SET_B_delayed", 0 0, o0000000003e95a88;  0 drivers
+v0000000003f243a0_0 .net8 "VGND", 0 0, L_00000000040fdb20;  1 drivers, strength-aware
+L_00000000040fe450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f22280_0 .net8 "VNB", 0 0, L_00000000040fe450;  1 drivers, strength-aware
+L_00000000040ff090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f24440_0 .net8 "VPB", 0 0, L_00000000040ff090;  1 drivers, strength-aware
+v0000000003f24620_0 .net8 "VPWR", 0 0, L_00000000040fe140;  1 drivers, strength-aware
+v0000000003f23040_0 .net *"_s10", 0 0, L_0000000003f984a0;  1 drivers
+L_000000000418adb0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f23180_0 .net/2u *"_s14", 0 0, L_000000000418adb0;  1 drivers
+v0000000003f23220_0 .net *"_s16", 0 0, L_0000000003f98540;  1 drivers
+L_000000000418adf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f228c0_0 .net/2u *"_s22", 0 0, L_000000000418adf8;  1 drivers
+v0000000003f23860_0 .net *"_s24", 0 0, L_0000000003f994e0;  1 drivers
+L_000000000418ae40 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f22320_0 .net/2u *"_s28", 0 0, L_000000000418ae40;  1 drivers
+v0000000003f22960_0 .net *"_s30", 0 0, L_0000000003f971e0;  1 drivers
+v0000000003f23900_0 .net *"_s34", 0 0, L_0000000003f98680;  1 drivers
+L_000000000418ad20 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f23a40_0 .net/2u *"_s4", 0 0, L_000000000418ad20;  1 drivers
+L_000000000418ad68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f25f20_0 .net/2u *"_s8", 0 0, L_000000000418ad68;  1 drivers
+v0000000003f24940_0 .net "awake", 0 0, L_0000000003f98400;  1 drivers
+v0000000003f25840_0 .net "buf_Q", 0 0, L_0000000004204fa0;  1 drivers
+v0000000003f24ee0_0 .net "cond0", 0 0, L_0000000004205470;  1 drivers
+v0000000003f261a0_0 .net "cond1", 0 0, L_0000000004205010;  1 drivers
+v0000000003f25de0_0 .net "cond_D", 0 0, L_00000000042052b0;  1 drivers
+v0000000003f269c0_0 .net "cond_SCD", 0 0, L_0000000004207bd0;  1 drivers
+v0000000003f24bc0_0 .net "cond_SCE", 0 0, L_0000000004205320;  1 drivers
+v0000000003f255c0_0 .net "condb", 0 0, L_00000000042051d0;  1 drivers
+v0000000003f26e20_0 .net "mux_out", 0 0, L_0000000004204f30;  1 drivers
+v0000000003f25340_0 .var "notifier", 0 0;
+L_0000000003f98400 .cmp/eeq 1, L_00000000040fe140, L_000000000418ad20;
+L_0000000003f984a0 .cmp/eeq 1, o0000000003e95938, L_000000000418ad68;
+L_0000000003f98540 .cmp/eeq 1, o0000000003e95a88, L_000000000418adb0;
+L_0000000003f994e0 .cmp/eeq 1, o0000000003e959f8, L_000000000418adf8;
+L_0000000003f971e0 .cmp/eeq 1, o0000000003e959f8, L_000000000418ae40;
+L_0000000003f98680 .cmp/nee 1, o0000000003e95848, o0000000003e95998;
+S_000000000298a970 .scope module, "sky130_fd_sc_hd__sdfrbp_1" "sky130_fd_sc_hd__sdfrbp_1" 4 22881;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "RESET_B"
+o0000000003e962f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f250c0_0 .net "CLK", 0 0, o0000000003e962f8;  0 drivers
+o0000000003e96358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f26420_0 .net "D", 0 0, o0000000003e96358;  0 drivers
+v0000000003f26920_0 .net "Q", 0 0, L_00000000042078c0;  1 drivers
+v0000000003f26c40_0 .net "Q_N", 0 0, L_0000000004208340;  1 drivers
+o0000000003e96448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f25160_0 .net "RESET_B", 0 0, o0000000003e96448;  0 drivers
+o0000000003e964a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f28c20_0 .net "SCD", 0 0, o0000000003e964a8;  0 drivers
+o0000000003e96508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f27820_0 .net "SCE", 0 0, o0000000003e96508;  0 drivers
+L_00000000040fe300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f28f40_0 .net8 "VGND", 0 0, L_00000000040fe300;  1 drivers, strength-aware
+L_00000000040fea70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f28220_0 .net8 "VNB", 0 0, L_00000000040fea70;  1 drivers, strength-aware
+L_00000000040fddc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f27fa0_0 .net8 "VPB", 0 0, L_00000000040fddc0;  1 drivers, strength-aware
+L_00000000040ff410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f27320_0 .net8 "VPWR", 0 0, L_00000000040ff410;  1 drivers, strength-aware
+S_0000000003eec680 .scope module, "base" "sky130_fd_sc_hd__sdfrbp" 4 22905, 4 22726 1, S_000000000298a970;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "RESET_B"
+o0000000003e96478 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042069e0 .functor NOT 1, o0000000003e96478, C4<0>, C4<0>, C4<0>;
+o0000000003e96388 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e964d8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e96538 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042082d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e96388, o0000000003e964d8, o0000000003e96538;
+o0000000003e96328 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040feae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fdb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004207150 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_00000000042082d0, o0000000003e96328, L_00000000042069e0, v0000000003f252a0_0, L_00000000040feae0, L_00000000040fdb90;
+L_0000000004207ee0 .functor AND 1, L_0000000003f998a0, L_0000000003f97820, C4<1>, C4<1>;
+L_0000000004207850 .functor AND 1, L_0000000003f98d60, L_0000000004207ee0, C4<1>, C4<1>;
+L_0000000004208180 .functor AND 1, L_0000000003f99760, L_0000000004207ee0, C4<1>, C4<1>;
+L_0000000004206c80 .functor AND 1, L_0000000003f975a0, L_0000000004207ee0, C4<1>, C4<1>;
+L_0000000004207460 .functor AND 1, L_0000000003f97280, L_0000000003f97820, C4<1>, C4<1>;
+L_00000000042078c0 .functor BUF 1, L_0000000004207150, C4<0>, C4<0>, C4<0>;
+L_0000000004208340 .functor NOT 1, L_0000000004207150, C4<0>, C4<0>, C4<0>;
+v0000000003f25b60_0 .net "CLK", 0 0, o0000000003e962f8;  alias, 0 drivers
+v0000000003f26240_0 .net "CLK_delayed", 0 0, o0000000003e96328;  0 drivers
+v0000000003f264c0_0 .net "D", 0 0, o0000000003e96358;  alias, 0 drivers
+v0000000003f26880_0 .net "D_delayed", 0 0, o0000000003e96388;  0 drivers
+v0000000003f26a60_0 .net "Q", 0 0, L_00000000042078c0;  alias, 1 drivers
+v0000000003f24a80_0 .net "Q_N", 0 0, L_0000000004208340;  alias, 1 drivers
+v0000000003f26560_0 .net "RESET", 0 0, L_00000000042069e0;  1 drivers
+v0000000003f26600_0 .net "RESET_B", 0 0, o0000000003e96448;  alias, 0 drivers
+v0000000003f25d40_0 .net "RESET_B_delayed", 0 0, o0000000003e96478;  0 drivers
+v0000000003f25fc0_0 .net "SCD", 0 0, o0000000003e964a8;  alias, 0 drivers
+v0000000003f26f60_0 .net "SCD_delayed", 0 0, o0000000003e964d8;  0 drivers
+v0000000003f262e0_0 .net "SCE", 0 0, o0000000003e96508;  alias, 0 drivers
+v0000000003f266a0_0 .net "SCE_delayed", 0 0, o0000000003e96538;  0 drivers
+v0000000003f26ce0_0 .net8 "VGND", 0 0, L_00000000040fdb90;  1 drivers, strength-aware
+L_00000000040ff480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f24da0_0 .net8 "VNB", 0 0, L_00000000040ff480;  1 drivers, strength-aware
+L_00000000040fe370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f270a0_0 .net8 "VPB", 0 0, L_00000000040fe370;  1 drivers, strength-aware
+v0000000003f24e40_0 .net8 "VPWR", 0 0, L_00000000040feae0;  1 drivers, strength-aware
+v0000000003f25480_0 .net *"_s10", 0 0, L_0000000003f998a0;  1 drivers
+L_000000000418af18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f26060_0 .net/2u *"_s14", 0 0, L_000000000418af18;  1 drivers
+v0000000003f26ba0_0 .net *"_s16", 0 0, L_0000000003f98d60;  1 drivers
+L_000000000418af60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f24c60_0 .net/2u *"_s20", 0 0, L_000000000418af60;  1 drivers
+v0000000003f258e0_0 .net *"_s22", 0 0, L_0000000003f99760;  1 drivers
+v0000000003f24b20_0 .net *"_s26", 0 0, L_0000000003f975a0;  1 drivers
+L_000000000418afa8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f25660_0 .net/2u *"_s30", 0 0, L_000000000418afa8;  1 drivers
+v0000000003f26740_0 .net *"_s32", 0 0, L_0000000003f97280;  1 drivers
+L_000000000418ae88 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f26100_0 .net/2u *"_s4", 0 0, L_000000000418ae88;  1 drivers
+L_000000000418aed0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f24d00_0 .net/2u *"_s8", 0 0, L_000000000418aed0;  1 drivers
+v0000000003f257a0_0 .net "awake", 0 0, L_0000000003f97820;  1 drivers
+v0000000003f26d80_0 .net "buf_Q", 0 0, L_0000000004207150;  1 drivers
+v0000000003f25a20_0 .net "cond0", 0 0, L_0000000004207ee0;  1 drivers
+v0000000003f26380_0 .net "cond1", 0 0, L_0000000004207850;  1 drivers
+v0000000003f267e0_0 .net "cond2", 0 0, L_0000000004208180;  1 drivers
+v0000000003f25020_0 .net "cond3", 0 0, L_0000000004206c80;  1 drivers
+v0000000003f25200_0 .net "cond4", 0 0, L_0000000004207460;  1 drivers
+v0000000003f253e0_0 .net "mux_out", 0 0, L_00000000042082d0;  1 drivers
+v0000000003f252a0_0 .var "notifier", 0 0;
+L_0000000003f97820 .cmp/eeq 1, L_00000000040feae0, L_000000000418ae88;
+L_0000000003f998a0 .cmp/eeq 1, o0000000003e96478, L_000000000418aed0;
+L_0000000003f98d60 .cmp/eeq 1, o0000000003e96538, L_000000000418af18;
+L_0000000003f99760 .cmp/eeq 1, o0000000003e96538, L_000000000418af60;
+L_0000000003f975a0 .cmp/nee 1, o0000000003e96388, o0000000003e964d8;
+L_0000000003f97280 .cmp/eeq 1, o0000000003e96448, L_000000000418afa8;
+S_00000000028e9820 .scope module, "sky130_fd_sc_hd__sdfrbp_2" "sky130_fd_sc_hd__sdfrbp_2" 4 22355;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "RESET_B"
+o0000000003e96d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f27b40_0 .net "CLK", 0 0, o0000000003e96d18;  0 drivers
+o0000000003e96d78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f29080_0 .net "D", 0 0, o0000000003e96d78;  0 drivers
+v0000000003f27780_0 .net "Q", 0 0, L_0000000004207d20;  1 drivers
+v0000000003f28e00_0 .net "Q_N", 0 0, L_00000000042070e0;  1 drivers
+o0000000003e96e68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f28400_0 .net "RESET_B", 0 0, o0000000003e96e68;  0 drivers
+o0000000003e96ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f28540_0 .net "SCD", 0 0, o0000000003e96ec8;  0 drivers
+o0000000003e96f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f28860_0 .net "SCE", 0 0, o0000000003e96f28;  0 drivers
+L_00000000040fde30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f278c0_0 .net8 "VGND", 0 0, L_00000000040fde30;  1 drivers, strength-aware
+L_00000000040fd8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f27aa0_0 .net8 "VNB", 0 0, L_00000000040fd8f0;  1 drivers, strength-aware
+L_00000000040fdc00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f27be0_0 .net8 "VPB", 0 0, L_00000000040fdc00;  1 drivers, strength-aware
+L_00000000040fd960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f28900_0 .net8 "VPWR", 0 0, L_00000000040fd960;  1 drivers, strength-aware
+S_0000000003eee180 .scope module, "base" "sky130_fd_sc_hd__sdfrbp" 4 22379, 4 22726 1, S_00000000028e9820;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "RESET_B"
+o0000000003e96e98 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207000 .functor NOT 1, o0000000003e96e98, C4<0>, C4<0>, C4<0>;
+o0000000003e96da8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e96ef8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e96f58 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207fc0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e96da8, o0000000003e96ef8, o0000000003e96f58;
+o0000000003e96d48 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040fe530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040feca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004206900 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000004207fc0, o0000000003e96d48, L_0000000004207000, v0000000003f287c0_0, L_00000000040fe530, L_00000000040feca0;
+L_0000000004207070 .functor AND 1, L_0000000003f987c0, L_0000000003f98720, C4<1>, C4<1>;
+L_0000000004206e40 .functor AND 1, L_0000000003f978c0, L_0000000004207070, C4<1>, C4<1>;
+L_0000000004207230 .functor AND 1, L_0000000003f98900, L_0000000004207070, C4<1>, C4<1>;
+L_0000000004207a80 .functor AND 1, L_0000000003f98ae0, L_0000000004207070, C4<1>, C4<1>;
+L_00000000042083b0 .functor AND 1, L_0000000003f97500, L_0000000003f98720, C4<1>, C4<1>;
+L_0000000004207d20 .functor BUF 1, L_0000000004206900, C4<0>, C4<0>, C4<0>;
+L_00000000042070e0 .functor NOT 1, L_0000000004206900, C4<0>, C4<0>, C4<0>;
+v0000000003f285e0_0 .net "CLK", 0 0, o0000000003e96d18;  alias, 0 drivers
+v0000000003f271e0_0 .net "CLK_delayed", 0 0, o0000000003e96d48;  0 drivers
+v0000000003f296c0_0 .net "D", 0 0, o0000000003e96d78;  alias, 0 drivers
+v0000000003f27500_0 .net "D_delayed", 0 0, o0000000003e96da8;  0 drivers
+v0000000003f28720_0 .net "Q", 0 0, L_0000000004207d20;  alias, 1 drivers
+v0000000003f29620_0 .net "Q_N", 0 0, L_00000000042070e0;  alias, 1 drivers
+v0000000003f282c0_0 .net "RESET", 0 0, L_0000000004207000;  1 drivers
+v0000000003f29800_0 .net "RESET_B", 0 0, o0000000003e96e68;  alias, 0 drivers
+v0000000003f289a0_0 .net "RESET_B_delayed", 0 0, o0000000003e96e98;  0 drivers
+v0000000003f28b80_0 .net "SCD", 0 0, o0000000003e96ec8;  alias, 0 drivers
+v0000000003f28ea0_0 .net "SCD_delayed", 0 0, o0000000003e96ef8;  0 drivers
+v0000000003f29760_0 .net "SCE", 0 0, o0000000003e96f28;  alias, 0 drivers
+v0000000003f273c0_0 .net "SCE_delayed", 0 0, o0000000003e96f58;  0 drivers
+v0000000003f298a0_0 .net8 "VGND", 0 0, L_00000000040feca0;  1 drivers, strength-aware
+L_00000000040fe6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f284a0_0 .net8 "VNB", 0 0, L_00000000040fe6f0;  1 drivers, strength-aware
+L_00000000040ff100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f28d60_0 .net8 "VPB", 0 0, L_00000000040ff100;  1 drivers, strength-aware
+v0000000003f28360_0 .net8 "VPWR", 0 0, L_00000000040fe530;  1 drivers, strength-aware
+v0000000003f27f00_0 .net *"_s10", 0 0, L_0000000003f987c0;  1 drivers
+L_000000000418b080 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f27140_0 .net/2u *"_s14", 0 0, L_000000000418b080;  1 drivers
+v0000000003f275a0_0 .net *"_s16", 0 0, L_0000000003f978c0;  1 drivers
+L_000000000418b0c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f28a40_0 .net/2u *"_s20", 0 0, L_000000000418b0c8;  1 drivers
+v0000000003f27e60_0 .net *"_s22", 0 0, L_0000000003f98900;  1 drivers
+v0000000003f28cc0_0 .net *"_s26", 0 0, L_0000000003f98ae0;  1 drivers
+L_000000000418b110 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f28040_0 .net/2u *"_s30", 0 0, L_000000000418b110;  1 drivers
+v0000000003f27640_0 .net *"_s32", 0 0, L_0000000003f97500;  1 drivers
+L_000000000418aff0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f27460_0 .net/2u *"_s4", 0 0, L_000000000418aff0;  1 drivers
+L_000000000418b038 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f27280_0 .net/2u *"_s8", 0 0, L_000000000418b038;  1 drivers
+v0000000003f27960_0 .net "awake", 0 0, L_0000000003f98720;  1 drivers
+v0000000003f28680_0 .net "buf_Q", 0 0, L_0000000004206900;  1 drivers
+v0000000003f28180_0 .net "cond0", 0 0, L_0000000004207070;  1 drivers
+v0000000003f29580_0 .net "cond1", 0 0, L_0000000004206e40;  1 drivers
+v0000000003f276e0_0 .net "cond2", 0 0, L_0000000004207230;  1 drivers
+v0000000003f280e0_0 .net "cond3", 0 0, L_0000000004207a80;  1 drivers
+v0000000003f27a00_0 .net "cond4", 0 0, L_00000000042083b0;  1 drivers
+v0000000003f28ae0_0 .net "mux_out", 0 0, L_0000000004207fc0;  1 drivers
+v0000000003f287c0_0 .var "notifier", 0 0;
+L_0000000003f98720 .cmp/eeq 1, L_00000000040fe530, L_000000000418aff0;
+L_0000000003f987c0 .cmp/eeq 1, o0000000003e96e98, L_000000000418b038;
+L_0000000003f978c0 .cmp/eeq 1, o0000000003e96f58, L_000000000418b080;
+L_0000000003f98900 .cmp/eeq 1, o0000000003e96f58, L_000000000418b0c8;
+L_0000000003f98ae0 .cmp/nee 1, o0000000003e96da8, o0000000003e96ef8;
+L_0000000003f97500 .cmp/eeq 1, o0000000003e96e68, L_000000000418b110;
+S_00000000028e9ca0 .scope module, "sky130_fd_sc_hd__sdfrtn_1" "sky130_fd_sc_hd__sdfrtn_1" 4 44917;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e97738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2b7e0_0 .net "CLK_N", 0 0, o0000000003e97738;  0 drivers
+o0000000003e97798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2c000_0 .net "D", 0 0, o0000000003e97798;  0 drivers
+v0000000003f2c0a0_0 .net "Q", 0 0, L_0000000004206b30;  1 drivers
+o0000000003e97858 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2b420_0 .net "RESET_B", 0 0, o0000000003e97858;  0 drivers
+o0000000003e978b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f299e0_0 .net "SCD", 0 0, o0000000003e978b8;  0 drivers
+o0000000003e97918 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2ade0_0 .net "SCE", 0 0, o0000000003e97918;  0 drivers
+L_00000000040fdce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a660_0 .net8 "VGND", 0 0, L_00000000040fdce0;  1 drivers, strength-aware
+L_00000000040fdc70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2bd80_0 .net8 "VNB", 0 0, L_00000000040fdc70;  1 drivers, strength-aware
+L_00000000040fdea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a700_0 .net8 "VPB", 0 0, L_00000000040fdea0;  1 drivers, strength-aware
+L_00000000040fdd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2b880_0 .net8 "VPWR", 0 0, L_00000000040fdd50;  1 drivers, strength-aware
+S_0000000003eea580 .scope module, "base" "sky130_fd_sc_hd__sdfrtn" 4 44939, 4 44766 1, S_00000000028e9ca0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK_N"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e97888 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206970 .functor NOT 1, o0000000003e97888, C4<0>, C4<0>, C4<0>;
+o0000000003e97768 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042080a0 .functor NOT 1, o0000000003e97768, C4<0>, C4<0>, C4<0>;
+o0000000003e977c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e978e8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e97948 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208110 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e977c8, o0000000003e978e8, o0000000003e97948;
+L_00000000040ff2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fe3e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004206a50 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000004208110, L_00000000042080a0, L_0000000004206970, v0000000003f2a520_0, L_00000000040ff2c0, L_00000000040fe3e0;
+L_0000000004208030 .functor AND 1, L_0000000003f98e00, L_0000000003f97960, C4<1>, C4<1>;
+L_0000000004207930 .functor AND 1, L_0000000003f989a0, L_0000000004208030, C4<1>, C4<1>;
+L_0000000004206ac0 .functor AND 1, L_0000000003f98ea0, L_0000000004208030, C4<1>, C4<1>;
+L_00000000042071c0 .functor AND 1, L_0000000003f97320, L_0000000004208030, C4<1>, C4<1>;
+L_00000000042081f0 .functor AND 1, L_0000000003f98e00, L_0000000003f98fe0, C4<1>, C4<1>;
+L_0000000004206b30 .functor BUF 1, L_0000000004206a50, C4<0>, C4<0>, C4<0>;
+v0000000003f28fe0_0 .net "CLK_N", 0 0, o0000000003e97738;  alias, 0 drivers
+v0000000003f27dc0_0 .net "CLK_N_delayed", 0 0, o0000000003e97768;  0 drivers
+v0000000003f29120_0 .net "D", 0 0, o0000000003e97798;  alias, 0 drivers
+v0000000003f293a0_0 .net "D_delayed", 0 0, o0000000003e977c8;  0 drivers
+v0000000003f291c0_0 .net "Q", 0 0, L_0000000004206b30;  alias, 1 drivers
+v0000000003f27c80_0 .net "RESET", 0 0, L_0000000004206970;  1 drivers
+v0000000003f27d20_0 .net "RESET_B", 0 0, o0000000003e97858;  alias, 0 drivers
+v0000000003f29260_0 .net "RESET_B_delayed", 0 0, o0000000003e97888;  0 drivers
+v0000000003f29300_0 .net "SCD", 0 0, o0000000003e978b8;  alias, 0 drivers
+v0000000003f29440_0 .net "SCD_delayed", 0 0, o0000000003e978e8;  0 drivers
+v0000000003f294e0_0 .net "SCE", 0 0, o0000000003e97918;  alias, 0 drivers
+v0000000003f29940_0 .net "SCE_delayed", 0 0, o0000000003e97948;  0 drivers
+v0000000003f2b560_0 .net8 "VGND", 0 0, L_00000000040fe3e0;  1 drivers, strength-aware
+L_00000000040fe4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f29da0_0 .net8 "VNB", 0 0, L_00000000040fe4c0;  1 drivers, strength-aware
+L_00000000040fe5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2be20_0 .net8 "VPB", 0 0, L_00000000040fe5a0;  1 drivers, strength-aware
+v0000000003f2bec0_0 .net8 "VPWR", 0 0, L_00000000040ff2c0;  1 drivers, strength-aware
+v0000000003f2aac0_0 .net *"_s10", 0 0, L_0000000003f97960;  1 drivers
+L_000000000418b1e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f29bc0_0 .net/2u *"_s14", 0 0, L_000000000418b1e8;  1 drivers
+v0000000003f2a5c0_0 .net *"_s16", 0 0, L_0000000003f989a0;  1 drivers
+L_000000000418b230 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2b1a0_0 .net/2u *"_s20", 0 0, L_000000000418b230;  1 drivers
+v0000000003f2b4c0_0 .net *"_s22", 0 0, L_0000000003f98ea0;  1 drivers
+v0000000003f29c60_0 .net *"_s26", 0 0, L_0000000003f97320;  1 drivers
+L_000000000418b278 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2b600_0 .net/2u *"_s30", 0 0, L_000000000418b278;  1 drivers
+v0000000003f2a200_0 .net *"_s32", 0 0, L_0000000003f98fe0;  1 drivers
+L_000000000418b158 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a480_0 .net/2u *"_s4", 0 0, L_000000000418b158;  1 drivers
+L_000000000418b1a0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2b6a0_0 .net/2u *"_s8", 0 0, L_000000000418b1a0;  1 drivers
+v0000000003f2af20_0 .net "awake", 0 0, L_0000000003f98e00;  1 drivers
+v0000000003f2ad40_0 .net "buf_Q", 0 0, L_0000000004206a50;  1 drivers
+v0000000003f2bf60_0 .net "cond0", 0 0, L_0000000004208030;  1 drivers
+v0000000003f2b2e0_0 .net "cond1", 0 0, L_0000000004207930;  1 drivers
+v0000000003f2b740_0 .net "cond2", 0 0, L_0000000004206ac0;  1 drivers
+v0000000003f2bce0_0 .net "cond3", 0 0, L_00000000042071c0;  1 drivers
+v0000000003f29e40_0 .net "cond4", 0 0, L_00000000042081f0;  1 drivers
+v0000000003f29d00_0 .net "intclk", 0 0, L_00000000042080a0;  1 drivers
+v0000000003f2b380_0 .net "mux_out", 0 0, L_0000000004208110;  1 drivers
+v0000000003f2a520_0 .var "notifier", 0 0;
+L_0000000003f98e00 .cmp/eeq 1, L_00000000040ff2c0, L_000000000418b158;
+L_0000000003f97960 .cmp/eeq 1, o0000000003e97888, L_000000000418b1a0;
+L_0000000003f989a0 .cmp/eeq 1, o0000000003e97948, L_000000000418b1e8;
+L_0000000003f98ea0 .cmp/eeq 1, o0000000003e97948, L_000000000418b230;
+L_0000000003f97320 .cmp/nee 1, o0000000003e977c8, o0000000003e978e8;
+L_0000000003f98fe0 .cmp/eeq 1, o0000000003e97858, L_000000000418b278;
+S_00000000028ead20 .scope module, "sky130_fd_sc_hd__sdfrtp_1" "sky130_fd_sc_hd__sdfrtp_1" 4 88789;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e980f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2e1c0_0 .net "CLK", 0 0, o0000000003e980f8;  0 drivers
+o0000000003e98158 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2dc20_0 .net "D", 0 0, o0000000003e98158;  0 drivers
+v0000000003f2da40_0 .net "Q", 0 0, L_0000000004206cf0;  1 drivers
+o0000000003e98218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2dd60_0 .net "RESET_B", 0 0, o0000000003e98218;  0 drivers
+o0000000003e98278 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2cfa0_0 .net "SCD", 0 0, o0000000003e98278;  0 drivers
+o0000000003e982d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2e4e0_0 .net "SCE", 0 0, o0000000003e982d8;  0 drivers
+L_00000000040ff330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2c5a0_0 .net8 "VGND", 0 0, L_00000000040ff330;  1 drivers, strength-aware
+L_00000000040fdff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2e800_0 .net8 "VNB", 0 0, L_00000000040fdff0;  1 drivers, strength-aware
+L_00000000040fe990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2c640_0 .net8 "VPB", 0 0, L_00000000040fe990;  1 drivers, strength-aware
+L_00000000040fe610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2cc80_0 .net8 "VPWR", 0 0, L_00000000040fe610;  1 drivers, strength-aware
+S_0000000003eea700 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88811, 4 88390 1, S_00000000028ead20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e98248 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207a10 .functor NOT 1, o0000000003e98248, C4<0>, C4<0>, C4<0>;
+o0000000003e98188 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e982a8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e98308 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207380 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e98188, o0000000003e982a8, o0000000003e98308;
+o0000000003e98128 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040fd9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fe220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004206eb0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000004207380, o0000000003e98128, L_0000000004207a10, v0000000003f2dcc0_0, L_00000000040fd9d0, L_00000000040fe220;
+L_0000000004206c10 .functor AND 1, L_0000000003f99300, L_0000000003f99080, C4<1>, C4<1>;
+L_0000000004207c40 .functor AND 1, L_0000000003f99120, L_0000000004206c10, C4<1>, C4<1>;
+L_0000000004206ba0 .functor AND 1, L_0000000003f97aa0, L_0000000004206c10, C4<1>, C4<1>;
+L_0000000004207af0 .functor AND 1, L_0000000003f99260, L_0000000004206c10, C4<1>, C4<1>;
+L_0000000004207b60 .functor AND 1, L_0000000003f993a0, L_0000000003f99080, C4<1>, C4<1>;
+L_0000000004206cf0 .functor BUF 1, L_0000000004206eb0, C4<0>, C4<0>, C4<0>;
+v0000000003f2ae80_0 .net "CLK", 0 0, o0000000003e980f8;  alias, 0 drivers
+v0000000003f2b920_0 .net "CLK_delayed", 0 0, o0000000003e98128;  0 drivers
+v0000000003f29a80_0 .net "D", 0 0, o0000000003e98158;  alias, 0 drivers
+v0000000003f2b240_0 .net "D_delayed", 0 0, o0000000003e98188;  0 drivers
+v0000000003f2b9c0_0 .net "Q", 0 0, L_0000000004206cf0;  alias, 1 drivers
+v0000000003f2afc0_0 .net "RESET", 0 0, L_0000000004207a10;  1 drivers
+v0000000003f2ba60_0 .net "RESET_B", 0 0, o0000000003e98218;  alias, 0 drivers
+v0000000003f2bb00_0 .net "RESET_B_delayed", 0 0, o0000000003e98248;  0 drivers
+v0000000003f2bba0_0 .net "SCD", 0 0, o0000000003e98278;  alias, 0 drivers
+v0000000003f2a2a0_0 .net "SCD_delayed", 0 0, o0000000003e982a8;  0 drivers
+v0000000003f29ee0_0 .net "SCE", 0 0, o0000000003e982d8;  alias, 0 drivers
+v0000000003f2a0c0_0 .net "SCE_delayed", 0 0, o0000000003e98308;  0 drivers
+v0000000003f2a7a0_0 .net8 "VGND", 0 0, L_00000000040fe220;  1 drivers, strength-aware
+L_00000000040fdab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f29b20_0 .net8 "VNB", 0 0, L_00000000040fdab0;  1 drivers, strength-aware
+L_00000000040ff250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a840_0 .net8 "VPB", 0 0, L_00000000040ff250;  1 drivers, strength-aware
+v0000000003f2aca0_0 .net8 "VPWR", 0 0, L_00000000040fd9d0;  1 drivers, strength-aware
+v0000000003f2ab60_0 .net *"_s10", 0 0, L_0000000003f99300;  1 drivers
+L_000000000418b350 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f2bc40_0 .net/2u *"_s14", 0 0, L_000000000418b350;  1 drivers
+v0000000003f29f80_0 .net *"_s16", 0 0, L_0000000003f99120;  1 drivers
+L_000000000418b398 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a020_0 .net/2u *"_s20", 0 0, L_000000000418b398;  1 drivers
+v0000000003f2a160_0 .net *"_s22", 0 0, L_0000000003f97aa0;  1 drivers
+v0000000003f2ac00_0 .net *"_s26", 0 0, L_0000000003f99260;  1 drivers
+L_000000000418b3e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a340_0 .net/2u *"_s30", 0 0, L_000000000418b3e0;  1 drivers
+v0000000003f2a3e0_0 .net *"_s32", 0 0, L_0000000003f993a0;  1 drivers
+L_000000000418b2c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2b060_0 .net/2u *"_s4", 0 0, L_000000000418b2c0;  1 drivers
+L_000000000418b308 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2a8e0_0 .net/2u *"_s8", 0 0, L_000000000418b308;  1 drivers
+v0000000003f2a980_0 .net "awake", 0 0, L_0000000003f99080;  1 drivers
+v0000000003f2aa20_0 .net "buf_Q", 0 0, L_0000000004206eb0;  1 drivers
+v0000000003f2b100_0 .net "cond0", 0 0, L_0000000004206c10;  1 drivers
+v0000000003f2db80_0 .net "cond1", 0 0, L_0000000004207c40;  1 drivers
+v0000000003f2dea0_0 .net "cond2", 0 0, L_0000000004206ba0;  1 drivers
+v0000000003f2e760_0 .net "cond3", 0 0, L_0000000004207af0;  1 drivers
+v0000000003f2c3c0_0 .net "cond4", 0 0, L_0000000004207b60;  1 drivers
+v0000000003f2df40_0 .net "mux_out", 0 0, L_0000000004207380;  1 drivers
+v0000000003f2dcc0_0 .var "notifier", 0 0;
+L_0000000003f99080 .cmp/eeq 1, L_00000000040fd9d0, L_000000000418b2c0;
+L_0000000003f99300 .cmp/eeq 1, o0000000003e98248, L_000000000418b308;
+L_0000000003f99120 .cmp/eeq 1, o0000000003e98308, L_000000000418b350;
+L_0000000003f97aa0 .cmp/eeq 1, o0000000003e98308, L_000000000418b398;
+L_0000000003f99260 .cmp/nee 1, o0000000003e98188, o0000000003e982a8;
+L_0000000003f993a0 .cmp/eeq 1, o0000000003e98218, L_000000000418b3e0;
+S_00000000028ea720 .scope module, "sky130_fd_sc_hd__sdfrtp_2" "sky130_fd_sc_hd__sdfrtp_2" 4 88539;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e98a88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2d720_0 .net "CLK", 0 0, o0000000003e98a88;  0 drivers
+o0000000003e98ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2c460_0 .net "D", 0 0, o0000000003e98ae8;  0 drivers
+v0000000003f2c960_0 .net "Q", 0 0, L_00000000042072a0;  1 drivers
+o0000000003e98ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2d9a0_0 .net "RESET_B", 0 0, o0000000003e98ba8;  0 drivers
+o0000000003e98c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2d040_0 .net "SCD", 0 0, o0000000003e98c08;  0 drivers
+o0000000003e98c68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2cb40_0 .net "SCE", 0 0, o0000000003e98c68;  0 drivers
+L_00000000040fe760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2cbe0_0 .net8 "VGND", 0 0, L_00000000040fe760;  1 drivers, strength-aware
+L_00000000040fdf10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2d180_0 .net8 "VNB", 0 0, L_00000000040fdf10;  1 drivers, strength-aware
+L_00000000040fe840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2d2c0_0 .net8 "VPB", 0 0, L_00000000040fe840;  1 drivers, strength-aware
+L_00000000040fdf80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2d400_0 .net8 "VPWR", 0 0, L_00000000040fdf80;  1 drivers, strength-aware
+S_0000000003eed580 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88561, 4 88390 1, S_00000000028ea720;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e98bd8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206d60 .functor NOT 1, o0000000003e98bd8, C4<0>, C4<0>, C4<0>;
+o0000000003e98b18 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e98c38 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e98c98 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208420 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e98b18, o0000000003e98c38, o0000000003e98c98;
+o0000000003e98ab8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040fe290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fe680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004207310 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000004208420, o0000000003e98ab8, L_0000000004206d60, v0000000003f2c280_0, L_00000000040fe290, L_00000000040fe680;
+L_0000000004206dd0 .functor AND 1, L_0000000003f99580, L_0000000003f97b40, C4<1>, C4<1>;
+L_0000000004207cb0 .functor AND 1, L_0000000003f973c0, L_0000000004206dd0, C4<1>, C4<1>;
+L_00000000042079a0 .functor AND 1, L_0000000003f9ad40, L_0000000004206dd0, C4<1>, C4<1>;
+L_0000000004207e00 .functor AND 1, L_0000000003f9a520, L_0000000004206dd0, C4<1>, C4<1>;
+L_0000000004206f20 .functor AND 1, L_0000000003f9a5c0, L_0000000003f97b40, C4<1>, C4<1>;
+L_00000000042072a0 .functor BUF 1, L_0000000004207310, C4<0>, C4<0>, C4<0>;
+v0000000003f2cd20_0 .net "CLK", 0 0, o0000000003e98a88;  alias, 0 drivers
+v0000000003f2de00_0 .net "CLK_delayed", 0 0, o0000000003e98ab8;  0 drivers
+v0000000003f2e620_0 .net "D", 0 0, o0000000003e98ae8;  alias, 0 drivers
+v0000000003f2d540_0 .net "D_delayed", 0 0, o0000000003e98b18;  0 drivers
+v0000000003f2cdc0_0 .net "Q", 0 0, L_00000000042072a0;  alias, 1 drivers
+v0000000003f2c6e0_0 .net "RESET", 0 0, L_0000000004206d60;  1 drivers
+v0000000003f2dae0_0 .net "RESET_B", 0 0, o0000000003e98ba8;  alias, 0 drivers
+v0000000003f2dfe0_0 .net "RESET_B_delayed", 0 0, o0000000003e98bd8;  0 drivers
+v0000000003f2e080_0 .net "SCD", 0 0, o0000000003e98c08;  alias, 0 drivers
+v0000000003f2ce60_0 .net "SCD_delayed", 0 0, o0000000003e98c38;  0 drivers
+v0000000003f2c140_0 .net "SCE", 0 0, o0000000003e98c68;  alias, 0 drivers
+v0000000003f2caa0_0 .net "SCE_delayed", 0 0, o0000000003e98c98;  0 drivers
+v0000000003f2e120_0 .net8 "VGND", 0 0, L_00000000040fe680;  1 drivers, strength-aware
+L_00000000040fe060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2e260_0 .net8 "VNB", 0 0, L_00000000040fe060;  1 drivers, strength-aware
+L_00000000040fe7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2c820_0 .net8 "VPB", 0 0, L_00000000040fe7d0;  1 drivers, strength-aware
+v0000000003f2e300_0 .net8 "VPWR", 0 0, L_00000000040fe290;  1 drivers, strength-aware
+v0000000003f2d4a0_0 .net *"_s10", 0 0, L_0000000003f99580;  1 drivers
+L_000000000418b4b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f2d0e0_0 .net/2u *"_s14", 0 0, L_000000000418b4b8;  1 drivers
+v0000000003f2e3a0_0 .net *"_s16", 0 0, L_0000000003f973c0;  1 drivers
+L_000000000418b500 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2d220_0 .net/2u *"_s20", 0 0, L_000000000418b500;  1 drivers
+v0000000003f2e440_0 .net *"_s22", 0 0, L_0000000003f9ad40;  1 drivers
+v0000000003f2e580_0 .net *"_s26", 0 0, L_0000000003f9a520;  1 drivers
+L_000000000418b548 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2e6c0_0 .net/2u *"_s30", 0 0, L_000000000418b548;  1 drivers
+v0000000003f2ca00_0 .net *"_s32", 0 0, L_0000000003f9a5c0;  1 drivers
+L_000000000418b428 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2c500_0 .net/2u *"_s4", 0 0, L_000000000418b428;  1 drivers
+L_000000000418b470 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2c780_0 .net/2u *"_s8", 0 0, L_000000000418b470;  1 drivers
+v0000000003f2c320_0 .net "awake", 0 0, L_0000000003f97b40;  1 drivers
+v0000000003f2cf00_0 .net "buf_Q", 0 0, L_0000000004207310;  1 drivers
+v0000000003f2d5e0_0 .net "cond0", 0 0, L_0000000004206dd0;  1 drivers
+v0000000003f2d360_0 .net "cond1", 0 0, L_0000000004207cb0;  1 drivers
+v0000000003f2c8c0_0 .net "cond2", 0 0, L_00000000042079a0;  1 drivers
+v0000000003f2e8a0_0 .net "cond3", 0 0, L_0000000004207e00;  1 drivers
+v0000000003f2c1e0_0 .net "cond4", 0 0, L_0000000004206f20;  1 drivers
+v0000000003f2d680_0 .net "mux_out", 0 0, L_0000000004208420;  1 drivers
+v0000000003f2c280_0 .var "notifier", 0 0;
+L_0000000003f97b40 .cmp/eeq 1, L_00000000040fe290, L_000000000418b428;
+L_0000000003f99580 .cmp/eeq 1, o0000000003e98bd8, L_000000000418b470;
+L_0000000003f973c0 .cmp/eeq 1, o0000000003e98c98, L_000000000418b4b8;
+L_0000000003f9ad40 .cmp/eeq 1, o0000000003e98c98, L_000000000418b500;
+L_0000000003f9a520 .cmp/nee 1, o0000000003e98b18, o0000000003e98c38;
+L_0000000003f9a5c0 .cmp/eeq 1, o0000000003e98ba8, L_000000000418b548;
+S_00000000028eaea0 .scope module, "sky130_fd_sc_hd__sdfrtp_4" "sky130_fd_sc_hd__sdfrtp_4" 4 88664;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e99418 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f2f200_0 .net "CLK", 0 0, o0000000003e99418;  0 drivers
+o0000000003e99478 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f30600_0 .net "D", 0 0, o0000000003e99478;  0 drivers
+v0000000003f306a0_0 .net "Q", 0 0, L_0000000004207770;  1 drivers
+o0000000003e99538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f30240_0 .net "RESET_B", 0 0, o0000000003e99538;  0 drivers
+o0000000003e99598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f30920_0 .net "SCD", 0 0, o0000000003e99598;  0 drivers
+o0000000003e995f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f302e0_0 .net "SCE", 0 0, o0000000003e995f8;  0 drivers
+L_00000000040fed80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f30740_0 .net8 "VGND", 0 0, L_00000000040fed80;  1 drivers, strength-aware
+L_00000000040fe8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2e9e0_0 .net8 "VNB", 0 0, L_00000000040fe8b0;  1 drivers, strength-aware
+L_00000000040fe1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2f160_0 .net8 "VPB", 0 0, L_00000000040fe1b0;  1 drivers, strength-aware
+L_00000000040ff3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2f480_0 .net8 "VPWR", 0 0, L_00000000040ff3a0;  1 drivers, strength-aware
+S_0000000003eede80 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88686, 4 88390 1, S_00000000028eaea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "RESET_B"
+o0000000003e99568 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207e70 .functor NOT 1, o0000000003e99568, C4<0>, C4<0>, C4<0>;
+o0000000003e994a8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e995c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e99628 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004206f90 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e994a8, o0000000003e995c8, o0000000003e99628;
+o0000000003e99448 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040febc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040fda40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000042073f0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000004206f90, o0000000003e99448, L_0000000004207e70, v0000000003f310a0_0, L_00000000040febc0, L_00000000040fda40;
+L_00000000042074d0 .functor AND 1, L_0000000003f9c0a0, L_0000000003f9b380, C4<1>, C4<1>;
+L_0000000004207540 .functor AND 1, L_0000000003f99bc0, L_00000000042074d0, C4<1>, C4<1>;
+L_00000000042075b0 .functor AND 1, L_0000000003f9b420, L_00000000042074d0, C4<1>, C4<1>;
+L_0000000004207620 .functor AND 1, L_0000000003f9af20, L_00000000042074d0, C4<1>, C4<1>;
+L_0000000004207690 .functor AND 1, L_0000000003f9b060, L_0000000003f9b380, C4<1>, C4<1>;
+L_0000000004207770 .functor BUF 1, L_00000000042073f0, C4<0>, C4<0>, C4<0>;
+v0000000003f2d7c0_0 .net "CLK", 0 0, o0000000003e99418;  alias, 0 drivers
+v0000000003f2d860_0 .net "CLK_delayed", 0 0, o0000000003e99448;  0 drivers
+v0000000003f2d900_0 .net "D", 0 0, o0000000003e99478;  alias, 0 drivers
+v0000000003f2eda0_0 .net "D_delayed", 0 0, o0000000003e994a8;  0 drivers
+v0000000003f2ec60_0 .net "Q", 0 0, L_0000000004207770;  alias, 1 drivers
+v0000000003f30ec0_0 .net "RESET", 0 0, L_0000000004207e70;  1 drivers
+v0000000003f2f520_0 .net "RESET_B", 0 0, o0000000003e99538;  alias, 0 drivers
+v0000000003f2ed00_0 .net "RESET_B_delayed", 0 0, o0000000003e99568;  0 drivers
+v0000000003f30880_0 .net "SCD", 0 0, o0000000003e99598;  alias, 0 drivers
+v0000000003f30d80_0 .net "SCD_delayed", 0 0, o0000000003e995c8;  0 drivers
+v0000000003f2e940_0 .net "SCE", 0 0, o0000000003e995f8;  alias, 0 drivers
+v0000000003f2f840_0 .net "SCE_delayed", 0 0, o0000000003e99628;  0 drivers
+v0000000003f2eee0_0 .net8 "VGND", 0 0, L_00000000040fda40;  1 drivers, strength-aware
+L_00000000040fe920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f30ce0_0 .net8 "VNB", 0 0, L_00000000040fe920;  1 drivers, strength-aware
+L_00000000040feb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2fde0_0 .net8 "VPB", 0 0, L_00000000040feb50;  1 drivers, strength-aware
+v0000000003f307e0_0 .net8 "VPWR", 0 0, L_00000000040febc0;  1 drivers, strength-aware
+v0000000003f2f5c0_0 .net *"_s10", 0 0, L_0000000003f9c0a0;  1 drivers
+L_000000000418b620 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f2f660_0 .net/2u *"_s14", 0 0, L_000000000418b620;  1 drivers
+v0000000003f30ba0_0 .net *"_s16", 0 0, L_0000000003f99bc0;  1 drivers
+L_000000000418b668 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f2f7a0_0 .net/2u *"_s20", 0 0, L_000000000418b668;  1 drivers
+v0000000003f2ef80_0 .net *"_s22", 0 0, L_0000000003f9b420;  1 drivers
+v0000000003f2f020_0 .net *"_s26", 0 0, L_0000000003f9af20;  1 drivers
+L_000000000418b6b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f304c0_0 .net/2u *"_s30", 0 0, L_000000000418b6b0;  1 drivers
+v0000000003f2f980_0 .net *"_s32", 0 0, L_0000000003f9b060;  1 drivers
+L_000000000418b590 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f30e20_0 .net/2u *"_s4", 0 0, L_000000000418b590;  1 drivers
+L_000000000418b5d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f30b00_0 .net/2u *"_s8", 0 0, L_000000000418b5d8;  1 drivers
+v0000000003f30560_0 .net "awake", 0 0, L_0000000003f9b380;  1 drivers
+v0000000003f2ee40_0 .net "buf_Q", 0 0, L_00000000042073f0;  1 drivers
+v0000000003f30f60_0 .net "cond0", 0 0, L_00000000042074d0;  1 drivers
+v0000000003f31000_0 .net "cond1", 0 0, L_0000000004207540;  1 drivers
+v0000000003f2fac0_0 .net "cond2", 0 0, L_00000000042075b0;  1 drivers
+v0000000003f2fca0_0 .net "cond3", 0 0, L_0000000004207620;  1 drivers
+v0000000003f2f700_0 .net "cond4", 0 0, L_0000000004207690;  1 drivers
+v0000000003f2f0c0_0 .net "mux_out", 0 0, L_0000000004206f90;  1 drivers
+v0000000003f310a0_0 .var "notifier", 0 0;
+L_0000000003f9b380 .cmp/eeq 1, L_00000000040febc0, L_000000000418b590;
+L_0000000003f9c0a0 .cmp/eeq 1, o0000000003e99568, L_000000000418b5d8;
+L_0000000003f99bc0 .cmp/eeq 1, o0000000003e99628, L_000000000418b620;
+L_0000000003f9b420 .cmp/eeq 1, o0000000003e99628, L_000000000418b668;
+L_0000000003f9af20 .cmp/nee 1, o0000000003e994a8, o0000000003e995c8;
+L_0000000003f9b060 .cmp/eeq 1, o0000000003e99538, L_000000000418b6b0;
+S_00000000028e9220 .scope module, "sky130_fd_sc_hd__sdfsbp_1" "sky130_fd_sc_hd__sdfsbp_1" 4 79454;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "SET_B"
+o0000000003e99da8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f33620_0 .net "CLK", 0 0, o0000000003e99da8;  0 drivers
+o0000000003e99e08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f31140_0 .net "D", 0 0, o0000000003e99e08;  0 drivers
+v0000000003f329a0_0 .net "Q", 0 0, L_0000000004209140;  1 drivers
+v0000000003f32b80_0 .net "Q_N", 0 0, L_0000000004209c30;  1 drivers
+o0000000003e99ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f32ea0_0 .net "SCD", 0 0, o0000000003e99ec8;  0 drivers
+o0000000003e99f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f338a0_0 .net "SCE", 0 0, o0000000003e99f28;  0 drivers
+o0000000003e99fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f31e60_0 .net "SET_B", 0 0, o0000000003e99fb8;  0 drivers
+L_00000000040fec30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f32f40_0 .net8 "VGND", 0 0, L_00000000040fec30;  1 drivers, strength-aware
+L_00000000040fed10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f32cc0_0 .net8 "VNB", 0 0, L_00000000040fed10;  1 drivers, strength-aware
+L_00000000040fedf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f322c0_0 .net8 "VPB", 0 0, L_00000000040fedf0;  1 drivers, strength-aware
+L_00000000040ff6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f32d60_0 .net8 "VPWR", 0 0, L_00000000040ff6b0;  1 drivers, strength-aware
+S_0000000003eed880 .scope module, "base" "sky130_fd_sc_hd__sdfsbp" 4 79478, 4 79299 1, S_00000000028e9220;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "SET_B"
+o0000000003e99fe8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004207700 .functor NOT 1, o0000000003e99fe8, C4<0>, C4<0>, C4<0>;
+o0000000003e99e38 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e99ef8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e99f58 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004209920 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e99e38, o0000000003e99ef8, o0000000003e99f58;
+o0000000003e99dd8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041007c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000041002f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004208ea0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000004209920, o0000000003e99dd8, L_0000000004207700, v0000000003f32400_0, L_00000000041007c0, L_00000000041002f0;
+L_0000000004209610 .functor AND 1, L_0000000003f9c000, L_0000000003f9b600, C4<1>, C4<1>;
+L_0000000004209d80 .functor AND 1, L_0000000003f9bba0, L_0000000004209610, C4<1>, C4<1>;
+L_0000000004209bc0 .functor AND 1, L_0000000003f9ba60, L_0000000004209610, C4<1>, C4<1>;
+L_0000000004209680 .functor AND 1, L_0000000003f999e0, L_0000000004209610, C4<1>, C4<1>;
+L_0000000004208a40 .functor AND 1, L_0000000003f9a660, L_0000000003f9b600, C4<1>, C4<1>;
+L_0000000004209140 .functor BUF 1, L_0000000004208ea0, C4<0>, C4<0>, C4<0>;
+L_0000000004209c30 .functor NOT 1, L_0000000004208ea0, C4<0>, C4<0>, C4<0>;
+v0000000003f2f8e0_0 .net "CLK", 0 0, o0000000003e99da8;  alias, 0 drivers
+v0000000003f309c0_0 .net "CLK_delayed", 0 0, o0000000003e99dd8;  0 drivers
+v0000000003f2ea80_0 .net "D", 0 0, o0000000003e99e08;  alias, 0 drivers
+v0000000003f2fd40_0 .net "D_delayed", 0 0, o0000000003e99e38;  0 drivers
+v0000000003f2fa20_0 .net "Q", 0 0, L_0000000004209140;  alias, 1 drivers
+v0000000003f2f2a0_0 .net "Q_N", 0 0, L_0000000004209c30;  alias, 1 drivers
+v0000000003f30380_0 .net "SCD", 0 0, o0000000003e99ec8;  alias, 0 drivers
+v0000000003f30420_0 .net "SCD_delayed", 0 0, o0000000003e99ef8;  0 drivers
+v0000000003f30a60_0 .net "SCE", 0 0, o0000000003e99f28;  alias, 0 drivers
+v0000000003f2fb60_0 .net "SCE_delayed", 0 0, o0000000003e99f58;  0 drivers
+v0000000003f2eb20_0 .net "SET", 0 0, L_0000000004207700;  1 drivers
+v0000000003f2f340_0 .net "SET_B", 0 0, o0000000003e99fb8;  alias, 0 drivers
+v0000000003f30c40_0 .net "SET_B_delayed", 0 0, o0000000003e99fe8;  0 drivers
+v0000000003f2ebc0_0 .net8 "VGND", 0 0, L_00000000041002f0;  1 drivers, strength-aware
+L_00000000040ffd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f2f3e0_0 .net8 "VNB", 0 0, L_00000000040ffd40;  1 drivers, strength-aware
+L_0000000004100750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f2fc00_0 .net8 "VPB", 0 0, L_0000000004100750;  1 drivers, strength-aware
+v0000000003f2fe80_0 .net8 "VPWR", 0 0, L_00000000041007c0;  1 drivers, strength-aware
+v0000000003f2ff20_0 .net *"_s10", 0 0, L_0000000003f9c000;  1 drivers
+L_000000000418b788 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f2ffc0_0 .net/2u *"_s14", 0 0, L_000000000418b788;  1 drivers
+v0000000003f30060_0 .net *"_s16", 0 0, L_0000000003f9bba0;  1 drivers
+L_000000000418b7d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f30100_0 .net/2u *"_s20", 0 0, L_000000000418b7d0;  1 drivers
+v0000000003f301a0_0 .net *"_s22", 0 0, L_0000000003f9ba60;  1 drivers
+v0000000003f32c20_0 .net *"_s26", 0 0, L_0000000003f999e0;  1 drivers
+L_000000000418b818 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f31820_0 .net/2u *"_s30", 0 0, L_000000000418b818;  1 drivers
+v0000000003f31500_0 .net *"_s32", 0 0, L_0000000003f9a660;  1 drivers
+L_000000000418b6f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f318c0_0 .net/2u *"_s4", 0 0, L_000000000418b6f8;  1 drivers
+L_000000000418b740 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f315a0_0 .net/2u *"_s8", 0 0, L_000000000418b740;  1 drivers
+v0000000003f31dc0_0 .net "awake", 0 0, L_0000000003f9b600;  1 drivers
+v0000000003f324a0_0 .net "buf_Q", 0 0, L_0000000004208ea0;  1 drivers
+v0000000003f32360_0 .net "cond0", 0 0, L_0000000004209610;  1 drivers
+v0000000003f31960_0 .net "cond1", 0 0, L_0000000004209d80;  1 drivers
+v0000000003f33300_0 .net "cond2", 0 0, L_0000000004209bc0;  1 drivers
+v0000000003f336c0_0 .net "cond3", 0 0, L_0000000004209680;  1 drivers
+v0000000003f325e0_0 .net "cond4", 0 0, L_0000000004208a40;  1 drivers
+v0000000003f32ae0_0 .net "mux_out", 0 0, L_0000000004209920;  1 drivers
+v0000000003f32400_0 .var "notifier", 0 0;
+L_0000000003f9b600 .cmp/eeq 1, L_00000000041007c0, L_000000000418b6f8;
+L_0000000003f9c000 .cmp/eeq 1, o0000000003e99fe8, L_000000000418b740;
+L_0000000003f9bba0 .cmp/eeq 1, o0000000003e99f58, L_000000000418b788;
+L_0000000003f9ba60 .cmp/eeq 1, o0000000003e99f58, L_000000000418b7d0;
+L_0000000003f999e0 .cmp/nee 1, o0000000003e99e38, o0000000003e99ef8;
+L_0000000003f9a660 .cmp/eeq 1, o0000000003e99fb8, L_000000000418b818;
+S_00000000028ea8a0 .scope module, "sky130_fd_sc_hd__sdfsbp_2" "sky130_fd_sc_hd__sdfsbp_2" 4 79585;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "SET_B"
+o0000000003e9a7c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f33800_0 .net "CLK", 0 0, o0000000003e9a7c8;  0 drivers
+o0000000003e9a828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f313c0_0 .net "D", 0 0, o0000000003e9a828;  0 drivers
+v0000000003f32900_0 .net "Q", 0 0, L_0000000004208d50;  1 drivers
+v0000000003f35ce0_0 .net "Q_N", 0 0, L_0000000004209990;  1 drivers
+o0000000003e9a8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f33da0_0 .net "SCD", 0 0, o0000000003e9a8e8;  0 drivers
+o0000000003e9a948 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f34160_0 .net "SCE", 0 0, o0000000003e9a948;  0 drivers
+o0000000003e9a9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f351a0_0 .net "SET_B", 0 0, o0000000003e9a9d8;  0 drivers
+L_00000000040ffe20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f34de0_0 .net8 "VGND", 0 0, L_00000000040ffe20;  1 drivers, strength-aware
+L_00000000040ffcd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f359c0_0 .net8 "VNB", 0 0, L_00000000040ffcd0;  1 drivers, strength-aware
+L_0000000004100a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f35740_0 .net8 "VPB", 0 0, L_0000000004100a60;  1 drivers, strength-aware
+L_0000000004100ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f35560_0 .net8 "VPWR", 0 0, L_0000000004100ad0;  1 drivers, strength-aware
+S_0000000003eece00 .scope module, "base" "sky130_fd_sc_hd__sdfsbp" 4 79609, 4 79299 1, S_00000000028ea8a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+    .port_info 6 /INPUT 1 "SET_B"
+o0000000003e9aa08 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004209220 .functor NOT 1, o0000000003e9aa08, C4<0>, C4<0>, C4<0>;
+o0000000003e9a858 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9a918 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9a978 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042098b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9a858, o0000000003e9a918, o0000000003e9a978;
+o0000000003e9a7f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004100de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004100d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004209e60 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_00000000042098b0, o0000000003e9a7f8, L_0000000004209220, v0000000003f31280_0, L_0000000004100de0, L_0000000004100d70;
+L_0000000004208ce0 .functor AND 1, L_0000000003f9b4c0, L_0000000003f9bf60, C4<1>, C4<1>;
+L_0000000004209ae0 .functor AND 1, L_0000000003f9b240, L_0000000004208ce0, C4<1>, C4<1>;
+L_0000000004209a00 .functor AND 1, L_0000000003f9b2e0, L_0000000004208ce0, C4<1>, C4<1>;
+L_0000000004209450 .functor AND 1, L_0000000003f9bce0, L_0000000004208ce0, C4<1>, C4<1>;
+L_0000000004209ed0 .functor AND 1, L_0000000003f99c60, L_0000000003f9bf60, C4<1>, C4<1>;
+L_0000000004208d50 .functor BUF 1, L_0000000004209e60, C4<0>, C4<0>, C4<0>;
+L_0000000004209990 .functor NOT 1, L_0000000004209e60, C4<0>, C4<0>, C4<0>;
+v0000000003f31fa0_0 .net "CLK", 0 0, o0000000003e9a7c8;  alias, 0 drivers
+v0000000003f31640_0 .net "CLK_delayed", 0 0, o0000000003e9a7f8;  0 drivers
+v0000000003f311e0_0 .net "D", 0 0, o0000000003e9a828;  alias, 0 drivers
+v0000000003f316e0_0 .net "D_delayed", 0 0, o0000000003e9a858;  0 drivers
+v0000000003f31a00_0 .net "Q", 0 0, L_0000000004208d50;  alias, 1 drivers
+v0000000003f33080_0 .net "Q_N", 0 0, L_0000000004209990;  alias, 1 drivers
+v0000000003f32720_0 .net "SCD", 0 0, o0000000003e9a8e8;  alias, 0 drivers
+v0000000003f31be0_0 .net "SCD_delayed", 0 0, o0000000003e9a918;  0 drivers
+v0000000003f31320_0 .net "SCE", 0 0, o0000000003e9a948;  alias, 0 drivers
+v0000000003f31780_0 .net "SCE_delayed", 0 0, o0000000003e9a978;  0 drivers
+v0000000003f334e0_0 .net "SET", 0 0, L_0000000004209220;  1 drivers
+v0000000003f32680_0 .net "SET_B", 0 0, o0000000003e9a9d8;  alias, 0 drivers
+v0000000003f32fe0_0 .net "SET_B_delayed", 0 0, o0000000003e9aa08;  0 drivers
+v0000000003f31f00_0 .net8 "VGND", 0 0, L_0000000004100d70;  1 drivers, strength-aware
+L_0000000004100600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f33120_0 .net8 "VNB", 0 0, L_0000000004100600;  1 drivers, strength-aware
+L_0000000004100bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f32e00_0 .net8 "VPB", 0 0, L_0000000004100bb0;  1 drivers, strength-aware
+v0000000003f333a0_0 .net8 "VPWR", 0 0, L_0000000004100de0;  1 drivers, strength-aware
+v0000000003f31aa0_0 .net *"_s10", 0 0, L_0000000003f9b4c0;  1 drivers
+L_000000000418b8f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f31b40_0 .net/2u *"_s14", 0 0, L_000000000418b8f0;  1 drivers
+v0000000003f31c80_0 .net *"_s16", 0 0, L_0000000003f9b240;  1 drivers
+L_000000000418b938 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f331c0_0 .net/2u *"_s20", 0 0, L_000000000418b938;  1 drivers
+v0000000003f32180_0 .net *"_s22", 0 0, L_0000000003f9b2e0;  1 drivers
+v0000000003f32540_0 .net *"_s26", 0 0, L_0000000003f9bce0;  1 drivers
+L_000000000418b980 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f33440_0 .net/2u *"_s30", 0 0, L_000000000418b980;  1 drivers
+v0000000003f33260_0 .net *"_s32", 0 0, L_0000000003f99c60;  1 drivers
+L_000000000418b860 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f31d20_0 .net/2u *"_s4", 0 0, L_000000000418b860;  1 drivers
+L_000000000418b8a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f32040_0 .net/2u *"_s8", 0 0, L_000000000418b8a8;  1 drivers
+v0000000003f327c0_0 .net "awake", 0 0, L_0000000003f9bf60;  1 drivers
+v0000000003f32860_0 .net "buf_Q", 0 0, L_0000000004209e60;  1 drivers
+v0000000003f320e0_0 .net "cond0", 0 0, L_0000000004208ce0;  1 drivers
+v0000000003f32220_0 .net "cond1", 0 0, L_0000000004209ae0;  1 drivers
+v0000000003f32a40_0 .net "cond2", 0 0, L_0000000004209a00;  1 drivers
+v0000000003f33760_0 .net "cond3", 0 0, L_0000000004209450;  1 drivers
+v0000000003f31460_0 .net "cond4", 0 0, L_0000000004209ed0;  1 drivers
+v0000000003f33580_0 .net "mux_out", 0 0, L_00000000042098b0;  1 drivers
+v0000000003f31280_0 .var "notifier", 0 0;
+L_0000000003f9bf60 .cmp/eeq 1, L_0000000004100de0, L_000000000418b860;
+L_0000000003f9b4c0 .cmp/eeq 1, o0000000003e9aa08, L_000000000418b8a8;
+L_0000000003f9b240 .cmp/eeq 1, o0000000003e9a978, L_000000000418b8f0;
+L_0000000003f9b2e0 .cmp/eeq 1, o0000000003e9a978, L_000000000418b938;
+L_0000000003f9bce0 .cmp/nee 1, o0000000003e9a858, o0000000003e9a918;
+L_0000000003f99c60 .cmp/eeq 1, o0000000003e9a9d8, L_000000000418b980;
+S_00000000028e99a0 .scope module, "sky130_fd_sc_hd__sdfstp_1" "sky130_fd_sc_hd__sdfstp_1" 4 46768;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9b1e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f34700_0 .net "CLK", 0 0, o0000000003e9b1e8;  0 drivers
+o0000000003e9b248 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f35420_0 .net "D", 0 0, o0000000003e9b248;  0 drivers
+v0000000003f34020_0 .net "Q", 0 0, L_0000000004209a70;  1 drivers
+o0000000003e9b2d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f343e0_0 .net "SCD", 0 0, o0000000003e9b2d8;  0 drivers
+o0000000003e9b338 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f34660_0 .net "SCE", 0 0, o0000000003e9b338;  0 drivers
+o0000000003e9b3c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f35600_0 .net "SET_B", 0 0, o0000000003e9b3c8;  0 drivers
+L_0000000004100b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f35ba0_0 .net8 "VGND", 0 0, L_0000000004100b40;  1 drivers, strength-aware
+L_0000000004100c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f340c0_0 .net8 "VNB", 0 0, L_0000000004100c20;  1 drivers, strength-aware
+L_00000000040ff720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f356a0_0 .net8 "VPB", 0 0, L_00000000040ff720;  1 drivers, strength-aware
+L_0000000004100050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f347a0_0 .net8 "VPWR", 0 0, L_0000000004100050;  1 drivers, strength-aware
+S_0000000003eea880 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 46790, 4 47127 1, S_00000000028e99a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9b3f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004209b50 .functor NOT 1, o0000000003e9b3f8, C4<0>, C4<0>, C4<0>;
+o0000000003e9b278 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9b308 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9b368 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004209300 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9b278, o0000000003e9b308, o0000000003e9b368;
+o0000000003e9b218 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041006e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004100c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004209370 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000004209300, o0000000003e9b218, L_0000000004209b50, v0000000003f33d00_0, L_00000000041006e0, L_0000000004100c90;
+L_0000000004208dc0 .functor AND 1, L_0000000003f9ae80, L_0000000003f9b920, C4<1>, C4<1>;
+L_0000000004208880 .functor AND 1, L_0000000003f9a020, L_0000000004208dc0, C4<1>, C4<1>;
+L_0000000004208f10 .functor AND 1, L_0000000003f9a7a0, L_0000000004208dc0, C4<1>, C4<1>;
+L_00000000042093e0 .functor AND 1, L_0000000003f9ac00, L_0000000004208dc0, C4<1>, C4<1>;
+L_0000000004208b90 .functor AND 1, L_0000000003f9b9c0, L_0000000003f9b920, C4<1>, C4<1>;
+L_0000000004209a70 .functor BUF 1, L_0000000004209370, C4<0>, C4<0>, C4<0>;
+v0000000003f34980_0 .net "CLK", 0 0, o0000000003e9b1e8;  alias, 0 drivers
+v0000000003f34d40_0 .net "CLK_delayed", 0 0, o0000000003e9b218;  0 drivers
+v0000000003f35d80_0 .net "D", 0 0, o0000000003e9b248;  alias, 0 drivers
+v0000000003f33e40_0 .net "D_delayed", 0 0, o0000000003e9b278;  0 drivers
+v0000000003f35e20_0 .net "Q", 0 0, L_0000000004209a70;  alias, 1 drivers
+v0000000003f35ec0_0 .net "SCD", 0 0, o0000000003e9b2d8;  alias, 0 drivers
+v0000000003f34200_0 .net "SCD_delayed", 0 0, o0000000003e9b308;  0 drivers
+v0000000003f33bc0_0 .net "SCE", 0 0, o0000000003e9b338;  alias, 0 drivers
+v0000000003f34ac0_0 .net "SCE_delayed", 0 0, o0000000003e9b368;  0 drivers
+v0000000003f35240_0 .net "SET", 0 0, L_0000000004209b50;  1 drivers
+v0000000003f35f60_0 .net "SET_B", 0 0, o0000000003e9b3c8;  alias, 0 drivers
+v0000000003f36000_0 .net "SET_B_delayed", 0 0, o0000000003e9b3f8;  0 drivers
+v0000000003f35880_0 .net8 "VGND", 0 0, L_0000000004100c90;  1 drivers, strength-aware
+L_00000000040ffdb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f35a60_0 .net8 "VNB", 0 0, L_00000000040ffdb0;  1 drivers, strength-aware
+L_00000000040ffe90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f342a0_0 .net8 "VPB", 0 0, L_00000000040ffe90;  1 drivers, strength-aware
+v0000000003f34480_0 .net8 "VPWR", 0 0, L_00000000041006e0;  1 drivers, strength-aware
+v0000000003f357e0_0 .net *"_s10", 0 0, L_0000000003f9ae80;  1 drivers
+L_000000000418ba58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f34e80_0 .net/2u *"_s14", 0 0, L_000000000418ba58;  1 drivers
+v0000000003f34f20_0 .net *"_s16", 0 0, L_0000000003f9a020;  1 drivers
+L_000000000418baa0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f360a0_0 .net/2u *"_s20", 0 0, L_000000000418baa0;  1 drivers
+v0000000003f34b60_0 .net *"_s22", 0 0, L_0000000003f9a7a0;  1 drivers
+v0000000003f33940_0 .net *"_s26", 0 0, L_0000000003f9ac00;  1 drivers
+L_000000000418bae8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f33ee0_0 .net/2u *"_s30", 0 0, L_000000000418bae8;  1 drivers
+v0000000003f339e0_0 .net *"_s32", 0 0, L_0000000003f9b9c0;  1 drivers
+L_000000000418b9c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f33f80_0 .net/2u *"_s4", 0 0, L_000000000418b9c8;  1 drivers
+L_000000000418ba10 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f34520_0 .net/2u *"_s8", 0 0, L_000000000418ba10;  1 drivers
+v0000000003f34340_0 .net "awake", 0 0, L_0000000003f9b920;  1 drivers
+v0000000003f35b00_0 .net "buf_Q", 0 0, L_0000000004209370;  1 drivers
+v0000000003f33c60_0 .net "cond0", 0 0, L_0000000004208dc0;  1 drivers
+v0000000003f354c0_0 .net "cond1", 0 0, L_0000000004208880;  1 drivers
+v0000000003f345c0_0 .net "cond2", 0 0, L_0000000004208f10;  1 drivers
+v0000000003f33a80_0 .net "cond3", 0 0, L_00000000042093e0;  1 drivers
+v0000000003f33b20_0 .net "cond4", 0 0, L_0000000004208b90;  1 drivers
+v0000000003f35380_0 .net "mux_out", 0 0, L_0000000004209300;  1 drivers
+v0000000003f33d00_0 .var "notifier", 0 0;
+L_0000000003f9b920 .cmp/eeq 1, L_00000000041006e0, L_000000000418b9c8;
+L_0000000003f9ae80 .cmp/eeq 1, o0000000003e9b3f8, L_000000000418ba10;
+L_0000000003f9a020 .cmp/eeq 1, o0000000003e9b368, L_000000000418ba58;
+L_0000000003f9a7a0 .cmp/eeq 1, o0000000003e9b368, L_000000000418baa0;
+L_0000000003f9ac00 .cmp/nee 1, o0000000003e9b278, o0000000003e9b308;
+L_0000000003f9b9c0 .cmp/eeq 1, o0000000003e9b3c8, L_000000000418bae8;
+S_00000000028eaba0 .scope module, "sky130_fd_sc_hd__sdfstp_2" "sky130_fd_sc_hd__sdfstp_2" 4 47401;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9bb78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f36640_0 .net "CLK", 0 0, o0000000003e9bb78;  0 drivers
+o0000000003e9bbd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f366e0_0 .net "D", 0 0, o0000000003e9bbd8;  0 drivers
+v0000000003f37180_0 .net "Q", 0 0, L_0000000004209f40;  1 drivers
+o0000000003e9bc68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f36be0_0 .net "SCD", 0 0, o0000000003e9bc68;  0 drivers
+o0000000003e9bcc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f36320_0 .net "SCE", 0 0, o0000000003e9bcc8;  0 drivers
+o0000000003e9bd58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f374a0_0 .net "SET_B", 0 0, o0000000003e9bd58;  0 drivers
+L_00000000041000c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f37d60_0 .net8 "VGND", 0 0, L_00000000041000c0;  1 drivers, strength-aware
+L_0000000004101010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f37360_0 .net8 "VNB", 0 0, L_0000000004101010;  1 drivers, strength-aware
+L_00000000040ff790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f37ea0_0 .net8 "VPB", 0 0, L_00000000040ff790;  1 drivers, strength-aware
+L_0000000004100e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f36280_0 .net8 "VPWR", 0 0, L_0000000004100e50;  1 drivers, strength-aware
+S_0000000003eec800 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 47423, 4 47127 1, S_00000000028eaba0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9bd88 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004209ca0 .functor NOT 1, o0000000003e9bd88, C4<0>, C4<0>, C4<0>;
+o0000000003e9bc08 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9bc98 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9bcf8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208f80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9bc08, o0000000003e9bc98, o0000000003e9bcf8;
+o0000000003e9bba8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ff800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040ff4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000042095a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000004208f80, o0000000003e9bba8, L_0000000004209ca0, v0000000003f37040_0, L_00000000040ff800, L_00000000040ff4f0;
+L_0000000004208810 .functor AND 1, L_0000000003f99da0, L_0000000003f99d00, C4<1>, C4<1>;
+L_0000000004209060 .functor AND 1, L_0000000003f9b6a0, L_0000000004208810, C4<1>, C4<1>;
+L_000000000420a090 .functor AND 1, L_0000000003f99940, L_0000000004208810, C4<1>, C4<1>;
+L_0000000004208e30 .functor AND 1, L_0000000003f99a80, L_0000000004208810, C4<1>, C4<1>;
+L_00000000042091b0 .functor AND 1, L_0000000003f99e40, L_0000000003f99d00, C4<1>, C4<1>;
+L_0000000004209f40 .functor BUF 1, L_00000000042095a0, C4<0>, C4<0>, C4<0>;
+v0000000003f35920_0 .net "CLK", 0 0, o0000000003e9bb78;  alias, 0 drivers
+v0000000003f34840_0 .net "CLK_delayed", 0 0, o0000000003e9bba8;  0 drivers
+v0000000003f34a20_0 .net "D", 0 0, o0000000003e9bbd8;  alias, 0 drivers
+v0000000003f348e0_0 .net "D_delayed", 0 0, o0000000003e9bc08;  0 drivers
+v0000000003f34c00_0 .net "Q", 0 0, L_0000000004209f40;  alias, 1 drivers
+v0000000003f34ca0_0 .net "SCD", 0 0, o0000000003e9bc68;  alias, 0 drivers
+v0000000003f34fc0_0 .net "SCD_delayed", 0 0, o0000000003e9bc98;  0 drivers
+v0000000003f35060_0 .net "SCE", 0 0, o0000000003e9bcc8;  alias, 0 drivers
+v0000000003f35c40_0 .net "SCE_delayed", 0 0, o0000000003e9bcf8;  0 drivers
+v0000000003f35100_0 .net "SET", 0 0, L_0000000004209ca0;  1 drivers
+v0000000003f352e0_0 .net "SET_B", 0 0, o0000000003e9bd58;  alias, 0 drivers
+v0000000003f36f00_0 .net "SET_B_delayed", 0 0, o0000000003e9bd88;  0 drivers
+v0000000003f361e0_0 .net8 "VGND", 0 0, L_00000000040ff4f0;  1 drivers, strength-aware
+L_0000000004100130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f38080_0 .net8 "VNB", 0 0, L_0000000004100130;  1 drivers, strength-aware
+L_0000000004100980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f37a40_0 .net8 "VPB", 0 0, L_0000000004100980;  1 drivers, strength-aware
+v0000000003f36500_0 .net8 "VPWR", 0 0, L_00000000040ff800;  1 drivers, strength-aware
+v0000000003f37720_0 .net *"_s10", 0 0, L_0000000003f99da0;  1 drivers
+L_000000000418bbc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f38620_0 .net/2u *"_s14", 0 0, L_000000000418bbc0;  1 drivers
+v0000000003f36140_0 .net *"_s16", 0 0, L_0000000003f9b6a0;  1 drivers
+L_000000000418bc08 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f37e00_0 .net/2u *"_s20", 0 0, L_000000000418bc08;  1 drivers
+v0000000003f36dc0_0 .net *"_s22", 0 0, L_0000000003f99940;  1 drivers
+v0000000003f36c80_0 .net *"_s26", 0 0, L_0000000003f99a80;  1 drivers
+L_000000000418bc50 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f36fa0_0 .net/2u *"_s30", 0 0, L_000000000418bc50;  1 drivers
+v0000000003f363c0_0 .net *"_s32", 0 0, L_0000000003f99e40;  1 drivers
+L_000000000418bb30 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f386c0_0 .net/2u *"_s4", 0 0, L_000000000418bb30;  1 drivers
+L_000000000418bb78 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f37cc0_0 .net/2u *"_s8", 0 0, L_000000000418bb78;  1 drivers
+v0000000003f372c0_0 .net "awake", 0 0, L_0000000003f99d00;  1 drivers
+v0000000003f37ae0_0 .net "buf_Q", 0 0, L_00000000042095a0;  1 drivers
+v0000000003f36e60_0 .net "cond0", 0 0, L_0000000004208810;  1 drivers
+v0000000003f381c0_0 .net "cond1", 0 0, L_0000000004209060;  1 drivers
+v0000000003f365a0_0 .net "cond2", 0 0, L_000000000420a090;  1 drivers
+v0000000003f379a0_0 .net "cond3", 0 0, L_0000000004208e30;  1 drivers
+v0000000003f37b80_0 .net "cond4", 0 0, L_00000000042091b0;  1 drivers
+v0000000003f37c20_0 .net "mux_out", 0 0, L_0000000004208f80;  1 drivers
+v0000000003f37040_0 .var "notifier", 0 0;
+L_0000000003f99d00 .cmp/eeq 1, L_00000000040ff800, L_000000000418bb30;
+L_0000000003f99da0 .cmp/eeq 1, o0000000003e9bd88, L_000000000418bb78;
+L_0000000003f9b6a0 .cmp/eeq 1, o0000000003e9bcf8, L_000000000418bbc0;
+L_0000000003f99940 .cmp/eeq 1, o0000000003e9bcf8, L_000000000418bc08;
+L_0000000003f99a80 .cmp/nee 1, o0000000003e9bc08, o0000000003e9bc98;
+L_0000000003f99e40 .cmp/eeq 1, o0000000003e9bd58, L_000000000418bc50;
+S_00000000028e93a0 .scope module, "sky130_fd_sc_hd__sdfstp_4" "sky130_fd_sc_hd__sdfstp_4" 4 47276;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9c508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f39f20_0 .net "CLK", 0 0, o0000000003e9c508;  0 drivers
+o0000000003e9c568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3a880_0 .net "D", 0 0, o0000000003e9c568;  0 drivers
+v0000000003f3a2e0_0 .net "Q", 0 0, L_0000000004209760;  1 drivers
+o0000000003e9c5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3ace0_0 .net "SCD", 0 0, o0000000003e9c5f8;  0 drivers
+o0000000003e9c658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f38ee0_0 .net "SCE", 0 0, o0000000003e9c658;  0 drivers
+o0000000003e9c6e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b000_0 .net "SET_B", 0 0, o0000000003e9c6e8;  0 drivers
+L_0000000004100d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f38e40_0 .net8 "VGND", 0 0, L_0000000004100d00;  1 drivers, strength-aware
+L_0000000004100910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f398e0_0 .net8 "VNB", 0 0, L_0000000004100910;  1 drivers, strength-aware
+L_0000000004100ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f395c0_0 .net8 "VPB", 0 0, L_0000000004100ec0;  1 drivers, strength-aware
+L_00000000040ff5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f38da0_0 .net8 "VPWR", 0 0, L_00000000040ff5d0;  1 drivers, strength-aware
+S_0000000003eeb480 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 47298, 4 47127 1, S_00000000028e93a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+    .port_info 5 /INPUT 1 "SET_B"
+o0000000003e9c718 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042094c0 .functor NOT 1, o0000000003e9c718, C4<0>, C4<0>, C4<0>;
+o0000000003e9c598 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9c628 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9c688 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000042096f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9c598, o0000000003e9c628, o0000000003e9c688;
+o0000000003e9c538 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ff9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004100670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000042097d0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_00000000042096f0, o0000000003e9c538, L_00000000042094c0, v0000000003f3b0a0_0, L_00000000040ff9c0, L_0000000004100670;
+L_0000000004209fb0 .functor AND 1, L_0000000003f9b7e0, L_0000000003f9a340, C4<1>, C4<1>;
+L_00000000042085e0 .functor AND 1, L_0000000003f9bc40, L_0000000004209fb0, C4<1>, C4<1>;
+L_0000000004208650 .functor AND 1, L_0000000003f99b20, L_0000000004209fb0, C4<1>, C4<1>;
+L_0000000004209df0 .functor AND 1, L_0000000003f9be20, L_0000000004209fb0, C4<1>, C4<1>;
+L_000000000420a020 .functor AND 1, L_0000000003f9bec0, L_0000000003f9a340, C4<1>, C4<1>;
+L_0000000004209760 .functor BUF 1, L_00000000042097d0, C4<0>, C4<0>, C4<0>;
+v0000000003f37680_0 .net "CLK", 0 0, o0000000003e9c508;  alias, 0 drivers
+v0000000003f36460_0 .net "CLK_delayed", 0 0, o0000000003e9c538;  0 drivers
+v0000000003f38760_0 .net "D", 0 0, o0000000003e9c568;  alias, 0 drivers
+v0000000003f36960_0 .net "D_delayed", 0 0, o0000000003e9c598;  0 drivers
+v0000000003f377c0_0 .net "Q", 0 0, L_0000000004209760;  alias, 1 drivers
+v0000000003f37860_0 .net "SCD", 0 0, o0000000003e9c5f8;  alias, 0 drivers
+v0000000003f36d20_0 .net "SCD_delayed", 0 0, o0000000003e9c628;  0 drivers
+v0000000003f36780_0 .net "SCE", 0 0, o0000000003e9c658;  alias, 0 drivers
+v0000000003f384e0_0 .net "SCE_delayed", 0 0, o0000000003e9c688;  0 drivers
+v0000000003f38580_0 .net "SET", 0 0, L_00000000042094c0;  1 drivers
+v0000000003f375e0_0 .net "SET_B", 0 0, o0000000003e9c6e8;  alias, 0 drivers
+v0000000003f37fe0_0 .net "SET_B_delayed", 0 0, o0000000003e9c718;  0 drivers
+v0000000003f370e0_0 .net8 "VGND", 0 0, L_0000000004100670;  1 drivers, strength-aware
+L_00000000040fff70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f37f40_0 .net8 "VNB", 0 0, L_00000000040fff70;  1 drivers, strength-aware
+L_00000000040ff560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f38120_0 .net8 "VPB", 0 0, L_00000000040ff560;  1 drivers, strength-aware
+v0000000003f383a0_0 .net8 "VPWR", 0 0, L_00000000040ff9c0;  1 drivers, strength-aware
+v0000000003f37220_0 .net *"_s10", 0 0, L_0000000003f9b7e0;  1 drivers
+L_000000000418bd28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f36820_0 .net/2u *"_s14", 0 0, L_000000000418bd28;  1 drivers
+v0000000003f36b40_0 .net *"_s16", 0 0, L_0000000003f9bc40;  1 drivers
+L_000000000418bd70 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f38260_0 .net/2u *"_s20", 0 0, L_000000000418bd70;  1 drivers
+v0000000003f37400_0 .net *"_s22", 0 0, L_0000000003f99b20;  1 drivers
+v0000000003f37540_0 .net *"_s26", 0 0, L_0000000003f9be20;  1 drivers
+L_000000000418bdb8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f38300_0 .net/2u *"_s30", 0 0, L_000000000418bdb8;  1 drivers
+v0000000003f38440_0 .net *"_s32", 0 0, L_0000000003f9bec0;  1 drivers
+L_000000000418bc98 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f368c0_0 .net/2u *"_s4", 0 0, L_000000000418bc98;  1 drivers
+L_000000000418bce0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f37900_0 .net/2u *"_s8", 0 0, L_000000000418bce0;  1 drivers
+v0000000003f38800_0 .net "awake", 0 0, L_0000000003f9a340;  1 drivers
+v0000000003f388a0_0 .net "buf_Q", 0 0, L_00000000042097d0;  1 drivers
+v0000000003f36a00_0 .net "cond0", 0 0, L_0000000004209fb0;  1 drivers
+v0000000003f36aa0_0 .net "cond1", 0 0, L_00000000042085e0;  1 drivers
+v0000000003f3a1a0_0 .net "cond2", 0 0, L_0000000004208650;  1 drivers
+v0000000003f3af60_0 .net "cond3", 0 0, L_0000000004209df0;  1 drivers
+v0000000003f3ae20_0 .net "cond4", 0 0, L_000000000420a020;  1 drivers
+v0000000003f3a4c0_0 .net "mux_out", 0 0, L_00000000042096f0;  1 drivers
+v0000000003f3b0a0_0 .var "notifier", 0 0;
+L_0000000003f9a340 .cmp/eeq 1, L_00000000040ff9c0, L_000000000418bc98;
+L_0000000003f9b7e0 .cmp/eeq 1, o0000000003e9c718, L_000000000418bce0;
+L_0000000003f9bc40 .cmp/eeq 1, o0000000003e9c688, L_000000000418bd28;
+L_0000000003f99b20 .cmp/eeq 1, o0000000003e9c688, L_000000000418bd70;
+L_0000000003f9be20 .cmp/nee 1, o0000000003e9c598, o0000000003e9c628;
+L_0000000003f9bec0 .cmp/eeq 1, o0000000003e9c6e8, L_000000000418bdb8;
+S_00000000028ea2a0 .scope module, "sky130_fd_sc_hd__sdfxbp_1" "sky130_fd_sc_hd__sdfxbp_1" 4 65736;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003e9ce98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f38940_0 .net "CLK", 0 0, o0000000003e9ce98;  0 drivers
+o0000000003e9cef8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3a240_0 .net "D", 0 0, o0000000003e9cef8;  0 drivers
+v0000000003f3a920_0 .net "Q", 0 0, L_00000000042086c0;  1 drivers
+v0000000003f3aa60_0 .net "Q_N", 0 0, L_00000000042087a0;  1 drivers
+o0000000003e9cfb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3ab00_0 .net "SCD", 0 0, o0000000003e9cfb8;  0 drivers
+o0000000003e9d018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f39980_0 .net "SCE", 0 0, o0000000003e9d018;  0 drivers
+L_0000000004100f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f389e0_0 .net8 "VGND", 0 0, L_0000000004100f30;  1 drivers, strength-aware
+L_0000000004100fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f38a80_0 .net8 "VNB", 0 0, L_0000000004100fa0;  1 drivers, strength-aware
+L_0000000004100440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f39b60_0 .net8 "VPB", 0 0, L_0000000004100440;  1 drivers, strength-aware
+L_0000000004101080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3aba0_0 .net8 "VPWR", 0 0, L_0000000004101080;  1 drivers, strength-aware
+S_0000000003eeed80 .scope module, "base" "sky130_fd_sc_hd__sdfxbp" 4 65758, 4 66082 1, S_00000000028ea2a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003e9cf28 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9cfe8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9d048 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208730 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9cf28, o0000000003e9cfe8, o0000000003e9d048;
+o0000000003e9cec8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004100830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004100360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000004208ff0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000004208730, o0000000003e9cec8, v0000000003f39660_0, L_0000000004100830, L_0000000004100360;
+L_0000000004209290 .functor AND 1, L_0000000003f9ade0, L_0000000003f99ee0, C4<1>, C4<1>;
+L_0000000004209840 .functor AND 1, L_0000000003f99f80, L_0000000003f99ee0, C4<1>, C4<1>;
+L_0000000004209d10 .functor AND 1, L_0000000003f9bb00, L_0000000003f99ee0, C4<1>, C4<1>;
+L_00000000042086c0 .functor BUF 1, L_0000000004208ff0, C4<0>, C4<0>, C4<0>;
+L_00000000042087a0 .functor NOT 1, L_0000000004208ff0, C4<0>, C4<0>, C4<0>;
+v0000000003f3a380_0 .net "CLK", 0 0, o0000000003e9ce98;  alias, 0 drivers
+v0000000003f39c00_0 .net "CLK_delayed", 0 0, o0000000003e9cec8;  0 drivers
+v0000000003f3aec0_0 .net "D", 0 0, o0000000003e9cef8;  alias, 0 drivers
+v0000000003f3ad80_0 .net "D_delayed", 0 0, o0000000003e9cf28;  0 drivers
+v0000000003f39700_0 .net "Q", 0 0, L_00000000042086c0;  alias, 1 drivers
+v0000000003f3a420_0 .net "Q_N", 0 0, L_00000000042087a0;  alias, 1 drivers
+v0000000003f3a560_0 .net "SCD", 0 0, o0000000003e9cfb8;  alias, 0 drivers
+v0000000003f3a600_0 .net "SCD_delayed", 0 0, o0000000003e9cfe8;  0 drivers
+v0000000003f39200_0 .net "SCE", 0 0, o0000000003e9d018;  alias, 0 drivers
+v0000000003f392a0_0 .net "SCE_delayed", 0 0, o0000000003e9d048;  0 drivers
+v0000000003f3a6a0_0 .net8 "VGND", 0 0, L_0000000004100360;  1 drivers, strength-aware
+L_00000000040fff00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3a9c0_0 .net8 "VNB", 0 0, L_00000000040fff00;  1 drivers, strength-aware
+L_00000000040ff640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f39020_0 .net8 "VPB", 0 0, L_00000000040ff640;  1 drivers, strength-aware
+v0000000003f3a740_0 .net8 "VPWR", 0 0, L_0000000004100830;  1 drivers, strength-aware
+v0000000003f39ca0_0 .net *"_s10", 0 0, L_0000000003f9ade0;  1 drivers
+L_000000000418be90 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f39840_0 .net/2u *"_s14", 0 0, L_000000000418be90;  1 drivers
+v0000000003f39d40_0 .net *"_s16", 0 0, L_0000000003f99f80;  1 drivers
+v0000000003f39a20_0 .net *"_s20", 0 0, L_0000000003f9bb00;  1 drivers
+L_000000000418be00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f39ac0_0 .net/2u *"_s4", 0 0, L_000000000418be00;  1 drivers
+L_000000000418be48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f3a7e0_0 .net/2u *"_s8", 0 0, L_000000000418be48;  1 drivers
+v0000000003f39480_0 .net "awake", 0 0, L_0000000003f99ee0;  1 drivers
+v0000000003f39340_0 .net "buf_Q", 0 0, L_0000000004208ff0;  1 drivers
+v0000000003f38d00_0 .net "cond1", 0 0, L_0000000004209290;  1 drivers
+v0000000003f390c0_0 .net "cond2", 0 0, L_0000000004209840;  1 drivers
+v0000000003f397a0_0 .net "cond3", 0 0, L_0000000004209d10;  1 drivers
+v0000000003f38b20_0 .net "mux_out", 0 0, L_0000000004208730;  1 drivers
+v0000000003f39660_0 .var "notifier", 0 0;
+L_0000000003f99ee0 .cmp/eeq 1, L_0000000004100830, L_000000000418be00;
+L_0000000003f9ade0 .cmp/eeq 1, o0000000003e9d048, L_000000000418be48;
+L_0000000003f99f80 .cmp/eeq 1, o0000000003e9d048, L_000000000418be90;
+L_0000000003f9bb00 .cmp/nee 1, o0000000003e9cf28, o0000000003e9cfe8;
+S_00000000028e9520 .scope module, "sky130_fd_sc_hd__sdfxbp_2" "sky130_fd_sc_hd__sdfxbp_2" 4 66224;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003e9d6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b500_0 .net "CLK", 0 0, o0000000003e9d6a8;  0 drivers
+o0000000003e9d708 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b5a0_0 .net "D", 0 0, o0000000003e9d708;  0 drivers
+v0000000003f3c180_0 .net "Q", 0 0, L_0000000004208b20;  1 drivers
+v0000000003f3bbe0_0 .net "Q_N", 0 0, L_0000000004208c00;  1 drivers
+o0000000003e9d7c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b320_0 .net "SCD", 0 0, o0000000003e9d7c8;  0 drivers
+o0000000003e9d828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b6e0_0 .net "SCE", 0 0, o0000000003e9d828;  0 drivers
+L_00000000041001a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3d4e0_0 .net8 "VGND", 0 0, L_00000000041001a0;  1 drivers, strength-aware
+L_00000000040ff870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c5e0_0 .net8 "VNB", 0 0, L_00000000040ff870;  1 drivers, strength-aware
+L_00000000040ff8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3cfe0_0 .net8 "VPB", 0 0, L_00000000040ff8e0;  1 drivers, strength-aware
+L_00000000040ff950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3b3c0_0 .net8 "VPWR", 0 0, L_00000000040ff950;  1 drivers, strength-aware
+S_0000000003ee9200 .scope module, "base" "sky130_fd_sc_hd__sdfxbp" 4 66246, 4 66082 1, S_00000000028e9520;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003e9d738 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9d7f8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9d858 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208960 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9d738, o0000000003e9d7f8, o0000000003e9d858;
+o0000000003e9d6d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000040ffbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000040ffa30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000042088f0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000004208960, o0000000003e9d6d8, v0000000003f3bfa0_0, L_00000000040ffbf0, L_00000000040ffa30;
+L_0000000004208ab0 .functor AND 1, L_0000000003f9a160, L_0000000003f9afc0, C4<1>, C4<1>;
+L_00000000042090d0 .functor AND 1, L_0000000003f9a480, L_0000000003f9afc0, C4<1>, C4<1>;
+L_0000000004209530 .functor AND 1, L_0000000003f9bd80, L_0000000003f9afc0, C4<1>, C4<1>;
+L_0000000004208b20 .functor BUF 1, L_00000000042088f0, C4<0>, C4<0>, C4<0>;
+L_0000000004208c00 .functor NOT 1, L_00000000042088f0, C4<0>, C4<0>, C4<0>;
+v0000000003f39de0_0 .net "CLK", 0 0, o0000000003e9d6a8;  alias, 0 drivers
+v0000000003f3ac40_0 .net "CLK_delayed", 0 0, o0000000003e9d6d8;  0 drivers
+v0000000003f38bc0_0 .net "D", 0 0, o0000000003e9d708;  alias, 0 drivers
+v0000000003f38c60_0 .net "D_delayed", 0 0, o0000000003e9d738;  0 drivers
+v0000000003f39e80_0 .net "Q", 0 0, L_0000000004208b20;  alias, 1 drivers
+v0000000003f38f80_0 .net "Q_N", 0 0, L_0000000004208c00;  alias, 1 drivers
+v0000000003f39160_0 .net "SCD", 0 0, o0000000003e9d7c8;  alias, 0 drivers
+v0000000003f39fc0_0 .net "SCD_delayed", 0 0, o0000000003e9d7f8;  0 drivers
+v0000000003f393e0_0 .net "SCE", 0 0, o0000000003e9d828;  alias, 0 drivers
+v0000000003f3a060_0 .net "SCE_delayed", 0 0, o0000000003e9d858;  0 drivers
+v0000000003f39520_0 .net8 "VGND", 0 0, L_00000000040ffa30;  1 drivers, strength-aware
+L_00000000040ffaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3a100_0 .net8 "VNB", 0 0, L_00000000040ffaa0;  1 drivers, strength-aware
+L_00000000040ffb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3bdc0_0 .net8 "VPB", 0 0, L_00000000040ffb10;  1 drivers, strength-aware
+v0000000003f3bc80_0 .net8 "VPWR", 0 0, L_00000000040ffbf0;  1 drivers, strength-aware
+v0000000003f3bf00_0 .net *"_s10", 0 0, L_0000000003f9a160;  1 drivers
+L_000000000418bf68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3d8a0_0 .net/2u *"_s14", 0 0, L_000000000418bf68;  1 drivers
+v0000000003f3d6c0_0 .net *"_s16", 0 0, L_0000000003f9a480;  1 drivers
+v0000000003f3ccc0_0 .net *"_s20", 0 0, L_0000000003f9bd80;  1 drivers
+L_000000000418bed8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3ce00_0 .net/2u *"_s4", 0 0, L_000000000418bed8;  1 drivers
+L_000000000418bf20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f3cae0_0 .net/2u *"_s8", 0 0, L_000000000418bf20;  1 drivers
+v0000000003f3b140_0 .net "awake", 0 0, L_0000000003f9afc0;  1 drivers
+v0000000003f3d120_0 .net "buf_Q", 0 0, L_00000000042088f0;  1 drivers
+v0000000003f3cc20_0 .net "cond1", 0 0, L_0000000004208ab0;  1 drivers
+v0000000003f3bd20_0 .net "cond2", 0 0, L_00000000042090d0;  1 drivers
+v0000000003f3be60_0 .net "cond3", 0 0, L_0000000004209530;  1 drivers
+v0000000003f3cb80_0 .net "mux_out", 0 0, L_0000000004208960;  1 drivers
+v0000000003f3bfa0_0 .var "notifier", 0 0;
+L_0000000003f9afc0 .cmp/eeq 1, L_00000000040ffbf0, L_000000000418bed8;
+L_0000000003f9a160 .cmp/eeq 1, o0000000003e9d858, L_000000000418bf20;
+L_0000000003f9a480 .cmp/eeq 1, o0000000003e9d858, L_000000000418bf68;
+L_0000000003f9bd80 .cmp/nee 1, o0000000003e9d738, o0000000003e9d7f8;
+S_00000000028eaa20 .scope module, "sky130_fd_sc_hd__sdfxtp_1" "sky130_fd_sc_hd__sdfxtp_1" 4 20753;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9deb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3baa0_0 .net "CLK", 0 0, o0000000003e9deb8;  0 drivers
+o0000000003e9df18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3c7c0_0 .net "D", 0 0, o0000000003e9df18;  0 drivers
+v0000000003f3d300_0 .net "Q", 0 0, L_000000000420ad40;  1 drivers
+o0000000003e9dfa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3b8c0_0 .net "SCD", 0 0, o0000000003e9dfa8;  0 drivers
+o0000000003e9e008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3c360_0 .net "SCE", 0 0, o0000000003e9e008;  0 drivers
+L_00000000040ffb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3d3a0_0 .net8 "VGND", 0 0, L_00000000040ffb80;  1 drivers, strength-aware
+L_00000000040ffc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c860_0 .net8 "VNB", 0 0, L_00000000040ffc60;  1 drivers, strength-aware
+L_00000000040fffe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c4a0_0 .net8 "VPB", 0 0, L_00000000040fffe0;  1 drivers, strength-aware
+L_0000000004100210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c900_0 .net8 "VPWR", 0 0, L_0000000004100210;  1 drivers, strength-aware
+S_0000000003eedd00 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20773, 4 20381 1, S_00000000028eaa20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9df48 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9dfd8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9e038 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004208c70 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9df48, o0000000003e9dfd8, o0000000003e9e038;
+o0000000003e9dee8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041003d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000041004b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420a800 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000004208c70, o0000000003e9dee8, v0000000003f3b820_0, L_00000000041003d0, L_00000000041004b0;
+L_000000000420a410 .functor AND 1, L_0000000003f9a200, L_0000000003f9a0c0, C4<1>, C4<1>;
+L_000000000420b050 .functor AND 1, L_0000000003f9b740, L_0000000003f9a0c0, C4<1>, C4<1>;
+L_000000000420aa30 .functor AND 1, L_0000000003f9a2a0, L_0000000003f9a0c0, C4<1>, C4<1>;
+L_000000000420ad40 .functor BUF 1, L_000000000420a800, C4<0>, C4<0>, C4<0>;
+v0000000003f3cd60_0 .net "CLK", 0 0, o0000000003e9deb8;  alias, 0 drivers
+v0000000003f3c220_0 .net "CLK_delayed", 0 0, o0000000003e9dee8;  0 drivers
+v0000000003f3c400_0 .net "D", 0 0, o0000000003e9df18;  alias, 0 drivers
+v0000000003f3b1e0_0 .net "D_delayed", 0 0, o0000000003e9df48;  0 drivers
+v0000000003f3cea0_0 .net "Q", 0 0, L_000000000420ad40;  alias, 1 drivers
+v0000000003f3c680_0 .net "SCD", 0 0, o0000000003e9dfa8;  alias, 0 drivers
+v0000000003f3c040_0 .net "SCD_delayed", 0 0, o0000000003e9dfd8;  0 drivers
+v0000000003f3d620_0 .net "SCE", 0 0, o0000000003e9e008;  alias, 0 drivers
+v0000000003f3ba00_0 .net "SCE_delayed", 0 0, o0000000003e9e038;  0 drivers
+v0000000003f3c0e0_0 .net8 "VGND", 0 0, L_00000000041004b0;  1 drivers, strength-aware
+L_0000000004100280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c2c0_0 .net8 "VNB", 0 0, L_0000000004100280;  1 drivers, strength-aware
+L_00000000041009f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c9a0_0 .net8 "VPB", 0 0, L_00000000041009f0;  1 drivers, strength-aware
+v0000000003f3d760_0 .net8 "VPWR", 0 0, L_00000000041003d0;  1 drivers, strength-aware
+v0000000003f3d800_0 .net *"_s10", 0 0, L_0000000003f9a200;  1 drivers
+L_000000000418c040 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3d080_0 .net/2u *"_s14", 0 0, L_000000000418c040;  1 drivers
+v0000000003f3b280_0 .net *"_s16", 0 0, L_0000000003f9b740;  1 drivers
+v0000000003f3b460_0 .net *"_s20", 0 0, L_0000000003f9a2a0;  1 drivers
+L_000000000418bfb0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3d1c0_0 .net/2u *"_s4", 0 0, L_000000000418bfb0;  1 drivers
+L_000000000418bff8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f3c540_0 .net/2u *"_s8", 0 0, L_000000000418bff8;  1 drivers
+v0000000003f3c720_0 .net "awake", 0 0, L_0000000003f9a0c0;  1 drivers
+v0000000003f3b640_0 .net "buf_Q", 0 0, L_000000000420a800;  1 drivers
+v0000000003f3cf40_0 .net "cond1", 0 0, L_000000000420a410;  1 drivers
+v0000000003f3d260_0 .net "cond2", 0 0, L_000000000420b050;  1 drivers
+v0000000003f3d580_0 .net "cond3", 0 0, L_000000000420aa30;  1 drivers
+v0000000003f3b780_0 .net "mux_out", 0 0, L_0000000004208c70;  1 drivers
+v0000000003f3b820_0 .var "notifier", 0 0;
+L_0000000003f9a0c0 .cmp/eeq 1, L_00000000041003d0, L_000000000418bfb0;
+L_0000000003f9a200 .cmp/eeq 1, o0000000003e9e038, L_000000000418bff8;
+L_0000000003f9b740 .cmp/eeq 1, o0000000003e9e038, L_000000000418c040;
+L_0000000003f9a2a0 .cmp/nee 1, o0000000003e9df48, o0000000003e9dfd8;
+S_00000000028e96a0 .scope module, "sky130_fd_sc_hd__sdfxtp_2" "sky130_fd_sc_hd__sdfxtp_2" 4 20517;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9e638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3e8e0_0 .net "CLK", 0 0, o0000000003e9e638;  0 drivers
+o0000000003e9e698 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f40000_0 .net "D", 0 0, o0000000003e9e698;  0 drivers
+v0000000003f3fd80_0 .net "Q", 0 0, L_000000000420a170;  1 drivers
+o0000000003e9e728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3efc0_0 .net "SCD", 0 0, o0000000003e9e728;  0 drivers
+o0000000003e9e788 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3ec00_0 .net "SCE", 0 0, o0000000003e9e788;  0 drivers
+L_0000000004100520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3fec0_0 .net8 "VGND", 0 0, L_0000000004100520;  1 drivers, strength-aware
+L_0000000004100590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f9c0_0 .net8 "VNB", 0 0, L_0000000004100590;  1 drivers, strength-aware
+L_00000000041008a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3e160_0 .net8 "VPB", 0 0, L_00000000041008a0;  1 drivers, strength-aware
+L_0000000004102430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f2e0_0 .net8 "VPWR", 0 0, L_0000000004102430;  1 drivers, strength-aware
+S_0000000003eeda00 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20537, 4 20381 1, S_00000000028e96a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9e6c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9e758 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9e7b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420adb0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9e6c8, o0000000003e9e758, o0000000003e9e7b8;
+o0000000003e9e668 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041018d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000041016a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420bc90 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420adb0, o0000000003e9e668, v0000000003f3ede0_0, L_00000000041018d0, L_00000000041016a0;
+L_000000000420a950 .functor AND 1, L_0000000003f9a700, L_0000000003f9a3e0, C4<1>, C4<1>;
+L_000000000420b980 .functor AND 1, L_0000000003f9a840, L_0000000003f9a3e0, C4<1>, C4<1>;
+L_000000000420a100 .functor AND 1, L_0000000003f9b880, L_0000000003f9a3e0, C4<1>, C4<1>;
+L_000000000420a170 .functor BUF 1, L_000000000420bc90, C4<0>, C4<0>, C4<0>;
+v0000000003f3ca40_0 .net "CLK", 0 0, o0000000003e9e638;  alias, 0 drivers
+v0000000003f3bb40_0 .net "CLK_delayed", 0 0, o0000000003e9e668;  0 drivers
+v0000000003f3d440_0 .net "D", 0 0, o0000000003e9e698;  alias, 0 drivers
+v0000000003f3b960_0 .net "D_delayed", 0 0, o0000000003e9e6c8;  0 drivers
+v0000000003f3f7e0_0 .net "Q", 0 0, L_000000000420a170;  alias, 1 drivers
+v0000000003f3eca0_0 .net "SCD", 0 0, o0000000003e9e728;  alias, 0 drivers
+v0000000003f3e840_0 .net "SCD_delayed", 0 0, o0000000003e9e758;  0 drivers
+v0000000003f3f240_0 .net "SCE", 0 0, o0000000003e9e788;  alias, 0 drivers
+v0000000003f3f920_0 .net "SCE_delayed", 0 0, o0000000003e9e7b8;  0 drivers
+v0000000003f3ef20_0 .net8 "VGND", 0 0, L_00000000041016a0;  1 drivers, strength-aware
+L_0000000004101f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f380_0 .net8 "VNB", 0 0, L_0000000004101f60;  1 drivers, strength-aware
+L_0000000004101e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f420_0 .net8 "VPB", 0 0, L_0000000004101e10;  1 drivers, strength-aware
+v0000000003f3f4c0_0 .net8 "VPWR", 0 0, L_00000000041018d0;  1 drivers, strength-aware
+v0000000003f3e020_0 .net *"_s10", 0 0, L_0000000003f9a700;  1 drivers
+L_000000000418c118 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f740_0 .net/2u *"_s14", 0 0, L_000000000418c118;  1 drivers
+v0000000003f3e0c0_0 .net *"_s16", 0 0, L_0000000003f9a840;  1 drivers
+v0000000003f3e7a0_0 .net *"_s20", 0 0, L_0000000003f9b880;  1 drivers
+L_000000000418c088 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3f6a0_0 .net/2u *"_s4", 0 0, L_000000000418c088;  1 drivers
+L_000000000418c0d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f3ed40_0 .net/2u *"_s8", 0 0, L_000000000418c0d0;  1 drivers
+v0000000003f3fce0_0 .net "awake", 0 0, L_0000000003f9a3e0;  1 drivers
+v0000000003f3dee0_0 .net "buf_Q", 0 0, L_000000000420bc90;  1 drivers
+v0000000003f3df80_0 .net "cond1", 0 0, L_000000000420a950;  1 drivers
+v0000000003f3dc60_0 .net "cond2", 0 0, L_000000000420b980;  1 drivers
+v0000000003f3f560_0 .net "cond3", 0 0, L_000000000420a100;  1 drivers
+v0000000003f3e480_0 .net "mux_out", 0 0, L_000000000420adb0;  1 drivers
+v0000000003f3ede0_0 .var "notifier", 0 0;
+L_0000000003f9a3e0 .cmp/eeq 1, L_00000000041018d0, L_000000000418c088;
+L_0000000003f9a700 .cmp/eeq 1, o0000000003e9e7b8, L_000000000418c0d0;
+L_0000000003f9a840 .cmp/eeq 1, o0000000003e9e7b8, L_000000000418c118;
+L_0000000003f9b880 .cmp/nee 1, o0000000003e9e6c8, o0000000003e9e758;
+S_00000000028eb020 .scope module, "sky130_fd_sc_hd__sdfxtp_4" "sky130_fd_sc_hd__sdfxtp_4" 4 20635;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9edb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3fe20_0 .net "CLK", 0 0, o0000000003e9edb8;  0 drivers
+o0000000003e9ee18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3e5c0_0 .net "D", 0 0, o0000000003e9ee18;  0 drivers
+v0000000003f3ff60_0 .net "Q", 0 0, L_000000000420b440;  1 drivers
+o0000000003e9eea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3d940_0 .net "SCD", 0 0, o0000000003e9eea8;  0 drivers
+o0000000003e9ef08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f3eb60_0 .net "SCE", 0 0, o0000000003e9ef08;  0 drivers
+L_0000000004101a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3da80_0 .net8 "VGND", 0 0, L_0000000004101a90;  1 drivers, strength-aware
+L_00000000041027b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3e3e0_0 .net8 "VNB", 0 0, L_00000000041027b0;  1 drivers, strength-aware
+L_0000000004102b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f412c0_0 .net8 "VPB", 0 0, L_0000000004102b30;  1 drivers, strength-aware
+L_0000000004101320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f41ae0_0 .net8 "VPWR", 0 0, L_0000000004101320;  1 drivers, strength-aware
+S_0000000003ee9380 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20655, 4 20381 1, S_00000000028eb020;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "SCD"
+    .port_info 4 /INPUT 1 "SCE"
+o0000000003e9ee48 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9eed8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9ef38 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b210 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003e9ee48, o0000000003e9eed8, o0000000003e9ef38;
+o0000000003e9ede8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004102740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004102820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420a9c0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420b210, o0000000003e9ede8, v0000000003f3f100_0, L_0000000004102740, L_0000000004102820;
+L_000000000420af00 .functor AND 1, L_0000000003f9a8e0, L_0000000003f9aac0, C4<1>, C4<1>;
+L_000000000420ba60 .functor AND 1, L_0000000003f9b100, L_0000000003f9aac0, C4<1>, C4<1>;
+L_000000000420a720 .functor AND 1, L_0000000003f9b1a0, L_0000000003f9aac0, C4<1>, C4<1>;
+L_000000000420b440 .functor BUF 1, L_000000000420a9c0, C4<0>, C4<0>, C4<0>;
+v0000000003f3dbc0_0 .net "CLK", 0 0, o0000000003e9edb8;  alias, 0 drivers
+v0000000003f3e200_0 .net "CLK_delayed", 0 0, o0000000003e9ede8;  0 drivers
+v0000000003f3de40_0 .net "D", 0 0, o0000000003e9ee18;  alias, 0 drivers
+v0000000003f3e980_0 .net "D_delayed", 0 0, o0000000003e9ee48;  0 drivers
+v0000000003f3f600_0 .net "Q", 0 0, L_000000000420b440;  alias, 1 drivers
+v0000000003f3ee80_0 .net "SCD", 0 0, o0000000003e9eea8;  alias, 0 drivers
+v0000000003f3f060_0 .net "SCD_delayed", 0 0, o0000000003e9eed8;  0 drivers
+v0000000003f3f880_0 .net "SCE", 0 0, o0000000003e9ef08;  alias, 0 drivers
+v0000000003f3fa60_0 .net "SCE_delayed", 0 0, o0000000003e9ef38;  0 drivers
+v0000000003f3e520_0 .net8 "VGND", 0 0, L_0000000004102820;  1 drivers, strength-aware
+L_0000000004102350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f3e2a0_0 .net8 "VNB", 0 0, L_0000000004102350;  1 drivers, strength-aware
+L_0000000004101b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f3dd00_0 .net8 "VPB", 0 0, L_0000000004101b70;  1 drivers, strength-aware
+v0000000003f3e340_0 .net8 "VPWR", 0 0, L_0000000004102740;  1 drivers, strength-aware
+v0000000003f3ea20_0 .net *"_s10", 0 0, L_0000000003f9a8e0;  1 drivers
+L_000000000418c1f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3db20_0 .net/2u *"_s14", 0 0, L_000000000418c1f0;  1 drivers
+v0000000003f3eac0_0 .net *"_s16", 0 0, L_0000000003f9b100;  1 drivers
+v0000000003f400a0_0 .net *"_s20", 0 0, L_0000000003f9b1a0;  1 drivers
+L_000000000418c160 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f3e660_0 .net/2u *"_s4", 0 0, L_000000000418c160;  1 drivers
+L_000000000418c1a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f3fb00_0 .net/2u *"_s8", 0 0, L_000000000418c1a8;  1 drivers
+v0000000003f3f1a0_0 .net "awake", 0 0, L_0000000003f9aac0;  1 drivers
+v0000000003f3e700_0 .net "buf_Q", 0 0, L_000000000420a9c0;  1 drivers
+v0000000003f3d9e0_0 .net "cond1", 0 0, L_000000000420af00;  1 drivers
+v0000000003f3fba0_0 .net "cond2", 0 0, L_000000000420ba60;  1 drivers
+v0000000003f3fc40_0 .net "cond3", 0 0, L_000000000420a720;  1 drivers
+v0000000003f3dda0_0 .net "mux_out", 0 0, L_000000000420b210;  1 drivers
+v0000000003f3f100_0 .var "notifier", 0 0;
+L_0000000003f9aac0 .cmp/eeq 1, L_0000000004102740, L_000000000418c160;
+L_0000000003f9a8e0 .cmp/eeq 1, o0000000003e9ef38, L_000000000418c1a8;
+L_0000000003f9b100 .cmp/eeq 1, o0000000003e9ef38, L_000000000418c1f0;
+L_0000000003f9b1a0 .cmp/nee 1, o0000000003e9ee48, o0000000003e9eed8;
+S_00000000028e9b20 .scope module, "sky130_fd_sc_hd__sdlclkp_1" "sky130_fd_sc_hd__sdlclkp_1" 4 14230;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+o0000000003e9f538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f42620_0 .net "CLK", 0 0, o0000000003e9f538;  0 drivers
+o0000000003e9f598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f42760_0 .net "GATE", 0 0, o0000000003e9f598;  0 drivers
+v0000000003f414a0_0 .net "GCLK", 0 0, L_000000000420a560;  1 drivers
+o0000000003e9f658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f41360_0 .net "SCE", 0 0, o0000000003e9f658;  0 drivers
+L_0000000004101be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f40780_0 .net8 "VGND", 0 0, L_0000000004101be0;  1 drivers, strength-aware
+L_0000000004102200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f42800_0 .net8 "VNB", 0 0, L_0000000004102200;  1 drivers, strength-aware
+L_0000000004101710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f428a0_0 .net8 "VPB", 0 0, L_0000000004101710;  1 drivers, strength-aware
+L_0000000004101630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f42080_0 .net8 "VPWR", 0 0, L_0000000004101630;  1 drivers, strength-aware
+S_0000000003eead00 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14248, 4 14676 1, S_00000000028e9b20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+L_000000000420b4b0 .functor NOT 1, L_000000000420b280, C4<0>, C4<0>, C4<0>;
+o0000000003e9f568 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b830 .functor NOT 1, o0000000003e9f568, C4<0>, C4<0>, C4<0>;
+o0000000003e9f5f8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9f6b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b520 .functor NOR 1, o0000000003e9f5f8, o0000000003e9f6b8, C4<0>, C4<0>;
+L_00000000041015c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004101940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420b280 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_000000000420b520, L_000000000420b830, v0000000003f42300_0, L_00000000041015c0, L_0000000004101940;
+L_000000000420a560 .functor AND 1, L_000000000420b4b0, o0000000003e9f568, C4<1>, C4<1>;
+L_000000000420b0c0 .functor AND 1, L_0000000003f9a980, L_0000000003f9aa20, C4<1>, C4<1>;
+L_000000000420bad0 .functor AND 1, L_0000000003f9a980, L_0000000003f9ab60, C4<1>, C4<1>;
+v0000000003f41040_0 .net "CLK", 0 0, o0000000003e9f538;  alias, 0 drivers
+v0000000003f41680_0 .net "CLK_delayed", 0 0, o0000000003e9f568;  0 drivers
+v0000000003f40460_0 .net "GATE", 0 0, o0000000003e9f598;  alias, 0 drivers
+v0000000003f426c0_0 .net "GATE_awake", 0 0, L_000000000420bad0;  1 drivers
+v0000000003f40d20_0 .net "GATE_delayed", 0 0, o0000000003e9f5f8;  0 drivers
+v0000000003f41720_0 .net "GCLK", 0 0, L_000000000420a560;  alias, 1 drivers
+v0000000003f41180_0 .net "SCE", 0 0, o0000000003e9f658;  alias, 0 drivers
+v0000000003f42580_0 .net "SCE_awake", 0 0, L_000000000420b0c0;  1 drivers
+v0000000003f40140_0 .net "SCE_delayed", 0 0, o0000000003e9f6b8;  0 drivers
+v0000000003f424e0_0 .net "SCE_gate_delayed", 0 0, L_000000000420b520;  1 drivers
+v0000000003f40960_0 .net8 "VGND", 0 0, L_0000000004101940;  1 drivers, strength-aware
+L_0000000004101400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f419a0_0 .net8 "VNB", 0 0, L_0000000004101400;  1 drivers, strength-aware
+L_0000000004102510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f415e0_0 .net8 "VPB", 0 0, L_0000000004102510;  1 drivers, strength-aware
+v0000000003f421c0_0 .net8 "VPWR", 0 0, L_00000000041015c0;  1 drivers, strength-aware
+v0000000003f403c0_0 .net *"_s10", 0 0, L_0000000003f9aa20;  1 drivers
+L_000000000418c2c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f40dc0_0 .net/2u *"_s14", 0 0, L_000000000418c2c8;  1 drivers
+v0000000003f423a0_0 .net *"_s16", 0 0, L_0000000003f9ab60;  1 drivers
+L_000000000418c238 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f40a00_0 .net/2u *"_s4", 0 0, L_000000000418c238;  1 drivers
+L_000000000418c280 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f40e60_0 .net/2u *"_s8", 0 0, L_000000000418c280;  1 drivers
+v0000000003f41cc0_0 .net "awake", 0 0, L_0000000003f9a980;  1 drivers
+v0000000003f42260_0 .net "clkn", 0 0, L_000000000420b830;  1 drivers
+v0000000003f41220_0 .net "m0", 0 0, L_000000000420b280;  1 drivers
+v0000000003f41400_0 .net "m0n", 0 0, L_000000000420b4b0;  1 drivers
+v0000000003f42300_0 .var "notifier", 0 0;
+L_0000000003f9a980 .cmp/eeq 1, L_00000000041015c0, L_000000000418c238;
+L_0000000003f9aa20 .cmp/eeq 1, o0000000003e9f5f8, L_000000000418c280;
+L_0000000003f9ab60 .cmp/eeq 1, o0000000003e9f6b8, L_000000000418c2c8;
+S_00000000028e9e20 .scope module, "sky130_fd_sc_hd__sdlclkp_2" "sky130_fd_sc_hd__sdlclkp_2" 4 14808;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+o0000000003e9fbf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f41fe0_0 .net "CLK", 0 0, o0000000003e9fbf8;  0 drivers
+o0000000003e9fc58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f40b40_0 .net "GATE", 0 0, o0000000003e9fc58;  0 drivers
+v0000000003f40be0_0 .net "GCLK", 0 0, L_000000000420a480;  1 drivers
+o0000000003e9fd18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f42440_0 .net "SCE", 0 0, o0000000003e9fd18;  0 drivers
+L_0000000004101e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f40fa0_0 .net8 "VGND", 0 0, L_0000000004101e80;  1 drivers, strength-aware
+L_0000000004102270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f410e0_0 .net8 "VNB", 0 0, L_0000000004102270;  1 drivers, strength-aware
+L_00000000041023c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f43480_0 .net8 "VPB", 0 0, L_00000000041023c0;  1 drivers, strength-aware
+L_0000000004101240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f44d80_0 .net8 "VPWR", 0 0, L_0000000004101240;  1 drivers, strength-aware
+S_0000000003eee300 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14826, 4 14676 1, S_00000000028e9e20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+L_000000000420a8e0 .functor NOT 1, L_000000000420aaa0, C4<0>, C4<0>, C4<0>;
+o0000000003e9fc28 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b590 .functor NOT 1, o0000000003e9fc28, C4<0>, C4<0>, C4<0>;
+o0000000003e9fcb8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003e9fd78 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420bbb0 .functor NOR 1, o0000000003e9fcb8, o0000000003e9fd78, C4<0>, C4<0>;
+L_0000000004102040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000041019b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420aaa0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_000000000420bbb0, L_000000000420b590, v0000000003f41900_0, L_0000000004102040, L_00000000041019b0;
+L_000000000420a480 .functor AND 1, L_000000000420a8e0, o0000000003e9fc28, C4<1>, C4<1>;
+L_000000000420ab10 .functor AND 1, L_0000000003f9aca0, L_0000000003f9b560, C4<1>, C4<1>;
+L_000000000420b130 .functor AND 1, L_0000000003f9aca0, L_0000000003f9d040, C4<1>, C4<1>;
+v0000000003f417c0_0 .net "CLK", 0 0, o0000000003e9fbf8;  alias, 0 drivers
+v0000000003f42120_0 .net "CLK_delayed", 0 0, o0000000003e9fc28;  0 drivers
+v0000000003f41b80_0 .net "GATE", 0 0, o0000000003e9fc58;  alias, 0 drivers
+v0000000003f40aa0_0 .net "GATE_awake", 0 0, L_000000000420b130;  1 drivers
+v0000000003f40500_0 .net "GATE_delayed", 0 0, o0000000003e9fcb8;  0 drivers
+v0000000003f40f00_0 .net "GCLK", 0 0, L_000000000420a480;  alias, 1 drivers
+v0000000003f41a40_0 .net "SCE", 0 0, o0000000003e9fd18;  alias, 0 drivers
+v0000000003f401e0_0 .net "SCE_awake", 0 0, L_000000000420ab10;  1 drivers
+v0000000003f40280_0 .net "SCE_delayed", 0 0, o0000000003e9fd78;  0 drivers
+v0000000003f41d60_0 .net "SCE_gate_delayed", 0 0, L_000000000420bbb0;  1 drivers
+v0000000003f40320_0 .net8 "VGND", 0 0, L_00000000041019b0;  1 drivers, strength-aware
+L_0000000004101390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f405a0_0 .net8 "VNB", 0 0, L_0000000004101390;  1 drivers, strength-aware
+L_0000000004101a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f41e00_0 .net8 "VPB", 0 0, L_0000000004101a20;  1 drivers, strength-aware
+v0000000003f41ea0_0 .net8 "VPWR", 0 0, L_0000000004102040;  1 drivers, strength-aware
+v0000000003f41540_0 .net *"_s10", 0 0, L_0000000003f9b560;  1 drivers
+L_000000000418c3a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f41c20_0 .net/2u *"_s14", 0 0, L_000000000418c3a0;  1 drivers
+v0000000003f40640_0 .net *"_s16", 0 0, L_0000000003f9d040;  1 drivers
+L_000000000418c310 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f41860_0 .net/2u *"_s4", 0 0, L_000000000418c310;  1 drivers
+L_000000000418c358 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f406e0_0 .net/2u *"_s8", 0 0, L_000000000418c358;  1 drivers
+v0000000003f40820_0 .net "awake", 0 0, L_0000000003f9aca0;  1 drivers
+v0000000003f408c0_0 .net "clkn", 0 0, L_000000000420b590;  1 drivers
+v0000000003f41f40_0 .net "m0", 0 0, L_000000000420aaa0;  1 drivers
+v0000000003f40c80_0 .net "m0n", 0 0, L_000000000420a8e0;  1 drivers
+v0000000003f41900_0 .var "notifier", 0 0;
+L_0000000003f9aca0 .cmp/eeq 1, L_0000000004102040, L_000000000418c310;
+L_0000000003f9b560 .cmp/eeq 1, o0000000003e9fcb8, L_000000000418c358;
+L_0000000003f9d040 .cmp/eeq 1, o0000000003e9fd78, L_000000000418c3a0;
+S_00000000028ea420 .scope module, "sky130_fd_sc_hd__sdlclkp_4" "sky130_fd_sc_hd__sdlclkp_4" 4 14342;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+o0000000003ea02b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f42d00_0 .net "CLK", 0 0, o0000000003ea02b8;  0 drivers
+o0000000003ea0318 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f450a0_0 .net "GATE", 0 0, o0000000003ea0318;  0 drivers
+v0000000003f44880_0 .net "GCLK", 0 0, L_000000000420a1e0;  1 drivers
+o0000000003ea03d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f45000_0 .net "SCE", 0 0, o0000000003ea03d8;  0 drivers
+L_0000000004101ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f441a0_0 .net8 "VGND", 0 0, L_0000000004101ef0;  1 drivers, strength-aware
+L_0000000004101b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f44560_0 .net8 "VNB", 0 0, L_0000000004101b00;  1 drivers, strength-aware
+L_0000000004102120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f44a60_0 .net8 "VPB", 0 0, L_0000000004102120;  1 drivers, strength-aware
+L_0000000004101d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f44f60_0 .net8 "VPWR", 0 0, L_0000000004101d30;  1 drivers, strength-aware
+S_0000000003eee480 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14360, 4 14676 1, S_00000000028ea420;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "GCLK"
+    .port_info 1 /INPUT 1 "SCE"
+    .port_info 2 /INPUT 1 "GATE"
+    .port_info 3 /INPUT 1 "CLK"
+L_000000000420ab80 .functor NOT 1, L_000000000420bc20, C4<0>, C4<0>, C4<0>;
+o0000000003ea02e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b2f0 .functor NOT 1, o0000000003ea02e8, C4<0>, C4<0>, C4<0>;
+o0000000003ea0378 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea0438 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b360 .functor NOR 1, o0000000003ea0378, o0000000003ea0438, C4<0>, C4<0>;
+L_0000000004102580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000041022e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420bc20 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_000000000420b360, L_000000000420b2f0, v0000000003f442e0_0, L_0000000004102580, L_00000000041022e0;
+L_000000000420a1e0 .functor AND 1, L_000000000420ab80, o0000000003ea02e8, C4<1>, C4<1>;
+L_000000000420ae20 .functor AND 1, L_0000000003f9cc80, L_0000000003f9c3c0, C4<1>, C4<1>;
+L_000000000420b3d0 .functor AND 1, L_0000000003f9cc80, L_0000000003f9e440, C4<1>, C4<1>;
+v0000000003f42940_0 .net "CLK", 0 0, o0000000003ea02b8;  alias, 0 drivers
+v0000000003f43200_0 .net "CLK_delayed", 0 0, o0000000003ea02e8;  0 drivers
+v0000000003f449c0_0 .net "GATE", 0 0, o0000000003ea0318;  alias, 0 drivers
+v0000000003f447e0_0 .net "GATE_awake", 0 0, L_000000000420b3d0;  1 drivers
+v0000000003f42e40_0 .net "GATE_delayed", 0 0, o0000000003ea0378;  0 drivers
+v0000000003f43840_0 .net "GCLK", 0 0, L_000000000420a1e0;  alias, 1 drivers
+v0000000003f44240_0 .net "SCE", 0 0, o0000000003ea03d8;  alias, 0 drivers
+v0000000003f44920_0 .net "SCE_awake", 0 0, L_000000000420ae20;  1 drivers
+v0000000003f43a20_0 .net "SCE_delayed", 0 0, o0000000003ea0438;  0 drivers
+v0000000003f44380_0 .net "SCE_gate_delayed", 0 0, L_000000000420b360;  1 drivers
+v0000000003f44420_0 .net8 "VGND", 0 0, L_00000000041022e0;  1 drivers, strength-aware
+L_00000000041020b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f444c0_0 .net8 "VNB", 0 0, L_00000000041020b0;  1 drivers, strength-aware
+L_00000000041026d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f43020_0 .net8 "VPB", 0 0, L_00000000041026d0;  1 drivers, strength-aware
+v0000000003f44740_0 .net8 "VPWR", 0 0, L_0000000004102580;  1 drivers, strength-aware
+v0000000003f43ac0_0 .net *"_s10", 0 0, L_0000000003f9c3c0;  1 drivers
+L_000000000418c478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f42da0_0 .net/2u *"_s14", 0 0, L_000000000418c478;  1 drivers
+v0000000003f42b20_0 .net *"_s16", 0 0, L_0000000003f9e440;  1 drivers
+L_000000000418c3e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f43b60_0 .net/2u *"_s4", 0 0, L_000000000418c3e8;  1 drivers
+L_000000000418c430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f43c00_0 .net/2u *"_s8", 0 0, L_000000000418c430;  1 drivers
+v0000000003f438e0_0 .net "awake", 0 0, L_0000000003f9cc80;  1 drivers
+v0000000003f446a0_0 .net "clkn", 0 0, L_000000000420b2f0;  1 drivers
+v0000000003f44060_0 .net "m0", 0 0, L_000000000420bc20;  1 drivers
+v0000000003f43de0_0 .net "m0n", 0 0, L_000000000420ab80;  1 drivers
+v0000000003f442e0_0 .var "notifier", 0 0;
+L_0000000003f9cc80 .cmp/eeq 1, L_0000000004102580, L_000000000418c3e8;
+L_0000000003f9c3c0 .cmp/eeq 1, o0000000003ea0378, L_000000000418c430;
+L_0000000003f9e440 .cmp/eeq 1, o0000000003ea0438, L_000000000418c478;
+S_00000000028e9fa0 .scope module, "sky130_fd_sc_hd__sedfxbp_1" "sky130_fd_sc_hd__sedfxbp_1" 4 99731;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+    .port_info 5 /INPUT 1 "SCD"
+    .port_info 6 /INPUT 1 "SCE"
+o0000000003ea0978 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f455a0_0 .net "CLK", 0 0, o0000000003ea0978;  0 drivers
+o0000000003ea09d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f45320_0 .net "D", 0 0, o0000000003ea09d8;  0 drivers
+o0000000003ea0a08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f46360_0 .net "DE", 0 0, o0000000003ea0a08;  0 drivers
+v0000000003f46400_0 .net "Q", 0 0, L_000000000420a5d0;  1 drivers
+v0000000003f45e60_0 .net "Q_N", 0 0, L_000000000420b9f0;  1 drivers
+o0000000003ea0af8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f46ea0_0 .net "SCD", 0 0, o0000000003ea0af8;  0 drivers
+o0000000003ea0b58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f46860_0 .net "SCE", 0 0, o0000000003ea0b58;  0 drivers
+L_00000000041024a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f465e0_0 .net8 "VGND", 0 0, L_00000000041024a0;  1 drivers, strength-aware
+L_0000000004102ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f46ae0_0 .net8 "VNB", 0 0, L_0000000004102ba0;  1 drivers, strength-aware
+L_0000000004101c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f47080_0 .net8 "VPB", 0 0, L_0000000004101c50;  1 drivers, strength-aware
+L_0000000004101cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f46a40_0 .net8 "VPWR", 0 0, L_0000000004101cc0;  1 drivers, strength-aware
+S_0000000003eee600 .scope module, "base" "sky130_fd_sc_hd__sedfxbp" 4 99755, 4 100229 1, S_00000000028e9fa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+    .port_info 5 /INPUT 1 "SCD"
+    .port_info 6 /INPUT 1 "SCE"
+o0000000003ea0b28 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea0b88 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420abf0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420a870, o0000000003ea0b28, o0000000003ea0b88;
+o0000000003ea0a68 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea0a38 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420a870 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420ac60, o0000000003ea0a68, o0000000003ea0a38;
+o0000000003ea09a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004101da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004102a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420ac60 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420abf0, o0000000003ea09a8, v0000000003f46b80_0, L_0000000004101da0, L_0000000004102a50;
+L_000000000420acd0 .functor AND 1, L_0000000003f9c1e0, L_0000000003f9d9a0, C4<1>, C4<1>;
+L_000000000420ae90 .functor AND 1, L_000000000420acd0, L_0000000003f9c8c0, C4<1>, C4<1>;
+L_000000000420b8a0 .functor AND 1, L_0000000003f9c1e0, L_0000000003f9d180, C4<1>, C4<1>;
+L_000000000420b910 .functor AND 1, L_0000000003f9c1e0, L_0000000003f9d360, C4<1>, C4<1>;
+L_000000000420b600 .functor AND 1, L_000000000420b910, L_0000000003f9d540, C4<1>, C4<1>;
+L_000000000420a5d0 .functor BUF 1, L_000000000420ac60, C4<0>, C4<0>, C4<0>;
+L_000000000420b9f0 .functor NOT 1, L_000000000420ac60, C4<0>, C4<0>, C4<0>;
+v0000000003f44600_0 .net "CLK", 0 0, o0000000003ea0978;  alias, 0 drivers
+v0000000003f429e0_0 .net "CLK_delayed", 0 0, o0000000003ea09a8;  0 drivers
+v0000000003f42ee0_0 .net "D", 0 0, o0000000003ea09d8;  alias, 0 drivers
+v0000000003f43520_0 .net "DE", 0 0, o0000000003ea0a08;  alias, 0 drivers
+v0000000003f43660_0 .net "DE_delayed", 0 0, o0000000003ea0a38;  0 drivers
+v0000000003f43980_0 .net "D_delayed", 0 0, o0000000003ea0a68;  0 drivers
+v0000000003f430c0_0 .net "Q", 0 0, L_000000000420a5d0;  alias, 1 drivers
+v0000000003f42f80_0 .net "Q_N", 0 0, L_000000000420b9f0;  alias, 1 drivers
+v0000000003f42c60_0 .net "SCD", 0 0, o0000000003ea0af8;  alias, 0 drivers
+v0000000003f44ec0_0 .net "SCD_delayed", 0 0, o0000000003ea0b28;  0 drivers
+v0000000003f435c0_0 .net "SCE", 0 0, o0000000003ea0b58;  alias, 0 drivers
+v0000000003f43160_0 .net "SCE_delayed", 0 0, o0000000003ea0b88;  0 drivers
+v0000000003f44b00_0 .net8 "VGND", 0 0, L_0000000004102a50;  1 drivers, strength-aware
+L_0000000004101160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f43f20_0 .net8 "VNB", 0 0, L_0000000004101160;  1 drivers, strength-aware
+L_00000000041025f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f433e0_0 .net8 "VPB", 0 0, L_00000000041025f0;  1 drivers, strength-aware
+v0000000003f42bc0_0 .net8 "VPWR", 0 0, L_0000000004101da0;  1 drivers, strength-aware
+v0000000003f44ce0_0 .net *"_s10", 0 0, L_0000000003f9d9a0;  1 drivers
+v0000000003f44e20_0 .net *"_s12", 0 0, L_000000000420acd0;  1 drivers
+L_000000000418c550 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f43e80_0 .net/2u *"_s14", 0 0, L_000000000418c550;  1 drivers
+v0000000003f44ba0_0 .net *"_s16", 0 0, L_0000000003f9c8c0;  1 drivers
+L_000000000418c598 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f432a0_0 .net/2u *"_s20", 0 0, L_000000000418c598;  1 drivers
+v0000000003f44c40_0 .net *"_s22", 0 0, L_0000000003f9d180;  1 drivers
+L_000000000418c5e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f42a80_0 .net/2u *"_s26", 0 0, L_000000000418c5e0;  1 drivers
+v0000000003f43340_0 .net *"_s28", 0 0, L_0000000003f9d360;  1 drivers
+v0000000003f43700_0 .net *"_s30", 0 0, L_000000000420b910;  1 drivers
+v0000000003f437a0_0 .net *"_s32", 0 0, L_0000000003f9d540;  1 drivers
+L_000000000418c4c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f43ca0_0 .net/2u *"_s4", 0 0, L_000000000418c4c0;  1 drivers
+L_000000000418c508 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f43d40_0 .net/2u *"_s8", 0 0, L_000000000418c508;  1 drivers
+v0000000003f43fc0_0 .net "awake", 0 0, L_0000000003f9c1e0;  1 drivers
+v0000000003f44100_0 .net "buf_Q", 0 0, L_000000000420ac60;  1 drivers
+v0000000003f474e0_0 .net "cond1", 0 0, L_000000000420ae90;  1 drivers
+v0000000003f45d20_0 .net "cond2", 0 0, L_000000000420b8a0;  1 drivers
+v0000000003f46680_0 .net "cond3", 0 0, L_000000000420b600;  1 drivers
+v0000000003f47620_0 .net "de_d", 0 0, L_000000000420a870;  1 drivers
+v0000000003f462c0_0 .net "mux_out", 0 0, L_000000000420abf0;  1 drivers
+v0000000003f46b80_0 .var "notifier", 0 0;
+L_0000000003f9c1e0 .cmp/eeq 1, L_0000000004101da0, L_000000000418c4c0;
+L_0000000003f9d9a0 .cmp/eeq 1, o0000000003ea0b88, L_000000000418c508;
+L_0000000003f9c8c0 .cmp/eeq 1, o0000000003ea0a38, L_000000000418c550;
+L_0000000003f9d180 .cmp/eeq 1, o0000000003ea0b88, L_000000000418c598;
+L_0000000003f9d360 .cmp/eeq 1, o0000000003ea0a38, L_000000000418c5e0;
+L_0000000003f9d540 .cmp/nee 1, o0000000003ea0a68, o0000000003ea0b28;
+S_00000000028ea120 .scope module, "sky130_fd_sc_hd__sedfxbp_2" "sky130_fd_sc_hd__sedfxbp_2" 4 99862;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+    .port_info 5 /INPUT 1 "SCD"
+    .port_info 6 /INPUT 1 "SCE"
+o0000000003ea1398 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f45280_0 .net "CLK", 0 0, o0000000003ea1398;  0 drivers
+o0000000003ea13f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f458c0_0 .net "D", 0 0, o0000000003ea13f8;  0 drivers
+o0000000003ea1428 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f46cc0_0 .net "DE", 0 0, o0000000003ea1428;  0 drivers
+v0000000003f47260_0 .net "Q", 0 0, L_000000000420a2c0;  1 drivers
+v0000000003f45960_0 .net "Q_N", 0 0, L_000000000420a3a0;  1 drivers
+o0000000003ea1518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f45a00_0 .net "SCD", 0 0, o0000000003ea1518;  0 drivers
+o0000000003ea1578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f45aa0_0 .net "SCE", 0 0, o0000000003ea1578;  0 drivers
+L_0000000004101780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f47300_0 .net8 "VGND", 0 0, L_0000000004101780;  1 drivers, strength-aware
+L_0000000004102970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f47440_0 .net8 "VNB", 0 0, L_0000000004102970;  1 drivers, strength-aware
+L_0000000004101470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f45b40_0 .net8 "VPB", 0 0, L_0000000004101470;  1 drivers, strength-aware
+L_0000000004102660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f45c80_0 .net8 "VPWR", 0 0, L_0000000004102660;  1 drivers, strength-aware
+S_0000000003ee9500 .scope module, "base" "sky130_fd_sc_hd__sedfxbp" 4 99886, 4 100229 1, S_00000000028ea120;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /OUTPUT 1 "Q_N"
+    .port_info 2 /INPUT 1 "CLK"
+    .port_info 3 /INPUT 1 "D"
+    .port_info 4 /INPUT 1 "DE"
+    .port_info 5 /INPUT 1 "SCD"
+    .port_info 6 /INPUT 1 "SCE"
+o0000000003ea1548 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea15a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420b670 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420af70, o0000000003ea1548, o0000000003ea15a8;
+o0000000003ea1488 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea1458 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420af70 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420b1a0, o0000000003ea1488, o0000000003ea1458;
+o0000000003ea13c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004102890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004101fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420b1a0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420b670, o0000000003ea13c8, v0000000003f451e0_0, L_0000000004102890, L_0000000004101fd0;
+L_000000000420b6e0 .functor AND 1, L_0000000003f9cbe0, L_0000000003f9db80, C4<1>, C4<1>;
+L_000000000420bb40 .functor AND 1, L_000000000420b6e0, L_0000000003f9e620, C4<1>, C4<1>;
+L_000000000420b750 .functor AND 1, L_0000000003f9cbe0, L_0000000003f9e6c0, C4<1>, C4<1>;
+L_000000000420a250 .functor AND 1, L_0000000003f9cbe0, L_0000000003f9da40, C4<1>, C4<1>;
+L_000000000420b7c0 .functor AND 1, L_000000000420a250, L_0000000003f9ca00, C4<1>, C4<1>;
+L_000000000420a2c0 .functor BUF 1, L_000000000420b1a0, C4<0>, C4<0>, C4<0>;
+L_000000000420a3a0 .functor NOT 1, L_000000000420b1a0, C4<0>, C4<0>, C4<0>;
+v0000000003f45dc0_0 .net "CLK", 0 0, o0000000003ea1398;  alias, 0 drivers
+v0000000003f46f40_0 .net "CLK_delayed", 0 0, o0000000003ea13c8;  0 drivers
+v0000000003f478a0_0 .net "D", 0 0, o0000000003ea13f8;  alias, 0 drivers
+v0000000003f476c0_0 .net "DE", 0 0, o0000000003ea1428;  alias, 0 drivers
+v0000000003f464a0_0 .net "DE_delayed", 0 0, o0000000003ea1458;  0 drivers
+v0000000003f46e00_0 .net "D_delayed", 0 0, o0000000003ea1488;  0 drivers
+v0000000003f47580_0 .net "Q", 0 0, L_000000000420a2c0;  alias, 1 drivers
+v0000000003f45f00_0 .net "Q_N", 0 0, L_000000000420a3a0;  alias, 1 drivers
+v0000000003f45140_0 .net "SCD", 0 0, o0000000003ea1518;  alias, 0 drivers
+v0000000003f45640_0 .net "SCD_delayed", 0 0, o0000000003ea1548;  0 drivers
+v0000000003f469a0_0 .net "SCE", 0 0, o0000000003ea1578;  alias, 0 drivers
+v0000000003f46c20_0 .net "SCE_delayed", 0 0, o0000000003ea15a8;  0 drivers
+v0000000003f46040_0 .net8 "VGND", 0 0, L_0000000004101fd0;  1 drivers, strength-aware
+L_00000000041011d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f460e0_0 .net8 "VNB", 0 0, L_00000000041011d0;  1 drivers, strength-aware
+L_00000000041029e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f45820_0 .net8 "VPB", 0 0, L_00000000041029e0;  1 drivers, strength-aware
+v0000000003f456e0_0 .net8 "VPWR", 0 0, L_0000000004102890;  1 drivers, strength-aware
+v0000000003f45460_0 .net *"_s10", 0 0, L_0000000003f9db80;  1 drivers
+v0000000003f47760_0 .net *"_s12", 0 0, L_000000000420b6e0;  1 drivers
+L_000000000418c6b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f45fa0_0 .net/2u *"_s14", 0 0, L_000000000418c6b8;  1 drivers
+v0000000003f46720_0 .net *"_s16", 0 0, L_0000000003f9e620;  1 drivers
+L_000000000418c700 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f46180_0 .net/2u *"_s20", 0 0, L_000000000418c700;  1 drivers
+v0000000003f45be0_0 .net *"_s22", 0 0, L_0000000003f9e6c0;  1 drivers
+L_000000000418c748 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f453c0_0 .net/2u *"_s26", 0 0, L_000000000418c748;  1 drivers
+v0000000003f45780_0 .net *"_s28", 0 0, L_0000000003f9da40;  1 drivers
+v0000000003f47800_0 .net *"_s30", 0 0, L_000000000420a250;  1 drivers
+v0000000003f467c0_0 .net *"_s32", 0 0, L_0000000003f9ca00;  1 drivers
+L_000000000418c628 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f46fe0_0 .net/2u *"_s4", 0 0, L_000000000418c628;  1 drivers
+L_000000000418c670 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f45500_0 .net/2u *"_s8", 0 0, L_000000000418c670;  1 drivers
+v0000000003f46d60_0 .net "awake", 0 0, L_0000000003f9cbe0;  1 drivers
+v0000000003f473a0_0 .net "buf_Q", 0 0, L_000000000420b1a0;  1 drivers
+v0000000003f46220_0 .net "cond1", 0 0, L_000000000420bb40;  1 drivers
+v0000000003f47120_0 .net "cond2", 0 0, L_000000000420b750;  1 drivers
+v0000000003f46540_0 .net "cond3", 0 0, L_000000000420b7c0;  1 drivers
+v0000000003f471c0_0 .net "de_d", 0 0, L_000000000420af70;  1 drivers
+v0000000003f46900_0 .net "mux_out", 0 0, L_000000000420b670;  1 drivers
+v0000000003f451e0_0 .var "notifier", 0 0;
+L_0000000003f9cbe0 .cmp/eeq 1, L_0000000004102890, L_000000000418c628;
+L_0000000003f9db80 .cmp/eeq 1, o0000000003ea15a8, L_000000000418c670;
+L_0000000003f9e620 .cmp/eeq 1, o0000000003ea1458, L_000000000418c6b8;
+L_0000000003f9e6c0 .cmp/eeq 1, o0000000003ea15a8, L_000000000418c700;
+L_0000000003f9da40 .cmp/eeq 1, o0000000003ea1458, L_000000000418c748;
+L_0000000003f9ca00 .cmp/nee 1, o0000000003ea1488, o0000000003ea1548;
+S_00000000028ea5a0 .scope module, "sky130_fd_sc_hd__sedfxtp_1" "sky130_fd_sc_hd__sedfxtp_1" 4 82068;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea1db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f479e0_0 .net "CLK", 0 0, o0000000003ea1db8;  0 drivers
+o0000000003ea1e18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f485c0_0 .net "D", 0 0, o0000000003ea1e18;  0 drivers
+o0000000003ea1e48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f49e20_0 .net "DE", 0 0, o0000000003ea1e48;  0 drivers
+v0000000003f49ec0_0 .net "Q", 0 0, L_000000000420c550;  1 drivers
+o0000000003ea1f08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f48340_0 .net "SCD", 0 0, o0000000003ea1f08;  0 drivers
+o0000000003ea1f68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f488e0_0 .net "SCE", 0 0, o0000000003ea1f68;  0 drivers
+L_0000000004102190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f48660_0 .net8 "VGND", 0 0, L_0000000004102190;  1 drivers, strength-aware
+L_00000000041012b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f492e0_0 .net8 "VNB", 0 0, L_00000000041012b0;  1 drivers, strength-aware
+L_0000000004102900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f49f60_0 .net8 "VPB", 0 0, L_0000000004102900;  1 drivers, strength-aware
+L_0000000004102ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f480c0_0 .net8 "VPWR", 0 0, L_0000000004102ac0;  1 drivers, strength-aware
+S_0000000003eee780 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82090, 4 82673 1, S_00000000028ea5a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea1f38 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea1f98 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420a330 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420a640, o0000000003ea1f38, o0000000003ea1f98;
+o0000000003ea1ea8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea1e78 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420a640 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420a4f0, o0000000003ea1ea8, o0000000003ea1e78;
+o0000000003ea1de8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000041014e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004102c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420a4f0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420a330, o0000000003ea1de8, v0000000003f47da0_0, L_00000000041014e0, L_0000000004102c10;
+L_000000000420a6b0 .functor AND 1, L_0000000003f9d5e0, L_0000000003f9c460, C4<1>, C4<1>;
+L_000000000420afe0 .functor AND 1, L_000000000420a6b0, L_0000000003f9e120, C4<1>, C4<1>;
+L_000000000420a790 .functor AND 1, L_0000000003f9d5e0, L_0000000003f9d680, C4<1>, C4<1>;
+L_000000000420cda0 .functor AND 1, L_0000000003f9d5e0, L_0000000003f9d720, C4<1>, C4<1>;
+L_000000000420bfa0 .functor AND 1, L_000000000420cda0, L_0000000003f9dc20, C4<1>, C4<1>;
+L_000000000420c550 .functor BUF 1, L_000000000420a4f0, C4<0>, C4<0>, C4<0>;
+v0000000003f49ba0_0 .net "CLK", 0 0, o0000000003ea1db8;  alias, 0 drivers
+v0000000003f47e40_0 .net "CLK_delayed", 0 0, o0000000003ea1de8;  0 drivers
+v0000000003f47ee0_0 .net "D", 0 0, o0000000003ea1e18;  alias, 0 drivers
+v0000000003f483e0_0 .net "DE", 0 0, o0000000003ea1e48;  alias, 0 drivers
+v0000000003f48ca0_0 .net "DE_delayed", 0 0, o0000000003ea1e78;  0 drivers
+v0000000003f49880_0 .net "D_delayed", 0 0, o0000000003ea1ea8;  0 drivers
+v0000000003f47bc0_0 .net "Q", 0 0, L_000000000420c550;  alias, 1 drivers
+v0000000003f49380_0 .net "SCD", 0 0, o0000000003ea1f08;  alias, 0 drivers
+v0000000003f48520_0 .net "SCD_delayed", 0 0, o0000000003ea1f38;  0 drivers
+v0000000003f48480_0 .net "SCE", 0 0, o0000000003ea1f68;  alias, 0 drivers
+v0000000003f49c40_0 .net "SCE_delayed", 0 0, o0000000003ea1f98;  0 drivers
+v0000000003f49240_0 .net8 "VGND", 0 0, L_0000000004102c10;  1 drivers, strength-aware
+L_0000000004102c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f49ce0_0 .net8 "VNB", 0 0, L_0000000004102c80;  1 drivers, strength-aware
+L_00000000041010f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f47c60_0 .net8 "VPB", 0 0, L_00000000041010f0;  1 drivers, strength-aware
+v0000000003f49d80_0 .net8 "VPWR", 0 0, L_00000000041014e0;  1 drivers, strength-aware
+v0000000003f49920_0 .net *"_s10", 0 0, L_0000000003f9c460;  1 drivers
+v0000000003f47f80_0 .net *"_s12", 0 0, L_000000000420a6b0;  1 drivers
+L_000000000418c820 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f48980_0 .net/2u *"_s14", 0 0, L_000000000418c820;  1 drivers
+v0000000003f49420_0 .net *"_s16", 0 0, L_0000000003f9e120;  1 drivers
+L_000000000418c868 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f49560_0 .net/2u *"_s20", 0 0, L_000000000418c868;  1 drivers
+v0000000003f47940_0 .net *"_s22", 0 0, L_0000000003f9d680;  1 drivers
+L_000000000418c8b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f482a0_0 .net/2u *"_s26", 0 0, L_000000000418c8b0;  1 drivers
+v0000000003f47d00_0 .net *"_s28", 0 0, L_0000000003f9d720;  1 drivers
+v0000000003f48de0_0 .net *"_s30", 0 0, L_000000000420cda0;  1 drivers
+v0000000003f49740_0 .net *"_s32", 0 0, L_0000000003f9dc20;  1 drivers
+L_000000000418c790 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f48020_0 .net/2u *"_s4", 0 0, L_000000000418c790;  1 drivers
+L_000000000418c7d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f48840_0 .net/2u *"_s8", 0 0, L_000000000418c7d8;  1 drivers
+v0000000003f48d40_0 .net "awake", 0 0, L_0000000003f9d5e0;  1 drivers
+v0000000003f48c00_0 .net "buf_Q", 0 0, L_000000000420a4f0;  1 drivers
+v0000000003f48e80_0 .net "cond1", 0 0, L_000000000420afe0;  1 drivers
+v0000000003f494c0_0 .net "cond2", 0 0, L_000000000420a790;  1 drivers
+v0000000003f487a0_0 .net "cond3", 0 0, L_000000000420bfa0;  1 drivers
+v0000000003f499c0_0 .net "de_d", 0 0, L_000000000420a640;  1 drivers
+v0000000003f48f20_0 .net "mux_out", 0 0, L_000000000420a330;  1 drivers
+v0000000003f47da0_0 .var "notifier", 0 0;
+L_0000000003f9d5e0 .cmp/eeq 1, L_00000000041014e0, L_000000000418c790;
+L_0000000003f9c460 .cmp/eeq 1, o0000000003ea1f98, L_000000000418c7d8;
+L_0000000003f9e120 .cmp/eeq 1, o0000000003ea1e78, L_000000000418c820;
+L_0000000003f9d680 .cmp/eeq 1, o0000000003ea1f98, L_000000000418c868;
+L_0000000003f9d720 .cmp/eeq 1, o0000000003ea1e78, L_000000000418c8b0;
+L_0000000003f9dc20 .cmp/nee 1, o0000000003ea1ea8, o0000000003ea1f38;
+S_00000000028e87a0 .scope module, "sky130_fd_sc_hd__sedfxtp_2" "sky130_fd_sc_hd__sedfxtp_2" 4 82318;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea2748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f09500_0 .net "CLK", 0 0, o0000000003ea2748;  0 drivers
+o0000000003ea27a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f095a0_0 .net "D", 0 0, o0000000003ea27a8;  0 drivers
+o0000000003ea27d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f09320_0 .net "DE", 0 0, o0000000003ea27d8;  0 drivers
+v0000000003f0a2c0_0 .net "Q", 0 0, L_000000000420bde0;  1 drivers
+o0000000003ea2898 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0b800_0 .net "SCD", 0 0, o0000000003ea2898;  0 drivers
+o0000000003ea28f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f09f00_0 .net "SCE", 0 0, o0000000003ea28f8;  0 drivers
+L_00000000041017f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f09fa0_0 .net8 "VGND", 0 0, L_00000000041017f0;  1 drivers, strength-aware
+L_0000000004101550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ad60_0 .net8 "VNB", 0 0, L_0000000004101550;  1 drivers, strength-aware
+L_0000000004101860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0a9a0_0 .net8 "VPB", 0 0, L_0000000004101860;  1 drivers, strength-aware
+L_00000000041046c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ae00_0 .net8 "VPWR", 0 0, L_00000000041046c0;  1 drivers, strength-aware
+S_0000000003eeaa00 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82340, 4 82673 1, S_00000000028e87a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea28c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea2928 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420c010 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420d190, o0000000003ea28c8, o0000000003ea2928;
+o0000000003ea2838 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea2808 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420d190 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420c940, o0000000003ea2838, o0000000003ea2808;
+o0000000003ea2778 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004103af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004104420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420c940 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420c010, o0000000003ea2778, v0000000003f0acc0_0, L_0000000004103af0, L_0000000004104420;
+L_000000000420cf60 .functor AND 1, L_0000000003f9e4e0, L_0000000003f9e800, C4<1>, C4<1>;
+L_000000000420bf30 .functor AND 1, L_000000000420cf60, L_0000000003f9dcc0, C4<1>, C4<1>;
+L_000000000420c9b0 .functor AND 1, L_0000000003f9e4e0, L_0000000003f9dd60, C4<1>, C4<1>;
+L_000000000420cb70 .functor AND 1, L_0000000003f9e4e0, L_0000000003f9d220, C4<1>, C4<1>;
+L_000000000420d660 .functor AND 1, L_000000000420cb70, L_0000000003f9c5a0, C4<1>, C4<1>;
+L_000000000420bde0 .functor BUF 1, L_000000000420c940, C4<0>, C4<0>, C4<0>;
+v0000000003f49600_0 .net "CLK", 0 0, o0000000003ea2748;  alias, 0 drivers
+v0000000003f47a80_0 .net "CLK_delayed", 0 0, o0000000003ea2778;  0 drivers
+v0000000003f48fc0_0 .net "D", 0 0, o0000000003ea27a8;  alias, 0 drivers
+v0000000003f47b20_0 .net "DE", 0 0, o0000000003ea27d8;  alias, 0 drivers
+v0000000003f48700_0 .net "DE_delayed", 0 0, o0000000003ea2808;  0 drivers
+v0000000003f48a20_0 .net "D_delayed", 0 0, o0000000003ea2838;  0 drivers
+v0000000003f49b00_0 .net "Q", 0 0, L_000000000420bde0;  alias, 1 drivers
+v0000000003f49060_0 .net "SCD", 0 0, o0000000003ea2898;  alias, 0 drivers
+v0000000003f496a0_0 .net "SCD_delayed", 0 0, o0000000003ea28c8;  0 drivers
+v0000000003f48160_0 .net "SCE", 0 0, o0000000003ea28f8;  alias, 0 drivers
+v0000000003f48ac0_0 .net "SCE_delayed", 0 0, o0000000003ea2928;  0 drivers
+v0000000003f48200_0 .net8 "VGND", 0 0, L_0000000004104420;  1 drivers, strength-aware
+L_00000000041034d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f497e0_0 .net8 "VNB", 0 0, L_00000000041034d0;  1 drivers, strength-aware
+L_00000000041040a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f48b60_0 .net8 "VPB", 0 0, L_00000000041040a0;  1 drivers, strength-aware
+v0000000003f49100_0 .net8 "VPWR", 0 0, L_0000000004103af0;  1 drivers, strength-aware
+v0000000003f491a0_0 .net *"_s10", 0 0, L_0000000003f9e800;  1 drivers
+v0000000003f49a60_0 .net *"_s12", 0 0, L_000000000420cf60;  1 drivers
+L_000000000418c988 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f09460_0 .net/2u *"_s14", 0 0, L_000000000418c988;  1 drivers
+v0000000003f09c80_0 .net *"_s16", 0 0, L_0000000003f9dcc0;  1 drivers
+L_000000000418c9d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f0b580_0 .net/2u *"_s20", 0 0, L_000000000418c9d0;  1 drivers
+v0000000003f0aae0_0 .net *"_s22", 0 0, L_0000000003f9dd60;  1 drivers
+L_000000000418ca18 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f0ab80_0 .net/2u *"_s26", 0 0, L_000000000418ca18;  1 drivers
+v0000000003f09140_0 .net *"_s28", 0 0, L_0000000003f9d220;  1 drivers
+v0000000003f09e60_0 .net *"_s30", 0 0, L_000000000420cb70;  1 drivers
+v0000000003f091e0_0 .net *"_s32", 0 0, L_0000000003f9c5a0;  1 drivers
+L_000000000418c8f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f09aa0_0 .net/2u *"_s4", 0 0, L_000000000418c8f8;  1 drivers
+L_000000000418c940 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f093c0_0 .net/2u *"_s8", 0 0, L_000000000418c940;  1 drivers
+v0000000003f09820_0 .net "awake", 0 0, L_0000000003f9e4e0;  1 drivers
+v0000000003f0ac20_0 .net "buf_Q", 0 0, L_000000000420c940;  1 drivers
+v0000000003f0a4a0_0 .net "cond1", 0 0, L_000000000420bf30;  1 drivers
+v0000000003f0a040_0 .net "cond2", 0 0, L_000000000420c9b0;  1 drivers
+v0000000003f0aa40_0 .net "cond3", 0 0, L_000000000420d660;  1 drivers
+v0000000003f0b120_0 .net "de_d", 0 0, L_000000000420d190;  1 drivers
+v0000000003f0a720_0 .net "mux_out", 0 0, L_000000000420c010;  1 drivers
+v0000000003f0acc0_0 .var "notifier", 0 0;
+L_0000000003f9e4e0 .cmp/eeq 1, L_0000000004103af0, L_000000000418c8f8;
+L_0000000003f9e800 .cmp/eeq 1, o0000000003ea2928, L_000000000418c940;
+L_0000000003f9dcc0 .cmp/eeq 1, o0000000003ea2808, L_000000000418c988;
+L_0000000003f9dd60 .cmp/eeq 1, o0000000003ea2928, L_000000000418c9d0;
+L_0000000003f9d220 .cmp/eeq 1, o0000000003ea2808, L_000000000418ca18;
+L_0000000003f9c5a0 .cmp/nee 1, o0000000003ea2838, o0000000003ea28c8;
+S_00000000028e69a0 .scope module, "sky130_fd_sc_hd__sedfxtp_4" "sky130_fd_sc_hd__sedfxtp_4" 4 82193;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea30d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f0a900_0 .net "CLK", 0 0, o0000000003ea30d8;  0 drivers
+o0000000003ea3138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f87ba0_0 .net "D", 0 0, o0000000003ea3138;  0 drivers
+o0000000003ea3168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f86d40_0 .net "DE", 0 0, o0000000003ea3168;  0 drivers
+v0000000003f879c0_0 .net "Q", 0 0, L_000000000420d270;  1 drivers
+o0000000003ea3228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f85bc0_0 .net "SCD", 0 0, o0000000003ea3228;  0 drivers
+o0000000003ea3288 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f86840_0 .net "SCE", 0 0, o0000000003ea3288;  0 drivers
+L_0000000004103ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87e20_0 .net8 "VGND", 0 0, L_0000000004103ee0;  1 drivers, strength-aware
+L_00000000041045e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86480_0 .net8 "VNB", 0 0, L_00000000041045e0;  1 drivers, strength-aware
+L_00000000041039a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87d80_0 .net8 "VPB", 0 0, L_00000000041039a0;  1 drivers, strength-aware
+L_0000000004102e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f86f20_0 .net8 "VPWR", 0 0, L_0000000004102e40;  1 drivers, strength-aware
+S_0000000003eec980 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82215, 4 82673 1, S_00000000028e69a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Q"
+    .port_info 1 /INPUT 1 "CLK"
+    .port_info 2 /INPUT 1 "D"
+    .port_info 3 /INPUT 1 "DE"
+    .port_info 4 /INPUT 1 "SCD"
+    .port_info 5 /INPUT 1 "SCE"
+o0000000003ea3258 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea32b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420d820 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420d430, o0000000003ea3258, o0000000003ea32b8;
+o0000000003ea31c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003ea3198 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000420d430 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000420d040, o0000000003ea31c8, o0000000003ea3198;
+o0000000003ea3108 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000004102f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000004103310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000420d040 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000420d820, o0000000003ea3108, v0000000003f09be0_0, L_0000000004102f20, L_0000000004103310;
+L_000000000420d200 .functor AND 1, L_0000000003f9e760, L_0000000003f9c280, C4<1>, C4<1>;
+L_000000000420c400 .functor AND 1, L_000000000420d200, L_0000000003f9c640, C4<1>, C4<1>;
+L_000000000420ca20 .functor AND 1, L_0000000003f9e760, L_0000000003f9d7c0, C4<1>, C4<1>;
+L_000000000420c5c0 .functor AND 1, L_0000000003f9e760, L_0000000003f9c820, C4<1>, C4<1>;
+L_000000000420c320 .functor AND 1, L_000000000420c5c0, L_0000000003f9c140, C4<1>, C4<1>;
+L_000000000420d270 .functor BUF 1, L_000000000420d040, C4<0>, C4<0>, C4<0>;
+v0000000003f0a360_0 .net "CLK", 0 0, o0000000003ea30d8;  alias, 0 drivers
+v0000000003f0aea0_0 .net "CLK_delayed", 0 0, o0000000003ea3108;  0 drivers
+v0000000003f09dc0_0 .net "D", 0 0, o0000000003ea3138;  alias, 0 drivers
+v0000000003f0af40_0 .net "DE", 0 0, o0000000003ea3168;  alias, 0 drivers
+v0000000003f0b760_0 .net "DE_delayed", 0 0, o0000000003ea3198;  0 drivers
+v0000000003f0a0e0_0 .net "D_delayed", 0 0, o0000000003ea31c8;  0 drivers
+v0000000003f0afe0_0 .net "Q", 0 0, L_000000000420d270;  alias, 1 drivers
+v0000000003f0b080_0 .net "SCD", 0 0, o0000000003ea3228;  alias, 0 drivers
+v0000000003f0b1c0_0 .net "SCD_delayed", 0 0, o0000000003ea3258;  0 drivers
+v0000000003f0b260_0 .net "SCE", 0 0, o0000000003ea3288;  alias, 0 drivers
+v0000000003f0a180_0 .net "SCE_delayed", 0 0, o0000000003ea32b8;  0 drivers
+v0000000003f0b300_0 .net8 "VGND", 0 0, L_0000000004103310;  1 drivers, strength-aware
+L_0000000004102eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f09640_0 .net8 "VNB", 0 0, L_0000000004102eb0;  1 drivers, strength-aware
+L_0000000004103a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f0b3a0_0 .net8 "VPB", 0 0, L_0000000004103a80;  1 drivers, strength-aware
+v0000000003f0b440_0 .net8 "VPWR", 0 0, L_0000000004102f20;  1 drivers, strength-aware
+v0000000003f0a220_0 .net *"_s10", 0 0, L_0000000003f9c280;  1 drivers
+v0000000003f0a400_0 .net *"_s12", 0 0, L_000000000420d200;  1 drivers
+L_000000000418caf0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f0a680_0 .net/2u *"_s14", 0 0, L_000000000418caf0;  1 drivers
+v0000000003f096e0_0 .net *"_s16", 0 0, L_0000000003f9c640;  1 drivers
+L_000000000418cb38 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f0b4e0_0 .net/2u *"_s20", 0 0, L_000000000418cb38;  1 drivers
+v0000000003f09d20_0 .net *"_s22", 0 0, L_0000000003f9d7c0;  1 drivers
+L_000000000418cb80 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f09780_0 .net/2u *"_s26", 0 0, L_000000000418cb80;  1 drivers
+v0000000003f0a540_0 .net *"_s28", 0 0, L_0000000003f9c820;  1 drivers
+v0000000003f0b620_0 .net *"_s30", 0 0, L_000000000420c5c0;  1 drivers
+v0000000003f09280_0 .net *"_s32", 0 0, L_0000000003f9c140;  1 drivers
+L_000000000418ca60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003f0a5e0_0 .net/2u *"_s4", 0 0, L_000000000418ca60;  1 drivers
+L_000000000418caa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003f09960_0 .net/2u *"_s8", 0 0, L_000000000418caa8;  1 drivers
+v0000000003f0a7c0_0 .net "awake", 0 0, L_0000000003f9e760;  1 drivers
+v0000000003f0b6c0_0 .net "buf_Q", 0 0, L_000000000420d040;  1 drivers
+v0000000003f0a860_0 .net "cond1", 0 0, L_000000000420c400;  1 drivers
+v0000000003f0b8a0_0 .net "cond2", 0 0, L_000000000420ca20;  1 drivers
+v0000000003f098c0_0 .net "cond3", 0 0, L_000000000420c320;  1 drivers
+v0000000003f09a00_0 .net "de_d", 0 0, L_000000000420d430;  1 drivers
+v0000000003f09b40_0 .net "mux_out", 0 0, L_000000000420d820;  1 drivers
+v0000000003f09be0_0 .var "notifier", 0 0;
+L_0000000003f9e760 .cmp/eeq 1, L_0000000004102f20, L_000000000418ca60;
+L_0000000003f9c280 .cmp/eeq 1, o0000000003ea32b8, L_000000000418caa8;
+L_0000000003f9c640 .cmp/eeq 1, o0000000003ea3198, L_000000000418caf0;
+L_0000000003f9d7c0 .cmp/eeq 1, o0000000003ea32b8, L_000000000418cb38;
+L_0000000003f9c820 .cmp/eeq 1, o0000000003ea3198, L_000000000418cb80;
+L_0000000003f9c140 .cmp/nee 1, o0000000003ea31c8, o0000000003ea3258;
+S_00000000028e7d20 .scope module, "sky130_fd_sc_hd__tap_1" "sky130_fd_sc_hd__tap_1" 4 90393;
+ .timescale -9 -12;
+L_0000000004103c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86200_0 .net8 "VGND", 0 0, L_0000000004103c40;  1 drivers, strength-aware
+L_0000000004103b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87a60_0 .net8 "VNB", 0 0, L_0000000004103b60;  1 drivers, strength-aware
+L_00000000041031c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f877e0_0 .net8 "VPB", 0 0, L_00000000041031c0;  1 drivers, strength-aware
+L_00000000041035b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f86ca0_0 .net8 "VPWR", 0 0, L_00000000041035b0;  1 drivers, strength-aware
+S_0000000003eeb000 .scope module, "base" "sky130_fd_sc_hd__tap" 4 90400, 4 90307 1, S_00000000028e7d20;
+ .timescale -9 -12;
+L_0000000004102f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86a20_0 .net8 "VGND", 0 0, L_0000000004102f90;  1 drivers, strength-aware
+L_0000000004103540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87560_0 .net8 "VNB", 0 0, L_0000000004103540;  1 drivers, strength-aware
+L_0000000004103620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f86660_0 .net8 "VPB", 0 0, L_0000000004103620;  1 drivers, strength-aware
+L_0000000004104180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f86340_0 .net8 "VPWR", 0 0, L_0000000004104180;  1 drivers, strength-aware
+S_00000000028e5c20 .scope module, "sky130_fd_sc_hd__tap_2" "sky130_fd_sc_hd__tap_2" 4 90073;
+ .timescale -9 -12;
+L_0000000004103cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86520_0 .net8 "VGND", 0 0, L_0000000004103cb0;  1 drivers, strength-aware
+L_0000000004103690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87740_0 .net8 "VNB", 0 0, L_0000000004103690;  1 drivers, strength-aware
+L_00000000041047a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f860c0_0 .net8 "VPB", 0 0, L_00000000041047a0;  1 drivers, strength-aware
+L_0000000004104880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f85da0_0 .net8 "VPWR", 0 0, L_0000000004104880;  1 drivers, strength-aware
+S_0000000003eeb600 .scope module, "base" "sky130_fd_sc_hd__tap" 4 90080, 4 90307 1, S_00000000028e5c20;
+ .timescale -9 -12;
+L_0000000004103930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86de0_0 .net8 "VGND", 0 0, L_0000000004103930;  1 drivers, strength-aware
+L_0000000004103e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86ac0_0 .net8 "VNB", 0 0, L_0000000004103e00;  1 drivers, strength-aware
+L_0000000004103700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87380_0 .net8 "VPB", 0 0, L_0000000004103700;  1 drivers, strength-aware
+L_0000000004102cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f862a0_0 .net8 "VPWR", 0 0, L_0000000004102cf0;  1 drivers, strength-aware
+S_00000000028e3220 .scope module, "sky130_fd_sc_hd__tapvgnd2_1" "sky130_fd_sc_hd__tapvgnd2_1" 4 41561;
+ .timescale -9 -12;
+L_0000000004102d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86fc0_0 .net8 "VGND", 0 0, L_0000000004102d60;  1 drivers, strength-aware
+L_0000000004103770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f859e0_0 .net8 "VNB", 0 0, L_0000000004103770;  1 drivers, strength-aware
+L_0000000004103000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87ec0_0 .net8 "VPB", 0 0, L_0000000004103000;  1 drivers, strength-aware
+L_0000000004103bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f85d00_0 .net8 "VPWR", 0 0, L_0000000004103bd0;  1 drivers, strength-aware
+S_0000000003eeb180 .scope module, "base" "sky130_fd_sc_hd__tapvgnd2" 4 41568, 4 41474 1, S_00000000028e3220;
+ .timescale -9 -12;
+L_00000000041037e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86e80_0 .net8 "VGND", 0 0, L_00000000041037e0;  1 drivers, strength-aware
+L_0000000004103f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86700_0 .net8 "VNB", 0 0, L_0000000004103f50;  1 drivers, strength-aware
+L_0000000004103fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f867a0_0 .net8 "VPB", 0 0, L_0000000004103fc0;  1 drivers, strength-aware
+L_0000000004103850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87060_0 .net8 "VPWR", 0 0, L_0000000004103850;  1 drivers, strength-aware
+S_00000000028e8f20 .scope module, "sky130_fd_sc_hd__tapvgnd_1" "sky130_fd_sc_hd__tapvgnd_1" 4 45024;
+ .timescale -9 -12;
+L_00000000041038c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f876a0_0 .net8 "VGND", 0 0, L_00000000041038c0;  1 drivers, strength-aware
+L_0000000004104260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f880a0_0 .net8 "VNB", 0 0, L_0000000004104260;  1 drivers, strength-aware
+L_00000000041042d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f88000_0 .net8 "VPB", 0 0, L_00000000041042d0;  1 drivers, strength-aware
+L_0000000004104570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f874c0_0 .net8 "VPWR", 0 0, L_0000000004104570;  1 drivers, strength-aware
+S_0000000003eecb00 .scope module, "base" "sky130_fd_sc_hd__tapvgnd" 4 45031, 4 45263 1, S_00000000028e8f20;
+ .timescale -9 -12;
+L_0000000004103e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87f60_0 .net8 "VGND", 0 0, L_0000000004103e70;  1 drivers, strength-aware
+L_00000000041043b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f85940_0 .net8 "VNB", 0 0, L_00000000041043b0;  1 drivers, strength-aware
+L_0000000004104650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f871a0_0 .net8 "VPB", 0 0, L_0000000004104650;  1 drivers, strength-aware
+L_0000000004104340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87420_0 .net8 "VPWR", 0 0, L_0000000004104340;  1 drivers, strength-aware
+S_00000000028e7720 .scope module, "sky130_fd_sc_hd__tapvpwrvgnd_1" "sky130_fd_sc_hd__tapvpwrvgnd_1" 4 55677;
+ .timescale -9 -12;
+L_0000000004104490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f868e0_0 .net8 "VGND", 0 0, L_0000000004104490;  1 drivers, strength-aware
+L_0000000004103070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86980_0 .net8 "VNB", 0 0, L_0000000004103070;  1 drivers, strength-aware
+L_0000000004103a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87100_0 .net8 "VPB", 0 0, L_0000000004103a10;  1 drivers, strength-aware
+L_0000000004104500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f85c60_0 .net8 "VPWR", 0 0, L_0000000004104500;  1 drivers, strength-aware
+S_0000000003eeb300 .scope module, "base" "sky130_fd_sc_hd__tapvpwrvgnd" 4 55684, 4 55911 1, S_00000000028e7720;
+ .timescale -9 -12;
+L_0000000004103d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f872e0_0 .net8 "VGND", 0 0, L_0000000004103d20;  1 drivers, strength-aware
+L_0000000004103d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f85a80_0 .net8 "VNB", 0 0, L_0000000004103d90;  1 drivers, strength-aware
+L_0000000004104030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f85e40_0 .net8 "VPB", 0 0, L_0000000004104030;  1 drivers, strength-aware
+L_0000000004103230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f865c0_0 .net8 "VPWR", 0 0, L_0000000004103230;  1 drivers, strength-aware
+S_00000000028e6ca0 .scope module, "sky130_fd_sc_hd__xnor2_1" "sky130_fd_sc_hd__xnor2_1" 4 99084;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea41e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f85b20_0 .net "A", 0 0, o0000000003ea41e8;  0 drivers
+o0000000003ea4218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f87880_0 .net "B", 0 0, o0000000003ea4218;  0 drivers
+L_0000000004104810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87920_0 .net8 "VGND", 0 0, L_0000000004104810;  1 drivers, strength-aware
+L_00000000041030e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f87c40_0 .net8 "VNB", 0 0, L_00000000041030e0;  1 drivers, strength-aware
+L_0000000004102dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87ce0_0 .net8 "VPB", 0 0, L_0000000004102dd0;  1 drivers, strength-aware
+L_0000000004104110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f86020_0 .net8 "VPWR", 0 0, L_0000000004104110;  1 drivers, strength-aware
+v0000000003f86160_0 .net "Y", 0 0, L_000000000420c8d0;  1 drivers
+S_0000000003eeb780 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99100, 4 99391 1, S_00000000028e6ca0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420bd00 .functor XNOR 1, o0000000003ea41e8, o0000000003ea4218, C4<0>, C4<0>;
+L_000000000420c8d0 .functor BUF 1, L_000000000420bd00, C4<0>, C4<0>, C4<0>;
+v0000000003f85ee0_0 .net "A", 0 0, o0000000003ea41e8;  alias, 0 drivers
+v0000000003f86b60_0 .net "B", 0 0, o0000000003ea4218;  alias, 0 drivers
+L_00000000041041f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f863e0_0 .net8 "VGND", 0 0, L_00000000041041f0;  1 drivers, strength-aware
+L_0000000004104730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f86c00_0 .net8 "VNB", 0 0, L_0000000004104730;  1 drivers, strength-aware
+L_0000000004103150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f85f80_0 .net8 "VPB", 0 0, L_0000000004103150;  1 drivers, strength-aware
+L_00000000041032a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f87240_0 .net8 "VPWR", 0 0, L_00000000041032a0;  1 drivers, strength-aware
+v0000000003f87600_0 .net "Y", 0 0, L_000000000420c8d0;  alias, 1 drivers
+v0000000003f87b00_0 .net "xnor0_out_Y", 0 0, L_000000000420bd00;  1 drivers
+S_00000000028e6220 .scope module, "sky130_fd_sc_hd__xnor2_2" "sky130_fd_sc_hd__xnor2_2" 4 99612;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea4548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f89fe0_0 .net "A", 0 0, o0000000003ea4548;  0 drivers
+o0000000003ea4578 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f89540_0 .net "B", 0 0, o0000000003ea4578;  0 drivers
+L_0000000004103380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88140_0 .net8 "VGND", 0 0, L_0000000004103380;  1 drivers, strength-aware
+L_00000000041033f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88d20_0 .net8 "VNB", 0 0, L_00000000041033f0;  1 drivers, strength-aware
+L_0000000004103460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89680_0 .net8 "VPB", 0 0, L_0000000004103460;  1 drivers, strength-aware
+L_0000000004105140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a760_0 .net8 "VPWR", 0 0, L_0000000004105140;  1 drivers, strength-aware
+v0000000003f892c0_0 .net "Y", 0 0, L_000000000420c390;  1 drivers
+S_0000000003eeb900 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99628, 4 99391 1, S_00000000028e6220;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420c710 .functor XNOR 1, o0000000003ea4548, o0000000003ea4578, C4<0>, C4<0>;
+L_000000000420c390 .functor BUF 1, L_000000000420c710, C4<0>, C4<0>, C4<0>;
+v0000000003f8a620_0 .net "A", 0 0, o0000000003ea4548;  alias, 0 drivers
+v0000000003f88a00_0 .net "B", 0 0, o0000000003ea4578;  alias, 0 drivers
+L_00000000041050d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88f00_0 .net8 "VGND", 0 0, L_00000000041050d0;  1 drivers, strength-aware
+L_00000000041051b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88780_0 .net8 "VNB", 0 0, L_00000000041051b0;  1 drivers, strength-aware
+L_0000000004105df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a800_0 .net8 "VPB", 0 0, L_0000000004105df0;  1 drivers, strength-aware
+L_0000000004105e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a6c0_0 .net8 "VPWR", 0 0, L_0000000004105e60;  1 drivers, strength-aware
+v0000000003f8a080_0 .net "Y", 0 0, L_000000000420c390;  alias, 1 drivers
+v0000000003f8a260_0 .net "xnor0_out_Y", 0 0, L_000000000420c710;  1 drivers
+S_00000000028e8620 .scope module, "sky130_fd_sc_hd__xnor2_4" "sky130_fd_sc_hd__xnor2_4" 4 99504;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea48a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8a4e0_0 .net "A", 0 0, o0000000003ea48a8;  0 drivers
+o0000000003ea48d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f885a0_0 .net "B", 0 0, o0000000003ea48d8;  0 drivers
+L_0000000004104ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88320_0 .net8 "VGND", 0 0, L_0000000004104ea0;  1 drivers, strength-aware
+L_0000000004105610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a3a0_0 .net8 "VNB", 0 0, L_0000000004105610;  1 drivers, strength-aware
+L_0000000004105220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89180_0 .net8 "VPB", 0 0, L_0000000004105220;  1 drivers, strength-aware
+L_0000000004105060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f88640_0 .net8 "VPWR", 0 0, L_0000000004105060;  1 drivers, strength-aware
+v0000000003f89720_0 .net "Y", 0 0, L_000000000420cbe0;  1 drivers
+S_0000000003ef0e80 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99520, 4 99391 1, S_00000000028e8620;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "Y"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420c780 .functor XNOR 1, o0000000003ea48a8, o0000000003ea48d8, C4<0>, C4<0>;
+L_000000000420cbe0 .functor BUF 1, L_000000000420c780, C4<0>, C4<0>, C4<0>;
+v0000000003f89cc0_0 .net "A", 0 0, o0000000003ea48a8;  alias, 0 drivers
+v0000000003f8a120_0 .net "B", 0 0, o0000000003ea48d8;  alias, 0 drivers
+L_0000000004104a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a8a0_0 .net8 "VGND", 0 0, L_0000000004104a40;  1 drivers, strength-aware
+L_0000000004105a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88c80_0 .net8 "VNB", 0 0, L_0000000004105a00;  1 drivers, strength-aware
+L_00000000041048f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a1c0_0 .net8 "VPB", 0 0, L_00000000041048f0;  1 drivers, strength-aware
+L_00000000041054c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f895e0_0 .net8 "VPWR", 0 0, L_00000000041054c0;  1 drivers, strength-aware
+v0000000003f89a40_0 .net "Y", 0 0, L_000000000420cbe0;  alias, 1 drivers
+v0000000003f8a300_0 .net "xnor0_out_Y", 0 0, L_000000000420c780;  1 drivers
+S_00000000028e90a0 .scope module, "sky130_fd_sc_hd__xnor3_1" "sky130_fd_sc_hd__xnor3_1" 4 57031;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea4c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8a580_0 .net "A", 0 0, o0000000003ea4c08;  0 drivers
+o0000000003ea4c38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f883c0_0 .net "B", 0 0, o0000000003ea4c38;  0 drivers
+o0000000003ea4c68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f894a0_0 .net "C", 0 0, o0000000003ea4c68;  0 drivers
+L_0000000004104dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f890e0_0 .net8 "VGND", 0 0, L_0000000004104dc0;  1 drivers, strength-aware
+L_00000000041055a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f89860_0 .net8 "VNB", 0 0, L_00000000041055a0;  1 drivers, strength-aware
+L_0000000004104d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89360_0 .net8 "VPB", 0 0, L_0000000004104d50;  1 drivers, strength-aware
+L_0000000004105290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89400_0 .net8 "VPWR", 0 0, L_0000000004105290;  1 drivers, strength-aware
+v0000000003f88460_0 .net "X", 0 0, L_000000000420cc50;  1 drivers
+S_0000000003ef4900 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57049, 4 57561 1, S_00000000028e90a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420c630 .functor XNOR 1, o0000000003ea4c08, o0000000003ea4c38, o0000000003ea4c68, C4<0>;
+L_000000000420cc50 .functor BUF 1, L_000000000420c630, C4<0>, C4<0>, C4<0>;
+v0000000003f89e00_0 .net "A", 0 0, o0000000003ea4c08;  alias, 0 drivers
+v0000000003f881e0_0 .net "B", 0 0, o0000000003ea4c38;  alias, 0 drivers
+v0000000003f897c0_0 .net "C", 0 0, o0000000003ea4c68;  alias, 0 drivers
+L_0000000004104b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a440_0 .net8 "VGND", 0 0, L_0000000004104b20;  1 drivers, strength-aware
+L_0000000004105530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f886e0_0 .net8 "VNB", 0 0, L_0000000004105530;  1 drivers, strength-aware
+L_0000000004105f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89220_0 .net8 "VPB", 0 0, L_0000000004105f40;  1 drivers, strength-aware
+L_0000000004105300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89d60_0 .net8 "VPWR", 0 0, L_0000000004105300;  1 drivers, strength-aware
+v0000000003f88280_0 .net "X", 0 0, L_000000000420cc50;  alias, 1 drivers
+v0000000003f88e60_0 .net "xnor0_out_X", 0 0, L_000000000420c630;  1 drivers
+S_00000000028e48a0 .scope module, "sky130_fd_sc_hd__xnor3_2" "sky130_fd_sc_hd__xnor3_2" 4 57255;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea4ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f89f40_0 .net "A", 0 0, o0000000003ea4ff8;  0 drivers
+o0000000003ea5028 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f88820_0 .net "B", 0 0, o0000000003ea5028;  0 drivers
+o0000000003ea5058 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f888c0_0 .net "C", 0 0, o0000000003ea5058;  0 drivers
+L_0000000004105370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88960_0 .net8 "VGND", 0 0, L_0000000004105370;  1 drivers, strength-aware
+L_0000000004105920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f88dc0_0 .net8 "VNB", 0 0, L_0000000004105920;  1 drivers, strength-aware
+L_00000000041053e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f88aa0_0 .net8 "VPB", 0 0, L_00000000041053e0;  1 drivers, strength-aware
+L_0000000004105c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f88b40_0 .net8 "VPWR", 0 0, L_0000000004105c30;  1 drivers, strength-aware
+v0000000003f88be0_0 .net "X", 0 0, L_000000000420bd70;  1 drivers
+S_0000000003ef3880 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57273, 4 57561 1, S_00000000028e48a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420d890 .functor XNOR 1, o0000000003ea4ff8, o0000000003ea5028, o0000000003ea5058, C4<0>;
+L_000000000420bd70 .functor BUF 1, L_000000000420d890, C4<0>, C4<0>, C4<0>;
+v0000000003f88fa0_0 .net "A", 0 0, o0000000003ea4ff8;  alias, 0 drivers
+v0000000003f89ea0_0 .net "B", 0 0, o0000000003ea5028;  alias, 0 drivers
+v0000000003f89900_0 .net "C", 0 0, o0000000003ea5058;  alias, 0 drivers
+L_0000000004104960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f89040_0 .net8 "VGND", 0 0, L_0000000004104960;  1 drivers, strength-aware
+L_00000000041058b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f899a0_0 .net8 "VNB", 0 0, L_00000000041058b0;  1 drivers, strength-aware
+L_0000000004105450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89ae0_0 .net8 "VPB", 0 0, L_0000000004105450;  1 drivers, strength-aware
+L_0000000004105d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f89b80_0 .net8 "VPWR", 0 0, L_0000000004105d80;  1 drivers, strength-aware
+v0000000003f89c20_0 .net "X", 0 0, L_000000000420bd70;  alias, 1 drivers
+v0000000003f88500_0 .net "xnor0_out_X", 0 0, L_000000000420d890;  1 drivers
+S_00000000028e5da0 .scope module, "sky130_fd_sc_hd__xnor3_4" "sky130_fd_sc_hd__xnor3_4" 4 57143;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea53e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8b980_0 .net "A", 0 0, o0000000003ea53e8;  0 drivers
+o0000000003ea5418 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8b3e0_0 .net "B", 0 0, o0000000003ea5418;  0 drivers
+o0000000003ea5448 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8b840_0 .net "C", 0 0, o0000000003ea5448;  0 drivers
+L_0000000004104f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b160_0 .net8 "VGND", 0 0, L_0000000004104f80;  1 drivers, strength-aware
+L_0000000004104ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c2e0_0 .net8 "VNB", 0 0, L_0000000004104ce0;  1 drivers, strength-aware
+L_00000000041049d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c7e0_0 .net8 "VPB", 0 0, L_00000000041049d0;  1 drivers, strength-aware
+L_0000000004105d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b5c0_0 .net8 "VPWR", 0 0, L_0000000004105d10;  1 drivers, strength-aware
+v0000000003f8c740_0 .net "X", 0 0, L_000000000420c4e0;  1 drivers
+S_0000000003ef3580 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57161, 4 57561 1, S_00000000028e5da0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420be50 .functor XNOR 1, o0000000003ea53e8, o0000000003ea5418, o0000000003ea5448, C4<0>;
+L_000000000420c4e0 .functor BUF 1, L_000000000420be50, C4<0>, C4<0>, C4<0>;
+v0000000003f8b660_0 .net "A", 0 0, o0000000003ea53e8;  alias, 0 drivers
+v0000000003f8c920_0 .net "B", 0 0, o0000000003ea5418;  alias, 0 drivers
+v0000000003f8c1a0_0 .net "C", 0 0, o0000000003ea5448;  alias, 0 drivers
+L_0000000004105680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b700_0 .net8 "VGND", 0 0, L_0000000004105680;  1 drivers, strength-aware
+L_0000000004104f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c380_0 .net8 "VNB", 0 0, L_0000000004104f10;  1 drivers, strength-aware
+L_00000000041056f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b020_0 .net8 "VPB", 0 0, L_00000000041056f0;  1 drivers, strength-aware
+L_0000000004105760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ada0_0 .net8 "VPWR", 0 0, L_0000000004105760;  1 drivers, strength-aware
+v0000000003f8ac60_0 .net "X", 0 0, L_000000000420c4e0;  alias, 1 drivers
+v0000000003f8c240_0 .net "xnor0_out_X", 0 0, L_000000000420be50;  1 drivers
+S_00000000028e8920 .scope module, "sky130_fd_sc_hd__xor2_1" "sky130_fd_sc_hd__xor2_1" 4 39544;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea57d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8ba20_0 .net "A", 0 0, o0000000003ea57d8;  0 drivers
+o0000000003ea5808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8aee0_0 .net "B", 0 0, o0000000003ea5808;  0 drivers
+L_0000000004104e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8abc0_0 .net8 "VGND", 0 0, L_0000000004104e30;  1 drivers, strength-aware
+L_00000000041057d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b8e0_0 .net8 "VNB", 0 0, L_00000000041057d0;  1 drivers, strength-aware
+L_0000000004105840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8cec0_0 .net8 "VPB", 0 0, L_0000000004105840;  1 drivers, strength-aware
+L_0000000004105ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8d0a0_0 .net8 "VPWR", 0 0, L_0000000004105ed0;  1 drivers, strength-aware
+v0000000003f8c600_0 .net "X", 0 0, L_000000000420c6a0;  1 drivers
+S_0000000003ef1180 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39560, 4 39851 1, S_00000000028e8920;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420bec0 .functor XOR 1, o0000000003ea5808, o0000000003ea57d8, C4<0>, C4<0>;
+L_000000000420c6a0 .functor BUF 1, L_000000000420bec0, C4<0>, C4<0>, C4<0>;
+v0000000003f8b7a0_0 .net "A", 0 0, o0000000003ea57d8;  alias, 0 drivers
+v0000000003f8ca60_0 .net "B", 0 0, o0000000003ea5808;  alias, 0 drivers
+L_0000000004105990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ce20_0 .net8 "VGND", 0 0, L_0000000004105990;  1 drivers, strength-aware
+L_0000000004104ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8cd80_0 .net8 "VNB", 0 0, L_0000000004104ab0;  1 drivers, strength-aware
+L_0000000004105a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bac0_0 .net8 "VPB", 0 0, L_0000000004105a70;  1 drivers, strength-aware
+L_0000000004105bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8cce0_0 .net8 "VPWR", 0 0, L_0000000004105bc0;  1 drivers, strength-aware
+v0000000003f8ae40_0 .net "X", 0 0, L_000000000420c6a0;  alias, 1 drivers
+v0000000003f8c880_0 .net "xor0_out_X", 0 0, L_000000000420bec0;  1 drivers
+S_00000000028e51a0 .scope module, "sky130_fd_sc_hd__xor2_2" "sky130_fd_sc_hd__xor2_2" 4 39964;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea5b38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8a9e0_0 .net "A", 0 0, o0000000003ea5b38;  0 drivers
+o0000000003ea5b68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8c420_0 .net "B", 0 0, o0000000003ea5b68;  0 drivers
+L_0000000004104ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bca0_0 .net8 "VGND", 0 0, L_0000000004104ff0;  1 drivers, strength-aware
+L_0000000004105ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bd40_0 .net8 "VNB", 0 0, L_0000000004105ae0;  1 drivers, strength-aware
+L_0000000004105b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c9c0_0 .net8 "VPB", 0 0, L_0000000004105b50;  1 drivers, strength-aware
+L_0000000004105ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c4c0_0 .net8 "VPWR", 0 0, L_0000000004105ca0;  1 drivers, strength-aware
+v0000000003f8b0c0_0 .net "X", 0 0, L_000000000420cfd0;  1 drivers
+S_0000000003ef2080 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39980, 4 39851 1, S_00000000028e51a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420c080 .functor XOR 1, o0000000003ea5b68, o0000000003ea5b38, C4<0>, C4<0>;
+L_000000000420cfd0 .functor BUF 1, L_000000000420c080, C4<0>, C4<0>, C4<0>;
+v0000000003f8af80_0 .net "A", 0 0, o0000000003ea5b38;  alias, 0 drivers
+v0000000003f8bb60_0 .net "B", 0 0, o0000000003ea5b68;  alias, 0 drivers
+L_0000000004104c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c560_0 .net8 "VGND", 0 0, L_0000000004104c70;  1 drivers, strength-aware
+L_0000000004104b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bc00_0 .net8 "VNB", 0 0, L_0000000004104b90;  1 drivers, strength-aware
+L_0000000004104c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8a940_0 .net8 "VPB", 0 0, L_0000000004104c00;  1 drivers, strength-aware
+L_00000000041262e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b200_0 .net8 "VPWR", 0 0, L_00000000041262e0;  1 drivers, strength-aware
+v0000000003f8ad00_0 .net "X", 0 0, L_000000000420cfd0;  alias, 1 drivers
+v0000000003f8bde0_0 .net "xor0_out_X", 0 0, L_000000000420c080;  1 drivers
+S_00000000028e7ea0 .scope module, "sky130_fd_sc_hd__xor2_4" "sky130_fd_sc_hd__xor2_4" 4 39436;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+o0000000003ea5e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8c100_0 .net "A", 0 0, o0000000003ea5e98;  0 drivers
+o0000000003ea5ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8cf60_0 .net "B", 0 0, o0000000003ea5ec8;  0 drivers
+L_0000000004125160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ab20_0 .net8 "VGND", 0 0, L_0000000004125160;  1 drivers, strength-aware
+L_00000000041259b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8cba0_0 .net8 "VNB", 0 0, L_00000000041259b0;  1 drivers, strength-aware
+L_0000000004124e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8cc40_0 .net8 "VPB", 0 0, L_0000000004124e50;  1 drivers, strength-aware
+L_0000000004125320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8b2a0_0 .net8 "VPWR", 0 0, L_0000000004125320;  1 drivers, strength-aware
+v0000000003f8b340_0 .net "X", 0 0, L_000000000420c0f0;  1 drivers
+S_0000000003eefb00 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39452, 4 39851 1, S_00000000028e7ea0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+L_000000000420c7f0 .functor XOR 1, o0000000003ea5ec8, o0000000003ea5e98, C4<0>, C4<0>;
+L_000000000420c0f0 .functor BUF 1, L_000000000420c7f0, C4<0>, C4<0>, C4<0>;
+v0000000003f8be80_0 .net "A", 0 0, o0000000003ea5e98;  alias, 0 drivers
+v0000000003f8d000_0 .net "B", 0 0, o0000000003ea5ec8;  alias, 0 drivers
+L_0000000004124ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bf20_0 .net8 "VGND", 0 0, L_0000000004124ec0;  1 drivers, strength-aware
+L_0000000004125a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c6a0_0 .net8 "VNB", 0 0, L_0000000004125a90;  1 drivers, strength-aware
+L_0000000004124f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8c060_0 .net8 "VPB", 0 0, L_0000000004124f30;  1 drivers, strength-aware
+L_0000000004125c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8bfc0_0 .net8 "VPWR", 0 0, L_0000000004125c50;  1 drivers, strength-aware
+v0000000003f8aa80_0 .net "X", 0 0, L_000000000420c0f0;  alias, 1 drivers
+v0000000003f8cb00_0 .net "xor0_out_X", 0 0, L_000000000420c7f0;  1 drivers
+S_00000000028e6e20 .scope module, "sky130_fd_sc_hd__xor3_1" "sky130_fd_sc_hd__xor3_1" 4 86643;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea61f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8d500_0 .net "A", 0 0, o0000000003ea61f8;  0 drivers
+o0000000003ea6228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8e180_0 .net "B", 0 0, o0000000003ea6228;  0 drivers
+o0000000003ea6258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8dbe0_0 .net "C", 0 0, o0000000003ea6258;  0 drivers
+L_0000000004125b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8e040_0 .net8 "VGND", 0 0, L_0000000004125b00;  1 drivers, strength-aware
+L_00000000041251d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8d6e0_0 .net8 "VNB", 0 0, L_00000000041251d0;  1 drivers, strength-aware
+L_00000000041255c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8eae0_0 .net8 "VPB", 0 0, L_00000000041255c0;  1 drivers, strength-aware
+L_0000000004124fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8e720_0 .net8 "VPWR", 0 0, L_0000000004124fa0;  1 drivers, strength-aware
+v0000000003f8f1c0_0 .net "X", 0 0, L_000000000420c160;  1 drivers
+S_0000000003ef1f00 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86661, 4 86525 1, S_00000000028e6e20;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420c2b0 .functor XOR 1, o0000000003ea61f8, o0000000003ea6228, o0000000003ea6258, C4<0>;
+L_000000000420c160 .functor BUF 1, L_000000000420c2b0, C4<0>, C4<0>, C4<0>;
+v0000000003f8b480_0 .net "A", 0 0, o0000000003ea61f8;  alias, 0 drivers
+v0000000003f8b520_0 .net "B", 0 0, o0000000003ea6228;  alias, 0 drivers
+v0000000003f8f120_0 .net "C", 0 0, o0000000003ea6258;  alias, 0 drivers
+L_0000000004125550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8e9a0_0 .net8 "VGND", 0 0, L_0000000004125550;  1 drivers, strength-aware
+L_0000000004126120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ea40_0 .net8 "VNB", 0 0, L_0000000004126120;  1 drivers, strength-aware
+L_0000000004125240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8eb80_0 .net8 "VPB", 0 0, L_0000000004125240;  1 drivers, strength-aware
+L_0000000004125b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8dfa0_0 .net8 "VPWR", 0 0, L_0000000004125b70;  1 drivers, strength-aware
+v0000000003f8e680_0 .net "X", 0 0, L_000000000420c160;  alias, 1 drivers
+v0000000003f8e5e0_0 .net "xor0_out_X", 0 0, L_000000000420c2b0;  1 drivers
+S_00000000028e5320 .scope module, "sky130_fd_sc_hd__xor3_2" "sky130_fd_sc_hd__xor3_2" 4 86757;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea65e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8e2c0_0 .net "A", 0 0, o0000000003ea65e8;  0 drivers
+o0000000003ea6618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8ec20_0 .net "B", 0 0, o0000000003ea6618;  0 drivers
+o0000000003ea6648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8ecc0_0 .net "C", 0 0, o0000000003ea6648;  0 drivers
+L_0000000004125e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f300_0 .net8 "VGND", 0 0, L_0000000004125e80;  1 drivers, strength-aware
+L_0000000004125fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f3a0_0 .net8 "VNB", 0 0, L_0000000004125fd0;  1 drivers, strength-aware
+L_0000000004125010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8d280_0 .net8 "VPB", 0 0, L_0000000004125010;  1 drivers, strength-aware
+L_00000000041254e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ed60_0 .net8 "VPWR", 0 0, L_00000000041254e0;  1 drivers, strength-aware
+v0000000003f8ee00_0 .net "X", 0 0, L_000000000420d0b0;  1 drivers
+S_0000000003ef4300 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86775, 4 86525 1, S_00000000028e5320;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420ccc0 .functor XOR 1, o0000000003ea65e8, o0000000003ea6618, o0000000003ea6648, C4<0>;
+L_000000000420d0b0 .functor BUF 1, L_000000000420ccc0, C4<0>, C4<0>, C4<0>;
+v0000000003f8f080_0 .net "A", 0 0, o0000000003ea65e8;  alias, 0 drivers
+v0000000003f8df00_0 .net "B", 0 0, o0000000003ea6618;  alias, 0 drivers
+v0000000003f8f260_0 .net "C", 0 0, o0000000003ea6648;  alias, 0 drivers
+L_0000000004125080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f620_0 .net8 "VGND", 0 0, L_0000000004125080;  1 drivers, strength-aware
+L_0000000004125630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8e540_0 .net8 "VNB", 0 0, L_0000000004125630;  1 drivers, strength-aware
+L_0000000004125cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f4e0_0 .net8 "VPB", 0 0, L_0000000004125cc0;  1 drivers, strength-aware
+L_0000000004125a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8dd20_0 .net8 "VPWR", 0 0, L_0000000004125a20;  1 drivers, strength-aware
+v0000000003f8e7c0_0 .net "X", 0 0, L_000000000420d0b0;  alias, 1 drivers
+v0000000003f8e0e0_0 .net "xor0_out_X", 0 0, L_000000000420ccc0;  1 drivers
+S_00000000028e5620 .scope module, "sky130_fd_sc_hd__xor3_4" "sky130_fd_sc_hd__xor3_4" 4 86871;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+o0000000003ea69d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8e360_0 .net "A", 0 0, o0000000003ea69d8;  0 drivers
+o0000000003ea6a08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8e900_0 .net "B", 0 0, o0000000003ea6a08;  0 drivers
+o0000000003ea6a38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003f8f800_0 .net "C", 0 0, o0000000003ea6a38;  0 drivers
+L_00000000041256a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8d5a0_0 .net8 "VGND", 0 0, L_00000000041256a0;  1 drivers, strength-aware
+L_0000000004125d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f8a0_0 .net8 "VNB", 0 0, L_0000000004125d30;  1 drivers, strength-aware
+L_0000000004125940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8d140_0 .net8 "VPB", 0 0, L_0000000004125940;  1 drivers, strength-aware
+L_0000000004125ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8da00_0 .net8 "VPWR", 0 0, L_0000000004125ef0;  1 drivers, strength-aware
+v0000000003f8d3c0_0 .net "X", 0 0, L_000000000420c240;  1 drivers
+S_0000000003ef4c00 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86889, 4 86525 1, S_00000000028e5620;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "X"
+    .port_info 1 /INPUT 1 "A"
+    .port_info 2 /INPUT 1 "B"
+    .port_info 3 /INPUT 1 "C"
+L_000000000420c1d0 .functor XOR 1, o0000000003ea69d8, o0000000003ea6a08, o0000000003ea6a38, C4<0>;
+L_000000000420c240 .functor BUF 1, L_000000000420c1d0, C4<0>, C4<0>, C4<0>;
+v0000000003f8f580_0 .net "A", 0 0, o0000000003ea69d8;  alias, 0 drivers
+v0000000003f8f6c0_0 .net "B", 0 0, o0000000003ea6a08;  alias, 0 drivers
+v0000000003f8e860_0 .net "C", 0 0, o0000000003ea6a38;  alias, 0 drivers
+L_0000000004125da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ddc0_0 .net8 "VGND", 0 0, L_0000000004125da0;  1 drivers, strength-aware
+L_0000000004126350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003f8ef40_0 .net8 "VNB", 0 0, L_0000000004126350;  1 drivers, strength-aware
+L_0000000004124d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8f760_0 .net8 "VPB", 0 0, L_0000000004124d70;  1 drivers, strength-aware
+L_00000000041252b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003f8db40_0 .net8 "VPWR", 0 0, L_00000000041252b0;  1 drivers, strength-aware
+v0000000003f8e220_0 .net "X", 0 0, L_000000000420c240;  alias, 1 drivers
+v0000000003f8f440_0 .net "xor0_out_X", 0 0, L_000000000420c1d0;  1 drivers
+    .scope S_000000000282f200;
+T_0 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000000003cc9af0_0, 0, 1;
+    %pushi/vec4 10, 0, 18;
+    %store/vec4 v0000000003cc8ab0_0, 0, 18;
+    %pushi/vec4 16, 0, 18;
+    %store/vec4 v0000000003cc9b90_0, 0, 18;
+    %delay 2632269824, 4656;
+    %pushi/vec4 50, 0, 18;
+    %store/vec4 v0000000003cc8ab0_0, 0, 18;
+    %pushi/vec4 34, 0, 18;
+    %store/vec4 v0000000003cc9b90_0, 0, 18;
+    %delay 2632269824, 4656;
+    %pushi/vec4 110, 0, 18;
+    %store/vec4 v0000000003cc8ab0_0, 0, 18;
+    %pushi/vec4 45, 0, 18;
+    %store/vec4 v0000000003cc9b90_0, 0, 18;
+    %delay 2632269824, 4656;
+    %pushi/vec4 2000, 0, 18;
+    %store/vec4 v0000000003cc8ab0_0, 0, 18;
+    %pushi/vec4 4535, 0, 18;
+    %store/vec4 v0000000003cc9b90_0, 0, 18;
+    %end;
+    .thread T_0;
+    .scope S_000000000282f200;
+T_1 ;
+    %vpi_call 2 22 "$dumpfile", "add_syn.vcd" {0 0 0};
+    %vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_000000000282f200 {0 0 0};
+    %vpi_call 2 24 "$monitor", "time = %2d, p = %d, q = %d, sum = %d", $time, v0000000003cc8ab0_0, v0000000003cc9b90_0, v0000000003cc9c30_0 {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+    "N/A";
+    "<interactive>";
+    "gls.v";
+    "adder.synthesis.v";
+    "sky130_fd_sc_hd.v";
diff --git a/Simulations/post_synthesis/add_syn.vcd b/Simulations/post_synthesis/add_syn.vcd
new file mode 100644
index 0000000..e6f192e
--- /dev/null
+++ b/Simulations/post_synthesis/add_syn.vcd
@@ -0,0 +1,18258 @@
+$date
+	Wed Oct 20 12:20:18 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module gls $end
+$var wire 19 ! sum [18:0] $end
+$var reg 1 " mode $end
+$var reg 18 # p [17:0] $end
+$var reg 18 $ q [17:0] $end
+$scope module u1 $end
+$var wire 1 " mode $end
+$var wire 25 % p [24:0] $end
+$var wire 25 & q [24:0] $end
+$var wire 26 ' sum [25:0] $end
+$var wire 1 ( _0505_ $end
+$var wire 1 ) _0504_ $end
+$var wire 1 * _0503_ $end
+$var wire 1 + _0502_ $end
+$var wire 1 , _0501_ $end
+$var wire 1 - _0500_ $end
+$var wire 1 . _0499_ $end
+$var wire 1 / _0498_ $end
+$var wire 1 0 _0497_ $end
+$var wire 1 1 _0496_ $end
+$var wire 1 2 _0495_ $end
+$var wire 1 3 _0494_ $end
+$var wire 1 4 _0493_ $end
+$var wire 1 5 _0492_ $end
+$var wire 1 6 _0491_ $end
+$var wire 1 7 _0490_ $end
+$var wire 1 8 _0489_ $end
+$var wire 1 9 _0488_ $end
+$var wire 1 : _0487_ $end
+$var wire 1 ; _0486_ $end
+$var wire 1 < _0485_ $end
+$var wire 1 = _0484_ $end
+$var wire 1 > _0483_ $end
+$var wire 1 ? _0482_ $end
+$var wire 1 @ _0481_ $end
+$var wire 1 A _0480_ $end
+$var wire 1 B _0479_ $end
+$var wire 1 C _0478_ $end
+$var wire 1 D _0477_ $end
+$var wire 1 E _0476_ $end
+$var wire 1 F _0475_ $end
+$var wire 1 G _0474_ $end
+$var wire 1 H _0473_ $end
+$var wire 1 I _0472_ $end
+$var wire 1 J _0471_ $end
+$var wire 1 K _0470_ $end
+$var wire 1 L _0469_ $end
+$var wire 1 M _0468_ $end
+$var wire 1 N _0467_ $end
+$var wire 1 O _0466_ $end
+$var wire 1 P _0465_ $end
+$var wire 1 Q _0464_ $end
+$var wire 1 R _0463_ $end
+$var wire 1 S _0462_ $end
+$var wire 1 T _0461_ $end
+$var wire 1 U _0460_ $end
+$var wire 1 V _0459_ $end
+$var wire 1 W _0458_ $end
+$var wire 1 X _0457_ $end
+$var wire 1 Y _0456_ $end
+$var wire 1 Z _0455_ $end
+$var wire 1 [ _0454_ $end
+$var wire 1 \ _0453_ $end
+$var wire 1 ] _0452_ $end
+$var wire 1 ^ _0451_ $end
+$var wire 1 _ _0450_ $end
+$var wire 1 ` _0449_ $end
+$var wire 1 a _0448_ $end
+$var wire 1 b _0447_ $end
+$var wire 1 c _0446_ $end
+$var wire 1 d _0445_ $end
+$var wire 1 e _0444_ $end
+$var wire 1 f _0443_ $end
+$var wire 1 g _0442_ $end
+$var wire 1 h _0441_ $end
+$var wire 1 i _0440_ $end
+$var wire 1 j _0439_ $end
+$var wire 1 k _0438_ $end
+$var wire 1 l _0437_ $end
+$var wire 1 m _0436_ $end
+$var wire 1 n _0435_ $end
+$var wire 1 o _0434_ $end
+$var wire 1 p _0433_ $end
+$var wire 1 q _0432_ $end
+$var wire 1 r _0431_ $end
+$var wire 1 s _0430_ $end
+$var wire 1 t _0429_ $end
+$var wire 1 u _0428_ $end
+$var wire 1 v _0427_ $end
+$var wire 1 w _0426_ $end
+$var wire 1 x _0425_ $end
+$var wire 1 y _0424_ $end
+$var wire 1 z _0423_ $end
+$var wire 1 { _0422_ $end
+$var wire 1 | _0421_ $end
+$var wire 1 } _0420_ $end
+$var wire 1 ~ _0419_ $end
+$var wire 1 !" _0418_ $end
+$var wire 1 "" _0417_ $end
+$var wire 1 #" _0416_ $end
+$var wire 1 $" _0415_ $end
+$var wire 1 %" _0414_ $end
+$var wire 1 &" _0413_ $end
+$var wire 1 '" _0412_ $end
+$var wire 1 (" _0411_ $end
+$var wire 1 )" _0410_ $end
+$var wire 1 *" _0409_ $end
+$var wire 1 +" _0408_ $end
+$var wire 1 ," _0407_ $end
+$var wire 1 -" _0406_ $end
+$var wire 1 ." _0405_ $end
+$var wire 1 /" _0404_ $end
+$var wire 1 0" _0403_ $end
+$var wire 1 1" _0402_ $end
+$var wire 1 2" _0401_ $end
+$var wire 1 3" _0400_ $end
+$var wire 1 4" _0399_ $end
+$var wire 1 5" _0398_ $end
+$var wire 1 6" _0397_ $end
+$var wire 1 7" _0396_ $end
+$var wire 1 8" _0395_ $end
+$var wire 1 9" _0394_ $end
+$var wire 1 :" _0393_ $end
+$var wire 1 ;" _0392_ $end
+$var wire 1 <" _0391_ $end
+$var wire 1 =" _0390_ $end
+$var wire 1 >" _0389_ $end
+$var wire 1 ?" _0388_ $end
+$var wire 1 @" _0387_ $end
+$var wire 1 A" _0386_ $end
+$var wire 1 B" _0385_ $end
+$var wire 1 C" _0384_ $end
+$var wire 1 D" _0383_ $end
+$var wire 1 E" _0382_ $end
+$var wire 1 F" _0381_ $end
+$var wire 1 G" _0380_ $end
+$var wire 1 H" _0379_ $end
+$var wire 1 I" _0378_ $end
+$var wire 1 J" _0377_ $end
+$var wire 1 K" _0376_ $end
+$var wire 1 L" _0375_ $end
+$var wire 1 M" _0374_ $end
+$var wire 1 N" _0373_ $end
+$var wire 1 O" _0372_ $end
+$var wire 1 P" _0371_ $end
+$var wire 1 Q" _0370_ $end
+$var wire 1 R" _0369_ $end
+$var wire 1 S" _0368_ $end
+$var wire 1 T" _0367_ $end
+$var wire 1 U" _0366_ $end
+$var wire 1 V" _0365_ $end
+$var wire 1 W" _0364_ $end
+$var wire 1 X" _0363_ $end
+$var wire 1 Y" _0362_ $end
+$var wire 1 Z" _0361_ $end
+$var wire 1 [" _0360_ $end
+$var wire 1 \" _0359_ $end
+$var wire 1 ]" _0358_ $end
+$var wire 1 ^" _0357_ $end
+$var wire 1 _" _0356_ $end
+$var wire 1 `" _0355_ $end
+$var wire 1 a" _0354_ $end
+$var wire 1 b" _0353_ $end
+$var wire 1 c" _0352_ $end
+$var wire 1 d" _0351_ $end
+$var wire 1 e" _0350_ $end
+$var wire 1 f" _0349_ $end
+$var wire 1 g" _0348_ $end
+$var wire 1 h" _0347_ $end
+$var wire 1 i" _0346_ $end
+$var wire 1 j" _0345_ $end
+$var wire 1 k" _0344_ $end
+$var wire 1 l" _0343_ $end
+$var wire 1 m" _0342_ $end
+$var wire 1 n" _0341_ $end
+$var wire 1 o" _0340_ $end
+$var wire 1 p" _0339_ $end
+$var wire 1 q" _0338_ $end
+$var wire 1 r" _0337_ $end
+$var wire 1 s" _0336_ $end
+$var wire 1 t" _0335_ $end
+$var wire 1 u" _0334_ $end
+$var wire 1 v" _0333_ $end
+$var wire 1 w" _0332_ $end
+$var wire 1 x" _0331_ $end
+$var wire 1 y" _0330_ $end
+$var wire 1 z" _0329_ $end
+$var wire 1 {" _0328_ $end
+$var wire 1 |" _0327_ $end
+$var wire 1 }" _0326_ $end
+$var wire 1 ~" _0325_ $end
+$var wire 1 !# _0324_ $end
+$var wire 1 "# _0323_ $end
+$var wire 1 ## _0322_ $end
+$var wire 1 $# _0321_ $end
+$var wire 1 %# _0320_ $end
+$var wire 1 &# _0319_ $end
+$var wire 1 '# _0318_ $end
+$var wire 1 (# _0317_ $end
+$var wire 1 )# _0316_ $end
+$var wire 1 *# _0315_ $end
+$var wire 1 +# _0314_ $end
+$var wire 1 ,# _0313_ $end
+$var wire 1 -# _0312_ $end
+$var wire 1 .# _0311_ $end
+$var wire 1 /# _0310_ $end
+$var wire 1 0# _0309_ $end
+$var wire 1 1# _0308_ $end
+$var wire 1 2# _0307_ $end
+$var wire 1 3# _0306_ $end
+$var wire 1 4# _0305_ $end
+$var wire 1 5# _0304_ $end
+$var wire 1 6# _0303_ $end
+$var wire 1 7# _0302_ $end
+$var wire 1 8# _0301_ $end
+$var wire 1 9# _0300_ $end
+$var wire 1 :# _0299_ $end
+$var wire 1 ;# _0298_ $end
+$var wire 1 <# _0297_ $end
+$var wire 1 =# _0296_ $end
+$var wire 1 ># _0295_ $end
+$var wire 1 ?# _0294_ $end
+$var wire 1 @# _0293_ $end
+$var wire 1 A# _0292_ $end
+$var wire 1 B# _0291_ $end
+$var wire 1 C# _0290_ $end
+$var wire 1 D# _0289_ $end
+$var wire 1 E# _0288_ $end
+$var wire 1 F# _0287_ $end
+$var wire 1 G# _0286_ $end
+$var wire 1 H# _0285_ $end
+$var wire 1 I# _0284_ $end
+$var wire 1 J# _0283_ $end
+$var wire 1 K# _0282_ $end
+$var wire 1 L# _0281_ $end
+$var wire 1 M# _0280_ $end
+$var wire 1 N# _0279_ $end
+$var wire 1 O# _0278_ $end
+$var wire 1 P# _0277_ $end
+$var wire 1 Q# _0276_ $end
+$var wire 1 R# _0275_ $end
+$var wire 1 S# _0274_ $end
+$var wire 1 T# _0273_ $end
+$var wire 1 U# _0272_ $end
+$var wire 1 V# _0271_ $end
+$var wire 1 W# _0270_ $end
+$var wire 1 X# _0269_ $end
+$var wire 1 Y# _0268_ $end
+$var wire 1 Z# _0267_ $end
+$var wire 1 [# _0266_ $end
+$var wire 1 \# _0265_ $end
+$var wire 1 ]# _0264_ $end
+$var wire 1 ^# _0263_ $end
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+$var wire 1 `# _0261_ $end
+$var wire 1 a# _0260_ $end
+$var wire 1 b# _0259_ $end
+$var wire 1 c# _0258_ $end
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+$var wire 1 e# _0256_ $end
+$var wire 1 f# _0255_ $end
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+$var wire 1 k# _0250_ $end
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+$var wire 1 q# _0244_ $end
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+$var wire 1 t# _0241_ $end
+$var wire 1 u# _0240_ $end
+$var wire 1 v# _0239_ $end
+$var wire 1 w# _0238_ $end
+$var wire 1 x# _0237_ $end
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+$var wire 1 z# _0235_ $end
+$var wire 1 {# _0234_ $end
+$var wire 1 |# _0233_ $end
+$var wire 1 }# _0232_ $end
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+$var wire 1 !$ _0230_ $end
+$var wire 1 "$ _0229_ $end
+$var wire 1 #$ _0228_ $end
+$var wire 1 $$ _0227_ $end
+$var wire 1 %$ _0226_ $end
+$var wire 1 &$ _0225_ $end
+$var wire 1 '$ _0224_ $end
+$var wire 1 ($ _0223_ $end
+$var wire 1 )$ _0222_ $end
+$var wire 1 *$ _0221_ $end
+$var wire 1 +$ _0220_ $end
+$var wire 1 ,$ _0219_ $end
+$var wire 1 -$ _0218_ $end
+$var wire 1 .$ _0217_ $end
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+$var wire 1 1$ _0214_ $end
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+$var wire 1 3$ _0212_ $end
+$var wire 1 4$ _0211_ $end
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+$var wire 1 6$ _0209_ $end
+$var wire 1 7$ _0208_ $end
+$var wire 1 8$ _0207_ $end
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+$var wire 1 ;$ _0204_ $end
+$var wire 1 <$ _0203_ $end
+$var wire 1 =$ _0202_ $end
+$var wire 1 >$ _0201_ $end
+$var wire 1 ?$ _0200_ $end
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+$var wire 1 C$ _0196_ $end
+$var wire 1 D$ _0195_ $end
+$var wire 1 E$ _0194_ $end
+$var wire 1 F$ _0193_ $end
+$var wire 1 G$ _0192_ $end
+$var wire 1 H$ _0191_ $end
+$var wire 1 I$ _0190_ $end
+$var wire 1 J$ _0189_ $end
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+$var wire 1 O$ _0184_ $end
+$var wire 1 P$ _0183_ $end
+$var wire 1 Q$ _0182_ $end
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+$var wire 1 S$ _0180_ $end
+$var wire 1 T$ _0179_ $end
+$var wire 1 U$ _0178_ $end
+$var wire 1 V$ _0177_ $end
+$var wire 1 W$ _0176_ $end
+$var wire 1 X$ _0175_ $end
+$var wire 1 Y$ _0174_ $end
+$var wire 1 Z$ _0173_ $end
+$var wire 1 [$ _0172_ $end
+$var wire 1 \$ _0171_ $end
+$var wire 1 ]$ _0170_ $end
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+$var wire 1 `$ _0167_ $end
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+$var wire 1 b$ _0165_ $end
+$var wire 1 c$ _0164_ $end
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+$var wire 1 r$ _0149_ $end
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+$var wire 1 z$ _0141_ $end
+$var wire 1 {$ _0140_ $end
+$var wire 1 |$ _0139_ $end
+$var wire 1 }$ _0138_ $end
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+$var wire 1 )% _0128_ $end
+$var wire 1 *% _0127_ $end
+$var wire 1 +% _0126_ $end
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+$var wire 1 .% _0123_ $end
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+$var wire 1 |% _0045_ $end
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+$var wire 1 #& _0040_ $end
+$var wire 1 $& _0039_ $end
+$var wire 1 %& _0038_ $end
+$var wire 1 && _0037_ $end
+$var wire 1 '& _0036_ $end
+$var wire 1 (& _0035_ $end
+$var wire 1 )& _0034_ $end
+$var wire 1 *& _0033_ $end
+$var wire 1 +& _0032_ $end
+$var wire 1 ,& _0031_ $end
+$var wire 1 -& _0030_ $end
+$var wire 1 .& _0029_ $end
+$var wire 1 /& _0028_ $end
+$var wire 1 0& _0027_ $end
+$var wire 1 1& _0026_ $end
+$var wire 1 2& _0025_ $end
+$var wire 1 3& _0024_ $end
+$var wire 1 4& _0023_ $end
+$var wire 1 5& _0022_ $end
+$var wire 1 6& _0021_ $end
+$var wire 1 7& _0020_ $end
+$var wire 1 8& _0019_ $end
+$var wire 1 9& _0018_ $end
+$var wire 1 :& _0017_ $end
+$var wire 1 ;& _0016_ $end
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+$var wire 1 =& _0014_ $end
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+$var wire 1 C& _0008_ $end
+$var wire 1 D& _0007_ $end
+$var wire 1 E& _0006_ $end
+$var wire 1 F& _0005_ $end
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+$var wire 1 H& _0003_ $end
+$var wire 1 I& _0002_ $end
+$var wire 1 J& _0001_ $end
+$var wire 1 K& _0000_ $end
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+$var wire 1 O& VPB $end
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+$var wire 1 T& VPWR $end
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+$var wire 1 U& buf0_out_X $end
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+$upscope $end
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+$var wire 1 ]& VPWR $end
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+$upscope $end
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+$var wire 1 `& VNB $end
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+$var wire 1 " A2_N $end
+$var wire 1 {& B1 $end
+$var wire 1 " B2 $end
+$var wire 1 |& VGND $end
+$var wire 1 }& VNB $end
+$var wire 1 ~& VPB $end
+$var wire 1 !' VPWR $end
+$var wire 1 s% X $end
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+$var wire 1 " A2_N $end
+$var wire 1 {& B1 $end
+$var wire 1 " B2 $end
+$var wire 1 "' VGND $end
+$var wire 1 #' VNB $end
+$var wire 1 $' VPB $end
+$var wire 1 %' VPWR $end
+$var wire 1 s% X $end
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+$var wire 1 '' nor0_out $end
+$var wire 1 (' or0_out_X $end
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+$var wire 1 *' VNB $end
+$var wire 1 +' VPB $end
+$var wire 1 ,' VPWR $end
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+$var wire 1 .' VNB $end
+$var wire 1 /' VPB $end
+$var wire 1 0' VPWR $end
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+$var wire 1 =' VPB $end
+$var wire 1 >' VPWR $end
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+$var wire 1 "( VPB $end
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+$var wire 1 )( VPWR $end
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+$var wire 1 ,( VPB $end
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+$var wire 1 ;( VPWR $end
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+$var wire 1 =( VNB $end
+$var wire 1 >( VPB $end
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+$var wire 1 T( VNB $end
+$var wire 1 U( VPB $end
+$var wire 1 V( VPWR $end
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+$var wire 1 B, VPB $end
+$var wire 1 C, VPWR $end
+$var wire 1 @% X $end
+$scope module base $end
+$var wire 1 M% A $end
+$var wire 1 A% B $end
+$var wire 1 D, VGND $end
+$var wire 1 E, VNB $end
+$var wire 1 F, VPB $end
+$var wire 1 G, VPWR $end
+$var wire 1 @% X $end
+$var wire 1 H, or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 @% A $end
+$var wire 1 I, VGND $end
+$var wire 1 J, VNB $end
+$var wire 1 K, VPB $end
+$var wire 1 L, VPWR $end
+$var wire 1 ?% Y $end
+$scope module base $end
+$var wire 1 @% A $end
+$var wire 1 M, VGND $end
+$var wire 1 N, VNB $end
+$var wire 1 O, VPB $end
+$var wire 1 P, VPWR $end
+$var wire 1 ?% Y $end
+$var wire 1 Q, not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 H% A1 $end
+$var wire 1 B% A2 $end
+$var wire 1 ?% B1 $end
+$var wire 1 R, VGND $end
+$var wire 1 S, VNB $end
+$var wire 1 T, VPB $end
+$var wire 1 U, VPWR $end
+$var wire 1 >% X $end
+$scope module base $end
+$var wire 1 H% A1 $end
+$var wire 1 B% A2 $end
+$var wire 1 ?% B1 $end
+$var wire 1 V, VGND $end
+$var wire 1 W, VNB $end
+$var wire 1 X, VPB $end
+$var wire 1 Y, VPWR $end
+$var wire 1 >% X $end
+$var wire 1 Z, and0_out_X $end
+$var wire 1 [, or0_out $end
+$upscope $end
+$upscope $end
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+$var wire 1 \, A $end
+$var wire 1 ], VGND $end
+$var wire 1 ^, VNB $end
+$var wire 1 _, VPB $end
+$var wire 1 `, VPWR $end
+$var wire 1 =% Y $end
+$scope module base $end
+$var wire 1 \, A $end
+$var wire 1 a, VGND $end
+$var wire 1 b, VNB $end
+$var wire 1 c, VPB $end
+$var wire 1 d, VPWR $end
+$var wire 1 =% Y $end
+$var wire 1 e, not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 t% A1_N $end
+$var wire 1 f, A2_N $end
+$var wire 1 t% B1 $end
+$var wire 1 g, B2 $end
+$var wire 1 h, VGND $end
+$var wire 1 i, VNB $end
+$var wire 1 j, VPB $end
+$var wire 1 k, VPWR $end
+$var wire 1 <% X $end
+$scope module base $end
+$var wire 1 t% A1_N $end
+$var wire 1 f, A2_N $end
+$var wire 1 t% B1 $end
+$var wire 1 g, B2 $end
+$var wire 1 l, VGND $end
+$var wire 1 m, VNB $end
+$var wire 1 n, VPB $end
+$var wire 1 o, VPWR $end
+$var wire 1 <% X $end
+$var wire 1 p, and0_out $end
+$var wire 1 q, nor0_out $end
+$var wire 1 r, or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 =% A1 $end
+$var wire 1 a% A2 $end
+$var wire 1 s, B1 $end
+$var wire 1 k% B2 $end
+$var wire 1 <% C1 $end
+$var wire 1 t, VGND $end
+$var wire 1 u, VNB $end
+$var wire 1 v, VPB $end
+$var wire 1 w, VPWR $end
+$var wire 1 ;% X $end
+$scope module base $end
+$var wire 1 =% A1 $end
+$var wire 1 a% A2 $end
+$var wire 1 s, B1 $end
+$var wire 1 k% B2 $end
+$var wire 1 <% C1 $end
+$var wire 1 x, VGND $end
+$var wire 1 y, VNB $end
+$var wire 1 z, VPB $end
+$var wire 1 {, VPWR $end
+$var wire 1 ;% X $end
+$var wire 1 |, and0_out $end
+$var wire 1 }, and1_out $end
+$var wire 1 ~, or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 ;% A $end
+$var wire 1 !- VGND $end
+$var wire 1 "- VNB $end
+$var wire 1 #- VPB $end
+$var wire 1 $- VPWR $end
+$var wire 1 :% Y $end
+$scope module base $end
+$var wire 1 ;% A $end
+$var wire 1 %- VGND $end
+$var wire 1 &- VNB $end
+$var wire 1 '- VPB $end
+$var wire 1 (- VPWR $end
+$var wire 1 :% Y $end
+$var wire 1 )- not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 `% A2 $end
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+$var wire 1 j% B2 $end
+$var wire 1 <% C1 $end
+$var wire 1 +- VGND $end
+$var wire 1 ,- VNB $end
+$var wire 1 -- VPB $end
+$var wire 1 .- VPWR $end
+$var wire 1 9% X $end
+$scope module base $end
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+$var wire 1 `% A2 $end
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+$var wire 1 j% B2 $end
+$var wire 1 <% C1 $end
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+$var wire 1 0- VNB $end
+$var wire 1 1- VPB $end
+$var wire 1 2- VPWR $end
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+$var wire 1 3- and0_out_X $end
+$var wire 1 4- or0_out $end
+$var wire 1 5- or1_out $end
+$upscope $end
+$upscope $end
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+$var wire 1 9% B $end
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+$var wire 1 7- VNB $end
+$var wire 1 8- VPB $end
+$var wire 1 9- VPWR $end
+$var wire 1 8% Y $end
+$scope module base $end
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+$var wire 1 9% B $end
+$var wire 1 :- VGND $end
+$var wire 1 ;- VNB $end
+$var wire 1 <- VPB $end
+$var wire 1 =- VPWR $end
+$var wire 1 8% Y $end
+$var wire 1 >- nor0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 B- VPB $end
+$var wire 1 C- VPWR $end
+$var wire 1 7% Y $end
+$scope module base $end
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+$var wire 1 E- VNB $end
+$var wire 1 F- VPB $end
+$var wire 1 G- VPWR $end
+$var wire 1 7% Y $end
+$var wire 1 H- not0_out_Y $end
+$upscope $end
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+$var wire 1 I- A2_N $end
+$var wire 1 Z% B1 $end
+$var wire 1 J- B2 $end
+$var wire 1 K- VGND $end
+$var wire 1 L- VNB $end
+$var wire 1 M- VPB $end
+$var wire 1 N- VPWR $end
+$var wire 1 6% X $end
+$scope module base $end
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+$var wire 1 I- A2_N $end
+$var wire 1 Z% B1 $end
+$var wire 1 J- B2 $end
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+$var wire 1 P- VNB $end
+$var wire 1 Q- VPB $end
+$var wire 1 R- VPWR $end
+$var wire 1 6% X $end
+$var wire 1 S- and0_out $end
+$var wire 1 T- nor0_out $end
+$var wire 1 U- or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 l% A2 $end
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+$var wire 1 b% B2 $end
+$var wire 1 6% C1 $end
+$var wire 1 W- VGND $end
+$var wire 1 X- VNB $end
+$var wire 1 Y- VPB $end
+$var wire 1 Z- VPWR $end
+$var wire 1 5% X $end
+$scope module base $end
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+$var wire 1 b% B2 $end
+$var wire 1 6% C1 $end
+$var wire 1 [- VGND $end
+$var wire 1 \- VNB $end
+$var wire 1 ]- VPB $end
+$var wire 1 ^- VPWR $end
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+$var wire 1 _- and0_out_X $end
+$var wire 1 `- or0_out $end
+$var wire 1 a- or1_out $end
+$upscope $end
+$upscope $end
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+$var wire 1 c- VNB $end
+$var wire 1 d- VPB $end
+$var wire 1 e- VPWR $end
+$var wire 1 4% Y $end
+$scope module base $end
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+$var wire 1 f- VGND $end
+$var wire 1 g- VNB $end
+$var wire 1 h- VPB $end
+$var wire 1 i- VPWR $end
+$var wire 1 4% Y $end
+$var wire 1 j- nand0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 l- VNB $end
+$var wire 1 m- VPB $end
+$var wire 1 n- VPWR $end
+$var wire 1 3% Y $end
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+$var wire 1 p- VNB $end
+$var wire 1 q- VPB $end
+$var wire 1 r- VPWR $end
+$var wire 1 3% Y $end
+$var wire 1 s- not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 k% A2 $end
+$var wire 1 t- B1 $end
+$var wire 1 `% B2 $end
+$var wire 1 D% C1 $end
+$var wire 1 u- VGND $end
+$var wire 1 v- VNB $end
+$var wire 1 w- VPB $end
+$var wire 1 x- VPWR $end
+$var wire 1 2% Y $end
+$scope module base $end
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+$var wire 1 k% A2 $end
+$var wire 1 t- B1 $end
+$var wire 1 `% B2 $end
+$var wire 1 D% C1 $end
+$var wire 1 y- VGND $end
+$var wire 1 z- VNB $end
+$var wire 1 {- VPB $end
+$var wire 1 |- VPWR $end
+$var wire 1 2% Y $end
+$var wire 1 }- and0_out $end
+$var wire 1 ~- and1_out $end
+$var wire 1 !. nor0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 C% A $end
+$var wire 1 2% B $end
+$var wire 1 ". VGND $end
+$var wire 1 #. VNB $end
+$var wire 1 $. VPB $end
+$var wire 1 %. VPWR $end
+$var wire 1 1% X $end
+$scope module base $end
+$var wire 1 C% A $end
+$var wire 1 2% B $end
+$var wire 1 &. VGND $end
+$var wire 1 '. VNB $end
+$var wire 1 (. VPB $end
+$var wire 1 ). VPWR $end
+$var wire 1 1% X $end
+$var wire 1 *. or0_out_X $end
+$upscope $end
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+$var wire 1 1% A $end
+$var wire 1 +. VGND $end
+$var wire 1 ,. VNB $end
+$var wire 1 -. VPB $end
+$var wire 1 .. VPWR $end
+$var wire 1 0% Y $end
+$scope module base $end
+$var wire 1 1% A $end
+$var wire 1 /. VGND $end
+$var wire 1 0. VNB $end
+$var wire 1 1. VPB $end
+$var wire 1 2. VPWR $end
+$var wire 1 0% Y $end
+$var wire 1 3. not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 :% A1 $end
+$var wire 1 3% A2 $end
+$var wire 1 0% B1 $end
+$var wire 1 4. VGND $end
+$var wire 1 5. VNB $end
+$var wire 1 6. VPB $end
+$var wire 1 7. VPWR $end
+$var wire 1 /% Y $end
+$scope module base $end
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+$var wire 1 3% A2 $end
+$var wire 1 0% B1 $end
+$var wire 1 8. VGND $end
+$var wire 1 9. VNB $end
+$var wire 1 :. VPB $end
+$var wire 1 ;. VPWR $end
+$var wire 1 /% Y $end
+$var wire 1 <. nand0_out_Y $end
+$var wire 1 =. or0_out $end
+$upscope $end
+$upscope $end
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+$var wire 1 /% A $end
+$var wire 1 >. VGND $end
+$var wire 1 ?. VNB $end
+$var wire 1 @. VPB $end
+$var wire 1 A. VPWR $end
+$var wire 1 .% Y $end
+$scope module base $end
+$var wire 1 /% A $end
+$var wire 1 B. VGND $end
+$var wire 1 C. VNB $end
+$var wire 1 D. VPB $end
+$var wire 1 E. VPWR $end
+$var wire 1 .% Y $end
+$var wire 1 F. not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 G. A $end
+$var wire 1 H. VGND $end
+$var wire 1 I. VNB $end
+$var wire 1 J. VPB $end
+$var wire 1 K. VPWR $end
+$var wire 1 -% Y $end
+$scope module base $end
+$var wire 1 G. A $end
+$var wire 1 L. VGND $end
+$var wire 1 M. VNB $end
+$var wire 1 N. VPB $end
+$var wire 1 O. VPWR $end
+$var wire 1 -% Y $end
+$var wire 1 P. not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 Z% A1_N $end
+$var wire 1 Q. A2_N $end
+$var wire 1 [% B1 $end
+$var wire 1 R. B2 $end
+$var wire 1 S. VGND $end
+$var wire 1 T. VNB $end
+$var wire 1 U. VPB $end
+$var wire 1 V. VPWR $end
+$var wire 1 ,% X $end
+$scope module base $end
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+$var wire 1 Q. A2_N $end
+$var wire 1 [% B1 $end
+$var wire 1 R. B2 $end
+$var wire 1 W. VGND $end
+$var wire 1 X. VNB $end
+$var wire 1 Y. VPB $end
+$var wire 1 Z. VPWR $end
+$var wire 1 ,% X $end
+$var wire 1 [. and0_out $end
+$var wire 1 \. nor0_out $end
+$var wire 1 ]. or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 m% A2 $end
+$var wire 1 -% B1 $end
+$var wire 1 b% B2 $end
+$var wire 1 ,% C1 $end
+$var wire 1 _. VGND $end
+$var wire 1 `. VNB $end
+$var wire 1 a. VPB $end
+$var wire 1 b. VPWR $end
+$var wire 1 +% X $end
+$scope module base $end
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+$var wire 1 m% A2 $end
+$var wire 1 -% B1 $end
+$var wire 1 b% B2 $end
+$var wire 1 ,% C1 $end
+$var wire 1 c. VGND $end
+$var wire 1 d. VNB $end
+$var wire 1 e. VPB $end
+$var wire 1 f. VPWR $end
+$var wire 1 +% X $end
+$var wire 1 g. and0_out_X $end
+$var wire 1 h. or0_out $end
+$var wire 1 i. or1_out $end
+$upscope $end
+$upscope $end
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+$var wire 1 l% A2 $end
+$var wire 1 j. B1 $end
+$var wire 1 b% B2 $end
+$var wire 1 ,% C1 $end
+$var wire 1 k. VGND $end
+$var wire 1 l. VNB $end
+$var wire 1 m. VPB $end
+$var wire 1 n. VPWR $end
+$var wire 1 *% Y $end
+$scope module base $end
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+$var wire 1 j. B1 $end
+$var wire 1 b% B2 $end
+$var wire 1 ,% C1 $end
+$var wire 1 o. VGND $end
+$var wire 1 p. VNB $end
+$var wire 1 q. VPB $end
+$var wire 1 r. VPWR $end
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+$var wire 1 u. nor0_out_Y $end
+$upscope $end
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+$var wire 1 *% B $end
+$var wire 1 v. VGND $end
+$var wire 1 w. VNB $end
+$var wire 1 x. VPB $end
+$var wire 1 y. VPWR $end
+$var wire 1 )% X $end
+$scope module base $end
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+$var wire 1 z. VGND $end
+$var wire 1 {. VNB $end
+$var wire 1 |. VPB $end
+$var wire 1 }. VPWR $end
+$var wire 1 )% X $end
+$var wire 1 ~. or0_out_X $end
+$upscope $end
+$upscope $end
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+$var wire 1 !/ A $end
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+$var wire 1 #/ VNB $end
+$var wire 1 $/ VPB $end
+$var wire 1 %/ VPWR $end
+$var wire 1 (% Y $end
+$scope module base $end
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+$var wire 1 &/ VGND $end
+$var wire 1 '/ VNB $end
+$var wire 1 (/ VPB $end
+$var wire 1 )/ VPWR $end
+$var wire 1 (% Y $end
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+$upscope $end
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+$var wire 1 ./ VNB $end
+$var wire 1 // VPB $end
+$var wire 1 0/ VPWR $end
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+$upscope $end
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+$var wire 1 ;/ VPB $end
+$var wire 1 </ VPWR $end
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+$upscope $end
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+$var wire 1 I/ VNB $end
+$var wire 1 J/ VPB $end
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+$upscope $end
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+$var wire 1 Q/ VPWR $end
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+$upscope $end
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+$var wire 1 [/ VPB $end
+$var wire 1 \/ VPWR $end
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+$var wire 1 _/ VPB $end
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+$var wire 1 g/ VPB $end
+$var wire 1 h/ VPWR $end
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+$upscope $end
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+$var wire 1 q/ VNB $end
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+$var wire 1 v/ VPB $end
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+$var wire 1 |/ VPB $end
+$var wire 1 }/ VPWR $end
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+$var wire 1 !0 VNB $end
+$var wire 1 "0 VPB $end
+$var wire 1 #0 VPWR $end
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+$var wire 1 $0 and0_out_X $end
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+$upscope $end
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+$var wire 1 !% A $end
+$var wire 1 ~$ B $end
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+$var wire 1 x# A $end
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+$var wire 1 5; VPWR $end
+$var wire 1 u# Y $end
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+$var wire 1 x# A $end
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+$scope module _0698_ $end
+$var wire 1 ;; A $end
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+$var wire 1 t# Y $end
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+$var wire 1 ;; A $end
+$var wire 1 @; VGND $end
+$var wire 1 A; VNB $end
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+$var wire 1 ^% A1_N $end
+$var wire 1 E; A2_N $end
+$var wire 1 ^% B1 $end
+$var wire 1 F; B2 $end
+$var wire 1 G; VGND $end
+$var wire 1 H; VNB $end
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+$var wire 1 J; VPWR $end
+$var wire 1 s# X $end
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+$var wire 1 ^% A1_N $end
+$var wire 1 E; A2_N $end
+$var wire 1 ^% B1 $end
+$var wire 1 F; B2 $end
+$var wire 1 K; VGND $end
+$var wire 1 L; VNB $end
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+$var wire 1 Q; or0_out_X $end
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+$var wire 1 R; A1 $end
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+$var wire 1 t# B1 $end
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+$var wire 1 s# C1 $end
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+$var wire 1 V; VPWR $end
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+$var wire 1 t# B1 $end
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+$var wire 1 s# C1 $end
+$var wire 1 W; VGND $end
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+$var wire 1 ]; or1_out $end
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+$var wire 1 u# A $end
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+$var wire 1 a; VPWR $end
+$var wire 1 q# X $end
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+$var wire 1 u# A $end
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+$var wire 1 q# A $end
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+$var wire 1 p# Y $end
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+$var wire 1 q# A $end
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+$var wire 1 o; not0_out_Y $end
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+$var wire 1 }# A $end
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+$var wire 1 o# X $end
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+$var wire 1 }# A $end
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+$var wire 1 {; VPB $end
+$var wire 1 |; VPWR $end
+$var wire 1 n# X $end
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+$var wire 1 w# A1 $end
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+$var wire 1 }; VGND $end
+$var wire 1 ~; VNB $end
+$var wire 1 !< VPB $end
+$var wire 1 "< VPWR $end
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+$var wire 1 #< and0_out_X $end
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+$var wire 1 '< VPB $end
+$var wire 1 (< VPWR $end
+$var wire 1 m# X $end
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+$var wire 1 !$ A $end
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+$var wire 1 )< VGND $end
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+$var wire 1 +< VPB $end
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+$var wire 1 .< B1 $end
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+$var wire 1 s# C1 $end
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+$var wire 1 1< VPB $end
+$var wire 1 2< VPWR $end
+$var wire 1 l# Y $end
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+$var wire 1 .< B1 $end
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+$var wire 1 s# C1 $end
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+$var wire 1 5< VPB $end
+$var wire 1 6< VPWR $end
+$var wire 1 l# Y $end
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+$var wire 1 8< and1_out $end
+$var wire 1 9< nor0_out_Y $end
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+$upscope $end
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+$var wire 1 r# A $end
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+$var wire 1 ;< VNB $end
+$var wire 1 << VPB $end
+$var wire 1 =< VPWR $end
+$var wire 1 k# X $end
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+$var wire 1 r# A $end
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+$var wire 1 >< VGND $end
+$var wire 1 ?< VNB $end
+$var wire 1 @< VPB $end
+$var wire 1 A< VPWR $end
+$var wire 1 k# X $end
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+$var wire 1 k# A $end
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+$var wire 1 D< VNB $end
+$var wire 1 E< VPB $end
+$var wire 1 F< VPWR $end
+$var wire 1 j# Y $end
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+$var wire 1 k# A $end
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+$var wire 1 H< VNB $end
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+$var wire 1 J< VPWR $end
+$var wire 1 j# Y $end
+$var wire 1 K< not0_out_Y $end
+$upscope $end
+$upscope $end
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+$var wire 1 L< A $end
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+$var wire 1 N< VNB $end
+$var wire 1 O< VPB $end
+$var wire 1 P< VPWR $end
+$var wire 1 i# Y $end
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+$var wire 1 L< A $end
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+$var wire 1 R< VNB $end
+$var wire 1 S< VPB $end
+$var wire 1 T< VPWR $end
+$var wire 1 i# Y $end
+$var wire 1 U< not0_out_Y $end
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+$var wire 1 x% A1_N $end
+$var wire 1 V< A2_N $end
+$var wire 1 x% B1 $end
+$var wire 1 W< B2 $end
+$var wire 1 X< VGND $end
+$var wire 1 Y< VNB $end
+$var wire 1 Z< VPB $end
+$var wire 1 [< VPWR $end
+$var wire 1 h# X $end
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+$var wire 1 x% B1 $end
+$var wire 1 W< B2 $end
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+$var wire 1 ^< VPB $end
+$var wire 1 _< VPWR $end
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+$var wire 1 a< nor0_out $end
+$var wire 1 b< or0_out_X $end
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+$var wire 1 c< B1 $end
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+$var wire 1 h# C1 $end
+$var wire 1 d< VGND $end
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+$var wire 1 f< VPB $end
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+$var wire 1 m< and1_out $end
+$var wire 1 n< or0_out_X $end
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+$var wire 1 p< VNB $end
+$var wire 1 q< VPB $end
+$var wire 1 r< VPWR $end
+$var wire 1 f# Y $end
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+$var wire 1 t< VNB $end
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+$var wire 1 w< not0_out_Y $end
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+$var wire 1 x< VGND $end
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+$var wire 1 z< VPB $end
+$var wire 1 {< VPWR $end
+$var wire 1 e# X $end
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+$var wire 1 |< VGND $end
+$var wire 1 }< VNB $end
+$var wire 1 ~< VPB $end
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+$var wire 1 e# X $end
+$var wire 1 "= or0_out_X $end
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+$var wire 1 %= VPB $end
+$var wire 1 &= VPWR $end
+$var wire 1 d# Y $end
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+$var wire 1 e# A $end
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+$var wire 1 )= VPB $end
+$var wire 1 *= VPWR $end
+$var wire 1 d# Y $end
+$var wire 1 += not0_out_Y $end
+$upscope $end
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+$var wire 1 ,= A $end
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+$var wire 1 .= VNB $end
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+$var wire 1 ,= A $end
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+$var wire 1 5= not0_out_Y $end
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+$var wire 1 6= A2_N $end
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+$var wire 1 7= B2 $end
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+$var wire 1 := VPB $end
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+$var wire 1 7= B2 $end
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+$var wire 1 >= VPB $end
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+$var wire 1 A= nor0_out $end
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+$var wire 1 b# C1 $end
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+$var wire 1 F= VPB $end
+$var wire 1 G= VPWR $end
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+$var wire 1 J= VPB $end
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+$var wire 1 L= and0_out_X $end
+$var wire 1 M= or0_out $end
+$var wire 1 N= or1_out $end
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+$var wire 1 R= VPB $end
+$var wire 1 S= VPWR $end
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+$var wire 1 V= VPB $end
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+$var wire 1 Y= or0_out $end
+$var wire 1 Z= or1_out $end
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+$var wire 1 ^= VPWR $end
+$var wire 1 _# Y $end
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+$var wire 1 `= VNB $end
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+$var wire 1 _# Y $end
+$var wire 1 c= nor0_out_Y $end
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+$var wire 1 g= VPWR $end
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+$var wire 1 r> VNB $end
+$var wire 1 s> VPB $end
+$var wire 1 t> VPWR $end
+$var wire 1 T# Y $end
+$var wire 1 u> nand0_out_Y $end
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+$var wire 1 Q[ VPWR $end
+$var wire 1 + X $end
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+$upscope $end
+$scope module _1008_ $end
+$var wire 1 0 A1 $end
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+$var wire 1 Z[ VPWR $end
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+$var wire 1 0 A1 $end
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+$var wire 1 [[ VGND $end
+$var wire 1 \[ VNB $end
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+$var wire 1 ^[ VPWR $end
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+$upscope $end
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+$var wire 1 c[ VPB $end
+$var wire 1 d[ VPWR $end
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+$var wire 1 i[ nand0_out_Y $end
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+$upscope $end
+$scope module _1010_ $end
+$var wire 1 %# A $end
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+$var wire 1 n[ VPWR $end
+$var wire 1 ) Y $end
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+$var wire 1 %# A $end
+$var wire 1 / B $end
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+$var wire 1 p[ VNB $end
+$var wire 1 q[ VPB $end
+$var wire 1 r[ VPWR $end
+$var wire 1 ) Y $end
+$var wire 1 s[ nor0_out_Y $end
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+$upscope $end
+$scope module _1011_ $end
+$var wire 1 L% A1 $end
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+$var wire 1 v[ VPB $end
+$var wire 1 w[ VPWR $end
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+$var wire 1 {[ VPWR $end
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+$var wire 1 }[ or0_out $end
+$var wire 1 ~[ or1_out $end
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+$upscope $end
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+$var wire 1 * A1_N $end
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+$var wire 1 * B1 $end
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+$var wire 1 !\ VGND $end
+$var wire 1 "\ VNB $end
+$var wire 1 #\ VPB $end
+$var wire 1 $\ VPWR $end
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+$var wire 1 * A1_N $end
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+$var wire 1 (\ VPWR $end
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+$upscope $end
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+$var wire 1 =\ VNB $end
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+$upscope $end
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+$upscope $end
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+$var wire 1 ?] VPB $end
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+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
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diff --git a/Simulations/post_synthesis/adder.synthesis.v b/Simulations/post_synthesis/adder.synthesis.v
new file mode 100644
index 0000000..1f10955
--- /dev/null
+++ b/Simulations/post_synthesis/adder.synthesis.v
@@ -0,0 +1,3488 @@
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+
+module adder(p, q, mode, sum);
+  wire _0000_;
+  wire _0001_;
+  wire _0002_;
+  wire _0003_;
+  wire _0004_;
+  wire _0005_;
+  wire _0006_;
+  wire _0007_;
+  wire _0008_;
+  wire _0009_;
+  wire _0010_;
+  wire _0011_;
+  wire _0012_;
+  wire _0013_;
+  wire _0014_;
+  wire _0015_;
+  wire _0016_;
+  wire _0017_;
+  wire _0018_;
+  wire _0019_;
+  wire _0020_;
+  wire _0021_;
+  wire _0022_;
+  wire _0023_;
+  wire _0024_;
+  wire _0025_;
+  wire _0026_;
+  wire _0027_;
+  wire _0028_;
+  wire _0029_;
+  wire _0030_;
+  wire _0031_;
+  wire _0032_;
+  wire _0033_;
+  wire _0034_;
+  wire _0035_;
+  wire _0036_;
+  wire _0037_;
+  wire _0038_;
+  wire _0039_;
+  wire _0040_;
+  wire _0041_;
+  wire _0042_;
+  wire _0043_;
+  wire _0044_;
+  wire _0045_;
+  wire _0046_;
+  wire _0047_;
+  wire _0048_;
+  wire _0049_;
+  wire _0050_;
+  wire _0051_;
+  wire _0052_;
+  wire _0053_;
+  wire _0054_;
+  wire _0055_;
+  wire _0056_;
+  wire _0057_;
+  wire _0058_;
+  wire _0059_;
+  wire _0060_;
+  wire _0061_;
+  wire _0062_;
+  wire _0063_;
+  wire _0064_;
+  wire _0065_;
+  wire _0066_;
+  wire _0067_;
+  wire _0068_;
+  wire _0069_;
+  wire _0070_;
+  wire _0071_;
+  wire _0072_;
+  wire _0073_;
+  wire _0074_;
+  wire _0075_;
+  wire _0076_;
+  wire _0077_;
+  wire _0078_;
+  wire _0079_;
+  wire _0080_;
+  wire _0081_;
+  wire _0082_;
+  wire _0083_;
+  wire _0084_;
+  wire _0085_;
+  wire _0086_;
+  wire _0087_;
+  wire _0088_;
+  wire _0089_;
+  wire _0090_;
+  wire _0091_;
+  wire _0092_;
+  wire _0093_;
+  wire _0094_;
+  wire _0095_;
+  wire _0096_;
+  wire _0097_;
+  wire _0098_;
+  wire _0099_;
+  wire _0100_;
+  wire _0101_;
+  wire _0102_;
+  wire _0103_;
+  wire _0104_;
+  wire _0105_;
+  wire _0106_;
+  wire _0107_;
+  wire _0108_;
+  wire _0109_;
+  wire _0110_;
+  wire _0111_;
+  wire _0112_;
+  wire _0113_;
+  wire _0114_;
+  wire _0115_;
+  wire _0116_;
+  wire _0117_;
+  wire _0118_;
+  wire _0119_;
+  wire _0120_;
+  wire _0121_;
+  wire _0122_;
+  wire _0123_;
+  wire _0124_;
+  wire _0125_;
+  wire _0126_;
+  wire _0127_;
+  wire _0128_;
+  wire _0129_;
+  wire _0130_;
+  wire _0131_;
+  wire _0132_;
+  wire _0133_;
+  wire _0134_;
+  wire _0135_;
+  wire _0136_;
+  wire _0137_;
+  wire _0138_;
+  wire _0139_;
+  wire _0140_;
+  wire _0141_;
+  wire _0142_;
+  wire _0143_;
+  wire _0144_;
+  wire _0145_;
+  wire _0146_;
+  wire _0147_;
+  wire _0148_;
+  wire _0149_;
+  wire _0150_;
+  wire _0151_;
+  wire _0152_;
+  wire _0153_;
+  wire _0154_;
+  wire _0155_;
+  wire _0156_;
+  wire _0157_;
+  wire _0158_;
+  wire _0159_;
+  wire _0160_;
+  wire _0161_;
+  wire _0162_;
+  wire _0163_;
+  wire _0164_;
+  wire _0165_;
+  wire _0166_;
+  wire _0167_;
+  wire _0168_;
+  wire _0169_;
+  wire _0170_;
+  wire _0171_;
+  wire _0172_;
+  wire _0173_;
+  wire _0174_;
+  wire _0175_;
+  wire _0176_;
+  wire _0177_;
+  wire _0178_;
+  wire _0179_;
+  wire _0180_;
+  wire _0181_;
+  wire _0182_;
+  wire _0183_;
+  wire _0184_;
+  wire _0185_;
+  wire _0186_;
+  wire _0187_;
+  wire _0188_;
+  wire _0189_;
+  wire _0190_;
+  wire _0191_;
+  wire _0192_;
+  wire _0193_;
+  wire _0194_;
+  wire _0195_;
+  wire _0196_;
+  wire _0197_;
+  wire _0198_;
+  wire _0199_;
+  wire _0200_;
+  wire _0201_;
+  wire _0202_;
+  wire _0203_;
+  wire _0204_;
+  wire _0205_;
+  wire _0206_;
+  wire _0207_;
+  wire _0208_;
+  wire _0209_;
+  wire _0210_;
+  wire _0211_;
+  wire _0212_;
+  wire _0213_;
+  wire _0214_;
+  wire _0215_;
+  wire _0216_;
+  wire _0217_;
+  wire _0218_;
+  wire _0219_;
+  wire _0220_;
+  wire _0221_;
+  wire _0222_;
+  wire _0223_;
+  wire _0224_;
+  wire _0225_;
+  wire _0226_;
+  wire _0227_;
+  wire _0228_;
+  wire _0229_;
+  wire _0230_;
+  wire _0231_;
+  wire _0232_;
+  wire _0233_;
+  wire _0234_;
+  wire _0235_;
+  wire _0236_;
+  wire _0237_;
+  wire _0238_;
+  wire _0239_;
+  wire _0240_;
+  wire _0241_;
+  wire _0242_;
+  wire _0243_;
+  wire _0244_;
+  wire _0245_;
+  wire _0246_;
+  wire _0247_;
+  wire _0248_;
+  wire _0249_;
+  wire _0250_;
+  wire _0251_;
+  wire _0252_;
+  wire _0253_;
+  wire _0254_;
+  wire _0255_;
+  wire _0256_;
+  wire _0257_;
+  wire _0258_;
+  wire _0259_;
+  wire _0260_;
+  wire _0261_;
+  wire _0262_;
+  wire _0263_;
+  wire _0264_;
+  wire _0265_;
+  wire _0266_;
+  wire _0267_;
+  wire _0268_;
+  wire _0269_;
+  wire _0270_;
+  wire _0271_;
+  wire _0272_;
+  wire _0273_;
+  wire _0274_;
+  wire _0275_;
+  wire _0276_;
+  wire _0277_;
+  wire _0278_;
+  wire _0279_;
+  wire _0280_;
+  wire _0281_;
+  wire _0282_;
+  wire _0283_;
+  wire _0284_;
+  wire _0285_;
+  wire _0286_;
+  wire _0287_;
+  wire _0288_;
+  wire _0289_;
+  wire _0290_;
+  wire _0291_;
+  wire _0292_;
+  wire _0293_;
+  wire _0294_;
+  wire _0295_;
+  wire _0296_;
+  wire _0297_;
+  wire _0298_;
+  wire _0299_;
+  wire _0300_;
+  wire _0301_;
+  wire _0302_;
+  wire _0303_;
+  wire _0304_;
+  wire _0305_;
+  wire _0306_;
+  wire _0307_;
+  wire _0308_;
+  wire _0309_;
+  wire _0310_;
+  wire _0311_;
+  wire _0312_;
+  wire _0313_;
+  wire _0314_;
+  wire _0315_;
+  wire _0316_;
+  wire _0317_;
+  wire _0318_;
+  wire _0319_;
+  wire _0320_;
+  wire _0321_;
+  wire _0322_;
+  wire _0323_;
+  wire _0324_;
+  wire _0325_;
+  wire _0326_;
+  wire _0327_;
+  wire _0328_;
+  wire _0329_;
+  wire _0330_;
+  wire _0331_;
+  wire _0332_;
+  wire _0333_;
+  wire _0334_;
+  wire _0335_;
+  wire _0336_;
+  wire _0337_;
+  wire _0338_;
+  wire _0339_;
+  wire _0340_;
+  wire _0341_;
+  wire _0342_;
+  wire _0343_;
+  wire _0344_;
+  wire _0345_;
+  wire _0346_;
+  wire _0347_;
+  wire _0348_;
+  wire _0349_;
+  wire _0350_;
+  wire _0351_;
+  wire _0352_;
+  wire _0353_;
+  wire _0354_;
+  wire _0355_;
+  wire _0356_;
+  wire _0357_;
+  wire _0358_;
+  wire _0359_;
+  wire _0360_;
+  wire _0361_;
+  wire _0362_;
+  wire _0363_;
+  wire _0364_;
+  wire _0365_;
+  wire _0366_;
+  wire _0367_;
+  wire _0368_;
+  wire _0369_;
+  wire _0370_;
+  wire _0371_;
+  wire _0372_;
+  wire _0373_;
+  wire _0374_;
+  wire _0375_;
+  wire _0376_;
+  wire _0377_;
+  wire _0378_;
+  wire _0379_;
+  wire _0380_;
+  wire _0381_;
+  wire _0382_;
+  wire _0383_;
+  wire _0384_;
+  wire _0385_;
+  wire _0386_;
+  wire _0387_;
+  wire _0388_;
+  wire _0389_;
+  wire _0390_;
+  wire _0391_;
+  wire _0392_;
+  wire _0393_;
+  wire _0394_;
+  wire _0395_;
+  wire _0396_;
+  wire _0397_;
+  wire _0398_;
+  wire _0399_;
+  wire _0400_;
+  wire _0401_;
+  wire _0402_;
+  wire _0403_;
+  wire _0404_;
+  wire _0405_;
+  wire _0406_;
+  wire _0407_;
+  wire _0408_;
+  wire _0409_;
+  wire _0410_;
+  wire _0411_;
+  wire _0412_;
+  wire _0413_;
+  wire _0414_;
+  wire _0415_;
+  wire _0416_;
+  wire _0417_;
+  wire _0418_;
+  wire _0419_;
+  wire _0420_;
+  wire _0421_;
+  wire _0422_;
+  wire _0423_;
+  wire _0424_;
+  wire _0425_;
+  wire _0426_;
+  wire _0427_;
+  wire _0428_;
+  wire _0429_;
+  wire _0430_;
+  wire _0431_;
+  wire _0432_;
+  wire _0433_;
+  wire _0434_;
+  wire _0435_;
+  wire _0436_;
+  wire _0437_;
+  wire _0438_;
+  wire _0439_;
+  wire _0440_;
+  wire _0441_;
+  wire _0442_;
+  wire _0443_;
+  wire _0444_;
+  wire _0445_;
+  wire _0446_;
+  wire _0447_;
+  wire _0448_;
+  wire _0449_;
+  wire _0450_;
+  wire _0451_;
+  wire _0452_;
+  wire _0453_;
+  wire _0454_;
+  wire _0455_;
+  wire _0456_;
+  wire _0457_;
+  wire _0458_;
+  wire _0459_;
+  wire _0460_;
+  wire _0461_;
+  wire _0462_;
+  wire _0463_;
+  wire _0464_;
+  wire _0465_;
+  wire _0466_;
+  wire _0467_;
+  wire _0468_;
+  wire _0469_;
+  wire _0470_;
+  wire _0471_;
+  wire _0472_;
+  wire _0473_;
+  wire _0474_;
+  wire _0475_;
+  wire _0476_;
+  wire _0477_;
+  wire _0478_;
+  wire _0479_;
+  wire _0480_;
+  wire _0481_;
+  wire _0482_;
+  wire _0483_;
+  wire _0484_;
+  wire _0485_;
+  wire _0486_;
+  wire _0487_;
+  wire _0488_;
+  wire _0489_;
+  wire _0490_;
+  wire _0491_;
+  wire _0492_;
+  wire _0493_;
+  wire _0494_;
+  wire _0495_;
+  wire _0496_;
+  wire _0497_;
+  wire _0498_;
+  wire _0499_;
+  wire _0500_;
+  wire _0501_;
+  wire _0502_;
+  wire _0503_;
+  wire _0504_;
+  wire _0505_;
+  input mode;
+  input [24:0] p;
+  input [24:0] q;
+  output [25:0] sum;
+  sky130_fd_sc_hd__buf_1 _0506_ (
+    .A(p[24]),
+    .X(_0049_)
+  );
+  sky130_fd_sc_hd__buf_1 _0507_ (
+    .A(_0049_),
+    .X(_0050_)
+  );
+  sky130_fd_sc_hd__buf_1 _0508_ (
+    .A(_0050_),
+    .X(_0051_)
+  );
+  sky130_fd_sc_hd__buf_1 _0509_ (
+    .A(_0051_),
+    .X(_0052_)
+  );
+  sky130_fd_sc_hd__buf_1 _0510_ (
+    .A(_0052_),
+    .X(_0053_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0511_ (
+    .A1_N(q[24]),
+    .A2_N(mode),
+    .B1(q[24]),
+    .B2(mode),
+    .X(_0054_)
+  );
+  sky130_fd_sc_hd__inv_2 _0512_ (
+    .A(_0054_),
+    .Y(_0055_)
+  );
+  sky130_fd_sc_hd__buf_1 _0513_ (
+    .A(_0055_),
+    .X(_0056_)
+  );
+  sky130_fd_sc_hd__buf_1 _0514_ (
+    .A(_0056_),
+    .X(_0057_)
+  );
+  sky130_fd_sc_hd__buf_1 _0515_ (
+    .A(_0057_),
+    .X(_0058_)
+  );
+  sky130_fd_sc_hd__buf_1 _0516_ (
+    .A(_0058_),
+    .X(_0059_)
+  );
+  sky130_fd_sc_hd__buf_1 _0517_ (
+    .A(_0059_),
+    .X(_0060_)
+  );
+  sky130_fd_sc_hd__buf_1 _0518_ (
+    .A(_0060_),
+    .X(_0061_)
+  );
+  sky130_fd_sc_hd__buf_1 _0519_ (
+    .A(_0061_),
+    .X(_0062_)
+  );
+  sky130_fd_sc_hd__buf_1 _0520_ (
+    .A(_0062_),
+    .X(_0063_)
+  );
+  sky130_fd_sc_hd__buf_1 _0521_ (
+    .A(_0063_),
+    .X(_0064_)
+  );
+  sky130_fd_sc_hd__inv_2 _0522_ (
+    .A(q[23]),
+    .Y(_0065_)
+  );
+  sky130_fd_sc_hd__buf_1 _0523_ (
+    .A(_0054_),
+    .X(_0066_)
+  );
+  sky130_fd_sc_hd__buf_1 _0524_ (
+    .A(_0066_),
+    .X(_0067_)
+  );
+  sky130_fd_sc_hd__buf_1 _0525_ (
+    .A(_0067_),
+    .X(_0068_)
+  );
+  sky130_fd_sc_hd__buf_1 _0526_ (
+    .A(_0068_),
+    .X(_0069_)
+  );
+  sky130_fd_sc_hd__buf_1 _0527_ (
+    .A(_0069_),
+    .X(_0070_)
+  );
+  sky130_fd_sc_hd__buf_1 _0528_ (
+    .A(_0070_),
+    .X(_0071_)
+  );
+  sky130_fd_sc_hd__buf_1 _0529_ (
+    .A(_0071_),
+    .X(_0072_)
+  );
+  sky130_fd_sc_hd__buf_1 _0530_ (
+    .A(_0072_),
+    .X(_0073_)
+  );
+  sky130_fd_sc_hd__buf_1 _0531_ (
+    .A(_0073_),
+    .X(_0074_)
+  );
+  sky130_fd_sc_hd__inv_2 _0532_ (
+    .A(_0049_),
+    .Y(_0075_)
+  );
+  sky130_fd_sc_hd__buf_1 _0533_ (
+    .A(_0075_),
+    .X(_0076_)
+  );
+  sky130_fd_sc_hd__buf_1 _0534_ (
+    .A(_0076_),
+    .X(_0077_)
+  );
+  sky130_fd_sc_hd__buf_1 _0535_ (
+    .A(_0077_),
+    .X(_0078_)
+  );
+  sky130_fd_sc_hd__buf_1 _0536_ (
+    .A(_0078_),
+    .X(_0079_)
+  );
+  sky130_fd_sc_hd__buf_1 _0537_ (
+    .A(_0079_),
+    .X(_0080_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0538_ (
+    .A1_N(_0080_),
+    .A2_N(p[23]),
+    .B1(_0080_),
+    .B2(p[23]),
+    .X(_0081_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0539_ (
+    .A1(q[23]),
+    .A2(_0064_),
+    .B1(_0065_),
+    .B2(_0074_),
+    .C1(_0081_),
+    .X(_0082_)
+  );
+  sky130_fd_sc_hd__buf_1 _0540_ (
+    .A(_0050_),
+    .X(_0083_)
+  );
+  sky130_fd_sc_hd__buf_1 _0541_ (
+    .A(_0057_),
+    .X(_0084_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0542_ (
+    .A1(_0083_),
+    .A2(_0084_),
+    .B1(_0077_),
+    .B2(_0068_),
+    .X(_0085_)
+  );
+  sky130_fd_sc_hd__buf_1 _0543_ (
+    .A(_0085_),
+    .X(_0086_)
+  );
+  sky130_fd_sc_hd__nand2_2 _0544_ (
+    .A(_0082_),
+    .B(_0086_),
+    .Y(_0087_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0545_ (
+    .A1(_0065_),
+    .A2(_0064_),
+    .B1(q[23]),
+    .B2(_0074_),
+    .C1(_0081_),
+    .Y(_0088_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0546_ (
+    .A(_0082_),
+    .B(_0088_),
+    .Y(_0089_)
+  );
+  sky130_fd_sc_hd__inv_2 _0547_ (
+    .A(q[22]),
+    .Y(_0090_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0548_ (
+    .A1_N(_0080_),
+    .A2_N(p[22]),
+    .B1(_0080_),
+    .B2(p[22]),
+    .X(_0091_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0549_ (
+    .A1(q[22]),
+    .A2(_0063_),
+    .B1(_0090_),
+    .B2(_0074_),
+    .C1(_0091_),
+    .X(_0092_)
+  );
+  sky130_fd_sc_hd__and2_2 _0550_ (
+    .A(_0089_),
+    .B(_0092_),
+    .X(_0093_)
+  );
+  sky130_fd_sc_hd__inv_2 _0551_ (
+    .A(q[21]),
+    .Y(_0094_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0552_ (
+    .A1_N(_0053_),
+    .A2_N(p[21]),
+    .B1(_0053_),
+    .B2(p[21]),
+    .X(_0095_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0553_ (
+    .A1(_0094_),
+    .A2(_0073_),
+    .B1(q[21]),
+    .B2(_0063_),
+    .C1(_0095_),
+    .X(_0096_)
+  );
+  sky130_fd_sc_hd__inv_2 _0554_ (
+    .A(_0096_),
+    .Y(_0097_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0555_ (
+    .A1(q[21]),
+    .A2(_0074_),
+    .B1(_0094_),
+    .B2(_0064_),
+    .C1(_0095_),
+    .X(_0098_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0556_ (
+    .A(_0097_),
+    .B(_0098_),
+    .Y(_0099_)
+  );
+  sky130_fd_sc_hd__inv_2 _0557_ (
+    .A(q[20]),
+    .Y(_0100_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0558_ (
+    .A1_N(_0080_),
+    .A2_N(p[20]),
+    .B1(_0079_),
+    .B2(p[20]),
+    .X(_0101_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0559_ (
+    .A1(q[20]),
+    .A2(_0062_),
+    .B1(_0100_),
+    .B2(_0072_),
+    .C1(_0101_),
+    .X(_0102_)
+  );
+  sky130_fd_sc_hd__and2_2 _0560_ (
+    .A(_0099_),
+    .B(_0102_),
+    .X(_0103_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0561_ (
+    .A1(_0090_),
+    .A2(_0064_),
+    .B1(q[22]),
+    .B2(_0074_),
+    .C1(_0091_),
+    .Y(_0104_)
+  );
+  sky130_fd_sc_hd__or2_2 _0562_ (
+    .A(_0092_),
+    .B(_0104_),
+    .X(_0105_)
+  );
+  sky130_fd_sc_hd__inv_2 _0563_ (
+    .A(_0105_),
+    .Y(_0106_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0564_ (
+    .A1(_0097_),
+    .A2(_0103_),
+    .B1(_0106_),
+    .X(_0107_)
+  );
+  sky130_fd_sc_hd__inv_2 _0565_ (
+    .A(q[19]),
+    .Y(_0108_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0566_ (
+    .A1_N(_0053_),
+    .A2_N(p[19]),
+    .B1(_0053_),
+    .B2(p[19]),
+    .X(_0109_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0567_ (
+    .A1(_0108_),
+    .A2(_0072_),
+    .B1(q[19]),
+    .B2(_0062_),
+    .C1(_0109_),
+    .X(_0110_)
+  );
+  sky130_fd_sc_hd__inv_2 _0568_ (
+    .A(_0110_),
+    .Y(_0111_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0569_ (
+    .A1(q[19]),
+    .A2(_0073_),
+    .B1(_0108_),
+    .B2(_0063_),
+    .C1(_0109_),
+    .X(_0112_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0570_ (
+    .A(_0111_),
+    .B(_0112_),
+    .Y(_0113_)
+  );
+  sky130_fd_sc_hd__inv_2 _0571_ (
+    .A(q[18]),
+    .Y(_0114_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0572_ (
+    .A1_N(_0079_),
+    .A2_N(p[18]),
+    .B1(_0079_),
+    .B2(p[18]),
+    .X(_0115_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0573_ (
+    .A1(q[18]),
+    .A2(_0061_),
+    .B1(_0114_),
+    .B2(_0071_),
+    .C1(_0115_),
+    .X(_0116_)
+  );
+  sky130_fd_sc_hd__nand2_2 _0574_ (
+    .A(_0113_),
+    .B(_0116_),
+    .Y(_0117_)
+  );
+  sky130_fd_sc_hd__inv_2 _0575_ (
+    .A(_0117_),
+    .Y(_0118_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0576_ (
+    .A1(_0100_),
+    .A2(_0062_),
+    .B1(q[20]),
+    .B2(_0073_),
+    .C1(_0101_),
+    .Y(_0119_)
+  );
+  sky130_fd_sc_hd__or2_2 _0577_ (
+    .A(_0102_),
+    .B(_0119_),
+    .X(_0120_)
+  );
+  sky130_fd_sc_hd__inv_2 _0578_ (
+    .A(_0120_),
+    .Y(_0121_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0579_ (
+    .A1(_0111_),
+    .A2(_0118_),
+    .B1(_0121_),
+    .Y(_0122_)
+  );
+  sky130_fd_sc_hd__inv_2 _0580_ (
+    .A(_0122_),
+    .Y(_0123_)
+  );
+  sky130_fd_sc_hd__inv_2 _0581_ (
+    .A(q[16]),
+    .Y(_0124_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0582_ (
+    .A1_N(_0079_),
+    .A2_N(p[16]),
+    .B1(_0078_),
+    .B2(p[16]),
+    .X(_0125_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0583_ (
+    .A1(q[16]),
+    .A2(_0060_),
+    .B1(_0124_),
+    .B2(_0071_),
+    .C1(_0125_),
+    .X(_0126_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0584_ (
+    .A1(_0124_),
+    .A2(_0061_),
+    .B1(q[16]),
+    .B2(_0071_),
+    .C1(_0125_),
+    .Y(_0127_)
+  );
+  sky130_fd_sc_hd__or2_2 _0585_ (
+    .A(_0126_),
+    .B(_0127_),
+    .X(_0128_)
+  );
+  sky130_fd_sc_hd__inv_2 _0586_ (
+    .A(q[15]),
+    .Y(_0129_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0587_ (
+    .A1_N(_0052_),
+    .A2_N(p[15]),
+    .B1(_0052_),
+    .B2(p[15]),
+    .X(_0130_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0588_ (
+    .A1(_0129_),
+    .A2(_0070_),
+    .B1(q[15]),
+    .B2(_0060_),
+    .C1(_0130_),
+    .X(_0131_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0589_ (
+    .A(_0128_),
+    .B(_0131_),
+    .Y(_0132_)
+  );
+  sky130_fd_sc_hd__inv_2 _0590_ (
+    .A(q[14]),
+    .Y(_0133_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0591_ (
+    .A1_N(_0077_),
+    .A2_N(p[14]),
+    .B1(_0077_),
+    .B2(p[14]),
+    .X(_0134_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0592_ (
+    .A1(q[14]),
+    .A2(_0058_),
+    .B1(_0133_),
+    .B2(_0068_),
+    .C1(_0134_),
+    .X(_0135_)
+  );
+  sky130_fd_sc_hd__inv_2 _0593_ (
+    .A(_0131_),
+    .Y(_0136_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0594_ (
+    .A1(q[15]),
+    .A2(_0071_),
+    .B1(_0129_),
+    .B2(_0061_),
+    .C1(_0130_),
+    .X(_0137_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0595_ (
+    .A(_0136_),
+    .B(_0137_),
+    .Y(_0138_)
+  );
+  sky130_fd_sc_hd__or2_2 _0596_ (
+    .A(_0135_),
+    .B(_0138_),
+    .X(_0139_)
+  );
+  sky130_fd_sc_hd__inv_2 _0597_ (
+    .A(_0128_),
+    .Y(_0140_)
+  );
+  sky130_fd_sc_hd__or2_2 _0598_ (
+    .A(_0140_),
+    .B(_0136_),
+    .X(_0141_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0599_ (
+    .A1(_0132_),
+    .A2(_0139_),
+    .B1(_0141_),
+    .Y(_0142_)
+  );
+  sky130_fd_sc_hd__inv_2 _0600_ (
+    .A(q[13]),
+    .Y(_0143_)
+  );
+  sky130_fd_sc_hd__buf_1 _0601_ (
+    .A(_0068_),
+    .X(_0144_)
+  );
+  sky130_fd_sc_hd__buf_1 _0602_ (
+    .A(_0058_),
+    .X(_0145_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0603_ (
+    .A1_N(_0051_),
+    .A2_N(p[13]),
+    .B1(_0051_),
+    .B2(p[13]),
+    .X(_0146_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0604_ (
+    .A1(_0143_),
+    .A2(_0144_),
+    .B1(q[13]),
+    .B2(_0145_),
+    .C1(_0146_),
+    .X(_0147_)
+  );
+  sky130_fd_sc_hd__inv_2 _0605_ (
+    .A(_0147_),
+    .Y(_0148_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0606_ (
+    .A1(q[13]),
+    .A2(_0070_),
+    .B1(_0143_),
+    .B2(_0060_),
+    .C1(_0146_),
+    .X(_0149_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0607_ (
+    .A(_0148_),
+    .B(_0149_),
+    .Y(_0150_)
+  );
+  sky130_fd_sc_hd__inv_2 _0608_ (
+    .A(q[12]),
+    .Y(_0151_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0609_ (
+    .A1_N(_0078_),
+    .A2_N(p[12]),
+    .B1(_0078_),
+    .B2(p[12]),
+    .X(_0152_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0610_ (
+    .A1(q[12]),
+    .A2(_0145_),
+    .B1(_0151_),
+    .B2(_0144_),
+    .C1(_0152_),
+    .X(_0153_)
+  );
+  sky130_fd_sc_hd__and2_2 _0611_ (
+    .A(_0150_),
+    .B(_0153_),
+    .X(_0154_)
+  );
+  sky130_fd_sc_hd__buf_1 _0612_ (
+    .A(_0084_),
+    .X(_0155_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0613_ (
+    .A1(_0133_),
+    .A2(_0155_),
+    .B1(q[14]),
+    .B2(_0069_),
+    .C1(_0134_),
+    .Y(_0156_)
+  );
+  sky130_fd_sc_hd__or2_2 _0614_ (
+    .A(_0135_),
+    .B(_0156_),
+    .X(_0157_)
+  );
+  sky130_fd_sc_hd__inv_2 _0615_ (
+    .A(_0157_),
+    .Y(_0158_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0616_ (
+    .A1(_0148_),
+    .A2(_0154_),
+    .B1(_0158_),
+    .Y(_0159_)
+  );
+  sky130_fd_sc_hd__and2_2 _0617_ (
+    .A(_0135_),
+    .B(_0138_),
+    .X(_0160_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0618_ (
+    .A1(_0136_),
+    .A2(_0160_),
+    .B1(_0140_),
+    .Y(_0161_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0619_ (
+    .A1(_0142_),
+    .A2(_0159_),
+    .B1(_0161_),
+    .X(_0162_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0620_ (
+    .A(_0121_),
+    .B(_0111_),
+    .Y(_0163_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0621_ (
+    .A(_0113_),
+    .B(_0116_),
+    .Y(_0164_)
+  );
+  sky130_fd_sc_hd__or2_2 _0622_ (
+    .A(_0120_),
+    .B(_0110_),
+    .X(_0165_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0623_ (
+    .A1(_0163_),
+    .A2(_0164_),
+    .B1(_0165_),
+    .X(_0166_)
+  );
+  sky130_fd_sc_hd__inv_2 _0624_ (
+    .A(q[17]),
+    .Y(_0167_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0625_ (
+    .A1_N(_0052_),
+    .A2_N(p[17]),
+    .B1(_0052_),
+    .B2(p[17]),
+    .X(_0168_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0626_ (
+    .A1(_0167_),
+    .A2(_0072_),
+    .B1(q[17]),
+    .B2(_0061_),
+    .C1(_0168_),
+    .X(_0169_)
+  );
+  sky130_fd_sc_hd__inv_2 _0627_ (
+    .A(_0169_),
+    .Y(_0170_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0628_ (
+    .A1(q[17]),
+    .A2(_0073_),
+    .B1(_0167_),
+    .B2(_0063_),
+    .C1(_0168_),
+    .X(_0171_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0629_ (
+    .A(_0170_),
+    .B(_0171_),
+    .Y(_0172_)
+  );
+  sky130_fd_sc_hd__and2_2 _0630_ (
+    .A(_0172_),
+    .B(_0126_),
+    .X(_0173_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0631_ (
+    .A1(_0114_),
+    .A2(_0062_),
+    .B1(q[18]),
+    .B2(_0072_),
+    .C1(_0115_),
+    .Y(_0174_)
+  );
+  sky130_fd_sc_hd__or2_2 _0632_ (
+    .A(_0116_),
+    .B(_0174_),
+    .X(_0175_)
+  );
+  sky130_fd_sc_hd__inv_2 _0633_ (
+    .A(_0175_),
+    .Y(_0176_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0634_ (
+    .A1(_0170_),
+    .A2(_0173_),
+    .B1(_0176_),
+    .Y(_0177_)
+  );
+  sky130_fd_sc_hd__or2_2 _0635_ (
+    .A(_0166_),
+    .B(_0177_),
+    .X(_0178_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0636_ (
+    .A1(_0151_),
+    .A2(_0060_),
+    .B1(q[12]),
+    .B2(_0070_),
+    .C1(_0152_),
+    .Y(_0179_)
+  );
+  sky130_fd_sc_hd__or2_2 _0637_ (
+    .A(_0153_),
+    .B(_0179_),
+    .X(_0180_)
+  );
+  sky130_fd_sc_hd__inv_2 _0638_ (
+    .A(_0180_),
+    .Y(_0181_)
+  );
+  sky130_fd_sc_hd__inv_2 _0639_ (
+    .A(q[11]),
+    .Y(_0182_)
+  );
+  sky130_fd_sc_hd__buf_1 _0640_ (
+    .A(_0066_),
+    .X(_0183_)
+  );
+  sky130_fd_sc_hd__buf_1 _0641_ (
+    .A(_0183_),
+    .X(_0184_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0642_ (
+    .A1_N(_0051_),
+    .A2_N(p[11]),
+    .B1(_0051_),
+    .B2(p[11]),
+    .X(_0185_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0643_ (
+    .A1(_0182_),
+    .A2(_0184_),
+    .B1(q[11]),
+    .B2(_0059_),
+    .C1(_0185_),
+    .X(_0186_)
+  );
+  sky130_fd_sc_hd__inv_2 _0644_ (
+    .A(_0186_),
+    .Y(_0187_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0645_ (
+    .A(_0181_),
+    .B(_0187_),
+    .Y(_0188_)
+  );
+  sky130_fd_sc_hd__inv_2 _0646_ (
+    .A(q[10]),
+    .Y(_0189_)
+  );
+  sky130_fd_sc_hd__buf_1 _0647_ (
+    .A(_0077_),
+    .X(_0190_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0648_ (
+    .A1_N(_0190_),
+    .A2_N(p[10]),
+    .B1(_0190_),
+    .B2(p[10]),
+    .X(_0191_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0649_ (
+    .A1(q[10]),
+    .A2(_0155_),
+    .B1(_0189_),
+    .B2(_0184_),
+    .C1(_0191_),
+    .X(_0192_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0650_ (
+    .A1(q[11]),
+    .A2(_0070_),
+    .B1(_0182_),
+    .B2(_0145_),
+    .C1(_0185_),
+    .X(_0193_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0651_ (
+    .A(_0187_),
+    .B(_0193_),
+    .Y(_0194_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0652_ (
+    .A(_0192_),
+    .B(_0194_),
+    .Y(_0195_)
+  );
+  sky130_fd_sc_hd__or2_2 _0653_ (
+    .A(_0180_),
+    .B(_0186_),
+    .X(_0196_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0654_ (
+    .A1(_0188_),
+    .A2(_0195_),
+    .B1(_0196_),
+    .X(_0197_)
+  );
+  sky130_fd_sc_hd__inv_2 _0655_ (
+    .A(q[9]),
+    .Y(_0198_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0656_ (
+    .A1_N(_0083_),
+    .A2_N(p[9]),
+    .B1(_0083_),
+    .B2(p[9]),
+    .X(_0199_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0657_ (
+    .A1(_0198_),
+    .A2(_0184_),
+    .B1(q[9]),
+    .B2(_0155_),
+    .C1(_0199_),
+    .X(_0200_)
+  );
+  sky130_fd_sc_hd__inv_2 _0658_ (
+    .A(_0200_),
+    .Y(_0201_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0659_ (
+    .A1(q[9]),
+    .A2(_0144_),
+    .B1(_0198_),
+    .B2(_0145_),
+    .C1(_0199_),
+    .X(_0202_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0660_ (
+    .A(_0201_),
+    .B(_0202_),
+    .Y(_0203_)
+  );
+  sky130_fd_sc_hd__inv_2 _0661_ (
+    .A(q[8]),
+    .Y(_0204_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0662_ (
+    .A1_N(_0190_),
+    .A2_N(p[8]),
+    .B1(_0190_),
+    .B2(p[8]),
+    .X(_0205_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0663_ (
+    .A1(q[8]),
+    .A2(_0155_),
+    .B1(_0204_),
+    .B2(_0184_),
+    .C1(_0205_),
+    .X(_0206_)
+  );
+  sky130_fd_sc_hd__and2_2 _0664_ (
+    .A(_0203_),
+    .B(_0206_),
+    .X(_0207_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0665_ (
+    .A1(_0189_),
+    .A2(_0059_),
+    .B1(q[10]),
+    .B2(_0069_),
+    .C1(_0191_),
+    .Y(_0208_)
+  );
+  sky130_fd_sc_hd__or2_2 _0666_ (
+    .A(_0192_),
+    .B(_0208_),
+    .X(_0209_)
+  );
+  sky130_fd_sc_hd__inv_2 _0667_ (
+    .A(_0209_),
+    .Y(_0210_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0668_ (
+    .A1(_0201_),
+    .A2(_0207_),
+    .B1(_0210_),
+    .Y(_0211_)
+  );
+  sky130_fd_sc_hd__and2_2 _0669_ (
+    .A(_0192_),
+    .B(_0194_),
+    .X(_0212_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0670_ (
+    .A1(_0187_),
+    .A2(_0212_),
+    .B1(_0181_),
+    .Y(_0213_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0671_ (
+    .A1(_0197_),
+    .A2(_0211_),
+    .B1(_0213_),
+    .Y(_0214_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0672_ (
+    .A1(_0204_),
+    .A2(_0059_),
+    .B1(q[8]),
+    .B2(_0069_),
+    .C1(_0205_),
+    .Y(_0215_)
+  );
+  sky130_fd_sc_hd__or2_2 _0673_ (
+    .A(_0206_),
+    .B(_0215_),
+    .X(_0216_)
+  );
+  sky130_fd_sc_hd__inv_2 _0674_ (
+    .A(_0216_),
+    .Y(_0217_)
+  );
+  sky130_fd_sc_hd__inv_2 _0675_ (
+    .A(q[7]),
+    .Y(_0218_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0676_ (
+    .A1_N(_0050_),
+    .A2_N(p[7]),
+    .B1(_0050_),
+    .B2(p[7]),
+    .X(_0219_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0677_ (
+    .A1(_0218_),
+    .A2(_0183_),
+    .B1(q[7]),
+    .B2(_0084_),
+    .C1(_0219_),
+    .X(_0220_)
+  );
+  sky130_fd_sc_hd__inv_2 _0678_ (
+    .A(_0220_),
+    .Y(_0221_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0679_ (
+    .A(_0217_),
+    .B(_0221_),
+    .Y(_0222_)
+  );
+  sky130_fd_sc_hd__inv_2 _0680_ (
+    .A(q[6]),
+    .Y(_0223_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0681_ (
+    .A1_N(_0078_),
+    .A2_N(p[6]),
+    .B1(_0190_),
+    .B2(p[6]),
+    .X(_0224_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0682_ (
+    .A1(q[6]),
+    .A2(_0155_),
+    .B1(_0223_),
+    .B2(_0069_),
+    .C1(_0224_),
+    .X(_0225_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0683_ (
+    .A1(q[7]),
+    .A2(_0184_),
+    .B1(_0218_),
+    .B2(_0058_),
+    .C1(_0219_),
+    .X(_0226_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0684_ (
+    .A(_0221_),
+    .B(_0226_),
+    .Y(_0227_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0685_ (
+    .A(_0225_),
+    .B(_0227_),
+    .Y(_0228_)
+  );
+  sky130_fd_sc_hd__or2_2 _0686_ (
+    .A(_0216_),
+    .B(_0220_),
+    .X(_0229_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0687_ (
+    .A1(_0222_),
+    .A2(_0228_),
+    .B1(_0229_),
+    .X(_0230_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0688_ (
+    .A1(_0223_),
+    .A2(_0059_),
+    .B1(q[6]),
+    .B2(_0144_),
+    .C1(_0224_),
+    .Y(_0231_)
+  );
+  sky130_fd_sc_hd__or2_2 _0689_ (
+    .A(_0225_),
+    .B(_0231_),
+    .X(_0232_)
+  );
+  sky130_fd_sc_hd__inv_2 _0690_ (
+    .A(_0232_),
+    .Y(_0233_)
+  );
+  sky130_fd_sc_hd__inv_2 _0691_ (
+    .A(q[5]),
+    .Y(_0234_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0692_ (
+    .A1_N(_0083_),
+    .A2_N(p[5]),
+    .B1(_0083_),
+    .B2(p[5]),
+    .X(_0235_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0693_ (
+    .A1(_0234_),
+    .A2(_0068_),
+    .B1(q[5]),
+    .B2(_0058_),
+    .C1(_0235_),
+    .X(_0236_)
+  );
+  sky130_fd_sc_hd__inv_2 _0694_ (
+    .A(_0236_),
+    .Y(_0237_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0695_ (
+    .A(_0233_),
+    .B(_0237_),
+    .Y(_0238_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0696_ (
+    .A1(q[5]),
+    .A2(_0144_),
+    .B1(_0234_),
+    .B2(_0145_),
+    .C1(_0235_),
+    .X(_0239_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0697_ (
+    .A(_0237_),
+    .B(_0239_),
+    .Y(_0240_)
+  );
+  sky130_fd_sc_hd__inv_2 _0698_ (
+    .A(q[4]),
+    .Y(_0241_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0699_ (
+    .A1_N(_0075_),
+    .A2_N(p[4]),
+    .B1(_0075_),
+    .B2(p[4]),
+    .X(_0242_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0700_ (
+    .A1(q[4]),
+    .A2(_0056_),
+    .B1(_0241_),
+    .B2(_0066_),
+    .C1(_0242_),
+    .X(_0243_)
+  );
+  sky130_fd_sc_hd__or2_2 _0701_ (
+    .A(_0240_),
+    .B(_0243_),
+    .X(_0244_)
+  );
+  sky130_fd_sc_hd__inv_2 _0702_ (
+    .A(_0244_),
+    .Y(_0245_)
+  );
+  sky130_fd_sc_hd__or2_2 _0703_ (
+    .A(_0232_),
+    .B(_0236_),
+    .X(_0246_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0704_ (
+    .A1(_0238_),
+    .A2(_0245_),
+    .B1(_0246_),
+    .X(_0247_)
+  );
+  sky130_fd_sc_hd__or2_2 _0705_ (
+    .A(_0230_),
+    .B(_0247_),
+    .X(_0248_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0706_ (
+    .A1(_0241_),
+    .A2(_0057_),
+    .B1(q[4]),
+    .B2(_0067_),
+    .C1(_0242_),
+    .Y(_0249_)
+  );
+  sky130_fd_sc_hd__or2_2 _0707_ (
+    .A(_0243_),
+    .B(_0249_),
+    .X(_0250_)
+  );
+  sky130_fd_sc_hd__inv_2 _0708_ (
+    .A(_0250_),
+    .Y(_0251_)
+  );
+  sky130_fd_sc_hd__inv_2 _0709_ (
+    .A(q[3]),
+    .Y(_0252_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0710_ (
+    .A1_N(_0049_),
+    .A2_N(p[3]),
+    .B1(_0049_),
+    .B2(p[3]),
+    .X(_0253_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0711_ (
+    .A1(_0252_),
+    .A2(_0066_),
+    .B1(q[3]),
+    .B2(_0056_),
+    .C1(_0253_),
+    .X(_0254_)
+  );
+  sky130_fd_sc_hd__inv_2 _0712_ (
+    .A(_0254_),
+    .Y(_0255_)
+  );
+  sky130_fd_sc_hd__or2_2 _0713_ (
+    .A(_0251_),
+    .B(_0255_),
+    .X(_0256_)
+  );
+  sky130_fd_sc_hd__inv_2 _0714_ (
+    .A(_0256_),
+    .Y(_0257_)
+  );
+  sky130_fd_sc_hd__inv_2 _0715_ (
+    .A(q[2]),
+    .Y(_0258_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0716_ (
+    .A1_N(_0076_),
+    .A2_N(p[2]),
+    .B1(_0075_),
+    .B2(p[2]),
+    .X(_0259_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0717_ (
+    .A1(q[2]),
+    .A2(_0056_),
+    .B1(_0258_),
+    .B2(_0067_),
+    .C1(_0259_),
+    .X(_0260_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0718_ (
+    .A1(q[3]),
+    .A2(_0183_),
+    .B1(_0252_),
+    .B2(_0084_),
+    .C1(_0253_),
+    .X(_0261_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0719_ (
+    .A(_0255_),
+    .B(_0261_),
+    .Y(_0262_)
+  );
+  sky130_fd_sc_hd__or2_2 _0720_ (
+    .A(_0260_),
+    .B(_0262_),
+    .X(_0263_)
+  );
+  sky130_fd_sc_hd__inv_2 _0721_ (
+    .A(_0263_),
+    .Y(_0264_)
+  );
+  sky130_fd_sc_hd__or2_2 _0722_ (
+    .A(_0250_),
+    .B(_0254_),
+    .X(_0265_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0723_ (
+    .A1(_0257_),
+    .A2(_0264_),
+    .B1(_0265_),
+    .X(_0266_)
+  );
+  sky130_fd_sc_hd__inv_2 _0724_ (
+    .A(q[1]),
+    .Y(_0267_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0725_ (
+    .A1_N(_0049_),
+    .A2_N(p[1]),
+    .B1(p[24]),
+    .B2(p[1]),
+    .X(_0268_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0726_ (
+    .A1(_0267_),
+    .A2(_0054_),
+    .B1(q[1]),
+    .B2(_0055_),
+    .C1(_0268_),
+    .X(_0269_)
+  );
+  sky130_fd_sc_hd__inv_2 _0727_ (
+    .A(_0269_),
+    .Y(_0270_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0728_ (
+    .A1(q[1]),
+    .A2(_0054_),
+    .B1(_0267_),
+    .B2(_0056_),
+    .C1(_0268_),
+    .X(_0271_)
+  );
+  sky130_fd_sc_hd__or2_2 _0729_ (
+    .A(_0270_),
+    .B(_0271_),
+    .X(_0272_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0730_ (
+    .A1(_0076_),
+    .A2(_0066_),
+    .B1(_0272_),
+    .Y(_0273_)
+  );
+  sky130_fd_sc_hd__inv_2 _0731_ (
+    .A(_0273_),
+    .Y(_0274_)
+  );
+  sky130_fd_sc_hd__a221oi_2 _0732_ (
+    .A1(_0258_),
+    .A2(_0057_),
+    .B1(q[2]),
+    .B2(_0067_),
+    .C1(_0259_),
+    .Y(_0275_)
+  );
+  sky130_fd_sc_hd__or2_2 _0733_ (
+    .A(_0260_),
+    .B(_0275_),
+    .X(_0276_)
+  );
+  sky130_fd_sc_hd__nand2_2 _0734_ (
+    .A(_0276_),
+    .B(_0269_),
+    .Y(_0277_)
+  );
+  sky130_fd_sc_hd__inv_2 _0735_ (
+    .A(_0277_),
+    .Y(_0278_)
+  );
+  sky130_fd_sc_hd__inv_2 _0736_ (
+    .A(q[0]),
+    .Y(_0279_)
+  );
+  sky130_fd_sc_hd__inv_2 _0737_ (
+    .A(p[0]),
+    .Y(_0280_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0738_ (
+    .A1(_0050_),
+    .A2(p[0]),
+    .B1(_0076_),
+    .B2(_0280_),
+    .X(_0281_)
+  );
+  sky130_fd_sc_hd__a221o_2 _0739_ (
+    .A1(_0279_),
+    .A2(_0057_),
+    .B1(q[0]),
+    .B2(_0183_),
+    .C1(_0281_),
+    .X(_0282_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0740_ (
+    .A1(q[0]),
+    .A2(_0084_),
+    .B1(_0279_),
+    .B2(_0183_),
+    .C1(_0281_),
+    .X(_0283_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0741_ (
+    .A1(_0085_),
+    .A2(_0282_),
+    .B1(_0283_),
+    .Y(_0284_)
+  );
+  sky130_fd_sc_hd__nor3_2 _0742_ (
+    .A(_0076_),
+    .B(_0067_),
+    .C(_0272_),
+    .Y(_0285_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0743_ (
+    .A(_0270_),
+    .B(_0285_),
+    .Y(_0286_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0744_ (
+    .A1(_0274_),
+    .A2(_0278_),
+    .A3(_0284_),
+    .B1(_0276_),
+    .B2(_0286_),
+    .X(_0287_)
+  );
+  sky130_fd_sc_hd__and2_2 _0745_ (
+    .A(_0260_),
+    .B(_0262_),
+    .X(_0288_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0746_ (
+    .A1(_0255_),
+    .A2(_0288_),
+    .B1(_0251_),
+    .Y(_0289_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0747_ (
+    .A1(_0266_),
+    .A2(_0287_),
+    .B1(_0289_),
+    .Y(_0290_)
+  );
+  sky130_fd_sc_hd__inv_2 _0748_ (
+    .A(_0290_),
+    .Y(_0291_)
+  );
+  sky130_fd_sc_hd__and2_2 _0749_ (
+    .A(_0240_),
+    .B(_0243_),
+    .X(_0292_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0750_ (
+    .A1(_0237_),
+    .A2(_0292_),
+    .B1(_0233_),
+    .Y(_0293_)
+  );
+  sky130_fd_sc_hd__and2_2 _0751_ (
+    .A(_0225_),
+    .B(_0227_),
+    .X(_0294_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0752_ (
+    .A1(_0221_),
+    .A2(_0294_),
+    .B1(_0217_),
+    .Y(_0295_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0753_ (
+    .A1(_0230_),
+    .A2(_0293_),
+    .B1(_0295_),
+    .Y(_0296_)
+  );
+  sky130_fd_sc_hd__inv_2 _0754_ (
+    .A(_0296_),
+    .Y(_0297_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0755_ (
+    .A1(_0248_),
+    .A2(_0291_),
+    .B1(_0297_),
+    .Y(_0298_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0756_ (
+    .A(_0210_),
+    .B(_0201_),
+    .Y(_0299_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0757_ (
+    .A(_0203_),
+    .B(_0206_),
+    .Y(_0300_)
+  );
+  sky130_fd_sc_hd__or2_2 _0758_ (
+    .A(_0209_),
+    .B(_0200_),
+    .X(_0301_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0759_ (
+    .A1(_0299_),
+    .A2(_0300_),
+    .B1(_0301_),
+    .X(_0302_)
+  );
+  sky130_fd_sc_hd__or2_2 _0760_ (
+    .A(_0302_),
+    .B(_0197_),
+    .X(_0303_)
+  );
+  sky130_fd_sc_hd__or2_2 _0761_ (
+    .A(_0158_),
+    .B(_0148_),
+    .X(_0304_)
+  );
+  sky130_fd_sc_hd__inv_2 _0762_ (
+    .A(_0304_),
+    .Y(_0305_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0763_ (
+    .A(_0150_),
+    .B(_0153_),
+    .Y(_0306_)
+  );
+  sky130_fd_sc_hd__or2_2 _0764_ (
+    .A(_0157_),
+    .B(_0147_),
+    .X(_0307_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0765_ (
+    .A1(_0305_),
+    .A2(_0306_),
+    .B1(_0307_),
+    .X(_0308_)
+  );
+  sky130_fd_sc_hd__or2_2 _0766_ (
+    .A(_0142_),
+    .B(_0308_),
+    .X(_0309_)
+  );
+  sky130_fd_sc_hd__and2_2 _0767_ (
+    .A(_0161_),
+    .B(_0309_),
+    .X(_0310_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0768_ (
+    .A1(_0213_),
+    .A2(_0303_),
+    .B1(_0310_),
+    .Y(_0311_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0769_ (
+    .A1(_0214_),
+    .A2(_0298_),
+    .B1(_0311_),
+    .Y(_0312_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0770_ (
+    .A(_0169_),
+    .B(_0175_),
+    .Y(_0313_)
+  );
+  sky130_fd_sc_hd__or2_2 _0771_ (
+    .A(_0172_),
+    .B(_0126_),
+    .X(_0314_)
+  );
+  sky130_fd_sc_hd__or2_2 _0772_ (
+    .A(_0170_),
+    .B(_0176_),
+    .X(_0315_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0773_ (
+    .A1(_0313_),
+    .A2(_0314_),
+    .B1(_0315_),
+    .Y(_0316_)
+  );
+  sky130_fd_sc_hd__or2_2 _0774_ (
+    .A(_0166_),
+    .B(_0316_),
+    .X(_0317_)
+  );
+  sky130_fd_sc_hd__a31oi_2 _0775_ (
+    .A1(_0162_),
+    .A2(_0178_),
+    .A3(_0312_),
+    .B1(_0317_),
+    .Y(_0318_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0776_ (
+    .A(_0105_),
+    .B(_0096_),
+    .Y(_0319_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0777_ (
+    .A(_0106_),
+    .B(_0097_),
+    .Y(_0320_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0778_ (
+    .A(_0099_),
+    .B(_0102_),
+    .Y(_0321_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0779_ (
+    .A(_0320_),
+    .B(_0321_),
+    .Y(_0322_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0780_ (
+    .A1(_0107_),
+    .A2(_0123_),
+    .A3(_0318_),
+    .B1(_0319_),
+    .B2(_0322_),
+    .X(_0323_)
+  );
+  sky130_fd_sc_hd__or2_2 _0781_ (
+    .A(_0089_),
+    .B(_0092_),
+    .X(_0324_)
+  );
+  sky130_fd_sc_hd__o221ai_2 _0782_ (
+    .A1(_0082_),
+    .A2(_0086_),
+    .B1(_0093_),
+    .B2(_0323_),
+    .C1(_0324_),
+    .Y(_0325_)
+  );
+  sky130_fd_sc_hd__o211a_2 _0783_ (
+    .A1(_0053_),
+    .A2(_0064_),
+    .B1(_0087_),
+    .C1(_0325_),
+    .X(sum[25])
+  );
+  sky130_fd_sc_hd__inv_2 _0784_ (
+    .A(sum[25]),
+    .Y(_0000_)
+  );
+  sky130_fd_sc_hd__inv_2 _0785_ (
+    .A(_0284_),
+    .Y(_0326_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0786_ (
+    .A(_0285_),
+    .B(_0274_),
+    .Y(_0327_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0787_ (
+    .A1(_0285_),
+    .A2(_0274_),
+    .A3(_0284_),
+    .B1(_0326_),
+    .B2(_0327_),
+    .X(_0001_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0788_ (
+    .A1(p[0]),
+    .A2(q[0]),
+    .B1(_0280_),
+    .B2(_0279_),
+    .X(sum[0])
+  );
+  sky130_fd_sc_hd__or2_2 _0789_ (
+    .A(_0001_),
+    .B(sum[0]),
+    .X(_0328_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0790_ (
+    .A1(_0001_),
+    .A2(sum[0]),
+    .B1_N(_0328_),
+    .Y(_0002_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0791_ (
+    .A(_0276_),
+    .B(_0269_),
+    .Y(_0329_)
+  );
+  sky130_fd_sc_hd__and2_2 _0792_ (
+    .A(_0282_),
+    .B(_0327_),
+    .X(_0330_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0793_ (
+    .A1(_0285_),
+    .A2(_0283_),
+    .B1(_0273_),
+    .Y(_0331_)
+  );
+  sky130_fd_sc_hd__a21bo_2 _0794_ (
+    .A1(_0085_),
+    .A2(_0330_),
+    .B1_N(_0331_),
+    .X(_0332_)
+  );
+  sky130_fd_sc_hd__inv_2 _0795_ (
+    .A(_0332_),
+    .Y(_0333_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0796_ (
+    .A(_0278_),
+    .B(_0329_),
+    .Y(_0334_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0797_ (
+    .A1(_0278_),
+    .A2(_0329_),
+    .A3(_0333_),
+    .B1(_0334_),
+    .B2(_0332_),
+    .X(_0003_)
+  );
+  sky130_fd_sc_hd__or2_2 _0798_ (
+    .A(_0328_),
+    .B(_0003_),
+    .X(_0335_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0799_ (
+    .A1(_0328_),
+    .A2(_0003_),
+    .B1_N(_0335_),
+    .Y(_0004_)
+  );
+  sky130_fd_sc_hd__inv_2 _0800_ (
+    .A(_0287_),
+    .Y(_0336_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0801_ (
+    .A(_0288_),
+    .B(_0264_),
+    .Y(_0337_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0802_ (
+    .A1(_0288_),
+    .A2(_0264_),
+    .A3(_0287_),
+    .B1(_0336_),
+    .B2(_0337_),
+    .X(_0005_)
+  );
+  sky130_fd_sc_hd__or2_2 _0803_ (
+    .A(_0335_),
+    .B(_0005_),
+    .X(_0338_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0804_ (
+    .A1(_0335_),
+    .A2(_0005_),
+    .B1_N(_0338_),
+    .Y(_0006_)
+  );
+  sky130_fd_sc_hd__inv_2 _0805_ (
+    .A(_0265_),
+    .Y(_0339_)
+  );
+  sky130_fd_sc_hd__or2_2 _0806_ (
+    .A(_0339_),
+    .B(_0257_),
+    .X(_0340_)
+  );
+  sky130_fd_sc_hd__inv_2 _0807_ (
+    .A(_0085_),
+    .Y(_0341_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0808_ (
+    .A1(_0288_),
+    .A2(_0277_),
+    .B1(_0263_),
+    .Y(_0342_)
+  );
+  sky130_fd_sc_hd__o21bai_2 _0809_ (
+    .A1(_0285_),
+    .A2(_0330_),
+    .B1_N(_0342_),
+    .Y(_0343_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0810_ (
+    .A1(_0260_),
+    .A2(_0329_),
+    .B1(_0262_),
+    .Y(_0344_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0811_ (
+    .A1(_0331_),
+    .A2(_0342_),
+    .B1(_0344_),
+    .X(_0345_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0812_ (
+    .A1(_0341_),
+    .A2(_0343_),
+    .B1(_0345_),
+    .Y(_0346_)
+  );
+  sky130_fd_sc_hd__inv_2 _0813_ (
+    .A(_0346_),
+    .Y(_0347_)
+  );
+  sky130_fd_sc_hd__inv_2 _0814_ (
+    .A(_0340_),
+    .Y(_0348_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0815_ (
+    .A1(_0340_),
+    .A2(_0347_),
+    .B1(_0348_),
+    .B2(_0346_),
+    .X(_0007_)
+  );
+  sky130_fd_sc_hd__or2_2 _0816_ (
+    .A(_0338_),
+    .B(_0007_),
+    .X(_0349_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0817_ (
+    .A1(_0338_),
+    .A2(_0007_),
+    .B1_N(_0349_),
+    .Y(_0008_)
+  );
+  sky130_fd_sc_hd__or2_2 _0818_ (
+    .A(_0292_),
+    .B(_0245_),
+    .X(_0350_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0819_ (
+    .A1_N(_0290_),
+    .A2_N(_0350_),
+    .B1(_0290_),
+    .B2(_0350_),
+    .X(_0009_)
+  );
+  sky130_fd_sc_hd__or2_2 _0820_ (
+    .A(_0349_),
+    .B(_0009_),
+    .X(_0351_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0821_ (
+    .A1(_0349_),
+    .A2(_0009_),
+    .B1_N(_0351_),
+    .Y(_0010_)
+  );
+  sky130_fd_sc_hd__inv_2 _0822_ (
+    .A(_0246_),
+    .Y(_0352_)
+  );
+  sky130_fd_sc_hd__or2_2 _0823_ (
+    .A(_0352_),
+    .B(_0238_),
+    .X(_0353_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0824_ (
+    .A1(_0292_),
+    .A2(_0256_),
+    .B1(_0244_),
+    .Y(_0354_)
+  );
+  sky130_fd_sc_hd__or2_2 _0825_ (
+    .A(_0342_),
+    .B(_0354_),
+    .X(_0355_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0826_ (
+    .A1(_0243_),
+    .A2(_0339_),
+    .B1(_0240_),
+    .Y(_0356_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0827_ (
+    .A1(_0344_),
+    .A2(_0354_),
+    .B1(_0333_),
+    .B2(_0355_),
+    .C1(_0356_),
+    .X(_0357_)
+  );
+  sky130_fd_sc_hd__inv_2 _0828_ (
+    .A(_0353_),
+    .Y(_0358_)
+  );
+  sky130_fd_sc_hd__inv_2 _0829_ (
+    .A(_0357_),
+    .Y(_0359_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0830_ (
+    .A1(_0353_),
+    .A2(_0357_),
+    .B1(_0358_),
+    .B2(_0359_),
+    .X(_0011_)
+  );
+  sky130_fd_sc_hd__or2_2 _0831_ (
+    .A(_0351_),
+    .B(_0011_),
+    .X(_0360_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0832_ (
+    .A1(_0351_),
+    .A2(_0011_),
+    .B1_N(_0360_),
+    .Y(_0012_)
+  );
+  sky130_fd_sc_hd__or2_2 _0833_ (
+    .A(_0247_),
+    .B(_0266_),
+    .X(_0361_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0834_ (
+    .A1(_0247_),
+    .A2(_0289_),
+    .B1(_0293_),
+    .Y(_0362_)
+  );
+  sky130_fd_sc_hd__inv_2 _0835_ (
+    .A(_0362_),
+    .Y(_0363_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0836_ (
+    .A1(_0287_),
+    .A2(_0361_),
+    .B1(_0363_),
+    .X(_0364_)
+  );
+  sky130_fd_sc_hd__or2_2 _0837_ (
+    .A(_0294_),
+    .B(_0228_),
+    .X(_0365_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0838_ (
+    .A1_N(_0364_),
+    .A2_N(_0365_),
+    .B1(_0364_),
+    .B2(_0365_),
+    .Y(_0013_)
+  );
+  sky130_fd_sc_hd__or2_2 _0839_ (
+    .A(_0360_),
+    .B(_0013_),
+    .X(_0366_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0840_ (
+    .A1(_0360_),
+    .A2(_0013_),
+    .B1_N(_0366_),
+    .Y(_0014_)
+  );
+  sky130_fd_sc_hd__inv_2 _0841_ (
+    .A(_0229_),
+    .Y(_0367_)
+  );
+  sky130_fd_sc_hd__or2_2 _0842_ (
+    .A(_0367_),
+    .B(_0222_),
+    .X(_0368_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0843_ (
+    .A1(_0225_),
+    .A2(_0352_),
+    .B1(_0227_),
+    .Y(_0369_)
+  );
+  sky130_fd_sc_hd__or2_2 _0844_ (
+    .A(_0238_),
+    .B(_0365_),
+    .X(_0370_)
+  );
+  sky130_fd_sc_hd__or2_2 _0845_ (
+    .A(_0354_),
+    .B(_0370_),
+    .X(_0371_)
+  );
+  sky130_fd_sc_hd__and2_2 _0846_ (
+    .A(_0369_),
+    .B(_0371_),
+    .X(_0372_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0847_ (
+    .A1(_0344_),
+    .A2(_0343_),
+    .B1(_0372_),
+    .Y(_0373_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0848_ (
+    .A1(_0356_),
+    .A2(_0370_),
+    .B1(_0369_),
+    .Y(_0374_)
+  );
+  sky130_fd_sc_hd__inv_2 _0849_ (
+    .A(_0374_),
+    .Y(_0375_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0850_ (
+    .A1(_0345_),
+    .A2(_0371_),
+    .B1(_0375_),
+    .Y(_0376_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0851_ (
+    .A1(_0086_),
+    .A2(_0373_),
+    .B1(_0376_),
+    .Y(_0377_)
+  );
+  sky130_fd_sc_hd__inv_2 _0852_ (
+    .A(_0368_),
+    .Y(_0378_)
+  );
+  sky130_fd_sc_hd__inv_2 _0853_ (
+    .A(_0377_),
+    .Y(_0379_)
+  );
+  sky130_fd_sc_hd__o22a_2 _0854_ (
+    .A1(_0368_),
+    .A2(_0377_),
+    .B1(_0378_),
+    .B2(_0379_),
+    .X(_0015_)
+  );
+  sky130_fd_sc_hd__or2_2 _0855_ (
+    .A(_0366_),
+    .B(_0015_),
+    .X(_0380_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0856_ (
+    .A1(_0366_),
+    .A2(_0015_),
+    .B1_N(_0380_),
+    .Y(_0016_)
+  );
+  sky130_fd_sc_hd__or2_2 _0857_ (
+    .A(_0300_),
+    .B(_0207_),
+    .X(_0381_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0858_ (
+    .A1_N(_0298_),
+    .A2_N(_0381_),
+    .B1(_0298_),
+    .B2(_0381_),
+    .X(_0017_)
+  );
+  sky130_fd_sc_hd__or2_2 _0859_ (
+    .A(_0380_),
+    .B(_0017_),
+    .X(_0382_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0860_ (
+    .A1(_0380_),
+    .A2(_0017_),
+    .B1_N(_0382_),
+    .Y(_0018_)
+  );
+  sky130_fd_sc_hd__inv_2 _0861_ (
+    .A(_0301_),
+    .Y(_0383_)
+  );
+  sky130_fd_sc_hd__or2_2 _0862_ (
+    .A(_0383_),
+    .B(_0299_),
+    .X(_0384_)
+  );
+  sky130_fd_sc_hd__or2_2 _0863_ (
+    .A(_0222_),
+    .B(_0381_),
+    .X(_0385_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0864_ (
+    .A1(_0206_),
+    .A2(_0367_),
+    .B1(_0203_),
+    .Y(_0386_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0865_ (
+    .A1(_0369_),
+    .A2(_0385_),
+    .B1(_0386_),
+    .Y(_0387_)
+  );
+  sky130_fd_sc_hd__and2b_2 _0866_ (
+    .A_N(_0294_),
+    .B(_0370_),
+    .X(_0388_)
+  );
+  sky130_fd_sc_hd__inv_2 _0867_ (
+    .A(_0387_),
+    .Y(_0389_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0868_ (
+    .A1(_0385_),
+    .A2(_0388_),
+    .B1(_0389_),
+    .Y(_0390_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0869_ (
+    .A1(_0359_),
+    .A2(_0387_),
+    .B1(_0390_),
+    .X(_0391_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0870_ (
+    .A1_N(_0384_),
+    .A2_N(_0391_),
+    .B1(_0384_),
+    .B2(_0391_),
+    .X(_0019_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0871_ (
+    .A(_0382_),
+    .B(_0019_),
+    .Y(_0392_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0872_ (
+    .A1(_0382_),
+    .A2(_0019_),
+    .B1(_0392_),
+    .Y(_0020_)
+  );
+  sky130_fd_sc_hd__or2_2 _0873_ (
+    .A(_0212_),
+    .B(_0195_),
+    .X(_0393_)
+  );
+  sky130_fd_sc_hd__or2_2 _0874_ (
+    .A(_0302_),
+    .B(_0230_),
+    .X(_0394_)
+  );
+  sky130_fd_sc_hd__and2_2 _0875_ (
+    .A(_0211_),
+    .B(_0394_),
+    .X(_0395_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0876_ (
+    .A1(_0293_),
+    .A2(_0361_),
+    .B1(_0395_),
+    .Y(_0396_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0877_ (
+    .A1(_0302_),
+    .A2(_0295_),
+    .B1(_0211_),
+    .X(_0397_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0878_ (
+    .A1(_0394_),
+    .A2(_0363_),
+    .B1(_0397_),
+    .Y(_0398_)
+  );
+  sky130_fd_sc_hd__a21o_2 _0879_ (
+    .A1(_0336_),
+    .A2(_0396_),
+    .B1(_0398_),
+    .X(_0399_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0880_ (
+    .A1_N(_0393_),
+    .A2_N(_0399_),
+    .B1(_0393_),
+    .B2(_0399_),
+    .X(_0021_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0881_ (
+    .A1_N(_0392_),
+    .A2_N(_0021_),
+    .B1(_0392_),
+    .B2(_0021_),
+    .X(_0022_)
+  );
+  sky130_fd_sc_hd__inv_2 _0882_ (
+    .A(_0196_),
+    .Y(_0400_)
+  );
+  sky130_fd_sc_hd__or2_2 _0883_ (
+    .A(_0400_),
+    .B(_0188_),
+    .X(_0401_)
+  );
+  sky130_fd_sc_hd__inv_2 _0884_ (
+    .A(_0385_),
+    .Y(_0402_)
+  );
+  sky130_fd_sc_hd__or2_2 _0885_ (
+    .A(_0299_),
+    .B(_0393_),
+    .X(_0403_)
+  );
+  sky130_fd_sc_hd__inv_2 _0886_ (
+    .A(_0403_),
+    .Y(_0404_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0887_ (
+    .A1(_0207_),
+    .A2(_0402_),
+    .B1(_0404_),
+    .Y(_0405_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0888_ (
+    .A1(_0192_),
+    .A2(_0383_),
+    .B1(_0194_),
+    .Y(_0406_)
+  );
+  sky130_fd_sc_hd__and2_2 _0889_ (
+    .A(_0405_),
+    .B(_0406_),
+    .X(_0407_)
+  );
+  sky130_fd_sc_hd__or2_2 _0890_ (
+    .A(_0372_),
+    .B(_0407_),
+    .X(_0408_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0891_ (
+    .A1(_0386_),
+    .A2(_0403_),
+    .B1(_0406_),
+    .Y(_0409_)
+  );
+  sky130_fd_sc_hd__inv_2 _0892_ (
+    .A(_0409_),
+    .Y(_0410_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0893_ (
+    .A1(_0375_),
+    .A2(_0405_),
+    .B1(_0347_),
+    .B2(_0408_),
+    .C1(_0410_),
+    .X(_0411_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0894_ (
+    .A1_N(_0401_),
+    .A2_N(_0411_),
+    .B1(_0401_),
+    .B2(_0411_),
+    .Y(_0023_)
+  );
+  sky130_fd_sc_hd__or2_2 _0895_ (
+    .A(_0017_),
+    .B(_0021_),
+    .X(_0412_)
+  );
+  sky130_fd_sc_hd__or4_2 _0896_ (
+    .A(_0015_),
+    .B(_0412_),
+    .C(_0019_),
+    .D(_0366_),
+    .X(_0413_)
+  );
+  sky130_fd_sc_hd__or2_2 _0897_ (
+    .A(_0023_),
+    .B(_0413_),
+    .X(_0414_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0898_ (
+    .A1(_0023_),
+    .A2(_0413_),
+    .B1_N(_0414_),
+    .Y(_0024_)
+  );
+  sky130_fd_sc_hd__or2_2 _0899_ (
+    .A(_0306_),
+    .B(_0154_),
+    .X(_0415_)
+  );
+  sky130_fd_sc_hd__a22o_2 _0900_ (
+    .A1(_0213_),
+    .A2(_0303_),
+    .B1(_0295_),
+    .B2(_0248_),
+    .X(_0416_)
+  );
+  sky130_fd_sc_hd__inv_2 _0901_ (
+    .A(_0214_),
+    .Y(_0417_)
+  );
+  sky130_fd_sc_hd__o221ai_2 _0902_ (
+    .A1(_0303_),
+    .A2(_0297_),
+    .B1(_0291_),
+    .B2(_0416_),
+    .C1(_0417_),
+    .Y(_0418_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0903_ (
+    .A1_N(_0415_),
+    .A2_N(_0418_),
+    .B1(_0415_),
+    .B2(_0418_),
+    .X(_0025_)
+  );
+  sky130_fd_sc_hd__or2_2 _0904_ (
+    .A(_0414_),
+    .B(_0025_),
+    .X(_0419_)
+  );
+  sky130_fd_sc_hd__a21boi_2 _0905_ (
+    .A1(_0414_),
+    .A2(_0025_),
+    .B1_N(_0419_),
+    .Y(_0026_)
+  );
+  sky130_fd_sc_hd__inv_2 _0906_ (
+    .A(_0307_),
+    .Y(_0420_)
+  );
+  sky130_fd_sc_hd__or2_2 _0907_ (
+    .A(_0420_),
+    .B(_0305_),
+    .X(_0421_)
+  );
+  sky130_fd_sc_hd__or2_2 _0908_ (
+    .A(_0188_),
+    .B(_0415_),
+    .X(_0422_)
+  );
+  sky130_fd_sc_hd__inv_2 _0909_ (
+    .A(_0422_),
+    .Y(_0423_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0910_ (
+    .A1(_0212_),
+    .A2(_0404_),
+    .B1(_0423_),
+    .Y(_0424_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0911_ (
+    .A1(_0153_),
+    .A2(_0400_),
+    .B1(_0150_),
+    .Y(_0425_)
+  );
+  sky130_fd_sc_hd__nand2_2 _0912_ (
+    .A(_0424_),
+    .B(_0425_),
+    .Y(_0426_)
+  );
+  sky130_fd_sc_hd__nand2_2 _0913_ (
+    .A(_0390_),
+    .B(_0426_),
+    .Y(_0427_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0914_ (
+    .A1(_0406_),
+    .A2(_0422_),
+    .B1(_0425_),
+    .X(_0428_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0915_ (
+    .A1(_0389_),
+    .A2(_0424_),
+    .B1(_0357_),
+    .B2(_0427_),
+    .C1(_0428_),
+    .X(_0429_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0916_ (
+    .A1_N(_0421_),
+    .A2_N(_0429_),
+    .B1(_0421_),
+    .B2(_0429_),
+    .Y(_0027_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0917_ (
+    .A(_0419_),
+    .B(_0027_),
+    .Y(_0430_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0918_ (
+    .A1(_0419_),
+    .A2(_0027_),
+    .B1(_0430_),
+    .Y(_0028_)
+  );
+  sky130_fd_sc_hd__or2b_2 _0919_ (
+    .A(_0160_),
+    .B_N(_0139_),
+    .X(_0431_)
+  );
+  sky130_fd_sc_hd__or2_2 _0920_ (
+    .A(_0308_),
+    .B(_0197_),
+    .X(_0432_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0921_ (
+    .A1(_0308_),
+    .A2(_0213_),
+    .B1(_0159_),
+    .X(_0433_)
+  );
+  sky130_fd_sc_hd__and2_2 _0922_ (
+    .A(_0159_),
+    .B(_0432_),
+    .X(_0434_)
+  );
+  sky130_fd_sc_hd__or3_2 _0923_ (
+    .A(_0395_),
+    .B(_0434_),
+    .C(_0364_),
+    .X(_0435_)
+  );
+  sky130_fd_sc_hd__o211ai_2 _0924_ (
+    .A1(_0432_),
+    .A2(_0397_),
+    .B1(_0433_),
+    .C1(_0435_),
+    .Y(_0436_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0925_ (
+    .A1_N(_0431_),
+    .A2_N(_0436_),
+    .B1(_0431_),
+    .B2(_0436_),
+    .X(_0029_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0926_ (
+    .A1_N(_0430_),
+    .A2_N(_0029_),
+    .B1(_0430_),
+    .B2(_0029_),
+    .X(_0030_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0927_ (
+    .A1(_0128_),
+    .A2(_0131_),
+    .B1(_0141_),
+    .Y(_0437_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0928_ (
+    .A1(_0160_),
+    .A2(_0304_),
+    .B1(_0139_),
+    .Y(_0438_)
+  );
+  sky130_fd_sc_hd__o21bai_2 _0929_ (
+    .A1(_0154_),
+    .A2(_0423_),
+    .B1_N(_0438_),
+    .Y(_0439_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0930_ (
+    .A1(_0135_),
+    .A2(_0420_),
+    .B1(_0138_),
+    .Y(_0440_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0931_ (
+    .A1(_0425_),
+    .A2(_0438_),
+    .B1(_0440_),
+    .X(_0441_)
+  );
+  sky130_fd_sc_hd__and2_2 _0932_ (
+    .A(_0439_),
+    .B(_0440_),
+    .X(_0442_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0933_ (
+    .A(_0407_),
+    .B(_0442_),
+    .Y(_0443_)
+  );
+  sky130_fd_sc_hd__o221ai_2 _0934_ (
+    .A1(_0086_),
+    .A2(_0376_),
+    .B1(_0374_),
+    .B2(_0373_),
+    .C1(_0443_),
+    .Y(_0444_)
+  );
+  sky130_fd_sc_hd__o211a_2 _0935_ (
+    .A1(_0410_),
+    .A2(_0439_),
+    .B1(_0441_),
+    .C1(_0444_),
+    .X(_0445_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0936_ (
+    .A1_N(_0437_),
+    .A2_N(_0445_),
+    .B1(_0437_),
+    .B2(_0445_),
+    .Y(_0031_)
+  );
+  sky130_fd_sc_hd__or2_2 _0937_ (
+    .A(_0025_),
+    .B(_0029_),
+    .X(_0446_)
+  );
+  sky130_fd_sc_hd__or4_2 _0938_ (
+    .A(_0023_),
+    .B(_0446_),
+    .C(_0027_),
+    .D(_0413_),
+    .X(_0447_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0939_ (
+    .A(_0031_),
+    .B(_0447_),
+    .Y(_0448_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0940_ (
+    .A1(_0031_),
+    .A2(_0447_),
+    .B1(_0448_),
+    .Y(_0032_)
+  );
+  sky130_fd_sc_hd__or2b_2 _0941_ (
+    .A(_0173_),
+    .B_N(_0314_),
+    .X(_0449_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0942_ (
+    .A1(_0309_),
+    .A2(_0417_),
+    .B1(_0162_),
+    .Y(_0450_)
+  );
+  sky130_fd_sc_hd__a21o_2 _0943_ (
+    .A1(_0311_),
+    .A2(_0298_),
+    .B1(_0450_),
+    .X(_0451_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0944_ (
+    .A1_N(_0449_),
+    .A2_N(_0451_),
+    .B1(_0449_),
+    .B2(_0451_),
+    .X(_0033_)
+  );
+  sky130_fd_sc_hd__inv_2 _0945_ (
+    .A(_0033_),
+    .Y(_0452_)
+  );
+  sky130_fd_sc_hd__or3_2 _0946_ (
+    .A(_0031_),
+    .B(_0033_),
+    .C(_0447_),
+    .X(_0453_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0947_ (
+    .A1(_0448_),
+    .A2(_0452_),
+    .B1(_0453_),
+    .X(_0034_)
+  );
+  sky130_fd_sc_hd__inv_2 _0948_ (
+    .A(_0315_),
+    .Y(_0454_)
+  );
+  sky130_fd_sc_hd__or2_2 _0949_ (
+    .A(_0454_),
+    .B(_0313_),
+    .X(_0455_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0950_ (
+    .A1(_0141_),
+    .A2(_0173_),
+    .B1(_0314_),
+    .Y(_0456_)
+  );
+  sky130_fd_sc_hd__inv_2 _0951_ (
+    .A(_0390_),
+    .Y(_0457_)
+  );
+  sky130_fd_sc_hd__o211a_2 _0952_ (
+    .A1(_0357_),
+    .A2(_0457_),
+    .B1(_0389_),
+    .C1(_0428_),
+    .X(_0458_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0953_ (
+    .A1(_0126_),
+    .A2(_0132_),
+    .B1(_0172_),
+    .Y(_0459_)
+  );
+  sky130_fd_sc_hd__inv_2 _0954_ (
+    .A(_0459_),
+    .Y(_0460_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0955_ (
+    .A(_0438_),
+    .B(_0456_),
+    .Y(_0461_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0956_ (
+    .A1(_0460_),
+    .A2(_0461_),
+    .B1(_0426_),
+    .Y(_0462_)
+  );
+  sky130_fd_sc_hd__o221a_2 _0957_ (
+    .A1(_0440_),
+    .A2(_0456_),
+    .B1(_0458_),
+    .B2(_0462_),
+    .C1(_0459_),
+    .X(_0463_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0958_ (
+    .A1_N(_0455_),
+    .A2_N(_0463_),
+    .B1(_0455_),
+    .B2(_0463_),
+    .Y(_0035_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0959_ (
+    .A(_0453_),
+    .B(_0035_),
+    .Y(_0464_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0960_ (
+    .A1(_0453_),
+    .A2(_0035_),
+    .B1(_0464_),
+    .Y(_0036_)
+  );
+  sky130_fd_sc_hd__or2_2 _0961_ (
+    .A(_0118_),
+    .B(_0164_),
+    .X(_0465_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0962_ (
+    .A1(_0336_),
+    .A2(_0362_),
+    .B1(_0396_),
+    .Y(_0466_)
+  );
+  sky130_fd_sc_hd__or3_2 _0963_ (
+    .A(_0316_),
+    .B(_0142_),
+    .C(_0434_),
+    .X(_0467_)
+  );
+  sky130_fd_sc_hd__a31o_2 _0964_ (
+    .A1(_0397_),
+    .A2(_0433_),
+    .A3(_0466_),
+    .B1(_0467_),
+    .X(_0468_)
+  );
+  sky130_fd_sc_hd__o211ai_2 _0965_ (
+    .A1(_0316_),
+    .A2(_0161_),
+    .B1(_0177_),
+    .C1(_0468_),
+    .Y(_0469_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0966_ (
+    .A1_N(_0465_),
+    .A2_N(_0469_),
+    .B1(_0465_),
+    .B2(_0469_),
+    .X(_0037_)
+  );
+  sky130_fd_sc_hd__inv_2 _0967_ (
+    .A(_0037_),
+    .Y(_0470_)
+  );
+  sky130_fd_sc_hd__or3_2 _0968_ (
+    .A(_0035_),
+    .B(_0037_),
+    .C(_0453_),
+    .X(_0471_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0969_ (
+    .A1(_0464_),
+    .A2(_0470_),
+    .B1(_0471_),
+    .X(_0038_)
+  );
+  sky130_fd_sc_hd__inv_2 _0970_ (
+    .A(_0165_),
+    .Y(_0472_)
+  );
+  sky130_fd_sc_hd__or2_2 _0971_ (
+    .A(_0472_),
+    .B(_0163_),
+    .X(_0473_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0972_ (
+    .A1(_0164_),
+    .A2(_0454_),
+    .B1(_0117_),
+    .X(_0474_)
+  );
+  sky130_fd_sc_hd__or2_2 _0973_ (
+    .A(_0456_),
+    .B(_0474_),
+    .X(_0475_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0974_ (
+    .A(_0346_),
+    .B(_0374_),
+    .Y(_0476_)
+  );
+  sky130_fd_sc_hd__o211a_2 _0975_ (
+    .A1(_0408_),
+    .A2(_0476_),
+    .B1(_0410_),
+    .C1(_0441_),
+    .X(_0477_)
+  );
+  sky130_fd_sc_hd__or2_2 _0976_ (
+    .A(_0459_),
+    .B(_0474_),
+    .X(_0478_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0977_ (
+    .A1(_0116_),
+    .A2(_0313_),
+    .B1(_0113_),
+    .Y(_0479_)
+  );
+  sky130_fd_sc_hd__o311a_2 _0978_ (
+    .A1(_0442_),
+    .A2(_0475_),
+    .A3(_0477_),
+    .B1(_0478_),
+    .C1(_0479_),
+    .X(_0480_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _0979_ (
+    .A1_N(_0473_),
+    .A2_N(_0480_),
+    .B1(_0473_),
+    .B2(_0480_),
+    .Y(_0039_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0980_ (
+    .A(_0471_),
+    .B(_0039_),
+    .Y(_0481_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _0981_ (
+    .A1(_0471_),
+    .A2(_0039_),
+    .B1(_0481_),
+    .Y(_0040_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0982_ (
+    .A(_0321_),
+    .B(_0103_),
+    .Y(_0482_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0983_ (
+    .A(_0296_),
+    .B(_0290_),
+    .Y(_0483_)
+  );
+  sky130_fd_sc_hd__o211a_2 _0984_ (
+    .A1(_0416_),
+    .A2(_0483_),
+    .B1(_0417_),
+    .C1(_0162_),
+    .X(_0484_)
+  );
+  sky130_fd_sc_hd__o311a_2 _0985_ (
+    .A1(_0317_),
+    .A2(_0310_),
+    .A3(_0484_),
+    .B1(_0122_),
+    .C1(_0178_),
+    .X(_0485_)
+  );
+  sky130_fd_sc_hd__o2bb2a_2 _0986_ (
+    .A1_N(_0482_),
+    .A2_N(_0485_),
+    .B1(_0482_),
+    .B2(_0485_),
+    .X(_0486_)
+  );
+  sky130_fd_sc_hd__inv_2 _0987_ (
+    .A(_0486_),
+    .Y(_0041_)
+  );
+  sky130_fd_sc_hd__or3_2 _0988_ (
+    .A(_0039_),
+    .B(_0041_),
+    .C(_0471_),
+    .X(_0487_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0989_ (
+    .A1(_0481_),
+    .A2(_0486_),
+    .B1(_0487_),
+    .X(_0042_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0990_ (
+    .A(_0319_),
+    .B(_0320_),
+    .Y(_0488_)
+  );
+  sky130_fd_sc_hd__inv_2 _0991_ (
+    .A(_0479_),
+    .Y(_0489_)
+  );
+  sky130_fd_sc_hd__o21a_2 _0992_ (
+    .A1(_0102_),
+    .A2(_0472_),
+    .B1(_0099_),
+    .X(_0490_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _0993_ (
+    .A1(_0379_),
+    .A2(_0409_),
+    .B1(_0443_),
+    .Y(_0491_)
+  );
+  sky130_fd_sc_hd__a31oi_2 _0994_ (
+    .A1(_0441_),
+    .A2(_0478_),
+    .A3(_0491_),
+    .B1(_0475_),
+    .Y(_0492_)
+  );
+  sky130_fd_sc_hd__nor2_2 _0995_ (
+    .A(_0321_),
+    .B(_0163_),
+    .Y(_0493_)
+  );
+  sky130_fd_sc_hd__o32a_2 _0996_ (
+    .A1(_0489_),
+    .A2(_0490_),
+    .A3(_0492_),
+    .B1(_0103_),
+    .B2(_0493_),
+    .X(_0494_)
+  );
+  sky130_fd_sc_hd__inv_2 _0997_ (
+    .A(_0494_),
+    .Y(_0495_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _0998_ (
+    .A1_N(_0488_),
+    .A2_N(_0495_),
+    .B1(_0488_),
+    .B2(_0495_),
+    .X(_0043_)
+  );
+  sky130_fd_sc_hd__or2_2 _0999_ (
+    .A(_0487_),
+    .B(_0043_),
+    .X(_0496_)
+  );
+  sky130_fd_sc_hd__inv_2 _1000_ (
+    .A(_0496_),
+    .Y(_0497_)
+  );
+  sky130_fd_sc_hd__a21oi_2 _1001_ (
+    .A1(_0487_),
+    .A2(_0043_),
+    .B1(_0497_),
+    .Y(_0044_)
+  );
+  sky130_fd_sc_hd__inv_2 _1002_ (
+    .A(_0324_),
+    .Y(_0498_)
+  );
+  sky130_fd_sc_hd__inv_2 _1003_ (
+    .A(_0323_),
+    .Y(_0499_)
+  );
+  sky130_fd_sc_hd__nor2_2 _1004_ (
+    .A(_0093_),
+    .B(_0498_),
+    .Y(_0500_)
+  );
+  sky130_fd_sc_hd__o32a_2 _1005_ (
+    .A1(_0093_),
+    .A2(_0498_),
+    .A3(_0323_),
+    .B1(_0499_),
+    .B2(_0500_),
+    .X(_0501_)
+  );
+  sky130_fd_sc_hd__inv_2 _1006_ (
+    .A(_0501_),
+    .Y(_0045_)
+  );
+  sky130_fd_sc_hd__or2_2 _1007_ (
+    .A(_0496_),
+    .B(_0045_),
+    .X(_0502_)
+  );
+  sky130_fd_sc_hd__o21a_2 _1008_ (
+    .A1(_0497_),
+    .A2(_0501_),
+    .B1(_0502_),
+    .X(_0046_)
+  );
+  sky130_fd_sc_hd__o21ai_2 _1009_ (
+    .A1(_0082_),
+    .A2(_0086_),
+    .B1(_0087_),
+    .Y(_0503_)
+  );
+  sky130_fd_sc_hd__nor2_2 _1010_ (
+    .A(_0320_),
+    .B(_0498_),
+    .Y(_0504_)
+  );
+  sky130_fd_sc_hd__o32a_2 _1011_ (
+    .A1(_0093_),
+    .A2(_0319_),
+    .A3(_0494_),
+    .B1(_0093_),
+    .B2(_0504_),
+    .X(_0505_)
+  );
+  sky130_fd_sc_hd__a2bb2o_2 _1012_ (
+    .A1_N(_0503_),
+    .A2_N(_0505_),
+    .B1(_0503_),
+    .B2(_0505_),
+    .X(_0047_)
+  );
+  sky130_fd_sc_hd__a2bb2oi_2 _1013_ (
+    .A1_N(_0502_),
+    .A2_N(_0047_),
+    .B1(_0502_),
+    .B2(_0047_),
+    .Y(_0048_)
+  );
+  sky130_fd_sc_hd__mux2_1 _1014_ (
+    .A0(_0002_),
+    .A1(_0001_),
+    .S(_0000_),
+    .X(sum[1])
+  );
+  sky130_fd_sc_hd__mux2_1 _1015_ (
+    .A0(_0004_),
+    .A1(_0003_),
+    .S(_0000_),
+    .X(sum[2])
+  );
+  sky130_fd_sc_hd__mux2_1 _1016_ (
+    .A0(_0006_),
+    .A1(_0005_),
+    .S(_0000_),
+    .X(sum[3])
+  );
+  sky130_fd_sc_hd__mux2_1 _1017_ (
+    .A0(_0008_),
+    .A1(_0007_),
+    .S(_0000_),
+    .X(sum[4])
+  );
+  sky130_fd_sc_hd__mux2_1 _1018_ (
+    .A0(_0010_),
+    .A1(_0009_),
+    .S(_0000_),
+    .X(sum[5])
+  );
+  sky130_fd_sc_hd__mux2_1 _1019_ (
+    .A0(_0012_),
+    .A1(_0011_),
+    .S(_0000_),
+    .X(sum[6])
+  );
+  sky130_fd_sc_hd__mux2_1 _1020_ (
+    .A0(_0014_),
+    .A1(_0013_),
+    .S(_0000_),
+    .X(sum[7])
+  );
+  sky130_fd_sc_hd__mux2_1 _1021_ (
+    .A0(_0016_),
+    .A1(_0015_),
+    .S(_0000_),
+    .X(sum[8])
+  );
+  sky130_fd_sc_hd__mux2_1 _1022_ (
+    .A0(_0018_),
+    .A1(_0017_),
+    .S(_0000_),
+    .X(sum[9])
+  );
+  sky130_fd_sc_hd__mux2_1 _1023_ (
+    .A0(_0020_),
+    .A1(_0019_),
+    .S(_0000_),
+    .X(sum[10])
+  );
+  sky130_fd_sc_hd__mux2_1 _1024_ (
+    .A0(_0022_),
+    .A1(_0021_),
+    .S(_0000_),
+    .X(sum[11])
+  );
+  sky130_fd_sc_hd__mux2_1 _1025_ (
+    .A0(_0024_),
+    .A1(_0023_),
+    .S(_0000_),
+    .X(sum[12])
+  );
+  sky130_fd_sc_hd__mux2_1 _1026_ (
+    .A0(_0026_),
+    .A1(_0025_),
+    .S(_0000_),
+    .X(sum[13])
+  );
+  sky130_fd_sc_hd__mux2_1 _1027_ (
+    .A0(_0028_),
+    .A1(_0027_),
+    .S(_0000_),
+    .X(sum[14])
+  );
+  sky130_fd_sc_hd__mux2_1 _1028_ (
+    .A0(_0030_),
+    .A1(_0029_),
+    .S(_0000_),
+    .X(sum[15])
+  );
+  sky130_fd_sc_hd__mux2_1 _1029_ (
+    .A0(_0032_),
+    .A1(_0031_),
+    .S(_0000_),
+    .X(sum[16])
+  );
+  sky130_fd_sc_hd__mux2_1 _1030_ (
+    .A0(_0034_),
+    .A1(_0033_),
+    .S(_0000_),
+    .X(sum[17])
+  );
+  sky130_fd_sc_hd__mux2_1 _1031_ (
+    .A0(_0036_),
+    .A1(_0035_),
+    .S(_0000_),
+    .X(sum[18])
+  );
+  sky130_fd_sc_hd__mux2_1 _1032_ (
+    .A0(_0038_),
+    .A1(_0037_),
+    .S(_0000_),
+    .X(sum[19])
+  );
+  sky130_fd_sc_hd__mux2_1 _1033_ (
+    .A0(_0040_),
+    .A1(_0039_),
+    .S(_0000_),
+    .X(sum[20])
+  );
+  sky130_fd_sc_hd__mux2_1 _1034_ (
+    .A0(_0042_),
+    .A1(_0041_),
+    .S(_0000_),
+    .X(sum[21])
+  );
+  sky130_fd_sc_hd__mux2_1 _1035_ (
+    .A0(_0044_),
+    .A1(_0043_),
+    .S(_0000_),
+    .X(sum[22])
+  );
+  sky130_fd_sc_hd__mux2_1 _1036_ (
+    .A0(_0046_),
+    .A1(_0045_),
+    .S(_0000_),
+    .X(sum[23])
+  );
+  sky130_fd_sc_hd__mux2_1 _1037_ (
+    .A0(_0048_),
+    .A1(_0047_),
+    .S(_0000_),
+    .X(sum[24])
+  );
+endmodule
diff --git a/Simulations/post_synthesis/gls.v b/Simulations/post_synthesis/gls.v
new file mode 100644
index 0000000..fee2ad8
--- /dev/null
+++ b/Simulations/post_synthesis/gls.v
@@ -0,0 +1,27 @@
+module gls;
+reg [17:0] p, q;
+reg mode;
+wire [18:0] sum;
+
+adder u1(
+p,q,mode,sum
+);
+
+initial
+begin
+mode=0;
+	     p = 10; q = 16;
+	#20; p = 50; q = 34; 
+	#20; p = 110; q = 45;
+	#20; p = 2000; q = 4535;
+
+end
+
+initial 
+begin
+	$dumpfile("add_syn.vcd");
+	$dumpvars(0, gls);
+	$monitor("time = %2d, p = %d, q = %d, sum = %d", $time, p, q, sum);
+end
+
+endmodule
\ No newline at end of file
diff --git a/Simulations/post_synthesis/primitives.v b/Simulations/post_synthesis/primitives.v
new file mode 100644
index 0000000..03689fe
--- /dev/null
+++ b/Simulations/post_synthesis/primitives.v
@@ -0,0 +1,1680 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+`define SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+
+/**
+ * udp_mux_2to1_N: Two to one multiplexer with inverting output
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_2to1_N (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    table
+     //  A0  A1  S  :  Y
+         0   ?   0  :  1   ;
+         1   ?   0  :  0   ;
+         ?   0   1  :  1   ;
+         ?   1   1  :  0   ;
+         0   0   ?  :  1   ;
+         1   1   ?  :  0   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PS_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    SET     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  SET     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  SET  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b    0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)  0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b   (?0)    ?      1    0   :  ?  :  -    ; // S => 0, hold unless CP==x
+                 ?            ?    1      ?      1    0   :  ?  :  1    ; // async set
+                 0            r    0      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r    ?      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)  0      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)  ?      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x    0      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x    ?      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b   (?x)    ?      1    0   :  1  :  1    ; // S=>x, hold when Q==1 unless CP==x
+                 ?           (?0)  x      ?      1    0   :  1  :  1    ;
+        // ['IfDef(functional)', '']                 ?            ?    ?      *      1    0   :  ?  :  -    ; // Q => - on any change on notifier
+        // ['Else', '']                 ?            ?    ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // ['EndIfDef(functional)', '']                 ?            ?    ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?    ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_P_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$P (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    reg Q;
+
+    table
+     //  D  GATE :  Qt : Qt+1
+         ?   0   :  ?  :  -    ; // hold
+         0   1   :  ?  :  0    ; // pass 0
+         1   1   :  ?  :  1    ; // pass 1
+         0   x   :  0  :  0    ; // reduce pessimism
+         1   x   :  1  :  1    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_P_V
+`define SKY130_FD_SC_HD__UDP_DFF_P_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$P (
+    Q  ,
+    D  ,
+    CLK
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+
+    reg Q;
+
+    table
+     //  D  CLK  :  Qt : Qt+1
+         1  (01) :  ?  :  1    ; // clocked data
+         0  (01) :  ?  :  0    ;
+         1  (x1) :  1  :  1    ; // reducing pessimism
+         0  (x1) :  0  :  0    ;
+         1  (0x) :  1  :  1    ;
+         0  (0x) :  0  :  0    ;
+         ?  (1x) :  ?  :  -    ; // no change on falling edge
+         ?  (?0) :  ?  :  -    ;
+         *   ?   :  ?  :  -    ; // ignore edges on data
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+
+/**
+ * udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
+ *                      (Q output UDP) with both active high reset and
+ *                      set (set dominate). Includes VPWR and VGND
+ *                      power pins and notifier pin.
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N (
+    Q       ,
+    SET     ,
+    RESET   ,
+    CLK_N   ,
+    D       ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  SET     ;
+    input  RESET   ;
+    input  CLK_N   ;
+    input  D       ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //         SET          RESET CLK_N  D  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 0             1     b    ?     ?      1    0   :  ?  :  0    ; // Asserting reset
+                 0             *     ?    ?     ?      1    0   :  0  :  0    ; // Changing reset
+                 1             ?     b    ?     ?      1    0   :  ?  :  1    ; // Asserting set  (dominates reset)
+                 *             0     ?    ?     ?      1    0   :  1  :  1    ; // Changing set
+                 1             ?     n    ?     ?      1    0   :  1  :  1    ;
+                 ?             1     n    ?     ?      1    0   :  0  :  0    ;
+                 x             ?     n    ?     ?      1    0   :  1  :  1    ;
+                 ?             x     n    ?     ?      1    0   :  0  :  0    ;
+                 0             ?    (01)  0     ?      1    0   :  ?  :  0    ; // rising clock
+                 ?             0    (01)  1     ?      1    0   :  ?  :  1    ; // rising clock
+                 0             ?     p    0     ?      1    0   :  0  :  0    ; // potential rising clock
+                 ?             0     p    1     ?      1    0   :  1  :  1    ; // potential rising clock
+                 0             ?     x    0     ?      1    0   :  1  :  x    ;
+                 ?             0     x    1     ?      1    0   :  0  :  x    ;
+                 0             0     n    ?     ?      1    0   :  ?  :  -    ; // Clock falling register output does not change
+                 0             0     ?    *     ?      1    0   :  ?  :  -    ; // Changing Data
+        // ['IfDef(functional)', '']                 ?             ?     ?    ?     *      1    0   :  ?  :  -    ; // go to - on notify
+        // ['Else', '']                 ?             ?     ?    ?     *      1    0   :  ?  :  X    ; // go to X on notify
+        // ['EndIfDef(functional)', '']                 ?             ?     ?    ?     ?      *    0   :  ?  :  X    ; // any change on vpwr
+                 ?             ?     ?    ?     ?      ?    *   :  ?  :  X    ; // any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_V
+`define SKY130_FD_SC_HD__UDP_DFF_PS_V
+
+/**
+ * udp_dff$PS: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PS (
+    Q  ,
+    D  ,
+    CLK,
+    SET
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+    input  SET;
+
+    reg Q;
+
+    table
+     //  D  CLK  SET  :  Qt : Qt+1
+         *   b    0   :  ?  :  -    ; // data event, hold unless CP==x
+         ?  (?0)  0   :  ?  :  -    ; // CP => 0, hold
+         ?   b   (?0) :  ?  :  -    ; // S => 0, hold unless CP==x
+         ?   ?    1   :  ?  :  1    ; // async set
+         0   r    0   :  ?  :  0    ; // clock data on CP
+         1   r    ?   :  ?  :  1    ; // clock data on CP
+         0  (x1)  0   :  0  :  0    ; // possible CP, hold when D==Q==0
+         1  (x1)  ?   :  1  :  1    ; // possible CP, hold when D==Q==1
+         0   x    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+         1   x    ?   :  1  :  1    ; // unkown CP, hold when D==Q==1
+         ?   b   (?x) :  1  :  1    ; // S=>x, hold when Q==1 unless CP==x
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_PS_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+
+/**
+ * udp_dlatch$lP: D-latch, gated standard drive / active high
+ *                (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$lP (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    reg Q;
+
+    table
+     //  D  GATE :  Qt : Qt+1
+         ?   0   :  ?  :  -    ; // hold
+         0   1   :  ?  :  0    ; // pass 0
+         1   1   :  ?  :  1    ; // pass 1
+         0   x   :  0  :  0    ; // reduce pessimism
+         1   x   :  1  :  1    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$P (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+
+    table
+     // UDP_IN VPWR : UDP_OUT
+          0     1   :    0     ;
+          1     1   :    1     ;
+          ?     0   :    x     ;
+          ?     x   :    x     ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$PG (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VPWR VGND : out
+          0     1    0   :  0   ;
+          1     1    0   :  1   ;
+          x     1    0   :  x   ;
+          ?     0    0   :  x   ;
+          ?     1    1   :  x   ;
+          ?     x    0   :  x   ;
+          ?     1    x   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  RESET NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b     0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)   0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b    (?0)    ?      1    0   :  ?  :  -    ; // R => 0, hold unless CP==x
+                 ?            ?     1      ?      1    0   :  ?  :  0    ; // async reset
+                 0            r     ?      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r     0      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)   ?      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)   0      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x     ?      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x     0      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b    (?x)    ?      1    0   :  0  :  0    ; // R=>x, hold when Q==0 unless CP==x
+                 ?           (?0)   x      ?      1    0   :  0  :  0    ;
+        // ['IfDef(functional)', '']                 ?            ?     ?      *      1    0   :  ?  :  -    ; // Q => - on any change on notifier
+        // ['Else', '']                 ?            ?     ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // ['EndIfDef(functional)', '']                 ?            ?     ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?     ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$PG (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VPWR VGND : out
+          0     1    0   :  0   ;
+          1     1    0   :  1   ;
+          x     1    0   :  x   ;
+          ?     0    0   :  x   ;
+          ?     1    1   :  x   ;
+          ?     x    0   :  x   ;
+          ?     1    x   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    VGND   ,
+    SLEEP
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  SLEEP  ;
+
+    table
+     // UDP_IN VPWR VGND SLEEP : out
+          0     1    0     ?   :  0   ;
+          1     1    0     0   :  1   ;
+          x     1    0     0   :  x   ;
+          ?     0    0     0   :  x   ;
+          ?     1    1     0   :  x   ;
+          ?     x    0     0   :  x   ;
+          ?     1    x     0   :  x   ;
+          ?     ?    0     1   :  0   ;
+          ?     ?    1     1   :  x   ;
+          ?     ?    x     1   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+`define SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_2to1 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    table
+     //  A0  A1  S  :  X
+         0   0   ?  :  0   ;
+         1   1   ?  :  1   ;
+         0   ?   0  :  0   ;
+         1   ?   0  :  1   ;
+         ?   0   1  :  0   ;
+         ?   1   1  :  1   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ *                       (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N (
+    Q       ,
+    D       ,
+    GATE    ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  GATE    ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           GATE NOTIFIER VPWR VGND : Qtn : Qtn+1
+                 *            0      ?      1    0   :  ?  :   -    ;
+                 ?           (?0)    ?      1    0   :  ?  :   -    ;
+                 ?           (1x)    ?      1    0   :  ?  :   -    ;
+                 0           (0x)    ?      1    0   :  0  :   0    ;
+                 1           (0x)    ?      1    0   :  1  :   1    ;
+                 0           (x1)    ?      1    0   :  ?  :   0    ;
+                 1           (x1)    ?      1    0   :  ?  :   1    ;
+                (?0)          1      ?      1    0   :  ?  :   0    ;
+                (?1)          1      ?      1    0   :  ?  :   1    ;
+                 0           (01)    ?      1    0   :  ?  :   0    ;
+                 1           (01)    ?      1    0   :  ?  :   1    ;
+                (?1)          x      ?      1    0   :  1  :   1    ; // Reducing pessimism.
+                (?0)          x      ?      1    0   :  0  :   0    ;
+        // ['IfDef(functional)', '']                 ?            ?      *      1    0   :  ?  :   -    ;
+        // ['Else', '']                 ?            ?      *      1    0   :  ?  :   x    ;
+        // ['EndIfDef(functional)', '']                 0            1      ?     (?1)  0   :  ?  :   0    ;
+                 1            1      ?     (?1)  0   :  ?  :   1    ;
+                 0            1      ?      1   (?0) :  ?  :   0    ;
+                 1            1      ?      1   (?0) :  ?  :   1    ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_V
+`define SKY130_FD_SC_HD__UDP_DFF_NSR_V
+
+/**
+ * udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
+ *              with both active high reset and set (set dominate).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$NSR (
+    Q    ,
+    SET  ,
+    RESET,
+    CLK_N,
+    D
+);
+
+    output Q    ;
+    input  SET  ;
+    input  RESET;
+    input  CLK_N;
+    input  D    ;
+
+    reg Q;
+
+    table
+     // SET RESET CLK_N  D  :  Qt : Qt+1
+         0    1     ?    ?  :  ?  :  0    ; // Asserting reset
+         0    *     ?    ?  :  0  :  0    ; // Changing reset
+         1    ?     ?    ?  :  ?  :  1    ; // Asserting set (dominates reset)
+         *    0     ?    ?  :  1  :  1    ; // Changing set
+         0    ?    (01)  0  :  ?  :  0    ; // rising clock
+         ?    0    (01)  1  :  ?  :  1    ; // rising clock
+         0    ?     p    0  :  0  :  0    ; // potential rising clock
+         ?    0     p    1  :  1  :  1    ; // potential rising clock
+         0    0     n    ?  :  ?  :  -    ; // Clock falling register output does not change
+         0    0     ?    *  :  ?  :  -    ; // Changing Data
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_NSR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+
+/**
+ * udp_dlatch$lP_pp$PG$N: D-latch, gated standard drive / active high
+ *                        (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N (
+    Q       ,
+    D       ,
+    GATE    ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  GATE    ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           GATE NOTIFIER VPWR VGND : Qtn : Qtn+1
+                 *            0      ?      1    0   :  ?  :   -    ;
+                 ?           (?0)    ?      1    0   :  ?  :   -    ;
+                 ?           (1x)    ?      1    0   :  ?  :   -    ;
+                 0           (0x)    ?      1    0   :  0  :   0    ;
+                 1           (0x)    ?      1    0   :  1  :   1    ;
+                 0           (x1)    ?      1    0   :  ?  :   0    ;
+                 1           (x1)    ?      1    0   :  ?  :   1    ;
+                (?0)          1      ?      1    0   :  ?  :   0    ;
+                (?1)          1      ?      1    0   :  ?  :   1    ;
+                 0           (01)    ?      1    0   :  ?  :   0    ;
+                 1           (01)    ?      1    0   :  ?  :   1    ;
+                (?1)          x      ?      1    0   :  1  :   1    ; // Reducing pessimism.
+                (?0)          x      ?      1    0   :  0  :   0    ;
+        // ['IfDef(functional)', '']                 ?            ?      *      1    0   :  ?  :   -    ;
+        // ['Else', '']                 ?            ?      *      1    0   :  ?  :   x    ;
+        // ['EndIfDef(functional)', '']                 ?            ?      ?      *    ?   :  ?  :   x    ; // any change on vpwr
+                 ?            ?      ?      ?    *   :  ?  :   x    ; // any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+
+/**
+
+ *   UDP_OUT :=x when VGND!=0
+ *   UDP_OUT :=UDP_IN when VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$G (
+    UDP_OUT,
+    UDP_IN ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VGND : out
+          0     0   :  0   ;
+          1     0   :  1   ;
+          x     0   :  x   ;
+          ?     1   :  x   ;
+          ?     x   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$P_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 1           (01)    ?      1    0   :  ?  :  1    ; // clocked data
+                 0           (01)    ?      1    0   :  ?  :  0    ;
+                 1           (x1)    ?      1    0   :  1  :  1    ; // reducing pessimism
+                 0           (x1)    ?      1    0   :  0  :  0    ;
+                 1           (0x)    ?      1    0   :  1  :  1    ;
+                 0           (0x)    ?      1    0   :  0  :  0    ;
+                 0            x      ?      1    0   :  0  :  0    ; // Hold when CLK=X and D=Q
+                 1            x      ?      1    0   :  1  :  1    ; // Hold when CLK=X and D=Q
+                 ?           (?0)    ?      1    0   :  ?  :  -    ;
+                 *            b      ?      1    0   :  ?  :  -    ; // ignore edges on data
+        // ['IfDef(functional)', '']                 ?            ?      *      1    0   :  ?  :  -    ;
+        // ['Else', '']                 ?            ?      *      1    0   :  ?  :  x    ;
+        // ['EndIfDef(functional)', '']                 ?            ?      ?      *    ?   :  ?  :  x    ; // any change on vpwr
+                 ?            ?      ?      ?    *   :  ?  :  x    ; // any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+`define SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_4to2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    table
+     //  A0  A1  A2  A3  S0  S1 :  X
+         0   ?   ?   ?   0   0  :  0   ;
+         1   ?   ?   ?   0   0  :  1   ;
+         ?   0   ?   ?   1   0  :  0   ;
+         ?   1   ?   ?   1   0  :  1   ;
+         ?   ?   0   ?   0   1  :  0   ;
+         ?   ?   1   ?   0   1  :  1   ;
+         ?   ?   ?   0   1   1  :  0   ;
+         ?   ?   ?   1   1   1  :  1   ;
+         0   0   0   0   ?   ?  :  0   ;
+         1   1   1   1   ?   ?  :  1   ;
+         0   0   ?   ?   ?   0  :  0   ;
+         1   1   ?   ?   ?   0  :  1   ;
+         ?   ?   0   0   ?   1  :  0   ;
+         ?   ?   1   1   ?   1  :  1   ;
+         0   ?   0   ?   0   ?  :  0   ;
+         1   ?   1   ?   0   ?  :  1   ;
+         ?   0   ?   0   1   ?  :  0   ;
+         ?   1   ?   1   1   ?  :  1   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$G (
+    UDP_OUT,
+    UDP_IN ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VPWR : UDP_OUT
+          0     0   :    0     ;
+          1     0   :    1     ;
+          ?     1   :    x     ;
+          ?     x   :    x     ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_V
+`define SKY130_FD_SC_HD__UDP_DFF_PR_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PR (
+    Q    ,
+    D    ,
+    CLK  ,
+    RESET
+);
+
+    output Q    ;
+    input  D    ;
+    input  CLK  ;
+    input  RESET;
+
+    reg Q;
+
+    table
+     //  D  CLK  RESET :  Qt : Qt+1
+         *   b     0   :  ?  :  -    ; // data event, hold unless CP==x
+         ?  (?0)   0   :  ?  :  -    ; // CP => 0, hold
+         ?   b    (?0) :  ?  :  -    ; // R => 0, hold unless CP==x
+         ?   ?     1   :  ?  :  0    ; // async reset
+         0   r     ?   :  ?  :  0    ; // clock data on CP
+         1   r     0   :  ?  :  1    ; // clock data on CP
+         0  (x1)   ?   :  0  :  0    ; // possible CP, hold when D==Q==0
+         1  (x1)   0   :  1  :  1    ; // possible CP, hold when D==Q==1
+         0   x     ?   :  0  :  0    ; // unkown CP, hold when D==Q==0
+         1   x     0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+         ?   b    (?x) :  0  :  0    ; // R=>x, hold when Q==0 unless CP==x
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DFF_PR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+
+/**
+ * udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
+ *                        high (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    GATE    ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  GATE    ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           GATE RESET NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            0     0      ?      1    0   :  ?  :  -    ;
+                 ?            ?     1      ?      1    0   :  ?  :  0    ; // asynchro clear
+                 ?           (?0)   0      ?      1    0   :  ?  :  -    ; // Changed R=? to R=0 ; jek 08/14/06/
+                 ?           (1x)   0      ?      1    0   :  ?  :  -    ; // Changed R=? to R=0 ; jek 08/14/06
+                 0           (0x)   0      ?      1    0   :  0  :  0    ;
+                 1           (0x)   0      ?      1    0   :  1  :  1    ;
+                 0           (x1)   0      ?      1    0   :  ?  :  0    ;
+                 1           (x1)   0      ?      1    0   :  ?  :  1    ;
+                (?0)          1     0      ?      1    0   :  ?  :  0    ;
+                (?1)          1     0      ?      1    0   :  ?  :  1    ;
+                 0           (01)   0      ?      1    0   :  ?  :  0    ;
+                 1           (01)   0      ?      1    0   :  ?  :  1    ;
+                 ?            0    (?x)    ?      1    0   :  0  :  0    ; // Reducing pessimism.//AB
+                 *            0     x      ?      1    0   :  0  :  0    ; // Reducing pessimism//AB
+                 0           (?1)   x      ?      1    0   :  ?  :  0    ; // Reducing pessimism.
+                (?0)          1     x      ?      1    0   :  ?  :  0    ; // Reducing pessimism.
+                 0            1    (?x)    ?      1    0   :  ?  :  0    ; // Reducing pessimism.//AB
+                 ?            0    (?0)    ?      1    0   :  ?  :  -    ; // ignore edge on clear
+                 0            1    (?0)    ?      1    0   :  ?  :  0    ; // pessimism .
+                 1            1    (?0)    ?      1    0   :  ?  :  1    ;
+                (?1)          x     0      ?      1    0   :  1  :  1    ; // Reducing pessimism.
+                (?0)          x     0      ?      1    0   :  0  :  0    ; // Reducing pessimism.
+        // ['IfDef(functional)', '']                 ?            ?     ?      *      1    0   :  ?  :  -    ;
+        // ['Else', '']                 ?            ?     ?      *      1    0   :  ?  :  x    ;
+        // ['EndIfDef(functional)', '']                 0            1     0      ?     (?1)  0   :  ?  :  0    ;
+                 1            1     0      ?     (?1)  0   :  ?  :  1    ;
+                 0            1     0      ?      1   (?0) :  ?  :  0    ;
+                 1            1     0      ?      1   (?0) :  ?  :  1    ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$PR (
+    Q    ,
+    D    ,
+    GATE ,
+    RESET
+);
+
+    output Q    ;
+    input  D    ;
+    input  GATE ;
+    input  RESET;
+
+    reg Q;
+
+    table
+     //  D  GATE RESET :  Qt : Qt+1
+         ?   0     0   :  ?  :  -    ; // hold
+         0   1     0   :  ?  :  0    ; // pass 0
+         1   1     0   :  ?  :  1    ; // pass 1
+         ?   ?     1   :  ?  :  0    ; // async reset
+         0   1     ?   :  ?  :  0    ; // reduce pessimism
+         0   x     0   :  0  :  0    ; // reduce pessimism
+         1   x     0   :  1  :  1    ; // reduce pessimism
+         ?   0     x   :  0  :  0    ; // reduce pessimism
+         0   x     x   :  0  :  0    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+
+
+//--------EOF---------
+
diff --git a/Simulations/post_synthesis/sky130_fd_sc_hd.v b/Simulations/post_synthesis/sky130_fd_sc_hd.v
new file mode 100644
index 0000000..2398035
--- /dev/null
+++ b/Simulations/post_synthesis/sky130_fd_sc_hd.v
@@ -0,0 +1,102454 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_6 (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_decapkapwr base (
+        .VPWR(VPWR),
+        .KAPWR(KAPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_6 ();
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_12 (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_decapkapwr base (
+        .VPWR(VPWR),
+        .KAPWR(KAPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_12 ();
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 3 units
+ * (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_3 (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_decapkapwr base (
+        .VPWR(VPWR),
+        .KAPWR(KAPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_3 ();
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_4 (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_decapkapwr base (
+        .VPWR(VPWR),
+        .KAPWR(KAPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_4 ();
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr ();
+
+    // Module supplies
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ *                    rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_8 (
+    VPWR ,
+    KAPWR,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input KAPWR;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_decapkapwr base (
+        .VPWR(VPWR),
+        .KAPWR(KAPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_8 ();
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply1 KAPWR;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DIODE_2_V
+`define SKY130_FD_SC_HD__DIODE_2_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog wrapper for diode with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__diode_2 (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__diode base (
+        .DIODE(DIODE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__diode_2 (
+    DIODE
+);
+
+    input DIODE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__diode base (
+        .DIODE(DIODE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DIODE_V
+`define SKY130_FD_SC_HD__DIODE_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+    DIODE
+);
+
+    // Module ports
+    input DIODE;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+    DIODE
+);
+
+    // Module ports
+    input DIODE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DIODE_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_V
+`define SKY130_FD_SC_HD__NOR3B_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , C_N, nor0_out         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , C_N, nor0_out         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B           );
+    and and0 (and0_out_Y, C_N, nor0_out  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B           );
+    and and0 (and0_out_Y, C_N, nor0_out  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_1_V
+`define SKY130_FD_SC_HD__NOR3B_1_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_2_V
+`define SKY130_FD_SC_HD__NOR3B_2_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_4_V
+`define SKY130_FD_SC_HD__NOR3B_4_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_4 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_4_V
+`define SKY130_FD_SC_HD__A211O_4_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_1_V
+`define SKY130_FD_SC_HD__A211O_1_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_2_V
+`define SKY130_FD_SC_HD__A211O_2_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_V
+`define SKY130_FD_SC_HD__A211O_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2          );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2          );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_2_V
+`define SKY130_FD_SC_HD__A221OI_2_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_1_V
+`define SKY130_FD_SC_HD__A221OI_1_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_4_V
+`define SKY130_FD_SC_HD__A221OI_4_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_V
+`define SKY130_FD_SC_HD__A221OI_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, C1, and1_out);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, C1, and1_out);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire and0_out  ;
+    wire and1_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2                );
+    and and1 (and1_out  , A1, A2                );
+    nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
+    buf buf0 (Y         , nor0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire and1_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2                );
+    and and1 (and1_out  , A1, A2                );
+    nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
+    buf buf0 (Y         , nor0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_V
+`define SKY130_FD_SC_HD__FILL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_4_V
+`define SKY130_FD_SC_HD__FILL_4_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_4 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_8_V
+`define SKY130_FD_SC_HD__FILL_8_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_8 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_8 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_2_V
+`define SKY130_FD_SC_HD__FILL_2_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_1_V
+`define SKY130_FD_SC_HD__FILL_1_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FILL_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_V
+`define SKY130_FD_SC_HD__NAND3_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A, C                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A, C                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A, C        );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A, C        );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_2_V
+`define SKY130_FD_SC_HD__NAND3_2_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_2 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_1_V
+`define SKY130_FD_SC_HD__NAND3_1_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_1 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_4_V
+`define SKY130_FD_SC_HD__NAND3_4_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_4 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_4_V
+`define SKY130_FD_SC_HD__DLCLKP_4_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_4 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_4 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_2_V
+`define SKY130_FD_SC_HD__DLCLKP_2_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_2 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_2 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_1_V
+`define SKY130_FD_SC_HD__DLCLKP_1_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_V
+`define SKY130_FD_SC_HD__DLCLKP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0  ;
+    wire clkn;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK                     );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE, clkn, , VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0          ;
+    wire clkn        ;
+    wire CLK_delayed ;
+    wire GATE_delayed;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK_delayed                             );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK_delayed                         );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Local signals
+    wire m0  ;
+    wire clkn;
+
+    //                            Name     Output  Other arguments
+    not                           not0    (clkn  , CLK            );
+    sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0    , GATE, clkn     );
+    and                           and0    (GCLK  , m0, CLK        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire m0          ;
+    wire clkn        ;
+    wire CLK_delayed ;
+    wire GATE_delayed;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK_delayed                             );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK_delayed                         );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLCLKP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_V
+`define SKY130_FD_SC_HD__NOR2B_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A                     );
+    and                                and0        (and0_out_Y       , not0_out, B_N         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A                     );
+    and                                and0        (and0_out_Y       , not0_out, B_N         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A              );
+    and and0 (and0_out_Y, not0_out, B_N  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A              );
+    and and0 (and0_out_Y, not0_out, B_N  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_2_V
+`define SKY130_FD_SC_HD__NOR2B_2_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_2 (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_2 (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_4_V
+`define SKY130_FD_SC_HD__NOR2B_4_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_4 (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_4 (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_1_V
+`define SKY130_FD_SC_HD__NOR2B_1_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_1 (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_1 (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_2_V
+`define SKY130_FD_SC_HD__O2111A_2_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_1_V
+`define SKY130_FD_SC_HD__O2111A_1_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_V
+`define SKY130_FD_SC_HD__O2111A_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , B1, C1, or0_out, D1   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , B1, C1, or0_out, D1   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1             );
+    and and0 (and0_out_X, B1, C1, or0_out, D1);
+    buf buf0 (X         , and0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1             );
+    and and0 (and0_out_X, B1, C1, or0_out, D1);
+    buf buf0 (X         , and0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_4_V
+`define SKY130_FD_SC_HD__O2111A_4_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_V
+`define SKY130_FD_SC_HD__NAND4B_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , D, C, B, not0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , D, C, B, not0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N              );
+    nand nand0 (nand0_out_Y, D, C, B, not0_out);
+    buf  buf0  (Y          , nand0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N              );
+    nand nand0 (nand0_out_Y, D, C, B, not0_out);
+    buf  buf0  (Y          , nand0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_4_V
+`define SKY130_FD_SC_HD__NAND4B_4_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_4 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_1_V
+`define SKY130_FD_SC_HD__NAND4B_1_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_1 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_1 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_2_V
+`define SKY130_FD_SC_HD__NAND4B_2_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_2 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_2 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf0_out_X    ;
+    wire pwrgood0_out_X;
+
+    //                                   Name      Output          Other arguments
+    buf                                  buf0     (buf0_out_X    , A                      );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
+    buf                                  buf1     (X             , pwrgood0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf0_out_X    ;
+    wire pwrgood0_out_X;
+
+    //                                   Name      Output          Other arguments
+    buf                                  buf0     (buf0_out_X    , A                      );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
+    buf                                  buf1     (X             , pwrgood0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
+    X    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_4_V
+`define SKY130_FD_SC_HD__NAND2_4_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_8_V
+`define SKY130_FD_SC_HD__NAND2_8_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_8 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_8 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_1_V
+`define SKY130_FD_SC_HD__NAND2_1_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_V
+`define SKY130_FD_SC_HD__NAND2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A                   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A                   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_2_V
+`define SKY130_FD_SC_HD__NAND2_2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_V
+`define SKY130_FD_SC_HD__MUX4_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_4to2      mux_4to20   (mux_4to20_out_X  , A0, A1, A2, A3, S0, S1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_4to2      mux_4to20   (mux_4to20_out_X  , A0, A1, A2, A3, S0, S1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Local signals
+    wire mux_4to20_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+    buf                           buf0      (X              , mux_4to20_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+    buf                           buf0      (X              , mux_4to20_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_1_V
+`define SKY130_FD_SC_HD__MUX4_1_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_1 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_1 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_4_V
+`define SKY130_FD_SC_HD__MUX4_4_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_2_V
+`define SKY130_FD_SC_HD__MUX4_2_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_2 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s4s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlymetal6s4s base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlymetal6s4s base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_4_V
+`define SKY130_FD_SC_HD__AND3_4_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_1_V
+`define SKY130_FD_SC_HD__AND3_1_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_2_V
+`define SKY130_FD_SC_HD__AND3_2_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_V
+`define SKY130_FD_SC_HD__AND3_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , C, A, B               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , C, A, B               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, C, A, B        );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, C, A, B        );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_1_V
+`define SKY130_FD_SC_HD__HA_1_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_4_V
+`define SKY130_FD_SC_HD__HA_4_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_V
+`define SKY130_FD_SC_HD__HA_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_COUT       ;
+    wire pwrgood_pp0_out_COUT;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    and                                and0        (and0_out_COUT       , A, B                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT     );
+    xor                                xor0        (xor0_out_SUM        , B, A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_COUT       ;
+    wire pwrgood_pp0_out_COUT;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    and                                and0        (and0_out_COUT       , A, B                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT     );
+    xor                                xor0        (xor0_out_SUM        , B, A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Local signals
+    wire and0_out_COUT;
+    wire xor0_out_SUM ;
+
+    //  Name  Output         Other arguments
+    and and0 (and0_out_COUT, A, B           );
+    buf buf0 (COUT         , and0_out_COUT  );
+    xor xor0 (xor0_out_SUM , B, A           );
+    buf buf1 (SUM          , xor0_out_SUM   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_COUT;
+    wire xor0_out_SUM ;
+
+    //  Name  Output         Other arguments
+    and and0 (and0_out_COUT, A, B           );
+    buf buf0 (COUT         , and0_out_COUT  );
+    xor xor0 (xor0_out_SUM , B, A           );
+    buf buf1 (SUM          , xor0_out_SUM   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_2_V
+`define SKY130_FD_SC_HD__HA_2_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__HA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCON_V
+`define SKY130_FD_SC_HD__FAHCON_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire xor0_out_SUM         ;
+    wire pwrgood_pp0_out_SUM  ;
+    wire a_b                  ;
+    wire a_ci                 ;
+    wire b_ci                 ;
+    wire or0_out_coutn        ;
+    wire pwrgood_pp1_out_coutn;
+
+    //                                 Name         Output                 Other arguments
+    xor                                xor0        (xor0_out_SUM         , A, B, CI                 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM  , xor0_out_SUM, VPWR, VGND );
+    buf                                buf0        (SUM                  , pwrgood_pp0_out_SUM      );
+    nor                                nor0        (a_b                  , A, B                     );
+    nor                                nor1        (a_ci                 , A, CI                    );
+    nor                                nor2        (b_ci                 , B, CI                    );
+    or                                 or0         (or0_out_coutn        , a_b, a_ci, b_ci          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+    buf                                buf1        (COUT_N               , pwrgood_pp1_out_coutn    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire xor0_out_SUM         ;
+    wire pwrgood_pp0_out_SUM  ;
+    wire a_b                  ;
+    wire a_ci                 ;
+    wire b_ci                 ;
+    wire or0_out_coutn        ;
+    wire pwrgood_pp1_out_coutn;
+
+    //                                 Name         Output                 Other arguments
+    xor                                xor0        (xor0_out_SUM         , A, B, CI                 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM  , xor0_out_SUM, VPWR, VGND );
+    buf                                buf0        (SUM                  , pwrgood_pp0_out_SUM      );
+    nor                                nor0        (a_b                  , A, B                     );
+    nor                                nor1        (a_ci                 , A, CI                    );
+    nor                                nor2        (b_ci                 , B, CI                    );
+    or                                 or0         (or0_out_coutn        , a_b, a_ci, b_ci          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+    buf                                buf1        (COUT_N               , pwrgood_pp1_out_coutn    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Local signals
+    wire xor0_out_SUM ;
+    wire a_b          ;
+    wire a_ci         ;
+    wire b_ci         ;
+    wire or0_out_coutn;
+
+    //  Name  Output         Other arguments
+    xor xor0 (xor0_out_SUM , A, B, CI       );
+    buf buf0 (SUM          , xor0_out_SUM   );
+    nor nor0 (a_b          , A, B           );
+    nor nor1 (a_ci         , A, CI          );
+    nor nor2 (b_ci         , B, CI          );
+    or  or0  (or0_out_coutn, a_b, a_ci, b_ci);
+    buf buf1 (COUT_N       , or0_out_coutn  );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_SUM ;
+    wire a_b          ;
+    wire a_ci         ;
+    wire b_ci         ;
+    wire or0_out_coutn;
+
+    //  Name  Output         Other arguments
+    xor xor0 (xor0_out_SUM , A, B, CI       );
+    buf buf0 (SUM          , xor0_out_SUM   );
+    nor nor0 (a_b          , A, B           );
+    nor nor1 (a_ci         , A, CI          );
+    nor nor2 (b_ci         , B, CI          );
+    or  or0  (or0_out_coutn, a_b, a_ci, b_ci);
+    buf buf1 (COUT_N       , or0_out_coutn  );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCON_1_V
+`define SKY130_FD_SC_HD__FAHCON_1_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog wrapper for fahcon with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcon_1 (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__fahcon base (
+        .COUT_N(COUT_N),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcon_1 (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fahcon base (
+        .COUT_N(COUT_N),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCON_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_2_V
+`define SKY130_FD_SC_HD__A21BOI_2_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_4_V
+`define SKY130_FD_SC_HD__A21BOI_4_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_V
+`define SKY130_FD_SC_HD__A21BOI_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                  );
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , b, and0_out           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                  );
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , b, and0_out           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire b         ;
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (b         , B1_N           );
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, b, and0_out    );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire b         ;
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (b         , B1_N           );
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, b, and0_out    );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_0_V
+`define SKY130_FD_SC_HD__A21BOI_0_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_0 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_0 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_1_V
+`define SKY130_FD_SC_HD__A21BOI_1_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BOI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_1_V
+`define SKY130_FD_SC_HD__DLRTN_1_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_V
+`define SKY130_FD_SC_HD__DLRTN_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                                     Delay       Name     Output   Other arguments
+    not                                                not0    (RESET  , RESET_B                        );
+    not                                                not1    (intgate, GATE_N                         );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q      , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                             Delay       Name     Output   Other arguments
+    not                                        not0    (RESET  , RESET_B          );
+    not                                        not1    (intgate, GATE_N           );
+    sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET);
+    buf                                        buf0    (Q      , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_4_V
+`define SKY130_FD_SC_HD__DLRTN_4_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_2_V
+`define SKY130_FD_SC_HD__DLRTN_2_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_2 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_2 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtn base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_4_V
+`define SKY130_FD_SC_HD__A211OI_4_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_1_V
+`define SKY130_FD_SC_HD__A211OI_1_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_2_V
+`define SKY130_FD_SC_HD__A211OI_2_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_V
+`define SKY130_FD_SC_HD__A211OI_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2          );
+    nor nor0 (nor0_out_Y, and0_out, B1, C1);
+    buf buf0 (Y         , nor0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2          );
+    nor nor0 (nor0_out_Y, and0_out, B1, C1);
+    buf buf0 (Y         , nor0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A211OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAH_1_V
+`define SKY130_FD_SC_HD__FAH_1_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog wrapper for fah with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fah_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fah_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAH_V
+`define SKY130_FD_SC_HD__FAH_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    xor                                xor0        (xor0_out_SUM        , A, B, CI                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, CI                   );
+    and                                and2        (b_ci                , B, CI                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    xor                                xor0        (xor0_out_SUM        , A, B, CI                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, CI                   );
+    and                                and2        (b_ci                , B, CI                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Local signals
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    xor xor0 (xor0_out_SUM, A, B, CI       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, CI          );
+    and and2 (b_ci        , B, CI          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    xor xor0 (xor0_out_SUM, A, B, CI       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, CI          );
+    and and2 (b_ci        , B, CI          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAH_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_1_V
+`define SKY130_FD_SC_HD__SDLCLKP_1_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_1 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_1 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_4_V
+`define SKY130_FD_SC_HD__SDLCLKP_4_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_4 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_4 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_V
+`define SKY130_FD_SC_HD__SDLCLKP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+
+    //                                    Name     Output    Other arguments
+    not                                   not0    (m0n     , m0                          );
+    not                                   not1    (clkn    , CLK                         );
+    nor                                   nor0    (SCE_GATE, GATE, SCE                   );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0      , SCE_GATE, clkn, , VPWR, VGND);
+    and                                   and0    (GCLK    , m0n, CLK                    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0              ;
+    wire m0n             ;
+    wire clkn            ;
+    wire CLK_delayed     ;
+    wire SCE_delayed     ;
+    wire GATE_delayed    ;
+    wire SCE_gate_delayed;
+    reg  notifier        ;
+    wire awake           ;
+    wire SCE_awake       ;
+    wire GATE_awake      ;
+
+    //                                    Name     Output            Other arguments
+    not                                   not0    (m0n             , m0                                          );
+    not                                   not1    (clkn            , CLK_delayed                                 );
+    nor                                   nor0    (SCE_gate_delayed, GATE_delayed, SCE_delayed                   );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0              , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK            , m0n, CLK_delayed                            );
+    assign awake = ( VPWR === 1'b1 );
+    assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
+    assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+
+    //                            Name     Output    Other arguments
+    not                           not0    (m0n     , m0             );
+    not                           not1    (clkn    , CLK            );
+    nor                           nor0    (SCE_GATE, GATE, SCE      );
+    sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0      , SCE_GATE, clkn );
+    and                           and0    (GCLK    , m0n, CLK       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire m0              ;
+    wire m0n             ;
+    wire clkn            ;
+    wire CLK_delayed     ;
+    wire SCE_delayed     ;
+    wire GATE_delayed    ;
+    wire SCE_gate_delayed;
+    reg  notifier        ;
+    wire awake           ;
+    wire SCE_awake       ;
+    wire GATE_awake      ;
+
+    //                                    Name     Output            Other arguments
+    not                                   not0    (m0n             , m0                                          );
+    not                                   not1    (clkn            , CLK_delayed                                 );
+    nor                                   nor0    (SCE_gate_delayed, GATE_delayed, SCE_delayed                   );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0              , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK            , m0n, CLK_delayed                            );
+    assign awake = ( VPWR === 1'b1 );
+    assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
+    assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_2_V
+`define SKY130_FD_SC_HD__SDLCLKP_2_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_2 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_2 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDLCLKP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_V
+`define SKY130_FD_SC_HD__DFRBP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (RESET , RESET_B                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                      );
+    not                                             not1 (Q_N   , buf_Q                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+    not                                 not1 (Q_N   , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (RESET , RESET_B        );
+    sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET  );
+    buf                                     buf0 (Q     , buf_Q          );
+    not                                     not1 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+    not                                 not1 (Q_N   , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_1_V
+`define SKY130_FD_SC_HD__DFRBP_1_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_2_V
+`define SKY130_FD_SC_HD__DFRBP_2_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_4_V
+`define SKY130_FD_SC_HD__OR4BB_4_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_4 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_4 (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_1_V
+`define SKY130_FD_SC_HD__OR4BB_1_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_1 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_1 (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_V
+`define SKY130_FD_SC_HD__OR4BB_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D_N, C_N             );
+    or                                 or0         (or0_out_X        , B, A, nand0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D_N, C_N             );
+    or                                 or0         (or0_out_X        , B, A, nand0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_X;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D_N, C_N       );
+    or   or0   (or0_out_X, B, A, nand0_out);
+    buf  buf0  (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_X;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D_N, C_N       );
+    or   or0   (or0_out_X, B, A, nand0_out);
+    buf  buf0  (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_2_V
+`define SKY130_FD_SC_HD__OR4BB_2_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_2 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_2 (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_4_V
+`define SKY130_FD_SC_HD__NOR3_4_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_4 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_2_V
+`define SKY130_FD_SC_HD__NOR3_2_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_2 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_V
+`define SKY130_FD_SC_HD__NOR3_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , C, A, B               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , C, A, B               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, C, A, B        );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, C, A, B        );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_1_V
+`define SKY130_FD_SC_HD__NOR3_1_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_1 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_V
+`define SKY130_FD_SC_HD__A41O_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4       );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4       );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2, A3, A4 );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2, A3, A4 );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_4_V
+`define SKY130_FD_SC_HD__A41O_4_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_2_V
+`define SKY130_FD_SC_HD__A41O_2_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_1_V
+`define SKY130_FD_SC_HD__A41O_1_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_4_V
+`define SKY130_FD_SC_HD__OR4B_4_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_4 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_V
+`define SKY130_FD_SC_HD__OR4B_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                  );
+    or                                 or0         (or0_out_X        , not0_out, C, B, A    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                  );
+    or                                 or0         (or0_out_X        , not0_out, C, B, A    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , D_N              );
+    or  or0  (or0_out_X, not0_out, C, B, A);
+    buf buf0 (X        , or0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , D_N              );
+    or  or0  (or0_out_X, not0_out, C, B, A);
+    buf buf0 (X        , or0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_2_V
+`define SKY130_FD_SC_HD__OR4B_2_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_2 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_1_V
+`define SKY130_FD_SC_HD__OR4B_1_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_1 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_2_V
+`define SKY130_FD_SC_HD__CLKINV_2_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_V
+`define SKY130_FD_SC_HD__CLKINV_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_4_V
+`define SKY130_FD_SC_HD__CLKINV_4_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_4 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_4 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_8_V
+`define SKY130_FD_SC_HD__CLKINV_8_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_8 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_1_V
+`define SKY130_FD_SC_HD__CLKINV_1_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_16_V
+`define SKY130_FD_SC_HD__CLKINV_16_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_V
+`define SKY130_FD_SC_HD__EDFXBP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, buf_Q, D, DE              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, buf_Q, D, DE   );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_1_V
+`define SKY130_FD_SC_HD__EDFXBP_1_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for edfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__edfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__edfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_2_V
+`define SKY130_FD_SC_HD__MUX2I_2_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_2 (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_2 (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_4_V
+`define SKY130_FD_SC_HD__MUX2I_4_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_4 (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_4 (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_V
+`define SKY130_FD_SC_HD__MUX2I_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1_N    mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S                    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1_N    mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S                    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+
+    //                              Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S        );
+    buf                             buf0        (Y                , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+
+    //                              Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S        );
+    buf                             buf0        (Y                , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_1_V
+`define SKY130_FD_SC_HD__MUX2I_1_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_1 (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_1 (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2I_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_V
+`define SKY130_FD_SC_HD__SDFXTP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, D, SCD, SCE               );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_2_V
+`define SKY130_FD_SC_HD__SDFXTP_2_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_2 (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_2 (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_4_V
+`define SKY130_FD_SC_HD__SDFXTP_4_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_4 (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_1_V
+`define SKY130_FD_SC_HD__SDFXTP_1_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CONB_1_V
+`define SKY130_FD_SC_HD__CONB_1_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog wrapper for conb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__conb_1 (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__conb base (
+        .HI(HI),
+        .LO(LO),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__conb_1 (
+    HI,
+    LO
+);
+
+    output HI;
+    output LO;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__conb base (
+        .HI(HI),
+        .LO(LO)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CONB_V
+`define SKY130_FD_SC_HD__CONB_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pullup0_out_HI  ;
+    wire pulldown0_out_LO;
+
+    //                                Name         Output            Other arguments
+    pullup                            pullup0     (pullup0_out_HI  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI              , pullup0_out_HI, VPWR  );
+    pulldown                          pulldown0   (pulldown0_out_LO);
+    sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO              , pulldown0_out_LO, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pullup0_out_HI  ;
+    wire pulldown0_out_LO;
+
+    //                                Name         Output            Other arguments
+    pullup                            pullup0     (pullup0_out_HI  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI              , pullup0_out_HI, VPWR  );
+    pulldown                          pulldown0   (pulldown0_out_LO);
+    sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO              , pulldown0_out_LO, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+    HI,
+    LO
+);
+
+    // Module ports
+    output HI;
+    output LO;
+
+    //       Name       Output
+    pullup   pullup0   (HI    );
+    pulldown pulldown0 (LO    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+    HI,
+    LO
+);
+
+    // Module ports
+    output HI;
+    output LO;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //       Name       Output
+    pullup   pullup0   (HI    );
+    pulldown pulldown0 (LO    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CONB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_V
+`define SKY130_FD_SC_HD__DFSBP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q;
+    wire SET  ;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (SET   , SET_B                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                    );
+    not                                             not1 (Q_N   , buf_Q                    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( SET_B_delayed === 1'b1 );
+    assign cond1 = ( SET_B === 1'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+    not                                 not1 (Q_N   , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire SET  ;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (SET   , SET_B          );
+    sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET    );
+    buf                                     buf0 (Q     , buf_Q          );
+    not                                     not1 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( SET_B_delayed === 1'b1 );
+    assign cond1 = ( SET_B === 1'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+    not                                 not1 (Q_N   , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_1_V
+`define SKY130_FD_SC_HD__DFSBP_1_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_2_V
+`define SKY130_FD_SC_HD__DFSBP_2_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s18 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s18 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s18 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s18 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s18 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s18 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_2_V
+`define SKY130_FD_SC_HD__SDFRBP_2_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_V
+`define SKY130_FD_SC_HD__SDFRBP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                          );
+    sky130_fd_sc_hd__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                      );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                            );
+    not                                             not1      (Q_N    , buf_Q                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+    not                                 not1      (Q_N    , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B            );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE        );
+    sky130_fd_sc_hd__udp_dff$PR   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET);
+    buf                                       buf0      (Q      , buf_Q              );
+    not                                       not1      (Q_N    , buf_Q              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+    not                                 not1      (Q_N    , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_1_V
+`define SKY130_FD_SC_HD__SDFRBP_1_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_1_V
+`define SKY130_FD_SC_HD__O221AI_1_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_4_V
+`define SKY130_FD_SC_HD__O221AI_4_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_V
+`define SKY130_FD_SC_HD__O221AI_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B2, B1                 );
+    or                                 or1         (or1_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , or1_out, or0_out, C1   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B2, B1                 );
+    or                                 or1         (or1_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , or1_out, or0_out, C1   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire or0_out    ;
+    wire or1_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , B2, B1              );
+    or   or1   (or1_out    , A2, A1              );
+    nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+    buf  buf0  (Y          , nand0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire or1_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , B2, B1              );
+    or   or1   (or1_out    , A2, A1              );
+    nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+    buf  buf0  (Y          , nand0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_2_V
+`define SKY130_FD_SC_HD__O221AI_2_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_4_V
+`define SKY130_FD_SC_HD__O22AI_4_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_V
+`define SKY130_FD_SC_HD__O22AI_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , B1, B2               );
+    nor                                nor1        (nor1_out         , A1, A2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , B1, B2               );
+    nor                                nor1        (nor1_out         , A1, A2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , B1, B2            );
+    nor nor1 (nor1_out , A1, A2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , B1, B2            );
+    nor nor1 (nor1_out , A1, A2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_1_V
+`define SKY130_FD_SC_HD__O22AI_1_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_2_V
+`define SKY130_FD_SC_HD__O22AI_2_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_4_V
+`define SKY130_FD_SC_HD__O32AI_4_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_2_V
+`define SKY130_FD_SC_HD__O32AI_2_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_V
+`define SKY130_FD_SC_HD__O32AI_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A3, A1, A2           );
+    nor                                nor1        (nor1_out         , B1, B2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A3, A1, A2           );
+    nor                                nor1        (nor1_out         , B1, B2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , A3, A1, A2        );
+    nor nor1 (nor1_out , B1, B2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , A3, A1, A2        );
+    nor nor1 (nor1_out , B1, B2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_1_V
+`define SKY130_FD_SC_HD__O32AI_1_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_2_V
+`define SKY130_FD_SC_HD__NAND4_2_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_2 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_V
+`define SKY130_FD_SC_HD__NAND4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , D, C, B, A             );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , D, C, B, A             );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, D, C, B, A     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, D, C, B, A     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_1_V
+`define SKY130_FD_SC_HD__NAND4_1_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_1 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_4_V
+`define SKY130_FD_SC_HD__NAND4_4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_2_V
+`define SKY130_FD_SC_HD__NOR4BB_2_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_4_V
+`define SKY130_FD_SC_HD__NOR4BB_4_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_4 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_1_V
+`define SKY130_FD_SC_HD__NOR4BB_1_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_V
+`define SKY130_FD_SC_HD__NOR4BB_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , nor0_out, C_N, D_N    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , nor0_out, C_N, D_N    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B              );
+    and and0 (and0_out_Y, nor0_out, C_N, D_N);
+    buf buf0 (Y         , and0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B              );
+    and and0 (and0_out_Y, nor0_out, C_N, D_N);
+    buf buf0 (Y         , and0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_V
+`define SKY130_FD_SC_HD__DLXTN_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE ;
+    wire buf_Q;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N               );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Local signals
+    wire GATE ;
+    wire buf_Q;
+
+    //                            Name     Output  Other arguments
+    not                           not0    (GATE  , GATE_N         );
+    sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE        );
+    buf                           buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_2_V
+`define SKY130_FD_SC_HD__DLXTN_2_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_2 (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_2 (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_1_V
+`define SKY130_FD_SC_HD__DLXTN_1_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_1 (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_1 (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_4_V
+`define SKY130_FD_SC_HD__DLXTN_4_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_4 (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_4 (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_2_V
+`define SKY130_FD_SC_HD__DFSTP_2_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_4_V
+`define SKY130_FD_SC_HD__DFSTP_4_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_V
+`define SKY130_FD_SC_HD__DFSTP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q;
+    wire SET  ;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (SET   , SET_B                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( SET_B_delayed === 1'b1 );
+    assign cond1 = ( SET_B === 1'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire SET  ;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (SET   , SET_B          );
+    sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET    );
+    buf                                     buf0 (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( SET_B_delayed === 1'b1 );
+    assign cond1 = ( SET_B === 1'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_1_V
+`define SKY130_FD_SC_HD__DFSTP_1_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFSTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_1_V
+`define SKY130_FD_SC_HD__DFRTP_1_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_V
+`define SKY130_FD_SC_HD__DFRTP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (RESET , RESET_B                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (RESET , RESET_B        );
+    sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET  );
+    buf                                     buf0 (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_2_V
+`define SKY130_FD_SC_HD__DFRTP_2_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_4_V
+`define SKY130_FD_SC_HD__DFRTP_4_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_1_V
+`define SKY130_FD_SC_HD__NAND4BB_1_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_1 (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_1 (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_V
+`define SKY130_FD_SC_HD__NAND4BB_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D, C                 );
+    or                                 or0         (or0_out_Y        , B_N, A_N, nand0_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D, C                 );
+    or                                 or0         (or0_out_Y        , B_N, A_N, nand0_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_Y;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D, C               );
+    or   or0   (or0_out_Y, B_N, A_N, nand0_out);
+    buf  buf0  (Y        , or0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_Y;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D, C               );
+    or   or0   (or0_out_Y, B_N, A_N, nand0_out);
+    buf  buf0  (Y        , or0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_2_V
+`define SKY130_FD_SC_HD__NAND4BB_2_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_2 (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_2 (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_4_V
+`define SKY130_FD_SC_HD__NAND4BB_4_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_4 (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_4 (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ *                  containing inverter, 2-input NOR, 2-input NAND,
+ *                  and constant cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ *                  containing inverter, 2-input NOR, 2-input NAND,
+ *                  and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+    LO  ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output LO  ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire nor2left ;
+    wire invleft  ;
+    wire nor2right;
+    wire invright ;
+    wire nd2left  ;
+    wire nd2right ;
+    wire tielo    ;
+    wire net7     ;
+
+    //                       Name    Output         Other arguments
+    sky130_fd_sc_hd__inv_2   inv0   (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)                );
+    sky130_fd_sc_hd__inv_2   inv1   (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)               );
+    sky130_fd_sc_hd__nor2_2  nor20  (.B(nd2left)  , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)  );
+    sky130_fd_sc_hd__nor2_2  nor21  (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
+    sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo)    , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)    );
+    sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo)    , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)     );
+    sky130_fd_sc_hd__conb_1  conb0  (.LO(tielo)   , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)                  );
+    buf                      buf0   (LO           , tielo                                                                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ *                  containing inverter, 2-input NOR, 2-input NAND,
+ *                  and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+    LO  ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output LO  ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire nor2left ;
+    wire invleft  ;
+    wire nor2right;
+    wire invright ;
+    wire nd2left  ;
+    wire nd2right ;
+    wire tielo    ;
+    wire net7     ;
+
+    //                       Name    Output         Other arguments
+    sky130_fd_sc_hd__inv_2   inv0   (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)                );
+    sky130_fd_sc_hd__inv_2   inv1   (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)               );
+    sky130_fd_sc_hd__nor2_2  nor20  (.B(nd2left)  , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)  );
+    sky130_fd_sc_hd__nor2_2  nor21  (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
+    sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo)    , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)    );
+    sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo)    , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)     );
+    sky130_fd_sc_hd__conb_1  conb0  (.LO(tielo)   , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB)                  );
+    buf                      buf0   (LO           , tielo                                                                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ *                  containing inverter, 2-input NOR, 2-input NAND,
+ *                  and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+    LO
+);
+
+    // Module ports
+    output LO;
+
+    // Local signals
+    wire nor2left ;
+    wire invleft  ;
+    wire nor2right;
+    wire invright ;
+    wire nd2left  ;
+    wire nd2right ;
+    wire tielo    ;
+    wire net7     ;
+
+    //                       Name    Output         Other arguments
+    sky130_fd_sc_hd__inv_2   inv0   (.A(nor2left) , .Y(invleft)                );
+    sky130_fd_sc_hd__inv_2   inv1   (.A(nor2right), .Y(invright)               );
+    sky130_fd_sc_hd__nor2_2  nor20  (.B(nd2left)  , .A(nd2left), .Y(nor2left)  );
+    sky130_fd_sc_hd__nor2_2  nor21  (.B(nd2right) , .A(nd2right), .Y(nor2right));
+    sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo)    , .A(tielo), .Y(nd2right)    );
+    sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo)    , .A(tielo), .Y(nd2left)     );
+    sky130_fd_sc_hd__conb_1  conb0  (.LO(tielo)   , .HI(net7)                  );
+    buf                      buf0   (LO           , tielo                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ *                  containing inverter, 2-input NOR, 2-input NAND,
+ *                  and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+    LO
+);
+
+    // Module ports
+    output LO;
+
+    // Local signals
+    wire nor2left ;
+    wire invleft  ;
+    wire nor2right;
+    wire invright ;
+    wire nd2left  ;
+    wire nd2right ;
+    wire tielo    ;
+    wire net7     ;
+
+    //                       Name    Output         Other arguments
+    sky130_fd_sc_hd__inv_2   inv0   (.A(nor2left) , .Y(invleft)                );
+    sky130_fd_sc_hd__inv_2   inv1   (.A(nor2right), .Y(invright)               );
+    sky130_fd_sc_hd__nor2_2  nor20  (.B(nd2left)  , .A(nd2left), .Y(nor2left)  );
+    sky130_fd_sc_hd__nor2_2  nor21  (.B(nd2right) , .A(nd2right), .Y(nor2right));
+    sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo)    , .A(tielo), .Y(nd2right)    );
+    sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo)    , .A(tielo), .Y(nd2left)     );
+    sky130_fd_sc_hd__conb_1  conb0  (.LO(tielo)   , .HI(net7)                  );
+    buf                      buf0   (LO           , tielo                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MACRO_SPARECELL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_1_V
+`define SKY130_FD_SC_HD__MUX2_1_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_1 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_1 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_V
+`define SKY130_FD_SC_HD__MUX2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to10_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10   (mux_2to10_out_X  , A0, A1, S                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to10_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10   (mux_2to10_out_X  , A0, A1, S                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Local signals
+    wire mux_2to10_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S      );
+    buf                           buf0      (X              , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_2to10_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S      );
+    buf                           buf0      (X              , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_2_V
+`define SKY130_FD_SC_HD__MUX2_2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_8_V
+`define SKY130_FD_SC_HD__MUX2_8_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_8 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_8 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_4_V
+`define SKY130_FD_SC_HD__MUX2_4_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_4 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_4 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MUX2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_2_V
+`define SKY130_FD_SC_HD__NOR2_2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_1_V
+`define SKY130_FD_SC_HD__NOR2_1_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_V
+`define SKY130_FD_SC_HD__NOR2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , A, B                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , A, B                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B           );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B           );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_4_V
+`define SKY130_FD_SC_HD__NOR2_4_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_8_V
+`define SKY130_FD_SC_HD__NOR2_8_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_8 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_8 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_V
+`define SKY130_FD_SC_HD__O21BA_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A1, A2                );
+    nor                                nor1        (nor1_out_X       , B1_N, nor0_out        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A1, A2                );
+    nor                                nor1        (nor1_out_X       , B1_N, nor0_out        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire nor1_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A1, A2         );
+    nor nor1 (nor1_out_X, B1_N, nor0_out );
+    buf buf0 (X         , nor1_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire nor1_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A1, A2         );
+    nor nor1 (nor1_out_X, B1_N, nor0_out );
+    buf buf0 (X         , nor1_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_1_V
+`define SKY130_FD_SC_HD__O21BA_1_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_2_V
+`define SKY130_FD_SC_HD__O21BA_2_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_4_V
+`define SKY130_FD_SC_HD__O21BA_4_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_1_V
+`define SKY130_FD_SC_HD__A41OI_1_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_4_V
+`define SKY130_FD_SC_HD__A41OI_4_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_2_V
+`define SKY130_FD_SC_HD__A41OI_2_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_V
+`define SKY130_FD_SC_HD__A41OI_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4        );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4        );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2, A3, A4 );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2, A3, A4 );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A41OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_1_V
+`define SKY130_FD_SC_HD__OR2_1_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_4_V
+`define SKY130_FD_SC_HD__OR2_4_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_V
+`define SKY130_FD_SC_HD__OR2_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A                 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A                 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A           );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A           );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_0_V
+`define SKY130_FD_SC_HD__OR2_0_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_0 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_0 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_2_V
+`define SKY130_FD_SC_HD__OR2_2_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlygate4sd2 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlygate4sd2 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_V
+`define SKY130_FD_SC_HD__O41AI_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1         );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1         );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A4, A3, A2, A1 );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A4, A3, A2, A1 );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_2_V
+`define SKY130_FD_SC_HD__O41AI_2_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_1_V
+`define SKY130_FD_SC_HD__O41AI_1_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_4_V
+`define SKY130_FD_SC_HD__O41AI_4_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_2_V
+`define SKY130_FD_SC_HD__AND2B_2_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_2 (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_4_V
+`define SKY130_FD_SC_HD__AND2B_4_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_4 (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_4 (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_V
+`define SKY130_FD_SC_HD__AND2B_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+    X  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, not0_out, B    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+    X  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, not0_out, B    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_1_V
+`define SKY130_FD_SC_HD__AND2B_1_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_1 (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_2_V
+`define SKY130_FD_SC_HD__A311O_2_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_1_V
+`define SKY130_FD_SC_HD__A311O_1_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_4_V
+`define SKY130_FD_SC_HD__A311O_4_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_V
+`define SKY130_FD_SC_HD__A311O_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2      );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2      );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_V
+`define SKY130_FD_SC_HD__A2111OI_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, C1, D1, and0_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, C1, D1, and0_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2              );
+    nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+    buf buf0 (Y         , nor0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2              );
+    nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+    buf buf0 (Y         , nor0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_0_V
+`define SKY130_FD_SC_HD__A2111OI_0_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_0 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_0 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_1_V
+`define SKY130_FD_SC_HD__A2111OI_1_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_4_V
+`define SKY130_FD_SC_HD__A2111OI_4_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_2_V
+`define SKY130_FD_SC_HD__A2111OI_2_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_4_V
+`define SKY130_FD_SC_HD__OR3B_4_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_4 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_4 (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_2_V
+`define SKY130_FD_SC_HD__OR3B_2_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_2 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_2 (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_V
+`define SKY130_FD_SC_HD__OR3B_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , C_N                  );
+    or                                 or0         (or0_out_X        , B, A, not0_out       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , C_N                  );
+    or                                 or0         (or0_out_X        , B, A, not0_out       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , C_N            );
+    or  or0  (or0_out_X, B, A, not0_out );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , C_N            );
+    or  or0  (or0_out_X, B, A, not0_out );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_1_V
+`define SKY130_FD_SC_HD__OR3B_1_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_1 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_1 (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_8_V
+`define SKY130_FD_SC_HD__BUFINV_8_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_8 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__bufinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__bufinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_16_V
+`define SKY130_FD_SC_HD__BUFINV_16_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__bufinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__bufinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_V
+`define SKY130_FD_SC_HD__BUFINV_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFINV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
+    X     ,
+    A     ,
+    VPWRIN,
+    VPWR  ,
+    VGND  ,
+    VPB
+);
+
+    output X     ;
+    input  A     ;
+    input  VPWRIN;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A),
+        .VPWRIN(VPWRIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    VPWRIN;
+    supply1 VPWR  ;
+    supply0 VGND  ;
+    supply1 VPB   ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+    X     ,
+    A     ,
+    VPWRIN,
+    VPWR  ,
+    VGND  ,
+    VPB
+);
+
+    // Module ports
+    output X     ;
+    input  A     ;
+    input  VPWRIN;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND       );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+    X     ,
+    A     ,
+    VPWRIN,
+    VPWR  ,
+    VGND  ,
+    VPB
+);
+
+    // Module ports
+    output X     ;
+    input  A     ;
+    input  VPWRIN;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND       );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
+    X     ,
+    A     ,
+    VPWRIN,
+    VPWR  ,
+    VGND  ,
+    VPB
+);
+
+    output X     ;
+    input  A     ;
+    input  VPWRIN;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A),
+        .VPWRIN(VPWRIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    VPWRIN;
+    supply1 VPWR  ;
+    supply0 VGND  ;
+    supply1 VPB   ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ *                                 isolated well on input buffer,
+ *                                 vpb/vnb taps, double-row-height
+ *                                 cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
+    X     ,
+    A     ,
+    VPWRIN,
+    VPWR  ,
+    VGND  ,
+    VPB
+);
+
+    output X     ;
+    input  A     ;
+    input  VPWRIN;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A),
+        .VPWRIN(VPWRIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    VPWRIN;
+    supply1 VPWR  ;
+    supply0 VGND  ;
+    supply1 VPB   ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s25 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s25 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s25 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s25 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s25 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s25 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_V
+`define SKY130_FD_SC_HD__A2111O_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_2_V
+`define SKY130_FD_SC_HD__A2111O_2_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_1_V
+`define SKY130_FD_SC_HD__A2111O_1_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_4_V
+`define SKY130_FD_SC_HD__A2111O_4_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_4_V
+`define SKY130_FD_SC_HD__XOR2_4_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_1_V
+`define SKY130_FD_SC_HD__XOR2_1_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_V
+`define SKY130_FD_SC_HD__XOR2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , B, A                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , B, A                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, B, A           );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, B, A           );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_2_V
+`define SKY130_FD_SC_HD__XOR2_2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_2_V
+`define SKY130_FD_SC_HD__AND3B_2_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_2 (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_V
+`define SKY130_FD_SC_HD__AND3B_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , C, not0_out, B        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , C, not0_out, B        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, C, not0_out, B );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, C, not0_out, B );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_4_V
+`define SKY130_FD_SC_HD__AND3B_4_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_4 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_4 (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_1_V
+`define SKY130_FD_SC_HD__AND3B_1_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_1 (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB
+);
+
+    // Module ports
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND     );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB
+);
+
+    // Module ports
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND     );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB
+);
+
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A),
+        .LOWLVPWR(LOWLVPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    LOWLVPWR;
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 VPB     ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB
+);
+
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A),
+        .LOWLVPWR(LOWLVPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    LOWLVPWR;
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 VPB     ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ *                              isolated well on input buffer, vpb/vnb
+ *                              taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB
+);
+
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A),
+        .LOWLVPWR(LOWLVPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    LOWLVPWR;
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 VPB     ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_V
+`define SKY130_FD_SC_HD__TAPVGND2_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ *           2 rows down.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_1_V
+`define SKY130_FD_SC_HD__TAPVGND2_1_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ *           2 rows down.
+ *
+ * Verilog wrapper for tapvgnd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__tapvgnd2 base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__tapvgnd2 base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_1_V
+`define SKY130_FD_SC_HD__A31O_1_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_V
+`define SKY130_FD_SC_HD__A31O_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2     );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2     );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_2_V
+`define SKY130_FD_SC_HD__A31O_2_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_4_V
+`define SKY130_FD_SC_HD__A31O_4_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_V
+`define SKY130_FD_SC_HD__AND4BB_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A_N, B_N              );
+    and                                and0        (and0_out_X       , nor0_out, C, D        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A_N, B_N              );
+    and                                and0        (and0_out_X       , nor0_out, C, D        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A_N, B_N       );
+    and and0 (and0_out_X, nor0_out, C, D );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A_N, B_N       );
+    and and0 (and0_out_X, nor0_out, C, D );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_4_V
+`define SKY130_FD_SC_HD__AND4BB_4_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_4 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_4 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_1_V
+`define SKY130_FD_SC_HD__AND4BB_1_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_1 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_1 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_2_V
+`define SKY130_FD_SC_HD__AND4BB_2_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_2 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_2 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_2_V
+`define SKY130_FD_SC_HD__DFXBP_2_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_1_V
+`define SKY130_FD_SC_HD__DFXBP_1_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_V
+`define SKY130_FD_SC_HD__DFXBP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                 Delay       Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
+    buf                                            buf0 (Q     , buf_Q               );
+    not                                            not0 (Q_N   , buf_Q               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+    not                                not0 (Q_N   , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                         Delay       Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK         );
+    buf                                    buf0 (Q     , buf_Q          );
+    not                                    not0 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+    not                                not0 (Q_N   , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBP_1_V
+`define SKY130_FD_SC_HD__DLXBP_1_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp_1 (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp_1 (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBP_V
+`define SKY130_FD_SC_HD__DLXBP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                    Delay       Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                               buf0    (Q     , buf_Q                );
+    not                                               not0    (Q_N   , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    not                                   not0    (Q_N   , buf_Q                                        );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Local signals
+    wire buf_Q;
+
+    //                            Delay       Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE        );
+    buf                                       buf0    (Q     , buf_Q          );
+    not                                       not0    (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    not                                   not0    (Q_N   , buf_Q                                        );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBP_1_V
+`define SKY130_FD_SC_HD__DFBBP_1_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBP_V
+`define SKY130_FD_SC_HD__DFBBP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire buf_Q;
+
+    //                                   Delay       Name  Output  Other arguments
+    not                                              not0 (RESET , RESET_B                         );
+    not                                              not1 (SET   , SET_B                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+    buf                                              buf0 (Q     , buf_Q                           );
+    not                                              not2 (Q_N   , buf_Q                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    wire CLK_delayed    ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                         );
+    not                                  not1 (SET   , SET_B_delayed                                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                                   );
+    not                                  not2 (Q_N   , buf_Q                                                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire buf_Q;
+
+    //                           Delay       Name  Output  Other arguments
+    not                                      not0 (RESET , RESET_B           );
+    not                                      not1 (SET   , SET_B             );
+    sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+    buf                                      buf0 (Q     , buf_Q             );
+    not                                      not2 (Q_N   , buf_Q             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    wire CLK_delayed    ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                         );
+    not                                  not1 (SET   , SET_B_delayed                                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                                   );
+    not                                  not2 (Q_N   , buf_Q                                                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_V
+`define SKY130_FD_SC_HD__SDFRTN_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire intclk ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                             );
+    not                                             not1      (intclk , CLK_N                               );
+    sky130_fd_sc_hd__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                         );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, intclk, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                             );
+    not                                 not1      (intclk , CLK_N_delayed                               );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed         );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0      (Q      , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire intclk ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B               );
+    not                                       not1      (intclk , CLK_N                 );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE           );
+    sky130_fd_sc_hd__udp_dff$PR   `UNIT_DELAY dff0      (buf_Q  , mux_out, intclk, RESET);
+    buf                                       buf0      (Q      , buf_Q                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                             );
+    not                                 not1      (intclk , CLK_N_delayed                               );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed         );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0      (Q      , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_1_V
+`define SKY130_FD_SC_HD__SDFRTN_1_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_1_V
+`define SKY130_FD_SC_HD__TAPVGND_1_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog wrapper for tapvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__tapvgnd base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__tapvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_V
+`define SKY130_FD_SC_HD__TAPVGND_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVGND_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_1_V
+`define SKY130_FD_SC_HD__O32A_1_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_4_V
+`define SKY130_FD_SC_HD__O32A_4_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_V
+`define SKY130_FD_SC_HD__O32A_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3      );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3      );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_2_V
+`define SKY130_FD_SC_HD__O32A_2_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O32A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_2_V
+`define SKY130_FD_SC_HD__A21O_2_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_2 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_V
+`define SKY130_FD_SC_HD__A21O_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2         );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2         );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_1_V
+`define SKY130_FD_SC_HD__A21O_1_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_1 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_4_V
+`define SKY130_FD_SC_HD__A21O_4_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_4 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_1_V
+`define SKY130_FD_SC_HD__SDFSTP_1_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_V
+`define SKY130_FD_SC_HD__SDFSTP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (SET    , SET_B                          );
+    sky130_fd_sc_hd__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (SET    , SET_B            );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE      );
+    sky130_fd_sc_hd__udp_dff$PS   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET);
+    buf                                       buf0      (Q      , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_4_V
+`define SKY130_FD_SC_HD__SDFSTP_4_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_2_V
+`define SKY130_FD_SC_HD__SDFSTP_2_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_8_V
+`define SKY130_FD_SC_HD__EBUFN_8_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_8 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_8 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_4_V
+`define SKY130_FD_SC_HD__EBUFN_4_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_4 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_4 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_2_V
+`define SKY130_FD_SC_HD__EBUFN_2_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_2 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_2 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_V
+`define SKY130_FD_SC_HD__EBUFN_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    bufif0                             bufif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    bufif0                             bufif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    //     Name     Output  Other arguments
+    bufif0 bufif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    bufif0 bufif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_1_V
+`define SKY130_FD_SC_HD__EBUFN_1_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_1 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_1 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EBUFN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_4_V
+`define SKY130_FD_SC_HD__O311A_4_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_2_V
+`define SKY130_FD_SC_HD__O311A_2_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_1_V
+`define SKY130_FD_SC_HD__O311A_1_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_V
+`define SKY130_FD_SC_HD__O311A_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1, C1);
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1, C1);
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //                                   Name      Output     Other arguments
+    or                                   or0      (or0_out_X, A, SLEEP             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X        , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //                                   Name      Output     Other arguments
+    or                                   or0      (or0_out_X, A, SLEEP             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X        , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    //  Name  Output  Other arguments
+    or  or0  (X     , A, SLEEP       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //  Name  Output  Other arguments
+    or  or0  (X     , A, SLEEP       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ *                    X = (A & !SLEEP)
+ *
+ * Verilog wrapper for lpflow_inputiso1p with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_inputiso1p base (
+        .X(X),
+        .A(A),
+        .SLEEP(SLEEP),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_inputiso1p base (
+        .X(X),
+        .A(A),
+        .SLEEP(SLEEP)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_4_V
+`define SKY130_FD_SC_HD__OR3_4_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_V
+`define SKY130_FD_SC_HD__OR3_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A, C              );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A, C              );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_1_V
+`define SKY130_FD_SC_HD__OR3_1_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_2_V
+`define SKY130_FD_SC_HD__OR3_2_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_2_V
+`define SKY130_FD_SC_HD__NAND2B_2_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_2 (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_2 (
+    Y  ,
+    A_N,
+    B
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_4_V
+`define SKY130_FD_SC_HD__NAND2B_4_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_4 (
+    Y  ,
+    A_N,
+    B
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_1_V
+`define SKY130_FD_SC_HD__NAND2B_1_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_1 (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_1 (
+    Y  ,
+    A_N,
+    B
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_V
+`define SKY130_FD_SC_HD__NAND2B_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B                    );
+    or                                 or0         (or0_out_Y        , not0_out, A_N        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B                    );
+    or                                 or0         (or0_out_Y        , not0_out, A_N        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+    Y  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B              );
+    or  or0  (or0_out_Y, not0_out, A_N  );
+    buf buf0 (Y        , or0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+    Y  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B              );
+    or  or0  (or0_out_Y, not0_out, A_N  );
+    buf buf0 (Y        , or0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_4_V
+`define SKY130_FD_SC_HD__O22A_4_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_2_V
+`define SKY130_FD_SC_HD__O22A_2_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_1_V
+`define SKY130_FD_SC_HD__O22A_1_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_V
+`define SKY130_FD_SC_HD__O22A_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1          );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1          );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O22A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_V
+`define SKY130_FD_SC_HD__A21OI_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_1_V
+`define SKY130_FD_SC_HD__A21OI_1_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_4_V
+`define SKY130_FD_SC_HD__A21OI_4_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_2_V
+`define SKY130_FD_SC_HD__A21OI_2_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_2_V
+`define SKY130_FD_SC_HD__AND2_2_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_4_V
+`define SKY130_FD_SC_HD__AND2_4_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_V
+`define SKY130_FD_SC_HD__AND2_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B                  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B           );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B           );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_0_V
+`define SKY130_FD_SC_HD__AND2_0_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_0 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_0 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_1_V
+`define SKY130_FD_SC_HD__AND2_1_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_0_V
+`define SKY130_FD_SC_HD__EINVN_0_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_0 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_0 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_4_V
+`define SKY130_FD_SC_HD__EINVN_4_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_4 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_4 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_1_V
+`define SKY130_FD_SC_HD__EINVN_1_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_V
+`define SKY130_FD_SC_HD__EINVN_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    notif0                             notif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    notif0                             notif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    //     Name     Output  Other arguments
+    notif0 notif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    notif0 notif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_2_V
+`define SKY130_FD_SC_HD__EINVN_2_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_2 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_2 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_8_V
+`define SKY130_FD_SC_HD__EINVN_8_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_8 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_8 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVN_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_V
+`define SKY130_FD_SC_HD__PROBE_P_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_8_V
+`define SKY130_FD_SC_HD__PROBE_P_8_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog wrapper for probe_p with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probe_p_8 (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+    sky130_fd_sc_hd__probe_p base (
+        .X(X),
+        .A(A),
+        .VGND(VGND),
+        .VNB(VNB),
+        .VPB(VPB),
+        .VPWR(VPWR)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probe_p_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply0 VGND;
+    supply0 VNB ;
+    supply1 VPB ;
+    supply1 VPWR;
+
+    sky130_fd_sc_hd__probe_p base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBE_P_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_1_V
+`define SKY130_FD_SC_HD__INV_1_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_2_V
+`define SKY130_FD_SC_HD__INV_2_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_6_V
+`define SKY130_FD_SC_HD__INV_6_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_6 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_6 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_16_V
+`define SKY130_FD_SC_HD__INV_16_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_4_V
+`define SKY130_FD_SC_HD__INV_4_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_4 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_4 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_8_V
+`define SKY130_FD_SC_HD__INV_8_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_8 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_12_V
+`define SKY130_FD_SC_HD__INV_12_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_12 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_12 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_V
+`define SKY130_FD_SC_HD__INV_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__INV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_2_V
+`define SKY130_FD_SC_HD__FA_2_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_4_V
+`define SKY130_FD_SC_HD__FA_4_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_1_V
+`define SKY130_FD_SC_HD__FA_1_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_V
+`define SKY130_FD_SC_HD__FA_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out             ;
+    wire and0_out            ;
+    wire and1_out            ;
+    wire and2_out            ;
+    wire nor0_out            ;
+    wire nor1_out            ;
+    wire or1_out_COUT        ;
+    wire pwrgood_pp0_out_COUT;
+    wire or2_out_SUM         ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    or                                 or0         (or0_out             , CIN, B                  );
+    and                                and0        (and0_out            , or0_out, A              );
+    and                                and1        (and1_out            , B, CIN                  );
+    or                                 or1         (or1_out_COUT        , and1_out, and0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT    );
+    and                                and2        (and2_out            , CIN, A, B               );
+    nor                                nor0        (nor0_out            , A, or0_out              );
+    nor                                nor1        (nor1_out            , nor0_out, COUT          );
+    or                                 or2         (or2_out_SUM         , nor1_out, and2_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out             ;
+    wire and0_out            ;
+    wire and1_out            ;
+    wire and2_out            ;
+    wire nor0_out            ;
+    wire nor1_out            ;
+    wire or1_out_COUT        ;
+    wire pwrgood_pp0_out_COUT;
+    wire or2_out_SUM         ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    or                                 or0         (or0_out             , CIN, B                  );
+    and                                and0        (and0_out            , or0_out, A              );
+    and                                and1        (and1_out            , B, CIN                  );
+    or                                 or1         (or1_out_COUT        , and1_out, and0_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT    );
+    and                                and2        (and2_out            , CIN, A, B               );
+    nor                                nor0        (nor0_out            , A, or0_out              );
+    nor                                nor1        (nor1_out            , nor0_out, COUT          );
+    or                                 or2         (or2_out_SUM         , nor1_out, and2_out      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Local signals
+    wire or0_out     ;
+    wire and0_out    ;
+    wire and1_out    ;
+    wire and2_out    ;
+    wire nor0_out    ;
+    wire nor1_out    ;
+    wire or1_out_COUT;
+    wire or2_out_SUM ;
+
+    //  Name  Output        Other arguments
+    or  or0  (or0_out     , CIN, B            );
+    and and0 (and0_out    , or0_out, A        );
+    and and1 (and1_out    , B, CIN            );
+    or  or1  (or1_out_COUT, and1_out, and0_out);
+    buf buf0 (COUT        , or1_out_COUT      );
+    and and2 (and2_out    , CIN, A, B         );
+    nor nor0 (nor0_out    , A, or0_out        );
+    nor nor1 (nor1_out    , nor0_out, COUT    );
+    or  or2  (or2_out_SUM , nor1_out, and2_out);
+    buf buf1 (SUM         , or2_out_SUM       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out     ;
+    wire and0_out    ;
+    wire and1_out    ;
+    wire and2_out    ;
+    wire nor0_out    ;
+    wire nor1_out    ;
+    wire or1_out_COUT;
+    wire or2_out_SUM ;
+
+    //  Name  Output        Other arguments
+    or  or0  (or0_out     , CIN, B            );
+    and and0 (and0_out    , or0_out, A        );
+    and and1 (and1_out    , B, CIN            );
+    or  or1  (or1_out_COUT, and1_out, and0_out);
+    buf buf0 (COUT        , or1_out_COUT      );
+    and and2 (and2_out    , CIN, A, B         );
+    nor nor0 (nor0_out    , A, or0_out        );
+    nor nor1 (nor1_out    , nor0_out, COUT    );
+    or  or2  (or2_out_SUM , nor1_out, and2_out);
+    buf buf1 (SUM         , or2_out_SUM       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog wrapper for tapvpwrvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__tapvpwrvgnd base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__tapvpwrvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAPVPWRVGND_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlygate4sd3 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlygate4sd3 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_2_V
+`define SKY130_FD_SC_HD__OR2B_2_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_2 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_2 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_4_V
+`define SKY130_FD_SC_HD__OR2B_4_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_4 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_4 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_1_V
+`define SKY130_FD_SC_HD__OR2B_1_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_1 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_1 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_V
+`define SKY130_FD_SC_HD__OR2B_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B_N                  );
+    or                                 or0         (or0_out_X        , not0_out, A          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B_N                  );
+    or                                 or0         (or0_out_X        , not0_out, A          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+    X  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B_N            );
+    or  or0  (or0_out_X, not0_out, A    );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+    X  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B_N            );
+    or  or0  (or0_out_X, not0_out, A    );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_1_V
+`define SKY130_FD_SC_HD__XNOR3_1_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_4_V
+`define SKY130_FD_SC_HD__XNOR3_4_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_2_V
+`define SKY130_FD_SC_HD__XNOR3_2_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_V
+`define SKY130_FD_SC_HD__XNOR3_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_X      , A, B, C                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_X      , A, B, C                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire xnor0_out_X;
+
+    //   Name   Output       Other arguments
+    xnor xnor0 (xnor0_out_X, A, B, C        );
+    buf  buf0  (X          , xnor0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xnor0_out_X;
+
+    //   Name   Output       Other arguments
+    xnor xnor0 (xnor0_out_X, A, B, C        );
+    buf  buf0  (X          , xnor0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_4_V
+`define SKY130_FD_SC_HD__DFXTP_4_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_4 (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_2_V
+`define SKY130_FD_SC_HD__DFXTP_2_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_2 (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_2 (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_V
+`define SKY130_FD_SC_HD__DFXTP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                 Delay       Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
+    buf                                            buf0 (Q     , buf_Q               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+    Q  ,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                         Delay       Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK         );
+    buf                                    buf0 (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+    Q  ,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_1_V
+`define SKY130_FD_SC_HD__DFXTP_1_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_1 (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_2_V
+`define SKY130_FD_SC_HD__DLRTP_2_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog wrapper for dlrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_2 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_2 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_4_V
+`define SKY130_FD_SC_HD__DLRTP_4_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog wrapper for dlrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_V
+`define SKY130_FD_SC_HD__DLRTP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                                     Delay       Name     Output  Other arguments
+    not                                                not0    (RESET , RESET_B                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q     , buf_Q                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                             Delay       Name     Output  Other arguments
+    not                                        not0    (RESET , RESET_B        );
+    sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+    buf                                        buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_1_V
+`define SKY130_FD_SC_HD__DLRTP_1_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog wrapper for dlrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_V
+`define SKY130_FD_SC_HD__FAHCIN_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire ci                  ;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    not                                not0        (ci                  , CIN                     );
+    xor                                xor0        (xor0_out_SUM        , A, B, ci                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, ci                   );
+    and                                and2        (b_ci                , B, ci                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire ci                  ;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    not                                not0        (ci                  , CIN                     );
+    xor                                xor0        (xor0_out_SUM        , A, B, ci                );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, ci                   );
+    and                                and2        (b_ci                , B, ci                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Local signals
+    wire ci          ;
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    not not0 (ci          , CIN            );
+    xor xor0 (xor0_out_SUM, A, B, ci       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, ci          );
+    and and2 (b_ci        , B, ci          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire ci          ;
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    not not0 (ci          , CIN            );
+    xor xor0 (xor0_out_SUM, A, B, ci       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, ci          );
+    and and2 (b_ci        , B, ci          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_1_V
+`define SKY130_FD_SC_HD__FAHCIN_1_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog wrapper for fahcin with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcin_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__fahcin base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcin_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fahcin base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__FAHCIN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_2_V
+`define SKY130_FD_SC_HD__DLRBP_2_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_1_V
+`define SKY130_FD_SC_HD__DLRBP_1_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_1 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_1 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_V
+`define SKY130_FD_SC_HD__DLRBP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                                     Delay       Name     Output  Other arguments
+    not                                                not0    (RESET , RESET_B                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q     , buf_Q                       );
+    not                                                not1    (Q_N   , buf_Q                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+    not                                    not1    (Q_N   , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                             Delay       Name     Output  Other arguments
+    not                                        not0    (RESET , RESET_B        );
+    sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+    buf                                        buf0    (Q     , buf_Q          );
+    not                                        not1    (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+    not                                    not1    (Q_N   , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out_Y    ;
+    wire pwrgood0_out_Y;
+
+    //                                   Name      Output          Other arguments
+    not                                  not0     (not0_out_Y    , A                      );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
+    buf                                  buf0     (Y             , pwrgood0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out_Y    ;
+    wire pwrgood0_out_Y;
+
+    //                                   Name      Output          Other arguments
+    not                                  not0     (not0_out_Y    , A                      );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
+    buf                                  buf0     (Y             , pwrgood0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
+    Y    ,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Y    ;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_2_V
+`define SKY130_FD_SC_HD__O21BAI_2_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_4_V
+`define SKY130_FD_SC_HD__O21BAI_4_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_V
+`define SKY130_FD_SC_HD__O21BAI_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                   );
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , b, or0_out             );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                   );
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , b, or0_out             );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire b          ;
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (b          , B1_N           );
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, b, or0_out     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire b          ;
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (b          , B1_N           );
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, b, or0_out     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_1_V
+`define SKY130_FD_SC_HD__O21BAI_1_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21BAI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_2_V
+`define SKY130_FD_SC_HD__A2BB2OI_2_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_1_V
+`define SKY130_FD_SC_HD__A2BB2OI_1_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_4_V
+`define SKY130_FD_SC_HD__A2BB2OI_4_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_V
+`define SKY130_FD_SC_HD__A2BB2OI_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire nor1_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    nor                                nor0        (nor0_out         , A1_N, A2_N            );
+    nor                                nor1        (nor1_out_Y       , nor0_out, and0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire nor1_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    nor                                nor0        (nor0_out         , A1_N, A2_N            );
+    nor                                nor1        (nor1_out_Y       , nor0_out, and0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out  ;
+    wire nor1_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2            );
+    nor nor0 (nor0_out  , A1_N, A2_N        );
+    nor nor1 (nor1_out_Y, nor0_out, and0_out);
+    buf buf0 (Y         , nor1_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out  ;
+    wire nor1_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2            );
+    nor nor0 (nor0_out  , A1_N, A2_N        );
+    nor nor1 (nor1_out_Y, nor0_out, and0_out);
+    buf buf0 (Y         , nor1_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_2_V
+`define SKY130_FD_SC_HD__A2BB2O_2_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_V
+`define SKY130_FD_SC_HD__A2BB2O_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    nor                                nor0        (nor0_out         , A1_N, A2_N           );
+    or                                 or0         (or0_out_X        , nor0_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    nor                                nor0        (nor0_out         , A1_N, A2_N           );
+    or                                 or0         (or0_out_X        , nor0_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire and0_out ;
+    wire nor0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    nor nor0 (nor0_out , A1_N, A2_N        );
+    or  or0  (or0_out_X, nor0_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire nor0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    nor nor0 (nor0_out , A1_N, A2_N        );
+    or  or0  (or0_out_X, nor0_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_1_V
+`define SKY130_FD_SC_HD__A2BB2O_1_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_4_V
+`define SKY130_FD_SC_HD__A2BB2O_4_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2BB2O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_1_V
+`define SKY130_FD_SC_HD__O2111AI_1_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_2_V
+`define SKY130_FD_SC_HD__O2111AI_2_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_4_V
+`define SKY130_FD_SC_HD__O2111AI_4_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_V
+`define SKY130_FD_SC_HD__O2111AI_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , C1, B1, D1, or0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , C1, B1, D1, or0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1             );
+    nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+    buf  buf0  (Y          , nand0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1             );
+    nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+    buf  buf0  (Y          , nand0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2111AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_4_V
+`define SKY130_FD_SC_HD__A22OI_4_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_V
+`define SKY130_FD_SC_HD__A22OI_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1              );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1              );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_1_V
+`define SKY130_FD_SC_HD__A22OI_1_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_2_V
+`define SKY130_FD_SC_HD__A22OI_2_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_1_V
+`define SKY130_FD_SC_HD__DFBBN_1_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_V
+`define SKY130_FD_SC_HD__DFBBN_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire CLK  ;
+    wire buf_Q;
+
+    //                                   Delay       Name  Output  Other arguments
+    not                                              not0 (RESET , RESET_B                         );
+    not                                              not1 (SET   , SET_B                           );
+    not                                              not2 (CLK   , CLK_N                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+    buf                                              buf0 (Q     , buf_Q                           );
+    not                                              not3 (Q_N   , buf_Q                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    wire CLK_N_delayed  ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                 );
+    not                                  not1 (SET   , SET_B_delayed                                   );
+    not                                  not2 (CLK   , CLK_N_delayed                                   );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                           );
+    not                                  not3 (Q_N   , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire CLK  ;
+    wire buf_Q;
+
+    //                           Delay       Name  Output  Other arguments
+    not                                      not0 (RESET , RESET_B           );
+    not                                      not1 (SET   , SET_B             );
+    not                                      not2 (CLK   , CLK_N             );
+    sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+    buf                                      buf0 (Q     , buf_Q             );
+    not                                      not3 (Q_N   , buf_Q             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    wire CLK_N_delayed  ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                 );
+    not                                  not1 (SET   , SET_B_delayed                                   );
+    not                                  not2 (CLK   , CLK_N_delayed                                   );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                           );
+    not                                  not3 (Q_N   , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_2_V
+`define SKY130_FD_SC_HD__DFBBN_2_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFBBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_1_V
+`define SKY130_FD_SC_HD__O21A_1_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_1 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_V
+`define SKY130_FD_SC_HD__O21A_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_4_V
+`define SKY130_FD_SC_HD__O21A_4_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_4 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_2_V
+`define SKY130_FD_SC_HD__O21A_2_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_2 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_1_V
+`define SKY130_FD_SC_HD__SDFXBP_1_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_V
+`define SKY130_FD_SC_HD__SDFXBP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, D, SCD, SCE               );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_2_V
+`define SKY130_FD_SC_HD__SDFXBP_2_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_8_V
+`define SKY130_FD_SC_HD__PROBEC_P_8_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog wrapper for probec_p with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probec_p_8 (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+    sky130_fd_sc_hd__probec_p base (
+        .X(X),
+        .A(A),
+        .VGND(VGND),
+        .VNB(VNB),
+        .VPB(VPB),
+        .VPWR(VPWR)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probec_p_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply0 VGND;
+    supply0 VNB ;
+    supply1 VPB ;
+    supply1 VPWR;
+
+    sky130_fd_sc_hd__probec_p base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_V
+`define SKY130_FD_SC_HD__PROBEC_P_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+    X   ,
+    A   ,
+    VGND,
+    VNB ,
+    VPB ,
+    VPWR
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VGND;
+    input  VNB ;
+    input  VPB ;
+    input  VPWR;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__PROBEC_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_V
+`define SKY130_FD_SC_HD__O31AI_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_1_V
+`define SKY130_FD_SC_HD__O31AI_1_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_2_V
+`define SKY130_FD_SC_HD__O31AI_2_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_4_V
+`define SKY130_FD_SC_HD__O31AI_4_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_V
+`define SKY130_FD_SC_HD__DLXBN_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE ;
+    wire buf_Q;
+
+    //                                    Delay       Name     Output  Other arguments
+    not                                               not0    (GATE  , GATE_N               );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                               buf0    (Q     , buf_Q                );
+    not                                               not1    (Q_N   , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+    wire 1             ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1 );
+    buf                                   buf0    (Q     , buf_Q                                );
+    not                                   not1    (Q_N   , buf_Q                                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Local signals
+    wire GATE ;
+    wire buf_Q;
+
+    //                            Delay       Name     Output  Other arguments
+    not                                       not0    (GATE  , GATE_N         );
+    sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE        );
+    buf                                       buf0    (Q     , buf_Q          );
+    not                                       not1    (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+    //kunal wire 1             ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1 );
+    buf                                   buf0    (Q     , buf_Q                                );
+    not                                   not1    (Q_N   , buf_Q                                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_1_V
+`define SKY130_FD_SC_HD__DLXBN_1_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_1 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_1 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_2_V
+`define SKY130_FD_SC_HD__DLXBN_2_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_2 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_hd__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_2 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A222OI_V
+`define SKY130_FD_SC_HD__A222OI_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire nand2_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                         );
+    nand                               nand1       (nand1_out        , B2, B1                         );
+    nand                               nand2       (nand2_out        , C2, C1                         );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out, nand2_out);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND         );
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire nand2_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                         );
+    nand                               nand1       (nand1_out        , B2, B1                         );
+    nand                               nand2       (nand2_out        , C2, C1                         );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out, nand2_out);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND         );
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire nand2_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1                         );
+    nand nand1 (nand1_out , B2, B1                         );
+    nand nand2 (nand2_out , C2, C1                         );
+    and  and0  (and0_out_Y, nand0_out, nand1_out, nand2_out);
+    buf  buf0  (Y         , and0_out_Y                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire nand2_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1                         );
+    nand nand1 (nand1_out , B2, B1                         );
+    nand nand2 (nand2_out , C2, C1                         );
+    and  and0  (and0_out_Y, nand0_out, nand1_out, nand2_out);
+    buf  buf0  (Y         , and0_out_Y                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A222OI_1_V
+`define SKY130_FD_SC_HD__A222OI_1_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog wrapper for a222oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a222oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a222oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a222oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a222oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A222OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_2_V
+`define SKY130_FD_SC_HD__DLRBN_2_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_V
+`define SKY130_FD_SC_HD__DLRBN_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                                     Delay       Name     Output   Other arguments
+    not                                                not0    (RESET  , RESET_B                        );
+    not                                                not1    (intgate, GATE_N                         );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q      , buf_Q                          );
+    not                                                not2    (Q_N    , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+    not                                    not2    (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                             Delay       Name     Output   Other arguments
+    not                                        not0    (RESET  , RESET_B          );
+    not                                        not1    (intgate, GATE_N           );
+    sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET);
+    buf                                        buf0    (Q      , buf_Q            );
+    not                                        not2    (Q_N    , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+    not                                    not2    (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_1_V
+`define SKY130_FD_SC_HD__DLRBN_1_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_1 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_1 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLRBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_4_V
+`define SKY130_FD_SC_HD__NAND3B_4_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_4 (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_1_V
+`define SKY130_FD_SC_HD__NAND3B_1_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_1 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_1 (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_V
+`define SKY130_FD_SC_HD__NAND3B_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , B, not0_out, C         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , B, not0_out, C         );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N            );
+    nand nand0 (nand0_out_Y, B, not0_out, C );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N            );
+    nand nand0 (nand0_out_Y, B, not0_out, C );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_2_V
+`define SKY130_FD_SC_HD__NAND3B_2_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_2 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_2 (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NAND3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire sleepn    ;
+    wire and0_out_X;
+
+    //                                   Name      Output      Other arguments
+    not                                  not0     (sleepn    , SLEEP                 );
+    and                                  and0     (and0_out_X, A, sleepn             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X         , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire sleepn    ;
+    wire and0_out_X;
+
+    //                                   Name      Output      Other arguments
+    not                                  not0     (sleepn    , SLEEP                 );
+    and                                  and0     (and0_out_X, A, sleepn             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X         , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    // Local signals
+    wire sleepn;
+
+    //  Name  Output  Other arguments
+    not not0 (sleepn, SLEEP          );
+    and and0 (X     , A, sleepn      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire sleepn;
+
+    //  Name  Output  Other arguments
+    not not0 (sleepn, SLEEP          );
+    and and0 (X     , A, sleepn      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ *                    X = (A & !SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso0p with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
+    X    ,
+    A    ,
+    SLEEP,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_inputiso0p base (
+        .X(X),
+        .A(A),
+        .SLEEP(SLEEP),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
+    X    ,
+    A    ,
+    SLEEP
+);
+
+    output X    ;
+    input  A    ;
+    input  SLEEP;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_inputiso0p base (
+        .X(X),
+        .A(A),
+        .SLEEP(SLEEP)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_8_V
+`define SKY130_FD_SC_HD__BUFBUF_8_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__bufbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__bufbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_V
+`define SKY130_FD_SC_HD__BUFBUF_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_16_V
+`define SKY130_FD_SC_HD__BUFBUF_16_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__bufbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__bufbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUFBUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_2_V
+`define SKY130_FD_SC_HD__SDFBBN_2_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_1_V
+`define SKY130_FD_SC_HD__SDFBBN_1_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_V
+`define SKY130_FD_SC_HD__SDFBBN_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire CLK    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                   Delay       Name       Output   Other arguments
+    not                                              not0      (RESET  , RESET_B                               );
+    not                                              not1      (SET    , SET_B                                 );
+    not                                              not2      (CLK    , CLK_N                                 );
+    sky130_fd_sc_hd__udp_mux_2to1                    mux_2to10 (mux_out, D, SCD, SCE                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out, , VPWR, VGND);
+    buf                                              buf0      (Q      , buf_Q                                 );
+    not                                              not3      (Q_N    , buf_Q                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_N_delayed  ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                               );
+    not                                  not1      (SET    , SET_B_delayed                                 );
+    not                                  not2      (CLK    , CLK_N_delayed                                 );
+    sky130_fd_sc_hd__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                         );
+    not                                  not3      (Q_N    , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire CLK    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B                 );
+    not                                       not1      (SET    , SET_B                   );
+    not                                       not2      (CLK    , CLK_N                   );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE             );
+    sky130_fd_sc_hd__udp_dff$NSR  `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out);
+    buf                                       buf0      (Q      , buf_Q                   );
+    not                                       not3      (Q_N    , buf_Q                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_N_delayed  ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                               );
+    not                                  not1      (SET    , SET_B_delayed                                 );
+    not                                  not2      (CLK    , CLK_N_delayed                                 );
+    sky130_fd_sc_hd__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                         );
+    not                                  not3      (Q_N    , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_1_V
+`define SKY130_FD_SC_HD__O41A_1_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_V
+`define SKY130_FD_SC_HD__O41A_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1        );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1        );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A4, A3, A2, A1 );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A4, A3, A2, A1 );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_2_V
+`define SKY130_FD_SC_HD__O41A_2_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_4_V
+`define SKY130_FD_SC_HD__O41A_4_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O41A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_4_V
+`define SKY130_FD_SC_HD__A31OI_4_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_1_V
+`define SKY130_FD_SC_HD__A31OI_1_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_V
+`define SKY130_FD_SC_HD__A31OI_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2     );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2     );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_2_V
+`define SKY130_FD_SC_HD__A31OI_2_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A31OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s6s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlymetal6s6s base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlymetal6s6s base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_1_V
+`define SKY130_FD_SC_HD__AND4B_1_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_1 (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_V
+`define SKY130_FD_SC_HD__AND4B_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B, C, D     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B, C, D     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N              );
+    and and0 (and0_out_X, not0_out, B, C, D);
+    buf buf0 (X         , and0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N              );
+    and and0 (and0_out_X, not0_out, B, C, D);
+    buf buf0 (X         , and0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_2_V
+`define SKY130_FD_SC_HD__AND4B_2_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_2 (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_4_V
+`define SKY130_FD_SC_HD__AND4B_4_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_4 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_4 (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB     ,
+    VNB
+);
+
+    // Module ports
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    input  VNB     ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND     );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB     ,
+    VNB
+);
+
+    // Module ports
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    input  VNB     ;
+
+    // Local signals
+    wire pwrgood0_out_A;
+    wire buf0_out_X    ;
+
+    //                                   Name      Output          Other arguments
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND     );
+    buf                                  buf0     (buf0_out_X    , pwrgood0_out_A        );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X             , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ *                          well on input buffer, no taps,
+ *                          double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
+    X       ,
+    A       ,
+    LOWLVPWR,
+    VPWR    ,
+    VGND    ,
+    VPB     ,
+    VNB
+);
+
+    output X       ;
+    input  A       ;
+    input  LOWLVPWR;
+    input  VPWR    ;
+    input  VGND    ;
+    input  VPB     ;
+    input  VNB     ;
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
+        .X(X),
+        .A(A),
+        .LOWLVPWR(LOWLVPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    wire    LOWLVPWR;
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+
+/**
+ * lpflow_bleeder: Current bleeder (weak pulldown to ground).
+ *
+ * Verilog wrapper for lpflow_bleeder with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder_1 (
+    SHORT,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input SHORT;
+    inout VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__lpflow_bleeder base (
+        .SHORT(SHORT),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder_1 (
+    SHORT
+);
+
+    input SHORT;
+
+    // Voltage supply signals
+    wire    VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_bleeder base (
+        .SHORT(SHORT)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+
+/**
+ * lpflow_bleeder: Current bleeder (weak pulldown to ground).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+    SHORT,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input SHORT;
+    inout VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif	// SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+    SHORT,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input SHORT;
+    inout VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+
+    wire gnd;
+
+    pulldown(gnd);
+    bufif1 (VPWR, gnd, SHORT);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif 	// SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+    SHORT
+);
+
+    input SHORT;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+    SHORT
+);
+
+    input SHORT;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif	// SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_1_V
+`define SKY130_FD_SC_HD__O221A_1_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_V
+`define SKY130_FD_SC_HD__O221A_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B2, B1                );
+    or                                 or1         (or1_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out, C1  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B2, B1                );
+    or                                 or1         (or1_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out, C1  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , B2, B1              );
+    or  or1  (or1_out   , A2, A1              );
+    and and0 (and0_out_X, or0_out, or1_out, C1);
+    buf buf0 (X         , and0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , B2, B1              );
+    or  or1  (or1_out   , A2, A1              );
+    and and0 (and0_out_X, or0_out, or1_out, C1);
+    buf buf0 (X         , and0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_4_V
+`define SKY130_FD_SC_HD__O221A_4_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_2_V
+`define SKY130_FD_SC_HD__O221A_2_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O221A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_1_V
+`define SKY130_FD_SC_HD__SDFBBP_1_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_V
+`define SKY130_FD_SC_HD__SDFBBP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                   Delay       Name       Output   Other arguments
+    not                                              not0      (RESET  , RESET_B                               );
+    not                                              not1      (SET    , SET_B                                 );
+    sky130_fd_sc_hd__udp_mux_2to1                    mux_2to10 (mux_out, D, SCD, SCE                           );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out, , VPWR, VGND);
+    buf                                              buf0      (Q      , buf_Q                                 );
+    not                                              not2      (Q_N    , buf_Q                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_delayed    ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                                       );
+    not                                  not1      (SET    , SET_B_delayed                                         );
+    sky130_fd_sc_hd__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed                   );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                                 );
+    not                                  not2      (Q_N    , buf_Q                                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B                 );
+    not                                       not1      (SET    , SET_B                   );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE             );
+    sky130_fd_sc_hd__udp_dff$NSR  `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out);
+    buf                                       buf0      (Q      , buf_Q                   );
+    not                                       not2      (Q_N    , buf_Q                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_delayed    ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                                       );
+    not                                  not1      (SET    , SET_B_delayed                                         );
+    sky130_fd_sc_hd__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed                   );
+    sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                                 );
+    not                                  not2      (Q_N    , buf_Q                                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFBBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_4_V
+`define SKY130_FD_SC_HD__NOR4_4_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_1_V
+`define SKY130_FD_SC_HD__NOR4_1_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_1 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_V
+`define SKY130_FD_SC_HD__NOR4_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , A, B, C, D            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , A, B, C, D            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B, C, D     );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B, C, D     );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_2_V
+`define SKY130_FD_SC_HD__NOR4_2_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_2 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_4_V
+`define SKY130_FD_SC_HD__O31A_4_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_2_V
+`define SKY130_FD_SC_HD__O31A_2_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_1_V
+`define SKY130_FD_SC_HD__O31A_1_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_V
+`define SKY130_FD_SC_HD__O31A_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O31A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_V
+`define SKY130_FD_SC_HD__O211A_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1, C1);
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1, C1);
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_1_V
+`define SKY130_FD_SC_HD__O211A_1_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_2_V
+`define SKY130_FD_SC_HD__O211A_2_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_4_V
+`define SKY130_FD_SC_HD__O211A_4_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_1_V
+`define SKY130_FD_SC_HD__O211AI_1_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_V
+`define SKY130_FD_SC_HD__O211AI_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, C1, or0_out, B1);
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, C1, or0_out, B1);
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_4_V
+`define SKY130_FD_SC_HD__O211AI_4_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_2_V
+`define SKY130_FD_SC_HD__O211AI_2_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O211AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+    Q      ,
+    D      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                     Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D, SLEEP_B, 1'b0, VPWR, VGND);
+    buf                                    buf0    (Q     , buf_Q                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+    Q      ,
+    D      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire SLEEP_B_delayed;
+    wire D_delayed      ;
+
+    //                                     Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
+    buf                                    buf0    (Q     , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+    Q      ,
+    D      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+
+    // Local signals
+    wire buf_Q;
+
+    //                             Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B     );
+    buf                            buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+    Q      ,
+    D      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire SLEEP_B_delayed;
+    wire D_delayed      ;
+
+    //                                     Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
+    buf                                    buf0    (Q     , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog wrapper for lpflow_inputisolatch with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
+    Q      ,
+    D      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__lpflow_inputisolatch base (
+        .Q(Q),
+        .D(D),
+        .SLEEP_B(SLEEP_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
+    Q      ,
+    D      ,
+    SLEEP_B
+);
+
+    output Q      ;
+    input  D      ;
+    input  SLEEP_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_inputisolatch base (
+        .Q(Q),
+        .D(D),
+        .SLEEP_B(SLEEP_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_V
+`define SKY130_FD_SC_HD__SDFSBP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (SET    , SET_B                          );
+    sky130_fd_sc_hd__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                    );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                          );
+    not                                             not1      (Q_N    , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+    not                                 not1      (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (SET    , SET_B            );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE      );
+    sky130_fd_sc_hd__udp_dff$PS   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET);
+    buf                                       buf0      (Q      , buf_Q            );
+    not                                       not1      (Q_N    , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+    not                                 not1      (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_1_V
+`define SKY130_FD_SC_HD__SDFSBP_1_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_2_V
+`define SKY130_FD_SC_HD__SDFSBP_2_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFSBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out      ;
+    wire and0_out_X    ;
+    wire pwrgood0_out_X;
+
+    //                                     Name      Output          Other arguments
+    not                                    not0     (not0_out      , SLEEP                        );
+    and                                    and0     (and0_out_X    , not0_out, A                  );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
+    buf                                    buf0     (X             , pwrgood0_out_X               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out      ;
+    wire and0_out_X    ;
+    wire pwrgood0_out_X;
+
+    //                                     Name      Output          Other arguments
+    not                                    not0     (not0_out      , SLEEP                        );
+    and                                    and0     (and0_out_X    , not0_out, A                  );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
+    buf                                    buf0     (X             , pwrgood0_out_X               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+    X    ,
+    SLEEP,
+    A
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , SLEEP          );
+    and and0 (and0_out_X, not0_out, A    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+    X    ,
+    SLEEP,
+    A
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , SLEEP          );
+    and and0 (and0_out_X, not0_out, A    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ *                   X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
+    X    ,
+    SLEEP,
+    A    ,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrc base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_12_V
+`define SKY130_FD_SC_HD__BUF_12_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_12 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_12 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_16_V
+`define SKY130_FD_SC_HD__BUF_16_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_V
+`define SKY130_FD_SC_HD__BUF_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_4_V
+`define SKY130_FD_SC_HD__BUF_4_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_4 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_1_V
+`define SKY130_FD_SC_HD__BUF_1_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_6_V
+`define SKY130_FD_SC_HD__BUF_6_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_6 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_6 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_2_V
+`define SKY130_FD_SC_HD__BUF_2_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_8_V
+`define SKY130_FD_SC_HD__BUF_8_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__BUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s15 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s15 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s15 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s15 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s15 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s15 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_1_V
+`define SKY130_FD_SC_HD__SEDFXTP_1_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_4_V
+`define SKY130_FD_SC_HD__SEDFXTP_4_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_4 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_2_V
+`define SKY130_FD_SC_HD__SEDFXTP_2_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_2 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_2 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_V
+`define SKY130_FD_SC_HD__SEDFXTP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, de_d, SCD, SCE            );
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to11 (de_d   , buf_Q, D, DE              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, de_d, SCD, SCE );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to11 (de_d   , buf_Q, D, DE   );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_V
+`define SKY130_FD_SC_HD__DECAP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_3_V
+`define SKY130_FD_SC_HD__DECAP_3_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 3 units (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_3 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_3 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_4_V
+`define SKY130_FD_SC_HD__DECAP_4_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_4 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_6_V
+`define SKY130_FD_SC_HD__DECAP_6_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_6 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_6 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_12_V
+`define SKY130_FD_SC_HD__DECAP_12_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_12 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_12 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_8_V
+`define SKY130_FD_SC_HD__DECAP_8_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_8 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_8 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DECAP_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_2_V
+`define SKY130_FD_SC_HD__AND4_2_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_2 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_1_V
+`define SKY130_FD_SC_HD__AND4_1_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_1 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_V
+`define SKY130_FD_SC_HD__AND4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B, C, D            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B, C, D            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B, C, D     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B, C, D     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_4_V
+`define SKY130_FD_SC_HD__AND4_4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__AND4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s2s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlymetal6s2s base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlymetal6s2s base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYMETAL6S2S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_V
+`define SKY130_FD_SC_HD__MAJ3_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or1_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B, A                 );
+    and                                and0        (and0_out         , or0_out, C           );
+    and                                and1        (and1_out         , A, B                 );
+    or                                 or1         (or1_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or1_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B, A                 );
+    and                                and0        (and0_out         , or0_out, C           );
+    and                                and1        (and1_out         , A, B                 );
+    or                                 or1         (or1_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire or0_out  ;
+    wire and0_out ;
+    wire and1_out ;
+    wire or1_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out  , B, A              );
+    and and0 (and0_out , or0_out, C        );
+    and and1 (and1_out , A, B              );
+    or  or1  (or1_out_X, and1_out, and0_out);
+    buf buf0 (X        , or1_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out  ;
+    wire and0_out ;
+    wire and1_out ;
+    wire or1_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out  , B, A              );
+    and and0 (and0_out , or0_out, C        );
+    and and1 (and1_out , A, B              );
+    or  or1  (or1_out_X, and1_out, and0_out);
+    buf buf0 (X        , or1_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_4_V
+`define SKY130_FD_SC_HD__MAJ3_4_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_1_V
+`define SKY130_FD_SC_HD__MAJ3_1_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_2_V
+`define SKY130_FD_SC_HD__MAJ3_2_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__MAJ3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso0n with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__lpflow_inputiso0n base (
+        .X(X),
+        .A(A),
+        .SLEEP_B(SLEEP_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_inputiso0n base (
+        .X(X),
+        .A(A),
+        .SLEEP_B(SLEEP_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //                                   Name      Output      Other arguments
+    and                                  and0     (and0_out_X, A, SLEEP_B            );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X         , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //                                   Name      Output      Other arguments
+    and                                  and0     (and0_out_X, A, SLEEP_B            );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X         , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    //  Name  Output  Other arguments
+    and and0 (X     , A, SLEEP_B     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //  Name  Output  Other arguments
+    and and0 (X     , A, SLEEP_B     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_1_V
+`define SKY130_FD_SC_HD__O2BB2A_1_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_2_V
+`define SKY130_FD_SC_HD__O2BB2A_2_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_4_V
+`define SKY130_FD_SC_HD__O2BB2A_4_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_V
+`define SKY130_FD_SC_HD__O2BB2A_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N            );
+    or                                 or0         (or0_out          , B2, B1                );
+    and                                and0        (and0_out_X       , nand0_out, or0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N            );
+    or                                 or0         (or0_out          , B2, B1                );
+    and                                and0        (and0_out_X       , nand0_out, or0_out    );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire nand0_out ;
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2_N, A1_N        );
+    or   or0   (or0_out   , B2, B1            );
+    and  and0  (and0_out_X, nand0_out, or0_out);
+    buf  buf0  (X         , and0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2_N, A1_N        );
+    or   or0   (or0_out   , B2, B1            );
+    and  and0  (and0_out_X, nand0_out, or0_out);
+    buf  buf0  (X         , and0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_V
+`define SKY130_FD_SC_HD__XOR3_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, A, B, C        );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, A, B, C        );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_1_V
+`define SKY130_FD_SC_HD__XOR3_1_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_2_V
+`define SKY130_FD_SC_HD__XOR3_2_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_4_V
+`define SKY130_FD_SC_HD__XOR3_4_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_4_V
+`define SKY130_FD_SC_HD__OR4_4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_V
+`define SKY130_FD_SC_HD__OR4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , D, C, B, A           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , D, C, B, A           );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, D, C, B, A     );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, D, C, B, A     );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_2_V
+`define SKY130_FD_SC_HD__OR4_2_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_2 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_1_V
+`define SKY130_FD_SC_HD__OR4_1_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_1 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__OR4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_V
+`define SKY130_FD_SC_HD__CLKINVLP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_2_V
+`define SKY130_FD_SC_HD__CLKINVLP_2_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog wrapper for clkinvlp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinvlp base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinvlp base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_4_V
+`define SKY130_FD_SC_HD__CLKINVLP_4_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog wrapper for clkinvlp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_4 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkinvlp base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_4 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkinvlp base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKINVLP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_V
+`define SKY130_FD_SC_HD__SDFRTP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                          );
+    sky130_fd_sc_hd__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                      );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B            );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE        );
+    sky130_fd_sc_hd__udp_dff$PR   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET);
+    buf                                       buf0      (Q      , buf_Q              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_hd__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_2_V
+`define SKY130_FD_SC_HD__SDFRTP_2_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_4_V
+`define SKY130_FD_SC_HD__SDFRTP_4_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_1_V
+`define SKY130_FD_SC_HD__SDFRTP_1_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SDFRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd1 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlygate4sd1 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlygate4sd1 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLYGATE4SD1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_V
+`define SKY130_FD_SC_HD__O21AI_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_2_V
+`define SKY130_FD_SC_HD__O21AI_2_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_1_V
+`define SKY130_FD_SC_HD__O21AI_1_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_4_V
+`define SKY130_FD_SC_HD__O21AI_4_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_0_V
+`define SKY130_FD_SC_HD__O21AI_0_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_0 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_0 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O21AI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_2_V
+`define SKY130_FD_SC_HD__TAP_2_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog wrapper for tap with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__tap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__tap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_V
+`define SKY130_FD_SC_HD__TAP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_1_V
+`define SKY130_FD_SC_HD__TAP_1_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog wrapper for tap with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hd__tap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__tap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s50 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s50 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s50 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog wrapper for clkdlybuf4s50 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkdlybuf4s50 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkdlybuf4s50 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ *                gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_1_V
+`define SKY130_FD_SC_HD__A21BO_1_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_2_V
+`define SKY130_FD_SC_HD__A21BO_2_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_V
+`define SKY130_FD_SC_HD__A21BO_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                 );
+    nand                               nand1       (nand1_out_X      , B1_N, nand0_out        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                 );
+    nand                               nand1       (nand1_out_X      , B1_N, nand0_out        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire nand0_out  ;
+    wire nand1_out_X;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2, A1         );
+    nand nand1 (nand1_out_X, B1_N, nand0_out);
+    buf  buf0  (X          , nand1_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire nand1_out_X;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2, A1         );
+    nand nand1 (nand1_out_X, B1_N, nand0_out);
+    buf  buf0  (X          , nand1_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_4_V
+`define SKY130_FD_SC_HD__A21BO_4_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A21BO_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_V
+`define SKY130_FD_SC_HD__A22O_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    and                                and1        (and1_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    and                                and1        (and1_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    and and1 (and1_out , A1, A2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    and and1 (and1_out , A1, A2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_2_V
+`define SKY130_FD_SC_HD__A22O_2_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_1_V
+`define SKY130_FD_SC_HD__A22O_1_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_4_V
+`define SKY130_FD_SC_HD__A22O_4_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A22O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTP_1_V
+`define SKY130_FD_SC_HD__DLXTP_1_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTP_V
+`define SKY130_FD_SC_HD__DLXTP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Local signals
+    wire buf_Q;
+
+    //                            Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE        );
+    buf                           buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DLXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_1_V
+`define SKY130_FD_SC_HD__NOR4B_1_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_V
+`define SKY130_FD_SC_HD__NOR4B_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                   );
+    nor                                nor0        (nor0_out_Y       , A, B, C, not0_out     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                   );
+    nor                                nor0        (nor0_out_Y       , A, B, C, not0_out     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Local signals
+    wire not0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , D_N              );
+    nor nor0 (nor0_out_Y, A, B, C, not0_out);
+    buf buf0 (Y         , nor0_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , D_N              );
+    nor nor0 (nor0_out_Y, A, B, C, not0_out);
+    buf buf0 (Y         , nor0_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_4_V
+`define SKY130_FD_SC_HD__NOR4B_4_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_4 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_2_V
+`define SKY130_FD_SC_HD__NOR4B_2_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__NOR4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_4_V
+`define SKY130_FD_SC_HD__O311AI_4_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_V
+`define SKY130_FD_SC_HD__O311AI_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, C1, or0_out, B1);
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, C1, or0_out, B1);
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_0_V
+`define SKY130_FD_SC_HD__O311AI_0_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_0 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_0 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_1_V
+`define SKY130_FD_SC_HD__O311AI_1_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_2_V
+`define SKY130_FD_SC_HD__O311AI_2_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O311AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTN_1_V
+`define SKY130_FD_SC_HD__DFRTN_1_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__dfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__dfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTN_V
+`define SKY130_FD_SC_HD__DFRTN_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q ;
+    wire RESET ;
+    wire intclk;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (RESET , RESET_B                       );
+    not                                             not1 (intclk, CLK_N                         );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                               );
+    not                                 not1 (intclk, CLK_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q ;
+    wire RESET ;
+    wire intclk;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (RESET , RESET_B         );
+    not                                     not1 (intclk, CLK_N           );
+    sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
+    buf                                     buf0 (Q     , buf_Q           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                               );
+    not                                 not1 (intclk, CLK_N_delayed                                 );
+    sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__DFRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_16_V
+`define SKY130_FD_SC_HD__CLKBUF_16_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_1_V
+`define SKY130_FD_SC_HD__CLKBUF_1_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_4_V
+`define SKY130_FD_SC_HD__CLKBUF_4_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_4 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_V
+`define SKY130_FD_SC_HD__CLKBUF_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_2_V
+`define SKY130_FD_SC_HD__CLKBUF_2_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_8_V
+`define SKY130_FD_SC_HD__CLKBUF_8_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__CLKBUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrckapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
+    X    ,
+    SLEEP,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A),
+        .KAPWR(KAPWR),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
+    X    ,
+    SLEEP,
+    A
+);
+
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Voltage supply signals
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
+        .X(X),
+        .SLEEP(SLEEP),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+    X    ,
+    SLEEP,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out       ;
+    wire and0_out_X     ;
+    wire pwrgood0_out_X ;
+    wire pwrgood1_out_x2;
+
+    //                                     Name      Output           Other arguments
+    not                                    not0     (not0_out       , SLEEP                        );
+    and                                    and0     (and0_out_X     , not0_out, A                  );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG   pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND  );
+    buf                                    buf0     (X              , pwrgood1_out_x2              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+    X    ,
+    SLEEP,
+    A    ,
+    KAPWR,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+    input  KAPWR;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire not0_out       ;
+    wire and0_out_X     ;
+    wire pwrgood0_out_X ;
+    wire pwrgood1_out_x2;
+
+    //                                     Name      Output           Other arguments
+    not                                    not0     (not0_out       , SLEEP                        );
+    and                                    and0     (and0_out_X     , not0_out, A                  );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG   pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND  );
+    buf                                    buf0     (X              , pwrgood1_out_x2              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+    X    ,
+    SLEEP,
+    A
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , SLEEP          );
+    and and0 (and0_out_X, not0_out, A    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ *                        keep-alive power rail.
+ *
+ *                        X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+    X    ,
+    SLEEP,
+    A
+);
+
+    // Module ports
+    output X    ;
+    input  SLEEP;
+    input  A    ;
+
+    // Module supplies
+    supply1 KAPWR;
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , SLEEP          );
+    and and0 (and0_out_X, not0_out, A    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_V
+`define SKY130_FD_SC_HD__EDFXTP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, buf_Q, D, DE              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, buf_Q, D, DE   );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_1_V
+`define SKY130_FD_SC_HD__EDFXTP_1_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for edfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__edfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__edfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_2_V
+`define SKY130_FD_SC_HD__A32O_2_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_1_V
+`define SKY130_FD_SC_HD__A32O_1_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_4_V
+`define SKY130_FD_SC_HD__A32O_4_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_V
+`define SKY130_FD_SC_HD__A32O_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    and                                and1        (and1_out         , B1, B2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    and                                and1        (and1_out         , B1, B2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2        );
+    and and1 (and1_out , B1, B2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2        );
+    and and1 (and1_out , B1, B2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso1n with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_hd__lpflow_inputiso1n base (
+        .X(X),
+        .A(A),
+        .SLEEP_B(SLEEP_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__lpflow_inputiso1n base (
+        .X(X),
+        .A(A),
+        .SLEEP_B(SLEEP_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire SLEEP    ;
+    wire or0_out_X;
+
+    //                                   Name      Output     Other arguments
+    not                                  not0     (SLEEP    , SLEEP_B              );
+    or                                   or0      (or0_out_X, A, SLEEP             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X        , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire SLEEP    ;
+    wire or0_out_X;
+
+    //                                   Name      Output     Other arguments
+    not                                  not0     (SLEEP    , SLEEP_B              );
+    or                                   or0      (or0_out_X, A, SLEEP             );
+    sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X        , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Local signals
+    wire SLEEP;
+
+    //  Name  Output  Other arguments
+    not not0 (SLEEP , SLEEP_B        );
+    or  or0  (X     , A, SLEEP       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ *                    X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire SLEEP;
+
+    //  Name  Output  Other arguments
+    not not0 (SLEEP , SLEEP_B        );
+    or  or0  (X     , A, SLEEP       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_V
+`define SKY130_FD_SC_HD__A221O_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    or                                 or0         (or0_out_X        , and1_out, and0_out, C1);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    or                                 or0         (or0_out_X        , and1_out, and0_out, C1);
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2                );
+    and and1 (and1_out , A1, A2                );
+    or  or0  (or0_out_X, and1_out, and0_out, C1);
+    buf buf0 (X        , or0_out_X             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2                );
+    and and1 (and1_out , A1, A2                );
+    or  or0  (or0_out_X, and1_out, and0_out, C1);
+    buf buf0 (X        , or0_out_X             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_4_V
+`define SKY130_FD_SC_HD__A221O_4_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_1_V
+`define SKY130_FD_SC_HD__A221O_1_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_2_V
+`define SKY130_FD_SC_HD__A221O_2_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A221O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_V
+`define SKY130_FD_SC_HD__A311OI_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2      );
+    nor nor0 (nor0_out_Y, and0_out, B1, C1);
+    buf buf0 (Y         , nor0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2      );
+    nor nor0 (nor0_out_Y, and0_out, B1, C1);
+    buf buf0 (Y         , nor0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_2_V
+`define SKY130_FD_SC_HD__A311OI_2_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_4_V
+`define SKY130_FD_SC_HD__A311OI_4_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_1_V
+`define SKY130_FD_SC_HD__A311OI_1_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A311OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_1_V
+`define SKY130_FD_SC_HD__XNOR2_1_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_V
+`define SKY130_FD_SC_HD__XNOR2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_Y      , A, B                   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_Y      , A, B                   );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire xnor0_out_Y;
+
+    //   Name   Output       Other arguments
+    xnor xnor0 (xnor0_out_Y, A, B           );
+    buf  buf0  (Y          , xnor0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xnor0_out_Y;
+
+    //   Name   Output       Other arguments
+    xnor xnor0 (xnor0_out_Y, A, B           );
+    buf  buf0  (Y          , xnor0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_4_V
+`define SKY130_FD_SC_HD__XNOR2_4_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_2_V
+`define SKY130_FD_SC_HD__XNOR2_2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__XNOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_1_V
+`define SKY130_FD_SC_HD__SEDFXBP_1_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_2_V
+`define SKY130_FD_SC_HD__SEDFXBP_2_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_V
+`define SKY130_FD_SC_HD__SEDFXBP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to10 (mux_out, de_d, SCD, SCE            );
+    sky130_fd_sc_hd__udp_mux_2to1                  mux_2to11 (de_d   , buf_Q, D, DE              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to10 (mux_out, de_d, SCD, SCE );
+    sky130_fd_sc_hd__udp_mux_2to1             mux_2to11 (de_d   , buf_Q, D, DE   );
+    sky130_fd_sc_hd__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hd__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__SEDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_4_V
+`define SKY130_FD_SC_HD__EINVP_4_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_4 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_4 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_1_V
+`define SKY130_FD_SC_HD__EINVP_1_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_1 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_1 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_2_V
+`define SKY130_FD_SC_HD__EINVP_2_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_2 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_2 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_8_V
+`define SKY130_FD_SC_HD__EINVP_8_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_8 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_8 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_V
+`define SKY130_FD_SC_HD__EINVP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A ;
+    wire pwrgood_pp1_out_TE;
+
+    //                                 Name         Output              Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND                        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND                       );
+    notif1                             notif10     (Z                 , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A ;
+    wire pwrgood_pp1_out_TE;
+
+    //                                 Name         Output              Other arguments
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND                        );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND                       );
+    notif1                             notif10     (Z                 , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+    Z ,
+    A ,
+    TE
+);
+
+    // Module ports
+    output Z ;
+    input  A ;
+    input  TE;
+
+    //     Name     Output  Other arguments
+    notif1 notif10 (Z     , A, TE          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+    Z ,
+    A ,
+    TE
+);
+
+    // Module ports
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    notif1 notif10 (Z     , A, TE          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__EINVP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_4_V
+`define SKY130_FD_SC_HD__A32OI_4_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_2_V
+`define SKY130_FD_SC_HD__A32OI_2_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_V
+`define SKY130_FD_SC_HD__A32OI_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1, A3            );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1, A3            );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1, A3          );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1, A3          );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_1_V
+`define SKY130_FD_SC_HD__A32OI_1_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A32OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_2_V
+`define SKY130_FD_SC_HD__O2BB2AI_2_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_1_V
+`define SKY130_FD_SC_HD__O2BB2AI_1_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_4_V
+`define SKY130_FD_SC_HD__O2BB2AI_4_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_V
+`define SKY130_FD_SC_HD__O2BB2AI_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire nand1_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N             );
+    or                                 or0         (or0_out          , B2, B1                 );
+    nand                               nand1       (nand1_out_Y      , nand0_out, or0_out     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire nand1_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N             );
+    or                                 or0         (or0_out          , B2, B1                 );
+    nand                               nand1       (nand1_out_Y      , nand0_out, or0_out     );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire or0_out    ;
+    wire nand1_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2_N, A1_N        );
+    or   or0   (or0_out    , B2, B1            );
+    nand nand1 (nand1_out_Y, nand0_out, or0_out);
+    buf  buf0  (Y          , nand1_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+`else  // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire or0_out    ;
+    wire nand1_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2_N, A1_N        );
+    or   or0   (or0_out    , B2, B1            );
+    nand nand1 (nand1_out_Y, nand0_out, or0_out);
+    buf  buf0  (Y          , nand1_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__O2BB2AI_V
+
+
+//--------EOF---------
+