| /* |
| * SPDX-FileCopyrightText: 2015 Clifford Wolf |
| * PicoRV32 -- A Small RISC-V (RV32I) Processor Core |
| * |
| * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at> |
| * |
| * Permission to use, copy, modify, and/or distribute this software for any |
| * purpose with or without fee is hereby granted, provided that the above |
| * copyright notice and this permission notice appear in all copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| * |
| * SPDX-License-Identifier: ISC |
| */ |
| |
| #define regnum_q0 0 |
| #define regnum_q1 1 |
| #define regnum_q2 2 |
| #define regnum_q3 3 |
| |
| #define regnum_x0 0 |
| #define regnum_x1 1 |
| #define regnum_x2 2 |
| #define regnum_x3 3 |
| #define regnum_x4 4 |
| #define regnum_x5 5 |
| #define regnum_x6 6 |
| #define regnum_x7 7 |
| #define regnum_x8 8 |
| #define regnum_x9 9 |
| #define regnum_x10 10 |
| #define regnum_x11 11 |
| #define regnum_x12 12 |
| #define regnum_x13 13 |
| #define regnum_x14 14 |
| #define regnum_x15 15 |
| #define regnum_x16 16 |
| #define regnum_x17 17 |
| #define regnum_x18 18 |
| #define regnum_x19 19 |
| #define regnum_x20 20 |
| #define regnum_x21 21 |
| #define regnum_x22 22 |
| #define regnum_x23 23 |
| #define regnum_x24 24 |
| #define regnum_x25 25 |
| #define regnum_x26 26 |
| #define regnum_x27 27 |
| #define regnum_x28 28 |
| #define regnum_x29 29 |
| #define regnum_x30 30 |
| #define regnum_x31 31 |
| |
| #define regnum_zero 0 |
| #define regnum_ra 1 |
| #define regnum_sp 2 |
| #define regnum_gp 3 |
| #define regnum_tp 4 |
| #define regnum_t0 5 |
| #define regnum_t1 6 |
| #define regnum_t2 7 |
| #define regnum_s0 8 |
| #define regnum_s1 9 |
| #define regnum_a0 10 |
| #define regnum_a1 11 |
| #define regnum_a2 12 |
| #define regnum_a3 13 |
| #define regnum_a4 14 |
| #define regnum_a5 15 |
| #define regnum_a6 16 |
| #define regnum_a7 17 |
| #define regnum_s2 18 |
| #define regnum_s3 19 |
| #define regnum_s4 20 |
| #define regnum_s5 21 |
| #define regnum_s6 22 |
| #define regnum_s7 23 |
| #define regnum_s8 24 |
| #define regnum_s9 25 |
| #define regnum_s10 26 |
| #define regnum_s11 27 |
| #define regnum_t3 28 |
| #define regnum_t4 29 |
| #define regnum_t5 30 |
| #define regnum_t6 31 |
| |
| // x8 is s0 and also fp |
| #define regnum_fp 8 |
| |
| #define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \ |
| .word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0)) |
| |
| #define picorv32_getq_insn(_rd, _qs) \ |
| r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011) |
| |
| #define picorv32_setq_insn(_qd, _rs) \ |
| r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011) |
| |
| #define picorv32_retirq_insn() \ |
| r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011) |
| |
| #define picorv32_maskirq_insn(_rd, _rs) \ |
| r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011) |
| |
| #define picorv32_waitirq_insn(_rd) \ |
| r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011) |
| |
| #define picorv32_timer_insn(_rd, _rs) \ |
| r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011) |
| |
