diff --git a/verilog/dv/jacaranda_test/jacaranda_test.c b/verilog/dv/jacaranda_test/jacaranda_test.c
index 746da67..42e1d36 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test.c
+++ b/verilog/dv/jacaranda_test/jacaranda_test.c
@@ -25,6 +25,7 @@
 
 #define BASE_ADDR 0x30000000
 #define IMEM_WRITE BASE_ADDR
+#define UART_CLK_FREQ BASE_ADDR + 0x4
 
 static void
 write(uint32_t addr, uint32_t val)
@@ -55,6 +56,9 @@
     // set reset to high
 	reg_la0_data = 1;
 
+    // set uart clk frequency
+    write(UART_CLK_FREQ, 40000000);
+
     for(int i = 0; i < 29; ++i) {
         write(IMEM_WRITE, i << 8 | mem[i]);
     }
diff --git a/verilog/rtl/jacaranda-8/UART/UART.v b/verilog/rtl/jacaranda-8/UART/UART.v
index 9262a66..f76325d 100644
--- a/verilog/rtl/jacaranda-8/UART/UART.v
+++ b/verilog/rtl/jacaranda-8/UART/UART.v
@@ -15,11 +15,17 @@
     output wire[7:0] rx_data,
     output wire busy_flag,
     output wire receive_flag,
-    output reg int_req
+    output reg int_req,
+    input wire [31:0] clk_freq
 );
 
+    parameter BAUD_RATE = 115200;
+
+    wire [31:0] clk_count_bit;
     reg state;
 
+    assign clk_count_bit = clk_freq / BAUD_RATE;
+
     always @(negedge clk) begin
         if(state == 1'b0) begin //データ待機中
             int_req <= 1'b0;
@@ -42,7 +48,7 @@
         state   <= 1'b0;
     end
 
-    tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag);
-    rx rx1(clk, rx_en, rx, rx_data, receive_flag);
+    tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag, clk_count_bit);
+    rx rx1(clk, rx_en, rx, rx_data, receive_flag, clk_count_bit);
     
 endmodule
diff --git a/verilog/rtl/jacaranda-8/UART/rx.v b/verilog/rtl/jacaranda-8/UART/rx.v
index 9f3efd3..3afd654 100644
--- a/verilog/rtl/jacaranda-8/UART/rx.v
+++ b/verilog/rtl/jacaranda-8/UART/rx.v
@@ -1,24 +1,24 @@
-module rx(clk, rx_en, rx, data, end_flag);
+module rx(clk, rx_en, rx, data, end_flag, clk_count_bit);
     input wire clk;
     input wire rx_en;
     input wire rx;
     output reg[7:0] data = 8'b00000000;
     output reg end_flag = 1'b0;
+    input wire [31:0] clk_count_bit;
 
-    parameter CLK_FREQ = 50_000_000;
-    parameter BAUD_RATE = 115200;
-    parameter CLK_COUNT_BIT = CLK_FREQ / BAUD_RATE;
-    parameter CLK_BEGIN_TO_RECEIVE = CLK_COUNT_BIT + CLK_COUNT_BIT / 2 - 4;
-    
+    wire [31:0] clk_begin_to_receive;
+
     reg[1:0] state = 2'b00;
     reg[31:0] clk_count = 32'd0;
     reg[2:0] bit_count = 3'd0;
     reg[3:0] recent = 4'b1111;
     wire update_flag;
 
+    assign clk_begin_to_receive = clk_count_bit + clk_count_bit / 2 - 4;
+
     assign update_flag = (state == 2'b01) 
-        ? clk_count == CLK_BEGIN_TO_RECEIVE 
-        : clk_count == CLK_COUNT_BIT - 32'd1;
+        ? clk_count == clk_begin_to_receive
+        : clk_count == clk_count_bit - 32'd1;
     
     always @(posedge clk) begin
         case(state)
diff --git a/verilog/rtl/jacaranda-8/UART/tx.v b/verilog/rtl/jacaranda-8/UART/tx.v
index 9389f8a..60d1b4a 100644
--- a/verilog/rtl/jacaranda-8/UART/tx.v
+++ b/verilog/rtl/jacaranda-8/UART/tx.v
@@ -1,4 +1,4 @@
-module tx(clk, reset, tx_en, begin_flag, data, tx, busy_flag);
+module tx(clk, reset, tx_en, begin_flag, data, tx, busy_flag, clk_count_bit);
     input wire clk;
     input wire reset;
     input wire tx_en;
@@ -6,17 +6,14 @@
     input wire[7:0] data;
     output reg tx;
     output wire busy_flag;
-
-    parameter CLK_FREQ = 40_000_000;
-    parameter BAUD_RATE = 115200;
-    parameter CLK_COUNT_BIT = CLK_FREQ / BAUD_RATE;
+    input wire [31:0] clk_count_bit;
 
     reg[1:0] state;
     reg[31:0] clk_count;
     reg[2:0] bit_count;
     wire update_flag;
     
-    assign update_flag = (clk_count == CLK_COUNT_BIT - 32'd1);
+    assign update_flag = (clk_count == clk_count_bit - 32'd1);
     assign busy_flag = ~(state == 2'b00);
 
     always @(posedge clk or posedge reset) begin
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 84b8325..52f8b4d 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -60,7 +60,6 @@
 
     wire [7:0] instr;
     wire [7:0] pc;
-    assign la_data_out[7:0] = pc;
     wire [7:0] rd_data;
     wire [7:0] rs_data;
     wire mem_w_en;
@@ -94,6 +93,8 @@
 
     wire [7:0] wb_instr_req_addr;
 
+    wire [31:0] uart_clk_freq;
+
     assign instr_mem_addr = reset ? wb_instr_req_addr: pc;
 
     wire reset;
@@ -115,7 +116,9 @@
                 .wbs_dat_o(wbs_dat_o),
                 .instr_mem_addr(wb_instr_req_addr),
                 .instr_mem_data(instr_mem_data),
-                .instr_mem_en(instr_mem_en));
+                .instr_mem_en(instr_mem_en),
+                .uart_freq(uart_clk_freq)
+            );
 
     instr_mem instr_mem(.addr(instr_mem_addr),
                         .w_data(instr_mem_data),
@@ -217,7 +220,9 @@
               .receive_flag(receive_flag),
               .int_req(int_req),
               .access_addr(rs_data),
-              .reg_w_en(reg_w_en));
+              .reg_w_en(reg_w_en),
+              .clk_freq(uart_clk_freq)
+        );
 //
 //    LED4 LED4(.in_data(led_in_data),
 //              .begin_flag(led_begin_flag),
diff --git a/verilog/rtl/jacaranda-8/wishbone.v b/verilog/rtl/jacaranda-8/wishbone.v
index 06e2125..01682f9 100644
--- a/verilog/rtl/jacaranda-8/wishbone.v
+++ b/verilog/rtl/jacaranda-8/wishbone.v
@@ -12,10 +12,13 @@
 
     output reg [7:0] instr_mem_addr,
     output reg [7:0] instr_mem_data,
-    output reg instr_mem_en
+    output reg instr_mem_en,
+
+    output reg [31:0] uart_freq
 );
 
 parameter IMEM_WRITE = 32'h3000_0000;
+parameter UART_CLK_FREQ = 32'h3000_0004;
 
 wire valid;
 wire we;
@@ -55,6 +58,9 @@
                     instr_mem_data <= wdata[7:0];
                     instr_mem_en <= 1'b1;
                 end
+                UART_CLK_FREQ: begin
+                    uart_freq <= wdata;
+                end
             endcase
             ready <= 1'b1;
         end