)]}'
{
  "commit": "997a4de5fee4c78b47a17b887cd6f2a942d00967",
  "tree": "10b4a9456ee36e9216e0d6a003a339e352a2caac",
  "parents": [
    "73d3498b19458b6ef8dfd063723de1ef3e5f06f3"
  ],
  "author": {
    "name": "Yuki Azuma",
    "email": "yuhki.yasuda@gmail.com",
    "time": "Sat Oct 09 17:01:55 2021 +0900"
  },
  "committer": {
    "name": "Yuki Azuma",
    "email": "yuhki.yasuda@gmail.com",
    "time": "Sat Oct 09 17:01:55 2021 +0900"
  },
  "message": "improve reset logic\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9d8b6c67b2b50631aa7651e837d0e1932a1ab1d9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/jacaranda-8/computer.v",
      "new_id": "13dccf46bc65d48222aea1b15965aa2f4f36839c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/jacaranda-8/computer.v"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/jacaranda-8/cpu.v",
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      "new_mode": 33188,
      "new_path": "verilog/rtl/jacaranda-8/cpu.v"
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}