jobs/tapeout/e4ceb7b1-c22f-4544-b388-9c5e66aede2f/logs/gen_gpio_defaults.log

/root/project/verilog/rtl/user_defines.v not found, using default /opt/caravel/verilog/rtl/user_defines.v
Step 1:  Create new cells for new GPIO default vectors.
Creating new layout file /root/project/mag/gpio_defaults_block_1800.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
Step 2:  Modify top-level layouts to use the specified defaults.
Done.