)]}'
{
  "commit": "ee00b8160c2fbc56860129b5a2f3e0279fbb578d",
  "tree": "123325da29382eb7cff77f38ee1e1eef5ad130ab",
  "parents": [
    "361442e1e9b14ce5415262285ef82362ef3e4c39"
  ],
  "author": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 18:36:26 2021 +0200"
  },
  "committer": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 18:44:55 2021 +0200"
  },
  "message": "Fix undeclared wire in cpu_core\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "908c959f938d7c6251c71ef641a263d7f1318929",
      "old_mode": 33188,
      "old_path": "verilog/rtl/cpu_core.v",
      "new_id": "350b22a118299742b8ec1d33a07a036e9310e37d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/cpu_core.v"
    }
  ]
}