)]}'
{
  "commit": "d627a7c87e8ba802bfc14144360af4c489f1ea6c",
  "tree": "dae4e0f3027d1d1d4921db5342df49156ca0e701",
  "parents": [
    "093751b5187b7cc4539f2e143e471b057c693c3e"
  ],
  "author": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 17:19:44 2021 +0200"
  },
  "committer": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 17:19:44 2021 +0200"
  },
  "message": "Add list of verilog files to user_project config\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7ac305c7e18ae43f07a14384b8c04e2e4e62c272",
      "old_mode": 33261,
      "old_path": "openlane/user_project/config.tcl",
      "new_id": "ddd965f9b9f6e46ad74e393454c04336c1b49c8c",
      "new_mode": 33261,
      "new_path": "openlane/user_project/config.tcl"
    }
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}