)]}'
{
  "commit": "c392d45896fe75daf9221874c437fa10924477a2",
  "tree": "503845a4271a12e385fb7732cf027d4b837f6144",
  "parents": [
    "0ae7f0121712222f94a1333485329d56d291355d"
  ],
  "author": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 23:17:17 2021 +0200"
  },
  "committer": {
    "name": "Tamas Hubai",
    "email": "mpw@htamas.net",
    "time": "Tue Oct 26 23:17:17 2021 +0200"
  },
  "message": "Refactor final parameter by pooling instr_mem\u0027s\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cd78fcc1f71d365ed4acfc96c868bfab98d544dd",
      "old_mode": 33188,
      "old_path": "verilog/rtl/instr_mem.v",
      "new_id": "50830dfdb24155d35cdeed1d0a88867bcfd5a47f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/instr_mem.v"
    },
    {
      "type": "modify",
      "old_id": "941bc3db8dee13af3f4940712e322fbe67381634",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mcu.v",
      "new_id": "0f65f188ed4a12550276052a0b62d85ae4ff7ee3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mcu.v"
    }
  ]
}