diff --git a/def/user_proj_example.def b/def/user_project.def
similarity index 99%
rename from def/user_proj_example.def
rename to def/user_project.def
index 95e0546..412268a 100644
--- a/def/user_proj_example.def
+++ b/def/user_project.def
@@ -1,7 +1,7 @@
 VERSION 5.8 ;
 DIVIDERCHAR "/" ;
 BUSBITCHARS "[]" ;
-DESIGN user_proj_example ;
+DESIGN user_project ;
 UNITS DISTANCE MICRONS 1000 ;
 DIEAREA ( 0 0 ) ( 900000 600000 ) ;
 ROW ROW_0 unithd 5520 10880 N DO 1932 BY 1 STEP 460 0 ;
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index 0527663..7263e45 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -1309,7 +1309,7 @@
     - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 350 400 350  + ROWCOL 2 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+    - mprj user_project + FIXED ( 1175000 1690000 ) N ;
 END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
diff --git a/docs/source/index.rst b/docs/source/index.rst
index bde1986..f1aad16 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -360,8 +360,8 @@
 
 .. code:: bash
 
-   # Run openlane to harden user_proj_example
-   make user_proj_example
+   # Run openlane to harden user_project
+   make user_project
    # Run openlane to harden user_project_wrapper
    make user_project_wrapper
 
diff --git a/gds/user_proj_example.gds b/gds/user_project.gds
similarity index 100%
rename from gds/user_proj_example.gds
rename to gds/user_project.gds
Binary files differ
diff --git a/lef/user_proj_example.lef b/lef/user_project.lef
similarity index 99%
rename from lef/user_proj_example.lef
rename to lef/user_project.lef
index 0297dcc..18a2519 100644
--- a/lef/user_proj_example.lef
+++ b/lef/user_project.lef
@@ -2,9 +2,9 @@
   NOWIREEXTENSIONATPIN ON ;
   DIVIDERCHAR "/" ;
   BUSBITCHARS "[]" ;
-MACRO user_proj_example
+MACRO user_project
   CLASS BLOCK ;
-  FOREIGN user_proj_example ;
+  FOREIGN user_project ;
   ORIGIN 0.000 0.000 ;
   SIZE 900.000 BY 600.000 ;
   PIN io_in[0]
@@ -5498,6 +5498,6 @@
       LAYER met4 ;
         RECT 174.640 9.015 867.440 587.760 ;
   END
-END user_proj_example
+END user_project
 END LIBRARY
 
diff --git a/mag/user_proj_example.mag b/mag/user_project.mag
similarity index 100%
rename from mag/user_proj_example.mag
rename to mag/user_project.mag
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index ff669ca..d8ff017 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -66345,7 +66345,7 @@
 rect 592298 -7622 592382 -7386
 rect 592618 -7622 592650 -7386
 rect -8726 -7654 592650 -7622
-use user_proj_example  mprj
+use user_project  mprj
 timestamp 1631895074
 transform 1 0 235000 0 1 338000
 box 106 0 179846 120000
diff --git a/maglef/user_proj_example.mag b/maglef/user_project.mag
similarity index 99%
rename from maglef/user_proj_example.mag
rename to maglef/user_project.mag
index 107ed2c..7905b11 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_project.mag
@@ -2453,7 +2453,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 180000 120000
 string LEFview TRUE
-string GDS_FILE /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds
+string GDS_FILE /project/openlane/user_project/runs/user_project/results/magic/user_project.gds
 string GDS_END 8095954
 string GDS_START 360410
 << end >>
diff --git a/openlane/user_proj_example/config.json b/openlane/user_project/config.json
similarity index 86%
rename from openlane/user_proj_example/config.json
rename to openlane/user_project/config.json
index a7671cd..182f0e2 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_project/config.json
@@ -4,7 +4,7 @@
     "CLOCK_PERIOD"             : "10",
     "CLOCK_PORT"               : "wb_clk_i",
     "DESIGN_IS_CORE"           : "0",
-    "DESIGN_NAME"              : "user_proj_example",
+    "DESIGN_NAME"              : "user_project",
     "DIE_AREA"                 : "0 0 900 600",
     "DIODE_INSERTION_STRATEGY" : "4",
     "FP_PIN_ORDER_CFG"         : "pin_order.cfg",
@@ -15,5 +15,5 @@
     "PL_TARGET_DENSITY"        : "0.05",
     "RUN_CVC"                  : "1",
     "VDD_NETS"                 : "vccd1",
-    "VERILOG_FILES"            : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"]
+    "VERILOG_FILES"            : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_project.v"]
 }
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_project/config.tcl
similarity index 94%
rename from openlane/user_proj_example/config.tcl
rename to openlane/user_project/config.tcl
index 2aa188c..7ac305c 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_project/config.tcl
@@ -15,11 +15,11 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 
-set ::env(DESIGN_NAME) user_proj_example
+set ::env(DESIGN_NAME) user_project
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../verilog/rtl/user_project.v"
 
 set ::env(DESIGN_IS_CORE) 0
 
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_project/pin_order.cfg
similarity index 100%
rename from openlane/user_proj_example/pin_order.cfg
rename to openlane/user_project/pin_order.cfg
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index ace94af..131743d 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -7,8 +7,8 @@
     "DESIGN_NAME"                     : "user_project_wrapper",
     "DIE_AREA"                        : "0 0 2920 3520",
     "DIODE_INSERTION_STRATEGY"        : "0",
-    "EXTRA_GDS_FILES"                 : "../../gds/user_proj_example.gds",
-    "EXTRA_LEFS"                      : "../../lef/user_proj_example.lef",
+    "EXTRA_GDS_FILES"                 : "../../gds/user_project.gds",
+    "EXTRA_LEFS"                      : "../../lef/user_project.lef",
     "FILL_INSERTION"                  : "0",
     "FP_IO_HEXTEND"                   : "4.8",
     "FP_IO_HLENGTH"                   : "2.4",
@@ -51,6 +51,6 @@
     "TAP_DECAP_INSERTION"             : "0",
     "VDD_NETS"                        : "vccd1 vccd2 vdda1 vdda2",
     "VERILOG_FILES"                   : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],  
-    "VERILOG_FILES_BLACKBOX"          : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"]  
+    "VERILOG_FILES_BLACKBOX"          : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project.v"]  
 }
 
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c94b7a0..36c664e 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -51,13 +51,13 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../verilog/rtl/user_project.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/../../lef/user_project.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/../../gds/user_project.gds"
 
 set ::env(GLB_RT_MAXLAYER) 5
 
diff --git a/signoff/user_proj_example/OPENLANE_VERSION b/signoff/user_project/OPENLANE_VERSION
similarity index 100%
rename from signoff/user_proj_example/OPENLANE_VERSION
rename to signoff/user_project/OPENLANE_VERSION
diff --git a/signoff/user_proj_example/PDK_SOURCES b/signoff/user_project/PDK_SOURCES
similarity index 100%
rename from signoff/user_proj_example/PDK_SOURCES
rename to signoff/user_project/PDK_SOURCES
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_project/final_summary_report.csv
similarity index 70%
rename from signoff/user_proj_example/final_summary_report.csv
rename to signoff/user_project/final_summary_report.csv
index ccefd43..b2564e1 100644
--- a/signoff/user_proj_example/final_summary_report.csv
+++ b/signoff/user_project/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h6m55s,0h3m29s,2077.777777777778,0.54,1038.888888888889,1.06,673.95,561,0,0,0,0,0,0,0,4,0,0,-1,70414,7173,-2.56,-4.44,0.0,-0.49,-0.66,-14.55,-34.44,0.0,-5.47,-5.31,62840367.0,0.08,3.22,2.62,0.6,0.0,-1,342,1149,29,836,0,0,0,380,0,0,0,0,0,0,0,4,169,135,20,424,7276,0,7700,93.80863039399625,10.66,10,AREA 0,5,50,1,153.6,153.18,0.05,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/user_project,user_project,user_project,flow_completed,0h6m55s,0h3m29s,2077.777777777778,0.54,1038.888888888889,1.06,673.95,561,0,0,0,0,0,0,0,4,0,0,-1,70414,7173,-2.56,-4.44,0.0,-0.49,-0.66,-14.55,-34.44,0.0,-5.47,-5.31,62840367.0,0.08,3.22,2.62,0.6,0.0,-1,342,1149,29,836,0,0,0,380,0,0,0,0,0,0,0,4,169,135,20,424,7276,0,7700,93.80863039399625,10.66,10,AREA 0,5,50,1,153.6,153.18,0.05,0.0,sky130_fd_sc_hd,4,4
diff --git a/spi/lvs/user_proj_example.spice b/spi/lvs/user_project.spice
similarity index 99%
rename from spi/lvs/user_proj_example.spice
rename to spi/lvs/user_project.spice
index 26f672f..49a1d70 100644
--- a/spi/lvs/user_proj_example.spice
+++ b/spi/lvs/user_project.spice
@@ -1,4 +1,4 @@
-* NGSPICE file created from user_proj_example.ext - technology: sky130A
+* NGSPICE file created from user_project.ext - technology: sky130A
 
 * Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
 .subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
@@ -228,7 +228,7 @@
 .subckt sky130_fd_sc_hd__or3_4 A B C VGND VNB VPB VPWR X
 .ends
 
-.subckt user_proj_example io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
+.subckt user_project io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
 + io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22]
 + io_in[23] io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30]
 + io_in[31] io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4]
diff --git a/spi/lvs/user_project_wrapper.spice b/spi/lvs/user_project_wrapper.spice
index bf713d2..451987d 100644
--- a/spi/lvs/user_project_wrapper.spice
+++ b/spi/lvs/user_project_wrapper.spice
@@ -1,7 +1,7 @@
 * NGSPICE file created from user_project_wrapper.ext - technology: sky130A
 
-* Black-box entry subcircuit for user_proj_example abstract view
-.subckt user_proj_example io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
+* Black-box entry subcircuit for user_project abstract view
+.subckt user_project io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
 + io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22]
 + io_in[23] io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30]
 + io_in[31] io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4]
@@ -295,6 +295,6 @@
 + wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
-+ wbs_stb_i wbs_we_i user_proj_example
++ wbs_stb_i wbs_we_i user_project
 .ends
 
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 1a834f7..81bff77 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -183,7 +183,7 @@
 	$display("LA Test 1 started");
 	```
 	
-* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the management SoC to monitor the counter value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_proj_example) to set the counter initial value. This is done by writing to the LA probes enable registers.   Note that the output enable is active low, while the input enable is active high.  Every channel can be configured for input, output, or both independently.
+* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the management SoC to monitor the counter value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_project) to set the counter initial value. This is done by writing to the LA probes enable registers.   Note that the output enable is active low, while the input enable is active high.  Every channel can be configured for input, output, or both independently.
 
  
 	```c
@@ -209,7 +209,7 @@
   
 ### Logic Analyzer Test 2
  
-* This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_proj_example](verilog/rtl/user_proj_example.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`.  The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register. 
+* This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_project](verilog/rtl/user_project.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`.  The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register. 
 
 	```c
 	reg_la2_oenb  = reg_la2_iena = 0xFFFFFFFC; 	// Configure LA[64] LA[65] as outputs from the cpu
diff --git a/verilog/gl/user_proj_example.v b/verilog/gl/user_project.v
similarity index 99%
rename from verilog/gl/user_proj_example.v
rename to verilog/gl/user_project.v
index df2ea69..e080b5e 100644
--- a/verilog/gl/user_proj_example.v
+++ b/verilog/gl/user_project.v
@@ -1,4 +1,4 @@
-module user_proj_example (vccd1,
+module user_project (vccd1,
     vssd1,
     wb_clk_i,
     wb_rst_i,
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index ecae883..e922d4f 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -54,7 +54,7 @@
  input [3:0] wbs_sel_i;
 
 
- user_proj_example mprj (.vccd1(vccd1),
+ user_project mprj (.vccd1(vccd1),
     .vssd1(vssd1),
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),