)]}'
{
  "commit": "2d40ac08f46a7d3ca23921ed0ac260fbf9ee6cde",
  "tree": "b8936d908832f97acaa744bad6699ba49f73f0a0",
  "parents": [
    "6e8caf14a70a365991f571b8b51eee278b5e8ca9"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Sun Sep 19 17:39:24 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Sun Sep 19 19:56:22 2021 +0200"
  },
  "message": "Fix la_test2 gl sim\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f9a293c71025bbc7cbb26da9c72fe491bcf46de5",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2.c",
      "new_id": "5875432d2683bc04de3fd49f7c5a10cf0b2e6f5e",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/la_test2.c"
    }
  ]
}