diff --git a/verilog/rtl/cpu_core.v b/verilog/rtl/cpu_core.v
index fb3c2b1..bfe8830 100644
--- a/verilog/rtl/cpu_core.v
+++ b/verilog/rtl/cpu_core.v
@@ -105,26 +105,26 @@
 ADDR_WIDTH = size of mem_mesh addresses, should be <= `DATA_WIDTH
 SPREAD_WIDTH = size of mem_mesh spread value
 INSTR_WIDTH = combined size of opcode & immediate, should be kept at 32
-CPU_NUM = id number to differentiate cpu cores, can be queried by code running on the processor
 */
 
-module cpu_core #(parameter CPU_NUM=0) (
-   input clk,                             // clock signal
-   input rst_n,                           // reset, active low
+module cpu_core (
+   input clk,                              // clock signal
+   input rst_n,                            // reset, active low
    input [`INSTR_WIDTH-1:0] opcode,        // opcode to be executed & immediate args
    input [`DATA_WIDTH-1:0] mem_rdata,      // connected to 'rdata' of memory module
+   input [`DATA_WIDTH-1:0] cpu_num,        // id to differentiate cpu cores
    input [`DATA_WIDTH-1:0] prng_in,        // random number from prng
-   input [1:0] debug_mode,                // debug: 00 = no change, 01 = single step, 10 = run, 11 = stop
-   input [3:0] debug_sel,                 // debug: cpu status register to query or modify
-   input debug_we,                        // debug: modify selected status register
+   input [1:0] debug_mode,                 // debug: 00 = no change, 01 = single step, 10 = run, 11 = stop
+   input [3:0] debug_sel,                  // debug: cpu status register to query or modify
+   input debug_we,                         // debug: modify selected status register
    input [`DATA_WIDTH-1:0] debug_wdata,    // debug: new value of selected status register
    output [`PC_WIDTH-1:0] progctr,         // program counter
-   output mem_we,                         // +-
+   output mem_we,                          // +-
    output [`ADDR_WIDTH-1:0] mem_waddr,     // | connected to
    output [`SPREAD_WIDTH-1:0] mem_wspread, // | corresponding ports
    output [`DATA_WIDTH-1:0] mem_wdata,     // | of memory module
    output [`ADDR_WIDTH-1:0] mem_raddr,     // +-
-   output debug_stopped,                  // debug: read back whether core is stopped
+   output debug_stopped,                   // debug: read back whether core is stopped
    output [`DATA_WIDTH-1:0] debug_rdata    // debug: current value of selected status register
 );
 
@@ -171,7 +171,7 @@
 assign sources1[4] = op_immed;
 assign sources1[5] = op_immed[15:8];
 assign sources1[6] = timer;
-assign sources1[7] = CPU_NUM;
+assign sources1[7] = cpu_num;
 
 wire [`DATA_WIDTH-1:0] sources2[7:0];
 assign sources2[0] = reg1;
diff --git a/verilog/rtl/mcu.v b/verilog/rtl/mcu.v
index b726176..941bc3d 100644
--- a/verilog/rtl/mcu.v
+++ b/verilog/rtl/mcu.v
@@ -150,13 +150,13 @@
 for(core=0; core<`CORES; core=core+1) begin:g_core
 
    // add the cpu core itself
-   cpu_core #(
-      .CPU_NUM(core)
-   ) cpu_core_inst (
+   wire [`DATA_WIDTH-1:0] cpu_num = core;
+   cpu_core cpu_core_inst (
       .clk(clk),
       .rst_n(rst_soft_n),
       .opcode(opcode[core]),
       .mem_rdata(mem_rdata[core]),
+      .cpu_num(cpu_num),
       .prng_in(prng_random[core]),
       .debug_mode(debug_cpu_mode[core]),
       .debug_sel(debug_reg_sel[core]),
@@ -191,11 +191,11 @@
    );
 
    // add its own pseudorandom number generator
-   prng_wrap #(
-      .INDEX(core)
-   ) prng_inst (
+   wire [`PRNG_STATE_BITS-1:0] index = core;
+   prng_wrap prng_inst (
       .clk(clk),
       .rst_n(rst_prng_n),
+      .index(index),
       .entropy(entropy_bit),
       .random(prng_random[core])
    );
diff --git a/verilog/rtl/prng.v b/verilog/rtl/prng.v
index 0406b46..2a2fa89 100644
--- a/verilog/rtl/prng.v
+++ b/verilog/rtl/prng.v
@@ -12,9 +12,11 @@
 `DATA_WIDTH = number of bits shifted out every clock cycle
 */
 
-module prng #(parameter POLYNOMIAL = 4'b1001, STATE_INIT = 4'b0000) (
+module prng (
    input clk,
    input rst_n,
+   input [`PRNG_STATE_BITS-1:0] polynomial,
+   input [`PRNG_STATE_BITS-1:0] state_init,
    input entropy,    // optional external entropy for more randomness
    output [`DATA_WIDTH-1:0] random
 );
@@ -30,10 +32,10 @@
    wire feedback;
    if (shift == 0) begin:i_first
       assign prev_state = state;
-      assign feedback = ^(prev_state & POLYNOMIAL) ^ entropy;
+      assign feedback = ^(prev_state & polynomial) ^ entropy;
    end else begin:i_nfirst
       assign prev_state = g_shift[shift-1].new_state;
-      assign feedback = ^(prev_state & POLYNOMIAL);
+      assign feedback = ^(prev_state & polynomial);
    end
    wire [`PRNG_STATE_BITS-1:0] new_state = {prev_state[`PRNG_STATE_BITS-2:0], ~feedback};
    assign random[`DATA_WIDTH-shift-1] = prev_state[`PRNG_STATE_BITS-1];
@@ -42,15 +44,15 @@
 
 // reuse the same shift register to shift out a couple of bits in the beginning so that
 // we can use a very simple seed without affecting the quality of the first few cycles
-// (this happens at synth time, so it's practically free)
+// (for constant seeds this happens at synth time, so it's practically free)
 for (shift=0; shift<SCRAMBLE_CYCLES; shift=shift+1) begin:g_scramble
    wire [`PRNG_STATE_BITS-1:0] prev_state;
    if (shift == 0) begin:i_first
-      assign prev_state = STATE_INIT;
+      assign prev_state = state_init;
    end else begin:i_nfirst
       assign prev_state = g_scramble[shift-1].new_state;
    end
-   wire feedback = ^(prev_state & POLYNOMIAL);
+   wire feedback = ^(prev_state & polynomial);
    wire [`PRNG_STATE_BITS-1:0] new_state = {prev_state[`PRNG_STATE_BITS-2:0], ~feedback};
 end
 wire [`PRNG_STATE_BITS-1:0] scrambled_init = g_scramble[SCRAMBLE_CYCLES-1].new_state;
diff --git a/verilog/rtl/prng_wrap.v b/verilog/rtl/prng_wrap.v
index 45f1543..9bb2290 100644
--- a/verilog/rtl/prng_wrap.v
+++ b/verilog/rtl/prng_wrap.v
@@ -9,10 +9,11 @@
 Different choices of 0 <= INDEX < 256 generate independent prng's. For even more, the table below should be extended.
 */
 
-module prng_wrap #(parameter INDEX = 0) (
+module prng_wrap (
    input clk,
    input rst_n,
    input entropy,
+   input [`PRNG_STATE_BITS-1:0] index,
    output [`DATA_WIDTH-1:0] random
 );
 
@@ -52,12 +53,11 @@
    32'h80001870, 32'h800018C1, 32'h80001928, 32'h80001A06, 32'h80001A12, 32'h80001C50, 32'h80001C88, 32'h80002053
 };
 
-prng #(
-   .POLYNOMIAL(POLY_ARRAY[(POLY_ARRAY_LEN-1-(INDEX % POLY_ARRAY_LEN))*`PRNG_STATE_BITS +: `PRNG_STATE_BITS]),
-   .STATE_INIT(INDEX)
-) prng_inst (
+prng prng_inst (
    .clk(clk),
    .rst_n(rst_n),
+   .polynomial(POLY_ARRAY[(POLY_ARRAY_LEN-1-(index % POLY_ARRAY_LEN))*`PRNG_STATE_BITS +: `PRNG_STATE_BITS]),
+   .state_init(index),
    .entropy(entropy),
    .random(random)
 );