/root/rotfpga/Makefile
/root/rotfpga/verilog/rtl/defines.v
/root/rotfpga/verilog/rtl/logic_cell.v
/root/rotfpga/verilog/rtl/user_project.v
/root/rotfpga/verilog/rtl/uprj_netlists.v
/root/rotfpga/verilog/rtl/user_project_wrapper.v
/root/rotfpga/verilog/rtl/logic_grid.v
/root/rotfpga/openlane/Makefile
/root/rotfpga/openlane/user_project/config.json
/root/rotfpga/openlane/user_project/config.tcl
/root/rotfpga/openlane/user_project_wrapper/config.json
/root/rotfpga/openlane/user_project_wrapper/config.tcl