2021-11-15 17:11:04 - [INFO] - {{Project Git Info}} Repository: https://github.com/htfab/rotfpga.git | Branch: main | Commit: c11f2c518f83fa7f22758b19a8d1836a5b737e21
2021-11-15 17:11:04 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: rotfpga
2021-11-15 17:11:04 - [INFO] - {{Project GDS Info}} user_project_wrapper: cf4abc1ff20cdc655c72a7e4b3b96b3d720ec4c1
2021-11-15 17:11:05 - [INFO] - {{Tools Info}} KLayout: v0.27.3 | Magic: v8.3.220
2021-11-15 17:11:05 - [INFO] - {{PDKs Info}} Open PDKs: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-11-15 17:11:05 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'rotfpga/jobs/mpw_precheck/e6bcbf16-3c57-46e3-8320-83136f4852ed/logs'
2021-11-15 17:11:05 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Manifest Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-11-15 17:11:05 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2021-11-15 17:11:05 - [INFO] - An approved LICENSE (MIT) was found in rotfpga.
2021-11-15 17:11:05 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-11-15 17:11:06 - [INFO] - An approved LICENSE (MIT) was found in rotfpga.
2021-11-15 17:11:06 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-11-15 17:11:06 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 12 non-compliant file(s) with the SPDX Standard.
2021-11-15 17:11:06 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['rotfpga/Makefile', 'rotfpga/verilog/rtl/defines.v', 'rotfpga/verilog/rtl/logic_cell.v', 'rotfpga/verilog/rtl/user_project.v', 'rotfpga/verilog/rtl/uprj_netlists.v', 'rotfpga/verilog/rtl/user_project_wrapper.v', 'rotfpga/verilog/rtl/logic_grid.v', 'rotfpga/openlane/Makefile', 'rotfpga/openlane/user_project/config.json', 'rotfpga/openlane/user_project/config.tcl', 'rotfpga/openlane/user_project_wrapper/config.json', 'rotfpga/openlane/user_project_wrapper/config.tcl']
2021-11-15 17:11:06 - [INFO] - For the full SPDX compliance report check: rotfpga/jobs/mpw_precheck/e6bcbf16-3c57-46e3-8320-83136f4852ed/logs/spdx_compliance_report.log
2021-11-15 17:11:06 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Manifest
2021-11-15 17:11:06 - [INFO] - Caravel version matches, for the full report check: rotfpga/jobs/mpw_precheck/e6bcbf16-3c57-46e3-8320-83136f4852ed/logs/manifest_check.log
2021-11-15 17:11:06 - [INFO] - {{MANIFEST CHECKS PASSED}} Manifest Checks Passed. Caravel version matches.
2021-11-15 17:11:06 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Makefile
2021-11-15 17:11:06 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-11-15 17:11:06 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Default
2021-11-15 17:11:06 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-11-15 17:11:07 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-11-15 17:11:07 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Documentation
2021-11-15 17:11:07 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-11-15 17:11:07 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: Consistency
2021-11-15 17:11:07 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-11-15 17:11:07 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-11-15 17:11:07 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-11-15 17:11:07 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-11-15 17:11:12 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2021-11-15 17:11:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (46 instances). 
2021-11-15 17:11:12 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2021-11-15 17:11:12 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2021-11-15 17:11:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2021-11-15 17:11:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2021-11-15 17:11:12 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2021-11-15 17:11:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
2021-11-15 17:11:12 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2021-11-15 17:11:12 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2021-11-15 17:11:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2021-11-15 17:11:12 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2021-11-15 17:11:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2021-11-15 17:11:12 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-11-15 17:11:12 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2021-11-15 17:11:12 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-11-15 17:11:12 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-11-15 17:11:30 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view rotfpga/jobs/mpw_precheck/e6bcbf16-3c57-46e3-8320-83136f4852ed/outputs/user_project_wrapper.xor.gds
2021-11-15 17:11:30 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-11-15 17:11:30 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2021-11-15 17:15:43 - [INFO] - 0 DRC violations
2021-11-15 17:15:43 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:15:43 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2021-11-15 17:16:06 - [INFO] - No DRC Violations found
2021-11-15 17:16:06 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:16:06 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2021-11-15 17:31:59 - [INFO] - No DRC Violations found
2021-11-15 17:31:59 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:31:59 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2021-11-15 17:32:50 - [INFO] - No DRC Violations found
2021-11-15 17:32:50 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:32:50 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2021-11-15 17:33:08 - [INFO] - No DRC Violations found
2021-11-15 17:33:08 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:33:08 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2021-11-15 17:33:19 - [INFO] - No DRC Violations found
2021-11-15 17:33:19 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:33:19 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2021-11-15 17:33:23 - [INFO] - No DRC Violations found
2021-11-15 17:33:23 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 17:33:23 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'rotfpga/jobs/mpw_precheck/e6bcbf16-3c57-46e3-8320-83136f4852ed/logs'
2021-11-15 17:33:23 - [INFO] - {{SUCCESS}} All Checks Passed !!!