2021-10-24 15:58:46 - [INFO] - {{Project Git Info}} Repository: https://github.com/Eyantra698Sumanto/caravel_avsdspamp_3v3_sky130.git | Branch: master | Commit: 0cce45b989c4621a4e0f8054395944c8641a7864
2021-10-24 15:58:46 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: sziklai_pair_amplifier
2021-10-24 15:58:47 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: cdef1c7652c84250caff5b5e7c3569ae24c87019
2021-10-24 15:58:47 - [INFO] - {{Tools Info}} KLayout: v0.27.3 | Magic: v8.3.220
2021-10-24 15:58:47 - [INFO] - {{PDKs Info}} Open PDKs: 6c05bc48dc88784f9d98b89d6791cdfd91526676 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-10-24 15:58:47 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'sziklai_pair_amplifier/jobs/mpw_precheck/09f137c4-e3e4-408a-b23d-8e74a11bdc39/logs'
2021-10-24 15:58:47 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Manifest Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-10-24 15:58:47 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2021-10-24 15:58:47 - [INFO] - An approved LICENSE (Apache-2.0) was found in sziklai_pair_amplifier.
2021-10-24 15:58:47 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-10-24 15:58:48 - [INFO] - An approved LICENSE (Apache-2.0) was found in sziklai_pair_amplifier.
2021-10-24 15:58:48 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Schematics/NMOS SZIKLAI PAIR.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Schematics/PMOS SZIKLAI PAIR.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Post_Layout_Simulations/output vs supply.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Post_Layout_Simulations/frequency response.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Post_Layout_Simulations/current gain vs output.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Post_Layout_Simulations/Input-Output_plot.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:51 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Layout_Files/spamplayout1.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:51 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (sziklai_pair_amplifier/Layout_Files/spamplayout.PNG): 'utf-8' codec can't decode byte 0x89 in position 0: invalid start byte
2021-10-24 15:58:51 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 1201 non-compliant file(s) with the SPDX Standard.
2021-10-24 15:58:51 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['sziklai_pair_amplifier/Makefile', 'sziklai_pair_amplifier/docs/environment.yml', 'sziklai_pair_amplifier/docs/Makefile', 'sziklai_pair_amplifier/docs/source/index.rst', 'sziklai_pair_amplifier/docs/source/conf.py', 'sziklai_pair_amplifier/verilog/dv/Makefile', 'sziklai_pair_amplifier/verilog/dv/mprj_por/mprj_por_tb.v', 'sziklai_pair_amplifier/verilog/dv/mprj_por/Makefile', 'sziklai_pair_amplifier/verilog/dv/mprj_por/mprj_por.c', 'sziklai_pair_amplifier/verilog/rtl/example_por.v', 'sziklai_pair_amplifier/verilog/rtl/uprj_analog_netlists.v', 'sziklai_pair_amplifier/verilog/rtl/user_analog_proj_example.v', 'sziklai_pair_amplifier/verilog/rtl/user_analog_project_wrapper.v', 'sziklai_pair_amplifier/mag/sky130A.tech', 'sziklai_pair_amplifier/mag/spamp.ext']
2021-10-24 15:58:51 - [INFO] - For the full SPDX compliance report check: sziklai_pair_amplifier/jobs/mpw_precheck/09f137c4-e3e4-408a-b23d-8e74a11bdc39/logs/spdx_compliance_report.log
2021-10-24 15:58:51 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Manifest
2021-10-24 15:58:51 - [INFO] - Caravel version matches, for the full report check: sziklai_pair_amplifier/jobs/mpw_precheck/09f137c4-e3e4-408a-b23d-8e74a11bdc39/logs/manifest_check.log
2021-10-24 15:58:51 - [INFO] - {{MANIFEST CHECKS PASSED}} Manifest Checks Passed. Caravel version matches.
2021-10-24 15:58:51 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Makefile
2021-10-24 15:58:51 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-10-24 15:58:51 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Default
2021-10-24 15:58:51 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-10-24 15:58:51 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-10-24 15:58:51 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Documentation
2021-10-24 15:58:51 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-10-24 15:58:51 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: Consistency
2021-10-24 15:58:51 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/verilog/rtl/__user_analog_project_wrapper.v
2021-10-24 15:58:52 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/verilog/rtl/__user_analog_project_wrapper.v
2021-10-24 15:58:52 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/verilog/rtl/defines.v
2021-10-24 15:58:52 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/verilog/rtl/defines.v
2021-10-24 15:58:53 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2021-10-24 15:58:53 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (39 instances). 
2021-10-24 15:58:53 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2021-10-24 15:58:53 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2021-10-24 15:58:53 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2021-10-24 15:58:53 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2021-10-24 15:58:53 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (1 instances). 
2021-10-24 15:58:53 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2021-10-24 15:58:53 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2021-10-24 15:58:53 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2021-10-24 15:58:53 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-10-24 15:58:53 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2021-10-24 15:58:53 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/gds/user_analog_project_wrapper_empty.gds.gz
2021-10-24 15:58:53 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/f80b2fea4aa53d68baec2160f6640b9e3b8d86e5/gds/user_analog_project_wrapper_empty.gds.gz
2021-10-24 15:58:55 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view sziklai_pair_amplifier/jobs/mpw_precheck/09f137c4-e3e4-408a-b23d-8e74a11bdc39/outputs/user_analog_project_wrapper.xor.gds
2021-10-24 15:58:55 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-10-24 15:58:55 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2021-10-24 15:58:56 - [INFO] - 0 DRC violations
2021-10-24 15:58:56 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:58:56 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2021-10-24 15:58:58 - [INFO] - No DRC Violations found
2021-10-24 15:58:58 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:58:58 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2021-10-24 15:59:01 - [INFO] - No DRC Violations found
2021-10-24 15:59:01 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:59:01 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2021-10-24 15:59:03 - [INFO] - No DRC Violations found
2021-10-24 15:59:03 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:59:03 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2021-10-24 15:59:05 - [INFO] - No DRC Violations found
2021-10-24 15:59:05 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:59:05 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2021-10-24 15:59:06 - [INFO] - No DRC Violations found
2021-10-24 15:59:06 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:59:06 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2021-10-24 15:59:07 - [INFO] - No DRC Violations found
2021-10-24 15:59:07 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-10-24 15:59:07 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'sziklai_pair_amplifier/jobs/mpw_precheck/09f137c4-e3e4-408a-b23d-8e74a11bdc39/logs'
2021-10-24 15:59:07 - [INFO] - {{SUCCESS}} All Checks Passed !!!