)]}'
{
  "commit": "75e41493a5d12e3dad7c81fa0fe7576e63a49a97",
  "tree": "766225551ce5e6894a994807e36e7380326a21b8",
  "parents": [
    "688d93dc93e950863282dc299804cbb94178fb26"
  ],
  "author": {
    "name": "H-S-S-11",
    "email": "harry@snell.org.uk",
    "time": "Sun Oct 10 22:57:11 2021 +0100"
  },
  "committer": {
    "name": "H-S-S-11",
    "email": "harry@snell.org.uk",
    "time": "Sun Oct 10 22:57:11 2021 +0100"
  },
  "message": "get verilog tb to run\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f8933e95093d495d7a0a9de7bc4348b4f00d6b95",
      "old_mode": 33188,
      "old_path": "netgen/user_analog_project_wrapper.spice",
      "new_id": "fa1638e21eda1dc3420f0989d28301cfb0a8cf95",
      "new_mode": 33188,
      "new_path": "netgen/user_analog_project_wrapper.spice"
    },
    {
      "type": "modify",
      "old_id": "d038cffe129cea1f5e44b49fa0ff7ef3b8e8c078",
      "old_mode": 33188,
      "old_path": "verilog/dv/comparator/comparator_tb.v",
      "new_id": "b4ac0da0107f3dd5b50146f7b26327e08d570778",
      "new_mode": 33188,
      "new_path": "verilog/dv/comparator/comparator_tb.v"
    }
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}