)]}'
{
  "commit": "38ab6891c7a56cb0c0b9870bdae56caa40f4dddc",
  "tree": "7b44546bb071573ad6e2a311dd919f5af257f002",
  "parents": [
    "10b25e4997c89c98f9cb62fd69ffca7b5a92eaf5"
  ],
  "author": {
    "name": "H-S-S-11",
    "email": "harry@snell.org.uk",
    "time": "Fri Oct 08 16:04:57 2021 +0100"
  },
  "committer": {
    "name": "H-S-S-11",
    "email": "harry@snell.org.uk",
    "time": "Fri Oct 08 16:04:57 2021 +0100"
  },
  "message": "make comparator verilog model\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c99b3571a64be70830757648e97bc1f476c98f79",
      "new_mode": 33188,
      "new_path": "verilog/rtl/comparator.v"
    }
  ]
}